Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/460gxPCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/460gxPCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/460gxPCI.h (revision 51223) @@ -0,0 +1,42 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/460gxPCI.h,v 1.1 2003/01/02 18:12:48 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_460GX_H +#define PCI_460GX_H 1 + +#include +#include + +Bool xorgProbe460GX(scanpciWrapperOpt flags); +void xf86PreScan460GX(void); +void xf86PostScan460GX(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/AttrValid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/AttrValid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/AttrValid.h (revision 51223) @@ -0,0 +1,216 @@ +/* $Xorg: AttrValid.h,v 1.4 2001/03/14 18:43:40 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_AttrValid_h +#define _Xp_AttrValid_h + +#include +#include "Oid.h" + +#define XpNumber(a) (sizeof(a) / sizeof(*(a))) + +/* + * Attribute pool validation valid values and defaults + */ +typedef struct +{ + XpOidList* valid_content_orientations_supported; + XpOidList* default_content_orientations_supported; + + XpOidDocFmtList* valid_document_formats_supported; + XpOidDocFmtList* default_document_formats_supported; + + XpOidList* valid_input_trays; + XpOidList* valid_medium_sizes; + + XpOidList* valid_plexes_supported; + XpOidList* default_plexes_supported; + + XpOidCardList* valid_printer_resolutions_supported; + XpOidCardList* default_printer_resolutions_supported; + + XpOidDocFmtList* valid_xp_embedded_formats_supported; + XpOidDocFmtList* default_xp_embedded_formats_supported; + + XpOidList* valid_xp_listfonts_modes_supported; + XpOidList* default_xp_listfonts_modes_supported; + + XpOidDocFmtList* valid_xp_raw_formats_supported; + XpOidDocFmtList* default_xp_raw_formats_supported; + + XpOidList* valid_xp_setup_proviso; + + XpOidDocFmt* default_document_format; + XpOidList* valid_available_compressions_supported; + XpOidList* default_available_compressions_supported; + +} XpValidatePoolsRec; + +/* + * XpOid resource access + */ +#define XpGetStringAttr(pContext, pool, oid) \ + (const char*)XpGetOneAttribute(pContext, pool, (char*)XpOidString(oid)) +#define XpPutStringAttr(pContext, pool, oid, value) \ + XpPutOneAttribute(pContext, pool, XpOidString(oid), value) + +#ifdef _XP_PRINT_SERVER_ /* needed for XpContextPtr in Printstr.h */ + +/* + * XpOid-valued attribute access + */ +XpOid XpGetOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oid_list); +void XpPutOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + XpOid value_oid); +void XpValidateOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oids, + XpOid default_oid); +/* + * cardinal-valued attribute access + */ +unsigned long XpGetCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_card_list); +void XpPutCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + unsigned long value_card); +void XpValidateCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_cards, + unsigned long default_card); +/* + * XpOidList-valued attribute access + */ +XpOidList* XpGetListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oid_list); +void XpPutListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* list); +void XpValidateListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oids, + const XpOidList* default_oids); +/* + * XpOidCardList-valued attribute access + */ +XpOidCardList* XpGetCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_card_list); +void XpPutCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* list); +void XpValidateCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_cards, + const XpOidCardList* default_cards); +/* + * XpOidDocFmtList-valued attribute access + */ +XpOidDocFmtList* XpGetDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* valid_fmt_list); +void XpPutDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* list); +void XpValidateDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* valid_fmts, + const XpOidDocFmtList* default_fmts); +/* + * XpOidMediumSS-valued attribute access + */ +XpOidMediumSS* XpGetMediumSSAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_trays, + const XpOidList* valid_sizes); +void XpPutMediumSSAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidMediumSS* msss); +const XpOidMediumSS* XpGetDefaultMediumSS(); + +/* + * XpOidTrayMediumList-valued attribute access + */ +XpOidTrayMediumList* XpGetTrayMediumListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_trays, + const XpOidMediumSS* msss); +void XpPutTrayMediumListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidTrayMediumList* tm); +/* + * Attribute pool validation + */ +void XpValidateAttributePool(XpContextPtr pContext, + XPAttributes pool, + const XpValidatePoolsRec* vpr); +void XpValidatePrinterPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidateJobPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidateDocumentPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidatePagePool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); + +#endif /* _XP_PRINT_SERVER_ */ + +#endif /* _Xp_AttrValid_h - don't add anything after this line */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BT.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BT.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BT.h (revision 51223) @@ -0,0 +1,33 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/BT.h,v 1.2 1998/07/25 16:57:17 dawes Exp $ */ + +#include "xf86RamDac.h" + +RamDacHelperRecPtr BTramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void BTramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void BTramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void BTramdacSetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); + +#define ATT20C504_RAMDAC (VENDOR_BT << 16) | 0x00 +#define ATT20C505_RAMDAC (VENDOR_BT << 16) | 0x01 +#define BT485_RAMDAC (VENDOR_BT << 16) | 0x02 + +/* + * BT registers + */ + +#define BT_WRITE_ADDR 0x00 +#define BT_RAMDAC_DATA 0x01 +#define BT_PIXEL_MASK 0x02 +#define BT_READ_ADDR 0x03 +#define BT_CURS_WR_ADDR 0x04 +#define BT_CURS_DATA 0x05 +#define BT_COMMAND_REG_0 0x06 +#define BT_CURS_RD_ADDR 0x07 +#define BT_COMMAND_REG_1 0x08 +#define BT_COMMAND_REG_2 0x09 +#define BT_STATUS_REG 0x0A +#define BT_CURS_RAM_DATA 0x0B +#define BT_CURS_X_LOW 0x0C +#define BT_CURS_X_HIGH 0x0D +#define BT_CURS_Y_LOW 0x0E +#define BT_CURS_Y_HIGH 0x0F Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BTPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BTPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/BTPriv.h (revision 51223) @@ -0,0 +1,21 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/BTPriv.h,v 1.1.2.1 1998/07/18 17:54:00 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "BT.h" + +typedef struct { + char *DeviceName; +} xf86BTramdacInfo; + +extern xf86BTramdacInfo BTramdacDeviceInfo[]; + +#ifdef INIT_BT_RAMDAC_INFO +xf86BTramdacInfo BTramdacDeviceInfo[] = { + {"AT&T 20C504"}, + {"AT&T 20C505"}, + {"BT485/484"} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Canvas.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Canvas.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Canvas.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + +Copyright 1987, 1998 The Open Group +Copyright 2002 Red Hat Inc., Durham, North Carolina. + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + * This file was originally taken from xc/lib/Xaw/Template.h + */ + +#ifndef _Canvas_h +#define _Canvas_h + +#include + +#define XtNcanvasExposeCallback "canvasExposeCallback" +#define XtCcanvasExposeCallback "CanvasExposeCallback" +#define XtNcanvasResizeCallback "canvasResizeCallback" +#define XtCcanvasResizeCallback "CanvasResizeCallback" + +typedef struct _CanvasClassRec *CanvasWidgetClass; +typedef struct _CanvasRec *CanvasWidget; +extern WidgetClass canvasWidgetClass; + +typedef struct _CanvasExposeDataRec { + Widget w; + XEvent *event; + Region region; +} CanvasExposeDataRec, *CanvasExposeDataPtr; + +#endif /* _Canvas_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/CanvasP.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/CanvasP.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/CanvasP.h (revision 51223) @@ -0,0 +1,66 @@ +/* $XFree86$ */ +/* + +Copyright 1987, 1998 The Open Group +Copyright 2002 Red Hat Inc., Durham, North Carolina. + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + * This file was originally taken from xc/lib/Xaw/TemplateP.h + */ + +#ifndef _CanvasP_h +#define _CanvasP_h + +#include "Canvas.h" + +/* include superclass private header file */ +#include + +typedef struct { + XtPointer extension; +} CanvasClassPart; + +typedef struct _CanvasClassRec { + CoreClassPart core_class; + CanvasClassPart canvas_class; +} CanvasClassRec; + +extern CanvasClassRec canvasClassRec; + +typedef struct { + XtCallbackList input_callback; + XtCallbackList expose_callback; + XtCallbackList resize_callback; +} CanvasPart; + +typedef struct _CanvasRec { + CorePart core; + CanvasPart canvas; +} CanvasRec; + +#endif /* _CanvasP_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ChkNotMaskEv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ChkNotMaskEv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ChkNotMaskEv.h (revision 51223) @@ -0,0 +1,41 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for #XCheckNotMaskEvent function. \see ChkNotMaskEv.c */ + +#ifndef _CHKNOTMASKEV_H_ +#define _CHKNOTMASKEV_H_ +extern Bool XCheckNotMaskEvent (Display *dpy, long mask, XEvent *event); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Configint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Configint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Configint.h (revision 51223) @@ -0,0 +1,226 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/Configint.h,v 1.21 2003/08/24 17:37:07 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * These definitions are used through out the configuration file parser, but + * they should not be visible outside of the parser. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _Configint_h_ +#define _Configint_h_ + +#include +#include +#include +#include +#include "xf86Parser.h" + +typedef struct +{ + int num; /* returned number */ + char *str; /* private copy of the return-string */ + double realnum; /* returned number as a real */ +} +LexRec, *LexPtr; + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#include "configProcs.h" +#include +#define xf86confmalloc malloc +#define xf86confrealloc realloc +#define xf86confcalloc calloc +#define xf86conffree free + +#define TestFree(a) if (a) { xf86conffree (a); a = NULL; } + +#define parsePrologue(typeptr,typerec) typeptr ptr; \ +if( (ptr=(typeptr)xf86confcalloc(1,sizeof(typerec))) == NULL ) { return NULL; } \ +memset(ptr,0,sizeof(typerec)); + +#define parsePrologueVoid(typeptr,typerec) int token; typeptr ptr; \ +if( (ptr=(typeptr)xf86confcalloc(1,sizeof(typerec))) == NULL ) { return; } \ +memset(ptr,0,sizeof(typerec)); + +#define HANDLE_RETURN(f,func)\ +if ((ptr->f=func) == NULL)\ +{\ + CLEANUP (ptr);\ + return (NULL);\ +} + +#define HANDLE_LIST(field,func,type)\ +{\ +type p = func ();\ +if (p == NULL)\ +{\ + CLEANUP (ptr);\ + return (NULL);\ +}\ +else\ +{\ + ptr->field = (type) xf86addListItem ((glp) ptr->field, (glp) p);\ +}\ +} + +#define Error(a,b) do { \ + xf86parseError (a, b); CLEANUP (ptr); return NULL; \ + } while (0) + +/* + * These are defines for error messages to promote consistency. + * error messages are preceded by the line number, section and file name, + * so these messages should be about the specific keyword and syntax in error. + * To help limit namespace polution, end each with _MSG. + * limit messages to 70 characters if possible. + */ + +#define BAD_OPTION_MSG \ +"The Option keyword requires 1 or 2 quoted strings to follow it." +#define INVALID_KEYWORD_MSG \ +"\"%s\" is not a valid keyword in this section." +#define INVALID_SECTION_MSG \ +"\"%s\" is not a valid section name." +#define UNEXPECTED_EOF_MSG \ +"Unexpected EOF. Missing EndSection keyword?" +#define QUOTE_MSG \ +"The %s keyword requires a quoted string to follow it." +#define NUMBER_MSG \ +"The %s keyword requires a number to follow it." +#define POSITIVE_INT_MSG \ +"The %s keyword requires a positive integer to follow it." +#define ZAXISMAPPING_MSG \ +"The ZAxisMapping keyword requires 2 positive numbers or X or Y to follow it." +#define AUTOREPEAT_MSG \ +"The AutoRepeat keyword requires 2 numbers (delay and rate) to follow it." +#define XLEDS_MSG \ +"The XLeds keyword requries one or more numbers to follow it." +#define DACSPEED_MSG \ +"The DacSpeed keyword must be followed by a list of up to %d numbers." +#define DISPLAYSIZE_MSG \ +"The DisplaySize keyword must be followed by the width and height in mm." +#define HORIZSYNC_MSG \ +"The HorizSync keyword must be followed by a list of numbers or ranges." +#define VERTREFRESH_MSG \ +"The VertRefresh keyword must be followed by a list of numbers or ranges." +#define VIEWPORT_MSG \ +"The Viewport keyword must be followed by an X and Y value." +#define VIRTUAL_MSG \ +"The Virtual keyword must be followed by a width and height value." +#define WEIGHT_MSG \ +"The Weight keyword must be followed by red, green and blue values." +#define BLACK_MSG \ +"The Black keyword must be followed by red, green and blue values." +#define WHITE_MSG \ +"The White keyword must be followed by red, green and blue values." +#define SCREEN_MSG \ +"The Screen keyword must be followed by an optional number, a screen name\n" \ +"\tin quotes, and optional position/layout information." +#define INVALID_SCR_MSG \ +"Invalid Screen line." +#define INPUTDEV_MSG \ +"The InputDevice keyword must be followed by an input device name in quotes." +#define INACTIVE_MSG \ +"The Inactive keyword must be followed by a Device name in quotes." +#define UNDEFINED_SCREEN_MSG \ +"Undefined Screen \"%s\" referenced by ServerLayout \"%s\"." +#define UNDEFINED_MONITOR_MSG \ +"Undefined Monitor \"%s\" referenced by Screen \"%s\"." +#define UNDEFINED_MODES_MSG \ +"Undefined Modes Section \"%s\" referenced by Monitor \"%s\"." +#define UNDEFINED_DEVICE_MSG \ +"Undefined Device \"%s\" referenced by Screen \"%s\"." +#define UNDEFINED_ADAPTOR_MSG \ +"Undefined VideoAdaptor \"%s\" referenced by Screen \"%s\"." +#define ADAPTOR_REF_TWICE_MSG \ +"VideoAdaptor \"%s\" already referenced by Screen \"%s\"." +#define UNDEFINED_DEVICE_LAY_MSG \ +"Undefined Device \"%s\" referenced by ServerLayout \"%s\"." +#define UNDEFINED_INPUT_MSG \ +"Undefined InputDevice \"%s\" referenced by ServerLayout \"%s\"." +#define NO_IDENT_MSG \ +"This section must have an Identifier line." +#define ONLY_ONE_MSG \ +"This section must have only one of either %s line." +#define UNDEFINED_DRIVER_MSG \ +"Device section \"%s\" must have a Driver line." +#define UNDEFINED_INPUTDRIVER_MSG \ +"InputDevice section \"%s\" must have a Driver line." +#define INVALID_GAMMA_MSG \ +"gamma correction value(s) expected\n either one value or three r/g/b values." +#define GROUP_MSG \ +"The Group keyword must be followed by either a group name in quotes or\n" \ +"\ta numerical group id." +#define MULTIPLE_MSG \ +"Multiple \"%s\" lines." + +/* Warning messages */ +#define OBSOLETE_MSG \ +"Ignoring obsolete keyword \"%s\"." +#define MOVED_TO_FLAGS_MSG \ +"Keyword \"%s\" is now an Option flag in the ServerFlags section." + +#endif /* _Configint_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/DiPrint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/DiPrint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/DiPrint.h (revision 51223) @@ -0,0 +1,81 @@ +/* $Xorg: DiPrint.h,v 1.3 2000/08/17 19:48:04 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* + * The XpDiListEntry struct is the type of each element of the array + * handed back to the extension code to handle a GetPrinterList request. + * We don't use the printerDb directly because of the desire to handle + * multiple locales. Creating this new array for each GetPrinterList + * request will allow us to build it with the description in the locale of + * the requesting client. + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XpDiPrint_H_ +#define _XpDiPrint_H_ 1 + +#include "scrnintstr.h" + +typedef struct _diListEntry { + char *name; + char *description; + char *localeName; + unsigned long rootWinId; +} XpDiListEntry; + +extern void XpDiFreePrinterList(XpDiListEntry **list); + +extern XpDiListEntry **XpDiGetPrinterList( + int nameLen, + char *name, + int localeLen, + char *locale); + +extern char * XpDiGetDriverName(int index, char *printerName); + +extern WindowPtr XpDiValidatePrinter(char *printerName, int printerNameLen); + +extern int PrinterOptions(int argc, char **argv, int i); + +extern void PrinterUseMsg(void); + +extern void PrinterInitGlobals(void); + +extern void PrinterInitOutput(ScreenInfo *pScreenInfo, int argc, char **argv); + +extern void _XpVoidNoop(void); + +extern Bool _XpBoolNoop(void); + +#endif /* _XpDiPrint_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/EVIstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/EVIstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/EVIstruct.h (revision 51223) @@ -0,0 +1,60 @@ +/* $Xorg: EVIstruct.h,v 1.3 2000/08/17 19:47:55 cpqbld Exp $ */ +/************************************************************ +Copyright (c) 1997 by Silicon Graphics Computer Systems, Inc. +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright +notice appear in all copies and that both that copyright +notice and this permission notice appear in supporting +documentation, and that the name of Silicon Graphics not be +used in advertising or publicity pertaining to distribution +of the software without specific prior written permission. +Silicon Graphics makes no representation about the suitability +of this software for any purpose. It is provided "as is" +without any express or implied warranty. +SILICON GRAPHICS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS +SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SILICON +GRAPHICS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL +DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE +OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. +********************************************************/ +/* $XFree86: xc/programs/Xserver/Xext/EVIstruct.h,v 3.5 2003/07/16 01:38:28 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef EVI_STRUCT_H +#define EVI_STRUCT_H + +/* + ****************************************************************************** + ** Per-ddx data + ****************************************************************************** + */ + +typedef int (*GetVisualInfoProc)( + VisualID32*, + int, + xExtendedVisualInfo**, + int*, + VisualID32**, + int* +); + +typedef void (*FreeVisualInfoProc)( + xExtendedVisualInfo*, + VisualID32* +); +typedef struct _EviPrivRec { + GetVisualInfoProc getVisualInfo; + FreeVisualInfoProc freeVisualInfo; +} EviPrivRec, *EviPrivPtr; + +extern EviPrivPtr eviDDXInit(void); +extern void eviDDXReset(void); + +#endif /* EVI_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBM.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBM.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBM.h (revision 51223) @@ -0,0 +1,386 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/IBM.h,v 1.7 1999/02/12 22:52:11 hohndel Exp $ */ + +#include + +RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +void IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +unsigned long IBMramdac526CalculateMNPCForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP, unsigned long *rC); +unsigned long IBMramdac640CalculateMNPCForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP, unsigned long *rC); +void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr); +void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr); + +typedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr); +IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void); + +#define IBM524_RAMDAC ((VENDOR_IBM << 16) | 0x00) +#define IBM524A_RAMDAC ((VENDOR_IBM << 16) | 0x01) +#define IBM525_RAMDAC ((VENDOR_IBM << 16) | 0x02) +#define IBM526_RAMDAC ((VENDOR_IBM << 16) | 0x03) +#define IBM526DB_RAMDAC ((VENDOR_IBM << 16) | 0x04) +#define IBM528_RAMDAC ((VENDOR_IBM << 16) | 0x05) +#define IBM528A_RAMDAC ((VENDOR_IBM << 16) | 0x06) +#define IBM624_RAMDAC ((VENDOR_IBM << 16) | 0x07) +#define IBM624DB_RAMDAC ((VENDOR_IBM << 16) | 0x08) +#define IBM640_RAMDAC ((VENDOR_IBM << 16) | 0x09) + +/* + * IBM Ramdac registers + */ + +#define IBMRGB_REF_FREQ_1 14.31818 +#define IBMRGB_REF_FREQ_2 50.00000 + +#define IBMRGB_rev 0x00 +#define IBMRGB_id 0x01 +#define IBMRGB_misc_clock 0x02 +#define IBMRGB_sync 0x03 +#define IBMRGB_hsync_pos 0x04 +#define IBMRGB_pwr_mgmt 0x05 +#define IBMRGB_dac_op 0x06 +#define IBMRGB_pal_ctrl 0x07 +#define IBMRGB_sysclk 0x08 /* not RGB525 */ +#define IBMRGB_pix_fmt 0x0a +#define IBMRGB_8bpp 0x0b +#define IBMRGB_16bpp 0x0c +#define IBMRGB_24bpp 0x0d +#define IBMRGB_32bpp 0x0e +#define IBMRGB_pll_ctrl1 0x10 +#define IBMRGB_pll_ctrl2 0x11 +#define IBMRGB_pll_ref_div_fix 0x14 +#define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */ +#define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */ +/* #define IBMRGB_f0 0x20 */ + +#define IBMRGB_sysclk_n 0x15 +#define IBMRGB_sysclk_m 0x16 +#define IBMRGB_sysclk_p 0x17 +#define IBMRGB_sysclk_c 0x18 + +#define IBMRGB_m0 0x20 +#define IBMRGB_n0 0x21 +#define IBMRGB_p0 0x22 +#define IBMRGB_c0 0x23 +#define IBMRGB_m1 0x24 +#define IBMRGB_n1 0x25 +#define IBMRGB_p1 0x26 +#define IBMRGB_c1 0x27 +#define IBMRGB_m2 0x28 +#define IBMRGB_n2 0x29 +#define IBMRGB_p2 0x2a +#define IBMRGB_c2 0x2b +#define IBMRGB_m3 0x2c +#define IBMRGB_n3 0x2d +#define IBMRGB_p3 0x2e +#define IBMRGB_c3 0x2f + +#define IBMRGB_curs 0x30 +#define IBMRGB_curs_xl 0x31 +#define IBMRGB_curs_xh 0x32 +#define IBMRGB_curs_yl 0x33 +#define IBMRGB_curs_yh 0x34 +#define IBMRGB_curs_hot_x 0x35 +#define IBMRGB_curs_hot_y 0x36 +#define IBMRGB_curs_col1_r 0x40 +#define IBMRGB_curs_col1_g 0x41 +#define IBMRGB_curs_col1_b 0x42 +#define IBMRGB_curs_col2_r 0x43 +#define IBMRGB_curs_col2_g 0x44 +#define IBMRGB_curs_col2_b 0x45 +#define IBMRGB_curs_col3_r 0x46 +#define IBMRGB_curs_col3_g 0x47 +#define IBMRGB_curs_col3_b 0x48 +#define IBMRGB_border_col_r 0x60 +#define IBMRGB_border_col_g 0x61 +#define IBMRGB_botder_col_b 0x62 +#define IBMRGB_key 0x68 +#define IBMRGB_key_mask 0x6C +#define IBMRGB_misc1 0x70 +#define IBMRGB_misc2 0x71 +#define IBMRGB_misc3 0x72 +#define IBMRGB_misc4 0x73 /* not RGB525 */ +#define IBMRGB_key_control 0x78 +#define IBMRGB_dac_sense 0x82 +#define IBMRGB_misr_r 0x84 +#define IBMRGB_misr_g 0x86 +#define IBMRGB_misr_b 0x88 +#define IBMRGB_pll_vco_div_in 0x8e +#define IBMRGB_pll_ref_div_in 0x8f +#define IBMRGB_vram_mask_0 0x90 +#define IBMRGB_vram_mask_1 0x91 +#define IBMRGB_vram_mask_2 0x92 +#define IBMRGB_vram_mask_3 0x93 +#define IBMRGB_curs_array 0x100 + + + +/* Constants rgb525.h */ + +/* RGB525_REVISION_LEVEL */ +#define RGB525_PRODUCT_REV_LEVEL 0xf0 + +/* RGB525_ID */ +#define RGB525_PRODUCT_ID 0x01 + +/* RGB525_MISC_CTRL_1 */ +#define MISR_CNTL_ENABLE 0x80 +#define VMSK_CNTL_ENABLE 0x40 +#define PADR_RDMT_RDADDR 0x0 +#define PADR_RDMT_PAL_STATE 0x20 +#define SENS_DSAB_DISABLE 0x10 +#define SENS_SEL_BIT3 0x0 +#define SENS_SEL_BIT7 0x08 +#define VRAM_SIZE_32 0x0 +#define VRAM_SIZE_64 0x01 + +/* RGB525_MISC_CTRL_2 */ +#define PCLK_SEL_LCLK 0x0 +#define PCLK_SEL_PLL 0x40 +#define PCLK_SEL_EXT 0x80 +#define INTL_MODE_ENABLE 0x20 +#define BLANK_CNTL_ENABLE 0x10 +#define COL_RES_6BIT 0x0 +#define COL_RES_8BIT 0x04 +#define PORT_SEL_VGA 0x0 +#define PORT_SEL_VRAM 0x01 + +/* RGB525_MISC_CTRL_3 */ +#define SWAP_RB 0x80 +#define SWAP_WORD_LOHI 0x0 +#define SWAP_WORD_HILO 0x10 +#define SWAP_NIB_HILO 0x0 +#define SWAP_NIB_LOHI 0x02 + +/* RGB525_MISC_CLK_CTRL */ +#define DDOT_CLK_ENABLE 0x0 +#define DDOT_CLK_DISABLE 0x80 +#define SCLK_ENABLE 0x0 +#define SCLK_DISABLE 0x40 +#define B24P_DDOT_PLL 0x0 +#define B24P_DDOT_SCLK 0x20 +#define DDOT_DIV_PLL_1 0x0 +#define DDOT_DIV_PLL_2 0x02 +#define DDOT_DIV_PLL_4 0x04 +#define DDOT_DIV_PLL_8 0x06 +#define DDOT_DIV_PLL_16 0x08 +#define PLL_DISABLE 0x0 +#define PLL_ENABLE 0x01 + +/* RGB525_SYNC_CTRL */ +#define DLY_CNTL_ADD 0x0 +#define DLY_SYNC_NOADD 0x80 +#define CSYN_INVT_DISABLE 0x0 +#define CSYN_INVT_ENABLE 0x40 +#define VSYN_INVT_DISABLE 0x0 +#define VSYN_INVT_ENABLE 0x20 +#define HSYN_INVT_DISABLE 0x0 +#define HSYN_INVT_ENABLE 0x10 +#define VSYN_CNTL_NORMAL 0x0 +#define VSYN_CNTL_HIGH 0x04 +#define VSYN_CNTL_LOW 0x08 +#define VSYN_CNTL_DISABLE 0x0C +#define HSYN_CNTL_NORMAL 0x0 +#define HSYN_CNTL_HIGH 0x01 +#define HSYN_CNTL_LOW 0x02 +#define HSYN_CNTL_DISABLE 0x03 + +/* RGB525_HSYNC_CTRL */ +#define HSYN_POS(n) (n) + +/* RGB525_POWER_MANAGEMENT */ +#define SCLK_PWR_NORMAL 0x0 +#define SCLK_PWR_DISABLE 0x10 +#define DDOT_PWR_NORMAL 0x0 +#define DDOT_PWR_DISABLE 0x08 +#define SYNC_PWR_NORMAL 0x0 +#define SYNC_PWR_DISABLE 0x04 +#define ICLK_PWR_NORMAL 0x0 +#define ICLK_PWR_DISABLE 0x02 +#define DAC_PWR_NORMAL 0x0 +#define DAC_PWR_DISABLE 0x01 + +/* RGB525_DAC_OPERATION */ +#define SOG_DISABLE 0x0 +#define SOG_ENABLE 0x08 +#define BRB_NORMAL 0x0 +#define BRB_ALWAYS 0x04 +#define DSR_DAC_SLOW 0x02 +#define DSR_DAC_FAST 0x0 +#define DPE_DISABLE 0x0 +#define DPE_ENABLE 0x01 + +/* RGB525_PALETTE_CTRL */ +#define SIXBIT_LINEAR_ENABLE 0x0 +#define SIXBIT_LINEAR_DISABLE 0x80 +#define PALETTE_PARITION(n) (n) + +/* RGB525_PIXEL_FORMAT */ +#define PIXEL_FORMAT_4BPP 0x02 +#define PIXEL_FORMAT_8BPP 0x03 +#define PIXEL_FORMAT_16BPP 0x04 +#define PIXEL_FORMAT_24BPP 0x05 +#define PIXEL_FORMAT_32BPP 0x06 + +/* RGB525_8BPP_CTRL */ +#define B8_DCOL_INDIRECT 0x0 +#define B8_DCOL_DIRECT 0x01 + +/* RGB525_16BPP_CTRL */ +#define B16_DCOL_INDIRECT 0x0 +#define B16_DCOL_DYNAMIC 0x40 +#define B16_DCOL_DIRECT 0xC0 +#define B16_POL_FORCE_BYPASS 0x0 +#define B16_POL_FORCE_LOOKUP 0x20 +#define B16_ZIB 0x0 +#define B16_LINEAR 0x04 +#define B16_555 0x0 +#define B16_565 0x02 +#define B16_SPARSE 0x0 +#define B16_CONTIGUOUS 0x01 + +/* RGB525_24BPP_CTRL */ +#define B24_DCOL_INDIRECT 0x0 +#define B24_DCOL_DIRECT 0x01 + +/* RGB525_32BPP_CTRL */ +#define B32_POL_FORCE_BYPASS 0x0 +#define B32_POL_FORCE_LOOKUP 0x04 +#define B32_DCOL_INDIRECT 0x0 +#define B32_DCOL_DYNAMIC 0x01 +#define B32_DCOL_DIRECT 0x03 + +/* RGB525_PLL_CTRL_1 */ +#define REF_SRC_REFCLK 0x0 +#define REF_SRC_EXTCLK 0x10 +#define PLL_EXT_FS_3_0 0x0 +#define PLL_EXT_FS_2_0 0x01 +#define PLL_CNTL2_3_0 0x02 +#define PLL_CNTL2_2_0 0x03 + +/* RGB525_PLL_CTRL_2 */ +#define PLL_INT_FS_3_0(n) (n) +#define PLL_INT_FS_2_0(n) (n) + +/* RGB525_PLL_REF_DIV_COUNT */ +#define REF_DIV_COUNT(n) (n) + +/* RGB525_F0 - RGB525_F15 */ +#define VCO_DIV_COUNT(n) (n) + +/* RGB525_PLL_REFCLK values */ +#define RGB525_PLL_REFCLK_MHz(n) ((n)/2) + +/* RGB525_CURSOR_CONTROL */ +#define SMLC_PART_0 0x0 +#define SMLC_PART_1 0x40 +#define SMLC_PART_2 0x80 +#define SMLC_PART_3 0xC0 +#define PIX_ORDER_RL 0x0 +#define PIX_ORDER_LR 0x20 +#define LOC_READ_LAST 0x0 +#define LOC_READ_ACTUAL 0x10 +#define UPDT_CNTL_DELAYED 0x0 +#define UPDT_CNTL_IMMEDIATE 0x08 +#define CURSOR_SIZE_32 0x0 +#define CURSOR_SIZE_64 0x40 +#define CURSOR_MODE_OFF 0x0 +#define CURSOR_MODE_3_COLOR 0x01 +#define CURSOR_MODE_2_COLOR_HL 0x02 +#define CURSOR_MODE_2_COLOR 0x03 + +/* RGB525_REVISION_LEVEL */ +#define REVISION_LEVEL 0xF0 /* predefined */ + +/* RGB525_ID */ +#define ID_CODE 0x01 /* predefined */ + +/* MISR status */ +#define RGB525_MISR_DONE 0x01 + +/* the IBMRGB640 is rather different from the rest of the RAMDACs, + so we define a completely new set of register names for it */ +#define RGB640_SER_07_00 0x02 +#define RGB640_SER_15_08 0x03 +#define RGB640_SER_23_16 0x04 +#define RGB640_SER_31_24 0x05 +#define RGB640_SER_WID_03_00 0x06 +#define RGB640_SER_WID_07_04 0x07 +#define RGB640_SER_MODE 0x08 +#define IBM640_SER_2_1 0x00 +#define IBM640_SER_4_1 0x01 +#define IBM640_SER_8_1 0x02 +#define IBM640_SER_16_1 0x03 +#define IBM640_SER_16_3 0x05 +#define IBM640_SER_5_1 0x06 +#define RGB640_PIXEL_INTERLEAVE 0x09 +#define RGB640_MISC_CONF 0x0a +#define IBM640_PCLK 0x00 +#define IBM640_PCLK_2 0x40 +#define IBM640_PCLK_4 0x80 +#define IBM640_PCLK_8 0xc0 +#define IBM640_PSIZE10 0x10 +#define IBM640_LCI 0x08 +#define IBM640_WIDCTL_MASK 0x07 +#define RGB640_VGA_CONTROL 0x0b +#define IBM640_RDBK 0x04 +#define IBM640_PSIZE8 0x02 +#define IBM640_VRAM 0x01 +#define RGB640_DAC_CONTROL 0x0d +#define IBM640_MONO 0x08 +#define IBM640_DACENBL 0x04 +#define IBM640_SHUNT 0x02 +#define IBM640_SLOWSLEW 0x01 +#define RGB640_OUTPUT_CONTROL 0x0e +#define IBM640_RDAI 0x04 +#define IBM640_WDAI 0x02 +#define IBM640_WATCTL 0x01 +#define RGB640_SYNC_CONTROL 0x0f +#define IBM640_PWR 0x20 +#define IBM640_VSP 0x10 +#define IBM640_HSP 0x08 +#define IBM640_CSE 0x04 +#define IBM640_CSG 0x02 +#define IBM640_BPE 0x01 +#define RGB640_PLL_N 0x10 +#define RGB640_PLL_M 0x11 +#define RGB640_PLL_P 0x12 +#define RGB640_PLL_CTL 0x13 +#define IBM640_PLL_EN 0x04 +#define IBM640_PLL_HIGH 0x10 +#define IBM640_PLL_LOW 0x01 +#define RGB640_AUX_PLL_CTL 0x17 +#define IBM640_AUXPLL 0x04 +#define IBM640_AUX_HI 0x02 +#define IBM640_AUX_LO 0x01 +#define RGB640_CHROMA_KEY0 0x20 +#define RGB640_CHROMA_MASK0 0x21 +#define RGB640_CURS_X_LOW 0x40 +#define RGB640_CURS_X_HIGH 0x41 +#define RGB640_CURS_Y_LOW 0x42 +#define RGB640_CURS_Y_HIGH 0x43 +#define RGB640_CURS_OFFSETX 0x44 +#define RGB640_CURS_OFFSETY 0x45 +#define RGB640_CURSOR_CONTROL 0x4B +#define IBM640_CURS_OFF 0x00 +#define IBM640_CURS_MODE0 0x01 +#define IBM640_CURS_MODE1 0x02 +#define IBM640_CURS_MODE2 0x03 +#define IBM640_CURS_ADV 0x04 +#define RGB640_CROSSHAIR_CONTROL 0x57 +#define RGB640_VRAM_MASK0 0xf0 +#define RGB640_VRAM_MASK1 0xf1 +#define RGB640_VRAM_MASK2 0xf2 +#define RGB640_DIAGS 0xfa +#define RGB640_CURS_WRITE 0x1000 +#define RGB640_CURS_COL0 0x4800 +#define RGB640_CURS_COL1 0x4801 +#define RGB640_CURS_COL2 0x4802 +#define RGB640_CURS_COL3 0x4803 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBMPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBMPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/IBMPriv.h (revision 51223) @@ -0,0 +1,28 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/IBMPriv.h,v 1.1.2.2 1998/07/18 17:54:01 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "IBM.h" + +typedef struct { + char *DeviceName; +} xf86IBMramdacInfo; + +extern xf86IBMramdacInfo IBMramdacDeviceInfo[]; + +#ifdef INIT_IBM_RAMDAC_INFO +xf86IBMramdacInfo IBMramdacDeviceInfo[] = { + {"IBM 524"}, + {"IBM 524A"}, + {"IBM 525"}, + {"IBM 526"}, + {"IBM 526DB(DoubleBuffer)"}, + {"IBM 528"}, + {"IBM 528A"}, + {"IBM 624"}, + {"IBM 624DB(DoubleBuffer)"}, + {"IBM 640"} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OScompiler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OScompiler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OScompiler.h (revision 51223) @@ -0,0 +1,61 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/OScompiler.h,v 1.3 1999/01/31 12:22:15 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/* $XConsortium: OScompiler.h /main/4 1996/02/21 17:56:09 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef __COMPILER_DEPENDANCIES__ +#define __COMPILER_DEPENDANCIES__ + +#define MOVE( src, dst, length ) memcpy( dst, src, length) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define ABS(x) (((x)>0)?(x):-(x)) + +#include "misc.h" +#include "xf86_ansic.h" +#include "compiler.h" + +#ifdef lint +/* So that lint doesn't complain about constructs it doesn't understand */ +#ifdef volatile +#undef volatile +#endif +#define volatile +#ifdef const +#undef const +#endif +#define const +#ifdef signed +#undef signed +#endif +#define signed +#ifdef _ANSI_DECLS_ +#undef _ANSI_DECLS_ +#endif +#endif + +#endif /* !__COMPILER_DEPENDANCIES__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Oid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Oid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Oid.h (revision 51223) @@ -0,0 +1,294 @@ +/* $Xorg: Oid.h,v 1.3 2000/08/17 19:48:06 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_Oid_h +#define _Xp_Oid_h + +#include + +/* + * include the auto-generated XpOid enum definition + */ +#include "OidDefs.h" + +/* + * messages + */ +#define XPMSG_WARN_MSS "Syntax error parsing medium-source-sizes" +#define XPMSG_WARN_ITM "Syntax error parsing input-trays-medium" +#define XPMSG_WARN_DOC_FMT "Syntax error parsing document format" +#define XPMSG_WARN_DOCFMT_LIST "Syntax error parsing document format list" +#define XPMSG_WARN_CARD_LIST "Syntax error parsing cardinal list" + +/* + * macros for memory allocation + */ +#define XpOidMalloc(size) ((char*)Xalloc((unsigned long)(size))) +#define XpOidCalloc(count, size) \ + ((char*)Xcalloc((unsigned long)((count)*(size)))) +#define XpOidFree(mem) (Xfree((unsigned long*)(mem))) + +/* + * list of object identifiers + */ +typedef struct _XpOidList +{ + XpOid* list; + int count; +} XpOidList; + +/* + * linked list of object identifiers + */ +typedef struct XpOidNodeStruct +{ + XpOid oid; + struct XpOidNodeStruct* next; +} *XpOidNode; + +typedef struct _XpOidLinkedList +{ + XpOidNode head; + XpOidNode tail; + XpOidNode current; + int count; +} XpOidLinkedList; + +/* + * XpOidMediumSourceSize and related definitions + */ +typedef struct +{ + float minimum_x; + float maximum_x; + float minimum_y; + float maximum_y; +} XpOidArea; + +typedef struct +{ + float lower_bound; + float upper_bound; +} XpOidRealRange; + +typedef struct +{ + XpOidRealRange range_across_feed; + float increment_across_feed; + XpOidRealRange range_in_feed; + float increment_in_feed; + BOOL long_edge_feeds; + XpOidArea assured_reproduction_area; +} XpOidMediumContinuousSize; + +typedef struct +{ + XpOid page_size; + BOOL long_edge_feeds; + XpOidArea assured_reproduction_area; +} XpOidMediumDiscreteSize; + +typedef struct +{ + XpOidMediumDiscreteSize* list; + int count; +} XpOidMediumDiscreteSizeList; + +typedef struct +{ + XpOid input_tray; /* may be set to xpoid_none or xpoid_unspecified */ + enum { XpOidMediumSS_DISCRETE, XpOidMediumSS_CONTINUOUS } mstag; + union + { + XpOidMediumDiscreteSizeList* discrete; + XpOidMediumContinuousSize* continuous_size; + } ms; /* "ms" is short for medium-size */ + +} XpOidMediumSourceSize; + +typedef struct +{ + XpOidMediumSourceSize* mss; + int count; +} XpOidMediumSS; + + +typedef struct +{ + XpOid input_tray; /* may be set to xpoid_none */ + XpOid medium; +} XpOidTrayMedium; + +typedef struct +{ + XpOidTrayMedium* list; + int count; +} XpOidTrayMediumList; + +typedef enum { + XPOID_NOTIFY_UNSUPPORTED, + XPOID_NOTIFY_NONE, + XPOID_NOTIFY_EMAIL +} XpOidNotify; + +typedef struct +{ + unsigned long *list; + int count; +} XpOidCardList; + +typedef struct +{ + char* format; + char* variant; + char* version; +} XpOidDocFmt; + +typedef struct +{ + XpOidDocFmt* list; + int count; +} XpOidDocFmtList; + + +/* + * XpOid public methods + */ +const char* XpOidString(XpOid); +int XpOidStringLength(XpOid); +XpOid XpOidFromString(const char* value); +BOOL XpOidTrayMediumListHasTray(const XpOidTrayMediumList* list, XpOid tray); + +/* + * XpOidList public methods + */ +XpOidList* XpOidListNew(const char* value_string, + const XpOidList* valid_oids); +#define XpOidListInit(l, a, c) { (l)->list = (a); (l)->count = (c); } +void XpOidListDelete(XpOidList*); +#define XpOidListCount(l) ((l) ? (l)->count : 0) +#define XpOidListGetOid(l, i) ((l) ? (l)->list[(i)] : xpoid_none) +int XpOidListGetIndex(const XpOidList* list, XpOid oid); +BOOL XpOidListHasOid(const XpOidList* list, XpOid oid); +char* XpOidListString(const XpOidList*); + + +/* + * XpOidLinkedList public methods + */ +XpOidLinkedList* XpOidLinkedListNew(); +void XpOidLinkedListDelete(XpOidLinkedList*); +#define XpOidLinkedListCount(l) ((l) ? (l)->count : 0) +XpOid XpOidLinkedListGetOid(XpOidLinkedList* list, int i); +void XpOidLinkedListAddOid(XpOidLinkedList* list, XpOid oid); +int XpOidLinkedListGetIndex(XpOidLinkedList* list, XpOid oid); +BOOL XpOidLinkedListHasOid(XpOidLinkedList* list, + XpOid oid); +XpOid XpOidLinkedListFirstOid(XpOidLinkedList* list); +XpOid XpOidLinkedListNextOid(XpOidLinkedList* list); + +/* + * XpOidMediumSourceSize public methods + */ +XpOidMediumSS* XpOidMediumSSNew(const char* value_string, + const XpOidList* valid_trays, + const XpOidList* valid_medium_sizes); +void XpOidMediumSSDelete(XpOidMediumSS*); +#define XpOidMediumSSCount(me) ((me) ? (me)->count : 0) +BOOL XpOidMediumSSHasSize(XpOidMediumSS*, XpOid medium_size); +char* XpOidMediumSSString(const XpOidMediumSS*); + +/* + * XpOidTrayMediumList public methods + */ +XpOidTrayMediumList* XpOidTrayMediumListNew(const char* value_string, + const XpOidList* valid_trays, + const XpOidMediumSS* msss); +void XpOidTrayMediumListDelete(XpOidTrayMediumList* me); +#define XpOidTrayMediumListCount(me) ((me) ? (me)->count : 0) +#define XpOidTrayMediumListTray(me, i) \ + ((me) ? (me)->list[(i)].input_tray : xpoid_none) +#define XpOidTrayMediumListMedium(me, i) \ + ((me) ? (me)->list[(i)].medium : xpoid_none) +char* XpOidTrayMediumListString(const XpOidTrayMediumList*); + +/* + * XpOidNotify public methods + */ +XpOidNotify XpOidNotifyParse(const char* value_string); +const char* XpOidNotifyString(XpOidNotify notify); + +/* + * XpOidDocFmt public methods + */ +XpOidDocFmt* XpOidDocFmtNew(const char* value_string); +void XpOidDocFmtDelete(XpOidDocFmt*); +char* XpOidDocFmtString(XpOidDocFmt*); + +/* + * XpOidDocFmtList public methods + */ +XpOidDocFmtList* XpOidDocFmtListNew(const char* value_string, + const XpOidDocFmtList* valid_fmts); +void XpOidDocFmtListDelete(XpOidDocFmtList*); +char* XpOidDocFmtListString(const XpOidDocFmtList*); +#define XpOidDocFmtListCount(me) ((me) ? (me)->count : 0) +#define XpOidDocFmtListGetDocFmt(me, i) \ + ((me) ? &(me)->list[(i)] : (XpDocFmt*)NULL) +BOOL XpOidDocFmtListHasFmt(const XpOidDocFmtList* list, + const XpOidDocFmt* fmt); +/* + * XpOidCardList public methods + */ +XpOidCardList* XpOidCardListNew(const char* value_string, + const XpOidCardList* valid_cards); +#define XpOidCardListInit(l, a, c) { (l)->list = (a); (l)->count = (c); } +void XpOidCardListDelete(XpOidCardList*); +char* XpOidCardListString(const XpOidCardList*); +#define XpOidCardListCount(me) ((me) ? (me)->count : 0) +#define XpOidCardListGetCard(me, i) ((me) ? (me)->list[(i)] : 0) +BOOL XpOidCardListHasCard(const XpOidCardList*, unsigned long); + +/* + * misc parsing functions + */ +BOOL XpOidParseUnsignedValue(const char* value_string, + const char** ptr_return, + unsigned long* unsigned_return); + + +#endif /* _Xp_Oid_h - don't add anything after this line */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidDefs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidDefs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidDefs.h (revision 51223) @@ -0,0 +1,171 @@ +/* $Xorg: OidDefs.h,v 1.4 2001/03/14 18:45:13 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* This is an automatically-generated file. Do not edit. */ + +typedef enum { + xpoid_none, + xpoid_unspecified, + xpoid_att_descriptor, + xpoid_att_content_orientation, + xpoid_att_copy_count, + xpoid_att_default_printer_resolution, + xpoid_att_default_input_tray, + xpoid_att_default_medium, + xpoid_att_document_format, + xpoid_att_plex, + xpoid_att_xp_listfonts_modes, + xpoid_att_job_name, + xpoid_att_job_owner, + xpoid_att_notification_profile, + xpoid_att_xp_setup_state, + xpoid_att_xp_spooler_command_options, + xpoid_att_content_orientations_supported, + xpoid_att_document_formats_supported, + xpoid_att_dt_pdm_command, + xpoid_att_input_trays_medium, + xpoid_att_medium_source_sizes_supported, + xpoid_att_plexes_supported, + xpoid_att_printer_model, + xpoid_att_printer_name, + xpoid_att_printer_resolutions_supported, + xpoid_att_xp_embedded_formats_supported, + xpoid_att_xp_listfonts_modes_supported, + xpoid_att_xp_page_attributes_supported, + xpoid_att_xp_raw_formats_supported, + xpoid_att_xp_setup_proviso, + xpoid_att_document_attributes_supported, + xpoid_att_job_attributes_supported, + xpoid_att_locale, + xpoid_att_multiple_documents_supported, + xpoid_att_available_compression, + xpoid_att_available_compressions_supported, + xpoid_val_content_orientation_portrait, + xpoid_val_content_orientation_landscape, + xpoid_val_content_orientation_reverse_portrait, + xpoid_val_content_orientation_reverse_landscape, + xpoid_val_medium_size_iso_a0, + xpoid_val_medium_size_iso_a1, + xpoid_val_medium_size_iso_a2, + xpoid_val_medium_size_iso_a3, + xpoid_val_medium_size_iso_a4, + xpoid_val_medium_size_iso_a5, + xpoid_val_medium_size_iso_a6, + xpoid_val_medium_size_iso_a7, + xpoid_val_medium_size_iso_a8, + xpoid_val_medium_size_iso_a9, + xpoid_val_medium_size_iso_a10, + xpoid_val_medium_size_iso_b0, + xpoid_val_medium_size_iso_b1, + xpoid_val_medium_size_iso_b2, + xpoid_val_medium_size_iso_b3, + xpoid_val_medium_size_iso_b4, + xpoid_val_medium_size_iso_b5, + xpoid_val_medium_size_iso_b6, + xpoid_val_medium_size_iso_b7, + xpoid_val_medium_size_iso_b8, + xpoid_val_medium_size_iso_b9, + xpoid_val_medium_size_iso_b10, + xpoid_val_medium_size_na_letter, + xpoid_val_medium_size_na_legal, + xpoid_val_medium_size_executive, + xpoid_val_medium_size_folio, + xpoid_val_medium_size_invoice, + xpoid_val_medium_size_ledger, + xpoid_val_medium_size_quarto, + xpoid_val_medium_size_iso_c3, + xpoid_val_medium_size_iso_c4, + xpoid_val_medium_size_iso_c5, + xpoid_val_medium_size_iso_c6, + xpoid_val_medium_size_iso_designated_long, + xpoid_val_medium_size_na_10x13_envelope, + xpoid_val_medium_size_na_9x12_envelope, + xpoid_val_medium_size_na_number_10_envelope, + xpoid_val_medium_size_na_7x9_envelope, + xpoid_val_medium_size_na_9x11_envelope, + xpoid_val_medium_size_na_10x14_envelope, + xpoid_val_medium_size_na_number_9_envelope, + xpoid_val_medium_size_na_6x9_envelope, + xpoid_val_medium_size_na_10x15_envelope, + xpoid_val_medium_size_monarch_envelope, + xpoid_val_medium_size_a, + xpoid_val_medium_size_b, + xpoid_val_medium_size_c, + xpoid_val_medium_size_d, + xpoid_val_medium_size_e, + xpoid_val_medium_size_jis_b0, + xpoid_val_medium_size_jis_b1, + xpoid_val_medium_size_jis_b2, + xpoid_val_medium_size_jis_b3, + xpoid_val_medium_size_jis_b4, + xpoid_val_medium_size_jis_b5, + xpoid_val_medium_size_jis_b6, + xpoid_val_medium_size_jis_b7, + xpoid_val_medium_size_jis_b8, + xpoid_val_medium_size_jis_b9, + xpoid_val_medium_size_jis_b10, + xpoid_val_medium_size_hp_2x_postcard, + xpoid_val_medium_size_hp_european_edp, + xpoid_val_medium_size_hp_mini, + xpoid_val_medium_size_hp_postcard, + xpoid_val_medium_size_hp_tabloid, + xpoid_val_medium_size_hp_us_edp, + xpoid_val_medium_size_hp_us_government_legal, + xpoid_val_medium_size_hp_us_government_letter, + xpoid_val_plex_simplex, + xpoid_val_plex_duplex, + xpoid_val_plex_tumble, + xpoid_val_input_tray_top, + xpoid_val_input_tray_middle, + xpoid_val_input_tray_bottom, + xpoid_val_input_tray_envelope, + xpoid_val_input_tray_manual, + xpoid_val_input_tray_large_capacity, + xpoid_val_input_tray_main, + xpoid_val_input_tray_side, + xpoid_val_event_report_job_completed, + xpoid_val_delivery_method_electronic_mail, + xpoid_val_xp_setup_mandatory, + xpoid_val_xp_setup_optional, + xpoid_val_xp_setup_ok, + xpoid_val_xp_setup_incomplete, + xpoid_val_xp_list_glyph_fonts, + xpoid_val_xp_list_internal_printer_fonts, + xpoid_val_available_compressions_0, + xpoid_val_available_compressions_01, + xpoid_val_available_compressions_02, + xpoid_val_available_compressions_03, + xpoid_val_available_compressions_012, + xpoid_val_available_compressions_013, + xpoid_val_available_compressions_023, + xpoid_val_available_compressions_0123 +} XpOid; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidStrs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidStrs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/OidStrs.h (revision 51223) @@ -0,0 +1,173 @@ +/* $Xorg: OidStrs.h,v 1.4 2001/03/14 18:45:40 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* This is an automatically-generated file. Do not edit. */ + +static int XpOidStringMapCount = 127; + +static const XpOidStringMapEntry XpOidStringMap[] = { + { "", 0 }, + { "", 0 }, + { "descriptor", 10 }, + { "content-orientation", 19 }, + { "copy-count", 10 }, + { "default-printer-resolution", 26 }, + { "default-input-tray", 18 }, + { "default-medium", 14 }, + { "document-format", 15 }, + { "plex", 4 }, + { "xp-listfonts-modes", 18 }, + { "job-name", 8 }, + { "job-owner", 9 }, + { "notification-profile", 20 }, + { "xp-setup-state", 14 }, + { "xp-spooler-command-options", 26 }, + { "content-orientations-supported", 30 }, + { "document-formats-supported", 26 }, + { "dt-pdm-command", 14 }, + { "input-trays-medium", 18 }, + { "medium-source-sizes-supported", 29 }, + { "plexes-supported", 16 }, + { "printer-model", 13 }, + { "printer-name", 12 }, + { "printer-resolutions-supported", 29 }, + { "xp-embedded-formats-supported", 29 }, + { "xp-listfonts-modes-supported", 28 }, + { "xp-page-attributes-supported", 28 }, + { "xp-raw-formats-supported", 24 }, + { "xp-setup-proviso", 16 }, + { "document-attributes-supported", 29 }, + { "job-attributes-supported", 24 }, + { "locale", 6 }, + { "multiple-documents-supported", 28 }, + { "available-compression", 21 }, + { "available-compressions-supported", 32 }, + { "portrait", 8 }, + { "landscape", 9 }, + { "reverse-portrait", 16 }, + { "reverse-landscape", 17 }, + { "iso-a0", 6 }, + { "iso-a1", 6 }, + { "iso-a2", 6 }, + { "iso-a3", 6 }, + { "iso-a4", 6 }, + { "iso-a5", 6 }, + { "iso-a6", 6 }, + { "iso-a7", 6 }, + { "iso-a8", 6 }, + { "iso-a9", 6 }, + { "iso-a10", 7 }, + { "iso-b0", 6 }, + { "iso-b1", 6 }, + { "iso-b2", 6 }, + { "iso-b3", 6 }, + { "iso-b4", 6 }, + { "iso-b5", 6 }, + { "iso-b6", 6 }, + { "iso-b7", 6 }, + { "iso-b8", 6 }, + { "iso-b9", 6 }, + { "iso-b10", 7 }, + { "na-letter", 9 }, + { "na-legal", 8 }, + { "executive", 9 }, + { "folio", 5 }, + { "invoice", 7 }, + { "ledger", 6 }, + { "quarto", 6 }, + { "iso-c3", 6 }, + { "iso-c4", 6 }, + { "iso-c5", 6 }, + { "iso-c6", 6 }, + { "iso-designated-long", 19 }, + { "na-10x13-envelope", 17 }, + { "na-9x12-envelope", 16 }, + { "na-number-10-envelope", 21 }, + { "na-7x9-envelope", 15 }, + { "na-9x11-envelope", 16 }, + { "na-10x14-envelope", 17 }, + { "na-number-9-envelope", 20 }, + { "na-6x9-envelope", 15 }, + { "na-10x15-envelope", 17 }, + { "monarch-envelope", 16 }, + { "a", 1 }, + { "b", 1 }, + { "c", 1 }, + { "d", 1 }, + { "e", 1 }, + { "jis-b0", 6 }, + { "jis-b1", 6 }, + { "jis-b2", 6 }, + { "jis-b3", 6 }, + { "jis-b4", 6 }, + { "jis-b5", 6 }, + { "jis-b6", 6 }, + { "jis-b7", 6 }, + { "jis-b8", 6 }, + { "jis-b9", 6 }, + { "jis-b10", 7 }, + { "hp-2x-postcard", 14 }, + { "hp-european-edp", 15 }, + { "hp-mini", 7 }, + { "hp-postcard", 11 }, + { "hp-tabloid", 10 }, + { "hp-us-edp", 9 }, + { "hp-us-government-legal", 22 }, + { "hp-us-government-letter", 23 }, + { "simplex", 7 }, + { "duplex", 6 }, + { "tumble", 6 }, + { "top", 3 }, + { "middle", 6 }, + { "bottom", 6 }, + { "envelope", 8 }, + { "manual", 6 }, + { "large-capacity", 14 }, + { "main", 4 }, + { "side", 4 }, + { "event-report-job-completed", 26 }, + { "electronic-mail", 15 }, + { "xp-setup-mandatory", 18 }, + { "xp-setup-optional", 17 }, + { "xp-setup-ok", 11 }, + { "xp-setup-incomplete", 19 }, + { "xp-list-glyph-fonts", 19 }, + { "xp-list-internal-printer-fonts", 30 }, + { "0", 1 }, + { "01", 2 }, + { "02", 2 }, + { "03", 2 }, + { "012", 3 }, + { "013", 3 }, + { "023", 3 }, + { "0123", 4 } +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pci.h (revision 51223) @@ -0,0 +1,449 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v 1.45 2004/02/02 03:55:31 dawes Exp $ */ +/* + * Copyright 1998 by Concurrent Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Concurrent Computer + * Corporation not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Concurrent Computer Corporation makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Copyright 1998 by Metro Link Incorporated + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Metro Link + * Incorporated not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Metro Link Incorporated makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * This file is derived in part from the original xf86_PCI.h that included + * following copyright message: + * + * Copyright 1995 by Robin Cutshaw + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file has the private Pci definitions. The public ones are imported + * from xf86Pci.h. Drivers should not use this file. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _PCI_H +#define _PCI_H 1 + +#include +#include +#include "xf86Pci.h" +#include "xf86PciInfo.h" + +/* + * Global Definitions + */ +#define MAX_PCI_DEVICES 128 /* Max number of devices accomodated */ + /* by xf86scanpci */ +#if defined(sun) && defined(SVR4) && defined(sparc) +# define MAX_PCI_BUSES 4096 /* Max number of PCI buses */ +#elif defined(__alpha__) && defined (linux) +# define MAX_PCI_DOMAINS 512 +# define PCI_DOM_MASK 0x01fful +# define MAX_PCI_BUSES (MAX_PCI_DOMAINS*256) /* 256 per domain */ +#else +# define MAX_PCI_BUSES 256 /* Max number of PCI buses */ +#endif + +#define DEVID(vendor, device) \ + ((CARD32)((PCI_##device << 16) | PCI_##vendor)) + +#ifndef PCI_DOM_MASK +# define PCI_DOM_MASK 0x0ffu +#endif +#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) + +/* + * "b" contains an optional domain number. + */ +#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ + (((d) & 0x00001fu) << 11) | \ + (((f) & 0x000007u) << 8)) + +#define PCI_MAKE_BUS(d,b) ((((d) & (PCI_DOM_MASK)) << 8) | ((b) & 0xffu)) + +#define PCI_DOM_FROM_TAG(tag) (((tag) >> 24) & (PCI_DOM_MASK)) +#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) +#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) +#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) + +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) +#define PCI_BDEV_FROM_TAG(tag) ((tag) & 0x00fff800u) + +#define PCI_DOM_FROM_BUS(bus) (((bus) >> 8) & (PCI_DOM_MASK)) +#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu) +#define PCI_TAG_NO_DOMAIN(tag) ((tag) & 0x00ffff00u) + +/* + * Macros for bus numbers found in P2P headers. + */ +#define PCI_PRIMARY_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_PRIMARY_BUS_MASK ) >> 0) | (PCI_DOM_FROM_TAG(tag) << 8)) +#define PCI_SECONDARY_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_SECONDARY_BUS_MASK ) >> 8) | (PCI_DOM_FROM_TAG(tag) << 8)) +#define PCI_SUBORDINATE_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_SUBORDINATE_BUS_MASK) >> 16) | (PCI_DOM_FROM_TAG(tag) << 8)) + +#define PCI_PRIMARY_BUS_INSERT(x, y) \ + (((x) & ~PCI_PRIMARY_BUS_MASK ) | (((y) & 0xffu) << 0)) +#define PCI_SECONDARY_BUS_INSERT(x, y) \ + (((x) & ~PCI_SECONDARY_BUS_MASK ) | (((y) & 0xffu) << 8)) +#define PCI_SUBORDINATE_BUS_INSERT(x, y) \ + (((x) & ~PCI_SUBORDINATE_BUS_MASK) | (((y) & 0xffu) << 16)) + +/* Ditto for CardBus bridges */ +#define PCI_CB_PRIMARY_BUS_EXTRACT(x, tag) \ + PCI_PRIMARY_BUS_EXTRACT(x, tag) +#define PCI_CB_CARDBUS_BUS_EXTRACT(x, tag) \ + PCI_SECONDARY_BUS_EXTRACT(x, tag) +#define PCI_CB_SUBORDINATE_BUS_EXTRACT(x, tag) \ + PCI_SUBORDINATE_BUS_EXTRACT(x, tag) + +#define PCI_CB_PRIMARY_BUS_INSERT(x, tag) \ + PCI_PRIMARY_BUS_INSERT(x, tag) +#define PCI_CB_CARDBUS_BUS_INSERT(x, tag) \ + PCI_SECONDARY_BUS_INSERT(x, tag) +#define PCI_CB_SUBORDINATE_BUS_INSERT(x, tag) \ + PCI_SUBORDINATE_BUS_INSERT(x, tag) + +#if X_BYTE_ORDER == X_BIG_ENDIAN +#define PCI_CPU(val) (((val >> 24) & 0x000000ff) | \ + ((val >> 8) & 0x0000ff00) | \ + ((val << 8) & 0x00ff0000) | \ + ((val << 24) & 0xff000000)) +#define PCI_CPU16(val) (((val >> 8) & 0x000000ff) | \ + ((val << 8) & 0x0000ff00)) +#else +#define PCI_CPU(val) (val) +#define PCI_CPU16(val) (val) +#endif + +/* + * Debug Macros/Definitions + */ +/* #define DEBUGPCI 2 */ /* Disable/enable trace in PCI code */ + +#if defined(DEBUGPCI) + +# define PCITRACE(lvl,printfargs) \ + if (lvl > xf86Verbose) { \ + ErrorF printfargs; \ + } + +#else /* !defined(DEBUGPCI) */ + +# define PCITRACE(lvl,printfargs) + +#endif /* !defined(DEBUGPCI) */ + +/* + * PCI Config mechanism definitions + */ +#define PCI_EN 0x80000000 + +#define PCI_CFGMECH1_ADDRESS_REG 0xCF8 +#define PCI_CFGMECH1_DATA_REG 0xCFC + +#define PCI_CFGMECH1_MAXDEV 32 + +/* + * Select architecture specific PCI init function + */ +#if defined(__alpha__) +# if defined(linux) +# define ARCH_PCI_INIT axpPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(__FreeBSD__) || defined(__OpenBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# elif defined(__NetBSD__) +# define ARCH_PCI_INIT netbsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__arm__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__hppa__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__ia64__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(FreeBSD) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +# define XF86SCANPCI_WRAPPER ia64ScanPCIWrapper +#elif defined(__i386__) || defined(i386) +# define ARCH_PCI_INIT ix86PciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# if defined(linux) +# define ARCH_PCI_OS_INIT linuxPciInit +# endif +#elif defined(__mc68000__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__mips__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__powerpc__) || defined(__powerpc64__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN /* Needs kernel work to remove */ +# elif defined(__FreeBSD__) || defined(__OpenBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# elif defined(__NetBSD__) +# define ARCH_PCI_INIT netbsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# elif defined(PowerMAX_OS) /* This port is broken */ +# define ARCH_PCI_INIT ppcPciInit +# else +# define ARCH_PCI_INIT ppcPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__s390__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__sh__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__sparc__) || defined(sparc) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(sun) +# define ARCH_PCI_INIT sparcPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif (defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc64__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +# if !defined(__FreeBSD__) +# define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge +# endif +#elif defined(__amd64__) || defined(__amd64) +# if defined(__FreeBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# else +# define ARCH_PCI_INIT ix86PciInit +# endif +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# if defined(linux) +# define ARCH_PCI_OS_INIT linuxPciInit +# endif +#endif + +#ifndef ARCH_PCI_INIT +#error No PCI support available for this architecture/OS combination +#endif + +extern void ARCH_PCI_INIT(void); +#if defined(ARCH_PCI_OS_INIT) +extern void ARCH_PCI_OS_INIT(void); +#endif + +#if defined(ARCH_PCI_PCI_BRIDGE) +extern void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI); +#endif + +#if defined(XF86SCANPCI_WRAPPER) +typedef enum { + SCANPCI_INIT, + SCANPCI_TERM +} scanpciWrapperOpt; +extern void XF86SCANPCI_WRAPPER(scanpciWrapperOpt flags); +#endif + +/* + * Table of functions used to access a specific PCI bus domain + * (e.g. a primary PCI bus and all of its secondaries) + */ +typedef struct pci_bus_funcs { + CARD32 (*pciReadLong)(PCITAG, int); + void (*pciWriteLong)(PCITAG, int, CARD32); + void (*pciSetBitsLong)(PCITAG, int, CARD32, CARD32); + ADDRESS (*pciAddrHostToBus)(PCITAG, PciAddrType, ADDRESS); + ADDRESS (*pciAddrBusToHost)(PCITAG, PciAddrType, ADDRESS); + /* + * The next three are optional. If NULL, the corresponding function is + * to be performed generically. + */ + CARD16 (*pciControlBridge)(int, CARD16, CARD16); + void (*pciGetBridgeBuses)(int, int *, int *, int *); + /* Use pointer's to avoid #include recursion */ + void (*pciGetBridgeResources)(int, pointer *, pointer *, pointer *); + + /* These are optional and will be implemented using read long + * if not present. */ + CARD8 (*pciReadByte)(PCITAG, int); + void (*pciWriteByte)(PCITAG, int, CARD8); + CARD16 (*pciReadWord)(PCITAG, int); + void (*pciWriteWord)(PCITAG, int, CARD16); + +} pciBusFuncs_t, *pciBusFuncs_p; + +/* + * pciBusInfo_t - One structure per defined PCI bus + */ +typedef struct pci_bus_info { + unsigned char configMech; /* PCI config type to use */ + unsigned char numDevices; /* Range of valid devnums */ + unsigned char secondary; /* Boolean: bus is a secondary */ + int primary_bus; /* Parent bus */ +#ifdef PowerMAX_OS + unsigned long ppc_io_base; /* PowerPC I/O spc membase */ + unsigned long ppc_io_size; /* PowerPC I/O spc size */ +#endif + pciBusFuncs_p funcs; /* PCI access functions */ + void *pciBusPriv; /* Implementation private data */ + pciConfigPtr bridge; /* bridge that opens this bus */ +} pciBusInfo_t; + +#define HOST_NO_BUS ((pciBusInfo_t *)(-1)) + +/* configMech values */ +#define PCI_CFG_MECH_UNKNOWN 0 /* Not yet known */ +#define PCI_CFG_MECH_1 1 /* Most machines */ +#define PCI_CFG_MECH_2 2 /* Older PC's */ +#define PCI_CFG_MECH_OTHER 3 /* Something else */ + +/* Generic PCI service functions and helpers */ +PCITAG pciGenFindFirst(void); +PCITAG pciGenFindNext(void); +CARD32 pciCfgMech1Read(PCITAG tag, int offset); +void pciCfgMech1Write(PCITAG tag, int offset, CARD32 val); +void pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, + CARD32 val); +CARD32 pciByteSwap(CARD32); +Bool pciMfDev(int, int); +ADDRESS pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS); + +extern PCITAG (*pciFindFirstFP)(void); +extern PCITAG (*pciFindNextFP)(void); + +extern CARD32 pciDevid; +extern CARD32 pciDevidMask; + +extern int pciMaxBusNum; + +extern int pciBusNum; +extern int pciDevNum; +extern int pciFuncNum; +extern PCITAG pciDeviceTag; + +extern pciBusInfo_t *pciBusInfo[]; + +#endif /* _PCI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pcl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pcl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pcl.h (revision 51223) @@ -0,0 +1,625 @@ +/* $Xorg: Pcl.h,v 1.3 2000/08/17 19:48:07 cpqbld Exp $ */ +/******************************************************************* +** +** ********************************************************* +** * +** * File: Pcl.h +** * +** * Contents: defines and includes for the Pcl driver +** * for a printing X server. +** * +** * Created: 1/30/95 +** * +** ********************************************************* +** +********************************************************************/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/Pcl.h,v 1.12 2001/12/21 21:02:05 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCL_H_ +#define _PCL_H_ + +#include +#include "scrnintstr.h" + +#include "PclDef.h" +#include "Pclmap.h" +#include "PclSFonts.h" + +#include +#include + +#include "regionstr.h" +#include +#include "dixfontstr.h" +#include "gcstruct.h" + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +typedef char *XPointer; +#endif +#define Status int +#define True 1 +#define False 0 +#include "misc.h" +#include +#include +#include "attributes.h" + +/****** + * externally visible variables from PclInit.c + ******/ +extern int PclScreenPrivateIndex, PclWindowPrivateIndex; +extern int PclContextPrivateIndex; +extern int PclPixmapPrivateIndex; +extern int PclGCPrivateIndex; + +/****** + * externally visible variables from PclAttVal.c + ******/ +extern XpValidatePoolsRec PclValidatePoolsRec; + +/* + * This structure defines a mapping from an X colormap ID to a list of + * print contexts which use the colormap. + */ +typedef struct _pclcontextlist { + XpContextPtr context; + struct _pclcontextlist *next; +} PclContextList, *PclContextListPtr; + +typedef struct _pclcmaptocontexts { + long colormapId; + PclContextListPtr contexts; + struct _pclcmaptocontexts *next; +} PclCmapToContexts; + +typedef struct { + PclCmapToContexts *colormaps; + CloseScreenProcPtr CloseScreen; +} PclScreenPrivRec, *PclScreenPrivPtr; + +/* + * This structure defines a mapping from an X colormap ID to a PCL + * palette ID. + */ +typedef struct _palettemap { + long colormapId; + int paletteId; + int downloaded; + struct _palettemap *next; +} PclPaletteMap, *PclPaletteMapPtr; + +typedef struct { + char *jobFileName; + FILE *pJobFile; + char *pageFileName; + FILE *pPageFile; + GC lastGC; + unsigned char *dash; + int validGC; + ClientPtr getDocClient; + int getDocBufSize; + PclSoftFontInfoPtr pSoftFontInfo; + PclPaletteMapPtr palettes; + int currentPalette; + int nextPaletteId; + PclPaletteMap staticGrayPalette; + PclPaletteMap trueColorPalette; + PclPaletteMap specialTrueColorPalette; + unsigned char *ctbl; + int ctbldim; + int isRaw; +#ifdef XP_PCL_LJ3 + unsigned int fcount; + unsigned int fcount_max; + char *figures; +#endif /* XP_PCL_LJ3 */ +} PclContextPrivRec, *PclContextPrivPtr; + +typedef struct { + int validContext; + XpContextPtr context; +} PclWindowPrivRec, *PclWindowPrivPtr; + +typedef struct { + unsigned long stippleFg, stippleBg; +} PclGCPrivRec, *PclGCPrivPtr; + +typedef struct { + XpContextPtr context; + char *tempFileName; + FILE *tempFile; + GC lastGC; + int validGC; +} PclPixmapPrivRec, *PclPixmapPrivPtr; + +/****** + * Defined functions + ******/ +#define SEND_PCL(f,c) fwrite( c, sizeof( char ), strlen( c ), f ) +#define SEND_PCL_COUNT(f,c,n) fwrite( c, sizeof( char ), n, f ) + +#ifndef XP_PCL_LJ3 +#define SAVE_PCL(f,p,c) SEND_PCL(f,c) +#define SAVE_PCL_COUNT(f,p,c,n) SEND_PCL_COUNT(f,c,n) +#define MACRO_START(f,p) SEND_PCL(f, "\033&f1Y\033&f0X") +#define MACRO_END(f) SEND_PCL(f, "\033&f1X") +#else +#define SAVE_PCL(f,p,c) PclSpoolFigs(p, c, strlen(c)) +#define SAVE_PCL_COUNT(f,p,c,n) PclSpoolFigs(p, c, n) +#define MACRO_START(f,p) p->fcount = 0 +#define MACRO_END(f) /* do nothing */ +#endif /* XP_PCL_LJ3 */ + +#define MIN(a,b) (((a)<(b))?(a):(b)) +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/****** + * Functions in PclArc.c + ******/ +extern void PclPolyArc( + DrawablePtr pDrawable, + GCPtr pGC, + int nArcs, + xArc *pArcs); +extern void PclPolyFillArc( + DrawablePtr pDrawable, + GCPtr pGC, + int nArcs, + xArc *pArcs); + +/****** + * Functions in PclArea.c + ******/ +extern void PclPutImage( + DrawablePtr pDrawable, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage); +extern RegionPtr PclCopyArea( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty); +RegionPtr PclCopyPlane( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + unsigned long plane); + + +/****** + * Functions in PclAttr.c + ******/ +extern char *PclGetAttributes( + XpContextPtr pCon, + XPAttributes pool ); +extern char *PclGetOneAttribute( + XpContextPtr pCon, + XPAttributes pool, + char *attr ); +extern int PclAugmentAttributes( + XpContextPtr pCon, + XPAttributes pool, + char *attrs ); +extern int PclSetAttributes( + XpContextPtr pCon, + XPAttributes pool, + char *attrs ); + +/****** + * Functions in PclColor.c + ******/ +extern Bool PclCreateDefColormap(ScreenPtr pScreen); +extern Bool PclCreateColormap(ColormapPtr pColor); +extern void PclDestroyColormap(ColormapPtr pColor); +extern void PclInstallColormap(ColormapPtr pColor); +extern void PclUninstallColormap(ColormapPtr pColor); +extern int PclListInstalledColormaps(ScreenPtr pScreen, + XID *pCmapList); +extern void PclStoreColors(ColormapPtr pColor, + int ndef, + xColorItem *pdefs); +extern void PclResolveColor(unsigned short *pRed, + unsigned short *pGreen, + unsigned short *pBlue, + VisualPtr pVisual); +extern int PclUpdateColormap(DrawablePtr pDrawable, + XpContextPtr pCon, + GCPtr gc, + FILE *outFile); +extern void PclLookUp(ColormapPtr cmap, + PclContextPrivPtr cPriv, + unsigned short *r, + unsigned short *g, + unsigned short *b); +extern PclPaletteMapPtr PclFindPaletteMap(PclContextPrivPtr cPriv, + ColormapPtr cmap, + GCPtr gc); +extern unsigned char *PclReadMap(char *, int *); + + +/****** + * Functions in PclCursor.c + ******/ +extern void PclConstrainCursor( + ScreenPtr pScreen, + BoxPtr pBox); +extern void PclCursorLimits( + ScreenPtr pScreen, + CursorPtr pCursor, + BoxPtr pHotBox, + BoxPtr pTopLeftbox); +extern Bool PclDisplayCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern Bool PclRealizeCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern Bool PclUnrealizeCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern void PclRecolorCursor( + ScreenPtr pScreen, + CursorPtr pCursor, + Bool displayed); +extern Bool PclSetCursorPosition( + ScreenPtr pScreen, + int x, + int y, + Bool generateEvent); + +/****** + * Functions in PclSFonts.c + ******/ +extern void +PclDownloadSoftFont8( + FILE *fp, + PclSoftFontInfoPtr pSoftFontInfo, + PclFontHead8Ptr pfh, + PclCharDataPtr pcd, + unsigned char *code); +extern void PclDownloadSoftFont16( + FILE *fp, + PclSoftFontInfoPtr pSoftFontInfo, + PclFontHead16Ptr pfh, + PclCharDataPtr pcd, + unsigned char row, + unsigned char col); +extern PclSoftFontInfoPtr PclCreateSoftFontInfo(void); +extern void PclDestroySoftFontInfo( + PclSoftFontInfoPtr pSoftFontInfo ); + +/****** + * Functions in PclGC.c + ******/ +extern Bool PclCreateGC(GCPtr pGC); +extern void PclDestroyGC(GCPtr pGC); +extern int PclUpdateDrawableGC( + GCPtr pGC, + DrawablePtr pDrawable, + FILE **outFile); +extern void PclValidateGC( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable); +extern void PclSetDrawablePrivateStuff( + DrawablePtr pDrawable, + GC gc ); +extern int PclGetDrawablePrivateStuff( + DrawablePtr pDrawable, + GC *gc, + unsigned long *valid, + FILE **file ); +extern void PclSetDrawablePrivateGC( + DrawablePtr pDrawable, + GC gc); +extern void PclComputeCompositeClip( + GCPtr pGC, + DrawablePtr pDrawable); + +/****** + * Functions in PclInit.c + ******/ +extern Bool PclCloseScreen( + int index, + ScreenPtr pScreen); +extern Bool InitializeColorPclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern Bool InitializeMonoPclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern Bool InitializeLj3PclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern XpContextPtr PclGetContextFromWindow( WindowPtr win ); + +/****** + * Functions in PclLine.c + ******/ +extern void PclPolyLine( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int nPoints, + xPoint *pPoints); +extern void PclPolySegment( + DrawablePtr pDrawable, + GCPtr pGC, + int nSegments, + xSegment *pSegments); + +/****** + * Functions in PclMisc.c + ******/ +extern void PclQueryBestSize( + int class, + short *pwidth, + short *pheight, + ScreenPtr pScreen); +extern char *GetPropString(WindowPtr pWin, char *propName); +extern int SystemCmd(char *cmdStr); +extern int PclGetMediumDimensions( + XpContextPtr pCon, + CARD16 *pWidth, + CARD16 *pHeight); +extern int PclGetReproducibleArea( + XpContextPtr pCon, + xRectangle *pRect); +extern void PclSendData( + FILE *outFile, + PclContextPrivPtr pConPriv, + BoxPtr pbox, + int nbox, + double ratio); + +/****** + * Functions in PclPixel.c + ******/ +extern void PclPolyPoint( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int nPoints, + xPoint *pPoints); +extern void PclPushPixels( + GCPtr pGC, + PixmapPtr pBitmap, + DrawablePtr pDrawable, + int width, + int height, + int x, + int y); + +/****** + * Functions in PclPixmap.c + ******/ +extern PixmapPtr PclCreatePixmap( + ScreenPtr pScreen, + int width, + int height, + int depth); +extern Bool PclDestroyPixmap(PixmapPtr pPixmap); + +/****** + * Functions in PclPolygon.c + ******/ +extern void PclPolyRectangle( + DrawablePtr pDrawable, + GCPtr pGC, + int nRects, + xRectangle *pRects); +extern void PclFillPolygon( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int nPoints, + DDXPointPtr pPoints); +extern void PclPolyFillRect( + DrawablePtr pDrawable, + GCPtr pGC, + int nRects, + xRectangle *pRects); + +/****** + * Functions in PclSpans.c + ******/ +extern void PclFillSpans( + DrawablePtr pDrawable, + GCPtr pGC, + int nSpans, + DDXPointPtr pPoints, + int *pWidths, + int fSorted); +extern void PclSetSpans( + DrawablePtr pDrawable, + GCPtr pGC, + char *pSrc, + DDXPointPtr pPoints, + int *pWidths, + int nSpans, + int fSorted); + +/****** + * Functions in PclText.c + ******/ +extern int PclPolyText8( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + char *string); +extern int PclPolyText16( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *string); +extern void PclImageText8( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + char *string); +extern void PclImageText16( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *string); +extern void PclImageGlyphBlt( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nGlyphs, + CharInfoPtr *pCharInfo, + pointer pGlyphBase); +extern void PclPolyGlyphBlt( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nGlyphs, + CharInfoPtr *pCharInfo, + pointer pGlyphBase); + +/****** + * Functions in PclWindow.c + ******/ +extern Bool PclCreateWindow(register WindowPtr pWin); +extern Bool PclDestroyWindow(WindowPtr pWin); +extern Bool PclMapWindow(WindowPtr pWindow); +extern Bool PclPositionWindow( + register WindowPtr pWin, + int x, + int y); +extern Bool PclUnmapWindow(WindowPtr pWindow); +extern void PclCopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); +extern Bool PclChangeWindowAttributes( + register WindowPtr pWin, + register unsigned long mask); +extern void PclPaintWindow( + WindowPtr pWin, + RegionPtr pRegion, + int what); + +/****** + * Functions in PclFonts.c + ******/ +extern Bool PclRealizeFont( + ScreenPtr pscr, + FontPtr pFont); +extern Bool PclUnrealizeFont( + ScreenPtr pscr, + FontPtr pFont); + +/****** + * Functions in PclPrint.c + ******/ +extern int PclStartJob( + XpContextPtr pCon, + Bool sendClientData, + ClientPtr client); +extern int PclEndJob( + XpContextPtr pCon, + Bool cancel); +extern int PclStartPage( + XpContextPtr pCon, + WindowPtr pWin); +extern int PclEndPage( + XpContextPtr pCon, + WindowPtr pWin); +extern int PclStartDoc(XpContextPtr pCon, + XPDocumentType type); +extern int PclEndDoc( + XpContextPtr pCon, + Bool cancel); +extern int PclDocumentData( + XpContextPtr pCon, + DrawablePtr pDraw, + char *pData, + int len_data, + char *pFmt, + int len_fmt, + char *pOpt, + int len_opt, + ClientPtr client); +extern int PclGetDocumentData( + XpContextPtr pCon, + ClientPtr client, + int maxBufferSize); + + +#endif /* _PCL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclDef.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclDef.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclDef.h (revision 51223) @@ -0,0 +1,68 @@ +/* $Xorg: PclDef.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +/******************************************************************* +** +** ********************************************************* +** * +** * File: PclDef.h +** * +** * Contents: extran defines and includes for the Pcl driver +** * for a printing X server. +** * +** * Created: 7/31/95 +** * +** ********************************************************* +** +********************************************************************/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLDEF_H_ +#define _PCLDEF_H_ + +#define DT_PRINT_JOB_HEADER "DT_PRINT_JOB_HEADER" +#define DT_PRINT_JOB_TRAILER "DT_PRINT_JOB_TRAILER" +#define DT_PRINT_JOB_COMMAND "DT_PRINT_JOB_COMMAND" +#define DT_PRINT_JOB_EXEC_COMMAND "DT_PRINT_JOB_EXEC_COMMAND" +#define DT_PRINT_JOB_EXEC_OPTIONS "DT_PRINT_JOB_EXEC_OPTION" +#define DT_PRINT_PAGE_HEADER "DT_PRINT_PAGE_HEADER" +#define DT_PRINT_PAGE_TRAILER "DT_PRINT_PAGE_TRAILER" +#define DT_PRINT_PAGE_COMMAND "DT_PRINT_PAGE_COMMAND" + +#define DT_IN_FILE_STRING "%(InFile)%" +#define DT_OUT_FILE_STRING "%(OutFile)%" +#define DT_ALLOWED_COMMANDS_FILE "printCommands" + +#endif /* _PCLDEF_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclSFonts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclSFonts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PclSFonts.h (revision 51223) @@ -0,0 +1,116 @@ +/* $Xorg: PclSFonts.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLFONTS_H +#define _PCLFONTS_H + +/* -*-H-*- +****************************************************************************** +****************************************************************************** +* +* File: PclFonts.h +* Description: Send Soft Font Download data to the specified file pointer. +* +* +****************************************************************************** +****************************************************************************** +*/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + + +typedef struct { + unsigned char fid; /* sfont font ID */ + unsigned char cindex; /* character indext */ +} PclFontMapRec, PclFontMapPtr; + +typedef struct { + int h_offset; + int v_offset; + unsigned int width; + unsigned int height; + int font_pitch; + unsigned char *raster_top; +} PclCharDataRec, *PclCharDataPtr; + +typedef struct { + unsigned char spacing; + unsigned int pitch; + unsigned int cellheight; + unsigned int cellwidth; + int ascent; + int descent; +} PclFontDescRec, *PclFontDescPtr; + +typedef struct _PclFontHead8Rec { + char *fontname; + PclFontDescRec fd; + unsigned short fid; + unsigned char *index; + struct _PclFontHead8Rec *next; +} PclFontHead8Rec, *PclFontHead8Ptr; + +typedef struct _PclFontHead16Rec { + char *fontname; + PclFontDescRec fd; + unsigned short cur_fid; + unsigned char cur_cindex; + PclFontMapRec **index; + unsigned short firstCol; + unsigned short lastCol; + unsigned short firstRow; + unsigned short lastRow; + struct _PclFontHead16Rec *next; +} PclFontHead16Rec, *PclFontHead16Ptr; + +typedef struct _PclInternalFontRec { + char *fontname; + float pitch; + float height; + char *pcl_font_name; + char *spacing; + struct _PclInternalFontRec *next; +} PclInternalFontRec, *PclInternalFontPtr; + +typedef struct { + PclFontHead8Ptr phead8; + PclFontHead16Ptr phead16; + PclInternalFontPtr pinfont; + unsigned char cur_max_fid; +} PclSoftFontInfoRec, *PclSoftFontInfoPtr; + +#define MONOSPACE 0 +#define PROPSPACE 1 + +#endif /* _PCLFONTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pclmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pclmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Pclmap.h (revision 51223) @@ -0,0 +1,213 @@ +/* $Xorg: Pclmap.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/Pclmap.h,v 1.5 2001/07/25 15:05:00 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLMAP_H_ +#define _PCLMAP_H_ + +#ifdef XP_PCL_COLOR +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclCr##subname +#define CATNAME(prefix,subname) prefix##Color##subname +#else +#define PCLNAME(subname) PclCr/**/subname +#define CATNAME(prefix,subname) prefix/**/Color/**/subname +#endif +#endif /* XP_PCL_COLOR */ + +#ifdef XP_PCL_MONO +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclMn##subname +#define CATNAME(prefix,subname) prefix##Mono##subname +#else +#define PCLNAME(subname) PclMn/**/subname +#define CATNAME(prefix,subname) prefix/**/Mono/**/subname +#endif +#endif /* XP_PCL_MONO */ + +#ifdef XP_PCL_LJ3 +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclLj3##subname +#define CATNAME(prefix,subname) prefix##Lj3##subname +#else +#define PCLNAME(subname) PclLj3/**/subname +#define CATNAME(prefix,subname) prefix/**/Lj3/**/subname +#endif +#endif /* XP_PCL_LJ3 */ + +#ifdef PCLNAME + +/* PclInit.c */ +#define InitializePclDriver CATNAME(Initialize, PclDriver) +#define PclCloseScreen PCLNAME(CloseScreen) +#define PclGetContextFromWindow PCLNAME(GetContextFromWindow) +#define PclScreenPrivateIndex PCLNAME(ScreenPrivateIndex) +#define PclWindowPrivateIndex PCLNAME(WindowPrivateIndex) +#define PclContextPrivateIndex PCLNAME(ContextPrivateIndex) +#define PclPixmapPrivateIndex PCLNAME(PixmapPrivateIndex) +#define PclGCPrivateIndex PCLNAME(GCPrivateIndex) + +/* PclPrint.c */ +#define PclStartJob PCLNAME(StartJob) +#define PclEndJob PCLNAME(EndJob) +#define PclStartPage PCLNAME(StartPage) +#define PclEndPage PCLNAME(EndPage) +#define PclStartDoc PCLNAME(StartDoc) +#define PclEndDoc PCLNAME(EndDoc) +#define PclDocumentData PCLNAME(DocumentData) +#define PclGetDocumentData PCLNAME(GetDocumentData) + +/* PclWindow.c */ +#define PclCreateWindow PCLNAME(CreateWindow) +#define PclMapWindow PCLNAME(MapWindow) +#define PclPositionWindow PCLNAME(PositionWindow) +#define PclUnmapWindow PCLNAME(UnmapWindow) +#define PclCopyWindow PCLNAME(CopyWindow) +#define PclChangeWindowAttributes PCLNAME(ChangeWindowAttributes) +#define PclPaintWindow PCLNAME(PaintWindow) +#define PclDestroyWindow PCLNAME(DestroyWindow) + +/* PclGC.c */ +#define PclCreateGC PCLNAME(CreateGC) +#define PclDestroyGC PCLNAME(DestroyGC) +#define PclGetDrawablePrivateStuff PCLNAME(GetDrawablePrivateStuff) +#define PclSetDrawablePrivateGC PCLNAME(SetDrawablePrivateGC) +#define PclSendPattern PCLNAME(SendPattern) +#define PclUpdateDrawableGC PCLNAME(UpdateDrawableGC) +#define PclComputeCompositeClip PCLNAME(ComputeCompositeClip) +#define PclValidateGC PCLNAME(ValidateGC) + +/* PclAttr.c */ +#define PclGetAttributes PCLNAME(GetAttributes) +#define PclGetOneAttribute PCLNAME(GetOneAttribute) +#define PclAugmentAttributes PCLNAME(AugmentAttributes) +#define PclSetAttributes PCLNAME(SetAttributes) + +/* PclColor.c */ +#define PclLookUp PCLNAME(LookUp) +#define PclCreateDefColormap PCLNAME(CreateDefColormap) +#define PclCreateColormap PCLNAME(CreateColormap) +#define PclDestroyColormap PCLNAME(DestroyColormap) +#define PclInstallColormap PCLNAME(InstallColormap) +#define PclUninstallColormap PCLNAME(UninstallColormap) +#define PclListInstalledColormaps PCLNAME(ListInstalledColormaps) +#define PclStoreColors PCLNAME(StoreColors) +#define PclResolveColor PCLNAME(ResolveColor) +#define PclFindPaletteMap PCLNAME(FindPaletteMap) +#define PclUpdateColormap PCLNAME(UpdateColormap) +#define PclReadMap PCLNAME(ReadMap) + +/* PclPixmap.c */ +#define PclCreatePixmap PCLNAME(CreatePixmap) +#define PclDestroyPixmap PCLNAME(DestroyPixmap) + +/* PclArc.c */ +#define PclDoArc PCLNAME(DoArc) +#define PclPolyArc PCLNAME(PolyArc) +#define PclPolyFillArc PCLNAME(PolyFillArc) + +/* PclArea.c */ +#define PclPutImage PCLNAME(PutImage) +#define PclCopyArea PCLNAME(CopyArea) +#define PclCopyPlane PCLNAME(CopyPlane) + +/* PclLine */ +#define PclPolyLine PCLNAME(PolyLine) +#define PclPolySegment PCLNAME(PolySegment) + +/* PclPixel.c */ +#define PclPolyPoint PCLNAME(PolyPoint) +#define PclPushPixels PCLNAME(PushPixels) + +/* PclPolygon.c */ +#define PclPolyRectangle PCLNAME(PolyRectangle) +#define PclFillPolygon PCLNAME(FillPolygon) +#define PclPolyFillRect PCLNAME(PolyFillRect) + +/* PclSpans.c */ +#define PclFillSpans PCLNAME(FillSpans) +#define PclSetSpans PCLNAME(SetSpans) + +/* PclText.c */ +#define PclPolyText8 PCLNAME(PolyText8) +#define PclPolyText16 PCLNAME(PolyText16) +#define PclImageText8 PCLNAME(ImageText8) +#define PclImageText16 PCLNAME(ImageText16) +#define PclImageGlyphBlt PCLNAME(ImageGlyphBlt) +#define PclPolyGlyphBlt PCLNAME(PolyGlyphBlt) +#define PclPolyGlyphBlt PCLNAME(PolyGlyphBlt) + +/* PclFonts.c */ +#define PclRealizeFont PCLNAME(RealizeFont) +#define PclUnrealizeFont PCLNAME(UnrealizeFont) + +/* PclSFonts.c */ +#define PclDownloadSoftFont8 PCLNAME(DownloadSoftFont8) +#define PclDownloadSoftFont16 PCLNAME(DownloadSoftFont16) +#define PclCreateSoftFontInfo PCLNAME(CreateSoftFontInfo) +#define PclDestroySoftFontInfo PCLNAME(DestroySoftFontInfo) + +/* PclMisc.c */ +#define PclQueryBestSize PCLNAME(QueryBestSize) +#define GetPropString PCLNAME(GetPropString) +#define SystemCmd PCLNAME(SystemCmd) +#define PclGetMediumDimensions PCLNAME(GetMediumDimensions) +#define PclGetReproducibleArea PCLNAME(GetReproducibleArea) +#define PclSpoolFigs PCLNAME(SpoolFigs) +#define PclSendData PCLNAME(SendData) + +/* PclCursor.c */ +#define PclConstrainCursor PCLNAME(ConstrainCursor) +#define PclCursorLimits PCLNAME(CursorLimits) +#define PclDisplayCursor PCLNAME(DisplayCursor) +#define PclRealizeCursor PCLNAME(RealizeCursor) +#define PclUnrealizeCursor PCLNAME(UnrealizeCursor) +#define PclRecolorCursor PCLNAME(RecolorCursor) +#define PclSetCursorPosition PCLNAME(SetCursorPosition) + +#endif + +#endif /* _PCLMAP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Preferences.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Preferences.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Preferences.h (revision 51223) @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/Preferences.h,v 1.2 2003/01/15 02:34:05 torrey Exp $ */ + +#import + +@interface Preferences : NSObject +{ + IBOutlet NSPanel *window; + IBOutlet id displayField; + IBOutlet id dockSwitchButton; + IBOutlet id fakeButton; + IBOutlet id button2ModifiersMatrix; + IBOutlet id button3ModifiersMatrix; + IBOutlet id switchKeyButton; + IBOutlet id keymapFileField; + IBOutlet id modeMatrix; + IBOutlet id modeWindowButton; + IBOutlet id startupHelpButton; + IBOutlet id systemBeepButton; + IBOutlet id mouseAccelChangeButton; + IBOutlet id useXineramaButton; + IBOutlet id addToPathButton; + IBOutlet id addToPathField; + IBOutlet id useDefaultShellMatrix; + IBOutlet id useOtherShellField; + IBOutlet id depthButton; + + BOOL isGettingKeyCode; + int keyCode; + int modifiers; + NSMutableString *switchString; +} + +- (IBAction)close:(id)sender; +- (IBAction)pickFile:(id)sender; +- (IBAction)saveChanges:(id)sender; +- (IBAction)setKey:(id)sender; + +- (BOOL)sendEvent:(NSEvent *)anEvent; + +- (void)awakeFromNib; +- (void)windowWillClose:(NSNotification *)aNotification; + ++ (void)setUseKeymapFile:(BOOL)newUseKeymapFile; ++ (void)setKeymapFile:(NSString *)newFile; ++ (void)setSwitchString:(NSString *)newString; ++ (void)setKeyCode:(int)newKeyCode; ++ (void)setModifiers:(int)newModifiers; ++ (void)setDisplay:(int)newDisplay; ++ (void)setDockSwitch:(BOOL)newDockSwitch; ++ (void)setFakeButtons:(BOOL)newFakeButtons; ++ (void)setButton2Mask:(int)newFakeMask; ++ (void)setButton3Mask:(int)newFakeMask; ++ (void)setMouseAccelChange:(BOOL)newMouseAccelChange; ++ (void)setUseQDCursor:(int)newUseQDCursor; ++ (void)setRootless:(BOOL)newRootless; ++ (void)setUseAGL:(BOOL)newUseAGL; ++ (void)setModeWindow:(BOOL)newModeWindow; ++ (void)setStartupHelp:(BOOL)newStartupHelp; ++ (void)setSystemBeep:(BOOL)newSystemBeep; ++ (void)setEnableKeyEquivalents:(BOOL)newKeyEquivs; ++ (void)setXinerama:(BOOL)newXinerama; ++ (void)setAddToPath:(BOOL)newAddToPath; ++ (void)setAddToPathString:(NSString *)newAddToPathString; ++ (void)setUseDefaultShell:(BOOL)newUseDefaultShell; ++ (void)setShellString:(NSString *)newShellString; ++ (void)setDepth:(int)newDepth; ++ (void)setDisplayModeBundles:(NSArray *)newBundles; ++ (void)saveToDisk; + ++ (BOOL)useKeymapFile; ++ (NSString *)keymapFile; ++ (NSString *)switchString; ++ (unsigned int)keyCode; ++ (unsigned int)modifiers; ++ (int)display; ++ (BOOL)dockSwitch; ++ (BOOL)fakeButtons; ++ (int)button2Mask; ++ (int)button3Mask; ++ (BOOL)mouseAccelChange; ++ (int)useQDCursor; ++ (BOOL)rootless; ++ (BOOL)useAGL; ++ (BOOL)modeWindow; ++ (BOOL)startupHelp; ++ (BOOL)systemBeep; ++ (BOOL)enableKeyEquivalents; ++ (BOOL)xinerama; ++ (BOOL)addToPath; ++ (NSString *)addToPathString; ++ (BOOL)useDefaultShell; ++ (NSString *)shellString; ++ (int)depth; ++ (NSArray *)displayModeBundles; + +@end + +// Possible settings for useQDCursor +enum { + qdCursor_Never, // never use QuickDraw cursor + qdCursor_Not8Bit, // don't try to use QuickDraw with 8-bit depth + qdCursor_Always // always try to use QuickDraw cursor +}; + +// Possible settings for depth +enum { + depth_Current, + depth_8Bit, + depth_15Bit, + depth_24Bit +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Ps.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Ps.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Ps.h (revision 51223) @@ -0,0 +1,590 @@ +/* $Xorg: Ps.h,v 1.5 2001/02/09 02:04:35 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: Ps.h +** * +** * Contents: defines and includes for the Ps driver +** * for a printing X server. +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PS_H_ +#define _PS_H_ + +#include + +#ifdef abs +#undef abs /* this is because of a non-Spec1170ness in misc.h */ +#endif +#include +#include "scrnintstr.h" +#include "dix.h" + +#include "PsDef.h" +#include "psout.h" + +#include +#include + +#include "regionstr.h" +#include +#include "dixfontstr.h" +#include "gcstruct.h" + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +typedef char *XPointer; +#define Status int +#define True 1 +#define False 0 +#endif + +#include "misc.h" +#include +#include +#include "attributes.h" + + +/* + * Public index variables from PsInit.c + */ + +extern int PsScreenPrivateIndex; +extern int PsWindowPrivateIndex; +extern int PsContextPrivateIndex; +extern int PsPixmapPrivateIndex; +extern XpValidatePoolsRec PsValidatePoolsRec; + +/* + * Display list structures + */ + +#define DPY_BLOCKSIZE 4096 + +typedef struct +{ + int mode; + int nPoints; + xPoint *pPoints; +} PsPolyPointsRec; + +typedef struct +{ + int nSegments; + xSegment *pSegments; +} PsSegmentsRec; + +typedef struct +{ + int nRects; + xRectangle *pRects; +} PsRectanglesRec; + +typedef struct +{ + int nArcs; + xArc *pArcs; +} PsArcsRec; + +typedef struct +{ + int x; + int y; + int count; + char *string; +} PsText8Rec; + +typedef struct +{ + int x; + int y; + int count; + unsigned short *string; +} PsText16Rec; + +typedef struct +{ + int depth; + int x; + int y; + int w; + int h; + int leftPad; + int format; + int res; /* image resolution */ + char *pData; +} PsImageRec; + +typedef struct +{ + int x; + int y; + int w; + int h; +} PsFrameRec; + +typedef enum +{ + PolyPointCmd, + PolyLineCmd, + PolySegmentCmd, + PolyRectangleCmd, + FillPolygonCmd, + PolyFillRectCmd, + PolyArcCmd, + PolyFillArcCmd, + Text8Cmd, + Text16Cmd, + TextI8Cmd, + TextI16Cmd, + PutImageCmd, + BeginFrameCmd, + EndFrameCmd +} DisplayElmType; + +typedef struct _DisplayElmRec +{ + DisplayElmType type; + GCPtr gc; + union + { + PsPolyPointsRec polyPts; + PsSegmentsRec segments; + PsRectanglesRec rects; + PsArcsRec arcs; + PsText8Rec text8; + PsText16Rec text16; + PsImageRec image; + PsFrameRec frame; + } c; +} DisplayElmRec; + +typedef DisplayElmRec *DisplayElmPtr; + +typedef struct _DisplayListRec +{ + struct _DisplayListRec *next; + int nelms; + DisplayElmRec elms[DPY_BLOCKSIZE]; +} DisplayListRec; + +typedef DisplayListRec *DisplayListPtr; + +/* + * Private structures + */ + +typedef struct +{ + XrmDatabase resDB; + Bool (*DestroyWindow)(WindowPtr); +} PsScreenPrivRec, *PsScreenPrivPtr; + +typedef struct PsFontTypeInfoRec PsFontTypeInfoRec; + +/* Structure to hold information about one font on disk + * Notes: + * - multiple XLFD names can refer to the same |PsFontTypeInfoRec| (if + * they all use the same font on the disk) + * - the FreeType font download code uses multiple |PsFontTypeInfoRec| + * records for one font on disk if they differ in the encoding being + * used (this is an exception from the + * 'one-|PsFontTypeInfoRec|-per-font-on-disk'-design; maybe it it is better + * to rework that in a later step and add a new per-encoding structure). + */ +struct PsFontTypeInfoRec +{ + PsFontTypeInfoRec *next; /* Next record in list... */ + char *adobe_ps_name; /* PostScript font name (from the + * "_ADOBE_POSTSCRIPT_FONTNAME" atom) */ + char *download_ps_name; /* PostScript font name used for font download */ + char *filename; /* File name of font */ +#ifdef XP_USE_FREETYPE + char *ft_download_encoding; /* encoding used for download */ + PsFTDownloadFontType ft_download_font_type; /* PS font type used for download (e.g. Type1/Type3/CID/etc.) */ +#endif /* XP_USE_FREETYPE */ + int is_iso_encoding; /* Is this font encoded in ISO Latin 1 ? */ + int font_type; /* See PSFTI_FONT_TYPE_* below... */ + Bool downloadableFont; /* Font can be downloaded */ + Bool alreadyDownloaded[256]; /* Font has been downloaded (for 256 8bit "sub"-font) */ +}; + +#define PSFTI_FONT_TYPE_OTHER (0) +#define PSFTI_FONT_TYPE_PMF (1) +#define PSFTI_FONT_TYPE_PS_TYPE1_PFA (2) +#define PSFTI_FONT_TYPE_PS_TYPE1_PFB (3) +#define PSFTI_FONT_TYPE_TRUETYPE (4) +/* PSFTI_FONT_TYPE_FREETYPE is means the font is handled by the freetype engine */ +#define PSFTI_FONT_TYPE_FREETYPE (5) + +typedef struct PsFontInfoRec PsFontInfoRec; + +/* Structure which represents our context info for a single XLFD font + * Note that multiple |PsFontInfoRec| records can share the same + * |PsFontTypeInfoRec| record - the |PsFontInfoRec| records represent + * different appearances of the same font on disk(=|PsFontTypeInfoRec|)). + */ +struct PsFontInfoRec +{ + PsFontInfoRec *next; /* Next record in list... */ + /* |font| and |font_fontPrivate| are used by |PsFindFontInfoRec()| to + * identify a font */ + FontPtr font; /* The font this record is for */ + pointer font_fontPrivate; + PsFontTypeInfoRec *ftir; /* Record about the font file on disk */ + const char *dfl_name; /* XLFD for this font */ + int size; /* Font size. Use |mtx| if |size==0| */ + float mtx[4]; /* Transformation matrix (see |size|) */ +}; + +typedef struct +{ + char *jobFileName; + FILE *pJobFile; + GC lastGC; + unsigned char *dash; + int validGC; + ClientPtr getDocClient; + int getDocBufSize; + PsOutPtr pPsOut; + PsFontTypeInfoRec *fontTypeInfoRecords; + PsFontInfoRec *fontInfoRecords; +} PsContextPrivRec, *PsContextPrivPtr; + +typedef struct +{ + int validContext; + XpContextPtr context; +} PsWindowPrivRec, *PsWindowPrivPtr; + +typedef struct +{ + XpContextPtr context; + GC lastGC; + int validGC; + DisplayListPtr dispList; +} PsPixmapPrivRec, *PsPixmapPrivPtr; + +/* + * Macro functions + */ + +#define SEND_PS(f,c) fwrite( c, sizeof( char ), strlen( c ), f ) +#define MIN(a,b) (((a)<(b))?(a):(b)) +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* + * Functions in PsInit.c + */ + +extern Bool InitializePsDriver(int ndx, ScreenPtr pScreen, int argc, + char **argv); +extern XpContextPtr PsGetContextFromWindow(WindowPtr win); + +/* + * Functions in PsPrint.c + */ + +extern int PsStartJob(XpContextPtr pCon, Bool sendClientData, ClientPtr client); +extern int PsEndJob(XpContextPtr pCon, Bool cancel); +extern int PsStartPage(XpContextPtr pCon, WindowPtr pWin); +extern int PsEndPage(XpContextPtr pCon, WindowPtr pWin); +extern int PsStartDoc(XpContextPtr pCon, XPDocumentType type); +extern int PsEndDoc(XpContextPtr pCon, Bool cancel); +extern int PsDocumentData(XpContextPtr pCon, DrawablePtr pDraw, char *pData, + int len_data, char *pFmt, int len_fmt, char *pOpt, int len_opt, + ClientPtr client); +extern int PsGetDocumentData(XpContextPtr pCon, ClientPtr client, + int maxBufferSize); + +/* + * Functions in PsGC.c + */ + +extern Bool PsCreateGC(GCPtr pGC); +extern PsContextPrivPtr PsGetPsContextPriv( DrawablePtr pDrawable ); +extern int PsUpdateDrawableGC(GCPtr pGC, DrawablePtr pDrawable, + PsOutPtr *psOut, ColormapPtr *cMap); +extern void PsValidateGC(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable); +extern void PsChangeGC(GCPtr pGC, unsigned long changes); +extern void PsCopyGC(GCPtr pGCSrc, unsigned long mask, GCPtr pGCDst); +extern void PsDestroyGC(GCPtr pGC); +extern void PsChangeClip(GCPtr pGC, int type, pointer pValue, int nrects); +extern void PsDestroyClip(GCPtr pGC); +extern void PsCopyClip(GCPtr pgcDst, GCPtr pgcSrc); + +extern GCPtr PsCreateAndCopyGC(DrawablePtr pDrawable, GCPtr pSrc); + +/* + * Functions in PsMisc.c + */ + +extern void PsQueryBestSize(int type, short *pwidth, short *pheight, + ScreenPtr pScreen); +extern Bool PsCloseScreen(int index, ScreenPtr pScreen); +extern void PsLineAttrs(PsOutPtr psOut, GCPtr pGC, ColormapPtr cMap); +extern int PsGetMediumDimensions( + XpContextPtr pCon, + CARD16 *pWidth, + CARD16 *pHeight); +extern int PsGetReproducibleArea( + XpContextPtr pCon, + xRectangle *pRect); +extern int PsSetImageResolution( + XpContextPtr pCon, + int imageRes, + Bool *status); + +/* + * Functions in PsSpans.c + */ + +extern void PsFillSpans(DrawablePtr pDrawable, GCPtr pGC, int nSpans, + DDXPointPtr pPoints, int *pWidths, int fSorted); +extern void PsSetSpans(DrawablePtr pDrawable, GCPtr pGC, char *pSrc, + DDXPointPtr pPoints, int *pWidths, int nSpans, + int fSorted); + +/* + * Functions in PsArea.c + */ + +extern void PsPutScaledImage(DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + int imageRes, char *pImage); +extern void PsPutImage(DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + char *pImage); +extern void PsPutImageMask(DrawablePtr pDrawable, GCPtr pGC, int depth, int x, int y, + int w, int h, int leftPad, int format, char *pImage); +extern RegionPtr PsCopyArea(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty); +extern RegionPtr PsCopyPlane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty, unsigned long plane); + +/* + * Functions in PsPixel.c + */ + +extern void PsPolyPoint(DrawablePtr pDrawable, GCPtr pGC, int mode, + int nPoints, xPoint *pPoints); +extern void PsPushPixels(GCPtr pGC, PixmapPtr pBitmap, DrawablePtr pDrawable, + int width, int height, int x, int y); + +/* + * Functions in PsLine.c + */ + +extern void PsPolyLine(DrawablePtr pDrawable, GCPtr pGC, int mode, + int nPoints, xPoint *pPoints); +extern void PsPolySegment(DrawablePtr pDrawable, GCPtr pGC, int nSegments, + xSegment *pSegments); + +/* + * Functions in PsPolygon.c + */ + +extern void PsPolyRectangle(DrawablePtr pDrawable, GCPtr pGC, int nRects, + xRectangle *pRects); +extern void PsFillPolygon(DrawablePtr pDrawable, GCPtr pGC, int shape, + int mode, int nPoints, DDXPointPtr pPoints); +extern void PsPolyFillRect(DrawablePtr pDrawable, GCPtr pGC, int nRects, + xRectangle *pRects); + +/* + * Functions in PsPolygon.c + */ + +extern void PsPolyArc(DrawablePtr pDrawable, GCPtr pGC, int nArcs, + xArc *pArcs); +extern void PsPolyFillArc(DrawablePtr pDrawable, GCPtr pGC, int nArcs, + xArc *pArcs); + +/* + * Functions in PsText.c + */ + +extern int PsPolyText8(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, char *string); +extern int PsPolyText16(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, unsigned short *string); +extern void PsImageText8(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, char *string); +extern void PsImageText16(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, unsigned short *string); +extern void PsImageGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + unsigned int nGlyphs, CharInfoPtr *pCharInfo, + pointer pGlyphBase); +extern void PsPolyGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + unsigned int nGlyphs, CharInfoPtr *pCharInfo, + pointer pGlyphBase); + +/* + * Functions in PsWindow.c + */ + +extern Bool PsCreateWindow(WindowPtr pWin); +extern Bool PsMapWindow(WindowPtr pWin); +extern Bool PsPositionWindow(WindowPtr pWin, int x, int y); +extern Bool PsUnmapWindow(WindowPtr pWin); +extern void PsCopyWindow(WindowPtr pWin, DDXPointRec ptOldOrg, + RegionPtr prgnSrc); +extern Bool PsChangeWindowAttributes(WindowPtr pWin, unsigned long mask); +extern void PsPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); +extern Bool PsDestroyWindow(WindowPtr pWin); + +/* + * Functions in PsFonts.c + */ + +extern Bool PsRealizeFont(ScreenPtr pscr, FontPtr pFont); +extern Bool PsUnrealizeFont(ScreenPtr pscr, FontPtr pFont); +extern char *PsGetFontName(FontPtr pFont); +extern int PsGetFontSize(FontPtr pFont, float *mtx); +extern char *PsGetPSFontName(FontPtr pFont); +extern char *PsGetPSFaceOrFontName(FontPtr pFont); +extern int PsIsISOLatin1Encoding(FontPtr pFont); +extern char *PsGetEncodingName(FontPtr pFont); +extern PsFontInfoRec *PsGetFontInfoRec(DrawablePtr pDrawable, FontPtr pFont); +extern void PsFreeFontInfoRecords(PsContextPrivPtr priv); +extern PsFTDownloadFontType PsGetFTDownloadFontType(void); + +/* + * Functions in PsFTFonts.c + */ + +extern char *PsGetFTFontFileName(FontPtr pFont); +extern Bool PsIsFreeTypeFont(FontPtr pFont); + +/* + * Functions in PsAttr.c + */ + +extern char *PsGetAttributes(XpContextPtr pCon, XPAttributes pool); +extern char *PsGetOneAttribute(XpContextPtr pCon, XPAttributes pool, + char *attr); +extern int PsAugmentAttributes(XpContextPtr pCon, XPAttributes pool, + char *attrs); +extern int PsSetAttributes(XpContextPtr pCon, XPAttributes pool, char *attrs); + +/* + * Functions in PsColor.c + */ + +extern Bool PsCreateColormap(ColormapPtr pColor); +extern void PsDestroyColormap(ColormapPtr pColor); +extern void PsInstallColormap(ColormapPtr pColor); +extern void PsUninstallColormap(ColormapPtr pColor); +extern int PsListInstalledColormaps(ScreenPtr pScreen, XID *pCmapList); +extern void PsStoreColors(ColormapPtr pColor, int ndef, xColorItem *pdefs); +extern void PsResolveColor(unsigned short *pRed, unsigned short *pGreen, + unsigned short *pBlue, VisualPtr pVisual); +extern PsOutColor PsGetPixelColor(ColormapPtr cMap, int pixval); +extern void PsSetFillColor(DrawablePtr pDrawable, GCPtr pGC, PsOutPtr psOut, + ColormapPtr cMap); + +/* + * Functions in PsPixmap.c + */ + +extern PixmapPtr PsCreatePixmap(ScreenPtr pScreen, int width, int height, + int depth); +extern void PsScrubPixmap(PixmapPtr pPixmap); +extern Bool PsDestroyPixmap(PixmapPtr pPixmap); +extern DisplayListPtr PsGetFreeDisplayBlock(PsPixmapPrivPtr priv); +extern void PsReplayPixmap(PixmapPtr pix, DrawablePtr pDrawable); +extern int PsCloneDisplayElm(PixmapPtr dst, + DisplayElmPtr elm, DisplayElmPtr newElm, + int xoff, int yoff); +extern void PsCopyDisplayList(PixmapPtr src, PixmapPtr dst, int xoff, + int yoff, int x, int y, int w, int h); +extern PsElmPtr PsCreateFillElementList(PixmapPtr pix, int *nElms); +extern PsElmPtr PsCloneFillElementList(int nElms, PsElmPtr elms); +extern void PsDestroyFillElementList(int nElms, PsElmPtr elms); + +/* + * Functions in PsImageUtil.c + */ + +extern unsigned long +PsGetImagePixel(char *pImage, int depth, int w, int h, int leftPad, int format, + int px, int py); + +#endif /* _PS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PsDef.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PsDef.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/PsDef.h (revision 51223) @@ -0,0 +1,97 @@ +/* $Xorg: PsDef.h,v 1.4 2001/02/09 02:04:36 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: PsDef.h +** * +** * Contents: extran defines and includes for the Ps driver +** * for a printing X server. +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PSDEF_H_ +#define _PSDEF_H_ + +#define DT_PRINT_JOB_HEADER "DT_PRINT_JOB_HEADER" +#define DT_PRINT_JOB_TRAILER "DT_PRINT_JOB_TRAILER" +#define DT_PRINT_JOB_COMMAND "DT_PRINT_JOB_COMMAND" +#define DT_PRINT_JOB_EXEC_COMMAND "DT_PRINT_JOB_EXEC_COMMAND" +#define DT_PRINT_JOB_EXEC_OPTIONS "DT_PRINT_JOB_EXEC_OPTION" +#define DT_PRINT_PAGE_HEADER "DT_PRINT_PAGE_HEADER" +#define DT_PRINT_PAGE_TRAILER "DT_PRINT_PAGE_TRAILER" +#define DT_PRINT_PAGE_COMMAND "DT_PRINT_PAGE_COMMAND" + +#define DT_IN_FILE_STRING "%(InFile)%" +#define DT_OUT_FILE_STRING "%(OutFile)%" +#define DT_ALLOWED_COMMANDS_FILE "printCommands" + +#endif /* _PSDEF_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/README =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/README (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/README (revision 51223) @@ -0,0 +1,13 @@ +The contents of this directory were extracted from the contents of the +archive xorg-server-X11R7.0-1.0.1.tar.bz2, as downloaded from ftp.x.org, using +the following shell script: + +for i in `find xorg-server-X11R7.0-1.0.1 -name '*.h' | grep -v hw/xwin \ + | grep -v hw/xquartz | grep -v hw/kdrive | grep -v hw/xnest \ + | grep -v hw/xprint | grep -v hw/xgl` + do + cp $i $PATH_VBOX/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ + done + +In addition, the file xf86config.h was removed, as it conflicts with +xf86Config.h on non-case-sensitive file-systems. Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Raster.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Raster.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Raster.h (revision 51223) @@ -0,0 +1,118 @@ +/* $Xorg: Raster.h,v 1.3 2000/08/17 19:48:12 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/******************************************************************* +** +** ********************************************************* +** * +** * File: printer/Raster.h +** * +** * Contents: defines and includes for the raster layer +** * for a printing X server. +** * +** * Copyright: Copyright 1993 Hewlett-Packard Company +** * +** ********************************************************* +** +********************************************************************/ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _RASTER_H_ +#define _RASTER_H_ + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +#define HAVE_XPointer 1 +typedef char *XPointer; +#endif +#define Status int +#define True 1 +#define False 0 +#include "misc.h" +#include +#include +#include "attributes.h" + +#include + +#define MAX_TOKEN_LEN 512 + +#define RASTER_PRINT_PAGE_COMMAND "_XP_RASTER_PAGE_PROC_COMMAND" + +#define RASTER_IN_FILE_STRING "%(InFile)%" +#define RASTER_OUT_FILE_STRING "%(OutFile)%" + +#define RASTER_ALLOWED_COMMANDS_FILE "printCommands" + +/* + * Defines for the "options" in DtPrintDocumentData. + */ +#define PRE_RASTER "PRE-RASTER" +#define POST_RASTER "POST-RASTER" +#define NO_RASTER "NO-RASTER" + + +typedef struct { + char *pBits; + CreateWindowProcPtr CreateWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + DestroyWindowProcPtr DestroyWindow; + CloseScreenProcPtr CloseScreen; +} RasterScreenPrivRec, *RasterScreenPrivPtr; + +typedef struct { + XrmDatabase config; + char *jobFileName; + FILE *pJobFile; + char *pageFileName; + FILE *pPageFile; + char *preRasterFileName; /* Pre-raster document data */ + FILE *pPreRasterFile; + char *noRasterFileName; /* Raster replacement document data */ + FILE *pNoRasterFile; + char *postRasterFileName; /* Post-raster document data */ + FILE *pPostRasterFile; + ClientPtr getDocClient; + int getDocBufSize; +} RasterContextPrivRec, *RasterContextPrivPtr; + + +extern XpValidatePoolsRec RasterValidatePoolsRec; + +extern Bool InitializeRasterDriver(int ndx, ScreenPtr pScreen, int argc, + char **argv); + +#endif /* _RASTER_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TI.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TI.h,v 1.4 2000/05/02 21:04:46 alanh Exp $ */ + +#include + +unsigned long TIramdacCalculateMNPForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP); +RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +void TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +unsigned long TIramdac3030CalculateMNPForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP); +void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr); +void TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); + +typedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *, + VisualPtr); +TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void); + +#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00 +#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01 + +/* + * TI Ramdac registers + */ + +#define TIDAC_rev 0x01 +#define TIDAC_ind_curs_ctrl 0x06 +#define TIDAC_byte_router_ctrl 0x07 +#define TIDAC_latch_ctrl 0x0f +#define TIDAC_true_color_ctrl 0x18 +#define TIDAC_multiplex_ctrl 0x19 +#define TIDAC_clock_select 0x1a +#define TIDAC_palette_page 0x1c +#define TIDAC_general_ctrl 0x1d +#define TIDAC_misc_ctrl 0x1e +#define TIDAC_pll_addr 0x2c +#define TIDAC_pll_pixel_data 0x2d +#define TIDAC_pll_memory_data 0x2e +#define TIDAC_pll_loop_data 0x2f +#define TIDAC_key_over_low 0x30 +#define TIDAC_key_over_high 0x31 +#define TIDAC_key_red_low 0x32 +#define TIDAC_key_red_high 0x33 +#define TIDAC_key_green_low 0x34 +#define TIDAC_key_green_high 0x35 +#define TIDAC_key_blue_low 0x36 +#define TIDAC_key_blue_high 0x37 +#define TIDAC_key_ctrl 0x38 +#define TIDAC_clock_ctrl 0x39 +#define TIDAC_sense_test 0x3a +#define TIDAC_test_mode_data 0x3b +#define TIDAC_crc_remain_lsb 0x3c +#define TIDAC_crc_remain_msb 0x3d +#define TIDAC_crc_bit_select 0x3e +#define TIDAC_id 0x3f + +/* These are pll values that are accessed via TIDAC_pll_pixel_data */ +#define TIDAC_PIXEL_N 0x80 +#define TIDAC_PIXEL_M 0x81 +#define TIDAC_PIXEL_P 0x82 +#define TIDAC_PIXEL_VALID 0x83 + +/* These are pll values that are accessed via TIDAC_pll_loop_data */ +#define TIDAC_LOOP_N 0x90 +#define TIDAC_LOOP_M 0x91 +#define TIDAC_LOOP_P 0x92 +#define TIDAC_LOOP_VALID 0x93 + +/* Direct mapping addresses */ +#define TIDAC_INDEX 0xa0 +#define TIDAC_PALETTE_DATA 0xa1 +#define TIDAC_READ_MASK 0xa2 +#define TIDAC_READ_ADDR 0xa3 +#define TIDAC_CURS_WRITE_ADDR 0xa4 +#define TIDAC_CURS_COLOR 0xa5 +#define TIDAC_CURS_READ_ADDR 0xa7 +#define TIDAC_CURS_CTL 0xa9 +#define TIDAC_INDEXED_DATA 0xaa +#define TIDAC_CURS_RAM_DATA 0xab +#define TIDAC_CURS_XLOW 0xac +#define TIDAC_CURS_XHIGH 0xad +#define TIDAC_CURS_YLOW 0xae +#define TIDAC_CURS_YHIGH 0xaf + +#define TIDAC_sw_reset 0xff + +/* Constants */ +#define TIDAC_TVP_3026_ID 0x26 +#define TIDAC_TVP_3030_ID 0x30 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TIPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TIPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/TIPriv.h (revision 51223) @@ -0,0 +1,30 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TIPriv.h,v 1.2 1998/07/25 16:57:19 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "TI.h" + +typedef struct { + char *DeviceName; +} xf86TIramdacInfo; + +extern xf86TIramdacInfo TIramdacDeviceInfo[]; + +#ifdef INIT_TI_RAMDAC_INFO +xf86TIramdacInfo TIramdacDeviceInfo[] = { + {"TI TVP3030"}, + {"TI TVP3026"} +}; +#endif + +#define TISAVE(_reg) do { \ + ramdacReg->DacRegs[_reg] = (*ramdacPtr->ReadDAC)(pScrn, _reg); \ +} while (0) + +#define TIRESTORE(_reg) do { \ + (*ramdacPtr->WriteDAC)(pScrn, _reg, \ + (ramdacReg->DacRegs[_reg] & 0xFF00) >> 8, \ + ramdacReg->DacRegs[_reg]); \ +} while (0) Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XApplication.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XApplication.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XApplication.h (revision 51223) @@ -0,0 +1,47 @@ +// +// XApplication.h +// +// Created by Andreas Monitzer on January 6, 2001. +// +/* + * Copyright (c) 2001 Andreas Monitzer. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XFree86: $ */ + +#import + +#import "XServer.h" +#import "Preferences.h" + +@interface XApplication : NSApplication { + IBOutlet XServer *xserver; + IBOutlet Preferences *preferences; +} + +- (void)sendEvent:(NSEvent *)anEvent; + +@end Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XIstubs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XIstubs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XIstubs.h (revision 51223) @@ -0,0 +1,76 @@ +/* $XFree86: xc/programs/Xserver/include/XIstubs.h,v 3.1 1996/04/15 11:34:22 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef XI_STUBS_H +#define XI_STUBS_H 1 + +int +ChangeKeyboardDevice ( + DeviceIntPtr /* old_dev */, + DeviceIntPtr /* new_dev */); + +int +ChangePointerDevice ( + DeviceIntPtr /* old_dev */, + DeviceIntPtr /* new_dev */, + unsigned char /* x */, + unsigned char /* y */); + +void +CloseInputDevice ( + DeviceIntPtr /* d */, + ClientPtr /* client */); + +void +AddOtherInputDevices (void); + +void +OpenInputDevice ( + DeviceIntPtr /* dev */, + ClientPtr /* client */, + int * /* status */); + +int +SetDeviceMode ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* mode */); + +int +SetDeviceValuators ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int * /* valuators */, + int /* first_valuator */, + int /* num_valuators */); + +int +ChangeDeviceControl ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + xDeviceCtl * /* control */); + +#endif /* XI_STUBS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XServer.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XServer.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XServer.h (revision 51223) @@ -0,0 +1,138 @@ +// +// XServer.h +// +/* + * Copyright (c) 2001 Andreas Monitzer. All Rights Reserved. + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XdotOrg: xc/programs/Xserver/hw/darwin/quartz/XServer.h,v 1.4 2005/04/20 12:25:19 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/XServer.h,v 1.16 2003/11/23 06:04:01 torrey Exp $ */ + +#define BOOL xBOOL +#include +#undef BOOL + +#import + +@interface XServer : NSObject { + // Server state + int serverState; + NSRecursiveLock *serverLock; + NSMutableArray *pendingClients; + BOOL serverVisible; + BOOL rootlessMenuBarVisible; + BOOL queueShowServer; + BOOL quitWithoutQuery; + BOOL pendingAppQuitReply; + UInt32 mouseState; + unsigned short swallowedKey; + BOOL sendServerEvents; + BOOL x11Active; + + // Aqua interface + IBOutlet NSWindow *modeWindow; + IBOutlet NSButton *startupModeButton; + IBOutlet NSButton *startFullScreenButton; + IBOutlet NSButton *startRootlessButton; + IBOutlet NSWindow *helpWindow; + IBOutlet NSButton *startupHelpButton; + IBOutlet NSPanel *switchWindow; + + // Menu elements setable by Apple-WM extension + IBOutlet NSMenu *windowMenu; + IBOutlet NSMenuItem *windowSeparator; + IBOutlet NSMenu *dockMenu; + int checkedWindowItem; +} + +- (id)init; + +- (BOOL)translateEvent:(NSEvent *)anEvent; +- (BOOL)getMousePosition:(xEvent *)xe fromEvent:(NSEvent *)anEvent; + +- (NSString *)makeSafePath:(NSString *)path; + +- (BOOL)loadDisplayBundle; +- (void)startX; +- (void)finishStartX; +- (BOOL)startXClients; +- (void)runClient:(NSString *)filename; +- (void)run; +- (void)toggle; +- (void)showServer:(BOOL)show; +- (void)forceShowServer:(BOOL)show; +- (void)setRootClip:(BOOL)enable; +- (void)readPasteboard; +- (void)writePasteboard; +- (void)quitServer; +- (void)sendXEvent:(xEvent *)xe; +- (void)sendShowHide:(BOOL)show; +- (void)clientProcessDone:(int)clientStatus; +- (void)activateX11:(BOOL)state; +- (void)windowBecameKey:(NSNotification *)notification; +- (void)setX11WindowList:(NSArray *)list; +- (void)setX11WindowCheck:(NSNumber *)nn; + +// Aqua interface actions +- (IBAction)startFullScreen:(id)sender; +- (IBAction)startRootless:(id)sender; +- (IBAction)closeHelpAndShow:(id)sender; +- (IBAction)showSwitchPanel:(id)sender; +- (IBAction)showAction:(id)sender; +- (IBAction)itemSelected:(id)sender; +- (IBAction)nextWindow:(id)sender; +- (IBAction)previousWindow:(id)sender; +- (IBAction)performClose:(id)sender; +- (IBAction)performMiniaturize:(id)sender; +- (IBAction)performZoom:(id)sender; +- (IBAction)bringAllToFront:(id)sender; +- (IBAction)copy:(id)sender; + +// NSApplication delegate +- (NSApplicationTerminateReply)applicationShouldTerminate:(NSApplication *)sender; +- (void)applicationWillTerminate:(NSNotification *)aNotification; +- (void)applicationDidFinishLaunching:(NSNotification *)aNotification; +- (void)applicationDidHide:(NSNotification *)aNotification; +- (void)applicationDidUnhide:(NSNotification *)aNotification; +- (BOOL)applicationShouldHandleReopen:(NSApplication *)theApplication hasVisibleWindows:(BOOL)flag; +- (void)applicationWillResignActive:(NSNotification *)aNotification; +- (void)applicationWillBecomeActive:(NSNotification *)aNotification; +- (BOOL)application:(NSApplication *)theApplication openFile:(NSString *)filename; + +// NSPort delegate +- (void)handlePortMessage:(NSPortMessage *)portMessage; + +@end + +// X server states +enum { + server_NotStarted, + server_Starting, + server_Running, + server_Quitting, + server_Done +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XView.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XView.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/XView.h (revision 51223) @@ -0,0 +1,42 @@ +/* + * NSView subclass for Mac OS X rootless X server + * + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/XView.h,v 1.2 2002/07/15 19:58:31 torrey Exp $ */ + +#import + +@interface XView : NSQuickDrawView + +- (BOOL)isFlipped; +- (BOOL)isOpaque; +- (BOOL)acceptsFirstResponder; +- (BOOL)acceptsFirstMouse:(NSEvent *)theEvent; +- (BOOL)shouldDelayWindowOrderingForEvent:(NSEvent *)theEvent; + +- (void)mouseDown:(NSEvent *)anEvent; + +@end Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Xplugin.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Xplugin.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/Xplugin.h (revision 51223) @@ -0,0 +1,591 @@ +/* Xplugin.h -- windowing API for rootless X11 server + $Id: Xplugin.h,v 1.3 2005/07/01 22:43:08 daniels Exp $ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. + + Note that these interfaces are provided solely for the use of the + X11 server. Any other uses are unsupported and strongly discouraged. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/Xplugin.h,v 1.2 2003/05/02 00:08:49 torrey Exp $ */ + +#ifndef XPLUGIN_H +#define XPLUGIN_H 1 + +#include + +/* By default we use the X server definition of BoxRec to define xp_box, + so that the compiler can silently convert between the two. But if + XP_NO_X_HEADERS is defined, we'll define it ourselves. */ + +#ifndef XP_NO_X_HEADERS +# include "miscstruct.h" + typedef BoxRec xp_box; +#else + struct xp_box_struct { + short x1, y1, x2, y2; + }; + typedef struct xp_box_struct xp_box; +#endif + +typedef unsigned int xp_resource_id; +typedef xp_resource_id xp_window_id; +typedef xp_resource_id xp_surface_id; +typedef unsigned int xp_client_id; +typedef unsigned int xp_request_type; +typedef int xp_error; +typedef int xp_bool; + + +/* Error codes that the functions declared here may return. They all + numerically match their X equivalents, i.e. the XP_ can be dropped + if has been included. */ + +enum xp_error_enum { + XP_Success = 0, + XP_BadRequest = 1, + XP_BadValue = 2, + XP_BadWindow = 3, + XP_BadMatch = 8, + XP_BadAccess = 10, + XP_BadImplementation = 17, +}; + + +/* Event types generated by the plugin. */ + +enum xp_event_type_enum { + /* The global display configuration changed somehow. */ + XP_EVENT_DISPLAY_CHANGED = 1 << 0, + + /* A window changed state. Argument is xp_window_state_event */ + XP_EVENT_WINDOW_STATE_CHANGED = 1 << 1, + + /* An async request encountered an error. Argument is of type + xp_async_error_event */ + XP_EVENT_ASYNC_ERROR = 1 << 2, + + /* Sent when a surface is destroyed as a side effect of destroying + a window. Arg is of type xp_surface_id. */ + XP_EVENT_SURFACE_DESTROYED = 1 << 3, + + /* Sent when any GL contexts pointing at the given surface need to + call xp_update_gl_context () to refresh their state (because the + window moved or was resized. Arg is of type xp_surface_id. */ + XP_EVENT_SURFACE_CHANGED = 1 << 4, + + /* Sent when a window has been moved. Arg is of type xp_window_id. */ + XP_EVENT_WINDOW_MOVED = 1 << 5, +}; + +/* Function type used to receive events. */ + +typedef void (xp_event_fun) (unsigned int type, const void *arg, + unsigned int arg_size, void *user_data); + + +/* Operation types. Used when reporting errors asynchronously. */ + +enum xp_request_type_enum { + XP_REQUEST_NIL = 0, + XP_REQUEST_DESTROY_WINDOW = 1, + XP_REQUEST_CONFIGURE_WINDOW = 2, + XP_REQUEST_FLUSH_WINDOW = 3, + XP_REQUEST_COPY_WINDOW = 4, + XP_REQUEST_UNLOCK_WINDOW = 5, + XP_REQUEST_DISABLE_UPDATE = 6, + XP_REQUEST_REENABLE_UPDATE = 7, + XP_REQUEST_HIDE_CURSOR = 8, + XP_REQUEST_SHOW_CURSOR = 9, + XP_REQUEST_FRAME_DRAW = 10, +}; + +/* Structure used to report an error asynchronously. Passed as the "arg" + of an XP_EVENT_ASYNC_ERROR event. */ + +struct xp_async_error_event_struct { + xp_request_type request_type; + xp_resource_id id; + xp_error error; +}; + +typedef struct xp_async_error_event_struct xp_async_error_event; + + +/* Possible window states. */ + +enum xp_window_state_enum { + /* The window is not in the global list of possibly-visible windows. */ + XP_WINDOW_STATE_OFFSCREEN = 1 << 0, + + /* Parts of the window may be obscured by other windows. */ + XP_WINDOW_STATE_OBSCURED = 1 << 1, +}; + +/* Structure passed as argument of an XP_EVENT_WINDOW_STATE_CHANGED event. */ + +struct xp_window_state_event_struct { + xp_window_id id; + unsigned int state; +}; + +typedef struct xp_window_state_event_struct xp_window_state_event; + + +/* Function type used to supply a colormap for indexed drawables. */ + +typedef xp_error (xp_colormap_fun) (void *data, int first_color, + int n_colors, uint32_t *colors); + + +/* Window attributes structure. Used when creating and configuring windows. + Also used when configuring surfaces attached to windows. Functions that + take one of these structures also take a bit mask defining which + fields are set to meaningful values. */ + +enum xp_window_changes_enum { + XP_ORIGIN = 1 << 0, + XP_SIZE = 1 << 1, + XP_BOUNDS = XP_ORIGIN | XP_SIZE, + XP_SHAPE = 1 << 2, + XP_STACKING = 1 << 3, + XP_DEPTH = 1 << 4, + XP_COLORMAP = 1 << 5, + XP_WINDOW_LEVEL = 1 << 6, +}; + +struct xp_window_changes_struct { + /* XP_ORIGIN */ + int x, y; + + /* XP_SIZE */ + unsigned int width, height; + int bit_gravity; /* how to resize the backing store */ + + /* XP_SHAPE */ + int shape_nrects; /* -1 = remove shape */ + xp_box *shape_rects; + int shape_tx, shape_ty; /* translation for shape */ + + /* XP_STACKING */ + int stack_mode; + xp_window_id sibling; /* may be zero; in ABOVE/BELOW modes + it may specify a relative window */ + /* XP_DEPTH, window-only */ + unsigned int depth; + + /* XP_COLORMAP, window-only */ + xp_colormap_fun *colormap; + void *colormap_data; + + /* XP_WINDOW_LEVEL, window-only */ + int window_level; +}; + +typedef struct xp_window_changes_struct xp_window_changes; + +/* Values for bit_gravity field */ + +enum xp_bit_gravity_enum { + XP_GRAVITY_NONE = 0, /* no gravity, fill everything */ + XP_GRAVITY_NORTH_WEST = 1, /* anchor to top-left corner */ + XP_GRAVITY_NORTH_EAST = 2, /* anchor to top-right corner */ + XP_GRAVITY_SOUTH_EAST = 3, /* anchor to bottom-right corner */ + XP_GRAVITY_SOUTH_WEST = 4, /* anchor to bottom-left corner */ +}; + +/* Values for stack_mode field */ + +enum xp_window_stack_mode_enum { + XP_UNMAPPED = 0, /* remove the window */ + XP_MAPPED_ABOVE = 1, /* display the window on top */ + XP_MAPPED_BELOW = 2, /* display the window at bottom */ +}; + +/* Data formats for depth field and composite functions */ + +enum xp_depth_enum { + XP_DEPTH_NIL = 0, /* null source when compositing */ + XP_DEPTH_ARGB8888, + XP_DEPTH_RGB555, + XP_DEPTH_A8, /* for masks when compositing */ + XP_DEPTH_INDEX8, +}; + +/* Options that may be passed to the xp_init () function. */ + +enum xp_init_options_enum { + /* Don't mark that this process can be in the foreground. */ + XP_IN_BACKGROUND = 1 << 0, + + /* Deliver background pointer events to this process. */ + XP_BACKGROUND_EVENTS = 1 << 1, +}; + + + +/* Miscellaneous functions */ + +/* Initialize the plugin library. Only the copy/fill/composite functions + may be called without having previously called xp_init () */ + +extern xp_error xp_init (unsigned int options); + +/* Sets the current set of requested notifications to MASK. When any of + these arrive, CALLBACK will be invoked with CALLBACK-DATA. Note that + calling this function cancels any previously requested notifications + that aren't set in MASK. */ + +extern xp_error xp_select_events (unsigned int mask, + xp_event_fun *callback, + void *callback_data); + +/* Waits for all initiated operations to complete. */ + +extern xp_error xp_synchronize (void); + +/* Causes any display update initiated through the plugin libary to be + queued until update is reenabled. Note that calls to these functions + nest. */ + +extern xp_error xp_disable_update (void); +extern xp_error xp_reenable_update (void); + + + +/* Cursor functions. */ + +/* Installs the specified cursor. ARGB-DATA should point to 32-bit + premultiplied big-endian ARGB data. The HOT-X,HOT-Y parameters + specify the offset to the cursor's hot spot from its top-left + corner. */ + +extern xp_error xp_set_cursor (unsigned int width, unsigned int height, + unsigned int hot_x, unsigned int hot_y, + const uint32_t *argb_data, + unsigned int rowbytes); + +/* Hide and show the cursor if it's owned by the current process. Calls + to these functions nest. */ + +extern xp_error xp_hide_cursor (void); +extern xp_error xp_show_cursor (void); + + + +/* Window functions. */ + +/* Create a new window as defined by MASK and VALUES. MASK must contain + XP_BOUNDS or an error is raised. The id of the newly created window + is stored in *RET-ID if this function returns XP_Success. */ + +extern xp_error xp_create_window (unsigned int mask, + const xp_window_changes *values, + xp_window_id *ret_id); + +/* Destroys the window identified by ID. */ + +extern xp_error xp_destroy_window (xp_window_id id); + +/* Reconfigures the given window according to MASK and VALUES. */ + +extern xp_error xp_configure_window (xp_window_id id, unsigned int mask, + const xp_window_changes *values); + + +/* Returns true if NATIVE-ID is a window created by the plugin library. + If so and RET-ID is non-null, stores the id of the window in *RET-ID. */ + +extern xp_bool xp_lookup_native_window (unsigned int native_id, + xp_window_id *ret_id); + +/* If ID names a window created by the plugin library, stores it's native + window id in *RET-NATIVE-ID. */ + +extern xp_error xp_get_native_window (xp_window_id id, + unsigned int *ret_native_id); + + +/* Locks the rectangle IN-RECT (or, if null, the entire window) of the + given window's backing store. Any other non-null parameters are filled + in as follows: + + DEPTH = format of returned data. Currently either XP_DEPTH_ARGB8888 + or XP_DEPTH_RGB565 (possibly with 8 bit planar alpha). Data is + always stored in native byte order. + + BITS[0] = pointer to top-left pixel of locked color data + BITS[1] = pointer to top-left of locked alpha data, or null if window + has no alpha. If the alpha data is meshed, then BITS[1] = BITS[0]. + + ROWBYTES[0,1] = size in bytes of each row of color,alpha data + + OUT-RECT = rectangle specifying the current position and size of the + locked region relative to the window origin. + + Note that an error is raised when trying to lock an already locked + window. While the window is locked, the only operations that may + be performed on it are to modify, access or flush its marked region. */ + +extern xp_error xp_lock_window (xp_window_id id, + const xp_box *in_rect, + unsigned int *depth, + void *bits[2], + unsigned int rowbytes[2], + xp_box *out_rect); + +/* Mark that the region specified by SHAPE-NRECTS, SHAPE-RECTS, + SHAPE-TX, and SHAPE-TY in the specified window has been updated, and + will need to subsequently be redisplayed. */ + +extern xp_error xp_mark_window (xp_window_id id, int shape_nrects, + const xp_box *shape_rects, + int shape_tx, int shape_ty); + +/* Unlocks the specified window. If FLUSH is true, then any marked + regions are immediately redisplayed. Note that it's an error to + unlock an already unlocked window. */ + +extern xp_error xp_unlock_window (xp_window_id id, xp_bool flush); + +/* If anything is marked in the given window for redisplay, do it now. */ + +extern xp_error xp_flush_window (xp_window_id id); + +/* Moves the contents of the region DX,DY pixels away from that specified + by DST_RECTS and DST_NRECTS in the window with SRC-ID to the + destination region in the window DST-ID. Note that currently source + and destination windows must be the same. */ + +extern xp_error xp_copy_window (xp_window_id src_id, xp_window_id dst_id, + int dst_nrects, const xp_box *dst_rects, + int dx, int dy); + +/* Returns true if the given window has any regions marked for + redisplay. */ + +extern xp_bool xp_is_window_marked (xp_window_id id); + +/* If successful returns a superset of the region marked for update in + the given window. Use xp_free_region () to release the returned data. */ + +extern xp_error xp_get_marked_shape (xp_window_id id, + int *ret_nrects, xp_box **ret_rects); + +extern void xp_free_shape (int nrects, xp_box *rects); + +/* Searches for the first window below ABOVE-ID containing the point X,Y, + and returns it's window id in *RET-ID. If no window is found, *RET-ID + is set to zero. If ABOVE-ID is zero, finds the topmost window + containing the given point. */ + +extern xp_error xp_find_window (int x, int y, xp_window_id above_id, + xp_window_id *ret_id); + +/* Returns the current origin and size of the window ID in *BOUNDS-RET if + successful. */ +extern xp_error xp_get_window_bounds (xp_window_id id, xp_box *bounds_ret); + + + +/* Window surface functions. */ + +/* Create a new VRAM surface on the specified window. If successful, + returns the identifier of the new surface in *RET-SID. */ + +extern xp_error xp_create_surface (xp_window_id id, xp_surface_id *ret_sid); + +/* Destroys the specified surface. */ + +extern xp_error xp_destroy_surface (xp_surface_id sid); + +/* Reconfigures the specified surface as defined by MASK and VALUES. + Note that specifying XP_DEPTH is an error. */ + +extern xp_error xp_configure_surface (xp_surface_id sid, unsigned int mask, + const xp_window_changes *values); + +/* If successful, places the client identifier of the current process + in *RET-CLIENT. */ + +extern xp_error xp_get_client_id (xp_client_id *ret_client); + +/* Given a valid window,surface combination created by the current + process, attempts to allow the specified external client access + to that surface. If successful, returns two integers in RET-KEY + which the client can use to import the surface into their process. */ + +extern xp_error xp_export_surface (xp_window_id wid, xp_surface_id sid, + xp_client_id client, + unsigned int ret_key[2]); + +/* Given a two integer key returned from xp_export_surface (), tries + to import the surface into the current process. If successful the + local surface identifier is stored in *SID-RET. */ + +extern xp_error xp_import_surface (const unsigned int key[2], + xp_surface_id *sid_ret); + +/* If successful, stores the number of surfaces attached to the + specified window in *RET. */ + +extern xp_error xp_get_window_surface_count (xp_window_id id, + unsigned int *ret); + +/* Attaches the CGLContextObj CGL-CTX to the specified surface. */ + +extern xp_error xp_attach_gl_context (void *cgl_ctx, xp_surface_id sid); + +/* Updates the CGLContextObj CGL-CTX to reflect any recent changes to + the surface it's attached to. */ + +extern xp_error xp_update_gl_context (void *cgl_ctx); + + + +/* Window frame functions. */ + +/* Possible arguments to xp_frame_get_rect (). */ + +enum xp_frame_rect_enum { + XP_FRAME_RECT_TITLEBAR = 1, + XP_FRAME_RECT_TRACKING = 2, + XP_FRAME_RECT_GROWBOX = 3, +}; + +/* Classes of window frame. */ + +enum xp_frame_class_enum { + XP_FRAME_CLASS_DOCUMENT = 1 << 0, + XP_FRAME_CLASS_DIALOG = 1 << 1, + XP_FRAME_CLASS_MODAL_DIALOG = 1 << 2, + XP_FRAME_CLASS_SYSTEM_MODAL_DIALOG = 1 << 3, + XP_FRAME_CLASS_UTILITY = 1 << 4, + XP_FRAME_CLASS_TOOLBAR = 1 << 5, + XP_FRAME_CLASS_MENU = 1 << 6, + XP_FRAME_CLASS_SPLASH = 1 << 7, + XP_FRAME_CLASS_BORDERLESS = 1 << 8, +}; + +/* Attributes of window frames. */ + +enum xp_frame_attr_enum { + XP_FRAME_ACTIVE = 0x0001, + XP_FRAME_URGENT = 0x0002, + XP_FRAME_TITLE = 0x0004, + XP_FRAME_PRELIGHT = 0x0008, + XP_FRAME_SHADED = 0x0010, + XP_FRAME_CLOSE_BOX = 0x0100, + XP_FRAME_COLLAPSE = 0x0200, + XP_FRAME_ZOOM = 0x0400, + XP_FRAME_ANY_BUTTON = 0x0700, + XP_FRAME_CLOSE_BOX_CLICKED = 0x0800, + XP_FRAME_COLLAPSE_BOX_CLICKED = 0x1000, + XP_FRAME_ZOOM_BOX_CLICKED = 0x2000, + XP_FRAME_ANY_CLICKED = 0x3800, + XP_FRAME_GROW_BOX = 0x4000, +}; + +#define XP_FRAME_ATTR_IS_SET(a,b) (((a) & (b)) == (b)) +#define XP_FRAME_ATTR_IS_CLICKED(a,m) ((a) & ((m) << 3)) +#define XP_FRAME_ATTR_SET_CLICKED(a,m) ((a) |= ((m) << 3)) +#define XP_FRAME_ATTR_UNSET_CLICKED(a,m) ((a) &= ~((m) << 3)) + +#define XP_FRAME_POINTER_ATTRS (XP_FRAME_PRELIGHT \ + | XP_FRAME_ANY_BUTTON \ + | XP_FRAME_ANY_CLICKED) + +extern xp_error xp_frame_get_rect (int type, int class, const xp_box *outer, + const xp_box *inner, xp_box *ret); +extern xp_error xp_frame_hit_test (int class, int x, int y, + const xp_box *outer, + const xp_box *inner, int *ret); +extern xp_error xp_frame_draw (xp_window_id wid, int class, unsigned int attr, + const xp_box *outer, const xp_box *inner, + unsigned int title_len, + const unsigned char *title_bytes); + + + +/* Memory manipulation functions. */ + +enum xp_composite_op_enum { + XP_COMPOSITE_SRC = 0, + XP_COMPOSITE_OVER, +}; + +#define XP_COMPOSITE_FUNCTION(op, src_depth, mask_depth, dest_depth) \ + (((op) << 24) | ((src_depth) << 16) \ + | ((mask_depth) << 8) | ((dest_depth) << 0)) + +#define XP_COMPOSITE_FUNCTION_OP(f) (((f) >> 24) & 255) +#define XP_COMPOSITE_FUNCTION_SRC_DEPTH(f) (((f) >> 16) & 255) +#define XP_COMPOSITE_FUNCTION_MASK_DEPTH(f) (((f) >> 8) & 255) +#define XP_COMPOSITE_FUNCTION_DEST_DEPTH(f) (((f) >> 0) & 255) + +/* Composite WIDTH by HEIGHT pixels from source and mask to destination + using a specified function (if source and destination overlap, + undefined behavior results). + + For SRC and DEST, the first element of the array is the color data. If + the second element is non-null it implies that there is alpha data + (which may be meshed or planar). Data without alpha is assumed to be + opaque. + + Passing a null SRC-ROWBYTES pointer implies that the data SRC points + to is a single element. + + Operations that are not supported will return XP_BadImplementation. */ + +extern xp_error xp_composite_pixels (unsigned int width, unsigned int height, + unsigned int function, + void *src[2], unsigned int src_rowbytes[2], + void *mask, unsigned int mask_rowbytes, + void *dest[2], unsigned int dest_rowbytes[2]); + +/* Fill HEIGHT rows of data starting at DST. Each row will have WIDTH + bytes filled with the 32-bit pattern VALUE. Each row is DST-ROWBYTES + wide in total. */ + +extern void xp_fill_bytes (unsigned int width, + unsigned int height, uint32_t value, + void *dst, unsigned int dst_rowbytes); + +/* Copy HEIGHT rows of bytes from SRC to DST. Each row will have WIDTH + bytes copied. SRC and DST may overlap, and the right thing will happen. */ + +extern void xp_copy_bytes (unsigned int width, unsigned int height, + const void *src, unsigned int src_rowbytes, + void *dst, unsigned int dst_rowbytes); + +/* Suggestions for the minimum number of bytes or pixels for which it + makes sense to use some of the xp_ functions */ + +extern unsigned int xp_fill_bytes_threshold, xp_copy_bytes_threshold, + xp_composite_area_threshold, xp_scroll_area_threshold; + + +#endif /* XPLUGIN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/afb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/afb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/afb.h (revision 51223) @@ -0,0 +1,1132 @@ +/* $XFree86: xc/programs/Xserver/afb/afb.h,v 3.10 2003/10/29 22:15:19 tsi Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.0, 1/17/89 */ +/*********************************************************** + +Copyright (c) 1987 X Consortium + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of the X Consortium shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the X Consortium. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XConsortium: afb.h,v 5.31 94/04/17 20:28:15 dpw Exp $ */ +/* Monochrome Frame Buffer definitions + written by drewry, september 1986 +*/ + +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "regionstr.h" +#include "mibstore.h" +#include "mfb.h" + +extern int afbInverseAlu[]; +extern int afbScreenPrivateIndex; +/* warning: PixelType definition duplicated in maskbits.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ + +#define AFB_MAX_DEPTH 8 + +/* afbbitblt.c */ + +extern void afbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr afbBitBlt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (*doBitBlt)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ + ), + unsigned long /*planemask*/ +); + +extern RegionPtr afbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern RegionPtr afbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); + +extern void afbCopy1ToN( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltC.c */ + +extern void afbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltCI.c */ + +extern void afbDoBitbltCopyInverted( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltG.c */ + +extern void afbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltO.c */ + +extern void afbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltX.c */ + +extern void afbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbres.c */ + +extern void afbBresS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* afbbresd.c */ + +extern void afbBresD( + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/, + unsigned char * /*bgrrops*/ +); +/* afbbstore.c */ + +extern void afbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void afbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* afbclip.c */ + +extern RegionPtr afbPixmapToRegion( + PixmapPtr /*pPix*/ +); + +/* afbcmap.c */ + +extern int afbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void afbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void afbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void afbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool afbInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern int afbExpandDirectColors( + ColormapPtr /*pmap*/, + int /*ndefs*/, + xColorItem * /*indefs*/, + xColorItem * /*outdefs*/ +); + +extern Bool afbCreateDefColormap( + ScreenPtr /*pScreen*/ +); + +extern Bool afbSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +extern Bool afbInitVisuals( + VisualPtr * /*visualp*/, + DepthPtr * /*depthp*/, + int * /*nvisualp*/, + int * /*ndepthp*/, + int * /*rootDepthp*/, + VisualID * /*defaultVisp*/, + unsigned long /*sizes*/, + int /*bitsPerRGB*/ +); + +/* afbfillarc.c */ + +extern void afbPolyFillArcSolid( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* afbfillrct.c */ + +extern void afbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); + +/* afbply1rct.c */ +extern void afbFillPolygonSolid( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*shape*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* afbfillsp.c */ + +extern void afbSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +/* afbfont.c */ + +extern Bool afbRealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +extern Bool afbUnrealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); +/* afbgc.c */ + +extern Bool afbCreateGC( + GCPtr /*pGC*/ +); + +extern void afbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +extern void afbDestroyGC( + GCPtr /*pGC*/ +); + +extern void afbReduceRop( + int /*alu*/, + Pixel /*src*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void afbReduceOpaqueStipple ( + Pixel /*fg*/, + Pixel /*bg*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void afbComputeCompositeClip( + GCPtr /*pGC*/, + DrawablePtr /*pDrawable*/ +); + +/* afbgetsp.c */ + +extern void afbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* afbhrzvert.c */ + +extern void afbHorzS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); + +extern void afbVertS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* afbigbblak.c */ + +extern void afbImageGlyphBlt ( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* afbigbwht.c */ + +/* afbimage.c */ + +extern void afbPutImage( + DrawablePtr /*dst*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void afbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* afbline.c */ + +extern void afbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void afbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +/* afbmisc.c */ + +extern void afbQueryBestSize( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/ +); +/* afbpntarea.c */ + +extern void afbSolidFillArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + unsigned char * /*rrops*/ +); + +extern void afbStippleAreaPPW( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + unsigned char * /*rrops*/ +); +extern void afbStippleArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + int /*xOff*/, + int /*yOff*/, + unsigned char * /*rrops*/ +); +/* afbplygblt.c */ + +extern void afbPolyGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +/* afbpixmap.c */ + +extern PixmapPtr afbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool afbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr afbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void afbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void afbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void afbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void afbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +extern void afbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); +/* afbpolypnt.c */ + +extern void afbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* afbpushpxl.c */ + +extern void afbPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* afbscrclse.c */ + +extern Bool afbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); +/* afbscrinit.c */ + +extern Bool afbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*pWinIndex*/, + int * /*pGCIndex*/ +); + +extern Bool afbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr afbGetWindowPixmap( + WindowPtr /*pWin*/ +); + +extern void afbSetWindowPixmap( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/ +); + +/* afbseg.c */ + +extern void afbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void afbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* afbsetsp.c */ + +extern void afbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + PixelType * /*psrc*/, + int /*alu*/, + PixelType * /*pdstBase*/, + int /*widthDst*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*sizeSrc*/ +); + +extern void afbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* afbtegblt.c */ + +extern void afbTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* afbtileC.c */ + +extern void afbTileAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbTileAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); + +extern void afbTileAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbTileAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); + +extern void afbOpaqueStippleAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbOpaqueStippleAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +extern void afbOpaqueStippleAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbOpaqueStippleAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +/* afbwindow.c */ + +extern Bool afbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool afbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool afbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool afbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool afbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void afbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool afbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* afbzerarc.c */ + +extern void afbZeroPolyArcSS( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* + private field of pixmap + pixmap.devPrivate = (PixelType *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes + + private field of screen + a pixmap, for which we allocate storage. devPrivate is a pointer to +the bits in the hardware framebuffer. note that devKind can be poked to +make the code work for framebuffers that are wider than their +displayable screen (e.g. the early vsII, which displayed 960 pixels +across, but was 1024 in the hardware.) + + private field of GC +*/ + +typedef struct { + unsigned char rrops[AFB_MAX_DEPTH]; /* reduction of rasterop to 1 of 3 */ + unsigned char rropOS[AFB_MAX_DEPTH]; /* rop for opaque stipple */ +} afbPrivGC; +typedef afbPrivGC *afbPrivGCPtr; + +extern int afbGCPrivateIndex; /* index into GC private array */ +extern int afbWindowPrivateIndex; /* index into Window private array */ +#ifdef PIXMAP_PER_WINDOW +extern int frameWindowPrivateIndex; /* index into Window private array */ +#endif + +#define afbGetGCPrivate(pGC) \ + ((afbPrivGC *)((pGC)->devPrivates[afbGCPrivateIndex].ptr)) + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border tile is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; +} afbPrivWin; + +/* Common macros for extracting drawing information */ + +#define afbGetTypedWidth(pDrawable,wtype)( \ + (((pDrawable)->type == DRAWABLE_WINDOW) ? \ + (int)(((PixmapPtr)((pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr))->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define afbGetByteWidth(pDrawable) afbGetTypedWidth(pDrawable, unsigned char) + +#define afbGetPixelWidth(pDrawable) afbGetTypedWidth(pDrawable, PixelType) + +#define afbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr)(pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + else \ + _pPix = (PixmapPtr)(pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define afbGetPixelWidthSizeDepthAndPointer(pDrawable, width, size, dep, pointer) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr)(pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + else \ + _pPix = (PixmapPtr)(pDrawable); \ + (pointer) = (PixelType *)_pPix->devPrivate.ptr; \ + (width) = ((int)_pPix->devKind) / sizeof (PixelType); \ + (size) = (width) * _pPix->drawable.height; \ + (dep) = _pPix->drawable.depth; (void)(dep); \ +} + +#define afbGetByteWidthAndPointer(pDrawable, width, pointer) \ + afbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define afbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + afbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define afbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = (PixmapPtr)(pWin)->drawable.pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define afbGetWindowPixelWidthAndPointer(pWin, width, pointer) \ + afbGetWindowTypedWidthAndPointer(pWin, width, pointer, PixelType, PixelType) + +#define afbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + afbGetWindowTypedWidthAndPointer(pWin, width, pointer, char, char) + +/* afb uses the following macros to calculate addresses in drawables. + * To support banked framebuffers, the macros come in four flavors. + * All four collapse into the same definition on unbanked devices. + * + * afbScanlineFoo - calculate address and do bank switching + * afbScanlineFooNoBankSwitch - calculate address, don't bank switch + * afbScanlineFooSrc - calculate address, switch source bank + * afbScanlineFooDst - calculate address, switch destination bank + */ + +/* The NoBankSwitch versions are the same for banked and unbanked cases */ + +#define afbScanlineIncNoBankSwitch(_ptr, _off) _ptr += (_off) +#define afbScanlineOffsetNoBankSwitch(_ptr, _off) ((_ptr) + (_off)) +#define afbScanlineDeltaNoBankSwitch(_ptr, _y, _w) \ + afbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w)) +#define afbScanlineNoBankSwitch(_ptr, _x, _y, _w) \ + afbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +#ifdef MFB_LINE_BANK + +#include "afblinebank.h" /* get macro definitions from this file */ + +#else /* !MFB_LINE_BANK - unbanked case */ + +#define afbScanlineInc(_ptr, _off) afbScanlineIncNoBankSwitch(_ptr, _off) +#define afbScanlineIncSrc(_ptr, _off) afbScanlineInc(_ptr, _off) +#define afbScanlineIncDst(_ptr, _off) afbScanlineInc(_ptr, _off) + +#define afbScanlineOffset(_ptr, _off) afbScanlineOffsetNoBankSwitch(_ptr, _off) +#define afbScanlineOffsetSrc(_ptr, _off) afbScanlineOffset(_ptr, _off) +#define afbScanlineOffsetDst(_ptr, _off) afbScanlineOffset(_ptr, _off) + +#define afbScanlineSrc(_ptr, _x, _y, _w) afbScanline(_ptr, _x, _y, _w) +#define afbScanlineDst(_ptr, _x, _y, _w) afbScanline(_ptr, _x, _y, _w) + +#define afbScanlineDeltaSrc(_ptr, _y, _w) afbScanlineDelta(_ptr, _y, _w) +#define afbScanlineDeltaDst(_ptr, _y, _w) afbScanlineDelta(_ptr, _y, _w) + +#endif /* MFB_LINE_BANK */ + +#define afbScanlineDelta(_ptr, _y, _w) \ + afbScanlineOffset(_ptr, (_y) * (_w)) + +#define afbScanline(_ptr, _x, _y, _w) \ + afbScanlineOffset(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +/* precomputed information about each glyph for GlyphBlt code. + this saves recalculating the per glyph information for each box. +*/ + +typedef struct _afbpos{ + int xpos; /* xposition of glyph's origin */ + int xchar; /* x position mod 32 */ + int leftEdge; + int rightEdge; + int topEdge; + int bottomEdge; + PixelType *pdstBase; /* longword with character origin */ + int widthGlyph; /* width in bytes of this glyph */ +} afbTEXTPOS; + +/* reduced raster ops for afb */ +#define RROP_BLACK GXclear +#define RROP_WHITE GXset +#define RROP_NOP GXnoop +#define RROP_INVERT GXinvert +#define RROP_COPY GXcopy + +/* macros for afbbitblt.c, afbfillsp.c + these let the code do one switch on the rop per call, rather + than a switch on the rop per item (span or rectangle.) +*/ + +#define fnCLEAR(src, dst) (0) +#define fnAND(src, dst) (src & dst) +#define fnANDREVERSE(src, dst) (src & ~dst) +#define fnCOPY(src, dst) (src) +#define fnANDINVERTED(src, dst) (~src & dst) +#define fnNOOP(src, dst) (dst) +#define fnXOR(src, dst) (src ^ dst) +#define fnOR(src, dst) (src | dst) +#define fnNOR(src, dst) (~(src | dst)) +#define fnEQUIV(src, dst) (~src ^ dst) +#define fnINVERT(src, dst) (~dst) +#define fnORREVERSE(src, dst) (src | ~dst) +#define fnCOPYINVERTED(src, dst) (~src) +#define fnORINVERTED(src, dst) (~src | dst) +#define fnNAND(src, dst) (~(src & dst)) +#undef fnSET +#define fnSET(src, dst) (~0) + +/* Using a "switch" statement is much faster in most cases + * since the compiler can do a look-up table or multi-way branch + * instruction, depending on the architecture. The result on + * A Sun 3/50 is at least 2.5 times faster, assuming a uniform + * distribution of RasterOp operation types. + * + * However, doing some profiling on a running system reveals + * GXcopy is the operation over 99.5% of the time and + * GXxor is the next most frequent (about .4%), so we make special + * checks for those first. + * + * Note that this requires a change to the "calling sequence" + * since we can't engineer a "switch" statement to have an lvalue. + */ +#undef DoRop +#define DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) \ + result = fnCOPY (src, dst); \ + else if (alu == GXxor) \ + result = fnXOR (src, dst); \ + else \ + switch (alu) { \ + case GXclear: \ + result = fnCLEAR (src, dst); \ + break; \ + case GXand: \ + result = fnAND (src, dst); \ + break; \ + case GXandReverse: \ + result = fnANDREVERSE (src, dst); \ + break; \ + case GXandInverted: \ + result = fnANDINVERTED (src, dst); \ + break; \ + default: \ + case GXnoop: \ + result = fnNOOP (src, dst); \ + break; \ + case GXor: \ + result = fnOR (src, dst); \ + break; \ + case GXnor: \ + result = fnNOR (src, dst); \ + break; \ + case GXequiv: \ + result = fnEQUIV (src, dst); \ + break; \ + case GXinvert: \ + result = fnINVERT (src, dst); \ + break; \ + case GXorReverse: \ + result = fnORREVERSE (src, dst); \ + break; \ + case GXcopyInverted: \ + result = fnCOPYINVERTED (src, dst); \ + break; \ + case GXorInverted: \ + result = fnORINVERTED (src, dst); \ + break; \ + case GXnand: \ + result = fnNAND (src, dst); \ + break; \ + case GXset: \ + result = fnSET (src, dst); \ + break; \ + } \ +} + + +/* C expression fragments for various operations. These get passed in + * as -D's on the compile command line. See afb/Imakefile. This + * fixes XBUG 6319. + * + * This seems like a good place to point out that afb's use of the + * words black and white is an unfortunate misnomer. In afb code, black + * means zero, and white means one. + */ +#define MFB_OPEQ_WHITE |= +#define MFB_OPEQ_BLACK &=~ +#define MFB_OPEQ_INVERT ^= +#define MFB_EQWHOLEWORD_WHITE =~0 +#define MFB_EQWHOLEWORD_BLACK =0 +#define MFB_EQWHOLEWORD_INVERT ^=~0 +#define MFB_OP_WHITE /* nothing */ +#define MFB_OP_BLACK ~ + +#ifdef XFree86LOADER +#include "xf86_ansic.h" +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/agpgart.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/agpgart.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/agpgart.h (revision 51223) @@ -0,0 +1,109 @@ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/os-support/sunos/agpgart.h,v 1.1 2005/06/09 03:11:58 alanc Exp $ */ +/* + * AGPGART module version 0.99 + * Copyright (C) 1999 Jeff Hartmann + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, and/or sell copies of the Software, and to permit persons + * to whom the Software is furnished to do so, provided that the above + * copyright notice(s) and this permission notice appear in all copies of + * the Software and that both the above copyright notice(s) and this + * permission notice appear in supporting documentation. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT + * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL + * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING + * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Except as contained in this notice, the name of a copyright holder + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * of the copyright holder. + */ + +#ifndef _AGPGART_H +#define _AGPGART_H + +#pragma ident "@(#)agpgart.h 1.1 05/04/04 SMI" + +typedef struct _agp_version { + uint16_t agpv_major; + uint16_t agpv_minor; +} agp_version_t; + +typedef struct _agp_info { + agp_version_t agpi_version; + uint32_t agpi_devid; /* bridge vendor + device */ + uint32_t agpi_mode; /* mode of bridge */ + ulong_t agpi_aperbase; /* base of aperture */ + size_t agpi_apersize; /* aperture range size */ + uint32_t agpi_pgtotal; /* max number of pages in aperture */ + uint32_t agpi_pgsystem; /* same as pg_total */ + uint32_t agpi_pgused; /* NUMBER of currently used pages */ +} agp_info_t; + +typedef struct _agp_setup { + uint32_t agps_mode; +} agp_setup_t; + +typedef struct _agp_allocate { + int32_t agpa_key; + uint32_t agpa_pgcount; + uint32_t agpa_type; + uint32_t agpa_physical; /* for i810/830 driver */ +} agp_allocate_t; + +typedef struct _agp_bind { + int32_t agpb_key; + uint32_t agpb_pgstart; +} agp_bind_t; + +typedef struct _agp_unbind { + int32_t agpu_key; + uint32_t agpu_pri; /* no use in solaris */ +} agp_unbind_t; + +#define AGPIOC_BASE 'G' +#define AGPIOC_INFO _IOR(AGPIOC_BASE, 0, 100) +#define AGPIOC_ACQUIRE _IO(AGPIOC_BASE, 1) +#define AGPIOC_RELEASE _IO(AGPIOC_BASE, 2) +#define AGPIOC_SETUP _IOW(AGPIOC_BASE, 3, agp_setup_t) +#define AGPIOC_ALLOCATE _IOWR(AGPIOC_BASE, 4, agp_allocate_t) +#define AGPIOC_DEALLOCATE _IOW(AGPIOC_BASE, 5, int) +#define AGPIOC_BIND _IOW(AGPIOC_BASE, 6, agp_bind_t) +#define AGPIOC_UNBIND _IOW(AGPIOC_BASE, 7, agp_unbind_t) + +#define AGP_DEVICE "/dev/agpgart" + +#endif /* _AGPGART_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/allowev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/allowev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/allowev.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/allowev.h,v 3.1 1996/04/15 11:18:23 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef ALLOWEV_H +#define ALLOWEV_H 1 + +int +SProcXAllowDeviceEvents( + ClientPtr /* client */ + ); + +int +ProcXAllowDeviceEvents( + ClientPtr /* client */ + ); + +#endif /* ALLOWEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/altixPCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/altixPCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/altixPCI.h (revision 51223) @@ -0,0 +1,20 @@ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_ALTIX_H +#define PCI_ALTIX_H 1 + +#include +#include + +Bool xorgProbeAltix(scanpciWrapperOpt flags); +void xf86PreScanAltix(void); +void xf86PostScanAltix(void); + +/* Some defines for PCI */ +#define VENDOR_SGI 0x10A9 +#define CHIP_TIO_CA 0x1010 +#define CHIP_PIC_PCI 0x1011 + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aout.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aout.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aout.h (revision 51223) @@ -0,0 +1,235 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/aout.h,v 1.7 2002/05/31 18:46:00 dawes Exp $ */ + +/* + * Borrowed from NetBSD's exec_aout.h + * + * Copyright (c) 1993, 1994 Christopher G. Demetriou + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AOUT_H +#define _AOUT_H + +#include + +/* Get prototype for ntohl, per SuSv3. */ +#include + +/* OS/2 EMX has ntohl in this file */ +#ifdef __UNIXOS2__ +#include +#endif + +#define __LDPGSZ 4096U +#ifndef AOUT_PAGSIZ +#define AOUT_PAGSIZ(ex) (__LDPGSZ) +#endif + +/* + * a.out header + */ +typedef struct AOUT_exec { + unsigned long a_midmag; /* htonl(flags<<26 | mid<<16 | magic) */ + unsigned long a_text; /* text segment size */ + unsigned long a_data; /* initialized data size */ + unsigned long a_bss; /* uninitialized data size */ + unsigned long a_syms; /* symbol table size */ + unsigned long a_entry; /* entry point */ + unsigned long a_trsize; /* text relocation size */ + unsigned long a_drsize; /* data relocation size */ +} AOUTHDR; + +/* a_magic */ +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ +#define QMAGIC 0314 /* "compact" demand load format; deprecated */ + +/* + * a_mid - keep sorted in numerical order for sanity's sake + * ensure that: 0 < mid < 0x3ff + */ +#define MID_ZERO 0 /* unknown - implementation dependent */ +#define MID_SUN010 1 /* sun 68010/68020 binary */ +#define MID_SUN020 2 /* sun 68020-only binary */ +#define MID_PC386 100 /* 386 PC binary. (so quoth BFD) */ +#define MID_HP200 200 /* hp200 (68010) BSD binary */ +#define MID_I386 134 /* i386 BSD binary */ +#define MID_M68K 135 /* m68k BSD binary with 8K page sizes */ +#define MID_M68K4K 136 /* m68k BSD binary with 4K page sizes */ +#define MID_NS32532 137 /* ns32532 */ +#define MID_SPARC 138 /* sparc */ +#define MID_PMAX 139 /* pmax */ +#define MID_VAX 140 /* vax */ +#define MID_ALPHA 141 /* Alpha BSD binary */ +#define MID_MIPS 142 /* big-endian MIPS */ +#define MID_ARM6 143 /* ARM6 */ +#define MID_HP300 300 /* hp300 (68020+68881) BSD binary */ +#define MID_HPUX 0x20C /* hp200/300 HP-UX binary */ +#define MID_HPUX800 0x20B /* hp800 HP-UX binary */ + +/* + * a_flags + */ +#define EX_DYNAMIC 0x20 +#define EX_PIC 0x10 +#define EX_DPMASK 0x30 +/* + * Interpretation of the (a_flags & EX_DPMASK) bits: + * + * 00 traditional executable or object file + * 01 object file contains PIC code (set by `as -k') + * 10 dynamic executable + * 11 position independent executable image + * (eg. a shared library) + * + */ + +/* + * The a.out structure's a_midmag field is a network-byteorder encoding + * of this int + * FFFFFFmmmmmmmmmmMMMMMMMMMMMMMMMM + * Where `F' is 6 bits of flag like EX_DYNAMIC, + * `m' is 10 bits of machine-id like MID_I386, and + * `M' is 16 bits worth of magic number, ie. ZMAGIC. + * The macros below will set/get the needed fields. + */ +#define AOUT_GETMAGIC(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? (ntohl(((ex)->a_midmag))&0xffffU) : ((ex)->a_midmag)) +#define AOUT_GETMAGIC2(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? (ntohl(((ex)->a_midmag))&0xffffU) : \ + (((ex)->a_midmag) | 0x10000) ) +#define AOUT_GETMID(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? ((ntohl(((ex)->a_midmag))>>16)&0x03ffU) : MID_ZERO ) +#define AOUT_GETFLAG(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? ((ntohl(((ex)->a_midmag))>>26)&0x3fU) : 0 ) +#define AOUT_SETMAGIC(ex,mag,mid,flag) \ + ( (ex)->a_midmag = htonl( (((flag)&0x3fU)<<26) | (((mid)&0x03ffU)<<16) | \ + (((mag)&0xffffU)) ) ) + +#define AOUT_ALIGN(ex,x) \ + (AOUT_GETMAGIC(ex) == ZMAGIC || AOUT_GETMAGIC(ex) == QMAGIC ? \ + ((x) + __LDPGSZ - 1) & ~(__LDPGSZ - 1) : (x)) + +/* Valid magic number check. */ +#define AOUT_BADMAG(ex) \ + (AOUT_GETMAGIC(ex) != NMAGIC && AOUT_GETMAGIC(ex) != OMAGIC && \ + AOUT_GETMAGIC(ex) != ZMAGIC && AOUT_GETMAGIC(ex) != QMAGIC) + +/* Address of the bottom of the text segment. */ +#define AOUT_TXTADDR(ex) (AOUT_GETMAGIC2(ex) == (ZMAGIC|0x10000) ? 0 : __LDPGSZ) + +/* Address of the bottom of the data segment. */ +#define AOUT_DATADDR(ex) \ + (AOUT_GETMAGIC(ex) == OMAGIC ? AOUT_TXTADDR(ex) + (ex)->a_text : \ + (AOUT_TXTADDR(ex) + (ex)->a_text + __LDPGSZ - 1) & ~(__LDPGSZ - 1)) + +/* Address of the bottom of the bss segment. */ +#define AOUT_BSSADDR(ex) \ + (AOUT_DATADDR(ex) + (ex)->a_data) + +/* Text segment offset. */ +#define AOUT_TXTOFF(ex) \ + ( AOUT_GETMAGIC2(ex)==ZMAGIC || AOUT_GETMAGIC2(ex)==(QMAGIC|0x10000) ? \ + 0 : (AOUT_GETMAGIC2(ex)==(ZMAGIC|0x10000) ? __LDPGSZ : \ + sizeof(struct AOUT_exec)) ) + +/* Data segment offset. */ +#define AOUT_DATOFF(ex) \ + AOUT_ALIGN(ex, AOUT_TXTOFF(ex) + (ex)->a_text) + +/* Text relocation table offset. */ +#define AOUT_TRELOFF(ex) \ + (AOUT_DATOFF(ex) + (ex)->a_data) + +/* Data relocation table offset. */ +#define AOUT_DRELOFF(ex) \ + (AOUT_TRELOFF(ex) + (ex)->a_trsize) + +/* Symbol table offset. */ +#define AOUT_SYMOFF(ex) \ + (AOUT_DRELOFF(ex) + (ex)->a_drsize) + +/* String table offset. */ +#define AOUT_STROFF(ex) \ + (AOUT_SYMOFF(ex) + (ex)->a_syms) + +/* Relocation format. */ +struct relocation_info_i386 { + int r_address; /* offset in text or data segment */ + unsigned int r_symbolnum:24, /* ordinal number of add symbol */ + r_pcrel:1, /* 1 if value should be pc-relative */ + r_length:2, /* log base 2 of value's width */ + r_extern:1, /* 1 if need to add symbol to value */ + r_baserel:1, /* linkage table relative */ + r_jmptable:1, /* relocate to jump table */ + r_relative:1, /* load address relative */ + r_copy:1; /* run time copy */ +}; + +#define relocation_info relocation_info_i386 + +/* + * Symbol table entry format. The #ifdef's are so that programs including + * nlist.h can initialize nlist structures statically. + */ +typedef struct AOUT_nlist { + union { + char *n_name; /* symbol name (in memory) */ + long n_strx; /* file string table offset (on disk) */ + } n_un; + +#define AOUT_UNDF 0x00 /* undefined */ +#define AOUT_ABS 0x02 /* absolute address */ +#define AOUT_TEXT 0x04 /* text segment */ +#define AOUT_DATA 0x06 /* data segment */ +#define AOUT_BSS 0x08 /* bss segment */ +#define AOUT_INDR 0x0a /* alias definition */ +#define AOUT_SIZE 0x0c /* pseudo type, defines a symbol's size */ +#define AOUT_COMM 0x12 /* common reference */ +#define AOUT_FN 0x1e /* file name (AOUT_EXT on) */ +#define AOUT_WARN 0x1e /* warning message (AOUT_EXT off) */ + +#define AOUT_EXT 0x01 /* external (global) bit, OR'ed in */ +#define AOUT_TYPE 0x1e /* mask for all the type bits */ + unsigned char n_type; /* type defines */ + + char n_other; /* spare */ +#define n_hash n_desc /* used internally by ld(1); XXX */ + short n_desc; /* used by stab entries */ + unsigned long n_value; /* address/value of the symbol */ +} AOUT_nlist; + +#define AOUT_FORMAT "%08x" /* namelist value format; XXX */ +#define AOUT_STAB 0x0e0 /* mask for debugger symbols -- stab(5) */ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aoutloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aoutloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/aoutloader.h (revision 51223) @@ -0,0 +1,35 @@ +/* + * Copyright 1997,1998 Metro Link, Inc. + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/aoutloader.h,v 1.3 1998/09/20 14:41:03 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AOUTLOADER_H +#define _AOUTLOADER_H +extern void *AOUTLoadModule(loaderPtr, int, LOOKUP **); +extern void AOUTResolveSymbols(void *); +extern int AOUTCheckForUnresolved(void *); +extern char *AOUTAddressToSection(void *, unsigned long); +extern void AOUTUnloadModule(void *); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/appgroup.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/appgroup.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/appgroup.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86$ */ + +void XagClientStateChange( + CallbackListPtr* pcbl, + pointer nulldata, + pointer calldata); +int ProcXagCreate ( + register ClientPtr client); +int ProcXagDestroy( + register ClientPtr client); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/applewmExt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/applewmExt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/applewmExt.h (revision 51223) @@ -0,0 +1,85 @@ +/* + * External interface for the server's AppleWM support + */ +/************************************************************************** + +Copyright (c) 2002 Apple Computer, Inc. All Rights Reserved. +Copyright (c) 2003-2004 Torrey T. Lyons. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/applewmExt.h,v 1.2 2003/11/11 23:48:41 torrey Exp $ */ + +#ifndef _APPLEWMEXT_H_ +#define _APPLEWMEXT_H_ + +#include "window.h" + +typedef int (*DisableUpdateProc)(void); +typedef int (*EnableUpdateProc)(void); +typedef int (*SetWindowLevelProc)(WindowPtr pWin, int level); +typedef int (*FrameGetRectProc)(int type, int class, const BoxRec *outer, + const BoxRec *inner, BoxRec *ret); +typedef int (*FrameHitTestProc)(int class, int x, int y, + const BoxRec *outer, + const BoxRec *inner, int *ret); +typedef int (*FrameDrawProc)(WindowPtr pWin, int class, unsigned int attr, + const BoxRec *outer, const BoxRec *inner, + unsigned int title_len, + const unsigned char *title_bytes); + +/* + * AppleWM implementation function list + */ +typedef struct _AppleWMProcs { + DisableUpdateProc DisableUpdate; + EnableUpdateProc EnableUpdate; + SetWindowLevelProc SetWindowLevel; + FrameGetRectProc FrameGetRect; + FrameHitTestProc FrameHitTest; + FrameDrawProc FrameDraw; +} AppleWMProcsRec, *AppleWMProcsPtr; + +void AppleWMExtensionInit( + AppleWMProcsPtr procsPtr +); + +void AppleWMSetScreenOrigin( + WindowPtr pWin +); + +Bool AppleWMDoReorderWindow( + WindowPtr pWin +); + +void AppleWMSendEvent( + int /* type */, + unsigned int /* mask */, + int /* which */, + int /* arg */ +); + +unsigned int AppleWMSelectedEvents( + void +); + +#endif /* _APPLEWMEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ar.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ar.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ar.h (revision 51223) @@ -0,0 +1,75 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/ar.h,v 1.3 1998/07/25 16:56:12 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AR_H +#define _AR_H + +#define ARMAG "!\n" +#define SARMAG 8 +#define ARFMAG "`\n" + +#if !(defined(__powerpc__) && defined(Lynx)) +struct ar_hdr { + char ar_name[16]; + char ar_date[12]; + char ar_uid[6]; + char ar_gid[6]; + char ar_mode[8]; + char ar_size[10]; + char ar_fmag[2]; +}; + +#else + +#define AIAMAG "\n" +#define SAIAMAG 8 +#define AIAFMAG "`\n" + +struct fl_hdr { /* archive fixed length header - printable ascii */ + char fl_magic[SAIAMAG]; /* Archive file magic string */ + char fl_memoff[12]; /* Offset to member table */ + char fl_gstoff[12]; /* Offset to global symbol table */ + char fl_fstmoff[12]; /* Offset to first archive member */ + char fl_lstmoff[12]; /* Offset to last archive member */ + char fl_freeoff[12]; /* Offset to first mem on free list */ +}; + +#define FL_HDR struct fl_hdr +#define FL_HSZ sizeof(FL_HDR) + +struct ar_hdr { /* archive file member header - printable ascii */ + char ar_size[12]; /* file member size - decimal */ + char ar_nxtmem[12]; /* pointer to next member - decimal */ + char ar_prvmem[12]; /* pointer to previous member - decimal */ + char ar_date[12]; /* file member date - decimal */ + char ar_uid[12]; /* file member user id - decimal */ + char ar_gid[12]; /* file member group id - decimal */ + char ar_mode[12]; /* file member mode - octal */ + char ar_namlen[4]; /* file member name length - decimal */ + union { + char an_name[2]; /* variable length member name */ + char an_fmag[2]; /* AIAFMAG - string to end header */ + } _ar_name; /* and variable length name */ +}; + +#define ar_name _ar_name.an_name + +/* + * Note: 'ar_namlen' contains the length of the member name which + * may be up to 255 chars. The character string containing + * the name begins at '_ar_name.ar_name'. The terminating + * string AIAFMAG, is only cosmetic. File member contents begin + * at the first even byte boundary past 'header position + + * sizeof(struct ar_hdr) + ar_namlen', and continue for + * 'ar_size' bytes. +*/ + +#define AR_HDR struct ar_hdr +#define AR_HSZ sizeof(AR_HDR) + +#endif /* !__powerpc__ && Lynx */ + +#endif /* _AR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/assyntax.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/assyntax.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/assyntax.h (revision 51223) @@ -0,0 +1,753 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/assyntax.h,v 3.13 2003/08/24 17:37:03 dawes Exp $ */ + +#ifndef __ASSYNTAX_H__ +#define __ASSYNTAX_H__ + +/* + * Copyright 1992 Vrije Universiteit, The Netherlands + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the Vrije Universiteit not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The Vrije Universiteit makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * The Vrije Universiteit DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL The Vrije Universiteit BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 1993-1999 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: assyntax.h /main/5 1996/02/21 17:50:49 kaleb $ */ + + /* + * assyntax.h + * + * Select the syntax appropriate to the 386 assembler being used + * To add support for more assemblers add more columns to the CHOICE + * macro. Note that register names must also have uppercase names + * to avoid macro recursion. e.g., #define ah %ah recurses! + * + * NB 1. Some of the macros for certain assemblers imply that the code is to + * run in protected mode!! Caveat emptor. + * + * NB 2. 486 specific instructions are not included. This is to discourage + * their accidental use in code that is intended to run on 386 and 486 + * systems. + * + * Supported assemblers: + * + * (a) AT&T SysVr4 as(1): default + * (b) GNU Assembler gas: define USE_GAS or GNU_ASSEMBLER + * (c) Amsterdam Compiler kit: define ACK_ASSEMBLER + * + * The following naming conventions have been used to identify the various + * data types: + * _SR = segment register version + * Integer: + * _Q = quadword = 64 bits + * _L = long = 32 bits + * _W = short = 16 bits + * _B = byte = 8 bits + * Floating-point: + * _X = m80real = 80 bits + * _D = double = 64 bits + * _S = single = 32 bits + * + * Author: Gregory J. Sharp, Sept 1992 + * Vrije Universiteit, Amsterdam, The Netherlands + */ + +#if defined(USE_GAS) && !defined(GNU_ASSEMBLER) +#define GNU_ASSEMBLER +#endif + +#if (defined(__STDC__) && !defined(UNIXCPP)) || (defined (sun) && defined (i386) && defined (SVR4) && defined (__STDC__) && !defined (__GNUC__)) +#define CONCAT(x, y) x ## y +#else +#define CONCAT(x, y) x/**/y +#endif + +#ifdef ACK_ASSEMBLER + +/* Assume we write code for 32-bit protected mode! */ + +/* Redefine register names for GAS & AT&T assemblers */ +#define AL al +#define AH ah +#define AX ax +#define EAX ax +#define BL bl +#define BH bh +#define BX bx +#define EBX bx +#define CL cl +#define CH ch +#define CX cx +#define ECX cx +#define DL dl +#define DH dh +#define DX dx +#define EDX dx +#define BP bp +#define EBP bp +#define SI si +#define ESI si +#define DI di +#define EDI di +#define SP sp +#define ESP sp +#define CS cs +#define SS ss +#define DS ds +#define ES es +#define FS fs +#define GS gs +/* Control Registers */ +#define CR0 cr0 +#define CR1 cr1 +#define CR2 cr2 +#define CR3 cr3 +/* Debug Registers */ +#define DR0 dr0 +#define DR1 dr1 +#define DR2 dr2 +#define DR3 dr3 +#define DR4 dr4 +#define DR5 dr5 +#define DR6 dr6 +#define DR7 dr7 +/* Floating-point Stack */ +#define ST st + +#define AS_BEGIN .sect .text; .sect .rom; .sect .data; .sect .bss; .sect .text + + +#define _WTOG o16 /* word toggle for _W instructions */ +#define _LTOG /* long toggle for _L instructions */ +#define ADDR_TOGGLE a16 +#define OPSZ_TOGGLE o16 +#define USE16 .use16 +#define USE32 .use32 + +#define CHOICE(a,b,c) c + +#else /* AT&T or GAS */ + +/* Redefine register names for GAS & AT&T assemblers */ +#define AL %al +#define AH %ah +#define AX %ax +#define EAX %eax +#define BL %bl +#define BH %bh +#define BX %bx +#define EBX %ebx +#define CL %cl +#define CH %ch +#define CX %cx +#define ECX %ecx +#define DL %dl +#define DH %dh +#define DX %dx +#define EDX %edx +#define BP %bp +#define EBP %ebp +#define SI %si +#define ESI %esi +#define DI %di +#define EDI %edi +#define SP %sp +#define ESP %esp +#define CS %cs +#define SS %ss +#define DS %ds +#define ES %es +#define FS %fs +#define GS %gs +/* Control Registers */ +#define CR0 %cr0 +#define CR1 %cr1 +#define CR2 %cr2 +#define CR3 %cr3 +/* Debug Registers */ +#define DR0 %db0 +#define DR1 %db1 +#define DR2 %db2 +#define DR3 %db3 +#define DR4 %db4 +#define DR5 %db5 +#define DR6 %db6 +#define DR7 %db7 +/* Floating-point Stack */ +#define ST %st + +#define AS_BEGIN +#define USE16 +#define USE32 + +#ifdef GNU_ASSEMBLER + +#define ADDR_TOGGLE aword +#define OPSZ_TOGGLE word + +#define CHOICE(a,b,c) b + +#else +/* + * AT&T ASSEMBLER SYNTAX + * ********************* + */ +#define CHOICE(a,b,c) a + +#define ADDR_TOGGLE addr16 +#define OPSZ_TOGGLE data16 + +#endif /* GNU_ASSEMBLER */ +#endif /* ACK_ASSEMBLER */ + + +#if defined(__QNX__) || defined(Lynx) || (defined(SYSV) || defined(SVR4)) && !defined(ACK_ASSEMBLER) || defined(__ELF__) || defined(__GNU__) +#define GLNAME(a) a +#else +#define GLNAME(a) CONCAT(_,a) +#endif + + + /****************************************/ + /* */ + /* Select the various choices */ + /* */ + /****************************************/ + + +/* Redefine assembler directives */ +/*********************************/ +#define GLOBL CHOICE(.globl, .globl, .extern) +#define ALIGNTEXT4 CHOICE(.align 4, .align ARG2(2,0x90), .align 4) +#define ALIGNTEXT2 CHOICE(.align 2, .align ARG2(1,0x90), .align 2) +/* ALIGNTEXT4ifNOP is the same as ALIGNTEXT4, but only if the space is + * guaranteed to be filled with NOPs. Otherwise it does nothing. + */ +#define ALIGNTEXT4ifNOP CHOICE(.align 4, .align ARG2(2,0x90), /*can't do it*/) +#define ALIGNDATA4 CHOICE(.align 4, .align ARG2(2,0x0), .align 4) +#define ALIGNDATA2 CHOICE(.align 2, .align ARG2(1,0x0), .align 2) +#define FILE(s) CHOICE(.file s, .file s, .file s) +#define STRING(s) CHOICE(.string s, .asciz s, .asciz s) +#define D_LONG CHOICE(.long, .long, .data4) +#define D_WORD CHOICE(.value, .short, .data2) +#define D_BYTE CHOICE(.byte, .byte, .data1) +#define SPACE CHOICE(.comm, .space, .space) +#define COMM CHOICE(.comm, .comm, .comm) +#define SEG_DATA CHOICE(.data, .data, .sect .data) +#define SEG_TEXT CHOICE(.text, .text, .sect .text) +#define SEG_BSS CHOICE(.bss, .bss, .sect .bss) + +#ifdef GNU_ASSEMBLER +#define D_SPACE(n) . = . + n +#else +#define D_SPACE(n) .space n +#endif + +/* Addressing Modes */ +/* Immediate Mode */ +#define ADDR(a) CHOICE(CONCAT($,a), CONCAT($,a), a) +#define CONST(a) CHOICE(CONCAT($,a), CONCAT($,a), a) + +/* Indirect Mode */ +#define CONTENT(a) CHOICE(a, a, (a)) /* take contents of variable */ +#define REGIND(a) CHOICE((a), (a), (a)) /* Register a indirect */ +/* Register b indirect plus displacement a */ +#define REGOFF(a, b) CHOICE(a(b), a(b), a(b)) +/* Reg indirect Base + Index + Displacement - this is mainly for 16-bit mode + * which has no scaling + */ +#define REGBID(b,i,d) CHOICE(d(b,i), d(b,i), d(b)(i)) +/* Reg indirect Base + (Index * Scale) + Displacement */ +#define REGBISD(b,i,s,d) CHOICE(d(b,i,s), d(b,i,s), d(b)(i*s)) +/* Displaced Scaled Index: */ +#define REGDIS(d,i,s) CHOICE(d(,i,s), d(,i,s), d(i * s)) +/* Indexed Base: */ +#define REGBI(b,i) CHOICE((b,i), (b,i), (b)(i)) +/* Displaced Base: */ +#define REGDB(d,b) CHOICE(d(b), d(b), d(b)) +/* Variable indirect: */ +#define VARINDIRECT(var) CHOICE(*var, *var, (var)) +/* Use register contents as jump/call target: */ +#define CODEPTR(reg) CHOICE(*reg, *reg, reg) + +/* For expressions requiring bracketing + * eg. (CRT0_PM | CRT_EM) + */ + +#define EXPR(a) CHOICE([a], (a), [a]) +#define ENOT(a) CHOICE(0!a, ~a, ~a) +#define EMUL(a,b) CHOICE(a\*b, a*b, a*b) +#define EDIV(a,b) CHOICE(a\/b, a/b, a/b) + +/* + * We have to beat the problem of commas within arguments to choice. + * eg. choice (add a,b, add b,a) will get argument mismatch. Luckily ANSI + * and other known cpp definitions evaluate arguments before substitution + * so the following works. + */ +#define ARG2(a, b) a,b +#define ARG3(a,b,c) a,b,c + +/* Redefine assembler commands */ +#define AAA CHOICE(aaa, aaa, aaa) +#define AAD CHOICE(aad, aad, aad) +#define AAM CHOICE(aam, aam, aam) +#define AAS CHOICE(aas, aas, aas) +#define ADC_L(a, b) CHOICE(adcl ARG2(a,b), adcl ARG2(a,b), _LTOG adc ARG2(b,a)) +#define ADC_W(a, b) CHOICE(adcw ARG2(a,b), adcw ARG2(a,b), _WTOG adc ARG2(b,a)) +#define ADC_B(a, b) CHOICE(adcb ARG2(a,b), adcb ARG2(a,b), adcb ARG2(b,a)) +#define ADD_L(a, b) CHOICE(addl ARG2(a,b), addl ARG2(a,b), _LTOG add ARG2(b,a)) +#define ADD_W(a, b) CHOICE(addw ARG2(a,b), addw ARG2(a,b), _WTOG add ARG2(b,a)) +#define ADD_B(a, b) CHOICE(addb ARG2(a,b), addb ARG2(a,b), addb ARG2(b,a)) +#define AND_L(a, b) CHOICE(andl ARG2(a,b), andl ARG2(a,b), _LTOG and ARG2(b,a)) +#define AND_W(a, b) CHOICE(andw ARG2(a,b), andw ARG2(a,b), _WTOG and ARG2(b,a)) +#define AND_B(a, b) CHOICE(andb ARG2(a,b), andb ARG2(a,b), andb ARG2(b,a)) +#define ARPL(a,b) CHOICE(arpl ARG2(a,b), arpl ARG2(a,b), arpl ARG2(b,a)) +#define BOUND_L(a, b) CHOICE(boundl ARG2(a,b), boundl ARG2(b,a), _LTOG bound ARG2(b,a)) +#define BOUND_W(a, b) CHOICE(boundw ARG2(a,b), boundw ARG2(b,a), _WTOG bound ARG2(b,a)) +#define BSF_L(a, b) CHOICE(bsfl ARG2(a,b), bsfl ARG2(a,b), _LTOG bsf ARG2(b,a)) +#define BSF_W(a, b) CHOICE(bsfw ARG2(a,b), bsfw ARG2(a,b), _WTOG bsf ARG2(b,a)) +#define BSR_L(a, b) CHOICE(bsrl ARG2(a,b), bsrl ARG2(a,b), _LTOG bsr ARG2(b,a)) +#define BSR_W(a, b) CHOICE(bsrw ARG2(a,b), bsrw ARG2(a,b), _WTOG bsr ARG2(b,a)) +#define BT_L(a, b) CHOICE(btl ARG2(a,b), btl ARG2(a,b), _LTOG bt ARG2(b,a)) +#define BT_W(a, b) CHOICE(btw ARG2(a,b), btw ARG2(a,b), _WTOG bt ARG2(b,a)) +#define BTC_L(a, b) CHOICE(btcl ARG2(a,b), btcl ARG2(a,b), _LTOG btc ARG2(b,a)) +#define BTC_W(a, b) CHOICE(btcw ARG2(a,b), btcw ARG2(a,b), _WTOG btc ARG2(b,a)) +#define BTR_L(a, b) CHOICE(btrl ARG2(a,b), btrl ARG2(a,b), _LTOG btr ARG2(b,a)) +#define BTR_W(a, b) CHOICE(btrw ARG2(a,b), btrw ARG2(a,b), _WTOG btr ARG2(b,a)) +#define BTS_L(a, b) CHOICE(btsl ARG2(a,b), btsl ARG2(a,b), _LTOG bts ARG2(b,a)) +#define BTS_W(a, b) CHOICE(btsw ARG2(a,b), btsw ARG2(a,b), _WTOG bts ARG2(b,a)) +#define CALL(a) CHOICE(call a, call a, call a) +#define CALLF(s,a) CHOICE(lcall ARG2(s,a), lcall ARG2(s,a), callf s:a) +#define CBW CHOICE(cbtw, cbw, cbw) +#define CWDE CHOICE(cwtd, cwde, cwde) +#define CLC CHOICE(clc, clc, clc) +#define CLD CHOICE(cld, cld, cld) +#define CLI CHOICE(cli, cli, cli) +#define CLTS CHOICE(clts, clts, clts) +#define CMC CHOICE(cmc, cmc, cmc) +#define CMP_L(a, b) CHOICE(cmpl ARG2(a,b), cmpl ARG2(a,b), _LTOG cmp ARG2(b,a)) +#define CMP_W(a, b) CHOICE(cmpw ARG2(a,b), cmpw ARG2(a,b), _WTOG cmp ARG2(b,a)) +#define CMP_B(a, b) CHOICE(cmpb ARG2(a,b), cmpb ARG2(a,b), cmpb ARG2(b,a)) +#define CMPS_L CHOICE(cmpsl, cmpsl, _LTOG cmps) +#define CMPS_W CHOICE(cmpsw, cmpsw, _WTOG cmps) +#define CMPS_B CHOICE(cmpsb, cmpsb, cmpsb) +#define CWD CHOICE(cwtl, cwd, cwd) +#define CDQ CHOICE(cltd, cdq, cdq) +#define DAA CHOICE(daa, daa, daa) +#define DAS CHOICE(das, das, das) +#define DEC_L(a) CHOICE(decl a, decl a, _LTOG dec a) +#define DEC_W(a) CHOICE(decw a, decw a, _WTOG dec a) +#define DEC_B(a) CHOICE(decb a, decb a, decb a) +#define DIV_L(a) CHOICE(divl a, divl a, div a) +#define DIV_W(a) CHOICE(divw a, divw a, div a) +#define DIV_B(a) CHOICE(divb a, divb a, divb a) +#define ENTER(a,b) CHOICE(enter ARG2(a,b), enter ARG2(a,b), enter ARG2(b,a)) +#define HLT CHOICE(hlt, hlt, hlt) +#define IDIV_L(a) CHOICE(idivl a, idivl a, _LTOG idiv a) +#define IDIV_W(a) CHOICE(idivw a, idivw a, _WTOG idiv a) +#define IDIV_B(a) CHOICE(idivb a, idivb a, idivb a) +/* More forms than this for imul!! */ +#define IMUL_L(a, b) CHOICE(imull ARG2(a,b), imull ARG2(a,b), _LTOG imul ARG2(b,a)) +#define IMUL_W(a, b) CHOICE(imulw ARG2(a,b), imulw ARG2(a,b), _WTOG imul ARG2(b,a)) +#define IMUL_B(a) CHOICE(imulb a, imulb a, imulb a) +#define IN_L CHOICE(inl (DX), inl ARG2(DX,EAX), _LTOG in DX) +#define IN_W CHOICE(inw (DX), inw ARG2(DX,AX), _WTOG in DX) +#define IN_B CHOICE(inb (DX), inb ARG2(DX,AL), inb DX) +/* Please AS code writer: use the following ONLY, if you refer to ports<256 + * directly, but not in IN1_W(DX), for instance, even if IN1_ looks nicer + */ +#if defined (sun) +#define IN1_L(a) CHOICE(inl (a), inl ARG2(a,EAX), _LTOG in a) +#define IN1_W(a) CHOICE(inw (a), inw ARG2(a,AX), _WTOG in a) +#define IN1_B(a) CHOICE(inb (a), inb ARG2(a,AL), inb a) +#else +#define IN1_L(a) CHOICE(inl a, inl ARG2(a,EAX), _LTOG in a) +#define IN1_W(a) CHOICE(inw a, inw ARG2(a,AX), _WTOG in a) +#define IN1_B(a) CHOICE(inb a, inb ARG2(a,AL), inb a) +#endif +#define INC_L(a) CHOICE(incl a, incl a, _LTOG inc a) +#define INC_W(a) CHOICE(incw a, incw a, _WTOG inc a) +#define INC_B(a) CHOICE(incb a, incb a, incb a) +#define INS_L CHOICE(insl, insl, _LTOG ins) +#define INS_W CHOICE(insw, insw, _WTOG ins) +#define INS_B CHOICE(insb, insb, insb) +#define INT(a) CHOICE(int a, int a, int a) +#define INT3 CHOICE(int CONST(3), int3, int CONST(3)) +#define INTO CHOICE(into, into, into) +#define IRET CHOICE(iret, iret, iret) +#define IRETD CHOICE(iret, iret, iretd) +#define JA(a) CHOICE(ja a, ja a, ja a) +#define JAE(a) CHOICE(jae a, jae a, jae a) +#define JB(a) CHOICE(jb a, jb a, jb a) +#define JBE(a) CHOICE(jbe a, jbe a, jbe a) +#define JC(a) CHOICE(jc a, jc a, jc a) +#define JE(a) CHOICE(je a, je a, je a) +#define JG(a) CHOICE(jg a, jg a, jg a) +#define JGE(a) CHOICE(jge a, jge a, jge a) +#define JL(a) CHOICE(jl a, jl a, jl a) +#define JLE(a) CHOICE(jle a, jle a, jle a) +#define JNA(a) CHOICE(jna a, jna a, jna a) +#define JNAE(a) CHOICE(jnae a, jnae a, jnae a) +#define JNB(a) CHOICE(jnb a, jnb a, jnb a) +#define JNBE(a) CHOICE(jnbe a, jnbe a, jnbe a) +#define JNC(a) CHOICE(jnc a, jnc a, jnc a) +#define JNE(a) CHOICE(jne a, jne a, jne a) +#define JNG(a) CHOICE(jng a, jng a, jng a) +#define JNGE(a) CHOICE(jnge a, jnge a, jnge a) +#define JNL(a) CHOICE(jnl a, jnl a, jnl a) +#define JNLE(a) CHOICE(jnle a, jnle a, jnle a) +#define JNO(a) CHOICE(jno a, jno a, jno a) +#define JNP(a) CHOICE(jnp a, jnp a, jnp a) +#define JNS(a) CHOICE(jns a, jns a, jns a) +#define JNZ(a) CHOICE(jnz a, jnz a, jnz a) +#define JO(a) CHOICE(jo a, jo a, jo a) +#define JP(a) CHOICE(jp a, jp a, jp a) +#define JPE(a) CHOICE(jpe a, jpe a, jpe a) +#define JPO(a) CHOICE(jpo a, jpo a, jpo a) +#define JS(a) CHOICE(js a, js a, js a) +#define JZ(a) CHOICE(jz a, jz a, jz a) +#define JMP(a) CHOICE(jmp a, jmp a, jmp a) +#define JMPF(s,a) CHOICE(ljmp ARG2(s,a), ljmp ARG2(s,a), jmpf s:a) +#define LAHF CHOICE(lahf, lahf, lahf) +#if !defined(_REAL_MODE) && !defined(_V86_MODE) +#define LAR(a, b) CHOICE(lar ARG2(a, b), lar ARG2(a, b), lar ARG2(b, a)) +#endif +#define LEA_L(a, b) CHOICE(leal ARG2(a,b), leal ARG2(a,b), _LTOG lea ARG2(b,a)) +#define LEA_W(a, b) CHOICE(leaw ARG2(a,b), leaw ARG2(a,b), _WTOG lea ARG2(b,a)) +#define LEAVE CHOICE(leave, leave, leave) +#define LGDT(a) CHOICE(lgdt a, lgdt a, lgdt a) +#define LIDT(a) CHOICE(lidt a, lidt a, lidt a) +#define LDS(a, b) CHOICE(ldsl ARG2(a,b), lds ARG2(a,b), lds ARG2(b,a)) +#define LES(a, b) CHOICE(lesl ARG2(a,b), les ARG2(a,b), les ARG2(b,a)) +#define LFS(a, b) CHOICE(lfsl ARG2(a,b), lfs ARG2(a,b), lfs ARG2(b,a)) +#define LGS(a, b) CHOICE(lgsl ARG2(a,b), lgs ARG2(a,b), lgs ARG2(b,a)) +#define LSS(a, b) CHOICE(lssl ARG2(a,b), lss ARG2(a,b), lss ARG2(b,a)) +#define LLDT(a) CHOICE(lldt a, lldt a, lldt a) +#define LMSW(a) CHOICE(lmsw a, lmsw a, lmsw a) +#define LOCK CHOICE(lock, lock, lock) +#define LODS_L CHOICE(lodsl, lodsl, _LTOG lods) +#define LODS_W CHOICE(lodsw, lodsw, _WTOG lods) +#define LODS_B CHOICE(lodsb, lodsb, lodsb) +#define LOOP(a) CHOICE(loop a, loop a, loop a) +#define LOOPE(a) CHOICE(loope a, loope a, loope a) +#define LOOPZ(a) CHOICE(loopz a, loopz a, loopz a) +#define LOOPNE(a) CHOICE(loopne a, loopne a, loopne a) +#define LOOPNZ(a) CHOICE(loopnz a, loopnz a, loopnz a) +#if !defined(_REAL_MODE) && !defined(_V86_MODE) +#define LSL(a, b) CHOICE(lsl ARG2(a,b), lsl ARG2(a,b), lsl ARG2(b,a)) +#endif +#define LTR(a) CHOICE(ltr a, ltr a, ltr a) +#define MOV_SR(a, b) CHOICE(movw ARG2(a,b), mov ARG2(a,b), mov ARG2(b,a)) +#define MOV_L(a, b) CHOICE(movl ARG2(a,b), movl ARG2(a,b), _LTOG mov ARG2(b,a)) +#define MOV_W(a, b) CHOICE(movw ARG2(a,b), movw ARG2(a,b), _WTOG mov ARG2(b,a)) +#define MOV_B(a, b) CHOICE(movb ARG2(a,b), movb ARG2(a,b), movb ARG2(b,a)) +#define MOVS_L CHOICE(movsl, movsl, _LTOG movs) +#define MOVS_W CHOICE(movsw, movsw, _WTOG movs) +#define MOVS_B CHOICE(movsb, movsb, movsb) +#define MOVSX_BL(a, b) CHOICE(movsbl ARG2(a,b), movsbl ARG2(a,b), movsx ARG2(b,a)) +#define MOVSX_BW(a, b) CHOICE(movsbw ARG2(a,b), movsbw ARG2(a,b), movsx ARG2(b,a)) +#define MOVSX_WL(a, b) CHOICE(movswl ARG2(a,b), movswl ARG2(a,b), movsx ARG2(b,a)) +#define MOVZX_BL(a, b) CHOICE(movzbl ARG2(a,b), movzbl ARG2(a,b), movzx ARG2(b,a)) +#define MOVZX_BW(a, b) CHOICE(movzbw ARG2(a,b), movzbw ARG2(a,b), movzx ARG2(b,a)) +#define MOVZX_WL(a, b) CHOICE(movzwl ARG2(a,b), movzwl ARG2(a,b), movzx ARG2(b,a)) +#define MUL_L(a) CHOICE(mull a, mull a, _LTOG mul a) +#define MUL_W(a) CHOICE(mulw a, mulw a, _WTOG mul a) +#define MUL_B(a) CHOICE(mulb a, mulb a, mulb a) +#define NEG_L(a) CHOICE(negl a, negl a, _LTOG neg a) +#define NEG_W(a) CHOICE(negw a, negw a, _WTOG neg a) +#define NEG_B(a) CHOICE(negb a, negb a, negb a) +#define NOP CHOICE(nop, nop, nop) +#define NOT_L(a) CHOICE(notl a, notl a, _LTOG not a) +#define NOT_W(a) CHOICE(notw a, notw a, _WTOG not a) +#define NOT_B(a) CHOICE(notb a, notb a, notb a) +#define OR_L(a,b) CHOICE(orl ARG2(a,b), orl ARG2(a,b), _LTOG or ARG2(b,a)) +#define OR_W(a,b) CHOICE(orw ARG2(a,b), orw ARG2(a,b), _WTOG or ARG2(b,a)) +#define OR_B(a,b) CHOICE(orb ARG2(a,b), orb ARG2(a,b), orb ARG2(b,a)) +#define OUT_L CHOICE(outl (DX), outl ARG2(EAX,DX), _LTOG out DX) +#define OUT_W CHOICE(outw (DX), outw ARG2(AX,DX), _WTOG out DX) +#define OUT_B CHOICE(outb (DX), outb ARG2(AL,DX), outb DX) +/* Please AS code writer: use the following ONLY, if you refer to ports<256 + * directly, but not in OUT1_W(DX), for instance, even if OUT1_ looks nicer + */ +#define OUT1_L(a) CHOICE(outl (a), outl ARG2(EAX,a), _LTOG out a) +#define OUT1_W(a) CHOICE(outw (a), outw ARG2(AX,a), _WTOG out a) +#define OUT1_B(a) CHOICE(outb (a), outb ARG2(AL,a), outb a) +#define OUTS_L CHOICE(outsl, outsl, _LTOG outs) +#define OUTS_W CHOICE(outsw, outsw, _WTOG outs) +#define OUTS_B CHOICE(outsb, outsb, outsb) +#define POP_SR(a) CHOICE(pop a, pop a, pop a) +#define POP_L(a) CHOICE(popl a, popl a, _LTOG pop a) +#define POP_W(a) CHOICE(popw a, popw a, _WTOG pop a) +#define POPA_L CHOICE(popal, popal, _LTOG popa) +#define POPA_W CHOICE(popaw, popaw, _WTOG popa) +#define POPF_L CHOICE(popfl, popfl, _LTOG popf) +#define POPF_W CHOICE(popfw, popfw, _WTOG popf) +#define PUSH_SR(a) CHOICE(push a, push a, push a) +#define PUSH_L(a) CHOICE(pushl a, pushl a, _LTOG push a) +#define PUSH_W(a) CHOICE(pushw a, pushw a, _WTOG push a) +#define PUSH_B(a) CHOICE(push a, pushb a, push a) +#define PUSHA_L CHOICE(pushal, pushal, _LTOG pusha) +#define PUSHA_W CHOICE(pushaw, pushaw, _WTOG pusha) +#define PUSHF_L CHOICE(pushfl, pushfl, _LTOG pushf) +#define PUSHF_W CHOICE(pushfw, pushfw, _WTOG pushf) +#define RCL_L(a, b) CHOICE(rcll ARG2(a,b), rcll ARG2(a,b), _LTOG rcl ARG2(b,a)) +#define RCL_W(a, b) CHOICE(rclw ARG2(a,b), rclw ARG2(a,b), _WTOG rcl ARG2(b,a)) +#define RCL_B(a, b) CHOICE(rclb ARG2(a,b), rclb ARG2(a,b), rclb ARG2(b,a)) +#define RCR_L(a, b) CHOICE(rcrl ARG2(a,b), rcrl ARG2(a,b), _LTOG rcr ARG2(b,a)) +#define RCR_W(a, b) CHOICE(rcrw ARG2(a,b), rcrw ARG2(a,b), _WTOG rcr ARG2(b,a)) +#define RCR_B(a, b) CHOICE(rcrb ARG2(a,b), rcrb ARG2(a,b), rcrb ARG2(b,a)) +#define ROL_L(a, b) CHOICE(roll ARG2(a,b), roll ARG2(a,b), _LTOG rol ARG2(b,a)) +#define ROL_W(a, b) CHOICE(rolw ARG2(a,b), rolw ARG2(a,b), _WTOG rol ARG2(b,a)) +#define ROL_B(a, b) CHOICE(rolb ARG2(a,b), rolb ARG2(a,b), rolb ARG2(b,a)) +#define ROR_L(a, b) CHOICE(rorl ARG2(a,b), rorl ARG2(a,b), _LTOG ror ARG2(b,a)) +#define ROR_W(a, b) CHOICE(rorw ARG2(a,b), rorw ARG2(a,b), _WTOG ror ARG2(b,a)) +#define ROR_B(a, b) CHOICE(rorb ARG2(a,b), rorb ARG2(a,b), rorb ARG2(b,a)) +#define REP CHOICE(rep ;, rep ;, repe) +#define REPE CHOICE(repz ;, repe ;, repe) +#define REPNE CHOICE(repnz ;, repne ;, repne) +#define REPNZ REPNE +#define REPZ REPE +#define RET CHOICE(ret, ret, ret) +#define SAHF CHOICE(sahf, sahf, sahf) +#define SAL_L(a, b) CHOICE(sall ARG2(a,b), sall ARG2(a,b), _LTOG sal ARG2(b,a)) +#define SAL_W(a, b) CHOICE(salw ARG2(a,b), salw ARG2(a,b), _WTOG sal ARG2(b,a)) +#define SAL_B(a, b) CHOICE(salb ARG2(a,b), salb ARG2(a,b), salb ARG2(b,a)) +#define SAR_L(a, b) CHOICE(sarl ARG2(a,b), sarl ARG2(a,b), _LTOG sar ARG2(b,a)) +#define SAR_W(a, b) CHOICE(sarw ARG2(a,b), sarw ARG2(a,b), _WTOG sar ARG2(b,a)) +#define SAR_B(a, b) CHOICE(sarb ARG2(a,b), sarb ARG2(a,b), sarb ARG2(b,a)) +#define SBB_L(a, b) CHOICE(sbbl ARG2(a,b), sbbl ARG2(a,b), _LTOG sbb ARG2(b,a)) +#define SBB_W(a, b) CHOICE(sbbw ARG2(a,b), sbbw ARG2(a,b), _WTOG sbb ARG2(b,a)) +#define SBB_B(a, b) CHOICE(sbbb ARG2(a,b), sbbb ARG2(a,b), sbbb ARG2(b,a)) +#define SCAS_L CHOICE(scasl, scasl, _LTOG scas) +#define SCAS_W CHOICE(scasw, scasw, _WTOG scas) +#define SCAS_B CHOICE(scasb, scasb, scasb) +#define SETA(a) CHOICE(seta a, seta a, seta a) +#define SETAE(a) CHOICE(setae a, setae a, setae a) +#define SETB(a) CHOICE(setb a, setb a, setb a) +#define SETBE(a) CHOICE(setbe a, setbe a, setbe a) +#define SETC(a) CHOICE(setc a, setb a, setb a) +#define SETE(a) CHOICE(sete a, sete a, sete a) +#define SETG(a) CHOICE(setg a, setg a, setg a) +#define SETGE(a) CHOICE(setge a, setge a, setge a) +#define SETL(a) CHOICE(setl a, setl a, setl a) +#define SETLE(a) CHOICE(setle a, setle a, setle a) +#define SETNA(a) CHOICE(setna a, setna a, setna a) +#define SETNAE(a) CHOICE(setnae a, setnae a, setnae a) +#define SETNB(a) CHOICE(setnb a, setnb a, setnb a) +#define SETNBE(a) CHOICE(setnbe a, setnbe a, setnbe a) +#define SETNC(a) CHOICE(setnc a, setnb a, setnb a) +#define SETNE(a) CHOICE(setne a, setne a, setne a) +#define SETNG(a) CHOICE(setng a, setng a, setng a) +#define SETNGE(a) CHOICE(setnge a, setnge a, setnge a) +#define SETNL(a) CHOICE(setnl a, setnl a, setnl a) +#define SETNLE(a) CHOICE(setnle a, setnle a, setnle a) +#define SETNO(a) CHOICE(setno a, setno a, setno a) +#define SETNP(a) CHOICE(setnp a, setnp a, setnp a) +#define SETNS(a) CHOICE(setns a, setns a, setna a) +#define SETNZ(a) CHOICE(setnz a, setnz a, setnz a) +#define SETO(a) CHOICE(seto a, seto a, seto a) +#define SETP(a) CHOICE(setp a, setp a, setp a) +#define SETPE(a) CHOICE(setpe a, setpe a, setpe a) +#define SETPO(a) CHOICE(setpo a, setpo a, setpo a) +#define SETS(a) CHOICE(sets a, sets a, seta a) +#define SETZ(a) CHOICE(setz a, setz a, setz a) +#define SGDT(a) CHOICE(sgdt a, sgdt a, sgdt a) +#define SIDT(a) CHOICE(sidt a, sidt a, sidt a) +#define SHL_L(a, b) CHOICE(shll ARG2(a,b), shll ARG2(a,b), _LTOG shl ARG2(b,a)) +#define SHL_W(a, b) CHOICE(shlw ARG2(a,b), shlw ARG2(a,b), _WTOG shl ARG2(b,a)) +#define SHL_B(a, b) CHOICE(shlb ARG2(a,b), shlb ARG2(a,b), shlb ARG2(b,a)) +#define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a)) +#define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL)) +#define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a)) +#define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL)) +#define SHR_L(a, b) CHOICE(shrl ARG2(a,b), shrl ARG2(a,b), _LTOG shr ARG2(b,a)) +#define SHR_W(a, b) CHOICE(shrw ARG2(a,b), shrw ARG2(a,b), _WTOG shr ARG2(b,a)) +#define SHR_B(a, b) CHOICE(shrb ARG2(a,b), shrb ARG2(a,b), shrb ARG2(b,a)) +#define SHRD_L(a,b,c) CHOICE(shrdl ARG3(a,b,c), shrdl ARG3(a,b,c), _LTOG shrd ARG3(c,b,a)) +#define SHRD2_L(a,b) CHOICE(shrdl ARG2(a,b), shrdl ARG3(CL,a,b), _LTOG shrd ARG3(b,a,CL)) +#define SHRD_W(a,b,c) CHOICE(shrdw ARG3(a,b,c), shrdw ARG3(a,b,c), _WTOG shrd ARG3(c,b,a)) +#define SHRD2_W(a,b) CHOICE(shrdw ARG2(a,b), shrdw ARG3(CL,a,b), _WTOG shrd ARG3(b,a,CL)) +#define SLDT(a) CHOICE(sldt a, sldt a, sldt a) +#define SMSW(a) CHOICE(smsw a, smsw a, smsw a) +#define STC CHOICE(stc, stc, stc) +#define STD CHOICE(std, std, std) +#define STI CHOICE(sti, sti, sti) +#define STOS_L CHOICE(stosl, stosl, _LTOG stos) +#define STOS_W CHOICE(stosw, stosw, _WTOG stos) +#define STOS_B CHOICE(stosb, stosb, stosb) +#define STR(a) CHOICE(str a, str a, str a) +#define SUB_L(a, b) CHOICE(subl ARG2(a,b), subl ARG2(a,b), _LTOG sub ARG2(b,a)) +#define SUB_W(a, b) CHOICE(subw ARG2(a,b), subw ARG2(a,b), _WTOG sub ARG2(b,a)) +#define SUB_B(a, b) CHOICE(subb ARG2(a,b), subb ARG2(a,b), subb ARG2(b,a)) +#define TEST_L(a, b) CHOICE(testl ARG2(a,b), testl ARG2(a,b), _LTOG test ARG2(b,a)) +#define TEST_W(a, b) CHOICE(testw ARG2(a,b), testw ARG2(a,b), _WTOG test ARG2(b,a)) +#define TEST_B(a, b) CHOICE(testb ARG2(a,b), testb ARG2(a,b), testb ARG2(b,a)) +#define VERR(a) CHOICE(verr a, verr a, verr a) +#define VERW(a) CHOICE(verw a, verw a, verw a) +#define WAIT CHOICE(wait, wait, wait) +#define XCHG_L(a, b) CHOICE(xchgl ARG2(a,b), xchgl ARG2(a,b), _LTOG xchg ARG2(b,a)) +#define XCHG_W(a, b) CHOICE(xchgw ARG2(a,b), xchgw ARG2(a,b), _WTOG xchg ARG2(b,a)) +#define XCHG_B(a, b) CHOICE(xchgb ARG2(a,b), xchgb ARG2(a,b), xchgb ARG2(b,a)) +#define XLAT CHOICE(xlat, xlat, xlat) +#define XOR_L(a, b) CHOICE(xorl ARG2(a,b), xorl ARG2(a,b), _LTOG xor ARG2(b,a)) +#define XOR_W(a, b) CHOICE(xorw ARG2(a,b), xorw ARG2(a,b), _WTOG xor ARG2(b,a)) +#define XOR_B(a, b) CHOICE(xorb ARG2(a,b), xorb ARG2(a,b), xorb ARG2(b,a)) + + +/* Floating Point Instructions */ +#define F2XM1 CHOICE(f2xm1, f2xm1, f2xm1) +#define FABS CHOICE(fabs, fabs, fabs) +#define FADD_D(a) CHOICE(faddl a, faddl a, faddd a) +#define FADD_S(a) CHOICE(fadds a, fadds a, fadds a) +#define FADD2(a, b) CHOICE(fadd ARG2(a,b), fadd ARG2(a,b), fadd ARG2(b,a)) +#define FADDP(a, b) CHOICE(faddp ARG2(a,b), faddp ARG2(a,b), faddp ARG2(b,a)) +#define FIADD_L(a) CHOICE(fiaddl a, fiaddl a, fiaddl a) +#define FIADD_W(a) CHOICE(fiadd a, fiadds a, fiadds a) +#define FBLD(a) CHOICE(fbld a, fbld a, fbld a) +#define FBSTP(a) CHOICE(fbstp a, fbstp a, fbstp a) +#define FCHS CHOICE(fchs, fchs, fchs) +#define FCLEX CHOICE(fclex, wait; fnclex, wait; fclex) +#define FNCLEX CHOICE(fnclex, fnclex, fclex) +#define FCOM(a) CHOICE(fcom a, fcom a, fcom a) +#define FCOM_D(a) CHOICE(fcoml a, fcoml a, fcomd a) +#define FCOM_S(a) CHOICE(fcoms a, fcoms a, fcoms a) +#define FCOMP(a) CHOICE(fcomp a, fcomp a, fcomp a) +#define FCOMP_D(a) CHOICE(fcompl a, fcompl a, fcompd a) +#define FCOMP_S(a) CHOICE(fcomps a, fcomps a, fcomps a) +#define FCOMPP CHOICE(fcompp, fcompp, fcompp) +#define FCOS CHOICE(fcos, fcos, fcos) +#define FDECSTP CHOICE(fdecstp, fdecstp, fdecstp) +#define FDIV_D(a) CHOICE(fdivl a, fdivl a, fdivd a) +#define FDIV_S(a) CHOICE(fdivs a, fdivs a, fdivs a) +#define FDIV2(a, b) CHOICE(fdiv ARG2(a,b), fdiv ARG2(a,b), fdiv ARG2(b,a)) +#define FDIVP(a, b) CHOICE(fdivp ARG2(a,b), fdivp ARG2(a,b), fdivp ARG2(b,a)) +#define FIDIV_L(a) CHOICE(fidivl a, fidivl a, fidivl a) +#define FIDIV_W(a) CHOICE(fidiv a, fidivs a, fidivs a) +#define FDIVR_D(a) CHOICE(fdivrl a, fdivrl a, fdivrd a) +#define FDIVR_S(a) CHOICE(fdivrs a, fdivrs a, fdivrs a) +#define FDIVR2(a, b) CHOICE(fdivr ARG2(a,b), fdivr ARG2(a,b), fdivr ARG2(b,a)) +#define FDIVRP(a, b) CHOICE(fdivrp ARG2(a,b), fdivrp ARG2(a,b), fdivrp ARG2(b,a)) +#define FIDIVR_L(a) CHOICE(fidivrl a, fidivrl a, fidivrl a) +#define FIDIVR_W(a) CHOICE(fidivr a, fidivrs a, fidivrs a) +#define FFREE(a) CHOICE(ffree a, ffree a, ffree a) +#define FICOM_L(a) CHOICE(ficoml a, ficoml a, ficoml a) +#define FICOM_W(a) CHOICE(ficom a, ficoms a, ficoms a) +#define FICOMP_L(a) CHOICE(ficompl a, ficompl a, ficompl a) +#define FICOMP_W(a) CHOICE(ficomp a, ficomps a, ficomps a) +#define FILD_Q(a) CHOICE(fildll a, fildq a, fildq a) +#define FILD_L(a) CHOICE(fildl a, fildl a, fildl a) +#define FILD_W(a) CHOICE(fild a, filds a, filds a) +#define FINCSTP CHOICE(fincstp, fincstp, fincstp) +#define FINIT CHOICE(finit, wait; fninit, wait; finit) +#define FNINIT CHOICE(fninit, fninit, finit) +#define FIST_L(a) CHOICE(fistl a, fistl a, fistl a) +#define FIST_W(a) CHOICE(fist a, fists a, fists a) +#define FISTP_Q(a) CHOICE(fistpll a, fistpq a, fistpq a) +#define FISTP_L(a) CHOICE(fistpl a, fistpl a, fistpl a) +#define FISTP_W(a) CHOICE(fistp a, fistps a, fistps a) +#define FLD_X(a) CHOICE(fldt a, fldt a, fldx a) /* 80 bit data type! */ +#define FLD_D(a) CHOICE(fldl a, fldl a, fldd a) +#define FLD_S(a) CHOICE(flds a, flds a, flds a) +#define FLD1 CHOICE(fld1, fld1, fld1) +#define FLDL2T CHOICE(fldl2t, fldl2t, fldl2t) +#define FLDL2E CHOICE(fldl2e, fldl2e, fldl2e) +#define FLDPI CHOICE(fldpi, fldpi, fldpi) +#define FLDLG2 CHOICE(fldlg2, fldlg2, fldlg2) +#define FLDLN2 CHOICE(fldln2, fldln2, fldln2) +#define FLDZ CHOICE(fldz, fldz, fldz) +#define FLDCW(a) CHOICE(fldcw a, fldcw a, fldcw a) +#define FLDENV(a) CHOICE(fldenv a, fldenv a, fldenv a) +#define FMUL_S(a) CHOICE(fmuls a, fmuls a, fmuls a) +#define FMUL_D(a) CHOICE(fmull a, fmull a, fmuld a) +#define FMUL2(a, b) CHOICE(fmul ARG2(a,b), fmul ARG2(a,b), fmul ARG2(b,a)) +#define FMULP(a, b) CHOICE(fmulp ARG2(a,b), fmulp ARG2(a,b), fmulp ARG2(b,a)) +#define FIMUL_L(a) CHOICE(fimull a, fimull a, fimull a) +#define FIMUL_W(a) CHOICE(fimul a, fimuls a, fimuls a) +#define FNOP CHOICE(fnop, fnop, fnop) +#define FPATAN CHOICE(fpatan, fpatan, fpatan) +#define FPREM CHOICE(fprem, fprem, fprem) +#define FPREM1 CHOICE(fprem1, fprem1, fprem1) +#define FPTAN CHOICE(fptan, fptan, fptan) +#define FRNDINT CHOICE(frndint, frndint, frndint) +#define FRSTOR(a) CHOICE(frstor a, frstor a, frstor a) +#define FSAVE(a) CHOICE(fsave a, wait; fnsave a, wait; fsave a) +#define FNSAVE(a) CHOICE(fnsave a, fnsave a, fsave a) +#define FSCALE CHOICE(fscale, fscale, fscale) +#define FSIN CHOICE(fsin, fsin, fsin) +#define FSINCOS CHOICE(fsincos, fsincos, fsincos) +#define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) +#define FST_D(a) CHOICE(fstl a, fstl a, fstd a) +#define FST_S(a) CHOICE(fsts a, fsts a, fsts a) +#define FSTP_X(a) CHOICE(fstpt a, fstpt a, fstpx a) +#define FSTP_D(a) CHOICE(fstpl a, fstpl a, fstpd a) +#define FSTP_S(a) CHOICE(fstps a, fstps a, fstps a) +#define FSTCW(a) CHOICE(fstcw a, wait; fnstcw a, wait; fstcw a) +#define FNSTCW(a) CHOICE(fnstcw a, fnstcw a, fstcw a) +#define FSTENV(a) CHOICE(fstenv a, wait; fnstenv a, fstenv a) +#define FNSTENV(a) CHOICE(fnstenv a, fnstenv a, fstenv a) +#define FSTSW(a) CHOICE(fstsw a, wait; fnstsw a, wait; fstsw a) +#define FNSTSW(a) CHOICE(fnstsw a, fnstsw a, fstsw a) +#define FSUB_S(a) CHOICE(fsubs a, fsubs a, fsubs a) +#define FSUB_D(a) CHOICE(fsubl a, fsubl a, fsubd a) +#define FSUB2(a, b) CHOICE(fsub ARG2(a,b), fsub ARG2(a,b), fsub ARG2(b,a)) +#define FSUBP(a, b) CHOICE(fsubp ARG2(a,b), fsubp ARG2(a,b), fsubp ARG2(b,a)) +#define FISUB_L(a) CHOICE(fisubl a, fisubl a, fisubl a) +#define FISUB_W(a) CHOICE(fisub a, fisubs a, fisubs a) +#define FSUBR_S(a) CHOICE(fsubrs a, fsubrs a, fsubrs a) +#define FSUBR_D(a) CHOICE(fsubrl a, fsubrl a, fsubrd a) +#define FSUBR2(a, b) CHOICE(fsubr ARG2(a,b), fsubr ARG2(a,b), fsubr ARG2(b,a)) +#define FSUBRP(a, b) CHOICE(fsubrp ARG2(a,b), fsubrp ARG2(a,b), fsubrp ARG2(b,a)) +#define FISUBR_L(a) CHOICE(fisubrl a, fisubrl a, fisubrl a) +#define FISUBR_W(a) CHOICE(fisubr a, fisubrs a, fisubrs a) +#define FTST CHOICE(ftst, ftst, ftst) +#define FUCOM(a) CHOICE(fucom a, fucom a, fucom a) +#define FUCOMP(a) CHOICE(fucomp a, fucomp a, fucomp a) +#define FUCOMPP CHOICE(fucompp, fucompp, fucompp) +#define FWAIT CHOICE(wait, wait, wait) +#define FXAM CHOICE(fxam, fxam, fxam) +#define FXCH(a) CHOICE(fxch a, fxch a, fxch a) +#define FXTRACT CHOICE(fxtract, fxtract, fxtract) +#define FYL2X CHOICE(fyl2x, fyl2x, fyl2x) +#define FYL2XP1 CHOICE(fyl2xp1, fyl2xp1, fyl2xp1) + +#endif /* __ASSYNTAX_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/atKeynames.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/atKeynames.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/atKeynames.h (revision 51223) @@ -0,0 +1,298 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/atKeynames.h,v 3.21 2003/10/09 11:43:59 pascal Exp $ */ +/* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Thomas Roell makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: atKeynames.h /main/11 1996/03/09 11:17:41 kaleb $ */ + +#ifndef _ATKEYNAMES_H +#define _ATKEYNAMES_H + +#define XK_TECHNICAL +#define XK_KATAKANA +#include +#include + +#define GLYPHS_PER_KEY 4 +#define NUM_KEYCODES 248 +#define MIN_KEYCODE 8 +#define MAX_KEYCODE (NUM_KEYCODES + MIN_KEYCODE - 1) + +#define AltMask Mod1Mask +#define NumLockMask Mod2Mask +#define AltLangMask Mod3Mask +#define KanaMask Mod4Mask +#define ScrollLockMask Mod5Mask + +#define KeyPressed(k) (keyc->down[k >> 3] & (1 << (k & 7))) +#define ModifierDown(k) ((keyc->state & (k)) == (k)) + +/* + * NOTE: The AT/MF keyboards can generate (via the 8042) two (MF: three) + * sets of scancodes. Set3 can only be generated by a MF keyboard. + * Set2 sends a makecode for keypress, and the same code prefixed by a + * F0 for keyrelease. This is a little bit ugly to handle. Thus we use + * here for X386 the PC/XT compatible Set1. This set uses 8bit scancodes. + * Bit 7 ist set if the key is released. The code E0 switches to a + * different meaning to add the new MF cursorkeys, while not breaking old + * applications. E1 is another special prefix. Since I assume that there + * will be further versions of PC/XT scancode compatible keyboards, we + * may be in trouble one day. + * + * IDEA: 1) Use Set2 on AT84 keyboards and translate it to MF Set3. + * 2) Use the keyboards native set and translate it to common keysyms. + */ + +/* + * definition of the AT84/MF101/MF102 Keyboard: + * ============================================================ + * Defined Key Cap Glyphs Pressed value + * Key Name Main Also (hex) (dec) + * ---------------- ---------- ------- ------ ------ + */ + +#define KEY_Escape /* Escape 0x01 */ 1 +#define KEY_1 /* 1 ! 0x02 */ 2 +#define KEY_2 /* 2 @ 0x03 */ 3 +#define KEY_3 /* 3 # 0x04 */ 4 +#define KEY_4 /* 4 $ 0x05 */ 5 +#define KEY_5 /* 5 % 0x06 */ 6 +#define KEY_6 /* 6 ^ 0x07 */ 7 +#define KEY_7 /* 7 & 0x08 */ 8 +#define KEY_8 /* 8 * 0x09 */ 9 +#define KEY_9 /* 9 ( 0x0a */ 10 +#define KEY_0 /* 0 ) 0x0b */ 11 +#define KEY_Minus /* - (Minus) _ (Under) 0x0c */ 12 +#define KEY_Equal /* = (Equal) + 0x0d */ 13 +#define KEY_BackSpace /* Back Space 0x0e */ 14 +#define KEY_Tab /* Tab 0x0f */ 15 +#define KEY_Q /* Q 0x10 */ 16 +#define KEY_W /* W 0x11 */ 17 +#define KEY_E /* E 0x12 */ 18 +#define KEY_R /* R 0x13 */ 19 +#define KEY_T /* T 0x14 */ 20 +#define KEY_Y /* Y 0x15 */ 21 +#define KEY_U /* U 0x16 */ 22 +#define KEY_I /* I 0x17 */ 23 +#define KEY_O /* O 0x18 */ 24 +#define KEY_P /* P 0x19 */ 25 +#define KEY_LBrace /* [ { 0x1a */ 26 +#define KEY_RBrace /* ] } 0x1b */ 27 +#define KEY_Enter /* Enter 0x1c */ 28 +#define KEY_LCtrl /* Ctrl(left) 0x1d */ 29 +#define KEY_A /* A 0x1e */ 30 +#define KEY_S /* S 0x1f */ 31 +#define KEY_D /* D 0x20 */ 32 +#define KEY_F /* F 0x21 */ 33 +#define KEY_G /* G 0x22 */ 34 +#define KEY_H /* H 0x23 */ 35 +#define KEY_J /* J 0x24 */ 36 +#define KEY_K /* K 0x25 */ 37 +#define KEY_L /* L 0x26 */ 38 +#define KEY_SemiColon /* ;(SemiColon) :(Colon) 0x27 */ 39 +#define KEY_Quote /* ' (Apostr) " (Quote) 0x28 */ 40 +#define KEY_Tilde /* ` (Accent) ~ (Tilde) 0x29 */ 41 +#define KEY_ShiftL /* Shift(left) 0x2a */ 42 +#define KEY_BSlash /* \(BckSlash) |(VertBar)0x2b */ 43 +#define KEY_Z /* Z 0x2c */ 44 +#define KEY_X /* X 0x2d */ 45 +#define KEY_C /* C 0x2e */ 46 +#define KEY_V /* V 0x2f */ 47 +#define KEY_B /* B 0x30 */ 48 +#define KEY_N /* N 0x31 */ 49 +#define KEY_M /* M 0x32 */ 50 +#define KEY_Comma /* , (Comma) < (Less) 0x33 */ 51 +#define KEY_Period /* . (Period) >(Greater)0x34 */ 52 +#define KEY_Slash /* / (Slash) ? 0x35 */ 53 +#define KEY_ShiftR /* Shift(right) 0x36 */ 54 +#define KEY_KP_Multiply /* * 0x37 */ 55 +#define KEY_Alt /* Alt(left) 0x38 */ 56 +#define KEY_Space /* (SpaceBar) 0x39 */ 57 +#define KEY_CapsLock /* CapsLock 0x3a */ 58 +#define KEY_F1 /* F1 0x3b */ 59 +#define KEY_F2 /* F2 0x3c */ 60 +#define KEY_F3 /* F3 0x3d */ 61 +#define KEY_F4 /* F4 0x3e */ 62 +#define KEY_F5 /* F5 0x3f */ 63 +#define KEY_F6 /* F6 0x40 */ 64 +#define KEY_F7 /* F7 0x41 */ 65 +#define KEY_F8 /* F8 0x42 */ 66 +#define KEY_F9 /* F9 0x43 */ 67 +#define KEY_F10 /* F10 0x44 */ 68 +#define KEY_NumLock /* NumLock 0x45 */ 69 +#define KEY_ScrollLock /* ScrollLock 0x46 */ 70 +#define KEY_KP_7 /* 7 Home 0x47 */ 71 +#define KEY_KP_8 /* 8 Up 0x48 */ 72 +#define KEY_KP_9 /* 9 PgUp 0x49 */ 73 +#define KEY_KP_Minus /* - (Minus) 0x4a */ 74 +#define KEY_KP_4 /* 4 Left 0x4b */ 75 +#define KEY_KP_5 /* 5 0x4c */ 76 +#define KEY_KP_6 /* 6 Right 0x4d */ 77 +#define KEY_KP_Plus /* + (Plus) 0x4e */ 78 +#define KEY_KP_1 /* 1 End 0x4f */ 79 +#define KEY_KP_2 /* 2 Down 0x50 */ 80 +#define KEY_KP_3 /* 3 PgDown 0x51 */ 81 +#define KEY_KP_0 /* 0 Insert 0x52 */ 82 +#define KEY_KP_Decimal /* . (Decimal) Delete 0x53 */ 83 +#define KEY_SysReqest /* SysReqest 0x54 */ 84 + /* NOTUSED 0x55 */ +#define KEY_Less /* < (Less) >(Greater) 0x56 */ 86 +#define KEY_F11 /* F11 0x57 */ 87 +#define KEY_F12 /* F12 0x58 */ 88 + +#define KEY_Prefix0 /* special 0x60 */ 96 +#define KEY_Prefix1 /* specail 0x61 */ 97 + +/* + * The 'scancodes' below are generated by the server, because the MF101/102 + * keyboard sends them as sequence of other scancodes + */ +#define KEY_Home /* Home 0x59 */ 89 +#define KEY_Up /* Up 0x5a */ 90 +#define KEY_PgUp /* PgUp 0x5b */ 91 +#define KEY_Left /* Left 0x5c */ 92 +#define KEY_Begin /* Begin 0x5d */ 93 +#define KEY_Right /* Right 0x5e */ 94 +#define KEY_End /* End 0x5f */ 95 +#define KEY_Down /* Down 0x60 */ 96 +#define KEY_PgDown /* PgDown 0x61 */ 97 +#define KEY_Insert /* Insert 0x62 */ 98 +#define KEY_Delete /* Delete 0x63 */ 99 +#define KEY_KP_Enter /* Enter 0x64 */ 100 +#define KEY_RCtrl /* Ctrl(right) 0x65 */ 101 +#define KEY_Pause /* Pause 0x66 */ 102 +#define KEY_Print /* Print 0x67 */ 103 +#define KEY_KP_Divide /* Divide 0x68 */ 104 +#define KEY_AltLang /* AtlLang(right) 0x69 */ 105 +#define KEY_Break /* Break 0x6a */ 106 +#define KEY_LMeta /* Left Meta 0x6b */ 107 +#define KEY_RMeta /* Right Meta 0x6c */ 108 +#define KEY_Menu /* Menu 0x6d */ 109 +#define KEY_F13 /* F13 0x6e */ 110 +#define KEY_F14 /* F14 0x6f */ 111 +#define KEY_F15 /* F15 0x70 */ 112 +#define KEY_HKTG /* Hirugana/Katakana tog 0x70 */ 112 +#define KEY_F16 /* F16 0x71 */ 113 +#define KEY_F17 /* F17 0x72 */ 114 +#define KEY_KP_DEC /* KP_DEC 0x73 */ 115 +#define KEY_BSlash2 /* \ _ 0x73 */ 115 +#define KEY_KP_Equal /* Equal (Keypad) 0x76 */ 118 +#define KEY_XFER /* Kanji Transfer 0x79 */ 121 +#define KEY_NFER /* No Kanji Transfer 0x7b */ 123 +#define KEY_Yen /* Yen 0x7d */ 125 + +#define KEY_Power /* Power Key 0x84 */ 132 +#define KEY_Mute /* Audio Mute 0x85 */ 133 +#define KEY_AudioLower /* Audio Lower 0x86 */ 134 +#define KEY_AudioRaise /* Audio Raise 0x87 */ 135 +#define KEY_Help /* Help 0x88 */ 136 +#define KEY_L1 /* Stop 0x89 */ 137 +#define KEY_L2 /* Again 0x8a */ 138 +#define KEY_L3 /* Props 0x8b */ 139 +#define KEY_L4 /* Undo 0x8c */ 140 +#define KEY_L5 /* Front 0x8d */ 141 +#define KEY_L6 /* Copy 0x8e */ 142 +#define KEY_L7 /* Open 0x8f */ 143 +#define KEY_L8 /* Paste 0x90 */ 144 +#define KEY_L9 /* Find 0x91 */ 145 +#define KEY_L10 /* Cut 0x92 */ 146 + +/* + * Fake 'scancodes' in the following ranges are generated for 2-byte + * codes not handled elsewhere. These correspond to most extended keys + * on so-called "Internet" keyboards: + * + * 0x79-0x93 + * 0x96-0xa1 + * 0xa3-0xac + * 0xb1-0xb4 + * 0xba-0xbd + * 0xc2 + * 0xcc-0xd2 + * 0xd6-0xf7 + */ + +/* + * Remapped 'scancodes' are generated for single-byte codes in the range + * 0x59-0x5f,0x62-0x76. These are used for some extra keys on some keyboards. + */ + +#define KEY_0x59 0x95 +#define KEY_0x5A 0xA2 +#define KEY_0x5B 0xAD +#define KEY_0x5C KEY_KP_EQUAL +#define KEY_0x5D 0xAE +#define KEY_0x5E 0xAF +#define KEY_0x5F 0xB0 +#define KEY_0x62 0xB5 +#define KEY_0x63 0xB6 +#define KEY_0x64 0xB7 +#define KEY_0x65 0xB8 +#define KEY_0x66 0xB9 +#define KEY_0x67 0xBE +#define KEY_0x68 0xBF +#define KEY_0x69 0xC0 +#define KEY_0x6A 0xC1 +#define KEY_0x6B 0xC3 +#define KEY_0x6C 0xC4 +#define KEY_0x6D 0xC5 +#define KEY_0x6E 0xC6 +#define KEY_0x6F 0xC7 +#define KEY_0x70 0xC8 +#define KEY_0x71 0xC9 +#define KEY_0x72 0xCA +#define KEY_0x73 0xCB +#define KEY_0x74 0xD3 +#define KEY_0x75 0xD4 +#define KEY_0x76 0xD5 + +/* These are for "notused" and "unknown" entries in translation maps. */ +#define KEY_NOTUSED 0 +#define KEY_UNKNOWN 255 + +#endif /* _ATKEYNAMES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/attributes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/attributes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/attributes.h (revision 51223) @@ -0,0 +1,131 @@ +/* $Xorg: attributes.h,v 1.4 2001/03/14 18:42:44 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_attributes_h +#define _Xp_attributes_h 1 + +#include "scrnintstr.h" +#include "AttrValid.h" + +#define BFuncArgs int ndx, ScreenPtr pScreen, int argc, char **argv +typedef Bool (*pBFunc)(BFuncArgs); + +#define VFuncArgs char *name, XpValidatePoolsRec *pValRec, float *width, float *height, int *res +typedef void (*pVFunc)(VFuncArgs); + +/* + * attributes.c + */ +void XpInitAttributes(XpContextPtr pContext); +void XpBuildAttributeStore(char *printerName, + char *qualifierName); +void XpAddPrinterAttribute(char *printerName, + char *printerQualifier, + char *attributeName, + char *attributeValue); +void XpDestroyAttributes(XpContextPtr pContext); +char *XpGetConfigDir(Bool useLocale); +char *XpGetOneAttribute(XpContextPtr pContext, + XPAttributes class, + char *attributeName); +void XpPutOneAttribute(XpContextPtr pContext, + XPAttributes class, + const char* attributeName, + const char* value); +int XpRehashAttributes(void); +char *XpGetAttributes(XpContextPtr pContext, + XPAttributes class); +int XpAugmentAttributes(XpContextPtr pContext, + XPAttributes class, + char *attributes); +int XpSetAttributes(XpContextPtr pContext, + XPAttributes class, + char *attributes); +const char *XpGetPrinterAttribute(const char *printerName, + const char *attribute); +void XpGetTrayMediumFromContext(XpContextPtr pCon, + char **medium, + char **tray); +int XpSubmitJob(char *fileName, XpContextPtr pContext); + +/* + * mediaSizes.c + */ +int XpGetResolution(XpContextPtr pContext); +XpOid XpGetContentOrientation(XpContextPtr pContext); +XpOid XpGetAvailableCompression(XpContextPtr pContext); +XpOid XpGetPlex(XpContextPtr pContext); +XpOid XpGetPageSize(XpContextPtr pContext, + XpOid* pTray, + const XpOidMediumSS* msss); +void XpGetMediumMillimeters(XpOid page_size, + float *width, + float *height); +void XpGetMediumDimensions(XpContextPtr pContext, + unsigned short *width, + unsigned short *height); +void XpGetReproductionArea(XpContextPtr pContext, + xRectangle *pRect); +void XpGetMaxWidthHeightRes(const char *printer_name, + const XpValidatePoolsRec* vpr, + float *width, + float *height, + int* resolution); + +/* Util.c */ +char *ReplaceAnyString(char *string, + char *target, + char *replacement); +char *ReplaceFileString(char *string, + char *inFileName, + char *outFileName); +int TransferBytes(FILE *pSrcFile, + FILE *pDstFile, + int numBytes); +Bool CopyContentsAndDelete(FILE **ppSrcFile, + char **pSrcFileName, + FILE *pDstFile); +int XpSendDocumentData(ClientPtr client, + FILE *fp, + int fileLen, + int maxBufSize); +int XpFinishDocData(ClientPtr client); +Bool XpOpenTmpFile(char *mode, + char **fname, + FILE **stream); + +#endif /* _Xp_attributes_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bsd_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bsd_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bsd_kbd.h (revision 51223) @@ -0,0 +1,5 @@ +/* $XFree86$ */ + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstore.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstore.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstore.h (revision 51223) @@ -0,0 +1,23 @@ +/* $XFree86: xc/programs/Xserver/include/bstore.h,v 1.1 1998/04/05 16:44:25 robin Exp $*/ +/* + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies. The University of + * California makes no representations about the suitability of this software + * for any purpose. It is provided "as is" without express or implied + * warranty. + */ + +/* + * Moved here from mi to allow wrapping of lower level backing store functions. + * -- 1997.10.27 Marc Aurele La France (tsi@xfree86.org) + */ + +#ifndef _BSTORE_H_ +#define _BSTORE_H_ + +#include "bstorestr.h" + +#endif /* _BSTORE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstorestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstorestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bstorestr.h (revision 51223) @@ -0,0 +1,58 @@ +/* $XFree86: xc/programs/Xserver/include/bstorestr.h,v 1.2 2001/01/06 20:58:12 tsi Exp $*/ +/* + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies. The University of + * California makes no representations about the suitability of this software + * for any purpose. It is provided "as is" without express or implied + * warranty. + */ + +/* + * Moved here from mi to allow wrapping of lower level backing store functions. + * -- 1997.10.27 Marc Aurele La France (tsi@xfree86.org) + */ + +#ifndef _BSTORESTR_H_ +#define _BSTORESTR_H_ + +#include "gc.h" +#include "pixmap.h" +#include "region.h" +#include "window.h" + +typedef void (* BackingStoreSaveAreasProcPtr)( + PixmapPtr /*pBackingPixmap*/, + RegionPtr /*pObscured*/, + int /*x*/, + int /*y*/, + WindowPtr /*pWin*/); + +typedef void (* BackingStoreRestoreAreasProcPtr)( + PixmapPtr /*pBackingPixmap*/, + RegionPtr /*pExposed*/, + int /*x*/, + int /*y*/, + WindowPtr /*pWin*/); + +typedef void (* BackingStoreSetClipmaskRgnProcPtr)( + GCPtr /*pBackingGC*/, + RegionPtr /*pbackingCompositeClip*/); + +typedef PixmapPtr (* BackingStoreGetImagePixmapProcPtr)(void); + +typedef PixmapPtr (* BackingStoreGetSpansPixmapProcPtr)(void); + +typedef struct _BSFuncs { + + BackingStoreSaveAreasProcPtr SaveAreas; + BackingStoreRestoreAreasProcPtr RestoreAreas; + BackingStoreSetClipmaskRgnProcPtr SetClipmaskRgn; + BackingStoreGetImagePixmapProcPtr GetImagePixmap; + BackingStoreGetSpansPixmapProcPtr GetSpansPixmap; + +} BSFuncRec, *BSFuncPtr; + +#endif /* _BSTORESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bt829.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bt829.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/bt829.h (revision 51223) @@ -0,0 +1,115 @@ +#ifndef __BT829_H__ +#define __BT829_H__ + +#include "xf86i2c.h" + +typedef struct { + int tunertype; /* Must be set before init */ + /* Private variables */ + I2CDevRec d; + + CARD8 brightness; + CARD8 ccmode; + CARD8 code; + CARD16 contrast; + CARD8 format; + int height; + CARD8 hue; + CARD8 len; + CARD8 mux; + CARD8 out_en; + CARD8 p_io; + CARD16 sat_u; + CARD16 sat_v; + CARD8 vbien; + CARD8 vbifmt; + int width; + + CARD16 hdelay; + CARD16 hscale; + CARD16 vactive; + CARD16 vdelay; + CARD16 vscale; + + CARD16 htotal; + CARD8 id; + CARD8 svideo_mux; +} BT829Rec, *BT829Ptr; + +BT829Ptr bt829_Detect(I2CBusPtr b, I2CSlaveAddr addr); + +/* ATI card specific initialization */ +#define BT829_ATI_ADDR_1 0x8A +#define BT829_ATI_ADDR_2 0x88 +int bt829_ATIInit(BT829Ptr bt); + +#define BT829_NTSC 1 /* NTSC-M */ +#define BT829_NTSC_JAPAN 2 /* NTSC-Japan */ +#define BT829_PAL 3 /* PAL-B,D,G,H,I */ +#define BT829_PAL_M 4 /* PAL-M */ +#define BT829_PAL_N 5 /* PAL-N */ +#define BT829_SECAM 6 /* SECAM */ +#define BT829_PAL_N_COMB 7 /* PAL-N combination */ +int bt829_SetFormat(BT829Ptr bt, CARD8 format); + +#define BT829_MUX2 1 /* ATI -> composite video */ +#define BT829_MUX0 2 /* ATI -> tv tuner */ +#define BT829_MUX1 3 /* ATI -> s-video */ +int bt829_SetMux(BT829Ptr bt, CARD8 mux); + +int bt829_SetCaptSize(BT829Ptr bt, int width, int height); + +void bt829_SetBrightness(BT829Ptr bt, int brightness); +void bt829_SetContrast(BT829Ptr bt, int contrast); +void bt829_SetSaturation(BT829Ptr bt, int saturation); +void bt829_SetTint(BT829Ptr bt, int hue); /* Hue */ + +void bt829_SetOUT_EN(BT829Ptr bt, BOOL out_en); /* VPOLE register */ +void bt829_SetP_IO(BT829Ptr bt, CARD8 p_io); /* P_IO register */ + +int bt829_SetCC(BT829Ptr bt); + +#define BT829SymbolsList \ + "bt829_Detect", \ + "bt829_ATIInit", \ + "bt829_SetFormat", \ + "bt829_SetMux", \ + "bt829_SetBrightness", \ + "bt829_SetContrast", \ + "bt829_SetSaturation", \ + "bt829_SetTint", \ + "bt829_SetCaptSize", \ + "bt829_SetOUT_EN", \ + "bt829_SetP_IO" + +#ifdef XFree86LOADER + +#define xf86_bt829_Detect ((BT829Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("bt829_Detect")) +#define xf86_bt829_ATIInit ((int (*)(BT829Ptr))LoaderSymbol("bt829_ATIInit")) +#define xf86_bt829_SetFormat ((int (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetFormat")) +#define xf86_bt829_SetMux ((int (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetMux")) +#define xf86_bt829_SetCaptSize ((int (*)(BT829Ptr, int, int))LoaderSymbol("bt829_SetCaptSize")) +#define xf86_bt829_SetBrightness ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetBrightness")) +#define xf86_bt829_SetContrast ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetContrast")) +#define xf86_bt829_SetSaturation ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetSaturation")) +#define xf86_bt829_SetTint ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetTint")) +#define xf86_bt829_SetOUT_EN ((void (*)(BT829Ptr, Bool))LoaderSymbol("bt829_SetOUT_EN")) +#define xf86_bt829_SetP_IO ((void (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetP_IO")) + +#else + +#define xf86_bt829_Detect bt829_Detect +#define xf86_bt829_ATIInit bt829_ATIInit +#define xf86_bt829_SetFormat bt829_SetFormat +#define xf86_bt829_SetMux bt829_SetMux +#define xf86_bt829_SetCaptSize bt829_SetCaptSize +#define xf86_bt829_SetBrightness bt829_SetBrightness +#define xf86_bt829_SetContrast bt829_SetContrast +#define xf86_bt829_SetSaturation bt829_SetSaturation +#define xf86_bt829_SetTint bt829_SetTint +#define xf86_bt829_SetOUT_EN bt829_SetOUT_EN +#define xf86_bt829_SetP_IO bt829_SetP_IO + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/card-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/card-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/card-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +#include "config.h" + +#ifndef _xf86cfg_card_h +#define _xf86cfg_card_h + +/* + * Prototypes + */ +XtPointer CardConfig(XtPointer); +void CardModel(XF86SetupInfo*); +void CardFilterAction(Widget, XEvent*, String*, Cardinal*); + +#endif /* _xf86cfg_card_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cards.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cards.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cards.h (revision 51223) @@ -0,0 +1,38 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.h,v 3.4 1999/03/28 15:33:07 dawes Exp $ */ + + + + + +/* $XConsortium: cards.h /main/3 1996/02/21 18:12:53 kaleb $ */ + +#ifndef CARD_DATABASE_FILE +#define CARD_DATABASE_FILE "Cards" +#endif + +#define MAX_CARDS 1000 + +typedef struct { + char *name; /* Name of the card. */ + char *chipset; /* Chipset (decriptive). */ + char *server; /* Server identifier. */ + char *driver; /* Driver identifier. */ + char *ramdac; /* Ramdac identifier. */ + char *clockchip; /* Clockchip identifier. */ + char *dacspeed; /* DAC speed rating. */ + int flags; + char *lines; /* Additional Device section lines. */ +} Card; + +/* Flags: */ +#define NOCLOCKPROBE 0x1 /* Never probe clocks of the card. */ +#define UNSUPPORTED 0x2 /* Card is not supported (only VGA). */ + +extern int lastcard; + +extern Card card[MAX_CARDS]; + +extern int lookupcard ( char *name ); +extern int parse_database ( void ); +extern void sort_database ( void ); +extern void keypress ( void ); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb.h (revision 51223) @@ -0,0 +1,1327 @@ +/* $Xorg: cfb.h,v 1.3 2000/08/17 19:48:12 cpqbld Exp $ */ +/************************************************************ +Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright no- +tice appear in all copies and that both that copyright no- +tice and this permission notice appear in supporting docu- +mentation, and that the names of Sun or The Open Group +not be used in advertising or publicity pertaining to +distribution of the software without specific prior +written permission. Sun and The Open Group make no +representations about the suitability of this software for +any purpose. It is provided "as is" without any express or +implied warranty. + +SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- +NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI- +ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/cfb/cfb.h,v 3.29tsi Exp $ */ + +#if !defined(__CFB_H__) || defined(CFB_PROTOTYPES_ONLY) + +#include +#include "globals.h" +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "servermd.h" +#include "windowstr.h" +#include "mfb.h" +#undef PixelType + +#include "cfbmap.h" + +#ifndef CfbBits +#define CfbBits CARD32 +#endif + +#ifndef CFB_PROTOTYPES_ONLY +#define __CFB_H__ +/* + private filed of pixmap + pixmap.devPrivate = (unsigned int *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes +*/ + +extern int cfbGCPrivateIndex; +extern int cfbWindowPrivateIndex; + +/* private field of GC */ +typedef struct { + unsigned char rop; /* special case rop values */ + /* next two values unused in cfb, included for compatibility with mfb */ + unsigned char ropOpStip; /* rop for opaque stipple */ + /* this value is ropFillArea in mfb, usurped for cfb */ + unsigned char oneRect; /* drawable has one clip rect */ + CfbBits xor, and; /* reduced rop values */ + } cfbPrivGC; + +typedef cfbPrivGC *cfbPrivGCPtr; + +#define cfbGetGCPrivate(pGC) ((cfbPrivGCPtr)\ + (pGC)->devPrivates[cfbGCPrivateIndex].ptr) + +#define cfbGetCompositeClip(pGC) ((pGC)->pCompositeClip) + +/* way to carry RROP info around */ +typedef struct { + unsigned char rop; + CfbBits xor, and; +} cfbRRopRec, *cfbRRopPtr; + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; + } cfbPrivWin; + +#define cfbGetWindowPrivate(_pWin) ((cfbPrivWin *)\ + (_pWin)->devPrivates[cfbWindowPrivateIndex].ptr) + + +/* cfb8bit.c */ + +extern int cfbSetStipple( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*planemask*/ +); + +extern int cfbSetOpaqueStipple( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*bg*/, + CfbBits /*planemask*/ +); + +extern int cfbComputeClipMasks32( + BoxPtr /*pBox*/, + int /*numRects*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + CARD32 * /*clips*/ +); +#endif /* !CFB_PROTOTYPES_ONLY */ +/* cfb8cppl.c */ + +extern void cfbCopyImagePlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbCopyPlane8to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane16to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane24to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane32to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); +#endif + +/* cfb8lineCO.c */ + +extern int cfb8LineSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8LineSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void cfb8ClippedLineCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8lineCP.c */ + +extern int cfb8LineSS1RectPreviousCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); +/* cfb8lineG.c */ + +extern int cfb8LineSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8ClippedLineGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8lineX.c */ + +extern int cfb8LineSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8ClippedLineXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8segC.c */ + +extern int cfb8SegmentSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfb8segCS.c */ + +extern int cfb8SegmentSS1RectShiftCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); + +extern void cfb8SegmentSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfb8segG.c */ + +extern int cfb8SegmentSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfbsegX.c */ + +extern int cfb8SegmentSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfballpriv.c */ + +extern Bool cfbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*window_index*/, + int * /*gc_index*/ +); +/* cfbbitblt.c */ + +extern RegionPtr cfbBitBlt( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (* /*doBitBlt*/)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ + ), + unsigned long /*bitPlane*/ +); + +#define cfbCopyPlaneExpand cfbBitBlt + +extern RegionPtr cfbCopyPlaneReduce( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (* /*doCopyPlane*/)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ /* We must know which plane to reduce! */ + ), + unsigned long /*bitPlane*/ +); + +extern void cfbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr cfbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbCopyPlane1to8( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +#endif + +extern RegionPtr cfbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/ +); +/* cfbbltC.c */ + +extern void cfbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltG.c */ + +extern void cfbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltO.c */ + +extern void cfbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltX.c */ + +extern void cfbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbres.c */ + +extern void cfbBresS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* cfbbresd.c */ + +extern void cfbBresD( + cfbRRopPtr /*rrops*/, + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* cfbbstore.c */ + +extern void cfbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void cfbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* cfbcmap.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern int cfbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void cfbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void cfbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void cfbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool cfbInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern int cfbExpandDirectColors( + ColormapPtr /*pmap*/, + int /*ndef*/, + xColorItem * /*indefs*/, + xColorItem * /*outdefs*/ +); + +extern Bool cfbCreateDefColormap( + ScreenPtr /*pScreen*/ +); + +extern Bool cfbSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +extern void cfbClearVisualTypes(void); + +extern Bool cfbInitVisuals( + VisualPtr * /*visualp*/, + DepthPtr * /*depthp*/, + int * /*nvisualp*/, + int * /*ndepthp*/, + int * /*rootDepthp*/, + VisualID * /*defaultVisp*/, + unsigned long /*sizes*/, + int /*bitsPerRGB*/ +); +#endif +/* cfbfillarcC.c */ + +extern void cfbPolyFillArcSolidCopy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbfillarcG.c */ + +extern void cfbPolyFillArcSolidGeneral( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbfillrct.c */ + +extern void cfbFillBoxTileOdd( + DrawablePtr /*pDrawable*/, + int /*n*/, + BoxPtr /*rects*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/ +); + +extern void cfbFillRectTileOdd( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); +/* cfbfillsp.c */ + +extern void cfbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void cfbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfb8Stipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void cfb8OpaqueStipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +#endif +/* cfbgc.c */ + +extern GCOpsPtr cfbMatchCommon( + GCPtr /*pGC*/, + cfbPrivGCPtr /*devPriv*/ +); + +extern Bool cfbCreateGC( + GCPtr /*pGC*/ +); + +extern void cfbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +/* cfbgetsp.c */ + +extern void cfbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* cfbglblt8.c */ + +extern void cfbPolyGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbglrop8.c */ + +extern void cfbPolyGlyphRop8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbhrzvert.c */ + +extern void cfbHorzS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); + +extern void cfbVertS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); +/* cfbigblt8.c */ + +extern void cfbImageGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbimage.c */ + +extern void cfbPutImage( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void cfbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* cfbline.c */ + +extern void cfbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void cfbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); +/* cfbmskbits.c */ +/* cfbpixmap.c */ + +extern PixmapPtr cfbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool cfbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr cfbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void cfbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void cfbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void cfbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void cfbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +/* cfbply1rctC.c */ + +extern void cfbFillPoly1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* cfbply1rctG.c */ + +extern void cfbFillPoly1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* cfbpntwin.c */ + +extern void cfbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); + +extern void cfbFillBoxSolid( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + unsigned long /*pixel*/ +); + +extern void cfbFillBoxTile32( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/ +); +/* cfbpolypnt.c */ + +extern void cfbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* cfbpush8.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbPushPixels8( + GCPtr /*pGC*/, + PixmapPtr /*pBitmap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* cfbrctstp8.c */ + +extern void cfb8FillRectOpaqueStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfb8FillRectTransparentStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfb8FillRectStippledUnnatural( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); +#endif +/* cfbrrop.c */ + +extern int cfbReduceRasterOp( + int /*rop*/, + CfbBits /*fg*/, + CfbBits /*pm*/, + CfbBits * /*andp*/, + CfbBits * /*xorp*/ +); +/* cfbscrinit.c */ + +extern Bool cfbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); + +extern Bool cfbSetupScreen( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern Bool cfbFinishScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern Bool cfbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr cfbGetScreenPixmap( + ScreenPtr /*pScreen*/ +); + +extern void cfbSetScreenPixmap( + PixmapPtr /*pPix*/ +); + +/* cfbseg.c */ + +extern void cfbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void cfbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* cfbsetsp.c */ + +extern void cfbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + unsigned int * /*psrc*/, + int /*alu*/, + int * /*pdstBase*/, + int /*widthDst*/, + unsigned long /*planemask*/ +); + +extern void cfbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* cfbsolidC.c */ + +extern void cfbFillRectSolidCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbsolidG.c */ + +extern void cfbFillRectSolidGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbsolidX.c */ + +extern void cfbFillRectSolidXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbteblt8.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbTEGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*xInit*/, + int /*yInit*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +#endif +/* cfbtegblt.c */ + +extern void cfbTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbtile32C.c */ + +extern void cfbFillRectTile32Copy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbTile32FSCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbtile32G.c */ + +extern void cfbFillRectTile32General( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbTile32FSGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbtileoddC.c */ + +extern void cfbFillBoxTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillBoxTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* cfbtileoddG.c */ + +extern void cfbFillBoxTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillBoxTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* cfbwindow.c */ + +extern Bool cfbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool cfbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool cfbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool cfbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool cfbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void cfbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool cfbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* cfbzerarcC.c */ + +extern void cfbZeroPolyArcSS8Copy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbzerarcG.c */ + +extern void cfbZeroPolyArcSS8General( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbzerarcX.c */ + +extern void cfbZeroPolyArcSS8Xor( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#if (!defined(SINGLEDEPTH) && PSZ != 8) || defined(FORCE_SEPARATE_PRIVATE) + +#define CFB_NEED_SCREEN_PRIVATE + +extern int cfbScreenPrivateIndex; +#endif + +#ifndef CFB_PROTOTYPES_ONLY + +/* Common macros for extracting drawing information */ + +#define cfbGetWindowPixmap(d) \ + ((* ((DrawablePtr)(d))->pScreen->GetWindowPixmap)((WindowPtr)(d))) + +#define cfbGetTypedWidth(pDrawable,wtype) (\ + (((pDrawable)->type != DRAWABLE_PIXMAP) ? \ + (int) (cfbGetWindowPixmap(pDrawable)->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define cfbGetByteWidth(pDrawable) cfbGetTypedWidth(pDrawable, unsigned char) + +#define cfbGetPixelWidth(pDrawable) cfbGetTypedWidth(pDrawable, PixelType) + +#define cfbGetLongWidth(pDrawable) cfbGetTypedWidth(pDrawable, CfbBits) + +#define cfbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) \ + _pPix = cfbGetWindowPixmap(pDrawable); \ + else \ + _pPix = (PixmapPtr) (pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define cfbGetByteWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define cfbGetLongWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, CfbBits, CfbBits) + +#define cfbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = cfbGetWindowPixmap((DrawablePtr) (pWin)); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define cfbGetWindowLongWidthAndPointer(pWin, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, CfbBits, CfbBits) + +#define cfbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, unsigned char, unsigned char) + +#define cfbGetWindowPixelWidthAndPointer(pDrawable, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +/* + * XFree86 empties the root BorderClip when the VT is inactive, + * here's a macro which uses that to disable GetImage and GetSpans + */ +#define cfbWindowEnabled(pWin) \ + REGION_NOTEMPTY((pWin)->drawable.pScreen, \ + &WindowTable[(pWin)->drawable.pScreen->myNum]->borderClip) + +#define cfbDrawableEnabled(pDrawable) \ + ((pDrawable)->type == DRAWABLE_PIXMAP ? \ + TRUE : cfbWindowEnabled((WindowPtr) pDrawable)) + +#include "micoord.h" + +/* + * if CFB is built as a module, it shouldn't call libc functions. + */ +#ifdef XFree86LOADER +#include "xf86_ansic.h" +#endif +#endif /* !CFB_PROTOTYPES_ONLY */ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb16.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb16.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb16.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb16.h,v 1.4 1998/11/28 10:42:50 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef _CFB16_H_ +#define _CFB16_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 16 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB16_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb24.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb24.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb24.h (revision 51223) @@ -0,0 +1,98 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb24.h,v 1.4 1998/11/28 10:42:51 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _CFB24_H_ +#define _CFB24_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 24 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB24_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb32.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb32.h,v 1.4 1998/11/28 10:42:51 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef _CFB32_H_ +#define _CFB32_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 32 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB32_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_16.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_16.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_16.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf8_16bpp/cfb8_16.h,v 1.1 1999/01/31 12:22:16 dawes Exp $ */ + +#ifndef _CFB8_16_H +#define _CFB8_16_H + +#include "regionstr.h" +#include "windowstr.h" + +typedef struct { + pointer pix8; + int width8; + pointer pix16; + int width16; + unsigned char key; +} cfb8_16ScreenRec, *cfb8_16ScreenPtr; + +extern int cfb8_16ScreenPrivateIndex; /* XXX */ +extern int cfb8_16GetScreenPrivateIndex(void); + +Bool +cfb8_16ScreenInit ( + ScreenPtr pScreen, + pointer pbits16, + pointer pbits8, + int xsize, int ysize, + int dpix, int dpiy, + int width16, + int width8 +); + +void +cfb8_16PaintWindow ( + WindowPtr pWin, + RegionPtr pRegion, + int what +); + +Bool cfb8_16CreateWindow(WindowPtr pWin); +Bool cfb8_16DestroyWindow(WindowPtr pWin); + +Bool +cfb8_16PositionWindow( + WindowPtr pWin, + int x, int y +); + +void +cfb8_16CopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + +Bool +cfb8_16ChangeWindowAttributes( + WindowPtr pWin, + unsigned long mask +); + +void +cfb8_16WindowExposures( + WindowPtr pWin, + RegionPtr pReg, + RegionPtr pOtherReg +); + +#define CFB8_16_GET_SCREEN_PRIVATE(pScreen)\ + (cfb8_16ScreenPtr)((pScreen)->devPrivates[cfb8_16GetScreenPrivateIndex()].ptr) + +#endif /* _CFB8_16_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32.h (revision 51223) @@ -0,0 +1,228 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf8_32bpp/cfb8_32.h,v 1.5 2000/03/02 02:32:52 mvojkovi Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _CFB8_32_H +#define _CFB8_32_H + +#include "gcstruct.h" + +typedef struct { + GCOps *Ops8bpp; + GCOps *Ops32bpp; + unsigned long changes; + Bool OpsAre8bpp; +} cfb8_32GCRec, *cfb8_32GCPtr; + +typedef struct { + unsigned char key; + void (*EnableDisableFBAccess)(int scrnIndex, Bool enable); + pointer visualData; +} cfb8_32ScreenRec, *cfb8_32ScreenPtr; + + +extern int cfb8_32GCPrivateIndex; /* XXX */ +extern int cfb8_32GetGCPrivateIndex(void); +extern int cfb8_32ScreenPrivateIndex; /* XXX */ +extern int cfb8_32GetScreenPrivateIndex(void); + +void +cfb8_32SaveAreas( + PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin +); + +void +cfb8_32RestoreAreas( + PixmapPtr pPixmap, + RegionPtr prgnRestore, + int xorg, + int yorg, + WindowPtr pWin +); + +RegionPtr +cfb8_32CopyArea( + DrawablePtr pSrcDraw, + DrawablePtr pDstDraw, + GC *pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty +); + +void +cfbDoBitblt8To32( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long planemask +); + +void +cfbDoBitblt32To8( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long planemask +); + + +void +cfb8_32ValidateGC8( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +void +cfb8_32ValidateGC32( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +void +cfb32ValidateGC_Underlay( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +Bool cfb8_32CreateGC(GCPtr pGC); + +void +cfb8_32GetSpans( + DrawablePtr pDraw, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart +); + +void +cfb8_32PutImage ( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, int y, int w, int h, + int leftPad, + int format, + char *pImage +); + +void +cfb8_32GetImage ( + DrawablePtr pDraw, + int sx, int sy, int w, int h, + unsigned int format, + unsigned long planeMask, + char *pdstLine +); + +void +cfb8_32PaintWindow ( + WindowPtr pWin, + RegionPtr pRegion, + int what +); + +Bool +cfb8_32ScreenInit ( + ScreenPtr pScreen, + pointer pbits, + int xsize, int ysize, + int dpix, int dpiy, + int width +); + +void +cfb8_32FillBoxSolid8 ( + DrawablePtr pDraw, + int nbox, + BoxPtr pBox, + unsigned long color +); + + +void +cfb8_32FillBoxSolid32 ( + DrawablePtr pDraw, + int nbox, + BoxPtr pBox, + unsigned long color +); + +RegionPtr +cfb8_32CopyPlane( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty, + unsigned long bitPlane +); + +void +cfbDoBitblt8To8GXcopy( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long pm +); + +void +cfbDoBitblt24To24GXcopy( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long pm +); + +Bool cfb8_32CreateWindow(WindowPtr pWin); +Bool cfb8_32DestroyWindow(WindowPtr pWin); + +Bool +cfb8_32PositionWindow( + WindowPtr pWin, + int x, int y +); + +void +cfb8_32CopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + +Bool +cfb8_32ChangeWindowAttributes( + WindowPtr pWin, + unsigned long mask +); + + +#define CFB8_32_GET_GC_PRIVATE(pGC)\ + (cfb8_32GCPtr)((pGC)->devPrivates[cfb8_32GetGCPrivateIndex()].ptr) + +#define CFB8_32_GET_SCREEN_PRIVATE(pScreen)\ + (cfb8_32ScreenPtr)((pScreen)->devPrivates[cfb8_32GetScreenPrivateIndex()].ptr) + +Bool xf86Overlay8Plus32Init (ScreenPtr pScreen); + +#endif /* _CFB8_32_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32wid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32wid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8_32wid.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86$ */ + +#ifndef _CFB8_32WID_H +#define _CFB8_32WID_H + +#include "regionstr.h" +#include "windowstr.h" + +typedef struct { + unsigned int (*WidGet)(WindowPtr); + Bool (*WidAlloc)(WindowPtr); + void (*WidFree)(WindowPtr); + void (*WidFillBox)(DrawablePtr, DrawablePtr, int, BoxPtr); + void (*WidCopyArea)(DrawablePtr, RegionPtr, DDXPointPtr); +} cfb8_32WidOps; + +typedef struct { + pointer pix8; + int width8; + pointer pix32; + int width32; + + /* WID information */ + pointer pixWid; + int widthWid; + int bitsPerWid; + cfb8_32WidOps *WIDOps; +} cfb8_32WidScreenRec, *cfb8_32WidScreenPtr; + +extern int cfb8_32WidScreenPrivateIndex; /* XXX */ +extern int cfb8_32WidGetScreenPrivateIndex(void); + +Bool +cfb8_32WidScreenInit ( + ScreenPtr pScreen, + pointer pbits32, + pointer pbits8, + pointer pbitsWid, + int xsize, int ysize, + int dpix, int dpiy, + int width32, + int width8, + int widthWid, + int bitsPerWid, + cfb8_32WidOps *WIDOps +); + +/* cfbwindow.c */ + +void +cfb8_32WidPaintWindow ( + WindowPtr pWin, + RegionPtr pRegion, + int what +); + +Bool cfb8_32WidCreateWindow(WindowPtr pWin); +Bool cfb8_32WidDestroyWindow(WindowPtr pWin); + +Bool +cfb8_32WidPositionWindow( + WindowPtr pWin, + int x, int y +); + +void +cfb8_32WidCopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + +Bool +cfb8_32WidChangeWindowAttributes( + WindowPtr pWin, + unsigned long mask +); + +void +cfb8_32WidWindowExposures( + WindowPtr pWin, + RegionPtr pReg, + RegionPtr pOtherReg +); + +/* cfbwid.c */ + +Bool +cfb8_32WidGenericOpsInit(cfb8_32WidScreenPtr pScreenPriv); + +#define CFB8_32WID_GET_SCREEN_PRIVATE(pScreen)\ + (cfb8_32WidScreenPtr)((pScreen)->devPrivates[cfb8_32WidGetScreenPrivateIndex()].ptr) + +#endif /* _CFB8_32WID_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8bit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8bit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfb8bit.h (revision 51223) @@ -0,0 +1,1572 @@ +/* + * cfb8bit.h + * + * Defines which are only useful to 8 bit color frame buffers + * + * That doesn't seem to be true any more. Some of the macros in here + * are used for depths other than 8. Perhaps the file should be + * renamed. dpw + */ +/* $XFree86: xc/programs/Xserver/cfb/cfb8bit.h,v 3.7 2001/12/14 19:59:20 dawes Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ + +/* $Xorg: cfb8bit.h,v 1.4 2001/02/09 02:04:37 xorgcvs Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "servermd.h" + +#if (BITMAP_BIT_ORDER == MSBFirst) +#define GetBitGroup(x) (((PixelGroup) (x)) >> (PGSZ - PGSZB)) +#define NextBitGroup(x) ((x) <<= PGSZB) +#define NextSomeBits(x,n) ((x) <<= (n)) +#else +#define GetBitGroup(x) ((x) & PGSZBMSK) +#define NextBitGroup(x) ((x) >>= PGSZB) +#define NextSomeBits(x,n) ((x) >>= (n)) +#endif + +#define RotBitsLeft(x,k) ((x) = BitLeft (x,k) | \ + BitRight (x, PGSZ-(k))) + +#if defined(__GNUC__) && defined(mc68020) +#undef RotBitsLeft +#define RotBitsLeft(x,k) asm("rol%.l %2,%0" \ + : "=d" (x) \ + : "0" (x), "dI" (k)) +#endif + +#if PSZ == 8 + +#define GetPixelGroup(x) (cfb8StippleXor[GetBitGroup(x)]) +#define RRopPixels(dst,x) (DoRRop(dst,cfb8StippleAnd[x], cfb8StippleXor[x])) +#define RRopPixelGroup(dst,x) (RRopPixels(dst,GetBitGroup(x))) +#define MaskRRopPixels(dst,x,mask) (DoMaskRRop(dst,cfb8StippleAnd[x], cfb8StippleXor[x], mask)) + +#define NUM_MASKS (1<= MFB_PPW) \ + { \ + inputBits = *srcTemp++; \ + bitsLeft -= MFB_PPW; \ + partBitsLeft = MFB_PPW; \ + } \ + else \ + { \ + inputBits = 0; \ + if (bitsLeft) \ + inputBits = *srcTemp & ~cfb8BitLenMasks[bitsLeft]; \ + srcTemp = srcStart; \ + partBitsLeft = bitsLeft; \ + bitsLeft = bitsWhole; \ + } + +#define NextUnnaturalStippleBits \ + if (partBitsLeft >= PPW) { \ + bits = GetBitGroup (inputBits); \ + NextBitGroup (inputBits); \ + partBitsLeft -= PPW; \ + } else { \ + bits = GetBitGroup (inputBits); \ + nextPartBits = PPW - partBitsLeft; \ + NextUnnaturalStippleWord \ + if (partBitsLeft < nextPartBits) { \ + if (partBitsLeft) {\ + bits |= BitRight (GetBitGroup (inputBits), \ + PPW - nextPartBits) & PPWMSK;\ + nextPartBits -= partBitsLeft; \ + } \ + NextUnnaturalStippleWord \ + } \ + bits |= BitRight (GetBitGroup (inputBits), \ + PPW - nextPartBits) & PPWMSK; \ + NextSomeBits (inputBits, nextPartBits); \ + partBitsLeft -= nextPartBits; \ + } + +#define NextUnnaturalStippleBitsFast \ + if (partBitsLeft >= PPW) { \ + bits = GetBitGroup(inputBits); \ + NextBitGroup(inputBits); \ + partBitsLeft -= PPW; \ + } else { \ + bits = GetBitGroup (inputBits); \ + nextPartBits = PPW - partBitsLeft; \ + inputBits = *srcTemp++; \ + bits |= BitRight (GetBitGroup (inputBits), \ + partBitsLeft) & PPWMSK; \ + NextSomeBits (inputBits, nextPartBits); \ + partBitsLeft = MFB_PPW - nextPartBits; \ + } + +/* + * WriteBitGroup takes the destination address, a pixel + * value (which must be 8 bits duplicated 4 time with PFILL) + * and the PPW bits to write, which must be in the low order + * bits of the register (probably from GetBitGroup) and writes + * the appropriate locations in memory with the pixel value. This + * is a copy-mode only operation. + */ + +#define RRopBitGroup(dst,bits) \ + { \ + *(dst) = RRopPixels(*(dst),bits); \ + } + +#define MaskRRopBitGroup(dst,bits,mask) \ + { \ + *(dst) = MaskRRopPixels(*(dst),bits,mask); \ + } +#endif /* PSZ == 8 */ + +#if !defined(AVOID_MEMORY_READ) && PSZ == 8 + +#define WriteBitGroup(dst,pixel,bits) \ + { \ + register PixelGroup _maskTmp = cfb8PixelMasks[(bits)]; \ + *(dst) = (*(dst) & ~_maskTmp) | ((pixel) & _maskTmp); \ + } + +#define SwitchBitGroup(dst,pixel,bits) \ + { \ + register PixelGroup _maskTmp = cfb8PixelMasks[(bits)]; \ + register PixelGroup _pixTmp = ((pixel) & _maskTmp); \ + _maskTmp = ~_maskTmp; \ + SwitchBitsLoop (*(dst) = (*(dst) & _maskTmp) | _pixTmp;) \ + } + +#else /* AVOID_MEMORY_READ */ + +#if PGSZ == 32 +#if (BITMAP_BIT_ORDER == MSBFirst) +#define SinglePixel0 3 +#define SinglePixel1 2 +#define SinglePixel2 1 +#define SinglePixel3 0 +#define SinglePixel4 7 +#define SinglePixel5 6 +#define SinglePixel6 5 +#define SinglePixel7 4 +#define SinglePixel8 0xB +#define SinglePixel9 0xA +#define DoublePixel0 1 +#define DoublePixel1 0 +#define DoublePixel2 3 +#define DoublePixel3 2 +#define DoublePixel4 5 +#define DoublePixel5 4 +#else +#define SinglePixel0 0 +#define SinglePixel1 1 +#define SinglePixel2 2 +#define SinglePixel3 3 +#define SinglePixel4 4 +#define SinglePixel5 5 +#define SinglePixel6 6 +#define SinglePixel7 7 +#define SinglePixel8 8 +#define SinglePixel9 9 +#define DoublePixel0 0 +#define DoublePixel1 1 +#define DoublePixel2 2 +#define DoublePixel3 3 +#define DoublePixel4 4 +#define DoublePixel5 5 +#endif +#define QuadPixel0 0 +#define QuadPixel1 1 +#define QuadPixel2 2 +#else /* PGSZ == 64 */ +#if (BITMAP_BIT_ORDER == MSBFirst) +#define SinglePixel0 7 +#define SinglePixel1 6 +#define SinglePixel2 5 +#define SinglePixel3 4 +#define SinglePixel4 3 +#define SinglePixel5 2 +#define SinglePixel6 1 +#define SinglePixel7 0 +#define DoublePixel0 3 +#define DoublePixel1 2 +#define DoublePixel2 1 +#define DoublePixel3 0 +#define QuadPixel0 1 +#define QuadPixel1 0 +#else +#define SinglePixel0 0 +#define SinglePixel1 1 +#define SinglePixel2 2 +#define SinglePixel3 3 +#define SinglePixel4 4 +#define SinglePixel5 5 +#define SinglePixel6 6 +#define SinglePixel7 7 +#define DoublePixel0 0 +#define DoublePixel1 1 +#define DoublePixel2 2 +#define DoublePixel3 3 +#define QuadPixel0 0 +#define QuadPixel1 1 +#endif +#define OctaPixel0 0 +#endif /* PGSZ == 64 */ + +#if PSZ == 8 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[0] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) \ + ((PixelGroup *) (dst))[OctaPixel0] = (pixel); \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ == 64 */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[0] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + if ( bits == 0xff ) \ + SwitchBitsLoop (((PixelGroup *) (dst))[OctaPixel0] = (pixel);) \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel);)\ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel);) \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel);)\ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel1] = (pixel);) \ + break; \ + } \ + } \ +} +#endif /* PGSZ == 64 */ +#endif /* PSZ == 8 */ + +#if PSZ == 16 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[QuadPixel0] = (pixel); \ + ((PixelGroup *) (dst))[QuadPixel1] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 16 */ + +#if PSZ == 24 +/* 32 000011112222*/ +/* 24 000111222333*/ +/* 16 001122334455*/ +/* 8 0123456789AB*/ +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + { \ + register CARD32 reg_pixel = (pixel); \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel2] = ((reg_pixel>>16)&0xFF); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel&0xFF; \ + ((CARD16 *) (dst))[DoublePixel2] = (reg_pixel>>8)&0xFFFF; \ + break; \ + case 3: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel & 0xFF; \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel2] = (reg_pixel>>8)&0xFFFF; \ + ((CARD8 *) (dst))[SinglePixel2] = (reg_pixel>>16&0xFF); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel8] = (reg_pixel>>16)&0xFF; \ + break; \ + case 5: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 16; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + ((CARD16 *) (dst))[DoublePixel5] = (reg_pixel>>8); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel&0xFF; \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + break; \ + case 11: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel; \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 13: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 15: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel; \ + break; \ + } \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[DoublePixel0] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel1] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel2] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel3] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);) \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 24 */ + +#if PSZ == 32 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[DoublePixel0] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel1] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel2] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel3] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 32 */ +#endif /* AVOID_MEMORY_READ */ + +extern PixelGroup cfb8BitLenMasks[PGSZ]; + +extern int cfb8SetStipple ( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*planemask*/ +); + +extern int cfb8SetOpaqueStipple ( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*bg*/, + CfbBits /*planemask*/ +); + +extern int cfb8ComputeClipMasks32 ( + BoxPtr /*pBox*/, + int /*numRects*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + CARD32 * /*clips*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmap.h (revision 51223) @@ -0,0 +1,344 @@ +/* + * $Xorg: cfbmap.h,v 1.4 2001/02/09 02:04:38 xorgcvs Exp $ + * +Copyright 1991, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ + +/* $XFree86: xc/programs/Xserver/cfb/cfbmap.h,v 3.11tsi Exp $ */ + +/* + * Map names around so that multiple depths can be supported simultaneously + */ + +#if 0 +#undef QuartetBitsTable +#undef QuartetPixelMaskTable +#undef cfb8ClippedLineCopy +#undef cfb8ClippedLineGeneral +#undef cfb8ClippedLineXor +#undef cfb8LineSS1Rect +#undef cfb8LineSS1RectCopy +#undef cfb8LineSS1RectGeneral +#undef cfb8LineSS1RectPreviousCopy +#undef cfb8LineSS1RectXor +#undef cfb8SegmentSS1Rect +#undef cfb8SegmentSS1RectCopy +#undef cfb8SegmentSS1RectGeneral +#undef cfb8SegmentSS1RectShiftCopy +#undef cfb8SegmentSS1RectXor +#undef cfbAllocatePrivates +#undef cfbBSFuncRec +#undef cfbBitBlt +#undef cfbBresD +#undef cfbBresS +#undef cfbChangeWindowAttributes +#undef cfbCloseScreen +#undef cfbCopyArea +#undef cfbCopyImagePlane +#undef cfbCopyPixmap +#undef cfbCopyPlane +#undef cfbCopyPlaneReduce +#undef cfbCopyRotatePixmap +#undef cfbCopyWindow +#undef cfbCreateGC +#undef cfbCreatePixmap +#undef cfbCreateScreenResources +#undef cfbCreateWindow +#undef cfbDestroyPixmap +#undef cfbDestroyWindow +#undef cfbDoBitblt +#undef cfbDoBitbltCopy +#undef cfbDoBitbltGeneral +#undef cfbDoBitbltOr +#undef cfbDoBitbltXor +#undef cfbFillBoxSolid +#undef cfbFillBoxTile32 +#undef cfbFillBoxTile32sCopy +#undef cfbFillBoxTile32sGeneral +#undef cfbFillBoxTileOdd +#undef cfbFillBoxTileOddCopy +#undef cfbFillBoxTileOddGeneral +#undef cfbFillPoly1RectCopy +#undef cfbFillPoly1RectGeneral +#undef cfbFillRectSolidCopy +#undef cfbFillRectSolidGeneral +#undef cfbFillRectSolidXor +#undef cfbFillRectTile32Copy +#undef cfbFillRectTile32General +#undef cfbFillRectTileOdd +#undef cfbFillSpanTile32sCopy +#undef cfbFillSpanTile32sGeneral +#undef cfbFillSpanTileOddCopy +#undef cfbFillSpanTileOddGeneral +#undef cfbFinishScreenInit +#undef cfbGCFuncs +#undef cfbGCPrivateIndex +#undef cfbGetImage +#undef cfbGetScreenPixmap +#undef cfbGetSpans +#undef cfbHorzS +#undef cfbImageGlyphBlt8 +#undef cfbInitializeColormap +#undef cfbInstallColormap +#undef cfbLineSD +#undef cfbLineSS +#undef cfbListInstalledColormaps +#undef cfbMapWindow +#undef cfbMatchCommon +#undef cfbNonTEOps +#undef cfbNonTEOps1Rect +#undef cfbPadPixmap +#undef cfbPaintWindow +#undef cfbPolyFillArcSolidCopy +#undef cfbPolyFillArcSolidGeneral +#undef cfbPolyFillRect +#undef cfbPolyGlyphBlt8 +#undef cfbPolyGlyphRop8 +#undef cfbPolyPoint +#undef cfbPositionWindow +#undef cfbPutImage +#undef cfbReduceRasterOp +#undef cfbResolveColor +#undef cfbRestoreAreas +#undef cfbSaveAreas +#undef cfbScreenInit +#undef cfbScreenPrivateIndex +#undef cfbSegmentSD +#undef cfbSegmentSS +#undef cfbSetScanline +#undef cfbSetScreenPixmap +#undef cfbSetSpans +#undef cfbSetupScreen +#undef cfbSolidSpansCopy +#undef cfbSolidSpansGeneral +#undef cfbSolidSpansXor +#undef cfbStippleStack +#undef cfbStippleStackTE +#undef cfbTEGlyphBlt +#undef cfbTEOps +#undef cfbTEOps1Rect +#undef cfbTile32FSCopy +#undef cfbTile32FSGeneral +#undef cfbUninstallColormap +#undef cfbUnmapWindow +#undef cfbUnnaturalStippleFS +#undef cfbUnnaturalTileFS +#undef cfbValidateGC +#undef cfbVertS +#undef cfbWindowPrivateIndex +#undef cfbXRotatePixmap +#undef cfbYRotatePixmap +#undef cfbZeroPolyArcSS8Copy +#undef cfbZeroPolyArcSS8General +#undef cfbZeroPolyArcSS8Xor +#undef cfbendpartial +#undef cfbendtab +#undef cfbmask +#undef cfbrmask +#undef cfbstartpartial +#undef cfbstarttab +#endif + +/* a losing vendor cpp dumps core if we define CFBNAME in terms of CATNAME */ + +#if PSZ != 8 + +#if PSZ == 32 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb32##subname +#else +#define CFBNAME(subname) cfb32/**/subname +#endif +#endif + +#if PSZ == 24 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb24##subname +#else +#define CFBNAME(subname) cfb24/**/subname +#endif +#endif + +#if PSZ == 16 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb16##subname +#else +#define CFBNAME(subname) cfb16/**/subname +#endif +#endif + +#if PSZ == 4 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb4##subname +#else +#define CFBNAME(subname) cfb4/**/subname +#endif +#endif + +#ifndef CFBNAME +cfb can not hack PSZ yet +#endif + +#undef CATNAME + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CATNAME(prefix,subname) prefix##subname +#else +#define CATNAME(prefix,subname) prefix/**/subname +#endif + +#define QuartetBitsTable CFBNAME(QuartetBitsTable) +#define QuartetPixelMaskTable CFBNAME(QuartetPixelMaskTable) +#define cfb8ClippedLineCopy CFBNAME(ClippedLineCopy) +#define cfb8ClippedLineGeneral CFBNAME(ClippedLineGeneral ) +#define cfb8ClippedLineXor CFBNAME(ClippedLineXor) +#define cfb8LineSS1Rect CFBNAME(LineSS1Rect) +#define cfb8LineSS1RectCopy CFBNAME(LineSS1RectCopy) +#define cfb8LineSS1RectGeneral CFBNAME(LineSS1RectGeneral ) +#define cfb8LineSS1RectPreviousCopy CFBNAME(LineSS1RectPreviousCopy) +#define cfb8LineSS1RectXor CFBNAME(LineSS1RectXor) +#define cfb8SegmentSS1Rect CFBNAME(SegmentSS1Rect) +#define cfb8SegmentSS1RectCopy CFBNAME(SegmentSS1RectCopy) +#define cfb8SegmentSS1RectGeneral CFBNAME(SegmentSS1RectGeneral ) +#define cfb8SegmentSS1RectShiftCopy CFBNAME(SegmentSS1RectShiftCopy) +#define cfb8SegmentSS1RectXor CFBNAME(SegmentSS1RectXor) +#define cfbAllocatePrivates CFBNAME(AllocatePrivates) +#define cfbBSFuncRec CFBNAME(BSFuncRec) +#define cfbBitBlt CFBNAME(BitBlt) +#define cfbBresD CFBNAME(BresD) +#define cfbBresS CFBNAME(BresS) +#define cfbChangeWindowAttributes CFBNAME(ChangeWindowAttributes) +#define cfbClearVisualTypes CFBNAME(cfbClearVisualTypes) +#define cfbCloseScreen CFBNAME(CloseScreen) +#define cfbCreateDefColormap CFBNAME (cfbCreateDefColormap) +#define cfbCopyArea CFBNAME(CopyArea) +#define cfbCopyImagePlane CFBNAME(CopyImagePlane) +#define cfbCopyPixmap CFBNAME(CopyPixmap) +#define cfbCopyPlane CFBNAME(CopyPlane) +#define cfbCopyPlaneReduce CFBNAME(CopyPlaneReduce) +#define cfbCopyRotatePixmap CFBNAME(CopyRotatePixmap) +#define cfbCopyWindow CFBNAME(CopyWindow) +#define cfbCreateGC CFBNAME(CreateGC) +#define cfbCreatePixmap CFBNAME(CreatePixmap) +#define cfbCreateScreenResources CFBNAME(CreateScreenResources) +#define cfbCreateWindow CFBNAME(CreateWindow) +#define cfbDestroyPixmap CFBNAME(DestroyPixmap) +#define cfbDestroyWindow CFBNAME(DestroyWindow) +#define cfbDoBitblt CFBNAME(DoBitblt) +#define cfbDoBitbltCopy CFBNAME(DoBitbltCopy) +#define cfbDoBitbltGeneral CFBNAME(DoBitbltGeneral) +#define cfbDoBitbltOr CFBNAME(DoBitbltOr) +#define cfbDoBitbltXor CFBNAME(DoBitbltXor) +#define cfbExpandDirectColors CFBNAME(cfbExpandDirectColors) +#define cfbFillBoxSolid CFBNAME(FillBoxSolid) +#define cfbFillBoxTile32 CFBNAME(FillBoxTile32) +#define cfbFillBoxTile32sCopy CFBNAME(FillBoxTile32sCopy) +#define cfbFillBoxTile32sGeneral CFBNAME(FillBoxTile32sGeneral) +#define cfbFillBoxTileOdd CFBNAME(FillBoxTileOdd) +#define cfbFillBoxTileOddCopy CFBNAME(FillBoxTileOddCopy) +#define cfbFillBoxTileOddGeneral CFBNAME(FillBoxTileOddGeneral) +#define cfbFillPoly1RectCopy CFBNAME(FillPoly1RectCopy) +#define cfbFillPoly1RectGeneral CFBNAME(FillPoly1RectGeneral) +#define cfbFillRectSolidCopy CFBNAME(FillRectSolidCopy) +#define cfbFillRectSolidGeneral CFBNAME(FillRectSolidGeneral) +#define cfbFillRectSolidXor CFBNAME(FillRectSolidXor) +#define cfbFillRectTile32Copy CFBNAME(FillRectTile32Copy) +#define cfbFillRectTile32General CFBNAME(FillRectTile32General) +#define cfbFillRectTileOdd CFBNAME(FillRectTileOdd) +#define cfbFillSpanTile32sCopy CFBNAME(FillSpanTile32sCopy) +#define cfbFillSpanTile32sGeneral CFBNAME(FillSpanTile32sGeneral) +#define cfbFillSpanTileOddCopy CFBNAME(FillSpanTileOddCopy) +#define cfbFillSpanTileOddGeneral CFBNAME(FillSpanTileOddGeneral) +#define cfbFinishScreenInit CFBNAME(FinishScreenInit) +#define cfbGCFuncs CFBNAME(GCFuncs) +#define cfbGCPrivateIndex CFBNAME(GCPrivateIndex) +#define cfbGetImage CFBNAME(GetImage) +#define cfbGetScreenPixmap CFBNAME(GetScreenPixmap) +#define cfbGetSpans CFBNAME(GetSpans) +#define cfbHorzS CFBNAME(HorzS) +#define cfbImageGlyphBlt8 CFBNAME(ImageGlyphBlt8) +#define cfbInitializeColormap CFBNAME(InitializeColormap) +#define cfbInitVisuals CFBNAME(cfbInitVisuals) +#define cfbInstallColormap CFBNAME(InstallColormap) +#define cfbLineSD CFBNAME(LineSD) +#define cfbLineSS CFBNAME(LineSS) +#define cfbListInstalledColormaps CFBNAME(ListInstalledColormaps) +#define cfbMapWindow CFBNAME(MapWindow) +#define cfbMatchCommon CFBNAME(MatchCommon) +#define cfbNonTEOps CFBNAME(NonTEOps) +#define cfbNonTEOps1Rect CFBNAME(NonTEOps1Rect) +#define cfbPadPixmap CFBNAME(PadPixmap) +#define cfbPaintWindow CFBNAME(PaintWindow) +#define cfbPolyFillArcSolidCopy CFBNAME(PolyFillArcSolidCopy) +#define cfbPolyFillArcSolidGeneral CFBNAME(PolyFillArcSolidGeneral) +#define cfbPolyFillRect CFBNAME(PolyFillRect) +#define cfbPolyGlyphBlt8 CFBNAME(PolyGlyphBlt8) +#define cfbPolyGlyphRop8 CFBNAME(PolyGlyphRop8) +#define cfbPolyPoint CFBNAME(PolyPoint) +#define cfbPositionWindow CFBNAME(PositionWindow) +#define cfbPutImage CFBNAME(PutImage) +#define cfbReduceRasterOp CFBNAME(ReduceRasterOp) +#define cfbResolveColor CFBNAME(ResolveColor) +#define cfbRestoreAreas CFBNAME(RestoreAreas) +#define cfbSaveAreas CFBNAME(SaveAreas) +#define cfbScreenInit CFBNAME(ScreenInit) +#define cfbScreenPrivateIndex CFBNAME(ScreenPrivateIndex) +#define cfbSegmentSD CFBNAME(SegmentSD) +#define cfbSegmentSS CFBNAME(SegmentSS) +#define cfbSetScanline CFBNAME(SetScanline) +#define cfbSetScreenPixmap CFBNAME(SetScreenPixmap) +#define cfbSetSpans CFBNAME(SetSpans) +#define cfbSetVisualTypes CFBNAME(cfbSetVisualTypes) +#define cfbSetupScreen CFBNAME(SetupScreen) +#define cfbSolidSpansCopy CFBNAME(SolidSpansCopy) +#define cfbSolidSpansGeneral CFBNAME(SolidSpansGeneral) +#define cfbSolidSpansXor CFBNAME(SolidSpansXor) +#define cfbStippleStack CFBNAME(StippleStack) +#define cfbStippleStackTE CFBNAME(StippleStackTE) +#define cfbTEGlyphBlt CFBNAME(TEGlyphBlt) +#define cfbTEOps CFBNAME(TEOps) +#define cfbTEOps1Rect CFBNAME(TEOps1Rect) +#define cfbTile32FSCopy CFBNAME(Tile32FSCopy) +#define cfbTile32FSGeneral CFBNAME(Tile32FSGeneral) +#define cfbUninstallColormap CFBNAME(UninstallColormap) +#define cfbUnmapWindow CFBNAME(UnmapWindow) +#define cfbUnnaturalStippleFS CFBNAME(UnnaturalStippleFS) +#define cfbUnnaturalTileFS CFBNAME(UnnaturalTileFS) +#define cfbValidateGC CFBNAME(ValidateGC) +#define cfbVertS CFBNAME(VertS) +#define cfbWindowPrivateIndex CFBNAME(WindowPrivateIndex) +#define cfbXRotatePixmap CFBNAME(XRotatePixmap) +#define cfbYRotatePixmap CFBNAME(YRotatePixmap) +#define cfbZeroPolyArcSS8Copy CFBNAME(ZeroPolyArcSSCopy) +#define cfbZeroPolyArcSS8General CFBNAME(ZeroPolyArcSSGeneral) +#define cfbZeroPolyArcSS8Xor CFBNAME(ZeroPolyArcSSXor) +#define cfbendpartial CFBNAME(endpartial) +#define cfbendtab CFBNAME(endtab) +#define cfbmask CFBNAME(mask) +#define cfbrmask CFBNAME(rmask) +#define cfbstartpartial CFBNAME(startpartial) +#define cfbstarttab CFBNAME(starttab) + +#endif /* PSZ != 8 */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmskbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmskbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbmskbits.h (revision 51223) @@ -0,0 +1,897 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfbmskbits.h,v 3.13tsi Exp $ */ +/************************************************************ +Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright no- +tice appear in all copies and that both that copyright no- +tice and this permission notice appear in supporting docu- +mentation, and that the names of Sun or The Open Group +not be used in advertising or publicity pertaining to +distribution of the software without specific prior +written permission. Sun and The Open Group make no +representations about the suitability of this software for +any purpose. It is provided "as is" without any express or +implied warranty. + +SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- +NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI- +ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/* $Xorg: cfbmskbits.h,v 1.3 2000/08/17 19:48:14 cpqbld Exp $ */ +/* Optimizations for PSZ == 32 added by Kyle Marvin (marvin@vitec.com) */ + +#include +#include +#include "servermd.h" +#if defined(XFREE86) || ( defined(__OpenBSD__) && defined(__alpha__) ) \ + || (defined(__bsdi__)) +#include "xf86_ansic.h" +#include "compiler.h" +#endif + +/* + * ========================================================================== + * Converted from mfb to support memory-mapped color framebuffer by smarks@sun, + * April-May 1987. + * + * The way I did the conversion was to consider each longword as an + * array of four bytes instead of an array of 32 one-bit pixels. So + * getbits() and putbits() retain much the same calling sequence, but + * they move bytes around instead of bits. Of course, this entails the + * removal of all of the one-bit-pixel dependencies from the other + * files, but the major bit-hacking stuff should be covered here. + * + * I've created some new macros that make it easier to understand what's + * going on in the pixel calculations, and that make it easier to change the + * pixel size. + * + * name explanation + * ---- ----------- + * PSZ pixel size (in bits) + * PGSZ pixel group size (in bits) + * PGSZB pixel group size (in bytes) + * PGSZBMSK mask with lowest PGSZB bits set to 1 + * PPW pixels per word (pixels per pixel group) + * PPWMSK mask with lowest PPW bits set to 1 + * PLST index of last pixel in a word (should be PPW-1) + * PIM pixel index mask (index within a pixel group) + * PWSH pixel-to-word shift (should be log2(PPW)) + * PMSK mask with lowest PSZ bits set to 1 + * + * + * Here are some sample values. In the notation cfbA,B: A is PSZ, and + * B is PGSZB. All the other values are derived from these + * two. This table does not show all combinations! + * + * name cfb8,4 cfb24,4 cfb32,4 cfb8,8 cfb24,8 cfb32,8 + * ---- ------ ------- ------ ------ ------ ------- + * PSZ 8 24 32 8 24 32 + * PGSZ 32 32 32 64 64 64 + * PGSZB 4 4 4 8 8 8 + * PGSZBMSK 0xF 0xF? 0xF 0xFF 0xFF 0xFF + * PPW 4 1 1 8 2 2 + * PPWMSK 0xF 0x1 0x1 0xFF 0x3? 0x3 + * PLST 3 0 0 7 1 1 + * PIM 0x3 0x0 0x0 0x7 0x1? 0x1 + * PWSH 2 0 0 3 1 1 + * PMSK 0xFF 0xFFFFFF 0xFFFFFFFF 0xFF 0xFFFFFF 0xFFFFFFFF + * + * + * I have also added a new macro, PFILL, that takes one pixel and + * replicates it throughout a word. This macro definition is dependent + * upon pixel and word size; it doesn't use macros like PPW and so + * forth. Examples: for monochrome, PFILL(1) => 0xffffffff, PFILL(0) => + * 0x00000000. For 8-bit color, PFILL(0x5d) => 0x5d5d5d5d. This macro + * is used primarily for replicating a plane mask into a word. + * + * Color framebuffers operations also support the notion of a plane + * mask. This mask determines which planes of the framebuffer can be + * altered; the others are left unchanged. I have added another + * parameter to the putbits and putbitsrop macros that is the plane + * mask. + * ========================================================================== + * + * Keith Packard (keithp@suse.com) + * 64bit code is no longer supported; it requires DIX support + * for repadding images which significantly impacts performance + */ + +/* + * PSZ needs to be defined before we get here. Usually it comes from a + * -DPSZ=foo on the compilation command line. + */ + +#ifndef PSZ +#define PSZ 8 +#endif + +/* + * PixelGroup is the data type used to operate on groups of pixels. + * We typedef it here to CARD32 with the assumption that you + * want to manipulate 32 bits worth of pixels at a time as you can. If CARD32 + * is not appropriate for your server, define it to something else + * before including this file. In this case you will also have to define + * PGSZB to the size in bytes of PixelGroup. + */ +#ifndef PixelGroup +#define PixelGroup CARD32 +#define PGSZB 4 +#endif /* PixelGroup */ + +#ifndef CfbBits +#define CfbBits CARD32 +#endif + +#define PGSZ (PGSZB << 3) +#define PPW (PGSZ/PSZ) +#define PLST (PPW-1) +#define PIM PLST +#define PMSK (((PixelGroup)1 << PSZ) - 1) +#define PPWMSK (((PixelGroup)1 << PPW) - 1) /* instead of BITMSK */ +#define PGSZBMSK (((PixelGroup)1 << PGSZB) - 1) + +/* set PWSH = log2(PPW) using brute force */ + +#if PPW == 1 +#define PWSH 0 +#else +#if PPW == 2 +#define PWSH 1 +#else +#if PPW == 4 +#define PWSH 2 +#else +#if PPW == 8 +#define PWSH 3 +#else +#if PPW == 16 +#define PWSH 4 +#endif /* PPW == 16 */ +#endif /* PPW == 8 */ +#endif /* PPW == 4 */ +#endif /* PPW == 2 */ +#endif /* PPW == 1 */ + +/* Defining PIXEL_ADDR means that individual pixels are addressable by this + * machine (as type PixelType). A possible CFB architecture which supported + * 8-bits-per-pixel on a non byte-addressable machine would not have this + * defined. + * + * Defining FOUR_BIT_CODE means that cfb knows how to stipple on this machine; + * eventually, stippling code for 16 and 32 bit devices should be written + * which would allow them to also use FOUR_BIT_CODE. There isn't that + * much to do in those cases, but it would make them quite a bit faster. + */ + +#if PSZ == 8 +#define PIXEL_ADDR +typedef CARD8 PixelType; +#define FOUR_BIT_CODE +#endif + +#if PSZ == 16 +#define PIXEL_ADDR +typedef CARD16 PixelType; +#endif + +#if PSZ == 24 +#undef PMSK +#define PMSK 0xFFFFFF +/*#undef PIM +#define PIM 3*/ +#define PIXEL_ADDR +typedef CARD32 PixelType; +#endif + +#if PSZ == 32 +#undef PMSK +#define PMSK 0xFFFFFFFF +#define PIXEL_ADDR +typedef CARD32 PixelType; +#endif + + +/* the following notes use the following conventions: +SCREEN LEFT SCREEN RIGHT +in this file and maskbits.c, left and right refer to screen coordinates, +NOT bit numbering in registers. + +cfbstarttab[n] + pixels[0,n-1] = 0's pixels[n,PPW-1] = 1's +cfbendtab[n] = + pixels[0,n-1] = 1's pixels[n,PPW-1] = 0's + +cfbstartpartial[], cfbendpartial[] + these are used as accelerators for doing putbits and masking out +bits that are all contained between longword boudaries. the extra +256 bytes of data seems a small price to pay -- code is smaller, +and narrow things (e.g. window borders) go faster. + +the names may seem misleading; they are derived not from which end +of the word the bits are turned on, but at which end of a scanline +the table tends to be used. + +look at the tables and macros to understand boundary conditions. +(careful readers will note that starttab[n] = ~endtab[n] for n != 0) + +----------------------------------------------------------------------- +these two macros depend on the screen's bit ordering. +in both of them x is a screen position. they are used to +combine bits collected from multiple longwords into a +single destination longword, and to unpack a single +source longword into multiple destinations. + +SCRLEFT(dst, x) + takes dst[x, PPW] and moves them to dst[0, PPW-x] + the contents of the rest of dst are 0 ONLY IF + dst is UNSIGNED. + is cast as an unsigned. + this is a right shift on the VAX, left shift on + Sun and pc-rt. + +SCRRIGHT(dst, x) + takes dst[0,x] and moves them to dst[PPW-x, PPW] + the contents of the rest of dst are 0 ONLY IF + dst is UNSIGNED. + this is a left shift on the VAX, right shift on + Sun and pc-rt. + + +the remaining macros are cpu-independent; all bit order dependencies +are built into the tables and the two macros above. + +maskbits(x, w, startmask, endmask, nlw) + for a span of width w starting at position x, returns +a mask for ragged pixels at start, mask for ragged pixels at end, +and the number of whole longwords between the ends. + +maskpartialbits(x, w, mask) + works like maskbits(), except all the pixels are in the + same longword (i.e. (x&0xPIM + w) <= PPW) + +mask32bits(x, w, startmask, endmask, nlw) + as maskbits, but does not calculate nlw. it is used by + cfbGlyphBlt to put down glyphs <= PPW bits wide. + +getbits(psrc, x, w, dst) + starting at position x in psrc (x < PPW), collect w + pixels and put them in the screen left portion of dst. + psrc is a longword pointer. this may span longword boundaries. + it special-cases fetching all w bits from one longword. + + +--------+--------+ +--------+ + | | m |n| | ==> | m |n| | + +--------+--------+ +--------+ + x x+w 0 w + psrc psrc+1 dst + m = PPW - x + n = w - m + + implementation: + get m pixels, move to screen-left of dst, zeroing rest of dst; + get n pixels from next word, move screen-right by m, zeroing + lower m pixels of word. + OR the two things together. + +putbits(src, x, w, pdst, planemask) + starting at position x in pdst, put down the screen-leftmost + w bits of src. pdst is a longword pointer. this may + span longword boundaries. + it special-cases putting all w bits into the same longword. + + +--------+ +--------+--------+ + | m |n| | ==> | | m |n| | + +--------+ +--------+--------+ + 0 w x x+w + dst pdst pdst+1 + m = PPW - x + n = w - m + + implementation: + get m pixels, shift screen-right by x, zero screen-leftmost x + pixels; zero rightmost m bits of *pdst and OR in stuff + from before the semicolon. + shift src screen-left by m, zero bits n-32; + zero leftmost n pixels of *(pdst+1) and OR in the + stuff from before the semicolon. + +putbitsrop(src, x, w, pdst, planemask, ROP) + like putbits but calls DoRop with the rasterop ROP (see cfb.h for + DoRop) + +getleftbits(psrc, w, dst) + get the leftmost w (w<=PPW) bits from *psrc and put them + in dst. this is used by the cfbGlyphBlt code for glyphs + <=PPW bits wide. +*/ + +#if (BITMAP_BIT_ORDER == MSBFirst) +#define BitRight(lw,n) ((lw) >> (n)) +#define BitLeft(lw,n) ((lw) << (n)) +#else /* (BITMAP_BIT_ORDER == LSBFirst) */ +#define BitRight(lw,n) ((lw) << (n)) +#define BitLeft(lw,n) ((lw) >> (n)) +#endif /* (BITMAP_BIT_ORDER == MSBFirst) */ + +#define SCRLEFT(lw, n) BitLeft (lw, (n) * PSZ) +#define SCRRIGHT(lw, n) BitRight(lw, (n) * PSZ) + +/* + * Note that the shift direction is independent of the byte ordering of the + * machine. The following is portable code. + */ +#if PPW == 16 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ | \ + ((p)&PMSK) << 4*PSZ | \ + ((p)&PMSK) << 5*PSZ | \ + ((p)&PMSK) << 6*PSZ | \ + ((p)&PMSK) << 7*PSZ | \ + ((p)&PMSK) << 8*PSZ | \ + ((p)&PMSK) << 9*PSZ | \ + ((p)&PMSK) << 10*PSZ | \ + ((p)&PMSK) << 11*PSZ | \ + ((p)&PMSK) << 12*PSZ | \ + ((p)&PMSK) << 13*PSZ | \ + ((p)&PMSK) << 14*PSZ | \ + ((p)&PMSK) << 15*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ + pf |= (pf << 4*PSZ); \ + pf |= (pf << 8*PSZ); \ +} +#endif /* PPW == 16 */ +#if PPW == 8 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ | \ + ((p)&PMSK) << 4*PSZ | \ + ((p)&PMSK) << 5*PSZ | \ + ((p)&PMSK) << 6*PSZ | \ + ((p)&PMSK) << 7*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ + pf |= (pf << 4*PSZ); \ +} +#endif +#if PPW == 4 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ +} +#endif +#if PPW == 2 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ +} +#endif +#if PPW == 1 +#define PFILL(p) (p) +#define PFILL2(p,pf) (pf = (p)) +#endif + +/* + * Reduced raster op - using precomputed values, perform the above + * in three instructions + */ + +#define DoRRop(dst, and, xor) (((dst) & (and)) ^ (xor)) + +#define DoMaskRRop(dst, and, xor, mask) \ + (((dst) & ((and) | ~(mask))) ^ (xor & mask)) + +#if PSZ != 32 || PPW != 1 + +# if (PSZ == 24 && PPW == 1) +#define maskbits(x, w, startmask, endmask, nlw) {\ + startmask = cfbstarttab[(x)&3]; \ + endmask = cfbendtab[((x)+(w)) & 3]; \ + nlw = ((((x)+(w))*3)>>2) - (((x)*3 +3)>>2); \ +} + +#define mask32bits(x, w, startmask, endmask) \ + startmask = cfbstarttab[(x)&3]; \ + endmask = cfbendtab[((x)+(w)) & 3]; + +#define maskpartialbits(x, w, mask) \ + mask = cfbstartpartial[(x) & 3] & cfbendpartial[((x)+(w)) & 3]; + +#define maskbits24(x, w, startmask, endmask, nlw) \ + startmask = cfbstarttab24[(x) & 3]; \ + endmask = cfbendtab24[((x)+(w)) & 3]; \ + if (startmask){ \ + nlw = (((w) - (4 - ((x) & 3))) >> 2); \ + } else { \ + nlw = (w) >> 2; \ + } + +#define getbits24(psrc, dst, index) {\ + register int idx; \ + switch(idx = ((index)&3)<<1){ \ + case 0: \ + dst = (*(psrc) &cfbmask[idx]); \ + break; \ + case 6: \ + dst = BitLeft((*(psrc) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dst = BitLeft((*(psrc) &cfbmask[idx]), cfb24Shift[idx]) | \ + BitRight(((*((psrc)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ +} + +#define putbits24(src, w, pdst, planemask, index) {\ + register PixelGroup dstpixel; \ + register unsigned int idx; \ + switch(idx = ((index)&3)<<1){ \ + case 0: \ + dstpixel = (*(pdst) &cfbmask[idx]); \ + break; \ + case 6: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx])| \ + BitRight(((*((pdst)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ + dstpixel &= ~(planemask); \ + dstpixel |= (src & planemask); \ + *(pdst) &= cfbrmask[idx]; \ + switch(idx){ \ + case 0: \ + *(pdst) |= (dstpixel & cfbmask[idx]); \ + break; \ + case 2: \ + case 4: \ + pdst++;idx++; \ + *(pdst) = ((*(pdst)) & cfbrmask[idx]) | \ + (BitLeft(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + pdst--;idx--; \ + case 6: \ + *(pdst) |= (BitRight(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + break; \ + }; \ +} + +#define putbitsrop24(src, x, pdst, planemask, rop) \ +{ \ + register PixelGroup t1, dstpixel; \ + register unsigned int idx; \ + switch(idx = (x)<<1){ \ + case 0: \ + dstpixel = (*(pdst) &cfbmask[idx]); \ + break; \ + case 6: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx])| \ + BitRight(((*((pdst)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ + DoRop(t1, rop, (src), dstpixel); \ + dstpixel &= ~planemask; \ + dstpixel |= (t1 & planemask); \ + *(pdst) &= cfbrmask[idx]; \ + switch(idx){ \ + case 0: \ + *(pdst) |= (dstpixel & cfbmask[idx]); \ + break; \ + case 2: \ + case 4: \ + *((pdst)+1) = ((*((pdst)+1)) & cfbrmask[idx+1]) | \ + (BitLeft(dstpixel, cfb24Shift[idx+1]) & (cfbmask[idx+1])); \ + case 6: \ + *(pdst) |= (BitRight(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + }; \ +} +# else /* PSZ == 24 && PPW == 1 */ +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = cfbstarttab[(x)&PIM]; \ + endmask = cfbendtab[((x)+(w)) & PIM]; \ + if (startmask) \ + nlw = (((w) - (PPW - ((x)&PIM))) >> PWSH); \ + else \ + nlw = (w) >> PWSH; + +#define maskpartialbits(x, w, mask) \ + mask = cfbstartpartial[(x) & PIM] & cfbendpartial[((x) + (w)) & PIM]; + +#define mask32bits(x, w, startmask, endmask) \ + startmask = cfbstarttab[(x)&PIM]; \ + endmask = cfbendtab[((x)+(w)) & PIM]; + +/* FIXME */ +#define maskbits24(x, w, startmask, endmask, nlw) \ + abort() +#define getbits24(psrc, dst, index) \ + abort() +#define putbits24(src, w, pdst, planemask, index) \ + abort() +#define putbitsrop24(src, x, pdst, planemask, rop) \ + abort() + +#endif /* PSZ == 24 && PPW == 1 */ + +#define getbits(psrc, x, w, dst) \ +if ( ((x) + (w)) <= PPW) \ +{ \ + dst = SCRLEFT(*(psrc), (x)); \ +} \ +else \ +{ \ + int m; \ + m = PPW-(x); \ + dst = (SCRLEFT(*(psrc), (x)) & cfbendtab[m]) | \ + (SCRRIGHT(*((psrc)+1), m) & cfbstarttab[m]); \ +} + + +#define putbits(src, x, w, pdst, planemask) \ +if ( ((x)+(w)) <= PPW) \ +{ \ + PixelGroup tmpmask; \ + maskpartialbits((x), (w), tmpmask); \ + tmpmask &= PFILL(planemask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (SCRRIGHT(src, x) & tmpmask); \ +} \ +else \ +{ \ + unsigned int m; \ + unsigned int n; \ + PixelGroup pm = PFILL(planemask); \ + m = PPW-(x); \ + n = (w) - m; \ + *(pdst) = (*(pdst) & (cfbendtab[x] | ~pm)) | \ + (SCRRIGHT(src, x) & (cfbstarttab[x] & pm)); \ + *((pdst)+1) = (*((pdst)+1) & (cfbstarttab[n] | ~pm)) | \ + (SCRLEFT(src, m) & (cfbendtab[n] & pm)); \ +} +#if defined(__GNUC__) && defined(mc68020) +#undef getbits +#define FASTGETBITS(psrc, x, w, dst) \ + asm ("bfextu %3{%1:%2},%0" \ + : "=d" (dst) : "di" (x), "di" (w), "o" (*(char *)(psrc))) + +#define getbits(psrc,x,w,dst) \ +{ \ + FASTGETBITS(psrc, (x) * PSZ, (w) * PSZ, dst); \ + dst = SCRLEFT(dst,PPW-(w)); \ +} + +#define FASTPUTBITS(src, x, w, pdst) \ + asm ("bfins %3,%0{%1:%2}" \ + : "=o" (*(char *)(pdst)) \ + : "di" (x), "di" (w), "d" (src), "0" (*(char *) (pdst))) + +#undef putbits +#define putbits(src, x, w, pdst, planemask) \ +{ \ + if (planemask != PMSK) { \ + PixelGroup _m, _pm; \ + FASTGETBITS(pdst, (x) * PSZ , (w) * PSZ, _m); \ + PFILL2(planemask, _pm); \ + _m &= (~_pm); \ + _m |= (SCRRIGHT(src, PPW-(w)) & _pm); \ + FASTPUTBITS(_m, (x) * PSZ, (w) * PSZ, pdst); \ + } else { \ + FASTPUTBITS(SCRRIGHT(src, PPW-(w)), (x) * PSZ, (w) * PSZ, pdst); \ + } \ +} + + +#endif /* mc68020 */ + +#define putbitsrop(src, x, w, pdst, planemask, rop) \ +if ( ((x)+(w)) <= PPW) \ +{ \ + PixelGroup tmpmask; \ + PixelGroup t1, t2; \ + maskpartialbits((x), (w), tmpmask); \ + PFILL2(planemask, t1); \ + tmpmask &= t1; \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ +} \ +else \ +{ \ + CfbBits m; \ + CfbBits n; \ + PixelGroup t1, t2; \ + PixelGroup pm; \ + PFILL2(planemask, pm); \ + m = PPW-(x); \ + n = (w) - m; \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + *(pdst) = (*(pdst) & (cfbendtab[x] | ~pm)) | (t2 & (cfbstarttab[x] & pm));\ + t1 = SCRLEFT((src), m); \ + DoRop(t2, rop, t1, *((pdst) + 1)); \ + *((pdst)+1) = (*((pdst)+1) & (cfbstarttab[n] | ~pm)) | \ + (t2 & (cfbendtab[n] & pm)); \ +} + +#else /* PSZ == 32 && PPW == 1*/ + +/* + * These macros can be optimized for 32-bit pixels since there is no + * need to worry about left/right edge masking. These macros were + * derived from the above using the following reductions: + * + * - x & PIW = 0 [since PIW = 0] + * - all masking tables are only indexed by 0 [ due to above ] + * - cfbstartab[0] and cfbendtab[0] = 0 [ no left/right edge masks] + * - cfbstartpartial[0] and cfbendpartial[0] = ~0 [no partial pixel mask] + * + * Macro reduction based upon constants cannot be performed automatically + * by the compiler since it does not know the contents of the masking + * arrays in cfbmskbits.c. + */ +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = endmask = 0; \ + nlw = (w); + +#define maskpartialbits(x, w, mask) \ + mask = 0xFFFFFFFF; + +#define mask32bits(x, w, startmask, endmask) \ + startmask = endmask = 0; + +/* + * For 32-bit operations, getbits(), putbits(), and putbitsrop() + * will only be invoked with x = 0 and w = PPW (1). The getbits() + * macro is only called within left/right edge logic, which doesn't + * happen for 32-bit pixels. + */ +#define getbits(psrc, x, w, dst) (dst) = *(psrc) + +#define putbits(src, x, w, pdst, planemask) \ + *(pdst) = (*(pdst) & ~planemask) | (src & planemask); + +#define putbitsrop(src, x, w, pdst, planemask, rop) \ +{ \ + PixelGroup t1; \ + DoRop(t1, rop, (src), *(pdst)); \ + *(pdst) = (*(pdst) & ~planemask) | (t1 & planemask); \ +} + +#endif /* PSZ != 32 */ + +/* + * Use these macros only when you're using the MergeRop stuff + * in ../mfb/mergerop.h + */ + +/* useful only when not spanning destination longwords */ +#if PSZ == 24 +#define putbitsmropshort24(src,x,w,pdst,index) {\ + PixelGroup _tmpmask; \ + PixelGroup _t1; \ + maskpartialbits ((x), (w), _tmpmask); \ + _t1 = SCRRIGHT((src), (x)); \ + DoMaskMergeRop24(_t1, pdst, _tmpmask, index); \ +} +#endif +#define putbitsmropshort(src,x,w,pdst) {\ + PixelGroup _tmpmask; \ + PixelGroup _t1; \ + maskpartialbits ((x), (w), _tmpmask); \ + _t1 = SCRRIGHT((src), (x)); \ + *pdst = DoMaskMergeRop(_t1, *pdst, _tmpmask); \ +} + +/* useful only when spanning destination longwords */ +#define putbitsmroplong(src,x,w,pdst) { \ + PixelGroup _startmask, _endmask; \ + int _m; \ + PixelGroup _t1; \ + _m = PPW - (x); \ + _startmask = cfbstarttab[x]; \ + _endmask = cfbendtab[(w) - _m]; \ + _t1 = SCRRIGHT((src), (x)); \ + pdst[0] = DoMaskMergeRop(_t1,pdst[0],_startmask); \ + _t1 = SCRLEFT ((src),_m); \ + pdst[1] = DoMaskMergeRop(_t1,pdst[1],_endmask); \ +} + +#define putbitsmrop(src,x,w,pdst) \ +if ((x) + (w) <= PPW) {\ + putbitsmropshort(src,x,w,pdst); \ +} else { \ + putbitsmroplong(src,x,w,pdst); \ +} + +#if GETLEFTBITS_ALIGNMENT == 1 +#define getleftbits(psrc, w, dst) dst = *((unsigned int *) psrc) +#define getleftbits24(psrc, w, dst, idx){ \ + regiseter int index; \ + switch(index = ((idx)&3)<<1){ \ + case 0: \ + dst = (*((unsigned int *) psrc))&cfbmask[index]; \ + break; \ + case 2: \ + case 4: \ + dst = BitLeft(((*((unsigned int *) psrc))&cfbmask[index]), cfb24Shift[index]); \ + dst |= BitRight(((*((unsigned int *) psrc)+1)&cfbmask[index]), cfb4Shift[index]); \ + break; \ + case 6: \ + dst = BitLeft((*((unsigned int *) psrc)),cfb24Shift[index]); \ + break; \ + }; \ +} +#endif /* GETLEFTBITS_ALIGNMENT == 1 */ + +#define getglyphbits(psrc, x, w, dst) \ +{ \ + dst = BitLeft((unsigned) *(psrc), (x)); \ + if ( ((x) + (w)) > 32) \ + dst |= (BitRight((unsigned) *((psrc)+1), 32-(x))); \ +} +#if GETLEFTBITS_ALIGNMENT == 2 +#define getleftbits(psrc, w, dst) \ + { \ + if ( ((int)(psrc)) & 0x01 ) \ + getglyphbits( ((unsigned int *)(((char *)(psrc))-1)), 8, (w), (dst) ); \ + else \ + dst = *((unsigned int *) psrc); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 2 */ + +#if GETLEFTBITS_ALIGNMENT == 4 +#define getleftbits(psrc, w, dst) \ + { \ + int off, off_b; \ + off_b = (off = ( ((int)(psrc)) & 0x03)) << 3; \ + getglyphbits( \ + (unsigned int *)( ((char *)(psrc)) - off), \ + (off_b), (w), (dst) \ + ); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 4 */ + +/* + * getstipplepixels( psrcstip, x, w, ones, psrcpix, destpix ) + * + * Converts bits to pixels in a reasonable way. Takes w (1 <= w <= PPW) + * bits from *psrcstip, starting at bit x; call this a quartet of bits. + * Then, takes the pixels from *psrcpix corresponding to the one-bits (if + * ones is TRUE) or the zero-bits (if ones is FALSE) of the quartet + * and puts these pixels into destpix. + * + * Example: + * + * getstipplepixels( &(0x08192A3B), 17, 4, 1, &(0x4C5D6E7F), dest ) + * + * 0x08192A3B = 0000 1000 0001 1001 0010 1010 0011 1011 + * + * This will take 4 bits starting at bit 17, so the quartet is 0x5 = 0101. + * It will take pixels from 0x4C5D6E7F corresponding to the one-bits in this + * quartet, so dest = 0x005D007F. + * + * XXX Works with both byte order. + * XXX This works for all values of x and w within a doubleword. + */ +#if (BITMAP_BIT_ORDER == MSBFirst) +#define getstipplepixels( psrcstip, x, w, ones, psrcpix, destpix ) \ +{ \ + PixelGroup q; \ + int m; \ + if ((m = ((x) - ((PPW*PSZ)-PPW))) > 0) { \ + q = (*(psrcstip)) << m; \ + if ( (x)+(w) > (PPW*PSZ) ) \ + q |= *((psrcstip)+1) >> ((PPW*PSZ)-m); \ + } \ + else \ + q = (*(psrcstip)) >> -m; \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +/* I just copied this to get the linker satisfied on PowerPC, + * so this may not be correct at all. + */ +#define getstipplepixels24(psrcstip,xt,ones,psrcpix,destpix,stipindex) \ +{ \ + PixelGroup q; \ + q = *(psrcstip) >> (xt); \ + q = ((ones) ? q : ~q) & 1; \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +#else /* BITMAP_BIT_ORDER == LSB */ + +/* this must load 32 bits worth; for most machines, thats an int */ +#define CfbFetchUnaligned(x) ldl_u(x) + +#define getstipplepixels( psrcstip, xt, w, ones, psrcpix, destpix ) \ +{ \ + PixelGroup q; \ + q = CfbFetchUnaligned(psrcstip) >> (xt); \ + if ( ((xt)+(w)) > (PPW*PSZ) ) \ + q |= (CfbFetchUnaligned((psrcstip)+1)) << ((PPW*PSZ)-(xt)); \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +#if PSZ == 24 +# if 0 +#define getstipplepixels24(psrcstip,xt,w,ones,psrcpix,destpix,stipindex,srcindex,dstindex) \ +{ \ + PixelGroup q; \ + CfbBits src; \ + register unsigned int sidx; \ + register unsigned int didx; \ + sidx = ((srcindex) & 3)<<1; \ + didx = ((dstindex) & 3)<<1; \ + q = *(psrcstip) >> (xt); \ +/* if((srcindex)!=0)*/ \ +/* src = (((*(psrcpix)) << cfb24Shift[sidx]) & (cfbmask[sidx])) |*/ \ +/* (((*((psrcpix)+1)) << cfb24Shift[sidx+1]) & (cfbmask[sidx+1])); */\ +/* else */\ + src = (*(psrcpix))&0xFFFFFF; \ + if ( ((xt)+(w)) > PGSZ ) \ + q |= (*((psrcstip)+1)) << (PGSZ -(xt)); \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + src &= QuartetPixelMaskTable[q]; \ + *(destpix) &= cfbrmask[didx]; \ + switch(didx) {\ + case 0: \ + *(destpix) |= (src &cfbmask[didx]); \ + break; \ + case 2: \ + case 4: \ + destpix++;didx++; \ + *(destpix) = ((*(destpix)) & (cfbrmask[didx]))| \ + (BitLeft(src, cfb24Shift[didx]) & (cfbmask[didx])); \ + destpix--; didx--;\ + case 6: \ + *(destpix) |= (BitRight(src, cfb24Shift[didx]) & cfbmask[didx]); \ + break; \ + }; \ +} +# else +#define getstipplepixels24(psrcstip,xt,ones,psrcpix,destpix,stipindex) \ +{ \ + PixelGroup q; \ + q = *(psrcstip) >> (xt); \ + q = ((ones) ? q : ~q) & 1; \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +# endif +#endif /* PSZ == 24 */ +#endif + +extern PixelGroup cfbstarttab[]; +extern PixelGroup cfbendtab[]; +extern PixelGroup cfbstartpartial[]; +extern PixelGroup cfbendpartial[]; +extern PixelGroup cfbrmask[]; +extern PixelGroup cfbmask[]; +extern PixelGroup QuartetBitsTable[]; +extern PixelGroup QuartetPixelMaskTable[]; +#if PSZ == 24 +extern int cfb24Shift[]; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop.h (revision 51223) @@ -0,0 +1,343 @@ +/* + * $Xorg: cfbrrop.h,v 1.4 2001/02/09 02:04:38 xorgcvs Exp $ + * +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ + +/* $XFree86: xc/programs/Xserver/cfb/cfbrrop.h,v 3.10tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GXcopy +#include +#endif + +#define RROP_FETCH_GC(gc) \ + RROP_FETCH_GCPRIV(((cfbPrivGCPtr)(gc)->devPrivates[cfbGCPrivateIndex].ptr)) + +#ifndef RROP +#define RROP GXset +#endif + +#if RROP == GXcopy +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_xor; \ + CfbBits piQxelXor[3], spiQxelXor[8]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[2] = rrop_xor << 24; \ + spiQxelXor[3] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[4] = rrop_xor << 16; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelXor[6] = rrop_xor << 8; \ + spiQxelXor[1] = spiQxelXor[7] = 0; \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) = (*(dst) & cfbrmask[idx])|spiQxelXor[idx]; \ + if (idx == 2 || idx == 4){ \ + idx++; \ + *((dst)+1) = (*((dst)+1) & cfbrmask[idx])|spiQxelXor[idx]; \ + } \ + } +#define RROP_SOLID(dst, idx) \ + (*(dst) = piQxelXor[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) = (*(dst) & ~(mask))|(piQxelXor[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelXor; (void)spiQxelXor; +#else +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; +#define RROP_DECLARE register CfbBits rrop_xor; +#define RROP_SOLID(dst) (*(dst) = (rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) = (*(dst) & ~(mask)) | ((rrop_xor) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Copy) +#endif /* GXcopy */ + +#if RROP == GXxor +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_xor; \ + CfbBits piQxelXor[3], spiQxelXor[8]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[2] = rrop_xor << 24; \ + spiQxelXor[3] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[4] = rrop_xor << 16; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelXor[6] = rrop_xor << 8; \ + spiQxelXor[1] = spiQxelXor[7] = 0; \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) ^= spiQxelXor[idx]; \ + if (idx == 2 || idx == 4) \ + *((dst)+1) ^= spiQxelXor[idx+1]; \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) ^= piQxelXor[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) ^= (piQxelXor[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelXor; (void)spiQxelXor; +#else +#define RROP_DECLARE register CfbBits rrop_xor; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) ^= (rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) ^= ((rrop_xor) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Xor) +#endif /* GXxor */ + +#if RROP == GXand +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_and; \ + CfbBits piQxelAnd[3], spiQxelAnd[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + spiQxelAnd[0] = (rrop_and & 0xFFFFFF) | 0xFF000000; \ + spiQxelAnd[2] = (rrop_and << 24) | 0xFFFFFF; \ + spiQxelAnd[3] = ((rrop_and & 0xFFFF00)>> 8) | 0xFFFF0000; \ + spiQxelAnd[4] = (rrop_and << 16) | 0xFFFF; \ + spiQxelAnd[5] = ((rrop_and & 0xFF0000)>> 16) | 0xFFFFFF00; \ + spiQxelAnd[1] = (rrop_and << 8) | 0xFF; \ + piQxelAnd[0] = (rrop_and & 0xFFFFFF)|(rrop_and << 24); \ + piQxelAnd[1] = (rrop_and << 16)|((rrop_and & 0xFFFF00)>> 8); \ + piQxelAnd[2] = (rrop_and << 8)|((rrop_and & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) &= spiQxelAnd[0]; \ + break; \ + case 3: \ + *(dst) &= spiQxelAnd[1]; \ + break; \ + case 1: \ + *(dst) &= spiQxelAnd[2]; \ + *((dst)+1) &= spiQxelAnd[3]; \ + break; \ + case 2: \ + *(dst) &= spiQxelAnd[4]; \ + *((dst)+1) &= spiQxelAnd[5]; \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) &= piQxelAnd[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) &= (piQxelAnd[(idx)] | ~(mask))) +#define RROP_UNDECLARE (void)piQxelAnd; (void)spiQxelAnd; +#else +#define RROP_DECLARE register CfbBits rrop_and; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; +#define RROP_SOLID(dst) (*(dst) &= (rrop_and)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) &= ((rrop_and) | ~(mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,And) +#endif /* GXand */ + +#if RROP == GXor +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_or; \ + CfbBits piQxelOr[3], spiQxelOr[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_or = (devPriv)->xor; \ + spiQxelOr[0] = rrop_or & 0xFFFFFF; \ + spiQxelOr[1] = rrop_or << 24; \ + spiQxelOr[2] = rrop_or << 16; \ + spiQxelOr[3] = rrop_or << 8; \ + spiQxelOr[4] = (rrop_or & 0xFFFF00)>> 8; \ + spiQxelOr[5] = (rrop_or & 0xFF0000)>> 16; \ + piQxelOr[0] = (rrop_or & 0xFFFFFF)|(rrop_or << 24); \ + piQxelOr[1] = (rrop_or << 16)|((rrop_or & 0xFFFF00)>> 8); \ + piQxelOr[2] = (rrop_or << 8)|((rrop_or & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) |= spiQxelOr[0]; \ + break; \ + case 3: \ + *(dst) |= spiQxelOr[3]; \ + break; \ + case 1: \ + *(dst) |= spiQxelOr[1]; \ + *((dst)+1) |= spiQxelOr[4]; \ + break; \ + case 2: \ + *(dst) |= spiQxelOr[2]; \ + *((dst)+1) |= spiQxelOr[5]; \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) |= piQxelOr[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) |= (piQxelOr[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelOr; (void)spiQxelOr; +#else +#define RROP_DECLARE register CfbBits rrop_or; +#define RROP_FETCH_GCPRIV(devPriv) rrop_or = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) |= (rrop_or)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) |= ((rrop_or) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Or) +#endif /* GXor */ + +#if RROP == GXnoop +#define RROP_DECLARE +#define RROP_FETCH_GCPRIV(devPriv) +#define RROP_SOLID(dst) +#define RROP_SOLID_MASK(dst,mask) +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Noop) +#define RROP_UNDECLARE +#endif /* GXnoop */ + +#if RROP == GXset +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_and, rrop_xor; \ + CfbBits piQxelAnd[3], piQxelXor[3], spiQxelAnd[6], spiQxelXor[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[1] = rrop_xor << 24; \ + spiQxelXor[2] = rrop_xor << 16; \ + spiQxelXor[3] = rrop_xor << 8; \ + spiQxelXor[4] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelAnd[0] = (rrop_and & 0xFFFFFF) | 0xFF000000; \ + spiQxelAnd[1] = (rrop_and << 24) | 0xFFFFFF; \ + spiQxelAnd[2] = (rrop_and << 16) | 0xFFFF; \ + spiQxelAnd[3] = (rrop_and << 8) | 0xFF; \ + spiQxelAnd[4] = ((rrop_and & 0xFFFF00)>> 8) | 0xFFFF0000; \ + spiQxelAnd[5] = ((rrop_and & 0xFF0000)>> 16) | 0xFFFFFF00; \ + piQxelAnd[0] = (rrop_and & 0xFFFFFF)|(rrop_and << 24); \ + piQxelAnd[1] = (rrop_and << 16)|((rrop_and & 0xFFFF00)>> 8); \ + piQxelAnd[2] = (rrop_and << 8)|((rrop_and & 0xFF0000)>> 16); \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) = ((*(dst) & (piQxelAnd[0] |0xFF000000))^(piQxelXor[0] & 0xFFFFFF)); \ + break; \ + case 3: \ + *(dst) = ((*(dst) & (piQxelAnd[2]|0xFF))^(piQxelXor[2] & 0xFFFFFF00)); \ + break; \ + case 1: \ + *(dst) = ((*(dst) & (piQxelAnd[0]|0xFFFFFF))^(piQxelXor[0] & 0xFF000000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[1]|0xFFFF0000))^(piQxelXor[1] & 0xFFFF)); \ + break; \ + case 2: \ + *(dst) = ((*(dst) & (piQxelAnd[1]|0xFFFF))^(piQxelXor[1] & 0xFFFF0000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[2]|0xFFFFFF00))^(piQxelXor[2] & 0xFF)); \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) = DoRRop (*(dst), piQxelAnd[(idx)], piQxelXor[(idx)])) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) = DoMaskRRop (*(dst), piQxelAnd[(idx)], piQxelXor[(idx)], (mask))) +#define RROP_UNDECLARE (void)piQxelAnd; (void)piQxelXor; \ + (void)spiQxelAnd; (void)spiQxelXor; +#else +#define RROP_DECLARE register CfbBits rrop_and, rrop_xor; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + rrop_xor = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) = DoRRop (*(dst), rrop_and, rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) = DoMaskRRop (*(dst), rrop_and, rrop_xor, (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,General) +#endif /* GXset */ + +#define RROP_UNROLL_CASE1(p,i) case (i): RROP_SOLID((p) - (i)); +#define RROP_UNROLL_CASE2(p,i) RROP_UNROLL_CASE1(p,(i)+1) RROP_UNROLL_CASE1(p,i) +#define RROP_UNROLL_CASE4(p,i) RROP_UNROLL_CASE2(p,(i)+2) RROP_UNROLL_CASE2(p,i) +#define RROP_UNROLL_CASE8(p,i) RROP_UNROLL_CASE4(p,(i)+4) RROP_UNROLL_CASE4(p,i) +#define RROP_UNROLL_CASE16(p,i) RROP_UNROLL_CASE8(p,(i)+8) RROP_UNROLL_CASE8(p,i) +#define RROP_UNROLL_CASE3(p) RROP_UNROLL_CASE2(p,2) RROP_UNROLL_CASE1(p,1) +#define RROP_UNROLL_CASE7(p) RROP_UNROLL_CASE4(p,4) RROP_UNROLL_CASE3(p) +#define RROP_UNROLL_CASE15(p) RROP_UNROLL_CASE8(p,8) RROP_UNROLL_CASE7(p) +#define RROP_UNROLL_CASE31(p) RROP_UNROLL_CASE16(p,16) RROP_UNROLL_CASE15(p) +#ifdef LONG64 +#define RROP_UNROLL_CASE63(p) RROP_UNROLL_CASE32(p,32) RROP_UNROLL_CASE31(p) +#endif /* LONG64 */ + +#define RROP_UNROLL_LOOP1(p,i) RROP_SOLID((p) + (i)); +#define RROP_UNROLL_LOOP2(p,i) RROP_UNROLL_LOOP1(p,(i)) RROP_UNROLL_LOOP1(p,(i)+1) +#define RROP_UNROLL_LOOP4(p,i) RROP_UNROLL_LOOP2(p,(i)) RROP_UNROLL_LOOP2(p,(i)+2) +#define RROP_UNROLL_LOOP8(p,i) RROP_UNROLL_LOOP4(p,(i)) RROP_UNROLL_LOOP4(p,(i)+4) +#define RROP_UNROLL_LOOP16(p,i) RROP_UNROLL_LOOP8(p,(i)) RROP_UNROLL_LOOP8(p,(i)+8) +#define RROP_UNROLL_LOOP32(p,i) RROP_UNROLL_LOOP16(p,(i)) RROP_UNROLL_LOOP16(p,(i)+16) +#ifdef LONG64 +#define RROP_UNROLL_LOOP64(p,i) RROP_UNROLL_LOOP32(p,(i)) RROP_UNROLL_LOOP32(p,(i)+32) +#endif /* LONG64 */ + +#if defined (FAST_CONSTANT_OFFSET_MODE) && defined (SHARED_IDCACHE) && (RROP == GXcopy) + +#ifdef LONG64 +#define RROP_UNROLL_SHIFT 6 +#define RROP_UNROLL_CASE(p) RROP_UNROLL_CASE63(p) +#define RROP_UNROLL_LOOP(p) RROP_UNROLL_LOOP64(p,-64) +#else /* not LONG64 */ +#define RROP_UNROLL_SHIFT 5 +#define RROP_UNROLL_CASE(p) RROP_UNROLL_CASE31(p) +#define RROP_UNROLL_LOOP(p) RROP_UNROLL_LOOP32(p,-32) +#endif /* LONG64 */ +#define RROP_UNROLL (1<>= RROP_UNROLL_SHIFT; \ + (pdst) += part * (sizeof (CfbBits) / sizeof (*pdst)); \ + switch (part) {\ + RROP_UNROLL_CASE((CfbBits *) (pdst)) \ + } \ + while (--(nmiddle) >= 0) { \ + (pdst) += RROP_UNROLL * (sizeof (CfbBits) / sizeof (*pdst)); \ + RROP_UNROLL_LOOP((CfbBits *) (pdst)) \ + } \ +} +#else +#define RROP_SPAN(pdst,nmiddle) \ + while (--(nmiddle) >= 0) { \ + RROP_SOLID((CfbBits *) (pdst)); \ + (pdst) += sizeof (CfbBits) / sizeof (*pdst); \ + } +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define RROP_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define RROP_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop24.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop24.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbrrop24.h (revision 51223) @@ -0,0 +1,54 @@ +/* $XFree86: xc/programs/Xserver/cfb24/cfbrrop24.h,v 3.1tsi Exp $ */ + +#define RROP_DECLARE \ + unsigned long piQxelAnd[3], piQxelXor[3], spiQxelXor[8]; + +#define RROP_COPY_SETUP(ptn) \ + spiQxelXor[0] = ptn & 0xFFFFFF; \ + spiQxelXor[2] = ptn << 24; \ + spiQxelXor[3] = (ptn & 0xFFFF00)>> 8; \ + spiQxelXor[4] = ptn << 16; \ + spiQxelXor[5] = (ptn & 0xFF0000)>> 16; \ + spiQxelXor[6] = ptn << 8; \ + spiQxelXor[1] = spiQxelXor[7] = 0; + +#define RROP_SOLID24_COPY(dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) = (*(dst) & cfbrmask[idx])|spiQxelXor[idx]; \ + idx++; \ + *((dst)+1) = (*((dst)+1) & cfbrmask[idx])|spiQxelXor[idx]; \ + } + +#define RROP_SET_SETUP(xor, and) \ + spiQxelXor[0] = xor & 0xFFFFFF; \ + spiQxelXor[1] = xor << 24; \ + spiQxelXor[2] = xor << 16; \ + spiQxelXor[3] = xor << 8; \ + spiQxelXor[4] = (xor >> 8) & 0xFFFF; \ + spiQxelXor[5] = (xor >> 16) & 0xFF; \ + piQxelAnd[0] = (and & 0xFFFFFF)|(and << 24); \ + piQxelAnd[1] = (and << 16)|((and >> 8) & 0xFFFF); \ + piQxelAnd[2] = (and << 8)|((and >> 16) & 0xFF); \ + piQxelXor[0] = (xor & 0xFFFFFF)|(xor << 24); \ + piQxelXor[1] = (xor << 16)|((xor >> 8) & 0xFFFF); \ + piQxelXor[2] = (xor << 8)|((xor >> 16) & 0xFF); + + +#define RROP_SOLID24_SET(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) = ((*(dst) & (piQxelAnd[0] |0xFF000000))^(piQxelXor[0] & 0xFFFFFF)); \ + break; \ + case 3: \ + *(dst) = ((*(dst) & (piQxelAnd[2]|0xFF))^(piQxelXor[2] & 0xFFFFFF00)); \ + break; \ + case 1: \ + *(dst) = ((*(dst) & (piQxelAnd[0]|0xFFFFFF))^(piQxelXor[0] & 0xFF000000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[1]|0xFFFF0000))^(piQxelXor[1] & 0xFFFF)); \ + break; \ + case 2: \ + *(dst) = ((*(dst) & (piQxelAnd[1]|0xFFFF))^(piQxelXor[1] & 0xFFFF0000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[2]|0xFFFFFF00))^(piQxelXor[2] & 0xFF)); \ + break; \ + } \ + } Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbtab.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbtab.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbtab.h (revision 51223) @@ -0,0 +1,16 @@ +/* $XFree86$ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _CFBTAB_H_ +#define _CFBTAB_H_ + +/* prototypes */ +#if 0 +extern int starttab[32], endtab[32]; +extern unsigned int partmasks[32][32]; +#endif + +#endif /* _CFBTAB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbunmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbunmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cfbunmap.h (revision 51223) @@ -0,0 +1,165 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfbunmap.h,v 1.6 2003/07/19 13:22:28 tsi Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +/* + * Unmap names + */ + +#undef CFBNAME +#undef CATNAME + +#undef QuartetBitsTable +#undef QuartetPixelMaskTable +#undef cfb8ClippedLineCopy +#undef cfb8ClippedLineGeneral +#undef cfb8ClippedLineXor +#undef cfb8LineSS1Rect +#undef cfb8LineSS1RectCopy +#undef cfb8LineSS1RectGeneral +#undef cfb8LineSS1RectPreviousCopy +#undef cfb8LineSS1RectXor +#undef cfb8SegmentSS1Rect +#undef cfb8SegmentSS1RectCopy +#undef cfb8SegmentSS1RectGeneral +#undef cfb8SegmentSS1RectShiftCopy +#undef cfb8SegmentSS1RectXor +#undef cfbAllocatePrivates +#undef cfbBSFuncRec +#undef cfbBitBlt +#undef cfbBresD +#undef cfbBresS +#undef cfbChangeWindowAttributes +#undef cfbClearVisualTypes +#undef cfbCloseScreen +#undef cfbCreateDefColormap +#undef cfbCopyArea +#undef cfbCopyImagePlane +#undef cfbCopyPixmap +#undef cfbCopyPlane +#undef cfbCopyPlaneReduce +#undef cfbCopyRotatePixmap +#undef cfbCopyWindow +#undef cfbCreateGC +#undef cfbCreatePixmap +#undef cfbCreateScreenResources +#undef cfbCreateWindow +#undef cfbDestroyPixmap +#undef cfbDestroyWindow +#undef cfbDoBitblt +#undef cfbDoBitbltCopy +#undef cfbDoBitbltGeneral +#undef cfbDoBitbltOr +#undef cfbDoBitbltXor +#undef cfbExpandDirectColors +#undef cfbFillBoxSolid +#undef cfbFillBoxTile32 +#undef cfbFillBoxTile32sCopy +#undef cfbFillBoxTile32sGeneral +#undef cfbFillBoxTileOdd +#undef cfbFillBoxTileOddCopy +#undef cfbFillBoxTileOddGeneral +#undef cfbFillPoly1RectCopy +#undef cfbFillPoly1RectGeneral +#undef cfbFillRectSolidCopy +#undef cfbFillRectSolidGeneral +#undef cfbFillRectSolidXor +#undef cfbFillRectTile32Copy +#undef cfbFillRectTile32General +#undef cfbFillRectTileOdd +#undef cfbFillSpanTile32sCopy +#undef cfbFillSpanTile32sGeneral +#undef cfbFillSpanTileOddCopy +#undef cfbFillSpanTileOddGeneral +#undef cfbFinishScreenInit +#undef cfbGCFuncs +#undef cfbGCPrivateIndex +#undef cfbGetImage +#undef cfbGetScreenPixmap +#undef cfbGetSpans +#undef cfbHorzS +#undef cfbImageGlyphBlt8 +#undef cfbInitializeColormap +#undef cfbInitVisuals +#undef cfbInstallColormap +#undef cfbLineSD +#undef cfbLineSS +#undef cfbListInstalledColormaps +#undef cfbMapWindow +#undef cfbMatchCommon +#undef cfbNonTEOps +#undef cfbNonTEOps1Rect +#undef cfbPadPixmap +#undef cfbPaintWindow +#undef cfbPolyFillArcSolidCopy +#undef cfbPolyFillArcSolidGeneral +#undef cfbPolyFillRect +#undef cfbPolyGlyphBlt8 +#undef cfbPolyGlyphRop8 +#undef cfbPolyPoint +#undef cfbPositionWindow +#undef cfbPutImage +#undef cfbReduceRasterOp +#undef cfbResolveColor +#undef cfbRestoreAreas +#undef cfbSaveAreas +#undef cfbScreenInit +#undef cfbScreenPrivateIndex +#undef cfbSegmentSD +#undef cfbSegmentSS +#undef cfbSetScanline +#undef cfbSetScreenPixmap +#undef cfbSetSpans +#undef cfbSetVisualTypes +#undef cfbSetupScreen +#undef cfbSolidSpansCopy +#undef cfbSolidSpansGeneral +#undef cfbSolidSpansXor +#undef cfbStippleStack +#undef cfbStippleStackTE +#undef cfbTEGlyphBlt +#undef cfbTEOps +#undef cfbTEOps1Rect +#undef cfbTile32FSCopy +#undef cfbTile32FSGeneral +#undef cfbUninstallColormap +#undef cfbUnmapWindow +#undef cfbUnnaturalStippleFS +#undef cfbUnnaturalTileFS +#undef cfbValidateGC +#undef cfbVertS +#undef cfbWindowPrivateIndex +#undef cfbXRotatePixmap +#undef cfbYRotatePixmap +#undef cfbZeroPolyArcSS8Copy +#undef cfbZeroPolyArcSS8General +#undef cfbZeroPolyArcSS8Xor +#undef cfbendpartial +#undef cfbendtab +#undef cfbmask +#undef cfbrmask +#undef cfbstartpartial +#undef cfbstarttab Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgdctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgdctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgdctl.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgdctl.h,v 3.1 1996/04/15 11:18:25 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGDCTL_H +#define CHGDCTL_H 1 + +int +SProcXChangeDeviceControl( + ClientPtr /* client */ + ); + +int +ProcXChangeDeviceControl( + ClientPtr /* client */ + ); + +void +SRepXChangeDeviceControl ( + ClientPtr /* client */, + int /* size */, + xChangeDeviceControlReply * /* rep */ + ); + +#endif /* CHGDCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgfctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgfctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgfctl.h (revision 51223) @@ -0,0 +1,98 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgfctl.h,v 3.1 1996/04/15 11:18:26 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGFCTL_H +#define CHGFCTL_H 1 + +int +SProcXChangeFeedbackControl( + ClientPtr /* client */ + ); + +int +ProcXChangeFeedbackControl( + ClientPtr /* client */ + ); + +int +ChangeKbdFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + KbdFeedbackPtr /* k */, + xKbdFeedbackCtl * /* f */ + ); + +int +ChangePtrFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + PtrFeedbackPtr /* p */, + xPtrFeedbackCtl * /* f */ + ); + +int +ChangeIntegerFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + IntegerFeedbackPtr /* i */, + xIntegerFeedbackCtl * /* f */ + ); + +int +ChangeStringFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + StringFeedbackPtr /* s */, + xStringFeedbackCtl * /* f */ + ); + +int +ChangeBellFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + BellFeedbackPtr /* b */, + xBellFeedbackCtl * /* f */ + ); + +int +ChangeLedFeedback ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned long /* mask */, + LedFeedbackPtr /* l */, + xLedFeedbackCtl * /* f */ + ); + +#endif /* CHGFCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkbd.h (revision 51223) @@ -0,0 +1,52 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgkbd.h,v 3.1 1996/04/15 11:18:27 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGKBD_H +#define CHGKBD_H 1 + +int +SProcXChangeKeyboardDevice( + ClientPtr /* client */ + ); + +int +ProcXChangeKeyboardDevice ( + ClientPtr /* client */ + ); + +void +SRepXChangeKeyboardDevice ( + ClientPtr /* client */, + int /* size */, + xChangeKeyboardDeviceReply * /* rep */ + ); + + +#endif /* CHGKBD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgkmap.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgkmap.h,v 3.1 1996/04/15 11:18:28 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGKMAP_H +#define CHGKMAP_H 1 + +int +SProcXChangeDeviceKeyMapping( + ClientPtr /* client */ + ); + +int +ProcXChangeDeviceKeyMapping( + ClientPtr /* client */ + ); + +#endif /* CHGKMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgprop.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgprop.h,v 3.1 1996/04/15 11:18:29 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGPROP_H +#define CHGPROP_H 1 + +int +SProcXChangeDeviceDontPropagateList ( + ClientPtr /* client */ + ); + +int +ProcXChangeDeviceDontPropagateList ( + ClientPtr /* client */ + ); + +#endif /* CHGPROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgptr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgptr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/chgptr.h (revision 51223) @@ -0,0 +1,73 @@ +/* $XFree86: xc/programs/Xserver/Xi/chgptr.h,v 3.1 1996/04/15 11:18:31 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGPTR_H +#define CHGPTR_H 1 + +int +SProcXChangePointerDevice( + ClientPtr /* client */ + ); + +int +ProcXChangePointerDevice ( + ClientPtr /* client */ + ); + +void +DeleteFocusClassDeviceStruct( + DeviceIntPtr /* dev */ + ); + +void +SendEventToAllWindows ( + DeviceIntPtr /* dev */, + Mask /* mask */, + xEvent * /* ev */, + int /* count */ + ); + +void +FindInterestedChildren ( /* FIXME: could be static? */ + DeviceIntPtr /* dev */, + WindowPtr /* p1 */, + Mask /* mask */, + xEvent * /* ev */, + int /* count */ + ); + +void +SRepXChangePointerDevice ( + ClientPtr /* client */, + int /* size */, + xChangePointerDeviceReply * /* rep */ + ); + +#endif /* CHGPTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closedev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closedev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closedev.h (revision 51223) @@ -0,0 +1,58 @@ +/* $XFree86: xc/programs/Xserver/Xi/closedev.h,v 3.1 1996/04/15 11:18:32 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CLOSEDEV_H +#define CLOSEDEV_H 1 + +int +SProcXCloseDevice( + ClientPtr /* client */ + ); + +int +ProcXCloseDevice( + ClientPtr /* client */ + ); + +void +DeleteEventsFromChildren( + DeviceIntPtr /* dev */, + WindowPtr /* p1 */, + ClientPtr /* client */ + ); + +void +DeleteDeviceEvents ( + DeviceIntPtr /* dev */, + WindowPtr /* pWin */, + ClientPtr /* client */ + ); + +#endif /* CLOSEDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closestr.h (revision 51223) @@ -0,0 +1,159 @@ +/* $Xorg: closestr.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ +/* + +Copyright 1991, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/include/closestr.h,v 3.4 2001/12/14 19:59:53 dawes Exp $ */ + + +#ifndef CLOSESTR_H +#define CLOSESTR_H + +#define NEED_REPLIES +#include +#include "closure.h" +#include "dix.h" +#include "misc.h" +#include "gcstruct.h" + +/* closure structures */ + +/* OpenFont */ + +typedef struct _OFclosure { + ClientPtr client; + short current_fpe; + short num_fpes; + FontPathElementPtr *fpe_list; + Mask flags; + Bool slept; + +/* XXX -- get these from request buffer instead? */ + char *origFontName; + int origFontNameLen; + XID fontid; + char *fontname; + int fnamelen; + FontPtr non_cachable_font; +} OFclosureRec; + +/* ListFontsWithInfo */ + +#define XLFDMAXFONTNAMELEN 256 +typedef struct _LFWIstate { + char pattern[XLFDMAXFONTNAMELEN]; + int patlen; + int current_fpe; + int max_names; + Bool list_started; + pointer private; +} LFWIstateRec, *LFWIstatePtr; + +typedef struct _LFWIclosure { + ClientPtr client; + int num_fpes; + FontPathElementPtr *fpe_list; + xListFontsWithInfoReply *reply; + int length; + LFWIstateRec current; + LFWIstateRec saved; + int savedNumFonts; + Bool haveSaved; + Bool slept; + char *savedName; +} LFWIclosureRec; + +/* ListFonts */ + +typedef struct _LFclosure { + ClientPtr client; + int num_fpes; + FontPathElementPtr *fpe_list; + FontNamesPtr names; + LFWIstateRec current; + LFWIstateRec saved; + Bool haveSaved; + Bool slept; + char *savedName; + int savedNameLen; +} LFclosureRec; + +/* PolyText */ + +typedef + int (* PolyTextPtr)( + DrawablePtr /* pDraw */, + GCPtr /* pGC */, + int /* x */, + int /* y */, + int /* count */, + void * /* chars or shorts */ + ); + +typedef struct _PTclosure { + ClientPtr client; + DrawablePtr pDraw; + GC *pGC; + unsigned char *pElt; + unsigned char *endReq; + unsigned char *data; + int xorg; + int yorg; + CARD8 reqType; + PolyTextPtr polyText; + int itemSize; + XID did; + int err; + Bool slept; +} PTclosureRec; + +/* ImageText */ + +typedef + void (* ImageTextPtr)( + DrawablePtr /* pDraw */, + GCPtr /* pGC */, + int /* x */, + int /* y */, + int /* count */, + void * /* chars or shorts */ + ); + +typedef struct _ITclosure { + ClientPtr client; + DrawablePtr pDraw; + GC *pGC; + BYTE nChars; + unsigned char *data; + int xorg; + int yorg; + CARD8 reqType; + ImageTextPtr imageText; + int itemSize; + XID did; + Bool slept; +} ITclosureRec; +#endif /* CLOSESTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closure.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closure.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/closure.h (revision 51223) @@ -0,0 +1,58 @@ +/* $Xorg: closure.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef CLOSURE_H +#define CLOSURE_H 1 + +typedef struct _LFclosure *LFclosurePtr; +typedef struct _LFWIclosure *LFWIclosurePtr; +typedef struct _OFclosure *OFclosurePtr; +typedef struct _PTclosure *PTclosurePtr; +typedef struct _ITclosure *ITclosurePtr; + +#endif /* CLOSURE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coff.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coff.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coff.h (revision 51223) @@ -0,0 +1,237 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/coff.h,v 1.5 1998/07/25 16:56:12 dawes Exp $ */ + +/* This file was implemented from the information in the book + Understanding and Using COFF + Gintaras R. Gircys + O'Reilly, 1988 + and by looking at the Linux kernel code. + + It is therefore most likely free to use... + + If the file format changes in the COFF object, this file should be + subsequently updated to reflect the changes. + + The actual loader module only uses a few of the COFF structures. + Only those are included here. If you wish more information about + COFF, thein check out the book mentioned above. +*/ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _COFF_H +#define _COFF_H + +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ +/* + * Intel 386/486 + */ + +/* + * FILE HEADER + */ + +typedef struct COFF_filehdr { + unsigned short f_magic; /* magic number */ + unsigned short f_nscns; /* number of sections */ + long f_timdat; /* time & date stamp */ + long f_symptr; /* file pointer to symtab */ + long f_nsyms; /* number of symtab entries */ + unsigned short f_opthdr; /* sizeof(optional hdr) */ + unsigned short f_flags; /* flags */ +} FILHDR; + +#define FILHSZ sizeof(FILHDR) + +/* + * SECTION HEADER + */ + +typedef struct COFF_scnhdr { + char s_name[8]; /* section name */ + long s_paddr; /* physical address */ + long s_vaddr; /* virtual address */ + long s_size; /* section size */ + long s_scnptr; /* raw data for section */ + long s_relptr; /* relocation */ + long s_lnnoptr; /* line numbers */ + unsigned short s_nreloc; /* number of relocation entries */ + unsigned short s_nlnno; /* number of line number entries */ + long s_flags; /* flags */ +} SCNHDR; + +#define COFF_SCNHDR struct COFF_scnhdr +#define COFF_SCNHSZ sizeof(COFF_SCNHDR) +#define SCNHSZ COFF_SCNHSZ + +/* + * the optional COFF header as used by Linux COFF + */ + +typedef struct { + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes */ + char dsize[4]; /* initialized data */ + char bsize[4]; /* uninitialized data */ + char entry[4]; /* entry point */ + char text_start[4]; /* base of text */ + char data_start[4]; /* base of data */ +} AOUTHDR; + +/* + * SYMBOLS + */ + +typedef struct COFF_syment { + union { + char _n_name[E_SYMNMLEN]; /* Symbol name (first 8 chars) */ + struct { + long _n_zeroes; /* Leading zeros */ + long _n_offset; /* Offset for a header section */ + } _n_n; + char *_n_nptr[2]; /* allows for overlaying */ + } _n; + + long n_value; /* address of the segment */ + short n_scnum; /* Section number */ + unsigned short n_type; /* Type of section */ + char n_sclass; /* Loader class */ + char n_numaux; /* Number of aux entries following */ +} SYMENT; + +#define n_name _n._n_name +#define n_nptr _n._n_nptr[1] +#define n_zeroes _n._n_n._n_zeroes +#define n_offset _n._n_n._n_offset + +#define COFF_E_SYMNMLEN 8 /* characters in a short symbol name */ +#define COFF_E_FILNMLEN 14 /* characters in a file name */ +#define COFF_E_DIMNUM 4 /* array dimensions in aux entry */ +#define SYMNMLEN COFF_E_SYMNMLEN +#define SYMESZ 18 /* not really sizeof(SYMENT) due to padding */ + +/* Special section number found in the symbol section */ +#define N_UNDEF 0 +#define N_ABS -1 +#define N_DEBUG -2 + +/* Symbol storage class values */ +#define C_NULL 0 +#define C_EXT 2 +#define C_FILE 103 +#define C_HIDEXT 107 + +/* + * AUX Entries + */ +typedef struct COFF_auxent { + long x_scnlen; + long x_parmhash; + unsigned short x_snhash; + unsigned char x_smtyp; + unsigned char x_smclas; + long x_stab; + unsigned short x_snstab; +} AUXENT; + +/* Auxillary Symbol type values */ +#define XTY_ER 0 /* Enternal Reference */ +#define XTY_SD 1 /* csect section definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* common csect definition */ + +/* Auxillary Symbol storage mapping class values */ +#define XMC_PR 0 /* Program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Debug dictionary */ +#define XMC_TC 3 /* TOC entry */ +#define XMC_UA 4 /* Unclassified */ +#define XMC_RW 5 /* Read/write data */ +#define XMC_GL 6 /* Global linkage */ +#define XMC_XO 7 /* Extended operation */ +#define XMC_SV 8 /* Supervisor call descriptor */ +#define XMC_BS 9 /* BSS class */ +#define XMC_DS 10 /* Function descriptor csect */ +#define XMC_UC 11 /* Unnamed FORTRAN comon */ +#define XMC_TI 12 /* Reserved */ +#define XMC_TB 13 /* Reserved */ +#define XMC_TC0 15 /* TOC anchor */ +#define XMC_TD 16 /* Scalar data entry in TOC */ + +/* + * RELOCATION DIRECTIVES + */ + +typedef struct COFF_reloc { + long r_vaddr; /* Virtual address of item */ + long r_symndx; /* Symbol index in the symtab */ +#if defined(__powerpc__) + union { + unsigned short _r_type; /* old style coff relocation type */ + struct { + char _r_rsize; /* sign and reloc bit len */ + char _r_rtype; /* toc relocation type */ + } _r_r; + } _r; +#define r_otype _r._r_type /* old style reloc - original name */ +#define r_rsize _r._r_r._r_rsize /* extract sign and bit len */ +#define r_type _r._r_r._r_rtype /* extract toc relocation type */ +#else + unsigned short r_type; /* Relocation type */ +#endif +} RELOC; + +#define COFF_RELOC struct COFF_reloc +#define COFF_RELSZ 10 +#define RELSZ COFF_RELSZ + +/* + * x86 Relocation types + */ +#define R_ABS 000 +#define R_DIR32 006 +#define R_PCRLONG 024 + +#if defined(__powerpc__) +/* + * Power PC + */ +#define R_LEN 0x1F /* extract bit-length field */ +#define R_SIGN 0x80 /* extract sign of relocation */ +#define R_FIXUP 0x40 /* extract code-fixup bit */ + +#define RELOC_RLEN(x) ((x)._r._r_r._r_rsize & R_LEN) +#define RELOC_RSIGN(x) ((x)._r._r_r._r_rsize & R_SIGN) +#define RELOC_RFIXUP(x) ((x)._r._r_r._r_rsize & R_FIXUP) +#define RELOC_RTYPE(x) ((x)._r._r_r._r_rtype) + +/* + * POWER and PowerPC - relocation types + */ +#define R_POS 0x00 /* A(sym) Positive Relocation */ +#define R_NEG 0x01 /* -A(sym) Negative Relocation */ +#define R_REL 0x02 /* A(sym-*) Relative to self */ +#define R_TOC 0x03 /* A(sym-TOC) Relative to TOC */ +#define R_TRL 0x12 /* A(sym-TOC) TOC Relative indirect load. */ + /* modifiable instruction */ +#define R_TRLA 0x13 /* A(sym-TOC) TOC Rel load address. modifiable inst */ +#define R_GL 0x05 /* A(external TOC of sym) Global Linkage */ +#define R_TCL 0x06 /* A(local TOC of sym) Local object TOC address */ +#define R_RL 0x0C /* A(sym) Pos indirect load. modifiable instruction */ +#define R_RLA 0x0D /* A(sym) Pos Load Address. modifiable instruction */ +#define R_REF 0x0F /* AL0(sym) Non relocating ref. No garbage collect */ +#define R_BA 0x08 /* A(sym) Branch absolute. Cannot modify instruction */ +#define R_RBA 0x18 /* A(sym) Branch absolute. modifiable instruction */ +#define R_RBAC 0x19 /* A(sym) Branch absolute constant. modifiable instr */ +#define R_BR 0x0A /* A(sym-*) Branch rel to self. non modifiable */ +#define R_RBR 0x1A /* A(sym-*) Branch rel to self. modifiable instr */ +#define R_RBRC 0x1B /* A(sym-*) Branch absolute const. */ + /* modifiable to R_RBR */ +#define R_RTB 0x04 /* A((sym-*)/2) RT IAR Rel Branch. non modifiable */ +#define R_RRTBI 0x14 /* A((sym-*)/2) RT IAR Rel Br. modifiable to R_RRTBA */ +#define R_RRTBA 0x15 /* A((sym-*)/2) RT absolute br. modifiable to R_RRTBI */ +#endif /* __powerpc */ + +#endif /* _COFF_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coffloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coffloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/coffloader.h (revision 51223) @@ -0,0 +1,38 @@ +/* + * + * Copyright 1997,1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/coffloader.h,v 1.3 1998/09/20 14:41:04 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _COFFLOADER_H +#define _COFFLOADER_H +/* coffloader.c */ +extern void *COFFLoadModule(loaderPtr, int, LOOKUP **); +extern void COFFResolveSymbols(void *); +extern int COFFCheckForUnresolved(void *); +extern char *COFFAddressToSection(void *, unsigned long); +extern void COFFUnloadModule(void *); +#endif /* _COFFLOADER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormap.h (revision 51223) @@ -0,0 +1,184 @@ +/* $XFree86: xc/programs/Xserver/include/colormap.h,v 1.5 2001/12/14 19:59:53 dawes Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +*/ +/* $Xorg: colormap.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ + +#ifndef CMAP_H +#define CMAP_H 1 + +#include +#include "screenint.h" +#include "window.h" + +/* these follow X.h's AllocNone and AllocAll */ +#define CM_PSCREEN 2 +#define CM_PWIN 3 +/* Passed internally in colormap.c */ +#define REDMAP 0 +#define GREENMAP 1 +#define BLUEMAP 2 +#define PSEUDOMAP 3 +#define AllocPrivate (-1) +#define AllocTemporary (-2) +#define DynamicClass 1 + +/* Values for the flags field of a colormap. These should have 1 bit set + * and not overlap */ +#define IsDefault 1 +#define AllAllocated 2 +#define BeingCreated 4 + + +typedef CARD32 Pixel; +typedef struct _CMEntry *EntryPtr; +/* moved to screenint.h: typedef struct _ColormapRec *ColormapPtr */ +typedef struct _colorResource *colorResourcePtr; + +extern int CreateColormap( + Colormap /*mid*/, + ScreenPtr /*pScreen*/, + VisualPtr /*pVisual*/, + ColormapPtr* /*ppcmap*/, + int /*alloc*/, + int /*client*/); + +extern int FreeColormap( + pointer /*pmap*/, + XID /*mid*/); + +extern int TellLostMap( + WindowPtr /*pwin*/, + pointer /* Colormap *pmid */); + +extern int TellGainedMap( + WindowPtr /*pwin*/, + pointer /* Colormap *pmid */); + +extern int CopyColormapAndFree( + Colormap /*mid*/, + ColormapPtr /*pSrc*/, + int /*client*/); + +extern int AllocColor( + ColormapPtr /*pmap*/, + unsigned short* /*pred*/, + unsigned short* /*pgreen*/, + unsigned short* /*pblue*/, + Pixel* /*pPix*/, + int /*client*/); + +extern void FakeAllocColor( + ColormapPtr /*pmap*/, + xColorItem * /*item*/); + +extern void FakeFreeColor( + ColormapPtr /*pmap*/, + Pixel /*pixel*/); + +typedef int (*ColorCompareProcPtr)( + EntryPtr /*pent*/, + xrgb * /*prgb*/); + +extern int FindColor( + ColormapPtr /*pmap*/, + EntryPtr /*pentFirst*/, + int /*size*/, + xrgb* /*prgb*/, + Pixel* /*pPixel*/, + int /*channel*/, + int /*client*/, + ColorCompareProcPtr /*comp*/); + +extern int QueryColors( + ColormapPtr /*pmap*/, + int /*count*/, + Pixel* /*ppixIn*/, + xrgb* /*prgbList*/); + +extern int FreeClientPixels( + pointer /*pcr*/, + XID /*fakeid*/); + +extern int AllocColorCells( + int /*client*/, + ColormapPtr /*pmap*/, + int /*colors*/, + int /*planes*/, + Bool /*contig*/, + Pixel* /*ppix*/, + Pixel* /*masks*/); + +extern int AllocColorPlanes( + int /*client*/, + ColormapPtr /*pmap*/, + int /*colors*/, + int /*r*/, + int /*g*/, + int /*b*/, + Bool /*contig*/, + Pixel* /*pixels*/, + Pixel* /*prmask*/, + Pixel* /*pgmask*/, + Pixel* /*pbmask*/); + +extern int FreeColors( + ColormapPtr /*pmap*/, + int /*client*/, + int /*count*/, + Pixel* /*pixels*/, + Pixel /*mask*/); + +extern int StoreColors( + ColormapPtr /*pmap*/, + int /*count*/, + xColorItem* /*defs*/); + +extern int IsMapInstalled( + Colormap /*map*/, + WindowPtr /*pWin*/); + +#endif /* CMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormapst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormapst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/colormapst.h (revision 51223) @@ -0,0 +1,121 @@ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +*/ +/* $Xorg: colormapst.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ + +#ifndef CMAPSTRUCT_H +#define CMAPSTRUCT_H 1 + +#include "colormap.h" +#include "screenint.h" + +/* Shared color -- the color is used by AllocColorPlanes */ +typedef struct +{ + unsigned short color; + short refcnt; +} SHAREDCOLOR; + +/* LOCO -- a local color for a PseudoColor cell. DirectColor maps always + * use the first value (called red) in the structure. What channel they + * are really talking about depends on which map they are in. */ +typedef struct +{ + unsigned short red, green, blue; +} LOCO; + +/* SHCO -- a shared color for a PseudoColor cell. Used with AllocColorPlanes. + * DirectColor maps always use the first value (called red) in the structure. + * What channel they are really talking about depends on which map they + * are in. */ +typedef struct +{ + SHAREDCOLOR *red, *green, *blue; +} SHCO; + + +/* color map entry */ +typedef struct _CMEntry +{ + union + { + LOCO local; + SHCO shco; + } co; + short refcnt; + Bool fShared; +} Entry; + +/* COLORMAPs can be used for either Direct or Pseudo color. PseudoColor + * only needs one cell table, we arbitrarily pick red. We keep track + * of that table with freeRed, numPixelsRed, and clientPixelsRed */ + +typedef struct _ColormapRec +{ + VisualPtr pVisual; + short class; /* PseudoColor or DirectColor */ + long mid; /* client's name for colormap */ + ScreenPtr pScreen; /* screen map is associated with */ + short flags; /* 1 = IsDefault + * 2 = AllAllocated */ + int freeRed; + int freeGreen; + int freeBlue; + int *numPixelsRed; + int *numPixelsGreen; + int *numPixelsBlue; + Pixel **clientPixelsRed; + Pixel **clientPixelsGreen; + Pixel **clientPixelsBlue; + Entry *red; + Entry *green; + Entry *blue; + pointer devPriv; + DevUnion *devPrivates; /* dynamic devPrivates added after devPriv + already existed - must keep devPriv */ +} ColormapRec; + +#endif /* COLORMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compiler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compiler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compiler.h (revision 51223) @@ -0,0 +1,1863 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/compiler.h,v 3.106 2004/02/02 03:55:28 dawes Exp $ */ +/* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Thomas Roell makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: compiler.h /main/16 1996/10/25 15:38:34 kaleb $ */ + +#ifndef _COMPILER_H + +# if !defined(_XF86_ANSIC_H) && defined(XFree86Module) +# error missing #include "xf86_ansic.h" before #include "compiler.h" +# endif + +# define _COMPILER_H + +#if defined(__SUNPRO_C) +# define DO_PROTOTYPES +#endif + +/* Allow drivers to use the GCC-supported __inline__ and/or __inline. */ +# ifndef __inline__ +# if defined(__GNUC__) + /* gcc has __inline__ */ +# elif defined(__HIGHC__) +# define __inline__ _Inline +# else +# define __inline__ /**/ +# endif +# endif /* __inline__ */ +# ifndef __inline +# if defined(__GNUC__) + /* gcc has __inline */ +# elif defined(__HIGHC__) +# define __inline _Inline +# else +# define __inline /**/ +# endif +# endif /* __inline */ + +# if defined(IODEBUG) && defined(__GNUC__) +# define outb RealOutb +# define outw RealOutw +# define outl RealOutl +# define inb RealInb +# define inw RealInw +# define inl RealInl +# endif + +# if defined(QNX4) /* Do this for now to keep Watcom happy */ +# define outb outp +# define outw outpw +# define outl outpd +# define inb inp +# define inw inpw +# define inl inpd + +/* Define the ffs function for inlining */ +extern int ffs(unsigned long); +# pragma aux ffs_ = \ + "bsf edx, eax" \ + "jnz bits_set" \ + "xor eax, eax" \ + "jmp exit1" \ + "bits_set:" \ + "mov eax, edx" \ + "inc eax" \ + "exit1:" \ + __parm [eax] \ + __modify [eax edx] \ + __value [eax] \ + ; +# endif + +# if defined(__SUNPRO_C) +# define DO_PROTOTYPES +# endif + +# if defined(NO_INLINE) || defined(DO_PROTOTYPES) + +# if !defined(__arm__) +# if !defined(__sparc__) && !defined(__arm32__) \ + && !(defined(__alpha__) && defined(linux)) \ + && !(defined(__ia64__) && defined(linux)) \ + +extern void outb(unsigned short, unsigned char); +extern void outw(unsigned short, unsigned short); +extern void outl(unsigned short, unsigned int); +extern unsigned int inb(unsigned short); +extern unsigned int inw(unsigned short); +extern unsigned int inl(unsigned short); + +# else /* __sparc__, __arm32__, __alpha__*/ + +extern void outb(unsigned long, unsigned char); +extern void outw(unsigned long, unsigned short); +extern void outl(unsigned long, unsigned int); +extern unsigned int inb(unsigned long); +extern unsigned int inw(unsigned long); +extern unsigned int inl(unsigned long); + +# endif /* __sparc__, __arm32__, __alpha__ */ +# endif /* __arm__ */ + +extern unsigned long ldq_u(unsigned long *); +extern unsigned long ldl_u(unsigned int *); +extern unsigned long ldw_u(unsigned short *); +extern void stq_u(unsigned long, unsigned long *); +extern void stl_u(unsigned long, unsigned int *); +extern void stw_u(unsigned long, unsigned short *); +extern void mem_barrier(void); +extern void write_mem_barrier(void); +extern void stl_brx(unsigned long, volatile unsigned char *, int); +extern void stw_brx(unsigned short, volatile unsigned char *, int); +extern unsigned long ldl_brx(volatile unsigned char *, int); +extern unsigned short ldw_brx(volatile unsigned char *, int); + +# endif + +# ifndef NO_INLINE +# ifdef __GNUC__ +# if (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) && (defined(__alpha__)) + +# ifdef linux +/* for Linux on Alpha, we use the LIBC _inx/_outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +extern void (*_alpha_outb)(char val, unsigned long port); +static __inline__ void +outb(unsigned long port, unsigned char val) +{ + _alpha_outb(val, port); +} + +extern void (*_alpha_outw)(short val, unsigned long port); +static __inline__ void +outw(unsigned long port, unsigned short val) +{ + _alpha_outw(val, port); +} + +extern void (*_alpha_outl)(int val, unsigned long port); +static __inline__ void +outl(unsigned long port, unsigned int val) +{ + _alpha_outl(val, port); +} + +extern unsigned int (*_alpha_inb)(unsigned long port); +static __inline__ unsigned int +inb(unsigned long port) +{ + return _alpha_inb(port); +} + +extern unsigned int (*_alpha_inw)(unsigned long port); +static __inline__ unsigned int +inw(unsigned long port) +{ + return _alpha_inw(port); +} + +extern unsigned int (*_alpha_inl)(unsigned long port); +static __inline__ unsigned int +inl(unsigned long port) +{ + return _alpha_inl(port); +} + +# endif /* linux */ + +# if (defined(__FreeBSD__) || defined(__OpenBSD__)) \ + && !defined(DO_PROTOTYPES) + +/* for FreeBSD and OpenBSD on Alpha, we use the libio (resp. libalpha) */ +/* inx/outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +extern void outb(unsigned int port, unsigned char val); +extern void outw(unsigned int port, unsigned short val); +extern void outl(unsigned int port, unsigned int val); +extern unsigned char inb(unsigned int port); +extern unsigned short inw(unsigned int port); +extern unsigned int inl(unsigned int port); + +# endif /* (__FreeBSD__ || __OpenBSD__ ) && !DO_PROTOTYPES */ + + +#if defined(__NetBSD__) +#include +#endif /* __NetBSD__ */ + +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +/* + * Elemental unaligned loads + */ +/* let's try making these things static */ + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +# endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +# endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +# endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +/* to flush the I-cache before jumping to code which just got loaded */ +# define PAL_imb 134 +# define istream_mem_barrier() \ + __asm__ __volatile__("call_pal %0 #imb" : : "i" (PAL_imb) : "memory") +# define mem_barrier() __asm__ __volatile__("mb" : : : "memory") +# ifdef __ELF__ +# define write_mem_barrier() __asm__ __volatile__("wmb" : : : "memory") +# else /* ECOFF gas 2.6 doesn't know "wmb" :-( */ +# define write_mem_barrier() mem_barrier() +# endif + + +# elif defined(linux) && defined(__ia64__) + +# include + +# include + +struct __una_u64 { uint64_t x __attribute__((packed)); }; +struct __una_u32 { uint32_t x __attribute__((packed)); }; +struct __una_u16 { uint16_t x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +__uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +__uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +__ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +__ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +__ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +# define ldq_u(p) __uldq(p) +# define ldl_u(p) __uldl(p) +# define ldw_u(p) __uldw(p) +# define stq_u(v,p) __ustq(v,p) +# define stl_u(v,p) __ustl(v,p) +# define stw_u(v,p) __ustw(v,p) + +# ifndef __INTEL_COMPILER +# define mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") +# define write_mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") +# else +# include "ia64intrin.h" +# define mem_barrier() __mf() +# define write_mem_barrier() __mf() +# endif + +/* + * This is overkill, but for different reasons depending on where it is used. + * This is thus general enough to be used everywhere cache flushes are needed. + * It doesn't handle memory access serialisation by other processors, though. + */ +# ifndef __INTEL_COMPILER +# define ia64_flush_cache(Addr) \ + __asm__ __volatile__ ( \ + "fc.i %0;;;" \ + "sync.i;;;" \ + "mf;;;" \ + "srlz.i;;;" \ + :: "r"(Addr) : "memory") +# else +# define ia64_flush_cache(Addr) { \ + __fc(Addr);\ + __synci();\ + __mf();\ + __isrlz();\ + } +# endif +# undef outb +# undef outw +# undef outl +# undef inb +# undef inw +# undef inl +extern void outb(unsigned long port, unsigned char val); +extern void outw(unsigned long port, unsigned short val); +extern void outl(unsigned long port, unsigned int val); +extern unsigned int inb(unsigned long port); +extern unsigned int inw(unsigned long port); +extern unsigned int inl(unsigned long port); + +# elif defined(linux) && defined(__amd64__) + +# include + +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) + +# define mem_barrier() \ + __asm__ __volatile__ ("lock; addl $0,0(%%rsp)": : :"memory") +# define write_mem_barrier() \ + __asm__ __volatile__ ("": : :"memory") + + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# elif (defined(linux) || defined(Lynx) || defined(sun) || defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc__) + +# if !defined(Lynx) +# ifndef ASI_PL +# define ASI_PL 0x88 +# endif + +# define barrier() __asm__ __volatile__(".word 0x8143e00a": : :"memory") + +static __inline__ void +outb(unsigned long port, unsigned char val) +{ + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +outw(unsigned long port, unsigned short val) +{ + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +outl(unsigned long port, unsigned int val) +{ + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ unsigned int +inb(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lda [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned char +xf86ReadMmio8(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned char ret; + + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned short +xf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned short ret; + + __asm__ __volatile__("lduh [%1], %0" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ unsigned short +xf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned short ret; + + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("ld [%1], %0" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ unsigned int +xf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("lda [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ void +xf86WriteMmio8(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sth %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); + barrier(); +} + +static __inline__ void +xf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("st %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); + barrier(); +} + +static __inline__ void +xf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio8NB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +static __inline__ void +xf86WriteMmio16BeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sth %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); +} + +static __inline__ void +xf86WriteMmio16LeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +static __inline__ void +xf86WriteMmio32BeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("st %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); +} + +static __inline__ void +xf86WriteMmio32LeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +# endif /* !Lynx */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +# if defined(__arch64__) || defined(__sparcv9) +struct __una_u64 { unsigned long x __attribute__((packed)); }; +# endif +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long ldq_u(unsigned long *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +# if defined(__arch64__) || defined(__sparcv9) + const struct __una_u64 *ptr = (const struct __una_u64 *) p; +# else + const struct __una_u32 *ptr = (const struct __una_u32 *) p; +# endif + return ptr->x; +# else + unsigned long ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ unsigned long ldl_u(unsigned int *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) p; + return ptr->x; +# else + unsigned int ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ unsigned long ldw_u(unsigned short *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) p; + return ptr->x; +# else + unsigned short ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ void stq_u(unsigned long val, unsigned long *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +# if defined(__arch64__) || defined(__sparcv9) + struct __una_u64 *ptr = (struct __una_u64 *) p; +# else + struct __una_u32 *ptr = (struct __una_u32 *) p; +# endif + ptr->x = val; +# else + unsigned long tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +static __inline__ void stl_u(unsigned long val, unsigned int *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) p; + ptr->x = val; +# else + unsigned int tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +static __inline__ void stw_u(unsigned long val, unsigned short *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) p; + ptr->x = val; +# else + unsigned short tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +# define mem_barrier() /* XXX: nop for now */ +# define write_mem_barrier() /* XXX: nop for now */ + +# elif defined(__mips__) || (defined(__arm32__) && !defined(__linux__)) +# ifdef __arm32__ +# define PORT_SIZE long +# else +# define PORT_SIZE short +# endif + +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void +outb(unsigned PORT_SIZE port, unsigned char val) +{ + *(volatile unsigned char*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ void +outw(unsigned PORT_SIZE port, unsigned short val) +{ + *(volatile unsigned short*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ void +outl(unsigned PORT_SIZE port, unsigned int val) +{ + *(volatile unsigned int*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int +inb(unsigned PORT_SIZE port) +{ + return *(volatile unsigned char*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + +static __inline__ unsigned int +inw(unsigned PORT_SIZE port) +{ + return *(volatile unsigned short*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + +static __inline__ unsigned int +inl(unsigned PORT_SIZE port) +{ + return *(volatile unsigned int*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + + +# if defined(__mips__) +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(3+(char *) r11))); + return r1; +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(3+(char *) r11))); + return r1; +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(1+(char *) r11))); + return r1; +} + +# ifdef linux /* don't mess with other OSs */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads (and we don't support older + * versions anyway. Define some packed structures to talk about such things + * with. + */ + +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ void stw_u(unsigned long val, unsigned short *p) +{ + struct __una_u16 *ptr = (struct __una_u16 *) p; + ptr->x = val; +} + +static __inline__ void stl_u(unsigned long val, unsigned int *p) +{ + struct __una_u32 *ptr = (struct __una_u32 *) p; + ptr->x = val; +} + +# if X_BYTE_ORDER == X_BIG_ENDIAN +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("lw %0, 0(%1)" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sw %0, 0(%1)" + : /* No outputs */ + : "r" (val), "r" (addr)); +} +# endif + +# define mem_barrier() \ + __asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ + ".set\tnoreorder\n\t" \ + "# 8 nops to fool the R4400 pipeline\n\t" \ + "nop;nop;nop;nop;nop;nop;nop;nop\n\t" \ + ".set\treorder" \ + : /* no output */ \ + : /* no input */ \ + : "memory") +# define write_mem_barrier() mem_barrier() + +# else /* !linux */ + +# define stq_u(v,p) stl_u(v,p) +# define stl_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*(unsigned char *)(p)+1) = ((v) >> 8); \ + (*(unsigned char *)(p)+2) = ((v) >> 16); \ + (*(unsigned char *)(p)+3) = ((v) >> 24) + +# define stw_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*(unsigned char *)(p)+1) = ((v) >> 8) + +# define mem_barrier() /* NOP */ +# endif /* !linux */ +# endif /* __mips__ */ + +# if defined(__arm32__) +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ +# endif /* __arm32__ */ + +# elif (defined(Lynx) || defined(linux) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__FreeBSD__)) && defined(__powerpc__) + +# ifndef MAP_FAILED +# define MAP_FAILED ((void *)-1) +# endif + +extern volatile unsigned char *ioBase; + +#if defined(linux) && defined(__powerpc64__) +# include +#endif /* defined(linux) && defined(__powerpc64__) */ +#ifndef eieio /* We deal with arch-specific eieio() routines above... */ +# define eieio() __asm__ __volatile__ ("eieio" ::: "memory") +#endif /* eieio */ + +static __inline__ unsigned char +xf86ReadMmio8(__volatile__ void *base, const unsigned long offset) +{ + register unsigned char val; + __asm__ __volatile__( + "lbzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned short +xf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset) +{ + register unsigned short val; + __asm__ __volatile__( + "lhzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned short +xf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset) +{ + register unsigned short val; + __asm__ __volatile__( + "lhbrx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + register unsigned int val; + __asm__ __volatile__( + "lwzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned int +xf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset) +{ + register unsigned int val; + __asm__ __volatile__( + "lwbrx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ void +xf86WriteMmioNB8(__volatile__ void *base, const unsigned long offset, + const unsigned char val) +{ + __asm__ __volatile__( + "stbx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB16Le(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + __asm__ __volatile__( + "sthbrx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB16Be(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + __asm__ __volatile__( + "sthx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + __asm__ __volatile__( + "stwbrx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + __asm__ __volatile__( + "stwx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmio8(__volatile__ void *base, const unsigned long offset, + const unsigned char val) +{ + xf86WriteMmioNB8(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + xf86WriteMmioNB16Le(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + xf86WriteMmioNB16Be(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + xf86WriteMmioNB32Le(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + xf86WriteMmioNB32Be(base, offset, val); + eieio(); +} + + +static __inline__ void +outb(unsigned short port, unsigned char value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio8((void *)ioBase, port, value); +} + +static __inline__ void +outw(unsigned short port, unsigned short value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio16Le((void *)ioBase, port, value); +} + +static __inline__ void +outl(unsigned short port, unsigned int value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio32Le((void *)ioBase, port, value); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio8((void *)ioBase, port); +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio16Le((void *)ioBase, port); +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio32Le((void *)ioBase, port); +} + +# define ldq_u(p) ldl_u(p) +# define ldl_u(p) ((*(unsigned char *)(p)) | \ + (*((unsigned char *)(p)+1)<<8) | \ + (*((unsigned char *)(p)+2)<<16) | \ + (*((unsigned char *)(p)+3)<<24)) +# define ldw_u(p) ((*(unsigned char *)(p)) | \ + (*((unsigned char *)(p)+1)<<8)) + +# define stq_u(v,p) stl_u(v,p) +# define stl_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*((unsigned char *)(p)+1)) = ((v) >> 8); \ + (*((unsigned char *)(p)+2)) = ((v) >> 16); \ + (*((unsigned char *)(p)+3)) = ((v) >> 24) +# define stw_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*((unsigned char *)(p)+1)) = ((v) >> 8) + +# define mem_barrier() eieio() +# define write_mem_barrier() eieio() + +#elif defined(__arm__) && defined(__linux__) + +#define ldq_u(p) (*((unsigned long *)(p))) +#define ldl_u(p) (*((unsigned int *)(p))) +#define ldw_u(p) (*((unsigned short *)(p))) +#define stq_u(v,p) (*(unsigned long *)(p)) = (v) +#define stl_u(v,p) (*(unsigned int *)(p)) = (v) +#define stw_u(v,p) (*(unsigned short *)(p)) = (v) +#define mem_barrier() /* NOP */ +#define write_mem_barrier() /* NOP */ + +/* for Linux on ARM, we use the LIBC inx/outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +#include + +static __inline__ void +xf_outb(unsigned short port, unsigned char val) +{ + outb(val, port); +} + +static __inline__ void +xf_outw(unsigned short port, unsigned short val) +{ + outw(val, port); +} + +static __inline__ void +xf_outl(unsigned short port, unsigned int val) +{ + outl(val, port); +} + +#define outb xf_outb +#define outw xf_outw +#define outl xf_outl + +#define arm_flush_cache(addr) \ +do { \ + register unsigned long _beg __asm ("a1") = (unsigned long) (addr); \ + register unsigned long _end __asm ("a2") = (unsigned long) (addr) + 4;\ + register unsigned long _flg __asm ("a3") = 0; \ + __asm __volatile ("swi 0x9f0002 @ sys_cacheflush" \ + : "=r" (_beg) \ + : "0" (_beg), "r" (_end), "r" (_flg)); \ +} while (0) + +# else /* ix86 */ + +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ + +# if !defined(__SUNPRO_C) +# if !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__) +# ifdef GCCUSESGAS + +/* + * If gcc uses gas rather than the native assembler, the syntax of these + * inlines has to be different. DHD + */ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# else /* GCCUSESGAS */ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("in%B0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("in%W0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("in%L0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# endif /* GCCUSESGAS */ + +# else /* !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__)*/ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ +} + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + return 0; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + return 0; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + return 0; +} + +# endif /* FAKEIT */ +# endif /* __SUNPRO_C */ + +# endif /* ix86 */ + +# elif defined(__powerpc__) /* && !__GNUC__ */ +/* + * NON-GCC PowerPC - Presumed to be PowerMAX OS for now + */ +# ifndef PowerMAX_OS +# error - Non-gcc PowerPC and !PowerMAXOS ??? +# endif + +# define PPCIO_DEBUG 0 +# define PPCIO_INLINE 1 +# define USE_ABS_MACRO 1 +/* + * Use compiler intrinsics to access certain PPC machine instructions + */ +# define eieio() __inst_eieio() +# define stw_brx(val,base,ndx) __inst_sthbrx(val,base,ndx) +# define stl_brx(val,base,ndx) __inst_stwbrx(val,base,ndx) +# define ldw_brx(base,ndx) __inst_lhbrx(base,ndx) +# define ldl_brx(base,ndx) __inst_lwbrx(base,ndx) + +# define ldq_u(p) (*((unsigned long long *)(p))) +# define ldl_u(p) (*((unsigned long *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned long *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() eieio() +# define write_mem_barrier() eieio() + +extern volatile unsigned char *ioBase; + +# if !defined(abs) && defined(USE_ABS_MACRO) +# define abs(x) ((x) >= 0 ? (x) : -(x)) +# endif + +# undef inb +# undef inw +# undef inl +# undef outb +# undef outw +# undef outl + +# if PPCIO_DEBUG + +extern void debug_outb(unsigned int a, unsigned char b, int line, char *file); +extern void debug_outw(unsigned int a, unsigned short w, int line, char *file); +extern void debug_outl(unsigned int a, unsigned int l, int line, char *file); +extern unsigned char debug_inb(unsigned int a, int line, char *file); +extern unsigned short debug_inw(unsigned int a, int line, char *file); +extern unsigned int debug_inl(unsigned int a, int line, char *file); + +# define outb(a,b) debug_outb(a,b, __LINE__, __FILE__) +# define outw(a,w) debug_outw(a,w, __LINE__, __FILE__) +# define outl(a,l) debug_outl(a,l, __LINE__, __FILE__) +# define inb(a) debug_inb(a, __LINE__, __FILE__) +# define inw(a) debug_inw(a, __LINE__, __FILE__) +# define inl(a) debug_inl(a, __LINE__, __FILE__) + +# else /* !PPCIO_DEBUG */ + +extern unsigned char inb(unsigned int a); +extern unsigned short inw(unsigned int a); +extern unsigned int inl(unsigned int a); + +# if PPCIO_INLINE + +# define outb(a,b) \ + (*((volatile unsigned char *)(ioBase + (a))) = (b), eieio()) +# define outw(a,w) (stw_brx((w),ioBase,(a)), eieio()) +# define outl(a,l) (stl_brx((l),ioBase,(a)), eieio()) + +# else /* !PPCIO_INLINE */ + +extern void outb(unsigned int a, unsigned char b); +extern void outw(unsigned int a, unsigned short w); +extern void outl(unsigned int a, unsigned int l); + +# endif /* PPCIO_INLINE */ + +# endif /* !PPCIO_DEBUG */ + +# else /* !GNUC && !PPC */ +# if !defined(QNX4) +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef asm +# define asm __asm +# endif +# endif +# ifndef SCO325 +# if defined(__UNIXWARE__) +# if defined(IN_MODULE) +# /* avoid including for on UnixWare */ +# define ushort unsigned short +# define ushort_t unsigned short +# define ulong unsigned long +# define ulong_t unsigned long +# define uint_t unsigned int +# define uchar_t unsigned char +# else +# include +# endif /* IN_MODULE */ +# endif /* __UNIXWARE__ */ +# if !defined(sgi) && !defined(__SUNPRO_C) +# include +# endif +# else +# include "scoasm.h" +# endif +# if (!defined(__HIGHC__) && !defined(sgi) && !defined(__SUNPRO_C)) || \ + defined(__USLC__) +# pragma asm partial_optimization outl +# pragma asm partial_optimization outw +# pragma asm partial_optimization outb +# pragma asm partial_optimization inl +# pragma asm partial_optimization inw +# pragma asm partial_optimization inb +# endif +# endif +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ +# endif /* __GNUC__ */ + +# if defined(QNX4) +# include +extern unsigned inb(unsigned port); +extern unsigned inw(unsigned port); +extern unsigned inl(unsigned port); +extern void outb(unsigned port, unsigned val); +extern void outw(unsigned port, unsigned val); +extern void outl(unsigned port, unsigned val); +# endif /* QNX4 */ + +# if defined(IODEBUG) && defined(__GNUC__) +# undef inb +# undef inw +# undef inl +# undef outb +# undef outw +# undef outl +# define inb(a) __extension__ ({unsigned char __c=RealInb(a); ErrorF("inb(0x%03x) = 0x%02x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) +# define inw(a) __extension__ ({unsigned short __c=RealInw(a); ErrorF("inw(0x%03x) = 0x%04x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) +# define inl(a) __extension__ ({unsigned int __c=RealInl(a); ErrorF("inl(0x%03x) = 0x%08x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) + +# define outb(a,b) (ErrorF("outb(0x%03x, 0x%02x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutb(a,b)) +# define outw(a,b) (ErrorF("outw(0x%03x, 0x%04x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutw(a,b)) +# define outl(a,b) (ErrorF("outl(0x%03x, 0x%08x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutl(a,b)) +# endif + +# endif /* NO_INLINE */ + +# ifdef __alpha__ +/* entry points for Mmio memory access routines */ +extern int (*xf86ReadMmio8)(void *, unsigned long); +extern int (*xf86ReadMmio16)(void *, unsigned long); +# ifndef STANDALONE_MMIO +extern int (*xf86ReadMmio32)(void *, unsigned long); +# else +/* Some DRI 3D drivers need MMIO_IN32. */ +static __inline__ int +xf86ReadMmio32(void *Base, unsigned long Offset) +{ + __asm__ __volatile__("mb" : : : "memory"); + return *(volatile unsigned int*)((unsigned long)Base+(Offset)); +} +# endif +extern void (*xf86WriteMmio8)(int, void *, unsigned long); +extern void (*xf86WriteMmio16)(int, void *, unsigned long); +extern void (*xf86WriteMmio32)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB8)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB16)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB32)(int, void *, unsigned long); +extern void xf86JensenMemToBus(char *, long, long, int); +extern void xf86JensenBusToMem(char *, char *, unsigned long, int); +extern void xf86SlowBCopyFromBus(unsigned char *, unsigned char *, int); +extern void xf86SlowBCopyToBus(unsigned char *, unsigned char *, int); + +/* Some macros to hide the system dependencies for MMIO accesses */ +/* Changed to kill noise generated by gcc's -Wcast-align */ +# define MMIO_IN8(base, offset) (*xf86ReadMmio8)(base, offset) +# define MMIO_IN16(base, offset) (*xf86ReadMmio16)(base, offset) +# ifndef STANDALONE_MMIO +# define MMIO_IN32(base, offset) (*xf86ReadMmio32)(base, offset) +# else +# define MMIO_IN32(base, offset) xf86ReadMmio32(base, offset) +# endif + +# if defined (JENSEN_SUPPORT) +# define MMIO_OUT32(base, offset, val) \ + (*xf86WriteMmio32)((CARD32)(val), base, offset) +# define MMIO_ONB32(base, offset, val) \ + (*xf86WriteMmioNB32)((CARD32)(val), base, offset) +# else +# define MMIO_OUT32(base, offset, val) \ + do { \ + write_mem_barrier(); \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val); \ + } while (0) +# define MMIO_ONB32(base, offset, val) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# endif + +# define MMIO_OUT8(base, offset, val) \ + (*xf86WriteMmio8)((CARD8)(val), base, offset) +# define MMIO_OUT16(base, offset, val) \ + (*xf86WriteMmio16)((CARD16)(val), base, offset) +# define MMIO_ONB8(base, offset, val) \ + (*xf86WriteMmioNB8)((CARD8)(val), base, offset) +# define MMIO_ONB16(base, offset, val) \ + (*xf86WriteMmioNB16)((CARD16)(val), base, offset) +# define MMIO_MOVE32(base, offset, val) \ + MMIO_OUT32(base, offset, val) + +# elif defined(__powerpc__) + /* + * we provide byteswapping and no byteswapping functions here + * with byteswapping as default, + * drivers that don't need byteswapping should define PPC_MMIO_IS_BE + */ +# define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset) +# define MMIO_OUT8(base, offset, val) \ + xf86WriteMmio8(base, offset, (CARD8)(val)) +# define MMIO_ONB8(base, offset, val) \ + xf86WriteMmioNB8(base, offset, (CARD8)(val)) + +# if defined(PPC_MMIO_IS_BE) /* No byteswapping */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Be(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmioNB16Be(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmioNB32Be(base, offset, (CARD32)(val)) +# else /* byteswapping is the default */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Le(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Le(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmioNB16Le(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmioNB32Le(base, offset, (CARD32)(val)) +# endif + +# define MMIO_MOVE32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) + +static __inline__ void ppc_flush_icache(char *addr) +{ + __asm__ volatile ( + "dcbf 0,%0;" + "sync;" + "icbi 0,%0;" + "sync;" + "isync;" + : : "r"(addr) : "memory"); +} + +# elif defined(__sparc__) || defined(sparc) + /* + * Like powerpc, we provide byteswapping and no byteswapping functions + * here with byteswapping as default, drivers that don't need byteswapping + * should define SPARC_MMIO_IS_BE (perhaps create a generic macro so that we + * do not need to use PPC_MMIO_IS_BE and the sparc one in all the same places + * of drivers?). + */ +# define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset) +# define MMIO_OUT8(base, offset, val) \ + xf86WriteMmio8(base, offset, (CARD8)(val)) +# define MMIO_ONB8(base, offset, val) \ + xf86WriteMmio8NB(base, offset, (CARD8)(val)) + +# if defined(SPARC_MMIO_IS_BE) /* No byteswapping */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Be(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmio16BeNB(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmio32BeNB(base, offset, (CARD32)(val)) +# else /* byteswapping is the default */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Le(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Le(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmio16LeNB(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmio32LeNB(base, offset, (CARD32)(val)) +# endif + +# define MMIO_MOVE32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) + +# else /* !__alpha__ && !__powerpc__ && !__sparc__ */ + +# define MMIO_IN8(base, offset) \ + *(volatile CARD8 *)(((CARD8*)(base)) + (offset)) +# define MMIO_IN16(base, offset) \ + *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset)) +# define MMIO_IN32(base, offset) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) +# define MMIO_OUT8(base, offset, val) \ + *(volatile CARD8 *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_OUT16(base, offset, val) \ + *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_OUT32(base, offset, val) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_ONB8(base, offset, val) MMIO_OUT8(base, offset, val) +# define MMIO_ONB16(base, offset, val) MMIO_OUT16(base, offset, val) +# define MMIO_ONB32(base, offset, val) MMIO_OUT32(base, offset, val) + +# define MMIO_MOVE32(base, offset, val) MMIO_OUT32(base, offset, val) + +# endif /* __alpha__ */ + +/* + * With Intel, the version in os-support/misc/SlowBcopy.s is used. + * This avoids port I/O during the copy (which causes problems with + * some hardware). + */ +# ifdef __alpha__ +# define slowbcopy_tobus(src,dst,count) xf86SlowBCopyToBus(src,dst,count) +# define slowbcopy_frombus(src,dst,count) xf86SlowBCopyFromBus(src,dst,count) +# else /* __alpha__ */ +# define slowbcopy_tobus(src,dst,count) xf86SlowBcopy(src,dst,count) +# define slowbcopy_frombus(src,dst,count) xf86SlowBcopy(src,dst,count) +# endif /* __alpha__ */ + +#endif /* _COMPILER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/compint.h (revision 51223) @@ -0,0 +1,260 @@ +/* + * $Id: compint.h,v 1.8 2005/07/03 08:53:37 daniels Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _COMPINT_H_ +#define _COMPINT_H_ + +#include "misc.h" +#include "scrnintstr.h" +#include "os.h" +#include "regionstr.h" +#include "validate.h" +#include "windowstr.h" +#include "input.h" +#include "resource.h" +#include "colormapst.h" +#include "cursorstr.h" +#include "dixstruct.h" +#include "gcstruct.h" +#include "servermd.h" +#include "dixevents.h" +#include "globals.h" +#include "picturestr.h" +#include "extnsionst.h" +#include "mi.h" +#include "damage.h" +#include "damageextint.h" +#include "xfixes.h" +#include +#include + +/* + * enable this for debugging + + #define COMPOSITE_DEBUG + */ + +typedef struct _CompClientWindow { + struct _CompClientWindow *next; + XID id; + int update; +} CompClientWindowRec, *CompClientWindowPtr; + +typedef struct _CompWindow { + RegionRec borderClip; + DamagePtr damage; /* for automatic update mode */ + Bool damageRegistered; + Bool damaged; + int update; + CompClientWindowPtr clients; + int oldx; + int oldy; + PixmapPtr pOldPixmap; + int borderClipX, borderClipY; +} CompWindowRec, *CompWindowPtr; + +#define COMP_ORIGIN_INVALID 0x80000000 + +typedef struct _CompSubwindows { + int update; + CompClientWindowPtr clients; +} CompSubwindowsRec, *CompSubwindowsPtr; + +#ifndef COMP_INCLUDE_RGB24_VISUAL +#define COMP_INCLUDE_RGB24_VISUAL 0 +#endif + +#if COMP_INCLUDE_RGB24_VISUAL +#define NUM_COMP_ALTERNATE_VISUALS 2 +#else +#define NUM_COMP_ALTERNATE_VISUALS 1 +#endif + +typedef struct _CompScreen { + PositionWindowProcPtr PositionWindow; + CopyWindowProcPtr CopyWindow; + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + PaintWindowProcPtr PaintWindowBackground; + ClipNotifyProcPtr ClipNotify; + /* + * Called from ConfigureWindow, these + * three track changes to the offscreen storage + * geometry + */ + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + ChangeBorderWidthProcPtr ChangeBorderWidth; + /* + * Reparenting has an effect on Subwindows redirect + */ + ReparentWindowProcPtr ReparentWindow; + + /* + * Colormaps for new visuals better not get installed + */ + InstallColormapProcPtr InstallColormap; + + ScreenBlockHandlerProcPtr BlockHandler; + CloseScreenProcPtr CloseScreen; + Bool damaged; + XID alternateVisuals[NUM_COMP_ALTERNATE_VISUALS]; +} CompScreenRec, *CompScreenPtr; + +extern int CompScreenPrivateIndex; +extern int CompWindowPrivateIndex; +extern int CompSubwindowsPrivateIndex; + +#define GetCompScreen(s) ((CompScreenPtr) ((s)->devPrivates[CompScreenPrivateIndex].ptr)) +#define GetCompWindow(w) ((CompWindowPtr) ((w)->devPrivates[CompWindowPrivateIndex].ptr)) +#define GetCompSubwindows(w) ((CompSubwindowsPtr) ((w)->devPrivates[CompSubwindowsPrivateIndex].ptr)) + +extern RESTYPE CompositeClientWindowType; +extern RESTYPE CompositeClientSubwindowsType; + +/* + * compalloc.c + */ + +void +compReportDamage (DamagePtr pDamage, RegionPtr pRegion, void *closure); + +Bool +compRedirectWindow (ClientPtr pClient, WindowPtr pWin, int update); + +void +compFreeClientWindow (WindowPtr pWin, XID id); + +int +compUnredirectWindow (ClientPtr pClient, WindowPtr pWin, int update); + +int +compRedirectSubwindows (ClientPtr pClient, WindowPtr pWin, int update); + +void +compFreeClientSubwindows (WindowPtr pWin, XID id); + +int +compUnredirectSubwindows (ClientPtr pClient, WindowPtr pWin, int update); + +int +compRedirectOneSubwindow (WindowPtr pParent, WindowPtr pWin); + +int +compUnredirectOneSubwindow (WindowPtr pParent, WindowPtr pWin); + +Bool +compAllocPixmap (WindowPtr pWin); + +void +compFreePixmap (WindowPtr pWin); + +Bool +compReallocPixmap (WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, int bw); + +/* + * compext.c + */ + +void +CompositeExtensionInit (void); + +/* + * compinit.c + */ + +Bool +compScreenInit (ScreenPtr pScreen); + +/* + * compwindow.c + */ + +#ifdef COMPOSITE_DEBUG +void +compCheckTree (ScreenPtr pScreen); +#else +#define compCheckTree(s) +#endif + +void +compSetPixmap (WindowPtr pWin, PixmapPtr pPixmap); + +Bool +compCheckRedirect (WindowPtr pWin); + +Bool +compPositionWindow (WindowPtr pWin, int x, int y); + +Bool +compRealizeWindow (WindowPtr pWin); + +Bool +compUnrealizeWindow (WindowPtr pWin); + +void +compPaintWindowBackground (WindowPtr pWin, RegionPtr pRegion, int what); + +void +compClipNotify (WindowPtr pWin, int dx, int dy); + +void +compMoveWindow (WindowPtr pWin, int x, int y, WindowPtr pSib, VTKind kind); + +void +compResizeWindow (WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); + +void +compChangeBorderWidth (WindowPtr pWin, unsigned int border_width); + +void +compReparentWindow (WindowPtr pWin, WindowPtr pPriorParent); + +Bool +compCreateWindow (WindowPtr pWin); + +Bool +compDestroyWindow (WindowPtr pWin); + +void +compSetRedirectBorderClip (WindowPtr pWin, RegionPtr pRegion); + +RegionPtr +compGetRedirectBorderClip (WindowPtr pWin); + +void +compCopyWindow (WindowPtr pWin, DDXPointRec ptOldOrg, RegionPtr prgnSrc); + +void +compWindowUpdate (WindowPtr pWin); + +#endif /* _COMPINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/config.h (revision 51223) @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/config.h,v 1.21 2004/02/13 23:58:52 dawes Exp $ + */ + +#ifdef HAVE_CONFIG_H +# include "xorg-config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef sun +#undef index +#undef rindex +#include +#endif +#include + +#include + +#ifdef __UNIXOS2__ +#define strcasecmp stricmp +#define setenv putenv +#define PATH_MAX 260 +#endif + +/* Get PATH_MAX */ +#ifndef PATH_MAX +# if defined(_POSIX_SOURCE) +# include +# else +# define _POSIX_SOURCE +# include +# undef _POSIX_SOURCE +# endif +# ifndef PATH_MAX +# ifdef MAXPATHLEN +# define PATH_MAX MAXPATHLEN +# else +# define PATH_MAX 1024 +# endif +# endif +#endif + +#include +#include +#include +#include +#include +#include +#include + +#ifndef _xf86cfg_config_h +#define _xf86cfg_config_h + +/* Must match the offset in the xf86info structure at config.c, + * and is used also by interface.c + */ +#define MOUSE 0 +#define KEYBOARD 1 +#define CARD 2 +#define MONITOR 3 +#define SCREEN 4 +#define SERVER 5 + +#define UNUSED 0 +#define USED 1 + +#define CONFIG_LAYOUT 0 +#define CONFIG_SCREEN 1 +#define CONFIG_MODELINE 2 +#define CONFIG_ACCESSX 3 +extern int config_mode; + +#ifndef __UNIXOS2__ +#define CONFPATH "%A," "%R," \ + "/etc/X11/%R," "%P/etc/X11/%R," \ + "%E," "%F," \ + "/etc/X11/%F," "%P/etc/X11/%F," \ + "%D/%X," \ + "/etc/X11/%X-%M," "/etc/X11/%X," "/etc/%X," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#define USER_CONFPATH "/etc/X11/%S," "%P/etc/X11/%S," \ + "/etc/X11/%G," "%P/etc/X11/%G," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#else +#define CONFPATH "%&"XF86CONFIGDIR"/%R," "%&"XF86CONFIGDIR"/%X," \ + "%A," "%R," \ + "/etc/X11/%R," "%P/etc/X11/%R," \ + "%E," "%F," \ + "/etc/X11/%F," "%P/etc/X11/%F," \ + "%D/%X," \ + "/etc/X11/%X-%M," "/etc/X11/%X," "/etc/%X," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#define USER_CONFPATH "%&"XF86CONFIGDIR"/%X," "%&"XF86CONFIGDIR"/%X," \ + "/etc/X11/%S," "%P/etc/X11/%S," \ + "/etc/X11/%G," "%P/etc/X11/%G," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#endif + +/* + * Types + */ +typedef struct _XF86SetupInfo XF86SetupInfo; +typedef void (*XF86SetupFunction)(XF86SetupInfo*); + +typedef struct _XF86SetupFunctionList { + XF86SetupFunction *functions; + int num_functions; + int cur_function; +} XF86SetupFunctionList; + +struct _XF86SetupInfo { + int num_lists; + int cur_list; + XF86SetupFunctionList *lists; +}; + +typedef Bool (*ConfigCheckFunction)(void); + +typedef struct _xf86cfgDevice xf86cfgDevice; + +struct _xf86cfgDevice { + XtPointer config; + Widget widget; + int type, state, refcount; +}; + +typedef struct { + XF86ConfScreenPtr screen; + Widget widget; + int type, state, refcount; + xf86cfgDevice *card; + xf86cfgDevice *monitor; + short row, column; + XRectangle rect; + short rotate; +} xf86cfgScreen; + +/* this structure is used just to restore + properly the monitors layout in the + screen window configuration. + */ +typedef struct { + XF86ConfLayoutPtr layout; + xf86cfgScreen **screen; + XPoint *position; + int num_layouts; +} xf86cfgLayout; + +/* The vidmode extension usage is controlled by this structure. + * The information is read at startup, and added monitors cannot + * be configured, since they are not attached to a particular screen. + */ +typedef struct _xf86cfgVidMode xf86cfgVidmode; + +typedef struct { + XF86ConfLayoutPtr layout; /* current layout */ + Widget cpu; + xf86cfgLayout **layouts; + Cardinal num_layouts; + xf86cfgScreen **screens; + Cardinal num_screens; + xf86cfgDevice **devices; + Cardinal num_devices; + xf86cfgVidmode **vidmodes; + Cardinal num_vidmodes; +} xf86cfgComputer; + +/* + * Prototypes + */ +void StartConfig(void); +Bool ConfigLoop(ConfigCheckFunction); +void ConfigError(void); +void ChangeScreen(XF86ConfMonitorPtr, XF86ConfMonitorPtr, + XF86ConfDevicePtr, XF86ConfDevicePtr); +void SetTip(xf86cfgDevice*); +Bool startx(void); +void endx(void); +void startaccessx(void); +void ConfigCancelAction(Widget, XEvent*, String*, Cardinal*); +void ExpertConfigureStart(void); +void ExpertConfigureEnd(void); +void ExpertCloseAction(Widget, XEvent*, String*, Cardinal*); +void ExpertCallback(Widget, XtPointer, XtPointer); + +/* + * Initialization + */ +extern Widget toplevel, configp, current, back, next; +extern XtAppContext appcon; +extern XF86SetupInfo xf86info; +extern Widget ident_widget; +extern char *ident_string; +extern XF86ConfigPtr XF86Config; +extern char *XF86Config_path; +extern char *XF86Module_path; +extern char *XFree86_path; +extern char *XF86Font_path; +extern char *XF86RGB_path; +extern char *XFree86Dir; +extern xf86cfgComputer computer; +extern Atom wm_delete_window; +extern Display *DPY; +extern Pixmap menuPixmap; +#ifdef USE_MODULES +extern int nomodules; +#endif + +#endif /* _xf86cfg_config_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/configProcs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/configProcs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/configProcs.h (revision 51223) @@ -0,0 +1,132 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/configProcs.h,v 1.17 2003/08/24 17:37:08 dawes Exp $ */ +/* + * Copyright (c) 1997-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Private procs. Public procs are in xf86Parser.h and xf86Optrec.h */ + +/* Device.c */ +XF86ConfDevicePtr xf86parseDeviceSection(void); +void xf86printDeviceSection(FILE *cf, XF86ConfDevicePtr ptr); +void xf86freeDeviceList(XF86ConfDevicePtr ptr); +int xf86validateDevice(XF86ConfigPtr p); +/* Files.c */ +XF86ConfFilesPtr xf86parseFilesSection(void); +void xf86printFileSection(FILE *cf, XF86ConfFilesPtr ptr); +void xf86freeFiles(XF86ConfFilesPtr p); +/* Flags.c */ +XF86ConfFlagsPtr xf86parseFlagsSection(void); +void xf86printServerFlagsSection(FILE *f, XF86ConfFlagsPtr flags); +void xf86freeFlags(XF86ConfFlagsPtr flags); +/* Input.c */ +XF86ConfInputPtr xf86parseInputSection(void); +void xf86printInputSection(FILE *f, XF86ConfInputPtr ptr); +void xf86freeInputList(XF86ConfInputPtr ptr); +int xf86validateInput (XF86ConfigPtr p); +/* Keyboard.c */ +XF86ConfInputPtr xf86parseKeyboardSection(void); +/* Layout.c */ +XF86ConfLayoutPtr xf86parseLayoutSection(void); +void xf86printLayoutSection(FILE *cf, XF86ConfLayoutPtr ptr); +void xf86freeLayoutList(XF86ConfLayoutPtr ptr); +void xf86freeAdjacencyList(XF86ConfAdjacencyPtr ptr); +void xf86freeInputrefList(XF86ConfInputrefPtr ptr); +int xf86validateLayout(XF86ConfigPtr p); +/* Module.c */ +XF86LoadPtr xf86parseModuleSubSection(XF86LoadPtr head, char *name); +XF86ConfModulePtr xf86parseModuleSection(void); +void xf86printModuleSection(FILE *cf, XF86ConfModulePtr ptr); +XF86LoadPtr xf86addNewLoadDirective(XF86LoadPtr head, char *name, int type, XF86OptionPtr opts); +void xf86freeModules(XF86ConfModulePtr ptr); +/* Monitor.c */ +XF86ConfModeLinePtr xf86parseModeLine(void); +XF86ConfModeLinePtr xf86parseVerboseMode(void); +XF86ConfMonitorPtr xf86parseMonitorSection(void); +XF86ConfModesPtr xf86parseModesSection(void); +void xf86printMonitorSection(FILE *cf, XF86ConfMonitorPtr ptr); +void xf86printModesSection(FILE *cf, XF86ConfModesPtr ptr); +void xf86freeMonitorList(XF86ConfMonitorPtr ptr); +void xf86freeModesList(XF86ConfModesPtr ptr); +void xf86freeModeLineList(XF86ConfModeLinePtr ptr); +int xf86validateMonitor(XF86ConfigPtr p, XF86ConfScreenPtr screen); +/* Pointer.c */ +XF86ConfInputPtr xf86parsePointerSection(void); +/* Screen.c */ +XF86ConfDisplayPtr xf86parseDisplaySubSection(void); +XF86ConfScreenPtr xf86parseScreenSection(void); +void xf86printScreenSection(FILE *cf, XF86ConfScreenPtr ptr); +void xf86freeScreenList(XF86ConfScreenPtr ptr); +void xf86freeAdaptorLinkList(XF86ConfAdaptorLinkPtr ptr); +void xf86freeDisplayList(XF86ConfDisplayPtr ptr); +void xf86freeModeList(XF86ModePtr ptr); +int xf86validateScreen(XF86ConfigPtr p); +/* Vendor.c */ +XF86ConfVendorPtr xf86parseVendorSection(void); +XF86ConfVendSubPtr xf86parseVendorSubSection (void); +void xf86freeVendorList(XF86ConfVendorPtr p); +void xf86printVendorSection(FILE * cf, XF86ConfVendorPtr ptr); +void xf86freeVendorSubList (XF86ConfVendSubPtr ptr); +/* Video.c */ +XF86ConfVideoPortPtr xf86parseVideoPortSubSection(void); +XF86ConfVideoAdaptorPtr xf86parseVideoAdaptorSection(void); +void xf86printVideoAdaptorSection(FILE *cf, XF86ConfVideoAdaptorPtr ptr); +void xf86freeVideoAdaptorList(XF86ConfVideoAdaptorPtr ptr); +void xf86freeVideoPortList(XF86ConfVideoPortPtr ptr); +/* read.c */ +int xf86validateConfig(XF86ConfigPtr p); +/* scan.c */ +unsigned int xf86strToUL(char *str); +int xf86getToken(xf86ConfigSymTabRec *tab); +int xf86getSubToken(char **comment); +int xf86getSubTokenWithTab(char **comment, xf86ConfigSymTabRec *tab); +void xf86unGetToken(int token); +char *xf86tokenString(void); +void xf86parseError(char *format, ...); +void xf86parseWarning(char *format, ...); +void xf86validationError(char *format, ...); +void xf86setSection(char *section); +int xf86getStringToken(xf86ConfigSymTabRec *tab); +/* write.c */ +/* DRI.c */ +XF86ConfBuffersPtr xf86parseBuffers (void); +void xf86freeBuffersList (XF86ConfBuffersPtr ptr); +XF86ConfDRIPtr xf86parseDRISection (void); +void xf86printDRISection (FILE * cf, XF86ConfDRIPtr ptr); +void xf86freeDRI (XF86ConfDRIPtr ptr); +/* Extensions.c */ +XF86ConfExtensionsPtr xf86parseExtensionsSection (void); +void xf86printExtensionsSection (FILE * cf, XF86ConfExtensionsPtr ptr); +void xf86freeExtensions (XF86ConfExtensionsPtr ptr); + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef IN_XSERVER +/* Externally provided functions */ +void ErrorF(const char *f, ...); +void VErrorF(const char *f, va_list args); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cr.h (revision 51223) @@ -0,0 +1,62 @@ +/* + * Internal definitions of the Cocoa rootless implementation + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86$ */ + +#ifndef _CR_H +#define _CR_H + +#ifdef __OBJC__ +#import +#import "XView.h" +#else +typedef struct OpaqueNSWindow NSWindow; +typedef struct OpaqueXView XView; +#endif + +#undef BOOL +#define BOOL xBOOL +#include "screenint.h" +#include "window.h" +#undef BOOL + +// Predefined style for the window which is about to be framed +extern WindowPtr nextWindowToFrame; +extern unsigned int nextWindowStyle; + +typedef struct { + NSWindow *window; + XView *view; + GrafPtr port; + CGContextRef context; +} CRWindowRec, *CRWindowPtr; + +Bool CRInit(ScreenPtr pScreen); +void CRAppleWMInit(void); + +#endif /* _CR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursor.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XdotOrg: xc/programs/Xserver/include/cursor.h,v 1.2 2004/04/23 19:54:23 eich Exp $ */ +/* $XFree86: xc/programs/Xserver/include/cursor.h,v 1.6 2002/09/17 01:15:14 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: cursor.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef CURSOR_H +#define CURSOR_H + +#include "misc.h" +#include "screenint.h" +#include "window.h" + +#define NullCursor ((CursorPtr)NULL) + +/* Provide support for alpha composited cursors */ +#ifdef RENDER +#define ARGB_CURSOR +#endif + +typedef struct _Cursor *CursorPtr; +typedef struct _CursorMetric *CursorMetricPtr; + +extern CursorPtr rootCursor; + +extern int FreeCursor( + pointer /*pCurs*/, + XID /*cid*/); + +/* Quartz support on Mac OS X pulls in the QuickDraw + framework whose AllocCursor function conflicts here. */ +#ifdef __DARWIN__ +#define AllocCursor Darwin_X_AllocCursor +#endif +extern CursorPtr AllocCursor( + unsigned char* /*psrcbits*/, + unsigned char* /*pmaskbits*/, + CursorMetricPtr /*cm*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/); + +extern CursorPtr AllocCursorARGB( + unsigned char* /*psrcbits*/, + unsigned char* /*pmaskbits*/, + CARD32* /*argb*/, + CursorMetricPtr /*cm*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/); + +extern int AllocGlyphCursor( + Font /*source*/, + unsigned int /*sourceChar*/, + Font /*mask*/, + unsigned int /*maskChar*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/, + CursorPtr* /*ppCurs*/, + ClientPtr /*client*/); + +extern CursorPtr CreateRootCursor( + char* /*pfilename*/, + unsigned int /*glyph*/); + +extern int ServerBitsFromGlyph( + FontPtr /*pfont*/, + unsigned int /*ch*/, + register CursorMetricPtr /*cm*/, + unsigned char ** /*ppbits*/); + +extern Bool CursorMetricsFromGlyph( + FontPtr /*pfont*/, + unsigned /*ch*/, + CursorMetricPtr /*cm*/); + +extern void CheckCursorConfinement( + WindowPtr /*pWin*/); + +extern void NewCurrentScreen( + ScreenPtr /*newScreen*/, + int /*x*/, + int /*y*/); + +extern Bool PointerConfinedToScreen(void); + +extern void GetSpritePosition( + int * /*px*/, + int * /*py*/); + +#ifdef PANORAMIX +extern int XineramaGetCursorScreen(void); +#endif /* PANORAMIX */ + +#endif /* CURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursorstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursorstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cursorstr.h (revision 51223) @@ -0,0 +1,98 @@ +/* $Xorg: cursorstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/cursorstr.h,v 1.8 2002/11/30 06:21:51 keithp Exp $ */ + +#ifndef CURSORSTRUCT_H +#define CURSORSTRUCT_H + +#include "cursor.h" +/* + * device-independent cursor storage + */ + +/* + * source and mask point directly to the bits, which are in the server-defined + * bitmap format. + */ +typedef struct _CursorBits { + unsigned char *source; /* points to bits */ + unsigned char *mask; /* points to bits */ + Bool emptyMask; /* all zeros mask */ + unsigned short width, height, xhot, yhot; /* metrics */ + int refcnt; /* can be shared */ + pointer devPriv[MAXSCREENS]; /* set by pScr->RealizeCursor*/ +#ifdef ARGB_CURSOR + CARD32 *argb; /* full-color alpha blended */ +#endif +} CursorBits, *CursorBitsPtr; + +typedef struct _Cursor { + CursorBitsPtr bits; + unsigned short foreRed, foreGreen, foreBlue; /* device-independent color */ + unsigned short backRed, backGreen, backBlue; /* device-independent color */ + int refcnt; + pointer devPriv[MAXSCREENS]; /* set by pScr->RealizeCursor*/ +#ifdef XFIXES + CARD32 serialNumber; + Atom name; +#endif +} CursorRec; + +typedef struct _CursorMetric { + unsigned short width, height, xhot, yhot; +} CursorMetricRec; + +typedef struct { + int x, y; + ScreenPtr pScreen; +} HotSpot; + +#ifdef XEVIE +extern HotSpot xeviehot; +#endif +#endif /* CURSORSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cw.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cw.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/cw.h (revision 51223) @@ -0,0 +1,174 @@ +/* + * Copyright © 2004 Eric Anholt + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Eric Anholt not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Eric Anholt makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* $Header: /cvs/xorg/xserver/xorg/miext/cw/cw.h,v 1.14 2005/12/09 18:32:46 ajax Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "gcstruct.h" +#include "picturestr.h" + +/* + * One of these structures is allocated per GC that gets used with a window with + * backing pixmap. + */ + +typedef struct { + GCPtr pBackingGC; /* Copy of the GC but with graphicsExposures + * set FALSE and the clientClip set to + * clip output to the valid regions of the + * backing pixmap. */ + unsigned long serialNumber; /* clientClip computed time */ + unsigned long stateChanges; /* changes in parent gc since last copy */ + GCOps *wrapOps; /* wrapped ops */ + GCFuncs *wrapFuncs; /* wrapped funcs */ +} cwGCRec, *cwGCPtr; + +extern int cwGCIndex; + +#define getCwGC(pGC) ((cwGCPtr)(pGC)->devPrivates[cwGCIndex].ptr) +#define setCwGC(pGC,p) ((pGC)->devPrivates[cwGCIndex].ptr = (pointer) (p)) + +/* + * One of these structures is allocated per Picture that gets used with a + * window with a backing pixmap + */ + +typedef struct { + PicturePtr pBackingPicture; + unsigned long serialNumber; + unsigned long stateChanges; +} cwPictureRec, *cwPicturePtr; + +#define getCwPicture(pPicture) ((cwPicturePtr)(pPicture)->devPrivates[cwPictureIndex].ptr) +#define setCwPicture(pPicture,p) ((pPicture)->devPrivates[cwPictureIndex].ptr = (pointer) (p)) + +extern int cwPictureIndex; + +extern int cwWindowIndex; + +#define cwWindowPrivate(pWindow) ((pWindow)->devPrivates[cwWindowIndex].ptr) +#define getCwPixmap(pWindow) ((PixmapPtr) cwWindowPrivate(pWindow)) +#define setCwPixmap(pWindow,pPixmap) (cwWindowPrivate(pWindow) = (pointer) (pPixmap)) + +#define cwDrawableIsRedirWindow(pDraw) \ + ((pDraw)->type == DRAWABLE_WINDOW && \ + getCwPixmap((WindowPtr) (pDraw)) != NULL) + +typedef struct { + /* + * screen func wrappers + */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + CreateGCProcPtr CreateGC; + + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + + GetWindowPixmapProcPtr GetWindowPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + +#ifdef RENDER + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; + + RasterizeTrapezoidProcPtr RasterizeTrapezoid; +#endif +} cwScreenRec, *cwScreenPtr; + +extern int cwScreenIndex; + +#define getCwScreen(pScreen) ((cwScreenPtr)(pScreen)->devPrivates[cwScreenIndex].ptr) +#define setCwScreen(pScreen,p) ((cwScreenPtr)(pScreen)->devPrivates[cwScreenIndex].ptr = (p)) + +#define CW_OFFSET_XYPOINTS(ppt, npt) do { \ + DDXPointPtr _ppt = (DDXPointPtr)(ppt); \ + int _i; \ + for (_i = 0; _i < npt; _i++) { \ + _ppt[_i].x += dst_off_x; \ + _ppt[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_RECTS(prect, nrect) do { \ + int _i; \ + for (_i = 0; _i < nrect; _i++) { \ + (prect)[_i].x += dst_off_x; \ + (prect)[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_ARCS(parc, narc) do { \ + int _i; \ + for (_i = 0; _i < narc; _i++) { \ + (parc)[_i].x += dst_off_x; \ + (parc)[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_XY_DST(x, y) do { \ + (x) = (x) + dst_off_x; \ + (y) = (y) + dst_off_y; \ +} while (0) + +#define CW_OFFSET_XY_SRC(x, y) do { \ + (x) = (x) + src_off_x; \ + (y) = (y) + src_off_y; \ +} while (0) + +/* cw.c */ +DrawablePtr +cwGetBackingDrawable(DrawablePtr pDrawable, int *x_off, int *y_off); + +/* cw_render.c */ + +void +cwInitializeRender (ScreenPtr pScreen); + +void +cwFiniRender (ScreenPtr pScreen); + +/* cw.c */ + +void +miInitializeCompositeWrapper(ScreenPtr pScreen); + +/* Must be called before miInitializeCompositeWrapper */ +void +miDisableCompositeWrapper(ScreenPtr pScreen); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damage.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damage.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damage.h (revision 51223) @@ -0,0 +1,84 @@ +/* + * $Id: damage.h,v 1.4 2005/07/03 07:02:01 daniels Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGE_H_ +#define _DAMAGE_H_ + +typedef struct _damage *DamagePtr; + +typedef enum _damageReportLevel { + DamageReportRawRegion, + DamageReportDeltaRegion, + DamageReportBoundingBox, + DamageReportNonEmpty, + DamageReportNone +} DamageReportLevel; + +typedef void (*DamageReportFunc) (DamagePtr pDamage, RegionPtr pRegion, void *closure); +typedef void (*DamageDestroyFunc) (DamagePtr pDamage, void *closure); + +Bool +DamageSetup (ScreenPtr pScreen); + +DamagePtr +DamageCreate (DamageReportFunc damageReport, + DamageDestroyFunc damageDestroy, + DamageReportLevel damageLevel, + Bool isInternal, + ScreenPtr pScreen, + void * closure); + +void +DamageDrawInternal (ScreenPtr pScreen, Bool enable); + +void +DamageRegister (DrawablePtr pDrawable, + DamagePtr pDamage); + +void +DamageUnregister (DrawablePtr pDrawable, + DamagePtr pDamage); + +void +DamageDestroy (DamagePtr pDamage); + +Bool +DamageSubtract (DamagePtr pDamage, + const RegionPtr pRegion); + +void +DamageEmpty (DamagePtr pDamage); + +RegionPtr +DamageRegion (DamagePtr pDamage); + +void +DamageDamageRegion (DrawablePtr pDrawable, + const RegionPtr pRegion); + +#endif /* _DAMAGE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageext.h (revision 51223) @@ -0,0 +1,35 @@ +/* + * $Id: damageext.h,v 1.5 2005/07/03 07:01:17 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGEEXT_H_ +#define _DAMAGEEXT_H_ + +void +DamageExtensionInit(void); + +#endif /* _DAMAGEEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageextint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageextint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damageextint.h (revision 51223) @@ -0,0 +1,88 @@ +/* + * $Id: damageextint.h,v 1.6 2005/07/03 08:53:38 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGEEXTINT_H_ +#define _DAMAGEEXTINT_H_ + +#define NEED_EVENTS +#include +#include +#include "misc.h" +#include "os.h" +#include "dixstruct.h" +#include "extnsionst.h" +#include +#include "windowstr.h" +#include "selection.h" +#include "scrnintstr.h" +#include "damageext.h" +#include "damage.h" +#include "xfixes.h" + +extern unsigned char DamageReqCode; +extern int DamageEventBase; +extern int DamageErrorBase; +extern int DamageClientPrivateIndex; +extern RESTYPE DamageExtType; +extern RESTYPE DamageExtWinType; + +typedef struct _DamageClient { + CARD32 major_version; + CARD32 minor_version; + int critical; +} DamageClientRec, *DamageClientPtr; + +#define GetDamageClient(pClient) ((DamageClientPtr) (pClient)->devPrivates[DamageClientPrivateIndex].ptr) + +typedef struct _DamageExt { + DamagePtr pDamage; + DrawablePtr pDrawable; + DamageReportLevel level; + ClientPtr pClient; + XID id; +} DamageExtRec, *DamageExtPtr; + +extern int (*ProcDamageVector[/*XDamageNumberRequests*/])(ClientPtr); +extern int (*SProcDamageVector[/*XDamageNumberRequests*/])(ClientPtr); + +#define VERIFY_DAMAGEEXT(pDamageExt, rid, client, mode) { \ + pDamageExt = SecurityLookupIDByType (client, rid, DamageExtType, mode); \ + if (!pDamageExt) { \ + client->errorValue = rid; \ + return DamageErrorBase + BadDamage; \ + } \ +} + +void +SDamageNotifyEvent (xDamageNotifyEvent *from, + xDamageNotifyEvent *to); + +void +DamageExtSetCritical (ClientPtr pClient, Bool critical); + +#endif /* _DAMAGEEXTINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damagestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damagestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/damagestr.h (revision 51223) @@ -0,0 +1,113 @@ +/* + * $Id: damagestr.h,v 1.6 2005/07/03 07:02:01 daniels Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGESTR_H_ +#define _DAMAGESTR_H_ + +#include "damage.h" +#ifdef RENDER +# include "picturestr.h" +#endif + +typedef struct _damage { + DamagePtr pNext; + DamagePtr pNextWin; + RegionRec damage; + + DamageReportLevel damageLevel; + Bool isInternal; + void *closure; + Bool isWindow; + DrawablePtr pDrawable; + + DamageReportFunc damageReport; + DamageDestroyFunc damageDestroy; +} DamageRec; + +typedef struct _damageScrPriv { + int internalLevel; + + /* + * For DDXen which don't provide GetScreenPixmap, this provides + * a place to hook damage for windows on the screen + */ + DamagePtr pScreenDamage; + + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + CloseScreenProcPtr CloseScreen; + CreateGCProcPtr CreateGC; + DestroyPixmapProcPtr DestroyPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + DestroyWindowProcPtr DestroyWindow; +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif + BSFuncRec BackingStoreFuncs; +} DamageScrPrivRec, *DamageScrPrivPtr; + +typedef struct _damageGCPriv { + GCOps *ops; + GCFuncs *funcs; +} DamageGCPrivRec, *DamageGCPrivPtr; + +extern int damageScrPrivateIndex; +extern int damagePixPrivateIndex; +extern int damageGCPrivateIndex; +extern int damageWinPrivateIndex; + +#define damageGetScrPriv(pScr) \ + ((DamageScrPrivPtr) (pScr)->devPrivates[damageScrPrivateIndex].ptr) + +#define damageScrPriv(pScr) \ + DamageScrPrivPtr pScrPriv = damageGetScrPriv(pScr) + +#define damageGetPixPriv(pPix) \ + ((DamagePtr) (pPix)->devPrivates[damagePixPrivateIndex].ptr) + +#define damgeSetPixPriv(pPix,v) \ + ((pPix)->devPrivates[damagePixPrivateIndex].ptr = (pointer ) (v)) + +#define damagePixPriv(pPix) \ + DamagePtr pDamage = damageGetPixPriv(pPix) + +#define damageGetGCPriv(pGC) \ + ((DamageGCPrivPtr) (pGC)->devPrivates[damageGCPrivateIndex].ptr) + +#define damageGCPriv(pGC) \ + DamageGCPrivPtr pGCPriv = damageGetGCPriv(pGC) + +#define damageGetWinPriv(pWin) \ + ((DamagePtr) (pWin)->devPrivates[damageWinPrivateIndex].ptr) + +#define damageSetWinPriv(pWin,d) \ + ((pWin)->devPrivates[damageWinPrivateIndex].ptr = (d)) + +#endif /* _DAMAGESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwin.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwin.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwin.h (revision 51223) @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2001-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwin.h,v 1.20 2003/11/15 00:07:09 torrey Exp $ */ + +#ifndef _DARWIN_H +#define _DARWIN_H + +#include +#include "inputstr.h" +#include "scrnintstr.h" +#include + +typedef struct { + void *framebuffer; + int x; + int y; + int width; + int height; + int pitch; + int colorType; + int bitsPerPixel; + int colorBitsPerPixel; + int bitsPerComponent; +} DarwinFramebufferRec, *DarwinFramebufferPtr; + + +// From darwin.c +void DarwinPrintBanner(); +int DarwinParseModifierList(const char *constmodifiers); +void DarwinAdjustScreenOrigins(ScreenInfo *pScreenInfo); +void xf86SetRootClip (ScreenPtr pScreen, BOOL enable); + +// From darwinEvents.c +Bool DarwinEQInit(DevicePtr pKbd, DevicePtr pPtr); +void DarwinEQEnqueue(const xEvent *e); +void DarwinEQPointerPost(xEvent *e); +void DarwinEQSwitchScreen(ScreenPtr pScreen, Bool fromDIX); + +// From darwinKeyboard.c +int DarwinModifierNXKeyToNXKeycode(int key, int side); +void DarwinKeyboardInit(DeviceIntPtr pDev); +int DarwinModifierNXKeycodeToNXKey(unsigned char keycode, int *outSide); +int DarwinModifierNXKeyToNXMask(int key); +int DarwinModifierNXMaskToNXKey(int mask); +int DarwinModifierStringToNXKey(const char *string); + +// Mode specific functions +Bool DarwinModeAddScreen(int index, ScreenPtr pScreen); +Bool DarwinModeSetupScreen(int index, ScreenPtr pScreen); +void DarwinModeInitOutput(int argc,char **argv); +void DarwinModeInitInput(int argc, char **argv); +int DarwinModeProcessArgument(int argc, char *argv[], int i); +void DarwinModeProcessEvent(xEvent *xe); +void DarwinModeGiveUp(void); +void DarwinModeBell(int volume, DeviceIntPtr pDevice, pointer ctrl, int class); + + +#undef assert +#define assert(x) { if ((x) == 0) \ + FatalError("assert failed on line %d of %s!\n", __LINE__, __FILE__); } +#define kern_assert(x) { if ((x) != KERN_SUCCESS) \ + FatalError("assert failed on line %d of %s with kernel return 0x%x!\n", \ + __LINE__, __FILE__, x); } +#define SCREEN_PRIV(pScreen) \ + ((DarwinFramebufferPtr)pScreen->devPrivates[darwinScreenIndex].ptr) + + +#define MIN_KEYCODE XkbMinLegalKeyCode // unfortunately, this isn't 0... + + +/* + * Global variables from darwin.c + */ +extern int darwinScreenIndex; // index into pScreen.devPrivates +extern int darwinScreensFound; +extern io_connect_t darwinParamConnect; +extern int darwinEventReadFD; +extern int darwinEventWriteFD; +extern DeviceIntPtr darwinPointer; +extern DeviceIntPtr darwinKeyboard; + +// User preferences +extern int darwinMouseAccelChange; +extern int darwinFakeButtons; +extern int darwinFakeMouse2Mask; +extern int darwinFakeMouse3Mask; +extern int darwinSwapAltMeta; +extern char *darwinKeymapFile; +extern int darwinSyncKeymap; +extern unsigned int darwinDesiredWidth, darwinDesiredHeight; +extern int darwinDesiredDepth; +extern int darwinDesiredRefresh; + +// location of X11's (0,0) point in global screen coordinates +extern int darwinMainScreenX; +extern int darwinMainScreenY; + + +/* + * Special ddx events understood by the X server + */ +enum { + kXDarwinUpdateModifiers // update all modifier keys + = LASTEvent+1, // (from X.h list of event names) + kXDarwinUpdateButtons, // update state of mouse buttons 2 and up + kXDarwinScrollWheel, // scroll wheel event + + /* + * Quartz-specific events -- not used in IOKit mode + */ + kXDarwinActivate, // restore X drawing and cursor + kXDarwinDeactivate, // clip X drawing and switch to Aqua cursor + kXDarwinSetRootClip, // enable or disable drawing to the X screen + kXDarwinQuit, // kill the X server and release the display + kXDarwinReadPasteboard, // copy Mac OS X pasteboard into X cut buffer + kXDarwinWritePasteboard, // copy X cut buffer onto Mac OS X pasteboard + /* + * AppleWM events + */ + kXDarwinControllerNotify, // send an AppleWMControllerNotify event + kXDarwinPasteboardNotify, // notify the WM to copy or paste + /* + * Xplugin notification events + */ + kXDarwinDisplayChanged, // display configuration has changed + kXDarwinWindowState, // window visibility state has changed + kXDarwinWindowMoved // window has moved on screen +}; + +#endif /* _DARWIN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinClut8.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinClut8.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinClut8.h (revision 51223) @@ -0,0 +1,532 @@ +/* + * Darwin default 8-bit Colormap for StaticColor + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwinClut8.h,v 1.1.8.1 2003/03/04 01:31:43 torrey Exp $ */ + +#ifndef _DARWIN_CLUT8_ +#define _DARWIN_CLUT8_ + +#ifdef USE_NEW_CLUT + +static xColorItem darwinClut8[] = { + { 0, 0xffff, 0xffff, 0xffff, 0, 0 }, + { 1, 0xfefe, 0xfefe, 0xfefe, 0, 0 }, + { 2, 0xfdfd, 0xfdfd, 0xfdfd, 0, 0 }, + { 3, 0xb8b8, 0x2727, 0x2b2b, 0, 0 }, + { 4, 0xfcfc, 0xfcfc, 0xfcfc, 0, 0 }, + { 5, 0xffff, 0xffff, 0x0, 0, 0 }, + { 6, 0xfafa, 0xfafa, 0xfafa, 0, 0 }, + { 7, 0xf9f9, 0xf9f9, 0xf9f9, 0, 0 }, + { 8, 0xf8f8, 0xf8f8, 0xf8f8, 0, 0 }, + { 9, 0xf7f7, 0xf7f7, 0xf7f7, 0, 0 }, + { 10, 0xf6f6, 0xf6f6, 0xf6f6, 0, 0 }, + { 11, 0xf5f5, 0xf5f5, 0xf5f5, 0, 0 }, + { 12, 0xf4f4, 0xf4f4, 0xf4f4, 0, 0 }, + { 13, 0xf2f2, 0xf2f2, 0xf2f2, 0, 0 }, + { 14, 0xf1f1, 0xf1f1, 0xf1f1, 0, 0 }, + { 15, 0x0, 0x0, 0x0, 0, 0 }, + { 16, 0xefef, 0xefef, 0xefef, 0, 0 }, + { 17, 0xeeee, 0xeeee, 0xeeee, 0, 0 }, + { 18, 0xeded, 0xeded, 0xeded, 0, 0 }, + { 19, 0xebeb, 0xebeb, 0xebeb, 0, 0 }, + { 20, 0xe8e8, 0xe8e8, 0xe8e8, 0, 0 }, + { 21, 0xe7e7, 0xe7e7, 0xe7e7, 0, 0 }, + { 22, 0xc9c9, 0x3838, 0x3e3e, 0, 0 }, + { 23, 0xe5e5, 0xe5e5, 0xe5e5, 0, 0 }, + { 24, 0xffff, 0x0, 0xffff, 0, 0 }, + { 25, 0xfbfb, 0xfbfb, 0xfbfb, 0, 0 }, + { 26, 0xdede, 0x6c6c, 0x7272, 0, 0 }, + { 27, 0xe0e0, 0xe0e0, 0xe0e0, 0, 0 }, + { 28, 0xe8e8, 0x8686, 0x9090, 0, 0 }, + { 29, 0xdede, 0xdede, 0xdede, 0, 0 }, + { 30, 0xdddd, 0xdddd, 0xdddd, 0, 0 }, + { 31, 0xd3d3, 0x7e7e, 0x8d8d, 0, 0 }, + { 32, 0xd9d9, 0xd9d9, 0xd9d9, 0, 0 }, + { 33, 0xf3f3, 0x9696, 0xa6a6, 0, 0 }, + { 34, 0xb1b1, 0x1c1c, 0x3939, 0, 0 }, + { 35, 0xffff, 0x0, 0x0, 0, 0 }, + { 36, 0xbebe, 0x5e5e, 0x7272, 0, 0 }, + { 37, 0xd3d3, 0xd3d3, 0xd3d3, 0, 0 }, + { 38, 0xc6c6, 0x2e2e, 0x6767, 0, 0 }, + { 39, 0xd1d1, 0xd1d1, 0xd1d1, 0, 0 }, + { 40, 0xa3a3, 0x606, 0x4545, 0, 0 }, + { 41, 0xcece, 0xcece, 0xcece, 0, 0 }, + { 42, 0xcccc, 0xcccc, 0xffff, 0, 0 }, + { 43, 0xcccc, 0xcccc, 0xcccc, 0, 0 }, + { 44, 0xc6c6, 0x8f8f, 0xa7a7, 0, 0 }, + { 45, 0xe1e1, 0xd3d3, 0xd9d9, 0, 0 }, + { 46, 0xcece, 0x9e9e, 0xb4b4, 0, 0 }, + { 47, 0xcaca, 0xcaca, 0xcaca, 0, 0 }, + { 48, 0xbfbf, 0x3f3f, 0x7d7d, 0, 0 }, + { 49, 0xc9c9, 0xc9c9, 0xc9c9, 0, 0 }, + { 50, 0xf4f4, 0x8989, 0xbebe, 0, 0 }, + { 51, 0xc6c6, 0xc6c6, 0xc6c6, 0, 0 }, + { 52, 0xd6d6, 0x5151, 0x9797, 0, 0 }, + { 53, 0xc9c9, 0x2c2c, 0x8484, 0, 0 }, + { 54, 0x9696, 0x1a1a, 0x6a6a, 0, 0 }, + { 55, 0xc2c2, 0xc2c2, 0xc2c2, 0, 0 }, + { 56, 0xf3f3, 0x6f6f, 0xc6c6, 0, 0 }, + { 57, 0xe5e5, 0x4c4c, 0xbbbb, 0, 0 }, + { 58, 0xb7b7, 0x5a5a, 0x9c9c, 0, 0 }, + { 59, 0xbfbf, 0xbfbf, 0xbfbf, 0, 0 }, + { 60, 0xbebe, 0xbebe, 0xbebe, 0, 0 }, + { 61, 0xbdbd, 0xbdbd, 0xbdbd, 0, 0 }, + { 62, 0xb8b8, 0x2121, 0xa2a2, 0, 0 }, + { 63, 0xd3d3, 0x4444, 0xc0c0, 0, 0 }, + { 64, 0xc2c2, 0x6666, 0xb7b7, 0, 0 }, + { 65, 0xf4f4, 0x6666, 0xe6e6, 0, 0 }, + { 66, 0xfcfc, 0x7373, 0xfdfd, 0, 0 }, + { 67, 0xb9b9, 0xb9b9, 0xb9b9, 0, 0 }, + { 68, 0xeaea, 0xdfdf, 0xeaea, 0, 0 }, + { 69, 0xd4d4, 0x7171, 0xd5d5, 0, 0 }, + { 70, 0xf9f9, 0x8b8b, 0xffff, 0, 0 }, + { 71, 0xf5f5, 0xadad, 0xffff, 0, 0 }, + { 72, 0xbcbc, 0x9292, 0xc2c2, 0, 0 }, + { 73, 0xc7c7, 0x4f4f, 0xd9d9, 0, 0 }, + { 74, 0xa0a0, 0x4444, 0xafaf, 0, 0 }, + { 75, 0xc8c8, 0x8c8c, 0xd5d5, 0, 0 }, + { 76, 0xd7d7, 0x7474, 0xf7f7, 0, 0 }, + { 77, 0xb4b4, 0xb4b4, 0xb4b4, 0, 0 }, + { 78, 0xdada, 0x9595, 0xf9f9, 0, 0 }, + { 79, 0xeded, 0xcbcb, 0xffff, 0, 0 }, + { 80, 0xb2b2, 0xb2b2, 0xb2b2, 0, 0 }, + { 81, 0xa1a1, 0x6161, 0xd7d7, 0, 0 }, + { 82, 0xb2b2, 0x8585, 0xe2e2, 0, 0 }, + { 83, 0x5959, 0x2626, 0x9c9c, 0, 0 }, + { 84, 0x7c7c, 0x5151, 0xcccc, 0, 0 }, + { 85, 0xb0b0, 0xb0b0, 0xb0b0, 0, 0 }, + { 86, 0xb4b4, 0x8e8e, 0xfcfc, 0, 0 }, + { 87, 0xd5d5, 0xc0c0, 0xffff, 0, 0 }, + { 88, 0x5d5d, 0x3232, 0xcccc, 0, 0 }, + { 89, 0x7b7b, 0x5c5c, 0xe5e5, 0, 0 }, + { 90, 0xc0c0, 0xb0b0, 0xfdfd, 0, 0 }, + { 91, 0x6060, 0x5353, 0xadad, 0, 0 }, + { 92, 0x1212, 0xc0c, 0x7e7e, 0, 0 }, + { 93, 0x2e2e, 0x2929, 0x9999, 0, 0 }, + { 94, 0x7979, 0x7878, 0xe9e9, 0, 0 }, + { 95, 0x5b5b, 0x5c5c, 0xd0d0, 0, 0 }, + { 96, 0x6969, 0x6a6a, 0xcccc, 0, 0 }, + { 97, 0x9393, 0x9494, 0xf8f8, 0, 0 }, + { 98, 0x9292, 0x9292, 0xc3c3, 0, 0 }, + { 99, 0x4141, 0x4444, 0xbaba, 0, 0 }, + { 100, 0xa8a8, 0xabab, 0xffff, 0, 0 }, + { 101, 0xa3a3, 0xa3a3, 0xa3a3, 0, 0 }, + { 102, 0xdbdb, 0xdddd, 0xeaea, 0, 0 }, + { 103, 0x3131, 0x4949, 0xaaaa, 0, 0 }, + { 104, 0x7070, 0x8f8f, 0xf9f9, 0, 0 }, + { 105, 0x4848, 0x6666, 0xc1c1, 0, 0 }, + { 106, 0x5c5c, 0x7e7e, 0xe9e9, 0, 0 }, + { 107, 0xe2e2, 0xe5e5, 0xebeb, 0, 0 }, + { 108, 0xb0b0, 0xcdcd, 0xffff, 0, 0 }, + { 109, 0x6c6c, 0x8989, 0xb7b7, 0, 0 }, + { 110, 0x3434, 0x6565, 0xafaf, 0, 0 }, + { 111, 0x8c8c, 0xb9b9, 0xffff, 0, 0 }, + { 112, 0x3737, 0x7979, 0xd4d4, 0, 0 }, + { 113, 0x5a5a, 0x9999, 0xeaea, 0, 0 }, + { 114, 0xe0e, 0x4c4c, 0x9595, 0, 0 }, + { 115, 0x7979, 0xb9b9, 0xffff, 0, 0 }, + { 116, 0x8a8a, 0xa3a3, 0xbcbc, 0, 0 }, + { 117, 0x2020, 0x6161, 0x9d9d, 0, 0 }, + { 118, 0x8f8f, 0xaeae, 0xcaca, 0, 0 }, + { 119, 0xa0a, 0x6060, 0xa8a8, 0, 0 }, + { 120, 0x3f3f, 0x9494, 0xd9d9, 0, 0 }, + { 121, 0x6363, 0xb5b5, 0xf9f9, 0, 0 }, + { 122, 0xe2e2, 0xe8e8, 0xeded, 0, 0 }, + { 123, 0x2828, 0x6a6a, 0x9999, 0, 0 }, + { 124, 0x5555, 0xb2b2, 0xe7e7, 0, 0 }, + { 125, 0x3232, 0x8989, 0xa9a9, 0, 0 }, + { 126, 0xcfcf, 0xdada, 0xdede, 0, 0 }, + { 127, 0x2929, 0xa1a1, 0xc7c7, 0, 0 }, + { 128, 0x8686, 0xa9a9, 0xb4b4, 0, 0 }, + { 129, 0x0, 0x5f5f, 0x7979, 0, 0 }, + { 130, 0xc0c, 0x7777, 0x8e8e, 0, 0 }, + { 131, 0x1212, 0x8f8f, 0xabab, 0, 0 }, + { 132, 0x4141, 0xbaba, 0xd5d5, 0, 0 }, + { 133, 0x2424, 0x8282, 0x8383, 0, 0 }, + { 134, 0x2c2c, 0xc4c4, 0xc3c3, 0, 0 }, + { 135, 0x1a1a, 0xabab, 0xa6a6, 0, 0 }, + { 136, 0x4b4b, 0xa8a8, 0xa2a2, 0, 0 }, + { 137, 0xa0a, 0x9393, 0x8585, 0, 0 }, + { 138, 0xd0d, 0xa5a5, 0x9696, 0, 0 }, + { 139, 0x2626, 0xbcbc, 0xacac, 0, 0 }, + { 140, 0x404, 0x8181, 0x7272, 0, 0 }, + { 141, 0x1919, 0xb3b3, 0x8686, 0, 0 }, + { 142, 0x2929, 0xc1c1, 0x9494, 0, 0 }, + { 143, 0x2121, 0x9c9c, 0x7171, 0, 0 }, + { 144, 0x202, 0x8c8c, 0x5050, 0, 0 }, + { 145, 0x3535, 0xd0d0, 0x8989, 0, 0 }, + { 146, 0x4646, 0xa5a5, 0x7676, 0, 0 }, + { 147, 0x202, 0x7d7d, 0x3939, 0, 0 }, + { 148, 0x2929, 0xc9c9, 0x7171, 0, 0 }, + { 149, 0x5757, 0xd6d6, 0x8f8f, 0, 0 }, + { 150, 0xa2a2, 0xb5b5, 0xaaaa, 0, 0 }, + { 151, 0x101, 0x8888, 0x2a2a, 0, 0 }, + { 152, 0x7474, 0xbebe, 0x8a8a, 0, 0 }, + { 153, 0x1919, 0xb6b6, 0x4747, 0, 0 }, + { 154, 0x2d2d, 0xc6c6, 0x5151, 0, 0 }, + { 155, 0x3838, 0xdede, 0x5d5d, 0, 0 }, + { 156, 0x4c4c, 0xf4f4, 0x6f6f, 0, 0 }, + { 157, 0x9191, 0x9c9c, 0x9393, 0, 0 }, + { 158, 0x0, 0x8e8e, 0x1919, 0, 0 }, + { 159, 0x1010, 0xafaf, 0x2828, 0, 0 }, + { 160, 0xe3e3, 0xe3e3, 0xe3e3, 0, 0 }, + { 161, 0x808, 0xa1a1, 0x1a1a, 0, 0 }, + { 162, 0x5959, 0xc2c2, 0x6161, 0, 0 }, + { 163, 0xf0f0, 0xf0f0, 0xf0f0, 0, 0 }, + { 164, 0x8f8f, 0x9c9c, 0x9090, 0, 0 }, + { 165, 0x2323, 0xcece, 0x2a2a, 0, 0 }, + { 166, 0x1212, 0xbaba, 0x1717, 0, 0 }, + { 167, 0x101, 0x8a8a, 0x202, 0, 0 }, + { 168, 0x303, 0x9a9a, 0x202, 0, 0 }, + { 169, 0x4040, 0xe4e4, 0x4040, 0, 0 }, + { 170, 0x808, 0xb2b2, 0x505, 0, 0 }, + { 171, 0x1313, 0xcccc, 0xf0f, 0, 0 }, + { 172, 0x3636, 0xd7d7, 0x3232, 0, 0 }, + { 173, 0x2828, 0xe9e9, 0x1f1f, 0, 0 }, + { 174, 0x5353, 0xfbfb, 0x4c4c, 0, 0 }, + { 175, 0x6f6f, 0xafaf, 0x6a6a, 0, 0 }, + { 176, 0x7171, 0xe0e0, 0x6767, 0, 0 }, + { 177, 0x3232, 0xc0c0, 0x1212, 0, 0 }, + { 178, 0x2929, 0xa5a5, 0x808, 0, 0 }, + { 179, 0x5c5c, 0xdddd, 0x3535, 0, 0 }, + { 180, 0x0, 0xffff, 0xffff, 0, 0 }, + { 181, 0x6363, 0xc8c8, 0x4545, 0, 0 }, + { 182, 0x8686, 0xfdfd, 0x5b5b, 0, 0 }, + { 183, 0x7171, 0xf6f6, 0x3939, 0, 0 }, + { 184, 0x5555, 0xcccc, 0x1515, 0, 0 }, + { 185, 0x0, 0xffff, 0x0, 0, 0 }, + { 186, 0x9090, 0xcaca, 0x6e6e, 0, 0 }, + { 187, 0x4343, 0xa7a7, 0x101, 0, 0 }, + { 188, 0x8d8d, 0xe4e4, 0x3737, 0, 0 }, + { 189, 0xb3b3, 0xf0f0, 0x6464, 0, 0 }, + { 190, 0x8585, 0x8e8e, 0x7a7a, 0, 0 }, + { 191, 0xb0b0, 0xfafa, 0x4d4d, 0, 0 }, + { 192, 0xd6d6, 0xd6d6, 0xd6d6, 0, 0 }, + { 193, 0x8888, 0xd0d0, 0x1a1a, 0, 0 }, + { 194, 0x6a6a, 0xa7a7, 0x303, 0, 0 }, + { 195, 0x9898, 0xbfbf, 0x4141, 0, 0 }, + { 196, 0xcdcd, 0xf8f8, 0x5151, 0, 0 }, + { 197, 0x9494, 0xa4a4, 0x5555, 0, 0 }, + { 198, 0x9191, 0xb0b0, 0xa0a, 0, 0 }, + { 199, 0xdada, 0xf1f1, 0x3c3c, 0, 0 }, + { 200, 0xbaba, 0xcaca, 0x5353, 0, 0 }, + { 201, 0xb9b9, 0xc3c3, 0x2828, 0, 0 }, + { 202, 0xb1b1, 0xbaba, 0x1212, 0, 0 }, + { 203, 0xd2d2, 0xd9d9, 0x2626, 0, 0 }, + { 204, 0xe8e8, 0xecec, 0x2d2d, 0, 0 }, + { 205, 0x9898, 0x9696, 0x202, 0, 0 }, + { 206, 0xadad, 0xadad, 0x5c5c, 0, 0 }, + { 207, 0xe2e2, 0xd8d8, 0x3838, 0, 0 }, + { 208, 0xd9d9, 0xc4c4, 0x3838, 0, 0 }, + { 209, 0xa8a8, 0x9a9a, 0x5050, 0, 0 }, + { 210, 0x0, 0x0, 0xffff, 0, 0 }, + { 211, 0xbebe, 0xaeae, 0x5e5e, 0, 0 }, + { 212, 0x9a9a, 0x9898, 0x8e8e, 0, 0 }, + { 213, 0xacac, 0x8d8d, 0xd0d, 0, 0 }, + { 214, 0xc5c5, 0xa0a0, 0x2b2b, 0, 0 }, + { 215, 0xdbdb, 0xb5b5, 0x4848, 0, 0 }, + { 216, 0xdddd, 0x0, 0x0, 0, 0 }, + { 217, 0x9c9c, 0x6d6d, 0x303, 0, 0 }, + { 218, 0xd4d4, 0xa8a8, 0x4747, 0, 0 }, + { 219, 0xb7b7, 0x7171, 0x1717, 0, 0 }, + { 220, 0xdcdc, 0xa1a1, 0x5a5a, 0, 0 }, + { 221, 0xb9b9, 0x9c9c, 0x7c7c, 0, 0 }, + { 222, 0xb4b4, 0xabab, 0xa2a2, 0, 0 }, + { 223, 0x9e9e, 0x4b4b, 0x101, 0, 0 }, + { 224, 0xc8c8, 0x7878, 0x3535, 0, 0 }, + { 225, 0xd2d2, 0x8d8d, 0x5151, 0, 0 }, + { 226, 0xadad, 0x5252, 0xf0f, 0, 0 }, + { 227, 0x0, 0xbbbb, 0x0, 0, 0 }, + { 228, 0xb2b2, 0x6666, 0x3838, 0, 0 }, + { 229, 0xb1b1, 0xa6a6, 0x9f9f, 0, 0 }, + { 230, 0xb1b1, 0x8787, 0x6f6f, 0, 0 }, + { 231, 0xa4a4, 0x3434, 0x303, 0, 0 }, + { 232, 0xeeee, 0x9e9e, 0x8585, 0, 0 }, + { 233, 0xc9c9, 0x7373, 0x5a5a, 0, 0 }, + { 234, 0xe6e6, 0x9494, 0x7c7c, 0, 0 }, + { 235, 0xa9a9, 0x2222, 0x606, 0, 0 }, + { 236, 0xdbdb, 0x8787, 0x7474, 0, 0 }, + { 237, 0xb0b0, 0x2e2e, 0x1515, 0, 0 }, + { 238, 0xb7b7, 0x5a5a, 0x5050, 0, 0 }, + { 239, 0xb2b2, 0x4242, 0x3b3b, 0, 0 }, + { 240, 0xcdcd, 0x7373, 0x6e6e, 0, 0 }, + { 241, 0xd9d9, 0x5858, 0x5858, 0, 0 }, + { 242, 0xacac, 0xacac, 0xacac, 0, 0 }, + { 243, 0xa0a0, 0xa0a0, 0xa0a0, 0, 0 }, + { 244, 0x9a9a, 0x9a9a, 0x9a9a, 0, 0 }, + { 245, 0x9292, 0x9292, 0x9292, 0, 0 }, + { 246, 0x8e8e, 0x8e8e, 0x8e8e, 0, 0 }, + { 247, 0xbbbb, 0xbbbb, 0xbbbb, 0, 0 }, + { 248, 0x8181, 0x8181, 0x8181, 0, 0 }, + { 249, 0x8888, 0x8888, 0x8888, 0, 0 }, + { 250, 0x7777, 0x7777, 0x7777, 0, 0 }, + { 251, 0x5555, 0x5555, 0x5555, 0, 0 }, + { 252, 0x4444, 0x4444, 0x4444, 0, 0 }, + { 253, 0x2222, 0x2222, 0x2222, 0, 0 }, + { 254, 0x7b7b, 0x7b7b, 0x7b7b, 0, 0 }, + { 255, 0x0, 0x0, 0x0, 0, 0 }, +}; + +#else /* !USE_NEW_CLUT */ + +static xColorItem darwinClut8[] = { + { 0, 0x0000, 0x0000, 0x0000, 0, 0 }, + { 1, 0xffff, 0xffff, 0xcccc, 0, 0 }, + { 2, 0xffff, 0xffff, 0x9999, 0, 0 }, + { 3, 0xffff, 0xffff, 0x6666, 0, 0 }, + { 4, 0xffff, 0xffff, 0x3333, 0, 0 }, + { 5, 0xffff, 0xffff, 0x0000, 0, 0 }, + { 6, 0xffff, 0xcccc, 0xffff, 0, 0 }, + { 7, 0xffff, 0xcccc, 0xcccc, 0, 0 }, + { 8, 0xffff, 0xcccc, 0x9999, 0, 0 }, + { 9, 0xffff, 0xcccc, 0x6666, 0, 0 }, + { 10, 0xffff, 0xcccc, 0x3333, 0, 0 }, + { 11, 0xffff, 0xcccc, 0x0000, 0, 0 }, + { 12, 0xffff, 0x9999, 0xffff, 0, 0 }, + { 13, 0xffff, 0x9999, 0xcccc, 0, 0 }, + { 14, 0xffff, 0x9999, 0x9999, 0, 0 }, + { 15, 0xffff, 0x9999, 0x6666, 0, 0 }, + { 16, 0xffff, 0x9999, 0x3333, 0, 0 }, + { 17, 0xffff, 0x9999, 0x0000, 0, 0 }, + { 18, 0xffff, 0x6666, 0xffff, 0, 0 }, + { 19, 0xffff, 0x6666, 0xcccc, 0, 0 }, + { 20, 0xffff, 0x6666, 0x9999, 0, 0 }, + { 21, 0xffff, 0x6666, 0x6666, 0, 0 }, + { 22, 0xffff, 0x6666, 0x3333, 0, 0 }, + { 23, 0xffff, 0x6666, 0x0000, 0, 0 }, + { 24, 0xffff, 0x3333, 0xffff, 0, 0 }, + { 25, 0xffff, 0x3333, 0xcccc, 0, 0 }, + { 26, 0xffff, 0x3333, 0x9999, 0, 0 }, + { 27, 0xffff, 0x3333, 0x6666, 0, 0 }, + { 28, 0xffff, 0x3333, 0x3333, 0, 0 }, + { 29, 0xffff, 0x3333, 0x0000, 0, 0 }, + { 30, 0xffff, 0x0000, 0xffff, 0, 0 }, + { 31, 0xffff, 0x0000, 0xcccc, 0, 0 }, + { 32, 0xffff, 0x0000, 0x9999, 0, 0 }, + { 33, 0xffff, 0x0000, 0x6666, 0, 0 }, + { 34, 0xffff, 0x0000, 0x3333, 0, 0 }, + { 35, 0xffff, 0x0000, 0x0000, 0, 0 }, + { 36, 0xcccc, 0xffff, 0xffff, 0, 0 }, + { 37, 0xcccc, 0xffff, 0xcccc, 0, 0 }, + { 38, 0xcccc, 0xffff, 0x9999, 0, 0 }, + { 39, 0xcccc, 0xffff, 0x6666, 0, 0 }, + { 40, 0xcccc, 0xffff, 0x3333, 0, 0 }, + { 41, 0xcccc, 0xffff, 0x0000, 0, 0 }, + { 42, 0xcccc, 0xcccc, 0xffff, 0, 0 }, + { 43, 0xcccc, 0xcccc, 0xcccc, 0, 0 }, + { 44, 0xcccc, 0xcccc, 0x9999, 0, 0 }, + { 45, 0xcccc, 0xcccc, 0x6666, 0, 0 }, + { 46, 0xcccc, 0xcccc, 0x3333, 0, 0 }, + { 47, 0xcccc, 0xcccc, 0x0000, 0, 0 }, + { 48, 0xcccc, 0x9999, 0xffff, 0, 0 }, + { 49, 0xcccc, 0x9999, 0xcccc, 0, 0 }, + { 50, 0xcccc, 0x9999, 0x9999, 0, 0 }, + { 51, 0xcccc, 0x9999, 0x6666, 0, 0 }, + { 52, 0xcccc, 0x9999, 0x3333, 0, 0 }, + { 53, 0xcccc, 0x9999, 0x0000, 0, 0 }, + { 54, 0xcccc, 0x6666, 0xffff, 0, 0 }, + { 55, 0xcccc, 0x6666, 0xcccc, 0, 0 }, + { 56, 0xcccc, 0x6666, 0x9999, 0, 0 }, + { 57, 0xcccc, 0x6666, 0x6666, 0, 0 }, + { 58, 0xcccc, 0x6666, 0x3333, 0, 0 }, + { 59, 0xcccc, 0x6666, 0x0000, 0, 0 }, + { 60, 0xcccc, 0x3333, 0xffff, 0, 0 }, + { 61, 0xcccc, 0x3333, 0xcccc, 0, 0 }, + { 62, 0xcccc, 0x3333, 0x9999, 0, 0 }, + { 63, 0xcccc, 0x3333, 0x6666, 0, 0 }, + { 64, 0xcccc, 0x3333, 0x3333, 0, 0 }, + { 65, 0xcccc, 0x3333, 0x0000, 0, 0 }, + { 66, 0xcccc, 0x0000, 0xffff, 0, 0 }, + { 67, 0xcccc, 0x0000, 0xcccc, 0, 0 }, + { 68, 0xcccc, 0x0000, 0x9999, 0, 0 }, + { 69, 0xcccc, 0x0000, 0x6666, 0, 0 }, + { 70, 0xcccc, 0x0000, 0x3333, 0, 0 }, + { 71, 0xcccc, 0x0000, 0x0000, 0, 0 }, + { 72, 0x9999, 0xffff, 0xffff, 0, 0 }, + { 73, 0x9999, 0xffff, 0xcccc, 0, 0 }, + { 74, 0x9999, 0xffff, 0x9999, 0, 0 }, + { 75, 0x9999, 0xffff, 0x6666, 0, 0 }, + { 76, 0x9999, 0xffff, 0x3333, 0, 0 }, + { 77, 0x9999, 0xffff, 0x0000, 0, 0 }, + { 78, 0x9999, 0xcccc, 0xffff, 0, 0 }, + { 79, 0x9999, 0xcccc, 0xcccc, 0, 0 }, + { 80, 0x9999, 0xcccc, 0x9999, 0, 0 }, + { 81, 0x9999, 0xcccc, 0x6666, 0, 0 }, + { 82, 0x9999, 0xcccc, 0x3333, 0, 0 }, + { 83, 0x9999, 0xcccc, 0x0000, 0, 0 }, + { 84, 0x9999, 0x9999, 0xffff, 0, 0 }, + { 85, 0x9999, 0x9999, 0xcccc, 0, 0 }, + { 86, 0x9999, 0x9999, 0x9999, 0, 0 }, + { 87, 0x9999, 0x9999, 0x6666, 0, 0 }, + { 88, 0x9999, 0x9999, 0x3333, 0, 0 }, + { 89, 0x9999, 0x9999, 0x0000, 0, 0 }, + { 90, 0x9999, 0x6666, 0xffff, 0, 0 }, + { 91, 0x9999, 0x6666, 0xcccc, 0, 0 }, + { 92, 0x9999, 0x6666, 0x9999, 0, 0 }, + { 93, 0x9999, 0x6666, 0x6666, 0, 0 }, + { 94, 0x9999, 0x6666, 0x3333, 0, 0 }, + { 95, 0x9999, 0x6666, 0x0000, 0, 0 }, + { 96, 0x9999, 0x3333, 0xffff, 0, 0 }, + { 97, 0x9999, 0x3333, 0xcccc, 0, 0 }, + { 98, 0x9999, 0x3333, 0x9999, 0, 0 }, + { 99, 0x9999, 0x3333, 0x6666, 0, 0 }, + { 100, 0x9999, 0x3333, 0x3333, 0, 0 }, + { 101, 0x9999, 0x3333, 0x0000, 0, 0 }, + { 102, 0x9999, 0x0000, 0xffff, 0, 0 }, + { 103, 0x9999, 0x0000, 0xcccc, 0, 0 }, + { 104, 0x9999, 0x0000, 0x9999, 0, 0 }, + { 105, 0x9999, 0x0000, 0x6666, 0, 0 }, + { 106, 0x9999, 0x0000, 0x3333, 0, 0 }, + { 107, 0x9999, 0x0000, 0x0000, 0, 0 }, + { 108, 0x6666, 0xffff, 0xffff, 0, 0 }, + { 109, 0x6666, 0xffff, 0xcccc, 0, 0 }, + { 110, 0x6666, 0xffff, 0x9999, 0, 0 }, + { 111, 0x6666, 0xffff, 0x6666, 0, 0 }, + { 112, 0x6666, 0xffff, 0x3333, 0, 0 }, + { 113, 0x6666, 0xffff, 0x0000, 0, 0 }, + { 114, 0x6666, 0xcccc, 0xffff, 0, 0 }, + { 115, 0x6666, 0xcccc, 0xcccc, 0, 0 }, + { 116, 0x6666, 0xcccc, 0x9999, 0, 0 }, + { 117, 0x6666, 0xcccc, 0x6666, 0, 0 }, + { 118, 0x6666, 0xcccc, 0x3333, 0, 0 }, + { 119, 0x6666, 0xcccc, 0x0000, 0, 0 }, + { 120, 0x6666, 0x9999, 0xffff, 0, 0 }, + { 121, 0x6666, 0x9999, 0xcccc, 0, 0 }, + { 122, 0x6666, 0x9999, 0x9999, 0, 0 }, + { 123, 0x6666, 0x9999, 0x6666, 0, 0 }, + { 124, 0x6666, 0x9999, 0x3333, 0, 0 }, + { 125, 0x6666, 0x9999, 0x0000, 0, 0 }, + { 126, 0x6666, 0x6666, 0xffff, 0, 0 }, + { 127, 0x6666, 0x6666, 0xcccc, 0, 0 }, + { 128, 0x6666, 0x6666, 0x9999, 0, 0 }, + { 129, 0x6666, 0x6666, 0x6666, 0, 0 }, + { 130, 0x6666, 0x6666, 0x3333, 0, 0 }, + { 131, 0x6666, 0x6666, 0x0000, 0, 0 }, + { 132, 0x6666, 0x3333, 0xffff, 0, 0 }, + { 133, 0x6666, 0x3333, 0xcccc, 0, 0 }, + { 134, 0x6666, 0x3333, 0x9999, 0, 0 }, + { 135, 0x6666, 0x3333, 0x6666, 0, 0 }, + { 136, 0x6666, 0x3333, 0x3333, 0, 0 }, + { 137, 0x6666, 0x3333, 0x0000, 0, 0 }, + { 138, 0x6666, 0x0000, 0xffff, 0, 0 }, + { 139, 0x6666, 0x0000, 0xcccc, 0, 0 }, + { 140, 0x6666, 0x0000, 0x9999, 0, 0 }, + { 141, 0x6666, 0x0000, 0x6666, 0, 0 }, + { 142, 0x6666, 0x0000, 0x3333, 0, 0 }, + { 143, 0x6666, 0x0000, 0x0000, 0, 0 }, + { 144, 0x3333, 0xffff, 0xffff, 0, 0 }, + { 145, 0x3333, 0xffff, 0xcccc, 0, 0 }, + { 146, 0x3333, 0xffff, 0x9999, 0, 0 }, + { 147, 0x3333, 0xffff, 0x6666, 0, 0 }, + { 148, 0x3333, 0xffff, 0x3333, 0, 0 }, + { 149, 0x3333, 0xffff, 0x0000, 0, 0 }, + { 150, 0x3333, 0xcccc, 0xffff, 0, 0 }, + { 151, 0x3333, 0xcccc, 0xcccc, 0, 0 }, + { 152, 0x3333, 0xcccc, 0x9999, 0, 0 }, + { 153, 0x3333, 0xcccc, 0x6666, 0, 0 }, + { 154, 0x3333, 0xcccc, 0x3333, 0, 0 }, + { 155, 0x3333, 0xcccc, 0x0000, 0, 0 }, + { 156, 0x3333, 0x9999, 0xffff, 0, 0 }, + { 157, 0x3333, 0x9999, 0xcccc, 0, 0 }, + { 158, 0x3333, 0x9999, 0x9999, 0, 0 }, + { 159, 0x3333, 0x9999, 0x6666, 0, 0 }, + { 160, 0x3333, 0x9999, 0x3333, 0, 0 }, + { 161, 0x3333, 0x9999, 0x0000, 0, 0 }, + { 162, 0x3333, 0x6666, 0xffff, 0, 0 }, + { 163, 0x3333, 0x6666, 0xcccc, 0, 0 }, + { 164, 0x3333, 0x6666, 0x9999, 0, 0 }, + { 165, 0x3333, 0x6666, 0x6666, 0, 0 }, + { 166, 0x3333, 0x6666, 0x3333, 0, 0 }, + { 167, 0x3333, 0x6666, 0x0000, 0, 0 }, + { 168, 0x3333, 0x3333, 0xffff, 0, 0 }, + { 169, 0x3333, 0x3333, 0xcccc, 0, 0 }, + { 170, 0x3333, 0x3333, 0x9999, 0, 0 }, + { 171, 0x3333, 0x3333, 0x6666, 0, 0 }, + { 172, 0x3333, 0x3333, 0x3333, 0, 0 }, + { 173, 0x3333, 0x3333, 0x0000, 0, 0 }, + { 174, 0x3333, 0x0000, 0xffff, 0, 0 }, + { 175, 0x3333, 0x0000, 0xcccc, 0, 0 }, + { 176, 0x3333, 0x0000, 0x9999, 0, 0 }, + { 177, 0x3333, 0x0000, 0x6666, 0, 0 }, + { 178, 0x3333, 0x0000, 0x3333, 0, 0 }, + { 179, 0x3333, 0x0000, 0x0000, 0, 0 }, + { 180, 0x0000, 0xffff, 0xffff, 0, 0 }, + { 181, 0x0000, 0xffff, 0xcccc, 0, 0 }, + { 182, 0x0000, 0xffff, 0x9999, 0, 0 }, + { 183, 0x0000, 0xffff, 0x6666, 0, 0 }, + { 184, 0x0000, 0xffff, 0x3333, 0, 0 }, + { 185, 0x0000, 0xffff, 0x0000, 0, 0 }, + { 186, 0x0000, 0xcccc, 0xffff, 0, 0 }, + { 187, 0x0000, 0xcccc, 0xcccc, 0, 0 }, + { 188, 0x0000, 0xcccc, 0x9999, 0, 0 }, + { 189, 0x0000, 0xcccc, 0x6666, 0, 0 }, + { 190, 0x0000, 0xcccc, 0x3333, 0, 0 }, + { 191, 0x0000, 0xcccc, 0x0000, 0, 0 }, + { 192, 0x0000, 0x9999, 0xffff, 0, 0 }, + { 193, 0x0000, 0x9999, 0xcccc, 0, 0 }, + { 194, 0x0000, 0x9999, 0x9999, 0, 0 }, + { 195, 0x0000, 0x9999, 0x6666, 0, 0 }, + { 196, 0x0000, 0x9999, 0x3333, 0, 0 }, + { 197, 0x0000, 0x9999, 0x0000, 0, 0 }, + { 198, 0x0000, 0x6666, 0xffff, 0, 0 }, + { 199, 0x0000, 0x6666, 0xcccc, 0, 0 }, + { 200, 0x0000, 0x6666, 0x9999, 0, 0 }, + { 201, 0x0000, 0x6666, 0x6666, 0, 0 }, + { 202, 0x0000, 0x6666, 0x3333, 0, 0 }, + { 203, 0x0000, 0x6666, 0x0000, 0, 0 }, + { 204, 0x0000, 0x3333, 0xffff, 0, 0 }, + { 205, 0x0000, 0x3333, 0xcccc, 0, 0 }, + { 206, 0x0000, 0x3333, 0x9999, 0, 0 }, + { 207, 0x0000, 0x3333, 0x6666, 0, 0 }, + { 208, 0x0000, 0x3333, 0x3333, 0, 0 }, + { 209, 0x0000, 0x3333, 0x0000, 0, 0 }, + { 210, 0x0000, 0x0000, 0xffff, 0, 0 }, + { 211, 0x0000, 0x0000, 0xcccc, 0, 0 }, + { 212, 0x0000, 0x0000, 0x9999, 0, 0 }, + { 213, 0x0000, 0x0000, 0x6666, 0, 0 }, + { 214, 0x0000, 0x0000, 0x3333, 0, 0 }, + { 215, 0xeeee, 0x0000, 0x0000, 0, 0 }, + { 216, 0xdddd, 0x0000, 0x0000, 0, 0 }, + { 217, 0xbbbb, 0x0000, 0x0000, 0, 0 }, + { 218, 0xaaaa, 0x0000, 0x0000, 0, 0 }, + { 219, 0x8888, 0x0000, 0x0000, 0, 0 }, + { 220, 0x7777, 0x0000, 0x0000, 0, 0 }, + { 221, 0x5555, 0x0000, 0x0000, 0, 0 }, + { 222, 0x4444, 0x0000, 0x0000, 0, 0 }, + { 223, 0x2222, 0x0000, 0x0000, 0, 0 }, + { 224, 0x1111, 0x0000, 0x0000, 0, 0 }, + { 225, 0x0000, 0xeeee, 0x0000, 0, 0 }, + { 226, 0x0000, 0xdddd, 0x0000, 0, 0 }, + { 227, 0x0000, 0xbbbb, 0x0000, 0, 0 }, + { 228, 0x0000, 0xaaaa, 0x0000, 0, 0 }, + { 229, 0x0000, 0x8888, 0x0000, 0, 0 }, + { 230, 0x0000, 0x7777, 0x0000, 0, 0 }, + { 231, 0x0000, 0x5555, 0x0000, 0, 0 }, + { 232, 0x0000, 0x4444, 0x0000, 0, 0 }, + { 233, 0x0000, 0x2222, 0x0000, 0, 0 }, + { 234, 0x0000, 0x1111, 0x0000, 0, 0 }, + { 235, 0x0000, 0x0000, 0xeeee, 0, 0 }, + { 236, 0x0000, 0x0000, 0xdddd, 0, 0 }, + { 237, 0x0000, 0x0000, 0xbbbb, 0, 0 }, + { 238, 0x0000, 0x0000, 0xaaaa, 0, 0 }, + { 239, 0x0000, 0x0000, 0x8888, 0, 0 }, + { 240, 0x0000, 0x0000, 0x7777, 0, 0 }, + { 241, 0x0000, 0x0000, 0x5555, 0, 0 }, + { 242, 0x0000, 0x0000, 0x4444, 0, 0 }, + { 243, 0x0000, 0x0000, 0x2222, 0, 0 }, + { 244, 0x0000, 0x0000, 0x1111, 0, 0 }, + { 245, 0xeeee, 0xeeee, 0xeeee, 0, 0 }, + { 246, 0xdddd, 0xdddd, 0xdddd, 0, 0 }, + { 247, 0xbbbb, 0xbbbb, 0xbbbb, 0, 0 }, + { 248, 0xaaaa, 0xaaaa, 0xaaaa, 0, 0 }, + { 249, 0x8888, 0x8888, 0x8888, 0, 0 }, + { 250, 0x7777, 0x7777, 0x7777, 0, 0 }, + { 251, 0x5555, 0x5555, 0x5555, 0, 0 }, + { 252, 0x4444, 0x4444, 0x4444, 0, 0 }, + { 253, 0x2222, 0x2222, 0x2222, 0, 0 }, + { 254, 0x1111, 0x1111, 0x1111, 0, 0 }, + { 255, 0xffff, 0xffff, 0xffff, 0, 0 } +}; +#endif /* USE_NEW_CLUT */ + +#endif /* _DARWIN_CLUT8_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinKeyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinKeyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/darwinKeyboard.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwinKeyboard.c,v 1.18 2003/05/14 05:27:55 torrey Exp $ */ + +#ifndef DARWIN_KEYBOARD_H +#define DARWIN_KEYBOARD_H 1 + +#define XK_TECHNICAL // needed to get XK_Escape +#define XK_PUBLISHING +#include "keysym.h" +#include "inputstr.h" + +// Each key can generate 4 glyphs. They are, in order: +// unshifted, shifted, modeswitch unshifted, modeswitch shifted +#define GLYPHS_PER_KEY 4 +#define NUM_KEYCODES 248 // NX_NUMKEYCODES might be better +#define MAX_KEYCODE NUM_KEYCODES + MIN_KEYCODE - 1 + +typedef struct darwinKeyboardInfo_struct { + CARD8 modMap[MAP_LENGTH]; + KeySym keyMap[MAP_LENGTH * GLYPHS_PER_KEY]; + unsigned char modifierKeycodes[32][2]; +} darwinKeyboardInfo; + +void DarwinKeyboardReload(DeviceIntPtr pDev); +unsigned int DarwinModeSystemKeymapSeed(void); +Bool DarwinModeReadSystemKeymap(darwinKeyboardInfo *info); + +#endif /* DARWIN_KEYBOARD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dbestruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dbestruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dbestruct.h (revision 51223) @@ -0,0 +1,237 @@ +/* $Xorg: dbestruct.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for DIX-related DBE + * + *****************************************************************************/ +/* $XFree86$ */ + +#ifndef DBE_STRUCT_H +#define DBE_STRUCT_H + + +/* INCLUDES */ + +#define NEED_DBE_PROTOCOL +#include +#include "windowstr.h" + + +/* DEFINES */ + +#define DBE_SCREEN_PRIV(pScreen) \ + ((dbeScreenPrivIndex < 0) ? \ + NULL : \ + ((DbeScreenPrivPtr)((pScreen)->devPrivates[dbeScreenPrivIndex].ptr))) + +#define DBE_SCREEN_PRIV_FROM_DRAWABLE(pDrawable) \ + DBE_SCREEN_PRIV((pDrawable)->pScreen) + +#define DBE_SCREEN_PRIV_FROM_WINDOW_PRIV(pDbeWindowPriv) \ + DBE_SCREEN_PRIV((pDbeWindowPriv)->pWindow->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_WINDOW(pWindow) \ + DBE_SCREEN_PRIV((pWindow)->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_PIXMAP(pPixmap) \ + DBE_SCREEN_PRIV((pPixmap)->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_GC(pGC)\ + DBE_SCREEN_PRIV((pGC)->pScreen) + +#define DBE_WINDOW_PRIV(pWindow)\ + ((dbeWindowPrivIndex < 0) ? \ + NULL : \ + ((DbeWindowPrivPtr)(pWindow->devPrivates[dbeWindowPrivIndex].ptr))) + +/* Initial size of the buffer ID array in the window priv. */ +#define DBE_INIT_MAX_IDS 2 + +/* Reallocation increment for the buffer ID array. */ +#define DBE_INCR_MAX_IDS 4 + +/* Marker for free elements in the buffer ID array. */ +#define DBE_FREE_ID_ELEMENT 0 + + +/* TYPEDEFS */ + +/* Record used to pass swap information between DIX and DDX swapping + * procedures. + */ +typedef struct _DbeSwapInfoRec +{ + WindowPtr pWindow; + unsigned char swapAction; + +} DbeSwapInfoRec, *DbeSwapInfoPtr; + +/* + ****************************************************************************** + ** Per-window data + ****************************************************************************** + */ + +typedef struct _DbeWindowPrivRec +{ + /* A pointer to the window with which the DBE window private (buffer) is + * associated. + */ + WindowPtr pWindow; + + /* Last known swap action for this buffer. Legal values for this field + * are XdbeUndefined, XdbeBackground, XdbeUntouched, and XdbeCopied. + */ + unsigned char swapAction; + + /* Last known buffer size. + */ + unsigned short width, height; + + /* Coordinates used for static gravity when the window is positioned. + */ + short x, y; + + /* Number of XIDs associated with this buffer. + */ + int nBufferIDs; + + /* Capacity of the current buffer ID array, IDs. */ + int maxAvailableIDs; + + /* Pointer to the array of buffer IDs. This initially points to initIDs. + * When the static limit of the initIDs array is reached, the array is + * reallocated and this pointer is set to the new array instead of initIDs. + */ + XID *IDs; + + /* Initial array of buffer IDs. We are defining the XID array within the + * window priv to optimize for data locality. In most cases, only one + * buffer will be associated with a window. Having the array declared + * here can prevent us from accessing the data in another memory page, + * possibly resulting in a page swap and loss of performance. Initially we + * will use this array to store buffer IDs. For situations where we have + * more IDs than can fit in this static array, we will allocate a larger + * array to use, possibly suffering a performance loss. + */ + XID initIDs[DBE_INIT_MAX_IDS]; + + /* Device-specific private information. + */ + DevUnion *devPrivates; + +} DbeWindowPrivRec, *DbeWindowPrivPtr; + + +/* + ****************************************************************************** + ** Per-screen data + ****************************************************************************** + */ + +typedef struct _DbeScreenPrivRec +{ + /* Info for creating window privs */ + int winPrivPrivLen; /* Length of privs in DbeWindowPrivRec */ + unsigned int *winPrivPrivSizes; /* Array of private record sizes */ + unsigned int totalWinPrivSize; /* PrivRec + size of all priv priv ptrs */ + + /* Resources created by DIX to be used by DDX */ + RESTYPE dbeDrawableResType; + RESTYPE dbeWindowPrivResType; + + /* Private indices created by DIX to be used by DDX */ + int dbeScreenPrivIndex; + int dbeWindowPrivIndex; + + /* Wrapped functions + * It is the responsibilty of the DDX layer to wrap PositionWindow(). + * DbeExtensionInit wraps DestroyWindow(). + */ + PositionWindowProcPtr PositionWindow; + DestroyWindowProcPtr DestroyWindow; + + /* Per-screen DIX routines */ + Bool (*SetupBackgroundPainter)( + WindowPtr /*pWin*/, + GCPtr /*pGC*/ +); + DbeWindowPrivPtr (*AllocWinPriv)( + ScreenPtr /*pScreen*/ +); + int (*AllocWinPrivPrivIndex)( + void +); + Bool (*AllocWinPrivPriv)( + ScreenPtr /*pScreen*/, + int /*index*/, + unsigned /*amount*/ +); + + /* Per-screen DDX routines */ + Bool (*GetVisualInfo)( + ScreenPtr /*pScreen*/, + XdbeScreenVisualInfo * /*pVisInfo*/ +); + int (*AllocBackBufferName)( + WindowPtr /*pWin*/, + XID /*bufId*/, + int /*swapAction*/ +); + int (*SwapBuffers)( + ClientPtr /*client*/, + int * /*pNumWindows*/, + DbeSwapInfoPtr /*swapInfo*/ +); + void (*BeginIdiom)( + ClientPtr /*client*/ +); + void (*EndIdiom)( + ClientPtr /*client*/ +); + void (*WinPrivDelete)( + DbeWindowPrivPtr /*pDbeWindowPriv*/, + XID /*bufId*/ +); + void (*ResetProc)( + ScreenPtr /*pScreen*/ +); + void (*ValidateBuffer)( + WindowPtr /*pWin*/, + XID /*bufId*/, + Bool /*dstbuffer*/ +); + + /* Device-specific private information. + */ + DevUnion *devPrivates; + +} DbeScreenPrivRec, *DbeScreenPrivPtr; + +#endif /* DBE_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ddcPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ddcPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ddcPriv.h (revision 51223) @@ -0,0 +1,9 @@ +extern unsigned char *GetEDID_DDC1( + unsigned int * +); + +extern int DDC_checksum( + unsigned char *, + int +); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/debug.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/debug.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/debug.h (revision 51223) @@ -0,0 +1,210 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() +# define CHECK_SP_ACCESS() +# define CHECK_MEM_ACCESS() +# define CHECK_DATA_ACCESS() +#endif + +#ifdef DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef DEBUG +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (char *x); +extern void x86emu_decode_printf2 (char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/decode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/decode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/decode.h (revision 51223) @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +u32 decode_rm00_address(int rm); +u32 decode_rm01_address(int rm); +u32 decode_rm10_address(int rm); +u32 decode_sib_address(int sib, int mod); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/devbell.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/devbell.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/devbell.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/devbell.h,v 3.1 1996/04/15 11:18:32 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DEVBELL_H +#define DEVBELL_H 1 + +int +SProcXDeviceBell ( + ClientPtr /* client */ + ); + +int +ProcXDeviceBell ( + ClientPtr /* client */ + ); + +#endif /* DEVBELL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dgaproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dgaproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dgaproc.h (revision 51223) @@ -0,0 +1,144 @@ +/* $XFree86: xc/programs/Xserver/Xext/dgaproc.h,v 1.21 2000/06/30 19:06:54 keithp Exp $ */ + +#ifndef __DGAPROC_H +#define __DGAPROC_H + +#include +#include "pixmap.h" + +#define DGA_CONCURRENT_ACCESS 0x00000001 +#define DGA_FILL_RECT 0x00000002 +#define DGA_BLIT_RECT 0x00000004 +#define DGA_BLIT_RECT_TRANS 0x00000008 +#define DGA_PIXMAP_AVAILABLE 0x00000010 + +#define DGA_INTERLACED 0x00010000 +#define DGA_DOUBLESCAN 0x00020000 + +#define DGA_FLIP_IMMEDIATE 0x00000001 +#define DGA_FLIP_RETRACE 0x00000002 + +#define DGA_COMPLETED 0x00000000 +#define DGA_PENDING 0x00000001 + +#define DGA_NEED_ROOT 0x00000001 + +typedef struct { + int num; /* A unique identifier for the mode (num > 0) */ + char *name; /* name of mode given in the XF86Config */ + int VSync_num; + int VSync_den; + int flags; /* DGA_CONCURRENT_ACCESS, etc... */ + int imageWidth; /* linear accessible portion (pixels) */ + int imageHeight; + int pixmapWidth; /* Xlib accessible portion (pixels) */ + int pixmapHeight; /* both fields ignored if no concurrent access */ + int bytesPerScanline; + int byteOrder; /* MSBFirst, LSBFirst */ + int depth; + int bitsPerPixel; + unsigned long red_mask; + unsigned long green_mask; + unsigned long blue_mask; + short visualClass; + int viewportWidth; + int viewportHeight; + int xViewportStep; /* viewport position granularity */ + int yViewportStep; + int maxViewportX; /* max viewport origin */ + int maxViewportY; + int viewportFlags; /* types of page flipping possible */ + int offset; + int reserved1; + int reserved2; +} XDGAModeRec, *XDGAModePtr; + +/* DDX interface */ + +int +DGASetMode( + int Index, + int num, + XDGAModePtr mode, + PixmapPtr *pPix +); + +void +DGASetInputMode( + int Index, + Bool keyboard, + Bool mouse +); + +void +DGASelectInput( + int Index, + ClientPtr client, + long mask +); + +Bool DGAAvailable(int Index); +Bool DGAActive(int Index); +void DGAShutdown(void); +void DGAInstallCmap(ColormapPtr cmap); +int DGAGetViewportStatus(int Index); +int DGASync(int Index); + +int +DGAFillRect( + int Index, + int x, int y, int w, int h, + unsigned long color +); + +int +DGABlitRect( + int Index, + int srcx, int srcy, + int w, int h, + int dstx, int dsty +); + +int +DGABlitTransRect( + int Index, + int srcx, int srcy, + int w, int h, + int dstx, int dsty, + unsigned long color +); + +int +DGASetViewport( + int Index, + int x, int y, + int mode +); + +int DGAGetModes(int Index); +int DGAGetOldDGAMode(int Index); + +int DGAGetModeInfo(int Index, XDGAModePtr mode, int num); + +Bool DGAVTSwitch(void); +Bool DGAStealMouseEvent(int Index, xEvent *e, int dx, int dy); +Bool DGAStealKeyEvent(int Index, xEvent *e); +Bool DGAIsDgaEvent (xEvent *e); + +Bool DGADeliverEvent (ScreenPtr pScreen, xEvent *e); + +Bool DGAOpenFramebuffer(int Index, char **name, unsigned char **mem, + int *size, int *offset, int *flags); +void DGACloseFramebuffer(int Index); +Bool DGAChangePixmapMode(int Index, int *x, int *y, int mode); +int DGACreateColormap(int Index, ClientPtr client, int id, int mode, + int alloc); + +extern unsigned char DGAReqCode; +extern int DGAErrorBase; +extern int DGAEventBase; +extern int *XDGAEventBase; + + + +#endif /* __DGAPROC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dispatch.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dispatch.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dispatch.h (revision 51223) @@ -0,0 +1,147 @@ +/* $XFree86: xc/programs/Xserver/dix/dispatch.h,v 3.2 2001/08/01 00:44:48 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/* + * This prototypes the dispatch.c module (except for functions declared in + * global headers), plus related dispatch procedures from devices.c, events.c, + * extension.c, property.c. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DISPATCH_H +#define DISPATCH_H 1 + +DISPATCH_PROC(InitClientPrivates); +DISPATCH_PROC(ProcAllocColor); +DISPATCH_PROC(ProcAllocColorCells); +DISPATCH_PROC(ProcAllocColorPlanes); +DISPATCH_PROC(ProcAllocNamedColor); +DISPATCH_PROC(ProcBell); +DISPATCH_PROC(ProcChangeAccessControl); +DISPATCH_PROC(ProcChangeCloseDownMode); +DISPATCH_PROC(ProcChangeGC); +DISPATCH_PROC(ProcChangeHosts); +DISPATCH_PROC(ProcChangeKeyboardControl); +DISPATCH_PROC(ProcChangeKeyboardMapping); +DISPATCH_PROC(ProcChangePointerControl); +DISPATCH_PROC(ProcChangeProperty); +DISPATCH_PROC(ProcChangeSaveSet); +DISPATCH_PROC(ProcChangeWindowAttributes); +DISPATCH_PROC(ProcCirculateWindow); +DISPATCH_PROC(ProcClearToBackground); +DISPATCH_PROC(ProcCloseFont); +DISPATCH_PROC(ProcConfigureWindow); +DISPATCH_PROC(ProcConvertSelection); +DISPATCH_PROC(ProcCopyArea); +DISPATCH_PROC(ProcCopyColormapAndFree); +DISPATCH_PROC(ProcCopyGC); +DISPATCH_PROC(ProcCopyPlane); +DISPATCH_PROC(ProcCreateColormap); +DISPATCH_PROC(ProcCreateCursor); +DISPATCH_PROC(ProcCreateGC); +DISPATCH_PROC(ProcCreateGlyphCursor); +DISPATCH_PROC(ProcCreatePixmap); +DISPATCH_PROC(ProcCreateWindow); +DISPATCH_PROC(ProcDeleteProperty); +DISPATCH_PROC(ProcDestroySubwindows); +DISPATCH_PROC(ProcDestroyWindow); +DISPATCH_PROC(ProcEstablishConnection); +DISPATCH_PROC(ProcFillPoly); +DISPATCH_PROC(ProcForceScreenSaver); +DISPATCH_PROC(ProcFreeColormap); +DISPATCH_PROC(ProcFreeColors); +DISPATCH_PROC(ProcFreeCursor); +DISPATCH_PROC(ProcFreeGC); +DISPATCH_PROC(ProcFreePixmap); +DISPATCH_PROC(ProcGetAtomName); +DISPATCH_PROC(ProcGetFontPath); +DISPATCH_PROC(ProcGetGeometry); +DISPATCH_PROC(ProcGetImage); +DISPATCH_PROC(ProcGetKeyboardControl); +DISPATCH_PROC(ProcGetKeyboardMapping); +DISPATCH_PROC(ProcGetModifierMapping); +DISPATCH_PROC(ProcGetMotionEvents); +DISPATCH_PROC(ProcGetPointerControl); +DISPATCH_PROC(ProcGetPointerMapping); +DISPATCH_PROC(ProcGetProperty); +DISPATCH_PROC(ProcGetScreenSaver); +DISPATCH_PROC(ProcGetSelectionOwner); +DISPATCH_PROC(ProcGetWindowAttributes); +DISPATCH_PROC(ProcGrabServer); +DISPATCH_PROC(ProcImageText16); +DISPATCH_PROC(ProcImageText8); +DISPATCH_PROC(ProcInitialConnection); +DISPATCH_PROC(ProcInstallColormap); +DISPATCH_PROC(ProcInternAtom); +DISPATCH_PROC(ProcKillClient); +DISPATCH_PROC(ProcListExtensions); +DISPATCH_PROC(ProcListFonts); +DISPATCH_PROC(ProcListFontsWithInfo); +DISPATCH_PROC(ProcListHosts); +DISPATCH_PROC(ProcListInstalledColormaps); +DISPATCH_PROC(ProcListProperties); +DISPATCH_PROC(ProcLookupColor); +DISPATCH_PROC(ProcMapSubwindows); +DISPATCH_PROC(ProcMapWindow); +DISPATCH_PROC(ProcNoOperation); +DISPATCH_PROC(ProcOpenFont); +DISPATCH_PROC(ProcPolyArc); +DISPATCH_PROC(ProcPolyFillArc); +DISPATCH_PROC(ProcPolyFillRectangle); +DISPATCH_PROC(ProcPolyLine); +DISPATCH_PROC(ProcPolyPoint); +DISPATCH_PROC(ProcPolyRectangle); +DISPATCH_PROC(ProcPolySegment); +DISPATCH_PROC(ProcPolyText); +DISPATCH_PROC(ProcPutImage); +DISPATCH_PROC(ProcQueryBestSize); +DISPATCH_PROC(ProcQueryColors); +DISPATCH_PROC(ProcQueryExtension); +DISPATCH_PROC(ProcQueryFont); +DISPATCH_PROC(ProcQueryKeymap); +DISPATCH_PROC(ProcQueryTextExtents); +DISPATCH_PROC(ProcQueryTree); +DISPATCH_PROC(ProcReparentWindow); +DISPATCH_PROC(ProcRotateProperties); +DISPATCH_PROC(ProcSetClipRectangles); +DISPATCH_PROC(ProcSetDashes); +DISPATCH_PROC(ProcSetFontPath); +DISPATCH_PROC(ProcSetModifierMapping); +DISPATCH_PROC(ProcSetPointerMapping); +DISPATCH_PROC(ProcSetScreenSaver); +DISPATCH_PROC(ProcSetSelectionOwner); +DISPATCH_PROC(ProcStoreColors); +DISPATCH_PROC(ProcStoreNamedColor); +DISPATCH_PROC(ProcTranslateCoords); +DISPATCH_PROC(ProcUngrabServer); +DISPATCH_PROC(ProcUninstallColormap); +DISPATCH_PROC(ProcUnmapSubwindows); +DISPATCH_PROC(ProcUnmapWindow); + +#endif /* DISPATCH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix-config.h (revision 51223) @@ -0,0 +1,425 @@ +/* include/dix-config.h. Generated by configure. */ +/* dix-config.h.in: not at all generated. -*- c -*- */ + +#ifndef _DIX_CONFIG_H_ +#define _DIX_CONFIG_H_ + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Builder address */ +#define BUILDERADDR "xorg@lists.freedesktop.org" + +/* Operating System Name */ +#define OSNAME "Linux 2.6.15-rc6-gdf7addbb ia64" + +/* Operating System Vendor */ +#define OSVENDOR "" + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/opt/debrix/lib/X11/fonts/misc/,/opt/debrix/lib/X11/fonts/TTF/,/opt/debrix/lib/X11/fonts/OTF,/opt/debrix/lib/X11/fonts/Type1/,/opt/debrix/lib/X11/fonts/CID/,/opt/debrix/lib/X11/fonts/100dpi/,/opt/debrix/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP + systems. This function is required for `alloca.c' support on those systems. + */ +/* #undef CRAY_STACKSEG_END */ + +/* Define to 1 if using `alloca.c'. */ +/* #undef C_ALLOCA */ + +/* Support Damage extension */ +#define DAMAGE 1 + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Use GetTimeInMillis */ +/* #undef DDXTIME */ + +/* Use OsVendorFatalError */ +/* #undef DDXOSFATALERROR */ + +/* Use OsVendorVErrorF */ +/* #undef DDXOSVERRORF */ + +/* Use ddxBeforeReset */ +/* #undef DDXBEFORERESET */ + +/* Build DPMS extension */ +#define DPMSExtension 1 + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Include handhelds.org h3600 touchscreen driver */ +/* #undef H3600_TS */ + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* Define to 1 if you have the `getdtablesize' function. */ +#define HAS_GETDTABLESIZE 1 + +/* Define to 1 if you have the `getifaddrs' function. */ +#define HAS_GETIFADDRS 1 + +/* Define to 1 if you have the `getpeereid' function. */ +/* #undef HAS_GETPEEREID */ + +/* Define to 1 if you have the `getpeerucred' function. */ +/* #undef HAS_GETPEERUCRED */ + +/* Support SHM */ +#define HAS_SHM 1 + +/* Define to 1 if you have `alloca', as a function or macro. */ +#define HAVE_ALLOCA 1 + +/* Define to 1 if you have and it should be used (not on Ultrix). + */ +#define HAVE_ALLOCA_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_ASM_MTRR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +#define HAVE_DIRENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you don't have `vprintf' but do have `_doprnt.' */ +/* #undef HAVE_DOPRNT */ + +/* Define to 1 if you have the header file. */ +#define HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `geteuid' function. */ +#define HAVE_GETEUID 1 + +/* Define to 1 if you have the `getopt' function. */ +#define HAVE_GETOPT 1 + +/* Define to 1 if you have the `getopt_long' function. */ +#define HAVE_GETOPT_LONG 1 + +/* Define to 1 if you have the `getuid' function. */ +#define HAVE_GETUID 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `m' library (-lm). */ +#define HAVE_LIBM 1 + +/* Define to 1 if you have the `link' function. */ +#define HAVE_LINK 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_AGPGART_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APM_BIOS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_FB_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_H3600_TS_H */ + +/* Define to 1 if you have the `memmove' function. */ +#define HAVE_MEMMOVE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have the `memset' function. */ +#define HAVE_MEMSET 1 + +/* Define to 1 if you have the `mkstemp' function. */ +#define HAVE_MKSTEMP 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_NDBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. */ +/* #undef HAVE_NDIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_RPCSVC_DBM_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the `strchr' function. */ +#define HAVE_STRCHR 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the `strrchr' function. */ +#define HAVE_STRRCHR 1 + +/* Define to 1 if you have the `strtol' function. */ +#define HAVE_STRTOL 1 + +/* Define to 1 if SYSV IPC is available */ +/* #undef HAVE_SYSV_IPC */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_AGPIO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_DIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_IO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_NDIR_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_VM86_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_TSLIB_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to 1 if you have the `vprintf' function. */ +#define HAVE_VPRINTF 1 + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM Extension */ +#define MITSHM 1 + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Name of package */ +#define PACKAGE "xorg-server" + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Overall prefix */ +#define PROJECTROOT "/opt/debrix" + +/* Support RANDR extension */ +#define RANDR 1 + +/* Support Record extension */ +#define XRECORD 1 + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ +/* #undef STACK_DIRECTION */ + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Enable touchscreen support */ +/* #undef TOUCHSCREEN */ + +/* Support tslib touchscreen abstraction library */ +/* #undef TSLIB */ + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* Use builtin rgb color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* unaligned word accesses behave as expected */ +/* #undef WORKING_UNALIGNED_INT */ + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Build Security extension */ +#define XCSECURITY 1 + +/* Support Xdmcp */ +#define XDMCP 1 + +/* Build XEvIE extension */ +#define XEVIE 1 + +/* Build XFree86 BigFont extension */ +#define XF86BIGFONT 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Support XFixes extension */ +#define XFIXES 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Enable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Vendor release */ +#define XORG_RELEASE "Release 7.0" + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((0) * 100000) + ((0) * 1000) + 0) + +/* Xorg release date */ +#define XORG_DATE "21 December 2005" + +/* Build Xv Extension */ +#define XvExtension 1 + +/* Build XvMC Extension */ +#define XvMCExtension 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv extension */ +#define XV 1 + +/* Build LBX extension */ +#define LBX 1 + +/* Build APPGROUP extension */ +#define XAPPGROUP 1 + +/* Build TOG-CUP extension */ +#define TOGCUP 1 + +/* Build Extended-Visual-Information extension */ +#define EVI 1 + +/* Build Multibuffer extension */ +/* #undef MULTIBUFFER */ + +/* Support DRI extension */ +#define XF86DRI 1 + +/* Build DBE support */ +#define DBE 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +#ifndef _XOPEN_SOURCE +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 +#endif + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ + +/* Define to `int' if does not define. */ +/* #undef pid_t */ + +/* Build Rootless code */ +/* #undef ROOTLESS */ + +/* Define to 1 if unsigned long is 64 bits. */ +#define _XSERVER64 1 + +/* Define to location of RGB database */ +#define RGB_DB "/opt/debrix/share/X11/rgb" + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +#endif /* _DIX_CONFIG_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dix.h (revision 51223) @@ -0,0 +1,817 @@ +/* $XFree86: xc/programs/Xserver/include/dix.h,v 3.26 2003/01/12 02:44:27 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: dix.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef DIX_H +#define DIX_H + +#include "gc.h" +#include "window.h" +#include "input.h" + +#define EARLIER -1 +#define SAMETIME 0 +#define LATER 1 + +#define NullClient ((ClientPtr) 0) +#define REQUEST(type) \ + register type *stuff = (type *)client->requestBuffer + + +#define REQUEST_SIZE_MATCH(req)\ + if ((sizeof(req) >> 2) != client->req_len)\ + return(BadLength) + +#define REQUEST_AT_LEAST_SIZE(req) \ + if ((sizeof(req) >> 2) > client->req_len )\ + return(BadLength) + +#define REQUEST_FIXED_SIZE(req, n)\ + if (((sizeof(req) >> 2) > client->req_len) || \ + (((sizeof(req) + (n) + 3) >> 2) != client->req_len)) \ + return(BadLength) + +#define LEGAL_NEW_RESOURCE(id,client)\ + if (!LegalNewID(id,client)) \ + {\ + client->errorValue = id;\ + return(BadIDChoice);\ + } + +/* XXX if you are using this macro, you are probably not generating Match + * errors where appropriate */ +#define LOOKUP_DRAWABLE(did, client)\ + ((client->lastDrawableID == did) ? \ + client->lastDrawable : (DrawablePtr)LookupDrawable(did, client)) + +#ifdef XCSECURITY + +#define SECURITY_VERIFY_DRAWABLE(pDraw, did, client, mode)\ + if (client->lastDrawableID == did && !client->trustLevel)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ + RC_DRAWABLE, mode);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + if (pDraw->type == UNDRAWABLE_WINDOW)\ + return BadMatch;\ + } + +#define SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, mode)\ + if (client->lastDrawableID == did && !client->trustLevel)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ + RC_DRAWABLE, mode);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + } + +#define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ + if (client->lastGCID == rid && !client->trustLevel)\ + pGC = client->lastGC;\ + else\ + pGC = (GC *) SecurityLookupIDByType(client, rid, RT_GC, mode);\ + if (!pGC)\ + {\ + client->errorValue = rid;\ + return (BadGC);\ + } + +#define VERIFY_DRAWABLE(pDraw, did, client)\ + SECURITY_VERIFY_DRAWABLE(pDraw, did, client, SecurityUnknownAccess) + +#define VERIFY_GEOMETRABLE(pDraw, did, client)\ + SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, SecurityUnknownAccess) + +#define VERIFY_GC(pGC, rid, client)\ + SECURITY_VERIFY_GC(pGC, rid, client, SecurityUnknownAccess) + +#else /* not XCSECURITY */ + +#define VERIFY_DRAWABLE(pDraw, did, client)\ + if (client->lastDrawableID == did)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) LookupIDByClass(did, RC_DRAWABLE);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + if (pDraw->type == UNDRAWABLE_WINDOW)\ + return BadMatch;\ + } + +#define VERIFY_GEOMETRABLE(pDraw, did, client)\ + if (client->lastDrawableID == did)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) LookupIDByClass(did, RC_DRAWABLE);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + } + +#define VERIFY_GC(pGC, rid, client)\ + if (client->lastGCID == rid)\ + pGC = client->lastGC;\ + else\ + pGC = (GC *)LookupIDByType(rid, RT_GC);\ + if (!pGC)\ + {\ + client->errorValue = rid;\ + return (BadGC);\ + } + +#define SECURITY_VERIFY_DRAWABLE(pDraw, did, client, mode)\ + VERIFY_DRAWABLE(pDraw, did, client) + +#define SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, mode)\ + VERIFY_GEOMETRABLE(pDraw, did, client) + +#define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ + VERIFY_GC(pGC, rid, client) + +#endif /* XCSECURITY */ + +/* + * We think that most hardware implementations of DBE will want + * LookupID*(dbe_back_buffer_id) to return the window structure that the + * id is a back buffer for. Since both front and back buffers will + * return the same structure, you need to be able to distinguish + * somewhere what kind of buffer (front/back) was being asked for, so + * that ddx can render to the right place. That's the problem that the + * following code solves. Note: we couldn't embed this in the LookupID* + * functions because the VALIDATE_DRAWABLE_AND_GC macro often circumvents + * those functions by checking a one-element cache. That's why we're + * mucking with VALIDATE_DRAWABLE_AND_GC. + * + * If you put -DNEED_DBE_BUF_BITS into PervasiveDBEDefines, the window + * structure will have two additional bits defined, srcBuffer and + * dstBuffer, and their values will be maintained via the macros + * SET_DBE_DSTBUF and SET_DBE_SRCBUF (below). If you also + * put -DNEED_DBE_BUF_VALIDATE into PervasiveDBEDefines, the function + * DbeValidateBuffer will be called any time the bits change to give you + * a chance to do some setup. See the DBE code for more details on this + * function. We put in these levels of conditionality so that you can do + * just what you need to do, and no more. If neither of these defines + * are used, the bits won't be there, and VALIDATE_DRAWABLE_AND_GC will + * be unchanged. dpw + */ + +#if defined(NEED_DBE_BUF_BITS) +#define SET_DBE_DSTBUF(_pDraw, _drawID) \ + SET_DBE_BUF(_pDraw, _drawID, dstBuffer, TRUE) +#define SET_DBE_SRCBUF(_pDraw, _drawID) \ + SET_DBE_BUF(_pDraw, _drawID, srcBuffer, FALSE) +#if defined (NEED_DBE_BUF_VALIDATE) +#define SET_DBE_BUF(_pDraw, _drawID, _whichBuffer, _dstbuf) \ + if (_pDraw->type == DRAWABLE_WINDOW)\ + {\ + int thisbuf = (_pDraw->id == _drawID);\ + if (thisbuf != ((WindowPtr)_pDraw)->_whichBuffer)\ + {\ + ((WindowPtr)_pDraw)->_whichBuffer = thisbuf;\ + DbeValidateBuffer((WindowPtr)_pDraw, _drawID, _dstbuf);\ + }\ + } +#else /* want buffer bits, but don't need to call DbeValidateBuffer */ +#define SET_DBE_BUF(_pDraw, _drawID, _whichBuffer, _dstbuf) \ + if (_pDraw->type == DRAWABLE_WINDOW)\ + {\ + ((WindowPtr)_pDraw)->_whichBuffer = (_pDraw->id == _drawID);\ + } +#endif /* NEED_DBE_BUF_VALIDATE */ +#else /* don't want buffer bits in window */ +#define SET_DBE_DSTBUF(_pDraw, _drawID) /**/ +#define SET_DBE_SRCBUF(_pDraw, _drawID) /**/ +#endif /* NEED_DBE_BUF_BITS */ + +#define VALIDATE_DRAWABLE_AND_GC(drawID, pDraw, pGC, client)\ + if ((stuff->gc == INVALID) || (client->lastGCID != stuff->gc) ||\ + (client->lastDrawableID != drawID))\ + {\ + SECURITY_VERIFY_GEOMETRABLE(pDraw, drawID, client, SecurityWriteAccess);\ + SECURITY_VERIFY_GC(pGC, stuff->gc, client, SecurityReadAccess);\ + if ((pGC->depth != pDraw->depth) ||\ + (pGC->pScreen != pDraw->pScreen))\ + return (BadMatch);\ + client->lastDrawable = pDraw;\ + client->lastDrawableID = drawID;\ + client->lastGC = pGC;\ + client->lastGCID = stuff->gc;\ + }\ + else\ + {\ + pGC = client->lastGC;\ + pDraw = client->lastDrawable;\ + }\ + SET_DBE_DSTBUF(pDraw, drawID);\ + if (pGC->serialNumber != pDraw->serialNumber)\ + ValidateGC(pDraw, pGC); + + +#define WriteReplyToClient(pClient, size, pReply) { \ + if ((pClient)->swapped) \ + (*ReplySwapVector[((xReq *)(pClient)->requestBuffer)->reqType]) \ + (pClient, (int)(size), pReply); \ + else (void) WriteToClient(pClient, (int)(size), (char *)(pReply)); } + +#define WriteSwappedDataToClient(pClient, size, pbuf) \ + if ((pClient)->swapped) \ + (*(pClient)->pSwapReplyFunc)(pClient, (int)(size), pbuf); \ + else (void) WriteToClient (pClient, (int)(size), (char *)(pbuf)); + +typedef struct _TimeStamp *TimeStampPtr; + +#ifndef _XTYPEDEF_CLIENTPTR +typedef struct _Client *ClientPtr; /* also in misc.h */ +#define _XTYPEDEF_CLIENTPTR +#endif + +typedef struct _WorkQueue *WorkQueuePtr; + +extern ClientPtr requestingClient; +extern ClientPtr *clients; +extern ClientPtr serverClient; +extern int currentMaxClients; + +typedef int HWEventQueueType; +typedef HWEventQueueType* HWEventQueuePtr; + +extern HWEventQueuePtr checkForInput[2]; + +typedef struct _TimeStamp { + CARD32 months; /* really ~49.7 days */ + CARD32 milliseconds; +} TimeStamp; + +/* dispatch.c */ + +extern void SetInputCheck( + HWEventQueuePtr /*c0*/, + HWEventQueuePtr /*c1*/); + +extern void CloseDownClient( + ClientPtr /*client*/); + +extern void UpdateCurrentTime(void); + +extern void UpdateCurrentTimeIf(void); + +extern void InitSelections(void); + +extern void FlushClientCaches(XID /*id*/); + +extern int dixDestroyPixmap( + pointer /*value*/, + XID /*pid*/); + +extern void CloseDownRetainedResources(void); + +extern void InitClient( + ClientPtr /*client*/, + int /*i*/, + pointer /*ospriv*/); + +extern ClientPtr NextAvailableClient( + pointer /*ospriv*/); + +extern void SendErrorToClient( + ClientPtr /*client*/, + unsigned int /*majorCode*/, + unsigned int /*minorCode*/, + XID /*resId*/, + int /*errorCode*/); + +extern void DeleteWindowFromAnySelections( + WindowPtr /*pWin*/); + +extern void MarkClientException( + ClientPtr /*client*/); + +extern int GetGeometry( + ClientPtr /*client*/, + xGetGeometryReply* /* wa */); + +extern int SendConnSetup( + ClientPtr /*client*/, + char* /*reason*/); + +extern int DoGetImage( + ClientPtr /*client*/, + int /*format*/, + Drawable /*drawable*/, + int /*x*/, + int /*y*/, + int /*width*/, + int /*height*/, + Mask /*planemask*/, + xGetImageReply ** /*im_return*/); + +#ifdef LBX +extern void IncrementClientCount(void); +#endif /* LBX */ + +#if defined(DDXBEFORERESET) +extern void ddxBeforeReset (void); +#endif + +/* dixutils.c */ + +extern void CopyISOLatin1Lowered( + unsigned char * /*dest*/, + unsigned char * /*source*/, + int /*length*/); + +extern int CompareISOLatin1Lowered( + unsigned char * /*a*/, + int alen, + unsigned char * /*b*/, + int blen); + +#ifdef XCSECURITY + +extern WindowPtr SecurityLookupWindow( + XID /*rid*/, + ClientPtr /*client*/, + Mask /*access_mode*/); + +extern pointer SecurityLookupDrawable( + XID /*rid*/, + ClientPtr /*client*/, + Mask /*access_mode*/); + +extern WindowPtr LookupWindow( + XID /*rid*/, + ClientPtr /*client*/); + +extern pointer LookupDrawable( + XID /*rid*/, + ClientPtr /*client*/); + +#else + +extern WindowPtr LookupWindow( + XID /*rid*/, + ClientPtr /*client*/); + +extern pointer LookupDrawable( + XID /*rid*/, + ClientPtr /*client*/); + +#define SecurityLookupWindow(rid, client, access_mode) \ + LookupWindow(rid, client) + +#define SecurityLookupDrawable(rid, client, access_mode) \ + LookupDrawable(rid, client) + +#endif /* XCSECURITY */ + +extern ClientPtr LookupClient( + XID /*rid*/, + ClientPtr /*client*/); + +extern void NoopDDA(void); + +extern int AlterSaveSetForClient( + ClientPtr /*client*/, + WindowPtr /*pWin*/, + unsigned /*mode*/, + Bool /*toRoot*/, + Bool /*remap*/); + +extern void DeleteWindowFromAnySaveSet( + WindowPtr /*pWin*/); + +extern void BlockHandler( + pointer /*pTimeout*/, + pointer /*pReadmask*/); + +extern void WakeupHandler( + int /*result*/, + pointer /*pReadmask*/); + +typedef void (* WakeupHandlerProcPtr)( + pointer /* blockData */, + int /* result */, + pointer /* pReadmask */); + +extern Bool RegisterBlockAndWakeupHandlers( + BlockHandlerProcPtr /*blockHandler*/, + WakeupHandlerProcPtr /*wakeupHandler*/, + pointer /*blockData*/); + +extern void RemoveBlockAndWakeupHandlers( + BlockHandlerProcPtr /*blockHandler*/, + WakeupHandlerProcPtr /*wakeupHandler*/, + pointer /*blockData*/); + +extern void InitBlockAndWakeupHandlers(void); + +extern void ProcessWorkQueue(void); + +extern void ProcessWorkQueueZombies(void); + +extern Bool QueueWorkProc( + Bool (* /*function*/)( + ClientPtr /*clientUnused*/, + pointer /*closure*/), + ClientPtr /*client*/, + pointer /*closure*/ +); + +typedef Bool (* ClientSleepProcPtr)( + ClientPtr /*client*/, + pointer /*closure*/); + +extern Bool ClientSleep( + ClientPtr /*client*/, + ClientSleepProcPtr /* function */, + pointer /*closure*/); + +#ifndef ___CLIENTSIGNAL_DEFINED___ +#define ___CLIENTSIGNAL_DEFINED___ +extern Bool ClientSignal( + ClientPtr /*client*/); +#endif /* ___CLIENTSIGNAL_DEFINED___ */ + +extern void ClientWakeup( + ClientPtr /*client*/); + +extern Bool ClientIsAsleep( + ClientPtr /*client*/); + +/* atom.c */ + +extern Atom MakeAtom( + char * /*string*/, + unsigned /*len*/, + Bool /*makeit*/); + +extern Bool ValidAtom( + Atom /*atom*/); + +extern char *NameForAtom( + Atom /*atom*/); + +extern void AtomError(void); + +extern void FreeAllAtoms(void); + +extern void InitAtoms(void); + +/* events.c */ + +extern void SetMaskForEvent( + Mask /* mask */, + int /* event */); + + +extern Bool IsParent( + WindowPtr /* maybeparent */, + WindowPtr /* child */); + +extern WindowPtr GetCurrentRootWindow(void); + +extern WindowPtr GetSpriteWindow(void); + + +extern void NoticeEventTime(xEventPtr /* xE */); + +extern void EnqueueEvent( + xEventPtr /* xE */, + DeviceIntPtr /* device */, + int /* count */); + +extern void ComputeFreezes(void); + +extern void CheckGrabForSyncs( + DeviceIntPtr /* dev */, + Bool /* thisMode */, + Bool /* otherMode */); + +extern void ActivatePointerGrab( + DeviceIntPtr /* mouse */, + GrabPtr /* grab */, + TimeStamp /* time */, + Bool /* autoGrab */); + +extern void DeactivatePointerGrab( + DeviceIntPtr /* mouse */); + +extern void ActivateKeyboardGrab( + DeviceIntPtr /* keybd */, + GrabPtr /* grab */, + TimeStamp /* time */, + Bool /* passive */); + +extern void DeactivateKeyboardGrab( + DeviceIntPtr /* keybd */); + +extern void AllowSome( + ClientPtr /* client */, + TimeStamp /* time */, + DeviceIntPtr /* thisDev */, + int /* newState */); + +extern void ReleaseActiveGrabs( + ClientPtr client); + +extern int DeliverEventsToWindow( + WindowPtr /* pWin */, + xEventPtr /* pEvents */, + int /* count */, + Mask /* filter */, + GrabPtr /* grab */, + int /* mskidx */); + +extern int DeliverDeviceEvents( + WindowPtr /* pWin */, + xEventPtr /* xE */, + GrabPtr /* grab */, + WindowPtr /* stopAt */, + DeviceIntPtr /* dev */, + int /* count */); + +extern void DefineInitialRootWindow( + WindowPtr /* win */); + +extern void WindowHasNewCursor( + WindowPtr /* pWin */); + +extern Bool CheckDeviceGrabs( + DeviceIntPtr /* device */, + xEventPtr /* xE */, + int /* checkFirst */, + int /* count */); + +extern void DeliverFocusedEvent( + DeviceIntPtr /* keybd */, + xEventPtr /* xE */, + WindowPtr /* window */, + int /* count */); + +extern void DeliverGrabbedEvent( + xEventPtr /* xE */, + DeviceIntPtr /* thisDev */, + Bool /* deactivateGrab */, + int /* count */); + +#ifdef XKB +extern void FixKeyState( + xEvent * /* xE */, + DeviceIntPtr /* keybd */); +#endif /* XKB */ + +extern void RecalculateDeliverableEvents( + WindowPtr /* pWin */); + +extern int OtherClientGone( + pointer /* value */, + XID /* id */); + +extern void DoFocusEvents( + DeviceIntPtr /* dev */, + WindowPtr /* fromWin */, + WindowPtr /* toWin */, + int /* mode */); + +extern int SetInputFocus( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + Window /* focusID */, + CARD8 /* revertTo */, + Time /* ctime */, + Bool /* followOK */); + +extern int GrabDevice( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned /* this_mode */, + unsigned /* other_mode */, + Window /* grabWindow */, + unsigned /* ownerEvents */, + Time /* ctime */, + Mask /* mask */, + CARD8 * /* status */); + +extern void InitEvents(void); + +extern void CloseDownEvents(void); + +extern void DeleteWindowFromAnyEvents( + WindowPtr /* pWin */, + Bool /* freeResources */); + + +extern Mask EventMaskForClient( + WindowPtr /* pWin */, + ClientPtr /* client */); + + + +extern int DeliverEvents( + WindowPtr /*pWin*/, + xEventPtr /*xE*/, + int /*count*/, + WindowPtr /*otherParent*/); + + +extern void WriteEventsToClient( + ClientPtr /*pClient*/, + int /*count*/, + xEventPtr /*events*/); + +extern int TryClientEvents( + ClientPtr /*client*/, + xEventPtr /*pEvents*/, + int /*count*/, + Mask /*mask*/, + Mask /*filter*/, + GrabPtr /*grab*/); + +extern void WindowsRestructured(void); + + +#ifdef RANDR +void +ScreenRestructured (ScreenPtr pScreen); +#endif + +extern void ResetClientPrivates(void); + +extern int AllocateClientPrivateIndex(void); + +extern Bool AllocateClientPrivate( + int /*index*/, + unsigned /*amount*/); + +/* + * callback manager stuff + */ + +#ifndef _XTYPEDEF_CALLBACKLISTPTR +typedef struct _CallbackList *CallbackListPtr; /* also in misc.h */ +#define _XTYPEDEF_CALLBACKLISTPTR +#endif + +typedef void (*CallbackProcPtr) ( + CallbackListPtr *, pointer, pointer); + +typedef Bool (*AddCallbackProcPtr) ( + CallbackListPtr *, CallbackProcPtr, pointer); + +typedef Bool (*DeleteCallbackProcPtr) ( + CallbackListPtr *, CallbackProcPtr, pointer); + +typedef void (*CallCallbacksProcPtr) ( + CallbackListPtr *, pointer); + +typedef void (*DeleteCallbackListProcPtr) ( + CallbackListPtr *); + +typedef struct _CallbackProcs { + AddCallbackProcPtr AddCallback; + DeleteCallbackProcPtr DeleteCallback; + CallCallbacksProcPtr CallCallbacks; + DeleteCallbackListProcPtr DeleteCallbackList; +} CallbackFuncsRec, *CallbackFuncsPtr; + +extern Bool CreateCallbackList( + CallbackListPtr * /*pcbl*/, + CallbackFuncsPtr /*cbfuncs*/); + +extern Bool AddCallback( + CallbackListPtr * /*pcbl*/, + CallbackProcPtr /*callback*/, + pointer /*data*/); + +extern Bool DeleteCallback( + CallbackListPtr * /*pcbl*/, + CallbackProcPtr /*callback*/, + pointer /*data*/); + +extern void CallCallbacks( + CallbackListPtr * /*pcbl*/, + pointer /*call_data*/); + +extern void DeleteCallbackList( + CallbackListPtr * /*pcbl*/); + +extern void InitCallbackManager(void); + +/* + * ServerGrabCallback stuff + */ + +extern CallbackListPtr ServerGrabCallback; + +typedef enum {SERVER_GRABBED, SERVER_UNGRABBED, + CLIENT_PERVIOUS, CLIENT_IMPERVIOUS } ServerGrabState; + +typedef struct { + ClientPtr client; + ServerGrabState grabstate; +} ServerGrabInfoRec; + +/* + * EventCallback stuff + */ + +extern CallbackListPtr EventCallback; + +typedef struct { + ClientPtr client; + xEventPtr events; + int count; +} EventInfoRec; + +/* + * DeviceEventCallback stuff + */ + +extern CallbackListPtr DeviceEventCallback; + +typedef struct { + xEventPtr events; + int count; +} DeviceEventInfoRec; + +/* + * SelectionCallback stuff + */ + +extern CallbackListPtr SelectionCallback; + +typedef enum { + SelectionSetOwner, + SelectionWindowDestroy, + SelectionClientClose +} SelectionCallbackKind; + +typedef struct { + struct _Selection *selection; + SelectionCallbackKind kind; +} SelectionInfoRec; + +#endif /* DIX_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixevents.h (revision 51223) @@ -0,0 +1,106 @@ +/* $XFree86: xc/programs/Xserver/include/dixevents.h,v 3.4 2001/09/04 14:03:27 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef DIXEVENTS_H +#define DIXEVENTS_H + +extern void SetCriticalEvent(int /* event */); + +extern CursorPtr GetSpriteCursor(void); + +extern int ProcAllowEvents(ClientPtr /* client */); + +extern int MaybeDeliverEventsToClient( + WindowPtr /* pWin */, + xEvent * /* pEvents */, + int /* count */, + Mask /* filter */, + ClientPtr /* dontClient */); + +extern int ProcWarpPointer(ClientPtr /* client */); + +#if 0 +extern void +#ifdef XKB +CoreProcessKeyboardEvent ( +#else +ProcessKeyboardEvent ( +#endif + xEvent * /* xE */, + DeviceIntPtr /* keybd */, + int /* count */); + +extern void +#ifdef XKB +CoreProcessPointerEvent ( +#else +ProcessPointerEvent ( +#endif + xEvent * /* xE */, + DeviceIntPtr /* mouse */, + int /* count */); +#endif + +extern int EventSelectForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */); + +extern int EventSuppressForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + Bool * /* checkOptional */); + +extern int ProcSetInputFocus(ClientPtr /* client */); + +extern int ProcGetInputFocus(ClientPtr /* client */); + +extern int ProcGrabPointer(ClientPtr /* client */); + +extern int ProcChangeActivePointerGrab(ClientPtr /* client */); + +extern int ProcUngrabPointer(ClientPtr /* client */); + +extern int ProcGrabKeyboard(ClientPtr /* client */); + +extern int ProcUngrabKeyboard(ClientPtr /* client */); + +extern int ProcQueryPointer(ClientPtr /* client */); + +extern int ProcSendEvent(ClientPtr /* client */); + +extern int ProcUngrabKey(ClientPtr /* client */); + +extern int ProcGrabKey(ClientPtr /* client */); + +extern int ProcGrabButton(ClientPtr /* client */); + +extern int ProcUngrabButton(ClientPtr /* client */); + +extern int ProcRecolorCursor(ClientPtr /* client */); + +#endif /* DIXEVENTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfont.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfont.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfont.h (revision 51223) @@ -0,0 +1,155 @@ +/* $Xorg: dixfont.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/dixfont.h,v 3.7 2001/02/02 21:39:02 herrb Exp $ */ + +#ifndef DIXFONT_H +#define DIXFONT_H 1 + +#include "dix.h" +#include +#include "closure.h" +#include + +#define NullDIXFontProp ((DIXFontPropPtr)0) + +typedef struct _DIXFontProp *DIXFontPropPtr; + +extern FPEFunctions *fpe_functions; + +extern int FontToXError(int /*err*/); + +extern Bool SetDefaultFont(char * /*defaultfontname*/); + +extern void QueueFontWakeup(FontPathElementPtr /*fpe*/); + +extern void RemoveFontWakeup(FontPathElementPtr /*fpe*/); + +extern void FontWakeup(pointer /*data*/, + int /*count*/, + pointer /*LastSelectMask*/); + +extern int OpenFont(ClientPtr /*client*/, + XID /*fid*/, + Mask /*flags*/, + unsigned /*lenfname*/, + char * /*pfontname*/); + +extern int CloseFont(pointer /*pfont*/, + XID /*fid*/); + +typedef struct _xQueryFontReply *xQueryFontReplyPtr; + +extern void QueryFont(FontPtr /*pFont*/, + xQueryFontReplyPtr /*pReply*/, + int /*nProtoCCIStructs*/); + +extern int ListFonts(ClientPtr /*client*/, + unsigned char * /*pattern*/, + unsigned int /*length*/, + unsigned int /*max_names*/); + +int +doListFontsWithInfo(ClientPtr /*client*/, + LFWIclosurePtr /*c*/); + +extern int doPolyText(ClientPtr /*client*/, + PTclosurePtr /*c*/ +); + +extern int PolyText(ClientPtr /*client*/, + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + unsigned char * /*pElt*/, + unsigned char * /*endReq*/, + int /*xorg*/, + int /*yorg*/, + int /*reqType*/, + XID /*did*/); + +extern int doImageText(ClientPtr /*client*/, + ITclosurePtr /*c*/); + +extern int ImageText(ClientPtr /*client*/, + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nChars*/, + unsigned char * /*data*/, + int /*xorg*/, + int /*yorg*/, + int /*reqType*/, + XID /*did*/); + +extern int SetFontPath(ClientPtr /*client*/, + int /*npaths*/, + unsigned char * /*paths*/, + int * /*error*/); + +extern int SetDefaultFontPath(char * /*path*/); + +extern unsigned char *GetFontPath(int * /*count*/, + int * /*length*/); + +extern int LoadGlyphs(ClientPtr /*client*/, + FontPtr /*pfont*/, + unsigned /*nchars*/, + int /*item_size*/, + unsigned char * /*data*/); + +extern void DeleteClientFontStuff(ClientPtr /*client*/); + +/* Quartz support on Mac OS X pulls in the QuickDraw + framework whose InitFonts function conflicts here. */ +#ifdef __DARWIN__ +#define InitFonts Darwin_X_InitFonts +#endif +extern void InitFonts(void); + +extern void FreeFonts(void); + +extern FontPtr find_old_font(XID /*id*/); + +extern void GetGlyphs(FontPtr /*font*/, + unsigned long /*count*/, + unsigned char * /*chars*/, + FontEncoding /*fontEncoding*/, + unsigned long * /*glyphcount*/, + CharInfoPtr * /*glyphs*/); + +extern void QueryGlyphExtents(FontPtr /*pFont*/, + CharInfoPtr * /*charinfo*/, + unsigned long /*count*/, + ExtentInfoPtr /*info*/); + +extern Bool QueryTextExtents(FontPtr /*pFont*/, + unsigned long /*count*/, + unsigned char * /*chars*/, + ExtentInfoPtr /*info*/); + +extern Bool ParseGlyphCachingMode(char * /*str*/); + +extern void InitGlyphCaching(void); + +extern void SetGlyphCachingMode(int /*newmode*/); + +#endif /* DIXFONT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfontstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfontstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixfontstr.h (revision 51223) @@ -0,0 +1,95 @@ +/* $Xorg: dixfontstr.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef DIXFONTSTRUCT_H +#define DIXFONTSTRUCT_H + +#include "servermd.h" +#include "dixfont.h" +#include +#include "closure.h" +#define NEED_REPLIES +#include /* for xQueryFontReply */ + +#define FONTCHARSET(font) (font) +#define FONTMAXBOUNDS(font,field) (font)->info.maxbounds.field +#define FONTMINBOUNDS(font,field) (font)->info.minbounds.field +#define TERMINALFONT(font) (font)->info.terminalFont +#define FONTASCENT(font) (font)->info.fontAscent +#define FONTDESCENT(font) (font)->info.fontDescent +#define FONTGLYPHS(font) 0 +#define FONTCONSTMETRICS(font) (font)->info.constantMetrics +#define FONTCONSTWIDTH(font) (font)->info.constantWidth +#define FONTALLEXIST(font) (font)->info.allExist +#define FONTFIRSTCOL(font) (font)->info.firstCol +#define FONTLASTCOL(font) (font)->info.lastCol +#define FONTFIRSTROW(font) (font)->info.firstRow +#define FONTLASTROW(font) (font)->info.lastRow +#define FONTDEFAULTCH(font) (font)->info.defaultCh +#define FONTINKMIN(font) (&((font)->info.ink_minbounds)) +#define FONTINKMAX(font) (&((font)->info.ink_maxbounds)) +#define FONTPROPS(font) (font)->info.props +#define FONTGLYPHBITS(base,pci) ((unsigned char *) (pci)->bits) +#define FONTINFONPROPS(font) (font)->info.nprops + +/* some things haven't changed names, but we'll be careful anyway */ + +#define FONTREFCNT(font) (font)->refcnt + +/* + * for linear char sets + */ +#define N1dChars(pfont) (FONTLASTCOL(pfont) - FONTFIRSTCOL(pfont) + 1) + +/* + * for 2D char sets + */ +#define N2dChars(pfont) (N1dChars(pfont) * \ + (FONTLASTROW(pfont) - FONTFIRSTROW(pfont) + 1)) + +#ifndef GLYPHPADBYTES +#define GLYPHPADBYTES -1 +#endif + +#if GLYPHPADBYTES == 0 || GLYPHPADBYTES == 1 +#define GLYPHWIDTHBYTESPADDED(pci) (GLYPHWIDTHBYTES(pci)) +#define PADGLYPHWIDTHBYTES(w) (((w)+7)>>3) +#endif + +#if GLYPHPADBYTES == 2 +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+1) & ~0x1) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+1) & ~0x1) +#endif + +#if GLYPHPADBYTES == 4 +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+3) & ~0x3) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+3) & ~0x3) +#endif + +#if GLYPHPADBYTES == 8 /* for a cray? */ +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+7) & ~0x7) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+7) & ~0x7) +#endif + +#endif /* DIXFONTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixgrabs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixgrabs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixgrabs.h (revision 51223) @@ -0,0 +1,59 @@ +/* $XFree86: xc/programs/Xserver/include/dixgrabs.h,v 3.0 1996/04/15 11:34:27 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef DIXGRABS_H +#define DIXGRABS_H 1 + +extern GrabPtr CreateGrab( + int /* client */, + DeviceIntPtr /* device */, + WindowPtr /* window */, + Mask /* eventMask */, + Bool /* ownerEvents */, + Bool /* keyboardMode */, + Bool /* pointerMode */, + DeviceIntPtr /* modDevice */, + unsigned short /* modifiers */, + int /* type */, + KeyCode /* keybut */, + WindowPtr /* confineTo */, + CursorPtr /* cursor */); + +extern int DeletePassiveGrab( + pointer /* value */, + XID /* id */); + +extern Bool GrabMatchesSecond( + GrabPtr /* pFirstGrab */, + GrabPtr /* pSecondGrab */); + +extern int AddPassiveGrabToList( + GrabPtr /* pGrab */); + +extern Bool DeletePassiveGrabFromList( + GrabPtr /* pMinuendGrab */); + +#endif /* DIXGRABS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dixstruct.h (revision 51223) @@ -0,0 +1,233 @@ +/* $XFree86: xc/programs/Xserver/include/dixstruct.h,v 3.19tsi Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: dixstruct.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ + +#ifndef DIXSTRUCT_H +#define DIXSTRUCT_H + +#include "dix.h" +#include "resource.h" +#include "cursor.h" +#include "gc.h" +#include "pixmap.h" +#include + +/* + * direct-mapped hash table, used by resource manager to store + * translation from client ids to server addresses. + */ + +#ifdef DEBUG +#define MAX_REQUEST_LOG 100 +#endif + +extern CallbackListPtr ClientStateCallback; + +typedef struct { + ClientPtr client; + xConnSetupPrefix *prefix; + xConnSetup *setup; +} NewClientInfoRec; + +typedef void (*ReplySwapPtr) ( + ClientPtr /* pClient */, + int /* size */, + void * /* pbuf */); + +extern void ReplyNotSwappd ( + ClientPtr /* pClient */, + int /* size */, + void * /* pbuf */); + +typedef enum {ClientStateInitial, + ClientStateAuthenticating, + ClientStateRunning, + ClientStateRetained, + ClientStateGone, + ClientStateCheckingSecurity, + ClientStateCheckedSecurity} ClientState; + +#ifdef XFIXES +typedef struct _saveSet { + struct _Window *windowPtr; + Bool toRoot; + Bool remap; +} SaveSetElt; +#define SaveSetWindow(ss) ((ss).windowPtr) +#define SaveSetToRoot(ss) ((ss).toRoot) +#define SaveSetRemap(ss) ((ss).remap) +#define SaveSetAssignWindow(ss,w) ((ss).windowPtr = (w)) +#define SaveSetAssignToRoot(ss,tr) ((ss).toRoot = (tr)) +#define SaveSetAssignRemap(ss,rm) ((ss).remap = (rm)) +#else +typedef struct _Window *SaveSetElt; +#define SaveSetWindow(ss) (ss) +#define SaveSetToRoot(ss) FALSE +#define SaveSetRemap(ss) TRUE +#define SaveSetAssignWindow(ss,w) ((ss) = (w)) +#define SaveSetAssignToRoot(ss,tr) +#define SaveSetAssignRemap(ss,rm) +#endif + +typedef struct _Client { + int index; + Mask clientAsMask; + pointer requestBuffer; + pointer osPrivate; /* for OS layer, including scheduler */ + Bool swapped; + ReplySwapPtr pSwapReplyFunc; + XID errorValue; + int sequence; + int closeDownMode; + int clientGone; + int noClientException; /* this client died or needs to be + * killed */ + DrawablePtr lastDrawable; + Drawable lastDrawableID; + GCPtr lastGC; + GContext lastGCID; + SaveSetElt *saveSet; + int numSaved; + pointer screenPrivate[MAXSCREENS]; + int (**requestVector) ( + ClientPtr /* pClient */); + CARD32 req_len; /* length of current request */ + Bool big_requests; /* supports large requests */ + int priority; + ClientState clientState; + DevUnion *devPrivates; +#ifdef XKB + unsigned short xkbClientFlags; + unsigned short mapNotifyMask; + unsigned short newKeyboardNotifyMask; + unsigned short vMajor,vMinor; + KeyCode minKC,maxKC; +#endif + +#ifdef DEBUG + unsigned char requestLog[MAX_REQUEST_LOG]; + int requestLogIndex; +#endif +#ifdef LBX + int (*readRequest)(ClientPtr /*client*/); +#endif + unsigned long replyBytesRemaining; +#ifdef XCSECURITY + XID authId; + unsigned int trustLevel; + pointer (* CheckAccess)( + ClientPtr /*pClient*/, + XID /*id*/, + RESTYPE /*classes*/, + Mask /*access_mode*/, + pointer /*resourceval*/); +#endif +#ifdef XAPPGROUP + struct _AppGroupRec* appgroup; +#endif + struct _FontResolution * (*fontResFunc) ( /* no need for font.h */ + ClientPtr /* pClient */, + int * /* num */); +#ifdef SMART_SCHEDULE + int smart_priority; + long smart_start_tick; + long smart_stop_tick; + long smart_check_tick; +#endif +} ClientRec; + +#ifdef SMART_SCHEDULE +/* + * Scheduling interface + */ +extern long SmartScheduleTime; +extern long SmartScheduleInterval; +extern long SmartScheduleSlice; +extern long SmartScheduleMaxSlice; +extern unsigned long SmartScheduleIdleCount; +extern Bool SmartScheduleDisable; +extern Bool SmartScheduleIdle; +extern Bool SmartScheduleTimerStopped; +extern Bool SmartScheduleStartTimer(void); +#define SMART_MAX_PRIORITY (20) +#define SMART_MIN_PRIORITY (-20) + +extern Bool SmartScheduleInit(void); + +#endif + +/* This prototype is used pervasively in Xext, dix */ +#define DISPATCH_PROC(func) int func(ClientPtr /* client */) + +typedef struct _WorkQueue { + struct _WorkQueue *next; + Bool (*function) ( + ClientPtr /* pClient */, + pointer /* closure */ +); + ClientPtr client; + pointer closure; +} WorkQueueRec; + +extern TimeStamp currentTime; +extern TimeStamp lastDeviceEventTime; + +extern int CompareTimeStamps( + TimeStamp /*a*/, + TimeStamp /*b*/); + +extern TimeStamp ClientTimeToServerTime(CARD32 /*c*/); + +typedef struct _CallbackRec { + CallbackProcPtr proc; + pointer data; + Bool deleted; + struct _CallbackRec *next; +} CallbackRec, *CallbackPtr; + +typedef struct _CallbackList { + CallbackFuncsRec funcs; + int inCallback; + Bool deleted; + int numDeleted; + CallbackPtr list; +} CallbackListRec; + +/* proc vectors */ + +extern int (* InitialVector[3]) (ClientPtr /*client*/); + +extern int (* ProcVector[256]) (ClientPtr /*client*/); + +extern int (* SwappedProcVector[256]) (ClientPtr /*client*/); + +#ifdef K5AUTH +extern int (*k5_Vector[256])(ClientPtr /*client*/); +#endif + +extern ReplySwapPtr ReplySwapVector[256]; + +extern int ProcBadRequest(ClientPtr /*client*/); + +#endif /* DIXSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dlloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dlloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dlloader.h (revision 51223) @@ -0,0 +1,36 @@ +/* + * Copyright 1997 Metro Link, Inc. + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/dlloader.h,v 1.2 1998/07/25 16:56:14 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _DLLOADER_H +#define _DLLOADER_H +extern void *DLLoadModule(loaderPtr, int, LOOKUP **); +extern void DLResolveSymbols(void *); +extern int DLCheckForUnresolved(void *); +extern void DLUnloadModule(void *); +extern void *DLFindSymbol(const char *name); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx-config.h (revision 51223) @@ -0,0 +1,98 @@ +/* + * Copyright 2005 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Provide configuration #define's and #undef's to build Xdmx in X.Org's + * modular source tree. + */ + +#ifndef DMX_CONFIG_H +#define DMX_CONFIG_H + +#include + +/* + * Note 1: This is a signed int that is printed as a decimal number. + * Since we want to make it human-interpretable, the fields are + * defined as: + * 2147483648 + * AAbbyymmdd + * AA: major version 01-20 + * bb: minor version 00-99 + * yy: year 00-99 [See Note 2] + * mm: month 01-12 + * dd: day 01-31 + * + * Note 2: The default epoch for the year is 2000. + * To change the default epoch, change the DMX_VENDOR_RELEASE + * macro below, bumb the minor version number, and change + * xdpyinfo to key off the major/minor version to determine the + * new epoch. Remember to do this on January 1, 2100 and every + * 100 years thereafter. + */ +#define DMX_VENDOR_RELEASE(major,minor,year,month,day) \ + ((major) * 100000000) + \ + ((minor) * 1000000) + \ + ((year-2000) * 10000) + \ + ((month) * 100) + \ + ((day) * 1) +#define VENDOR_RELEASE DMX_VENDOR_RELEASE(1,2,2004,6,30) +#define VENDOR_STRING "DMX Project" + +/* Enable the DMX extension */ +#define DMXEXT + +/* Disable the extensions that are not currently supported */ +#undef BEZIER +#undef PEXEXT +#undef MULTIBUFFER +#undef XV +#undef XIE +#undef DBE +#undef XF86VIDMODE +#undef XF86MISC +#undef XFreeXDGA +#undef XF86DRI +#undef MITSHM +#undef TOGCUP +#undef DPSEXT +#undef MITMISC +#undef SCREENSAVER +#undef RANDR +#undef XFIXES +#undef DAMAGE +#undef COMPOSITE +#undef FONTCACHE +#undef XFree86LOADER + +#endif /* DMX_CONFIG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx.h (revision 51223) @@ -0,0 +1,374 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Main header file included by all other DMX-related files. + */ + +/** \mainpage + * - DMX Home Page + * - DMX Project Page (on + * Source Forge) + * - Distributed Multihead + * X design, the design document for DMX + * - Client-to-Server + * DMX Extension to the X Protocol + */ + +#ifndef DMX_H +#define DMX_H + +#include "gcstruct.h" + +/* Handle client-side include files in one place. */ +#include "dmxclient.h" + +#include "globals.h" +#include "scrnintstr.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +#ifdef GLXEXT +#include +#include +#endif + +typedef enum { + PosNone = -1, + PosAbsolute = 0, + PosRightOf, + PosLeftOf, + PosAbove, + PosBelow, + PosRelative +} PositionType; + +/** Provide the typedef globally, but keep the contents opaque outside + * of the input routines. \see dmxinput.h */ +typedef struct _DMXInputInfo DMXInputInfo; + +/** Provide the typedef globally, but keep the contents opaque outside + * of the XSync statistic routines. \see dmxstat.c */ +typedef struct _DMXStatInfo DMXStatInfo; + +/** Global structure containing information about each backend screen. */ +typedef struct _DMXScreenInfo { + const char *name; /**< Name from command line or config file */ + int index; /**< Index into dmxScreens global */ + + /*---------- Back-end X server information ----------*/ + + Display *beDisplay; /**< Back-end X server's display */ + int beWidth; /**< Width of BE display */ + int beHeight; /**< Height of BE display */ + int beDepth; /**< Depth of BE display */ + int beBPP; /**< Bits per pixel of BE display */ + int beXDPI; /**< Horizontal dots per inch of BE */ + int beYDPI; /**< Vertical dots per inch of BE */ + + int beNumDepths; /**< Number of depths on BE server */ + int *beDepths; /**< Depths from BE server */ + + int beNumPixmapFormats; /**< Number of pixmap formats on BE */ + XPixmapFormatValues *bePixmapFormats; /**< Pixmap formats on BE */ + + int beNumVisuals; /**< Number of visuals on BE */ + XVisualInfo *beVisuals; /**< Visuals from BE server */ + int beDefVisualIndex; /**< Default visual index of BE */ + + int beNumDefColormaps; /**< Number of default colormaps */ + Colormap *beDefColormaps; /**< Default colormaps for DMX server */ + + Pixel beBlackPixel; /**< Default black pixel for BE */ + Pixel beWhitePixel; /**< Default white pixel for BE */ + + /*---------- Screen window information ----------*/ + + Window scrnWin; /**< "Screen" window on backend display */ + int scrnX; /**< X offset of "screen" WRT BE display */ + int scrnY; /**< Y offset of "screen" WRT BE display */ + int scrnWidth; /**< Width of "screen" */ + int scrnHeight; /**< Height of "screen" */ + int scrnXSign; /**< X offset sign of "screen" */ + int scrnYSign; /**< Y offset sign of "screen" */ + + /** Default drawables for "screen" */ + Drawable scrnDefDrawables[MAXFORMATS]; + + struct _DMXScreenInfo *next; /**< List of "screens" on same display */ + struct _DMXScreenInfo *over; /**< List of "screens" that overlap */ + + /*---------- Root window information ----------*/ + + Window rootWin; /**< "Root" window on backend display */ + int rootX; /**< X offset of "root" window WRT "screen"*/ + int rootY; /**< Y offset of "root" window WRT "screen"*/ + int rootWidth; /**< Width of "root" window */ + int rootHeight; /**< Height of "root" window */ + + int rootXOrigin; /**< Global X origin of "root" window */ + int rootYOrigin; /**< Global Y origin of "root" window */ + + /*---------- Shadow framebuffer information ----------*/ + + void *shadow; /**< Shadow framebuffer data (if enabled) */ + XlibGC shadowGC; /**< Default GC used by shadow FB code */ + XImage *shadowFBImage; /**< Screen image used by shadow FB code */ + + /*---------- Other related information ----------*/ + + int shared; /**< Non-zero if another Xdmx is running */ + + Bool WMRunningOnBE; + + Cursor noCursor; + Cursor curCursor; + /* Support for cursors on overlapped + * backend displays. */ + CursorPtr cursor; + int cursorVisible; + int cursorNotShared; /* for overlapping screens on a backend */ + + PositionType where; /**< Relative layout information */ + int whereX; /**< Relative layout information */ + int whereY; /**< Relative layout information */ + int whereRefScreen; /**< Relative layout information */ + + int savedTimeout; /**< Original screen saver timeout */ + int dpmsCapable; /**< Non-zero if backend is DPMS capable */ + int dpmsEnabled; /**< Non-zero if DPMS enabled */ + int dpmsStandby; /**< Original DPMS standby value */ + int dpmsSuspend; /**< Original DPMS suspend value */ + int dpmsOff; /**< Original DPMS off value */ + + DMXStatInfo *stat; /**< Statistics about XSync */ + Bool needsSync; /**< True if an XSync is pending */ + +#ifdef GLXEXT + /** Visual information for glxProxy */ + int numGlxVisuals; + __GLXvisualConfig *glxVisuals; + int glxMajorOpcode; + int glxErrorBase; + + /** FB config information for glxProxy */ + __GLXFBConfig *fbconfigs; + int numFBConfigs; +#endif + + /** Function pointers to wrapped screen + * functions */ + CloseScreenProcPtr CloseScreen; + SaveScreenProcPtr SaveScreen; + + CreateGCProcPtr CreateGC; + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + RestackWindowProcPtr RestackWindow; + WindowExposuresProcPtr WindowExposures; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + + ResizeWindowProcPtr ResizeWindow; + ReparentWindowProcPtr ReparentWindow; + + ChangeBorderWidthProcPtr ChangeBorderWidth; + + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + BitmapToRegionProcPtr BitmapToRegion; + + RealizeFontProcPtr RealizeFont; + UnrealizeFontProcPtr UnrealizeFont; + + CreateColormapProcPtr CreateColormap; + DestroyColormapProcPtr DestroyColormap; + InstallColormapProcPtr InstallColormap; + StoreColorsProcPtr StoreColors; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif + +#ifdef RENDER + CreatePictureProcPtr CreatePicture; + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + InitIndexedProcPtr InitIndexed; + CloseIndexedProcPtr CloseIndexed; + UpdateIndexedProcPtr UpdateIndexed; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; +#endif +} DMXScreenInfo; + +/* Global variables available to all Xserver/hw/dmx routines. */ +extern int dmxNumScreens; /**< Number of dmxScreens */ +extern DMXScreenInfo *dmxScreens; /**< List of outputs */ +extern int dmxShadowFB; /**< Non-zero if using + * shadow frame-buffer + * (deprecated) */ +extern XErrorEvent dmxLastErrorEvent; /**< Last error that + * occurred */ +extern Bool dmxErrorOccurred; /**< True if an error + * occurred */ +extern Bool dmxOffScreenOpt; /**< True if using off + * screen + * optimizations */ +extern Bool dmxSubdividePrimitives; /**< True if using the + * primitive subdivision + * optimization */ +extern Bool dmxLazyWindowCreation; /**< True if using the + * lazy window creation + * optimization */ +extern Bool dmxUseXKB; /**< True if the XKB + * extension should be + * used with the backend + * servers */ +extern int dmxDepth; /**< Requested depth if + * non-zero */ +#ifdef GLXEXT +extern Bool dmxGLXProxy; /**< True if glxProxy + * support is enabled */ +extern Bool dmxGLXSwapGroupSupport; /**< True if glxProxy + * support for swap + * groups and barriers + * is enabled */ +extern Bool dmxGLXSyncSwap; /**< True if glxProxy + * should force an XSync + * request after each + * swap buffers call */ +extern Bool dmxGLXFinishSwap; /**< True if glxProxy + * should force a + * glFinish request + * after each swap + * buffers call */ +#endif +extern char *dmxFontPath; /**< NULL if no font + * path is set on the + * command line; + * otherwise, a string + * of comma separated + * paths built from the + * command line + * specified font + * paths */ +extern Bool dmxIgnoreBadFontPaths; /**< True if bad font + * paths should be + * ignored during server + * init */ +extern Bool dmxAddRemoveScreens; /**< True if add and + * remove screens support + * is enabled */ + +/** Wrap screen or GC function pointer */ +#define DMX_WRAP(_entry, _newfunc, _saved, _actual) \ +do { \ + (_saved)->_entry = (_actual)->_entry; \ + (_actual)->_entry = (_newfunc); \ +} while (0) + +/** Unwrap screen or GC function pointer */ +#define DMX_UNWRAP(_entry, _saved, _actual) \ +do { \ + (_actual)->_entry = (_saved)->_entry; \ +} while (0) + +/* Define the MAXSCREENSALLOC/FREE macros, when MAXSCREENS patch has not + * been applied to sources. */ +#ifdef MAXSCREENS +#define MAXSCREEN_MAKECONSTSTR1(x) #x +#define MAXSCREEN_MAKECONSTSTR2(x) MAXSCREEN_MAKECONSTSTR1(x) + +#define MAXSCREEN_FAILED_TXT "Failed at [" \ + MAXSCREEN_MAKECONSTSTR2(__LINE__) ":" __FILE__ "] to allocate object: " + +#define _MAXSCREENSALLOCF(o,size,fatal) \ + do { \ + if (!o) { \ + o = xalloc((size) * sizeof(*(o))); \ + if (o) memset(o, 0, (size) * sizeof(*(o))); \ + if (!o && fatal) FatalError(MAXSCREEN_FAILED_TXT #o); \ + } \ + } while (0) +#define _MAXSCREENSALLOCR(o,size,retval) \ + do { \ + if (!o) { \ + o = xalloc((size) * sizeof(*(o))); \ + if (o) memset(o, 0, (size) * sizeof(*(o))); \ + if (!o) return retval; \ + } \ + } while (0) + +#define MAXSCREENSFREE(o) \ + do { \ + if (o) xfree(o); \ + o = NULL; \ + } while (0) + +#define MAXSCREENSALLOC(o) _MAXSCREENSALLOCF(o,MAXSCREENS, 0) +#define MAXSCREENSALLOC_FATAL(o) _MAXSCREENSALLOCF(o,MAXSCREENS, 1) +#define MAXSCREENSALLOC_RETURN(o,r) _MAXSCREENSALLOCR(o,MAXSCREENS, (r)) +#define MAXSCREENSALLOCPLUSONE(o) _MAXSCREENSALLOCF(o,MAXSCREENS+1,0) +#define MAXSCREENSALLOCPLUSONE_FATAL(o) _MAXSCREENSALLOCF(o,MAXSCREENS+1,1) +#define MAXSCREENSCALLOC(o,m) _MAXSCREENSALLOCF(o,MAXSCREENS*(m),0) +#define MAXSCREENSCALLOC_FATAL(o,m) _MAXSCREENSALLOCF(o,MAXSCREENS*(m),1) +#endif + +#endif /* DMX_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx_glxvisuals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx_glxvisuals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmx_glxvisuals.h (revision 51223) @@ -0,0 +1,64 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLXVISUALS_H +#define _GLXVISUALS_H + +#include + +/** GLX Visual private area. */ +typedef struct { + int x_visual_depth; + int x_visual_class; +} dmxGlxVisualPrivate; + +__GLXvisualConfig *GetGLXVisualConfigs(Display *dpy, + int screen, + int *nconfigs); + +__GLXFBConfig *GetGLXFBConfigs(Display *dpy, + int glxMajorOpcode, + int *nconfigs); + +__GLXvisualConfig *GetGLXVisualConfigsFromFBConfigs(__GLXFBConfig *fbconfigs, + int nfbconfigs, + XVisualInfo *visuals, + int nvisuals, + __GLXvisualConfig + *glxConfigs, + int nGlxConfigs, + int *nconfigs); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxarg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxarg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxarg.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to argument handling functions. \see dmxarg.c */ + +#ifndef _DMXARG_H_ +#define _DMXARG_H_ + +typedef struct _dmxArg *dmxArg; + +extern dmxArg dmxArgCreate(void); +extern void dmxArgFree(dmxArg a); +extern void dmxArgAdd(dmxArg a, const char *string); +extern const char *dmxArgV(dmxArg a, int item); +extern int dmxArgC(dmxArg a); +extern dmxArg dmxArgParse(const char *string); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxbackend.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxbackend.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxbackend.h (revision 51223) @@ -0,0 +1,57 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to backend input device support. \see dmxbackend.c \see + * dmxcommon.c */ + +#ifndef _DMXBACKEND_H_ +#define _DMXBACKEND_H_ + +extern pointer dmxBackendCreatePrivate(DeviceIntPtr pDevice); +extern void dmxBackendDestroyPrivate(pointer private); +extern void dmxBackendInit(DevicePtr pDev); +extern void dmxBackendLateReInit(DevicePtr pDev); +extern void dmxBackendMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxBackendKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxBackendCollectEvents(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void dmxBackendProcessInput(pointer private); +extern int dmxBackendFunctions(pointer private, DMXFunctionType function); +extern void dmxBackendUpdatePosition(pointer private, int x, int y); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcb.h (revision 51223) @@ -0,0 +1,54 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Header file for connection block functions. \see dmxcb.c. + */ + +#ifndef _DMXCB_H_ +#define _DMXCB_H_ +/** The cursor position, in global coordinates. */ +extern int dmxGlobalWidth, dmxGlobalHeight; + +/** #dmxComputeWidthHeight can either recompute the global bounding box + * or not. */ +typedef enum { + DMX_RECOMPUTE_BOUNDING_BOX, + DMX_NO_RECOMPUTE_BOUNDING_BOX +} DMXRecomputeFlag; + +extern void dmxSetWidthHeight(int width, int height); +extern void dmxComputeWidthHeight(DMXRecomputeFlag flag); +extern void dmxConnectionBlockCallback(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxclient.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxclient.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxclient.h (revision 51223) @@ -0,0 +1,152 @@ +/* $XFree86$ */ +/* + * Copyright (c) 1995 X Consortium + * Copyright 2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT, THE X CONSORTIUM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the X Consortium + * shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written + * authorization from the X Consortium. + */ + +/* + * Derived from hw/xnest/Xnest.h by Rickard E. (Rik) Faith + */ + +/** \file + * This file includes all client-side include files with proper wrapping. + */ + +#ifndef _DMXCLIENT_H_ +#define _DMXCLIENT_H_ + +#define GC XlibGC + +#ifdef _XSERVER64 +#define DMX64 +#undef _XSERVER64 +typedef unsigned long XID64; +typedef unsigned long Mask64; +typedef unsigned long Atom64; +typedef unsigned long VisualID64; +typedef unsigned long Time64; +#define XID XID64 +#define Mask Mask64 +#define Atom Atom64 +#define VisualID VisualID64 +#define Time Time64 +typedef XID Window64; +typedef XID Drawable64; +typedef XID Font64; +typedef XID Pixmap64; +typedef XID Cursor64; +typedef XID Colormap64; +typedef XID GContext64; +typedef XID KeySym64; +#define Window Window64 +#define Drawable Drawable64 +#define Font Font64 +#define Pixmap Pixmap64 +#define Cursor Cursor64 +#define Colormap Colormap64 +#define GContext GContext64 +#define KeySym KeySym64 +#endif + +#include +#include /* For _XExtension */ +#include /* from glxserver.h */ +#include /* from glxserver.h */ +#include +#include +#include +#include +#include /* For XmuSnprintf */ + +#ifdef SHAPE +#include +#endif + +#ifdef RENDER +#include +#undef PictFormatType +#endif + +#ifdef XKB +#include +#include +#endif + +#ifdef XINPUT +#include +#endif + +/* Always include these, since we query them even if we don't export XINPUT. */ +#include /* For XDevice */ +#include + +#undef GC + +#ifdef DMX64 +#define _XSERVER64 +#undef XID +#undef Mask +#undef Atom +#undef VisualID +#undef Time +#undef Window +#undef Drawable +#undef Font +#undef Pixmap +#undef Cursor +#undef Colormap +#undef GContext +#undef KeySym +#endif + +/* These are in exglobals.h, but that conflicts with X11/extensions/XKBsrv.h */ +extern int ProximityIn; +extern int ProximityOut; +extern int DeviceValuator; +extern int DeviceMotionNotify; +extern int DeviceFocusIn; +extern int DeviceFocusOut; +extern int DeviceStateNotify; +extern int DeviceMappingNotify; +extern int ChangeDeviceNotify; + +/* Some protocol gets included last, after undefines. */ +#include +#ifdef XKB +#include +#ifndef XKB_IN_SERVER +#define XKB_IN_SERVER +#endif +#include +#undef XPointer +#endif +#include + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcmap.h (revision 51223) @@ -0,0 +1,71 @@ +/* $XFree86$ */ +/* + * Copyright 2002-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Header file for colormap support. \see dmxcmap.c. */ + +#ifndef DMXCMAP_H +#define DMXCMAP_H + +#include "colormapst.h" + +/** Colormap private area. */ +typedef struct _dmxColormapPriv { + Colormap cmap; +} dmxColormapPrivRec, *dmxColormapPrivPtr; + + +extern Bool dmxCreateColormap(ColormapPtr pColormap); +extern void dmxDestroyColormap(ColormapPtr pColormap); +extern void dmxInstallColormap(ColormapPtr pColormap); +extern void dmxStoreColors(ColormapPtr pColormap, int ndef, xColorItem *pdef); + +extern Bool dmxCreateDefColormap(ScreenPtr pScreen); + +extern Bool dmxBECreateColormap(ColormapPtr pColormap); +extern Bool dmxBEFreeColormap(ColormapPtr pColormap); + +/** Private index. \see dmxcmap.c \see dmxscrinit.c \see dmxwindow.c */ +extern int dmxColormapPrivateIndex; + +/** Set colormap private structure. */ +#define DMX_SET_COLORMAP_PRIV(_pCMap, _pCMapPriv) \ + (_pCMap)->devPrivates[dmxColormapPrivateIndex].ptr \ + = (pointer)(_pCMapPriv); + +/** Get colormap private structure. */ +#define DMX_GET_COLORMAP_PRIV(_pCMap) \ + (dmxColormapPrivPtr)(_pCMap)->devPrivates[dmxColormapPrivateIndex].ptr + +#endif /* DMXCMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcommon.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86$ */ +/* + * Copyright 2002,2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to functions used by backend and console input devices. + * \see dmxcommon.c \see dmxbackend.c \see dmxconsole.c */ + +#ifndef _DMXCOMMON_H_ +#define _DMXCOMMON_H_ + +#define DMX_COMMON_OTHER \ + Display *display; \ + Window window; \ + DMXScreenInfo *be; \ + DMXLocalInputInfoPtr dmxLocal; \ + int initPointerX; \ + int initPointerY; \ + long eventMask; \ + KeybdCtrl kctrl; \ + PtrCtrl mctrl; \ + int kctrlset; \ + int mctrlset; \ + KeybdCtrl savedKctrl; \ + XModifierKeymap *savedModMap; \ + int stateSaved + +#ifdef XKB +#define DMX_COMMON_XKB \ + DMX_COMMON_OTHER; \ + XkbDescPtr xkb; \ + XkbIndicatorRec savedIndicators +#else +#define DMX_COMMON_XKB DMX_COMMON_OTHER +#endif + +#ifdef XINPUT +#define DMX_COMMON_PRIVATE \ + DMX_COMMON_XKB; \ + XDevice *xi +#else +#define DMX_COMMON_PRIVATE DMX_COMMON_OTHER +#endif + +#define GETONLYPRIVFROMPRIVATE \ + myPrivate *priv = private + +#define GETPRIVFROMPRIVATE \ + GETONLYPRIVFROMPRIVATE; \ + DMXInputInfo *dmxInput = &dmxInputs[priv->dmxLocal->inputIdx] + +#define GETDMXLOCALFROMPDEVICE \ + DevicePtr pDev = &pDevice->public; \ + DMXLocalInputInfoPtr dmxLocal = pDev->devicePrivate + +#define GETDMXINPUTFROMPRIV \ + DMXInputInfo *dmxInput = &dmxInputs[priv->dmxLocal->inputIdx] + +#define GETDMXINPUTFROMPDEVICE \ + GETDMXLOCALFROMPDEVICE; \ + DMXInputInfo *dmxInput = &dmxInputs[dmxLocal->inputIdx] + +#define GETDMXLOCALFROMPDEV \ + DMXLocalInputInfoPtr dmxLocal = pDev->devicePrivate + +#define GETDMXINPUTFROMPDEV \ + GETDMXLOCALFROMPDEV; \ + DMXInputInfo *dmxInput = &dmxInputs[dmxLocal->inputIdx] + +#define GETPRIVFROMPDEV \ + GETDMXLOCALFROMPDEV; \ + myPrivate *priv = dmxLocal->private + +#define DMX_KEYBOARD_EVENT_MASK \ + (KeyPressMask | KeyReleaseMask | KeymapStateMask) + +#define DMX_POINTER_EVENT_MASK \ + (ButtonPressMask | ButtonReleaseMask | PointerMotionMask) + +extern void dmxCommonKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxCommonKbdGetMap(DevicePtr pDev, + KeySymsPtr pKeySyms, CARD8 *pModMap); +extern void dmxCommonKbdCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +extern void dmxCommonKbdBell(DevicePtr pDev, int percent, + int volume, int pitch, int duration); +extern int dmxCommonKbdOn(DevicePtr pDev); +extern void dmxCommonKbdOff(DevicePtr pDev); +extern void dmxCommonMouGetMap(DevicePtr pDev, + unsigned char *map, int *nButtons); +extern void dmxCommonMouCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern int dmxCommonMouOn(DevicePtr pDev); +extern void dmxCommonMouOff(DevicePtr pDev); +extern int dmxFindPointerScreen(int x, int y); + +extern int dmxCommonOthOn(DevicePtr pDev); +extern void dmxCommonOthOff(DevicePtr pDev); +extern void dmxCommonOthGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); + + /* helper functions */ +extern pointer dmxCommonCopyPrivate(DeviceIntPtr pDevice); +extern void dmxCommonSaveState(pointer private); +extern void dmxCommonRestoreState(pointer private); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcompat.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcompat.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcompat.h (revision 51223) @@ -0,0 +1,45 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to VDL compatibility support. \see dmxcompat.c + * + * This file is not used by the DMX server. + */ + +#ifndef _DMXCOMPAT_H_ +#define _DMXCOMPAT_H_ + +extern DMXConfigEntryPtr dmxVDLRead(const char *filename); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconfig.h (revision 51223) @@ -0,0 +1,65 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for DMX configuration file support. \see dmxconfig.c */ + +#ifndef _DMXCONFIG_H_ +#define _DMXCONFIG_H_ +#define DMX_DEFAULT_XKB_RULES "xfree86" +#define DMX_DEFAULT_XKB_MODEL "pc101" +#define DMX_DEFAULT_XKB_LAYOUT "us" +#define DMX_DEFAULT_XKB_VARIANT NULL +#define DMX_DEFAULT_XKB_OPTIONS NULL + +extern void dmxConfigStoreDisplay(const char *display); +extern void dmxConfigStoreInput(const char *input); /* Core devices */ +extern void dmxConfigStoreXInput(const char *input); /* Non-core devices */ +extern void dmxConfigStoreFile(const char *file); +extern void dmxConfigStoreConfig(const char *config); +extern void dmxConfigConfigure(void); +extern void dmxConfigSetMaxScreens(void); + +extern void dmxConfigSetXkbRules(const char *rules); +extern void dmxConfigSetXkbModel(const char *model); +extern void dmxConfigSetXkbLayout(const char *layout); +extern void dmxConfigSetXkbVariant(const char *variant); +extern void dmxConfigSetXkbOptions(const char *options); + +extern char *dmxConfigGetXkbRules(void); +extern char *dmxConfigGetXkbModel(void); +extern char *dmxConfigGetXkbLayout(void); +extern char *dmxConfigGetXkbVariant(void); +extern char *dmxConfigGetXkbOptions(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconsole.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconsole.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxconsole.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for console device support. \see dmxconsole.c \see dmxcommon.c */ + +#ifndef _DMXCONSOLE_H_ +#define _DMXCONSOLE_H_ + +extern pointer dmxConsoleCreatePrivate(DeviceIntPtr pDevice); +extern void dmxConsoleDestroyPrivate(pointer private); +extern void dmxConsoleInit(DevicePtr pDev); +extern void dmxConsoleReInit(DevicePtr pDev); +extern void dmxConsoleMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxConsoleKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxConsoleCollectEvents(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern int dmxConsoleFunctions(pointer private, DMXFunctionType function); +extern void dmxConsoleUpdatePosition(pointer private, int x, int y); +extern void dmxConsoleKbdSetCtrl(pointer private, KeybdCtrl *ctrl); +extern void dmxConsoleCapture(DMXInputInfo *dmxInput); +extern void dmxConsoleUncapture(DMXInputInfo *dmxInput); +extern void dmxConsoleUpdateInfo(pointer private, + DMXUpdateType, WindowPtr pWindow); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxcursor.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * David H. Dawes + * Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for cursor support. \see dmxcursor.c. */ + +#ifndef DMXCURSOR_H +#define DMXCURSOR_H + +#include "mipointer.h" + +/** Cursor private area. */ +typedef struct _dmxCursorPriv { + Cursor cursor; +} dmxCursorPrivRec, *dmxCursorPrivPtr; + +/** Cursor functions for mi layer. \see dmxcursor.c \see dmxscrinit.c */ +extern miPointerScreenFuncRec dmxPointerCursorFuncs; +/** Sprite functions for mi layer. \see dmxcursor.c \see dmxscrinit.c */ +extern miPointerSpriteFuncRec dmxPointerSpriteFuncs; + +extern void dmxReInitOrigins(void); +extern void dmxInitOrigins(void); +extern void dmxInitOverlap(void); +extern void dmxCursorNoMulti(void); +extern void dmxMoveCursor(ScreenPtr pScreen, int x, int y); +extern void dmxCheckCursor(void); +extern int dmxOnScreen(int x, int y, DMXScreenInfo *dmxScreen); +extern void dmxHideCursor(DMXScreenInfo *dmxScreen); + +extern void dmxBECreateCursor(ScreenPtr pScreen, CursorPtr pCursor); +extern Bool dmxBEFreeCursor(ScreenPtr pScreen, CursorPtr pCursor); + +#define DMX_GET_CURSOR_PRIV(_pCursor, _pScreen) \ + (dmxCursorPrivPtr)(_pCursor)->devPriv[(_pScreen)->myNum] + +#endif /* DMXCURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdpms.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdpms.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdpms.h (revision 51223) @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Author: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for DPMS extension support. \see dmxdpms.c */ + +#ifndef _DMXDPMS_H_ +#define _DMXDPMS_H_ +extern void dmxDPMSInit(DMXScreenInfo *dmxScreen); +extern void dmxDPMSTerm(DMXScreenInfo *dmxScreen); +extern void dmxDPMSWakeup(void); /* Call when input is processed */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdummy.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdummy.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxdummy.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to dummy input device support. \see dmxdummy.c */ + +#ifndef _DMXDUMMY_H_ +#define _DMXDUMMY_H_ + +extern void dmxDummyMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxDummyKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxeq.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxeq.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxeq.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to the event queue support. Some of these functions are + * included in dmxinput.h, since they are used by top-level .c + * files. \see dmxeq.c \see dmxinput.h */ + +#ifndef _DMXEQ_H_ +#define _DMXEQ_H_ +extern Bool dmxeqInit(DevicePtr pKbd, DevicePtr pPtr); +extern void dmxeqProcessInputEvents(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxevents.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to event processing functions. \see dmxevents.h */ + +#ifndef _DMXEVENTS_H_ +#define _DMXEVENTS_H_ + +extern void dmxMotion(DevicePtr pDev, int *v, int firstAxis, int axesCount, + DMXMotionType type, DMXBlockType block); +extern void dmxEnqueue(DevicePtr pDev, int type, int detail, KeySym keySym, + XEvent *e, DMXBlockType block); +extern int dmxCheckSpecialKeys(DevicePtr pDev, KeySym keySym); +extern void dmxInvalidateGlobalPosition(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxextension.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxextension.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxextension.h (revision 51223) @@ -0,0 +1,119 @@ +/* $XFree86$ */ +/* + * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Author: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * + */ + +/** \file + * Interface for DMX extension support. These routines are called by + * function in Xserver/Xext/dmx.c. \see dmxextension.c */ + +#ifndef _DMXEXTENSION_H_ +#define _DMXEXTENSION_H_ + +/** Screen attributes. Used by #ProcDMXGetScreenAttributes and + * #ProcDMXChangeScreenAttributes. */ +typedef struct { + const char *displayName; + int logicalScreen; + + unsigned int screenWindowWidth; /* displayName's coordinate system */ + unsigned int screenWindowHeight; /* displayName's coordinate system */ + int screenWindowXoffset; /* displayName's coordinate system */ + int screenWindowYoffset; /* displayName's coordinate system */ + + unsigned int rootWindowWidth; /* screenWindow's coordinate system */ + unsigned int rootWindowHeight; /* screenWindow's coordinate system */ + int rootWindowXoffset; /* screenWindow's coordinate system */ + int rootWindowYoffset; /* screenWindow's coordinate system */ + + int rootWindowXorigin; /* global coordinate system */ + int rootWindowYorigin; /* global coordinate system */ +} DMXScreenAttributesRec, *DMXScreenAttributesPtr; + +/** Window attributes. Used by #ProcDMXGetWidowAttributes. */ +typedef struct { + int screen; + Window window; + xRectangle pos; + xRectangle vis; +} DMXWindowAttributesRec, *DMXWindowAttributesPtr; + +/** Desktop attributes. Used by #ProcDMXGetDesktopAttributes and + * #ProcDMXChangeDesktopAttributes. */ +typedef struct { + int width; + int height; + int shiftX; + int shiftY; +} DMXDesktopAttributesRec, *DMXDesktopAttributesPtr; + +/** Input attributes. Used by #ProcDMXGetInputAttributes. */ +typedef struct { + const char *name; + int inputType; + int physicalScreen; + int physicalId; + int isCore; + int sendsCore; + int detached; +} DMXInputAttributesRec, *DMXInputAttributesPtr; + + +extern unsigned long dmxGetNumScreens(void); +extern void dmxForceWindowCreation(WindowPtr pWindow); +extern void dmxFlushPendingSyncs(void); +extern Bool dmxGetScreenAttributes(int physical, + DMXScreenAttributesPtr attr); +extern Bool dmxGetWindowAttributes(WindowPtr pWindow, + DMXWindowAttributesPtr attr); +extern void dmxGetDesktopAttributes(DMXDesktopAttributesPtr attr); +extern int dmxGetInputCount(void); +extern int dmxGetInputAttributes(int deviceId, + DMXInputAttributesPtr attr); +extern int dmxAddInput(DMXInputAttributesPtr attr, int *deviceId); +extern int dmxRemoveInput(int deviceId); + +extern int dmxConfigureScreenWindows(int nscreens, + CARD32 *screens, + DMXScreenAttributesPtr attribs, + int *errorScreen); + +extern int dmxConfigureDesktop(DMXDesktopAttributesPtr attribs); + +/* dmxUpdateScreenResources exposed for dmxCreateWindow in dmxwindow.c */ +extern void dmxUpdateScreenResources(ScreenPtr pScreen, + int x, int y, int w, int h); + +extern int dmxAttachScreen(int idx, DMXScreenAttributesPtr attr); +extern int dmxDetachScreen(int idx); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxfont.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxfont.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxfont.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for font-related functions. \see dmxfont.c */ + +#ifndef DMXFONT_H +#define DMXFONT_H + +#include + +/** Font private area. */ +typedef struct _dmxFontPriv { + int refcnt; + XFontStruct **font; +} dmxFontPrivRec, *dmxFontPrivPtr; + +extern void dmxInitFonts(void); +extern void dmxResetFonts(void); + +extern Bool dmxRealizeFont(ScreenPtr pScreen, FontPtr pFont); +extern Bool dmxUnrealizeFont(ScreenPtr pScreen, FontPtr pFont); + +extern Bool dmxBELoadFont(ScreenPtr pScreen, FontPtr pFont); +extern Bool dmxBEFreeFont(ScreenPtr pScreen, FontPtr pFont); + +extern int dmxFontPrivateIndex; + +#endif /* DMXFONT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgc.h (revision 51223) @@ -0,0 +1,90 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for GC support. \see dmxgc.c */ + +#ifndef DMXGC_H +#define DMXGC_H + +#include "gcstruct.h" + +/** GC private area. */ +typedef struct _dmxGCPriv { + GCOps *ops; + GCFuncs *funcs; + XlibGC gc; + Bool msc; +} dmxGCPrivRec, *dmxGCPrivPtr; + + +extern Bool dmxInitGC(ScreenPtr pScreen); + +extern Bool dmxCreateGC(GCPtr pGC); +extern void dmxValidateGC(GCPtr pGC, unsigned long changes, + DrawablePtr pDrawable); +extern void dmxChangeGC(GCPtr pGC, unsigned long mask); +extern void dmxCopyGC(GCPtr pGCSrc, unsigned long changes, GCPtr pGCDst); +extern void dmxDestroyGC(GCPtr pGC); +extern void dmxChangeClip(GCPtr pGC, int type, pointer pvalue, int nrects); +extern void dmxDestroyClip(GCPtr pGC); +extern void dmxCopyClip(GCPtr pGCDst, GCPtr pGCSrc); + +extern void dmxBECreateGC(ScreenPtr pScreen, GCPtr pGC); +extern Bool dmxBEFreeGC(GCPtr pGC); + +/** Private index. \see dmxgc.c \see dmxscrinit.c */ +extern int dmxGCPrivateIndex; + +/** Get private. */ +#define DMX_GET_GC_PRIV(_pGC) \ + (dmxGCPrivPtr)(_pGC)->devPrivates[dmxGCPrivateIndex].ptr + +#define DMX_GC_FUNC_PROLOGUE(_pGC) \ +do { \ + dmxGCPrivPtr _pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_UNWRAP(funcs, _pGCPriv, (_pGC)); \ + if (_pGCPriv->ops) \ + DMX_UNWRAP(ops, _pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_GC_FUNC_EPILOGUE(_pGC) \ +do { \ + dmxGCPrivPtr _pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_WRAP(funcs, &dmxGCFuncs, _pGCPriv, (_pGC)); \ + if (_pGCPriv->ops) \ + DMX_WRAP(ops, &dmxGCOps, _pGCPriv, (_pGC)); \ +} while (0) + +#endif /* DMXGC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgcops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgcops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxgcops.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for gcops support. \see dmxgcops.c */ + +#ifndef DMXGCOPS_H +#define DMXGCOPS_H + +extern void dmxFillSpans(DrawablePtr pDrawable, GCPtr pGC, + int nInit, DDXPointPtr pptInit, int *pwidthInit, + int fSorted); +extern void dmxSetSpans(DrawablePtr pDrawable, GCPtr pGC, + char *psrc, DDXPointPtr ppt, int *pwidth, int nspans, + int fSorted); +extern void dmxPutImage(DrawablePtr pDrawable, GCPtr pGC, + int depth, int x, int y, int w, int h, + int leftPad, int format, char *pBits); +extern RegionPtr dmxCopyArea(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, + int dstx, int dsty); +extern RegionPtr dmxCopyPlane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty, unsigned long bitPlane); +extern void dmxPolyPoint(DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr pptInit); +extern void dmxPolylines(DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr pptInit); +extern void dmxPolySegment(DrawablePtr pDrawable, GCPtr pGC, + int nseg, xSegment *pSegs); +extern void dmxPolyRectangle(DrawablePtr pDrawable, GCPtr pGC, + int nrects, xRectangle *pRects); +extern void dmxPolyArc(DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *parcs); +extern void dmxFillPolygon(DrawablePtr pDrawable, GCPtr pGC, + int shape, int mode, int count, DDXPointPtr pPts); +extern void dmxPolyFillRect(DrawablePtr pDrawable, GCPtr pGC, + int nrectFill, xRectangle *prectInit); +extern void dmxPolyFillArc(DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *parcs); +extern int dmxPolyText8(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, char *chars); +extern int dmxPolyText16(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, unsigned short *chars); +extern void dmxImageText8(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, char *chars); +extern void dmxImageText16(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, unsigned short *chars); +extern void dmxImageGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); +extern void dmxPolyGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); +extern void dmxPushPixels(GCPtr pGC, PixmapPtr pBitMap, DrawablePtr pDst, + int w, int h, int x, int y); + +extern void dmxGetImage(DrawablePtr pDrawable, int sx, int sy, int w, int h, + unsigned int format, unsigned long planeMask, + char *pdstLine); +extern void dmxGetSpans(DrawablePtr pDrawable, int wMax, + DDXPointPtr ppt, int *pwidth, int nspans, + char *pdstStart); + +#endif /* DMXGCOPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinit.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86$ */ +/* + * Copyright 2004 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for initialization. \see dmxinit.c */ + +#ifndef DMXINIT_H +#define DMXINIT_H + +#include "scrnintstr.h" + +extern Bool dmxOpenDisplay(DMXScreenInfo *dmxScreen); +extern void dmxSetErrorHandler(DMXScreenInfo *dmxScreen); +extern void dmxCheckForWM(DMXScreenInfo *dmxScreen); +extern void dmxGetScreenAttribs(DMXScreenInfo *dmxScreen); +extern Bool dmxGetVisualInfo(DMXScreenInfo *dmxScreen); +extern void dmxGetColormaps(DMXScreenInfo *dmxScreen); +extern void dmxGetPixmapFormats(DMXScreenInfo *dmxScreen); + +#endif /* DMXINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinput.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinput.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinput.h (revision 51223) @@ -0,0 +1,163 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * David H. Dawes + * Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +/** \file + * This file provides access to: + * - global variables available to all hw/dmx routines, and + * - enumerations and typedefs needed by input routines in hw/dmx (and + * hw/dmx/input). + * + * The goal is that no files in hw/dmx should include header files from + * hw/dmx/input -- the interface defined here should be the only + * interface exported to the hw/dmx layer. \see input/dmxinputinit.c. + */ + +#ifndef DMXINPUT_H +#define DMXINPUT_H + +/** Maximum number of file descriptors for SIGIO handling */ +#define DMX_MAX_SIGIO_FDS 4 + +struct _DMXInputInfo; + +/** Reason why window layout was updated. */ +typedef enum { + DMX_UPDATE_REALIZE, /**< Window realized */ + DMX_UPDATE_UNREALIZE, /**< Window unrealized */ + DMX_UPDATE_RESTACK, /**< Stacking order changed */ + DMX_UPDATE_COPY, /**< Window copied */ + DMX_UPDATE_RESIZE, /**< Window resized */ + DMX_UPDATE_REPARENT /**< Window reparented */ +} DMXUpdateType; + +typedef void (*ProcessInputEventsProc)(struct _DMXInputInfo *); +typedef void (*UpdateWindowInfoProc)(struct _DMXInputInfo *, + DMXUpdateType, WindowPtr); + +/** An opaque structure that is only exposed in the dmx/input layer. */ +typedef struct _DMXLocalInputInfo *DMXLocalInputInfoPtr; + +/** State of the SIGIO engine */ +typedef enum { + DMX_NOSIGIO = 0, /**< Device does not use SIGIO at all. */ + DMX_USESIGIO, /**< Device can use SIGIO, but is not + * (e.g., because the VT is switch + * away). */ + DMX_ACTIVESIGIO /**< Device is currently using SIGIO. */ +} dmxSigioState; + +/** DMXInputInfo is typedef'd in #dmx.h so that all routines can have + * access to the global pointers. However, the elements are only + * available to input-related routines. */ +struct _DMXInputInfo { + const char *name; /**< Name of input display or device + * (from command line or config + * file) */ + Bool freename; /**< If true, free name on destroy */ + Bool detached; /**< If true, input screen is detached */ + int inputIdx; /**< Index into #dmxInputs global */ + int scrnIdx; /**< Index into #dmxScreens global */ + Bool core; /**< If True, initialize these + * devices as devices that send core + * events */ + Bool console; /**< True if console and backend + * input share the same backend + * display */ + + Bool windows; /**< True if window outlines are + * draw in console */ + + ProcessInputEventsProc processInputEvents; + UpdateWindowInfoProc updateWindowInfo; + + /* Local input information */ + dmxSigioState sigioState; /**< Current stat */ + int sigioFdCount; /**< Number of fds in use */ + int sigioFd[DMX_MAX_SIGIO_FDS]; /**< List of fds */ + Bool sigioAdded[DMX_MAX_SIGIO_FDS]; /**< Active fds */ + + + /** True if a VT switch is pending, but has not yet happened. */ + int vt_switch_pending; + + /** True if a VT switch has happened. */ + int vt_switched; + + /** Number of devices handled in this _DMXInputInfo structure. */ + int numDevs; + + /** List of actual input devices. Each _DMXInputInfo structure can + * refer to more than one device. For example, the keyboard and the + * pointer of a backend display; or all of the XInput extension + * devices on a backend display. */ + DMXLocalInputInfoPtr *devs; + + char *keycodes; /**< XKB keycodes from command line */ + char *symbols; /**< XKB symbols from command line */ + char *geometry; /**< XKB geometry from command line */ +}; + +extern int dmxNumInputs; /**< Number of #dmxInputs */ +extern DMXInputInfo *dmxInputs; /**< List of inputs */ + +extern void dmxInputInit(DMXInputInfo *dmxInput); +extern void dmxInputReInit(DMXInputInfo *dmxInput); +extern void dmxInputLateReInit(DMXInputInfo *dmxInput); +extern void dmxInputFree(DMXInputInfo *dmxInput); +extern void dmxInputLogDevices(void); +extern void dmxUpdateWindowInfo(DMXUpdateType type, WindowPtr pWindow); + +/* These functions are defined in input/dmxeq.c */ +extern Bool dmxeqInitialized(void); +extern void dmxeqEnqueue(xEvent *e); +extern void dmxeqSwitchScreen(ScreenPtr pScreen, Bool fromDIX); + +/* This type is used in input/dmxevents.c. Also, these functions are + * defined in input/dmxevents.c */ +typedef enum { + DMX_NO_BLOCK = 0, + DMX_BLOCK = 1 +} DMXBlockType; + +extern void dmxGetGlobalPosition(int *x, int *y); +extern DMXScreenInfo *dmxFindFirstScreen(int x, int y); +extern void dmxCoreMotion(int x, int y, int delta, + DMXBlockType block); + +/* Support for dynamic addition of inputs. This functions is defined in + * config/dmxconfig.c */ +extern DMXInputInfo *dmxConfigAddInput(const char *name, int core); +#endif /* DMXINPUT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinputinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinputinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxinputinit.h (revision 51223) @@ -0,0 +1,294 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for low-level input support. \see dmxinputinit.c */ + +#ifndef _DMXINPUTINIT_H_ +#define _DMXINPUTINIT_H_ + +#include "dmx.h" +#include "dmxinput.h" +#include "dmxlog.h" + + +#define DMX_LOCAL_DEFAULT_KEYBOARD "kbd" +#define DMX_LOCAL_DEFAULT_POINTER "ps2" +#define DMX_MAX_BUTTONS 256 +#define DMX_MOTION_SIZE 256 +#define DMX_MAX_VALUATORS 32 +#define DMX_MAX_AXES 32 +#define DMX_MAX_XINPUT_EVENT_TYPES 100 +#define DMX_MAP_ENTRIES 16 /* Must be a power of 2 */ +#define DMX_MAP_MASK (DMX_MAP_ENTRIES - 1) + +typedef enum { + DMX_FUNCTION_GRAB, + DMX_FUNCTION_TERMINATE, + DMX_FUNCTION_FINE +} DMXFunctionType; + +typedef enum { + DMX_LOCAL_HIGHLEVEL, + DMX_LOCAL_KEYBOARD, + DMX_LOCAL_MOUSE, + DMX_LOCAL_OTHER +} DMXLocalInputType; + +typedef enum { + DMX_LOCAL_TYPE_LOCAL, + DMX_LOCAL_TYPE_CONSOLE, + DMX_LOCAL_TYPE_BACKEND, + DMX_LOCAL_TYPE_COMMON +} DMXLocalInputExtType; + +typedef enum { + DMX_RELATIVE, + DMX_ABSOLUTE, + DMX_ABSOLUTE_CONFINED +} DMXMotionType; + +/** Stores information from low-level device that is used to initialize + * the device at the dix level. */ +typedef struct _DMXLocalInitInfo { + int keyboard; /**< Non-zero if the device is a keyboard */ + + int keyClass; /**< Non-zero if keys are present */ + KeySymsRec keySyms; /**< Key symbols */ + int freemap; /**< If non-zero, free keySyms.map */ + CARD8 modMap[MAP_LENGTH]; /**< Modifier map */ +#ifdef XKB + XkbDescPtr xkb; /**< XKB description */ + XkbComponentNamesRec names; /**< XKB component names */ + int freenames; /**< Non-zero if names should be free'd */ + int force; /**< Do not allow command line override */ +#endif + + int buttonClass; /**< Non-zero if buttons are present */ + int numButtons; /**< Number of buttons */ + unsigned char map[DMX_MAX_BUTTONS]; /**< Button map */ + + int valuatorClass; /**< Non-zero if valuators are + * present */ + int numRelAxes; /**< Number of relative axes */ + int numAbsAxes; /**< Number of absolute axes */ + int minval[DMX_MAX_AXES]; /**< Minimum values */ + int maxval[DMX_MAX_AXES]; /**< Maximum values */ + int res[DMX_MAX_AXES]; /**< Resolution */ + int minres[DMX_MAX_AXES]; /**< Minimum resolutions */ + int maxres[DMX_MAX_AXES]; /**< Maximum resolutions */ + + int focusClass; /**< Non-zero if device can + * cause focus */ + int proximityClass; /**< Non-zero if device + * causes proximity events */ + int kbdFeedbackClass; /**< Non-zero if device has + * keyboard feedback */ + int ptrFeedbackClass; /**< Non-zero if device has + * pointer feedback */ + int ledFeedbackClass; /**< Non-zero if device has + * LED indicators */ + int belFeedbackClass; /**< Non-zero if device has a + * bell */ + int intFeedbackClass; /**< Non-zero if device has + * integer feedback */ + int strFeedbackClass; /**< Non-zero if device has + * string feedback */ + + int maxSymbols; /**< Maximum symbols */ + int maxSymbolsSupported; /**< Maximum symbols supported */ + KeySym *symbols; /**< Key symbols */ +} DMXLocalInitInfo, *DMXLocalInitInfoPtr; + +typedef pointer (*dmxCreatePrivateProcPtr)(DeviceIntPtr); +typedef void (*dmxDestroyPrivateProcPtr)(pointer); + +typedef void (*dmxInitProcPtr)(DevicePtr); +typedef void (*dmxReInitProcPtr)(DevicePtr); +typedef void (*dmxLateReInitProcPtr)(DevicePtr); +typedef void (*dmxGetInfoProcPtr)(DevicePtr, DMXLocalInitInfoPtr); +typedef int (*dmxOnProcPtr)(DevicePtr); +typedef void (*dmxOffProcPtr)(DevicePtr); +typedef void (*dmxUpdatePositionProcPtr)(pointer, int x, int y); + +typedef void (*dmxVTPreSwitchProcPtr)(pointer); /* Turn I/O Off */ +typedef void (*dmxVTPostSwitchProcPtr)(pointer); /* Turn I/O On */ +typedef void (*dmxVTSwitchReturnProcPtr)(pointer); +typedef int (*dmxVTSwitchProcPtr)(pointer, int vt, + dmxVTSwitchReturnProcPtr, pointer); + +typedef void (*dmxMotionProcPtr)(DevicePtr, + int *valuators, + int firstAxis, + int axesCount, + DMXMotionType type, + DMXBlockType block); +typedef void (*dmxEnqueueProcPtr)(DevicePtr, int type, int detail, + KeySym keySym, XEvent *e, + DMXBlockType block); +typedef int (*dmxCheckSpecialProcPtr)(DevicePtr, KeySym keySym); +typedef void (*dmxCollectEventsProcPtr)(DevicePtr, + dmxMotionProcPtr, + dmxEnqueueProcPtr, + dmxCheckSpecialProcPtr, + DMXBlockType); +typedef void (*dmxProcessInputProcPtr)(pointer); +typedef void (*dmxUpdateInfoProcPtr)(pointer, DMXUpdateType, WindowPtr); +typedef int (*dmxFunctionsProcPtr)(pointer, DMXFunctionType); + +typedef void (*dmxKBCtrlProcPtr)(DevicePtr, KeybdCtrl *ctrl); +typedef void (*dmxMCtrlProcPtr)(DevicePtr, PtrCtrl *ctrl); +typedef void (*dmxKBBellProcPtr)(DevicePtr, int percent, + int volume, int pitch, int duration); + +/** Stores a mapping between the device id on the remote X server and + * the id on the DMX server */ +typedef struct _DMXEventMap { + int remote; /**< Event number on remote X server */ + int server; /**< Event number (unbiased) on DMX server */ +} DMXEventMap; + +/** This is the device-independent structure used by the low-level input + * routines. The contents are not exposed to top-level .c files (except + * dmxextensions.c). \see dmxinput.h \see dmxextensions.c */ +typedef struct _DMXLocalInputInfo { + const char *name; /**< Device name */ + DMXLocalInputType type; /**< Device type */ + DMXLocalInputExtType extType; /**< Extended device type */ + int binding; /**< Count of how many consecutive + * structs are bound to the same + * device */ + + /* Low-level (e.g., keyboard/mouse drivers) */ + + dmxCreatePrivateProcPtr create_private; /**< Create + * device-dependent + * private */ + dmxDestroyPrivateProcPtr destroy_private; /**< Destroy + * device-dependent + * private */ + dmxInitProcPtr init; /**< Initialize device */ + dmxReInitProcPtr reinit; /**< Reinitialize device + * (during a + * reconfiguration) */ + dmxLateReInitProcPtr latereinit; /**< Reinitialize a device + * (called very late + * during a + * reconfiguration) */ + dmxGetInfoProcPtr get_info; /**< Get device information */ + dmxOnProcPtr on; /**< Turn device on */ + dmxOffProcPtr off; /**< Turn device off */ + dmxUpdatePositionProcPtr update_position; /**< Called when another + * device updates the + * cursor position */ + dmxVTPreSwitchProcPtr vt_pre_switch; /**< Called before a VT switch */ + dmxVTPostSwitchProcPtr vt_post_switch; /**< Called after a VT switch */ + dmxVTSwitchProcPtr vt_switch; /**< Causes a VT switch */ + + dmxCollectEventsProcPtr collect_events; /**< Collect and enqueue + * events from the + * device*/ + dmxProcessInputProcPtr process_input; /**< Process event (from + * queue) */ + dmxFunctionsProcPtr functions; + dmxUpdateInfoProcPtr update_info; /**< Update window layout + * information */ + + dmxMCtrlProcPtr mCtrl; /**< Pointer control */ + dmxKBCtrlProcPtr kCtrl; /**< Keyboard control */ + dmxKBBellProcPtr kBell; /**< Bell control */ + + pointer private; /**< Device-dependent private */ + int isCore; /**< Is a DMX core device */ + int sendsCore; /**< Sends DMX core events */ + KeybdCtrl kctrl; /**< Keyboard control */ + PtrCtrl mctrl; /**< Pointer control */ + + DeviceIntPtr pDevice; /**< X-level device */ + int inputIdx; /**< High-level index */ + int lastX, lastY; /**< Last known position; + * for XInput in + * dmxevents.c */ + + int head; /**< XInput motion history + * head */ + int tail; /**< XInput motion history + * tail */ + unsigned long *history; /**< XInput motion history */ + int *valuators; /**< Cache of previous values */ + + /* for XInput ChangePointerDevice */ + int (*savedMotionProc)(DeviceIntPtr, + xTimecoord *, + unsigned long, + unsigned long, + ScreenPtr); + int savedMotionEvents; /**< Saved motion events */ + int savedSendsCore; /**< Saved sends-core flag */ + + DMXEventMap map[DMX_MAP_ENTRIES]; /**< XInput device id map */ + int mapOptimize; /**< XInput device id + * map + * optimization */ + + long deviceId; /**< device id on remote side, + * if any */ + const char *deviceName; /**< devive name on remote + * side, if any */ +} DMXLocalInputInfoRec; + +extern DMXLocalInputInfoPtr dmxLocalCorePointer, dmxLocalCoreKeyboard; + +extern void dmxLocalInitInput(DMXInputInfo *dmxInput); +extern DMXLocalInputInfoPtr dmxInputCopyLocal(DMXInputInfo *dmxInput, + DMXLocalInputInfoPtr s); + +extern void dmxChangePointerControl(DeviceIntPtr pDevice, PtrCtrl *ctrl); +extern void dmxKeyboardKbdCtrlProc(DeviceIntPtr pDevice, KeybdCtrl *ctrl); +extern void dmxKeyboardBellProc(int percent, DeviceIntPtr pDevice, + pointer ctrl, int unknown); + +extern int dmxInputExtensionErrorHandler(Display *dsp, char *name, + char *reason); + +extern int dmxInputDetach(DMXInputInfo *dmxInput); +extern void dmxInputDetachAll(DMXScreenInfo *dmxScreen); +extern int dmxInputDetachId(int id); +extern DMXInputInfo *dmxInputLocateId(int id); +extern int dmxInputAttachConsole(const char *name, int isCore, + int *id); +extern int dmxInputAttachBackend(int physicalScreen, int isCore, + int *id); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxlog.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxlog.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxlog.h (revision 51223) @@ -0,0 +1,79 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * This header is included by all files that need to use the DMX logging + * facilities. */ + +#ifndef _DMXLOG_H_ +#define _DMXLOG_H_ + +/** Logging levels -- output is tunable with #dmxSetLogLevel. */ +typedef enum { + dmxDebug, /**< Usually verbose debugging info */ + dmxInfo, /**< Non-warning information */ + dmxWarning, /**< A warning that may indicate DMX + * will not function as the user + * intends. */ + dmxError, /**< A non-fatal error that probably + * indicates DMX will not function as + * desired.*/ + dmxFatal /**< A fatal error that will cause DMX + * to shut down. */ +} dmxLogLevel; + +/* Logging functions used by Xserver/hw/dmx routines. */ +extern dmxLogLevel dmxSetLogLevel(dmxLogLevel newLevel); +extern dmxLogLevel dmxGetLogLevel(void); +extern void dmxLog(dmxLogLevel logLevel, const char *format, ...); +extern void dmxLogCont(dmxLogLevel logLevel, const char *format, ...); +extern const char *dmxEventName(int type); + +#ifndef DMX_LOG_STANDALONE +extern void dmxLogOutput(DMXScreenInfo *dmxScreen, const char *format, ...); +extern void dmxLogOutputCont(DMXScreenInfo *dmxScreen, const char *format, + ...); +extern void dmxLogOutputWarning(DMXScreenInfo *dmxScreen, const char *format, + ...); +extern void dmxLogInput(DMXInputInfo *dmxInput, const char *format, ...); +extern void dmxLogInputCont(DMXInputInfo *dmxInput, const char *format, ...); +extern void dmxLogArgs(dmxLogLevel logLevel, int argc, char **argv); +extern void dmxLogVisual(DMXScreenInfo *dmxScreen, XVisualInfo *vi, + int defaultVisual); +#ifdef XINPUT +extern const char *dmxXInputEventName(int type); +#endif +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmap.h (revision 51223) @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + */ + +/** \file + * Interface to XInput event mapping support. \see dmxmap.c */ + +#ifndef _DMXMAP_H_ +#define _DMXMAP_H_ +extern void dmxMapInsert(DMXLocalInputInfoPtr dmxLocal, + int remoteEvent, int serverEvent); +extern void dmxMapClear(DMXLocalInputInfoPtr dmxLocal); +extern int dmxMapLookup(DMXLocalInputInfoPtr dmxLocal, int remoteEvent); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmotion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmotion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxmotion.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to functions supporting motion events. \see dmxmotion.c */ + +#ifndef _DMXMOTION_H_ +#define _DMXMOTION_H_ + +extern int dmxPointerGetMotionBufferSize(void); +extern int dmxPointerGetMotionEvents(DeviceIntPtr pDevice, + xTimecoord *coords, + unsigned long start, + unsigned long stop, + ScreenPtr pScreen); +extern void dmxPointerPutMotionEvent(DeviceIntPtr pDevice, + int firstAxis, int axesCount, int *v, + unsigned long time); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxparse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxparse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxparse.h (revision 51223) @@ -0,0 +1,298 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to DMX configuration file parser. \see dmxparse.c */ + +#ifndef _DMXPARSE_H_ +#define _DMXPARSE_H_ + +#include /* For FILE */ + +/** Stores tokens not stored in other structures (e.g., keywords and ;) */ +typedef struct _DMXConfigToken { + int token; + int line; + const char *comment; +} DMXConfigToken, *DMXConfigTokenPtr; + +/** Stores parsed strings. */ +typedef struct _DMXConfigString { + int token; + int line; + const char *comment; + const char *string; + struct _DMXConfigString *next; +} DMXConfigString, *DMXConfigStringPtr; + +/** Stores parsed numbers. */ +typedef struct _DMXConfigNumber { + int token; + int line; + const char *comment; + int number; +} DMXConfigNumber, *DMXConfigNumberPtr; + +/** Stores parsed pairs (e.g., x y) */ +typedef struct _DMXConfigPair { + int token; + int line; + const char *comment; + int x; + int y; + int xsign; + int ysign; +} DMXConfigPair, *DMXConfigPairPtr; + +/** Stores parsed comments not stored with a token. */ +typedef struct _DMXConfigComment { + int token; + int line; + const char *comment; +} DMXConfigComment, *DMXConfigCommentPtr; + +typedef enum { + dmxConfigComment, + dmxConfigVirtual, + dmxConfigDisplay, + dmxConfigWall, + dmxConfigOption, + dmxConfigParam +} DMXConfigType; + +/** Stores a geometry specification. */ +typedef struct _DMXConfigPartDim { + DMXConfigPairPtr dim; + DMXConfigPairPtr offset; +} DMXConfigPartDim, *DMXConfigPartDimPtr; + +/** Stores a pair of geometry specifications. */ +typedef struct _DMXConfigFullDim { + DMXConfigPartDimPtr scrn; + DMXConfigPartDimPtr root; +} DMXConfigFullDim, *DMXConfigFullDimPtr; + +/** Stores parsed display information. */ +typedef struct _DMXConfigDisplay { + /* Summary information */ + const char *name; + /* Screen Window Geometry */ + int scrnWidth, scrnHeight; + int scrnX, scrnY; + int scrnXSign, scrnYSign; + /* Root Window Geometry */ + int rootWidth, rootHeight; + int rootX, rootY; + int rootXSign, rootYSign; + /* Origin in global space */ + int rootXOrigin, rootYOrigin; + + /* Raw configuration information */ + DMXConfigTokenPtr start; + DMXConfigStringPtr dname; + DMXConfigFullDimPtr dim; + DMXConfigPairPtr origin; + DMXConfigTokenPtr end; +} DMXConfigDisplay, *DMXConfigDisplayPtr; + +/** Stores parsed wall information. */ +typedef struct _DMXConfigWall { + /* Summary information */ + int width, height; /* dimensions of displays */ + int xwall, ywall; /* dimensions of wall, in tiles */ + + + /* Raw configuration informaiton */ + DMXConfigTokenPtr start; + DMXConfigPairPtr wallDim; + DMXConfigPairPtr displayDim; + DMXConfigStringPtr nameList; + DMXConfigTokenPtr end; +} DMXConfigWall, *DMXConfigWallPtr; + +/** Stores parsed option information. */ +typedef struct _DMXConfigOption { + /* Summary information */ + char *string; + + /* Raw configuration informaiton */ + DMXConfigTokenPtr start; + DMXConfigStringPtr option; + DMXConfigTokenPtr end; +} DMXConfigOption, *DMXConfigOptionPtr; + +/** Stores parsed param information. */ +typedef struct _DMXConfigParam { + int argc; + const char **argv; + + DMXConfigTokenPtr start; + DMXConfigTokenPtr open; + DMXConfigStringPtr param; + DMXConfigTokenPtr close; + DMXConfigTokenPtr end; /* Either open/close OR end */ + struct _DMXConfigParam *next; +} DMXConfigParam, *DMXConfigParamPtr; + +/** Stores options under an entry (subentry). */ +typedef struct _DMXConfigSub { + DMXConfigType type; + DMXConfigCommentPtr comment; + DMXConfigDisplayPtr display; + DMXConfigWallPtr wall; + DMXConfigOptionPtr option; + DMXConfigParamPtr param; + struct _DMXConfigSub *next; +} DMXConfigSub, *DMXConfigSubPtr; + +/** Stores parsed virtual information. */ +typedef struct _DMXConfigVirtual { + /* Summary information */ + const char *name; + int width, height; + + /* Raw configuration information */ + DMXConfigTokenPtr start; + DMXConfigStringPtr vname; + DMXConfigPairPtr dim; + DMXConfigTokenPtr open; + DMXConfigSubPtr subentry; + DMXConfigTokenPtr close; +} DMXConfigVirtual, *DMXConfigVirtualPtr; + +/** Heads entry storage. */ +typedef struct _DMXConfigEntry { + DMXConfigType type; + DMXConfigCommentPtr comment; + DMXConfigVirtualPtr virtual; + struct _DMXConfigEntry *next; +} DMXConfigEntry, *DMXConfigEntryPtr; + +extern DMXConfigEntryPtr dmxConfigEntry; + +extern int yylex(void); +extern int yydebug; +extern void yyerror(const char *message); + +extern void dmxConfigLog(const char *format, ...); +extern void *dmxConfigAlloc(unsigned long bytes); +extern void *dmxConfigRealloc(void *orig, + unsigned long orig_bytes, + unsigned long bytes); +extern const char *dmxConfigCopyString(const char *string, + int length); +extern void dmxConfigFree(void *area); +extern DMXConfigTokenPtr dmxConfigCreateToken(int token, int line, + const char *comment); +extern void dmxConfigFreeToken(DMXConfigTokenPtr p); +extern DMXConfigStringPtr dmxConfigCreateString(int token, int line, + const char *comment, + const char *string); +extern void dmxConfigFreeString(DMXConfigStringPtr p); +extern DMXConfigNumberPtr dmxConfigCreateNumber(int token, int line, + const char *comment, + int number); +extern void dmxConfigFreeNumber(DMXConfigNumberPtr p); +extern DMXConfigPairPtr dmxConfigCreatePair(int token, int line, + const char *comment, + int x, int y, + int xsign, int ysign); +extern void dmxConfigFreePair(DMXConfigPairPtr p); +extern DMXConfigCommentPtr dmxConfigCreateComment(int token, int line, + const char *comment); +extern void dmxConfigFreeComment(DMXConfigCommentPtr p); +extern DMXConfigPartDimPtr dmxConfigCreatePartDim(DMXConfigPairPtr pDim, + DMXConfigPairPtr pOffset); +extern void dmxConfigFreePartDim(DMXConfigPartDimPtr p); +extern DMXConfigFullDimPtr dmxConfigCreateFullDim(DMXConfigPartDimPtr pScrn, + DMXConfigPartDimPtr pRoot); +extern void dmxConfigFreeFullDim(DMXConfigFullDimPtr p); +extern DMXConfigDisplayPtr dmxConfigCreateDisplay(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pName, + DMXConfigFullDimPtr pDim, + DMXConfigPairPtr pOrigin, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeDisplay(DMXConfigDisplayPtr p); +extern DMXConfigWallPtr dmxConfigCreateWall(DMXConfigTokenPtr pStart, + DMXConfigPairPtr pWallDim, + DMXConfigPairPtr pDisplayDim, + DMXConfigStringPtr pNameList, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeWall(DMXConfigWallPtr p); +extern DMXConfigOptionPtr dmxConfigCreateOption(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pOption, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeOption(DMXConfigOptionPtr p); +extern DMXConfigParamPtr dmxConfigCreateParam(DMXConfigTokenPtr pStart, + DMXConfigTokenPtr pOpen, + DMXConfigStringPtr pParam, + DMXConfigTokenPtr pClose, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeParam(DMXConfigParamPtr p); +extern const char **dmxConfigLookupParam(DMXConfigParamPtr p, + const char *key, + int *argc); +extern DMXConfigSubPtr dmxConfigCreateSub(DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigDisplayPtr display, + DMXConfigWallPtr wall, + DMXConfigOptionPtr option, + DMXConfigParamPtr param); +extern void dmxConfigFreeSub(DMXConfigSubPtr sub); +extern DMXConfigSubPtr dmxConfigSubComment(DMXConfigCommentPtr comment); +extern DMXConfigSubPtr dmxConfigSubDisplay(DMXConfigDisplayPtr display); +extern DMXConfigSubPtr dmxConfigSubWall(DMXConfigWallPtr wall); +extern DMXConfigSubPtr dmxConfigSubOption(DMXConfigOptionPtr option); +extern DMXConfigSubPtr dmxConfigSubParam(DMXConfigParamPtr param); +extern DMXConfigSubPtr dmxConfigAddSub(DMXConfigSubPtr head, + DMXConfigSubPtr sub); +extern DMXConfigVirtualPtr dmxConfigCreateVirtual(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pName, + DMXConfigPairPtr pDim, + DMXConfigTokenPtr pOpen, + DMXConfigSubPtr pSubentry, + DMXConfigTokenPtr pClose); +extern void dmxConfigFreeVirtual(DMXConfigVirtualPtr virtual); +extern DMXConfigEntryPtr dmxConfigCreateEntry(DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigVirtualPtr virtual); +extern void dmxConfigFreeEntry(DMXConfigEntryPtr entry); +extern DMXConfigEntryPtr dmxConfigAddEntry(DMXConfigEntryPtr head, + DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigVirtualPtr virtual); +extern DMXConfigEntryPtr dmxConfigEntryComment(DMXConfigCommentPtr comment); +extern DMXConfigEntryPtr dmxConfigEntryVirtual(DMXConfigVirtualPtr virtual); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpict.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * This file provides access to the externally visible RENDER support + * functions, global variables and macros for DMX. + * + * FIXME: Move function definitions for non-externally visible function + * to .c file. */ + +#ifndef DMXPICT_H +#define DMXPICT_H + +/** Picture private structure */ +typedef struct _dmxPictPriv { + Picture pict; /**< Picture ID from back-end server */ + Mask savedMask; /**< Mask of picture attributes saved for + * lazy window creation. */ +} dmxPictPrivRec, *dmxPictPrivPtr; + + +/** Glyph Set private structure */ +typedef struct _dmxGlyphPriv { + GlyphSet *glyphSets; /**< Glyph Set IDs from back-end server */ +} dmxGlyphPrivRec, *dmxGlyphPrivPtr; + + +extern void dmxInitRender(void); +extern void dmxResetRender(void); + +extern Bool dmxPictureInit(ScreenPtr pScreen, + PictFormatPtr formats, int nformats); + +extern void dmxCreatePictureList(WindowPtr pWindow); +extern Bool dmxDestroyPictureList(WindowPtr pWindow); + +extern int dmxCreatePicture(PicturePtr pPicture); +extern void dmxDestroyPicture(PicturePtr pPicture); +extern int dmxChangePictureClip(PicturePtr pPicture, int clipType, + pointer value, int n); +extern void dmxDestroyPictureClip(PicturePtr pPicture); +extern void dmxChangePicture(PicturePtr pPicture, Mask mask); +extern void dmxValidatePicture(PicturePtr pPicture, Mask mask); +extern void dmxComposite(CARD8 op, + PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst, + INT16 xSrc, INT16 ySrc, + INT16 xMask, INT16 yMask, + INT16 xDst, INT16 yDst, + CARD16 width, CARD16 height); +extern void dmxGlyphs(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int nlists, GlyphListPtr lists, GlyphPtr *glyphs); +extern void dmxCompositeRects(CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, xRectangle *rects); +extern Bool dmxInitIndexed(ScreenPtr pScreen, PictFormatPtr pFormat); +extern void dmxCloseIndexed(ScreenPtr pScreen, PictFormatPtr pFormat); +extern void dmxUpdateIndexed(ScreenPtr pScreen, PictFormatPtr pFormat, + int ndef, xColorItem *pdef); +extern void dmxTrapezoids(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int ntrap, xTrapezoid *traps); +extern void dmxTriangles(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int ntri, xTriangle *tris); +extern void dmxTriStrip(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int npoint, xPointFixed *points); +extern void dmxTriFan(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int npoint, xPointFixed *points); + +extern Bool dmxBEFreeGlyphSet(ScreenPtr pScreen, GlyphSetPtr glyphSet); +extern Bool dmxBEFreePicture(PicturePtr pPicture); + +extern int dmxPictPrivateIndex; /**< Index for picture private data */ +extern int dmxGlyphSetPrivateIndex; /**< Index for glyphset private data */ + + +/** Get the picture private data given a picture pointer */ +#define DMX_GET_PICT_PRIV(_pPict) \ + (dmxPictPrivPtr)(_pPict)->devPrivates[dmxPictPrivateIndex].ptr + +/** Set the glyphset private data given a glyphset pointer */ +#define DMX_SET_GLYPH_PRIV(_pGlyph, _pPriv) \ + GlyphSetSetPrivate((_pGlyph), dmxGlyphSetPrivateIndex, (_pPriv)) +/** Get the glyphset private data given a glyphset pointer */ +#define DMX_GET_GLYPH_PRIV(_pGlyph) \ + (dmxGlyphPrivPtr)GlyphSetGetPrivate((_pGlyph), dmxGlyphSetPrivateIndex) + +#endif /* DMXPICT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpixmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpixmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxpixmap.h (revision 51223) @@ -0,0 +1,67 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for pixmap support. \see dmxpixmap.c */ + +#ifndef DMXPIXMAP_H +#define DMXPIXMAP_H + +#include "pixmapstr.h" + +/** Pixmap private area. */ +typedef struct _dmxPixPriv { + Pixmap pixmap; + XImage *detachedImage; +} dmxPixPrivRec, *dmxPixPrivPtr; + + +extern Bool dmxInitPixmap(ScreenPtr pScreen); + +extern PixmapPtr dmxCreatePixmap(ScreenPtr pScreen, + int width, int height, int depth); +extern Bool dmxDestroyPixmap(PixmapPtr pPixmap); +extern RegionPtr dmxBitmapToRegion(PixmapPtr pPixmap); + +extern void dmxBECreatePixmap(PixmapPtr pPixmap); +extern Bool dmxBEFreePixmap(PixmapPtr pPixmap); + +/** Private index. \see dmxpicmap.h \see dmxscrinit.c */ +extern int dmxPixPrivateIndex; + +/** Get pixmap private pointer. */ +#define DMX_GET_PIXMAP_PRIV(_pPix) \ + (dmxPixPrivPtr)(_pPix)->devPrivates[dmxPixPrivateIndex].ptr + +#endif /* DMXPIXMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprint.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to DMX configuration file pretty-printer. \see dmxprint.c */ + +#ifndef _DMXPRINT_H_ +#define _DMXPRINT_H_ + +void dmxConfigPrint(FILE *str, DMXConfigEntryPtr entry); +void dmxConfigVirtualPrint(FILE *str, DMXConfigVirtualPtr p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxprop.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2002,2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for property support. \see dmxprop.c */ + +#ifndef _DMXPROP_H_ +#define _DMXPROP_H_ +extern int dmxPropertyDisplay(DMXScreenInfo *dmxScreen); +extern void dmxPropertyWindow(DMXScreenInfo *dmxScreen); +extern void *dmxPropertyIterate(DMXScreenInfo *start, + void *(*f)(DMXScreenInfo *dmxScreen, + void *closure), + void *closure); +extern int dmxPropertySameDisplay(DMXScreenInfo *dmxScreen, const char *name); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxscrinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxscrinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxscrinit.h (revision 51223) @@ -0,0 +1,52 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * + */ + +/** \file + * Interface for screen initialization. \see dmxscrinit.c */ + +#ifndef DMXSCRINIT_H +#define DMXSCRINIT_H + +#include "scrnintstr.h" + +/** Private index. \see dmxscrrinit.c \see input/dmxconcole.c */ +extern int dmxScreenPrivateIndex; + +extern Bool dmxScreenInit(int idx, ScreenPtr pScreen, int argc, char *argv[]); + +extern void dmxBEScreenInit(int idx, ScreenPtr pScreen); +extern void dmxBECloseScreen(ScreenPtr pScreen); + +#endif /* DMXSCRINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxshadow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxshadow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxshadow.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * + */ + +/** \file + * Interface for shadow framebuffer support. \see dmxshadow.c */ + +#ifndef DMXSHADOW_H +#define DMXSHADOW_H + +#include "shadow.h" +#include "scrnintstr.h" + +extern void dmxShadowUpdateProc(ScreenPtr pScreen, shadowBufPtr pBuf); + +#endif /* DMXSHADOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsigio.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsigio.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsigio.h (revision 51223) @@ -0,0 +1,46 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to SIGIO handling support. \see dmxsigio.c */ + +#ifndef _DMXSIGIO_H_ +#define _DMXSIGIO_H_ +extern void dmxSigioBlock(void); +extern void dmxSigioUnblock(void); +extern void dmxSigioEnableInput(void); +extern void dmxSigioDisableInput(void); +extern void dmxSigioRegister(DMXInputInfo *dmxInput, int fd); +extern void dmxSigioUnregister(DMXInputInfo *dmxInput); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxstat.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxstat.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxstat.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for statistic gathering interface. \see dmxstat.c */ + +#ifndef _DMXSTAT_H_ +#define _DMXSTAT_H_ + +#define DMX_STAT_LENGTH 10 /**< number of events for moving average */ +#define DMX_STAT_INTERVAL 1000 /**< msec between printouts */ +#define DMX_STAT_BINS 3 /**< number of bins */ +#define DMX_STAT_BIN0 10000 /**< us for bin[0] */ +#define DMX_STAT_BINMULT 100 /**< multiplier for next bin[] */ + +extern int dmxStatInterval; /**< Only for dmxstat.c and dmxsync.c */ +extern void dmxStatActivate(const char *interval, const char *displays); +extern DMXStatInfo *dmxStatAlloc(void); +extern void dmxStatFree(DMXStatInfo *); +extern void dmxStatInit(void); +extern void dmxStatSync(DMXScreenInfo *dmxScreen, + struct timeval *stop, struct timeval *start, + unsigned long pending); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsync.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsync.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxsync.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for sync support. \see dmxsync.c */ + +#ifndef _DMXSYNC_H_ +#define _DMXSYNC_H_ + +extern void dmxSyncActivate(const char *interval); +extern void dmxSyncInit(void); +extern void dmxSync(DMXScreenInfo *dmxScreen, Bool now); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxvisual.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxvisual.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxvisual.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for visual support. \see dmxvisual.c */ + +#ifndef DMXVISUAL_H +#define DMXVISUAL_H + +#include "scrnintstr.h" + +extern Visual *dmxLookupVisual(ScreenPtr pScreen, VisualPtr pVisual); +extern Visual *dmxLookupVisualFromID(ScreenPtr pScreen, VisualID vid); +extern Colormap dmxColormapFromDefaultVisual(ScreenPtr pScreen, + Visual *visual); + +#endif /* DMXVISUAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxwindow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxwindow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dmxwindow.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for window support. \see dmxwindow.c */ + +#ifndef DMXWINDOW_H +#define DMXWINDOW_H + +#include "windowstr.h" + +/** Window private area. */ +typedef struct _dmxWinPriv { + Window window; + Bool offscreen; + Bool mapped; + Bool restacked; + unsigned long attribMask; + Colormap cmap; + Visual *visual; +#ifdef SHAPE + Bool isShaped; +#endif +#ifdef RENDER + Bool hasPict; +#endif +#ifdef GLXEXT + void *swapGroup; + int barrier; + void (*windowDestroyed)(WindowPtr); + void (*windowUnmapped)(WindowPtr); +#endif +} dmxWinPrivRec, *dmxWinPrivPtr; + + +extern Bool dmxInitWindow(ScreenPtr pScreen); + +extern Window dmxCreateRootWindow(WindowPtr pWindow); + +extern void dmxGetDefaultWindowAttributes(WindowPtr pWindow, + Colormap *cmap, + Visual **visual); +extern void dmxCreateAndRealizeWindow(WindowPtr pWindow, Bool doSync); + +extern Bool dmxCreateWindow(WindowPtr pWindow); +extern Bool dmxDestroyWindow(WindowPtr pWindow); +extern Bool dmxPositionWindow(WindowPtr pWindow, int x, int y); +extern Bool dmxChangeWindowAttributes(WindowPtr pWindow, unsigned long mask); +extern Bool dmxRealizeWindow(WindowPtr pWindow); +extern Bool dmxUnrealizeWindow(WindowPtr pWindow); +extern void dmxRestackWindow(WindowPtr pWindow, WindowPtr pOldNextSib); +extern void dmxWindowExposures(WindowPtr pWindow, RegionPtr prgn, + RegionPtr other_exposed); +extern void dmxPaintWindowBackground(WindowPtr pWindow, RegionPtr pRegion, + int what); +extern void dmxPaintWindowBorder(WindowPtr pWindow, RegionPtr pRegion, + int what); +extern void dmxCopyWindow(WindowPtr pWindow, DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +extern void dmxResizeWindow(WindowPtr pWindow, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); +extern void dmxReparentWindow(WindowPtr pWindow, WindowPtr pPriorParent); + +extern void dmxChangeBorderWidth(WindowPtr pWindow, unsigned int width); + +extern void dmxResizeScreenWindow(ScreenPtr pScreen, + int x, int y, int w, int h); +extern void dmxResizeRootWindow(WindowPtr pRoot, + int x, int y, int w, int h); + +extern Bool dmxBEDestroyWindow(WindowPtr pWindow); + +#ifdef SHAPE +/* Support for shape extension */ +extern void dmxSetShape(WindowPtr pWindow); +#endif + +/** Private index. \see dmxwindow.c \see dmxscrinit.c */ +extern int dmxWinPrivateIndex; + +/** Get window private pointer. */ +#define DMX_GET_WINDOW_PRIV(_pWin) \ + ((dmxWinPrivPtr)(_pWin)->devPrivates[dmxWinPrivateIndex].ptr) + +/* All of these macros are only used in dmxwindow.c */ +#define DMX_WINDOW_FUNC_PROLOGUE(_pGC) \ +do { \ + dmxGCPrivPtr pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_UNWRAP(funcs, pGCPriv, (_pGC)); \ + if (pGCPriv->ops) \ + DMX_UNWRAP(ops, pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_WINDOW_FUNC_EPILOGUE(_pGC) \ +do { \ + dmxGCPrivPtr pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_WRAP(funcs, &dmxGCFuncs, pGCPriv, (_pGC)); \ + if (pGCPriv->ops) \ + DMX_WRAP(ops, &dmxGCOps, pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_WINDOW_X1(_pWin) \ + ((_pWin)->drawable.x - wBorderWidth(_pWin)) +#define DMX_WINDOW_Y1(_pWin) \ + ((_pWin)->drawable.y - wBorderWidth(_pWin)) +#define DMX_WINDOW_X2(_pWin) \ + ((_pWin)->drawable.x + wBorderWidth(_pWin) + (_pWin)->drawable.width) +#define DMX_WINDOW_Y2(_pWin) \ + ((_pWin)->drawable.y + wBorderWidth(_pWin) + (_pWin)->drawable.height) + +#define DMX_WINDOW_OFFSCREEN(_pWin) \ + (DMX_WINDOW_X1(_pWin) >= (_pWin)->drawable.pScreen->width || \ + DMX_WINDOW_Y1(_pWin) >= (_pWin)->drawable.pScreen->height || \ + DMX_WINDOW_X2(_pWin) <= 0 || \ + DMX_WINDOW_Y2(_pWin) <= 0) + +#endif /* DMXWINDOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/do-not-use-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/do-not-use-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/do-not-use-config.h (revision 51223) @@ -0,0 +1,581 @@ +/* include/do-not-use-config.h. Generated by configure. */ +/* include/do-not-use-config.h.in. Generated from configure.ac by autoheader. */ + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Define to 1 if `struct sockaddr_in' has a `sin_len' member */ +/* #undef BSD44SOCKETS */ + +/* Builder address */ +#define BUILDERADDR "xorg@lists.freedesktop.org" + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/opt/debrix/lib/X11/fonts/misc/,/opt/debrix/lib/X11/fonts/TTF/,/opt/debrix/lib/X11/fonts/OTF,/opt/debrix/lib/X11/fonts/Type1/,/opt/debrix/lib/X11/fonts/CID/,/opt/debrix/lib/X11/fonts/100dpi/,/opt/debrix/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP + systems. This function is required for `alloca.c' support on those systems. + */ +/* #undef CRAY_STACKSEG_END */ + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* Simple debug messages */ +/* #undef CYGDEBUG */ + +/* Debug window manager */ +/* #undef CYGMULTIWINDOW_DEBUG */ + +/* Debug messages for window handling */ +/* #undef CYGWINDOWING_DEBUG */ + +/* Define to 1 if using `alloca.c'. */ +/* #undef C_ALLOCA */ + +/* Support Damage extension */ +#define DAMAGE 1 + +/* Support DBE extension */ +#define DBE 1 + +/* Use ddxBeforeReset */ +/* #undef DDXBEFORERESET */ + +/* Use OsVendorFatalError */ +/* #undef DDXOSFATALERROR */ + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Use OsVendorVErrorF */ +/* #undef DDXOSVERRORF */ + +/* Use GetTimeInMillis */ +/* #undef DDXTIME */ + +/* Default log location */ +#define DEFAULT_LOGPREFIX "/opt/debrix/var/log/Xorg." + +/* Default module search path */ +#define DEFAULT_MODULE_PATH "/opt/debrix/lib/xorg/modules" + +/* Support DGA extension */ +#define DGA 1 + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Use libdl-based loader */ +#define DLOPEN_SUPPORT 1 + +/* Build DPMS extension */ +#define DPMSExtension 1 + +/* Built-in output drivers (none) */ +#define DRIVERS {} + +/* Build Extended-Visual-Information extension */ +#define EVI 1 + +/* Build FontCache extension */ +/* #undef FONTCACHE */ + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* Cygwin has /dev/windows for signaling new win32 messages */ +/* #undef HAS_DEVWINDOWS */ + +/* Have the `getdtablesize' function. */ +#define HAS_GETDTABLESIZE 1 + +/* Have the `getifaddrs' function. */ +#define HAS_GETIFADDRS 1 + +/* Have the `getpeereid' function. */ +/* #undef HAS_GETPEEREID */ + +/* Have the `getpeerucred' function. */ +/* #undef HAS_GETPEERUCRED */ + +/* Define to 1 if NetBSD built-in MTRR support is available */ +/* #undef HAS_MTRR_BUILTIN */ + +/* Define to 1 if BSD MTRR support is available */ +/* #undef HAS_MTRR_SUPPORT */ + +/* Support SHM */ +#define HAS_SHM 1 + +/* Use Windows sockets */ +/* #undef HAS_WINSOCK */ + +/* Define to 1 if you have `alloca', as a function or macro. */ +#define HAVE_ALLOCA 1 + +/* Define to 1 if you have and it should be used (not on Ultrix). + */ +#define HAVE_ALLOCA_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_ASM_MTRR_H */ + +/* Define to 1 if you have the `authdes_create' function. */ +#define HAVE_AUTHDES_CREATE 1 + +/* Define to 1 if you have the `authdes_seccreate' function. */ +/* #undef HAVE_AUTHDES_SECCREATE */ + +/* Has backtrace support */ +#define HAVE_BACKTRACE 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +#define HAVE_DIRENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you don't have `vprintf' but do have `_doprnt.' */ +/* #undef HAVE_DOPRNT */ + +/* Define to 1 if you have the header file. */ +#define HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `geteuid' function. */ +#define HAVE_GETEUID 1 + +/* Define to 1 if you have the `getopt' function. */ +#define HAVE_GETOPT 1 + +/* Define to 1 if you have the `getopt_long' function. */ +#define HAVE_GETOPT_LONG 1 + +/* Define to 1 if you have the `getuid' function. */ +#define HAVE_GETUID 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `m' library (-lm). */ +#define HAVE_LIBM 1 + +/* Define to 1 if you have the `link' function. */ +#define HAVE_LINK 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_AGPGART_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APM_BIOS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_FB_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_MACHINE_MTRR_H */ + +/* Define to 1 if you have the `memmove' function. */ +#define HAVE_MEMMOVE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have the `memset' function. */ +#define HAVE_MEMSET 1 + +/* Define to 1 if you have the `mkstemp' function. */ +#define HAVE_MKSTEMP 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_NDBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. */ +/* #undef HAVE_NDIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_RPCSVC_DBM_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the `strchr' function. */ +#define HAVE_STRCHR 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the `strrchr' function. */ +#define HAVE_STRRCHR 1 + +/* Define to 1 if you have the `strtol' function. */ +#define HAVE_STRTOL 1 + +/* Define to 1 if SYSV IPC is available */ +/* #undef HAVE_SYSV_IPC */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_AGPIO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_DIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_IO_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_MEMRANGE_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_NDIR_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_VM86_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to 1 if you have the `vprintf' function. */ +#define HAVE_VPRINTF 1 + +/* Define to 1 if you have the `vsnprintf' function. */ +#define HAVE_VSNPRINTF 1 + +/* Define to 1 if you have the `walkcontext' function. */ +/* #undef HAVE_WALKCONTEXT */ + +/* Built-in input drivers (none) */ +#define IDRIVERS {} + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Support LBX extension */ +#define LBX 1 + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM extension */ +#define MITSHM 1 + +/* Build Multibuffer extension */ +/* #undef MULTIBUFFER */ + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Need XFree86 helper functions */ +#define NEED_XF86_PROTOTYPES 1 + +/* Need XFree86 typedefs */ +#define NEED_XF86_TYPES 1 + +/* Operating System Name */ +#define OSNAME "Linux 2.6.15-rc6-gdf7addbb ia64" + +/* Operating System Vendor */ +#define OSVENDOR "" + +/* Name of package */ +#define PACKAGE "xorg-server" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "https://bugs.freedesktop.org/enter_bug.cgi?product=xorg" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "xorg-server" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "xorg-server 1.0.1" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "xorg-server" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "1.0.1" + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PCVT console */ +/* #undef PCVT_SUPPORT */ + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Overall prefix */ +#define PROJECTROOT "/opt/debrix" + +/* Support RANDR extension */ +#define RANDR 1 + +/* Make PROJECT_ROOT relative to the xserver location */ +/* #undef RELOCATE_PROJECTROOT */ + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Define as the return type of signal handlers (`int' or `void'). */ +/* #undef RETSIGTYPE */ + +/* Default RGB path */ +#define RGB_DB "/opt/debrix/share/X11/rgb" + +/* Build Rootless code */ +/* #undef ROOTLESS */ + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Support Secure RPC ("SUN-DES-1") authentication for X11 clients */ +#define SECURE_RPC 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* The size of a `unsigned long', as computed by sizeof. */ +#define SIZEOF_UNSIGNED_LONG 8 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ +/* #undef STACK_DIRECTION */ + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Build TOG-CUP extension */ +#define TOGCUP 1 + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* NetBSD PIO alpha IO */ +/* #undef USE_ALPHA_PIO */ + +/* BSD AMD64 iopl */ +/* #undef USE_AMD64_IOPL */ + +/* BSD /dev/io */ +/* #undef USE_DEV_IO */ + +/* BSD i386 iopl */ +/* #undef USE_I386_IOPL */ + +/* Use built-in RGB color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* Version number of package */ +#define VERSION "1.0.1" + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +/* Build APPGROUP extension */ +#define XAPPGROUP 1 + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Build Security extension */ +#define XCSECURITY 1 + +/* Support XDM Control Protocol */ +#define XDMCP 1 + +/* Build XEvIE extension */ +#define XEVIE 1 + +/* Build XFree86 BigFont extension */ +#define XF86BIGFONT 1 + +/* Name of configuration file */ +#define XF86CONFIGFILE "xorg.conf" + +/* Build DRI extension */ +#define XF86DRI 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Support XFixes extension */ +#define XFIXES 1 + +/* Building XFree86 server */ +#define XFree86Server 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Path to XKB data */ +#define XKB_BASE_DIRECTORY "/opt/debrix/share/X11/xkb" + +/* Path to XKB bin dir */ +#define XKB_BIN_DIRECTORY "/opt/debrix/bin" + +/* Disable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Path to XKB output dir */ +#define XKM_OUTPUT_DIR "/opt/debrix/share/X11/xkb/compiled/" + +/* Building Xorg server */ +#define XORGSERVER 1 + +/* Vendor release */ +#define XORG_DATE "21 December 2005" + +/* Vendor man version */ +#define XORG_MAN_VERSION "Version 7.0" + +/* Vendor release */ +#define XORG_RELEASE "Release 7.0" + +/* Building Xorg server */ +#define XORG_SERVER 1 + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((0) * 100000) + ((0) * 1000) + 0) + +/* Build Print extension */ +#define XPRINT 1 + +/* Support Record extension */ +#define XRECORD 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv extension */ +#define XV 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Short vendor name */ +#define XVENDORNAMESHORT "X.Org" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* Build Xv extension */ +#define XvExtension 1 + +/* Build XvMC extension */ +#define XvMCExtension 1 + +/* Define to 1 if `lex' declares `yytext' as a `char *' by default, not a + `char[]'. */ +#define YYTEXT_POINTER 1 + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 + +/* Define to 1 if unsigned long is 64 bits. */ +#define _XSERVER64 1 + +/* Solaris 8 or later */ +/* #undef __SOL8__ */ + +/* Vendor web address for support */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Name of configuration file */ +#define __XCONFIGFILE__ "xorg.conf" + +/* Default XKB rules */ +#define __XKBDEFRULES__ "xorg" + +/* Name of X server */ +#define __XSERVERNAME__ "Xorg" + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ + +/* Define to `int' if does not define. */ +/* #undef pid_t */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dpmsproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dpmsproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dpmsproc.h (revision 51223) @@ -0,0 +1,16 @@ +/* $XFree86: xc/programs/Xserver/Xext/dpmsproc.h,v 1.3 2001/10/28 03:32:50 tsi Exp $ */ + +/* Prototypes for functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DPMSPROC_H_ +#define _DPMSPROC_H_ + +void DPMSSet(int level); +int DPMSGet(int *plevel); +Bool DPMSSupported(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dri.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dri.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dri.h (revision 51223) @@ -0,0 +1,129 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/dri.h,v 1.18 2001/03/21 16:21:40 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright (c) 2002 Apple Computer, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Jens Owen + * + */ + +/* Prototypes for AppleDRI functions */ + +#ifndef _DRI_H_ +#define _DRI_H_ + +#include +#include "scrnintstr.h" +#define _APPLEDRI_SERVER_ +#include "appledri.h" +#include "Xplugin.h" + +typedef void (*ClipNotifyPtr)( WindowPtr, int, int ); + + +/* + * These functions can be wrapped by the DRI. Each of these have + * generic default funcs (initialized in DRICreateInfoRec) and can be + * overridden by the driver in its [driver]DRIScreenInit function. + */ +typedef struct { + WindowExposuresProcPtr WindowExposures; + CopyWindowProcPtr CopyWindow; + ValidateTreeProcPtr ValidateTree; + PostValidateTreeProcPtr PostValidateTree; + ClipNotifyProcPtr ClipNotify; +} DRIWrappedFuncsRec, *DRIWrappedFuncsPtr; + +typedef struct { + xp_surface_id id; + int kind; +} DRISurfaceNotifyArg; + +extern Bool DRIScreenInit(ScreenPtr pScreen); + +extern Bool DRIFinishScreenInit(ScreenPtr pScreen); + +extern void DRICloseScreen(ScreenPtr pScreen); + +extern Bool DRIExtensionInit(void); + +extern void DRIReset(void); + +extern Bool DRIQueryDirectRenderingCapable(ScreenPtr pScreen, + Bool *isCapable); + +extern Bool DRIAuthConnection(ScreenPtr pScreen, unsigned int magic); + +extern Bool DRICreateSurface(ScreenPtr pScreen, + Drawable id, + DrawablePtr pDrawable, + xp_client_id client_id, + xp_surface_id *surface_id, + unsigned int key[2], + void (*notify) (void *arg, void *data), + void *notify_data); + +extern Bool DRIDestroySurface(ScreenPtr pScreen, + Drawable id, + DrawablePtr pDrawable, + void (*notify) (void *arg, void *data), + void *notify_data); + +extern Bool DRIDrawablePrivDelete(pointer pResource, + XID id); + +extern DRIWrappedFuncsRec *DRIGetWrappedFuncs(ScreenPtr pScreen); + +extern void DRICopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +extern int DRIValidateTree(WindowPtr pParent, + WindowPtr pChild, + VTKind kind); + +extern void DRIPostValidateTree(WindowPtr pParent, + WindowPtr pChild, + VTKind kind); + +extern void DRIClipNotify(WindowPtr pWin, + int dx, + int dy); + +extern void DRIWindowExposures(WindowPtr pWin, + RegionPtr prgn, + RegionPtr bsreg); + +extern void DRISurfaceNotify (xp_surface_id id, int kind); + +extern void DRIQueryVersion(int *majorVersion, + int *minorVersion, + int *patchVersion); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dristruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dristruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dristruct.h (revision 51223) @@ -0,0 +1,82 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/dristruct.h,v 1.10 2001/03/21 16:21:40 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright (c) 2002 Apple Computer, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Jens Owen + * + */ + +#ifndef DRI_STRUCT_H +#define DRI_STRUCT_H + +#include "dri.h" +#include "x-list.h" + +#define DRI_MAX_DRAWABLES 256 + +#define DRI_DRAWABLE_PRIV_FROM_WINDOW(pWin) \ + ((DRIWindowPrivIndex < 0) ? \ + NULL : \ + ((DRIDrawablePrivPtr)((pWin)->devPrivates[DRIWindowPrivIndex].ptr))) + +#define DRI_DRAWABLE_PRIV_FROM_PIXMAP(pPix) \ + ((DRIPixmapPrivIndex < 0) ? \ + NULL : \ + ((DRIDrawablePrivPtr)((pPix)->devPrivates[DRIPixmapPrivIndex].ptr))) + +typedef struct _DRIDrawablePrivRec +{ + xp_surface_id sid; + int drawableIndex; + DrawablePtr pDraw; + ScreenPtr pScreen; + int refCount; + unsigned int key[2]; + x_list *notifiers; /* list of (FUN . DATA) */ +} DRIDrawablePrivRec, *DRIDrawablePrivPtr; + +#define DRI_SCREEN_PRIV(pScreen) \ + ((DRIScreenPrivIndex < 0) ? \ + NULL : \ + ((DRIScreenPrivPtr)((pScreen)->devPrivates[DRIScreenPrivIndex].ptr))) + +#define DRI_SCREEN_PRIV_FROM_INDEX(screenIndex) ((DRIScreenPrivPtr) \ + (screenInfo.screens[screenIndex]->devPrivates[DRIScreenPrivIndex].ptr)) + + +typedef struct _DRIScreenPrivRec +{ + Bool directRenderingSupport; + int nrWindows; + DRIWrappedFuncsRec wrap; + DrawablePtr DRIDrawables[DRI_MAX_DRAWABLES]; +} DRIScreenPrivRec, *DRIScreenPrivPtr; + +#endif /* DRI_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dummylib.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dummylib.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/dummylib.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/dummylib/dummylib.h,v 1.1 2000/02/13 03:06:38 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _DUMMY_LIB_H +#define _DUMMY_LIB_H + +#endif /* _DUMMY_LIB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/e8870PCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/e8870PCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/e8870PCI.h (revision 51223) @@ -0,0 +1,42 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/e8870PCI.h,v 1.1 2003/02/23 20:26:49 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_E8870_H +#define PCI_E8870_H 1 + +#include +#include + +Bool xorgProbeE8870(scanpciWrapperOpt flags); +void xf86PreScanE8870(void); +void xf86PostScanE8870(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/edid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/edid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/edid.h (revision 51223) @@ -0,0 +1,463 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/edid.h,v 1.6 2000/04/17 16:29:55 eich Exp $ */ + +/* edid.h: defines to parse an EDID block + * + * This file contains all information to interpret a standard EDIC block + * transmitted by a display device via DDC (Display Data Channel). So far + * there is no information to deal with optional EDID blocks. + * DDC is a Trademark of VESA (Video Electronics Standard Association). + * + * Copyright 1998 by Egbert Eich + */ + +#ifndef _EDID_H_ +#define _EDID_H_ + +#include "vdif.h" + +/* read complete EDID record */ +#define EDID1_LEN 128 +#define BITS_PER_BYTE 9 +#define NUM BITS_PER_BYTE*EDID1_LEN +#define HEADER 6 + +#define STD_TIMINGS 8 +#define DET_TIMINGS 4 + +#ifdef _PARSE_EDID_ + +/* header: 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 */ +#define HEADER_SECTION 0 +#define HEADER_LENGTH 8 + +/* vendor section */ +#define VENDOR_SECTION (HEADER_SECTION + HEADER_LENGTH) +#define V_MANUFACTURER 0 +#define V_PROD_ID (V_MANUFACTURER + 2) +#define V_SERIAL (V_PROD_ID + 2) +#define V_WEEK (V_SERIAL + 4) +#define V_YEAR (V_WEEK + 1) +#define VENDOR_LENGTH (V_YEAR + 1) + +/* EDID version */ +#define VERSION_SECTION (VENDOR_SECTION + VENDOR_LENGTH) +#define V_VERSION 0 +#define V_REVISION (V_VERSION + 1) +#define VERSION_LENGTH (V_REVISION + 1) + +/* display information */ +#define DISPLAY_SECTION (VERSION_SECTION + VERSION_LENGTH) +#define D_INPUT 0 +#define D_HSIZE (D_INPUT + 1) +#define D_VSIZE (D_HSIZE + 1) +#define D_GAMMA (D_VSIZE + 1) +#define FEAT_S (D_GAMMA + 1) +#define D_RG_LOW (FEAT_S + 1) +#define D_BW_LOW (D_RG_LOW + 1) +#define D_REDX (D_BW_LOW + 1) +#define D_REDY (D_REDX + 1) +#define D_GREENX (D_REDY + 1) +#define D_GREENY (D_GREENX + 1) +#define D_BLUEX (D_GREENY + 1) +#define D_BLUEY (D_BLUEX + 1) +#define D_WHITEX (D_BLUEY + 1) +#define D_WHITEY (D_WHITEX + 1) +#define DISPLAY_LENGTH (D_WHITEY + 1) + +/* supported VESA and other standard timings */ +#define ESTABLISHED_TIMING_SECTION (DISPLAY_SECTION + DISPLAY_LENGTH) +#define E_T1 0 +#define E_T2 (E_T1 + 1) +#define E_TMANU (E_T2 + 1) +#define E_TIMING_LENGTH (E_TMANU + 1) + +/* non predefined standard timings supported by display */ +#define STD_TIMING_SECTION (ESTABLISHED_TIMING_SECTION + E_TIMING_LENGTH) +#define STD_TIMING_INFO_LEN 2 +#define STD_TIMING_INFO_NUM STD_TIMINGS +#define STD_TIMING_LENGTH (STD_TIMING_INFO_LEN * STD_TIMING_INFO_NUM) + +/* detailed timing info of non standard timings */ +#define DET_TIMING_SECTION (STD_TIMING_SECTION + STD_TIMING_LENGTH) +#define DET_TIMING_INFO_LEN 18 +#define MONITOR_DESC_LEN DET_TIMING_INFO_LEN +#define DET_TIMING_INFO_NUM DET_TIMINGS +#define DET_TIMING_LENGTH (DET_TIMING_INFO_LEN * DET_TIMING_INFO_NUM) + +/* number of EDID sections to follow */ +#define NO_EDID (DET_TIMING_SECTION + DET_TIMING_LENGTH) +/* one byte checksum */ +#define CHECKSUM (NO_EDID + 1) + +#if (CHECKSUM != (EDID1_LEN - 1)) +# error "EDID1 length != 128!" +#endif + + +#define SECTION(x,y) (Uchar *)(x + y) +#define GET_ARRAY(y) ((Uchar *)(c + y)) +#define GET(y) *(Uchar *)(c + y) + +/* extract information from vendor section */ +#define _PROD_ID(x) x[0] + (x[1] << 8); +#define PROD_ID _PROD_ID(GET_ARRAY(V_PROD_ID)) +#define _SERIAL_NO(x) x[0] + (x[1] << 8) + (x[2] << 16) + (x[3] << 24) +#define SERIAL_NO _SERIAL_NO(GET_ARRAY(V_SERIAL)) +#define _YEAR(x) (x & 0xFF) + 1990 +#define YEAR _YEAR(GET(V_YEAR)) +#define WEEK GET(V_WEEK) & 0xFF +#define _L1(x) ((x[0] & 0x7C) >> 2) + '@' +#define _L2(x) ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@' +#define _L3(x) (x[1] & 0x1F) + '@'; +#define L1 _L1(GET_ARRAY(V_MANUFACTURER)) +#define L2 _L2(GET_ARRAY(V_MANUFACTURER)) +#define L3 _L3(GET_ARRAY(V_MANUFACTURER)) + +/* extract information from version section */ +#define VERSION GET(V_VERSION) +#define REVISION GET(V_REVISION) + +/* extract information from display section */ +#define _INPUT_TYPE(x) ((x & 0x80) >> 7) +#define INPUT_TYPE _INPUT_TYPE(GET(D_INPUT)) +#define _INPUT_VOLTAGE(x) ((x & 0x60) >> 5) +#define INPUT_VOLTAGE _INPUT_VOLTAGE(GET(D_INPUT)) +#define _SETUP(x) ((x & 0x10) >> 4) +#define SETUP _SETUP(GET(D_INPUT)) +#define _SYNC(x) (x & 0x0F) +#define SYNC _SYNC(GET(D_INPUT)) +#define _DFP(x) (x & 0x01) +#define DFP _DFP(GET(D_INPUT)) +#define _GAMMA(x) (x == 0xff ? 1.0 : ((x + 100.0)/100.0)) +#define GAMMA _GAMMA(GET(D_GAMMA)) +#define HSIZE_MAX GET(D_HSIZE) +#define VSIZE_MAX GET(D_VSIZE) +#define _DPMS(x) ((x & 0xE0) >> 5) +#define DPMS _DPMS(GET(FEAT_S)) +#define _DISPLAY_TYPE(x) ((x & 0x18) >> 3) +#define DISPLAY_TYPE _DISPLAY_TYPE(GET(FEAT_S)) +#define _MSC(x) (x & 0x7) +#define MSC _MSC(GET(FEAT_S)) + + +/* color characteristics */ +#define CC_L(x,y) ((x & (0x03 << y)) >> y) +#define CC_H(x) (x << 2) +#define I_CC(x,y,z) CC_H(y) | CC_L(x,z) +#define F_CC(x) ((x)/1024.0) +#define REDX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDX)),6)) +#define REDY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDY)),4)) +#define GREENX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENX)),2)) +#define GREENY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENY)),0)) +#define BLUEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEX)),6)) +#define BLUEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEY)),4)) +#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2)) +#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0)) + +/* extract information from standard timing section */ +#define T1 GET(E_T1) +#define T2 GET(E_T2) +#define T_MANU GET(E_TMANU) + +/* extract information from estabished timing section */ +#define _VALID_TIMING(x) !(((x[0] == 0x01) && (x[1] == 0x01)) \ + || ((x[0] == 0x00) && (x[1] == 0x00)) \ + || ((x[0] == 0x20) && (x[1] == 0x20)) ) +#define VALID_TIMING _VALID_TIMING(c) +#define _HSIZE1(x) ((x[0] + 31) * 8) +#define HSIZE1 _HSIZE1(c) +#define RATIO(x) ((x[1] & 0xC0) >> 6) +#define RATIO1_1 0 +/* EDID Ver. 1.3 redefined this */ +#define RATIO16_10 RATIO1_1 +#define RATIO4_3 1 +#define RATIO5_4 2 +#define RATIO16_9 3 +#define _VSIZE1(x,y,r) switch(RATIO(x)){ \ + case RATIO1_1: y = ((v->version > 1 || v->revision > 2) \ + ? (_HSIZE1(x) * 10) / 16 : _HSIZE1(x)); break; \ + case RATIO4_3: y = _HSIZE1(x) * 3 / 4; break; \ + case RATIO5_4: y = _HSIZE1(x) * 4 / 5; break; \ + case RATIO16_9: y = _HSIZE1(x) * 9 / 16; break; \ + } +#define VSIZE1(x) _VSIZE1(c,x,v) +#define _REFRESH_R(x) (x[1] & 0x3F) + 60 +#define REFRESH_R _REFRESH_R(c) +#define _ID_LOW(x) x[0] +#define ID_LOW _ID_LOW(c) +#define _ID_HIGH(x) (x[1] << 8) +#define ID_HIGH _ID_HIGH(c) +#define STD_TIMING_ID (ID_LOW | ID_HIGH) +#define _NEXT_STD_TIMING(x) (x = (x + STD_TIMING_INFO_LEN)) +#define NEXT_STD_TIMING _NEXT_STD_TIMING(c) + + +/* EDID Ver. >= 1.2 */ +#define _IS_MONITOR_DESC(x) (x[0] == 0 && x[1] == 0 && x[2] == 0 && x[4] == 0) +#define IS_MONITOR_DESC _IS_MONITOR_DESC(c) +#define _PIXEL_CLOCK(x) (x[0] + (x[1] << 8)) * 10000 +#define PIXEL_CLOCK _PIXEL_CLOCK(c) +#define _H_ACTIVE(x) (x[2] + ((x[4] & 0xF0) << 4)) +#define H_ACTIVE _H_ACTIVE(c) +#define _H_BLANK(x) (x[3] + ((x[4] & 0x0F) << 8)) +#define H_BLANK _H_BLANK(c) +#define _V_ACTIVE(x) (x[5] + ((x[7] & 0xF0) << 4)) +#define V_ACTIVE _V_ACTIVE(c) +#define _V_BLANK(x) (x[6] + ((x[7] & 0x0F) << 8)) +#define V_BLANK _V_BLANK(c) +#define _H_SYNC_OFF(x) (x[8] + ((x[11] & 0xC0) << 2)) +#define H_SYNC_OFF _H_SYNC_OFF(c) +#define _H_SYNC_WIDTH(x) (x[9] + ((x[11] & 0x30) << 4)) +#define H_SYNC_WIDTH _H_SYNC_WIDTH(c) +#define _V_SYNC_OFF(x) ((x[10] >> 4) + ((x[11] & 0x0C) << 2)) +#define V_SYNC_OFF _V_SYNC_OFF(c) +#define _V_SYNC_WIDTH(x) ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)) +#define V_SYNC_WIDTH _V_SYNC_WIDTH(c) +#define _H_SIZE(x) (x[12] + ((x[14] & 0xF0) << 4)) +#define H_SIZE _H_SIZE(c) +#define _V_SIZE(x) (x[13] + ((x[14] & 0x0F) << 8)) +#define V_SIZE _V_SIZE(c) +#define _H_BORDER(x) (x[15]) +#define H_BORDER _H_BORDER(c) +#define _V_BORDER(x) (x[16]) +#define V_BORDER _V_BORDER(c) +#define _INTERLACED(x) ((x[17] & 0x80) >> 7) +#define INTERLACED _INTERLACED(c) +#define _STEREO(x) ((x[17] & 0x60) >> 5) +#define STEREO _STEREO(c) +#define _STEREO1(x) (x[17] & 0x1) +#define STEREO1 _STEREO(c) +#define _SYNC_T(x) ((x[17] & 0x18) >> 4) +#define SYNC_T _SYNC_T(c) +#define _MISC(x) ((x[17] & 0x06) >> 2) +#define MISC _MISC(c) + +#define _MONITOR_DESC_TYPE(x) x[3] +#define MONITOR_DESC_TYPE _MONITOR_DESC_TYPE(c) +#define SERIAL_NUMBER 0xFF +#define ASCII_STR 0xFE +#define MONITOR_RANGES 0xFD +#define _MIN_V(x) x[5] +#define MIN_V _MIN_V(c) +#define _MAX_V(x) x[6] +#define MAX_V _MAX_V(c) +#define _MIN_H(x) x[7] +#define MIN_H _MIN_H(c) +#define _MAX_H(x) x[8] +#define MAX_H _MAX_H(c) +#define _MAX_CLOCK(x) x[9] +#define MAX_CLOCK _MAX_CLOCK(c) +#define _HAVE_2ND_GTF(x) (x[10] == 0x02) +#define HAVE_2ND_GTF _HAVE_2ND_GTF(c) +#define _F_2ND_GTF(x) (x[12] * 2) +#define F_2ND_GTF _F_2ND_GTF(c) +#define _C_2ND_GTF(x) (x[13] / 2) +#define C_2ND_GTF _C_2ND_GTF(c) +#define _M_2ND_GTF(x) (x[14] + (x[15] << 8)) +#define M_2ND_GTF _M_2ND_GTF(c) +#define _K_2ND_GTF(x) (x[16]) +#define K_2ND_GTF _K_2ND_GTF(c) +#define _J_2ND_GTF(x) (x[17] / 2) +#define J_2ND_GTF _J_2ND_GTF(c) +#define MONITOR_NAME 0xFC +#define ADD_COLOR_POINT 0xFB +#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2)) +#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0)) +#define _WHITEX_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 1)),2)) +#define _WHITEY_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 2)),0)) +#define _WHITE_INDEX1(x) x[5] +#define WHITE_INDEX1 _WHITE_INDEX1(c) +#define _WHITE_INDEX2(x) x[10] +#define WHITE_INDEX2 _WHITE_INDEX2(c) +#define WHITEX1 _WHITEX_ADD(c,6) +#define WHITEY1 _WHITEY_ADD(c,6) +#define WHITEX2 _WHITEX_ADD(c,12) +#define WHITEY2 _WHITEY_ADD(c,12) +#define _WHITE_GAMMA1(x) _GAMMA(x[9]) +#define WHITE_GAMMA1 _WHITE_GAMMA1(c) +#define _WHITE_GAMMA2(x) _GAMMA(x[14]) +#define WHITE_GAMMA2 _WHITE_GAMMA2(c) +#define ADD_STD_TIMINGS 0xFA +#define ADD_DUMMY 0x10 + +#define _NEXT_DT_MD_SECTION(x) (x = (x + DET_TIMING_INFO_LEN)) +#define NEXT_DT_MD_SECTION _NEXT_DT_MD_SECTION(c) + +#endif /* _PARSE_EDID_ */ + +/* input type */ +#define DIGITAL(x) x + +/* DFP */ +#define DFP1(x) x + +/* input voltage level */ +#define V070 0 /* 0.700V/0.300V */ +#define V071 1 /* 0.714V/0.286V */ +#define V100 2 /* 1.000V/0.400V */ +#define V007 3 /* 0.700V/0.000V */ + +/* Signal level setup */ +#define SIG_SETUP(x) (x) + +/* sync characteristics */ +#define SEP_SYNC(x) (x & 0x08) +#define COMP_SYNC(x) (x & 0x04) +#define SYNC_O_GREEN(x) (x & 0x02) +#define SYNC_SERR(x) (x & 0x01) + +/* DPMS features */ +#define DPMS_STANDBY(x) (x & 0x04) +#define DPMS_SUSPEND(x) (x & 0x02) +#define DPMS_OFF(x) (x & 0x01) + +/* display type */ +#define DISP_MONO 0 +#define DISP_RGB 1 +#define DISP_MULTCOLOR 2 + +/* Msc stuff EDID Ver > 1.1 */ +#define STD_COLOR_SPACE(x) (x & 0x4) +#define PREFERRED_TIMING_MODE(x) (x & 0x2) +#define GFT_SUPPORTED(x) (x & 0x1) + +/* detailed timing misc */ +#define IS_INTERLACED(x) (x) +#define IS_STEREO(x) (x) +#define IS_RIGHT_STEREO(x) (x & 0x01) +#define IS_LEFT_STEREO(x) (x & 0x02) +#define IS_4WAY_STEREO(x) (x & 0x03) +#define IS_RIGHT_ON_SYNC(x) IS_RIGHT_STEREO(x) +#define IS_LEFT_ON_SYNC(x) IS_LEFT_STEREO(x) + + +typedef unsigned int Uint; +typedef unsigned char Uchar; + +struct vendor { + char name[4]; + int prod_id; + Uint serial; + int week; + int year; +}; + +struct edid_version { + int version; + int revision; +}; + +struct disp_features { + unsigned int input_type:1; + unsigned int input_voltage:2; + unsigned int input_setup:1; + unsigned int input_sync:5; + unsigned int input_dfp:1; + int hsize; + int vsize; + float gamma; + unsigned int dpms:3; + unsigned int display_type:2; + unsigned int msc:3; + float redx; + float redy; + float greenx; + float greeny; + float bluex; + float bluey; + float whitex; + float whitey; +}; + +struct established_timings { + Uchar t1; + Uchar t2; + Uchar t_manu; +}; + +struct std_timings { + int hsize; + int vsize; + int refresh; + CARD16 id; +}; + +struct detailed_timings { + int clock; + int h_active; + int h_blanking; + int v_active; + int v_blanking; + int h_sync_off; + int h_sync_width; + int v_sync_off; + int v_sync_width; + int h_size; + int v_size; + int h_border; + int v_border; + unsigned int interlaced:1; + unsigned int stereo:2; + unsigned int sync:2; + unsigned int misc:2; + unsigned int stereo_1:1; +}; + +#define DT 0 +#define DS_SERIAL 0xFF +#define DS_ASCII_STR 0xFE +#define DS_NAME 0xFC +#define DS_RANGES 0xFD +#define DS_WHITE_P 0xFB +#define DS_STD_TIMINGS 0xFA +#define DS_DUMMY 0x10 + +struct monitor_ranges { + int min_v; + int max_v; + int min_h; + int max_h; + int max_clock; + int gtf_2nd_f; + int gtf_2nd_c; + int gtf_2nd_m; + int gtf_2nd_k; + int gtf_2nd_j; +}; + +struct whitePoints{ + int index; + float white_x; + float white_y; + float white_gamma; +}; + +struct detailed_monitor_section { + int type; + union { + struct detailed_timings d_timings; + Uchar serial[13]; + Uchar ascii_data[13]; + Uchar name[13]; + struct monitor_ranges ranges; + struct std_timings std_t[5]; + struct whitePoints wp[2]; + } section; +}; + +typedef struct { + int scrnIndex; + struct vendor vendor; + struct edid_version ver; + struct disp_features features; + struct established_timings timings1; + struct std_timings timings2[8]; + struct detailed_monitor_section det_mon[4]; + xf86vdifPtr vdif; + int no_sections; + Uchar *rawData; +} xf86Monitor, *xf86MonPtr; + +extern xf86MonPtr ConfiguredMonitor; + +#endif /* _EDID_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elf.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elf.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elf.h (revision 51223) @@ -0,0 +1,712 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/elf.h,v 1.16 2003/06/12 14:12:34 eich Exp $ */ + +typedef unsigned int Elf32_Addr; +typedef unsigned short Elf32_Half; +typedef unsigned int Elf32_Off; +typedef long Elf32_Sword; +typedef unsigned int Elf32_Word; + +typedef unsigned long Elf64_Addr; +typedef unsigned short Elf64_Half; +typedef unsigned long Elf64_Off; +typedef int Elf64_Sword; +typedef unsigned int Elf64_Word; +typedef unsigned long Elf64_Xword; +typedef long Elf64_Sxword; + +/* These constants are for the segment types stored in the image headers */ +#define PT_NULL 0 +#define PT_LOAD 1 +#define PT_DYNAMIC 2 +#define PT_INTERP 3 +#define PT_NOTE 4 +#define PT_SHLIB 5 +#define PT_PHDR 6 +#define PT_LOPROC 0x70000000 +#define PT_HIPROC 0x7fffffff + +/* These constants define the different elf file types */ +#define ET_NONE 0 +#define ET_REL 1 +#define ET_EXEC 2 +#define ET_DYN 3 +#define ET_CORE 4 +#define ET_LOPROC 5 +#define ET_HIPROC 6 + +/* These constants define the various ELF target machines */ +#define EM_NONE 0 +#define EM_M32 1 +#define EM_SPARC 2 +#define EM_386 3 +#define EM_68K 4 +#define EM_88K 5 +#define EM_486 6 /* Perhaps disused */ +#define EM_860 7 +#define EM_MIPS 8 +#define EM_MIPS_RS4_BE 10 +#define EM_PARISC 15 +#define EM_SPARC32PLUS 18 +#define EM_PPC 20 +#define EM_SPARCV9 43 +#define EM_IA_64 50 +#define EM_ALPHA 0x9026 + +/* This is the info that is needed to parse the dynamic section of the file */ +#define DT_NULL 0 +#define DT_NEEDED 1 +#define DT_PLTRELSZ 2 +#define DT_PLTGOT 3 +#define DT_HASH 4 +#define DT_STRTAB 5 +#define DT_SYMTAB 6 +#define DT_RELA 7 +#define DT_RELASZ 8 +#define DT_RELAENT 9 +#define DT_STRSZ 10 +#define DT_SYMENT 11 +#define DT_INIT 12 +#define DT_FINI 13 +#define DT_SONAME 14 +#define DT_RPATH 15 +#define DT_SYMBOLIC 16 +#define DT_REL 17 +#define DT_RELSZ 18 +#define DT_RELENT 19 +#define DT_PLTREL 20 +#define DT_DEBUG 21 +#define DT_TEXTREL 22 +#define DT_JMPREL 23 +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* This info is needed when parsing the symbol table */ +#define STB_LOCAL 0 +#define STB_GLOBAL 1 +#define STB_WEAK 2 + +#define STT_NOTYPE 0 +#define STT_OBJECT 1 +#define STT_FUNC 2 +#define STT_SECTION 3 +#define STT_FILE 4 +#define STT_LOPROC 13 +#define STT_HIPROC 15 + +#define ELF32_ST_BIND(x) ((x) >> 4) +#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) + +#define ELF64_ST_BIND(x) ELF32_ST_BIND (x) +#define ELF64_ST_TYPE(x) ELF32_ST_TYPE (x) + +typedef struct dynamic32 { + Elf32_Sword d_tag; + union { + Elf32_Sword d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; + +typedef struct dynamic64 { + Elf64_Sxword d_tag; + union { + Elf64_Xword d_val; + Elf64_Addr d_ptr; + } d_un; +} Elf64_Dyn; + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef QNX4 +extern Elf32_Dyn _DYNAMIC[]; +#endif + +/* The following are used with relocations */ +#define ELF32_R_SYM(x) ((x) >> 8) +#define ELF32_R_TYPE(x) ((x) & 0xff) + +#define ELF64_R_SYM(x) ((x) >> 32) +#define ELF64_R_TYPE(x) ((x) & 0xffffffff) + +/* x86 Relocation Types */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +/* AMD64 Relocation Types */ +#define R_X86_64_NONE 0 +#define R_X86_64_64 1 +#define R_X86_64_PC32 2 +#define R_X86_64_GOT32 3 +#define R_X86_64_PLT32 4 +#define R_X86_64_COPY 5 +#define R_X86_64_GLOB_DAT 6 +#define R_X86_64_JUMP_SLOT 7 +#define R_X86_64_RELATIVE 8 +#define R_X86_64_GOTPCREL 9 +#define R_X86_64_32 10 +#define R_X86_64_32S 11 +#define R_X86_64_16 12 +#define R_X86_64_PC16 13 +#define R_X86_64_8 14 +#define R_X86_64_PC8 15 +#define R_X86_64_GNU_VTINHERIT 250 +#define R_X86_64_GNU_VTENTRY 251 + +/* sparc Relocation Types */ +#define R_SPARC_NONE 0 +#define R_SPARC_8 1 +#define R_SPARC_16 2 +#define R_SPARC_32 3 +#define R_SPARC_DISP8 4 +#define R_SPARC_DISP16 5 +#define R_SPARC_DISP32 6 +#define R_SPARC_WDISP30 7 +#define R_SPARC_WDISP22 8 +#define R_SPARC_HI22 9 +#define R_SPARC_22 10 +#define R_SPARC_13 11 +#define R_SPARC_LO10 12 +#define R_SPARC_GOT10 13 +#define R_SPARC_GOT13 14 +#define R_SPARC_GOT22 15 +#define R_SPARC_PC10 16 +#define R_SPARC_PC22 17 +#define R_SPARC_WPLT30 18 +#define R_SPARC_COPY 19 +#define R_SPARC_GLOB_DAT 20 +#define R_SPARC_JMP_SLOT 21 +#define R_SPARC_RELATIVE 22 +#define R_SPARC_UA32 23 +#define R_SPARC_PLT32 24 +#define R_SPARC_HIPLT22 25 +#define R_SPARC_LOPLT10 26 +#define R_SPARC_PCPLT32 27 +#define R_SPARC_PCPLT22 28 +#define R_SPARC_PCPLT10 29 +#define R_SPARC_10 30 +#define R_SPARC_11 31 +#define R_SPARC_64 32 +#define R_SPARC_OLO10 33 +#define R_SPARC_HH22 34 +#define R_SPARC_HM10 35 +#define R_SPARC_LM22 36 +#define R_SPARC_PC_HH22 37 +#define R_SPARC_PC_HM10 38 +#define R_SPARC_PC_LM22 39 +#define R_SPARC_WDISP16 40 +#define R_SPARC_WDISP19 41 +#define R_SPARC_GLOB_JMP 42 +#define R_SPARC_7 43 +#define R_SPARC_5 44 +#define R_SPARC_6 45 +#define R_SPARC_DISP64 46 +#define R_SPARC_PLT64 47 +#define R_SPARC_HIX22 48 +#define R_SPARC_LOX10 49 +#define R_SPARC_H44 50 +#define R_SPARC_M44 51 +#define R_SPARC_L44 52 +#define R_SPARC_REGISTER 53 +#define R_SPARC_UA64 54 +#define R_SPARC_UA16 55 +#define R_SPARC_NUM 56 + +/* m68k Relocation Types */ +#define R_68K_NONE 0 /* No reloc */ +#define R_68K_32 1 /* Direct 32 bit */ +#define R_68K_16 2 /* Direct 16 bit */ +#define R_68K_8 3 /* Direct 8 bit */ +#define R_68K_PC32 4 /* PC relative 32 bit */ +#define R_68K_PC16 5 /* PC relative 16 bit */ +#define R_68K_PC8 6 /* PC relative 8 bit */ +#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ +#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ +#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ +#define R_68K_GOT32O 10 /* 32 bit GOT offset */ +#define R_68K_GOT16O 11 /* 16 bit GOT offset */ +#define R_68K_GOT8O 12 /* 8 bit GOT offset */ +#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ +#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ +#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ +#define R_68K_PLT32O 16 /* 32 bit PLT offset */ +#define R_68K_PLT16O 17 /* 16 bit PLT offset */ +#define R_68K_PLT8O 18 /* 8 bit PLT offset */ +#define R_68K_COPY 19 /* Copy symbol at runtime */ +#define R_68K_GLOB_DAT 20 /* Create GOT entry */ +#define R_68K_JMP_SLOT 21 /* Create PLT entry */ +#define R_68K_RELATIVE 22 /* Adjust by program base */ + +/* Alpha Relocation Types */ +#define R_ALPHA_NONE 0 /* No reloc */ +#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ +#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ +#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ +#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ +#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ +#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ +#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define R_ALPHA_OP_PUSH 12 /* OP stack push */ +#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */ +#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */ +#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */ +#define R_ALPHA_GPVALUE 16 +#define R_ALPHA_GPRELHIGH 17 +#define R_ALPHA_GPRELLOW 18 +#define R_ALPHA_GPREL16 19 +#define R_ALPHA_IMMED_GP_HI32 20 +#define R_ALPHA_IMMED_SCN_HI32 21 +#define R_ALPHA_IMMED_BR_HI32 22 +#define R_ALPHA_IMMED_LO32 23 +#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ +#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ +#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ +#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ +#define R_ALPHA_BRSGP 28 /* Calc displacement for BRS */ + +/* IA-64 relocations. */ +#define R_IA64_NONE 0x00 /* none */ +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ +#define R_IA64_LTV32MSB 0x70 /* symbol + addend, data4 MSB */ +#define R_IA64_LTV32LSB 0x71 /* symbol + addend, data4 LSB */ +#define R_IA64_LTV64MSB 0x72 /* symbol + addend, data8 MSB */ +#define R_IA64_LTV64LSB 0x73 /* symbol + addend, data8 LSB */ +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ + +#define R_IA64_TYPE(R) ((R) & -8) +#define R_IA64_FORMAT(R) ((R) & 7) + +/* + * Apparantly, Linux and PowerMAXOS use different version of ELF as the + * Relocation types are very different. + */ +#if defined(PowerMAX_OS) +/* PPC Relocation Types */ +#define R_PPC_NONE 0 +#define R_PPC_COPY 1 +#define R_PPC_GOTP_ENT 2 +#define R_PPC_8 4 +#define R_PPC_8S 5 +#define R_PPC_16S 7 +#define R_PPC_14 8 +#define R_PPC_DISP14 9 +#define R_PPC_24 10 +#define R_PPC_DISP24 11 +#define R_PPC_PLT_DISP24 14 +#define R_PPC_BBASED_16HU 15 +#define R_PPC_BBASED_32 16 +#define R_PPC_BBASED_32UA 17 +#define R_PPC_BBASED_16H 18 +#define R_PPC_BBASED_16L 19 +#define R_PPC_ABDIFF_16HU 23 +#define R_PPC_ABDIFF_32 24 +#define R_PPC_ABDIFF_32UA 25 +#define R_PPC_ABDIFF_16H 26 +#define R_PPC_ABDIFF_16L 27 +#define R_PPC_ABDIFF_16 28 +#define R_PPC_16HU 31 +#define R_PPC_32 32 +#define R_PPC_32UA 33 +#define R_PPC_16H 34 +#define R_PPC_16L 35 +#define R_PPC_16 36 +#define R_PPC_GOT_16HU 39 +#define R_PPC_GOT_32 40 +#define R_PPC_GOT_32UA 41 +#define R_PPC_GOT_16H 42 +#define R_PPC_GOT_16L 43 +#define R_PPC_GOT_16 44 +#define R_PPC_GOTP_16HU 47 +#define R_PPC_GOTP_32 48 +#define R_PPC_GOTP_32UA 49 +#define R_PPC_GOTP_16H 50 +#define R_PPC_GOTP_16L 51 +#define R_PPC_GOTP_16 52 +#define R_PPC_PLT_16HU 55 +#define R_PPC_PLT_32 56 +#define R_PPC_PLT_32UA 57 +#define R_PPC_PLT_16H 58 +#define R_PPC_PLT_16L 59 +#define R_PPC_PLT_16 60 +#define R_PPC_ABREL_16HU 63 +#define R_PPC_ABREL_32 64 +#define R_PPC_ABREL_32UA 65 +#define R_PPC_ABREL_16H 66 +#define R_PPC_ABREL_16L 67 +#define R_PPC_ABREL_16 68 +#define R_PPC_GOT_ABREL_16HU 71 +#define R_PPC_GOT_ABREL_32 72 +#define R_PPC_GOT_ABREL_32UA 73 +#define R_PPC_GOT_ABREL_16H 74 +#define R_PPC_GOT_ABREL_16L 75 +#define R_PPC_GOT_ABREL_16 76 +#define R_PPC_GOTP_ABREL_16HU 79 +#define R_PPC_GOTP_ABREL_32 80 +#define R_PPC_GOTP_ABREL_32UA 81 +#define R_PPC_GOTP_ABREL_16H 82 +#define R_PPC_GOTP_ABREL_16L 83 +#define R_PPC_GOTP_ABREL_16 84 +#define R_PPC_PLT_ABREL_16HU 87 +#define R_PPC_PLT_ABREL_32 88 +#define R_PPC_PLT_ABREL_32UA 89 +#define R_PPC_PLT_ABREL_16H 90 +#define R_PPC_PLT_ABREL_16L 91 +#define R_PPC_PLT_ABREL_16 92 +#define R_PPC_SREL_16HU 95 +#define R_PPC_SREL_32 96 +#define R_PPC_SREL_32UA 97 +#define R_PPC_SREL_16H 98 +#define R_PPC_SREL_16L 99 +#else +/* + * The Linux version + */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 +#define R_PPC_ADDR24 2 +#define R_PPC_ADDR16 3 +#define R_PPC_ADDR16_LO 4 +#define R_PPC_ADDR16_HI 5 +#define R_PPC_ADDR16_HA 6 +#define R_PPC_ADDR14 7 +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 +#define R_PPC_REL14 11 +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +#endif + +/* ARM relocs. */ +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_PC24 1 /* PC relative 26 bit branch */ +#define R_ARM_ABS32 2 /* Direct 32 bit */ +#define R_ARM_REL32 3 /* PC relative 32 bit */ +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 /* Direct 16 bit */ +#define R_ARM_ABS12 6 /* Direct 12 bit */ +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 /* Direct 8 bit */ +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 +#define R_ARM_COPY 20 /* Copy symbol at runtime */ +#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ +#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ +#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ +#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ +#define R_ARM_GOT32 26 /* 32 bit GOT entry */ +#define R_ARM_PLT32 27 /* 32 bit PLT address */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ +#define R_ARM_THM_PC9 103 /* thumb conditional branch */ +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS22 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + +typedef struct elf32_rel { + Elf32_Addr r_offset; + Elf32_Word r_info; +} Elf32_Rel; + +typedef struct elf64_rel { + Elf64_Addr r_offset; + Elf64_Xword r_info; +} Elf64_Rel; + +typedef struct elf32_rela { + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; +} Elf32_Rela; + +typedef struct elf64_rela { + Elf64_Addr r_offset; + Elf64_Xword r_info; + Elf64_Sxword r_addend; +} Elf64_Rela; + +typedef struct elf32_sym { + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_Sym; + +typedef struct elf64_sym { + Elf64_Word st_name; + unsigned char st_info; + unsigned char st_other; + Elf64_Half st_shndx; + Elf64_Addr st_value; + Elf64_Xword st_size; +} Elf64_Sym; + +#define EI_NIDENT 16 + +typedef struct elf32hdr { + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; /* Entry point */ + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; +} Elf32_Ehdr; + +typedef struct elf64hdr { + unsigned char e_ident[EI_NIDENT]; + Elf64_Half e_type; + Elf64_Half e_machine; + Elf64_Word e_version; + Elf64_Addr e_entry; + Elf64_Off e_phoff; + Elf64_Off e_shoff; + Elf64_Word e_flags; + Elf64_Half e_ehsize; + Elf64_Half e_phentsize; + Elf64_Half e_phnum; + Elf64_Half e_shentsize; + Elf64_Half e_shnum; + Elf64_Half e_shstrndx; +} Elf64_Ehdr; + +/* These constants define the permissions on sections in the program + header, p_flags. */ +#define PF_R 0x4 +#define PF_W 0x2 +#define PF_X 0x1 + +typedef struct elf_phdr { + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; +} Elf32_Phdr; + +typedef struct { + Elf64_Word p_type; + Elf64_Word p_flags; + Elf64_Off p_offset; + Elf64_Addr p_vaddr; + Elf64_Addr p_paddr; + Elf64_Xword p_filesz; + Elf64_Xword p_memsz; + Elf64_Xword p_align; +} Elf64_Phdr; + +/* sh_type */ +#define SHT_NULL 0 +#define SHT_PROGBITS 1 +#define SHT_SYMTAB 2 +#define SHT_STRTAB 3 +#define SHT_RELA 4 +#define SHT_HASH 5 +#define SHT_DYNAMIC 6 +#define SHT_NOTE 7 +#define SHT_NOBITS 8 +#define SHT_REL 9 +#define SHT_SHLIB 10 +#define SHT_DYNSYM 11 +#define SHT_NUM 12 +#define SHT_LOPROC 0x70000000 +#define SHT_HIPROC 0x7fffffff +#define SHT_LOUSER 0x80000000 +#define SHT_HIUSER 0xffffffff + +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* sh_flags */ +#define SHF_WRITE 0x1 +#define SHF_ALLOC 0x2 +#define SHF_EXECINSTR 0x4 +#define SHF_MASKPROC 0xf0000000 + +/* special section indexes */ +#define SHN_UNDEF 0 +#define SHN_LORESERVE 0xff00 +#define SHN_LOPROC 0xff00 +#define SHN_HIPROC 0xff1f +#define SHN_ABS 0xfff1 +#define SHN_COMMON 0xfff2 +#define SHN_HIRESERVE 0xffff + +typedef struct { + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +} Elf32_Shdr; + +typedef struct { + Elf64_Word sh_name; + Elf64_Word sh_type; + Elf64_Xword sh_flags; + Elf64_Addr sh_addr; + Elf64_Off sh_offset; + Elf64_Xword sh_size; + Elf64_Word sh_link; + Elf64_Word sh_info; + Elf64_Xword sh_addralign; + Elf64_Xword sh_entsize; +} Elf64_Shdr; + +#define EI_MAG0 0 /* e_ident[] indexes */ +#define EI_MAG1 1 +#define EI_MAG2 2 +#define EI_MAG3 3 +#define EI_CLASS 4 +#define EI_DATA 5 +#define EI_VERSION 6 +#define EI_PAD 7 + +#define ELFMAG0 0x7f /* EI_MAG */ +#define ELFMAG1 'E' +#define ELFMAG2 'L' +#define ELFMAG3 'F' +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define ELFDLMAG 3 +#define ELFDLOFF 16 + +#define ELFCLASSNONE 0 /* EI_CLASS */ +#define ELFCLASS32 1 +#define ELFCLASS64 2 +#define ELFCLASSNUM 3 + +#define ELFDATANONE 0 /* e_ident[EI_DATA] */ +#define ELFDATA2LSB 1 +#define ELFDATA2MSB 2 + +#define EV_NONE 0 /* e_version, EI_VERSION */ +#define EV_CURRENT 1 +#define EV_NUM 2 + +/* Notes used in ET_CORE */ +#define NT_PRSTATUS 1 +#define NT_PRFPREG 2 +#define NT_PRPSINFO 3 +#define NT_TASKSTRUCT 4 + +/* Note header in a PT_NOTE section */ +typedef struct elf_note { + Elf32_Word n_namesz; /* Name size */ + Elf32_Word n_descsz; /* Content size */ + Elf32_Word n_type; /* Content type */ +} Elf32_Nhdr; + +#define ELF_START_MMAP 0x80000000 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elfloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elfloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/elfloader.h (revision 51223) @@ -0,0 +1,38 @@ +/* + * + * Copyright 1997,1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/elfloader.h,v 1.3 1998/09/20 14:41:05 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _ELFLOADER_H +#define _ELFLOADER_H +/* elfloader.c */ +extern void *ELFLoadModule(loaderPtr, int, LOOKUP **); +extern void ELFResolveSymbols(void *); +extern int ELFCheckForUnresolved(void *); +extern char *ELFAddressToSection(void *, unsigned long); +extern void ELFUnloadModule(void *); +#endif /* _ELFLOADER_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exa.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exa.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exa.h (revision 51223) @@ -0,0 +1,265 @@ +/* + * + * Copyright (C) 2000 Keith Packard + * 2004 Eric Anholt + * 2005 Zack Rusin + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of copyright holders not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Copyright holders make no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + */ +#ifndef EXA_H +#define EXA_H + +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "windowstr.h" +#include "gcstruct.h" +#include "picturestr.h" + +#define EXA_VERSION_MAJOR 0 +#define EXA_VERSION_MINOR 2 +#define EXA_VERSION_RELEASE 0 + +typedef struct _ExaOffscreenArea ExaOffscreenArea; + +typedef void (*ExaOffscreenSaveProc) (ScreenPtr pScreen, ExaOffscreenArea *area); + +typedef enum _ExaOffscreenState { + ExaOffscreenAvail, + ExaOffscreenRemovable, + ExaOffscreenLocked +} ExaOffscreenState; + +struct _ExaOffscreenArea { + int base_offset; /* allocation base */ + int offset; /* aligned offset */ + int size; /* total allocation size */ + int score; + pointer privData; + + ExaOffscreenSaveProc save; + + ExaOffscreenState state; + + ExaOffscreenArea *next; +}; + +typedef struct _ExaCardInfo { + /* These are here because I don't want to be adding more to + * ScrnInfoRec */ + CARD8 *memoryBase; + unsigned long offScreenBase; + + /* It's fix.smem_len. + This one could be potentially substituted by ScrnInfoRec + videoRam member, but I do not want to be doing the silly + << 10, >>10 all over the place */ + unsigned long memorySize; + + int pixmapOffsetAlign; + int pixmapPitchAlign; + int flags; + + /* The coordinate limitations for rendering for this hardware. + * Exa breaks larger pixmaps into smaller pieces and calls Prepare multiple times + * to handle larger pixmaps + */ + int maxX; + int maxY; + + /* private */ + ExaOffscreenArea *offScreenAreas; + Bool needsSync; + int lastMarker; +} ExaCardInfoRec, *ExaCardInfoPtr; + +typedef struct _ExaAccelInfo { + /* PrepareSolid may fail if the pixmaps can't be accelerated to/from. + * This is an important feature for handling strange corner cases + * in hardware that are poorly expressed through flags. + */ + Bool (*PrepareSolid) (PixmapPtr pPixmap, + int alu, + Pixel planemask, + Pixel fg); + void (*Solid) (PixmapPtr pPixmap, int x1, int y1, int x2, int y2); + void (*DoneSolid) (PixmapPtr pPixmap); + + /* PrepareSolid may fail if the pixmaps can't be accelerated to/from. + * This is an important feature for handling strange corner cases + * in hardware that are poorly expressed through flags. + */ + Bool (*PrepareCopy) (PixmapPtr pSrcPixmap, + PixmapPtr pDstPixmap, + int dx, + int dy, + int alu, + Pixel planemask); + void (*Copy) (PixmapPtr pDstPixmap, + int srcX, + int srcY, + int dstX, + int dstY, + int width, + int height); + void (*DoneCopy) (PixmapPtr pDstPixmap); + + /* The Composite hooks are a wrapper around the Composite operation. + * The CheckComposite occurs before pixmap migration occurs, + * and may fail for many hardware-dependent reasons. + * PrepareComposite should not fail, and the Bool return may + * not be necessary if we can + * adequately represent pixmap location/pitch limitations.. + */ + Bool (*CheckComposite) (int op, + PicturePtr pSrcPicture, + PicturePtr pMaskPicture, + PicturePtr pDstPicture); + Bool (*PrepareComposite) (int op, + PicturePtr pSrcPicture, + PicturePtr pMaskPicture, + PicturePtr pDstPicture, + PixmapPtr pSrc, + PixmapPtr pMask, + PixmapPtr pDst); + void (*Composite) (PixmapPtr pDst, + int srcX, + int srcY, + int maskX, + int maskY, + int dstX, + int dstY, + int width, + int height); + void (*DoneComposite) (PixmapPtr pDst); + + /* Attempt to upload the data from src into the rectangle of the + * in-framebuffer pDst beginning at x,y and of width w,h. May fail. + */ + Bool (*UploadToScreen) (PixmapPtr pDst, + int x, + int y, + int w, + int h, + char *src, + int src_pitch); + Bool (*UploadToScratch) (PixmapPtr pSrc, + PixmapPtr pDst); + + /* Attempt to download the rectangle from the in-framebuffer pSrc into + * dst, given the pitch. May fail. Since it is likely + * accelerated, a markSync will follow it as with other acceleration + * hooks. + */ + Bool (*DownloadFromScreen)(PixmapPtr pSrc, + int x, int y, + int w, int h, + char *dst, int dst_pitch); + + /* Should return a hrdware-dependent marker number which can + * be waited for with WaitMarker. It can be not implemented in which + * case WaitMarker must wait for idle on any given marker + * number. + */ + int (*MarkSync) (ScreenPtr pScreen); + void (*WaitMarker) (ScreenPtr pScreen, int marker); + + /* These are wrapping all fb or composite operations that will cause + * a direct access to the framebuffer. You can use them to update + * endian swappers, force migration to RAM, or whatever else you find + * useful at this point. EXA can stack up to 3 calls to Prepare/Finish + * access, though they will have a different index. If your hardware + * doesn't have enough separate configurable swapper, you can return + * FALSE from PrepareAccess() to force EXA to migrate the pixmap to RAM. + * Note that DownloadFromScreen and UploadToScreen can both be called + * between PrepareAccess() and FinishAccess(). If they need to use a + * swapper, they should save & restore its setting. + */ + Bool (*PrepareAccess)(PixmapPtr pPix, int index); + void (*FinishAccess)(PixmapPtr pPix, int index); + #define EXA_PREPARE_DEST 0 + #define EXA_PREPARE_SRC 1 + #define EXA_PREPARE_MASK 2 + +} ExaAccelInfoRec, *ExaAccelInfoPtr; + +typedef struct _ExaDriver { + ExaCardInfoRec card; + ExaAccelInfoRec accel; +} ExaDriverRec, *ExaDriverPtr; + +#define EXA_OFFSCREEN_PIXMAPS (1 << 0) +#define EXA_OFFSCREEN_ALIGN_POT (1 << 1) + + +#define EXA_MAKE_VERSION(a, b, c) (((a) << 16) | ((b) << 8) | (c)) +#define EXA_VERSION \ + EXA_MAKE_VERSION(EXA_VERSION_MAJOR, EXA_VERSION_MINOR, EXA_VERSION_RELEASE) +#define EXA_IS_VERSION(a,b,c) (EXA_VERSION >= EXA_MAKE_VERSION(a,b,c)) + +unsigned int +exaGetVersion(void); + +Bool +exaDriverInit(ScreenPtr pScreen, + ExaDriverPtr pScreenInfo); + +void +exaDriverFini(ScreenPtr pScreen); + +void +exaMarkSync(ScreenPtr pScreen); +void +exaWaitSync(ScreenPtr pScreen); + +Bool +exaOffscreenInit(ScreenPtr pScreen); + +ExaOffscreenArea * +exaOffscreenAlloc(ScreenPtr pScreen, int size, int align, + Bool locked, + ExaOffscreenSaveProc save, + pointer privData); + +ExaOffscreenArea * +exaOffscreenFree(ScreenPtr pScreen, ExaOffscreenArea *area); + +unsigned long +exaGetPixmapOffset(PixmapPtr pPix); + +unsigned long +exaGetPixmapPitch(PixmapPtr pPix); + +unsigned long +exaGetPixmapSize(PixmapPtr pPix); + +#define exaInitCard(exa, sync, memory_base, off_screen_base, memory_size, \ + offscreen_byte_align, offscreen_pitch, flags, \ + max_x, max_y) \ + (exa)->card.Sync = sync; \ + (exa)->card.memoryBase = memory_base; \ + (exa)->card.offScreenBase = off_screen_base; \ + (exa)->card.memorySize = memory_size; \ + (exa)->card.offscreenByteAlign = offscreen_byte_align; \ + (exa)->card.offscreenPitch = offscreen_pitch; \ + (exa)->card.flags = flags; \ + (exa)->card.maxX = max_x; \ + (exa)->card.maxY = max_y + +#endif /* EXA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exaPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exaPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exaPriv.h (revision 51223) @@ -0,0 +1,343 @@ +/* + * + * Copyright (C) 2000 Keith Packard, member of The XFree86 Project, Inc. + * 2005 Zack Rusin, Trolltech + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + */ + +#ifndef EXAPRIV_H +#define EXAPRIV_H + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "exa.h" + +#include +#define NEED_EVENTS +#include +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "windowstr.h" +#include "servermd.h" +#include "mibstore.h" +#include "colormapst.h" +#include "gcstruct.h" +#include "input.h" +#include "mipointer.h" +#include "mi.h" +#include "dix.h" +#include "fb.h" +#include "fboverlay.h" +#ifdef RENDER +#include "fbpict.h" +#endif + +#define DEBUG_TRACE_FALL 0 +#define DEBUG_MIGRATE 0 +#define DEBUG_PIXMAP 0 +#define DEBUG_OFFSCREEN 0 + +#if DEBUG_TRACE_FALL +#define EXA_FALLBACK(x) \ +do { \ + ErrorF("EXA fallback at %s: ", __FUNCTION__); \ + ErrorF x; \ +} while (0) +#else +#define EXA_FALLBACK(x) +#endif + +#ifndef EXA_MAX_FB +#define EXA_MAX_FB FB_OVERLAY_MAX +#endif + +typedef void (*EnableDisableFBAccessProcPtr)(int, Bool); +typedef struct { + ExaDriverPtr info; + CreateGCProcPtr SavedCreateGC; + CloseScreenProcPtr SavedCloseScreen; + GetImageProcPtr SavedGetImage; + GetSpansProcPtr SavedGetSpans; + PaintWindowBackgroundProcPtr SavedPaintWindowBackground; + CreatePixmapProcPtr SavedCreatePixmap; + DestroyPixmapProcPtr SavedDestroyPixmap; + PaintWindowBorderProcPtr SavedPaintWindowBorder; + CopyWindowProcPtr SavedCopyWindow; +#ifdef RENDER + CompositeProcPtr SavedComposite; + GlyphsProcPtr SavedGlyphs; +#endif + EnableDisableFBAccessProcPtr SavedEnableDisableFBAccess; + Bool wrappedEnableDisableFB; + Bool swappedOut; +} ExaScreenPrivRec, *ExaScreenPrivPtr; + +/* + * This is the only completely portable way to + * compute this info. + */ +#ifndef BitsPerPixel +#define BitsPerPixel(d) (\ + PixmapWidthPaddingInfo[d].notPower2 ? \ + (PixmapWidthPaddingInfo[d].bytesPerPixel * 8) : \ + ((1 << PixmapWidthPaddingInfo[d].padBytesLog2) * 8 / \ + (PixmapWidthPaddingInfo[d].padRoundUp+1))) +#endif + +extern int exaScreenPrivateIndex; +extern int exaPixmapPrivateIndex; +#define ExaGetScreenPriv(s) ((ExaScreenPrivPtr)(s)->devPrivates[exaScreenPrivateIndex].ptr) +#define ExaScreenPriv(s) ExaScreenPrivPtr pExaScr = ExaGetScreenPriv(s) + +#define ExaGetPixmapPriv(p) ((ExaPixmapPrivPtr)(p)->devPrivates[exaPixmapPrivateIndex].ptr) +#define ExaSetPixmapPriv(p,a) ((p)->devPrivates[exaPixmapPrivateIndex].ptr = (pointer) (a)) +#define ExaPixmapPriv(p) ExaPixmapPrivPtr pExaPixmap = ExaGetPixmapPriv(p) + +typedef struct { + ExaOffscreenArea *area; + int score; + int devKind; + DevUnion devPrivate; + + /* If area is NULL, then dirty == TRUE means that the pixmap has been + * modified, so the contents are defined. Used to avoid uploads of + * undefined data. + * If area is non-NULL, then dirty == TRUE means that the in-framebuffer + * copy has been changed from the system-memory copy. Used to avoid + * downloads of unmodified data. + */ + Bool dirty; + unsigned int size; +} ExaPixmapPrivRec, *ExaPixmapPrivPtr; + + +/* exaasync.c */ +void +ExaCheckFillSpans (DrawablePtr pDrawable, GCPtr pGC, int nspans, + DDXPointPtr ppt, int *pwidth, int fSorted); + +void +ExaCheckSetSpans (DrawablePtr pDrawable, GCPtr pGC, char *psrc, + DDXPointPtr ppt, int *pwidth, int nspans, int fSorted); + +void +ExaCheckPutImage (DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + char *bits); + +RegionPtr +ExaCheckCopyArea (DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, int dstx, int dsty); + +RegionPtr +ExaCheckCopyPlane (DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, int dstx, int dsty, + unsigned long bitPlane); + +void +ExaCheckPolyPoint (DrawablePtr pDrawable, GCPtr pGC, int mode, int npt, + DDXPointPtr pptInit); + +void +ExaCheckPolylines (DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr ppt); + +void +ExaCheckPolySegment (DrawablePtr pDrawable, GCPtr pGC, + int nsegInit, xSegment *pSegInit); + +void +ExaCheckPolyRectangle (DrawablePtr pDrawable, GCPtr pGC, + int nrects, xRectangle *prect); + +void +ExaCheckPolyArc (DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *pArcs); + +#define ExaCheckFillPolygon miFillPolygon + +void +ExaCheckPolyFillRect (DrawablePtr pDrawable, GCPtr pGC, + int nrect, xRectangle *prect); + +void +ExaCheckPolyFillArc (DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *pArcs); + +void +ExaCheckImageGlyphBlt (DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); + +void +ExaCheckPolyGlyphBlt (DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); + +void +ExaCheckPushPixels (GCPtr pGC, PixmapPtr pBitmap, + DrawablePtr pDrawable, + int w, int h, int x, int y); + +void +ExaCheckGetImage (DrawablePtr pDrawable, + int x, int y, int w, int h, + unsigned int format, unsigned long planeMask, + char *d); + +void +ExaCheckGetSpans (DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pdstStart); + +void +ExaCheckSaveAreas (PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +ExaCheckRestoreAreas (PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +ExaCheckPaintWindow (WindowPtr pWin, RegionPtr pRegion, int what); + +extern const GCOps exaAsyncPixmapGCOps; + +#ifdef RENDER +void +ExaCheckComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +#endif + +/* exaoffscreen.c */ +void +ExaOffscreenMarkUsed (PixmapPtr pPixmap); + +void +ExaOffscreenSwapOut (ScreenPtr pScreen); + +void +ExaOffscreenSwapIn (ScreenPtr pScreen); + +void +ExaOffscreenFini (ScreenPtr pScreen); + +void +exaEnableDisableFBAccess (int index, Bool enable); + +/* exa.c */ +void +exaDrawableUseScreen(DrawablePtr pDrawable); + +void +exaDrawableUseMemory(DrawablePtr pDrawable); + +void +exaPixmapUseScreen (PixmapPtr pPixmap); + +void +exaPixmapUseMemory (PixmapPtr pPixmap); + +void +exaPrepareAccess(DrawablePtr pDrawable, int index); + +void +exaFinishAccess(DrawablePtr pDrawable, int index); + +void +exaDrawableDirty(DrawablePtr pDrawable); + +Bool +exaDrawableIsOffscreen (DrawablePtr pDrawable); + +Bool +exaPixmapIsOffscreen(PixmapPtr p); + +PixmapPtr +exaGetOffscreenPixmap (DrawablePtr pDrawable, int *xp, int *yp); + +void +exaMoveInPixmap (PixmapPtr pPixmap); + +RegionPtr +exaCopyArea(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable, GCPtr pGC, + int srcx, int srcy, int width, int height, int dstx, int dsty); + +void +exaCopyNtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +exaComposite(CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +exaGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +#endif /* EXAPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exevents.h (revision 51223) @@ -0,0 +1,183 @@ +/* $XFree86: xc/programs/Xserver/include/exevents.h,v 3.1 1996/04/15 11:34:29 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/******************************************************************** + * Interface of 'exevents.c' + */ + +#ifndef EXEVENTS_H +#define EXEVENTS_H + +extern void RegisterOtherDevice ( + DeviceIntPtr /* device */); + +extern void ProcessOtherEvent ( + xEventPtr /* FIXME deviceKeyButtonPointer * xE */, + DeviceIntPtr /* other */, + int /* count */); + +extern int InitProximityClassDeviceStruct( + DeviceIntPtr /* dev */); + +extern void InitValuatorAxisStruct( + DeviceIntPtr /* dev */, + int /* axnum */, + int /* minval */, + int /* maxval */, + int /* resolution */, + int /* min_res */, + int /* max_res */); + +extern void DeviceFocusEvent( + DeviceIntPtr /* dev */, + int /* type */, + int /* mode */, + int /* detail */, + WindowPtr /* pWin */); + +extern int GrabButton( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + BYTE /* this_device_mode */, + BYTE /* other_devices_mode */, + CARD16 /* modifiers */, + DeviceIntPtr /* modifier_device */, + CARD8 /* button */, + Window /* grabWindow */, + BOOL /* ownerEvents */, + Cursor /* rcursor */, + Window /* rconfineTo */, + Mask /* eventMask */); + +extern int GrabKey( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + BYTE /* this_device_mode */, + BYTE /* other_devices_mode */, + CARD16 /* modifiers */, + DeviceIntPtr /* modifier_device */, + CARD8 /* key */, + Window /* grabWindow */, + BOOL /* ownerEvents */, + Mask /* mask */); + +extern int SelectForWindow( + DeviceIntPtr /* dev */, + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + Mask /* exclusivemasks */, + Mask /* validmasks */); + +extern int AddExtensionClient ( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + int /* mskidx */); + +extern void RecalculateDeviceDeliverableEvents( + WindowPtr /* pWin */); + +extern int InputClientGone( + WindowPtr /* pWin */, + XID /* id */); + +extern int SendEvent ( + ClientPtr /* client */, + DeviceIntPtr /* d */, + Window /* dest */, + Bool /* propagate */, + xEvent * /* ev */, + Mask /* mask */, + int /* count */); + +extern int SetButtonMapping ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* nElts */, + BYTE * /* map */); + +extern int SetModifierMapping( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* len */, + int /* rlen */, + int /* numKeyPerModifier */, + KeyCode * /* inputMap */, + KeyClassPtr * /* k */); + +extern void SendDeviceMappingNotify( + CARD8 /* request, */, + KeyCode /* firstKeyCode */, + CARD8 /* count */, + DeviceIntPtr /* dev */); + +extern int ChangeKeyMapping( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned /* len */, + int /* type */, + KeyCode /* firstKeyCode */, + CARD8 /* keyCodes */, + CARD8 /* keySymsPerKeyCode */, + KeySym * /* map */); + +extern void DeleteWindowFromAnyExtEvents( + WindowPtr /* pWin */, + Bool /* freeResources */); + +extern void DeleteDeviceFromAnyExtEvents( + WindowPtr /* pWin */, + DeviceIntPtr /* dev */); + +extern int MaybeSendDeviceMotionNotifyHint ( + deviceKeyButtonPointer * /* pEvents */, + Mask /* mask */); + +extern void CheckDeviceGrabAndHintWindow ( + WindowPtr /* pWin */, + int /* type */, + deviceKeyButtonPointer * /* xE */, + GrabPtr /* grab */, + ClientPtr /* client */, + Mask /* deliveryMask */); + +extern Mask DeviceEventMaskForClient( + DeviceIntPtr /* dev */, + WindowPtr /* pWin */, + ClientPtr /* client */); + +extern void MaybeStopDeviceHint( + DeviceIntPtr /* dev */, + ClientPtr /* client */); + +extern int DeviceEventSuppressForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + int /* maskndx */); + +#endif /* EXEVENTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exglobals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exglobals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/exglobals.h (revision 51223) @@ -0,0 +1,80 @@ +/* $XFree86: xc/programs/Xserver/Xi/exglobals.h,v 3.2 1996/05/06 05:56:03 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/***************************************************************** + * + * Globals referenced elsewhere in the server. + * + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef EXGLOBALS_H +#define EXGLOBALS_H 1 + +extern int IReqCode; +extern int BadDevice; +extern int BadEvent; +extern int BadMode; +extern int DeviceBusy; +extern int BadClass; + +extern Mask DevicePointerMotionMask; +extern Mask DevicePointerMotionHintMask; +extern Mask DeviceFocusChangeMask; +extern Mask DeviceStateNotifyMask; +extern Mask ChangeDeviceNotifyMask; +extern Mask DeviceMappingNotifyMask; +extern Mask DeviceOwnerGrabButtonMask; +extern Mask DeviceButtonGrabMask; +extern Mask DeviceButtonMotionMask; +extern Mask PropagateMask[]; + +extern int DeviceValuator; +extern int DeviceKeyPress; +extern int DeviceKeyRelease; +extern int DeviceButtonPress; +extern int DeviceButtonRelease; +extern int DeviceMotionNotify; +extern int DeviceFocusIn; +extern int DeviceFocusOut; +extern int ProximityIn; +extern int ProximityOut; +extern int DeviceStateNotify; +extern int DeviceKeyStateNotify; +extern int DeviceButtonStateNotify; +extern int DeviceMappingNotify; +extern int ChangeDeviceNotify; + +extern int RT_INPUTCLIENT; + +#if 0 +/* FIXME: in dix */ +extern InputInfo inputInfo; +#endif + +#endif /* EXGLOBALS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extension.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extension.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extension.h (revision 51223) @@ -0,0 +1,67 @@ +/* $Xorg: extension.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/extension.h,v 1.5 2001/12/14 19:59:54 dawes Exp $ */ + +#ifndef EXTENSION_H +#define EXTENSION_H + +_XFUNCPROTOBEGIN + +extern unsigned short StandardMinorOpcode(ClientPtr /*client*/); + +extern unsigned short MinorOpcodeOfRequest(ClientPtr /*client*/); + +extern void InitExtensions(int argc, char **argv); + +extern void InitVisualWrap(void); + +extern void CloseDownExtensions(void); + +_XFUNCPROTOEND + +#endif /* EXTENSION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extinit.h (revision 51223) @@ -0,0 +1,166 @@ +/* $XFree86: xc/programs/Xserver/include/extinit.h,v 3.2 2001/08/01 00:44:58 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/******************************************************************** + * Interface of extinit.c + */ + +#ifndef EXTINIT_H +#define EXTINIT_H + +#include "extnsionst.h" + +void +XInputExtensionInit( + void + ); + + +int +ProcIDispatch ( + ClientPtr /* client */ + ); + +int +SProcIDispatch( + ClientPtr /* client */ + ); + +void +SReplyIDispatch ( + ClientPtr /* client */, + int /* len */, + xGrabDeviceReply * /* rep */ + ); + +void +SEventIDispatch ( + xEvent * /* from */, + xEvent * /* to */ + ); + +void +SEventDeviceValuator ( + deviceValuator * /* from */, + deviceValuator * /* to */ + ); + +void +SEventFocus ( + deviceFocus * /* from */, + deviceFocus * /* to */ + ); + +void +SDeviceStateNotifyEvent ( + deviceStateNotify * /* from */, + deviceStateNotify * /* to */ + ); + +void +SDeviceKeyStateNotifyEvent ( + deviceKeyStateNotify * /* from */, + deviceKeyStateNotify * /* to */ + ); + +void +SDeviceButtonStateNotifyEvent ( + deviceButtonStateNotify * /* from */, + deviceButtonStateNotify * /* to */ + ); + +void +SChangeDeviceNotifyEvent ( + changeDeviceNotify * /* from */, + changeDeviceNotify * /* to */ + ); + +void +SDeviceMappingNotifyEvent ( + deviceMappingNotify * /* from */, + deviceMappingNotify * /* to */ + ); + +void +FixExtensionEvents ( + ExtensionEntry * /* extEntry */ + ); + +void +RestoreExtensionEvents ( + void + ); + +void +IResetProc( + ExtensionEntry * /* unused */ + ); + +void +AssignTypeAndName ( + DeviceIntPtr /* dev */, + Atom /* type */, + char * /* name */ + ); + +void +MakeDeviceTypeAtoms ( + void +); + +DeviceIntPtr +LookupDeviceIntRec ( + CARD8 /* id */ + ); + +void +SetExclusiveAccess ( + Mask /* mask */ + ); + +void +AllowPropagateSuppress ( + Mask /* mask */ + ); + +Mask +GetNextExtEventMask ( + void +); + +void +SetMaskForExtEvent( + Mask /* mask */, + int /* event */ + ); + +void +SetEventInfo( + Mask /* mask */, + int /* constant */ + ); + +#endif /* EXTINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extnsionst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extnsionst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/extnsionst.h (revision 51223) @@ -0,0 +1,152 @@ +/* $Xorg: extnsionst.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/extnsionst.h,v 3.8 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef EXTENSIONSTRUCT_H +#define EXTENSIONSTRUCT_H + +#include "misc.h" +#include "screenint.h" +#include "extension.h" +#include "gc.h" + +typedef struct _ExtensionEntry { + int index; + void (* CloseDown)( /* called at server shutdown */ + struct _ExtensionEntry * /* extension */); + char *name; /* extension name */ + int base; /* base request number */ + int eventBase; + int eventLast; + int errorBase; + int errorLast; + int num_aliases; + char **aliases; + pointer extPrivate; + unsigned short (* MinorOpcode)( /* called for errors */ + ClientPtr /* client */); +#ifdef XCSECURITY + Bool secure; /* extension visible to untrusted clients? */ +#endif +} ExtensionEntry; + +/* + * The arguments may be different for extension event swapping functions. + * Deal with this by casting when initializing the event's EventSwapVector[] + * entries. + */ +typedef void (*EventSwapPtr) (xEvent *, xEvent *); + +extern EventSwapPtr EventSwapVector[128]; + +extern void NotImplemented ( /* FIXME: this may move to another file... */ + xEvent *, + xEvent *); + +typedef void (* ExtensionLookupProc)( +#ifdef EXTENSION_PROC_ARGS + EXTENSION_PROC_ARGS +#else + /* args no longer indeterminate */ + char *name, + GCPtr pGC +#endif +); + +typedef struct _ProcEntry { + char *name; + ExtensionLookupProc proc; +} ProcEntryRec, *ProcEntryPtr; + +typedef struct _ScreenProcEntry { + int num; + ProcEntryPtr procList; +} ScreenProcEntry; + +#define SetGCVector(pGC, VectorElement, NewRoutineAddress, Atom) \ + pGC->VectorElement = NewRoutineAddress; + +#define GetGCValue(pGC, GCElement) (pGC->GCElement) + + +extern ExtensionEntry *AddExtension( + char* /*name*/, + int /*NumEvents*/, + int /*NumErrors*/, + int (* /*MainProc*/)(ClientPtr /*client*/), + int (* /*SwappedMainProc*/)(ClientPtr /*client*/), + void (* /*CloseDownProc*/)(ExtensionEntry * /*extension*/), + unsigned short (* /*MinorOpcodeProc*/)(ClientPtr /*client*/) +); + +extern Bool AddExtensionAlias( + char* /*alias*/, + ExtensionEntry * /*extension*/); + +extern ExtensionEntry *CheckExtension(const char *extname); + +extern ExtensionLookupProc LookupProc( + char* /*name*/, + GCPtr /*pGC*/); + +extern Bool RegisterProc( + char* /*name*/, + GCPtr /*pGC*/, + ExtensionLookupProc /*proc*/); + +extern Bool RegisterScreenProc( + char* /*name*/, + ScreenPtr /*pScreen*/, + ExtensionLookupProc /*proc*/); + +extern void DeclareExtensionSecurity( + char * /*extname*/, + Bool /*secure*/); + +#endif /* EXTENSIONSTRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fastblt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fastblt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fastblt.h (revision 51223) @@ -0,0 +1,98 @@ +/* $Xorg: fastblt.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mfb/fastblt.h,v 1.4 2001/01/17 22:37:01 dawes Exp $ */ + +/* + * Fast bitblt macros for certain hardware. If your machine has an addressing + * mode of small constant + register, you'll probably want this magic specific + * code. It's 25% faster for the R2000. I haven't studied the Sparc + * instruction set, but I suspect it also has this addressing mode. Also, + * unrolling the loop by 32 is possibly excessive for mfb. The number of times + * the loop is actually looped through is pretty small. + */ + +/* + * WARNING: These macros make *a lot* of assumptions about + * the environment they are invoked in. Plenty of implicit + * arguments, lots of side effects. Don't use them casually. + */ + +#define SwitchOdd(n) case n: BodyOdd(n) +#define SwitchEven(n) case n: BodyEven(n) + +/* to allow mfb and cfb to share code... */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef BitRight +#define BitRight(a,b) SCRRIGHT(a,b) +#define BitLeft(a,b) SCRLEFT(a,b) +#endif + +#ifdef LARGE_INSTRUCTION_CACHE +#define UNROLL 8 +#define PackedLoop \ + switch (nl & (UNROLL-1)) { \ + SwitchOdd( 7) SwitchEven( 6) SwitchOdd( 5) SwitchEven( 4) \ + SwitchOdd( 3) SwitchEven( 2) SwitchOdd( 1) \ + } \ + while ((nl -= UNROLL) >= 0) { \ + LoopReset \ + BodyEven( 8) \ + BodyOdd( 7) BodyEven( 6) BodyOdd( 5) BodyEven( 4) \ + BodyOdd( 3) BodyEven( 2) BodyOdd( 1) \ + } +#else +#define UNROLL 4 +#define PackedLoop \ + switch (nl & (UNROLL-1)) { \ + SwitchOdd( 3) SwitchEven( 2) SwitchOdd( 1) \ + } \ + while ((nl -= UNROLL) >= 0) { \ + LoopReset \ + BodyEven( 4) \ + BodyOdd( 3) BodyEven( 2) BodyOdd( 1) \ + } +#endif + +#define DuffL(counter,label,body) \ + switch (counter & 3) { \ + label: \ + body \ + case 3: \ + body \ + case 2: \ + body \ + case 1: \ + body \ + case 0: \ + if ((counter -= 4) >= 0) \ + goto label; \ + } Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb.h (revision 51223) @@ -0,0 +1,2054 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fb.h,v 1.36tsi Exp $ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XdotOrg: xc/programs/Xserver/fb/fb.h,v 1.12 2005/08/24 11:18:33 daniels Exp $ */ + +#ifndef _FB_H_ +#define _FB_H_ + +#include +#include "scrnintstr.h" +#include "pixmap.h" +#include "pixmapstr.h" +#include "region.h" +#include "gcstruct.h" +#include "colormap.h" +#include "miscstruct.h" +#include "servermd.h" +#include "windowstr.h" +#include "mi.h" +#include "migc.h" +#include "mibstore.h" +#ifdef RENDER +#include "picturestr.h" +#else +#include "picture.h" +#endif + +/* + * This single define controls the basic size of data manipulated + * by this software; it must be log2(sizeof (FbBits) * 8) + */ + +#ifndef FB_SHIFT +#define FB_SHIFT LOG2_BITMAP_PAD +#endif + +#if FB_SHIFT < LOG2_BITMAP_PAD + error FB_SHIFT must be >= LOG2_BITMAP_PAD +#endif + +#define FB_UNIT (1 << FB_SHIFT) +#define FB_HALFUNIT (1 << (FB_SHIFT-1)) +#define FB_MASK (FB_UNIT - 1) +#define FB_ALLONES ((FbBits) -1) + +#if GLYPHPADBYTES != 4 +#error "GLYPHPADBYTES must be 4" +#endif +#if GETLEFTBITS_ALIGNMENT != 1 +#error "GETLEFTBITS_ALIGNMENT must be 1" +#endif +/* whether to bother to include 24bpp support */ +#ifndef FBNO24BIT +#define FB_24BIT +#endif + +/* + * Unless otherwise instructed, fb includes code to advertise 24bpp + * windows with 32bpp image format for application compatibility + */ + +#ifdef FB_24BIT +#ifndef FBNO24_32 +#define FB_24_32BIT +#endif +#endif + +#define FB_STIP_SHIFT LOG2_BITMAP_PAD +#define FB_STIP_UNIT (1 << FB_STIP_SHIFT) +#define FB_STIP_MASK (FB_STIP_UNIT - 1) +#define FB_STIP_ALLONES ((FbStip) -1) + +#define FB_STIP_ODDSTRIDE(s) (((s) & (FB_MASK >> FB_STIP_SHIFT)) != 0) +#define FB_STIP_ODDPTR(p) ((((long) (p)) & (FB_MASK >> 3)) != 0) + +#define FbStipStrideToBitsStride(s) (((s) >> (FB_SHIFT - FB_STIP_SHIFT))) +#define FbBitsStrideToStipStride(s) (((s) << (FB_SHIFT - FB_STIP_SHIFT))) + +#define FbFullMask(n) ((n) == FB_UNIT ? FB_ALLONES : ((((FbBits) 1) << n) - 1)) + +#if FB_SHIFT == 6 +# ifdef WIN32 +typedef unsigned __int64 FbBits; +# else +# if defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || defined(_LP64) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + defined (__powerpc64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef unsigned long FbBits; +# else +typedef unsigned long long FbBits; +# endif +# endif +#endif + +#if FB_SHIFT == 5 +typedef CARD32 FbBits; +#endif + +#if FB_SHIFT == 4 +typedef CARD16 FbBits; +#endif + +#if LOG2_BITMAP_PAD == FB_SHIFT +typedef FbBits FbStip; +#else +# if LOG2_BITMAP_PAD == 5 +typedef CARD32 FbStip; +# endif +#endif + +typedef int FbStride; + + +#ifdef FB_DEBUG +extern void fbValidateDrawable(DrawablePtr d); +extern void fbInitializeDrawable(DrawablePtr d); +extern void fbSetBits (FbStip *bits, int stride, FbStip data); +#define FB_HEAD_BITS (FbStip) (0xbaadf00d) +#define FB_TAIL_BITS (FbStip) (0xbaddf0ad) +#else +#define fbValidateDrawable(d) +#define fdInitializeDrawable(d) +#endif + +#include "fbrop.h" + +#if BITMAP_BIT_ORDER == LSBFirst +#define FbScrLeft(x,n) ((x) >> (n)) +#define FbScrRight(x,n) ((x) << (n)) +/* #define FbLeftBits(x,n) ((x) & ((((FbBits) 1) << (n)) - 1)) */ +#define FbLeftStipBits(x,n) ((x) & ((((FbStip) 1) << (n)) - 1)) +#define FbStipMoveLsb(x,s,n) (FbStipRight (x,(s)-(n))) +#define FbPatternOffsetBits 0 +#else +#define FbScrLeft(x,n) ((x) << (n)) +#define FbScrRight(x,n) ((x) >> (n)) +/* #define FbLeftBits(x,n) ((x) >> (FB_UNIT - (n))) */ +#define FbLeftStipBits(x,n) ((x) >> (FB_STIP_UNIT - (n))) +#define FbStipMoveLsb(x,s,n) (x) +#define FbPatternOffsetBits (sizeof (FbBits) - 1) +#endif + +#include "micoord.h" + +#define FbStipLeft(x,n) FbScrLeft(x,n) +#define FbStipRight(x,n) FbScrRight(x,n) + +#define FbRotLeft(x,n) FbScrLeft(x,n) | (n ? FbScrRight(x,FB_UNIT-n) : 0) +#define FbRotRight(x,n) FbScrRight(x,n) | (n ? FbScrLeft(x,FB_UNIT-n) : 0) + +#define FbRotStipLeft(x,n) FbStipLeft(x,n) | (n ? FbStipRight(x,FB_STIP_UNIT-n) : 0) +#define FbRotStipRight(x,n) FbStipRight(x,n) | (n ? FbStipLeft(x,FB_STIP_UNIT-n) : 0) + +#define FbLeftMask(x) ( ((x) & FB_MASK) ? \ + FbScrRight(FB_ALLONES,(x) & FB_MASK) : 0) +#define FbRightMask(x) ( ((FB_UNIT - (x)) & FB_MASK) ? \ + FbScrLeft(FB_ALLONES,(FB_UNIT - (x)) & FB_MASK) : 0) + +#define FbLeftStipMask(x) ( ((x) & FB_STIP_MASK) ? \ + FbStipRight(FB_STIP_ALLONES,(x) & FB_STIP_MASK) : 0) +#define FbRightStipMask(x) ( ((FB_STIP_UNIT - (x)) & FB_STIP_MASK) ? \ + FbScrLeft(FB_STIP_ALLONES,(FB_STIP_UNIT - (x)) & FB_STIP_MASK) : 0) + +#define FbBitsMask(x,w) (FbScrRight(FB_ALLONES,(x) & FB_MASK) & \ + FbScrLeft(FB_ALLONES,(FB_UNIT - ((x) + (w))) & FB_MASK)) + +#define FbStipMask(x,w) (FbStipRight(FB_STIP_ALLONES,(x) & FB_STIP_MASK) & \ + FbStipLeft(FB_STIP_ALLONES,(FB_STIP_UNIT - ((x)+(w))) & FB_STIP_MASK)) + + +#define FbMaskBits(x,w,l,n,r) { \ + n = (w); \ + r = FbRightMask((x)+n); \ + l = FbLeftMask(x); \ + if (l) { \ + n -= FB_UNIT - ((x) & FB_MASK); \ + if (n < 0) { \ + n = 0; \ + l &= r; \ + r = 0; \ + } \ + } \ + n >>= FB_SHIFT; \ +} + +#ifdef FBNOPIXADDR +#define FbMaskBitsBytes(x,w,copy,l,lb,n,r,rb) FbMaskBits(x,w,l,n,r) +#define FbDoLeftMaskByteRRop(dst,lb,l,and,xor) { \ + *dst = FbDoMaskRRop(*dst,and,xor,l); \ +} +#define FbDoRightMaskByteRRop(dst,rb,r,and,xor) { \ + *dst = FbDoMaskRRop(*dst,and,xor,r); \ +} +#else + +#define FbByteMaskInvalid 0x10 + +#define FbPatternOffset(o,t) ((o) ^ (FbPatternOffsetBits & ~(sizeof (t) - 1))) + +#define FbPtrOffset(p,o,t) ((t *) ((CARD8 *) (p) + (o))) +#define FbSelectPatternPart(xor,o,t) ((xor) >> (FbPatternOffset (o,t) << 3)) +#define FbStorePart(dst,off,t,xor) (*FbPtrOffset(dst,off,t) = \ + FbSelectPart(xor,off,t)) +#ifndef FbSelectPart +#define FbSelectPart(x,o,t) FbSelectPatternPart(x,o,t) +#endif + +#define FbMaskBitsBytes(x,w,copy,l,lb,n,r,rb) { \ + n = (w); \ + lb = 0; \ + rb = 0; \ + r = FbRightMask((x)+n); \ + if (r) { \ + /* compute right byte length */ \ + if ((copy) && (((x) + n) & 7) == 0) { \ + rb = (((x) + n) & FB_MASK) >> 3; \ + } else { \ + rb = FbByteMaskInvalid; \ + } \ + } \ + l = FbLeftMask(x); \ + if (l) { \ + /* compute left byte length */ \ + if ((copy) && ((x) & 7) == 0) { \ + lb = ((x) & FB_MASK) >> 3; \ + } else { \ + lb = FbByteMaskInvalid; \ + } \ + /* subtract out the portion painted by leftMask */ \ + n -= FB_UNIT - ((x) & FB_MASK); \ + if (n < 0) { \ + if (lb != FbByteMaskInvalid) { \ + if (rb == FbByteMaskInvalid) { \ + lb = FbByteMaskInvalid; \ + } else if (rb) { \ + lb |= (rb - lb) << (FB_SHIFT - 3); \ + rb = 0; \ + } \ + } \ + n = 0; \ + l &= r; \ + r = 0; \ + }\ + } \ + n >>= FB_SHIFT; \ +} + +#if FB_SHIFT == 6 +#define FbDoLeftMaskByteRRop6Cases(dst,xor) \ + case (sizeof (FbBits) - 7) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (5 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (6 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (5 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 4): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; + +#define FbDoRightMaskByteRRop6Cases(dst,xor) \ + case 4: \ + FbStorePart(dst,0,CARD32,xor); \ + break; \ + case 5: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD8,xor); \ + break; \ + case 6: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD16,xor); \ + break; \ + case 7: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD16,xor); \ + FbStorePart(dst,6,CARD8,xor); \ + break; +#else +#define FbDoLeftMaskByteRRop6Cases(dst,xor) +#define FbDoRightMaskByteRRop6Cases(dst,xor) +#endif + +#define FbDoLeftMaskByteRRop(dst,lb,l,and,xor) { \ + switch (lb) { \ + FbDoLeftMaskByteRRop6Cases(dst,xor) \ + case (sizeof (FbBits) - 3) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 3) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 2) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case sizeof (FbBits) - 3: \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + case sizeof (FbBits) - 2: \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD16,xor); \ + break; \ + case sizeof (FbBits) - 1: \ + FbStorePart(dst,sizeof (FbBits) - 1,CARD8,xor); \ + break; \ + default: \ + *dst = FbDoMaskRRop(*dst, and, xor, l); \ + break; \ + } \ +} + + +#define FbDoRightMaskByteRRop(dst,rb,r,and,xor) { \ + switch (rb) { \ + case 1: \ + FbStorePart(dst,0,CARD8,xor); \ + break; \ + case 2: \ + FbStorePart(dst,0,CARD16,xor); \ + break; \ + case 3: \ + FbStorePart(dst,0,CARD16,xor); \ + FbStorePart(dst,2,CARD8,xor); \ + break; \ + FbDoRightMaskByteRRop6Cases(dst,xor) \ + default: \ + *dst = FbDoMaskRRop (*dst, and, xor, r); \ + } \ +} +#endif + +#define FbMaskStip(x,w,l,n,r) { \ + n = (w); \ + r = FbRightStipMask((x)+n); \ + l = FbLeftStipMask(x); \ + if (l) { \ + n -= FB_STIP_UNIT - ((x) & FB_STIP_MASK); \ + if (n < 0) { \ + n = 0; \ + l &= r; \ + r = 0; \ + } \ + } \ + n >>= FB_STIP_SHIFT; \ +} + +/* + * These macros are used to transparently stipple + * in copy mode; the expected usage is with 'n' constant + * so all of the conditional parts collapse into a minimal + * sequence of partial word writes + * + * 'n' is the bytemask of which bytes to store, 'a' is the address + * of the FbBits base unit, 'o' is the offset within that unit + * + * The term "lane" comes from the hardware term "byte-lane" which + */ + +#define FbLaneCase1(n,a,o) ((n) == 0x01 ? \ + (*(CARD8 *) ((a)+FbPatternOffset(o,CARD8)) = \ + fgxor) : 0) +#define FbLaneCase2(n,a,o) ((n) == 0x03 ? \ + (*(CARD16 *) ((a)+FbPatternOffset(o,CARD16)) = \ + fgxor) : \ + ((void)FbLaneCase1((n)&1,a,o), \ + FbLaneCase1((n)>>1,a,(o)+1))) +#define FbLaneCase4(n,a,o) ((n) == 0x0f ? \ + (*(CARD32 *) ((a)+FbPatternOffset(o,CARD32)) = \ + fgxor) : \ + ((void)FbLaneCase2((n)&3,a,o), \ + FbLaneCase2((n)>>2,a,(o)+2))) +#define FbLaneCase8(n,a,o) ((n) == 0x0ff ? (*(FbBits *) ((a)+(o)) = fgxor) : \ + ((void)FbLaneCase4((n)&15,a,o), \ + FbLaneCase4((n)>>4,a,(o)+4))) + +#if FB_SHIFT == 6 +#define FbLaneCase(n,a) FbLaneCase8(n,(CARD8 *) (a),0) +#endif + +#if FB_SHIFT == 5 +#define FbLaneCase(n,a) FbLaneCase4(n,(CARD8 *) (a),0) +#endif + +/* Rotate a filled pixel value to the specified alignement */ +#define FbRot24(p,b) (FbScrRight(p,b) | FbScrLeft(p,24-(b))) +#define FbRot24Stip(p,b) (FbStipRight(p,b) | FbStipLeft(p,24-(b))) + +/* step a filled pixel value to the next/previous FB_UNIT alignment */ +#define FbNext24Pix(p) (FbRot24(p,(24-FB_UNIT%24))) +#define FbPrev24Pix(p) (FbRot24(p,FB_UNIT%24)) +#define FbNext24Stip(p) (FbRot24(p,(24-FB_STIP_UNIT%24))) +#define FbPrev24Stip(p) (FbRot24(p,FB_STIP_UNIT%24)) + +/* step a rotation value to the next/previous rotation value */ +#if FB_UNIT == 64 +#define FbNext24Rot(r) ((r) == 16 ? 0 : (r) + 8) +#define FbPrev24Rot(r) ((r) == 0 ? 16 : (r) - 8) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define FbFirst24Rot(x) (((x) + 8) % 24) +#else +#define FbFirst24Rot(x) ((x) % 24) +#endif + +#endif + +#if FB_UNIT == 32 +#define FbNext24Rot(r) ((r) == 0 ? 16 : (r) - 8) +#define FbPrev24Rot(r) ((r) == 16 ? 0 : (r) + 8) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define FbFirst24Rot(x) (((x) + 16) % 24) +#else +#define FbFirst24Rot(x) ((x) % 24) +#endif +#endif + +#define FbNext24RotStip(r) ((r) == 0 ? 16 : (r) - 8) +#define FbPrev24RotStip(r) ((r) == 16 ? 0 : (r) + 8) + +/* Whether 24-bit specific code is needed for this filled pixel value */ +#define FbCheck24Pix(p) ((p) == FbNext24Pix(p)) + +/* Macros for dealing with dashing */ + +#define FbDashDeclare \ + unsigned char *__dash, *__firstDash, *__lastDash + +#define FbDashInit(pGC,pPriv,dashOffset,dashlen,even) { \ + (even) = TRUE; \ + __firstDash = (pGC)->dash; \ + __lastDash = __firstDash + (pGC)->numInDashList; \ + (dashOffset) %= (pPriv)->dashLength; \ + \ + __dash = __firstDash; \ + while ((dashOffset) >= ((dashlen) = *__dash)) \ + { \ + (dashOffset) -= (dashlen); \ + (even) = 1-(even); \ + if (++__dash == __lastDash) \ + __dash = __firstDash; \ + } \ + (dashlen) -= (dashOffset); \ +} + +#define FbDashNext(dashlen) { \ + if (++__dash == __lastDash) \ + __dash = __firstDash; \ + (dashlen) = *__dash; \ +} + +/* as numInDashList is always even, this case can skip a test */ + +#define FbDashNextEven(dashlen) { \ + (dashlen) = *++__dash; \ +} + +#define FbDashNextOdd(dashlen) FbDashNext(dashlen) + +#define FbDashStep(dashlen,even) { \ + if (!--(dashlen)) { \ + FbDashNext(dashlen); \ + (even) = 1-(even); \ + } \ +} + +/* XXX fb*PrivateIndex should be static, but it breaks the ABI */ + +extern int fbGCPrivateIndex; +extern int fbGetGCPrivateIndex(void); +#ifndef FB_NO_WINDOW_PIXMAPS +extern int fbWinPrivateIndex; +extern int fbGetWinPrivateIndex(void); +#endif +extern const GCOps fbGCOps; +extern const GCFuncs fbGCFuncs; + +#ifdef TEKX11 +#define FB_OLD_GC +#define FB_OLD_SCREEN +#endif + +#ifdef FB_OLD_SCREEN +# define FB_OLD_MISCREENINIT /* miScreenInit requires 14 args, not 13 */ +extern WindowPtr *WindowTable; +#endif + +#ifdef FB_24_32BIT +#define FB_SCREEN_PRIVATE +#endif + +#ifdef FB_SCREEN_PRIVATE +extern int fbScreenPrivateIndex; +extern int fbGetScreenPrivateIndex(void); + +/* private field of a screen */ +typedef struct { + unsigned char win32bpp; /* window bpp for 32-bpp images */ + unsigned char pix32bpp; /* pixmap bpp for 32-bpp images */ +} FbScreenPrivRec, *FbScreenPrivPtr; + +#define fbGetScreenPrivate(pScreen) ((FbScreenPrivPtr) \ + (pScreen)->devPrivates[fbGetScreenPrivateIndex()].ptr) +#endif + +/* private field of GC */ +typedef struct { +#ifdef FB_OLD_GC + unsigned char pad1; + unsigned char pad2; + unsigned char pad3; + unsigned fExpose:1; + unsigned freeCompClip:1; + PixmapPtr pRotatedPixmap; + RegionPtr pCompositeClip; +#endif + FbBits and, xor; /* reduced rop values */ + FbBits bgand, bgxor; /* for stipples */ + FbBits fg, bg, pm; /* expanded and filled */ + unsigned int dashLength; /* total of all dash elements */ + unsigned char oneRect; /* clip list is single rectangle */ + unsigned char evenStipple; /* stipple is even */ + unsigned char bpp; /* current drawable bpp */ +} FbGCPrivRec, *FbGCPrivPtr; + +#define fbGetGCPrivate(pGC) ((FbGCPrivPtr)\ + (pGC)->devPrivates[fbGetGCPrivateIndex()].ptr) + +#ifdef FB_OLD_GC +#define fbGetCompositeClip(pGC) (fbGetGCPrivate(pGC)->pCompositeClip) +#define fbGetExpose(pGC) (fbGetGCPrivate(pGC)->fExpose) +#define fbGetFreeCompClip(pGC) (fbGetGCPrivate(pGC)->freeCompClip) +#define fbGetRotatedPixmap(pGC) (fbGetGCPrivate(pGC)->pRotatedPixmap) +#else +#define fbGetCompositeClip(pGC) ((pGC)->pCompositeClip) +#define fbGetExpose(pGC) ((pGC)->fExpose) +#define fbGetFreeCompClip(pGC) ((pGC)->freeCompClip) +#define fbGetRotatedPixmap(pGC) ((pGC)->pRotatedPixmap) +#endif + +#define fbGetScreenPixmap(s) ((PixmapPtr) (s)->devPrivate) +#ifdef FB_NO_WINDOW_PIXMAPS +#define fbGetWindowPixmap(d) fbGetScreenPixmap(((DrawablePtr) (d))->pScreen) +#else +#define fbGetWindowPixmap(pWin) ((PixmapPtr)\ + ((WindowPtr) (pWin))->devPrivates[fbGetWinPrivateIndex()].ptr) +#endif + +#ifdef ROOTLESS +#define __fbPixDrawableX(pPix) ((pPix)->drawable.x) +#define __fbPixDrawableY(pPix) ((pPix)->drawable.y) +#else +#define __fbPixDrawableX(pPix) 0 +#define __fbPixDrawableY(pPix) 0 +#endif + +#ifdef COMPOSITE +#define __fbPixOffXWin(pPix) (__fbPixDrawableX(pPix) - (pPix)->screen_x) +#define __fbPixOffYWin(pPix) (__fbPixDrawableY(pPix) - (pPix)->screen_y) +#else +#define __fbPixOffXWin(pPix) (__fbPixDrawableX(pPix)) +#define __fbPixOffYWin(pPix) (__fbPixDrawableY(pPix)) +#endif +#define __fbPixOffXPix(pPix) (__fbPixDrawableX(pPix)) +#define __fbPixOffYPix(pPix) (__fbPixDrawableY(pPix)) + +#define fbGetDrawable(pDrawable, pointer, stride, bpp, xoff, yoff) { \ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) { \ + _pPix = fbGetWindowPixmap(pDrawable); \ + (xoff) = __fbPixOffXWin(_pPix); \ + (yoff) = __fbPixOffYWin(_pPix); \ + } else { \ + _pPix = (PixmapPtr) (pDrawable); \ + (xoff) = __fbPixOffXPix(_pPix); \ + (yoff) = __fbPixOffYPix(_pPix); \ + } \ + (pointer) = (FbBits *) _pPix->devPrivate.ptr; \ + (stride) = ((int) _pPix->devKind) / sizeof (FbBits); (void)(stride); \ + (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ +} + +#define fbGetStipDrawable(pDrawable, pointer, stride, bpp, xoff, yoff) { \ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) { \ + _pPix = fbGetWindowPixmap(pDrawable); \ + (xoff) = __fbPixOffXWin(_pPix); \ + (yoff) = __fbPixOffYWin(_pPix); \ + } else { \ + _pPix = (PixmapPtr) (pDrawable); \ + (xoff) = __fbPixOffXPix(_pPix); \ + (yoff) = __fbPixOffYPix(_pPix); \ + } \ + (pointer) = (FbStip *) _pPix->devPrivate.ptr; \ + (stride) = ((int) _pPix->devKind) / sizeof (FbStip); (void)(stride); \ + (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ +} + +/* + * XFree86 empties the root BorderClip when the VT is inactive, + * here's a macro which uses that to disable GetImage and GetSpans + */ + +#define fbWindowEnabled(pWin) \ + REGION_NOTEMPTY((pWin)->drawable.pScreen, \ + &WindowTable[(pWin)->drawable.pScreen->myNum]->borderClip) + +#define fbDrawableEnabled(pDrawable) \ + ((pDrawable)->type == DRAWABLE_PIXMAP ? \ + TRUE : fbWindowEnabled((WindowPtr) pDrawable)) + +#ifdef FB_OLD_SCREEN +#define BitsPerPixel(d) (\ + ((1 << PixmapWidthPaddingInfo[d].padBytesLog2) * 8 / \ + (PixmapWidthPaddingInfo[d].padRoundUp+1))) +#endif + +#define FbPowerOfTwo(w) (((w) & ((w) - 1)) == 0) +/* + * Accelerated tiles are power of 2 width <= FB_UNIT + */ +#define FbEvenTile(w) ((w) <= FB_UNIT && FbPowerOfTwo(w)) +/* + * Accelerated stipples are power of 2 width and <= FB_UNIT/dstBpp + * with dstBpp a power of 2 as well + */ +#define FbEvenStip(w,bpp) ((w) * (bpp) <= FB_UNIT && FbPowerOfTwo(w) && FbPowerOfTwo(bpp)) + +/* + * fb24_32.c + */ +void +fb24_32GetSpans(DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart); + +void +fb24_32SetSpans (DrawablePtr pDrawable, + GCPtr pGC, + char *src, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted); + +void +fb24_32PutZImage (DrawablePtr pDrawable, + RegionPtr pClip, + int alu, + FbBits pm, + int x, + int y, + int width, + int height, + CARD8 *src, + FbStride srcStride); + +void +fb24_32GetImage (DrawablePtr pDrawable, + int x, + int y, + int w, + int h, + unsigned int format, + unsigned long planeMask, + char *d); + +void +fb24_32CopyMtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +PixmapPtr +fb24_32ReformatTile(PixmapPtr pOldTile, int bitsPerPixel); + +Bool +fb24_32CreateScreenResources(ScreenPtr pScreen); + +Bool +fb24_32ModifyPixmapHeader (PixmapPtr pPixmap, + int width, + int height, + int depth, + int bitsPerPixel, + int devKind, + pointer pPixData); + +/* + * fballpriv.c + */ +Bool +fbAllocatePrivates(ScreenPtr pScreen, int *pGCIndex); + +/* + * fbarc.c + */ + +void +fbPolyArc (DrawablePtr pDrawable, + GCPtr pGC, + int narcs, + xArc *parcs); + +/* + * fbbits.c + */ + +void +fbBresSolid8(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash8 (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots8 (FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc8 (FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph8 (FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline8 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment8 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +void +fbBresSolid16(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash16(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots16(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc16(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph16(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline16 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment16 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + + +void +fbBresSolid24(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash24(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots24(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc24(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph24(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline24 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment24 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + + +void +fbBresSolid32(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash32(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots32(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc32(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph32(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); +void +fbPolyline32 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment32 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +/* + * fbblt.c + */ +void +fbBlt (FbBits *src, + FbStride srcStride, + int srcX, + + FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp, + + Bool reverse, + Bool upsidedown); + +void +fbBlt24 (FbBits *srcLine, + FbStride srcStride, + int srcX, + + FbBits *dstLine, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + + Bool reverse, + Bool upsidedown); + +void +fbBltStip (FbStip *src, + FbStride srcStride, /* in FbStip units, not FbBits units */ + int srcX, + + FbStip *dst, + FbStride dstStride, /* in FbStip units, not FbBits units */ + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp); + +/* + * fbbltone.c + */ +void +fbBltOne (FbStip *src, + FbStride srcStride, + int srcX, + FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbBits fgand, + FbBits fbxor, + FbBits bgand, + FbBits bgxor); + +#ifdef FB_24BIT +void +fbBltOne24 (FbStip *src, + FbStride srcStride, /* FbStip units per scanline */ + int srcX, /* bit position of source */ + FbBits *dst, + FbStride dstStride, /* FbBits units per scanline */ + int dstX, /* bit position of dest */ + int dstBpp, /* bits per destination unit */ + + int width, /* width in bits of destination */ + int height, /* height in scanlines */ + + FbBits fgand, /* rrop values */ + FbBits fgxor, + FbBits bgand, + FbBits bgxor); +#endif + +void +fbBltPlane (FbBits *src, + FbStride srcStride, + int srcX, + int srcBpp, + + FbStip *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbStip fgand, + FbStip fgxor, + FbStip bgand, + FbStip bgxor, + Pixel planeMask); + +/* + * fbbstore.c + */ +void +fbSaveAreas(PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +fbRestoreAreas(PixmapPtr pPixmap, + RegionPtr prgnRestore, + int xorg, + int yorg, + WindowPtr pWin); + +/* + * fbcmap.c + */ +int +fbListInstalledColormaps(ScreenPtr pScreen, Colormap *pmaps); + +void +fbInstallColormap(ColormapPtr pmap); + +void +fbUninstallColormap(ColormapPtr pmap); + +void +fbResolveColor(unsigned short *pred, + unsigned short *pgreen, + unsigned short *pblue, + VisualPtr pVisual); + +Bool +fbInitializeColormap(ColormapPtr pmap); + +int +fbExpandDirectColors (ColormapPtr pmap, + int ndef, + xColorItem *indefs, + xColorItem *outdefs); + +Bool +fbCreateDefColormap(ScreenPtr pScreen); + +void +fbClearVisualTypes(void); + +Bool +fbSetVisualTypes (int depth, int visuals, int bitsPerRGB); + +Bool +fbSetVisualTypesAndMasks (int depth, int visuals, int bitsPerRGB, + Pixel redMask, Pixel greenMask, Pixel blueMask); + +Bool +fbInitVisuals (VisualPtr *visualp, + DepthPtr *depthp, + int *nvisualp, + int *ndepthp, + int *rootDepthp, + VisualID *defaultVisp, + unsigned long sizes, + int bitsPerRGB); + +/* + * fbcopy.c + */ + +typedef void (*fbCopyProc) (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pDstBox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyNtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopy1toN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyNto1 (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyRegion (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + RegionPtr pDstRegion, + int dx, + int dy, + fbCopyProc copyProc, + Pixel bitPlane, + void *closure); + +RegionPtr +fbDoCopy (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut, + fbCopyProc copyProc, + Pixel bitplane, + void *closure); + +RegionPtr +fbCopyArea (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut); + +RegionPtr +fbCopyPlane (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut, + unsigned long bitplane); + +/* + * fbfill.c + */ +void +fbFill (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int width, + int height); + +void +fbSolidBoxClipped (DrawablePtr pDrawable, + RegionPtr pClip, + int xa, + int ya, + int xb, + int yb, + FbBits and, + FbBits xor); + +/* + * fbfillrect.c + */ +void +fbPolyFillRect(DrawablePtr pDrawable, + GCPtr pGC, + int nrectInit, + xRectangle *prectInit); + +#define fbPolyFillArc miPolyFillArc + +#define fbFillPolygon miFillPolygon + +/* + * fbfillsp.c + */ +void +fbFillSpans (DrawablePtr pDrawable, + GCPtr pGC, + int nInit, + DDXPointPtr pptInit, + int *pwidthInit, + int fSorted); + + +/* + * fbgc.c + */ + +Bool +fbCreateGC(GCPtr pGC); + +void +fbPadPixmap (PixmapPtr pPixmap); + +void +fbValidateGC(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable); + +/* + * fbgetsp.c + */ +void +fbGetSpans(DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart); + +/* + * fbglyph.c + */ + +Bool +fbGlyphIn (RegionPtr pRegion, + int x, + int y, + int width, + int height); + +void +fbPolyGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase); + +void +fbImageGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase); + +/* + * fbimage.c + */ + +void +fbPutImage (DrawablePtr pDrawable, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage); + +void +fbPutZImage (DrawablePtr pDrawable, + RegionPtr pClip, + int alu, + FbBits pm, + int x, + int y, + int width, + int height, + FbStip *src, + FbStride srcStride); + +void +fbPutXYImage (DrawablePtr pDrawable, + RegionPtr pClip, + FbBits fg, + FbBits bg, + FbBits pm, + int alu, + Bool opaque, + + int x, + int y, + int width, + int height, + + FbStip *src, + FbStride srcStride, + int srcX); + +void +fbGetImage (DrawablePtr pDrawable, + int x, + int y, + int w, + int h, + unsigned int format, + unsigned long planeMask, + char *d); +/* + * fbline.c + */ + +void +fbZeroLine (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ppt); + +void +fbZeroSegment (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSegs); + +void +fbPolyLine (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ppt); + +void +fbFixCoordModePrevious (int npt, + DDXPointPtr ppt); + +void +fbPolySegment (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +#define fbPolyRectangle miPolyRectangle + +/* + * fbpict.c + */ + +Bool +fbPictureInit (ScreenPtr pScreen, + PictFormatPtr formats, + int nformats); + +/* + * fbpixmap.c + */ + +PixmapPtr +fbCreatePixmapBpp (ScreenPtr pScreen, int width, int height, int depth, int bpp); + +PixmapPtr +fbCreatePixmap (ScreenPtr pScreen, int width, int height, int depth); + +Bool +fbDestroyPixmap (PixmapPtr pPixmap); + +RegionPtr +fbPixmapToRegion(PixmapPtr pPix); + +/* + * fbpoint.c + */ + +void +fbDots (FbBits *dstOrig, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits andOrig, + FbBits xorOrig); + +void +fbPolyPoint (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + xPoint *pptInit); + +/* + * fbpush.c + */ +void +fbPushPattern (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + + int width, + int height); + +void +fbPushFill (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + int width, + int height); + +void +fbPush1toN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbPushImage (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + int width, + int height); + +void +fbPushPixels (GCPtr pGC, + PixmapPtr pBitmap, + DrawablePtr pDrawable, + int dx, + int dy, + int xOrg, + int yOrg); + + +/* + * fbscreen.c + */ + +Bool +fbCloseScreen (int indx, ScreenPtr pScreen); + +Bool +fbRealizeFont(ScreenPtr pScreen, FontPtr pFont); + +Bool +fbUnrealizeFont(ScreenPtr pScreen, FontPtr pFont); + +void +fbQueryBestSize (int class, + unsigned short *width, unsigned short *height, + ScreenPtr pScreen); + +#ifndef FB_OLD_SCREEN +PixmapPtr +_fbGetWindowPixmap (WindowPtr pWindow); + +void +_fbSetWindowPixmap (WindowPtr pWindow, PixmapPtr pPixmap); +#endif + +Bool +fbSetupScreen(ScreenPtr pScreen, + pointer pbits, /* pointer to screen bitmap */ + int xsize, /* in pixels */ + int ysize, + int dpix, /* dots per inch */ + int dpiy, + int width, /* pixel width of frame buffer */ + int bpp); /* bits per pixel of frame buffer */ + +Bool +fbFinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +Bool +fbScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +void +fbInitializeBackingStore (ScreenPtr pScreen); + +/* + * fbseg.c + */ +typedef void FbBres (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +FbBres fbBresSolid, fbBresDash, fbBresFill, fbBresFillDash; +/* + * fbsetsp.c + */ + +void +fbSetSpans (DrawablePtr pDrawable, + GCPtr pGC, + char *src, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted); + +FbBres * +fbSelectBres (DrawablePtr pDrawable, + GCPtr pGC); + +void +fbBres (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbSegment (DrawablePtr pDrawable, + GCPtr pGC, + int xa, + int ya, + int xb, + int yb, + Bool drawLast, + int *dashOffset); + + +/* + * fbsolid.c + */ + +void +fbSolid (FbBits *dst, + FbStride dstStride, + int dstX, + int bpp, + + int width, + int height, + + FbBits and, + FbBits xor); + +#ifdef FB_24BIT +void +fbSolid24 (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits and, + FbBits xor); +#endif + +/* + * fbstipple.c + */ + +void +fbTransparentSpan (FbBits *dst, + FbBits stip, + FbBits fgxor, + int n); + +void +fbEvenStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipHeight, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +void +fbOddStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipWidth, + int stipHeight, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +void +fbStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipWidth, + int stipHeight, + Bool even, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +/* + * fbtile.c + */ + +void +fbEvenTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + int tileHeight, + + int alu, + FbBits pm, + int xRot, + int yRot); + +void +fbOddTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + FbStride tileStride, + int tileWidth, + int tileHeight, + + int alu, + FbBits pm, + int bpp, + + int xRot, + int yRot); + +void +fbTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + FbStride tileStride, + int tileWidth, + int tileHeight, + + int alu, + FbBits pm, + int bpp, + + int xRot, + int yRot); + +/* + * fbutil.c + */ +FbBits +fbReplicatePixel (Pixel p, int bpp); + +void +fbReduceRasterOp (int rop, FbBits fg, FbBits pm, FbBits *andp, FbBits *xorp); + +/* + * fbwindow.c + */ + +Bool +fbCreateWindow(WindowPtr pWin); + +Bool +fbDestroyWindow(WindowPtr pWin); + +Bool +fbMapWindow(WindowPtr pWindow); + +Bool +fbPositionWindow(WindowPtr pWin, int x, int y); + +Bool +fbUnmapWindow(WindowPtr pWindow); + +void +fbCopyWindowProc (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +Bool +fbChangeWindowAttributes(WindowPtr pWin, unsigned long mask); + +void +fbFillRegionSolid (DrawablePtr pDrawable, + RegionPtr pRegion, + FbBits and, + FbBits xor); + +void +fbFillRegionTiled (DrawablePtr pDrawable, + RegionPtr pRegion, + PixmapPtr pTile); + +void +fbPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + + +#endif /* _FB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb24_32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb24_32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fb24_32.h (revision 51223) @@ -0,0 +1,53 @@ +/* + * $XFree86$ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _FB24_32_H_ +#define _FB24_32_H_ + +Bool +fb24_32FinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +Bool +fb24_32ScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbbits.h (revision 51223) @@ -0,0 +1,964 @@ +/* + * $XFree86$ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file defines functions for drawing some primitives using + * underlying datatypes instead of masks + */ + +#define isClipped(c,ul,lr) ((((c) - (ul)) | ((lr) - (c))) & 0x80008000) + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifdef BITSMUL +#define MUL BITSMUL +#else +#define MUL 1 +#endif + +#ifdef BITSSTORE +#define STORE(b,x) BITSSTORE(b,x) +#else +#define STORE(b,x) (*(b) = (x)) +#endif + +#ifdef BITSRROP +#define RROP(b,a,x) BITSRROP(b,a,x) +#else +#define RROP(b,a,x) (*(b) = FbDoRRop (*(b), (a), (x))) +#endif + +#ifdef BITSUNIT +#define UNIT BITSUNIT +#define USE_SOLID +#else +#define UNIT BITS +#endif + +/* + * Define the following before including this file: + * + * BRESSOLID name of function for drawing a solid segment + * BRESDASH name of function for drawing a dashed segment + * DOTS name of function for drawing dots + * ARC name of function for drawing a solid arc + * BITS type of underlying unit + */ + +#ifdef BRESSOLID +void +BRESSOLID (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x1, + int y1, + int e, + int e1, + int e3, + int len) +{ + FbBits *dst; + FbStride dstStride; + int dstBpp; + int dstXoff, dstYoff; + FbGCPrivPtr pPriv = fbGetGCPrivate (pGC); + UNIT *bits; + FbStride bitsStride; + FbStride majorStep, minorStep; + BITS xor = (BITS) pPriv->xor; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bits = ((UNIT *) (dst + ((y1 + dstYoff) * dstStride))) + (x1 + dstXoff) * MUL; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + if (signdy < 0) + bitsStride = -bitsStride; + if (axis == X_AXIS) + { + majorStep = signdx * MUL; + minorStep = bitsStride; + } + else + { + majorStep = bitsStride; + minorStep = signdx * MUL; + } + while (len--) + { + STORE(bits,xor); + bits += majorStep; + e += e1; + if (e >= 0) + { + bits += minorStep; + e += e3; + } + } +} +#endif + +#ifdef BRESDASH +void +BRESDASH (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x1, + int y1, + int e, + int e1, + int e3, + int len) +{ + FbBits *dst; + FbStride dstStride; + int dstBpp; + int dstXoff, dstYoff; + FbGCPrivPtr pPriv = fbGetGCPrivate (pGC); + UNIT *bits; + FbStride bitsStride; + FbStride majorStep, minorStep; + BITS xorfg, xorbg; + FbDashDeclare; + int dashlen; + Bool even; + Bool doOdd; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + doOdd = pGC->lineStyle == LineDoubleDash; + xorfg = (BITS) pPriv->xor; + xorbg = (BITS) pPriv->bgxor; + + FbDashInit (pGC, pPriv, dashOffset, dashlen, even); + + bits = ((UNIT *) (dst + ((y1 + dstYoff) * dstStride))) + (x1 + dstXoff) * MUL; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + if (signdy < 0) + bitsStride = -bitsStride; + if (axis == X_AXIS) + { + majorStep = signdx * MUL; + minorStep = bitsStride; + } + else + { + majorStep = bitsStride; + minorStep = signdx * MUL; + } + if (dashlen >= len) + dashlen = len; + if (doOdd) + { + if (!even) + goto doubleOdd; + for (;;) + { + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorfg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextEven(dashlen); + + if (dashlen >= len) + dashlen = len; +doubleOdd: + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorbg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextOdd(dashlen); + + if (dashlen >= len) + dashlen = len; + } + } + else + { + if (!even) + goto onOffOdd; + for (;;) + { + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorfg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextEven (dashlen); + + if (dashlen >= len) + dashlen = len; +onOffOdd: + len -= dashlen; + while (dashlen--) + { + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextOdd (dashlen); + + if (dashlen >= len) + dashlen = len; + } + } +} +#endif + +#ifdef DOTS +void +DOTS (FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *ptsOrig, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor) +{ + INT32 *pts = (INT32 *) ptsOrig; + UNIT *bits = (UNIT *) dst; + UNIT *point; + BITS bxor = (BITS) xor; + BITS band = (BITS) and; + FbStride bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + INT32 ul, lr; + INT32 pt; + + ul = coordToInt(pBox->x1 - xorg, pBox->y1 - yorg); + lr = coordToInt(pBox->x2 - xorg - 1, pBox->y2 - yorg - 1); + + bits += bitsStride * (yorg + yoff) + (xorg + xoff) * MUL; + + if (and == 0) + { + while (npt--) + { + pt = *pts++; + if (!isClipped(pt,ul,lr)) + { + point = bits + intToY(pt) * bitsStride + intToX(pt) * MUL; + STORE(point,bxor); + } + } + } + else + { + while (npt--) + { + pt = *pts++; + if (!isClipped(pt,ul,lr)) + { + point = bits + intToY(pt) * bitsStride + intToX(pt) * MUL; + RROP(point,band,bxor); + } + } + } +} +#endif + +#ifdef ARC + +#define ARCCOPY(d) STORE(d,xorBits) +#define ARCRROP(d) RROP(d,andBits,xorBits) + +void +ARC (FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int drawX, + int drawY, + FbBits and, + FbBits xor) +{ + UNIT *bits; + FbStride bitsStride; + miZeroArcRec info; + Bool do360; + int x; + UNIT *yorgp, *yorgop; + BITS andBits, xorBits; + int yoffset, dyoffset; + int y, a, b, d, mask; + int k1, k3, dx, dy; + + bits = (UNIT *) dst; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + andBits = (BITS) and; + xorBits = (BITS) xor; + do360 = miZeroArcSetup(arc, &info, TRUE); + yorgp = bits + ((info.yorg + drawY) * bitsStride); + yorgop = bits + ((info.yorgo + drawY) * bitsStride); + info.xorg = (info.xorg + drawX) * MUL; + info.xorgo = (info.xorgo + drawX) * MUL; + MIARCSETUP(); + yoffset = y ? bitsStride : 0; + dyoffset = 0; + mask = info.initialMask; + + if (!(arc->width & 1)) + { + if (andBits == 0) + { + if (mask & 2) + ARCCOPY(yorgp + info.xorgo); + if (mask & 8) + ARCCOPY(yorgop + info.xorgo); + } + else + { + if (mask & 2) + ARCRROP(yorgp + info.xorgo); + if (mask & 8) + ARCRROP(yorgop + info.xorgo); + } + } + if (!info.end.x || !info.end.y) + { + mask = info.end.mask; + info.end = info.altend; + } + if (do360 && (arc->width == arc->height) && !(arc->width & 1)) + { + int xoffset = bitsStride; + UNIT *yorghb = yorgp + (info.h * bitsStride) + info.xorg; + UNIT *yorgohb = yorghb - info.h * MUL; + + yorgp += info.xorg; + yorgop += info.xorg; + yorghb += info.h * MUL; + while (1) + { + if (andBits == 0) + { + ARCCOPY(yorgp + yoffset + x * MUL); + ARCCOPY(yorgp + yoffset - x * MUL); + ARCCOPY(yorgop - yoffset - x * MUL); + ARCCOPY(yorgop - yoffset + x * MUL); + } + else + { + ARCRROP(yorgp + yoffset + x * MUL); + ARCRROP(yorgp + yoffset - x * MUL); + ARCRROP(yorgop - yoffset - x * MUL); + ARCRROP(yorgop - yoffset + x * MUL); + } + if (a < 0) + break; + if (andBits == 0) + { + ARCCOPY(yorghb - xoffset - y * MUL); + ARCCOPY(yorgohb - xoffset + y * MUL); + ARCCOPY(yorgohb + xoffset + y * MUL); + ARCCOPY(yorghb + xoffset - y * MUL); + } + else + { + ARCRROP(yorghb - xoffset - y * MUL); + ARCRROP(yorgohb - xoffset + y * MUL); + ARCRROP(yorgohb + xoffset + y * MUL); + ARCRROP(yorghb + xoffset - y * MUL); + } + xoffset += bitsStride; + MIARCCIRCLESTEP(yoffset += bitsStride;); + } + yorgp -= info.xorg; + yorgop -= info.xorg; + x = info.w; + yoffset = info.h * bitsStride; + } + else if (do360) + { + while (y < info.h || x < info.w) + { + MIARCOCTANTSHIFT(dyoffset = bitsStride;); + if (andBits == 0) + { + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + else + { + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + MIARCSTEP(yoffset += dyoffset;, yoffset += bitsStride;); + } + } + else + { + while (y < info.h || x < info.w) + { + MIARCOCTANTSHIFT(dyoffset = bitsStride;); + if ((x == info.start.x) || (y == info.start.y)) + { + mask = info.start.mask; + info.start = info.altstart; + } + if (andBits == 0) + { + if (mask & 1) + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 2) + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 4) + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + else + { + if (mask & 1) + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 2) + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 4) + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + if ((x == info.end.x) || (y == info.end.y)) + { + mask = info.end.mask; + info.end = info.altend; + } + MIARCSTEP(yoffset += dyoffset;, yoffset += bitsStride;); + } + } + if ((x == info.start.x) || (y == info.start.y)) + mask = info.start.mask; + if (andBits == 0) + { + if (mask & 1) + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 4) + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + if (arc->height & 1) + { + if (mask & 2) + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + } + else + { + if (mask & 1) + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 4) + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + if (arc->height & 1) + { + if (mask & 2) + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + } +} +#undef ARCCOPY +#undef ARCRROP +#endif + +#ifdef GLYPH +#if BITMAP_BIT_ORDER == LSBFirst +# define WRITE_ADDR1(n) (n) +# define WRITE_ADDR2(n) (n) +# define WRITE_ADDR4(n) (n) +#else +# define WRITE_ADDR1(n) ((n) ^ 3) +# define WRITE_ADDR2(n) ((n) ^ 2) +# define WRITE_ADDR4(n) ((n)) +#endif + +#define WRITE1(d,n,fg) ((d)[WRITE_ADDR1(n)] = (BITS) (fg)) + +#ifdef BITS2 +# define WRITE2(d,n,fg) (*((BITS2 *) &((d)[WRITE_ADDR2(n)])) = (BITS2) (fg)) +#else +# define WRITE2(d,n,fg) WRITE1(d,(n)+1,WRITE1(d,n,fg)) +#endif + +#ifdef BITS4 +# define WRITE4(d,n,fg) (*((BITS4 *) &((d)[WRITE_ADDR4(n)])) = (BITS4) (fg)) +#else +# define WRITE4(d,n,fg) WRITE2(d,(n)+2,WRITE2(d,n,fg)) +#endif + +void +GLYPH (FbBits *dstBits, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int x, + int height) +{ + int lshift; + FbStip bits; + BITS *dstLine; + BITS *dst; + int n; + int shift; + + dstLine = (BITS *) dstBits; + dstLine += x & ~3; + dstStride *= (sizeof (FbBits) / sizeof (BITS)); + shift = x & 3; + lshift = 4 - shift; + while (height--) + { + bits = *stipple++; + dst = (BITS *) dstLine; + n = lshift; + while (bits) + { + switch (FbStipMoveLsb (FbLeftStipBits (bits, n), 4, n)) { + case 0: + break; + case 1: + WRITE1(dst,0,fg); + break; + case 2: + WRITE1(dst,1,fg); + break; + case 3: + WRITE2(dst,0,fg); + break; + case 4: + WRITE1(dst,2,fg); + break; + case 5: + WRITE1(dst,0,fg); + WRITE1(dst,2,fg); + break; + case 6: + WRITE1(dst,1,fg); + WRITE1(dst,2,fg); + break; + case 7: + WRITE2(dst,0,fg); + WRITE1(dst,2,fg); + break; + case 8: + WRITE1(dst,3,fg); + break; + case 9: + WRITE1(dst,0,fg); + WRITE1(dst,3,fg); + break; + case 10: + WRITE1(dst,1,fg); + WRITE1(dst,3,fg); + break; + case 11: + WRITE2(dst,0,fg); + WRITE1(dst,3,fg); + break; + case 12: + WRITE2(dst,2,fg); + break; + case 13: + WRITE1(dst,0,fg); + WRITE2(dst,2,fg); + break; + case 14: + WRITE1(dst,1,fg); + WRITE2(dst,2,fg); + break; + case 15: + WRITE4(dst,0,fg); + break; + } + bits = FbStipLeft (bits, n); + n = 4; + dst += 4; + } + dstLine += dstStride; + } +} +#undef WRITE_ADDR1 +#undef WRITE_ADDR2 +#undef WRITE_ADDR4 +#undef WRITE1 +#undef WRITE2 +#undef WRITE4 + +#endif + +#ifdef POLYLINE +void +POLYLINE (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig) +{ + INT32 *pts = (INT32 *) ptsOrig; + int xoff = pDrawable->x; + int yoff = pDrawable->y; + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + BoxPtr pBox = REGION_EXTENTS (pDrawable->pScreen, fbGetCompositeClip (pGC)); + + FbBits *dst; + int dstStride; + int dstBpp; + int dstXoff, dstYoff; + + UNIT *bits, *bitsBase; + FbStride bitsStride; + BITS xor = fbGetGCPrivate(pGC)->xor; + BITS and = fbGetGCPrivate(pGC)->and; + int dashoffset = 0; + + INT32 ul, lr; + INT32 pt1, pt2; + + int e, e1, e3, len; + int stepmajor, stepminor; + int octant; + + if (mode == CoordModePrevious) + fbFixCoordModePrevious (npt, ptsOrig); + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + bitsBase = ((UNIT *) dst) + (yoff + dstYoff) * bitsStride + (xoff + dstXoff) * MUL; + ul = coordToInt(pBox->x1 - xoff, pBox->y1 - yoff); + lr = coordToInt(pBox->x2 - xoff - 1, pBox->y2 - yoff - 1); + + pt1 = *pts++; + npt--; + pt2 = *pts++; + npt--; + for (;;) + { + if (isClipped (pt1, ul, lr) | isClipped (pt2, ul, lr)) + { + fbSegment (pDrawable, pGC, + intToX(pt1) + xoff, intToY(pt1) + yoff, + intToX(pt2) + xoff, intToY(pt2) + yoff, + npt == 0 && pGC->capStyle != CapNotLast, + &dashoffset); + if (!npt) + return; + pt1 = pt2; + pt2 = *pts++; + npt--; + } + else + { + bits = bitsBase + intToY(pt1) * bitsStride + intToX(pt1) * MUL; + for (;;) + { + CalcLineDeltas (intToX(pt1), intToY(pt1), + intToX(pt2), intToY(pt2), + len, e1, stepmajor, stepminor, 1, bitsStride, + octant); + stepmajor *= MUL; + if (len < e1) + { + e3 = len; + len = e1; + e1 = e3; + + e3 = stepminor; + stepminor = stepmajor; + stepmajor = e3; + SetYMajorOctant(octant); + } + e = -len; + e1 <<= 1; + e3 = e << 1; + FIXUP_ERROR (e, octant, bias); + if (and == 0) + { + while (len--) + { + STORE(bits,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + else + { + while (len--) + { + RROP(bits,and,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + if (!npt) + { + if (pGC->capStyle != CapNotLast && + pt2 != *((INT32 *) ptsOrig)) + { + RROP(bits,and,xor); + } + return; + } + pt1 = pt2; + pt2 = *pts++; + --npt; + if (isClipped (pt2, ul, lr)) + break; + } + } + } +} +#endif + +#ifdef POLYSEGMENT +void +POLYSEGMENT (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg) +{ + INT32 *pts = (INT32 *) pseg; + int xoff = pDrawable->x; + int yoff = pDrawable->y; + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + BoxPtr pBox = REGION_EXTENTS (pDrawable->pScreen, fbGetCompositeClip (pGC)); + + FbBits *dst; + int dstStride; + int dstBpp; + int dstXoff, dstYoff; + + UNIT *bits, *bitsBase; + FbStride bitsStride; + FbBits xorBits = fbGetGCPrivate(pGC)->xor; + FbBits andBits = fbGetGCPrivate(pGC)->and; + BITS xor = xorBits; + BITS and = andBits; + int dashoffset = 0; + + INT32 ul, lr; + INT32 pt1, pt2; + + int e, e1, e3, len; + int stepmajor, stepminor; + int octant; + Bool capNotLast; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + bitsBase = ((UNIT *) dst) + (yoff + dstYoff) * bitsStride + (xoff + dstXoff) * MUL; + ul = coordToInt(pBox->x1 - xoff, pBox->y1 - yoff); + lr = coordToInt(pBox->x2 - xoff - 1, pBox->y2 - yoff - 1); + + bits += bitsStride * yoff + xoff * MUL; + + capNotLast = pGC->capStyle == CapNotLast; + + while (nseg--) + { + pt1 = *pts++; + pt2 = *pts++; + if (isClipped (pt1, ul, lr) | isClipped (pt2, ul, lr)) + { + fbSegment (pDrawable, pGC, + intToX(pt1) + xoff, intToY(pt1) + yoff, + intToX(pt2) + xoff, intToY(pt2) + yoff, + !capNotLast, &dashoffset); + } + else + { + CalcLineDeltas (intToX(pt1), intToY(pt1), + intToX(pt2), intToY(pt2), + len, e1, stepmajor, stepminor, 1, bitsStride, + octant); + if (e1 == 0 && len > 3 +#if MUL != 1 + && FbCheck24Pix(and) && FbCheck24Pix(xor) +#endif + ) + { + int x1, x2; + FbBits *dstLine; + int dstX, width; + FbBits startmask, endmask; + int nmiddle; + + if (stepmajor < 0) + { + x1 = intToX(pt2); + x2 = intToX(pt1) + 1; + if (capNotLast) + x1++; + } + else + { + x1 = intToX(pt1); + x2 = intToX(pt2); + if (!capNotLast) + x2++; + } + dstX = (x1 + xoff + dstXoff) * (sizeof (UNIT) * 8 * MUL); + width = (x2 - x1) * (sizeof (UNIT) * 8 * MUL); + + dstLine = dst + (intToY(pt1) + yoff + dstYoff) * dstStride; + dstLine += dstX >> FB_SHIFT; + dstX &= FB_MASK; + FbMaskBits (dstX, width, startmask, nmiddle, endmask); + if (startmask) + { + *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, startmask); + dstLine++; + } + if (!andBits) + while (nmiddle--) + *dstLine++ = xorBits; + else + while (nmiddle--) + { + *dstLine = FbDoRRop (*dstLine, andBits, xorBits); + dstLine++; + } + if (endmask) + *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, endmask); + } + else + { + stepmajor *= MUL; + bits = bitsBase + intToY(pt1) * bitsStride + intToX(pt1) * MUL; + if (len < e1) + { + e3 = len; + len = e1; + e1 = e3; + + e3 = stepminor; + stepminor = stepmajor; + stepmajor = e3; + SetYMajorOctant(octant); + } + e = -len; + e1 <<= 1; + e3 = e << 1; + FIXUP_ERROR (e, octant, bias); + if (!capNotLast) + len++; + if (and == 0) + { + while (len--) + { + STORE(bits,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + else + { + while (len--) + { + RROP(bits,and,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + } + } + } +} +#endif + +#undef MUL +#undef STORE +#undef RROP +#undef UNIT +#undef USE_SOLID + +#undef isClipped Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbdevhw.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbdevhw.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbdevhw.h (revision 51223) @@ -0,0 +1,61 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/fbdevhw/fbdevhw.h,v 1.11 2001/10/01 13:44:12 eich Exp $ */ + +#ifndef _FBDEVHW_H_ +#define _FBDEVHW_H_ + +#include "xf86str.h" +#include "colormapst.h" + +#define FBDEVHW_PACKED_PIXELS 0 /* Packed Pixels */ +#define FBDEVHW_PLANES 1 /* Non interleaved planes */ +#define FBDEVHW_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FBDEVHW_TEXT 3 /* Text/attributes */ +#define FBDEVHW_VGA_PLANES 4 /* EGA/VGA planes */ + +Bool fbdevHWGetRec(ScrnInfoPtr pScrn); +void fbdevHWFreeRec(ScrnInfoPtr pScrn); + +Bool fbdevHWProbe(pciVideoPtr pPci, char *device, char **namep); +Bool fbdevHWInit(ScrnInfoPtr pScrn, pciVideoPtr pPci, char *device); + +char* fbdevHWGetName(ScrnInfoPtr pScrn); +int fbdevHWGetDepth(ScrnInfoPtr pScrn, int *fbbpp); +int fbdevHWGetLineLength(ScrnInfoPtr pScrn); +int fbdevHWGetType(ScrnInfoPtr pScrn); +int fbdevHWGetVidmem(ScrnInfoPtr pScrn); + +void* fbdevHWMapVidmem(ScrnInfoPtr pScrn); +int fbdevHWLinearOffset(ScrnInfoPtr pScrn); +Bool fbdevHWUnmapVidmem(ScrnInfoPtr pScrn); +void* fbdevHWMapMMIO(ScrnInfoPtr pScrn); +Bool fbdevHWUnmapMMIO(ScrnInfoPtr pScrn); + +void fbdevHWSetVideoModes(ScrnInfoPtr pScrn); +DisplayModePtr fbdevHWGetBuildinMode(ScrnInfoPtr pScrn); +void fbdevHWUseBuildinMode(ScrnInfoPtr pScrn); +Bool fbdevHWModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode); +void fbdevHWSave(ScrnInfoPtr pScrn); +void fbdevHWRestore(ScrnInfoPtr pScrn); + +void fbdevHWLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); + +ModeStatus fbdevHWValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags); +Bool fbdevHWSwitchMode(int scrnIndex, DisplayModePtr mode, int flags); +void fbdevHWAdjustFrame(int scrnIndex, int x, int y, int flags); +Bool fbdevHWEnterVT(int scrnIndex, int flags); +void fbdevHWLeaveVT(int scrnIndex, int flags); +void fbdevHWDPMSSet(ScrnInfoPtr pScrn, int mode, int flags); + +Bool fbdevHWSaveScreen(ScreenPtr pScreen, int mode); + +xf86SwitchModeProc *fbdevHWSwitchModeWeak(void); +xf86AdjustFrameProc *fbdevHWAdjustFrameWeak(void); +xf86EnterVTProc *fbdevHWEnterVTWeak(void); +xf86LeaveVTProc *fbdevHWLeaveVTWeak(void); +xf86ValidModeProc *fbdevHWValidModeWeak(void); +xf86DPMSSetProc *fbdevHWDPMSSetWeak(void); +xf86LoadPaletteProc *fbdevHWLoadPaletteWeak(void); +SaveScreenProcPtr fbdevHWSaveScreenWeak(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbedgeimp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbedgeimp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbedgeimp.h (revision 51223) @@ -0,0 +1,143 @@ +/* + * $Id: fbedgeimp.h,v 1.4 2005/08/30 03:05:21 anholt Exp $ + * + * Copyright © 2004 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef rasterizeSpan +#endif + +static void +rasterizeEdges (FbBits *buf, + int width, + int stride, + RenderEdge *l, + RenderEdge *r, + xFixed t, + xFixed b) +{ + xFixed y = t; + FbBits *line; + + line = buf + xFixedToInt (y) * stride; + + for (;;) + { + xFixed lx, rx; + int lxi, rxi; + + /* clip X */ + lx = l->x; + if (lx < 0) + lx = 0; + rx = r->x; + if (xFixedToInt (rx) >= width) + rx = IntToxFixed (width); + + /* Skip empty (or backwards) sections */ + if (rx > lx) + { + + /* Find pixel bounds for span */ + lxi = xFixedToInt (lx); + rxi = xFixedToInt (rx); + +#if N_BITS == 1 + { + FbBits *a = line; + FbBits startmask, endmask; + int nmiddle; + int width = rxi - lxi; + int x = lxi; + + a += x >> FB_SHIFT; + x &= FB_MASK; + + FbMaskBits (x, width, startmask, nmiddle, endmask); + if (startmask) + *a++ |= startmask; + while (nmiddle--) + *a++ = FB_ALLONES; + if (endmask) + *a |= endmask; + } +#else + { + DefineAlpha(line,lxi); + int lxs, rxs; + + /* Sample coverage for edge pixels */ + lxs = RenderSamplesX (lx, N_BITS); + rxs = RenderSamplesX (rx, N_BITS); + + /* Add coverage across row */ + if (lxi == rxi) + { + AddAlpha (rxs - lxs); + } + else + { + int xi; + + AddAlpha (N_X_FRAC(N_BITS) - lxs); + StepAlpha; + for (xi = lxi + 1; xi < rxi; xi++) + { + AddAlpha (N_X_FRAC(N_BITS)); + StepAlpha; + } + /* Do not add in a 0 alpha here. This check is necessary + * to avoid a buffer overrun when rx is exactly on a pixel + * boundary. + */ + if (rxs != 0) + AddAlpha (rxs); + } + } +#endif + } + + if (y == b) + break; + +#if N_BITS > 1 + if (xFixedFrac (y) != Y_FRAC_LAST(N_BITS)) + { + RenderEdgeStepSmall (l); + RenderEdgeStepSmall (r); + y += STEP_Y_SMALL(N_BITS); + } + else +#endif + { + RenderEdgeStepBig (l); + RenderEdgeStepBig (r); + y += STEP_Y_BIG(N_BITS); + line += stride; + } + } +} + +#undef rasterizeSpan Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbmmx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbmmx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbmmx.h (revision 51223) @@ -0,0 +1,220 @@ +/* + * Copyright © 2004 Red Hat, Inc. + * Copyright © 2005 Trolltech AS + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Red Hat not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Red Hat makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Author: Søren Sandmann (sandmann@redhat.com) + * Lars Knoll (lars@trolltech.com) + * + * Based on work by Owen Taylor + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifdef USE_MMX + +#if !defined(__amd64__) && !defined(__x86_64__) +Bool fbHaveMMX(void); +#else +#define fbHaveMMX() TRUE +#endif + +#else +#define fbHaveMMX() FALSE +#endif + +#ifdef USE_MMX + +void fbComposeSetupMMX(void); + +void fbCompositeSolidMask_nx8888x0565Cmmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrcAdd_8888x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8888x8888Cmmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrcAdd_8000x8000mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888RevNPx8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888RevNPx0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolid_nx8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolid_nx0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8x0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888x8x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +Bool fbCopyAreammx (DrawablePtr pSrc, + DrawablePtr pDst, + int src_x, + int src_y, + int dst_x, + int dst_y, + int width, + int height); +void fbCompositeCopyAreammx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +Bool fbSolidFillmmx (DrawablePtr pDraw, + int x, + int y, + int width, + int height, + FbBits xor); + +#endif /* USE_MMX */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fboverlay.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fboverlay.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fboverlay.h (revision 51223) @@ -0,0 +1,129 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fboverlay.h,v 1.4tsi Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _FBOVERLAY_H_ +#define _FBOVERLAY_H_ + +extern int fbOverlayGeneration; +extern int fbOverlayScreenPrivateIndex; /* XXX should be static */ +extern int fbOverlayGetScreenPrivateIndex(void); + +#ifndef FB_OVERLAY_MAX +#define FB_OVERLAY_MAX 2 +#endif + +typedef void (*fbOverlayPaintKeyProc) (DrawablePtr, RegionPtr, CARD32, int); + +typedef struct _fbOverlayLayer { + union { + struct { + pointer pbits; + int width; + int depth; + } init; + struct { + PixmapPtr pixmap; + RegionRec region; + } run; + } u; + CARD32 key; /* special pixel value */ +} FbOverlayLayer; + +typedef struct _fbOverlayScrPriv { + int nlayers; + fbOverlayPaintKeyProc PaintKey; + fbCopyProc CopyWindow; + FbOverlayLayer layer[FB_OVERLAY_MAX]; +} FbOverlayScrPrivRec, *FbOverlayScrPrivPtr; + +#define fbOverlayGetScrPriv(s) \ + ((fbOverlayGetScreenPrivateIndex() != -1) ? \ + (s)->devPrivates[fbOverlayGetScreenPrivateIndex()].ptr : NULL) +Bool +fbOverlayCreateWindow(WindowPtr pWin); + +Bool +fbOverlayCloseScreen (int iScreen, ScreenPtr pScreen); + +int +fbOverlayWindowLayer(WindowPtr pWin); + +Bool +fbOverlayCreateScreenResources(ScreenPtr pScreen); + +void +fbOverlayPaintKey (DrawablePtr pDrawable, + RegionPtr pRegion, + CARD32 pixel, + int layer); +void +fbOverlayUpdateLayerRegion (ScreenPtr pScreen, + int layer, + RegionPtr prgn); + + +void +fbOverlayCopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +void +fbOverlayWindowExposures (WindowPtr pWin, + RegionPtr prgn, + RegionPtr other_exposed); + +void +fbOverlayPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + + +Bool +fbOverlaySetupScreen(ScreenPtr pScreen, + pointer pbits1, + pointer pbits2, + int xsize, + int ysize, + int dpix, + int dpiy, + int width1, + int width2, + int bpp1, + int bpp2); + +Bool +fbOverlayFinishScreenInit(ScreenPtr pScreen, + pointer pbits1, + pointer pbits2, + int xsize, + int ysize, + int dpix, + int dpiy, + int width1, + int width2, + int bpp1, + int bpp2, + int depth1, + int depth2); + +#endif /* _FBOVERLAY_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpict.h (revision 51223) @@ -0,0 +1,612 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fbpict.h,v 1.7 2001/07/18 10:15:02 keithp Exp $ + * + * Copyright © 2000 Keith Packard, member of The XFree86 Project, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _FBPICT_H_ +#define _FBPICT_H_ + +#include "renderedge.h" + +#define FbIntMult(a,b,t) ( (t) = (a) * (b) + 0x80, ( ( ( (t)>>8 ) + (t) )>>8 ) ) +#define FbIntDiv(a,b) (((CARD16) (a) * 255) / (b)) + +#define FbGet8(v,i) ((CARD16) (CARD8) ((v) >> i)) + +/* + * There are two ways of handling alpha -- either as a single unified value or + * a separate value for each component, hence each macro must have two + * versions. The unified alpha version has a 'U' at the end of the name, + * the component version has a 'C'. Similarly, functions which deal with + * this difference will have two versions using the same convention. + */ + +#define FbOverU(x,y,i,a,t) ((t) = FbIntMult(FbGet8(y,i),(a),(t)) + FbGet8(x,i),\ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + +#define FbOverC(x,y,i,a,t) ((t) = FbIntMult(FbGet8(y,i),FbGet8(a,i),(t)) + FbGet8(x,i),\ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + +#define FbInU(x,i,a,t) ((CARD32) FbIntMult(FbGet8(x,i),(a),(t)) << (i)) + +#define FbInC(x,i,a,t) ((CARD32) FbIntMult(FbGet8(x,i),FbGet8(a,i),(t)) << (i)) + +#define FbGen(x,y,i,ax,ay,t,u,v) ((t) = (FbIntMult(FbGet8(y,i),ay,(u)) + \ + FbIntMult(FbGet8(x,i),ax,(v))),\ + (CARD32) ((CARD8) ((t) | \ + (0 - ((t) >> 8)))) << (i)) + +#define FbAdd(x,y,i,t) ((t) = FbGet8(x,i) + FbGet8(y,i), \ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + + +#define Alpha(x) ((x) >> 24) +#define Red(x) (((x) >> 16) & 0xff) +#define Green(x) (((x) >> 8) & 0xff) +#define Blue(x) ((x) & 0xff) + +#define fbComposeGetSolid(pict, bits, fmt) { \ + FbBits *__bits__; \ + FbStride __stride__; \ + int __bpp__; \ + int __xoff__,__yoff__; \ +\ + fbGetDrawable((pict)->pDrawable,__bits__,__stride__,__bpp__,__xoff__,__yoff__); \ + switch (__bpp__) { \ + case 32: \ + (bits) = *(CARD32 *) __bits__; \ + break; \ + case 24: \ + (bits) = Fetch24 ((CARD8 *) __bits__); \ + break; \ + case 16: \ + (bits) = *(CARD16 *) __bits__; \ + (bits) = cvt0565to8888(bits); \ + break; \ + default: \ + return; \ + } \ + /* If necessary, convert RGB <--> BGR. */ \ + if (PICT_FORMAT_TYPE((pict)->format) != PICT_FORMAT_TYPE(fmt)) \ + { \ + (bits) = (((bits) & 0xff000000) | \ + (((bits) & 0x00ff0000) >> 16) | \ + (((bits) & 0x0000ff00) >> 0) | \ + (((bits) & 0x000000ff) << 16)); \ + } \ + /* manage missing src alpha */ \ + if ((pict)->pFormat->direct.alphaMask == 0) \ + (bits) |= 0xff000000; \ +} + +#define fbComposeGetStart(pict,x,y,type,stride,line,mul) {\ + FbBits *__bits__; \ + FbStride __stride__; \ + int __bpp__; \ + int __xoff__,__yoff__; \ +\ + fbGetDrawable((pict)->pDrawable,__bits__,__stride__,__bpp__,__xoff__,__yoff__); \ + (stride) = __stride__ * sizeof (FbBits) / sizeof (type); \ + (line) = ((type *) __bits__) + (stride) * ((y) + __yoff__) + (mul) * ((x) + __xoff__); \ +} +#define cvt8888to0565(s) ((((s) >> 3) & 0x001f) | \ + (((s) >> 5) & 0x07e0) | \ + (((s) >> 8) & 0xf800)) +#define cvt0565to8888(s) (((((s) << 3) & 0xf8) | (((s) >> 2) & 0x7)) | \ + ((((s) << 5) & 0xfc00) | (((s) >> 1) & 0x300)) | \ + ((((s) << 8) & 0xf80000) | (((s) << 3) & 0x70000))) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define Fetch24(a) ((unsigned long) (a) & 1 ? \ + ((*(a) << 16) | *((CARD16 *) ((a)+1))) : \ + ((*((CARD16 *) (a)) << 8) | *((a)+2))) +#define Store24(a,v) ((unsigned long) (a) & 1 ? \ + ((*(a) = (CARD8) ((v) >> 16)), \ + (*((CARD16 *) ((a)+1)) = (CARD16) (v))) : \ + ((*((CARD16 *) (a)) = (CARD16) ((v) >> 8)), \ + (*((a)+2) = (CARD8) (v)))) +#else +#define Fetch24(a) ((unsigned long) (a) & 1 ? \ + ((*(a)) | (*((CARD16 *) ((a)+1)) << 8)) : \ + ((*((CARD16 *) (a))) | (*((a)+2) << 16))) +#define Store24(a,v) ((unsigned long) (a) & 1 ? \ + ((*(a) = (CARD8) (v)), \ + (*((CARD16 *) ((a)+1)) = (CARD16) ((v) >> 8))) : \ + ((*((CARD16 *) (a)) = (CARD16) (v)),\ + (*((a)+2) = (CARD8) ((v) >> 16)))) +#endif + +/* + The methods below use some tricks to be able to do two color + components at the same time. +*/ + +/* + x_c = (x_c * a) / 255 +*/ +#define FbByteMul(x, a) do { \ + CARD32 t = ((x & 0xff00ff) * a) + 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + \ + x = (((x >> 8) & 0xff00ff) * a) + 0x800080; \ + x = (x + ((x >> 8) & 0xff00ff)); \ + x &= 0xff00ff00; \ + x += t; \ + } while (0) + +/* + x_c = (x_c * a) / 255 + y +*/ +#define FbByteMulAdd(x, a, y) do { \ + CARD32 t = ((x & 0xff00ff) * a) + 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + t += y & 0xff00ff; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + \ + x = (((x >> 8) & 0xff00ff) * a) + 0x800080; \ + x = (x + ((x >> 8) & 0xff00ff)) >> 8; \ + x &= 0xff00ff; \ + x += (y >> 8) & 0xff00ff; \ + x |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x <<= 8; \ + x += t; \ + } while (0) + +/* + x_c = (x_c * a + y_c * b) / 255 +*/ +#define FbByteAddMul(x, a, y, b) do { \ + CARD32 t; \ + CARD32 r = (x >> 24) * a + (y >> 24) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + t = (x & 0xff00) * a + (y & 0xff00) * b; \ + t += (t >> 8) + 0x8000; \ + t >>= 16; \ + \ + t |= r << 16; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + t <<= 8; \ + \ + r = ((x >> 16) & 0xff) * a + ((y >> 16) & 0xff) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + x = (x & 0xff) * a + (y & 0xff) * b + 0x80; \ + x += (x >> 8); \ + x >>= 8; \ + x |= r << 16; \ + x |= 0x1000100 - ((x >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x |= t; \ +} while (0) + +/* + x_c = (x_c * a + y_c *b) / 256 +*/ +#define FbByteAddMul_256(x, a, y, b) do { \ + CARD32 t = (x & 0xff00ff) * a + (y & 0xff00ff) * b; \ + t >>= 8; \ + t &= 0xff00ff; \ + \ + x = ((x >> 8) & 0xff00ff) * a + ((y >> 8) & 0xff00ff) * b; \ + x &= 0xff00ff00; \ + x += t; \ +} while (0) +/* + x_c = (x_c * a_c) / 255 +*/ +#define FbByteMulC(x, a) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff) * (a & 0xff); \ + r |= (x & 0xff0000) * ((a >> 16) & 0xff); \ + r += 0x800080; \ + r = (r + ((r >> 8) & 0xff00ff)) >> 8; \ + r &= 0xff00ff; \ + \ + x >>= 8; \ + t = (x & 0xff) * ((a >> 8) & 0xff); \ + t |= (x & 0xff0000) * (a >> 24); \ + t += 0x800080; \ + t = t + ((t >> 8) & 0xff00ff); \ + x = r | (t & 0xff00ff00); \ + \ + } while (0) + +/* + x_c = (x_c * a) / 255 + y +*/ +#define FbByteMulAddC(x, a, y) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff) * (a & 0xff); \ + r |= (x & 0xff0000) * ((a >> 16) & 0xff); \ + r += 0x800080; \ + r = (r + ((r >> 8) & 0xff00ff)) >> 8; \ + r &= 0xff00ff; \ + r += y & 0xff00ff; \ + r |= 0x1000100 - ((r >> 8) & 0xff00ff); \ + r &= 0xff00ff; \ + \ + x >>= 8; \ + t = (x & 0xff) * ((a >> 8) & 0xff); \ + t |= (x & 0xff0000) * (a >> 24); \ + t += 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + t += (y >> 8) & 0xff00ff; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + x = r | (t << 8); \ + } while (0) + +/* + x_c = (x_c * a_c + y_c * b) / 255 +*/ +#define FbByteAddMulC(x, a, y, b) do { \ + CARD32 t; \ + CARD32 r = (x >> 24) * (a >> 24) + (y >> 24) * b; \ + r += (r >> 8) + 0x80; \ + r >>= 8; \ + \ + t = (x & 0xff00) * ((a >> 8) & 0xff) + (y & 0xff00) * b; \ + t += (t >> 8) + 0x8000; \ + t >>= 16; \ + \ + t |= r << 16; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + t <<= 8; \ + \ + r = ((x >> 16) & 0xff) * ((a >> 16) & 0xff) + ((y >> 16) & 0xff) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + x = (x & 0xff) * (a & 0xff) + (y & 0xff) * b + 0x80; \ + x += (x >> 8); \ + x >>= 8; \ + x |= r << 16; \ + x |= 0x1000100 - ((x >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x |= t; \ + } while (0) + +/* + x_c = min(x_c + y_c, 255) +*/ +#define FbByteAdd(x, y) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff00ff) + (y & 0xff00ff); \ + r |= 0x1000100 - ((r >> 8) & 0xff00ff); \ + r &= 0xff00ff; \ + \ + t = ((x >> 8) & 0xff00ff) + ((y >> 8) & 0xff00ff); \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + r |= (t & 0xff00ff) << 8; \ + x = r; \ + } while (0) + +#define div_255(x) (((x) + 0x80 + (((x) + 0x80) >> 8)) >> 8) + +#if defined(__i386__) && defined(__GNUC__) +#define FASTCALL __attribute__((regparm(3))) +#else +#define FASTCALL +#endif + +#if defined(__GNUC__) +#define INLINE __inline__ +#else +#define INLINE +#endif + +typedef struct _FbComposeData { + CARD8 op; + PicturePtr src; + PicturePtr mask; + PicturePtr dest; + INT16 xSrc; + INT16 ySrc; + INT16 xMask; + INT16 yMask; + INT16 xDest; + INT16 yDest; + CARD16 width; + CARD16 height; +} FbComposeData; + +typedef FASTCALL void (*CombineMaskU) (CARD32 *src, const CARD32 *mask, int width); +typedef FASTCALL void (*CombineFuncU) (CARD32 *dest, const CARD32 *src, int width); +typedef FASTCALL void (*CombineFuncC) (CARD32 *dest, CARD32 *src, CARD32 *mask, int width); + +typedef struct _FbComposeFunctions { + CombineFuncU *combineU; + CombineFuncC *combineC; + CombineMaskU combineMaskU; +} FbComposeFunctions; + +/* fbcompose.c */ + +void +fbCompositeGeneral (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +/* fbedge.c */ +void +fbRasterizeEdges (FbBits *buf, + int bpp, + int width, + int stride, + RenderEdge *l, + RenderEdge *r, + xFixed t, + xFixed b); + +/* fbpict.c */ +CARD32 +fbOver (CARD32 x, CARD32 y); + +CARD32 +fbOver24 (CARD32 x, CARD32 y); + +CARD32 +fbIn (CARD32 x, CARD8 y); + +void +fbCompositeSolidMask_nx8x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8x0888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8888x8888C (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8888x0565C (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x0888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_0565x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_8000x8000 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_8888x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_1000x1000 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx1xn (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +/* fbtrap.c */ + +void +fbAddTraps (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntrap, + xTrap *traps); + +void +fbRasterizeTrapezoid (PicturePtr alpha, + xTrapezoid *trap, + int x_off, + int y_off); + +void +fbAddTriangles (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntri, + xTriangle *tris); + +#endif /* _FBPICT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpriv.h (revision 51223) @@ -0,0 +1,266 @@ +/* + * copyed from from linux kernel 2.2.4 + * removed internal stuff (#ifdef __KERNEL__) + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/fbdevhw/fbpriv.h,v 1.2 2000/01/21 02:30:02 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _LINUX_FB_H +#define _LINUX_FB_H + +#include + +/* Definitions of frame buffers */ + +#define FB_MAJOR 29 + +#define FB_MODES_SHIFT 5 /* 32 modes per framebuffer */ +#define FB_NUM_MINORS 256 /* 256 Minors */ +#define FB_MAX (FB_NUM_MINORS / (1 << FB_MODES_SHIFT)) +#define GET_FB_IDX(node) (MINOR(node) >> FB_MODES_SHIFT) + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +/* 0x4607-0x460B are defined below */ +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 + +#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ +#define FB_TYPE_PLANES 1 /* Non interleaved planes */ +#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FB_TYPE_TEXT 3 /* Text/attributes */ + +#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ +#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ +#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ +#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ +#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ + +#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ +#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ +#define FB_VISUAL_TRUECOLOR 2 /* True color */ +#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ +#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ +#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ + +#define FB_ACCEL_NONE 0 /* no hardware accelerator */ +#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ +#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ +#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ +#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ +#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ +#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ +#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ +#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ +#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ +#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ +#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ +#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ +#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ +#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ +#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ +#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ +#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ +#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ +#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ +#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ +#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ +#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ +#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ +#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ +#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ +#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ +#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ +#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ +#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ +#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ + +struct fb_fix_screeninfo { + char id[16]; /* identification string eg "TT Builtin" */ + char *smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + __u32 smem_len; /* Length of frame buffer mem */ + __u32 type; /* see FB_TYPE_* */ + __u32 type_aux; /* Interleave for interleaved Planes */ + __u32 visual; /* see FB_VISUAL_* */ + __u16 xpanstep; /* zero if no hardware panning */ + __u16 ypanstep; /* zero if no hardware panning */ + __u16 ywrapstep; /* zero if no hardware ywrap */ + __u32 line_length; /* length of a line in bytes */ + char *mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + __u32 mmio_len; /* Length of Memory Mapped I/O */ + __u32 accel; /* Type of acceleration available */ + __u16 reserved[3]; /* Reserved for future compatibility */ +}; + +/* Interpretation of offset for color fields: All offsets are from the right, + * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you + * can use the offset as right argument to <<). A pixel afterwards is a bit + * stream and is written to video memory as that unmodified. This implies + * big-endian byte order if bits_per_pixel is greater than 8. + */ +struct fb_bitfield { + __u32 offset; /* beginning of bitfield */ + __u32 length; /* length of bitfield */ + __u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ + +#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ +#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ +#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ +#define FB_ACTIVATE_MASK 15 + /* values */ +#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ +#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ +#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ + +#define FB_ACCELF_TEXT 1 /* text mode acceleration */ + +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +struct fb_var_screeninfo { + __u32 xres; /* visible resolution */ + __u32 yres; + __u32 xres_virtual; /* virtual resolution */ + __u32 yres_virtual; + __u32 xoffset; /* offset from virtual to visible */ + __u32 yoffset; /* resolution */ + + __u32 bits_per_pixel; /* guess what */ + __u32 grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ + + __u32 nonstd; /* != 0 Non standard pixel format */ + + __u32 activate; /* see FB_ACTIVATE_* */ + + __u32 height; /* height of picture in mm */ + __u32 width; /* width of picture in mm */ + + __u32 accel_flags; /* acceleration flags (hints) */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + __u32 pixclock; /* pixel clock in ps (pico seconds) */ + __u32 left_margin; /* time from sync to picture */ + __u32 right_margin; /* time from picture to sync */ + __u32 upper_margin; /* time from sync to picture */ + __u32 lower_margin; + __u32 hsync_len; /* length of horizontal sync */ + __u32 vsync_len; /* length of vertical sync */ + __u32 sync; /* see FB_SYNC_* */ + __u32 vmode; /* see FB_VMODE_* */ + __u32 reserved[6]; /* Reserved for future compatibility */ +}; + +struct fb_cmap { + __u32 start; /* First entry */ + __u32 len; /* Number of entries */ + __u16 *red; /* Red values */ + __u16 *green; + __u16 *blue; + __u16 *transp; /* transparency, can be NULL */ +}; + +struct fb_con2fbmap { + __u32 console; + __u32 framebuffer; +}; + +struct fb_monspecs { + __u32 hfmin; /* hfreq lower limit (Hz) */ + __u32 hfmax; /* hfreq upper limit (Hz) */ + __u16 vfmin; /* vfreq lower limit (Hz) */ + __u16 vfmax; /* vfreq upper limit (Hz) */ + unsigned dpms : 1; /* supports DPMS */ +}; + +#if 1 + +#define FBCMD_GET_CURRENTPAR 0xDEAD0005 +#define FBCMD_SET_CURRENTPAR 0xDEAD8005 + +#endif + + +#if 1 /* Preliminary */ + + /* + * Hardware Cursor + */ + +#define FBIOGET_FCURSORINFO 0x4607 +#define FBIOGET_VCURSORINFO 0x4608 +#define FBIOPUT_VCURSORINFO 0x4609 +#define FBIOGET_CURSORSTATE 0x460A +#define FBIOPUT_CURSORSTATE 0x460B + + +struct fb_fix_cursorinfo { + __u16 crsr_width; /* width and height of the cursor in */ + __u16 crsr_height; /* pixels (zero if no cursor) */ + __u16 crsr_xsize; /* cursor size in display pixels */ + __u16 crsr_ysize; + __u16 crsr_color1; /* colormap entry for cursor color1 */ + __u16 crsr_color2; /* colormap entry for cursor color2 */ +}; + +struct fb_var_cursorinfo { + __u16 width; + __u16 height; + __u16 xspot; + __u16 yspot; + __u8 data[1]; /* field with [height][width] */ +}; + +struct fb_cursorstate { + __s16 xoffset; + __s16 yoffset; + __u16 mode; +}; + +#define FB_CURSOR_OFF 0 +#define FB_CURSOR_ON 1 +#define FB_CURSOR_FLASH 2 + +#endif /* Preliminary */ + +#endif /* _LINUX_FB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpseudocolor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpseudocolor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbpseudocolor.h (revision 51223) @@ -0,0 +1,20 @@ +#ifndef _FB_XX_H_ +# define _FB_XX_H_ + +typedef void (*xxSyncFunc)(ScreenPtr); +extern Bool xxSetup(ScreenPtr pScreen, int myDepth, + int baseDepth, char *addr, xxSyncFunc sync); +extern void xxPrintVisuals(void); + + +#endif /* _FB_XX_H_ */ + + + + + + + + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbrop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbrop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fbrop.h (revision 51223) @@ -0,0 +1,139 @@ +/* + * Id: fbrop.h,v 1.1 1999/11/02 03:54:45 keithp Exp $ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* $XFree86: xc/programs/Xserver/fb/fbrop.h,v 1.3 2000/02/14 19:20:30 dawes Exp $ */ + +#ifndef _FBROP_H_ +#define _FBROP_H_ + +typedef struct _mergeRopBits { + FbBits ca1, cx1, ca2, cx2; +} FbMergeRopRec, *FbMergeRopPtr; + +extern const FbMergeRopRec FbMergeRopBits[16]; + +#define FbDeclareMergeRop() FbBits _ca1, _cx1, _ca2, _cx2; +#define FbDeclarePrebuiltMergeRop() FbBits _cca, _ccx; + +#define FbInitializeMergeRop(alu,pm) {\ + const FbMergeRopRec *_bits; \ + _bits = &FbMergeRopBits[alu]; \ + _ca1 = _bits->ca1 & pm; \ + _cx1 = _bits->cx1 | ~pm; \ + _ca2 = _bits->ca2 & pm; \ + _cx2 = _bits->cx2 & pm; \ +} + +#define FbDestInvarientRop(alu,pm) ((pm) == FB_ALLONES && \ + (((alu) >> 1 & 5) == ((alu) & 5))) + +#define FbDestInvarientMergeRop() (_ca1 == 0 && _cx1 == 0) + +/* AND has higher precedence than XOR */ + +#define FbDoMergeRop(src, dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (((src) & _ca2) ^ _cx2)) + +#define FbDoDestInvarientMergeRop(src) (((src) & _ca2) ^ _cx2) + +#define FbDoMaskMergeRop(src, dst, mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1) | ~(mask))) ^ ((((src) & _ca2) ^ _cx2) & (mask))) + +#define FbDoLeftMaskByteMergeRop(dst, src, lb, l) { \ + FbBits __xor = ((src) & _ca2) ^ _cx2; \ + FbDoLeftMaskByteRRop(dst,lb,l,((src) & _ca1) ^ _cx1,__xor); \ +} + +#define FbDoRightMaskByteMergeRop(dst, src, rb, r) { \ + FbBits __xor = ((src) & _ca2) ^ _cx2; \ + FbDoRightMaskByteRRop(dst,rb,r,((src) & _ca1) ^ _cx1,__xor); \ +} + +#define FbDoRRop(dst, and, xor) (((dst) & (and)) ^ (xor)) + +#define FbDoMaskRRop(dst, and, xor, mask) \ + (((dst) & ((and) | ~(mask))) ^ (xor & mask)) + +/* + * Take a single bit (0 or 1) and generate a full mask + */ +#define fbFillFromBit(b,t) (~((t) ((b) & 1)-1)) + +#define fbXorT(rop,fg,pm,t) ((((fg) & fbFillFromBit((rop) >> 1,t)) | \ + (~(fg) & fbFillFromBit((rop) >> 3,t))) & (pm)) + +#define fbAndT(rop,fg,pm,t) ((((fg) & fbFillFromBit (rop ^ (rop>>1),t)) | \ + (~(fg) & fbFillFromBit((rop>>2) ^ (rop>>3),t))) | \ + ~(pm)) + +#define fbXor(rop,fg,pm) fbXorT(rop,fg,pm,FbBits) + +#define fbAnd(rop,fg,pm) fbAndT(rop,fg,pm,FbBits) + +#define fbXorStip(rop,fg,pm) fbXorT(rop,fg,pm,FbStip) + +#define fbAndStip(rop,fg,pm) fbAndT(rop,fg,pm,FbStip) + +/* + * Stippling operations; + */ + +extern const FbBits fbStipple16Bits[256]; /* half of table */ +#define FbStipple16Bits(b) \ + (fbStipple16Bits[(b)&0xff] | fbStipple16Bits[(b) >> 8] << FB_HALFUNIT) +extern const FbBits fbStipple8Bits[256]; +extern const FbBits fbStipple4Bits[16]; +extern const FbBits fbStipple2Bits[4]; +extern const FbBits fbStipple1Bits[2]; +extern const FbBits *const fbStippleTable[]; + +#define FbStippleRRop(dst, b, fa, fx, ba, bx) \ + (FbDoRRop(dst, fa, fx) & b) | (FbDoRRop(dst, ba, bx) & ~b) + +#define FbStippleRRopMask(dst, b, fa, fx, ba, bx, m) \ + (FbDoMaskRRop(dst, fa, fx, m) & (b)) | (FbDoMaskRRop(dst, ba, bx, m) & ~(b)) + +#define FbDoLeftMaskByteStippleRRop(dst, b, fa, fx, ba, bx, lb, l) { \ + FbBits __xor = ((fx) & (b)) | ((bx) & ~(b)); \ + FbDoLeftMaskByteRRop(dst, lb, l, ((fa) & (b)) | ((ba) & ~(b)), __xor); \ +} + +#define FbDoRightMaskByteStippleRRop(dst, b, fa, fx, ba, bx, rb, r) { \ + FbBits __xor = ((fx) & (b)) | ((bx) & ~(b)); \ + FbDoRightMaskByteRRop(dst, rb, r, ((fa) & (b)) | ((ba) & ~(b)), __xor); \ +} + +#define FbOpaqueStipple(b, fg, bg) (((fg) & (b)) | ((bg) & ~(b))) + +/* + * Compute rop for using tile code for 1-bit dest stipples; modifies + * existing rop to flip depending on pixel values + */ +#define FbStipple1RopPick(alu,b) (((alu) >> (2 - (((b) & 1) << 1))) & 3) + +#define FbOpaqueStipple1Rop(alu,fg,bg) (FbStipple1RopPick(alu,fg) | \ + (FbStipple1RopPick(alu,bg) << 2)) + +#define FbStipple1Rop(alu,fg) (FbStipple1RopPick(alu,fg) | 4) + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fi1236.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fi1236.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fi1236.h (revision 51223) @@ -0,0 +1,122 @@ +#ifndef __FI1236_H__ +#define __FI1236_H__ + +#include "xf86i2c.h" + +/* why someone has defined NUM someplace else is beyoung me.. */ +#undef NUM + +typedef struct { + CARD32 fcar; /* 16 * fcar_Mhz */ + CARD32 min_freq; /* 16 * min_freq_Mhz */ + CARD32 max_freq; /* 16 * max_freq_Mhz */ + + CARD32 threshold1; /* 16 * Value_Mhz */ + CARD32 threshold2; /* 16 * Value_Mhz */ + + CARD8 band_low; + CARD8 band_mid; + CARD8 band_high; + CARD8 control; + } FI1236_parameters; + + +typedef struct { + /* what we want */ + /* all frequencies are in Mhz */ + double f_rf; /* frequency to tune to */ + double f_if1; /* first intermediate frequency */ + double f_if2; /* second intermediate frequency */ + double f_ref; /* reference frequency */ + double f_ifbw; /* bandwidth */ + double f_step; /* step */ + + /* what we compute */ + double f_lo1; + double f_lo2; + int LO1I; + int LO2I; + int SEL; + int STEP; + int NUM; + } MT2032_parameters; + +typedef struct { + I2CDevRec d; + int type; + + void* afc_source; /* The AFC source may be another chip like TDA988x */ + + int afc_delta; + CARD32 original_frequency; + Bool afc_timer_installed; + int afc_count; + int last_afc_hint; + + double video_if; + FI1236_parameters parm; + int xogc; /* for MT2032 */ + + struct { + CARD8 div1; + CARD8 div2; + CARD8 control; + CARD8 band; + CARD8 aux; /* this is for MK3 tuners */ + } tuner_data; + } FI1236Rec, *FI1236Ptr; + +#define TUNER_TYPE_FI1236 0 +#define TUNER_TYPE_FI1216 1 +#define TUNER_TYPE_TEMIC_FN5AL 2 +#define TUNER_TYPE_MT2032 3 +#define TUNER_TYPE_FI1246 4 +#define TUNER_TYPE_FI1256 5 +#define TUNER_TYPE_FI1236W 6 +#define TUNER_TYPE_FM1216ME 7 + +#define FI1236_ADDR(a) ((a)->d.SlaveAddr) + +#define FI1236_ADDR_1 0xC6 +#define FI1236_ADDR_2 0xC0 + +#define TUNER_TUNED 0 +#define TUNER_JUST_BELOW 1 +#define TUNER_JUST_ABOVE -1 +#define TUNER_OFF 4 +#define TUNER_STILL_TUNING 5 + + +FI1236Ptr Detect_FI1236(I2CBusPtr b, I2CSlaveAddr addr); +void FI1236_set_tuner_type(FI1236Ptr f, int type); +void TUNER_set_frequency(FI1236Ptr f, CARD32 frequency); +int FI1236_AFC(FI1236Ptr f); +int TUNER_get_afc_hint(FI1236Ptr f); +void fi1236_dump_status(FI1236Ptr f); + +#define FI1236SymbolsList \ + "Detect_FI1236", \ + "FI1236_set_tuner_type", \ + "TUNER_set_frequency" + +#ifdef XFree86LOADER + +#define xf86_Detect_FI1236 ((FI1236Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_FI1236")) +#define xf86_FI1236_set_tuner_type ((void (*)(FI1236Ptr, int))LoaderSymbol("FI1236_set_tuner_type")) +#define xf86_TUNER_set_frequency ((void (*)(FI1236Ptr, CARD32))LoaderSymbol("TUNER_set_frequency")) +#define xf86_FI1236_AFC ((int (*)(FI1236Ptr))LoaderSymbol("FI1236_AFC")) +#define xf86_TUNER_get_afc_hint ((int (*)(FI1236Ptr))LoaderSymbol("TUNER_get_afc_hint")) +#define xf86_fi1236_dump_status ((void (*)(FI1236Ptr))LoaderSymbol("fi1236_dump_status")) + +#else + +#define xf86_Detect_FI1236 Detect_FI1236 +#define xf86_FI1236_set_tuner_type FI1236_set_tuner_type +#define xf86_TUNER_set_frequency TUNER_set_frequency +#define xf86_FI1236_AFC FI1236_AFC +#define xf86_TUNER_get_afc_hint TUNER_get_afc_hint +#define xf86_fi1236_dump_status fi1236_dump_status + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fourcc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fourcc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fourcc.h (revision 51223) @@ -0,0 +1,161 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/fourcc.h,v 1.5 2003/08/24 17:36:48 dawes Exp $ */ + +/* + * Copyright (c) 2000-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + This header file contains listings of STANDARD guids for video formats. + Please do not place non-registered, or incomplete entries in this file. + A list of some popular fourcc's are at: http://www.webartz.com/fourcc/ + For an explanation of fourcc <-> guid mappings see RFC2361. +*/ + +#ifndef _XF86_FOURCC_H_ +#define _XF86_FOURCC_H_ 1 + +#define FOURCC_YUY2 0x32595559 +#define XVIMAGE_YUY2 \ + { \ + FOURCC_YUY2, \ + XvYUV, \ + LSBFirst, \ + {'Y','U','Y','2', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'Y','U','Y','V', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_YV12 0x32315659 +#define XVIMAGE_YV12 \ + { \ + FOURCC_YV12, \ + XvYUV, \ + LSBFirst, \ + {'Y','V','1','2', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 12, \ + XvPlanar, \ + 3, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 2, 2, \ + {'Y','V','U', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_I420 0x30323449 +#define XVIMAGE_I420 \ + { \ + FOURCC_I420, \ + XvYUV, \ + LSBFirst, \ + {'I','4','2','0', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 12, \ + XvPlanar, \ + 3, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 2, 2, \ + {'Y','U','V', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + + +#define FOURCC_UYVY 0x59565955 +#define XVIMAGE_UYVY \ + { \ + FOURCC_UYVY, \ + XvYUV, \ + LSBFirst, \ + {'U','Y','V','Y', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'U','Y','V','Y', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_IA44 0x34344149 +#define XVIMAGE_IA44 \ + { \ + FOURCC_IA44, \ + XvYUV, \ + LSBFirst, \ + {'I','A','4','4', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 1, 1, \ + 1, 1, 1, \ + {'A','I', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_AI44 0x34344941 +#define XVIMAGE_AI44 \ + { \ + FOURCC_AI44, \ + XvYUV, \ + LSBFirst, \ + {'A','I','4','4', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 1, 1, \ + 1, 1, 1, \ + {'I','A', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#endif /* _XF86_FOURCC_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu.h (revision 51223) @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu_regs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu_regs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/fpu_regs.h (revision 51223) @@ -0,0 +1,119 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#ifdef PACK +# pragma PACK +#endif + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab.h (revision 51223) @@ -0,0 +1,676 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/g_disptab.h,v 1.3 2001/03/21 16:29:35 dawes Exp $ */ +/* DO NOT EDIT - THIS FILE IS AUTOMATICALLY GENERATED */ +#ifndef _GLX_g_disptab_h_ +#define _GLX_g_disptab_h_ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: This software was created using the +** OpenGL(R) version 1.2.1 Sample Implementation published by SGI, but has +** not been independently verified as being compliant with the OpenGL(R) +** version 1.2.1 Specification. +*/ + +extern int __glXRender(__GLXclientState*, GLbyte*); +extern int __glXRenderLarge(__GLXclientState*, GLbyte*); +extern int __glXSendLargeCommand(__GLXclientState *cl, GLXContextTag contextTag); +extern int __glXCreateContext(__GLXclientState*, GLbyte*); +extern int __glXCreateNewContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyContext(__GLXclientState*, GLbyte*); +extern int __glXMakeCurrent(__GLXclientState*, GLbyte*); +extern int __glXMakeContextCurrent(__GLXclientState*, GLbyte*); +extern int __glXCreatePbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyPbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXGetDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXChangeDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXIsDirect(__GLXclientState*, GLbyte*); +extern int __glXQueryVersion(__GLXclientState*, GLbyte*); +extern int __glXWaitGL(__GLXclientState*, GLbyte*); +extern int __glXWaitX(__GLXclientState*, GLbyte*); +extern int __glXCopyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapBuffers(__GLXclientState*, GLbyte*); +extern int __glXUseXFont(__GLXclientState*, GLbyte*); +extern int __glXCreateGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXCreatePixmap(__GLXclientState *cl, GLbyte *pc); +extern int __glXGetVisualConfigs(__GLXclientState*, GLbyte*); +extern int __glXDestroyGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXVendorPrivate(__GLXclientState*, GLbyte*); +extern int __glXVendorPrivateWithReply(__GLXclientState*, GLbyte*); +extern int __glXQueryExtensionsString(__GLXclientState*, GLbyte*); +extern int __glXQueryServerString(__GLXclientState*, GLbyte*); +extern int __glXClientInfo(__GLXclientState*, GLbyte*); +extern int __glXGetFBConfigs(__GLXclientState*, GLbyte*); +extern int __glXCreateWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXQueryContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDisp_NewList(__GLXclientState*, GLbyte*); +extern int __glXDisp_EndList(__GLXclientState*, GLbyte*); +extern int __glXDisp_DeleteLists(__GLXclientState*, GLbyte*); +extern int __glXDisp_GenLists(__GLXclientState*, GLbyte*); +extern int __glXDisp_FeedbackBuffer(__GLXclientState*, GLbyte*); +extern int __glXDisp_SelectBuffer(__GLXclientState*, GLbyte*); +extern int __glXDisp_RenderMode(__GLXclientState*, GLbyte*); +extern int __glXDisp_Finish(__GLXclientState*, GLbyte*); +extern int __glXDisp_PixelStoref(__GLXclientState*, GLbyte*); +extern int __glXDisp_PixelStorei(__GLXclientState*, GLbyte*); +extern int __glXDisp_ReadPixels(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetBooleanv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetClipPlane(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetDoublev(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetError(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetFloatv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetIntegerv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetLightfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetLightiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapdv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMaterialfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMaterialiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapuiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapusv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPolygonStipple(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetString(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexEnvfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexEnviv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGendv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGenfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGeniv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexImage(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexLevelParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexLevelParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsEnabled(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsList(__GLXclientState*, GLbyte*); +extern int __glXDisp_Flush(__GLXclientState*, GLbyte*); +extern int __glXDisp_AreTexturesResident(__GLXclientState*, GLbyte*); +extern int __glXDisp_DeleteTextures(__GLXclientState*, GLbyte*); +extern int __glXDisp_GenTextures(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsTexture(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTable(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTableParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTableParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionFilter(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetSeparableFilter(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogram(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogramParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogramParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmax(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmaxParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmaxParameteriv(__GLXclientState*, GLbyte*); + +extern void __glXDisp_CallList(GLbyte*); +extern void __glXDisp_CallLists(GLbyte*); +extern void __glXDisp_ListBase(GLbyte*); +extern void __glXDisp_Begin(GLbyte*); +extern void __glXDisp_Bitmap(GLbyte*); +extern void __glXDisp_Color3bv(GLbyte*); +extern void __glXDisp_Color3dv(GLbyte*); +extern void __glXDisp_Color3fv(GLbyte*); +extern void __glXDisp_Color3iv(GLbyte*); +extern void __glXDisp_Color3sv(GLbyte*); +extern void __glXDisp_Color3ubv(GLbyte*); +extern void __glXDisp_Color3uiv(GLbyte*); +extern void __glXDisp_Color3usv(GLbyte*); +extern void __glXDisp_Color4bv(GLbyte*); +extern void __glXDisp_Color4dv(GLbyte*); +extern void __glXDisp_Color4fv(GLbyte*); +extern void __glXDisp_Color4iv(GLbyte*); +extern void __glXDisp_Color4sv(GLbyte*); +extern void __glXDisp_Color4ubv(GLbyte*); +extern void __glXDisp_Color4uiv(GLbyte*); +extern void __glXDisp_Color4usv(GLbyte*); +extern void __glXDisp_EdgeFlagv(GLbyte*); +extern void __glXDisp_End(GLbyte*); +extern void __glXDisp_Indexdv(GLbyte*); +extern void __glXDisp_Indexfv(GLbyte*); +extern void __glXDisp_Indexiv(GLbyte*); +extern void __glXDisp_Indexsv(GLbyte*); +extern void __glXDisp_Normal3bv(GLbyte*); +extern void __glXDisp_Normal3dv(GLbyte*); +extern void __glXDisp_Normal3fv(GLbyte*); +extern void __glXDisp_Normal3iv(GLbyte*); +extern void __glXDisp_Normal3sv(GLbyte*); +extern void __glXDisp_RasterPos2dv(GLbyte*); +extern void __glXDisp_RasterPos2fv(GLbyte*); +extern void __glXDisp_RasterPos2iv(GLbyte*); +extern void __glXDisp_RasterPos2sv(GLbyte*); +extern void __glXDisp_RasterPos3dv(GLbyte*); +extern void __glXDisp_RasterPos3fv(GLbyte*); +extern void __glXDisp_RasterPos3iv(GLbyte*); +extern void __glXDisp_RasterPos3sv(GLbyte*); +extern void __glXDisp_RasterPos4dv(GLbyte*); +extern void __glXDisp_RasterPos4fv(GLbyte*); +extern void __glXDisp_RasterPos4iv(GLbyte*); +extern void __glXDisp_RasterPos4sv(GLbyte*); +extern void __glXDisp_Rectdv(GLbyte*); +extern void __glXDisp_Rectfv(GLbyte*); +extern void __glXDisp_Rectiv(GLbyte*); +extern void __glXDisp_Rectsv(GLbyte*); +extern void __glXDisp_TexCoord1dv(GLbyte*); +extern void __glXDisp_TexCoord1fv(GLbyte*); +extern void __glXDisp_TexCoord1iv(GLbyte*); +extern void __glXDisp_TexCoord1sv(GLbyte*); +extern void __glXDisp_TexCoord2dv(GLbyte*); +extern void __glXDisp_TexCoord2fv(GLbyte*); +extern void __glXDisp_TexCoord2iv(GLbyte*); +extern void __glXDisp_TexCoord2sv(GLbyte*); +extern void __glXDisp_TexCoord3dv(GLbyte*); +extern void __glXDisp_TexCoord3fv(GLbyte*); +extern void __glXDisp_TexCoord3iv(GLbyte*); +extern void __glXDisp_TexCoord3sv(GLbyte*); +extern void __glXDisp_TexCoord4dv(GLbyte*); +extern void __glXDisp_TexCoord4fv(GLbyte*); +extern void __glXDisp_TexCoord4iv(GLbyte*); +extern void __glXDisp_TexCoord4sv(GLbyte*); +extern void __glXDisp_Vertex2dv(GLbyte*); +extern void __glXDisp_Vertex2fv(GLbyte*); +extern void __glXDisp_Vertex2iv(GLbyte*); +extern void __glXDisp_Vertex2sv(GLbyte*); +extern void __glXDisp_Vertex3dv(GLbyte*); +extern void __glXDisp_Vertex3fv(GLbyte*); +extern void __glXDisp_Vertex3iv(GLbyte*); +extern void __glXDisp_Vertex3sv(GLbyte*); +extern void __glXDisp_Vertex4dv(GLbyte*); +extern void __glXDisp_Vertex4fv(GLbyte*); +extern void __glXDisp_Vertex4iv(GLbyte*); +extern void __glXDisp_Vertex4sv(GLbyte*); +extern void __glXDisp_ClipPlane(GLbyte*); +extern void __glXDisp_ColorMaterial(GLbyte*); +extern void __glXDisp_CullFace(GLbyte*); +extern void __glXDisp_Fogf(GLbyte*); +extern void __glXDisp_Fogfv(GLbyte*); +extern void __glXDisp_Fogi(GLbyte*); +extern void __glXDisp_Fogiv(GLbyte*); +extern void __glXDisp_FrontFace(GLbyte*); +extern void __glXDisp_Hint(GLbyte*); +extern void __glXDisp_Lightf(GLbyte*); +extern void __glXDisp_Lightfv(GLbyte*); +extern void __glXDisp_Lighti(GLbyte*); +extern void __glXDisp_Lightiv(GLbyte*); +extern void __glXDisp_LightModelf(GLbyte*); +extern void __glXDisp_LightModelfv(GLbyte*); +extern void __glXDisp_LightModeli(GLbyte*); +extern void __glXDisp_LightModeliv(GLbyte*); +extern void __glXDisp_LineStipple(GLbyte*); +extern void __glXDisp_LineWidth(GLbyte*); +extern void __glXDisp_Materialf(GLbyte*); +extern void __glXDisp_Materialfv(GLbyte*); +extern void __glXDisp_Materiali(GLbyte*); +extern void __glXDisp_Materialiv(GLbyte*); +extern void __glXDisp_PointSize(GLbyte*); +extern void __glXDisp_PolygonMode(GLbyte*); +extern void __glXDisp_PolygonStipple(GLbyte*); +extern void __glXDisp_Scissor(GLbyte*); +extern void __glXDisp_ShadeModel(GLbyte*); +extern void __glXDisp_TexParameterf(GLbyte*); +extern void __glXDisp_TexParameterfv(GLbyte*); +extern void __glXDisp_TexParameteri(GLbyte*); +extern void __glXDisp_TexParameteriv(GLbyte*); +extern void __glXDisp_TexImage1D(GLbyte*); +extern void __glXDisp_TexImage2D(GLbyte*); +extern void __glXDisp_TexEnvf(GLbyte*); +extern void __glXDisp_TexEnvfv(GLbyte*); +extern void __glXDisp_TexEnvi(GLbyte*); +extern void __glXDisp_TexEnviv(GLbyte*); +extern void __glXDisp_TexGend(GLbyte*); +extern void __glXDisp_TexGendv(GLbyte*); +extern void __glXDisp_TexGenf(GLbyte*); +extern void __glXDisp_TexGenfv(GLbyte*); +extern void __glXDisp_TexGeni(GLbyte*); +extern void __glXDisp_TexGeniv(GLbyte*); +extern void __glXDisp_InitNames(GLbyte*); +extern void __glXDisp_LoadName(GLbyte*); +extern void __glXDisp_PassThrough(GLbyte*); +extern void __glXDisp_PopName(GLbyte*); +extern void __glXDisp_PushName(GLbyte*); +extern void __glXDisp_DrawBuffer(GLbyte*); +extern void __glXDisp_Clear(GLbyte*); +extern void __glXDisp_ClearAccum(GLbyte*); +extern void __glXDisp_ClearIndex(GLbyte*); +extern void __glXDisp_ClearColor(GLbyte*); +extern void __glXDisp_ClearStencil(GLbyte*); +extern void __glXDisp_ClearDepth(GLbyte*); +extern void __glXDisp_StencilMask(GLbyte*); +extern void __glXDisp_ColorMask(GLbyte*); +extern void __glXDisp_DepthMask(GLbyte*); +extern void __glXDisp_IndexMask(GLbyte*); +extern void __glXDisp_Accum(GLbyte*); +extern void __glXDisp_Disable(GLbyte*); +extern void __glXDisp_Enable(GLbyte*); +extern void __glXDisp_PopAttrib(GLbyte*); +extern void __glXDisp_PushAttrib(GLbyte*); +extern void __glXDisp_Map1d(GLbyte*); +extern void __glXDisp_Map1f(GLbyte*); +extern void __glXDisp_Map2d(GLbyte*); +extern void __glXDisp_Map2f(GLbyte*); +extern void __glXDisp_MapGrid1d(GLbyte*); +extern void __glXDisp_MapGrid1f(GLbyte*); +extern void __glXDisp_MapGrid2d(GLbyte*); +extern void __glXDisp_MapGrid2f(GLbyte*); +extern void __glXDisp_EvalCoord1dv(GLbyte*); +extern void __glXDisp_EvalCoord1fv(GLbyte*); +extern void __glXDisp_EvalCoord2dv(GLbyte*); +extern void __glXDisp_EvalCoord2fv(GLbyte*); +extern void __glXDisp_EvalMesh1(GLbyte*); +extern void __glXDisp_EvalPoint1(GLbyte*); +extern void __glXDisp_EvalMesh2(GLbyte*); +extern void __glXDisp_EvalPoint2(GLbyte*); +extern void __glXDisp_AlphaFunc(GLbyte*); +extern void __glXDisp_BlendFunc(GLbyte*); +extern void __glXDisp_LogicOp(GLbyte*); +extern void __glXDisp_StencilFunc(GLbyte*); +extern void __glXDisp_StencilOp(GLbyte*); +extern void __glXDisp_DepthFunc(GLbyte*); +extern void __glXDisp_PixelZoom(GLbyte*); +extern void __glXDisp_PixelTransferf(GLbyte*); +extern void __glXDisp_PixelTransferi(GLbyte*); +extern void __glXDisp_PixelMapfv(GLbyte*); +extern void __glXDisp_PixelMapuiv(GLbyte*); +extern void __glXDisp_PixelMapusv(GLbyte*); +extern void __glXDisp_ReadBuffer(GLbyte*); +extern void __glXDisp_CopyPixels(GLbyte*); +extern void __glXDisp_DrawPixels(GLbyte*); +extern void __glXDisp_DepthRange(GLbyte*); +extern void __glXDisp_Frustum(GLbyte*); +extern void __glXDisp_LoadIdentity(GLbyte*); +extern void __glXDisp_LoadMatrixf(GLbyte*); +extern void __glXDisp_LoadMatrixd(GLbyte*); +extern void __glXDisp_MatrixMode(GLbyte*); +extern void __glXDisp_MultMatrixf(GLbyte*); +extern void __glXDisp_MultMatrixd(GLbyte*); +extern void __glXDisp_Ortho(GLbyte*); +extern void __glXDisp_PopMatrix(GLbyte*); +extern void __glXDisp_PushMatrix(GLbyte*); +extern void __glXDisp_Rotated(GLbyte*); +extern void __glXDisp_Rotatef(GLbyte*); +extern void __glXDisp_Scaled(GLbyte*); +extern void __glXDisp_Scalef(GLbyte*); +extern void __glXDisp_Translated(GLbyte*); +extern void __glXDisp_Translatef(GLbyte*); +extern void __glXDisp_Viewport(GLbyte*); +extern void __glXDisp_PolygonOffset(GLbyte*); +extern void __glXDisp_DrawArrays(GLbyte*); +extern void __glXDisp_Indexubv(GLbyte*); +extern void __glXDisp_ColorSubTable(GLbyte*); +extern void __glXDisp_CopyColorSubTable(GLbyte*); +extern void __glXDisp_ActiveTextureARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4svARB(GLbyte*); + +extern int __glXSwapRender(__GLXclientState*, GLbyte*); +extern int __glXSwapRenderLarge(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateContext(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateNewContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapMakeCurrent(__GLXclientState*, GLbyte*); +extern int __glXSwapMakeContextCurrent(__GLXclientState*, GLbyte*); +extern int __glXSwapCreatePbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyPbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapGetDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapChangeDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapIsDirect(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryVersion(__GLXclientState*, GLbyte*); +extern int __glXSwapWaitGL(__GLXclientState*, GLbyte*); +extern int __glXSwapWaitX(__GLXclientState*, GLbyte*); +extern int __glXSwapCopyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapSwapBuffers(__GLXclientState*, GLbyte*); +extern int __glXSwapUseXFont(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXSwapCreatePixmap(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapGetVisualConfigs(__GLXclientState*, GLbyte*); +extern int __glXSwapDestroyGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXSwapVendorPrivate(__GLXclientState*, GLbyte*); +extern int __glXSwapVendorPrivateWithReply(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryExtensionsString(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryServerString(__GLXclientState*, GLbyte*); +extern int __glXSwapClientInfo(__GLXclientState*, GLbyte*); +extern int __glXSwapGetFBConfigs(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapQueryContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_NewList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_EndList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_DeleteLists(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GenLists(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_FeedbackBuffer(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_SelectBuffer(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_RenderMode(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_Finish(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_PixelStoref(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_PixelStorei(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_ReadPixels(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetBooleanv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetClipPlane(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetDoublev(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetError(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetFloatv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetIntegerv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetLightfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetLightiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapdv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMaterialfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMaterialiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapuiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapusv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPolygonStipple(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetString(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexEnvfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexEnviv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGendv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGenfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGeniv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexImage(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexLevelParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexLevelParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsEnabled(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_Flush(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_AreTexturesResident(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_DeleteTextures(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GenTextures(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsTexture(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTable(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTableParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTableParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionFilter(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetSeparableFilter(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogram(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogramParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogramParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmax(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmaxParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmaxParameteriv(__GLXclientState*, GLbyte*); + +extern void __glXDispSwap_CallList(GLbyte*); +extern void __glXDispSwap_CallLists(GLbyte*); +extern void __glXDispSwap_ListBase(GLbyte*); +extern void __glXDispSwap_Begin(GLbyte*); +extern void __glXDispSwap_Bitmap(GLbyte*); +extern void __glXDispSwap_Color3bv(GLbyte*); +extern void __glXDispSwap_Color3dv(GLbyte*); +extern void __glXDispSwap_Color3fv(GLbyte*); +extern void __glXDispSwap_Color3iv(GLbyte*); +extern void __glXDispSwap_Color3sv(GLbyte*); +extern void __glXDispSwap_Color3ubv(GLbyte*); +extern void __glXDispSwap_Color3uiv(GLbyte*); +extern void __glXDispSwap_Color3usv(GLbyte*); +extern void __glXDispSwap_Color4bv(GLbyte*); +extern void __glXDispSwap_Color4dv(GLbyte*); +extern void __glXDispSwap_Color4fv(GLbyte*); +extern void __glXDispSwap_Color4iv(GLbyte*); +extern void __glXDispSwap_Color4sv(GLbyte*); +extern void __glXDispSwap_Color4ubv(GLbyte*); +extern void __glXDispSwap_Color4uiv(GLbyte*); +extern void __glXDispSwap_Color4usv(GLbyte*); +extern void __glXDispSwap_EdgeFlagv(GLbyte*); +extern void __glXDispSwap_End(GLbyte*); +extern void __glXDispSwap_Indexdv(GLbyte*); +extern void __glXDispSwap_Indexfv(GLbyte*); +extern void __glXDispSwap_Indexiv(GLbyte*); +extern void __glXDispSwap_Indexsv(GLbyte*); +extern void __glXDispSwap_Normal3bv(GLbyte*); +extern void __glXDispSwap_Normal3dv(GLbyte*); +extern void __glXDispSwap_Normal3fv(GLbyte*); +extern void __glXDispSwap_Normal3iv(GLbyte*); +extern void __glXDispSwap_Normal3sv(GLbyte*); +extern void __glXDispSwap_RasterPos2dv(GLbyte*); +extern void __glXDispSwap_RasterPos2fv(GLbyte*); +extern void __glXDispSwap_RasterPos2iv(GLbyte*); +extern void __glXDispSwap_RasterPos2sv(GLbyte*); +extern void __glXDispSwap_RasterPos3dv(GLbyte*); +extern void __glXDispSwap_RasterPos3fv(GLbyte*); +extern void __glXDispSwap_RasterPos3iv(GLbyte*); +extern void __glXDispSwap_RasterPos3sv(GLbyte*); +extern void __glXDispSwap_RasterPos4dv(GLbyte*); +extern void __glXDispSwap_RasterPos4fv(GLbyte*); +extern void __glXDispSwap_RasterPos4iv(GLbyte*); +extern void __glXDispSwap_RasterPos4sv(GLbyte*); +extern void __glXDispSwap_Rectdv(GLbyte*); +extern void __glXDispSwap_Rectfv(GLbyte*); +extern void __glXDispSwap_Rectiv(GLbyte*); +extern void __glXDispSwap_Rectsv(GLbyte*); +extern void __glXDispSwap_TexCoord1dv(GLbyte*); +extern void __glXDispSwap_TexCoord1fv(GLbyte*); +extern void __glXDispSwap_TexCoord1iv(GLbyte*); +extern void __glXDispSwap_TexCoord1sv(GLbyte*); +extern void __glXDispSwap_TexCoord2dv(GLbyte*); +extern void __glXDispSwap_TexCoord2fv(GLbyte*); +extern void __glXDispSwap_TexCoord2iv(GLbyte*); +extern void __glXDispSwap_TexCoord2sv(GLbyte*); +extern void __glXDispSwap_TexCoord3dv(GLbyte*); +extern void __glXDispSwap_TexCoord3fv(GLbyte*); +extern void __glXDispSwap_TexCoord3iv(GLbyte*); +extern void __glXDispSwap_TexCoord3sv(GLbyte*); +extern void __glXDispSwap_TexCoord4dv(GLbyte*); +extern void __glXDispSwap_TexCoord4fv(GLbyte*); +extern void __glXDispSwap_TexCoord4iv(GLbyte*); +extern void __glXDispSwap_TexCoord4sv(GLbyte*); +extern void __glXDispSwap_Vertex2dv(GLbyte*); +extern void __glXDispSwap_Vertex2fv(GLbyte*); +extern void __glXDispSwap_Vertex2iv(GLbyte*); +extern void __glXDispSwap_Vertex2sv(GLbyte*); +extern void __glXDispSwap_Vertex3dv(GLbyte*); +extern void __glXDispSwap_Vertex3fv(GLbyte*); +extern void __glXDispSwap_Vertex3iv(GLbyte*); +extern void __glXDispSwap_Vertex3sv(GLbyte*); +extern void __glXDispSwap_Vertex4dv(GLbyte*); +extern void __glXDispSwap_Vertex4fv(GLbyte*); +extern void __glXDispSwap_Vertex4iv(GLbyte*); +extern void __glXDispSwap_Vertex4sv(GLbyte*); +extern void __glXDispSwap_ClipPlane(GLbyte*); +extern void __glXDispSwap_ColorMaterial(GLbyte*); +extern void __glXDispSwap_CullFace(GLbyte*); +extern void __glXDispSwap_Fogf(GLbyte*); +extern void __glXDispSwap_Fogfv(GLbyte*); +extern void __glXDispSwap_Fogi(GLbyte*); +extern void __glXDispSwap_Fogiv(GLbyte*); +extern void __glXDispSwap_FrontFace(GLbyte*); +extern void __glXDispSwap_Hint(GLbyte*); +extern void __glXDispSwap_Lightf(GLbyte*); +extern void __glXDispSwap_Lightfv(GLbyte*); +extern void __glXDispSwap_Lighti(GLbyte*); +extern void __glXDispSwap_Lightiv(GLbyte*); +extern void __glXDispSwap_LightModelf(GLbyte*); +extern void __glXDispSwap_LightModelfv(GLbyte*); +extern void __glXDispSwap_LightModeli(GLbyte*); +extern void __glXDispSwap_LightModeliv(GLbyte*); +extern void __glXDispSwap_LineStipple(GLbyte*); +extern void __glXDispSwap_LineWidth(GLbyte*); +extern void __glXDispSwap_Materialf(GLbyte*); +extern void __glXDispSwap_Materialfv(GLbyte*); +extern void __glXDispSwap_Materiali(GLbyte*); +extern void __glXDispSwap_Materialiv(GLbyte*); +extern void __glXDispSwap_PointSize(GLbyte*); +extern void __glXDispSwap_PolygonMode(GLbyte*); +extern void __glXDispSwap_PolygonStipple(GLbyte*); +extern void __glXDispSwap_Scissor(GLbyte*); +extern void __glXDispSwap_ShadeModel(GLbyte*); +extern void __glXDispSwap_TexParameterf(GLbyte*); +extern void __glXDispSwap_TexParameterfv(GLbyte*); +extern void __glXDispSwap_TexParameteri(GLbyte*); +extern void __glXDispSwap_TexParameteriv(GLbyte*); +extern void __glXDispSwap_TexImage1D(GLbyte*); +extern void __glXDispSwap_TexImage2D(GLbyte*); +extern void __glXDispSwap_TexEnvf(GLbyte*); +extern void __glXDispSwap_TexEnvfv(GLbyte*); +extern void __glXDispSwap_TexEnvi(GLbyte*); +extern void __glXDispSwap_TexEnviv(GLbyte*); +extern void __glXDispSwap_TexGend(GLbyte*); +extern void __glXDispSwap_TexGendv(GLbyte*); +extern void __glXDispSwap_TexGenf(GLbyte*); +extern void __glXDispSwap_TexGenfv(GLbyte*); +extern void __glXDispSwap_TexGeni(GLbyte*); +extern void __glXDispSwap_TexGeniv(GLbyte*); +extern void __glXDispSwap_InitNames(GLbyte*); +extern void __glXDispSwap_LoadName(GLbyte*); +extern void __glXDispSwap_PassThrough(GLbyte*); +extern void __glXDispSwap_PopName(GLbyte*); +extern void __glXDispSwap_PushName(GLbyte*); +extern void __glXDispSwap_DrawBuffer(GLbyte*); +extern void __glXDispSwap_Clear(GLbyte*); +extern void __glXDispSwap_ClearAccum(GLbyte*); +extern void __glXDispSwap_ClearIndex(GLbyte*); +extern void __glXDispSwap_ClearColor(GLbyte*); +extern void __glXDispSwap_ClearStencil(GLbyte*); +extern void __glXDispSwap_ClearDepth(GLbyte*); +extern void __glXDispSwap_StencilMask(GLbyte*); +extern void __glXDispSwap_ColorMask(GLbyte*); +extern void __glXDispSwap_DepthMask(GLbyte*); +extern void __glXDispSwap_IndexMask(GLbyte*); +extern void __glXDispSwap_Accum(GLbyte*); +extern void __glXDispSwap_Disable(GLbyte*); +extern void __glXDispSwap_Enable(GLbyte*); +extern void __glXDispSwap_PopAttrib(GLbyte*); +extern void __glXDispSwap_PushAttrib(GLbyte*); +extern void __glXDispSwap_Map1d(GLbyte*); +extern void __glXDispSwap_Map1f(GLbyte*); +extern void __glXDispSwap_Map2d(GLbyte*); +extern void __glXDispSwap_Map2f(GLbyte*); +extern void __glXDispSwap_MapGrid1d(GLbyte*); +extern void __glXDispSwap_MapGrid1f(GLbyte*); +extern void __glXDispSwap_MapGrid2d(GLbyte*); +extern void __glXDispSwap_MapGrid2f(GLbyte*); +extern void __glXDispSwap_EvalCoord1dv(GLbyte*); +extern void __glXDispSwap_EvalCoord1fv(GLbyte*); +extern void __glXDispSwap_EvalCoord2dv(GLbyte*); +extern void __glXDispSwap_EvalCoord2fv(GLbyte*); +extern void __glXDispSwap_EvalMesh1(GLbyte*); +extern void __glXDispSwap_EvalPoint1(GLbyte*); +extern void __glXDispSwap_EvalMesh2(GLbyte*); +extern void __glXDispSwap_EvalPoint2(GLbyte*); +extern void __glXDispSwap_AlphaFunc(GLbyte*); +extern void __glXDispSwap_BlendFunc(GLbyte*); +extern void __glXDispSwap_LogicOp(GLbyte*); +extern void __glXDispSwap_StencilFunc(GLbyte*); +extern void __glXDispSwap_StencilOp(GLbyte*); +extern void __glXDispSwap_DepthFunc(GLbyte*); +extern void __glXDispSwap_PixelZoom(GLbyte*); +extern void __glXDispSwap_PixelTransferf(GLbyte*); +extern void __glXDispSwap_PixelTransferi(GLbyte*); +extern void __glXDispSwap_PixelMapfv(GLbyte*); +extern void __glXDispSwap_PixelMapuiv(GLbyte*); +extern void __glXDispSwap_PixelMapusv(GLbyte*); +extern void __glXDispSwap_ReadBuffer(GLbyte*); +extern void __glXDispSwap_CopyPixels(GLbyte*); +extern void __glXDispSwap_DrawPixels(GLbyte*); +extern void __glXDispSwap_DepthRange(GLbyte*); +extern void __glXDispSwap_Frustum(GLbyte*); +extern void __glXDispSwap_LoadIdentity(GLbyte*); +extern void __glXDispSwap_LoadMatrixf(GLbyte*); +extern void __glXDispSwap_LoadMatrixd(GLbyte*); +extern void __glXDispSwap_MatrixMode(GLbyte*); +extern void __glXDispSwap_MultMatrixf(GLbyte*); +extern void __glXDispSwap_MultMatrixd(GLbyte*); +extern void __glXDispSwap_Ortho(GLbyte*); +extern void __glXDispSwap_PopMatrix(GLbyte*); +extern void __glXDispSwap_PushMatrix(GLbyte*); +extern void __glXDispSwap_Rotated(GLbyte*); +extern void __glXDispSwap_Rotatef(GLbyte*); +extern void __glXDispSwap_Scaled(GLbyte*); +extern void __glXDispSwap_Scalef(GLbyte*); +extern void __glXDispSwap_Translated(GLbyte*); +extern void __glXDispSwap_Translatef(GLbyte*); +extern void __glXDispSwap_Viewport(GLbyte*); +extern void __glXDispSwap_PolygonOffset(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); +extern void __glXDispSwap_Indexubv(GLbyte*); +extern void __glXDispSwap_ColorSubTable(GLbyte*); +extern void __glXDispSwap_CopyColorSubTable(GLbyte*); +extern void __glXDispSwap_ActiveTextureARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4svARB(GLbyte*); + +extern void __glXDispSwap_TexSubImage1D(GLbyte*); +extern void __glXDispSwap_TexSubImage2D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_ConvolutionParameterfv(GLbyte*); +extern void __glXDispSwap_ConvolutionParameteriv(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_SeparableFilter2D(GLbyte*); +extern void __glXDispSwap_TexImage3D(GLbyte*); +extern void __glXDispSwap_TexSubImage3D(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); +extern void __glXDispSwap_PrioritizeTextures(GLbyte*); +extern void __glXDispSwap_CopyTexImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage3D(GLbyte*); + +#define __GLX_MIN_GLXCMD_OPCODE 1 +#define __GLX_MAX_GLXCMD_OPCODE 20 +#define __GLX_MIN_RENDER_OPCODE 1 +#define __GLX_MAX_RENDER_OPCODE 213 +#define __GLX_MIN_SINGLE_OPCODE 1 +#define __GLX_MAX_SINGLE_OPCODE 159 +#define __GLX_SINGLE_TABLE_SIZE 160 +#define __GLX_RENDER_TABLE_SIZE 214 + +#define __GLX_MIN_RENDER_OPCODE_EXT 4096 +#define __GLX_MAX_RENDER_OPCODE_EXT 4123 + +extern __GLXdispatchSingleProcPtr __glXSingleTable[__GLX_SINGLE_TABLE_SIZE]; +extern __GLXdispatchSingleProcPtr __glXSwapSingleTable[__GLX_SINGLE_TABLE_SIZE]; +#endif /* _GLX_g_disptab_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab_EXT.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab_EXT.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/g_disptab_EXT.h (revision 51223) @@ -0,0 +1,159 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/g_disptab_EXT.h,v 1.5 2004/01/28 18:11:50 alanh Exp $ */ +/* DO NOT EDIT - THIS FILE IS AUTOMATICALLY GENERATED */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _GLX_g_disptab_EXT_h_ +#define _GLX_g_disptab_EXT_h_ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: This software was created using the +** OpenGL(R) version 1.2.1 Sample Implementation published by SGI, but has +** not been independently verified as being compliant with the OpenGL(R) +** version 1.2.1 Specification. +*/ + +extern int __glXDisp_AreTexturesResidentEXT(__GLXclientState*, GLbyte*); +extern int __glXDisp_DeleteTexturesEXT(__GLXclientState*, GLbyte*); +extern int __glXDisp_GenTexturesEXT(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsTextureEXT(__GLXclientState*, GLbyte*); + +extern void __glXDisp_ColorTable(GLbyte*); +extern void __glXDisp_ColorTableParameterfv(GLbyte*); +extern void __glXDisp_ColorTableParameteriv(GLbyte*); +extern void __glXDisp_CopyColorTable(GLbyte*); +extern void __glXDisp_BlendColor(GLbyte*); +extern void __glXDisp_BlendEquation(GLbyte*); +extern void __glXDisp_TexSubImage1D(GLbyte*); +extern void __glXDisp_TexSubImage2D(GLbyte*); +extern void __glXDisp_ConvolutionFilter1D(GLbyte*); +extern void __glXDisp_ConvolutionFilter2D(GLbyte*); +extern void __glXDisp_ConvolutionParameterf(GLbyte*); +extern void __glXDisp_ConvolutionParameterfv(GLbyte*); +extern void __glXDisp_ConvolutionParameteri(GLbyte*); +extern void __glXDisp_ConvolutionParameteriv(GLbyte*); +extern void __glXDisp_CopyConvolutionFilter1D(GLbyte*); +extern void __glXDisp_CopyConvolutionFilter2D(GLbyte*); +extern void __glXDisp_SeparableFilter2D(GLbyte*); +extern void __glXDisp_Histogram(GLbyte*); +extern void __glXDisp_Minmax(GLbyte*); +extern void __glXDisp_ResetHistogram(GLbyte*); +extern void __glXDisp_ResetMinmax(GLbyte*); +extern void __glXDisp_TexImage3D(GLbyte*); +extern void __glXDisp_TexSubImage3D(GLbyte*); +extern void __glXDisp_DrawArraysEXT(GLbyte*); +extern void __glXDisp_BindTexture(GLbyte*); +extern void __glXDisp_PrioritizeTextures(GLbyte*); +extern void __glXDisp_CopyTexImage1D(GLbyte*); +extern void __glXDisp_CopyTexImage2D(GLbyte*); +extern void __glXDisp_CopyTexSubImage1D(GLbyte*); +extern void __glXDisp_CopyTexSubImage2D(GLbyte*); +extern void __glXDisp_CopyTexSubImage3D(GLbyte*); +extern void __glXDisp_PointParameterfARB(GLbyte*); +extern void __glXDisp_PointParameterfvARB(GLbyte*); + +extern void __glXDisp_FogCoordfv(GLbyte *); +extern void __glXDisp_FogCoorddv(GLbyte *); +extern void __glXDispSwap_FogCoordfv(GLbyte *); +extern void __glXDispSwap_FogCoorddv(GLbyte *); + +extern void __glXDisp_SecondaryColor3bv(GLbyte *); +extern void __glXDisp_SecondaryColor3sv(GLbyte *); +extern void __glXDisp_SecondaryColor3iv(GLbyte *); +extern void __glXDisp_SecondaryColor3ubv(GLbyte *); +extern void __glXDisp_SecondaryColor3usv(GLbyte *); +extern void __glXDisp_SecondaryColor3uiv(GLbyte *); +extern void __glXDisp_SecondaryColor3fv(GLbyte *); +extern void __glXDisp_SecondaryColor3dv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3bv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3sv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3iv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3ubv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3usv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3uiv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3fv(GLbyte *); +extern void __glXDispSwap_SecondaryColor3dv(GLbyte *); + +extern void __glXDisp_BlendFuncSeparate(GLbyte *); +extern void __glXDispSwap_BlendFuncSeparate(GLbyte *); + +extern void __glXDisp_PointParameteriNV(GLbyte *); +extern void __glXDisp_PointParameterivNV(GLbyte *); +extern void __glXDispSwap_PointParameteriNV(GLbyte *); +extern void __glXDispSwap_PointParameterivNV(GLbyte *); + +extern void __glXDisp_ActiveStencilFaceEXT(GLbyte*); + +extern int __glXDispSwap_AreTexturesResidentEXT(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_DeleteTexturesEXT(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GenTexturesEXT(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsTextureEXT(__GLXclientState*, GLbyte*); + +extern void __glXDispSwap_ColorTable(GLbyte*); +extern void __glXDispSwap_ColorTableParameterfv(GLbyte*); +extern void __glXDispSwap_ColorTableParameteriv(GLbyte*); +extern void __glXDispSwap_CopyColorTable(GLbyte*); +extern void __glXDispSwap_BlendColor(GLbyte*); +extern void __glXDispSwap_BlendEquation(GLbyte*); +extern void __glXDispSwap_TexSubImage1D(GLbyte*); +extern void __glXDispSwap_TexSubImage2D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_ConvolutionParameterf(GLbyte*); +extern void __glXDispSwap_ConvolutionParameterfv(GLbyte*); +extern void __glXDispSwap_ConvolutionParameteri(GLbyte*); +extern void __glXDispSwap_ConvolutionParameteriv(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_SeparableFilter2D(GLbyte*); +extern void __glXDispSwap_Histogram(GLbyte*); +extern void __glXDispSwap_Minmax(GLbyte*); +extern void __glXDispSwap_ResetHistogram(GLbyte*); +extern void __glXDispSwap_ResetMinmax(GLbyte*); +extern void __glXDispSwap_TexImage3D(GLbyte*); +extern void __glXDispSwap_TexSubImage3D(GLbyte*); +extern void __glXDispSwap_DrawArraysEXT(GLbyte*); +extern void __glXDispSwap_BindTexture(GLbyte*); +extern void __glXDispSwap_PrioritizeTextures(GLbyte*); +extern void __glXDispSwap_CopyTexImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage3D(GLbyte*); +extern void __glXDispSwap_PointParameterfARB(GLbyte*); +extern void __glXDispSwap_PointParameterfvARB(GLbyte*); +extern void __glXDispSwap_ActiveStencilFaceEXT(GLbyte*); + +#define __GLX_MIN_RENDER_OPCODE_EXT 2053 +#define __GLX_MAX_RENDER_OPCODE_EXT 4222 +#define __GLX_MIN_VENDPRIV_OPCODE_EXT 11 +#define __GLX_MAX_VENDPRIV_OPCODE_EXT 14 +#define __GLX_VENDPRIV_TABLE_SIZE_EXT (__GLX_MAX_VENDPRIV_OPCODE_EXT - __GLX_MIN_VENDPRIV_OPCODE_EXT + 1) +#define __GLX_RENDER_TABLE_SIZE_EXT (__GLX_MAX_RENDER_OPCODE_EXT - __GLX_MIN_RENDER_OPCODE_EXT + 1) +extern __GLXdispatchRenderProcPtr __glXRenderTable_EXT[__GLX_RENDER_TABLE_SIZE_EXT]; +extern __GLXdispatchVendorPrivProcPtr __glXVendorPrivTable_EXT[__GLX_VENDPRIV_TABLE_SIZE_EXT]; +extern __GLXdispatchRenderProcPtr __glXSwapRenderTable_EXT[__GLX_RENDER_TABLE_SIZE_EXT]; +extern __GLXdispatchVendorPrivProcPtr __glXSwapVendorPrivTable_EXT[__GLX_VENDPRIV_TABLE_SIZE_EXT]; +#endif /* _GLX_g_disptab_EXT_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gc.h (revision 51223) @@ -0,0 +1,178 @@ +/* $XFree86: xc/programs/Xserver/include/gc.h,v 1.5 2001/12/14 19:59:54 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: gc.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef GC_H +#define GC_H + +#include /* for GContext, Mask */ +#include /* for Bool */ +#include +#include "screenint.h" /* for ScreenPtr */ +#include "pixmap.h" /* for DrawablePtr */ + +/* clientClipType field in GC */ +#define CT_NONE 0 +#define CT_PIXMAP 1 +#define CT_REGION 2 +#define CT_UNSORTED 6 +#define CT_YSORTED 10 +#define CT_YXSORTED 14 +#define CT_YXBANDED 18 + +#define GCQREASON_VALIDATE 1 +#define GCQREASON_CHANGE 2 +#define GCQREASON_COPY_SRC 3 +#define GCQREASON_COPY_DST 4 +#define GCQREASON_DESTROY 5 + +#define GC_CHANGE_SERIAL_BIT (((unsigned long)1)<<31) +#define GC_CALL_VALIDATE_BIT (1L<<30) +#define GCExtensionInterest (1L<<29) + +#define DRAWABLE_SERIAL_BITS (~(GC_CHANGE_SERIAL_BIT)) + +#define MAX_SERIAL_NUM (1L<<28) + +#define NEXT_SERIAL_NUMBER ((++globalSerialNumber) > MAX_SERIAL_NUM ? \ + (globalSerialNumber = 1): globalSerialNumber) + +typedef struct _GCInterest *GCInterestPtr; +typedef struct _GC *GCPtr; +typedef struct _GCOps *GCOpsPtr; + +extern void ValidateGC( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/); + +extern int ChangeGC( + GCPtr/*pGC*/, + BITS32 /*mask*/, + XID* /*pval*/); + +extern int DoChangeGC( + GCPtr/*pGC*/, + BITS32 /*mask*/, + XID* /*pval*/, + int /*fPointer*/); + +typedef union { + CARD32 val; + pointer ptr; +} ChangeGCVal, *ChangeGCValPtr; + +extern int dixChangeGC( + ClientPtr /*client*/, + GCPtr /*pGC*/, + BITS32 /*mask*/, + CARD32 * /*pval*/, + ChangeGCValPtr /*pCGCV*/); + +extern GCPtr CreateGC( + DrawablePtr /*pDrawable*/, + BITS32 /*mask*/, + XID* /*pval*/, + int* /*pStatus*/); + +extern int CopyGC( + GCPtr/*pgcSrc*/, + GCPtr/*pgcDst*/, + BITS32 /*mask*/); + +extern int FreeGC( + pointer /*pGC*/, + XID /*gid*/); + +extern void SetGCMask( + GCPtr /*pGC*/, + Mask /*selectMask*/, + Mask /*newDataMask*/); + +extern GCPtr CreateScratchGC( + ScreenPtr /*pScreen*/, + unsigned /*depth*/); + +extern void FreeGCperDepth( + int /*screenNum*/); + +extern Bool CreateGCperDepth( + int /*screenNum*/); + +extern Bool CreateDefaultStipple( + int /*screenNum*/); + +extern void FreeDefaultStipple( + int /*screenNum*/); + +extern int SetDashes( + GCPtr /*pGC*/, + unsigned /*offset*/, + unsigned /*ndash*/, + unsigned char* /*pdash*/); + +extern int VerifyRectOrder( + int /*nrects*/, + xRectangle* /*prects*/, + int /*ordering*/); + +extern int SetClipRects( + GCPtr /*pGC*/, + int /*xOrigin*/, + int /*yOrigin*/, + int /*nrects*/, + xRectangle* /*prects*/, + int /*ordering*/); + +extern GCPtr GetScratchGC( + unsigned /*depth*/, + ScreenPtr /*pScreen*/); + +extern void FreeScratchGC( + GCPtr /*pGC*/); + +#endif /* GC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gcstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gcstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gcstruct.h (revision 51223) @@ -0,0 +1,328 @@ +/* $Xorg: gcstruct.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + + +/* $XFree86: xc/programs/Xserver/include/gcstruct.h,v 1.7 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef GCSTRUCT_H +#define GCSTRUCT_H + +#include "gc.h" + +#include "regionstr.h" +#include "region.h" +#include "pixmap.h" +#include "screenint.h" +#include + +/* + * functions which modify the state of the GC + */ + +typedef struct _GCFuncs { + void (* ValidateGC)( + GCPtr /*pGC*/, + unsigned long /*stateChanges*/, + DrawablePtr /*pDrawable*/); + + void (* ChangeGC)( + GCPtr /*pGC*/, + unsigned long /*mask*/); + + void (* CopyGC)( + GCPtr /*pGCSrc*/, + unsigned long /*mask*/, + GCPtr /*pGCDst*/); + + void (* DestroyGC)( + GCPtr /*pGC*/); + + void (* ChangeClip)( + GCPtr /*pGC*/, + int /*type*/, + pointer /*pvalue*/, + int /*nrects*/); + + void (* DestroyClip)( + GCPtr /*pGC*/); + + void (* CopyClip)( + GCPtr /*pgcDst*/, + GCPtr /*pgcSrc*/); + DevUnion devPrivate; +} GCFuncs; + +/* + * graphics operations invoked through a GC + */ + +typedef struct _GCOps { + void (* FillSpans)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/); + + void (* SetSpans)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/); + + void (* PutImage)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pBits*/); + + RegionPtr (* CopyArea)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*w*/, + int /*h*/, + int /*dstx*/, + int /*dsty*/); + + RegionPtr (* CopyPlane)( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/); + void (* PolyPoint)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/); + + void (* Polylines)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/); + + void (* PolySegment)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegs*/); + + void (* PolyRectangle)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrects*/, + xRectangle * /*pRects*/); + + void (* PolyArc)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/); + + void (* FillPolygon)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*pPts*/); + + void (* PolyFillRect)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/); + + void (* PolyFillArc)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/); + + int (* PolyText8)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/); + + int (* PolyText16)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/); + + void (* ImageText8)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/); + + void (* ImageText16)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/); + + void (* ImageGlyphBlt)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/); + + void (* PolyGlyphBlt)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/); + + void (* PushPixels)( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDst*/, + int /*w*/, + int /*h*/, + int /*x*/, + int /*y*/); + +#ifdef NEED_LINEHELPER + void (* LineHelper)(); +#endif + + DevUnion devPrivate; +} GCOps; + +/* there is padding in the bit fields because the Sun compiler doesn't + * force alignment to 32-bit boundaries. losers. + */ +typedef struct _GC { + ScreenPtr pScreen; + unsigned char depth; + unsigned char alu; + unsigned short lineWidth; + unsigned short dashOffset; + unsigned short numInDashList; + unsigned char *dash; + unsigned int lineStyle : 2; + unsigned int capStyle : 2; + unsigned int joinStyle : 2; + unsigned int fillStyle : 2; + unsigned int fillRule : 1; + unsigned int arcMode : 1; + unsigned int subWindowMode : 1; + unsigned int graphicsExposures : 1; + unsigned int clientClipType : 2; /* CT_ */ + unsigned int miTranslate:1; /* should mi things translate? */ + unsigned int tileIsPixel:1; /* tile is solid pixel */ + unsigned int fExpose:1; /* Call exposure handling */ + unsigned int freeCompClip:1; /* Free composite clip */ + unsigned int unused:14; /* see comment above */ + unsigned long planemask; + unsigned long fgPixel; + unsigned long bgPixel; + /* + * alas -- both tile and stipple must be here as they + * are independently specifiable + */ + PixUnion tile; + PixmapPtr stipple; + DDXPointRec patOrg; /* origin for (tile, stipple) */ + struct _Font *font; + DDXPointRec clipOrg; + DDXPointRec lastWinOrg; /* position of window last validated */ + pointer clientClip; + unsigned long stateChanges; /* masked with GC_ */ + unsigned long serialNumber; + GCFuncs *funcs; + GCOps *ops; + DevUnion *devPrivates; + /* + * The following were moved here from private storage to allow device- + * independent access to them from screen wrappers. + * --- 1997.11.03 Marc Aurele La France (tsi@xfree86.org) + */ + PixmapPtr pRotatedPixmap; /* tile/stipple rotated for alignment */ + RegionPtr pCompositeClip; + /* fExpose & freeCompClip defined above */ +} GC; + +#endif /* GCSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getbmap.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getbmap.h,v 3.1 1996/04/15 11:18:37 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETBMAP_H +#define GETBMAP_H 1 + +int +SProcXGetDeviceButtonMapping( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceButtonMapping ( + ClientPtr /* client */ + ); + +void +SRepXGetDeviceButtonMapping ( + ClientPtr /* client */, + int /* size */, + xGetDeviceButtonMappingReply * /* rep */ + ); + +#endif /* GETBMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getdctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getdctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getdctl.h (revision 51223) @@ -0,0 +1,59 @@ +/* $XFree86: xc/programs/Xserver/Xi/getdctl.h,v 3.1 1996/04/15 11:18:38 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETDCTL_H +#define GETDCTL_H 1 + +int +SProcXGetDeviceControl ( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceControl ( + ClientPtr /* client */ + ); + +void +CopySwapDeviceResolution ( + ClientPtr /* client */, + ValuatorClassPtr /* v */, + char * /* buf */, + int /* length */ + ); + +void +SRepXGetDeviceControl ( + ClientPtr /* client */, + int /* size */, + xGetDeviceControlReply * /* rep */ + ); + +#endif /* GETDCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfctl.h (revision 51223) @@ -0,0 +1,93 @@ +/* $XFree86: xc/programs/Xserver/Xi/getfctl.h,v 3.1 1996/04/15 11:18:39 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETFCTL_H +#define GETFCTL_H 1 + +int +SProcXGetFeedbackControl( + ClientPtr /* client */ + ); + +int +ProcXGetFeedbackControl( + ClientPtr /* client */ + ); + +void +CopySwapKbdFeedback ( + ClientPtr /* client */, + KbdFeedbackPtr /* k */, + char ** /* buf */ + ); + +void +CopySwapPtrFeedback ( + ClientPtr /* client */, + PtrFeedbackPtr /* p */, + char ** /* buf */ + ); + +void +CopySwapIntegerFeedback ( + ClientPtr /* client */, + IntegerFeedbackPtr /* i */, + char ** /* buf */ + ); + +void +CopySwapStringFeedback ( + ClientPtr /* client */, + StringFeedbackPtr /* s */, + char ** /* buf */ + ); + +void +CopySwapLedFeedback ( + ClientPtr /* client */, + LedFeedbackPtr /* l */, + char ** /* buf */ + ); + +void +CopySwapBellFeedback ( + ClientPtr /* client */, + BellFeedbackPtr /* b */, + char ** /* buf */ + ); + +void +SRepXGetFeedbackControl ( + ClientPtr /* client */, + int /* size */, + xGetFeedbackControlReply * /* rep */ + ); + +#endif /* GETFCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfocus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfocus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getfocus.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getfocus.h,v 3.1 1996/04/15 11:18:40 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETFOCUS_H +#define GETFOCUS_H 1 + +int +SProcXGetDeviceFocus( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceFocus( + ClientPtr /* client */ + ); + +void +SRepXGetDeviceFocus ( + ClientPtr /* client */, + int /* size */, + xGetDeviceFocusReply * /* rep */ + ); + +#endif /* GETFOCUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getkmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getkmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getkmap.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getkmap.h,v 3.1 1996/04/15 11:18:41 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETKMAP_H +#define GETKMAP_H 1 + +int +SProcXGetDeviceKeyMapping( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceKeyMapping( + ClientPtr /* client */ + ); + +void +SRepXGetDeviceKeyMapping ( + ClientPtr /* client */, + int /* size */, + xGetDeviceKeyMappingReply * /* rep */ + ); + +#endif /* GETKMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getmmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getmmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getmmap.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getmmap.h,v 3.1 1996/04/15 11:18:42 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETMMAP_H +#define GETMMAP_H 1 + +int +SProcXGetDeviceModifierMapping( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceModifierMapping( + ClientPtr /* client */ + ); + +void +SRepXGetDeviceModifierMapping ( + ClientPtr /* client */, + int /* size */, + xGetDeviceModifierMappingReply * /* rep */ + ); + +#endif /* GETMMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getprop.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86: xc/programs/Xserver/Xi/getprop.h,v 3.1 1996/04/15 11:18:44 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETPROP_H +#define GETPROP_H 1 + +int +SProcXGetDeviceDontPropagateList( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceDontPropagateList ( + ClientPtr /* client */ + ); + +XEventClass * +ClassFromMask ( + XEventClass * /* buf */, + Mask /* mask */, + int /* maskndx */, + CARD16 * /* count */, + int /* mode */ + ); + +void +SRepXGetDeviceDontPropagateList ( + ClientPtr /* client */, + int /* size */, + xGetDeviceDontPropagateListReply * /* rep */ + ); + +#endif /* GETPROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getselev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getselev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getselev.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getselev.h,v 3.1 1996/04/15 11:18:49 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETSELEV_H +#define GETSELEV_H 1 + +int +SProcXGetSelectedExtensionEvents( + ClientPtr /* client */ + ); + +int +ProcXGetSelectedExtensionEvents( + ClientPtr /* client */ + ); + +void +SRepXGetSelectedExtensionEvents ( + ClientPtr /* client */, + int /* size */, + xGetSelectedExtensionEventsReply * /* rep */ + ); + +#endif /* GETSELEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getvers.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getvers.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/getvers.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/getvers.h,v 3.1 1996/04/15 11:18:50 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETVERS_H +#define GETVERS_H 1 + +int +SProcXGetExtensionVersion( + ClientPtr /* client */ + ); + +int +ProcXGetExtensionVersion ( + ClientPtr /* client */ + ); + +void +SRepXGetExtensionVersion ( + ClientPtr /* client */, + int /* size */, + xGetExtensionVersionReply * /* rep */ + ); + +#endif /* GETVERS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glcontextmodes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glcontextmodes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glcontextmodes.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * (C) Copyright IBM Corporation 2003 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEM, IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * \file glcontextmodes.h + * \author Ian Romanick + */ + +#ifndef GLCONTEXTMODES_H +#define GLCONTEXTMODES_H + +#include "GL/internal/glcore.h" + +#if !defined(IN_MINI_GLX) +extern GLint _gl_convert_from_x_visual_type( int visualType ); +extern GLint _gl_convert_to_x_visual_type( int visualType ); +extern void _gl_copy_visual_to_context_mode( __GLcontextModes * mode, + const __GLXvisualConfig * config ); +extern int _gl_get_context_mode_data( const __GLcontextModes *mode, + int attribute, int *value_return ); +#endif /* !defined(IN_MINI_GLX) */ + +extern __GLcontextModes * _gl_context_modes_create( unsigned count, + size_t minimum_size ); +extern void _gl_context_modes_destroy( __GLcontextModes * modes ); +extern __GLcontextModes * _gl_context_modes_find_visual( + __GLcontextModes * modes, int vid ); +extern GLboolean _gl_context_modes_are_same( const __GLcontextModes * a, + const __GLcontextModes * b ); + +#endif /* GLCONTEXTMODES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/globals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/globals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/globals.h (revision 51223) @@ -0,0 +1,192 @@ +/* $XdotOrg: xc/programs/Xserver/include/globals.h,v 1.6 2005/05/19 18:53:49 ajax Exp $ */ +/* $XFree86: xc/programs/Xserver/include/globals.h,v 1.3 1999/09/25 14:38:21 dawes Exp $ */ + +#ifndef _XSERV_GLOBAL_H_ +#define _XSERV_GLOBAL_H_ + +#include "window.h" /* for WindowPtr */ + +/* Global X server variables that are visible to mi, dix, os, and ddx */ + +extern CARD32 defaultScreenSaverTime; +extern CARD32 defaultScreenSaverInterval; +extern CARD32 ScreenSaverTime; +extern CARD32 ScreenSaverInterval; + +extern char *defaultFontPath; +extern char *rgbPath; +extern int monitorResolution; +extern Bool loadableFonts; +extern int defaultColorVisualClass; + +extern Bool Must_have_memory; +extern WindowPtr *WindowTable; +extern int GrabInProgress; +extern Bool noTestExtensions; + +extern DDXPointRec dixScreenOrigins[MAXSCREENS]; + +#ifdef DPMSExtension +extern CARD32 defaultDPMSStandbyTime; +extern CARD32 defaultDPMSSuspendTime; +extern CARD32 defaultDPMSOffTime; +extern CARD32 DPMSStandbyTime; +extern CARD32 DPMSSuspendTime; +extern CARD32 DPMSOffTime; +extern CARD16 DPMSPowerLevel; +extern Bool defaultDPMSEnabled; +extern Bool DPMSEnabled; +extern Bool DPMSEnabledSwitch; +extern Bool DPMSDisabledSwitch; +extern Bool DPMSCapableFlag; +#endif + +#ifdef PANORAMIX +extern Bool PanoramiXMapped; +extern Bool PanoramiXVisibilityNotifySent; +extern Bool PanoramiXWindowExposureSent; +extern Bool PanoramiXOneExposeRequest; +#endif + +#ifdef BIGREQS +extern Bool noBigReqExtension; +#endif + +#ifdef COMPOSITE +extern Bool noCompositeExtension; +#endif + +#ifdef DAMAGE +extern Bool noDamageExtension; +#endif + +#ifdef DBE +extern Bool noDbeExtension; +#endif + +#ifdef DPSEXT +extern Bool noDPSExtension; +#endif + +#ifdef DPMSExtension +extern Bool noDPMSExtension; +#endif + +#ifdef EVI +extern Bool noEVIExtension; +#endif + +#ifdef FONTCACHE +extern Bool noFontCacheExtension; +#endif + +#ifdef GLXEXT +extern Bool noGlxExtension; +#endif + +#ifdef LBX +extern Bool noLbxExtension; +#endif + +#ifdef SCREENSAVER +extern Bool noScreenSaverExtension; +#endif + +#ifdef MITSHM +extern Bool noMITShmExtension; +#endif + +#ifdef MITMISC +extern Bool noMITMiscExtension; +#endif + +#ifdef MULTIBUFFER +extern Bool noMultibufferExtension; +#endif + +#ifdef RANDR +extern Bool noRRExtension; +#endif + +#ifdef RENDER +extern Bool noRenderExtension; +#endif + +#ifdef SHAPE +extern Bool noShapeExtension; +#endif + +#ifdef XCSECURITY +extern Bool noSecurityExtension; +#endif + +#ifdef XSYNC +extern Bool noSyncExtension; +#endif + +#ifdef TOGCUP +extern Bool noXcupExtension; +#endif + +#ifdef RES +extern Bool noResExtension; +#endif + +#ifdef XAPPGROUP +extern Bool noXagExtension; +#endif + +#ifdef XCMISC +extern Bool noXCMiscExtension; +#endif + +#ifdef XEVIE +extern Bool noXevieExtension; +#endif + +#ifdef XF86BIGFONT +extern Bool noXFree86BigfontExtension; +#endif + +#ifdef XFreeXDGA +extern Bool noXFree86DGAExtension; +#endif + +#ifdef XF86DRI +extern Bool noXFree86DRIExtension; +#endif + +#ifdef XF86MISC +extern Bool noXFree86MiscExtension; +#endif + +#ifdef XF86VIDMODE +extern Bool noXFree86VidModeExtension; +#endif + +#ifdef XFIXES +extern Bool noXFixesExtension; +#endif + +#ifdef XKB +/* |noXkbExtension| is defined in xc/programs/Xserver/xkb/xkbInit.c */ +extern Bool noXkbExtension; +#endif + +#ifdef PANORAMIX +extern Bool noPanoramiXExtension; +#endif + +#ifdef XINPUT +extern Bool noXInputExtension; +#endif + +#ifdef XIDLE +extern Bool noXIdleExtension; +#endif + +#ifdef XV +extern Bool noXvExtension; +#endif + +#endif /* !_XSERV_GLOBAL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glwindows.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glwindows.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glwindows.h (revision 51223) @@ -0,0 +1,64 @@ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +typedef struct { + unsigned enableDebug : 1; + unsigned enableTrace : 1; + unsigned dumpPFD : 1; + unsigned dumpHWND : 1; + unsigned dumpDC : 1; +} glWinDebugSettingsRec, *glWinDebugSettingsPtr; +extern glWinDebugSettingsRec glWinDebugSettings; + +typedef struct { + int num_vis; + __GLcontextModes *modes; + void **priv; + + /* wrapped screen functions */ + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + CopyWindowProcPtr CopyWindow; +} glWinScreenRec; + +extern glWinScreenRec glWinScreens[MAXSCREENS]; + +#define glWinGetScreenPriv(pScreen) &glWinScreens[pScreen->myNum] +#define glWinScreenPriv(pScreen) glWinScreenRec *pScreenPriv = glWinGetScreenPriv(pScreen); + +#if 1 +#define GLWIN_TRACE() if (glWinDebugSettings.enableTrace) ErrorF("%s:%d: Trace\n", __FUNCTION__, __LINE__ ) +#define GLWIN_TRACE_MSG(msg, args...) if (glWinDebugSettings.enableTrace) ErrorF("%s:%d: " msg, __FUNCTION__, __LINE__, ##args ) +#define GLWIN_DEBUG_MSG(msg, args...) if (glWinDebugSettings.enableDebug) ErrorF("%s:%d: " msg, __FUNCTION__, __LINE__, ##args ) +#define GLWIN_DEBUG_MSG2(msg, args...) if (glWinDebugSettings.enableDebug) ErrorF(msg, ##args ) +#else +#define GLWIN_TRACE() +#define GLWIN_TRACE_MSG(a, ...) +#define GLWIN_DEBUG_MSG(a, ...) +#define GLWIN_DEBUG_MSG2(a, ...) +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glx_ansic.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glx_ansic.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glx_ansic.h (revision 51223) @@ -0,0 +1,115 @@ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glx_ansic_h_ +#define _glx_ansic_h_ + +/* $XFree86: xc/programs/Xserver/GL/include/GL/glx_ansic.h,v 1.5 2001/03/21 20:49:08 dawes Exp $ */ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +*/ + +/* +** this needs to check whether we're using XFree86 at all, and then +** which version we're using. Use these macros if version is 3.9+, else +** use normal commands below. +*/ + +/* +** turns out this include file only exists for XFree86 3.9+ +** I notice that not having it is not an error and does not stop the build, +** but having it will allow opengl and glx to be built for 3.9+. We no longer +** need an explicit define in the Makefile, just point to the correct X source +** tree and all should be taken care of. +*/ + +#ifdef XFree86Server + +#ifdef XFree86LOADER +#include "xf86_ansic.h" +#endif +#ifndef assert +#define assert(a) +#endif + +#else + +#if defined(Lynx) && defined(__assert_h) +#undef __assert_h +#endif +#ifdef assert +#undef assert +#endif +#include + +#endif + + +#define GLX_STDOUT stdout +#define GLX_STDERR stderr +#define __glXPrintf printf +#define __glXFprintf fprintf +#define __glXSprintf sprintf +#define __glXVfprintf vfprintf +#define __glXVsprintf vsprintf +#define __glXFopen fopen +#define __glXFclose fclose +#define __glXCos(x) cos(x) +#define __glXSin(x) sin(x) +#define __glXAtan(x) atan(x) +#define __glXAbs(x) abs(x) +#define __glXLog(x) log(x) +#define __glXCeil(x) ceil(x) +#define __glXFloor(x) floor(x) +#define __glXSqrt(x) sqrt(x) +#define __glXPow(x, y) pow(x, y) +#define __glXMemmove(dest, src, n) memmove(dest, src, n) +#define __glXMemcpy(dest, src, n) memcpy(dest, src, n) +#define __glXMemset(s, c, n) memset(s, c, n) +#define __glXStrdup(str) xstrdup(str) +#define __glXStrcpy(dest, src) strcpy(dest, src) +#define __glXStrncpy(dest, src, n) strncpy(dest, src, n) +#define __glXStrcat(dest, src) strcat(dest, src) +#define __glXStrncat(dest, src, n) strncat(dest, src, n) +#define __glXStrcmp(s1, s2) strcmp(s1, s2) +#define __glXStrncmp(s1, s2, n) strncmp(s1, s2, n) +#define __glXStrlen(str) strlen(str) +#define __glXAbort() abort() +#define __glXStrtok(s, delim) strtok(s, delim) +#define __glXStrcspn(s, reject) strcspn(s, reject) +#define __glXGetenv(a) getenv(a) +#define __glXAtoi(a) atoi(a) + +#endif /* _glx_ansic_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxbuf.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxbuf.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxbuf.h (revision 51223) @@ -0,0 +1,57 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glxbuf_h_ +#define _glxbuf_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXFBInitDrawable(__GLXdrawablePrivate *glxPriv, + __GLcontextModes *modes); +extern void __glXPixInitDrawable(__GLXdrawablePrivate *glxPriv, + __GLcontextModes *modes); + +extern GLboolean __glXResizeBuffers(__GLdrawablePrivate *glPriv, + GLint x, GLint y, + GLuint width, GLuint height); + +extern void __glXFreeBuffers(__GLXdrawablePrivate *glxPriv); +extern void __glXUpdatePalette(__GLXdrawablePrivate *); + +#endif /* _glxbuf_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxcontext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxcontext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxcontext.h (revision 51223) @@ -0,0 +1,117 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxcontext.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_context_h_ +#define _GLX_context_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +typedef struct __GLXcontextRec __GLXcontext; + +#include "GL/internal/glcore.h" + +struct __GLXcontextRec { + /* + ** list of context structs + */ + struct __GLXcontextRec *last; + struct __GLXcontextRec *next; + + /* + ** Pointer to screen info data for this context. This is set + ** when the context is created. + */ + ScreenPtr pScreen; + __GLXscreenInfo *pGlxScreen; + + /* + ** This context is created with respect to this visual. + */ + VisualRec *pVisual; + __GLXvisualConfig *pGlxVisual; + __GLXFBConfig *pFBConfig; + + /* + ** The XID of this context. + */ + XID id; + XID *real_ids; + + /* + ** The XID of the shareList context. + */ + XID share_id; + + /* + ** Visual id. + */ + VisualID vid; + VisualID *real_vids; + + /* + ** screen number. + */ + GLint screen; + + /* + ** Whether this context's ID still exists. + */ + GLboolean idExists; + + /* + ** Whether this context is current for some client. + */ + GLboolean isCurrent; + + /* + ** Buffers for feedback and selection. + */ + GLfloat *feedbackBuf; + GLint feedbackBufSize; /* number of elements allocated */ + GLuint *selectBuf; + GLint selectBufSize; /* number of elements allocated */ + + /* + ** Set only if current drawable is a glx pixmap. + */ + __GLXpixmap *pGlxPixmap; + __GLXpixmap *pGlxReadPixmap; + __glXWindow *pGlxWindow; + __glXWindow *pGlxReadWindow; + __glXPbuffer *pGlxPbuffer; + __glXPbuffer *pGlxReadPbuffer; + +}; + +#endif /* !__GLX_context_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxdrawable.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxdrawable.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxdrawable.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxdrawable.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_drawable_h_ +#define _GLX_drawable_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +typedef struct { + + DrawablePtr pDraw; + __GLXvisualConfig *pGlxVisual; + __GLXscreenInfo *pGlxScreen; + __GLXFBConfig *pFBConfig; + ScreenPtr pScreen; + Bool idExists; + int refcnt; + XID *be_xids; + +} __GLXpixmap; + +struct __GLXdrawablePrivateRec { + /* + ** list of drawable private structs + */ + struct __GLXdrawablePrivateRec *last; + struct __GLXdrawablePrivateRec *next; + + DrawablePtr pDraw; + XID drawId; + __GLXpixmap *pGlxPixmap; + + /* + ** Either DRAWABLE_PIXMAP or DRAWABLE_WINDOW, copied from pDraw above. + ** Needed by the resource freer because pDraw might already have been + ** freed. + */ + int type; + + /* + ** Configuration of the visual to which this drawable was created. + */ + __GLXvisualConfig *pGlxVisual; + + /* + ** cached drawable size and origin + */ + GLint xorigin, yorigin; + GLint width, height; + + /* + ** list of contexts bound to this drawable + */ + struct __GLXcontextRec *glxc; + + /* + ** "methods" that the drawble should be able to respond to. + */ + void (*freeBuffers)(struct __GLXdrawablePrivateRec *); + void (*updatePalette)(struct __GLXdrawablePrivateRec *); + GLboolean (*swapBuffers)(struct __GLXdrawablePrivateRec *); + + /* + ** The GL drawable (information shared between GLX and the GL core) + */ + __GLdrawablePrivate glPriv; + + /* + ** reference count + */ + int refCount; +}; + +typedef struct { + DrawablePtr pDraw; + int type; + Bool idExists; + int refcnt; /* contexts bound */ + __GLXFBConfig *pGlxFBConfig; + ScreenPtr pScreen; +} __glXWindow; + + +typedef struct { + __GLXscreenInfo *pGlxScreen; + __GLXFBConfig *pFBConfig; + ScreenPtr pScreen; + Bool idExists; + int refcnt; + XID *be_xids; +} __glXPbuffer; + +#endif /* !__GLX_drawable_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxerror.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxerror.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxerror.h (revision 51223) @@ -0,0 +1,58 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxerror.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_error_h_ +#define _GLX_error_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +/* +** Error codes. These have the extension error base added to them +** when the extension initializes. +*/ +extern int __glXerrorBase; +extern int __glXBadContext; +extern int __glXBadContextState; +extern int __glXBadDrawable; +extern int __glXBadPixmap; +extern int __glXBadCurrentWindow; +extern int __glXBadContextTag; +extern int __glXBadRenderRequest; +extern int __glXBadLargeRequest; +extern int __glXUnsupportedPrivateRequest; +extern int __glXBadFBConfig; +extern int __glXBadPbuffer; + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxext.h (revision 51223) @@ -0,0 +1,98 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxext.h,v 1.4 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _glxext_h_ +#define _glxext_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +/* + * Added by VA Linux for XFree86 4.0.x + */ +typedef struct { + int type; + void (*resetExtension)(void); + Bool (*initVisuals)( + VisualPtr * visualp, + DepthPtr * depthp, + int * nvisualp, + int * ndepthp, + int * rootDepthp, + VisualID * defaultVisp, + unsigned long sizes, + int bitsPerRGB + ); + void (*setVisualConfigs)( + int nconfigs, + __GLXvisualConfig *configs, + void **privates + ); +} __GLXextensionInfo; + +extern GLboolean __glXFreeContext(__GLXcontext *glxc); +extern void __glXFlushContextCache(void); + +extern void __glXFreeGLXWindow(__glXWindow *pGlxWindow); +extern void __glXFreeGLXPixmap( __GLXpixmap *pGlxPixmap ); + +extern void __glXNoSuchRenderOpcode(GLbyte*); +extern int __glXNoSuchSingleOpcode(__GLXclientState*, GLbyte*); +extern void __glXErrorCallBack(__GLinterface *gc, GLenum code); +extern void __glXClearErrorOccured(void); +extern GLboolean __glXErrorOccured(void); +extern void __glXResetLargeCommandStatus(__GLXclientState*); + +extern int __glXQueryContextInfoEXT(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapQueryContextInfoEXT(__GLXclientState *cl, char *pc); + +extern void GlxExtensionInit(void); + +extern Bool __glXCoreType(void); + +extern int GlxInitVisuals( +#if NeedFunctionPrototypes + VisualPtr * visualp, + DepthPtr * depthp, + int * nvisualp, + int * ndepthp, + int * rootDepthp, + VisualID * defaultVisp, + unsigned long sizes, + int bitsPerRGB, + int preferredVis +#endif +); + +#endif /* _glxext_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfb.h (revision 51223) @@ -0,0 +1,52 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glxfb_h_ +#define _glxfb_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXInitFB(__GLdrawableBuffer *buf, __GLdrawablePrivate *glPriv, + GLint bits); + +extern GCPtr __glXFBGetGC(__GLdrawableBuffer *buf); + +extern GLboolean __glXFBMemSwapBuffers(__GLXdrawablePrivate *glxPriv); + +#endif /* _glxfb_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfbconfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfbconfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxfbconfig.h (revision 51223) @@ -0,0 +1,43 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLXFBCONFIG_H + +#include + +int AreFBConfigsMatch( __GLXFBConfig *c1, __GLXFBConfig *c2 ); +__GLXFBConfig *FindMatchingFBConfig( __GLXFBConfig *c, __GLXFBConfig *configs, int nconfigs ); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glximports.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glximports.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glximports.h (revision 51223) @@ -0,0 +1,66 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glximports.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glximports_h_ +#define _glximports_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void *__glXImpMalloc(__GLcontext *gc, size_t size); +extern void *__glXImpCalloc(__GLcontext *gc, size_t nElem, size_t eSize); +extern void *__glXImpRealloc(__GLcontext *gc, void *addr, size_t newSize); +extern void __glXImpFree(__GLcontext *gc, void *addr); + +extern void __glXImpWarning(__GLcontext *gc, char *msg); +extern void __glXImpFatal(__GLcontext *gc, char *msg); + +extern char *__glXImpGetenv(__GLcontext *gc, const char *var); +extern int __glXImpAtoi(__GLcontext *gc, const char *str); +extern int __glXImpSprintf(__GLcontext *gc, char *str, const char *fmt, ...); +extern void *__glXImpFopen(__GLcontext *gc, const char *path, + const char *mode); +extern int __glXImpFclose(__GLcontext *gc, void *stream); +extern int __glXImpFprintf(__GLcontext *gc, void *stream, + const char *fmt, ...); + +extern __GLdrawablePrivate *__glXImpGetDrawablePrivate(__GLcontext *gc); +extern __GLdrawablePrivate *__glXImpGetReadablePrivate(__GLcontext *gc); + + +#endif /* _glximports_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxmem.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxmem.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxmem.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glxmem_h_ +#define _glxmem_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXInitMem(__GLdrawableBuffer *buf, __GLdrawablePrivate *glPriv, + GLint bits); + +#endif /* _glxmem_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxpix.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxpix.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxpix.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glxpix_h_ +#define _glxpix_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXInitPix(__GLdrawableBuffer *buf, __GLdrawablePrivate *glPriv, + GLint bits, XID glxpixmapId, __GLXpixmap *pGlxPixmap); + +#endif /* _glxpix_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxscreens.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxscreens.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxscreens.h (revision 51223) @@ -0,0 +1,63 @@ +#ifndef _GLX_screens_h_ +#define _GLX_screens_h_ + +/* $XFree86: xc/programs/Xserver/GL/glx/glxscreens.h,v 1.4 2001/03/21 16:29:37 dawes Exp $ */ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "GL/internal/glcore.h" + + + +typedef struct { + + __GLXvisualConfig *pGlxVisual; + GLint numVisuals; + GLint numGLXVisuals; + GLint *isGLXvis; + + char *GLXvendor; + char *GLXversion; + char *GLXextensions; + +} __GLXscreenInfo; + + +extern void __glXScreenInit(GLint); +extern void __glXScreenReset(void); + +extern char *__glXGetServerString( unsigned int name ); + +#endif /* !__GLX_screens_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxserver.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxserver.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxserver.h (revision 51223) @@ -0,0 +1,327 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxserver.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef _GLX_server_h_ +#define _GLX_server_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "dmx.h" + +#include +#include +#include +#include +#include +#include +#include +#include "GL/glx_ansic.h" + + +/* +** The X header misc.h defines these math functions. +*/ +#undef abs +#undef fabs + +#define GL_GLEXT_PROTOTYPES /* we want prototypes */ +#include +#include +#include + +/* For glxscreens.h */ +typedef struct __GLXdrawablePrivateRec __GLXdrawablePrivate; + +#include "glxscreens.h" +#include "glxdrawable.h" +#include "glxcontext.h" +#include "glxerror.h" + + +#define GLX_SERVER_MAJOR_VERSION 1 +#define GLX_SERVER_MINOR_VERSION 3 + +#ifndef True +#define True 1 +#endif +#ifndef False +#define False 0 +#endif + +/* +** GLX resources. +typedef XID GLXContextID; +typedef XID GLXPixmap; +typedef XID GLXDrawable; +typedef XID GLXWindow; +typedef XID GLXPbuffer; + +typedef struct __GLXcontextRec *GLXContext; +*/ +typedef struct __GLXclientStateRec __GLXclientState; + +extern __GLXscreenInfo *__glXActiveScreens; +extern GLint __glXNumActiveScreens; + +/************************************************************************/ + +/* +** The last context used (from the server's persective) is cached. +*/ +extern __GLXcontext *__glXLastContext; +extern __GLXcontext *__glXForceCurrent(__GLXclientState*, GLXContextTag, int*); + +/* +** Macros to set, unset, and retrieve the flag that says whether a context +** has unflushed commands. +*/ +#define __GLX_NOTE_UNFLUSHED_CMDS(glxc) glxc->hasUnflushedCommands = GL_TRUE +#define __GLX_NOTE_FLUSHED_CMDS(glxc) glxc->hasUnflushedCommands = GL_FALSE +#define __GLX_HAS_UNFLUSHED_CMDS(glxc) (glxc->hasUnflushedCommands) + +/************************************************************************/ + +typedef struct { + int elem_size; /* element size in bytes */ + int nelems; /* number of elements to swap */ + void (*swapfunc)(GLbyte *pc); +} __GLXRenderSwapInfo; + +/* +** State kept per client. +*/ +struct __GLXclientStateRec { + /* + ** Whether this structure is currently being used to support a client. + */ + Bool inUse; + + /* + ** Buffer for returned data. + */ + GLbyte *returnBuf; + GLint returnBufSize; + + /* + ** Keep a list of all the contexts that are current for this client's + ** threads. + */ + __GLXcontext **currentContexts; + DrawablePtr *currentDrawables; + GLint numCurrentContexts; + + /* Back pointer to X client record */ + ClientPtr client; + + int GLClientmajorVersion; + int GLClientminorVersion; + char *GLClientextensions; + + GLXContextTag *be_currentCTag; + Display **be_displays; + + /* + ** Keep track of large rendering commands, which span multiple requests. + */ + GLint largeCmdBytesSoFar; /* bytes received so far */ + GLint largeCmdBytesTotal; /* total bytes expected */ + GLint largeCmdRequestsSoFar; /* requests received so far */ + GLint largeCmdRequestsTotal; /* total requests expected */ + void (*largeCmdRequestsSwapProc)(GLbyte *); + __GLXRenderSwapInfo *largeCmdRequestsSwap_info; + GLbyte *largeCmdBuf; + GLint largeCmdBufSize; + GLint largeCmdMaxReqDataSize; + +}; + +extern __GLXclientState *__glXClients[]; + +/************************************************************************/ + +/* +** Dispatch tables. +*/ +typedef void (*__GLXdispatchRenderProcPtr)(GLbyte *); +typedef int (*__GLXdispatchSingleProcPtr)(__GLXclientState *, GLbyte *); +typedef int (*__GLXdispatchVendorPrivProcPtr)(__GLXclientState *, GLbyte *); +extern __GLXdispatchSingleProcPtr __glXSingleTable[]; +extern __GLXdispatchVendorPrivProcPtr __glXVendorPrivTable_EXT[]; +extern __GLXdispatchSingleProcPtr __glXSwapSingleTable[]; +extern __GLXdispatchVendorPrivProcPtr __glXSwapVendorPrivTable_EXT[]; +extern __GLXdispatchRenderProcPtr __glXSwapRenderTable[]; + +extern __GLXRenderSwapInfo __glXSwapRenderTable_EXT[]; + +/* + * Dispatch for GLX commands. + */ +typedef int (*__GLXprocPtr)(__GLXclientState *, char *pc); +extern __GLXprocPtr __glXProcTable[]; + +/* + * Tables for computing the size of each rendering command. + */ +typedef struct { + int bytes; + int (*varsize)(GLbyte *pc, Bool swap); +} __GLXrenderSizeData; +extern __GLXrenderSizeData __glXRenderSizeTable[]; +extern __GLXrenderSizeData __glXRenderSizeTable_EXT[]; + +/************************************************************************/ + +/* +** X resources. +*/ +extern RESTYPE __glXContextRes; +extern RESTYPE __glXClientRes; +extern RESTYPE __glXPixmapRes; +extern RESTYPE __glXDrawableRes; +extern RESTYPE __glXWindowRes; +extern RESTYPE __glXPbufferRes; + +/************************************************************************/ + +/* +** Prototypes. +*/ + + +extern char *__glXcombine_strings(const char *, const char *); + +extern void __glXDisp_DrawArrays(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); + + +/* +** Routines for sending swapped replies. +*/ + +extern void __glXSwapMakeCurrentReply(ClientPtr client, + xGLXMakeCurrentReadSGIReply *reply); + +extern void __glXSwapIsDirectReply(ClientPtr client, + xGLXIsDirectReply *reply); +extern void __glXSwapQueryVersionReply(ClientPtr client, + xGLXQueryVersionReply *reply); +extern void __glXSwapQueryContextInfoEXTReply(ClientPtr client, + xGLXQueryContextInfoEXTReply *reply, + int *buf); +extern void glxSwapQueryExtensionsStringReply(ClientPtr client, + xGLXQueryExtensionsStringReply *reply, char *buf); +extern void glxSwapQueryServerStringReply(ClientPtr client, + xGLXQueryServerStringReply *reply, char *buf); +extern void __glXSwapQueryContextReply(ClientPtr client, + xGLXQueryContextReply *reply, int *buf); +extern void __glXSwapGetDrawableAttributesReply(ClientPtr client, + xGLXGetDrawableAttributesReply *reply, int *buf); +extern void __glXSwapQueryMaxSwapBarriersSGIXReply(ClientPtr client, + xGLXQueryMaxSwapBarriersSGIXReply *reply); + +/* + * Routines for computing the size of variably-sized rendering commands. + */ + +extern int __glXTypeSize(GLenum enm); +extern int __glXImageSize(GLenum format, GLenum type, GLsizei w, GLsizei h, + GLint rowLength, GLint skipRows, GLint alignment); +extern int __glXImage3DSize(GLenum format, GLenum type, + GLsizei w, GLsizei h, GLsizei d, + GLint imageHeight, GLint rowLength, + GLint skipImages, GLint skipRows, + GLint alignment); + +extern int __glXCallListsReqSize(GLbyte *pc, Bool swap); +extern int __glXBitmapReqSize(GLbyte *pc, Bool swap); +extern int __glXFogfvReqSize(GLbyte *pc, Bool swap); +extern int __glXFogivReqSize(GLbyte *pc, Bool swap); +extern int __glXLightfvReqSize(GLbyte *pc, Bool swap); +extern int __glXLightivReqSize(GLbyte *pc, Bool swap); +extern int __glXLightModelfvReqSize(GLbyte *pc, Bool swap); +extern int __glXLightModelivReqSize(GLbyte *pc, Bool swap); +extern int __glXMaterialfvReqSize(GLbyte *pc, Bool swap); +extern int __glXMaterialivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexParameterivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage1DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage2DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexEnvfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexEnvivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGendvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGenfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGenivReqSize(GLbyte *pc, Bool swap); +extern int __glXMap1dReqSize(GLbyte *pc, Bool swap); +extern int __glXMap1fReqSize(GLbyte *pc, Bool swap); +extern int __glXMap2dReqSize(GLbyte *pc, Bool swap); +extern int __glXMap2fReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapfvReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapuivReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapusvReqSize(GLbyte *pc, Bool swap); +extern int __glXDrawPixelsReqSize(GLbyte *pc, Bool swap); +extern int __glXDrawArraysSize(GLbyte *pc, Bool swap); +extern int __glXPrioritizeTexturesReqSize(GLbyte *pc, Bool swap); +extern int __glXTexSubImage1DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexSubImage2DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage3DReqSize(GLbyte *pc, Bool swap ); +extern int __glXTexSubImage3DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionFilter1DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionFilter2DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionParameterivReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXSeparableFilter2DReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableReqSize(GLbyte *pc, Bool swap); +extern int __glXColorSubTableReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableParameterivReqSize(GLbyte *pc, Bool swap); + +/* + * Routines for computing the size of returned data. + */ +extern int __glXConvolutionParameterivSize(GLenum pname); +extern int __glXConvolutionParameterfvSize(GLenum pname); +extern int __glXColorTableParameterfvSize(GLenum pname); +extern int __glXColorTableParameterivSize(GLenum pname); + +extern void __glXFreeGLXWindow(__glXWindow *pGlxWindow); +extern void __glXFreeGLXPbuffer(__glXPbuffer *pGlxPbuffer); + +extern int __glXVersionMajor; +extern int __glXVersionMinor; + +#define __GLX_IS_VERSION_SUPPORTED(major,minor) \ + ( (__glXVersionMajor > (major)) || \ + ((__glXVersionMajor == (major)) && (__glXVersionMinor >= (minor))) ) + +#endif /* !__GLX_server_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxsingle.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxsingle.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxsingle.h (revision 51223) @@ -0,0 +1,59 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef __GLXSINGLE_H +#define __GLXSINGLE_H + +extern int __glXForwardSingleReq( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReply( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReply( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardSingleReqSwap( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardPipe0WithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardAllWithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXDisp_ReadPixels(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_GetTexImage(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxswap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxswap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxswap.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifndef __GLX_swap_h__ +#define __GLX_swap_h__ + +extern int JoinSwapGroupSGIX(DrawablePtr pDraw, DrawablePtr pMember); +extern int SGSwapBuffers(__GLXclientState *cl, XID drawId, GLXContextTag tag, + DrawablePtr pDraw); + +extern void SwapBarrierInit(void); +extern void SwapBarrierReset(void); +extern int QueryMaxSwapBarriersSGIX(int screen); +extern int BindSwapBarrierSGIX(DrawablePtr pDraw, int barrier); + +#endif /* !__GLX_swap_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxutil.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxutil.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxutil.h (revision 51223) @@ -0,0 +1,54 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxutil.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef _glxcmds_h_ +#define _glxcmds_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXNop(void); + +/* memory management */ +extern void *__glXMalloc(size_t size); +extern void *__glXCalloc(size_t numElements, size_t elementSize); +extern void *__glXRealloc(void *addr, size_t newSize); +extern void __glXFree(void *ptr); + +/* context helper routines */ +extern __GLXcontext *__glXLookupContextByTag(__GLXclientState*, GLXContextTag); +extern DrawablePtr __glXLookupDrawableByTag(__GLXclientState *cl, GLXContextTag tag); + + +#endif /* _glxcmds_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvendor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvendor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvendor.h (revision 51223) @@ -0,0 +1,55 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef __GLXVENDOR_H +#define __GLXVENDOR_H + +extern int __glXVForwardSingleReq( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReply( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReply( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardSingleReqSwap( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardPipe0WithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardAllWithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvisuals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvisuals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glxvisuals.h (revision 51223) @@ -0,0 +1,55 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLX_VISUALS_H +#define _GLX_VISUALS_H + +int glxVisualsMatch( __GLXvisualConfig *v1, __GLXvisualConfig *v2 ); + +VisualID glxMatchGLXVisualInConfigList( __GLXvisualConfig *pGlxVisual, __GLXvisualConfig *configs, int nconfigs ); + +VisualID glxMatchVisualInConfigList( ScreenPtr pScreen, VisualPtr pVisual, __GLXvisualConfig *configs, int nconfigs ); + +VisualPtr glxMatchVisual( ScreenPtr pScreen, VisualPtr pVisual, ScreenPtr pMatchScreen ); + +void glxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, + void **privates); + +Bool glxInitVisuals(int *nvisualp, VisualPtr *visualp, + VisualID *defaultVisp, + int ndepth, DepthPtr pdepth, + int rootDepth); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glyphstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glyphstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/glyphstr.h (revision 51223) @@ -0,0 +1,148 @@ +/* + * $XFree86: xc/programs/Xserver/render/glyphstr.h,v 1.3 2000/11/20 07:13:13 keithp Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _GLYPHSTR_H_ +#define _GLYPHSTR_H_ + +#include +#include "picture.h" +#include "screenint.h" + +#define GlyphFormat1 0 +#define GlyphFormat4 1 +#define GlyphFormat8 2 +#define GlyphFormat16 3 +#define GlyphFormat32 4 +#define GlyphFormatNum 5 + +typedef struct _Glyph { + CARD32 refcnt; + CARD32 size; /* info + bitmap */ + xGlyphInfo info; + /* bits follow */ +} GlyphRec, *GlyphPtr; + +typedef struct _GlyphRef { + CARD32 signature; + GlyphPtr glyph; +} GlyphRefRec, *GlyphRefPtr; + +#define DeletedGlyph ((GlyphPtr) 1) + +typedef struct _GlyphHashSet { + CARD32 entries; + CARD32 size; + CARD32 rehash; +} GlyphHashSetRec, *GlyphHashSetPtr; + +typedef struct _GlyphHash { + GlyphRefPtr table; + GlyphHashSetPtr hashSet; + CARD32 tableEntries; +} GlyphHashRec, *GlyphHashPtr; + +typedef struct _GlyphSet { + CARD32 refcnt; + PictFormatPtr format; + int fdepth; + GlyphHashRec hash; + int maxPrivate; + pointer *devPrivates; +} GlyphSetRec, *GlyphSetPtr; + +#define GlyphSetGetPrivate(pGlyphSet,n) \ + ((n) > (pGlyphSet)->maxPrivate ? \ + (pointer) 0 : \ + (pGlyphSet)->devPrivates[n]) + +#define GlyphSetSetPrivate(pGlyphSet,n,ptr) \ + ((n) > (pGlyphSet)->maxPrivate ? \ + _GlyphSetSetNewPrivate(pGlyphSet, n, ptr) : \ + ((((pGlyphSet)->devPrivates[n] = (ptr)) != 0) || TRUE)) + +typedef struct _GlyphList { + INT16 xOff; + INT16 yOff; + CARD8 len; + PictFormatPtr format; +} GlyphListRec, *GlyphListPtr; + +extern GlyphHashRec globalGlyphs[GlyphFormatNum]; + +GlyphHashSetPtr +FindGlyphHashSet (CARD32 filled); + +int +AllocateGlyphSetPrivateIndex (void); + +void +ResetGlyphSetPrivateIndex (void); + +Bool +_GlyphSetSetNewPrivate (GlyphSetPtr glyphSet, int n, pointer ptr); + +Bool +GlyphInit (ScreenPtr pScreen); + +GlyphRefPtr +FindGlyphRef (GlyphHashPtr hash, CARD32 signature, Bool match, GlyphPtr compare); + +CARD32 +HashGlyph (GlyphPtr glyph); + +void +FreeGlyph (GlyphPtr glyph, int format); + +void +AddGlyph (GlyphSetPtr glyphSet, GlyphPtr glyph, Glyph id); + +Bool +DeleteGlyph (GlyphSetPtr glyphSet, Glyph id); + +GlyphPtr +FindGlyph (GlyphSetPtr glyphSet, Glyph id); + +GlyphPtr +AllocateGlyph (xGlyphInfo *gi, int format); + +Bool +AllocateGlyphHash (GlyphHashPtr hash, GlyphHashSetPtr hashSet); + +Bool +ResizeGlyphHash (GlyphHashPtr hash, CARD32 change, Bool global); + +Bool +ResizeGlyphSet (GlyphSetPtr glyphSet, CARD32 change); + +GlyphSetPtr +AllocateGlyphSet (int fdepth, PictFormatPtr format); + +int +FreeGlyphSet (pointer value, + XID gid); + + + +#endif /* _GLYPHSTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdev.h (revision 51223) @@ -0,0 +1,61 @@ +/* $XFree86: xc/programs/Xserver/Xi/grabdev.h,v 3.1 1996/04/15 11:18:51 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEV_H +#define GRABDEV_H 1 + +int +SProcXGrabDevice( + ClientPtr /* client */ + ); + +int +ProcXGrabDevice( + ClientPtr /* client */ + ); + +int +CreateMaskFromList ( + ClientPtr /* client */, + XEventClass * /* list */, + int /* count */, + struct tmask /* mask */[], + DeviceIntPtr /* dev */, + int /* req */ + ); + +void +SRepXGrabDevice ( + ClientPtr /* client */, + int /* size */, + xGrabDeviceReply * /* rep */ + ); + +#endif /* GRABDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevb.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/grabdevb.h,v 3.1 1996/04/15 11:18:52 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEVB_H +#define GRABDEVB_H 1 + +int +SProcXGrabDeviceButton( + ClientPtr /* client */ + ); + +int +ProcXGrabDeviceButton( + ClientPtr /* client */ + ); + +#endif /* GRABDEVB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevk.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevk.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/grabdevk.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/grabdevk.h,v 3.1 1996/04/15 11:18:53 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEVK_H +#define GRABDEVK_H 1 + +int +SProcXGrabDeviceKey( + ClientPtr /* client */ + ); + +int +ProcXGrabDeviceKey( + ClientPtr /* client */ + ); + +#endif /* GRABDEVK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gtmotion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gtmotion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/gtmotion.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/gtmotion.h,v 3.1 1996/04/15 11:18:56 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GTMOTION_H +#define GTMOTION_H 1 + +int +SProcXGetDeviceMotionEvents( + ClientPtr /* client */ + ); + +int +ProcXGetDeviceMotionEvents( + ClientPtr /* client */ + ); + +void +SRepXGetDeviceMotionEvents ( + ClientPtr /* client */, + int /* size */, + xGetDeviceMotionEventsReply * /* rep */ + ); + +#endif /* GTMOTION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/hash.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/hash.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/hash.h (revision 51223) @@ -0,0 +1,40 @@ +/* + * + * Copyright 1995-1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/hash.h,v 1.2.2.2 1998/07/04 13:32:45 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _HASH_H +#define _HASH_H + +#include "loader.h" + +typedef struct _HashIterator { + itemPtr pItem; + int bucket; +} HashIteratorRec, *HashIteratorPtr; + +#endif /* _HASH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/help.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/help.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/help.h (revision 51223) @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +/* help string definitions */ +#define HELP_DEVICES "helpDevices" /* Configure Layout */ +#define HELP_SCREEN "helpScreen" /* Configure Screen */ +#define HELP_MODELINE "helpModeline" /* Configure Modeline */ +#define HELP_ACCESSX "helpAccessX" /* Configure AccessX */ + +/* + * Prototypes + */ +void Help(char*); +void HelpCancelAction(Widget, XEvent*, String*, Cardinal*); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/i2c_def.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/i2c_def.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/i2c_def.h (revision 51223) @@ -0,0 +1,29 @@ +#ifndef __I2C_DEF_H__ +#define __I2C_DEF_H__ + +/* the following are a workaround for possible loader bug.. + WATCH function types ! */ +#if XFree86LOADER + +#define CreateI2CBusRec ((pointer (*)(void))LoaderSymbol("xf86CreateI2CBusRec")) +#define DestroyI2CBusRec ((pointer (*)(I2CBusPtr, Bool, Bool))LoaderSymbol("xf86DestroyI2CBusRec")) +#define I2CBusInit ((Bool (*)(pointer))LoaderSymbol("xf86I2CBusInit")) +#define I2C_WriteRead ((Bool (*)(I2CDevPtr, I2CByte *, int, I2CByte *, int))LoaderSymbol("xf86I2CWriteRead")) +#define CreateI2CDevRec ((pointer (*)(void))LoaderSymbol("xf86CreateI2CDevRec")) +#define I2CDevInit ((Bool (*)(I2CDevPtr))LoaderSymbol("xf86I2CDevInit")) +#define I2CProbeAddress ((Bool (*)(I2CBusPtr,I2CSlaveAddr))LoaderSymbol("xf86I2CProbeAddress")) + +#else + +#define CreateI2CBusRec xf86CreateI2CBusRec +#define DestroyI2CBusRec xf86DestroyI2CBusRec +#define I2CBusInit xf86I2CBusInit +#define I2C_WriteRead xf86I2CWriteRead +#define CreateI2CDevRec xf86CreateI2CDevRec +#define I2CDevInit xf86I2CDevInit +#define I2CProbeAddress xf86I2CProbeAddress + +#endif + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ia64Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ia64Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ia64Pci.h (revision 51223) @@ -0,0 +1,46 @@ +/* + * Copyright 2004, Egbert Eich + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * EGBERT EICH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CON- + * NECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Egbert Eich shall not + * be used in advertising or otherwise to promote the sale, use or other deal- + *ings in this Software without prior written authorization from Egbert Eich. + * + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _IA64_PCI_H +# define _IA64_PCI_H + +#include "Pci.h" + +typedef enum { + NONE_CHIPSET, + I460GX_CHIPSET, + E8870_CHIPSET, + ZX1_CHIPSET, + ALTIX_CHIPSET +} IA64Chipset; + +# ifdef OS_PROBE_PCI_CHIPSET +extern IA64Chipset OS_PROBE_PCI_CHIPSET(scanpciWrapperOpt flags); +# endif +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ibmTrace.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ibmTrace.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ibmTrace.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ibmTrace.h,v 1.1.2.1 1998/06/27 14:48:30 dawes Exp $ */ + + + + + +/* $XConsortium: ibmTrace.h /main/3 1996/02/21 17:56:27 kaleb $ */ + +#define TRACE(x) /* empty */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ilbm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ilbm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ilbm.h (revision 51223) @@ -0,0 +1,1051 @@ +/* $XFree86: xc/programs/Xserver/ilbm/ilbm.h,v 3.2 1998/04/05 16:42:23 robin Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.0, 1/17/89 */ +/*********************************************************** + +Copyright (c) 1987 X Consortium + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of the X Consortium shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the X Consortium. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XConsortium: ilbm.h,v 5.31 94/04/17 20:28:15 dpw Exp $ */ +/* Monochrome Frame Buffer definitions + written by drewry, september 1986 +*/ + +/* Modified jun 95 by Geert Uytterhoeven (Geert.Uytterhoeven@cs.kuleuven.ac.be) + to use interleaved bitplanes instead of normal bitplanes */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "mibstore.h" + +extern int ilbmInverseAlu[]; +extern int ilbmScreenPrivateIndex; +/* warning: PixelType definition duplicated in maskbits.h */ +#ifndef PixelType +#define PixelType unsigned long +#endif /* PixelType */ + +#define AFB_MAX_DEPTH 8 + +/* ilbmbitblt.c */ + +extern void ilbmDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr ilbmBitBlt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (*doBitBlt)(), + unsigned long /*planemask*/ +); + +extern RegionPtr ilbmCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern RegionPtr ilbmCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); + +extern void ilbmCopy1ToN( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbltC.c */ + +extern void ilbmDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbltCI.c */ + +extern void ilbmDoBitbltCopyInverted( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbltG.c */ + +extern void ilbmDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbltO.c */ + +extern void ilbmDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbltX.c */ + +extern void ilbmDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* ilbmbres.c */ + +extern void ilbmBresS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* ilbmbresd.c */ + +extern void ilbmBresD( + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/, + unsigned char * /*bgrrops*/ +); +/* ilbmbstore.c */ + +extern void ilbmSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void ilbmRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* ilbmclip.c */ + +extern RegionPtr ilbmPixmapToRegion( + PixmapPtr /*pPix*/ +); + +/* ilbmcmap.c */ + +extern Bool ilbmInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern void ilbmResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool ilbmSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +/* ilbmfillarc.c */ + +extern void ilbmPolyFillArcSolid( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* ilbmfillrct.c */ + +extern void ilbmPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); + +/* ilbmply1rct.c */ +extern void ilbmFillPolygonSolid( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*shape*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* ilbmfillsp.c */ + +extern void ilbmSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ilbmUnnaturalOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +/* ilbmfont.c */ + +extern Bool ilbmRealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +extern Bool ilbmUnrealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); +/* ilbmgc.c */ + +extern Bool ilbmCreateGC( + GCPtr /*pGC*/ +); + +extern void ilbmValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +extern void ilbmDestroyGC( + GCPtr /*pGC*/ +); + +extern void ilbmReduceRop( + int /*alu*/, + Pixel /*src*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void ilbmReduceOpaqueStipple ( + Pixel /*fg*/, + Pixel /*bg*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void ilbmComputeCompositeClip( + GCPtr /*pGC*/, + DrawablePtr /*pDrawable*/ +); + +/* ilbmgetsp.c */ + +extern void ilbmGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* ilbmhrzvert.c */ + +extern int ilbmHorzS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); + +extern int ilbmVertS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* ilbmigbblak.c */ + +extern void ilbmImageGlyphBlt ( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* ilbmigbwht.c */ + +/* ilbmimage.c */ + +extern void ilbmPutImage( + DrawablePtr /*dst*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void ilbmGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* ilbmline.c */ + +extern void ilbmLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void ilbmLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +/* ilbmmisc.c */ + +extern void ilbmQueryBestSize( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/ +); +/* ilbmpntarea.c */ + +extern void ilbmSolidFillArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + unsigned char * /*rrops*/ +); + +extern void ilbmStippleAreaPPW( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + unsigned char * /*rrops*/ +); +extern void ilbmStippleArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + int /*xOff*/, + int /*yOff*/, + unsigned char * /*rrops*/ +); +/* ilbmplygblt.c */ + +extern void ilbmPolyGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +/* ilbmpixmap.c */ + +extern PixmapPtr ilbmCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool ilbmDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr ilbmCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void ilbmPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void ilbmXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void ilbmYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void ilbmCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +extern void ilbmPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); +/* ilbmpolypnt.c */ + +extern void ilbmPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* ilbmpushpxl.c */ + +extern void ilbmPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* ilbmscrclse.c */ + +extern Bool ilbmCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); +/* ilbmscrinit.c */ + +extern Bool ilbmAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*pWinIndex*/, + int * /*pGCIndex*/ +); + +extern Bool ilbmScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr ilbmGetWindowPixmap( + WindowPtr /*pWin*/ +); + +extern void ilbmSetWindowPixmap( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/ +); + +/* ilbmseg.c */ + +extern void ilbmSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void ilbmSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* ilbmsetsp.c */ + +extern int ilbmSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + PixelType * /*psrc*/, + int /*alu*/, + PixelType * /*pdstBase*/, + int /*widthDst*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*sizeSrc*/ +); + +extern void ilbmSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* ilbmtegblt.c */ + +extern void ilbmTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* ilbmtileC.c */ + +extern void ilbmTileAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); +/* ilbmtileG.c */ + +extern void ilbmTileAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); + +extern void ilbmTileAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); +/* ilbmtileG.c */ + +extern void ilbmTileAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); + +extern void ilbmOpaqueStippleAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* ilbmtileG.c */ + +extern void ilbmOpaqueStippleAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +extern void ilbmOpaqueStippleAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* ilbmtileG.c */ + +extern void ilbmOpaqueStippleAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +/* ilbmwindow.c */ + +extern Bool ilbmCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool ilbmDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool ilbmMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool ilbmPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool ilbmUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void ilbmCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool ilbmChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* ilbmzerarc.c */ + +extern void ilbmZeroPolyArcSS( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* + private field of pixmap + pixmap.devPrivate = (PixelType *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes + + private field of screen + a pixmap, for which we allocate storage. devPrivate is a pointer to +the bits in the hardware framebuffer. note that devKind can be poked to +make the code work for framebuffers that are wider than their +displayable screen (e.g. the early vsII, which displayed 960 pixels +across, but was 1024 in the hardware.) + + private field of GC +*/ + +typedef struct { + unsigned char rrops[AFB_MAX_DEPTH]; /* reduction of rasterop to 1 of 3 */ + unsigned char rropOS[AFB_MAX_DEPTH]; /* rop for opaque stipple */ +} ilbmPrivGC; +typedef ilbmPrivGC *ilbmPrivGCPtr; + +extern int ilbmGCPrivateIndex; /* index into GC private array */ +extern int ilbmWindowPrivateIndex; /* index into Window private array */ +#ifdef PIXMAP_PER_WINDOW +extern int frameWindowPrivateIndex; /* index into Window private array */ +#endif + +#define ilbmGetGCPrivate(pGC) \ + ((ilbmPrivGC *)((pGC)->devPrivates[ilbmGCPrivateIndex].ptr)) + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border tile is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; +} ilbmPrivWin; + +/* Common macros for extracting drawing information */ + +#define ilbmGetPixelWidthAuxDepthAndPointer(pDrawable, width, aux, dep, pointer) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr)(pDrawable)->pScreen->devPrivates[ilbmScreenPrivateIndex].ptr; \ + else \ + _pPix = (PixmapPtr)(pDrawable); \ + (pointer) = (PixelType *)_pPix->devPrivate.ptr; \ + (width) = ((int)_pPix->devKind)/sizeof(PixelType); \ + (dep) = _pPix->drawable.depth; \ + (aux) = (width)*(dep); \ +} + +/* ilbm uses the following macros to calculate addresses in drawables. + * To support banked framebuffers, the macros come in four flavors. + * All four collapse into the same definition on unbanked devices. + * + * ilbmScanlineFoo - calculate address and do bank switching + * ilbmScanlineFooNoBankSwitch - calculate address, don't bank switch + * ilbmScanlineFooSrc - calculate address, switch source bank + * ilbmScanlineFooDst - calculate address, switch destination bank + */ + +/* The NoBankSwitch versions are the same for banked and unbanked cases */ + +#define ilbmScanlineIncNoBankSwitch(_ptr, _off) _ptr += (_off) +#define ilbmScanlineOffsetNoBankSwitch(_ptr, _off) ((_ptr)+(_off)) +#define ilbmScanlineDeltaNoBankSwitch(_ptr, _y, _w) \ + ilbmScanlineOffsetNoBankSwitch(_ptr, (_y)*(_w)) +#define ilbmScanlineNoBankSwitch(_ptr, _x, _y, _w) \ + ilbmScanlineOffsetNoBankSwitch(_ptr, (_y)*(_w)+((_x)>>MFB_PWSH)) + +#ifdef MFB_LINE_BANK + +#include "ilbmlinebank.h" /* get macro definitions from this file */ + +#else /* !MFB_LINE_BANK - unbanked case */ + +#define ilbmScanlineInc(_ptr, _off) ilbmScanlineIncNoBankSwitch(_ptr, _off) +#define ilbmScanlineIncSrc(_ptr, _off) ilbmScanlineInc(_ptr, _off) +#define ilbmScanlineIncDst(_ptr, _off) ilbmScanlineInc(_ptr, _off) + +#define ilbmScanlineOffset(_ptr, _off) ilbmScanlineOffsetNoBankSwitch(_ptr, _off) +#define ilbmScanlineOffsetSrc(_ptr, _off) ilbmScanlineOffset(_ptr, _off) +#define ilbmScanlineOffsetDst(_ptr, _off) ilbmScanlineOffset(_ptr, _off) + +#define ilbmScanlineSrc(_ptr, _x, _y, _w) ilbmScanline(_ptr, _x, _y, _w) +#define ilbmScanlineDst(_ptr, _x, _y, _w) ilbmScanline(_ptr, _x, _y, _w) + +#define ilbmScanlineDeltaSrc(_ptr, _y, _w) ilbmScanlineDelta(_ptr, _y, _w) +#define ilbmScanlineDeltaDst(_ptr, _y, _w) ilbmScanlineDelta(_ptr, _y, _w) + +#endif /* MFB_LINE_BANK */ + +#define ilbmScanlineDelta(_ptr, _y, _w) \ + ilbmScanlineOffset(_ptr, (_y)*(_w)) + +#define ilbmScanline(_ptr, _x, _y, _w) \ + ilbmScanlineOffset(_ptr, (_y)*(_w)+((_x)>>MFB_PWSH)) + +/* precomputed information about each glyph for GlyphBlt code. + this saves recalculating the per glyph information for each box. +*/ + +typedef struct _ilbmpos{ + int xpos; /* xposition of glyph's origin */ + int xchar; /* x position mod 32 */ + int leftEdge; + int rightEdge; + int topEdge; + int bottomEdge; + PixelType *pdstBase; /* longword with character origin */ + int widthGlyph; /* width in bytes of this glyph */ +} ilbmTEXTPOS; + +/* reduced raster ops for ilbm */ +#define RROP_BLACK GXclear +#define RROP_WHITE GXset +#define RROP_NOP GXnoop +#define RROP_INVERT GXinvert +#define RROP_COPY GXcopy + +/* macros for ilbmbitblt.c, ilbmfillsp.c + these let the code do one switch on the rop per call, rather + than a switch on the rop per item (span or rectangle.) +*/ + +#define fnCLEAR(src, dst) (0) +#define fnAND(src, dst) (src & dst) +#define fnANDREVERSE(src, dst) (src & ~dst) +#define fnCOPY(src, dst) (src) +#define fnANDINVERTED(src, dst) (~src & dst) +#define fnNOOP(src, dst) (dst) +#define fnXOR(src, dst) (src ^ dst) +#define fnOR(src, dst) (src | dst) +#define fnNOR(src, dst) (~(src | dst)) +#define fnEQUIV(src, dst) (~src ^ dst) +#define fnINVERT(src, dst) (~dst) +#define fnORREVERSE(src, dst) (src | ~dst) +#define fnCOPYINVERTED(src, dst) (~src) +#define fnORINVERTED(src, dst) (~src | dst) +#define fnNAND(src, dst) (~(src & dst)) +#define fnSET(src, dst) (~0) + +/* Using a "switch" statement is much faster in most cases + * since the compiler can do a look-up table or multi-way branch + * instruction, depending on the architecture. The result on + * A Sun 3/50 is at least 2.5 times faster, assuming a uniform + * distribution of RasterOp operation types. + * + * However, doing some profiling on a running system reveals + * GXcopy is the operation over 99.5% of the time and + * GXxor is the next most frequent (about .4%), so we make special + * checks for those first. + * + * Note that this requires a change to the "calling sequence" + * since we can't engineer a "switch" statement to have an lvalue. + */ +#define DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) \ + result = fnCOPY (src, dst); \ + else if (alu == GXxor) \ + result = fnXOR (src, dst); \ + else \ + switch (alu) { \ + case GXclear: \ + result = fnCLEAR (src, dst); \ + break; \ + case GXand: \ + result = fnAND (src, dst); \ + break; \ + case GXandReverse: \ + result = fnANDREVERSE (src, dst); \ + break; \ + case GXandInverted: \ + result = fnANDINVERTED (src, dst); \ + break; \ + case GXnoop: \ + result = fnNOOP (src, dst); \ + break; \ + case GXor: \ + result = fnOR (src, dst); \ + break; \ + case GXnor: \ + result = fnNOR (src, dst); \ + break; \ + case GXequiv: \ + result = fnEQUIV (src, dst); \ + break; \ + case GXinvert: \ + result = fnINVERT (src, dst); \ + break; \ + case GXorReverse: \ + result = fnORREVERSE (src, dst); \ + break; \ + case GXcopyInverted: \ + result = fnCOPYINVERTED (src, dst); \ + break; \ + case GXorInverted: \ + result = fnORINVERTED (src, dst); \ + break; \ + case GXnand: \ + result = fnNAND (src, dst); \ + break; \ + case GXset: \ + result = fnSET (src, dst); \ + break; \ + } \ +} + + +/* C expression fragments for various operations. These get passed in + * as -D's on the compile command line. See ilbm/Imakefile. This + * fixes XBUG 6319. + * + * This seems like a good place to point out that ilbm's use of the + * words black and white is an unfortunate misnomer. In ilbm code, black + * means zero, and white means one. + */ +#define MFB_OPEQ_WHITE |= +#define MFB_OPEQ_BLACK &=~ +#define MFB_OPEQ_INVERT ^= +#define MFB_EQWHOLEWORD_WHITE =~0 +#define MFB_EQWHOLEWORD_BLACK =0 +#define MFB_EQWHOLEWORD_INVERT ^=~0 +#define MFB_OP_WHITE /* nothing */ +#define MFB_OP_BLACK ~ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/impsize.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/impsize.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/impsize.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/impsize.h,v 1.4 2003/09/28 20:15:43 alanh Exp $ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _impsize_h_ +#define _impsize_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +/* +** These are defined in libsampleGL.a. They are not technically part of +** the defined interface between libdixGL.a and libsampleGL.a (that interface +** being the functions in the __glXScreenInfo structure, plus the OpenGL API +** itself), but we thought it was better to call these routines than to +** replicate the code in here. +*/ + +#include "indirect_size.h" + +extern int __glDrawPixels_size(GLenum format, GLenum type, GLsizei w,GLsizei h); + +#endif /* _impsize_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/input.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/input.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/input.h (revision 51223) @@ -0,0 +1,391 @@ +/* $Xorg: input.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/include/input.h,v 3.8 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef INPUT_H +#define INPUT_H + +#include "misc.h" +#include "screenint.h" +#include +#include +#include "window.h" /* for WindowPtr */ + +#define DEVICE_INIT 0 +#define DEVICE_ON 1 +#define DEVICE_OFF 2 +#define DEVICE_CLOSE 3 + +#define MAP_LENGTH 256 +#define DOWN_LENGTH 32 /* 256/8 => number of bytes to hold 256 bits */ +#define NullGrab ((GrabPtr)NULL) +#define PointerRootWin ((WindowPtr)PointerRoot) +#define NoneWin ((WindowPtr)None) +#define NullDevice ((DevicePtr)NULL) + +#ifndef FollowKeyboard +#define FollowKeyboard 3 +#endif +#ifndef FollowKeyboardWin +#define FollowKeyboardWin ((WindowPtr) FollowKeyboard) +#endif +#ifndef RevertToFollowKeyboard +#define RevertToFollowKeyboard 3 +#endif + +typedef unsigned long Leds; +typedef struct _OtherClients *OtherClientsPtr; +typedef struct _InputClients *InputClientsPtr; +typedef struct _DeviceIntRec *DeviceIntPtr; + +typedef int (*DeviceProc)( + DeviceIntPtr /*device*/, + int /*what*/); + +typedef void (*ProcessInputProc)( + xEventPtr /*events*/, + DeviceIntPtr /*device*/, + int /*count*/); + +typedef Bool (*DeviceHandleProc)( + DeviceIntPtr /*device*/, + void* /*data*/ + ); + +typedef void (*DeviceUnwrapProc)( + DeviceIntPtr /*device*/, + DeviceHandleProc /*proc*/, + void* /*data*/ + ); + +typedef struct _DeviceRec { + pointer devicePrivate; + ProcessInputProc processInputProc; /* current */ + ProcessInputProc realInputProc; /* deliver */ + ProcessInputProc enqueueInputProc; /* enqueue */ + Bool on; /* used by DDX to keep state */ +} DeviceRec, *DevicePtr; + +typedef struct { + int click, bell, bell_pitch, bell_duration; + Bool autoRepeat; + unsigned char autoRepeats[32]; + Leds leds; + unsigned char id; +} KeybdCtrl; + +typedef struct { + KeySym *map; + KeyCode minKeyCode, + maxKeyCode; + int mapWidth; +} KeySymsRec, *KeySymsPtr; + +typedef struct { + int num, den, threshold; + unsigned char id; +} PtrCtrl; + +typedef struct { + int resolution, min_value, max_value; + int integer_displayed; + unsigned char id; +} IntegerCtrl; + +typedef struct { + int max_symbols, num_symbols_supported; + int num_symbols_displayed; + KeySym *symbols_supported; + KeySym *symbols_displayed; + unsigned char id; +} StringCtrl; + +typedef struct { + int percent, pitch, duration; + unsigned char id; +} BellCtrl; + +typedef struct { + Leds led_values; + Mask led_mask; + unsigned char id; +} LedCtrl; + +extern int AllocateDevicePrivateIndex(void); +extern Bool AllocateDevicePrivate(DeviceIntPtr device, int index); +extern void ResetDevicePrivateIndex(void); + +extern KeybdCtrl defaultKeyboardControl; +extern PtrCtrl defaultPointerControl; + +#undef AddInputDevice +extern DevicePtr AddInputDevice( + DeviceProc /*deviceProc*/, + Bool /*autoStart*/); + +#define AddInputDevice(deviceProc, autoStart) \ + _AddInputDevice(deviceProc, autoStart) + +extern DeviceIntPtr _AddInputDevice( + DeviceProc /*deviceProc*/, + Bool /*autoStart*/); + +extern Bool EnableDevice( + DeviceIntPtr /*device*/); + +extern Bool DisableDevice( + DeviceIntPtr /*device*/); + +extern int InitAndStartDevices(void); + +extern void CloseDownDevices(void); + +extern void RemoveDevice( + DeviceIntPtr /*dev*/); + +extern int NumMotionEvents(void); + +#undef RegisterPointerDevice +extern void RegisterPointerDevice( + DevicePtr /*device*/); + +#define RegisterPointerDevice(device) \ + _RegisterPointerDevice(device) + +extern void _RegisterPointerDevice( + DeviceIntPtr /*device*/); + +#undef RegisterKeyboardDevice +extern void RegisterKeyboardDevice( + DevicePtr /*device*/); + +#define RegisterKeyboardDevice(device) \ + _RegisterKeyboardDevice(device) + +extern void _RegisterKeyboardDevice( + DeviceIntPtr /*device*/); + +extern DevicePtr LookupKeyboardDevice(void); + +extern DevicePtr LookupPointerDevice(void); + +extern DevicePtr LookupDevice( + int /* id */); + +extern void QueryMinMaxKeyCodes( + KeyCode* /*minCode*/, + KeyCode* /*maxCode*/); + +extern Bool SetKeySymsMap( + KeySymsPtr /*dst*/, + KeySymsPtr /*src*/); + +extern Bool InitKeyClassDeviceStruct( + DeviceIntPtr /*device*/, + KeySymsPtr /*pKeySyms*/, + CARD8 /*pModifiers*/[]); + +extern Bool InitButtonClassDeviceStruct( + DeviceIntPtr /*device*/, + int /*numButtons*/, + CARD8* /*map*/); + +typedef int (*ValuatorMotionProcPtr)( + DeviceIntPtr /*pdevice*/, + xTimecoord * /*coords*/, + unsigned long /*start*/, + unsigned long /*stop*/, + ScreenPtr /*pScreen*/); + +extern Bool InitValuatorClassDeviceStruct( + DeviceIntPtr /*device*/, + int /*numAxes*/, + ValuatorMotionProcPtr /* motionProc */, + int /*numMotionEvents*/, + int /*mode*/); + +extern Bool InitFocusClassDeviceStruct( + DeviceIntPtr /*device*/); + +typedef void (*BellProcPtr)( + int /*percent*/, + DeviceIntPtr /*device*/, + pointer /*ctrl*/, + int); + +typedef void (*KbdCtrlProcPtr)( + DeviceIntPtr /*device*/, + KeybdCtrl * /*ctrl*/); + +extern Bool InitKbdFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + BellProcPtr /*bellProc*/, + KbdCtrlProcPtr /*controlProc*/); + +typedef void (*PtrCtrlProcPtr)( + DeviceIntPtr /*device*/, + PtrCtrl * /*ctrl*/); + +extern Bool InitPtrFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + PtrCtrlProcPtr /*controlProc*/); + +typedef void (*StringCtrlProcPtr)( + DeviceIntPtr /*device*/, + StringCtrl * /*ctrl*/); + +extern Bool InitStringFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + StringCtrlProcPtr /*controlProc*/, + int /*max_symbols*/, + int /*num_symbols_supported*/, + KeySym* /*symbols*/); + +typedef void (*BellCtrlProcPtr)( + DeviceIntPtr /*device*/, + BellCtrl * /*ctrl*/); + +extern Bool InitBellFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + BellProcPtr /*bellProc*/, + BellCtrlProcPtr /*controlProc*/); + +typedef void (*LedCtrlProcPtr)( + DeviceIntPtr /*device*/, + LedCtrl * /*ctrl*/); + +extern Bool InitLedFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + LedCtrlProcPtr /*controlProc*/); + +typedef void (*IntegerCtrlProcPtr)( + DeviceIntPtr /*device*/, + IntegerCtrl * /*ctrl*/); + + +extern Bool InitIntegerFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + IntegerCtrlProcPtr /*controlProc*/); + +extern Bool InitPointerDeviceStruct( + DevicePtr /*device*/, + CARD8* /*map*/, + int /*numButtons*/, + ValuatorMotionProcPtr /*motionProc*/, + PtrCtrlProcPtr /*controlProc*/, + int /*numMotionEvents*/); + +extern Bool InitKeyboardDeviceStruct( + DevicePtr /*device*/, + KeySymsPtr /*pKeySyms*/, + CARD8 /*pModifiers*/[], + BellProcPtr /*bellProc*/, + KbdCtrlProcPtr /*controlProc*/); + +extern void SendMappingNotify( + unsigned int /*request*/, + unsigned int /*firstKeyCode*/, + unsigned int /*count*/, + ClientPtr /* client */); + +extern Bool BadDeviceMap( + BYTE* /*buff*/, + int /*length*/, + unsigned /*low*/, + unsigned /*high*/, + XID* /*errval*/); + +extern Bool AllModifierKeysAreUp( + DeviceIntPtr /*device*/, + CARD8* /*map1*/, + int /*per1*/, + CARD8* /*map2*/, + int /*per2*/); + +extern void NoteLedState( + DeviceIntPtr /*keybd*/, + int /*led*/, + Bool /*on*/); + +extern void MaybeStopHint( + DeviceIntPtr /*device*/, + ClientPtr /*client*/); + +extern void ProcessPointerEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*mouse*/, + int /*count*/); + +extern void ProcessKeyboardEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*keybd*/, + int /*count*/); + +#ifdef XKB +extern void CoreProcessPointerEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*mouse*/, + int /*count*/); + +extern void CoreProcessKeyboardEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*keybd*/, + int /*count*/); +#endif + +extern Bool LegalModifier( + unsigned int /*key*/, + DevicePtr /*pDev*/); + +extern void ProcessInputEvents(void); + +extern void InitInput( + int /*argc*/, + char ** /*argv*/); + +#endif /* INPUT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/inputstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/inputstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/inputstr.h (revision 51223) @@ -0,0 +1,314 @@ +/* $XFree86: xc/programs/Xserver/include/inputstr.h,v 1.6 2003/04/27 21:31:04 herrb Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ + +/* $Xorg: inputstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef INPUTSTRUCT_H +#define INPUTSTRUCT_H + +#include "input.h" +#include "window.h" +#include "dixstruct.h" + +#define BitIsOn(ptr, bit) (((BYTE *) (ptr))[(bit)>>3] & (1 << ((bit) & 7))) + +#define SameClient(obj,client) \ + (CLIENT_BITS((obj)->resource) == (client)->clientAsMask) + +#define MAX_DEVICES 20 + +#define EMASKSIZE MAX_DEVICES + +/* Kludge: OtherClients and InputClients must be compatible, see code */ + +typedef struct _OtherClients { + OtherClientsPtr next; + XID resource; /* id for putting into resource manager */ + Mask mask; +} OtherClients; + +typedef struct _InputClients { + InputClientsPtr next; + XID resource; /* id for putting into resource manager */ + Mask mask[EMASKSIZE]; +} InputClients; + +typedef struct _OtherInputMasks { + Mask deliverableEvents[EMASKSIZE]; + Mask inputEvents[EMASKSIZE]; + Mask dontPropagateMask[EMASKSIZE]; + InputClientsPtr inputClients; +} OtherInputMasks; + +/* + * The following structure gets used for both active and passive grabs. For + * active grabs some of the fields (e.g. modifiers) are not used. However, + * that is not much waste since there aren't many active grabs (one per + * keyboard/pointer device) going at once in the server. + */ + +#define MasksPerDetailMask 8 /* 256 keycodes and 256 possible + modifier combinations, but only + 3 buttons. */ + + typedef struct _DetailRec { /* Grab details may be bit masks */ + unsigned short exact; + Mask *pMask; + } DetailRec; + + typedef struct _GrabRec { + GrabPtr next; /* for chain of passive grabs */ + XID resource; + DeviceIntPtr device; + WindowPtr window; + unsigned ownerEvents:1; + unsigned keyboardMode:1; + unsigned pointerMode:1; + unsigned coreGrab:1; /* grab is on core device */ + unsigned coreMods:1; /* modifiers are on core keyboard */ + CARD8 type; /* event type */ + DetailRec modifiersDetail; + DeviceIntPtr modifierDevice; + DetailRec detail; /* key or button */ + WindowPtr confineTo; /* always NULL for keyboards */ + CursorPtr cursor; /* always NULL for keyboards */ + Mask eventMask; +} GrabRec; + +typedef struct _KeyClassRec { + CARD8 down[DOWN_LENGTH]; + KeyCode *modifierKeyMap; + KeySymsRec curKeySyms; + int modifierKeyCount[8]; + CARD8 modifierMap[MAP_LENGTH]; + CARD8 maxKeysPerModifier; + unsigned short state; + unsigned short prev_state; +#ifdef XKB + struct _XkbSrvInfo *xkbInfo; +#endif +} KeyClassRec, *KeyClassPtr; + +typedef struct _AxisInfo { + int resolution; + int min_resolution; + int max_resolution; + int min_value; + int max_value; +} AxisInfo, *AxisInfoPtr; + +typedef struct _ValuatorClassRec { + ValuatorMotionProcPtr GetMotionProc; + int numMotionEvents; + WindowPtr motionHintWindow; + AxisInfoPtr axes; + unsigned short numAxes; + int *axisVal; + CARD8 mode; +} ValuatorClassRec, *ValuatorClassPtr; + +typedef struct _ButtonClassRec { + CARD8 numButtons; + CARD8 buttonsDown; /* number of buttons currently down */ + unsigned short state; + Mask motionMask; + CARD8 down[DOWN_LENGTH]; + CARD8 map[MAP_LENGTH]; +#ifdef XKB + union _XkbAction * xkb_acts; +#endif +} ButtonClassRec, *ButtonClassPtr; + +typedef struct _FocusClassRec { + WindowPtr win; + int revert; + TimeStamp time; + WindowPtr *trace; + int traceSize; + int traceGood; +} FocusClassRec, *FocusClassPtr; + +typedef struct _ProximityClassRec { + char pad; +} ProximityClassRec, *ProximityClassPtr; + +typedef struct _KbdFeedbackClassRec *KbdFeedbackPtr; +typedef struct _PtrFeedbackClassRec *PtrFeedbackPtr; +typedef struct _IntegerFeedbackClassRec *IntegerFeedbackPtr; +typedef struct _StringFeedbackClassRec *StringFeedbackPtr; +typedef struct _BellFeedbackClassRec *BellFeedbackPtr; +typedef struct _LedFeedbackClassRec *LedFeedbackPtr; + +typedef struct _KbdFeedbackClassRec { + BellProcPtr BellProc; + KbdCtrlProcPtr CtrlProc; + KeybdCtrl ctrl; + KbdFeedbackPtr next; +#ifdef XKB + struct _XkbSrvLedInfo *xkb_sli; +#endif +} KbdFeedbackClassRec; + +typedef struct _PtrFeedbackClassRec { + PtrCtrlProcPtr CtrlProc; + PtrCtrl ctrl; + PtrFeedbackPtr next; +} PtrFeedbackClassRec; + +typedef struct _IntegerFeedbackClassRec { + IntegerCtrlProcPtr CtrlProc; + IntegerCtrl ctrl; + IntegerFeedbackPtr next; +} IntegerFeedbackClassRec; + +typedef struct _StringFeedbackClassRec { + StringCtrlProcPtr CtrlProc; + StringCtrl ctrl; + StringFeedbackPtr next; +} StringFeedbackClassRec; + +typedef struct _BellFeedbackClassRec { + BellProcPtr BellProc; + BellCtrlProcPtr CtrlProc; + BellCtrl ctrl; + BellFeedbackPtr next; +} BellFeedbackClassRec; + +typedef struct _LedFeedbackClassRec { + LedCtrlProcPtr CtrlProc; + LedCtrl ctrl; + LedFeedbackPtr next; +#ifdef XKB + struct _XkbSrvLedInfo *xkb_sli; +#endif +} LedFeedbackClassRec; + +/* states for devices */ + +#define NOT_GRABBED 0 +#define THAWED 1 +#define THAWED_BOTH 2 /* not a real state */ +#define FREEZE_NEXT_EVENT 3 +#define FREEZE_BOTH_NEXT_EVENT 4 +#define FROZEN 5 /* any state >= has device frozen */ +#define FROZEN_NO_EVENT 5 +#define FROZEN_WITH_EVENT 6 +#define THAW_OTHERS 7 + +typedef struct _DeviceIntRec { + DeviceRec public; + DeviceIntPtr next; + TimeStamp grabTime; + Bool startup; /* true if needs to be turned on at + server intialization time */ + DeviceProc deviceProc; /* proc(DevicePtr, DEVICE_xx). It is + used to initialize, turn on, or + turn off the device */ + Bool inited; /* TRUE if INIT returns Success */ + GrabPtr grab; /* the grabber - used by DIX */ + struct { + Bool frozen; + int state; + GrabPtr other; /* if other grab has this frozen */ + xEvent *event; /* saved to be replayed */ + int evcount; + } sync; + Atom type; + char *name; + CARD8 id; + CARD8 activatingKey; + Bool fromPassiveGrab; + GrabRec activeGrab; + void (*ActivateGrab) ( + DeviceIntPtr /*device*/, + GrabPtr /*grab*/, + TimeStamp /*time*/, + Bool /*autoGrab*/); + void (*DeactivateGrab)( + DeviceIntPtr /*device*/); + KeyClassPtr key; + ValuatorClassPtr valuator; + ButtonClassPtr button; + FocusClassPtr focus; + ProximityClassPtr proximity; + KbdFeedbackPtr kbdfeed; + PtrFeedbackPtr ptrfeed; + IntegerFeedbackPtr intfeed; + StringFeedbackPtr stringfeed; + BellFeedbackPtr bell; + LedFeedbackPtr leds; +#ifdef XKB + struct _XkbInterest * xkb_interest; +#endif + DevUnion *devPrivates; + int nPrivates; + DeviceUnwrapProc unwrapProc; +} DeviceIntRec; + +typedef struct { + int numDevices; /* total number of devices */ + DeviceIntPtr devices; /* all devices turned on */ + DeviceIntPtr off_devices; /* all devices turned off */ + DeviceIntPtr keyboard; /* the main one for the server */ + DeviceIntPtr pointer; +} InputInfo; + +extern InputInfo inputInfo; + +/* for keeping the events for devices grabbed synchronously */ +typedef struct _QdEvent *QdEventPtr; +typedef struct _QdEvent { + QdEventPtr next; + DeviceIntPtr device; + ScreenPtr pScreen; /* what screen the pointer was on */ + unsigned long months; /* milliseconds is in the event */ + xEvent *event; + int evcount; +} QdEventRec; + +#endif /* INPUTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/int10Defines.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/int10Defines.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/int10Defines.h (revision 51223) @@ -0,0 +1,90 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/int10Defines.h,v 1.4 2003/08/24 17:37:03 dawes Exp $ */ +/* + * Copyright (c) 2000-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _INT10DEFINES_H_ +#define _INT10DEFINES_H_ 1 + +#ifdef _VM86_LINUX + +#include + +#define CPU_R(type,name,num) \ + (((type *)&(((struct vm86_struct *)REG->cpuRegs)->regs.name))[num]) +#define CPU_RD(name,num) CPU_R(CARD32,name,num) +#define CPU_RW(name,num) CPU_R(CARD16,name,num) +#define CPU_RB(name,num) CPU_R(CARD8,name,num) + +#define X86_EAX CPU_RD(eax,0) +#define X86_EBX CPU_RD(ebx,0) +#define X86_ECX CPU_RD(ecx,0) +#define X86_EDX CPU_RD(edx,0) +#define X86_ESI CPU_RD(esi,0) +#define X86_EDI CPU_RD(edi,0) +#define X86_EBP CPU_RD(ebp,0) +#define X86_EIP CPU_RD(eip,0) +#define X86_ESP CPU_RD(esp,0) +#define X86_EFLAGS CPU_RD(eflags,0) + +#define X86_FLAGS CPU_RW(eflags,0) +#define X86_AX CPU_RW(eax,0) +#define X86_BX CPU_RW(ebx,0) +#define X86_CX CPU_RW(ecx,0) +#define X86_DX CPU_RW(edx,0) +#define X86_SI CPU_RW(esi,0) +#define X86_DI CPU_RW(edi,0) +#define X86_BP CPU_RW(ebp,0) +#define X86_IP CPU_RW(eip,0) +#define X86_SP CPU_RW(esp,0) +#define X86_CS CPU_RW(cs,0) +#define X86_DS CPU_RW(ds,0) +#define X86_ES CPU_RW(es,0) +#define X86_SS CPU_RW(ss,0) +#define X86_FS CPU_RW(fs,0) +#define X86_GS CPU_RW(gs,0) + +#define X86_AL CPU_RB(eax,0) +#define X86_BL CPU_RB(ebx,0) +#define X86_CL CPU_RB(ecx,0) +#define X86_DL CPU_RB(edx,0) + +#define X86_AH CPU_RB(eax,1) +#define X86_BH CPU_RB(ebx,1) +#define X86_CH CPU_RB(ecx,1) +#define X86_DH CPU_RB(edx,1) + +#elif defined(_X86EMU) + +#include "xf86x86emu.h" + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ipl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ipl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ipl.h (revision 51223) @@ -0,0 +1,1254 @@ +/* $XFree86: xc/programs/Xserver/iplan2p4/ipl.h,v 3.5 2001/01/30 22:06:21 tsi Exp $ */ +/* $XConsortium: ipl.h,v 5.37 94/04/17 20:28:38 dpw Exp $ */ +/************************************************************ +Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright no- +tice appear in all copies and that both that copyright no- +tice and this permission notice appear in supporting docu- +mentation, and that the names of Sun or X Consortium +not be used in advertising or publicity pertaining to +distribution of the software without specific prior +written permission. Sun and X Consortium make no +representations about the suitability of this software for +any purpose. It is provided "as is" without any express or +implied warranty. + +SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- +NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI- +ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/* Modified nov 94 by Martin Schaller (Martin_Schaller@maus.r.de) for use with +interleaved planes */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "servermd.h" +#include "windowstr.h" +#include "mfb.h" +#undef PixelType + +#include "iplmap.h" + +/* + private filed of pixmap + pixmap.devPrivate = (unsigned int *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes +*/ + +extern int iplGCPrivateIndex; +extern int iplWindowPrivateIndex; + +/* private field of GC */ +typedef struct { + unsigned char rop; /* special case rop values */ + /* next two values unused in ipl, included for compatibility with mfb */ + unsigned char ropOpStip; /* rop for opaque stipple */ + /* this value is ropFillArea in mfb, usurped for ipl */ + unsigned char oneRect; /* drawable has one clip rect */ + unsigned long xor, and; /* reduced rop values */ + unsigned short xorg[INTER_PLANES],andg[INTER_PLANES]; + } iplPrivGC; + +typedef iplPrivGC *iplPrivGCPtr; + +#define iplGetGCPrivate(pGC) ((iplPrivGCPtr)\ + (pGC)->devPrivates[iplGCPrivateIndex].ptr) + +#define iplGetCompositeClip(pGC) ((pGC)->pCompositeClip) + +/* way to carry RROP info around */ +typedef struct { + unsigned char rop; + unsigned long xor, and; + unsigned short xorg[INTER_PLANES],andg[INTER_PLANES]; +} iplRRopRec, *iplRRopPtr; + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; + } iplPrivWin; + +#define iplGetWindowPrivate(_pWin) ((iplPrivWin *)\ + (_pWin)->devPrivates[iplWindowPrivateIndex].ptr) + + +/* ipl8bit.c */ + +extern int iplSetStipple( + int /*alu*/, + unsigned long /*fg*/, + unsigned long /*planemask*/ +); + +extern int iplSetOpaqueStipple( + int /*alu*/, + unsigned long /*fg*/, + unsigned long /*bg*/, + unsigned long /*planemask*/ +); + +extern int iplComputeClipMasks32( + BoxPtr /*pBox*/, + int /*numRects*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + CARD32 * /*clips*/ +); +/* ipl8cppl.c */ + +extern void iplCopyImagePlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern void iplCopyPlane8to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); +/* ipl8lineCO.c */ + +extern int ipl8LineSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void ipl8LineSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void ipl8ClippedLineCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* ipl8lineCP.c */ + +extern int ipl8LineSS1RectPreviousCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); +/* ipl8lineG.c */ + +extern int ipl8LineSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void ipl8ClippedLineGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* ipl8lineX.c */ + +extern int ipl8LineSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void ipl8ClippedLineXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* ipl8segC.c */ + +extern int ipl8SegmentSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* ipl8segCS.c */ + +extern int ipl8SegmentSS1RectShiftCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); + +extern void ipl8SegmentSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* ipl8segG.c */ + +extern int ipl8SegmentSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* iplsegX.c */ + +extern int ipl8SegmentSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* iplallpriv.c */ + +extern Bool iplAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*window_index*/, + int * /*gc_index*/ +); +/* iplbitblt.c */ + +extern RegionPtr iplBitBlt( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (* /*doBitBlt*/)(), + unsigned long /*bitPlane*/ +); + +extern void iplDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr iplCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern void iplCopyPlane1to8( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern RegionPtr iplCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/ +); +/* iplbltC.c */ + +extern void iplDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* iplbltG.c */ + +extern void iplDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* iplbltO.c */ + +extern void iplDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* iplbltX.c */ + +extern void iplDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* iplbres.c */ + +extern void iplBresS( + int /*rop*/, + unsigned short * /*and*/, + unsigned short * /*xor*/, + unsigned short * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* iplbresd.c */ + +extern void iplBresD( + iplRRopPtr /*rrops*/, + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + unsigned short * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* iplbstore.c */ + +extern void iplSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void iplRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* iplcmap.c */ + +extern int iplListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void iplInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void iplUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void iplResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool iplInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern int iplExpandDirectColors( + ColormapPtr /*pmap*/, + int /*ndef*/, + xColorItem * /*indefs*/, + xColorItem * /*outdefs*/ +); + +extern Bool iplCreateDefColormap( + ScreenPtr /*pScreen*/ +); + +extern Bool iplSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +extern Bool iplInitVisuals( + VisualPtr * /*visualp*/, + DepthPtr * /*depthp*/, + int * /*nvisualp*/, + int * /*ndepthp*/, + int * /*rootDepthp*/, + VisualID * /*defaultVisp*/, + unsigned long /*sizes*/, + int /*bitsPerRGB*/ +); +/* iplfillarcC.c */ + +extern void iplPolyFillArcSolidCopy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* iplfillarcG.c */ + +extern void iplPolyFillArcSolidGeneral( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* iplfillrct.c */ + +extern void iplFillBoxTileOdd( + DrawablePtr /*pDrawable*/, + int /*n*/, + BoxPtr /*rects*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/ +); + +extern void iplFillRectTileOdd( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); +/* iplfillsp.c */ + +extern void iplUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void iplUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ipl8Stipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void ipl8OpaqueStipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* iplgc.c */ + +extern GCOpsPtr iplMatchCommon( + GCPtr /*pGC*/, + iplPrivGCPtr /*devPriv*/ +); + +extern Bool iplCreateGC( + GCPtr /*pGC*/ +); + +extern void iplValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +/* iplgetsp.c */ + +extern void iplGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* iplglblt8.c */ + +extern void iplPolyGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* iplglrop8.c */ + +extern void iplPolyGlyphRop8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* iplhrzvert.c */ + +extern int iplHorzS( + int /*rop*/, + unsigned short * /*and*/, + unsigned short * /*xor*/, + unsigned short * /*addrg*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); + +extern int iplVertS( + int /*rop*/, + unsigned short * /*and*/, + unsigned short * /*xor*/, + unsigned short * /*addrg*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); +/* ipligblt8.c */ + +extern void iplImageGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* iplimage.c */ + +extern void iplPutImage( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void iplGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* iplline.c */ + +extern void iplLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void iplLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); +/* iplmskbits.c */ +/* iplpixmap.c */ + +extern PixmapPtr iplCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool iplDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr iplCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void iplPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void iplXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void iplYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void iplCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +/* iplply1rctC.c */ + +extern void iplFillPoly1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* iplply1rctG.c */ + +extern void iplFillPoly1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* iplpntwin.c */ + +extern void iplPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); + +extern void iplFillBoxSolid( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + unsigned long /*pixel*/ +); + +extern void iplFillBoxTile32( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/ +); +/* iplpolypnt.c */ + +extern void iplPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* iplpush8.c */ + +extern void iplPushPixels8( + GCPtr /*pGC*/, + PixmapPtr /*pBitmap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* iplrctstp8.c */ + +extern void ipl8FillRectOpaqueStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void ipl8FillRectTransparentStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void ipl8FillRectStippledUnnatural( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); +/* iplrrop.c */ + +extern int iplReduceRasterOp( + int /*rop*/, + unsigned long /*fg*/, + unsigned long /*pm*/, + unsigned short * /*andp*/, + unsigned short * /*xorp*/ +); +/* iplscrinit.c */ + +extern Bool iplCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); + +extern Bool iplSetupScreen( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern int iplFinishScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern Bool iplScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr iplGetScreenPixmap( + ScreenPtr /*pScreen*/ +); + +extern void iplSetScreenPixmap( + PixmapPtr /*pPix*/ +); + +/* iplseg.c */ + +extern void iplSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void iplSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* iplsetsp.c */ + +extern int iplSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + unsigned int * /*psrc*/, + int /*alu*/, + unsigned short * /*pdstBase*/, + int /*widthDst*/, + unsigned long /*planemask*/ +); + +extern void iplSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* iplsolidC.c */ + +extern void iplFillRectSolidCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplSolidSpansCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* iplsolidG.c */ + +extern void iplFillRectSolidGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplSolidSpansGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* iplsolidX.c */ + +extern void iplFillRectSolidXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplSolidSpansXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* iplteblt8.c */ + +extern void iplTEGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*xInit*/, + int /*yInit*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* ipltegblt.c */ + +extern void iplTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* ipltile32C.c */ + +extern void iplFillRectTile32Copy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplTile32FSCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* ipltile32G.c */ + +extern void iplFillRectTile32General( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void iplTile32FSGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* ipltileoddC.c */ + +extern void iplFillBoxTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillSpanTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillBoxTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillSpanTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* ipltileoddG.c */ + +extern void iplFillBoxTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillSpanTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillBoxTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void iplFillSpanTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* iplwindow.c */ + +extern Bool iplCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool iplDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool iplMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool iplPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool iplUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void iplCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool iplChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* iplzerarcC.c */ + +extern void iplZeroPolyArcSS8Copy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* iplzerarcG.c */ + +extern void iplZeroPolyArcSS8General( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* iplzerarcX.c */ + +extern void iplZeroPolyArcSS8Xor( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* Common macros for extracting drawing information */ + +#if (!defined(SINGLEDEPTH) && PSZ != 8) || defined(FORCE_SEPARATE_PRIVATE) + +#define CFB_NEED_SCREEN_PRIVATE + +extern int iplScreenPrivateIndex; +#endif + +#define iplGetWindowPixmap(d) \ + ((* ((DrawablePtr)(d))->pScreen->GetWindowPixmap)((WindowPtr)(d))) + +#define iplGetTypedWidth(pDrawable,wtype) (\ + (((pDrawable)->type != DRAWABLE_PIXMAP) ? \ + (int) (iplGetWindowPixmap(pDrawable)->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define iplGetByteWidth(pDrawable) iplGetTypedWidth(pDrawable, unsigned char) + +#define iplGetPixelWidth(pDrawable) iplGetTypedWidth(pDrawable, PixelType) + +#define iplGetLongWidth(pDrawable) iplGetTypedWidth(pDrawable, unsigned long) + +#define iplGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) \ + _pPix = iplGetWindowPixmap(pDrawable); \ + else \ + _pPix = (PixmapPtr) (pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define iplGetByteWidthAndPointer(pDrawable, width, pointer) \ + iplGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define iplGetLongWidthAndPointer(pDrawable, width, pointer) \ + iplGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned long, unsigned long) + +#define iplGetPixelWidthAndPointer(pDrawable, width, pointer) \ + iplGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define iplGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = iplGetWindowPixmap((DrawablePtr) (pWin)); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define iplGetWindowLongWidthAndPointer(pWin, width, pointer) \ + iplGetWindowTypedWidthAndPointer(pWin, width, pointer, unsigned long, unsigned long) + +#define iplGetWindowByteWidthAndPointer(pWin, width, pointer) \ + iplGetWindowTypedWidthAndPointer(pWin, width, pointer, unsigned char, unsigned char) + +#define iplGetWindowPixelWidthAndPointer(pDrawable, width, pointer) \ + iplGetWindowTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +/* Macros which handle a coordinate in a single register */ + +/* Most compilers will convert divide by 65536 into a shift, if signed + * shifts exist. If your machine does arithmetic shifts and your compiler + * can't get it right, add to this line. + */ + +/* mips compiler - what a joke - it CSEs the 65536 constant into a reg + * forcing as to use div instead of shift. Let's be explicit. + */ + +#if defined(mips) || defined(sparc) || defined(__alpha) || defined(__alpha__) +#define GetHighWord(x) (((int) (x)) >> 16) +#else +#define GetHighWord(x) (((int) (x)) / 65536) +#endif + +#if IMAGE_BYTE_ORDER == MSBFirst +#define intToCoord(i,x,y) (((x) = GetHighWord(i)), ((y) = (int) ((short) (i)))) +#define coordToInt(x,y) (((x) << 16) | (y)) +#define intToX(i) (GetHighWord(i)) +#define intToY(i) ((int) ((short) i)) +#else +#define intToCoord(i,x,y) (((x) = (int) ((short) (i))), ((y) = GetHighWord(i))) +#define coordToInt(x,y) (((y) << 16) | (x)) +#define intToX(i) ((int) ((short) (i))) +#define intToY(i) (GetHighWord(i)) +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmap.h (revision 51223) @@ -0,0 +1,176 @@ +/* $XFree86: xc/programs/Xserver/iplan2p4/iplmap.h,v 3.1 1998/04/05 16:42:26 robin Exp $ */ +/* + * $XConsortium: iplmap.h,v 1.9 94/04/17 20:28:54 dpw Exp $ + * +Copyright (c) 1991 X Consortium + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of the X Consortium shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the X Consortium. + * + * Author: Keith Packard, MIT X Consortium + */ + +/* Modified nov 94 by Martin Schaller (Martin_Schaller@maus.r.de) for use with +interleaved planes */ + +/* + * Map names around so that multiple depths can be supported simultaneously + */ + +/* a losing vendor cpp dumps core if we define NAME in terms of CATNAME */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#if INTER_PLANES == 2 +#define NAME(subname) ipl2p2##subname +#elif INTER_PLANES == 4 +#define NAME(subname) ipl2p4##subname +#elif INTER_PLANES == 8 +#define NAME(subname) ipl2p8##subname +#endif + + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CATNAME(prefix,subname) prefix##subname +#else +#define CATNAME(prefix,subname) prefix/**/subname +#endif + +#define iplScreenPrivateIndex NAME(ScreenPrivateIndex) +#define QuartetBitsTable NAME(QuartetBitsTable) +#define QuartetPixelMaskTable NAME(QuartetPixelMaskTable) +#define iplAllocatePrivates NAME(AllocatePrivates) +#define iplBSFuncRec NAME(BSFuncRec) +#define iplBitBlt NAME(BitBlt) +#define iplBresD NAME(BresD) +#define iplBresS NAME(BresS) +#define iplChangeWindowAttributes NAME(ChangeWindowAttributes) +#define iplCloseScreen NAME(CloseScreen) +#define iplCopyArea NAME(CopyArea) +#define iplCopyImagePlane NAME(CopyImagePlane) +#define iplCopyPixmap NAME(CopyPixmap) +#define iplCopyPlane NAME(CopyPlane) +#define iplCopyRotatePixmap NAME(CopyRotatePixmap) +#define iplCopyWindow NAME(CopyWindow) +#define iplCreateGC NAME(CreateGC) +#define iplCreatePixmap NAME(CreatePixmap) +#define iplCreateWindow NAME(CreateWindow) +#define iplCreateScreenResources NAME(CreateScreenResoures) +#define iplDestroyPixmap NAME(DestroyPixmap) +#define iplDestroyWindow NAME(DestroyWindow) +#define iplDoBitblt NAME(DoBitblt) +#define iplDoBitbltCopy NAME(DoBitbltCopy) +#define iplDoBitbltGeneral NAME(DoBitbltGeneral) +#define iplDoBitbltOr NAME(DoBitbltOr) +#define iplDoBitbltXor NAME(DoBitbltXor) +#define iplFillBoxSolid NAME(FillBoxSolid) +#define iplFillBoxTile32 NAME(FillBoxTile32) +#define iplFillBoxTile32sCopy NAME(FillBoxTile32sCopy) +#define iplFillBoxTile32sGeneral NAME(FillBoxTile32sGeneral) +#define iplFillBoxTileOdd NAME(FillBoxTileOdd) +#define iplFillBoxTileOddCopy NAME(FillBoxTileOddCopy) +#define iplFillBoxTileOddGeneral NAME(FillBoxTileOddGeneral) +#define iplFillPoly1RectCopy NAME(FillPoly1RectCopy) +#define iplFillPoly1RectGeneral NAME(FillPoly1RectGeneral) +#define iplFillRectSolidCopy NAME(FillRectSolidCopy) +#define iplFillRectSolidGeneral NAME(FillRectSolidGeneral) +#define iplFillRectSolidXor NAME(FillRectSolidXor) +#define iplFillRectTile32Copy NAME(FillRectTile32Copy) +#define iplFillRectTile32General NAME(FillRectTile32General) +#define iplFillRectTileOdd NAME(FillRectTileOdd) +#define iplFillSpanTile32sCopy NAME(FillSpanTile32sCopy) +#define iplFillSpanTile32sGeneral NAME(FillSpanTile32sGeneral) +#define iplFillSpanTileOddCopy NAME(FillSpanTileOddCopy) +#define iplFillSpanTileOddGeneral NAME(FillSpanTileOddGeneral) +#define iplFinishScreenInit NAME(FinishScreenInit) +#define iplGCFuncs NAME(GCFuncs) +#define iplGetImage NAME(GetImage) +#define iplGetScreenPixmap NAME(GetScreenPixmap) +#define iplGetSpans NAME(GetSpans) +#define iplHorzS NAME(HorzS) +#define iplImageGlyphBlt8 NAME(ImageGlyphBlt8) +#define iplLineSD NAME(LineSD) +#define iplLineSS NAME(LineSS) +#define iplMapWindow NAME(MapWindow) +#define iplMatchCommon NAME(MatchCommon) +#define iplNonTEOps NAME(NonTEOps) +#define iplNonTEOps1Rect NAME(NonTEOps1Rect) +#define iplPadPixmap NAME(PadPixmap) +#define iplPaintWindow NAME(PaintWindow) +#define iplPolyGlyphBlt8 NAME(PolyGlyphBlt8) +#define iplPolyGlyphRop8 NAME(PolyGlyphRop8) +#define iplPolyFillArcSolidCopy NAME(PolyFillArcSolidCopy) +#define iplPolyFillArcSolidGeneral NAME(PolyFillArcSolidGeneral) +#define iplPolyFillRect NAME(PolyFillRect) +#define iplPolyPoint NAME(PolyPoint) +#define iplPositionWindow NAME(PositionWindow) +#define iplPutImage NAME(PutImage) +#define iplReduceRasterOp NAME(ReduceRasterOp) +#define iplRestoreAreas NAME(RestoreAreas) +#define iplSaveAreas NAME(SaveAreas) +#define iplScreenInit NAME(ScreenInit) +#define iplSegmentSD NAME(SegmentSD) +#define iplSegmentSS NAME(SegmentSS) +#define iplSetScanline NAME(SetScanline) +#define iplSetScreenPixmap NAME(SetScreenPixmap) +#define iplSetSpans NAME(SetSpans) +#define iplSetupScreen NAME(SetupScreen) +#define iplSolidSpansCopy NAME(SolidSpansCopy) +#define iplSolidSpansGeneral NAME(SolidSpansGeneral) +#define iplSolidSpansXor NAME(SolidSpansXor) +#define iplStippleStack NAME(StippleStack) +#define iplStippleStackTE NAME(StippleStackTE) +#define iplTEGlyphBlt NAME(TEGlyphBlt) +#define iplTEOps NAME(TEOps) +#define iplTEOps1Rect NAME(TEOps1Rect) +#define iplTile32FSCopy NAME(Tile32FSCopy) +#define iplTile32FSGeneral NAME(Tile32FSGeneral) +#define iplUnmapWindow NAME(UnmapWindow) +#define iplUnnaturalStippleFS NAME(UnnaturalStippleFS) +#define iplUnnaturalTileFS NAME(UnnaturalTileFS) +#define iplValidateGC NAME(ValidateGC) +#define iplVertS NAME(VertS) +#define iplXRotatePixmap NAME(XRotatePixmap) +#define iplYRotatePixmap NAME(YRotatePixmap) +#define iplendpartial NAME(endpartial) +#define iplendtab NAME(endtab) +#define iplmask NAME(mask) +#define iplrmask NAME(rmask) +#define iplstartpartial NAME(startpartial) +#define iplstarttab NAME(starttab) +#define ipl8LineSS1Rect NAME(LineSS1Rect) +#define ipl8SegmentSS1Rect NAME(SegmentSS1Rect) +#define ipl8ClippedLineCopy NAME(ClippedLineCopy) +#define ipl8ClippedLineXor NAME(ClippedLineXor) +#define ipl8ClippedLineGeneral NAME(ClippedLineGeneral ) +#define ipl8SegmentSS1RectCopy NAME(SegmentSS1RectCopy) +#define ipl8SegmentSS1RectXor NAME(SegmentSS1RectXor) +#define ipl8SegmentSS1RectGeneral NAME(SegmentSS1RectGeneral ) +#define ipl8SegmentSS1RectShiftCopy NAME(SegmentSS1RectShiftCopy) +#define ipl8LineSS1RectCopy NAME(LineSS1RectCopy) +#define ipl8LineSS1RectXor NAME(LineSS1RectXor) +#define ipl8LineSS1RectGeneral NAME(LineSS1RectGeneral ) +#define ipl8LineSS1RectPreviousCopy NAME(LineSS1RectPreviousCopy) +#define iplZeroPolyArcSS8Copy NAME(ZeroPolyArcSSCopy) +#define iplZeroPolyArcSS8Xor NAME(ZeroPolyArcSSXor) +#define iplZeroPolyArcSS8General NAME(ZeroPolyArcSSGeneral) Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmergerop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmergerop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplmergerop.h (revision 51223) @@ -0,0 +1,146 @@ +/* $XFree86: xc/programs/Xserver/iplan2p4/iplmergerop.h,v 3.0 1996/08/18 01:54:53 dawes Exp $ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _IPLANMERGEROP_H_ +#define _IPLANMERGEROP_H_ + +/* Modified nov 94 by Martin Schaller (Martin_Schaller@maus.r.de) for use with +interleaved planes */ + +/* defines: + INTER_MROP_NAME + INTER_MROP_DECLARE_REG() + INTER_MROP_INITIALIZE(alu, pm) + INTER_MROP_SOLID(src1, src2, dst) + INTER_MROP_MASK(src1, src2, mask, dst) + INTER_MROP_PREBUILD(src) + INTER_MROP_PREBUILT_DECLARE() + INTER_MROP_PREBUILT_SOLID(src,dst) + INTER_MROP_PREBUILT_MASK(src,dst,mask) +*/ + +#ifndef GXcopy +#include +#endif + +typedef struct _mergeRopBits { + unsigned long ca1, cx1, ca2, cx2; +} mergeRopRec, *mergeRopPtr; + +extern mergeRopRec mergeRopBits[16]; + +#define INTER_DeclareMergeRop() \ + INTER_DECLAREGP(_ca1); \ + INTER_DECLAREGP(_cx1); \ + INTER_DECLAREGP(_ca2); \ + INTER_DECLAREGP(_cx2); + +#define INTER_DeclarePrebuiltMergeRop() \ + INTER_DECLAREGP(_cca); \ + INTER_DECLAREGP(_ccx); + +#define INTER_InitializeMergeRop(alu,pm) { \ + INTER_DECLAREGP(_pm); \ + mergeRopPtr _bits; \ + INTER_PFILL(pm, _pm); \ + _bits = &mergeRopBits[alu]; \ + INTER_ANDMSK(_pm, _bits->ca1, _ca1); \ + INTER_ANDMSK(_pm, _bits->ca2, _ca2); \ + INTER_ANDMSK(_pm, _bits->cx2, _cx2); \ + INTER_NOT(_pm, _pm); \ + INTER_ORMSK(_pm, _bits->cx1, _cx1); \ +} + +#define INTER_DoMergeRop(src1, src2, dst) \ + INTER_CPLX(src1, src2, _ca1, _cx1, _ca2, _cx2, dst) + +#define INTER_DoMaskMergeRop(src1, src2, mask, dst) \ + INTER_CPLXM(src1, src2, _ca1, _cx1, _ca2, _cx2, mask, dst) + +#define INTER_DoPrebuiltMergeRop(src, dst) \ + INTER_DoRRop(src, _cca, _ccx, dst) + +#define INTER_DoMaskPrebuiltMergeRop(src, mask, dst) \ + INTER_DoMaskRRop(src, _cca, _ccx, mask, dst) + +#define INTER_PrebuildMergeRop(src) \ + INTER_DoRRop(src, _ca1, _cx1, _cca); \ + INTER_DoRRop(src, _ca2, _cx2, _ccx); + +#ifndef MROP +#define MROP 0 +#endif + +#define Mclear (1< +#endif + +#if INTER_PLANES == 2 + +#define PLANE_TIMESCONDG(x) \ + ({ int _INDEX; \ + int _ret; \ + _ret=(_INDEX=0, (x)) && \ + (_INDEX=1, (x)) && \ + _ret; \ + }) + +#define PLANE_TIMESCOND(x) \ + ({ int _INDEX; \ + (_INDEX=0, x) \ + }) + +#define PLANE_TIMESG(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + _INDEX=1; x; \ + } + +#define PLANE_TIMES(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + } + +#elif INTER_PLANES == 4 + +#define PLANE_TIMESCONDG(x) \ + ({ int _INDEX; \ + int _ret; \ + _ret=(_INDEX=0, (x)) && \ + (_INDEX=1, (x)) && \ + (_INDEX=2, (x)) && \ + (_INDEX=3, (x)); \ + _ret; \ + }) + +#define PLANE_TIMESCOND(x) \ + ({ int _INDEX; \ + ((_INDEX=0, x) && \ + (_INDEX=1, x)) \ + }) + +#define PLANE_TIMESG(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + _INDEX=1; x; \ + _INDEX=2; x; \ + _INDEX=3; x; \ + } + +#define PLANE_TIMES(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + _INDEX=1; x; \ + } + +#elif INTER_PLANES == 8 + +#define PLANE_TIMESCONDG(x) \ + ({ int _INDEX; \ + int _ret; \ + _ret=((_INDEX=0, (x)) && \ + (_INDEX=1, (x)) && \ + (_INDEX=2, (x)) && \ + (_INDEX=3, (x)) && \ + (_INDEX=4, (x)) && \ + (_INDEX=5, (x)) && \ + (_INDEX=6, (x)) && \ + (_INDEX=7, (x))); \ + _ret; \ + }) + +#define PLANE_TIMESCOND(x) \ + ({ int _INDEX; \ + ((_INDEX=0, x) && \ + (_INDEX=1, x) && \ + (_INDEX=2, x) && \ + (_INDEX=3, x)) \ + }) + +#define PLANE_TIMESG(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + _INDEX=1; x; \ + _INDEX=2; x; \ + _INDEX=3; x; \ + _INDEX=4; x; \ + _INDEX=5; x; \ + _INDEX=6; x; \ + _INDEX=7; x; \ + } + +#define PLANE_TIMES(x) \ + { int _INDEX; \ + _INDEX=0; x; \ + _INDEX=1; x; \ + _INDEX=2; x; \ + _INDEX=3; x; \ + } + +#endif + +/* src = 0 */ +#define INTER_IS_CLR(src) \ + PLANE_TIMESCONDG(_IG(src) == 0) + +/* src = PPGMSK ? */ +#define INTER_IS_SET(src) \ + PLANE_TIMESCONDG(_IG(src) == INTER_PPGMSK) + +/* (src1 ^ scr2) = PPGMSK ? */ +#define INTER_IS_XOR_SET(src1, src2) \ + PLANE_TIMESCONDG((_IG(src1) ^ _IG(src2)) == INTER_PPGMSK) + +/* dst = ~src */ +#define INTER_NOT(src, dst) \ + PLANE_TIMES(_I(dst) = ~_I(src)) + +/* dst = 0 */ +#define INTER_CLR(dst) \ + PLANE_TIMES(_I(dst) = 0) + +/* dst = PPGMSK */ +#define INTER_SET(dst) \ + PLANE_TIMESG(_IG(dst) = INTER_PPGMSK) + +/* dst = src */ +#define INTER_COPY(src,dst) \ + PLANE_TIMES(_I(dst) = _I(src)) + +/* dst2 = (dst & ~mask) | (src & mask) */ +#define INTER_COPYM(src,dst,mask,dst2) \ + PLANE_TIMESG( \ + _IG(dst2) = (_IG(dst) & ~mask) | (_IG(src) & mask) \ + ) + +/* dst2 = dst ^ src */ +#define INTER_XOR(src,dst,dst2) \ + PLANE_TIMES(_I(dst2) = _I(dst) ^ _I(src)) + +/* dst2 = dst ^ (src & mask) */ +#define INTER_XORM(src,dst,mask,dst2) \ + PLANE_TIMESG(_IG(dst2) = _IG(dst) ^ (_IG(src) & (mask))) + +/* dst2 = dst & src */ +#define INTER_AND(src,dst,dst2) \ + PLANE_TIMES(_I(dst2) = _I(dst) & _I(src)) + +/* dst2 = dst & (src | ~mask) */ +#define INTER_ANDM(mask,src,dst,dst2) \ + PLANE_TIMESG(_IG(dst2) = _IG(dst) & (_IG(src) | ~(mask))) + +/* dst2 = dst | src */ +#define INTER_OR(src,dst,dst2) \ + PLANE_TIMES(_I(dst2) = _I(dst) | _I(src)) + +/* dst2 = dst | (src & mask) */ +#define INTER_ORM(src,dst,mask,dst2) \ + PLANE_TIMESG(_IG(dst2) = _IG(dst) | (_IG(src) & (mask))) + +/* dst = src | msk */ +#define INTER_ORMSK(src,msk,dst) \ + PLANE_TIMESG(_IG(dst) = _IG(src) | (msk)) + +/* dst = src & msk */ +#define INTER_ANDMSK(src,msk,dst) \ + PLANE_TIMESG(_IG(dst) = _IG(src) & (msk)) + +/* dst = (src1 & msk1) | (src2 & msk2) */ +#define INTER_ANDMSK2(src1,msk1,src2,msk2,dst) \ + PLANE_TIMESG(_IG(dst) = (_IG(src1) & (msk1)) | (_IG(src2) & (msk2))) + +#define INTER_PLANE(x) (1<<(x)) + +#define INTER_PFILL(col, fill) \ + PLANE_TIMESG(_IG(fill) = \ + ((col) & INTER_PLANE(_INDEX)) ? INTER_PPGMSK : 0) + +/* dst = src >> cnt */ +#define INTER_SCRRIGHT(cnt, src, dst) \ + PLANE_TIMESG(_IG(dst) = _IG(src) >> (cnt)) + +/* dst = src << cnt */ +#define INTER_SCRLEFT(cnt, src, dst) \ + PLANE_TIMESG(_IG(dst) = _IG(src) << (cnt)) + +/* bits1=(bits >> right) | (bits=psrc) << left) */ +#define INTER_GETRLC(right, left, psrc, bits, bits1) \ + PLANE_TIMESG( _IG(bits1)=(_IG(bits) >> (right)) | \ + ((_IG(bits) = _IG(psrc)) << (left))) + +/* bits1=(bits << left) | (bits=psrc) >> right) */ +#define INTER_GETLRC(left, right, psrc, bits, bits1) \ + PLANE_TIMESG( _IG(bits1)=(_IG(bits) << (left)) | \ + ((_IG(bits) = _IG(psrc)) >> (right))) + +/* dst=src2 & (src1 & a1 ^ x1) ^ (src1 & a2 ^ x2) */ +#define INTER_CPLX(src1, src2, a1, x1, a2, x2, dst) \ + PLANE_TIMES( _I(dst) = (_I(src2) \ + & (_I(src1) & _I(a1) ^ _I(x1)) \ + ^ (_I(src1) & _I(a2) ^ _I(x2)))) \ + +/* dst=src2 & ((src1 & a1 ^ x1) | ~mask) ^ ((src1 & a2 ^ x2) & mask) */ +#define INTER_CPLXM(src1, src2, a1, x1, a2, x2, mask, dst) \ + PLANE_TIMESG( _IG(dst) = (_IG(src2) \ + & ((_IG(src1) & _IG(a1) ^ _IG(x1)) | ~mask) \ + ^ ((_IG(src1) & _IG(a2) ^ _IG(x2)) & mask))) + +/* dst = (src & ~(bitmask | planemask)) | (insert | (bitmask | planemask)) */ +#define INTER_PMSKINS(bitmask, planemask, insert, src, dst) \ + PLANE_TIMESG( \ + if (planemask & INTER_PLANE(_INDEX)) \ + _IG(dst) = (_IG(src) & ~bitmask) | (_IG(insert) & bitmask) \ + ) + +/* dst = (src & ~bitmask) | ((insert >> shift) & bitmask) */ +#define INTER_SCRRMSKINS(bitmask, planemask, insert, shift, src, dst) \ + PLANE_TIMESG( \ + if (planemask & INTER_PLANE(_INDEX)) \ + _IG(dst) = (_IG(src) & ~(bitmask)) | \ + ((_IG(insert) >> shift) & (bitmask)) \ + ) + +/* dst = (src & ~bitmask) | ((insert << shift) & bitmask) */ +#define INTER_SCRLMSKINS(bitmask, planemask, insert, shift, src, dst) \ + PLANE_TIMESG( \ + if (planemask & INTER_PLANE(_INDEX)) \ + _IG(dst) = (_IG(src) & ~bitmask) | \ + ((_IG(insert) << shift) & bitmask) \ + ) + +/* dst = ((src1 << sl1) & bitmask1) | ((src2 >> sr2) & bitmask2) */ +#define INTER_MSKINSM(bitmask1, sl1, src1, bitmask2, sr2, src2, dst) \ + PLANE_TIMESG( \ + _IG(dst) = ((_IG(src1) << sl1) & (bitmask1)) | \ + ((_IG(src2) >> sr2) & (bitmask2)) \ + ) + +/* dst = src & and ^ xor */ +#define INTER_DoRRop(src, and, xor, dst) \ + PLANE_TIMES(_I(dst) = (_I(src) & _I(and) ^ _I(xor))) \ + +#define INTER_DoMaskRRop(src, and, xor, mask, dst) \ + PLANE_TIMESG( \ + _IG(dst) = (_IG(src) & ((_IG(and) | ~(mask))) \ + ^ (_IG(xor) & mask))) + +#define INTER_DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) { \ + PLANE_TIMES( \ + _I(result) = fnCOPY (_I(src), _I(dst))); \ + } else if (alu == GXxor) { \ + PLANE_TIMES( \ + _I(result) = fnXOR (_I(src), _I(dst))); \ + } \ + else { \ + switch (alu) \ + { \ + case GXclear: \ + PLANE_TIMES( \ + _I(result) = fnCLEAR (_I(src), _I(dst))); \ + break; \ + case GXand: \ + PLANE_TIMES( \ + _I(result) = fnAND (_I(src), _I(dst))); \ + break; \ + case GXandReverse: \ + PLANE_TIMES( \ + _I(result) = fnANDREVERSE (_I(src), _I(dst))); \ + break; \ + case GXandInverted: \ + PLANE_TIMES( \ + _I(result) = fnANDINVERTED (_I(src), _I(dst))); \ + break; \ + case GXnoop: \ + PLANE_TIMES( \ + _I(result) = fnNOOP (_I(src), _I(dst))); \ + break; \ + case GXor: \ + PLANE_TIMES( \ + _I(result) = fnOR (_I(src), _I(dst))); \ + break; \ + case GXnor: \ + PLANE_TIMES( \ + _I(result) = fnNOR (_I(src), _I(dst))); \ + break; \ + case GXequiv: \ + PLANE_TIMES( \ + _I(result) = fnEQUIV (_I(src), _I(dst))); \ + break; \ + case GXinvert: \ + PLANE_TIMES( \ + _I(result) = fnINVERT (_I(src), _I(dst))); \ + break; \ + case GXorReverse: \ + PLANE_TIMES( \ + _I(result) = fnORREVERSE (_I(src), _I(dst))); \ + break; \ + case GXcopyInverted: \ + PLANE_TIMES( \ + _I(result) = fnCOPYINVERTED (_I(src), _I(dst))); \ + break; \ + case GXorInverted: \ + PLANE_TIMES( \ + _I(result) = fnORINVERTED (_I(src), _I(dst))); \ + break; \ + case GXnand: \ + PLANE_TIMES( \ + _I(result) = fnNAND (_I(src), _I(dst))); \ + break; \ + case GXset: \ + PLANE_TIMES( \ + _I(result) = fnSET (_I(src), _I(dst))); \ + break; \ + } \ + } \ +} + +#define iplGetGroupWidthAndPointer(pDrawable, width, pointer) \ + iplGetTypedWidthAndPointer(pDrawable, width, pointer, INTER_PIXGRP, INTER_PIXGRP) + +#define INTER_getstipplepixels(psrcstip, x, w, ones, psrcpix, pdstpix) \ +{ \ + unsigned long q; \ + int m; \ + if (ones) { \ + if ((m = ((x) - ((MFB_PPW*MFB_PSZ)-MFB_PPW))) > 0) { \ + q = (*(psrcstip)) << m; \ + if ( (x)+(w) > (MFB_PPW*MFB_PSZ) ) \ + q |= *((psrcstip)+1) >> ((MFB_PPW*MFB_PSZ)-m); \ + } \ + else \ + q = (*(psrcstip)) >> -m; \ + } \ + else { \ + if ((m = ((x) - ((MFB_PPW*MFB_PSZ)-MFB_PPW))) > 0) { \ + q = (~ *(psrcstip)) << m; \ + if ( (x)+(w) > (MFB_PPW*MFB_PSZ) ) \ + q |= (~*((psrcstip)+1)) >> ((MFB_PPW*MFB_PSZ)-m); \ + } \ + else \ + q = (~ *(psrcstip)) >> -m; \ + } \ + q >>=16; \ + INTER_ANDMSK(psrcpix,q,pdstpix); \ +} + +#define INTER_getstipplepixelsb(psrcstip, x, w, psrcpix0, psrcpix1, pdstpix) \ +{ \ + unsigned long q,qn; \ + int m; \ + if ((m = ((x) - ((MFB_PPW*MFB_PSZ)-MFB_PPW))) > 0) { \ + q = (*(psrcstip)) << m; \ + qn = (~ *(psrcstip)) << m; \ + if ( (x)+(w) > (MFB_PPW*MFB_PSZ) ) { \ + q |= *((psrcstip)+1) >> ((MFB_PPW*MFB_PSZ)-m); \ + qn |= (~ *((psrcstip)+1)) >> ((MFB_PPW*MFB_PSZ)-m); \ + } \ + } \ + else { \ + q = (*(psrcstip)) >> -m; \ + qn = (~ *(psrcstip)) >> -m; \ + } \ + q >>=16; \ + qn >>=16; \ + INTER_ANDMSK2(psrcpix0,qn,psrcpix1,q,pdstpix); \ +} + +#define INTER_maskbits(x, w, startmask, endmask, nlg) \ + startmask = iplstarttab[(x) & INTER_PIM]; \ + endmask = iplendtab[((x)+(w)) & INTER_PIM]; \ + if (startmask) \ + nlg = (((w) - (INTER_PPG - ((x) & INTER_PIM))) >> INTER_PGSH); \ + else \ + nlg = (w) >> INTER_PGSH; + +#define INTER_maskpartialbits(x, w, mask) \ + mask = iplstartpartial[(x) & INTER_PIM] & \ + iplendpartial[((x) + (w)) & INTER_PIM]; + +#define INTER_mask32bits(x, w, startmask, endmask, nlw) \ + startmask = iplstarttab[(x) & INTER_PIM]; \ + endmask = iplendtab[((x)+(w)) & INTER_PIM]; + +#define INTER_getbits(psrc, x, w, pdst) \ + if ( ((x) + (w)) <= INTER_PPG) \ + { \ + INTER_SCRLEFT((x), psrc, pdst); \ + } \ + else \ + { \ + int m; \ + m = INTER_PPG-(x); \ + INTER_MSKINSM(iplendtab[m], x, psrc, \ + iplstarttab[m], m, INTER_NEXT(psrc), pdst); \ + } + +#define INTER_putbits(psrc, x, w, pdst, planemask) \ + if ( ((x)+(w)) <= INTER_PPG) \ + { \ + INTER_DECLAREG(tmpmask); \ + INTER_maskpartialbits((x), (w), tmpmask); \ + INTER_SCRRMSKINS(tmpmask, planemask, psrc, x, pdst, pdst); \ + } \ + else \ + { \ + unsigned long m; \ + unsigned long n; \ + m = INTER_PPG-(x); \ + n = (w) - m; \ + INTER_SCRRMSKINS(iplstarttab[x], planemask, psrc, x, \ + pdst, pdst); \ + INTER_SCRLMSKINS(iplendtab[n], planemask, psrc, m, \ + INTER_NEXT(pdst), INTER_NEXT(pdst)); \ + } + +#define INTER_putbitsrop(psrc, x, w, pdst, planemask, rop) \ +if ( ((x)+(w)) <= INTER_PPG) \ +{ \ + INTER_DECLAREG(tmpmask); \ + INTER_DECLAREGP(t1); INTER_DECLAREGP(t2); \ + INTER_maskpartialbits((x), (w), tmpmask); \ + INTER_SCRRIGHT((x), (psrc), (t1)); \ + INTER_DoRop(t2, rop, t1, pdst); \ + INTER_PMSKINS(tmpmask, planemask, t2, pdst, pdst); \ +} \ +else \ +{ \ + unsigned long m; \ + unsigned long n; \ + INTER_DECLAREGP(t1); INTER_DECLAREGP(t2); \ + m = INTER_PPG-(x); \ + n = (w) - m; \ + INTER_SCRRIGHT((x), (psrc), (t1)); \ + INTER_DoRop(t2, rop, t1, pdst); \ + INTER_PMSKINS(iplstarttab[x], planemask, t2, pdst, pdst); \ + INTER_SCRLEFT(m, (psrc), (t1)); \ + INTER_DoRop(t2, rop, t1, pdst+1); \ + INTER_PMSKINS(iplendtab[n], planemask, t2, pdst, pdst); \ +} + +#define INTER_putbitsmropshort(src, x, w, pdst) { \ + INTER_DECLAREG(_tmpmask); \ + INTER_DECLAREGP(_t1); \ + INTER_maskpartialbits((x), (w), _tmpmask); \ + INTER_SCRRIGHT((x), (src), _t1); \ + INTER_DoMaskMergeRop(_t1, pdst, _tmpmask, pdst); \ +} + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplpack.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplpack.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplpack.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86$ */ +/* Modified nov 94 by Martin Schaller (Martin_Schaller@maus.r.de) for use with +interleaved planes */ + +#define NUM_LONGS(planes, xs, xe) \ + (((((xe) * (planes) + 31) & ~31) - \ + (((xs) * (planes)) & ~31))/32) + +#define NUM_TEMP_BYTES(planes, longs) \ + (((2 * (longs) + (planes) - 1) / planes + 1) * planes * 2) Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplrrop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplrrop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/iplrrop.h (revision 51223) @@ -0,0 +1,80 @@ +/* $XFree86: xc/programs/Xserver/iplan2p4/iplrrop.h,v 3.0 1996/08/18 01:55:04 dawes Exp $ */ +/* Modified nov 94 by Martin Schaller (Martin_Schaller@maus.r.de) for use with +interleaved planes */ + +/* reduced raster ops */ +/* INTER_RROP_DECLARE INTER_RROP_FETCH_GC, + INTER_RROP_SOLID_MASK, INTER_RROP_SPAN INTER_RROP_NAME */ + +#define INTER_RROP_FETCH_GC(gc) \ +INTER_RROP_FETCH_GCPRIV(((iplPrivGCPtr)(gc)->devPrivates[iplGCPrivateIndex].ptr)) + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#if RROP == GXcopy +#define INTER_RROP_DECLARE register unsigned short *rrop_xor; +#define INTER_RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xorg; +#define INTER_RROP_SOLID(dst) INTER_COPY(rrop_xor, dst) +#define INTER_RROP_SOLID_MASK(dst,mask) INTER_COPYM(rrop_xor, dst, mask, dst) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,Copy) +#endif /* GXcopy */ + +#if RROP == GXxor +#define INTER_RROP_DECLARE register unsigned short *rrop_xor; +#define INTER_RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xorg; +#define INTER_RROP_SOLID(dst) INTER_XOR(rrop_xor, dst, dst) +#define INTER_RROP_SOLID_MASK(dst,mask) INTER_XORM(rrop_xor, dst, mask, dst) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,Xor) +#endif /* GXxor */ + +#if RROP == GXand +#define INTER_RROP_DECLARE register unsigned short *rrop_and; +#define INTER_RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->andg; +#define INTER_RROP_SOLID(dst) INTER_AND(rrop_and, dst, dst) +#define INTER_RROP_SOLID_MASK(dst,mask) INTER_ANDM(rrop_and, dst, mask, dst) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,And) +#endif /* GXand */ + +#if RROP == GXor +#define INTER_RROP_DECLARE register unsigned short *rrop_or; +#define INTER_RROP_FETCH_GCPRIV(devPriv) rrop_or = (devPriv)->xorg; +#define INTER_RROP_SOLID(dst) INTER_OR(rrop_or, dst, dst) +#define INTER_RROP_SOLID_MASK(dst,mask) INTER_ORM(mask, rrop_or, dst, dst) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,Or) +#endif /* GXor */ + +#if RROP == GXnoop +#define INTER_RROP_DECLARE +#define INTER_RROP_FETCH_GCPRIV(devPriv) +#define INTER_RROP_SOLID(dst) +#define INTER_RROP_SOLID_MASK(dst,mask) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,Noop) +#endif /* GXnoop */ + +#if RROP == GXset +#define INTER_RROP_DECLARE register unsigned short *rrop_and, *rrop_xor; +#define INTER_RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->andg; \ + rrop_xor = (devPriv)->xorg; +#define INTER_RROP_SOLID(dst) INTER_DoRRop(dst, rrop_and, rrop_xor, dst) +#define INTER_RROP_SOLID_MASK(dst,mask) \ + INTER_DoMaskRRop(dst, rrop_and, rrop_xor, mask, dst) +#define INTER_RROP_NAME(prefix) INTER_RROP_NAME_CAT(prefix,General) +#endif /* GXset */ + +#ifndef INTER_RROP_SPAN +#define INTER_RROP_SPAN(pdst,nmiddle) \ + while (--(nmiddle) >= 0) { \ + INTER_RROP_SOLID(pdst); \ + (pdst) = INTER_NEXT(pdst); \ + } + +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define INTER_RROP_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define INTER_RROP_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keyboard-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keyboard-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keyboard-cfg.h (revision 51223) @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/keyboard-cfg.h,v 1.2 2000/06/13 23:15:51 dawes Exp $ + */ + +#include "config.h" +#include + +#ifndef _xf86cfg_keyboard_h +#define _xf86cfg_keyboard_h + +/* + * All file names are from XProjectRoot or XWINHOME environment variable. + */ +#define XkbConfigDir "lib/X11/xkb/" +#define XkbConfigFile "X0-config.keyboard" + +/* + * Types + */ +typedef struct { + char **name; + char **desc; + int nelem; +} XF86XkbDescInfo; + +typedef struct { + XF86ConfInputPtr conf; + XkbDescPtr xkb; + XkbRF_VarDefsRec defs; + XkbConfigRtrnRec config; +} XkbInfo; + +/* + * Prototypes + */ +XtPointer KeyboardConfig(XtPointer); +void KeyboardModelAndLayout(XF86SetupInfo*); +void InitializeKeyboard(void); +Bool UpdateKeyboard(Bool); +Bool WriteXKBConfiguration(char*, XkbConfigRtrnPtr); + +/* + * Initialization + */ +extern XkbInfo *xkb_info; + +#endif /* _xf86cfg_keyboard_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keysym2ucs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keysym2ucs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/keysym2ucs.h (revision 51223) @@ -0,0 +1,37 @@ +/* $XFree86: $ + * + * This module converts keysym values into the corresponding ISO 10646 + * (UCS, Unicode) values. + * + * The array keysymtab[] contains pairs of X11 keysym values for graphical + * characters and the corresponding Unicode value. The function + * keysym2ucs() maps a keysym onto a Unicode value using a binary search, + * therefore keysymtab[] must remain SORTED by keysym value. + * + * The keysym -> UTF-8 conversion will hopefully one day be provided + * by Xlib via XmbLookupString() and should ideally not have to be + * done in X applications. But we are not there yet. + * + * We allow to represent any UCS character in the range U-00000000 to + * U-00FFFFFF by a keysym value in the range 0x01000000 to 0x01ffffff. + * This admittedly does not cover the entire 31-bit space of UCS, but + * it does cover all of the characters up to U-10FFFF, which can be + * represented by UTF-16, and more, and it is very unlikely that higher + * UCS codes will ever be assigned by ISO. So to get Unicode character + * U+ABCD you can directly use keysym 0x0100abcd. + * + * Author: Markus G. Kuhn , University of Cambridge, April 2001 + * + * Special thanks to Richard Verhoeven for preparing + * an initial draft of the mapping table. + * + * This software is in the public domain. Share and enjoy! + */ + +#ifndef KEYSYM2UCS_H +#define KEYSYM2UCS_H 1 + +extern long keysym2ucs(int keysym); +extern int ucs2keysym(long ucs); + +#endif /* KEYSYM2UCS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layer.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layer.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layer.h (revision 51223) @@ -0,0 +1,149 @@ +/* + * $XFree86: xc/programs/Xserver/miext/layer/layer.h,v 1.4 2001/08/01 00:44:58 tsi Exp $ + * + * Copyright © 2001 Keith Packard, member of The XFree86 Project, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LAYER_H_ +#define _LAYER_H_ + +#include + +#define LAYER_FB 0 +#define LAYER_SHADOW 1 + +typedef struct _LayerKind *LayerKindPtr; +typedef struct _LayerWin *LayerWinPtr; +typedef struct _LayerList *LayerListPtr; +typedef struct _LayerGC *LayerGCPtr; +typedef struct _Layer *LayerPtr; +typedef struct _LayerScreen *LayerScreenPtr; + +/* + * We'll try to work without a list of windows in each layer + * for now, this will make computing bounding boxes for each + * layer rather expensive, so that may need to change at some point. + */ + +#define LAYER_SCREEN_PIXMAP ((PixmapPtr) 1) + +typedef struct _Layer { + LayerPtr pNext; /* a list of all layers for this screen */ + LayerKindPtr pKind; /* characteristics of this layer */ + int refcnt; /* reference count, layer is freed when zero */ + int windows; /* number of windows, free pixmap when zero */ + int depth; /* window depth in this layer */ + PixmapPtr pPixmap; /* pixmap for this layer (may be frame buffer) */ + Bool freePixmap; /* whether to free this pixmap when done */ + RegionRec region; /* valid set of pPixmap for drawing */ + ShadowUpdateProc update; /* for shadow layers, update/window/closure values */ + ShadowWindowProc window; + int randr; + void *closure; +} LayerRec; + +/* + * Call this before wrapping stuff for acceleration, it + * gives layer pointers to the raw frame buffer functions + */ + +Bool +LayerStartInit (ScreenPtr pScreen); + +/* + * Initialize wrappers for each acceleration type and + * call this function, it will move the needed functions + * into a new LayerKind and replace them with the generic + * functions. + */ + +int +LayerNewKind (ScreenPtr pScreen); + +/* + * Finally, call this function and layer + * will wrap the screen functions and prepare for execution + */ + +Bool +LayerFinishInit (ScreenPtr pScreen); + +/* + * At any point after LayerStartInit, a new layer can be created. + */ +LayerPtr +LayerCreate (ScreenPtr pScreen, + int kind, + int depth, + PixmapPtr pPixmap, + ShadowUpdateProc update, + ShadowWindowProc window, + int randr, + void *closure); + +/* + * Create a layer pixmap + */ +Bool +LayerCreatePixmap (ScreenPtr pScreen, LayerPtr pLayer); + +/* + * Change a layer pixmap + */ +void +LayerSetPixmap (ScreenPtr pScreen, LayerPtr pLayer, PixmapPtr pPixmap); + +/* + * Destroy a layer pixmap + */ +void +LayerDestroyPixmap (ScreenPtr pScreen, LayerPtr pLayer); + +/* + * Change a layer kind + */ +void +LayerSetKind (ScreenPtr pScreen, LayerPtr pLayer, int kind); + +/* + * Destroy a layer. The layer must not contain any windows. + */ +void +LayerDestroy (ScreenPtr pScreen, LayerPtr layer); + +/* + * Add a window to a layer + */ +Bool +LayerWindowAdd (ScreenPtr pScreen, LayerPtr pLayer, WindowPtr pWin); + +/* + * Remove a window from a layer + */ + +void +LayerWindowRemove (ScreenPtr pScreen, LayerPtr pLayer, WindowPtr pWin); + +#endif /* _LAYER_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layerstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layerstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/layerstr.h (revision 51223) @@ -0,0 +1,425 @@ +/* + * $XFree86: xc/programs/Xserver/miext/layer/layerstr.h,v 1.2 2001/06/04 09:45:41 keithp Exp $ + * + * Copyright © 2001 Keith Packard, member of The XFree86 Project, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LAYERSTR_H_ +#define _LAYERSTR_H_ + +#include +#include "scrnintstr.h" +#include "windowstr.h" +#include +#include "dixfontstr.h" +#include +#include "mi.h" +#include "regionstr.h" +#include "globals.h" +#include "gcstruct.h" +#include "layer.h" +#ifdef RENDER +#include "picturestr.h" +#endif + +extern int layerScrPrivateIndex; +extern int layerGCPrivateIndex; +extern int layerWinPrivateIndex; + +/* + * One of these for each possible set of underlying + * rendering code. The first kind always points at the + * underlying frame buffer code and is created in LayerStartInit + * so that LayerNewKind can unwrap the screen and prepare it + * for another wrapping sequence. + * + * The set of functions wrapped here must be at least the union + * of all functions wrapped by any rendering layer in use; they're + * easy to add, so don't be shy + */ + +typedef struct _LayerKind { + int kind; /* kind index */ + + CloseScreenProcPtr CloseScreen; + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + + CreateGCProcPtr CreateGC; +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; +#endif +} LayerKindRec; + +#define LayerWrap(orig,lay,member,func) \ + (((lay)->member = (orig)->member),\ + ((orig)->member = (func))) +#define LayerUnwrap(orig,lay,member) \ + ((orig)->member = (lay)->member) + +/* + * This is the window private structure allocated for + * all windows. There are two possible alternatives here, + * either the window belongs to a single layer and uses its + * internal clip/borderClip lists or the window belongs to one + * or more layers and uses a separate clip/borderclip for each + * layer. When this is integrated into the core window struct, + * the LayerWinKind can become a single bit saving 8 bytes per + * window. + */ + +typedef struct _LayerWin { + Bool isList; + union { + LayerPtr pLayer; + LayerListPtr pLayList; + } u; +} LayerWinRec; + +typedef struct _LayerList { + LayerListPtr pNext; /* list of layers for this window */ + LayerPtr pLayer; /* the layer */ + Bool inheritClip; /* use the window clipList/borderClip */ + RegionRec clipList; /* per-layer clip/border clip lists */ + RegionRec borderClip; +} LayerListRec; + +#define layerGetWinPriv(pWin) ((LayerWinPtr) (pWin)->devPrivates[layerWinPrivateIndex].ptr) +#define layerWinPriv(pWin) LayerWinPtr pLayWin = layerGetWinPriv(pWin) + +#define layerWinLayer(pLayWin) ((pLayWin)->isList ? (pLayWin)->u.pLayList->pLayer : (pLayWin)->u.pLayer) + +typedef struct _LayerWinLoop { + LayerWinPtr pLayWin; + LayerListPtr pLayList; + PixmapPtr pPixmap; /* original window pixmap */ + RegionRec clipList; /* saved original clipList contents */ + RegionRec borderClip; /* saved original borderClip contents */ +} LayerWinLoopRec, *LayerWinLoopPtr; + +#define layerWinFirstLayer(pLayWin,pLayList) ((pLayWin)->isList ? ((pLayList) = (pLayWin)->u.pLayList)->pLayer : pLayWin->u.pLayer) +#define layerWinNextLayer(pLayWin,pLayList) ((pLayWin)->isList ? ((pLayList) = (pLayList)->pNext)->pLayer : 0) + +LayerPtr +LayerWindowFirst (WindowPtr pWin, LayerWinLoopPtr pLoop); + +LayerPtr +LayerWindowNext (WindowPtr pWin, LayerWinLoopPtr pLoop); + +void +LayerWindowDone (WindowPtr pWin, LayerWinLoopPtr pLoop); + + +/* + * This is the GC private structure allocated for all GCs. + * XXX this is really messed up; I'm not sure how to fix it yet + */ + +typedef struct _LayerGC { + GCFuncs *funcs; + LayerKindPtr pKind; +} LayerGCRec; + +#define layerGetGCPriv(pGC) ((LayerGCPtr) (pGC)->devPrivates[layerGCPrivateIndex].ptr) +#define layerGCPriv(pGC) LayerGCPtr pLayGC = layerGetGCPriv(pGC) + +/* + * This is the screen private, it contains + * the layer kinds and the layers themselves + */ +typedef struct _LayerScreen { + int nkinds; /* number of elements in kinds array */ + LayerKindPtr kinds; /* created kinds; reallocated when new ones added */ + LayerPtr pLayers; /* list of layers for this screen */ +} LayerScreenRec; + +#define layerGetScrPriv(pScreen) ((LayerScreenPtr) (pScreen)->devPrivates[layerScrPrivateIndex].ptr) +#define layerScrPriv(pScreen) LayerScreenPtr pLayScr = layerGetScrPriv(pScreen) + +Bool +layerCloseScreen (int index, ScreenPtr pScreen); + +Bool +layerCreateWindow (WindowPtr pWin); + +Bool +layerDestroyWindow (WindowPtr pWin); + +Bool +layerChangeWindowAttributes (WindowPtr pWin, unsigned long mask); + +void +layerPaintWindowBackground (WindowPtr pWin, RegionPtr pRegion, int what); + +void +layerPaintWindowBorder (WindowPtr pWin, RegionPtr pRegion, int what); + +void +layerCopyWindow(WindowPtr pWin, DDXPointRec ptOldOrg, RegionPtr prgnSrc); + +PixmapPtr +layerCreatePixmap (ScreenPtr pScreen, int width, int height, int depth); + +Bool +layerDestroyPixmap (PixmapPtr pPixmap); + +Bool +layerCreateGC (GCPtr pGC); + +#ifdef RENDER +void +layerComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void +layerGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +void +layerCompositeRects (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); +#endif +void layerValidateGC(GCPtr, unsigned long, DrawablePtr); +void layerChangeGC(GCPtr, unsigned long); +void layerCopyGC(GCPtr, unsigned long, GCPtr); +void layerDestroyGC(GCPtr); +void layerChangeClip(GCPtr, int, pointer, int); +void layerDestroyClip(GCPtr); +void layerCopyClip(GCPtr, GCPtr); + +void +layerFillSpans(DrawablePtr pDraw, + GC *pGC, + int nInit, + DDXPointPtr pptInit, + int *pwidthInit, + int fSorted); + +void +layerSetSpans(DrawablePtr pDraw, + GCPtr pGC, + char *pcharsrc, + DDXPointPtr pptInit, + int *pwidthInit, + int nspans, + int fSorted); + +void +layerPutImage( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, int y, int w, int h, + int leftPad, + int format, + char *pImage +); + +RegionPtr +layerCopyArea( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty +); + +RegionPtr +layerCopyPlane( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty, + unsigned long bitPlane +); + +void +layerPolyPoint( + DrawablePtr pDraw, + GCPtr pGC, + int mode, + int npt, + xPoint *pptInit +); +void +layerPolylines( + DrawablePtr pDraw, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit +); + +void +layerPolySegment( + DrawablePtr pDraw, + GCPtr pGC, + int nseg, + xSegment *pSeg +); + +void +layerPolyRectangle( + DrawablePtr pDraw, + GCPtr pGC, + int nRects, + xRectangle *pRects +); + +void +layerPolyArc( + DrawablePtr pDraw, + GCPtr pGC, + int narcs, + xArc *parcs +); + +void +layerFillPolygon( + DrawablePtr pDraw, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr pptInit +); + +void +layerPolyFillRect( + DrawablePtr pDraw, + GCPtr pGC, + int nRectsInit, + xRectangle *pRectsInit +); + +void +layerPolyFillArc( + DrawablePtr pDraw, + GCPtr pGC, + int narcs, + xArc *parcs +); + +int +layerPolyText8( + DrawablePtr pDraw, + GCPtr pGC, + int x, + int y, + int count, + char *chars +); + +int +layerPolyText16( + DrawablePtr pDraw, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *chars +); + +void +layerImageText8( + DrawablePtr pDraw, + GCPtr pGC, + int x, + int y, + int count, + char *chars +); + +void +layerImageText16( + DrawablePtr pDraw, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *chars +); + +void +layerImageGlyphBlt( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +layerPolyGlyphBlt( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +layerPushPixels( + GCPtr pGC, + PixmapPtr pBitMap, + DrawablePtr pDraw, + int dx, int dy, int xOrg, int yOrg +); + +#endif /* _LAYERSTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxdata.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxdata.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxdata.h (revision 51223) @@ -0,0 +1,48 @@ +/* $Xorg: lbxdata.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* + * Copyright 1994 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXDATA_H_ +#define _LBXDATA_H_ +#define NEED_REPLIES +#include +#include +#define _XLBX_SERVER_ +#include +#include "dixfontstr.h" + +extern int lbx_font_private; + +typedef struct _fonttaginfo { + XID tid; + FontPtr pfont; + unsigned long size; + int compression; + xLbxFontInfo *fontinfo; +} FontTagInfoRec, *FontTagInfoPtr; + +#endif /* _LBXDATA_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxserve.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxserve.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxserve.h (revision 51223) @@ -0,0 +1,289 @@ +/* $Xorg: lbxserve.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * Copyright 1992 Network Computing Devices + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of NCD. not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. NCD. makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * NCD. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL NCD. + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxserve.h,v 1.4 2001/08/01 00:44:58 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXSERVE_H_ + +#include "colormap.h" +#include "property.h" + +#define _LBXSERVE_H_ +#define _XLBX_SERVER_ +#include +#include +#include + +#define MAX_LBX_CLIENTS MAXCLIENTS +#define MAX_NUM_PROXIES (MAXCLIENTS >> 1) + +typedef struct _LbxClient *LbxClientPtr; +typedef struct _LbxProxy *LbxProxyPtr; + +typedef struct _LbxClient { + CARD32 id; + ClientPtr client; + LbxProxyPtr proxy; + Bool ignored; + Bool input_blocked; + int reqs_pending; + long bytes_in_reply; + long bytes_remaining; + Drawable drawableCache[GFX_CACHE_SIZE]; + GContext gcontextCache[GFX_CACHE_SIZE]; + pointer gfx_buffer; /* tmp buffer for unpacking gfx requests */ + unsigned long gb_size; +} LbxClientRec; + +typedef struct _connectionOutput *OSBufPtr; + +typedef struct _LbxProxy { + LbxProxyPtr next; + /* this array is indexed by lbx proxy index */ + LbxClientPtr lbxClients[MAX_LBX_CLIENTS]; + LbxClientPtr curRecv, + curDix; + int fd; + int pid; /* proxy ID */ + int uid; + int numClients; + int maxIndex; + Bool aborted; + int grabClient; + pointer compHandle; + Bool dosquishing; + Bool useTags; + LBXDeltasRec indeltas; + LBXDeltasRec outdeltas; + char *iDeltaBuf; + char *replyBuf; + char *oDeltaBuf; + OSBufPtr ofirst; + OSBufPtr olast; + CARD32 cur_send_id; + + LbxStreamOpts streamOpts; + + int numBitmapCompMethods; + unsigned char *bitmapCompMethods; /* array of indices */ + int numPixmapCompMethods; + unsigned char *pixmapCompMethods; /* array of indices */ + int **pixmapCompDepths; /* depths supported from each method */ + + struct _ColormapRec *grabbedCmaps; /* chained via lbx private */ + int motion_allowed_events; + lbxMotionCache motionCache; +} LbxProxyRec; + +/* This array is indexed by server client index, not lbx proxy index */ + +extern LbxClientPtr lbxClients[MAXCLIENTS]; + +#define LbxClient(client) (lbxClients[(client)->index]) +#define LbxProxy(client) (LbxClient(client)->proxy) +#define LbxMaybeProxy(client) (LbxClient(client) ? LbxProxy(client) : 0) +#define LbxProxyID(client) (LbxProxy(client)->pid) +#define LbxProxyClient(proxy) ((proxy)->lbxClients[0]->client) + +extern int LbxEventCode; + + +/* os/connection.c */ +extern ClientPtr AllocLbxClientConnection ( ClientPtr client, + LbxProxyPtr proxy ); +extern void LbxProxyConnection ( ClientPtr client, LbxProxyPtr proxy ); + +/* os/libxio.c */ +extern int UncompressedWriteToClient ( ClientPtr who, int count, char *buf ); +extern void LbxForceOutput ( LbxProxyPtr proxy ); +extern void SwitchClientInput ( ClientPtr client, Bool pending ); +extern int PrepareLargeReqBuffer ( ClientPtr client ); +extern Bool AppendFakeRequest ( ClientPtr client, char *data, int count ); +extern void LbxFreeOsBuffers ( LbxProxyPtr proxy ); +extern Bool AllocateLargeReqBuffer ( ClientPtr client, int size ); +extern Bool AddToLargeReqBuffer ( ClientPtr client, char *data, int size ); +extern void LbxPrimeInput ( ClientPtr client, LbxProxyPtr proxy ); + +/* lbxcmap.c */ +extern int LbxCmapInit ( void ); +extern Bool LbxCheckColorRequest ( ClientPtr client, ColormapPtr pmap, + xReq *req ); +extern int LbxCheckCmapGrabbed ( ColormapPtr pmap ); +extern void LbxDisableSmartGrab ( ColormapPtr pmap ); +extern void LbxBeginFreeCellsEvent ( ColormapPtr pmap ); +extern void LbxAddFreeCellToEvent ( ColormapPtr pmap, Pixel pixel ); +extern void LbxEndFreeCellsEvent ( ColormapPtr pmap ); +extern void LbxSortPixelList ( Pixel *pixels, int count ); +extern int ProcLbxGrabCmap ( ClientPtr client ); +extern void LbxReleaseCmap ( ColormapPtr pmap, Bool smart ); +extern int ProcLbxReleaseCmap ( ClientPtr client ); +extern int ProcLbxAllocColor ( ClientPtr client ); +extern int ProcLbxIncrementPixel ( ClientPtr client ); + +/* lbxdix.h */ +extern void LbxDixInit ( void ); +extern void LbxResetTags ( void ); +extern int LbxSendConnSetup ( ClientPtr client, char *reason ); +extern int LbxGetModifierMapping ( ClientPtr client ); +extern int LbxGetKeyboardMapping ( ClientPtr client ); +extern int LbxQueryFont ( ClientPtr client ); +extern int LbxTagData ( ClientPtr client, XID tag, unsigned long len, + pointer data ); +extern int LbxInvalidateTag ( ClientPtr client, XID tag ); +extern void LbxAllowMotion ( ClientPtr client, int num ); +extern void LbxFlushModifierMapTag ( void ); +extern void LbxFlushKeyboardMapTag ( void ); +extern void LbxFreeFontTag ( FontPtr pfont ); +extern void LbxSendInvalidateTag ( ClientPtr client, XID tag, int tagtype ); +extern Bool LbxFlushQTag ( XID tag ); +extern void ProcessQTagZombies ( void ); +extern void LbxQueryTagData ( ClientPtr client, int owner_pid, XID tag, + int tagtype ); + +/* lbxexts.c */ +extern Bool LbxAddExtension ( char *name, int opcode, int ev_base, + int err_base ); +extern Bool LbxAddExtensionAlias ( int idx, char *alias ); +extern void LbxDeclareExtensionSecurity ( char *extname, Bool secure ); +extern Bool LbxRegisterExtensionGenerationMasks ( int idx, int num_reqs, + char *rep_mask, + char *ev_mask ); +extern int LbxQueryExtension ( ClientPtr client, char *ename, int nlen ); +extern void LbxCloseDownExtensions ( void ); +extern void LbxSetReqMask ( CARD8 *mask, int req, Bool on ); + +/* lbxgfx.c */ +extern int LbxDecodePoly( ClientPtr client, CARD8 xreqtype, + int (*decode_rtn)(char *, char *, short *) ); +extern int LbxDecodeFillPoly ( ClientPtr client ); +extern int LbxDecodeCopyArea ( ClientPtr client ); +extern int LbxDecodeCopyPlane ( ClientPtr client ); +extern int LbxDecodePolyText ( ClientPtr client ); +extern int LbxDecodeImageText ( ClientPtr client ); +extern int LbxDecodePutImage ( ClientPtr client ); +extern int LbxDecodeGetImage ( ClientPtr client ); +extern int LbxDecodePoints ( char *in, char *inend, short *out ); +extern int LbxDecodeSegment ( char *in, char *inend, short *out ); +extern int LbxDecodeRectangle ( char *in, char *inend, short *out ); +extern int LbxDecodeArc ( char *in, char *inend, short *out ); + +/* lbxmain.c */ +extern LbxProxyPtr LbxPidToProxy ( int pid ); +extern void LbxReencodeOutput ( ClientPtr client, char *pbuf, int *pcount, + char *cbuf, int *ccount ); +extern void LbxExtensionInit ( void ); +extern void LbxCloseClient ( ClientPtr client ); +extern void LbxSetForBlock ( LbxClientPtr lbxClient ); +extern int ProcLbxDispatch ( ClientPtr client ); +extern int ProcLbxSwitch ( ClientPtr client ); +extern int ProcLbxQueryVersion ( ClientPtr client ); +extern int ProcLbxStartProxy ( ClientPtr client ); +extern int ProcLbxStopProxy ( ClientPtr client ); +extern int ProcLbxBeginLargeRequest ( ClientPtr client ); +extern int ProcLbxLargeRequestData ( ClientPtr client ); +extern int ProcLbxEndLargeRequest ( ClientPtr client ); +extern int ProcLbxInternAtoms ( ClientPtr client ); +extern int ProcLbxGetWinAttrAndGeom ( ClientPtr client ); +extern int ProcLbxNewClient ( ClientPtr client ); +extern int ProcLbxEstablishConnection ( ClientPtr client ); +extern int ProcLbxCloseClient ( ClientPtr client ); +extern int ProcLbxModifySequence ( ClientPtr client ); +extern int ProcLbxAllowMotion ( ClientPtr client ); +extern int ProcLbxGetModifierMapping ( ClientPtr client ); +extern int ProcLbxGetKeyboardMapping ( ClientPtr client ); +extern int ProcLbxQueryFont ( ClientPtr client ); +extern int ProcLbxChangeProperty ( ClientPtr client ); +extern int ProcLbxGetProperty ( ClientPtr client ); +extern int ProcLbxTagData ( ClientPtr client ); +extern int ProcLbxInvalidateTag ( ClientPtr client ); +extern int ProcLbxPolyPoint ( ClientPtr client ); +extern int ProcLbxPolyLine ( ClientPtr client ); +extern int ProcLbxPolySegment ( ClientPtr client ); +extern int ProcLbxPolyRectangle ( ClientPtr client ); +extern int ProcLbxPolyArc ( ClientPtr client ); +extern int ProcLbxFillPoly ( ClientPtr client ); +extern int ProcLbxPolyFillRectangle ( ClientPtr client ); +extern int ProcLbxPolyFillArc ( ClientPtr client ); +extern int ProcLbxCopyArea ( ClientPtr client ); +extern int ProcLbxCopyPlane ( ClientPtr client ); +extern int ProcLbxPolyText ( ClientPtr client ); +extern int ProcLbxImageText ( ClientPtr client ); +extern int ProcLbxQueryExtension ( ClientPtr client ); +extern int ProcLbxPutImage ( ClientPtr client ); +extern int ProcLbxGetImage ( ClientPtr client ); +extern int ProcLbxSync ( ClientPtr client ); + +/* lbxprop.c */ +extern int LbxChangeProperty ( ClientPtr client ); +extern int LbxGetProperty ( ClientPtr client ); +extern void LbxStallPropRequest ( ClientPtr client, PropertyPtr pProp ); +extern int LbxChangeWindowProperty ( ClientPtr client, WindowPtr pWin, + Atom property, Atom type, int format, + int mode, unsigned long len, + Bool have_data, pointer value, + Bool sendevent, XID *tag ); +/* lbxsquish.c */ +extern int LbxSquishEvent ( char *buf ); + +/* lbwswap.c */ +extern int SProcLbxDispatch( ClientPtr client ); +extern int SProcLbxSwitch ( ClientPtr client ); +extern int SProcLbxBeginLargeRequest ( ClientPtr client ); +extern int SProcLbxLargeRequestData ( ClientPtr client ); +extern int SProcLbxEndLargeRequest ( ClientPtr client ); +extern void LbxWriteSConnSetupPrefix ( ClientPtr pClient, + xLbxConnSetupPrefix *pcsp ); +extern void LbxSwapFontInfo ( xLbxFontInfo *pr, Bool compressed ); + +/* lbxzerorep.c */ +extern void ZeroReplyPadBytes ( char *buf, int reqType ); + +#endif /* _LBXSERVE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxsrvopts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxsrvopts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxsrvopts.h (revision 51223) @@ -0,0 +1,67 @@ +/* $Xorg: lbxsrvopts.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* + * Copyright 1994 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxsrvopts.h,v 1.2 2000/05/18 23:46:24 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBX_SRVOPTS_H_ +#define _LBX_SRVOPTS_H_ + +#include + +typedef struct _LbxNegOpts { + int nopts; + short proxyDeltaN; + short proxyDeltaMaxLen; + short serverDeltaN; + short serverDeltaMaxLen; + LbxStreamOpts streamOpts; + int numBitmapCompMethods; + unsigned char *bitmapCompMethods; /* array of indices */ + int numPixmapCompMethods; + unsigned char *pixmapCompMethods; /* array of indices */ + int **pixmapCompDepths; /* depths supported from each method */ + Bool squish; + Bool useTags; +} LbxNegOptsRec; + +typedef LbxNegOptsRec *LbxNegOptsPtr; + + +extern void LbxOptionInit ( LbxNegOptsPtr pno ); +extern int LbxOptionParse ( LbxNegOptsPtr pno, unsigned char *popt, + int optlen, unsigned char *preply ); +extern LbxBitmapCompMethod * +LbxSrvrLookupBitmapCompMethod ( LbxProxyPtr proxy, int methodOpCode ); +extern LbxPixmapCompMethod * +LbxSrvrLookupPixmapCompMethod ( LbxProxyPtr proxy, int methodOpCode ); +extern LbxBitmapCompMethod * +LbxSrvrFindPreferredBitmapCompMethod ( LbxProxyPtr proxy ); +extern LbxPixmapCompMethod * +LbxSrvrFindPreferredPixmapCompMethod ( LbxProxyPtr proxy, int format, int depth ); + + +#endif /* _LBX_SRVOPTS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxtags.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxtags.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lbxtags.h (revision 51223) @@ -0,0 +1,86 @@ +/* $Xorg: lbxtags.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * Copyright 1993 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxtags.h,v 1.3 2001/01/17 22:37:00 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXTAGS_H_ +#define _LBXTAGS_H_ +#include "lbxserve.h" + +#include "os.h" +#include "opaque.h" +#include "resource.h" +#include +#include + +typedef struct _tagdata { + XID tid; + short data_type; + unsigned char sent_to_proxy[(MAX_NUM_PROXIES + 7) / 8]; + int size; + pointer tdata; + XID *global; +} TagDataRec; + +typedef struct _tagdata *TagData; + +extern void TagInit ( void ); +extern XID TagNewTag ( void ); +extern void TagClearProxy ( XID tid, int pid ); +extern void TagMarkProxy ( XID tid, int pid ); +extern Bool TagProxyMarked ( XID tid, int pid ); +extern XID TagSaveTag ( int dtype, int size, pointer data, XID *global ); +extern void TagDeleteTag ( XID tid ); +extern TagData TagGetTag ( XID tid ); +extern void LbxFlushTags ( LbxProxyPtr proxy ); + +#endif /* _LBXTAGS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/listdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/listdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/listdev.h (revision 51223) @@ -0,0 +1,103 @@ +/* $XFree86: xc/programs/Xserver/Xi/listdev.h,v 3.1 1996/04/15 11:18:57 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef LISTDEV_H +#define LISTDEV_H 1 + +int +SProcXListInputDevices( + ClientPtr /* client */ + ); + +int +ProcXListInputDevices ( + ClientPtr /* client */ + ); + +void +SizeDeviceInfo ( + DeviceIntPtr /* d */, + int * /* namesize */, + int * /* size */ + ); + +void +ListDeviceInfo ( + ClientPtr /* client */, + DeviceIntPtr /* d */, + xDeviceInfoPtr /* dev */, + char ** /* devbuf */, + char ** /* classbuf */, + char ** /* namebuf */ + ); + +void +CopyDeviceName ( + char ** /* namebuf */, + char * /* name */ + ); + +void +CopySwapDevice ( + ClientPtr /* client */, + DeviceIntPtr /* d */, + int /* num_classes */, + char ** /* buf */ + ); + +void +CopySwapKeyClass ( + ClientPtr /* client */, + KeyClassPtr /* k */, + char ** /* buf */ + ); + +void +CopySwapButtonClass ( + ClientPtr /* client */, + ButtonClassPtr /* b */, + char ** /* buf */ + ); + +int +CopySwapValuatorClass ( + ClientPtr /* client */, + ValuatorClassPtr /* v */, + char ** /* buf */ + ); + +void +SRepXListInputDevices ( + ClientPtr /* client */, + int /* size */, + xListInputDevicesReply * /* rep */ + ); + +#endif /* LISTDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lk201kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lk201kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lk201kbd.h (revision 51223) @@ -0,0 +1,159 @@ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: lk201kbd.h,v 1.4 2001/02/09 02:04:45 xorgcvs Exp $ */ + +#define MIN_LK201_KEY 86 +#define MAX_LK201_KEY 251 +#define LK201_GLYPHS_PER_KEY 2 + +#define KEY_F1 86 +#define KEY_F2 87 +#define KEY_F3 88 +#define KEY_F4 89 +#define KEY_F5 90 +#define KEY_F6 100 +#define KEY_F7 101 +#define KEY_F8 102 +#define KEY_F9 103 +#define KEY_F10 104 +#define KEY_F11 113 +#define KEY_F12 114 +#define KEY_F13 115 +#define KEY_F14 116 +#define KEY_HELP 124 +#define KEY_MENU 125 +#define KEY_F17 128 +#define KEY_F18 129 +#define KEY_F19 130 +#define KEY_F20 131 +#define KEY_FIND 138 +#define KEY_INSERT_HERE 139 +#define KEY_REMOVE 140 +#define KEY_SELECT 141 +#define KEY_PREV_SCREEN 142 +#define KEY_NEXT_SCREEN 143 +#define KEY_KP_0 146 /* key pad */ +#define KEY_KP_PERIOD 148 /* key pad */ +#define KEY_KP_ENTER 149 /* key pad */ +#define KEY_KP_1 150 /* key pad */ +#define KEY_KP_2 151 /* key pad */ +#define KEY_KP_3 152 /* key pad */ +#define KEY_KP_4 153 /* key pad */ +#define KEY_KP_5 154 /* key pad */ +#define KEY_KP_6 155 /* key pad */ +#define KEY_KP_COMMA 156 /* key pad */ +#define KEY_KP_7 157 /* key pad */ +#define KEY_KP_8 158 /* key pad */ +#define KEY_KP_9 159 /* key pad */ +#define KEY_KP_HYPHEN 160 +#define KEY_KP_PF1 161 +#define KEY_KP_PF2 162 +#define KEY_KP_PF3 163 +#define KEY_KP_PF4 164 +#define KEY_LEFT 167 +#define KEY_RIGHT 168 +#define KEY_DOWN 169 +#define KEY_UP 170 +#define KEY_SHIFT 174 +#define KEY_CTRL 175 +#define KEY_LOCK 176 +#define KEY_COMPOSE 177 +#define KEY_APPLE 177 +#define KEY_META 177 +#define KEY_DELETE 188 +#define KEY_RETURN 189 +#define KEY_TAB 190 +#define KEY_TILDE 191 +#define KEY_TR_1 192 /* Top Row */ +#define KEY_Q 193 +#define KEY_A 194 +#define KEY_Z 195 +#define KEY_TR_2 197 +#define KEY_W 198 +#define KEY_S 199 +#define KEY_X 200 +#define KEY_LANGLE_RANGLE 201 /* xxx */ +#define KEY_TR_3 203 +#define KEY_E 204 +#define KEY_D 205 +#define KEY_C 206 +#define KEY_TR_4 208 +#define KEY_R 209 +#define KEY_F 210 +#define KEY_V 211 +#define KEY_SPACE 212 +#define KEY_TR_5 214 +#define KEY_T 215 +#define KEY_G 216 +#define KEY_B 217 +#define KEY_TR_6 219 +#define KEY_Y 220 +#define KEY_H 221 +#define KEY_N 222 +#define KEY_TR_7 224 +#define KEY_U 225 +#define KEY_J 226 +#define KEY_M 227 +#define KEY_TR_8 229 +#define KEY_I 230 +#define KEY_K 231 +#define KEY_COMMA 232 /* xxx */ +#define KEY_TR_9 234 +#define KEY_O 235 +#define KEY_L 236 +#define KEY_PERIOD 237 /* xxx */ +#define KEY_TR_0 239 +#define KEY_P 240 +#define KEY_SEMICOLON 242 /* xxx */ +#define KEY_QMARK 243 +#define KEY_PLUS 245 /* xxx */ +#define KEY_RBRACE 246 +#define KEY_VBAR 247 /* xxx */ +#define KEY_UBAR 249 /* xxx */ +#define KEY_LBRACE 250 +#define KEY_QUOTE 251 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-keyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-keyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-keyboard.h (revision 51223) @@ -0,0 +1,64 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux keyboard driver. \see lnx-keyboard.c */ + +#ifndef _LNX_KEYBOARD_H_ +#define _LNX_KEYBOARD_H_ + +extern pointer kbdLinuxCreatePrivate(DeviceIntPtr pKeyboard); +extern void kbdLinuxDestroyPrivate(pointer private); + +extern void kbdLinuxInit(DevicePtr pDev); +extern void kbdLinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int kbdLinuxOn(DevicePtr pDev); +extern void kbdLinuxOff(DevicePtr pDev); + +extern void kbdLinuxVTPreSwitch(pointer p); +extern void kbdLinuxVTPostSwitch(pointer p); +extern int kbdLinuxVTSwitch(pointer p, int vt, + dmxVTSwitchReturnProcPtr switch_return, + pointer switch_return_data); + +extern void kbdLinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); + +extern void kbdLinuxCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +extern void kbdLinuxBell(DevicePtr pDev, int percent, + int volume, int pitch, int duration); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ms.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ms.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ms.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux MS mouse driver. \see lnx-ms.c */ + +#ifndef _LNX_MS_H_ +#define _LNX_MS_H_ + +extern pointer msLinuxCreatePrivate(DeviceIntPtr pMouse); +extern void msLinuxDestroyPrivate(pointer priv); +extern void msLinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void msLinuxInit(DevicePtr pDev); +extern void msLinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int msLinuxOn(DevicePtr pDev); +extern void msLinuxOff(DevicePtr pDev); +extern void msLinuxCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern void msLinuxVTPreSwitch(pointer p); +extern void msLinuxVTPostSwitch(pointer p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ps2.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ps2.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx-ps2.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux PS/2 mouse driver. \see lnx-ps2.c */ + +#ifndef _LNX_PS2_H_ +#define _LNX_PS2_H_ + +extern pointer ps2LinuxCreatePrivate(DeviceIntPtr pMouse); +extern void ps2LinuxDestroyPrivate(pointer priv); +extern void ps2LinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void ps2LinuxInit(DevicePtr pDev); +extern void ps2LinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int ps2LinuxOn(DevicePtr pDev); +extern void ps2LinuxOff(DevicePtr pDev); +extern void ps2LinuxCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern void ps2LinuxVTPreSwitch(pointer p); +extern void ps2LinuxVTPostSwitch(pointer p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx.h (revision 51223) @@ -0,0 +1,55 @@ +/* $XFree86: Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef LNX_H_ +# ifdef __alpha__ +extern unsigned long _bus_base __P ((void)) __attribute__ ((const)); +extern unsigned long _bus_base_sparse __P ((void)) __attribute__ ((const)); +extern int iopl __P ((int __level)); + +/* new pciconfig_iobase syscall added in 2.2.15 and 2.3.99 */ +# include +# include +extern long (*_iobase)(unsigned, int, int, int); + +/* + * _iobase deals with the case the __NR_pciconfig_iobase is either undefined + * or unsupported by the kernel, but we need to make sure that the `which' + * argument symbols are defined. + */ +# ifndef IOBASE_HOSE +# define IOBASE_HOSE 0 +# endif +# ifndef IOBASE_SPARSE_MEM +# define IOBASE_SPARSE_MEM 1 +# endif +# ifndef IOBASE_DENSE_MEM +# define IOBASE_DENSE_MEM 2 +# endif +# ifndef IOBASE_SPARSE_IO +# define IOBASE_SPARSE_IO 3 +# endif +# ifndef IOBASE_DENSE_IO +# define IOBASE_DENSE_IO 4 +# endif +# ifndef IOBASE_ROOT_BUS +# define IOBASE_ROOT_BUS 5 +# endif +# ifndef IOBASE_FROM_HOSE +# define IOBASE_FROM_HOSE 0x10000 +# endif +# endif /* __alpha__ */ + +# if defined(DO_OS_FONTRESTORE) +Bool lnx_savefont(void); +Bool lnx_restorefont(void); +Bool lnx_switchaway(void); +void lnx_freefontdata(void); +# endif + +#define LNX_H_ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/lnx_kbd.h (revision 51223) @@ -0,0 +1,5 @@ +/* $XFree86$ */ + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loader.h (revision 51223) @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/loader.h,v 1.6 2001/07/07 01:43:58 paulo Exp $ + */ + +#ifdef USE_MODULES +#ifndef LOADER_PRIVATE +#include "config.h" +#include "stubs.h" + +#else + +#ifndef XFree86LOADER +#define XFree86LOADER /* not really */ +#endif +#define IN_LOADER + +#include "xf86.h" +#include "xf86str.h" +#include "xf86Opt.h" +#include "xf86Module.h" + +#ifndef XINPUT +#define XINPUT +#endif +#include "xf86Xinput.h" + +#include +#include "loaderProcs.h" + +#include +#include + +void LoaderDefaultFunc(void); +#endif + +#ifndef _xf86cfg_loader_h +#define _xf86cfg_loader_h + +void xf86cfgLoaderInit(void); +void xf86cfgLoaderInitList(int); +void xf86cfgLoaderFreeList(void); +int xf86cfgCheckModule(void); + +#ifndef LOADER_PRIVATE +/* common/xf86Opt.h */ +typedef struct { + double freq; + int units; +} OptFrequency; + +typedef union { + unsigned long num; + char * str; + double realnum; + Bool xbool; + OptFrequency freq; +} ValueUnion; + +typedef enum { + OPTV_NONE = 0, + OPTV_INTEGER, + OPTV_STRING, /* a non-empty string */ + OPTV_ANYSTR, /* Any string, including an empty one */ + OPTV_REAL, + OPTV_BOOLEAN, + OPTV_FREQ +} OptionValueType; + +typedef enum { + OPTUNITS_HZ = 1, + OPTUNITS_KHZ, + OPTUNITS_MHZ +} OptFreqUnits; + +typedef struct { + int token; + const char* name; + OptionValueType type; + ValueUnion value; + Bool found; +} OptionInfoRec, *OptionInfoPtr; + +/* fontmod.h */ +typedef void (*InitFont)(void); + +typedef struct { + InitFont initFunc; + char * name; + void *module; +} FontModule; + +extern FontModule *FontModuleList; + +typedef struct { + int token; /* id of the token */ + const char * name; /* token name */ +} SymTabRec, *SymTabPtr; +#endif /* !LOADER_PRIVATE */ + +typedef enum { + NullModule = 0, + VideoModule, + InputModule, + GenericModule, + FontRendererModule +} ModuleType; + +typedef struct _xf86cfgModuleOptions { + char *name; + ModuleType type; + OptionInfoPtr option; + int vendor; + SymTabPtr chipsets; + struct _xf86cfgModuleOptions *next; +} xf86cfgModuleOptions; + +extern xf86cfgModuleOptions *module_options; + +/* When adding a new code to the LEGEND, also update checkerLegend + * in loader.c + */ +extern char **checkerLegend; +extern int *checkerErrors; +#define CHECKER_OPTIONS_FILE_MISSING 1 +#define CHECKER_OPTION_DESCRIPTION_MISSING 2 +#define CHECKER_LOAD_FAILED 3 +#define CHECKER_RECOGNIZED_AS 4 +#define CHECKER_NO_OPTIONS_AVAILABLE 5 +#define CHECKER_NO_VENDOR_CHIPSET 6 +#define CHECKER_CANNOT_VERIFY_CHIPSET 7 +#define CHECKER_OPTION_UNUSED 8 +#define CHECKER_NOMATCH_CHIPSET_STRINGS 9 +#define CHECKER_CHIPSET_NOT_LISTED 10 +#define CHECKER_CHIPSET_NOT_SUPPORTED 11 +#define CHECKER_CHIPSET_NO_VENDOR 12 +#define CHECKER_NO_CHIPSETS 13 +#define CHECKER_FILE_MODULE_NAME_MISMATCH 14 + +#define CHECKER_LAST_MESSAGE 14 + +extern void CheckMsg(int, char*, ...); + +#ifndef LOADER_PRIVATE +int LoaderInitializeOptions(void); +#endif +#endif /* USE_MODULES */ + +#endif /* _xf86cfg_loader_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loaderProcs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loaderProcs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/loaderProcs.h (revision 51223) @@ -0,0 +1,123 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/loaderProcs.h,v 1.21 2003/10/15 16:29:04 dawes Exp $ */ + +/* + * + * Copyright 1995-1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _LOADERPROCS_H +#define _LOADERPROCS_H + +#define IN_LOADER +#include "xf86Module.h" +#include + +typedef struct module_desc { + struct module_desc *child; + struct module_desc *sib; + struct module_desc *parent; + struct module_desc *demand_next; + char *name; + char *filename; + char *identifier; + XID client_id; + int in_use; + int handle; + ModuleSetupProc SetupProc; + ModuleTearDownProc TearDownProc; + void *TearDownData; /* returned from SetupProc */ + const char *path; + const XF86ModuleVersionInfo *VersionInfo; +} ModuleDesc, *ModuleDescPtr; + +/* + * Extenal API for the loader + */ + +void LoaderInit(void); + +ModuleDescPtr LoadDriver(const char *, const char *, int, pointer, int *, + int *); +ModuleDescPtr LoadModule(const char *, const char *, const char **, + const char **, pointer, const XF86ModReqInfo *, + int *, int *); +ModuleDescPtr LoadSubModule(ModuleDescPtr, const char *, + const char **, const char **, pointer, + const XF86ModReqInfo *, int *, int *); +ModuleDescPtr DuplicateModule(ModuleDescPtr mod, ModuleDescPtr parent); +void LoadFont(FontModule *); +void UnloadModule(ModuleDescPtr); +void UnloadSubModule(ModuleDescPtr); +void UnloadDriver(ModuleDescPtr); +void FreeModuleDesc(ModuleDescPtr mod); +ModuleDescPtr NewModuleDesc(const char *); +ModuleDescPtr AddSibling(ModuleDescPtr head, ModuleDescPtr new); +void LoaderSetPath(const char *path); +void LoaderSortExtensions(void); + +void LoaderVReqSymLists(const char **, va_list args); +void LoaderVReqSymbols(const char *, va_list args); +void LoaderVRefSymLists(const char **, va_list args); +void LoaderVRefSymbols(const char *, va_list args); + +void LoaderShowStack(void); +void *LoaderSymbolHandle(const char *, int); +int LoaderUnload(int); +unsigned long LoaderGetModuleVersion(ModuleDescPtr mod); + +void LoaderResetOptions(void); +void LoaderSetOptions(unsigned long); +void LoaderClearOptions(unsigned long); + +/* Options for LoaderSetOptions */ +#define LDR_OPT_ABI_MISMATCH_NONFATAL 0x0001 + +#endif /* _LOADERPROCS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/maskbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/maskbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/maskbits.h (revision 51223) @@ -0,0 +1,691 @@ +/* $XFree86: xc/programs/Xserver/mfb/maskbits.h,v 3.8tsi Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.1, 1/24/89 */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: maskbits.h,v 1.3 2000/08/17 19:53:34 cpqbld Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include +#include "servermd.h" + + +/* the following notes use the following conventions: +SCREEN LEFT SCREEN RIGHT +in this file and maskbits.c, left and right refer to screen coordinates, +NOT bit numbering in registers. + +starttab[n] + bits[0,n-1] = 0 bits[n,PLST] = 1 +endtab[n] = + bits[0,n-1] = 1 bits[n,PLST] = 0 + +startpartial[], endpartial[] + these are used as accelerators for doing putbits and masking out +bits that are all contained between longword boudaries. the extra +256 bytes of data seems a small price to pay -- code is smaller, +and narrow things (e.g. window borders) go faster. + +the names may seem misleading; they are derived not from which end +of the word the bits are turned on, but at which end of a scanline +the table tends to be used. + +look at the tables and macros to understand boundary conditions. +(careful readers will note that starttab[n] = ~endtab[n] for n != 0) + +----------------------------------------------------------------------- +these two macros depend on the screen's bit ordering. +in both of them x is a screen position. they are used to +combine bits collected from multiple longwords into a +single destination longword, and to unpack a single +source longword into multiple destinations. + +SCRLEFT(dst, x) + takes dst[x, PPW] and moves them to dst[0, PPW-x] + the contents of the rest of dst are 0. + this is a right shift on LSBFirst (forward-thinking) + machines like the VAX, and left shift on MSBFirst + (backwards) machines like the 680x0 and pc/rt. + +SCRRIGHT(dst, x) + takes dst[0,x] and moves them to dst[PPW-x, PPW] + the contents of the rest of dst are 0. + this is a left shift on LSBFirst, right shift + on MSBFirst. + + +the remaining macros are cpu-independent; all bit order dependencies +are built into the tables and the two macros above. + +maskbits(x, w, startmask, endmask, nlw) + for a span of width w starting at position x, returns +a mask for ragged bits at start, mask for ragged bits at end, +and the number of whole longwords between the ends. + +maskpartialbits(x, w, mask) + works like maskbits(), except all the bits are in the + same longword (i.e. (x&PIM + w) <= PPW) + +maskPPWbits(x, w, startmask, endmask, nlw) + as maskbits, but does not calculate nlw. it is used by + mfbGlyphBlt to put down glyphs <= PPW bits wide. + +------------------------------------------------------------------- + +NOTE + any pointers passed to the following 4 macros are + guranteed to be PPW-bit aligned. + The only non-PPW-bit-aligned references ever made are + to font glyphs, and those are made with getleftbits() + and getshiftedleftbits (qq.v.) + + For 64-bit server, it is assumed that we will never have font padding + of more than 4 bytes. The code uses int's to access the fonts + intead of longs. + +getbits(psrc, x, w, dst) + starting at position x in psrc (x < PPW), collect w + bits and put them in the screen left portion of dst. + psrc is a longword pointer. this may span longword boundaries. + it special-cases fetching all w bits from one longword. + + +--------+--------+ +--------+ + | | m |n| | ==> | m |n| | + +--------+--------+ +--------+ + x x+w 0 w + psrc psrc+1 dst + m = PPW - x + n = w - m + + implementation: + get m bits, move to screen-left of dst, zeroing rest of dst; + get n bits from next word, move screen-right by m, zeroing + lower m bits of word. + OR the two things together. + +putbits(src, x, w, pdst) + starting at position x in pdst, put down the screen-leftmost + w bits of src. pdst is a longword pointer. this may + span longword boundaries. + it special-cases putting all w bits into the same longword. + + +--------+ +--------+--------+ + | m |n| | ==> | | m |n| | + +--------+ +--------+--------+ + 0 w x x+w + dst pdst pdst+1 + m = PPW - x + n = w - m + + implementation: + get m bits, shift screen-right by x, zero screen-leftmost x + bits; zero rightmost m bits of *pdst and OR in stuff + from before the semicolon. + shift src screen-left by m, zero bits n-PPW; + zero leftmost n bits of *(pdst+1) and OR in the + stuff from before the semicolon. + +putbitsrop(src, x, w, pdst, ROP) + like putbits but calls DoRop with the rasterop ROP (see mfb.h for + DoRop) + +putbitsrrop(src, x, w, pdst, ROP) + like putbits but calls DoRRop with the reduced rasterop ROP + (see mfb.h for DoRRop) + +----------------------------------------------------------------------- + The two macros below are used only for getting bits from glyphs +in fonts, and glyphs in fonts are gotten only with the following two +mcros. + You should tune these macros toyour font format and cpu +byte ordering. + +NOTE +getleftbits(psrc, w, dst) + get the leftmost w (w<=32) bits from *psrc and put them + in dst. this is used by the mfbGlyphBlt code for glyphs + <=PPW bits wide. + psrc is declared (unsigned char *) + + psrc is NOT guaranteed to be PPW-bit aligned. on many + machines this will cause problems, so there are several + versions of this macro. + + this macro is called ONLY for getting bits from font glyphs, + and depends on the server-natural font padding. + + for blazing text performance, you want this macro + to touch memory as infrequently as possible (e.g. + fetch longwords) and as efficiently as possible + (e.g. don't fetch misaligned longwords) + +getshiftedleftbits(psrc, offset, w, dst) + used by the font code; like getleftbits, but shifts the + bits SCRLEFT by offset. + this is implemented portably, calling getleftbits() + and SCRLEFT(). + psrc is declared (unsigned char *). +*/ + +/* to match CFB and allow algorithm sharing ... + * name mfb32 mfb64 explanation + * ---- ------ ----- ----------- + * PGSZ 32 64 pixel group size (in bits; same as PPW for mfb) + * PGSZB 4 8 pixel group size (in bytes) + * PPW 32 64 pixels per word (pixels per pixel group) + * PLST 31 63 index of last pixel in a word (should be PPW-1) + * PIM 0x1f 0x3f pixel index mask (index within a pixel group) + * PWSH 5 6 pixel-to-word shift (should be log2(PPW)) + * + * The MFB_ versions are here so that cfb can include maskbits.h to get + * the bitmap constants without conflicting with its own P* constants. + * + * Keith Packard (keithp@suse.com): + * Note mfb64 is no longer supported; it requires DIX support + * for realigning images which costs too much + */ + +/* warning: PixelType definition duplicated in mfb.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ +#ifndef MfbBits +#define MfbBits CARD32 +#endif + +#define MFB_PGSZB 4 +#define MFB_PPW (MFB_PGSZB<<3) /* assuming 8 bits per byte */ +#define MFB_PGSZ MFB_PPW +#define MFB_PLST (MFB_PPW-1) +#define MFB_PIM MFB_PLST + +/* set PWSH = log2(PPW) using brute force */ + +#if MFB_PPW == 32 +#define MFB_PWSH 5 +#endif /* MFB_PPW == 32 */ + +/* XXX don't use these five */ +extern PixelType starttab[]; +extern PixelType endtab[]; +extern PixelType partmasks[MFB_PPW][MFB_PPW]; +extern PixelType rmask[]; +extern PixelType mask[]; +/* XXX use these five */ +extern PixelType mfbGetstarttab(int); +extern PixelType mfbGetendtab(int); +extern PixelType mfbGetpartmasks(int, int); +extern PixelType mfbGetrmask(int); +extern PixelType mfbGetmask(int); + +#ifndef MFB_CONSTS_ONLY + +#define PGSZB MFB_PGSZB +#define PPW MFB_PPW +#define PGSZ MFB_PGSZ +#define PLST MFB_PLST +#define PIM MFB_PIM +#define PWSH MFB_PWSH + +#define BitLeft(b,s) SCRLEFT(b,s) +#define BitRight(b,s) SCRRIGHT(b,s) + +#ifdef XFree86Server +#define LONG2CHARSSAMEORDER(x) ((MfbBits)(x)) +#define LONG2CHARSDIFFORDER( x ) ( ( ( ( x ) & (MfbBits)0x000000FF ) << 0x18 ) \ + | ( ( ( x ) & (MfbBits)0x0000FF00 ) << 0x08 ) \ + | ( ( ( x ) & (MfbBits)0x00FF0000 ) >> 0x08 ) \ + | ( ( ( x ) & (MfbBits)0xFF000000 ) >> 0x18 ) ) +#endif /* XFree86Server */ + +#if (BITMAP_BIT_ORDER == IMAGE_BYTE_ORDER) +#define LONG2CHARS(x) ((MfbBits)(x)) +#else +/* + * the unsigned case below is for compilers like + * the Danbury C and i386cc + */ +#define LONG2CHARS( x ) ( ( ( ( x ) & (MfbBits)0x000000FF ) << 0x18 ) \ + | ( ( ( x ) & (MfbBits)0x0000FF00 ) << 0x08 ) \ + | ( ( ( x ) & (MfbBits)0x00FF0000 ) >> 0x08 ) \ + | ( ( ( x ) & (MfbBits)0xFF000000 ) >> 0x18 ) ) +#endif /* BITMAP_BIT_ORDER */ + +#ifdef STRICT_ANSI_SHIFT +#define SHL(x,y) ((y) >= PPW ? 0 : LONG2CHARS(LONG2CHARS(x) << (y))) +#define SHR(x,y) ((y) >= PPW ? 0 : LONG2CHARS(LONG2CHARS(x) >> (y))) +#else +#define SHL(x,y) LONG2CHARS(LONG2CHARS(x) << (y)) +#define SHR(x,y) LONG2CHARS(LONG2CHARS(x) >> (y)) +#endif + +#if (BITMAP_BIT_ORDER == MSBFirst) /* pc/rt, 680x0 */ +#define SCRLEFT(lw, n) SHL((PixelType)(lw),(n)) +#define SCRRIGHT(lw, n) SHR((PixelType)(lw),(n)) +#else /* vax, intel */ +#define SCRLEFT(lw, n) SHR((PixelType)(lw),(n)) +#define SCRRIGHT(lw, n) SHL((PixelType)(lw),(n)) +#endif + +#define DoRRop(alu, src, dst) \ +(((alu) == RROP_BLACK) ? ((dst) & ~(src)) : \ + ((alu) == RROP_WHITE) ? ((dst) | (src)) : \ + ((alu) == RROP_INVERT) ? ((dst) ^ (src)) : \ + (dst)) + +/* A generalized form of a x4 Duff's Device */ +#define Duff(counter, block) { \ + while (counter >= 4) {\ + { block; } \ + { block; } \ + { block; } \ + { block; } \ + counter -= 4; \ + } \ + switch (counter & 3) { \ + case 3: { block; } \ + case 2: { block; } \ + case 1: { block; } \ + case 0: \ + counter = 0; \ + } \ +} + +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = mfbGetstarttab((x) & PIM); \ + endmask = mfbGetendtab(((x)+(w)) & PIM); \ + if (startmask) \ + nlw = (((w) - (PPW - ((x) & PIM))) >> PWSH); \ + else \ + nlw = (w) >> PWSH; + +#define maskpartialbits(x, w, mask) \ + mask = mfbGetpartmasks((x) & PIM, (w) & PIM); + +#define maskPPWbits(x, w, startmask, endmask) \ + startmask = mfbGetstarttab((x) & PIM); \ + endmask = mfbGetendtab(((x)+(w)) & PIM); + +#ifdef __GNUC__ /* XXX don't want for Alpha? */ +#ifdef vax +#define FASTGETBITS(psrc,x,w,dst) \ + __asm ("extzv %1,%2,%3,%0" \ + : "=g" (dst) \ + : "g" (x), "g" (w), "m" (*(char *)(psrc))) +#define getbits(psrc,x,w,dst) FASTGETBITS(psrc,x,w,dst) + +#define FASTPUTBITS(src, x, w, pdst) \ + __asm ("insv %3,%1,%2,%0" \ + : "=m" (*(char *)(pdst)) \ + : "g" (x), "g" (w), "g" (src)) +#define putbits(src, x, w, pdst) FASTPUTBITS(src, x, w, pdst) +#endif /* vax */ +#ifdef mc68020 +#define FASTGETBITS(psrc, x, w, dst) \ + __asm ("bfextu %3{%1:%2},%0" \ + : "=d" (dst) : "di" (x), "di" (w), "o" (*(char *)(psrc))) + +#define getbits(psrc,x,w,dst) \ +{ \ + FASTGETBITS(psrc, x, w, dst);\ + dst = SHL(dst,(32-(w))); \ +} + +#define FASTPUTBITS(src, x, w, pdst) \ + __asm ("bfins %3,%0{%1:%2}" \ + : "=o" (*(char *)(pdst)) \ + : "di" (x), "di" (w), "d" (src), "0" (*(char *) (pdst))) + +#define putbits(src, x, w, pdst) FASTPUTBITS(SHR((src),32-(w)), x, w, pdst) + +#endif /* mc68020 */ +#endif /* __GNUC__ */ + +/* The following flag is used to override a bugfix for sun 3/60+CG4 machines, + */ + +/* We don't need to be careful about this unless we're dealing with sun3's + * We will default its usage for those who do not know anything, but will + * override its effect if the machine doesn't look like a sun3 + */ +#if !defined(mc68020) || !defined(sun) +#define NO_3_60_CG4 +#endif + +/* This is gross. We want to #define u_putbits as something which can be used + * in the case of the 3/60+CG4, but if we use /bin/cc or are on another + * machine type, we want nothing to do with u_putbits. What a hastle. Here + * I used slo_putbits as something which either u_putbits or putbits could be + * defined as. + * + * putbits gets it iff it is not already defined with FASTPUTBITS above. + * u_putbits gets it if we have FASTPUTBITS (putbits) from above and have not + * overridden the NO_3_60_CG4 flag. + */ + +#define slo_putbits(src, x, w, pdst) \ +{ \ + register int n = (x)+(w)-PPW; \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | \ + (SCRRIGHT(src, x) & tmpmask); \ + } \ + else \ + { \ + register int d = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (SCRRIGHT((src), x)); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | \ + (SCRLEFT(src, d) & mfbGetendtab(n)); \ + } \ +} + +#if defined(putbits) && !defined(NO_3_60_CG4) +#define u_putbits(src, x, w, pdst) slo_putbits(src, x, w, pdst) +#else +#define u_putbits(src, x, w, pdst) putbits(src, x, w, pdst) +#endif + +#if !defined(putbits) +#define putbits(src, x, w, pdst) slo_putbits(src, x, w, pdst) +#endif + +/* Now if we have not gotten any really good bitfield macros, try some + * moderately fast macros. Alas, I don't know how to do asm instructions + * without gcc. + */ + +#ifndef getbits +#define getbits(psrc, x, w, dst) \ +{ \ + dst = SCRLEFT(*(psrc), (x)); \ + if ( ((x) + (w)) > PPW) \ + dst |= (SCRRIGHT(*((psrc)+1), PPW-(x))); \ +} +#endif + +/* We have to special-case putbitsrop because of 3/60+CG4 combos + */ + +#define u_putbitsrop(src, x, w, pdst, rop) \ +{\ + register PixelType t1, t2; \ + register int n = (x)+(w)-PPW; \ + \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ + } \ + else \ + { \ + int m = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (t2 & mfbGetstarttab(x)); \ + t1 = SCRLEFT((src), m); \ + DoRop(t2, rop, t1, (pdst)[1]); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | (t2 & mfbGetendtab(n)); \ + } \ +} + +/* If our getbits and putbits are FAST enough, + * do this brute force, it's faster + */ + +#if defined(FASTPUTBITS) && defined(FASTGETBITS) && defined(NO_3_60_CG4) +#if (BITMAP_BIT_ORDER == MSBFirst) +#define putbitsrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp, _tmp2; \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp2 = SCRRIGHT(src, PPW-(w)); \ + DoRop(_tmp, rop, _tmp2, _tmp) \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#define putbitsrrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp, _tmp2; \ + \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp2 = SCRRIGHT(src, PPW-(w)); \ + _tmp= DoRRop(rop, _tmp2, _tmp); \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#undef u_putbitsrop +#else +#define putbitsrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp; \ + FASTGETBITS(pdst, x, w, _tmp); \ + DoRop(_tmp, rop, src, _tmp) \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#define putbitsrrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp; \ + \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp= DoRRop(rop, src, _tmp); \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#undef u_putbitsrop +#endif +#endif + +#ifndef putbitsrop +#define putbitsrop(src, x, w, pdst, rop) u_putbitsrop(src, x, w, pdst, rop) +#endif + +#ifndef putbitsrrop +#define putbitsrrop(src, x, w, pdst, rop) \ +{\ + register PixelType t1, t2; \ + register int n = (x)+(w)-PPW; \ + \ + t1 = SCRRIGHT((src), (x)); \ + t2 = DoRRop(rop, t1, *(pdst)); \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ + } \ + else \ + { \ + int m = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (t2 & mfbGetstarttab(x)); \ + t1 = SCRLEFT((src), m); \ + t2 = DoRRop(rop, t1, (pdst)[1]); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | (t2 & mfbGetendtab(n)); \ + } \ +} +#endif + +#if GETLEFTBITS_ALIGNMENT == 1 +#define getleftbits(psrc, w, dst) dst = *((CARD32 *)(pointer) psrc) +#endif /* GETLEFTBITS_ALIGNMENT == 1 */ + +#if GETLEFTBITS_ALIGNMENT == 2 +#define getleftbits(psrc, w, dst) \ + { \ + if ( ((int)(psrc)) & 0x01 ) \ + getbits( ((CARD32 *)(((char *)(psrc))-1)), 8, (w), (dst) ); \ + else \ + getbits(psrc, 0, w, dst); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 2 */ + +#if GETLEFTBITS_ALIGNMENT == 4 +#define getleftbits(psrc, w, dst) \ + { \ + int off, off_b; \ + off_b = (off = ( ((int)(psrc)) & 0x03)) << 3; \ + getbits( \ + (CARD32 *)( ((char *)(psrc)) - off), \ + (off_b), (w), (dst) \ + ); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 4 */ + + +#define getshiftedleftbits(psrc, offset, w, dst) \ + getleftbits((psrc), (w), (dst)); \ + dst = SCRLEFT((dst), (offset)); + +/* FASTGETBITS and FASTPUTBITS are not necessarily correct implementations of + * getbits and putbits, but they work if used together. + * + * On a MSBFirst machine, a cpu bitfield extract instruction (like bfextu) + * could normally assign its result to a 32-bit word register in the screen + * right position. This saves canceling register shifts by not fighting the + * natural cpu byte order. + * + * Unfortunately, these fail on a 3/60+CG4 and cannot be used unmodified. Sigh. + */ +#if defined(FASTGETBITS) && defined(FASTPUTBITS) +#ifdef NO_3_60_CG4 +#define u_FASTPUT(aa, bb, cc, dd) FASTPUTBITS(aa, bb, cc, dd) +#else +#define u_FASTPUT(aa, bb, cc, dd) u_putbits(SCRLEFT(aa, PPW-(cc)), bb, cc, dd) +#endif + +#define getandputbits(psrc, srcbit, dstbit, width, pdst) \ +{ \ + register PixelType _tmpbits; \ + FASTGETBITS(psrc, srcbit, width, _tmpbits); \ + u_FASTPUT(_tmpbits, dstbit, width, pdst); \ +} + +#define getandputrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpsrc, _tmpdst; \ + FASTGETBITS(pdst, dstbit, width, _tmpdst); \ + FASTGETBITS(psrc, srcbit, width, _tmpsrc); \ + DoRop(_tmpdst, rop, _tmpsrc, _tmpdst); \ + u_FASTPUT(_tmpdst, dstbit, width, pdst); \ +} + +#define getandputrrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpsrc, _tmpdst; \ + FASTGETBITS(pdst, dstbit, width, _tmpdst); \ + FASTGETBITS(psrc, srcbit, width, _tmpsrc); \ + _tmpdst = DoRRop(rop, _tmpsrc, _tmpdst); \ + u_FASTPUT(_tmpdst, dstbit, width, pdst); \ +} + +#define getandputbits0(psrc, srcbit, width, pdst) \ + getandputbits(psrc, srcbit, 0, width, pdst) + +#define getandputrop0(psrc, srcbit, width, pdst, rop) \ + getandputrop(psrc, srcbit, 0, width, pdst, rop) + +#define getandputrrop0(psrc, srcbit, width, pdst, rop) \ + getandputrrop(psrc, srcbit, 0, width, pdst, rop) + + +#else /* Slow poke */ + +/* pairs of getbits/putbits happen frequently. Some of the code can + * be shared or avoided in a few specific instances. It gets us a + * small advantage, so we do it. The getandput...0 macros are the only ones + * which speed things here. The others are here for compatibility w/the above + * FAST ones + */ + +#define getandputbits(psrc, srcbit, dstbit, width, pdst) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits); \ + putbits(_tmpbits, dstbit, width, pdst); \ +} + +#define getandputrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits) \ + putbitsrop(_tmpbits, dstbit, width, pdst, rop) \ +} + +#define getandputrrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits) \ + putbitsrrop(_tmpbits, dstbit, width, pdst, rop) \ +} + + +#define getandputbits0(psrc, sbindex, width, pdst) \ +{ /* unroll the whole damn thing to see how it * behaves */ \ + register int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + + +#define getandputrop0(psrc, sbindex, width, pdst, rop) \ +{ \ + register int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + DoRop(_src, rop, _src, *(pdst)); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + +#define getandputrrop0(psrc, sbindex, width, pdst, rop) \ +{ \ + int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + _src = DoRRop(rop, _src, *(pdst)); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + +#endif /* FASTGETBITS && FASTPUTBITS */ + +#endif /* MFB_CONSTS_ONLY */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/memrange.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/memrange.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/memrange.h (revision 51223) @@ -0,0 +1,72 @@ +/* + * Memory range attribute operations, peformed on /dev/mem + * + * $FreeBSD: src/sys/sys/memrange.h,v 1.4 1999/12/29 04:24:44 peter Exp $ + */ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _MEMRANGE_H +#define _MEMRANGE_H + +/* Memory range attributes */ +#define MDF_UNCACHEABLE (1<<0) /* region not cached */ +#define MDF_WRITECOMBINE (1<<1) /* region supports "write combine" + * action */ +#define MDF_WRITETHROUGH (1<<2) /* write-through cached */ +#define MDF_WRITEBACK (1<<3) /* write-back cached */ +#define MDF_WRITEPROTECT (1<<4) /* read-only region */ +#define MDF_ATTRMASK (0x00ffffff) + +#define MDF_FIXBASE (1<<24) /* fixed base */ +#define MDF_FIXLEN (1<<25) /* fixed length */ +#define MDF_FIRMWARE (1<<26) /* set by firmware (XXX not useful?) */ +#define MDF_ACTIVE (1<<27) /* currently active */ +#define MDF_BOGUS (1<<28) /* we don't like it */ +#define MDF_FIXACTIVE (1<<29) /* can't be turned off */ +#define MDF_BUSY (1<<30) /* range is in use */ + +struct mem_range_desc { + u_int64_t mr_base; + u_int64_t mr_len; + int mr_flags; + char mr_owner[8]; +}; + +struct mem_range_op { + struct mem_range_desc *mo_desc; + int mo_arg[2]; +#define MEMRANGE_SET_UPDATE 0 +#define MEMRANGE_SET_REMOVE 1 + /* XXX want a flag that says "set and undo when I exit" */ +}; +#define MEMRANGE_GET _IOWR('m', 50, struct mem_range_op) +#define MEMRANGE_SET _IOW('m', 51, struct mem_range_op) + +#ifdef _KERNEL + +struct mem_range_softc; +struct mem_range_ops { + void (*init) __P((struct mem_range_softc * sc)); + int (*set) __P((struct mem_range_softc * sc, struct mem_range_desc * mrd, int *arg)); + void (*initAP) __P((struct mem_range_softc * sc)); +}; + +struct mem_range_softc { + struct mem_range_ops *mr_op; + int mr_cap; + int mr_ndesc; + struct mem_range_desc *mr_desc; +}; + +extern struct mem_range_softc mem_range_softc; + +extern int mem_range_attr_get __P((struct mem_range_desc * mrd, int *arg)); +extern int mem_range_attr_set __P((struct mem_range_desc * mrd, int *arg)); +extern void mem_range_AP_init __P((void)); +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mergerop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mergerop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mergerop.h (revision 51223) @@ -0,0 +1,400 @@ +/* + * $Xorg: mergerop.h,v 1.4 2001/02/09 02:05:18 xorgcvs Exp $ + * +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ +/* $XFree86: xc/programs/Xserver/mfb/mergerop.h,v 3.13 2001/10/28 03:34:13 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _MERGEROP_H_ +#define _MERGEROP_H_ + +#ifndef GXcopy +#include +#endif + +typedef struct _mergeRopBits { + MfbBits ca1, cx1, ca2, cx2; +} mergeRopRec, *mergeRopPtr; + +extern mergeRopRec mergeRopBits[16]; +extern mergeRopPtr mergeGetRopBits(int i); + +#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ) /* cfb */ +#define DeclareMergeRop() MfbBits _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0; +#define DeclarePrebuiltMergeRop() MfbBits _cca, _ccx; +#if PSZ == 24 /* both for PGSZ == 32 and 64 */ +#define DeclareMergeRop24() \ + MfbBits _ca1u[4], _cx1u[4], _ca2u[4], _cx2u[4]; + /* int _unrollidx[3]={0,0,1,2};*/ +#define DeclarePrebuiltMergeRop24() MfbBits _ccau[4], _ccxu[4]; +#endif /* PSZ == 24 */ +#else /* mfb */ +#define DeclareMergeRop() MfbBits _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0; +#define DeclarePrebuiltMergeRop() MfbBits _cca, _ccx; +#endif + +#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ) /* cfb */ +#define InitializeMergeRop(alu,pm) {\ + MfbBits _pm; \ + mergeRopPtr _bits; \ + _pm = PFILL(pm); \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1 & _pm; \ + _cx1 = _bits->cx1 | ~_pm; \ + _ca2 = _bits->ca2 & _pm; \ + _cx2 = _bits->cx2 & _pm; \ +} +#if PSZ == 24 +#if (BITMAP_BIT_ORDER == MSBFirst) +#define InitializeMergeRop24(alu,pm) {\ + register int i; \ + register MfbBits _pm = (pm) & 0xFFFFFF; \ + mergeRopPtr _bits = mergeGetRopBits(alu); \ + MfbBits _bits_ca1 = _bits->ca1; \ + MfbBits _bits_cx1 = _bits->cx1; \ + MfbBits _bits_ca2 = _bits->ca2; \ + MfbBits _bits_cx2 = _bits->cx2; \ + _pm = (_pm << 8) | (_pm >> 16); \ + for(i = 0; i < 4; i++){ \ + _ca1u[i] = _bits_ca1 & _pm; \ + _cx1u[i] = _bits_cx1 | ~_pm; \ + _ca2u[i] = _bits_ca2 & _pm; \ + _cx2u[i] = _bits_cx2 & _pm; \ + _pm = (_pm << 16)|(_pm >> 8); \ + } \ +} +#else /*(BITMAP_BIT_ORDER == LSBFirst)*/ +#define InitializeMergeRop24(alu,pm) {\ + register int i; \ + register MfbBits _pm = (pm) & cfbmask[0]; \ + mergeRopPtr _bits = mergeGetRopBits(alu); \ + MfbBits _bits_ca1 = _bits->ca1 & cfbmask[0]; \ + MfbBits _bits_cx1 = _bits->cx1 & cfbmask[0]; \ + MfbBits _bits_ca2 = _bits->ca2 & cfbmask[0]; \ + MfbBits _bits_cx2 = _bits->cx2 & cfbmask[0]; \ + _pm |= (_pm << 24); \ + _bits_ca1 |= (_bits->ca1 << 24); \ + _bits_cx1 |= (_bits->cx1 << 24); \ + _bits_ca2 |= (_bits->ca2 << 24); \ + _bits_cx2 |= (_bits->cx2 << 24); \ + for(i = 0; i < 4; i++){ \ + _ca1u[i] = _bits_ca1 & _pm; \ + _cx1u[i] = _bits_cx1 | ~_pm; \ + _ca2u[i] = _bits_ca2 & _pm; \ + _cx2u[i] = _bits_cx2 & _pm; \ + _pm = (_pm << 16)|(_pm >> 8); \ + } \ +} +#endif /*(BITMAP_BIT_ORDER == MSBFirst)*/ +#endif /* PSZ == 24 */ +#else /* mfb */ +#define InitializeMergeRop(alu,pm) {\ + mergeRopPtr _bits; \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1; \ + _cx1 = _bits->cx1; \ + _ca2 = _bits->ca2; \ + _cx2 = _bits->cx2; \ +} +#endif + +/* AND has higher precedence than XOR */ + +#define DoMergeRop(src, dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (((src) & _ca2) ^ _cx2)) + +#define DoMergeRop24u(src, dst, i) \ +(((dst) & (((src) & _ca1u[i]) ^ _cx1u[i])) ^ (((src) & _ca2u[i]) ^ _cx2u[i])) + +#define DoMaskMergeRop24(src, dst, mask, index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src0 = (src);\ + MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \ + MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | (((*(dst)) & cfbmask[idx]) & \ + (((( _src1 |(~mask))<>cfb24Shift[idx])&cfbmask[idx]) ^ \ + (((_src2 &(mask))>>cfb24Shift[idx])&cfbmask[idx])))); \ + (dst)--; \ + } + +#define DoMaskMergeRop(src, dst, mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1) | ~(mask))) ^ ((((src) & _ca2) ^ _cx2) & (mask))) + +#define DoMaskMergeRop24u(src, dst, mask, i) \ +(((dst) & ((((src) & _ca1u[(i)]) ^ _cx1u[(i)]) | ~(mask))) ^ ((((src) & _ca2u[(i)]) ^ _cx2u[(i)]) & (mask))) + +#define DoMergeRop24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src0 = (src);\ + MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \ + MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \ + ((_src1 << cfb24Shift[idx])&cfbmask[idx])) ^ \ + ((_src2 << cfb24Shift[idx])&cfbmask[idx]))); \ + idx++; \ + (dst)++; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \ + ((_src1 >> cfb24Shift[idx])&cfbmask[idx])) ^ \ + ((_src2 >> cfb24Shift[idx])&cfbmask[idx]))); \ + (dst)--; \ + } + +#define DoPrebuiltMergeRop(dst) (((dst) & _cca) ^ _ccx) + +#define DoPrebuiltMergeRop24(dst,index) { \ + register int idx = ((index) & 3)<< 1; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) &\ + (( _cca <>cfb24Shift[idx])&cfbmask[idx])) ^ \ + (( _ccx >>cfb24Shift[idx])&cfbmask[idx]))); \ + (dst)--; \ + } + +#define DoMaskPrebuiltMergeRop(dst,mask) \ + (((dst) & (_cca | ~(mask))) ^ (_ccx & (mask))) + +#define PrebuildMergeRop(src) ((_cca = ((src) & _ca1) ^ _cx1), \ + (_ccx = ((src) & _ca2) ^ _cx2)) + +#ifndef MROP +#define MROP 0 +#endif + +#define Mclear (1<> cfb24Shift[(idx)<<1])| \ + ((*((pix)+1) & cfbmask[((idx)<<1)+1]) << cfb24Shift[((idx)<<1)+1])) + +#define MROP_SOLID24P(src,dst,sindex, index) \ + MROP_SOLID24(MROP_PIXEL24(src,sindex),dst,index) + +#define MROP_MASK24P(src,dst,mask,sindex,index) \ + MROP_MASK24(MROP_PIXEL24(src,sindex),dst,mask,index) + +#if (MROP) == Mcopy +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) (src) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src<>cfb24Shift[idx])&cfbmask[idx]); \ + } +#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((src) & (mask))) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src&(mask))>>cfb24Shift[idx])&cfbmask[idx])); \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Copy) +#endif + +#if (MROP) == McopyInverted +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) (~(src)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = ~(src); \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src << cfb24Shift[idx])&cfbmask[idx]); \ + idx++; \ + (dst)++; \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src >>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((~(src)) & (mask))) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = ~(src); \ + *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx])) | \ + ((((_src & (mask))>>cfb24Shift[idx])&cfbmask[idx])); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,CopyInverted) +#endif + +#if (MROP) == Mxor +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) ((src) ^ (dst)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) ^= ((_src << cfb24Shift[idx])&cfbmask[idx]); \ + idx++; \ + (dst)++; \ + *(dst) ^= ((_src >>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((src) & (mask)) ^ (dst)) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) ^= ((((src)&(mask))<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Xor) +#endif + +#if (MROP) == Mor +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) ((src) | (dst)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) |= (((src)<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((src) & (mask)) | (dst)) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) |= (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Or) +#endif + +#if (MROP) == (Mcopy|Mxor|MandReverse|Mor) +#define MROP_DECLARE() MfbBits _ca1 = 0, _cx1 = 0; +#define MROP_DECLARE_REG() register MROP_DECLARE() +#define MROP_INITIALIZE(alu,pm) { \ + mergeRopPtr _bits; \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1; \ + _cx1 = _bits->cx1; \ +} +#define MROP_SOLID(src,dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (src)) +#define MROP_MASK(src,dst,mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1)) | (~(mask)) ^ ((src) & (mask)))) +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,CopyXorAndReverseOr) +#define MROP_PREBUILD(src) PrebuildMergeRop(src) +#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop() +#define MROP_PREBUILT_SOLID(src,dst) DoPrebuiltMergeRop(dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) DoPrebuiltMergeRop24(dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) DoMaskPrebuiltMergeRop(dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) DoMaskPrebuiltMergeRop24(dst,mask,index) +#endif + +#if (MROP) == 0 +#if !defined(PSZ) || (PSZ != 24) +#define MROP_DECLARE() DeclareMergeRop() +#define MROP_DECLARE_REG() register DeclareMergeRop() +#define MROP_INITIALIZE(alu,pm) InitializeMergeRop(alu,pm) +#define MROP_SOLID(src,dst) DoMergeRop(src,dst) +#define MROP_MASK(src,dst,mask) DoMaskMergeRop(src, dst, mask) +#else +#define MROP_DECLARE() \ + DeclareMergeRop() \ + DeclareMergeRop24() +#define MROP_DECLARE_REG() \ + register DeclareMergeRop()\ + DeclareMergeRop24() +#define MROP_INITIALIZE(alu,pm) \ + InitializeMergeRop(alu,pm)\ + InitializeMergeRop24(alu,pm) +#define MROP_SOLID(src,dst) DoMergeRop24u(src,dst,((int)(&(dst)-pdstBase) % 3)) +#define MROP_MASK(src,dst,mask) DoMaskMergeRop24u(src, dst, mask,((int)(&(dst) - pdstBase)%3)) +#endif +#define MROP_SOLID24(src,dst,index) DoMergeRop24(src,dst,index) +#define MROP_MASK24(src,dst,mask,index) DoMaskMergeRop24(src, dst, mask,index) +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,General) +#define MROP_PREBUILD(src) PrebuildMergeRop(src) +#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop() +#define MROP_PREBUILT_SOLID(src,dst) DoPrebuiltMergeRop(dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) DoPrebuiltMergeRop24(dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) DoMaskPrebuiltMergeRop(dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) \ + DoMaskPrebuiltMergeRop24(dst,mask,index) +#endif + +#ifndef MROP_PREBUILD +#define MROP_PREBUILD(src) +#define MROP_PREBUILT_DECLARE() +#define MROP_PREBUILT_SOLID(src,dst) MROP_SOLID(src,dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) MROP_SOLID24(src,dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) MROP_MASK(src,dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) MROP_MASK24(src,dst,mask,index) +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define MROP_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define MROP_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfb.h (revision 51223) @@ -0,0 +1,1158 @@ +/* $XFree86: xc/programs/Xserver/mfb/mfb.h,v 1.21 2003/07/16 03:35:16 dawes Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.0, 1/17/89 */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: mfb.h,v 1.4 2001/02/09 02:05:18 xorgcvs Exp $ */ + +#if !defined(_MFB_H_) || defined(MFB_PROTOTYPES_ONLY) +#ifndef MFB_PROTOTYPES_ONLY +#define _MFB_H_ +#endif + +/* Monochrome Frame Buffer definitions + written by drewry, september 1986 +*/ +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "mibstore.h" + +extern int InverseAlu[]; +extern int mfbGetInverseAlu(int i); + +/* warning: PixelType definition duplicated in maskbits.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ +#ifndef MfbBits +#define MfbBits CARD32 +#endif + +/* mfbbitblt.c */ + +extern void mfbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); + +extern RegionPtr mfbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern Bool mfbRegisterCopyPlaneProc( + ScreenPtr /*pScreen*/, + RegionPtr (* /*proc*/)( + DrawablePtr /* pSrcDrawable */, + DrawablePtr /* pDstDrawable */, + GCPtr /* pGC */, + int /* srcx */, + int /* srcy */, + int /* width */, + int /* height */, + int /* dstx */, + int /* dsty */, + unsigned long /* bitPlane */ + ) +); + +extern RegionPtr mfbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); +/* mfbbltC.c */ + +extern void mfbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltCI.c */ + +extern void mfbDoBitbltCopyInverted( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltG.c */ + +extern void mfbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltO.c */ + +extern void mfbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltX.c */ + +extern void mfbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbres.c */ + +extern void mfbBresS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* mfbbresd.c */ + +extern void mfbBresD( + int /*fgrop*/, + int /*bgrop*/, + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* mfbbstore.c */ + +extern void mfbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void mfbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* mfbclip.c */ + +extern RegionPtr mfbPixmapToRegion( + PixmapPtr /*pPix*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef RegionPtr (*mfbPixmapToRegionProc)(PixmapPtr); + +extern mfbPixmapToRegionProc *mfbPixmapToRegionWeak(void); +#endif + +/* mfbcmap.c */ + +extern int mfbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void mfbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void mfbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void mfbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool mfbCreateColormap( + ColormapPtr /*pMap*/ +); + +extern void mfbDestroyColormap( + ColormapPtr /*pMap*/ +); + +extern Bool mfbCreateDefColormap( + ScreenPtr /*pScreen*/ +); +/* mfbfillarc.c */ + +extern void mfbPolyFillArcSolid( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* mfbfillrct.c */ + +extern void mfbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); +/* mfbfillsp.c */ + +extern void mfbBlackSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbWhiteSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbInvertSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbWhiteStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbBlackStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbInvertStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* mfbfont.c */ + +extern Bool mfbRealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +extern Bool mfbUnrealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbRealizeFontProc)(ScreenPtr, FontPtr); +typedef void (*mfbUnrealizeFontProc)(ScreenPtr, FontPtr); + +extern mfbRealizeFontProc *mfbRealizeFontWeak(void); +extern mfbUnrealizeFontProc *mfbUnrealizeFontWeak(void); +#endif + +/* mfbgc.c */ + +extern Bool mfbCreateGC( + GCPtr /*pGC*/ +); + +extern void mfbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +extern int mfbReduceRop( + int /*alu*/, + Pixel /*src*/ +); + +/* mfbgetsp.c */ + +extern void mfbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* mfbhrzvert.c */ + +extern void mfbHorzS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); + +extern void mfbVertS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); +/* mfbigbblak.c */ + +extern void mfbImageGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbigbwht.c */ + +extern void mfbImageGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbimage.c */ + +extern void mfbPutImage( + DrawablePtr /*dst*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void mfbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* mfbline.c */ + +extern void mfbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void mfbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +/* mfbmisc.c */ + +extern void mfbQueryBestSize( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbQueryBestSizeProc)(int, unsigned short *, unsigned short *, + ScreenPtr); + +extern mfbQueryBestSizeProc *mfbQueryBestSizeWeak(void); +#endif + +/* mfbpablack.c */ + +extern void mfbSolidBlackArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleBlackArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); +/* mfbpainv.c */ + +extern void mfbSolidInvertArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleInvertArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); +/* mfbpawhite.c */ + +extern void mfbSolidWhiteArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleWhiteArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); + +/* mfbpgbinv.c */ + +extern void mfbPolyGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpgbinv.c */ + +extern void mfbPolyGlyphBltInvert( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpgbwht.c */ + +extern void mfbPolyGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpixmap.c */ + +extern PixmapPtr mfbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool mfbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr mfbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void mfbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void mfbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void mfbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void mfbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +/* mfbplyblack.c */ + +extern void mfbFillPolyBlack( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* mfbplyinv.c */ + +extern void mfbFillPolyInvert( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mfbpntwin.c */ + +extern void mfbFillPolyWhite( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* mfbpntwin.c */ + +extern void mfbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); +/* mfbpolypnt.c */ + +extern void mfbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* mfbpushpxl.c */ + +extern void mfbSolidPP( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +extern void mfbPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbPushPixelsProc)(GCPtr, PixmapPtr, DrawablePtr, int, int, + int, int); + +extern mfbPushPixelsProc *mfbPushPixelsWeak(void); +#endif + +/* mfbscrclse.c */ + +extern Bool mfbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); +/* mfbscrinit.c */ + +extern Bool mfbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*pWinIndex*/, + int * /*pGCIndex*/ +); + +extern Bool mfbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr mfbGetWindowPixmap( + WindowPtr /*pWin*/ +); + +extern void mfbSetWindowPixmap( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/ +); + +extern void mfbFillInScreen(ScreenPtr pScreen); + +/* mfbseg.c */ + +extern void mfbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void mfbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* mfbsetsp.c */ + +extern void mfbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + PixelType * /*psrc*/, + int /*alu*/, + PixelType * /*pdstBase*/, + int /*widthDst*/ +); + +extern void mfbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* mfbteblack.c */ + +extern void mfbTEGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbtewhite.c */ + +extern void mfbTEGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbtileC.c */ + +extern void mfbTileAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); +/* mfbtileG.c */ + +extern void mfbTileAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); + +extern void mfbTileAreaPPW( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); +/* mfbwindow.c */ + +extern Bool mfbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool mfbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool mfbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool mfbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool mfbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void mfbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool mfbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* mfbzerarc.c */ + +extern void mfbZeroPolyArcSS( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +/* + private filed of pixmap + pixmap.devPrivate = (PixelType *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes + + private field of screen + a pixmap, for which we allocate storage. devPrivate is a pointer to +the bits in the hardware framebuffer. note that devKind can be poked to +make the code work for framebuffers that are wider than their +displayable screen (e.g. the early vsII, which displayed 960 pixels +across, but was 1024 in the hardware.) + + private field of GC +*/ +typedef void (*mfbFillAreaProcPtr)( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ + ); + +typedef struct { + unsigned char rop; /* reduction of rasterop to 1 of 3 */ + unsigned char ropOpStip; /* rop for opaque stipple */ + unsigned char ropFillArea; /* == alu, rop, or ropOpStip */ + unsigned char unused1[sizeof(long) - 3]; /* Alignment */ + mfbFillAreaProcPtr FillArea; /* fills regions; look at the code */ + } mfbPrivGC; +typedef mfbPrivGC *mfbPrivGCPtr; +#endif + +/* XXX these should be static, but it breaks the ABI */ +extern int mfbGCPrivateIndex; /* index into GC private array */ +extern int mfbGetGCPrivateIndex(void); +extern int mfbWindowPrivateIndex; /* index into Window private array */ +extern int mfbGetWindowPrivateIndex(void); +#ifdef PIXMAP_PER_WINDOW +extern int frameWindowPrivateIndex; /* index into Window private array */ +extern int frameGetWindowPrivateIndex(void); +#endif + +#ifndef MFB_PROTOTYPES_ONLY +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border tile is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; + } mfbPrivWin; + +/* Common macros for extracting drawing information */ + +#define mfbGetTypedWidth(pDrawable,wtype) (\ + (((pDrawable)->type == DRAWABLE_WINDOW) ? \ + (int) (((PixmapPtr)((pDrawable)->pScreen->devPrivate))->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define mfbGetByteWidth(pDrawable) mfbGetTypedWidth(pDrawable, unsigned char) + +#define mfbGetPixelWidth(pDrawable) mfbGetTypedWidth(pDrawable, PixelType) + +#define mfbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr) (pDrawable)->pScreen->devPrivate; \ + else \ + _pPix = (PixmapPtr) (pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define mfbGetByteWidthAndPointer(pDrawable, width, pointer) \ + mfbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define mfbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + mfbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = (PixmapPtr) (pWin)->drawable.pScreen->devPrivate; \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define mfbGetWindowPixelWidthAndPointer(pWin, width, pointer) \ + mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, PixelType, PixelType) + +#define mfbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, char, char) + +/* mfb uses the following macros to calculate addresses in drawables. + * To support banked framebuffers, the macros come in four flavors. + * All four collapse into the same definition on unbanked devices. + * + * mfbScanlineFoo - calculate address and do bank switching + * mfbScanlineFooNoBankSwitch - calculate address, don't bank switch + * mfbScanlineFooSrc - calculate address, switch source bank + * mfbScanlineFooDst - calculate address, switch destination bank + */ + +/* The NoBankSwitch versions are the same for banked and unbanked cases */ + +#define mfbScanlineIncNoBankSwitch(_ptr, _off) _ptr += (_off) +#define mfbScanlineOffsetNoBankSwitch(_ptr, _off) ((_ptr) + (_off)) +#define mfbScanlineDeltaNoBankSwitch(_ptr, _y, _w) \ + mfbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w)) +#define mfbScanlineNoBankSwitch(_ptr, _x, _y, _w) \ + mfbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +#ifdef MFB_LINE_BANK + +#include "mfblinebank.h" /* get macro definitions from this file */ + +#else /* !MFB_LINE_BANK - unbanked case */ + +#define mfbScanlineInc(_ptr, _off) mfbScanlineIncNoBankSwitch(_ptr, _off) +#define mfbScanlineIncSrc(_ptr, _off) mfbScanlineInc(_ptr, _off) +#define mfbScanlineIncDst(_ptr, _off) mfbScanlineInc(_ptr, _off) + +#define mfbScanlineOffset(_ptr, _off) mfbScanlineOffsetNoBankSwitch(_ptr, _off) +#define mfbScanlineOffsetSrc(_ptr, _off) mfbScanlineOffset(_ptr, _off) +#define mfbScanlineOffsetDst(_ptr, _off) mfbScanlineOffset(_ptr, _off) + +#define mfbScanlineSrc(_ptr, _x, _y, _w) mfbScanline(_ptr, _x, _y, _w) +#define mfbScanlineDst(_ptr, _x, _y, _w) mfbScanline(_ptr, _x, _y, _w) + +#define mfbScanlineDeltaSrc(_ptr, _y, _w) mfbScanlineDelta(_ptr, _y, _w) +#define mfbScanlineDeltaDst(_ptr, _y, _w) mfbScanlineDelta(_ptr, _y, _w) + +#endif /* MFB_LINE_BANK */ + +#define mfbScanlineDelta(_ptr, _y, _w) \ + mfbScanlineOffset(_ptr, (_y) * (_w)) + +#define mfbScanline(_ptr, _x, _y, _w) \ + mfbScanlineOffset(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + + +/* precomputed information about each glyph for GlyphBlt code. + this saves recalculating the per glyph information for each box. +*/ +typedef struct _pos{ + int xpos; /* xposition of glyph's origin */ + int xchar; /* x position mod 32 */ + int leftEdge; + int rightEdge; + int topEdge; + int bottomEdge; + PixelType *pdstBase; /* longword with character origin */ + int widthGlyph; /* width in bytes of this glyph */ +} TEXTPOS; + +/* reduced raster ops for mfb */ +#define RROP_BLACK GXclear +#define RROP_WHITE GXset +#define RROP_NOP GXnoop +#define RROP_INVERT GXinvert + +/* macros for mfbbitblt.c, mfbfillsp.c + these let the code do one switch on the rop per call, rather +than a switch on the rop per item (span or rectangle.) +*/ + +#define fnCLEAR(src, dst) (0) +#define fnAND(src, dst) (src & dst) +#define fnANDREVERSE(src, dst) (src & ~dst) +#define fnCOPY(src, dst) (src) +#define fnANDINVERTED(src, dst) (~src & dst) +#define fnNOOP(src, dst) (dst) +#define fnXOR(src, dst) (src ^ dst) +#define fnOR(src, dst) (src | dst) +#define fnNOR(src, dst) (~(src | dst)) +#define fnEQUIV(src, dst) (~src ^ dst) +#define fnINVERT(src, dst) (~dst) +#define fnORREVERSE(src, dst) (src | ~dst) +#define fnCOPYINVERTED(src, dst)(~src) +#define fnORINVERTED(src, dst) (~src | dst) +#define fnNAND(src, dst) (~(src & dst)) +#undef fnSET +#define fnSET(src, dst) (MfbBits)(~0) + +/* Using a "switch" statement is much faster in most cases + * since the compiler can do a look-up table or multi-way branch + * instruction, depending on the architecture. The result on + * A Sun 3/50 is at least 2.5 times faster, assuming a uniform + * distribution of RasterOp operation types. + * + * However, doing some profiling on a running system reveals + * GXcopy is the operation over 99.5% of the time and + * GXxor is the next most frequent (about .4%), so we make special + * checks for those first. + * + * Note that this requires a change to the "calling sequence" + * since we can't engineer a "switch" statement to have an lvalue. + */ +#undef DoRop +#define DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) \ + result = fnCOPY (src, dst); \ + else if (alu == GXxor) \ + result = fnXOR (src, dst); \ + else \ + switch (alu) \ + { \ + case GXclear: \ + result = fnCLEAR (src, dst); \ + break; \ + case GXand: \ + result = fnAND (src, dst); \ + break; \ + case GXandReverse: \ + result = fnANDREVERSE (src, dst); \ + break; \ + case GXandInverted: \ + result = fnANDINVERTED (src, dst); \ + break; \ + default: \ + case GXnoop: \ + result = fnNOOP (src, dst); \ + break; \ + case GXor: \ + result = fnOR (src, dst); \ + break; \ + case GXnor: \ + result = fnNOR (src, dst); \ + break; \ + case GXequiv: \ + result = fnEQUIV (src, dst); \ + break; \ + case GXinvert: \ + result = fnINVERT (src, dst); \ + break; \ + case GXorReverse: \ + result = fnORREVERSE (src, dst); \ + break; \ + case GXcopyInverted: \ + result = fnCOPYINVERTED (src, dst); \ + break; \ + case GXorInverted: \ + result = fnORINVERTED (src, dst); \ + break; \ + case GXnand: \ + result = fnNAND (src, dst); \ + break; \ + case GXset: \ + result = fnSET (src, dst); \ + break; \ + } \ +} + + +/* C expression fragments for various operations. These get passed in + * as -D's on the compile command line. See mfb/Imakefile. This + * fixes XBUG 6319. + * + * This seems like a good place to point out that mfb's use of the + * words black and white is an unfortunate misnomer. In mfb code, black + * means zero, and white means one. + */ +#define MFB_OPEQ_WHITE |= +#define MFB_OPEQ_BLACK &=~ +#define MFB_OPEQ_INVERT ^= +#define MFB_EQWHOLEWORD_WHITE =~0 +#define MFB_EQWHOLEWORD_BLACK =0 +#define MFB_EQWHOLEWORD_INVERT ^=~0 +#define MFB_OP_WHITE /* nothing */ +#define MFB_OP_BLACK ~ + +/* + * if MFB is built as a module, it shouldn't call libc functions. + */ +#ifdef XFree86LOADER +#include "xf86_ansic.h" +#endif + +#endif /* MFB_PROTOTYPES_ONLY */ +#endif /* _MFB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbmap.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/mfbmap.h,v 1.1.2.2 1998/06/08 15:13:15 dawes Exp $ */ + +#ifndef _MFBMAP_H +#define _MFBMAP_H + +#define InverseAlu xf1bppInverseAlu +#define endtab xf1bppendtab +#define mask xf1bppmask +#define mergeRopBits xf1bppmergeRopBits +#define mergeGetRopBits xf1bppmergeGetRopBits +#define mfbAllocatePrivates xf1bppAllocatePrivates +#define mfbBSFuncRec xf1bppBSFuncRec +#define mfbBlackSolidFS xf1bppBlackSolidFS +#define mfbBlackStippleFS xf1bppBlackStippleFS +#define mfbBresD xf1bppBresD +#define mfbBresS xf1bppBresS +#define mfbChangeWindowAttributes xf1bppChangeWindowAttributes +#define mfbCloseScreen xf1bppCloseScreen +#define mfbCopyArea xf1bppCopyArea +#define mfbCopyPixmap xf1bppCopyPixmap +#define mfbCopyPlane xf1bppCopyPlane +#define mfbCopyRotatePixmap xf1bppCopyRotatePixmap +#define mfbCopyWindow xf1bppCopyWindow +#define mfbCreateColormap xf1bppCreateColormap +#define mfbCreateDefColormap xf1bppCreateDefColormap +#define mfbCreateGC xf1bppCreateGC +#define mfbCreatePixmap xf1bppCreatePixmap +#define mfbCreateWindow xf1bppCreateWindow +#define mfbDestroyColormap xf1bppDestroyColormap +#define mfbDestroyPixmap xf1bppDestroyPixmap +#define mfbDestroyWindow xf1bppDestroyWindow +#define mfbDoBitblt xf1bppDoBitblt +#define mfbDoBitbltCopy xf1bppDoBitbltCopy +#define mfbDoBitbltCopyInverted xf1bppDoBitbltCopyInverted +#define mfbDoBitbltGeneral xf1bppDoBitbltGeneral +#define mfbDoBitbltOr xf1bppDoBitbltOr +#define mfbDoBitbltXor xf1bppDoBitbltXor +#define mfbFillInScreen xf1bppFillInScreen +#define mfbFillPolyBlack xf1bppFillPolyBlack +#define mfbFillPolyInvert xf1bppFillPolyInvert +#define mfbFillPolyWhite xf1bppFillPolyWhite +#define mfbGCPrivateIndex xf1bppGCPrivateIndex +#define mfbGetGCPrivateIndex xf1bppGetGCPrivateIndex +#define mfbGetImage xf1bppGetImage +#define mfbGetInverseAlu xf1bppGetInverseAlu +#define mfbGetSpans xf1bppGetSpans +#define mfbGetWindowPixmap xf1bppGetWindowPixmap +#define mfbGetWindowPrivateIndex xf1bppGetWindowPrivateIndex +#define mfbGetmask xf1bppGetmask +#define mfbGetpartmasks xf1bppGetpartmasks +#define mfbGetrmask xf1bppGetrmask +#define mfbGetstarttab xf1bppGetstarttab +#define mfbGetendtab xf1bppGetendtab +#define mfbHorzS xf1bppHorzS +#define mfbImageGlyphBltBlack xf1bppImageGlyphBltBlack +#define mfbImageGlyphBltWhite xf1bppImageGlyphBltWhite +#define mfbInstallColormap xf1bppInstallColormap +#define mfbInvertSolidFS xf1bppInvertSolidFS +#define mfbInvertStippleFS xf1bppInvertStippleFS +#define mfbLineSD xf1bppLineSD +#define mfbLineSS xf1bppLineSS +#define mfbListInstalledColormaps xf1bppListInstalledColormaps +#define mfbMapWindow xf1bppMapWindow +#define mfbPadPixmap xf1bppPadPixmap +#define mfbPaintWindow xf1bppPaintWindow +#define mfbPixmapToRegion xf1bppPixmapToRegion +#define mfbPixmapToRegionWeak xf1bppPixmapToRegionWeak +#define mfbPolyFillArcSolid xf1bppPolyFillArcSolid +#define mfbPolyFillRect xf1bppPolyFillRect +#define mfbPolyGlyphBltBlack xf1bppPolyGlyphBltBlack +#define mfbPolyGlyphBltInvert xf1bppPolyGlyphBltInvert +#define mfbPolyGlyphBltWhite xf1bppPolyGlyphBltWhite +#define mfbPolyPoint xf1bppPolyPoint +#define mfbPositionWindow xf1bppPositionWindow +#define mfbPushPixels xf1bppPushPixels +#define mfbPushPixelsWeak xf1bppPushPixelsWeak +#define mfbPutImage xf1bppPutImage +#define mfbQueryBestSize xf1bppQueryBestSize +#define mfbQueryBestSizeWeak xf1bppQueryBestSizeWeak +#define mfbRealizeFont xf1bppRealizeFont +#define mfbRealizeFontWeak xf1bppRealizeFontWeak +#define mfbReduceRop xf1bppReduceRop +#define mfbRegisterCopyPlaneProc xf1bppRegisterCopyPlaneProc +#define mfbResolveColor xf1bppResolveColor +#define mfbRestoreAreas xf1bppRestoreAreas +#define mfbSaveAreas xf1bppSaveAreas +#define mfbScreenInit xf1bppScreenInit +#define mfbSegmentSD xf1bppSegmentSD +#define mfbSegmentSS xf1bppSegmentSS +#define mfbSetScanline xf1bppSetScanline +#define mfbSetSpans xf1bppSetSpans +#define mfbSetWindowPixmap xf1bppSetWindowPixmap +#define mfbSolidBlackArea xf1bppSolidBlackArea +#define mfbSolidInvertArea xf1bppSolidInvertArea +#define mfbSolidPP xf1bppSolidPP +#define mfbSolidWhiteArea xf1bppSolidWhiteArea +#define mfbStippleBlackArea xf1bppStippleBlackArea +#define mfbStippleInvertArea xf1bppStippleInvertArea +#define mfbStippleWhiteArea xf1bppStippleWhiteArea +#define mfbTEGlyphBltBlack xf1bppTEGlyphBltBlack +#define mfbTEGlyphBltWhite xf1bppTEGlyphBltWhite +#define mfbTileAreaPPW xf1bppTileAreaPPW +#define mfbTileAreaPPWCopy xf1bppTileAreaPPWCopy +#define mfbTileAreaPPWGeneral xf1bppTileAreaPPWGeneral +#define mfbTileFS xf1bppTileFS +#define mfbUninstallColormap xf1bppUninstallColormap +#define mfbUnmapWindow xf1bppUnmapWindow +#define mfbUnnaturalStippleFS xf1bppUnnaturalStippleFS +#define mfbUnnaturalTileFS xf1bppUnnaturalTileFS +#define mfbUnrealizeFont xf1bppUnrealizeFont +#define mfbUnrealizeFontWeak xf1bppUnrealizeFontWeak +#define mfbValidateGC xf1bppValidateGC +#define mfbVertS xf1bppVertS +#define mfbWhiteSolidFS xf1bppWhiteSolidFS +#define mfbWhiteStippleFS xf1bppWhiteStippleFS +#define mfbWindowPrivateIndex xf1bppWindowPrivateIndex +#define mfbXRotatePixmap xf1bppXRotatePixmap +#define mfbYRotatePixmap xf1bppYRotatePixmap +#define mfbZeroPolyArcSS xf1bppZeroPolyArcSS +#define partmasks xf1bpppartmasks +#define rmask xf1bpprmask +#define starttab xf1bppstarttab + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbunmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbunmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mfbunmap.h (revision 51223) @@ -0,0 +1,116 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/mfbunmap.h,v 1.1.2.1 1998/06/27 14:48:24 dawes Exp $ */ + +#ifdef _MFBMAP_H +#undef _MFBMAP_H + +#undef InverseAlu +#undef endtab +#undef mask +#undef mergeRopBits +#undef mergeGetRopBits +#undef mfbAllocatePrivates +#undef mfbBSFuncRec +#undef mfbBlackSolidFS +#undef mfbBlackStippleFS +#undef mfbBresD +#undef mfbBresS +#undef mfbChangeWindowAttributes +#undef mfbCloseScreen +#undef mfbCopyArea +#undef mfbCopyPixmap +#undef mfbCopyPlane +#undef mfbCopyRotatePixmap +#undef mfbCopyWindow +#undef mfbCreateColormap +#undef mfbCreateDefColormap +#undef mfbCreateGC +#undef mfbCreatePixmap +#undef mfbCreateWindow +#undef mfbDestroyColormap +#undef mfbDestroyPixmap +#undef mfbDestroyWindow +#undef mfbDoBitblt +#undef mfbDoBitbltCopy +#undef mfbDoBitbltCopyInverted +#undef mfbDoBitbltGeneral +#undef mfbDoBitbltOr +#undef mfbDoBitbltXor +#undef mfbFillPolyBlack +#undef mfbFillPolyInvert +#undef mfbFillPolyWhite +#undef mfbGCPrivateIndex +#undef mfbGetImage +#undef mfbGetInverseAlu +#undef mfbGetSpans +#undef mfbGetWindowPixmap +#undef mfbHorzS +#undef mfbImageGlyphBltBlack +#undef mfbImageGlyphBltWhite +#undef mfbInstallColormap +#undef mfbInvertSolidFS +#undef mfbInvertStippleFS +#undef mfbLineSD +#undef mfbLineSS +#undef mfbListInstalledColormaps +#undef mfbMapWindow +#undef mfbPadPixmap +#undef mfbPaintWindow +#undef mfbPixmapToRegion +#undef mfbPixmapToRegionWeak +#undef mfbPolyFillArcSolid +#undef mfbPolyFillRect +#undef mfbPolyGlyphBltBlack +#undef mfbPolyGlyphBltInvert +#undef mfbPolyGlyphBltWhite +#undef mfbPolyPoint +#undef mfbPositionWindow +#undef mfbPushPixels +#undef mfbPushPixelsWeak +#undef mfbPutImage +#undef mfbQueryBestSize +#undef mfbQueryBestSizeWeak +#undef mfbRealizeFont +#undef mfbRealizeFontWeak +#undef mfbReduceRop +#undef mfbRegisterCopyPlaneProc +#undef mfbResolveColor +#undef mfbRestoreAreas +#undef mfbSaveAreas +#undef mfbScreenInit +#undef mfbSegmentSD +#undef mfbSegmentSS +#undef mfbSetScanline +#undef mfbSetSpans +#undef mfbSetWindowPixmap +#undef mfbSolidBlackArea +#undef mfbSolidInvertArea +#undef mfbSolidPP +#undef mfbSolidWhiteArea +#undef mfbStippleBlackArea +#undef mfbStippleInvertArea +#undef mfbStippleWhiteArea +#undef mfbTEGlyphBltBlack +#undef mfbTEGlyphBltWhite +#undef mfbTileAreaPPW +#undef mfbTileAreaPPWCopy +#undef mfbTileAreaPPWGeneral +#undef mfbTileFS +#undef mfbUninstallColormap +#undef mfbUnmapWindow +#undef mfbUnnaturalStippleFS +#undef mfbUnnaturalTileFS +#undef mfbUnrealizeFont +#undef mfbUnrealizeFontWeak +#undef mfbValidateGC +#undef mfbVertS +#undef mfbWhiteSolidFS +#undef mfbWhiteStippleFS +#undef mfbWindowPrivateIndex +#undef mfbXRotatePixmap +#undef mfbYRotatePixmap +#undef mfbZeroPolyArcSS +#undef partmasks +#undef rmask +#undef starttab + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mi.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mi.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mi.h (revision 51223) @@ -0,0 +1,645 @@ +/* $Xorg: mi.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/mi/mi.h,v 3.9 2001/08/06 20:51:16 dawes Exp $ */ + +#ifndef MI_H +#define MI_H +#include +#include "region.h" +#include "validate.h" +#include "window.h" +#include "gc.h" +#include +#include "input.h" +#include "cursor.h" + +#define MiBits CARD32 + +typedef struct _miDash *miDashPtr; +#define EVEN_DASH 0 +#define ODD_DASH ~0 + +/* miarc.c */ + +extern void miPolyArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* mibitblt.c */ + +extern RegionPtr miCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*xIn*/, + int /*yIn*/, + int /*widthSrc*/, + int /*heightSrc*/, + int /*xOut*/, + int /*yOut*/ +); + +extern void miOpqStipDrawable( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + RegionPtr /*prgnSrc*/, + MiBits * /*pbits*/, + int /*srcx*/, + int /*w*/, + int /*h*/, + int /*dstx*/, + int /*dsty*/ +); + +extern RegionPtr miCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/ +); + +extern void miGetImage( + DrawablePtr /*pDraw*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); + +extern void miPutImage( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +/* miclipn.c */ + +extern void miClipNotify( + void (* /*func*/)( + WindowPtr /* pWin */, + int /* dx */, + int /* dy */ + ) +); + +/* micursor.c */ + +extern void miRecolorCursor( + ScreenPtr /*pScr*/, + CursorPtr /*pCurs*/, + Bool /*displayed*/ +); + +/* midash.c */ + +extern miDashPtr miDashLine( + int /*npt*/, + DDXPointPtr /*ppt*/, + unsigned int /*nDash*/, + unsigned char * /*pDash*/, + unsigned int /*offset*/, + int * /*pnseg*/ +); + +extern void miStepDash( + int /*dist*/, + int * /*pDashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pDashOffset*/ +); + +/* mieq.c */ + + +#ifndef INPUT_H +typedef struct _DeviceRec *DevicePtr; +#endif + +extern Bool mieqInit( + DevicePtr /*pKbd*/, + DevicePtr /*pPtr*/ +); + +extern void mieqEnqueue( + xEventPtr /*e*/ +); + +extern void mieqSwitchScreen( + ScreenPtr /*pScreen*/, + Bool /*fromDIX*/ +); + +extern void mieqProcessInputEvents( + void +); + +/* miexpose.c */ + +extern RegionPtr miHandleExposures( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); + +extern void miSendGraphicsExpose( + ClientPtr /*client*/, + RegionPtr /*pRgn*/, + XID /*drawable*/, + int /*major*/, + int /*minor*/ +); + +extern void miSendExposures( + WindowPtr /*pWin*/, + RegionPtr /*pRgn*/, + int /*dx*/, + int /*dy*/ +); + +extern void miWindowExposures( + WindowPtr /*pWin*/, + RegionPtr /*prgn*/, + RegionPtr /*other_exposed*/ +); + +extern void miPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*prgn*/, + int /*what*/ +); + +extern void miClearDrawable( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/ +); + +/* mifillrct.c */ + +extern void miPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); + +/* miglblt.c */ + +extern void miPolyGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +extern void miImageGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +/* mipoly.c */ + +extern void miFillPolygon( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*pPts*/ +); + +/* mipolycon.c */ + +extern Bool miFillConvexPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mipolygen.c */ + +extern Bool miFillGeneralPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mipolypnt.c */ + +extern void miPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); + +/* mipolyrect.c */ + +extern void miPolyRectangle( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nrects*/, + xRectangle * /*pRects*/ +); + +/* mipolyseg.c */ + +extern void miPolySegment( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegs*/ +); + +/* mipolytext.c */ + +extern int miPolyText( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/, + FontEncoding /*fontEncoding*/ +); + +extern int miPolyText8( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/ +); + +extern int miPolyText16( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/ +); + +extern int miImageText( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/, + FontEncoding /*fontEncoding*/ +); + +extern void miImageText8( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/ +); + +extern void miImageText16( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/ +); + +/* mipushpxl.c */ + +extern void miPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +/* miregion.c */ + +/* see also region.h */ + +extern Bool miRectAlloc( + RegionPtr /*pRgn*/, + int /*n*/ +); + +extern void miSetExtents( + RegionPtr /*pReg*/ +); + +extern int miFindMaxBand( + RegionPtr /*prgn*/ +); + +#ifdef DEBUG +extern Bool miValidRegion( + RegionPtr /*prgn*/ +); +#endif + +extern Bool miRegionDataCopy(RegionPtr dst, RegionPtr src); +extern Bool miRegionBroken(RegionPtr pReg); + +/* miscrinit.c */ + +extern Bool miModifyPixmapHeader( + PixmapPtr /*pPixmap*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/ +); + +extern Bool miCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); + +extern Bool miCreateScreenResources( + ScreenPtr /*pScreen*/ +); + +extern Bool miScreenDevPrivateInit( + ScreenPtr /*pScreen*/, + int /*width*/, + pointer /*pbits*/ +); + +extern Bool miScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/, + int /*rootDepth*/, + int /*numDepths*/, + DepthPtr /*depths*/, + VisualID /*rootVisual*/, + int /*numVisuals*/, + VisualPtr /*visuals*/ +); + +extern int miAllocateGCPrivateIndex( + void +); + +extern PixmapPtr miGetScreenPixmap( + ScreenPtr pScreen +); + +extern void miSetScreenPixmap( + PixmapPtr pPix +); + +/* mivaltree.c */ + +extern int miShapedWindowIn( + ScreenPtr /*pScreen*/, + RegionPtr /*universe*/, + RegionPtr /*bounding*/, + BoxPtr /*rect*/, + int /*x*/, + int /*y*/ +); + +typedef void +(*SetRedirectBorderClipProcPtr) (WindowPtr pWindow, RegionPtr pRegion); + +typedef RegionPtr +(*GetRedirectBorderClipProcPtr) (WindowPtr pWindow); + +void +miRegisterRedirectBorderClipProc (SetRedirectBorderClipProcPtr setBorderClip, + GetRedirectBorderClipProcPtr getBorderClip); + +extern int miValidateTree( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/ +); + +extern void miWideLine( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pPts*/ +); + +extern void miWideDash( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pPts*/ +); + +extern void miMiter( + void +); + +extern void miNotMiter( + void +); + +/* miwindow.c */ + +extern void miClearToBackground( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/ +); + +extern Bool miChangeSaveUnder( + WindowPtr /*pWin*/, + WindowPtr /*first*/ +); + +extern void miPostChangeSaveUnder( + WindowPtr /*pWin*/, + WindowPtr /*pFirst*/ +); + +extern void miMarkWindow( + WindowPtr /*pWin*/ +); + +extern Bool miMarkOverlappedWindows( + WindowPtr /*pWin*/, + WindowPtr /*pFirst*/, + WindowPtr * /*ppLayerWin*/ +); + +extern void miHandleValidateExposures( + WindowPtr /*pWin*/ +); + +extern void miMoveWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + WindowPtr /*pNextSib*/, + VTKind /*kind*/ +); + +extern void miSlideAndSizeWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + WindowPtr /*pSib*/ +); + +extern WindowPtr miGetLayerWindow( + WindowPtr /*pWin*/ +); + +extern void miSetShape( + WindowPtr /*pWin*/ +); + +extern void miChangeBorderWidth( + WindowPtr /*pWin*/, + unsigned int /*width*/ +); + +extern void miMarkUnrealizedWindow( + WindowPtr /*pChild*/, + WindowPtr /*pWin*/, + Bool /*fromConfigure*/ +); + +extern void miSegregateChildren(WindowPtr pWin, RegionPtr pReg, int depth); + +/* mizerarc.c */ + +extern void miZeroPolyArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* mizerline.c */ + +extern void miZeroLine( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*mode*/, + int /*nptInit*/, + DDXPointRec * /*pptInit*/ +); + +extern void miZeroDashLine( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*mode*/, + int /*nptInit*/, + DDXPointRec * /*pptInit*/ +); + +extern void miPolyFillArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#endif /* MI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibank.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibank.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibank.h (revision 51223) @@ -0,0 +1,119 @@ +/* + * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/mi/mibank.h,v 1.10 2003/01/01 19:16:42 tsi Exp $ */ + +#ifndef __MIBANK_H__ +#define __MIBANK_H__ 1 + +#include "scrnintstr.h" + +/* + * Banking external interface. + */ + +/* + * This is the banking function type. The return value is normally zero. + * Non-zero returns can be used to implement the likes of scanline interleave, + * etc. + */ +typedef int miBankProc( + ScreenPtr /*pScreen*/, + unsigned int /*iBank*/ +); + +typedef miBankProc *miBankProcPtr; + +typedef struct _miBankInfo +{ + /* + * Banking refers to the use of one or more apertures (in the server's + * address space) to access various parts of a potentially larger hardware + * frame buffer. + * + * Three different banking schemes are supported: + * + * Single banking is indicated when pBankA and pBankB are equal and all + * three miBankProcPtr's point to the same function. Here, both reads and + * writes through the aperture access the same hardware location. + * + * Shared banking is indicated when pBankA and pBankB are equal but the + * source and destination functions differ. Here reads through the + * aperture do not necessarily access the same hardware location as writes. + * + * Double banking is indicated when pBankA and pBankB differ. Here two + * independent apertures are used to provide read/write access to + * potentially different hardware locations. + * + * Any other combination will result in no banking. + */ + miBankProcPtr SetSourceBank; /* Set pBankA bank number */ + miBankProcPtr SetDestinationBank; /* Set pBankB bank number */ + miBankProcPtr SetSourceAndDestinationBanks; /* Set both bank numbers */ + + pointer pBankA; /* First aperture location */ + pointer pBankB; /* First or second aperture location */ + + /* + * BankSize is in units of sizeof(char) and is the size of each bank. + */ + unsigned long BankSize; + + /* + * nBankDepth is the colour depth associated with the maximum number of a + * pixel's bits that are simultaneously accessible through the frame buffer + * aperture. + */ + unsigned int nBankDepth; +} miBankInfoRec, *miBankInfoPtr; + +Bool +miInitializeBanking( + ScreenPtr /*pScreen*/, + unsigned int /*xsize*/, + unsigned int /*ysize*/, + unsigned int /*width*/, + miBankInfoPtr /*pBankInfo*/ +); + +Bool +miModifyBanking( + ScreenPtr /*pScreen*/, + miBankInfoPtr /*pBankInfo*/ +); + +/* + * This function determines the minimum screen width, given a initial estimate + * and various screen attributes. DDX needs to determine this width before + * initializing the screen. + */ +int +miScanLineWidth( + unsigned int /*xsize*/, + unsigned int /*ysize*/, + unsigned int /*width*/, + unsigned long /*BankSize*/, + PixmapFormatRec * /*pBankFormat*/, + unsigned int /*nWidthUnit*/ +); + +#endif /* __MIBANK_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstore.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstore.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstore.h (revision 51223) @@ -0,0 +1,30 @@ +/*- + * mibstore.h -- + * Header file for users of the MI backing-store scheme. + * + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this + * software and its documentation for any purpose and without + * fee is hereby granted, provided that the above copyright + * notice appear in all copies. The University of California + * makes no representations about the suitability of this + * software for any purpose. It is provided "as is" without + * express or implied warranty. + * + * "$Xorg: mibstore.h,v 1.3 2000/08/17 19:53:37 cpqbld Exp $ + */ + + +/* $XFree86: xc/programs/Xserver/mi/mibstore.h,v 1.4 2001/01/17 22:37:06 dawes Exp $ */ + +#ifndef _MIBSTORE_H +#define _MIBSTORE_H + +#include "screenint.h" + +extern void miInitializeBackingStore( + ScreenPtr /*pScreen*/ +); + +#endif /* _MIBSTORE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstorest.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstorest.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mibstorest.h (revision 51223) @@ -0,0 +1,93 @@ +/* + * mibstorest.h + * + * internal structure definitions for mi backing store + */ + +/* $Xorg: mibstorest.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ + +/* $XFree86: xc/programs/Xserver/mi/mibstorest.h,v 1.4 2001/01/17 22:37:06 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "mibstore.h" +#include "regionstr.h" + +/* + * One of these structures is allocated per GC used with a backing-store + * drawable. + */ + +typedef struct { + GCPtr pBackingGC; /* Copy of the GC but with graphicsExposures + * set FALSE and the clientClip set to + * clip output to the valid regions of the + * backing pixmap. */ + int guarantee; /* GuaranteeNothing, etc. */ + unsigned long serialNumber; /* clientClip computed time */ + unsigned long stateChanges; /* changes in parent gc since last copy */ + GCOps *wrapOps; /* wrapped ops */ + GCFuncs *wrapFuncs; /* wrapped funcs */ +} miBSGCRec, *miBSGCPtr; + +/* + * one of these structures is allocated per Window with backing store + */ + +typedef struct { + PixmapPtr pBackingPixmap; /* Pixmap for saved areas */ + short x; /* origin of pixmap relative to window */ + short y; + RegionRec SavedRegion; /* Valid area in pBackingPixmap */ + char viewable; /* Tracks pWin->viewable so SavedRegion may + * be initialized correctly when the window + * is first mapped */ + char status; /* StatusNoPixmap, etc. */ + char backgroundState; /* background type */ + PixUnion background; /* background pattern */ +} miBSWindowRec, *miBSWindowPtr; + +#define StatusNoPixmap 1 /* pixmap has not been created */ +#define StatusVirtual 2 /* pixmap is virtual, tiled with background */ +#define StatusVDirty 3 /* pixmap is virtual, visiblt has contents */ +#define StatusBadAlloc 4 /* pixmap create failed, do not try again */ +#define StatusContents 5 /* pixmap is created, has valid contents */ + +typedef struct { + /* + * screen func wrappers + */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + CreateGCProcPtr CreateGC; + DestroyWindowProcPtr DestroyWindow; +} miBSScreenRec, *miBSScreenPtr; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micmap.h (revision 51223) @@ -0,0 +1,65 @@ +/* $XFree86: xc/programs/Xserver/mi/micmap.h,v 1.5 1999/06/14 07:32:11 dawes Exp $ */ + +#include "colormapst.h" + +#ifndef _MICMAP_H_ +#define _MICMAP_H_ + +extern ColormapPtr miInstalledMaps[MAXSCREENS]; + +typedef Bool (* miInitVisualsProcPtr)(VisualPtr *, DepthPtr *, int *, int *, + int *, VisualID *, unsigned long, int, + int); + +extern miInitVisualsProcPtr miInitVisualsProc; + +int miListInstalledColormaps(ScreenPtr pScreen, Colormap *pmaps); +void miInstallColormap(ColormapPtr pmap); +void miUninstallColormap(ColormapPtr pmap); + +void miResolveColor(unsigned short *, unsigned short *, unsigned short *, + VisualPtr); +Bool miInitializeColormap(ColormapPtr); +int miExpandDirectColors(ColormapPtr, int, xColorItem *, xColorItem *); +Bool miCreateDefColormap(ScreenPtr); +void miClearVisualTypes(void); +Bool miSetVisualTypes(int, int, int, int); +Bool miSetPixmapDepths(void); +Bool miSetVisualTypesAndMasks(int depth, int visuals, int bitsPerRGB, + int preferredCVC, + Pixel redMask, Pixel greenMask, Pixel blueMask); +int miGetDefaultVisualMask(int); +Bool miInitVisuals(VisualPtr *, DepthPtr *, int *, int *, int *, VisualID *, + unsigned long, int, int); +void miResetInitVisuals(void); + +void miHookInitVisuals(void (**old)(miInitVisualsProcPtr *), + void (*new)(miInitVisualsProcPtr *)); + + +#define MAX_PSEUDO_DEPTH 10 +#define MIN_TRUE_DEPTH 6 + +#define StaticGrayMask (1 << StaticGray) +#define GrayScaleMask (1 << GrayScale) +#define StaticColorMask (1 << StaticColor) +#define PseudoColorMask (1 << PseudoColor) +#define TrueColorMask (1 << TrueColor) +#define DirectColorMask (1 << DirectColor) + +#define ALL_VISUALS (StaticGrayMask|\ + GrayScaleMask|\ + StaticColorMask|\ + PseudoColorMask|\ + TrueColorMask|\ + DirectColorMask) + +#define LARGE_VISUALS (TrueColorMask|\ + DirectColorMask) + +#define SMALL_VISUALS (StaticGrayMask|\ + GrayScaleMask|\ + StaticColorMask|\ + PseudoColorMask) + +#endif /* _MICMAP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micoord.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micoord.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/micoord.h (revision 51223) @@ -0,0 +1,71 @@ +/* $XFree86: xc/programs/Xserver/mi/micoord.h,v 1.7 2003/10/29 22:57:48 tsi Exp $ */ +/* + * Copyright (C) 2000 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + * + */ + +#ifndef _MICOORD_H_ +#define _MICOORD_H_ 1 + +#include "servermd.h" + +/* Macros which handle a coordinate in a single register */ + +/* + * Most compilers will convert divisions by 65536 into shifts, if signed + * shifts exist. If your machine does arithmetic shifts and your compiler + * can't get it right, add to this line. + */ + +/* + * mips compiler - what a joke - it CSEs the 65536 constant into a reg + * forcing as to use div instead of shift. Let's be explicit. + */ + +#if defined(mips) || defined(sgi) || \ + defined(sparc) || defined(__sparc64__) || \ + defined(__alpha) || defined(__alpha__) || \ + defined(__i386__) || defined(i386) || \ + defined(__ia64__) || defined(ia64) || \ + defined(__s390x__) || defined(__s390__) || \ + defined(__amd64__) || defined(amd64) || defined(__amd64) +#define GetHighWord(x) (((int) (x)) >> 16) +#else +#define GetHighWord(x) (((int) (x)) / 65536) +#endif + +#if IMAGE_BYTE_ORDER == MSBFirst +#define intToCoord(i,x,y) (((x) = GetHighWord(i)), ((y) = (int) ((short) (i)))) +#define coordToInt(x,y) (((x) << 16) | ((y) & 0xffff)) +#define intToX(i) (GetHighWord(i)) +#define intToY(i) ((int) ((short) i)) +#else +#define intToCoord(i,x,y) (((x) = (int) ((short) (i))), ((y) = GetHighWord(i))) +#define coordToInt(x,y) (((y) << 16) | ((x) & 0xffff)) +#define intToX(i) ((int) ((short) (i))) +#define intToY(i) (GetHighWord(i)) +#endif + +#endif /* _MICOORD_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbe.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbe.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbe.h (revision 51223) @@ -0,0 +1,51 @@ +/* $Xorg: midbe.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for users of machine-independent DBE code + * + *****************************************************************************/ +/* $XFree86$ */ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIDBE_H +#define MIDBE_H + +/* EXTERNS */ + +extern Bool miDbeInit( + ScreenPtr pScreen, + DbeScreenPrivPtr pDbeScreenPriv +); + +#endif /* MIDBE_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/midbestr.h (revision 51223) @@ -0,0 +1,100 @@ +/* $Xorg: midbestr.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for users of machine-independent DBE code + * + *****************************************************************************/ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIDBE_STRUCT_H +#define MIDBE_STRUCT_H + + +/* DEFINES */ + +#define MI_DBE_WINDOW_PRIV_PRIV(pDbeWindowPriv) \ + (((miDbeWindowPrivPrivIndex < 0) || (!pDbeWindowPriv)) ? \ + NULL : \ + ((MiDbeWindowPrivPrivPtr) \ + ((pDbeWindowPriv)->devPrivates[miDbeWindowPrivPrivIndex].ptr))) + +#define MI_DBE_WINDOW_PRIV_PRIV_FROM_WINDOW(pWin)\ + MI_DBE_WINDOW_PRIV_PRIV(DBE_WINDOW_PRIV(pWin)) + +#define MI_DBE_SCREEN_PRIV_PRIV(pDbeScreenPriv) \ + (((miDbeScreenPrivPrivIndex < 0) || (!pDbeScreenPriv)) ? \ + NULL : \ + ((MiDbeScreenPrivPrivPtr) \ + ((pDbeScreenPriv)->devPrivates[miDbeScreenPrivPrivIndex].ptr))) + + +/* TYPEDEFS */ + +typedef struct _MiDbeWindowPrivPrivRec +{ + /* Place machine-specific fields in here. + * Since this is mi code, we do not really have machine-specific fields. + */ + + /* Pointer to a drawable that contains the contents of the back buffer. + */ + PixmapPtr pBackBuffer; + + /* Pointer to a drawable that contains the contents of the front buffer. + * This pointer is only used for the XdbeUntouched swap action. For that + * swap action, we need to copy the front buffer (window) contents into + * this drawable, copy the contents of current back buffer drawable (the + * back buffer) into the window, swap the front and back drawable pointers, + * and then swap the drawable/resource associations in the resource + * database. + */ + PixmapPtr pFrontBuffer; + + /* Pointer back to our window private with which we are associated. */ + DbeWindowPrivPtr pDbeWindowPriv; + +} MiDbeWindowPrivPrivRec, *MiDbeWindowPrivPrivPtr; + +typedef struct _MiDbeScreenPrivPrivRec +{ + /* Place machine-specific fields in here. + * Since this is mi code, we do not really have machine-specific fields. + */ + + /* Pointer back to our screen private with which we are associated. */ + DbeScreenPrivPtr pDbeScreenPriv; + +} MiDbeScreenPrivPrivRec, *MiDbeScreenPrivPrivPtr; + +#endif /* MIDBE_STRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifillarc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifillarc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifillarc.h (revision 51223) @@ -0,0 +1,216 @@ +/* $XFree86: xc/programs/Xserver/mi/mifillarc.h,v 3.6 2001/10/25 12:03:47 alanh Exp $ */ +/************************************************************ + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +********************************************************/ + +/* $Xorg: mifillarc.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ + +#ifndef __MIFILLARC_H__ +#define __MIFILLARC_H__ + +#define FULLCIRCLE (360 * 64) + +typedef struct _miFillArc { + int xorg, yorg; + int y; + int dx, dy; + int e; + int ym, yk, xm, xk; +} miFillArcRec; + +/* could use 64-bit integers */ +typedef struct _miFillArcD { + int xorg, yorg; + int y; + int dx, dy; + double e; + double ym, yk, xm, xk; +} miFillArcDRec; + +#define miFillArcEmpty(arc) (!(arc)->angle2 || \ + !(arc)->width || !(arc)->height || \ + (((arc)->width == 1) && ((arc)->height & 1))) + +#define miCanFillArc(arc) (((arc)->width == (arc)->height) || \ + (((arc)->width <= 800) && ((arc)->height <= 800))) + +#define MIFILLARCSETUP() \ + x = 0; \ + y = info.y; \ + e = info.e; \ + xk = info.xk; \ + xm = info.xm; \ + yk = info.yk; \ + ym = info.ym; \ + dx = info.dx; \ + dy = info.dy; \ + xorg = info.xorg; \ + yorg = info.yorg + +#define MIFILLARCSTEP(slw) \ + e += yk; \ + while (e >= 0) \ + { \ + x++; \ + xk -= xm; \ + e += xk; \ + } \ + y--; \ + yk -= ym; \ + slw = (x << 1) + dx; \ + if ((e == xk) && (slw > 1)) \ + slw-- + +#define MIFILLCIRCSTEP(slw) MIFILLARCSTEP(slw) +#define MIFILLELLSTEP(slw) MIFILLARCSTEP(slw) + +#define miFillArcLower(slw) (((y + dy) != 0) && ((slw > 1) || (e != xk))) + +typedef struct _miSliceEdge { + int x; + int stepx; + int deltax; + int e; + int dy; + int dx; +} miSliceEdgeRec, *miSliceEdgePtr; + +typedef struct _miArcSlice { + miSliceEdgeRec edge1, edge2; + int min_top_y, max_top_y; + int min_bot_y, max_bot_y; + Bool edge1_top, edge2_top; + Bool flip_top, flip_bot; +} miArcSliceRec; + +#define MIARCSLICESTEP(edge) \ + edge.x -= edge.stepx; \ + edge.e -= edge.dx; \ + if (edge.e <= 0) \ + { \ + edge.x -= edge.deltax; \ + edge.e += edge.dy; \ + } + +#define miFillSliceUpper(slice) \ + ((y >= slice.min_top_y) && (y <= slice.max_top_y)) + +#define miFillSliceLower(slice) \ + ((y >= slice.min_bot_y) && (y <= slice.max_bot_y)) + +#define MIARCSLICEUPPER(xl,xr,slice,slw) \ + xl = xorg - x; \ + xr = xl + slw - 1; \ + if (slice.edge1_top && (slice.edge1.x < xr)) \ + xr = slice.edge1.x; \ + if (slice.edge2_top && (slice.edge2.x > xl)) \ + xl = slice.edge2.x; + +#define MIARCSLICELOWER(xl,xr,slice,slw) \ + xl = xorg - x; \ + xr = xl + slw - 1; \ + if (!slice.edge1_top && (slice.edge1.x > xl)) \ + xl = slice.edge1.x; \ + if (!slice.edge2_top && (slice.edge2.x < xr)) \ + xr = slice.edge2.x; + +#define MIWIDEARCSETUP(x,y,dy,slw,e,xk,xm,yk,ym) \ + x = 0; \ + y = slw >> 1; \ + yk = y << 3; \ + xm = 8; \ + ym = 8; \ + if (dy) \ + { \ + xk = 0; \ + if (slw & 1) \ + e = -1; \ + else \ + e = -(y << 2) - 2; \ + } \ + else \ + { \ + y++; \ + yk += 4; \ + xk = -4; \ + if (slw & 1) \ + e = -(y << 2) - 3; \ + else \ + e = - (y << 3); \ + } + +#define MIFILLINARCSTEP(slw) \ + ine += inyk; \ + while (ine >= 0) \ + { \ + inx++; \ + inxk -= inxm; \ + ine += inxk; \ + } \ + iny--; \ + inyk -= inym; \ + slw = (inx << 1) + dx; \ + if ((ine == inxk) && (slw > 1)) \ + slw-- + +#define miFillInArcLower(slw) (((iny + dy) != 0) && \ + ((slw > 1) || (ine != inxk))) + +extern int miFreeArcCache( + pointer /*data*/, + XID /*id*/ +); + +extern struct finalSpan *realAllocSpan( + void +); + +extern void miFillArcSetup( + xArc * /*arc*/, + miFillArcRec * /*info*/ +); + +extern void miFillArcDSetup( + xArc * /*arc*/, + miFillArcDRec * /*info*/ +); + +extern void miEllipseAngleToSlope( + int /*angle*/, + int /*width*/, + int /*height*/, + int * /*dxp*/, + int * /*dyp*/, + double * /*d_dxp*/, + double * /*d_dyp*/ +); + +extern void miFillArcSliceSetup( + xArc * /*arc*/, + miArcSliceRec * /*slice*/, + GCPtr /*pGC*/ +); + +#endif /* __MIFILLARC_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifpoly.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifpoly.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mifpoly.h (revision 51223) @@ -0,0 +1,111 @@ +/* $Xorg: mifpoly.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/mi/mifpoly.h,v 1.3 2001/10/25 12:03:47 alanh Exp $ */ + +#ifndef __MIFPOLY_H__ +#define __MIFPOLY_H__ + +#define EPSILON 0.000001 +#define ISEQUAL(a,b) (Fabs((a) - (b)) <= EPSILON) +#define UNEQUAL(a,b) (Fabs((a) - (b)) > EPSILON) +#define WITHINHALF(a, b) (((a) - (b) > 0.0) ? (a) - (b) < 0.5 : \ + (b) - (a) <= 0.5) +#define ROUNDTOINT(x) ((int) (((x) > 0.0) ? ((x) + 0.5) : ((x) - 0.5))) +#define ISZERO(x) (Fabs((x)) <= EPSILON) +#define PTISEQUAL(a,b) (ISEQUAL(a.x,b.x) && ISEQUAL(a.y,b.y)) +#define PTUNEQUAL(a,b) (UNEQUAL(a.x,b.x) || UNEQUAL(a.y,b.y)) +#define PtEqual(a, b) (((a).x == (b).x) && ((a).y == (b).y)) + +#define NotEnd 0 +#define FirstEnd 1 +#define SecondEnd 2 + +#define SQSECANT 108.856472512142 /* 1/sin^2(11/2) - for 11o miter cutoff */ +#define D2SECANT 5.21671526231167 /* 1/2*sin(11/2) - max extension per width */ + +#ifdef NOINLINEICEIL +#define ICEIL(x) ((int)ceil(x)) +#else +#ifdef __GNUC__ +static __inline int ICEIL(double x) +{ + int _cTmp = x; + return ((x == _cTmp) || (x < 0.0)) ? _cTmp : _cTmp+1; +} +#else +#define ICEIL(x) ((((x) == (_cTmp = (x))) || ((x) < 0.0)) ? _cTmp : _cTmp+1) +#define ICEILTEMPDECL static int _cTmp; +#endif +#endif + +/* Point with sub-pixel positioning. In this case we use doubles, but + * see mifpolycon.c for other suggestions + */ +typedef struct _SppPoint { + double x, y; +} SppPointRec, *SppPointPtr; + +typedef struct _SppArc { + double x, y, width, height; + double angle1, angle2; +} SppArcRec, *SppArcPtr; + +/* mifpolycon.c */ + +extern void miFillSppPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + SppPointPtr /*ptsIn*/, + int /*xTrans*/, + int /*yTrans*/, + double /*xFtrans*/, + double /*yFtrans*/ +); + +#endif /* __MIFPOLY_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/migc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/migc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/migc.h (revision 51223) @@ -0,0 +1,74 @@ +/* $Xorg: migc.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1993, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ + +/* $XFree86: xc/programs/Xserver/mi/migc.h,v 1.7 2001/08/06 20:51:18 dawes Exp $ */ + +extern void miChangeGC( + GCPtr /*pGC*/, + unsigned long /*mask*/ +); + +extern void miDestroyGC( + GCPtr /*pGC*/ +); + +extern GCOpsPtr miCreateGCOps( + GCOpsPtr /*prototype*/ +); + +extern void miDestroyGCOps( + GCOpsPtr /*ops*/ +); + +extern void miDestroyClip( + GCPtr /*pGC*/ +); + +extern void miChangeClip( + GCPtr /*pGC*/, + int /*type*/, + pointer /*pvalue*/, + int /*nrects*/ +); + +extern void miCopyClip( + GCPtr /*pgcDst*/, + GCPtr /*pgcSrc*/ +); + +extern void miCopyGC( + GCPtr /*pGCSrc*/, + unsigned long /*changes*/, + GCPtr /*pGCDst*/ +); + +extern void miComputeCompositeClip( + GCPtr /*pGC*/, + DrawablePtr /*pDrawable*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miline.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miline.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miline.h (revision 51223) @@ -0,0 +1,174 @@ +/* $Xorg: miline.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1994, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/miline.h,v 1.6 2001/08/06 20:51:19 dawes Exp $ */ + +#ifndef MILINE_H + +#include "screenint.h" + +/* + * Public definitions used for configuring basic pixelization aspects + * of the sample implementation line-drawing routines provided in + * {mfb,mi,cfb*} at run-time. + */ + +#define XDECREASING 4 +#define YDECREASING 2 +#define YMAJOR 1 + +#define OCTANT1 (1 << (YDECREASING)) +#define OCTANT2 (1 << (YDECREASING|YMAJOR)) +#define OCTANT3 (1 << (XDECREASING|YDECREASING|YMAJOR)) +#define OCTANT4 (1 << (XDECREASING|YDECREASING)) +#define OCTANT5 (1 << (XDECREASING)) +#define OCTANT6 (1 << (XDECREASING|YMAJOR)) +#define OCTANT7 (1 << (YMAJOR)) +#define OCTANT8 (1 << (0)) + +#define XMAJOROCTANTS (OCTANT1 | OCTANT4 | OCTANT5 | OCTANT8) + +#define DEFAULTZEROLINEBIAS (OCTANT2 | OCTANT3 | OCTANT4 | OCTANT5) + +/* + * Devices can configure the rendering of routines in mi, mfb, and cfb* + * by specifying a thin line bias to be applied to a particular screen + * using the following function. The bias parameter is an OR'ing of + * the appropriate OCTANT constants defined above to indicate which + * octants to bias a line to prefer an axial step when the Bresenham + * error term is exactly zero. The octants are mapped as follows: + * + * \ | / + * \ 3 | 2 / + * \ | / + * 4 \ | / 1 + * \|/ + * ----------- + * /|\ + * 5 / | \ 8 + * / | \ + * / 6 | 7 \ + * / | \ + * + * For more information, see "Ambiguities in Incremental Line Rastering," + * Jack E. Bresenham, IEEE CG&A, May 1987. + */ + +extern void miSetZeroLineBias( + ScreenPtr /* pScreen */, + unsigned int /* bias */ +); + +/* + * Private definitions needed for drawing thin (zero width) lines + * Used by the mi, mfb, and all cfb* components. + */ + +#define X_AXIS 0 +#define Y_AXIS 1 + +#define OUT_LEFT 0x08 +#define OUT_RIGHT 0x04 +#define OUT_ABOVE 0x02 +#define OUT_BELOW 0x01 + +#define OUTCODES(_result, _x, _y, _pbox) \ + if ( (_x) < (_pbox)->x1) (_result) |= OUT_LEFT; \ + else if ( (_x) >= (_pbox)->x2) (_result) |= OUT_RIGHT; \ + if ( (_y) < (_pbox)->y1) (_result) |= OUT_ABOVE; \ + else if ( (_y) >= (_pbox)->y2) (_result) |= OUT_BELOW; + +#define MIOUTCODES(outcode, x, y, xmin, ymin, xmax, ymax) \ +{\ + if (x < xmin) outcode |= OUT_LEFT;\ + if (x > xmax) outcode |= OUT_RIGHT;\ + if (y < ymin) outcode |= OUT_ABOVE;\ + if (y > ymax) outcode |= OUT_BELOW;\ +} + +#define SWAPINT(i, j) \ +{ register int _t = i; i = j; j = _t; } + +#define SWAPPT(i, j) \ +{ DDXPointRec _t; _t = i; i = j; j = _t; } + +#define SWAPINT_PAIR(x1, y1, x2, y2)\ +{ int t = x1; x1 = x2; x2 = t;\ + t = y1; y1 = y2; y2 = t;\ +} + +#define miGetZeroLineBias(_pScreen) \ + ((miZeroLineScreenIndex < 0) ? \ + 0 : ((_pScreen)->devPrivates[miZeroLineScreenIndex].uval)) + +#define CalcLineDeltas(_x1,_y1,_x2,_y2,_adx,_ady,_sx,_sy,_SX,_SY,_octant) \ + (_octant) = 0; \ + (_sx) = (_SX); \ + if (((_adx) = (_x2) - (_x1)) < 0) { \ + (_adx) = -(_adx); \ + (_sx = -(_sx)); \ + (_octant) |= XDECREASING; \ + } \ + (_sy) = (_SY); \ + if (((_ady) = (_y2) - (_y1)) < 0) { \ + (_ady) = -(_ady); \ + (_sy = -(_sy)); \ + (_octant) |= YDECREASING; \ + } + +#define SetYMajorOctant(_octant) ((_octant) |= YMAJOR) + +#define FIXUP_ERROR(_e, _octant, _bias) \ + (_e) -= (((_bias) >> (_octant)) & 1) + +#define IsXMajorOctant(_octant) (!((_octant) & YMAJOR)) +#define IsYMajorOctant(_octant) ((_octant) & YMAJOR) +#define IsXDecreasingOctant(_octant) ((_octant) & XDECREASING) +#define IsYDecreasingOctant(_octant) ((_octant) & YDECREASING) + +extern int miZeroLineScreenIndex; + +extern int miZeroClipLine( + int /*xmin*/, + int /*ymin*/, + int /*xmax*/, + int /*ymax*/, + int * /*new_x1*/, + int * /*new_y1*/, + int * /*new_x2*/, + int * /*new_y2*/, + unsigned int /*adx*/, + unsigned int /*ady*/, + int * /*pt1_clipped*/, + int * /*pt2_clipped*/, + int /*octant*/, + unsigned int /*bias*/, + int /*oc1*/, + int /*oc2*/ +); + +#endif /* MILINE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mioverlay.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mioverlay.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mioverlay.h (revision 51223) @@ -0,0 +1,33 @@ +/* $XFree86: xc/programs/Xserver/mi/mioverlay.h,v 3.3 2000/02/29 00:16:03 mvojkovi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef __MIOVERLAY_H +#define __MIOVERLAY_H + +typedef void (*miOverlayTransFunc)(ScreenPtr, int, BoxPtr); +typedef Bool (*miOverlayInOverlayFunc)(WindowPtr); + +Bool +miInitOverlay( + ScreenPtr pScreen, + miOverlayInOverlayFunc inOverlay, + miOverlayTransFunc trans +); + +Bool +miOverlayGetPrivateClips( + WindowPtr pWin, + RegionPtr *borderClip, + RegionPtr *clipList +); + +Bool miOverlayCollectUnderlayRegions(WindowPtr, RegionPtr*); +void miOverlayComputeCompositeClip(GCPtr, WindowPtr); +Bool miOverlayCopyUnderlay(ScreenPtr); +void miOverlaySetTransFunction(ScreenPtr, miOverlayTransFunc); +void miOverlaySetRootClip(ScreenPtr, Bool); + +#endif /* __MIOVERLAY_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipict.h (revision 51223) @@ -0,0 +1,213 @@ +/* + * $XFree86: xc/programs/Xserver/render/mipict.h,v 1.12 2002/11/05 05:34:40 keithp Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _MIPICT_H_ +#define _MIPICT_H_ + +#include "picturestr.h" + +#define MI_MAX_INDEXED 256 /* XXX depth must be <= 8 */ + +#if MI_MAX_INDEXED <= 256 +typedef CARD8 miIndexType; +#endif + +typedef struct _miIndexed { + Bool color; + CARD32 rgba[MI_MAX_INDEXED]; + miIndexType ent[32768]; +} miIndexedRec, *miIndexedPtr; + +#define miCvtR8G8B8to15(s) ((((s) >> 3) & 0x001f) | \ + (((s) >> 6) & 0x03e0) | \ + (((s) >> 9) & 0x7c00)) +#define miIndexToEnt15(mif,rgb15) ((mif)->ent[rgb15]) +#define miIndexToEnt24(mif,rgb24) miIndexToEnt15(mif,miCvtR8G8B8to15(rgb24)) + +#define miIndexToEntY24(mif,rgb24) ((mif)->ent[CvtR8G8B8toY15(rgb24)]) + +int +miCreatePicture (PicturePtr pPicture); + +void +miDestroyPicture (PicturePtr pPicture); + +void +miDestroyPictureClip (PicturePtr pPicture); + +int +miChangePictureClip (PicturePtr pPicture, + int type, + pointer value, + int n); + +void +miChangePicture (PicturePtr pPicture, + Mask mask); + +void +miValidatePicture (PicturePtr pPicture, + Mask mask); + + +Bool +miClipPicture (RegionPtr pRegion, + PicturePtr pPicture, + INT16 xReg, + INT16 yReg, + INT16 xPict, + INT16 yPict); + +Bool +miComputeCompositeRegion (RegionPtr pRegion, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +Bool +miPictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); + +void +miGlyphExtents (int nlist, + GlyphListPtr list, + GlyphPtr *glyphs, + BoxPtr extents); + +void +miGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +void +miRenderColorToPixel (PictFormatPtr pPict, + xRenderColor *color, + CARD32 *pixel); + +void +miRenderPixelToColor (PictFormatPtr pPict, + CARD32 pixel, + xRenderColor *color); + +Bool +miIsSolidAlpha (PicturePtr pSrc); + +void +miCompositeRects (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +void +miTrapezoidBounds (int ntrap, xTrapezoid *traps, BoxPtr box); + +void +miTrapezoids (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +void +miPointFixedBounds (int npoint, xPointFixed *points, BoxPtr bounds); + +void +miTriangleBounds (int ntri, xTriangle *tris, BoxPtr bounds); + +void +miRasterizeTriangle (PicturePtr pMask, + xTriangle *tri, + int x_off, + int y_off); + +void +miTriangles (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntri, + xTriangle *tris); + +void +miTriStrip (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +void +miTriFan (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +PicturePtr +miCreateAlphaPicture (ScreenPtr pScreen, + PicturePtr pDst, + PictFormatPtr pPictFormat, + CARD16 width, + CARD16 height); + +Bool +miInitIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat); + +void +miCloseIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat); + +void +miUpdateIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat, + int ndef, + xColorItem *pdef); + +#endif /* _MIPICT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointer.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointer.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointer.h (revision 51223) @@ -0,0 +1,162 @@ +/* + * mipointer.h + * + */ + +/* $Xorg: mipointer.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mipointer.h,v 3.8 2001/08/06 20:51:19 dawes Exp $ */ + +#ifndef MIPOINTER_H +#define MIPOINTER_H + +#include "cursor.h" +#include "input.h" + +typedef struct _miPointerSpriteFuncRec { + Bool (*RealizeCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */ + ); + Bool (*UnrealizeCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */ + ); + void (*SetCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */, + int /* x */, + int /* y */ + ); + void (*MoveCursor)( + ScreenPtr /* pScr */, + int /* x */, + int /* y */ + ); +} miPointerSpriteFuncRec, *miPointerSpriteFuncPtr; + +typedef struct _miPointerScreenFuncRec { + Bool (*CursorOffScreen)( + ScreenPtr* /* ppScr */, + int* /* px */, + int* /* py */ + ); + void (*CrossScreen)( + ScreenPtr /* pScr */, + int /* entering */ + ); + void (*WarpCursor)( + ScreenPtr /* pScr */, + int /* x */, + int /* y */ + ); + void (*EnqueueEvent)( + xEventPtr /* event */ + ); + void (*NewEventScreen)( + ScreenPtr /* pScr */, + Bool /* fromDIX */ + ); +} miPointerScreenFuncRec, *miPointerScreenFuncPtr; + +extern Bool miDCInitialize( + ScreenPtr /*pScreen*/, + miPointerScreenFuncPtr /*screenFuncs*/ +); + +extern Bool miPointerInitialize( + ScreenPtr /*pScreen*/, + miPointerSpriteFuncPtr /*spriteFuncs*/, + miPointerScreenFuncPtr /*screenFuncs*/, + Bool /*waitForUpdate*/ +); + +extern void miPointerWarpCursor( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/ +); + +extern int miPointerGetMotionBufferSize( + void +); + +extern int miPointerGetMotionEvents( + DeviceIntPtr /*pPtr*/, + xTimecoord * /*coords*/, + unsigned long /*start*/, + unsigned long /*stop*/, + ScreenPtr /*pScreen*/ +); + +extern void miPointerUpdate( + void +); + +extern void miPointerDeltaCursor( + int /*dx*/, + int /*dy*/, + unsigned long /*time*/ +); + +extern void miPointerAbsoluteCursor( + int /*x*/, + int /*y*/, + unsigned long /*time*/ +); + +extern void miPointerPosition( + int * /*x*/, + int * /*y*/ +); + +#undef miRegisterPointerDevice +extern void miRegisterPointerDevice( + ScreenPtr /*pScreen*/, + DevicePtr /*pDevice*/ +); + +extern void miPointerSetNewScreen( + int, /*screen_no*/ + int, /*x*/ + int /*y*/ +); +extern ScreenPtr miPointerCurrentScreen( + void +); + +#define miRegisterPointerDevice(pScreen,pDevice) \ + _miRegisterPointerDevice(pScreen,pDevice) + +extern void _miRegisterPointerDevice( + ScreenPtr /*pScreen*/, + DeviceIntPtr /*pDevice*/ +); + +extern int miPointerScreenIndex; + +#endif /* MIPOINTER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointrst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointrst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipointrst.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * mipointrst.h + * + */ + +/* $Xorg: mipointrst.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mipointrst.h,v 1.3 2001/04/19 14:14:07 tsi Exp $ */ + +#include "mipointer.h" +#include "scrnintstr.h" + +#define MOTION_SIZE 256 + +typedef struct { + xTimecoord event; + ScreenPtr pScreen; +} miHistoryRec, *miHistoryPtr; + +typedef struct { + ScreenPtr pScreen; /* current screen */ + ScreenPtr pSpriteScreen;/* screen containing current sprite */ + CursorPtr pCursor; /* current cursor */ + CursorPtr pSpriteCursor;/* cursor on screen */ + BoxRec limits; /* current constraints */ + Bool confined; /* pointer can't change screens */ + int x, y; /* hot spot location */ + int devx, devy; /* sprite position */ + DevicePtr pPointer; /* pointer device structure */ + miHistoryRec history[MOTION_SIZE]; + int history_start, history_end; +} miPointerRec, *miPointerPtr; + +typedef struct { + miPointerSpriteFuncPtr spriteFuncs; /* sprite-specific methods */ + miPointerScreenFuncPtr screenFuncs; /* screen-specific methods */ + CloseScreenProcPtr CloseScreen; + Bool waitForUpdate; /* don't move cursor in SIGIO */ + Bool showTransparent; /* show empty cursors */ +} miPointerScreenRec, *miPointerScreenPtr; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipoly.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipoly.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mipoly.h (revision 51223) @@ -0,0 +1,218 @@ +/* $Xorg: mipoly.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/mipoly.h,v 1.2 2001/08/06 20:51:19 dawes Exp $ */ + + +/* + * fill.h + * + * Created by Brian Kelleher; Oct 1985 + * + * Include file for filled polygon routines. + * + * These are the data structures needed to scan + * convert regions. Two different scan conversion + * methods are available -- the even-odd method, and + * the winding number method. + * The even-odd rule states that a point is inside + * the polygon if a ray drawn from that point in any + * direction will pass through an odd number of + * path segments. + * By the winding number rule, a point is decided + * to be inside the polygon if a ray drawn from that + * point in any direction passes through a different + * number of clockwise and counter-clockwise path + * segments. + * + * These data structures are adapted somewhat from + * the algorithm in (Foley/Van Dam) for scan converting + * polygons. + * The basic algorithm is to start at the top (smallest y) + * of the polygon, stepping down to the bottom of + * the polygon by incrementing the y coordinate. We + * keep a list of edges which the current scanline crosses, + * sorted by x. This list is called the Active Edge Table (AET) + * As we change the y-coordinate, we update each entry in + * in the active edge table to reflect the edges new xcoord. + * This list must be sorted at each scanline in case + * two edges intersect. + * We also keep a data structure known as the Edge Table (ET), + * which keeps track of all the edges which the current + * scanline has not yet reached. The ET is basically a + * list of ScanLineList structures containing a list of + * edges which are entered at a given scanline. There is one + * ScanLineList per scanline at which an edge is entered. + * When we enter a new edge, we move it from the ET to the AET. + * + * From the AET, we can implement the even-odd rule as in + * (Foley/Van Dam). + * The winding number rule is a little trickier. We also + * keep the EdgeTableEntries in the AET linked by the + * nextWETE (winding EdgeTableEntry) link. This allows + * the edges to be linked just as before for updating + * purposes, but only uses the edges linked by the nextWETE + * link as edges representing spans of the polygon to + * drawn (as with the even-odd rule). + */ + +/* + * for the winding number rule + */ +#define CLOCKWISE 1 +#define COUNTERCLOCKWISE -1 + +typedef struct _EdgeTableEntry { + int ymax; /* ycoord at which we exit this edge. */ + BRESINFO bres; /* Bresenham info to run the edge */ + struct _EdgeTableEntry *next; /* next in the list */ + struct _EdgeTableEntry *back; /* for insertion sort */ + struct _EdgeTableEntry *nextWETE; /* for winding num rule */ + int ClockWise; /* flag for winding number rule */ +} EdgeTableEntry; + + +typedef struct _ScanLineList{ + int scanline; /* the scanline represented */ + EdgeTableEntry *edgelist; /* header node */ + struct _ScanLineList *next; /* next in the list */ +} ScanLineList; + + +typedef struct { + int ymax; /* ymax for the polygon */ + int ymin; /* ymin for the polygon */ + ScanLineList scanlines; /* header node */ +} EdgeTable; + + +/* + * Here is a struct to help with storage allocation + * so we can allocate a big chunk at a time, and then take + * pieces from this heap when we need to. + */ +#define SLLSPERBLOCK 25 + +typedef struct _ScanLineListBlock { + ScanLineList SLLs[SLLSPERBLOCK]; + struct _ScanLineListBlock *next; +} ScanLineListBlock; + +/* + * number of points to buffer before sending them off + * to scanlines() : Must be an even number + */ +#define NUMPTSTOBUFFER 200 + + + +/* + * + * a few macros for the inner loops of the fill code where + * performance considerations don't allow a procedure call. + * + * Evaluate the given edge at the given scanline. + * If the edge has expired, then we leave it and fix up + * the active edge table; otherwise, we increment the + * x value to be ready for the next scanline. + * The winding number rule is in effect, so we must notify + * the caller when the edge has been removed so he + * can reorder the Winding Active Edge Table. + */ +#define EVALUATEEDGEWINDING(pAET, pPrevAET, y, fixWAET) { \ + if (pAET->ymax == y) { /* leaving this edge */ \ + pPrevAET->next = pAET->next; \ + pAET = pPrevAET->next; \ + fixWAET = 1; \ + if (pAET) \ + pAET->back = pPrevAET; \ + } \ + else { \ + BRESINCRPGONSTRUCT(pAET->bres); \ + pPrevAET = pAET; \ + pAET = pAET->next; \ + } \ +} + + +/* + * Evaluate the given edge at the given scanline. + * If the edge has expired, then we leave it and fix up + * the active edge table; otherwise, we increment the + * x value to be ready for the next scanline. + * The even-odd rule is in effect. + */ +#define EVALUATEEDGEEVENODD(pAET, pPrevAET, y) { \ + if (pAET->ymax == y) { /* leaving this edge */ \ + pPrevAET->next = pAET->next; \ + pAET = pPrevAET->next; \ + if (pAET) \ + pAET->back = pPrevAET; \ + } \ + else { \ + BRESINCRPGONSTRUCT(pAET->bres); \ + pPrevAET = pAET; \ + pAET = pAET->next; \ + } \ +} + +/* mipolyutil.c */ + +extern Bool miInsertEdgeInET( + EdgeTable * /*ET*/, + EdgeTableEntry * /*ETE*/, + int /*scanline*/, + ScanLineListBlock ** /*SLLBlock*/, + int * /*iSLLBlock*/ +); + +extern Bool miCreateETandAET( + int /*count*/, + DDXPointPtr /*pts*/, + EdgeTable * /*ET*/, + EdgeTableEntry * /*AET*/, + EdgeTableEntry * /*pETEs*/, + ScanLineListBlock * /*pSLLBlock*/ +); + +extern void miloadAET( + EdgeTableEntry * /*AET*/, + EdgeTableEntry * /*ETEs*/ +); + +extern void micomputeWAET( + EdgeTableEntry * /*AET*/ +); + +extern int miInsertionSort( + EdgeTableEntry * /*AET*/ +); + +extern void miFreeStorage( + ScanLineListBlock * /*pSLLBlock*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misc.h (revision 51223) @@ -0,0 +1,269 @@ +/* $XFree86: xc/programs/Xserver/include/misc.h,v 3.28 2001/12/14 19:59:55 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +Copyright 1992, 1993 Data General Corporation; +Copyright 1992, 1993 OMRON Corporation + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that the +above copyright notice appear in all copies and that both that copyright +notice and this permission notice appear in supporting documentation, and that +neither the name OMRON or DATA GENERAL be used in advertising or publicity +pertaining to distribution of the software without specific, written prior +permission of the party whose name is to be used. Neither OMRON or +DATA GENERAL make any representation about the suitability of this software +for any purpose. It is provided "as is" without express or implied warranty. + +OMRON AND DATA GENERAL EACH DISCLAIM ALL WARRANTIES WITH REGARD TO THIS +SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, +IN NO EVENT SHALL OMRON OR DATA GENERAL BE LIABLE FOR ANY SPECIAL, INDIRECT +OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE +OF THIS SOFTWARE. + +******************************************************************/ +/* $Xorg: misc.h,v 1.5 2001/02/09 02:05:15 xorgcvs Exp $ */ +#ifndef MISC_H +#define MISC_H 1 +/* + * X internal definitions + * + */ + +extern unsigned long globalSerialNumber; +extern unsigned long serverGeneration; + +#include +#include +#include +#include +#include + +#ifndef IN_MODULE +#ifndef NULL +#include +#endif +#endif + +#ifndef MAXSCREENS +#define MAXSCREENS 16 +#endif +#define MAXCLIENTS 256 +#define MAXDITS 1 +#define MAXEXTENSIONS 128 +#define MAXFORMATS 8 +#define MAXVISUALS_PER_SCREEN 50 + +typedef unsigned long PIXEL; +typedef unsigned long ATOM; + + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif + +#ifndef _XTYPEDEF_CALLBACKLISTPTR +typedef struct _CallbackList *CallbackListPtr; /* also in dix.h */ +#define _XTYPEDEF_CALLBACKLISTPTR +#endif + +typedef struct _xReq *xReqPtr; + +#include "os.h" /* for ALLOCATE_LOCAL and DEALLOCATE_LOCAL */ +#ifndef IN_MODULE +#include /* for bcopy, bzero, and bcmp */ +#endif + +#define NullBox ((BoxPtr)0) +#define MILLI_PER_MIN (1000 * 60) +#define MILLI_PER_SECOND (1000) + + /* this next is used with None and ParentRelative to tell + PaintWin() what to use to paint the background. Also used + in the macro IS_VALID_PIXMAP */ + +#define USE_BACKGROUND_PIXEL 3 +#define USE_BORDER_PIXEL 3 + + +/* byte swap a 32-bit literal */ +#define lswapl(x) ((((x) & 0xff) << 24) |\ + (((x) & 0xff00) << 8) |\ + (((x) & 0xff0000) >> 8) |\ + (((x) >> 24) & 0xff)) + +/* byte swap a short literal */ +#define lswaps(x) ((((x) & 0xff) << 8) | (((x) >> 8) & 0xff)) + +#undef min +#undef max + +#define min(a, b) (((a) < (b)) ? (a) : (b)) +#define max(a, b) (((a) > (b)) ? (a) : (b)) +#ifndef IN_MODULE +/* abs() is a function, not a macro; include the file declaring + * it in case we haven't done that yet. + */ +#include +#endif /* IN_MODULE */ +#ifndef Fabs +#define Fabs(a) ((a) > 0.0 ? (a) : -(a)) /* floating absolute value */ +#endif +#define sign(x) ((x) < 0 ? -1 : ((x) > 0 ? 1 : 0)) +/* this assumes b > 0 */ +#define modulus(a, b, d) if (((d) = (a) % (b)) < 0) (d) += (b) +/* + * return the least significant bit in x which is set + * + * This works on 1's complement and 2's complement machines. + * If you care about the extra instruction on 2's complement + * machines, change to ((x) & (-(x))) + */ +#define lowbit(x) ((x) & (~(x) + 1)) + +#ifndef IN_MODULE +/* XXX Not for modules */ +#include +#if !defined(MAXSHORT) || !defined(MINSHORT) || \ + !defined(MAXINT) || !defined(MININT) +/* + * Some implementations #define these through , so preclude + * #include'ing it later. + */ + +#include +#endif +#undef MAXSHORT +#define MAXSHORT SHRT_MAX +#undef MINSHORT +#define MINSHORT SHRT_MIN +#undef MAXINT +#define MAXINT INT_MAX +#undef MININT +#define MININT INT_MIN + +#include +#include +#include /* for fopen, etc... */ + +#endif + +/* some macros to help swap requests, replies, and events */ + +#define LengthRestB(stuff) \ + ((client->req_len << 2) - sizeof(*stuff)) + +#define LengthRestS(stuff) \ + ((client->req_len << 1) - (sizeof(*stuff) >> 1)) + +#define LengthRestL(stuff) \ + (client->req_len - (sizeof(*stuff) >> 2)) + +#define SwapRestS(stuff) \ + SwapShorts((short *)(stuff + 1), LengthRestS(stuff)) + +#define SwapRestL(stuff) \ + SwapLongs((CARD32 *)(stuff + 1), LengthRestL(stuff)) + +/* byte swap a 32-bit value */ +#define swapl(x, n) { \ + n = ((char *) (x))[0];\ + ((char *) (x))[0] = ((char *) (x))[3];\ + ((char *) (x))[3] = n;\ + n = ((char *) (x))[1];\ + ((char *) (x))[1] = ((char *) (x))[2];\ + ((char *) (x))[2] = n; } + +/* byte swap a short */ +#define swaps(x, n) { \ + n = ((char *) (x))[0];\ + ((char *) (x))[0] = ((char *) (x))[1];\ + ((char *) (x))[1] = n; } + +/* copy 32-bit value from src to dst byteswapping on the way */ +#define cpswapl(src, dst) { \ + ((char *)&(dst))[0] = ((char *) &(src))[3];\ + ((char *)&(dst))[1] = ((char *) &(src))[2];\ + ((char *)&(dst))[2] = ((char *) &(src))[1];\ + ((char *)&(dst))[3] = ((char *) &(src))[0]; } + +/* copy short from src to dst byteswapping on the way */ +#define cpswaps(src, dst) { \ + ((char *) &(dst))[0] = ((char *) &(src))[1];\ + ((char *) &(dst))[1] = ((char *) &(src))[0]; } + +extern void SwapLongs( + CARD32 *list, + unsigned long count); + +extern void SwapShorts( + short *list, + unsigned long count); + +extern void MakePredeclaredAtoms(void); + +extern int Ones( + unsigned long /*mask*/); + +typedef struct _xPoint *DDXPointPtr; +typedef struct _Box *BoxPtr; +typedef struct _xEvent *xEventPtr; +typedef struct _xRectangle *xRectanglePtr; +typedef struct _GrabRec *GrabPtr; + +/* typedefs from other places - duplicated here to minimize the amount + * of unnecessary junk that one would normally have to include to get + * these symbols defined + */ + +#ifndef _XTYPEDEF_CHARINFOPTR +typedef struct _CharInfo *CharInfoPtr; /* also in fonts/include/font.h */ +#define _XTYPEDEF_CHARINFOPTR +#endif + +#endif /* MISC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscanfill.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscanfill.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscanfill.h (revision 51223) @@ -0,0 +1,151 @@ +/* $Xorg: miscanfill.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SCANFILLINCLUDED +#define SCANFILLINCLUDED +/* + * scanfill.h + * + * Written by Brian Kelleher; Jan 1985 + * + * This file contains a few macros to help track + * the edge of a filled object. The object is assumed + * to be filled in scanline order, and thus the + * algorithm used is an extension of Bresenham's line + * drawing algorithm which assumes that y is always the + * major axis. + * Since these pieces of code are the same for any filled shape, + * it is more convenient to gather the library in one + * place, but since these pieces of code are also in + * the inner loops of output primitives, procedure call + * overhead is out of the question. + * See the author for a derivation if needed. + */ + + + +/* + * In scan converting polygons, we want to choose those pixels + * which are inside the polygon. Thus, we add .5 to the starting + * x coordinate for both left and right edges. Now we choose the + * first pixel which is inside the pgon for the left edge and the + * first pixel which is outside the pgon for the right edge. + * Draw the left pixel, but not the right. + * + * How to add .5 to the starting x coordinate: + * If the edge is moving to the right, then subtract dy from the + * error term from the general form of the algorithm. + * If the edge is moving to the left, then add dy to the error term. + * + * The reason for the difference between edges moving to the left + * and edges moving to the right is simple: If an edge is moving + * to the right, then we want the algorithm to flip immediately. + * If it is moving to the left, then we don't want it to flip until + * we traverse an entire pixel. + */ +#define BRESINITPGON(dy, x1, x2, xStart, d, m, m1, incr1, incr2) { \ + int dx; /* local storage */ \ +\ + /* \ + * if the edge is horizontal, then it is ignored \ + * and assumed not to be processed. Otherwise, do this stuff. \ + */ \ + if ((dy) != 0) { \ + xStart = (x1); \ + dx = (x2) - xStart; \ + if (dx < 0) { \ + m = dx / (dy); \ + m1 = m - 1; \ + incr1 = -2 * dx + 2 * (dy) * m1; \ + incr2 = -2 * dx + 2 * (dy) * m; \ + d = 2 * m * (dy) - 2 * dx - 2 * (dy); \ + } else { \ + m = dx / (dy); \ + m1 = m + 1; \ + incr1 = 2 * dx - 2 * (dy) * m1; \ + incr2 = 2 * dx - 2 * (dy) * m; \ + d = -2 * m * (dy) + 2 * dx; \ + } \ + } \ +} + + +#define BRESINCRPGON(d, minval, m, m1, incr1, incr2) { \ + if (m1 > 0) { \ + if (d > 0) { \ + minval += m1; \ + d += incr1; \ + } \ + else { \ + minval += m; \ + d += incr2; \ + } \ + } else {\ + if (d >= 0) { \ + minval += m1; \ + d += incr1; \ + } \ + else { \ + minval += m; \ + d += incr2; \ + } \ + } \ +} + + + +/* + * This structure contains all of the information needed + * to run the bresenham algorithm. + * The variables may be hardcoded into the declarations + * instead of using this structure to make use of + * register declarations. + */ +typedef struct { + int minor; /* minor axis */ + int d; /* decision variable */ + int m, m1; /* slope and slope+1 */ + int incr1, incr2; /* error increments */ +} BRESINFO; + + +#define BRESINITPGONSTRUCT(dmaj, min1, min2, bres) \ + BRESINITPGON(dmaj, min1, min2, bres.minor, bres.d, \ + bres.m, bres.m1, bres.incr1, bres.incr2) + +#define BRESINCRPGONSTRUCT(bres) \ + BRESINCRPGON(bres.d, bres.minor, bres.m, bres.m1, bres.incr1, bres.incr2) + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miscstruct.h (revision 51223) @@ -0,0 +1,80 @@ +/* $Xorg: miscstruct.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/miscstruct.h,v 3.4 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef MISCSTRUCT_H +#define MISCSTRUCT_H 1 + +#include "misc.h" +#include +#include "gc.h" + +typedef xPoint DDXPointRec; + +typedef struct _Box { + short x1, y1, x2, y2; +} BoxRec; + +typedef union _DevUnion { + pointer ptr; + long val; + unsigned long uval; + RegionPtr (*fptr)( + DrawablePtr /* pSrcDrawable */, + DrawablePtr /* pDstDrawable */, + GCPtr /* pGC */, + int /* srcx */, + int /* srcy */, + int /* width */, + int /* height */, + int /* dstx */, + int /* dsty */, + unsigned long /* bitPlane */); +} DevUnion; + +#endif /* MISCSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispans.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispans.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispans.h (revision 51223) @@ -0,0 +1,117 @@ +/* $XFree86: xc/programs/Xserver/mi/mispans.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ +/*********************************************************** + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1989 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: mispans.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +typedef struct { + int count; /* number of spans */ + DDXPointPtr points; /* pointer to list of start points */ + int *widths; /* pointer to list of widths */ +} Spans; + +typedef struct { + int size; /* Total number of *Spans allocated */ + int count; /* Number of *Spans actually in group */ + Spans *group; /* List of Spans */ + int ymin, ymax; /* Min, max y values encountered */ +} SpanGroup; + +/* Initialize SpanGroup. MUST BE DONE before use. */ +extern void miInitSpanGroup( + SpanGroup * /*spanGroup*/ +); + +/* Add a Spans to a SpanGroup. The spans MUST BE in y-sorted order */ +extern void miAppendSpans( + SpanGroup * /*spanGroup*/, + SpanGroup * /*otherGroup*/, + Spans * /*spans*/ +); + +/* Paint a span group, possibly with some overlap */ +extern void miFillSpanGroup( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + SpanGroup * /*spanGroup*/ +); + +/* Paint a span group, insuring that each pixel is painted at most once */ +extern void miFillUniqueSpanGroup( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + SpanGroup * /*spanGroup*/ +); + +/* Free up data in a span group. MUST BE DONE or you'll suffer memory leaks */ +extern void miFreeSpanGroup( + SpanGroup * /*spanGroup*/ +); + +extern void miSubtractSpans( + SpanGroup * /*spanGroup*/, + Spans * /*sub*/ +); + +extern void miDisposeSpanGroup( + SpanGroup * /*spanGroup*/ +); + +extern int miClipSpans( + RegionPtr /*prgnDst*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + DDXPointPtr /*pptNew*/, + int * /*pwidthNew*/, + int /*fSorted*/ +); + +/* Rops which must use span groups */ +#define miSpansCarefulRop(rop) (((rop) & 0xc) == 0x8 || ((rop) & 0x3) == 0x2) +#define miSpansEasyRop(rop) (!miSpansCarefulRop(rop)) + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misprite.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misprite.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/misprite.h (revision 51223) @@ -0,0 +1,96 @@ +/* + * misprite.h + * + * software-sprite/sprite drawing interface spec + * + * mi versions of these routines exist. + */ + +/* $Xorg: misprite.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/misprite.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ + +typedef struct { + Bool (*RealizeCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/ +); + Bool (*UnrealizeCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/ +); + Bool (*PutUpCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + int /*x*/, + int /*y*/, + unsigned long /*source*/, + unsigned long /*mask*/ +); + Bool (*SaveUnderCursor)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/ +); + Bool (*RestoreUnderCursor)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/ +); + Bool (*MoveCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*dx*/, + int /*dy*/, + unsigned long /*source*/, + unsigned long /*mask*/ +); + Bool (*ChangeSave)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*dx*/, + int /*dy*/ +); + +} miSpriteCursorFuncRec, *miSpriteCursorFuncPtr; + +extern Bool miSpriteInitialize( + ScreenPtr /*pScreen*/, + miSpriteCursorFuncPtr /*cursorFuncs*/, + miPointerScreenFuncPtr /*screenFuncs*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispritest.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispritest.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mispritest.h (revision 51223) @@ -0,0 +1,134 @@ +/* + * mispritest.h + * + * mi sprite structures + */ + +/* $Xorg: mispritest.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mispritest.h,v 1.4 2001/01/17 22:37:07 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _MISPRITEST_H_ +#define _MISPRITEST_H_ + +# include "misprite.h" +#ifdef RENDER +# include "picturestr.h" +#endif +# include "damage.h" + +/* + * per screen information + */ + +typedef struct { + /* screen procedures */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + SourceValidateProcPtr SourceValidate; + + /* window procedures */ + CopyWindowProcPtr CopyWindow; + + /* backing store procedures */ + SaveDoomedAreasProcPtr SaveDoomedAreas; + + /* colormap procedures */ + InstallColormapProcPtr InstallColormap; + StoreColorsProcPtr StoreColors; + + /* os layer procedures */ + ScreenBlockHandlerProcPtr BlockHandler; + + CursorPtr pCursor; + int x; /* cursor hotspot */ + int y; + BoxRec saved; /* saved area from the screen */ + Bool isUp; /* cursor in frame buffer */ + Bool shouldBeUp; /* cursor should be displayed */ + WindowPtr pCacheWin; /* window the cursor last seen in */ + Bool isInCacheWin; + Bool checkPixels; /* check colormap collision */ + xColorItem colors[2]; + ColormapPtr pInstalledMap; + ColormapPtr pColormap; + VisualPtr pVisual; + miSpriteCursorFuncPtr funcs; + DamagePtr pDamage; /* damage tracking structure */ +} miSpriteScreenRec, *miSpriteScreenPtr; + +#define SOURCE_COLOR 0 +#define MASK_COLOR 1 + +#define miSpriteIsUpTRUE(pScreen, pScreenPriv) if (!pScreenPriv->isUp) { \ + pScreenPriv->isUp = TRUE; \ + DamageRegister (&(*pScreen->GetScreenPixmap) (pScreen)->drawable, pScreenPriv->pDamage); \ +} + +#define miSpriteIsUpFALSE(pScreen, pScreenPriv) if (pScreenPriv->isUp) { \ + DamageUnregister (&(*pScreen->GetScreenPixmap) (pScreen)->drawable, pScreenPriv->pDamage); \ + pScreenPriv->isUp = FALSE; \ +} + +/* + * Overlap BoxPtr and Box elements + */ +#define BOX_OVERLAP(pCbox,X1,Y1,X2,Y2) \ + (((pCbox)->x1 <= (X2)) && ((X1) <= (pCbox)->x2) && \ + ((pCbox)->y1 <= (Y2)) && ((Y1) <= (pCbox)->y2)) + +/* + * Overlap BoxPtr, origins, and rectangle + */ +#define ORG_OVERLAP(pCbox,xorg,yorg,x,y,w,h) \ + BOX_OVERLAP((pCbox),(x)+(xorg),(y)+(yorg),(x)+(xorg)+(w),(y)+(yorg)+(h)) + +/* + * Overlap BoxPtr, origins and RectPtr + */ +#define ORGRECT_OVERLAP(pCbox,xorg,yorg,pRect) \ + ORG_OVERLAP((pCbox),(xorg),(yorg),(pRect)->x,(pRect)->y, \ + (int)((pRect)->width), (int)((pRect)->height)) +/* + * Overlap BoxPtr and horizontal span + */ +#define SPN_OVERLAP(pCbox,y,x,w) BOX_OVERLAP((pCbox),(x),(y),(x)+(w),(y)) + +#define LINE_SORT(x1,y1,x2,y2) \ +{ int _t; \ + if (x1 > x2) { _t = x1; x1 = x2; x2 = _t; } \ + if (y1 > y2) { _t = y1; y1 = y2; y2 = _t; } } + +#define LINE_OVERLAP(pCbox,x1,y1,x2,y2,lw2) \ + BOX_OVERLAP((pCbox), (x1)-(lw2), (y1)-(lw2), (x2)+(lw2), (y2)+(lw2)) + +#endif /* _MISPRITEST_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mistruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mistruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mistruct.h (revision 51223) @@ -0,0 +1,65 @@ +/* $Xorg: mistruct.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef MISTRUCT_H +#define MISTRUCT_H + +#include "mi.h" +#include "regionstr.h" + +/* information about dashes */ +typedef struct _miDash { + DDXPointRec pt; + int e1, e2; /* keep these, so we don't have to do it again */ + int e; /* bresenham error term for this point on line */ + int which; + int newLine;/* 0 if part of same original line as previous dash */ + } miDashRec; + +#endif /* MISTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mivalidate.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mivalidate.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mivalidate.h (revision 51223) @@ -0,0 +1,55 @@ +/* $Xorg: mivalidate.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/* + +Copyright 1993, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86$ */ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIVALIDATE_H +#define MIVALIDATE_H + +#include "regionstr.h" + +typedef union _Validate { + struct BeforeValidate { + DDXPointRec oldAbsCorner; /* old window position */ + RegionPtr borderVisible; /* visible region of border, */ + /* non-null when size changes */ + Bool resized; /* unclipped winSize has changed - */ + /* don't call SaveDoomedAreas */ + } before; + struct AfterValidate { + RegionRec exposed; /* exposed regions, absolute pos */ + RegionRec borderExposed; + } after; +} ValidateRec; + +#endif /* MIVALIDATE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miwideline.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miwideline.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/miwideline.h (revision 51223) @@ -0,0 +1,224 @@ +/* $Xorg: miwideline.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/* + +Copyright 1988, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/miwideline.h,v 1.11 2001/10/25 12:03:47 alanh Exp $ */ + +/* Author: Keith Packard, MIT X Consortium */ + +#include "mispans.h" +#include "mifpoly.h" /* for ICEIL */ + +/* + * interface data to span-merging polygon filler + */ + +typedef struct _SpanData { + SpanGroup fgGroup, bgGroup; +} SpanDataRec, *SpanDataPtr; + +#define AppendSpanGroup(pGC, pixel, spanPtr, spanData) { \ + SpanGroup *group, *othergroup = NULL; \ + if (pixel == pGC->fgPixel) \ + { \ + group = &spanData->fgGroup; \ + if (pGC->lineStyle == LineDoubleDash) \ + othergroup = &spanData->bgGroup; \ + } \ + else \ + { \ + group = &spanData->bgGroup; \ + othergroup = &spanData->fgGroup; \ + } \ + miAppendSpans (group, othergroup, spanPtr); \ +} + +/* + * Polygon edge description for integer wide-line routines + */ + +typedef struct _PolyEdge { + int height; /* number of scanlines to process */ + int x; /* starting x coordinate */ + int stepx; /* fixed integral dx */ + int signdx; /* variable dx sign */ + int e; /* initial error term */ + int dy; + int dx; +} PolyEdgeRec, *PolyEdgePtr; + +#define SQSECANT 108.856472512142 /* 1/sin^2(11/2) - miter limit constant */ + +/* + * types for general polygon routines + */ + +typedef struct _PolyVertex { + double x, y; +} PolyVertexRec, *PolyVertexPtr; + +typedef struct _PolySlope { + int dx, dy; + double k; /* x0 * dy - y0 * dx */ +} PolySlopeRec, *PolySlopePtr; + +/* + * Line face description for caps/joins + */ + +typedef struct _LineFace { + double xa, ya; + int dx, dy; + int x, y; + double k; +} LineFaceRec, *LineFacePtr; + +/* + * macros for polygon fillers + */ + +#define MIPOLYRELOADLEFT if (!left_height && left_count) { \ + left_height = left->height; \ + left_x = left->x; \ + left_stepx = left->stepx; \ + left_signdx = left->signdx; \ + left_e = left->e; \ + left_dy = left->dy; \ + left_dx = left->dx; \ + --left_count; \ + ++left; \ + } + +#define MIPOLYRELOADRIGHT if (!right_height && right_count) { \ + right_height = right->height; \ + right_x = right->x; \ + right_stepx = right->stepx; \ + right_signdx = right->signdx; \ + right_e = right->e; \ + right_dy = right->dy; \ + right_dx = right->dx; \ + --right_count; \ + ++right; \ + } + +#define MIPOLYSTEPLEFT left_x += left_stepx; \ + left_e += left_dx; \ + if (left_e > 0) \ + { \ + left_x += left_signdx; \ + left_e -= left_dy; \ + } + +#define MIPOLYSTEPRIGHT right_x += right_stepx; \ + right_e += right_dx; \ + if (right_e > 0) \ + { \ + right_x += right_signdx; \ + right_e -= right_dy; \ + } + +#define MILINESETPIXEL(pDrawable, pGC, pixel, oldPixel) { \ + oldPixel = pGC->fgPixel; \ + if (pixel != oldPixel) { \ + DoChangeGC (pGC, GCForeground, (XID *) &pixel, FALSE); \ + ValidateGC (pDrawable, pGC); \ + } \ +} +#define MILINERESETPIXEL(pDrawable, pGC, pixel, oldPixel) { \ + if (pixel != oldPixel) { \ + DoChangeGC (pGC, GCForeground, (XID *) &oldPixel, FALSE); \ + ValidateGC (pDrawable, pGC); \ + } \ +} + +extern void miFillPolyHelper( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + unsigned long /*pixel*/, + SpanDataPtr /*spanData*/, + int /*y*/, + int /*overall_height*/, + PolyEdgePtr /*left*/, + PolyEdgePtr /*right*/, + int /*left_count*/, + int /*right_count*/ +); +extern int miRoundJoinFace( + LineFacePtr /*face*/, + PolyEdgePtr /*edge*/, + Bool * /*leftEdge*/ +); + +extern void miRoundJoinClip( + LineFacePtr /*pLeft*/, + LineFacePtr /*pRight*/, + PolyEdgePtr /*edge1*/, + PolyEdgePtr /*edge2*/, + int * /*y1*/, + int * /*y2*/, + Bool * /*left1*/, + Bool * /*left2*/ +); + +extern int miRoundCapClip( + LineFacePtr /*face*/, + Bool /*isInt*/, + PolyEdgePtr /*edge*/, + Bool * /*leftEdge*/ +); + +extern void miLineProjectingCap( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + unsigned long /*pixel*/, + SpanDataPtr /*spanData*/, + LineFacePtr /*face*/, + Bool /*isLeft*/, + double /*xorg*/, + double /*yorg*/, + Bool /*isInt*/ +); + +extern SpanDataPtr miSetupSpanData( + GCPtr /*pGC*/, + SpanDataPtr /*spanData*/, + int /*npt*/ +); + +extern void miCleanupSpanData( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + SpanDataPtr /*spanData*/ +); + +extern int miPolyBuildEdge(double x0, double y0, double k, int dx, int dy, + int xi, int yi, int left, PolyEdgePtr edge); +extern int miPolyBuildPoly(PolyVertexPtr vertices, PolySlopePtr slopes, + int count, int xi, int yi, PolyEdgePtr left, + PolyEdgePtr right, int *pnleft, int *pnright, + int *h); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mizerarc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mizerarc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mizerarc.h (revision 51223) @@ -0,0 +1,134 @@ +/* $XFree86: xc/programs/Xserver/mi/mizerarc.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ +/************************************************************ + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +********************************************************/ + +/* $Xorg: mizerarc.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +typedef struct { + int x; + int y; + int mask; +} miZeroArcPtRec; + +typedef struct { + int x, y, k1, k3, a, b, d, dx, dy; + int alpha, beta; + int xorg, yorg; + int xorgo, yorgo; + int w, h; + int initialMask; + miZeroArcPtRec start, altstart, end, altend; + int firstx, firsty; + int startAngle, endAngle; +} miZeroArcRec; + +#define miCanZeroArc(arc) (((arc)->width == (arc)->height) || \ + (((arc)->width <= 800) && ((arc)->height <= 800))) + +#define MIARCSETUP() \ + x = info.x; \ + y = info.y; \ + k1 = info.k1; \ + k3 = info.k3; \ + a = info.a; \ + b = info.b; \ + d = info.d; \ + dx = info.dx; \ + dy = info.dy + +#define MIARCOCTANTSHIFT(clause) \ + if (a < 0) \ + { \ + if (y == info.h) \ + { \ + d = -1; \ + a = b = k1 = 0; \ + } \ + else \ + { \ + dx = (k1 << 1) - k3; \ + k1 = dx - k1; \ + k3 = -k3; \ + b = b + a - (k1 >> 1); \ + d = b + ((-a) >> 1) - d + (k3 >> 3); \ + if (dx < 0) \ + a = -((-dx) >> 1) - a; \ + else \ + a = (dx >> 1) - a; \ + dx = 0; \ + dy = 1; \ + clause \ + } \ + } + +#define MIARCSTEP(move1,move2) \ + b -= k1; \ + if (d < 0) \ + { \ + x += dx; \ + y += dy; \ + a += k1; \ + d += b; \ + move1 \ + } \ + else \ + { \ + x++; \ + y++; \ + a += k3; \ + d -= a; \ + move2 \ + } + +#define MIARCCIRCLESTEP(clause) \ + b -= k1; \ + x++; \ + if (d < 0) \ + { \ + a += k1; \ + d += b; \ + } \ + else \ + { \ + y++; \ + a += k3; \ + d -= a; \ + clause \ + } + +/* mizerarc.c */ + +extern Bool miZeroArcSetup( + xArc * /*arc*/, + miZeroArcRec * /*info*/, + Bool /*ok360*/ +); + +extern DDXPointPtr miZeroArcPts( + xArc * /*arc*/, + DDXPointPtr /*pts*/ +); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/modinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/modinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/modinit.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XdotOrg: xc/programs/Xserver/Xext/extmod/modinit.h,v 1.3 2005/04/20 12:25:13 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/Xext/extmod/modinit.h,v 1.1 2003/07/16 01:38:33 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef INITARGS +#define INITARGS void +#endif + +#ifdef SHAPE +extern void ShapeExtensionInit(INITARGS); +#define _SHAPE_SERVER_ /* don't want Xlib structures */ +#include +#endif + +#ifdef MULTIBUFFER +extern void MultibufferExtensionInit(INITARGS); +#define _MULTIBUF_SERVER_ /* don't want Xlib structures */ +#include +#endif + +#ifdef MITMISC +extern void MITMiscExtensionInit(INITARGS); +#define _MITMISC_SERVER_ +#include +#endif + +#ifdef XTEST +extern void XTestExtensionInit(INITARGS); +#define _XTEST_SERVER_ +#include +#include +#endif + +#if 1 +extern void XTestExtension1Init(INITARGS); +#endif + +#ifdef BIGREQS +extern void BigReqExtensionInit(INITARGS); +#include +#endif + +#ifdef XSYNC +extern void SyncExtensionInit(INITARGS); +#define _SYNC_SERVER +#include +#include +#endif + +#ifdef SCREENSAVER +extern void ScreenSaverExtensionInit (INITARGS); +#include +#endif + +#ifdef XCMISC +extern void XCMiscExtensionInit(INITARGS); +#include +#endif + +#ifdef XF86VIDMODE +extern void XFree86VidModeExtensionInit(INITARGS); +#define _XF86VIDMODE_SERVER_ +#include +#endif + +#ifdef XF86MISC +extern void XFree86MiscExtensionInit(INITARGS); +#define _XF86MISC_SERVER_ +#define _XF86MISC_SAVER_COMPAT_ +#include +#endif + +#ifdef XFreeXDGA +extern void XFree86DGAExtensionInit(INITARGS); +extern void XFree86DGARegister(INITARGS); +#define _XF86DGA_SERVER_ +#include +#endif + +#ifdef DPMSExtension +extern void DPMSExtensionInit(INITARGS); +#include +#endif + +#ifdef FONTCACHE +extern void FontCacheExtensionInit(INITARGS); +#define _FONTCACHE_SERVER_ +#include "fontcacheP.h" +#include "fontcachstr.h" +#endif + +#ifdef TOGCUP +extern void XcupExtensionInit(INITARGS); +#define _XCUP_SERVER_ +#include +#endif + +#ifdef EVI +extern void EVIExtensionInit(INITARGS); +#define _XEVI_SERVER_ +#include +#endif + +#ifdef XV +extern void XvExtensionInit(INITARGS); +extern void XvMCExtensionInit(INITARGS); +extern void XvRegister(INITARGS); +#include +#include +#endif + +#ifdef RES +extern void ResExtensionInit(INITARGS); +#include +#endif + +#ifdef SHM +extern void ShmExtensionInit(INITARGS); +#include +extern void ShmSetPixmapFormat( + ScreenPtr pScreen, + int format); +extern void ShmRegisterFuncs( + ScreenPtr pScreen, + ShmFuncsPtr funcs); +#endif + +#if 1 +extern void SecurityExtensionInit(INITARGS); +#endif + +#if 1 +extern void XagExtensionInit(INITARGS); +#endif + +#if 1 +extern void XpExtensionInit(INITARGS); +#endif + +#if 1 +extern void PanoramiXExtensionInit(int argc, char *argv[]); +#endif + +#if 1 +extern void XkbExtensionInit(INITARGS); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/monitor-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/monitor-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/monitor-cfg.h (revision 51223) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/monitor-cfg.h,v 1.1 2000/04/04 22:37:00 dawes Exp $ + */ + +#include "config.h" + +#ifndef _xf86cfg_monitor_h +#define _xf86cfg_monitor_h + +/* + * Prototypes + */ +XtPointer MonitorConfig(XtPointer); +void MonitorLayout(XF86SetupInfo*); +void MonitorVidtune(XF86SetupInfo*); +int string_to_parser_range(char*, parser_range*, int); +#define PARSER_RANGE_SIZE 256 +/* string must have at least 256 bytes */ +int parser_range_to_string(char*, parser_range*, int); + +#endif /* _xf86cfg_monitor_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mouse-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mouse-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/mouse-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +#include "config.h" + +#ifndef _xf86cfg_mouse_h +#define _xf86cfg_mouse_h + +/* + * Prototypes + */ +XtPointer MouseConfig(XtPointer); +void MouseDeviceAndProtocol(XF86SetupInfo*); + +#endif /* _xf86cfg_mouse_h */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/msp3430.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/msp3430.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/msp3430.h (revision 51223) @@ -0,0 +1,126 @@ +#ifndef __MSP3430_H__ +#define __MSP3430_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int standard; + int connector; + int mode; + + CARD8 hardware_version, major_revision, product_code, rom_version; +#ifdef MSP_DEBUG + CARD8 registers_present[256]; +#endif + + CARD16 chip_id; + CARD8 chip_family; + Bool recheck; /*reinitialization needed after channel change */ + CARD8 c_format; /*current state of audio format */ + CARD16 c_standard; /*current state of standard register */ + CARD8 c_source; /*current state of source register */ + CARD8 c_matrix; /*current state of matrix register */ + CARD8 c_fmmatrix; /*current state of fmmatrix register */ + int c_mode; /* current state of mode for autoswitchimg */ + CARD8 volume; + } MSP3430Rec, * MSP3430Ptr; + + +#define MSP3430_ADDR_1 0x80 +#define MSP3430_ADDR_2 0x84 +#define MSP3430_ADDR_3 0x88 + +#define MSP3430_PAL 1 +#define MSP3430_NTSC 2 +#define MSP3430_PAL_DK1 (0x100 | MSP3430_PAL) +#define MSP3430_SECAM 3 + +#define MSP3430_CONNECTOR_1 1 /* tuner on AIW cards */ +#define MSP3430_CONNECTOR_2 2 /* SVideo on AIW cards */ +#define MSP3430_CONNECTOR_3 3 /* composite on AIW cards */ + +#define MSP3430_ADDR(a) ((a)->d.SlaveAddr) + +#define MSP3430_FAST_MUTE 0xFF +/* a handy volume transform function, -1000..1000 -> 0x01..0x7F */ +#define MSP3430_VOLUME(value) (0x01+(0x7F-0x01)*log(value+1001)/log(2001)) + +/*----------------------------------------------------------*/ + +/* MSP chip families */ +#define MSPFAMILY_UNKNOWN 0 +#define MSPFAMILY_34x0D 1 +#define MSPFAMILY_34x5D 2 +#define MSPFAMILY_34x0G 3 +#define MSPFAMILY_34x5G 4 + +/* values for MSP standard */ +#define MSPSTANDARD_UNKNOWN 0x00 +#define MSPSTANDARD_AUTO 0x01 +#define MSPSTANDARD_FM_M 0x02 +#define MSPSTANDARD_FM_BG 0x03 +#define MSPSTANDARD_FM_DK1 0x04 +#define MSPSTANDARD_FM_DK2 0x04 +#define MSPSTANDARD_NICAM_BG 0x08 +#define MSPSTANDARD_NICAM_L 0x09 +#define MSPSTANDARD_NICAM_I 0x0A +#define MSPSTANDARD_NICAM_DK 0x0B + +/* values for MSP format */ +#define MSPFORMAT_UNKNOWN 0x00 +#define MSPFORMAT_FM 0x10 +#define MSPFORMAT_1xFM 0x00|MSPFORMAT_FM +#define MSPFORMAT_2xFM 0x01|MSPFORMAT_FM +#define MSPFORMAT_NICAM 0x20 +#define MSPFORMAT_NICAM_FM 0x00|MSPFORMAT_NICAM +#define MSPFORMAT_NICAM_AM 0x01|MSPFORMAT_NICAM +#define MSPFORMAT_SCART 0x30 + +/* values for MSP mode */ +#define MSPMODE_UNKNOWN 0 +/* automatic modes */ +#define MSPMODE_STEREO_AB 1 +#define MSPMODE_STEREO_A 2 +#define MSPMODE_STEREO_B 3 +/* forced modes */ +#define MSPMODE_MONO 4 +#define MSPMODE_STEREO 5 +#define MSPMODE_AB 6 +#define MSPMODE_A 7 +#define MSPMODE_B 8 +/*----------------------------------------------------------*/ + +void InitMSP3430(MSP3430Ptr m); +MSP3430Ptr DetectMSP3430(I2CBusPtr b, I2CSlaveAddr addr); +void ResetMSP3430(MSP3430Ptr m); +void MSP3430SetVolume (MSP3430Ptr m, CARD8 value); +void MSP3430SetSAP (MSP3430Ptr m, int mode); + +#define MSP3430SymbolsList \ + "InitMSP3430", \ + "DetectMSP3430", \ + "ResetMSP3430", \ + "MSP3430SetVolume", \ + "MSP3430SetSAP" + +#ifdef XFree86LOADER + +#define xf86_DetectMSP3430 ((MSP3430Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("DetectMSP3430")) +#define xf86_ResetMSP3430 ((void (*)(MSP3430Ptr))LoaderSymbol("ResetMSP3430")) +#define xf86_MSP3430SetVolume ((void (*)(MSP3430Ptr, CARD8))LoaderSymbol("MSP3430SetVolume")) +#define xf86_MSP3430SetSAP ((void (*)(MSP3430Ptr, int))LoaderSymbol("MSP3430SetSAP")) +#define xf86_InitMSP3430 ((void (*)(MSP3430Ptr))LoaderSymbol("InitMSP3430")) + +#else + +#define xf86_DetectMSP3430 DetectMSP3430 +#define xf86_ResetMSP3430 ResetMSP3430 +#define xf86_MSP3430SetVolume MSP3430SetVolume +#define xf86_MSP3430SetSAP MSP3430SetSAP +#define xf86_InitMSP3430 InitMSP3430 + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opaque.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opaque.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opaque.h (revision 51223) @@ -0,0 +1,83 @@ +/* $Xorg: opaque.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/include/opaque.h,v 1.13 2003/07/24 13:50:25 eich Exp $ */ + +#ifndef OPAQUE_H +#define OPAQUE_H + +#include + +#include "globals.h" + +extern char *defaultTextFont; +extern char *defaultCursorFont; +extern int MaxClients; +extern volatile char isItTimeToYield; +extern volatile char dispatchException; + +/* bit values for dispatchException */ +#define DE_RESET 1 +#define DE_TERMINATE 2 +#define DE_PRIORITYCHANGE 4 /* set when a client's priority changes */ + +extern CARD32 TimeOutValue; +extern int ScreenSaverBlanking; +extern int ScreenSaverAllowExposures; +extern int defaultScreenSaverBlanking; +extern int defaultScreenSaverAllowExposures; +extern int argcGlobal; +extern char **argvGlobal; +extern char *display; + +extern int defaultBackingStore; +extern Bool disableBackingStore; +extern Bool enableBackingStore; +extern Bool disableSaveUnders; +extern Bool PartialNetwork; +#ifndef NOLOGOHACK +extern int logoScreenSaver; +#endif +#ifdef RLIMIT_DATA +extern int limitDataSpace; +#endif +#ifdef RLIMIT_STACK +extern int limitStackSpace; +#endif +#ifdef RLIMIT_NOFILE +extern int limitNoFile; +#endif +extern Bool permitOldBugs; +extern Bool defeatAccessControl; +extern long maxBigRequestSize; +extern Bool blackRoot; + +extern Bool CoreDump; + + +#endif /* OPAQUE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opendev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opendev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/opendev.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/opendev.h,v 3.1 1996/04/15 11:18:58 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef OPENDEV_H +#define OPENDEV_H 1 + +int +SProcXOpenDevice( + ClientPtr /* client */ + ); + +int +ProcXOpenDevice( + ClientPtr /* client */ + ); + +void +SRepXOpenDevice ( + ClientPtr /* client */, + int /* size */, + xOpenDeviceReply * /* rep */ + ); + +#endif /* OPENDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ops.h (revision 51223) @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/options.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/options.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/options.h (revision 51223) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/options.h,v 1.6 2001/06/01 18:43:50 tsi Exp $ + */ + +#include "config.h" +#ifdef USE_MODULES +#include "loader.h" +#endif + +/* + * Prototypes + */ +#ifdef USE_MODULES +void OptionsPopup(XF86OptionPtr*, char*, OptionInfoPtr); +void ModuleOptionsPopup(Widget, XtPointer, XtPointer); +#else +void OptionsPopup(XF86OptionPtr*); +#endif +void OptionsCancelAction(Widget, XEvent*, String*, Cardinal*); +void ModuleOptionsCancelAction(Widget, XEvent*, String*, Cardinal*); +char *GetOptionDescription(char *module, char *option); +Bool InitializeOptionsDatabase(void); + +void CreateOptionsShell(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/os.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/os.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/os.h (revision 51223) @@ -0,0 +1,546 @@ +/* $XFree86: xc/programs/Xserver/include/os.h,v 3.54 2003/10/30 21:21:06 herrb Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: os.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef OS_H +#define OS_H + +#include "misc.h" +#define ALLOCATE_LOCAL_FALLBACK(_size) Xalloc((unsigned long)(_size)) +#define DEALLOCATE_LOCAL_FALLBACK(_ptr) Xfree((pointer)(_ptr)) +#include +#ifndef IN_MODULE +#include +#else +#include "xf86_ansic.h" +#endif + +#define NullFID ((FID) 0) + +#define SCREEN_SAVER_ON 0 +#define SCREEN_SAVER_OFF 1 +#define SCREEN_SAVER_FORCER 2 +#define SCREEN_SAVER_CYCLE 3 + +#ifndef MAX_REQUEST_SIZE +#define MAX_REQUEST_SIZE 65535 +#endif +#ifndef MAX_BIG_REQUEST_SIZE +#define MAX_BIG_REQUEST_SIZE 4194303 +#endif + +typedef pointer FID; +typedef struct _FontPathRec *FontPathPtr; +typedef struct _NewClientRec *NewClientPtr; + +#ifndef xalloc +#define xnfalloc(size) XNFalloc((unsigned long)(size)) +#define xnfcalloc(_num, _size) XNFcalloc((unsigned long)(_num)*(unsigned long)(_size)) +#define xnfrealloc(ptr, size) XNFrealloc((pointer)(ptr), (unsigned long)(size)) + +#define xalloc(size) Xalloc((unsigned long)(size)) +#define xcalloc(_num, _size) Xcalloc((unsigned long)(_num)*(unsigned long)(_size)) +#define xrealloc(ptr, size) Xrealloc((pointer)(ptr), (unsigned long)(size)) +#define xfree(ptr) Xfree((pointer)(ptr)) +#define xstrdup(s) Xstrdup(s) +#define xnfstrdup(s) XNFstrdup(s) +#endif + +#ifndef IN_MODULE +#ifdef __SCO__ +#include +#endif +#include +#endif + +/* have to put $(SIGNAL_DEFINES) in DEFINES in Imakefile to get this right */ +#ifdef SIGNALRETURNSINT +#define SIGVAL int +#else +#define SIGVAL void +#endif + +extern Bool OsDelayInitColors; +extern void (*OsVendorVErrorFProc)(const char *, va_list args); + +extern int WaitForSomething( + int* /*pClientsReady*/ +); + +#ifdef LBX +#define ReadRequestFromClient(client) ((client)->readRequest(client)) +extern int StandardReadRequestFromClient(ClientPtr /*client*/); + +extern int ClientConnectionNumber(ClientPtr /*client*/); +#else +extern int ReadRequestFromClient(ClientPtr /*client*/); +#endif /* LBX */ + +extern Bool InsertFakeRequest( + ClientPtr /*client*/, + char* /*data*/, + int /*count*/); + +extern void ResetCurrentRequest(ClientPtr /*client*/); + +extern void FlushAllOutput(void); + +extern void FlushIfCriticalOutputPending(void); + +extern void SetCriticalOutputPending(void); + +extern int WriteToClient(ClientPtr /*who*/, int /*count*/, char* /*buf*/); + +extern void ResetOsBuffers(void); + +extern void InitConnectionLimits(void); + +extern void CreateWellKnownSockets(void); + +extern void ResetWellKnownSockets(void); + +extern void CloseWellKnownConnections(void); + +extern XID AuthorizationIDOfClient(ClientPtr /*client*/); + +extern char *ClientAuthorized( + ClientPtr /*client*/, + unsigned int /*proto_n*/, + char* /*auth_proto*/, + unsigned int /*string_n*/, + char* /*auth_string*/); + +extern Bool EstablishNewConnections( + ClientPtr /*clientUnused*/, + pointer /*closure*/); + +extern void CheckConnections(void); + +extern void CloseDownConnection(ClientPtr /*client*/); + +extern void AddEnabledDevice(int /*fd*/); + +extern void RemoveEnabledDevice(int /*fd*/); + +extern void OnlyListenToOneClient(ClientPtr /*client*/); + +extern void ListenToAllClients(void); + +extern void IgnoreClient(ClientPtr /*client*/); + +extern void AttendClient(ClientPtr /*client*/); + +extern void MakeClientGrabImpervious(ClientPtr /*client*/); + +extern void MakeClientGrabPervious(ClientPtr /*client*/); + +#ifdef LBX +extern void CloseDownFileDescriptor(ClientPtr /* client */); +#endif + +extern void AvailableClientInput(ClientPtr /* client */); + +extern CARD32 GetTimeInMillis(void); + +extern void AdjustWaitForDelay( + pointer /*waitTime*/, + unsigned long /*newdelay*/); + +typedef struct _OsTimerRec *OsTimerPtr; + +typedef CARD32 (*OsTimerCallback)( + OsTimerPtr /* timer */, + CARD32 /* time */, + pointer /* arg */); + +extern void TimerInit(void); + +extern Bool TimerForce(OsTimerPtr /* timer */); + +#define TimerAbsolute (1<<0) +#define TimerForceOld (1<<1) + +extern OsTimerPtr TimerSet( + OsTimerPtr /* timer */, + int /* flags */, + CARD32 /* millis */, + OsTimerCallback /* func */, + pointer /* arg */); + +extern void TimerCheck(void); +extern void TimerCancel(OsTimerPtr /* pTimer */); +extern void TimerFree(OsTimerPtr /* pTimer */); + +extern void SetScreenSaverTimer(void); +extern void FreeScreenSaverTimer(void); + +#ifdef DPMSExtension +extern void SetDPMSTimers(void); +extern void FreeDPMSTimers(void); +#endif + +extern SIGVAL AutoResetServer(int /*sig*/); + +extern SIGVAL GiveUp(int /*sig*/); + +extern void UseMsg(void); + +extern void InitGlobals(void); + +extern void ProcessCommandLine(int /*argc*/, char* /*argv*/[]); + +extern int set_font_authorizations( + char ** /* authorizations */, + int * /*authlen */, + pointer /* client */); + +#ifndef _HAVE_XALLOC_DECLS +#define _HAVE_XALLOC_DECLS +extern pointer Xalloc(unsigned long /*amount*/); +extern pointer Xcalloc(unsigned long /*amount*/); +extern pointer Xrealloc(pointer /*ptr*/, unsigned long /*amount*/); +extern void Xfree(pointer /*ptr*/); +#endif + +extern pointer XNFalloc(unsigned long /*amount*/); +extern pointer XNFcalloc(unsigned long /*amount*/); +extern pointer XNFrealloc(pointer /*ptr*/, unsigned long /*amount*/); + +extern void OsInitAllocator(void); + +extern char *Xstrdup(const char *s); +extern char *XNFstrdup(const char *s); +extern char *Xprintf(const char *fmt, ...); +extern char *Xvprintf(const char *fmt, va_list va); +extern char *XNFprintf(const char *fmt, ...); +extern char *XNFvprintf(const char *fmt, va_list va); + +typedef SIGVAL (*OsSigHandlerPtr)(int /* sig */); + +extern OsSigHandlerPtr OsSignal(int /* sig */, OsSigHandlerPtr /* handler */); + +extern int auditTrailLevel; + +#ifdef SERVER_LOCK +extern void LockServer(void); +extern void UnlockServer(void); +#endif + +extern int OsLookupColor( + int /*screen*/, + char * /*name*/, + unsigned /*len*/, + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/); + +extern void OsInit(void); + +extern void OsCleanup(Bool); + +extern void OsVendorFatalError(void); + +extern void OsVendorInit(void); + +extern int OsInitColors(void); + +void OsBlockSignals (void); + +void OsReleaseSignals (void); + +#if !defined(WIN32) && !defined(__UNIXOS2__) +extern int System(char *); +extern pointer Popen(char *, char *); +extern int Pclose(pointer); +extern pointer Fopen(char *, char *); +extern int Fclose(pointer); +#else +#define System(a) system(a) +#define Popen(a,b) popen(a,b) +#define Pclose(a) pclose(a) +#define Fopen(a,b) fopen(a,b) +#define Fclose(a) fclose(a) +#endif + +extern void CheckUserParameters(int argc, char **argv, char **envp); +extern void CheckUserAuthorization(void); + +extern int AddHost( + ClientPtr /*client*/, + int /*family*/, + unsigned /*length*/, + pointer /*pAddr*/); + +extern Bool ForEachHostInFamily ( + int /*family*/, + Bool (* /*func*/ )( + unsigned char * /* addr */, + short /* len */, + pointer /* closure */), + pointer /*closure*/); + +extern int RemoveHost( + ClientPtr /*client*/, + int /*family*/, + unsigned /*length*/, + pointer /*pAddr*/); + +extern int GetHosts( + pointer * /*data*/, + int * /*pnHosts*/, + int * /*pLen*/, + BOOL * /*pEnabled*/); + +typedef struct sockaddr * sockaddrPtr; + +extern int InvalidHost(sockaddrPtr /*saddr*/, int /*len*/, ClientPtr client); + +extern int LocalClient(ClientPtr /* client */); + +extern int LocalClientCred(ClientPtr, int *, int *); + +extern int ChangeAccessControl(ClientPtr /*client*/, int /*fEnabled*/); + +extern int GetAccessControl(void); + + +extern void AddLocalHosts(void); + +extern void ResetHosts(char *display); + +extern void EnableLocalHost(void); + +extern void DisableLocalHost(void); + +extern void AccessUsingXdmcp(void); + +extern void DefineSelf(int /*fd*/); + +extern void AugmentSelf(pointer /*from*/, int /*len*/); + +extern void InitAuthorization(char * /*filename*/); + +/* extern int LoadAuthorization(void); */ + +extern void RegisterAuthorizations(void); + +extern XID AuthorizationToID ( + unsigned short name_length, + char *name, + unsigned short data_length, + char *data); + +extern int AuthorizationFromID ( + XID id, + unsigned short *name_lenp, + char **namep, + unsigned short *data_lenp, + char **datap); + +extern XID CheckAuthorization( + unsigned int /*namelength*/, + char * /*name*/, + unsigned int /*datalength*/, + char * /*data*/, + ClientPtr /*client*/, + char ** /*reason*/ +); + +extern void ResetAuthorization(void); + +extern int RemoveAuthorization ( + unsigned short name_length, + char *name, + unsigned short data_length, + char *data); + +extern int AddAuthorization( + unsigned int /*name_length*/, + char * /*name*/, + unsigned int /*data_length*/, + char * /*data*/); + +extern XID GenerateAuthorization( + unsigned int /* name_length */, + char * /* name */, + unsigned int /* data_length */, + char * /* data */, + unsigned int * /* data_length_return */, + char ** /* data_return */); + +#ifdef COMMANDLINE_CHALLENGED_OPERATING_SYSTEMS +extern void ExpandCommandLine(int * /*pargc*/, char *** /*pargv*/); +#endif + +extern void ddxInitGlobals(void); + +extern int ddxProcessArgument(int /*argc*/, char * /*argv*/ [], int /*i*/); + +extern void ddxUseMsg(void); + +/* + * idiom processing stuff + */ + +extern xReqPtr PeekNextRequest(xReqPtr req, ClientPtr client, Bool readmore); + +extern void SkipRequests(xReqPtr req, ClientPtr client, int numskipped); + +/* int ReqLen(xReq *req, ClientPtr client) + * Given a pointer to a *complete* request, return its length in bytes. + * Note that if the request is a big request (as defined in the Big + * Requests extension), the macro lies by returning 4 less than the + * length that it actually occupies in the request buffer. This is so you + * can blindly compare the length with the various sz_ constants + * in Xproto.h without having to know/care about big requests. + */ +#define ReqLen(_pxReq, _client) \ + ((_pxReq->length ? \ + (_client->swapped ? lswaps(_pxReq->length) : _pxReq->length) \ + : ((_client->swapped ? \ + lswapl(((CARD32*)_pxReq)[1]) : ((CARD32*)_pxReq)[1])-1) \ + ) << 2) + +/* otherReqTypePtr CastxReq(xReq *req, otherReqTypePtr) + * Cast the given request to one of type otherReqTypePtr to access + * fields beyond the length field. + */ +#define CastxReq(_pxReq, otherReqTypePtr) \ + (_pxReq->length ? (otherReqTypePtr)_pxReq \ + : (otherReqTypePtr)(((CARD32*)_pxReq)+1)) + +/* stuff for SkippedRequestsCallback */ +extern CallbackListPtr SkippedRequestsCallback; +typedef struct { + xReqPtr req; + ClientPtr client; + int numskipped; +} SkippedRequestInfoRec; + +/* stuff for ReplyCallback */ +extern CallbackListPtr ReplyCallback; +typedef struct { + ClientPtr client; + pointer replyData; + unsigned long dataLenBytes; + unsigned long bytesRemaining; + Bool startOfReply; +} ReplyInfoRec; + +/* stuff for FlushCallback */ +extern CallbackListPtr FlushCallback; + +extern void AbortDDX(void); +extern void ddxGiveUp(void); +extern int TimeSinceLastInputEvent(void); + +/* Logging. */ +typedef enum _LogParameter { + XLOG_FLUSH, + XLOG_SYNC, + XLOG_VERBOSITY, + XLOG_FILE_VERBOSITY +} LogParameter; + +/* Flags for log messages. */ +typedef enum { + X_PROBED, /* Value was probed */ + X_CONFIG, /* Value was given in the config file */ + X_DEFAULT, /* Value is a default */ + X_CMDLINE, /* Value was given on the command line */ + X_NOTICE, /* Notice */ + X_ERROR, /* Error message */ + X_WARNING, /* Warning message */ + X_INFO, /* Informational message */ + X_NONE, /* No prefix */ + X_NOT_IMPLEMENTED, /* Not implemented */ + X_UNKNOWN = -1 /* unknown -- this must always be last */ +} MessageType; + +/* XXX Need to check which GCC versions have the format(printf) attribute. */ +#if defined(__GNUC__) && \ + ((__GNUC__ > 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ > 4))) +#define _printf_attribute(a,b) __attribute((format(__printf__,a,b))) +#else +#define _printf_attribute(a,b) /**/ +#endif + +extern const char *LogInit(const char *fname, const char *backup); +extern void LogClose(void); +extern Bool LogSetParameter(LogParameter param, int value); +extern void LogVWrite(int verb, const char *f, va_list args); +extern void LogWrite(int verb, const char *f, ...) _printf_attribute(2,3); +extern void LogVMessageVerb(MessageType type, int verb, const char *format, + va_list args); +extern void LogMessageVerb(MessageType type, int verb, const char *format, + ...) _printf_attribute(3,4); +extern void LogMessage(MessageType type, const char *format, ...) + _printf_attribute(2,3); +extern void FreeAuditTimer(void); +extern void AuditF(const char *f, ...) _printf_attribute(1,2); +extern void VAuditF(const char *f, va_list args); +extern void FatalError(const char *f, ...) _printf_attribute(1,2) +#if defined(__GNUC__) && \ + ((__GNUC__ > 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ > 4))) +__attribute((noreturn)) +#endif +; + +extern void VErrorF(const char *f, va_list args); +extern void ErrorF(const char *f, ...) _printf_attribute(1,2); +extern void Error(char *str); +extern void LogPrintMarkers(void); + +#if defined(NEED_SNPRINTF) && !defined(IN_MODULE) +extern int snprintf(char *str, size_t size, const char *format, ...) + _printf_attribute(3,4); +extern int vsnprintf(char *str, size_t size, const char *format, va_list ap); +#endif + +#endif /* OS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/osdep.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/osdep.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/osdep.h (revision 51223) @@ -0,0 +1,358 @@ +/* $XFree86: xc/programs/Xserver/os/osdep.h,v 3.17 2002/05/31 18:46:06 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: osdep.h,v 1.5 2001/02/09 02:05:23 xorgcvs Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _OSDEP_H_ +#define _OSDEP_H_ 1 + +#define BOTIMEOUT 200 /* in milliseconds */ +#define BUFSIZE 4096 +#define BUFWATERMARK 8192 +#ifndef MAXBUFSIZE +#define MAXBUFSIZE (1 << 22) +#endif + +#include + +#ifndef sgi /* SGI defines OPEN_MAX in a useless way */ +#ifndef X_NOT_POSIX +#ifdef _POSIX_SOURCE +#include +#else +#define _POSIX_SOURCE +#include +#undef _POSIX_SOURCE +#endif +#else /* X_NOT_POSIX */ +#ifdef WIN32 +#define _POSIX_ +#include +#undef _POSIX_ +#endif +#endif /* X_NOT_POSIX */ +#endif + +#ifdef __QNX__ +#define NOFILES_MAX 256 +#endif +#ifndef OPEN_MAX +#ifdef SVR4 +#define OPEN_MAX 256 +#else +#include +#ifndef OPEN_MAX +#if defined(NOFILE) && !defined(NOFILES_MAX) +#define OPEN_MAX NOFILE +#else +#if !defined(__UNIXOS2__) && !defined(WIN32) +#define OPEN_MAX NOFILES_MAX +#else +#define OPEN_MAX 256 +#endif +#endif +#endif +#endif +#endif + +#include + +/* + * MAXSOCKS is used only for initialising MaxClients when no other method + * like sysconf(_SC_OPEN_MAX) is not supported. + */ + +#if OPEN_MAX <= 256 +#define MAXSOCKS (OPEN_MAX - 1) +#else +#define MAXSOCKS 256 +#endif + +/* MAXSELECT is the number of fds that select() can handle */ +#define MAXSELECT (sizeof(fd_set) * NBBY) + +#if !defined(hpux) && !defined(SVR4) && !defined(SYSV) +#define HAS_GETDTABLESIZE +#endif + +#include + +typedef Bool (*ValidatorFunc)(ARRAY8Ptr Auth, ARRAY8Ptr Data, int packet_type); +typedef Bool (*GeneratorFunc)(ARRAY8Ptr Auth, ARRAY8Ptr Data, int packet_type); +typedef Bool (*AddAuthorFunc)(unsigned name_length, char *name, unsigned data_length, char *data); + +typedef struct _connectionInput { + struct _connectionInput *next; + char *buffer; /* contains current client input */ + char *bufptr; /* pointer to current start of data */ + int bufcnt; /* count of bytes in buffer */ + int lenLastReq; + int size; +} ConnectionInput, *ConnectionInputPtr; + +typedef struct _connectionOutput { + struct _connectionOutput *next; + int size; + unsigned char *buf; + int count; +#ifdef LBX + Bool nocompress; +#endif +} ConnectionOutput, *ConnectionOutputPtr; + +#ifdef K5AUTH +typedef struct _k5_state { + int stageno; /* current stage of auth protocol */ + pointer srvcreds; /* server credentials */ + pointer srvname; /* server principal name */ + pointer ktname; /* key table: principal-key pairs */ + pointer skey; /* session key */ +} k5_state; +#endif + +#ifdef LBX +typedef struct _LbxProxy *OsProxyPtr; +#endif + +struct _osComm; + +#define AuthInitArgs void +typedef void (*AuthInitFunc) (AuthInitArgs); + +#define AuthAddCArgs unsigned short data_length, char *data, XID id +typedef int (*AuthAddCFunc) (AuthAddCArgs); + +#define AuthCheckArgs unsigned short data_length, char *data, ClientPtr client, char **reason +typedef XID (*AuthCheckFunc) (AuthCheckArgs); + +#define AuthFromIDArgs XID id, unsigned short *data_lenp, char **datap +typedef int (*AuthFromIDFunc) (AuthFromIDArgs); + +#define AuthGenCArgs unsigned data_length, char *data, XID id, unsigned *data_length_return, char **data_return +typedef XID (*AuthGenCFunc) (AuthGenCArgs); + +#define AuthRemCArgs unsigned short data_length, char *data +typedef int (*AuthRemCFunc) (AuthRemCArgs); + +#define AuthRstCArgs void +typedef int (*AuthRstCFunc) (AuthRstCArgs); + +#define AuthToIDArgs unsigned short data_length, char *data +typedef XID (*AuthToIDFunc) (AuthToIDArgs); + +typedef void (*OsCloseFunc)(ClientPtr); + +typedef int (*OsFlushFunc)(ClientPtr who, struct _osComm * oc, char* extraBuf, int extraCount); + +typedef struct _osComm { + int fd; + ConnectionInputPtr input; + ConnectionOutputPtr output; + XID auth_id; /* authorization id */ +#ifdef K5AUTH + k5_state authstate; /* state of setup auth conversation */ +#endif + CARD32 conn_time; /* timestamp if not established, else 0 */ + struct _XtransConnInfo *trans_conn; /* transport connection object */ +#ifdef LBX + OsProxyPtr proxy; + ConnectionInputPtr largereq; + OsCloseFunc Close; + OsFlushFunc Flush; +#endif +} OsCommRec, *OsCommPtr; + +#ifdef LBX +#define FlushClient(who, oc, extraBuf, extraCount) \ + (*(oc)->Flush)(who, oc, extraBuf, extraCount) +extern int StandardFlushClient( + ClientPtr /*who*/, + OsCommPtr /*oc*/, + char* /*extraBuf*/, + int /*extraCount*/ +); +extern int LbxFlushClient(ClientPtr /*who*/, OsCommPtr /*oc*/, + char * /*extraBuf*/, int /*extraCount*/); +#else +extern int FlushClient( + ClientPtr /*who*/, + OsCommPtr /*oc*/, + char* /*extraBuf*/, + int /*extraCount*/ +); +#endif + +extern void FreeOsBuffers( + OsCommPtr /*oc*/ +); + +#include "dix.h" + +extern ConnectionInputPtr AllocateInputBuffer(void); + +extern ConnectionOutputPtr AllocateOutputBuffer(void); + +extern fd_set AllSockets; +extern fd_set AllClients; +extern fd_set LastSelectMask; +extern fd_set WellKnownConnections; +extern fd_set EnabledDevices; +extern fd_set ClientsWithInput; +extern fd_set ClientsWriteBlocked; +extern fd_set OutputPending; +extern fd_set IgnoredClientsWithInput; + +#ifndef WIN32 +extern int *ConnectionTranslation; +#else +extern int GetConnectionTranslation(int conn); +extern void SetConnectionTranslation(int conn, int client); +extern void ClearConnectionTranslation(); +#endif + +extern Bool NewOutputPending; +extern Bool AnyClientsWriteBlocked; +extern Bool CriticalOutputPending; + +extern int timesThisConnection; +extern ConnectionInputPtr FreeInputs; +extern ConnectionOutputPtr FreeOutputs; +extern OsCommPtr AvailableInput; + +extern WorkQueuePtr workQueue; + +/* added by raphael */ +#ifdef WIN32 +typedef long int fd_mask; +#endif +#define ffs mffs +extern int mffs(fd_mask); + +/* in auth.c */ +extern void GenerateRandomData (int len, char *buf); + +/* in mitauth.c */ +extern XID MitCheckCookie (AuthCheckArgs); +extern XID MitGenerateCookie (AuthGenCArgs); +extern XID MitToID (AuthToIDArgs); +extern int MitAddCookie (AuthAddCArgs); +extern int MitFromID (AuthFromIDArgs); +extern int MitRemoveCookie (AuthRemCArgs); +extern int MitResetCookie (AuthRstCArgs); + +/* in xdmauth.c */ +#ifdef HASXDMAUTH +extern XID XdmCheckCookie (AuthCheckArgs); +extern XID XdmToID (AuthToIDArgs); +extern int XdmAddCookie (AuthAddCArgs); +extern int XdmFromID (AuthFromIDArgs); +extern int XdmRemoveCookie (AuthRemCArgs); +extern int XdmResetCookie (AuthRstCArgs); +#endif + +/* in rpcauth.c */ +#ifdef SECURE_RPC +extern void SecureRPCInit (AuthInitArgs); +extern XID SecureRPCCheck (AuthCheckArgs); +extern XID SecureRPCToID (AuthToIDArgs); +extern int SecureRPCAdd (AuthAddCArgs); +extern int SecureRPCFromID (AuthFromIDArgs); +extern int SecureRPCRemove (AuthRemCArgs); +extern int SecureRPCReset (AuthRstCArgs); +#endif + +/* in k5auth.c */ +#ifdef K5AUTH +extern XID K5Check (AuthCheckArgs); +extern XID K5ToID (AuthToIDArgs); +extern int K5Add (AuthAddCArgs); +extern int K5FromID (AuthFromIDArgs); +extern int K5Remove (AuthRemCArgs); +extern int K5Reset (AuthRstCArgs); +#endif + +/* in secauth.c */ +extern XID AuthSecurityCheck (AuthCheckArgs); + +/* in xdmcp.c */ +extern void XdmcpUseMsg (void); +extern int XdmcpOptions(int argc, char **argv, int i); +extern void XdmcpSetAuthentication (ARRAY8Ptr name); +extern void XdmcpRegisterConnection ( + int type, + char *address, + int addrlen); +extern void XdmcpRegisterAuthorizations (void); +extern void XdmcpRegisterAuthorization (char *name, int namelen); +extern void XdmcpRegisterDisplayClass (char *name, int length); +extern void XdmcpInit (void); +extern void XdmcpReset (void); +extern void XdmcpOpenDisplay(int sock); +extern void XdmcpCloseDisplay(int sock); +extern void XdmcpRegisterAuthentication ( + char *name, + int namelen, + char *data, + int datalen, + ValidatorFunc Validator, + GeneratorFunc Generator, + AddAuthorFunc AddAuth); +extern int XdmcpCheckAuthentication (ARRAY8Ptr Name, ARRAY8Ptr Data, int packet_type); +extern int XdmcpAddAuthorization (ARRAY8Ptr name, ARRAY8Ptr data); + +struct sockaddr_in; +extern void XdmcpRegisterBroadcastAddress (struct sockaddr_in *addr); + +#ifdef HASXDMAUTH +extern void XdmAuthenticationInit (char *cookie, int cookie_length); +#endif + +#endif /* _OSDEP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiX.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiX.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiX.h (revision 51223) @@ -0,0 +1,115 @@ +/* $TOG: panoramiX.h /main/4 1998/03/17 06:51:02 kaleb $ */ +/* $XdotOrg: xc/programs/Xserver/Xext/panoramiX.h,v 1.3 2005/04/20 12:25:12 daniels Exp $ */ +/***************************************************************** + +Copyright (c) 1991, 1997 Digital Equipment Corporation, Maynard, Massachusetts. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +DIGITAL EQUIPMENT CORPORATION BE LIABLE FOR ANY CLAIM, DAMAGES, INCLUDING, +BUT NOT LIMITED TO CONSEQUENTIAL OR INCIDENTAL DAMAGES, OR OTHER LIABILITY, +WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of Digital Equipment Corporation +shall not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from Digital +Equipment Corporation. + +******************************************************************/ + +/* $XFree86: xc/programs/Xserver/Xext/panoramiX.h,v 1.5 2001/01/03 02:54:17 keithp Exp $ */ + +/* THIS IS NOT AN X PROJECT TEAM SPECIFICATION */ + +/* + * PanoramiX definitions + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PANORAMIX_H_ +#define _PANORAMIX_H_ + +#include +#include "gcstruct.h" + + +typedef struct _PanoramiXData { + int x; + int y; + int width; + int height; +} PanoramiXData; + +typedef struct _PanoramiXInfo { + XID id ; +} PanoramiXInfo; + +typedef struct { + PanoramiXInfo info[MAXSCREENS]; + RESTYPE type; + union { + struct { + char visibility; + char class; + char root; + } win; + struct { + Bool shared; + } pix; +#ifdef RENDER + struct { + Bool root; + } pict; +#endif + char raw_data[4]; + } u; +} PanoramiXRes; + +#define FOR_NSCREENS_FORWARD(j) for(j = 0; j < PanoramiXNumScreens; j++) +#define FOR_NSCREENS_BACKWARD(j) for(j = PanoramiXNumScreens - 1; j >= 0; j--) +#define FOR_NSCREENS(j) FOR_NSCREENS_FORWARD(j) + +#define BREAK_IF(a) if ((a)) break +#define IF_RETURN(a,b) if ((a)) return (b) + +#define FORCE_ROOT(a) { \ + int _j; \ + for (_j = PanoramiXNumScreens - 1; _j; _j--) \ + if ((a).root == WindowTable[_j]->drawable.id) \ + break; \ + (a).rootX += panoramiXdataPtr[_j].x; \ + (a).rootY += panoramiXdataPtr[_j].y; \ + (a).root = WindowTable[0]->drawable.id; \ +} + +#define FORCE_WIN(a) { \ + if ((win = PanoramiXFindIDOnAnyScreen(XRT_WINDOW, a))) { \ + (a) = win->info[0].id; /* Real ID */ \ + } \ +} + +#define FORCE_CMAP(a) { \ + if ((win = PanoramiXFindIDOnAnyScreen(XRT_COLORMAP, a))) { \ + (a) = win->info[0].id; /* Real ID */ \ + } \ +} + +#define IS_SHARED_PIXMAP(r) (((r)->type == XRT_PIXMAP) && (r)->u.pix.shared) + +#define SKIP_FAKE_WINDOW(a) if(!LookupIDByType(a, XRT_WINDOW)) return + +#endif /* _PANORAMIX_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXh.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXh.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXh.h (revision 51223) @@ -0,0 +1,78 @@ +/* $XFree86: xc/programs/Xserver/Xext/panoramiXh.h,v 1.2 2003/09/13 21:33:03 dawes Exp $ */ + +/* + * Server dispatcher function replacements + */ + +extern int PanoramiXCreateWindow(ClientPtr client); +extern int PanoramiXChangeWindowAttributes(ClientPtr client); +extern int PanoramiXDestroyWindow(ClientPtr client); +extern int PanoramiXDestroySubwindows(ClientPtr client); +extern int PanoramiXChangeSaveSet(ClientPtr client); +extern int PanoramiXReparentWindow(ClientPtr client); +extern int PanoramiXMapWindow(ClientPtr client); +extern int PanoramiXMapSubwindows(ClientPtr client); +extern int PanoramiXUnmapWindow(ClientPtr client); +extern int PanoramiXUnmapSubwindows(ClientPtr client); +extern int PanoramiXConfigureWindow(ClientPtr client); +extern int PanoramiXCirculateWindow(ClientPtr client); +extern int PanoramiXGetGeometry(ClientPtr client); +extern int PanoramiXTranslateCoords(ClientPtr client); +extern int PanoramiXCreatePixmap(ClientPtr client); +extern int PanoramiXFreePixmap(ClientPtr client); +extern int PanoramiXCreateGC(ClientPtr client); +extern int PanoramiXChangeGC(ClientPtr client); +extern int PanoramiXCopyGC(ClientPtr client); +extern int PanoramiXCopyColormapAndFree(ClientPtr client); +extern int PanoramiXSetDashes(ClientPtr client); +extern int PanoramiXSetClipRectangles(ClientPtr client); +extern int PanoramiXFreeGC(ClientPtr client); +extern int PanoramiXClearToBackground(ClientPtr client); +extern int PanoramiXCopyArea(ClientPtr client); +extern int PanoramiXCopyPlane(ClientPtr client); +extern int PanoramiXPolyPoint(ClientPtr client); +extern int PanoramiXPolyLine(ClientPtr client); +extern int PanoramiXPolySegment(ClientPtr client); +extern int PanoramiXPolyRectangle(ClientPtr client); +extern int PanoramiXPolyArc(ClientPtr client); +extern int PanoramiXFillPoly(ClientPtr client); +extern int PanoramiXPolyFillArc(ClientPtr client); +extern int PanoramiXPolyFillRectangle(ClientPtr client); +extern int PanoramiXPutImage(ClientPtr client); +extern int PanoramiXGetImage(ClientPtr client); +extern int PanoramiXPolyText8(ClientPtr client); +extern int PanoramiXPolyText16(ClientPtr client); +extern int PanoramiXImageText8(ClientPtr client); +extern int PanoramiXImageText16(ClientPtr client); +extern int PanoramiXCreateColormap(ClientPtr client); +extern int PanoramiXFreeColormap(ClientPtr client); +extern int PanoramiXInstallColormap(ClientPtr client); +extern int PanoramiXUninstallColormap(ClientPtr client); +extern int PanoramiXAllocColor(ClientPtr client); +extern int PanoramiXAllocNamedColor(ClientPtr client); +extern int PanoramiXAllocColorCells(ClientPtr client); +extern int PanoramiXStoreNamedColor(ClientPtr client); +extern int PanoramiXFreeColors(ClientPtr client); +extern int PanoramiXStoreColors(ClientPtr client); +extern int PanoramiXAllocColorPlanes(ClientPtr client); + +#define PROC_EXTERN(pfunc) extern int pfunc(ClientPtr) + +PROC_EXTERN(ProcPanoramiXQueryVersion); +PROC_EXTERN(ProcPanoramiXGetState); +PROC_EXTERN(ProcPanoramiXGetScreenCount); +PROC_EXTERN(ProcPanoramiXGetScreenSize); + +PROC_EXTERN(ProcXineramaQueryScreens); +PROC_EXTERN(ProcXineramaIsActive); +extern Bool XineramaCreateGC(GCPtr pGC); + +extern int SProcPanoramiXDispatch(ClientPtr client); + +extern char *ConnectionInfo; +extern int connBlockScreenStart; +extern xConnSetupPrefix connSetupPrefix; + +extern ScreenInfo *GlobalScrInfo; +extern int (* SavedProcVector[256]) (ClientPtr client); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXsrv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXsrv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/panoramiXsrv.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86: xc/programs/Xserver/Xext/panoramiXsrv.h,v 1.8 2001/08/01 00:44:44 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PANORAMIXSRV_H_ +#define _PANORAMIXSRV_H_ + +#include "panoramiX.h" + +extern int PanoramiXNumScreens; +extern PanoramiXData *panoramiXdataPtr; +extern int PanoramiXPixWidth; +extern int PanoramiXPixHeight; +extern RegionRec PanoramiXScreenRegion; +extern XID *PanoramiXVisualTable; + +extern void PanoramiXConsolidate(void); +extern Bool PanoramiXCreateConnectionBlock(void); +extern PanoramiXRes * PanoramiXFindIDByScrnum(RESTYPE, XID, int); +extern PanoramiXRes * PanoramiXFindIDOnAnyScreen(RESTYPE, XID); +extern WindowPtr PanoramiXChangeWindow(int, WindowPtr); +extern Bool XineramaRegisterConnectionBlockCallback(void (*func)(void)); +extern int XineramaDeleteResource(pointer, XID); + +extern void XineramaReinitData(ScreenPtr); + +extern RegionRec XineramaScreenRegions[MAXSCREENS]; + +extern unsigned long XRC_DRAWABLE; +extern unsigned long XRT_WINDOW; +extern unsigned long XRT_PIXMAP; +extern unsigned long XRT_GC; +extern unsigned long XRT_COLORMAP; + +extern void XineramaGetImageData( + DrawablePtr *pDrawables, + int left, + int top, + int width, + int height, + unsigned int format, + unsigned long planemask, + char *data, + int pitch, + Bool isRoot +); + +#endif /* _PANORAMIXSRV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/parser.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/parser.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/parser.h (revision 51223) @@ -0,0 +1,88 @@ +/* A Bison parser, made by GNU Bison 1.875c. */ + +/* Skeleton parser for Yacc-like parsing with Bison, + Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* As a special exception, when this file is copied by Bison into a + Bison output file, you may use that output file without restriction. + This special exception was added by the Free Software Foundation + in version 1.24 of Bison. */ + +/* Tokens. */ +#ifndef YYTOKENTYPE +# define YYTOKENTYPE + /* Put the tokens into the symbol table, so that GDB and other debuggers + know about them. */ + enum yytokentype { + T_VIRTUAL = 258, + T_DISPLAY = 259, + T_WALL = 260, + T_OPTION = 261, + T_PARAM = 262, + T_STRING = 263, + T_DIMENSION = 264, + T_OFFSET = 265, + T_ORIGIN = 266, + T_COMMENT = 267, + T_LINE_COMMENT = 268 + }; +#endif +#define T_VIRTUAL 258 +#define T_DISPLAY 259 +#define T_WALL 260 +#define T_OPTION 261 +#define T_PARAM 262 +#define T_STRING 263 +#define T_DIMENSION 264 +#define T_OFFSET 265 +#define T_ORIGIN 266 +#define T_COMMENT 267 +#define T_LINE_COMMENT 268 + + + + +#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED) +#line 56 "parser.y" +typedef union YYSTYPE { + DMXConfigTokenPtr token; + DMXConfigStringPtr string; + DMXConfigNumberPtr number; + DMXConfigPairPtr pair; + DMXConfigFullDimPtr fdim; + DMXConfigPartDimPtr pdim; + DMXConfigDisplayPtr display; + DMXConfigWallPtr wall; + DMXConfigOptionPtr option; + DMXConfigParamPtr param; + DMXConfigCommentPtr comment; + DMXConfigSubPtr subentry; + DMXConfigVirtualPtr virtual; + DMXConfigEntryPtr entry; +} YYSTYPE; +/* Line 1275 of yacc.c. */ +#line 80 "y.tab.h" +# define yystype YYSTYPE /* obsolescent; will be withdrawn */ +# define YYSTYPE_IS_DECLARED 1 +# define YYSTYPE_IS_TRIVIAL 1 +#endif + +extern YYSTYPE yylval; + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picture.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picture.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picture.h (revision 51223) @@ -0,0 +1,238 @@ +/* + * $XFree86: xc/programs/Xserver/render/picture.h,v 1.20tsi Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _PICTURE_H_ +#define _PICTURE_H_ + +typedef struct _DirectFormat *DirectFormatPtr; +typedef struct _PictFormat *PictFormatPtr; +typedef struct _Picture *PicturePtr; + +/* + * While the protocol is generous in format support, the + * sample implementation allows only packed RGB and GBR + * representations for data to simplify software rendering, + */ +#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \ + ((type) << 16) | \ + ((a) << 12) | \ + ((r) << 8) | \ + ((g) << 4) | \ + ((b))) + +/* + * gray/color formats use a visual index instead of argb + */ +#define PICT_VISFORMAT(bpp,type,vi) (((bpp) << 24) | \ + ((type) << 16) | \ + ((vi))) + +#define PICT_FORMAT_BPP(f) (((f) >> 24) ) +#define PICT_FORMAT_TYPE(f) (((f) >> 16) & 0xff) +#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f) +#define PICT_FORMAT_R(f) (((f) >> 8) & 0x0f) +#define PICT_FORMAT_G(f) (((f) >> 4) & 0x0f) +#define PICT_FORMAT_B(f) (((f) ) & 0x0f) +#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) +#define PICT_FORMAT_VIS(f) (((f) ) & 0xffff) + +#define PICT_TYPE_OTHER 0 +#define PICT_TYPE_A 1 +#define PICT_TYPE_ARGB 2 +#define PICT_TYPE_ABGR 3 +#define PICT_TYPE_COLOR 4 +#define PICT_TYPE_GRAY 5 + +#define PICT_FORMAT_COLOR(f) (PICT_FORMAT_TYPE(f) & 2) + +/* 32bpp formats */ +#define PICT_a8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8) +#define PICT_x8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_a8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8) +#define PICT_x8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8) + +/* 24bpp formats */ +#define PICT_r8g8b8 PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_b8g8r8 PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8) + +/* 16bpp formats */ +#define PICT_r5g6b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5) +#define PICT_b5g6r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5) + +#define PICT_a1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5) +#define PICT_x1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5) +#define PICT_a1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5) +#define PICT_x1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5) +#define PICT_a4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +#define PICT_x4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4) +#define PICT_a4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4) +#define PICT_x4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4) + +/* 8bpp formats */ +#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0) +#define PICT_r3g3b2 PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2) +#define PICT_b2g3r3 PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2) +#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2) +#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2) + +#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0) + +/* 4bpp formats */ +#define PICT_a4 PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0) +#define PICT_r1g2b1 PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1) +#define PICT_b1g2r1 PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1) +#define PICT_a1r1g1b1 PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1) +#define PICT_a1b1g1r1 PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1) + +#define PICT_c4 PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_g4 PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0) + +/* 1bpp formats */ +#define PICT_a1 PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0) + +#define PICT_g1 PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0) + +/* + * For dynamic indexed visuals (GrayScale and PseudoColor), these control the + * selection of colors allocated for drawing to Pictures. The default + * policy depends on the size of the colormap: + * + * Size Default Policy + * ---------------------------- + * < 64 PolicyMono + * < 256 PolicyGray + * 256 PolicyColor (only on PseudoColor) + * + * The actual allocation code lives in miindex.c, and so is + * austensibly server dependent, but that code does: + * + * PolicyMono Allocate no additional colors, use black and white + * PolicyGray Allocate 13 gray levels (11 cells used) + * PolicyColor Allocate a 4x4x4 cube and 13 gray levels (71 cells used) + * PolicyAll Allocate as big a cube as possible, fill with gray (all) + * + * Here's a picture to help understand how many colors are + * actually allocated (this is just the gray ramp): + * + * gray level + * all 0000 1555 2aaa 4000 5555 6aaa 8000 9555 aaaa bfff d555 eaaa ffff + * b/w 0000 ffff + * 4x4x4 5555 aaaa + * extra 1555 2aaa 4000 6aaa 8000 9555 bfff d555 eaaa + * + * The default colormap supplies two gray levels (black/white), the + * 4x4x4 cube allocates another two and nine more are allocated to fill + * in the 13 levels. When the 4x4x4 cube is not allocated, a total of + * 11 cells are allocated. + */ + +#define PictureCmapPolicyInvalid -1 +#define PictureCmapPolicyDefault 0 +#define PictureCmapPolicyMono 1 +#define PictureCmapPolicyGray 2 +#define PictureCmapPolicyColor 3 +#define PictureCmapPolicyAll 4 + +extern int PictureCmapPolicy; + +int PictureParseCmapPolicy (const char *name); + +extern int RenderErrBase; +extern int RenderClientPrivateIndex; + +/* Fixed point updates from Carl Worth, USC, Information Sciences Institute */ + +#if defined(WIN32) && !defined(__GNUC__) +typedef __int64 xFixed_32_32; +#else +# if defined (_LP64) || \ + defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef long xFixed_32_32; +# else +# if defined(__GNUC__) && \ + ((__GNUC__ > 2) || \ + ((__GNUC__ == 2) && defined(__GNUC_MINOR__) && (__GNUC_MINOR__ > 7))) +__extension__ +# endif +typedef long long int xFixed_32_32; +# endif +#endif + +typedef xFixed_32_32 xFixed_48_16; + +#define MAX_FIXED_48_16 ((xFixed_48_16) 0x7fffffff) +#define MIN_FIXED_48_16 (-((xFixed_48_16) 1 << 31)) + +typedef CARD32 xFixed_1_31; +typedef CARD32 xFixed_1_16; +typedef INT32 xFixed_16_16; + +/* + * An unadorned "xFixed" is the same as xFixed_16_16, + * (since it's quite common in the code) + */ +typedef xFixed_16_16 xFixed; +#define XFIXED_BITS 16 + +#define xFixedToInt(f) (int) ((f) >> XFIXED_BITS) +#define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) +#define xFixedE ((xFixed) 1) +#define xFixed1 (IntToxFixed(1)) +#define xFixed1MinusE (xFixed1 - xFixedE) +#define xFixedFrac(f) ((f) & xFixed1MinusE) +#define xFixedFloor(f) ((f) & ~xFixed1MinusE) +#define xFixedCeil(f) xFixedFloor((f) + xFixed1MinusE) + +#define xFixedFraction(f) ((f) & xFixed1MinusE) +#define xFixedMod2(f) ((f) & (xFixed1 | xFixed1MinusE)) + +/* whether 't' is a well defined not obviously empty trapezoid */ +#define xTrapezoidValid(t) ((t)->left.p1.y != (t)->left.p2.y && \ + (t)->right.p1.y != (t)->right.p2.y && \ + (int) ((t)->bottom - (t)->top) > 0) + +/* + * Standard NTSC luminance conversions: + * + * y = r * 0.299 + g * 0.587 + b * 0.114 + * + * Approximate this for a bit more speed: + * + * y = (r * 153 + g * 301 + b * 58) / 512 + * + * This gives 17 bits of luminance; to get 15 bits, lop the low two + */ + +#define CvtR8G8B8toY15(s) (((((s) >> 16) & 0xff) * 153 + \ + (((s) >> 8) & 0xff) * 301 + \ + (((s) ) & 0xff) * 58) >> 2) + +#endif /* _PICTURE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picturestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picturestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/picturestr.h (revision 51223) @@ -0,0 +1,654 @@ +/* + * $Id: picturestr.h,v 1.15 2005/12/09 18:35:21 ajax Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _PICTURESTR_H_ +#define _PICTURESTR_H_ + +#include "glyphstr.h" +#include "scrnintstr.h" +#include "resource.h" + +typedef struct _DirectFormat { + CARD16 red, redMask; + CARD16 green, greenMask; + CARD16 blue, blueMask; + CARD16 alpha, alphaMask; +} DirectFormatRec; + +typedef struct _IndexFormat { + VisualID vid; + ColormapPtr pColormap; + int nvalues; + xIndexValue *pValues; + void *devPrivate; +} IndexFormatRec; + +typedef struct _PictFormat { + CARD32 id; + CARD32 format; /* except bpp */ + unsigned char type; + unsigned char depth; + DirectFormatRec direct; + IndexFormatRec index; +} PictFormatRec; + +typedef struct _PictVector { + xFixed vector[3]; +} PictVector, *PictVectorPtr; + +typedef struct _PictTransform { + xFixed matrix[3][3]; +} PictTransform, *PictTransformPtr; + +#define PICT_GRADIENT_STOPTABLE_SIZE 1024 +#define SourcePictTypeSolidFill 0 +#define SourcePictTypeLinear 1 +#define SourcePictTypeRadial 2 +#define SourcePictTypeConical 3 + +typedef struct _PictSolidFill { + unsigned int type; + CARD32 color; +} PictSolidFill, *PictSolidFillPtr; + +typedef struct _PictGradientStop { + xFixed x; + xRenderColor color; +} PictGradientStop, *PictGradientStopPtr; + +typedef struct _PictGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; +} PictGradient, *PictGradientPtr; + +typedef struct _PictLinearGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + xPointFixed p1; + xPointFixed p2; +} PictLinearGradient, *PictLinearGradientPtr; + +typedef struct _PictRadialGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + double fx; + double fy; + double dx; + double dy; + double a; + double m; + double b; +} PictRadialGradient, *PictRadialGradientPtr; + +typedef struct _PictConicalGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + xPointFixed center; + xFixed angle; +} PictConicalGradient, *PictConicalGradientPtr; + +typedef union _SourcePict { + unsigned int type; + PictSolidFill solidFill; + PictGradient gradient; + PictLinearGradient linear; + PictRadialGradient radial; + PictConicalGradient conical; +} SourcePict, *SourcePictPtr; + +typedef struct _Picture { + DrawablePtr pDrawable; + PictFormatPtr pFormat; + CARD32 format; /* PICT_FORMAT */ + int refcnt; + CARD32 id; + PicturePtr pNext; /* chain on same drawable */ + + unsigned int repeat : 1; + unsigned int graphicsExposures : 1; + unsigned int subWindowMode : 1; + unsigned int polyEdge : 1; + unsigned int polyMode : 1; + unsigned int freeCompClip : 1; + unsigned int clientClipType : 2; + unsigned int componentAlpha : 1; + unsigned int repeatType : 2; + unsigned int unused : 21; + + PicturePtr alphaMap; + DDXPointRec alphaOrigin; + + DDXPointRec clipOrigin; + pointer clientClip; + + Atom dither; + + unsigned long stateChanges; + unsigned long serialNumber; + + RegionPtr pCompositeClip; + + DevUnion *devPrivates; + + PictTransform *transform; + + int filter; + xFixed *filter_params; + int filter_nparams; + SourcePictPtr pSourcePict; +} PictureRec; + +typedef Bool (*PictFilterValidateParamsProcPtr) (PicturePtr pPicture, int id, + xFixed *params, int nparams); +typedef struct { + char *name; + int id; + PictFilterValidateParamsProcPtr ValidateParams; +} PictFilterRec, *PictFilterPtr; + +#define PictFilterNearest 0 +#define PictFilterBilinear 1 + +#define PictFilterFast 2 +#define PictFilterGood 3 +#define PictFilterBest 4 + +#define PictFilterConvolution 5 + +typedef struct { + char *alias; + int alias_id; + int filter_id; +} PictFilterAliasRec, *PictFilterAliasPtr; + +typedef int (*CreatePictureProcPtr) (PicturePtr pPicture); +typedef void (*DestroyPictureProcPtr) (PicturePtr pPicture); +typedef int (*ChangePictureClipProcPtr) (PicturePtr pPicture, + int clipType, + pointer value, + int n); +typedef void (*DestroyPictureClipProcPtr)(PicturePtr pPicture); + +typedef int (*ChangePictureTransformProcPtr) (PicturePtr pPicture, + PictTransform *transform); + +typedef int (*ChangePictureFilterProcPtr) (PicturePtr pPicture, + int filter, + xFixed *params, + int nparams); + +typedef void (*DestroyPictureFilterProcPtr) (PicturePtr pPicture); + +typedef void (*ChangePictureProcPtr) (PicturePtr pPicture, + Mask mask); +typedef void (*ValidatePictureProcPtr) (PicturePtr pPicture, + Mask mask); +typedef void (*CompositeProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +typedef void (*GlyphsProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlists, + GlyphListPtr lists, + GlyphPtr *glyphs); + +typedef void (*CompositeRectsProcPtr) (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +typedef void (*RasterizeTrapezoidProcPtr)(PicturePtr pMask, + xTrapezoid *trap, + int x_off, + int y_off); + +typedef void (*TrapezoidsProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +typedef void (*TrianglesProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntri, + xTriangle *tris); + +typedef void (*TriStripProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +typedef void (*TriFanProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +typedef Bool (*InitIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat); + +typedef void (*CloseIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat); + +typedef void (*UpdateIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat, + int ndef, + xColorItem *pdef); + +typedef void (*AddTrapsProcPtr) (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntrap, + xTrap *traps); + +typedef void (*AddTrianglesProcPtr) (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntri, + xTriangle *tris); + +typedef struct _PictureScreen { + int totalPictureSize; + unsigned int *PicturePrivateSizes; + int PicturePrivateLen; + + PictFormatPtr formats; + PictFormatPtr fallback; + int nformats; + + CreatePictureProcPtr CreatePicture; + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + DestroyWindowProcPtr DestroyWindow; + CloseScreenProcPtr CloseScreen; + + StoreColorsProcPtr StoreColors; + + InitIndexedProcPtr InitIndexed; + CloseIndexedProcPtr CloseIndexed; + UpdateIndexedProcPtr UpdateIndexed; + + int subpixel; + + PictFilterPtr filters; + int nfilters; + PictFilterAliasPtr filterAliases; + int nfilterAliases; + + ChangePictureTransformProcPtr ChangePictureTransform; + ChangePictureFilterProcPtr ChangePictureFilter; + DestroyPictureFilterProcPtr DestroyPictureFilter; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; + + RasterizeTrapezoidProcPtr RasterizeTrapezoid; + + AddTrianglesProcPtr AddTriangles; + + AddTrapsProcPtr AddTraps; + +} PictureScreenRec, *PictureScreenPtr; + +extern int PictureScreenPrivateIndex; +extern int PictureWindowPrivateIndex; +extern RESTYPE PictureType; +extern RESTYPE PictFormatType; +extern RESTYPE GlyphSetType; + +#define GetPictureScreen(s) ((PictureScreenPtr) ((s)->devPrivates[PictureScreenPrivateIndex].ptr)) +#define GetPictureScreenIfSet(s) ((PictureScreenPrivateIndex != -1) ? GetPictureScreen(s) : NULL) +#define SetPictureScreen(s,p) ((s)->devPrivates[PictureScreenPrivateIndex].ptr = (pointer) (p)) +#define GetPictureWindow(w) ((PicturePtr) ((w)->devPrivates[PictureWindowPrivateIndex].ptr)) +#define SetPictureWindow(w,p) ((w)->devPrivates[PictureWindowPrivateIndex].ptr = (pointer) (p)) + +#define VERIFY_PICTURE(pPicture, pid, client, mode, err) {\ + pPicture = SecurityLookupIDByType(client, pid, PictureType, mode);\ + if (!pPicture) { \ + client->errorValue = pid; \ + return err; \ + } \ +} + +#define VERIFY_ALPHA(pPicture, pid, client, mode, err) {\ + if (pid == None) \ + pPicture = 0; \ + else { \ + VERIFY_PICTURE(pPicture, pid, client, mode, err); \ + } \ +} \ + +void +ResetPicturePrivateIndex (void); + +int +AllocatePicturePrivateIndex (void); + +Bool +AllocatePicturePrivate (ScreenPtr pScreen, int index2, unsigned int amount); + +Bool +PictureDestroyWindow (WindowPtr pWindow); + +Bool +PictureCloseScreen (int Index, ScreenPtr pScreen); + +void +PictureStoreColors (ColormapPtr pColormap, int ndef, xColorItem *pdef); + +Bool +PictureInitIndexedFormats (ScreenPtr pScreen); + +Bool +PictureSetSubpixelOrder (ScreenPtr pScreen, int subpixel); + +int +PictureGetSubpixelOrder (ScreenPtr pScreen); + +PictFormatPtr +PictureCreateDefaultFormats (ScreenPtr pScreen, int *nformatp); + +PictFormatPtr +PictureMatchVisual (ScreenPtr pScreen, int depth, VisualPtr pVisual); + +PictFormatPtr +PictureMatchFormat (ScreenPtr pScreen, int depth, CARD32 format); + +Bool +PictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); + +int +PictureGetFilterId (char *filter, int len, Bool makeit); + +char * +PictureGetFilterName (int id); + +int +PictureAddFilter (ScreenPtr pScreen, + char *filter, + PictFilterValidateParamsProcPtr ValidateParams); + +Bool +PictureSetFilterAlias (ScreenPtr pScreen, char *filter, char *alias); + +Bool +PictureSetDefaultFilters (ScreenPtr pScreen); + +void +PictureResetFilters (ScreenPtr pScreen); + +PictFilterPtr +PictureFindFilter (ScreenPtr pScreen, char *name, int len); + +int +SetPictureFilter (PicturePtr pPicture, char *name, int len, xFixed *params, int nparams); + +Bool +PictureFinishInit (void); + +void +SetPictureToDefaults (PicturePtr pPicture); + +PicturePtr +AllocatePicture (ScreenPtr pScreen); + +#if 0 +Bool +miPictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); +#endif + + +PicturePtr +CreatePicture (Picture pid, + DrawablePtr pDrawable, + PictFormatPtr pFormat, + Mask mask, + XID *list, + ClientPtr client, + int *error); + +int +ChangePicture (PicturePtr pPicture, + Mask vmask, + XID *vlist, + DevUnion *ulist, + ClientPtr client); + +int +SetPictureClipRects (PicturePtr pPicture, + int xOrigin, + int yOrigin, + int nRect, + xRectangle *rects); + +int +SetPictureClipRegion (PicturePtr pPicture, + int xOrigin, + int yOrigin, + RegionPtr pRegion); + +int +SetPictureTransform (PicturePtr pPicture, + PictTransform *transform); + +void +CopyPicture (PicturePtr pSrc, + Mask mask, + PicturePtr pDst); + +void +ValidatePicture(PicturePtr pPicture); + +int +FreePicture (pointer pPicture, + XID pid); + +int +FreePictFormat (pointer pPictFormat, + XID pid); + +void +CompositePicture (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +CompositeGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr lists, + GlyphPtr *glyphs); + +void +CompositeRects (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +void +CompositeTrapezoids (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +void +CompositeTriangles (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntriangles, + xTriangle *triangles); + +void +CompositeTriStrip (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoints, + xPointFixed *points); + +void +CompositeTriFan (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoints, + xPointFixed *points); + +Bool +PictureTransformPoint (PictTransformPtr transform, + PictVectorPtr vector); + +Bool +PictureTransformPoint3d (PictTransformPtr transform, + PictVectorPtr vector); + +void RenderExtensionInit (void); + +Bool +AnimCurInit (ScreenPtr pScreen); + +int +AnimCursorCreate (CursorPtr *cursors, CARD32 *deltas, int ncursor, CursorPtr *ppCursor); + +void +AddTraps (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntraps, + xTrap *traps); + +PicturePtr +CreateSolidPicture (Picture pid, + xRenderColor *color, + int *error); + +PicturePtr +CreateLinearGradientPicture (Picture pid, + xPointFixed *p1, + xPointFixed *p2, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +PicturePtr +CreateRadialGradientPicture (Picture pid, + xPointFixed *inner, + xPointFixed *outer, + xFixed innerRadius, + xFixed outerRadius, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +PicturePtr +CreateConicalGradientPicture (Picture pid, + xPointFixed *center, + xFixed angle, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +#ifdef PANORAMIX +void PanoramiXRenderInit (void); +void PanoramiXRenderReset (void); +#endif + +#endif /* _PICTURESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmap.h (revision 51223) @@ -0,0 +1,110 @@ +/* $Xorg: pixmap.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef PIXMAP_H +#define PIXMAP_H + +#include "misc.h" +#include "screenint.h" + +/* types for Drawable */ +#define DRAWABLE_WINDOW 0 +#define DRAWABLE_PIXMAP 1 +#define UNDRAWABLE_WINDOW 2 +#define DRAWABLE_BUFFER 3 + +/* flags to PaintWindow() */ +#define PW_BACKGROUND 0 +#define PW_BORDER 1 + +#define NullPixmap ((PixmapPtr)0) + +typedef struct _Drawable *DrawablePtr; +typedef struct _Pixmap *PixmapPtr; + +typedef union _PixUnion { + PixmapPtr pixmap; + unsigned long pixel; +} PixUnion; + +#define SamePixUnion(a,b,isPixel)\ + ((isPixel) ? (a).pixel == (b).pixel : (a).pixmap == (b).pixmap) + +#define EqualPixUnion(as, a, bs, b) \ + ((as) == (bs) && (SamePixUnion (a, b, as))) + +#define OnScreenDrawable(type) \ + ((type == DRAWABLE_WINDOW) || (type == DRAWABLE_BUFFER)) + +#define WindowDrawable(type) \ + ((type == DRAWABLE_WINDOW) || (type == UNDRAWABLE_WINDOW)) + +extern PixmapPtr GetScratchPixmapHeader( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/); + +extern void FreeScratchPixmapHeader( + PixmapPtr /*pPixmap*/); + +extern Bool CreateScratchPixmapsForScreen( + int /*scrnum*/); + +extern void FreeScratchPixmapsForScreen( + int /*scrnum*/); + +extern PixmapPtr AllocatePixmap( + ScreenPtr /*pScreen*/, + int /*pixDataSize*/); + +#endif /* PIXMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmapstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmapstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pixmapstr.h (revision 51223) @@ -0,0 +1,88 @@ +/* $Xorg: pixmapstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef PIXMAPSTRUCT_H +#define PIXMAPSTRUCT_H +#include "pixmap.h" +#include "screenint.h" +#include "regionstr.h" + +typedef struct _Drawable { + unsigned char type; /* DRAWABLE_ */ + unsigned char class; /* specific to type */ + unsigned char depth; + unsigned char bitsPerPixel; + unsigned long id; /* resource id */ + short x; /* window: screen absolute, pixmap: 0 */ + short y; /* window: screen absolute, pixmap: 0 */ + unsigned short width; + unsigned short height; + ScreenPtr pScreen; + unsigned long serialNumber; +} DrawableRec; + +/* + * PIXMAP -- device dependent + */ + +typedef struct _Pixmap { + DrawableRec drawable; + int refcnt; + int devKind; + DevUnion devPrivate; +#ifdef PIXPRIV + DevUnion *devPrivates; /* real devPrivates like gcs & windows */ +#endif +#ifdef COMPOSITE + short screen_x; + short screen_y; +#endif +} PixmapRec; + +#endif /* PIXMAPSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcGCstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcGCstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcGCstr.h (revision 51223) @@ -0,0 +1,95 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ppcGCstr.h,v 1.3 2003/02/18 21:29:59 tsi Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/*********************************************************** + Copyright IBM Corporation 1988 + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of IBM not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XConsortium: ppcGCstr.h /main/3 1996/02/21 17:57:42 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "gc.h" +#include "mfb.h" + +typedef struct { + unsigned long planemask ; + unsigned long fgPixel ; + unsigned long bgPixel ; + int alu ; + int fillStyle ; + } ppcReducedRrop ; + +/* ************************************************************************ */ + +/* private field of GC */ +typedef struct { +/* The next five (5) fields MUST CORRESPOND to + * the fields of a "mfbPrivGC" struct + * ----- BEGINNING OF "DO-NOT-CHANGE" REGION ----- + */ + unsigned char rop ; /* reduction of rasterop to 1 of 3 */ + unsigned char ropOpStip ; /* rop for opaque stipple */ + unsigned char ropFillArea ; /* == alu, rop, or ropOpStip */ + unsigned char unused[sizeof(long) - 3]; + mfbFillAreaProcPtr FillArea; /* fills regions; look at the code */ +/* ----- END OF "DO-NOT-CHANGE" REGION ----- */ + ppcReducedRrop colorRrop ; + short lastDrawableType ; /* was last drawable a window or a pixmap? */ + short lastDrawableDepth ; /* was last drawable 1 or 8 planes? */ + pointer devPriv ; /* Private area for device specific stuff */ + } ppcPrivGC ; +typedef ppcPrivGC *ppcPrivGCPtr ; + +/* ppcCReduce.c */ +void xf4bppGetReducedColorRrop( + GCPtr, + int, + ppcReducedRrop * +); + +/* vgaGC.c */ +void xf4bppChangeGCtype( + GCPtr, + ppcPrivGCPtr +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcSpMcro.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcSpMcro.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ppcSpMcro.h (revision 51223) @@ -0,0 +1,45 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ppcSpMcro.h,v 1.1.2.1 1998/06/27 14:48:49 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/* $XConsortium: ppcSpMcro.h /main/3 1996/02/21 17:58:36 kaleb $ */ + +/* This screwy macro is used in all the spans routines and you find + it all over the place, so it is a macro just to tidy things up. +*/ + +#define SETSPANPTRS(IN,N,IPW,PW,IPPT,PPT,FPW,FPPT,FSORT) \ + { \ + N = IN * miFindMaxBand(pGC->pCompositeClip); \ + if(!(PW = (int *)ALLOCATE_LOCAL(N * sizeof(int)))) \ + return; \ + if(!(PPT = (DDXPointRec *)ALLOCATE_LOCAL(N * sizeof(DDXPointRec)))) \ + { \ + DEALLOCATE_LOCAL(PW); \ + return; \ + } \ + FPW = PW; \ + FPPT = PPT; \ + N = miClipSpans(pGC->pCompositeClip, IPPT, IPW, IN, \ + PPT, PW, FSORT); \ + } + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_asm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_asm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_asm.h (revision 51223) @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C++ 10.6 or later +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Inline assembler versions of the primitive operand +* functions for faster performance. At the moment this is +* x86 inline assembler, but these functions could be replaced +* with native inline assembler for each supported processor +* platform. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_ASM_H +#define __X86EMU_PRIM_ASM_H + +#ifdef __WATCOMC__ + +#ifndef VALIDATE +#define __HAVE_INLINE_ASSEMBLER__ +#endif + +u32 get_flags_asm(void); +#pragma aux get_flags_asm = \ + "pushf" \ + "pop eax" \ + value [eax] \ + modify exact [eax]; + +u16 aaa_word_asm(u32 *flags,u16 d); +#pragma aux aaa_word_asm = \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aas_word_asm(u32 *flags,u16 d); +#pragma aux aas_word_asm = \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aad_word_asm(u32 *flags,u16 d); +#pragma aux aad_word_asm = \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aam_word_asm(u32 *flags,u8 d); +#pragma aux aam_word_asm = \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [ax] \ + modify exact [ax]; + +u8 adc_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux adc_byte_asm = \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 adc_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux adc_word_asm = \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 adc_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux adc_long_asm = \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 add_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux add_byte_asm = \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 add_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux add_word_asm = \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 add_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux add_long_asm = \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 and_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux and_byte_asm = \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 and_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux and_word_asm = \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 and_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux and_long_asm = \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux cmp_byte_asm = \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 cmp_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux cmp_word_asm = \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 cmp_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux cmp_long_asm = \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 daa_byte_asm(u32 *flags,u8 d); +#pragma aux daa_byte_asm = \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 das_byte_asm(u32 *flags,u8 d); +#pragma aux das_byte_asm = \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 dec_byte_asm(u32 *flags,u8 d); +#pragma aux dec_byte_asm = \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 dec_word_asm(u32 *flags,u16 d); +#pragma aux dec_word_asm = \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 dec_long_asm(u32 *flags,u32 d); +#pragma aux dec_long_asm = \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 inc_byte_asm(u32 *flags,u8 d); +#pragma aux inc_byte_asm = \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 inc_word_asm(u32 *flags,u16 d); +#pragma aux inc_word_asm = \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 inc_long_asm(u32 *flags,u32 d); +#pragma aux inc_long_asm = \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 or_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux or_byte_asm = \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 or_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux or_word_asm = \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 or_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux or_long_asm = \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 neg_byte_asm(u32 *flags,u8 d); +#pragma aux neg_byte_asm = \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 neg_word_asm(u32 *flags,u16 d); +#pragma aux neg_word_asm = \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 neg_long_asm(u32 *flags,u32 d); +#pragma aux neg_long_asm = \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 not_byte_asm(u32 *flags,u8 d); +#pragma aux not_byte_asm = \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 not_word_asm(u32 *flags,u16 d); +#pragma aux not_word_asm = \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 not_long_asm(u32 *flags,u32 d); +#pragma aux not_long_asm = \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcl_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcl_word_asm = \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcl_long_asm = \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcr_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcr_word_asm = \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcr_long_asm = \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rol_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rol_byte_asm = \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rol_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rol_word_asm = \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rol_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rol_long_asm = \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 ror_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux ror_byte_asm = \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 ror_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux ror_word_asm = \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 ror_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux ror_long_asm = \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shl_byte_asm = \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shl_word_asm = \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shl_long_asm = \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shr_byte_asm = \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shr_word_asm = \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shr_long_asm = \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 sar_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sar_byte_asm = \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 sar_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux sar_word_asm = \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 sar_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux sar_long_asm = \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shld_word_asm = \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shld_long_asm = \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shrd_word_asm = \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shrd_long_asm = \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sbb_byte_asm = \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sbb_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sbb_word_asm = \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sbb_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sbb_long_asm = \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 sub_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sub_byte_asm = \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sub_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sub_word_asm = \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sub_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sub_long_asm = \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void test_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux test_byte_asm = \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + modify exact [al bl]; + +void test_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux test_word_asm = \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + modify exact [ax bx]; + +void test_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux test_long_asm = \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + modify exact [eax ebx]; + +u8 xor_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux xor_byte_asm = \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 xor_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux xor_word_asm = \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 xor_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux xor_long_asm = \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux imul_byte_asm = \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux imul_word_asm = \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux imul_long_asm = \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux mul_byte_asm = \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux mul_word_asm = \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux mul_long_asm = \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux idiv_byte_asm = \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux idiv_word_asm = \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux idiv_long_asm = \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux div_byte_asm = \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux div_word_asm = \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux div_long_asm = \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +#endif + +#endif /* __X86EMU_PRIM_ASM_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_ops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_ops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/prim_ops.h (revision 51223) @@ -0,0 +1,141 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/property.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/property.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/property.h (revision 51223) @@ -0,0 +1,74 @@ +/* $Xorg: property.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/property.h,v 1.3 2001/12/14 19:59:55 dawes Exp $ */ + +#ifndef PROPERTY_H +#define PROPERTY_H + +#include "window.h" + +typedef struct _Property *PropertyPtr; + +extern int ChangeWindowProperty( + WindowPtr /*pWin*/, + Atom /*property*/, + Atom /*type*/, + int /*format*/, + int /*mode*/, + unsigned long /*len*/, + pointer /*value*/, + Bool /*sendevent*/); + +extern int DeleteProperty( + WindowPtr /*pWin*/, + Atom /*propName*/); + +extern void DeleteAllWindowProperties( + WindowPtr /*pWin*/); + +#endif /* PROPERTY_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/propertyst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/propertyst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/propertyst.h (revision 51223) @@ -0,0 +1,76 @@ +/* $Xorg: propertyst.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/propertyst.h,v 3.2 2001/01/17 22:36:57 dawes Exp $ */ + +#ifndef PROPERTYSTRUCT_H +#define PROPERTYSTRUCT_H +#include "misc.h" +#include "property.h" +/* + * PROPERTY -- property element + */ + +typedef struct _Property { + struct _Property *next; + ATOM propertyName; + ATOM type; /* ignored by server */ + short format; /* format of data for swapping - 8,16,32 */ + long size; /* size of data in (format/8) bytes */ + pointer data; /* private to client */ +#if defined(LBX) || defined(LBX_COMPAT) + /* If space is at a premium and binary compatibility is not + * an issue, you may want to put the owner_pid next to format + * so that the two shorts pack together without padding. + */ + short owner_pid; /* proxy that has the data */ + XID tag_id; +#endif +} PropertyRec; + +#endif /* PROPERTYSTRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pseudoramiX.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pseudoramiX.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/pseudoramiX.h (revision 51223) @@ -0,0 +1,10 @@ +/* + * Minimal implementation of PanoramiX/Xinerama + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/pseudoramiX.h,v 1.3 2004/07/02 01:30:33 torrey Exp $ */ + +extern int noPseudoramiXExtension; + +void PseudoramiXAddScreen(int x, int y, int w, int h); +void PseudoramiXExtensionInit(int argc, char *argv[]); +void PseudoramiXResetScreens(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/psout.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/psout.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/psout.h (revision 51223) @@ -0,0 +1,335 @@ +/* $Xorg: psout.h,v 1.6 2001/02/09 02:04:37 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: psout.h +** * +** * Contents: Include file for psout.c +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _psout_ +#define _psout_ + +#include + +typedef enum PsCapEnum_ { PsCButt=0, PsCRound, PsCSquare } PsCapEnum; +typedef enum PsJoinEnum_ { PsJMiter=0, PsJRound, PsJBevel } PsJoinEnum; +typedef enum PsArcEnum_ { PsChord, PsPieSlice } PsArcEnum; +typedef enum PsRuleEnum_ { PsEvenOdd, PsNZWinding } PsRuleEnum; +typedef enum PsFillEnum_ { PsSolid=0, PsTile, PsStip, PsOpStip } PsFillEnum; + +typedef struct PsPointRec_ +{ + int x; + int y; +} PsPointRec; + +typedef PsPointRec *PsPointPtr; + +typedef struct PsRectRec_ +{ + int x; + int y; + int w; + int h; +} PsRectRec; + +typedef PsRectRec *PsRectPtr; + +typedef struct PsArcRec_ +{ + int x; + int y; + int w; + int h; + int a1; + int a2; + PsArcEnum style; +} PsArcRec; + +typedef PsArcRec *PsArcPtr; + +#define PSOUT_RECT 0 +#define PSOUT_ARC 1 +#define PSOUT_POINTS 2 + +typedef struct PsElmRec_ +{ + int type; + int nPoints; + union + { + PsRectRec rect; + PsArcRec arc; + PsPointPtr points; + } c; +} PsElmRec; + +typedef PsElmRec *PsElmPtr; + +typedef struct PsClipRec_ +{ + int nRects; + PsRectPtr rects; + int nElms; + PsElmPtr elms; + int nOutterClips; + PsRectPtr outterClips; +} PsClipRec; + +typedef PsClipRec *PsClipPtr; + +typedef enum PsFTDownloadFontType_ +{ + PsFontBitmap=0, + PsFontType1, + PsFontType3 +} PsFTDownloadFontType; + +/* Define |PsOutColor| color type which can hold one RGB value + * (note: this needs to be |signed| long/long long to represent + * special values such as |PSOUTCOLOR_NOCOLOR|) + */ +#ifdef PSOUT_USE_DEEPCOLOR +/* 64bit |PsOutColor| which can hold 16bit R-,G-,B-values */ +#ifdef WIN32 +typedef signed __int64 PsOutColor; +#else +# if defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || defined(_LP64) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + defined (__powerpc64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef signed long PsOutColor; +# else +typedef signed long long PsOutColor; +# endif /* native 64bit platform */ +#endif /* WIN32 */ + +#define PSOUTCOLOR_TO_REDBITS(clr) ((clr) >> 32) +#define PSOUTCOLOR_TO_GREENBITS(clr) (((clr) >> 16) & 0xFFFF) +#define PSOUTCOLOR_TO_BLUEBITS(clr) ((clr) & 0xFFFF) +#define PSOUTCOLOR_BITS_TO_PSFLOAT(b) ((float)(b) / 65535.) +#define PSOUTCOLOR_WHITE (0xFFFFFFFFFFFFLL) +#define PSOUTCOLOR_NOCOLOR (-1LL) +#define PSOUTCOLOR_TO_RGB24BIT(clr) (((PSOUTCOLOR_TO_REDBITS(clr) >> 8) << 16) | \ + ((PSOUTCOLOR_TO_GREENBITS(clr) >> 8) << 8) | \ + ((PSOUTCOLOR_TO_BLUEBITS(clr) >> 8) << 0)) +#else +/* 32bit |PsOutColor| which can hold 8bit R-,G-,B-values */ +typedef signed long PsOutColor; +#define PSOUTCOLOR_TO_REDBITS(clr) ((clr) >> 16) +#define PSOUTCOLOR_TO_GREENBITS(clr) (((clr) >> 8) & 0xFF) +#define PSOUTCOLOR_TO_BLUEBITS(clr) ((clr) & 0xFF) +#define PSOUTCOLOR_BITS_TO_PSFLOAT(b) ((float)(b) / 255.) +#define PSOUTCOLOR_WHITE (0xFFFFFF) +#define PSOUTCOLOR_NOCOLOR (-1) +#define PSOUTCOLOR_TO_RGB24BIT(clr) ((PSOUTCOLOR_TO_REDBITS(clr) << 16) | \ + (PSOUTCOLOR_TO_GREENBITS(clr) << 8) | \ + (PSOUTCOLOR_TO_BLUEBITS(clr) << 0)) +#endif /* PSOUT_USE_DEEPCOLOR */ + +#ifdef USE_PSOUT_PRIVATE +typedef void *voidPtr; + +typedef struct PsPatRec_ +{ + PsFillEnum type; + voidPtr tag; +} PsPatRec; + +typedef PsPatRec *PsPatPtr; + +typedef struct PsOutRec_ +{ + FILE *Fp; + char Buf[16384]; + PsOutColor CurColor; + int LineWidth; + PsCapEnum LineCap; + PsJoinEnum LineJoin; + int NDashes; + int *Dashes; + int DashOffset; + PsOutColor LineBClr; + PsRuleEnum FillRule; + char *FontName; + int FontSize; + float FontMtx[4]; + int ImageFormat; + int RevImage; + int NPatterns; + int MxPatterns; + PsPatPtr Patterns; + int ClipType; + PsClipRec Clip; + int InFrame; + int XOff; + int YOff; + + PsFillEnum InTile; + int ImgSkip; + PsOutColor ImgBClr; + PsOutColor ImgFClr; + int ImgX; + int ImgY; + int ImgW; + int ImgH; + int SclW; + int SclH; + + Bool isRaw; + + int pagenum; + + int start_image; +} PsOutRec; + +typedef struct PsOutRec_ *PsOutPtr; + +extern void S_Flush(PsOutPtr self); +extern void S_OutNum(PsOutPtr self, float num); +extern void S_OutTok(PsOutPtr self, char *tok, int cr); +#else +typedef struct PsOutRec_ *PsOutPtr; +#endif /* USE_PSOUT_PRIVATE */ + +extern PsOutPtr PsOut_BeginFile(FILE *fp, char *title, int orient, int count, int plex, + int res, int wd, int ht, Bool raw); +extern void PsOut_EndFile(PsOutPtr self, int closeFile); +extern void PsOut_BeginPage(PsOutPtr self, int orient, int count, int plex, + int res, int wd, int ht); +extern void PsOut_EndPage(PsOutPtr self); +extern void PsOut_DirtyAttributes(PsOutPtr self); +extern void PsOut_Comment(PsOutPtr self, char *comment); +extern void PsOut_Offset(PsOutPtr self, int x, int y); + +extern void PsOut_Clip(PsOutPtr self, int clpTyp, PsClipPtr clpinf); + +extern void PsOut_Color(PsOutPtr self, PsOutColor clr); +extern void PsOut_FillRule(PsOutPtr self, PsRuleEnum rule); +extern void PsOut_LineAttrs(PsOutPtr self, int wd, PsCapEnum cap, + PsJoinEnum join, int nDsh, int *dsh, int dshOff, + PsOutColor bclr); +extern void PsOut_TextAttrs(PsOutPtr self, char *fnam, int siz, int iso); +extern void PsOut_TextAttrsMtx(PsOutPtr self, char *fnam, float *mtx, int iso); + +extern void PsOut_Polygon(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_FillRect(PsOutPtr self, int x, int y, int w, int h); +extern void PsOut_FillArc(PsOutPtr self, int x, int y, int w, int h, + float ang1, float ang2, PsArcEnum style); + +extern void PsOut_Lines(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_Points(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_DrawRect(PsOutPtr self, int x, int y, int w, int h); +extern void PsOut_DrawArc(PsOutPtr self, int x, int y, int w, int h, + float ang1, float ang2); + +extern void PsOut_Text(PsOutPtr self, int x, int y, char *text, int textl, + PsOutColor bclr); +extern void PsOut_Text16(PsOutPtr self, int x, int y, unsigned short *text, int textl, PsOutColor bclr); + +extern void PsOut_BeginImage(PsOutPtr self, PsOutColor bclr, PsOutColor fclr, int x, int y, + int w, int h, int sw, int sh, int format); +extern void PsOut_BeginImageIM(PsOutPtr self, PsOutColor bclr, PsOutColor fclr, int x, int y, + int w, int h, int sw, int sh, int format); +extern void PsOut_EndImage(PsOutPtr self); +extern void PsOut_OutImageBytes(PsOutPtr self, int nBytes, char *bytes); + +extern void PsOut_BeginFrame(PsOutPtr self, int xoff, int yoff, int x, int y, + int w, int h); +extern void PsOut_EndFrame(PsOutPtr self); + +extern int PsOut_BeginPattern(PsOutPtr self, void *tag, int w, int h, + PsFillEnum type, PsOutColor bclr, PsOutColor fclr); +extern void PsOut_EndPattern(PsOutPtr self); +extern void PsOut_SetPattern(PsOutPtr self, void *tag, PsFillEnum type); + +extern void PsOut_RawData(PsOutPtr self, char *data, int len); + +extern int PsOut_DownloadType1(PsOutPtr self, const char *auditmsg, const char *name, const char *fname); + +extern int PsOut_DownloadFreeType1(PsOutPtr self, const char *psfontname, FontPtr pFont, long block_offset); +extern int PsOut_DownloadFreeType3(PsOutPtr self, const char *psfontname, FontPtr pFont, long block_offset); + +extern int PsOut_DownloadFreeType(PsOutPtr self, PsFTDownloadFontType downloadfonttype, const char *psfontname, FontPtr pFont, long block_offset); +extern void PsOut_Get_FreeType_Glyph_Name( char *destbuf, FontPtr pFont, unsigned long x11fontindex); +extern void PsOut_FreeType_Text(FontPtr pFont, PsOutPtr self, int x, int y, char *text, int textl); +extern void PsOut_FreeType_Text16(FontPtr pFont, PsOutPtr self, int x, int y, unsigned short *text, int textl); + +extern void PsOut_FreeType_TextAttrs16(PsOutPtr self, char *fnam, int siz, int iso); +extern void PsOut_FreeType_TextAttrsMtx16(PsOutPtr self, char *fnam, float *mtx, int iso); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartz.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartz.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartz.h (revision 51223) @@ -0,0 +1,131 @@ +/* + * quartz.h + * + * External interface of the Quartz display modes seen by the generic, mode + * independent parts of the Darwin X server. + */ +/* + * Copyright (c) 2001-2003 Greg Parker and Torrey T. Lyons. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XdotOrg: xc/programs/Xserver/hw/darwin/quartz/quartz.h,v 1.3 2004/07/30 19:12:17 torrey Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/quartz.h,v 1.7 2003/11/12 20:21:51 torrey Exp $ */ + +#ifndef _QUARTZ_H +#define _QUARTZ_H + +#include "quartzPasteboard.h" + +#include "screenint.h" +#include "window.h" + +/*------------------------------------------ + Quartz display mode function types + ------------------------------------------*/ + +/* + * Display mode initialization + */ +typedef void (*DisplayInitProc)(void); +typedef Bool (*AddScreenProc)(int index, ScreenPtr pScreen); +typedef Bool (*SetupScreenProc)(int index, ScreenPtr pScreen); +typedef void (*InitInputProc)(int argc, char **argv); + +/* + * Cursor functions + */ +typedef Bool (*InitCursorProc)(ScreenPtr pScreen); +typedef void (*CursorUpdateProc)(void); + +/* + * Suspend and resume X11 activity + */ +typedef void (*SuspendScreenProc)(ScreenPtr pScreen); +typedef void (*ResumeScreenProc)(ScreenPtr pScreen, int x, int y); +typedef void (*CaptureScreensProc)(void); +typedef void (*ReleaseScreensProc)(void); + +/* + * Screen state change support + */ +typedef void (*ScreenChangedProc)(void); +typedef void (*AddPseudoramiXScreensProc)(int *x, int *y, int *width, int *height); +typedef void (*UpdateScreenProc)(ScreenPtr pScreen); + +/* + * Rootless helper functions + */ +typedef Bool (*IsX11WindowProc)(void *nsWindow, int windowNumber); +typedef void (*HideWindowsProc)(Bool hide); + +/* + * Rootless functions for optional export to GLX layer + */ +typedef void * (*FrameForWindowProc)(WindowPtr pWin, Bool create); +typedef WindowPtr (*TopLevelParentProc)(WindowPtr pWindow); +typedef Bool (*CreateSurfaceProc) + (ScreenPtr pScreen, Drawable id, DrawablePtr pDrawable, + unsigned int client_id, unsigned int *surface_id, + unsigned int key[2], void (*notify) (void *arg, void *data), + void *notify_data); +typedef Bool (*DestroySurfaceProc) + (ScreenPtr pScreen, Drawable id, DrawablePtr pDrawable, + void (*notify) (void *arg, void *data), void *notify_data); + +/* + * Quartz display mode function list + */ +typedef struct _QuartzModeProcs { + DisplayInitProc DisplayInit; + AddScreenProc AddScreen; + SetupScreenProc SetupScreen; + InitInputProc InitInput; + + InitCursorProc InitCursor; + CursorUpdateProc CursorUpdate; // Not used if NULL + + SuspendScreenProc SuspendScreen; + ResumeScreenProc ResumeScreen; + CaptureScreensProc CaptureScreens; // Only called in fullscreen + ReleaseScreensProc ReleaseScreens; // Only called in fullscreen + + ScreenChangedProc ScreenChanged; + AddPseudoramiXScreensProc AddPseudoramiXScreens; + UpdateScreenProc UpdateScreen; + + IsX11WindowProc IsX11Window; + HideWindowsProc HideWindows; + + FrameForWindowProc FrameForWindow; + TopLevelParentProc TopLevelParent; + CreateSurfaceProc CreateSurface; + DestroySurfaceProc DestroySurface; +} QuartzModeProcsRec, *QuartzModeProcsPtr; + +extern QuartzModeProcsPtr quartzProcs; + +Bool QuartzLoadDisplayBundle(const char *dpyBundleName); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzAudio.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzAudio.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzAudio.h (revision 51223) @@ -0,0 +1,41 @@ +// +// QuartzAudio.h +// +// X Window bell support using CoreAudio or AppKit. +// Greg Parker gparker@cs.stanford.edu 19 Feb 2001 +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzAudio.h,v 1.2 2001/04/01 20:45:43 tsi Exp $ */ + +#ifndef _QUARTZAUDIO_H +#define _QUARTZAUDIO_H + +#include "input.h" + +void QuartzAudioInit(void); +void QuartzBell(int volume, DeviceIntPtr pDevice, pointer ctrl, int class); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCommon.h (revision 51223) @@ -0,0 +1,108 @@ +/* $XdotOrg: xc/programs/Xserver/hw/darwin/quartz/quartzCommon.h,v 1.3 2004/07/30 19:12:17 torrey Exp $ */ +/* + * quartzCommon.h + * + * Common definitions used internally by all Quartz modes + * + * This file should be included before any X11 or IOKit headers + * so that it can avoid symbol conflicts. + * + * Copyright (c) 2001-2004 Torrey T. Lyons and Greg Parker. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/quartzCommon.h,v 1.15 2004/06/08 22:58:10 torrey Exp $ */ + +#ifndef _QUARTZCOMMON_H +#define _QUARTZCOMMON_H + +// QuickDraw in ApplicationServices has the following conflicts with +// the basic X server headers. Use QD_ to use the QuickDraw +// definition of any of these symbols, or the normal name for the +// X11 definition. +#define Cursor QD_Cursor +#define WindowPtr QD_WindowPtr +#define Picture QD_Picture +#include +#undef Cursor +#undef WindowPtr +#undef Picture + +// Quartz specific per screen storage structure +typedef struct { + // List of CoreGraphics displays that this X11 screen covers. + // This is more than one CG display for video mirroring and + // rootless PseudoramiX mode. + // No CG display will be covered by more than one X11 screen. + int displayCount; + CGDirectDisplayID *displayIDs; +} QuartzScreenRec, *QuartzScreenPtr; + +#define QUARTZ_PRIV(pScreen) \ + ((QuartzScreenPtr)pScreen->devPrivates[quartzScreenIndex].ptr) + +// Data stored at startup for Cocoa front end +extern int quartzEventWriteFD; +extern int quartzStartClients; + +// User preferences used by Quartz modes +extern int quartzRootless; +extern int quartzUseSysBeep; +extern int quartzUseAGL; +extern int quartzEnableKeyEquivalents; + +// Other shared data +extern int quartzServerVisible; +extern int quartzServerQuitting; +extern int quartzScreenIndex; +extern int aquaMenuBarHeight; + +// Name of GLX bundle for native OpenGL +extern const char *quartzOpenGLBundle; + +void QuartzReadPreferences(void); +void QuartzMessageMainThread(unsigned msg, void *data, unsigned length); +void QuartzMessageServerThread(int type, int argc, ...); +void QuartzSetWindowMenu(int nitems, const char **items, + const char *shortcuts); +void QuartzFSCapture(void); +void QuartzFSRelease(void); +int QuartzFSUseQDCursor(int depth); +void QuartzBlockHandler(void *blockData, void *pTimeout, void *pReadmask); +void QuartzWakeupHandler(void *blockData, int result, void *pReadmask); + +// Messages that can be sent to the main thread. +enum { + kQuartzServerHidden, + kQuartzServerStarted, + kQuartzServerDied, + kQuartzCursorUpdate, + kQuartzPostEvent, + kQuartzSetWindowMenu, + kQuartzSetWindowMenuCheck, + kQuartzSetFrontProcess, + kQuartzSetCanQuit +}; + +#endif /* _QUARTZCOMMON_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzCursor.h (revision 51223) @@ -0,0 +1,43 @@ +/* + * quartzCursor.h + * + * External interface for Quartz hardware cursor + */ +/* + * Copyright (c) 2001 Torrey T. Lyons and Greg Parker. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzCursor.h,v 1.2 2001/09/23 04:04:49 torrey Exp $ */ + +#ifndef QUARTZCURSOR_H +#define QUARTZCURSOR_H + +#include "screenint.h" + +Bool QuartzInitCursor(ScreenPtr pScreen); +void QuartzSuspendXCursor(ScreenPtr pScreen); +void QuartzResumeXCursor(ScreenPtr pScreen, int x, int y); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzPasteboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzPasteboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/quartzPasteboard.h (revision 51223) @@ -0,0 +1,45 @@ +/* + QuartzPasteboard.h + + Mac OS X pasteboard <-> X cut buffer + Greg Parker gparker@cs.stanford.edu March 8, 2001 +*/ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzPasteboard.h,v 1.1 2001/03/15 22:24:27 torrey Exp $ */ + +#ifndef _QUARTZPASTEBOARD_H +#define _QUARTZPASTEBOARD_H + +// Aqua->X +void QuartzReadPasteboard(); +char * QuartzReadCocoaPasteboard(void); // caller must free string + +// X->Aqua +void QuartzWritePasteboard(); +void QuartzWriteCocoaPasteboard(char *text); + +#endif /* _QUARTZPASTEBOARD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/queryst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/queryst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/queryst.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/queryst.h,v 3.1 1996/04/15 11:19:00 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef QUERYST_H +#define QUERYST_H 1 + +int +SProcXQueryDeviceState( + ClientPtr /* client */ + ); + +int +ProcXQueryDeviceState( + ClientPtr /* client */ + ); + +void +SRepXQueryDeviceState ( + ClientPtr /* client */, + int /* size */, + xQueryDeviceStateReply * /* rep */ + ); + +#endif /* QUERYST_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/randrstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/randrstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/randrstr.h (revision 51223) @@ -0,0 +1,142 @@ +/* + * $XFree86: xc/programs/Xserver/randr/randrstr.h,v 1.5 2002/09/29 23:39:45 keithp Exp $ + * + * Copyright © 2000 Compaq Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Compaq not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Compaq makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * COMPAQ DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL COMPAQ BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _RANDRSTR_H_ +#define _RANDRSTR_H_ + +#include + +typedef struct _rrScreenRate { + int rate; + Bool referenced; + Bool oldReferenced; +} RRScreenRate, *RRScreenRatePtr; + +typedef struct _rrScreenSize { + int id; + short width, height; + short mmWidth, mmHeight; + RRScreenRatePtr pRates; + int nRates; + int nRatesInUse; + Bool referenced; + Bool oldReferenced; +} RRScreenSize, *RRScreenSizePtr; + +typedef Bool (*RRSetConfigProcPtr) (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +typedef Bool (*RRGetInfoProcPtr) (ScreenPtr pScreen, Rotation *rotations); +typedef Bool (*RRCloseScreenProcPtr) ( int i, ScreenPtr pscreen); + +typedef struct _rrScrPriv { + RRSetConfigProcPtr rrSetConfig; + RRGetInfoProcPtr rrGetInfo; + + TimeStamp lastSetTime; /* last changed by client */ + TimeStamp lastConfigTime; /* possible configs changed */ + RRCloseScreenProcPtr CloseScreen; + + /* + * Configuration information + */ + Rotation rotations; + + int nSizes; + int nSizesInUse; + RRScreenSizePtr pSizes; + + /* + * Current state + */ + Rotation rotation; + int size; + int rate; +} rrScrPrivRec, *rrScrPrivPtr; + +extern int rrPrivIndex; + +#define rrGetScrPriv(pScr) ((rrScrPrivPtr) (pScr)->devPrivates[rrPrivIndex].ptr) +#define rrScrPriv(pScr) rrScrPrivPtr pScrPriv = rrGetScrPriv(pScr) +#define SetRRScreen(s,p) ((s)->devPrivates[rrPrivIndex].ptr = (pointer) (p)) + +/* Initialize the extension */ +void +RRExtensionInit (void); + +/* + * Then, register the specific size with the screen + */ + +RRScreenSizePtr +RRRegisterSize (ScreenPtr pScreen, + short width, + short height, + short mmWidth, + short mmHeight); + +Bool RRRegisterRate (ScreenPtr pScreen, + RRScreenSizePtr pSize, + int rate); + +/* + * Finally, set the current configuration of the screen + */ + +void +RRSetCurrentConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +Bool RRScreenInit(ScreenPtr pScreen); + +int +RRSetScreenConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +Bool +miRandRInit (ScreenPtr pScreen); + +Bool +miRRGetInfo (ScreenPtr pScreen, Rotation *rotations); + +Bool +miRRSetConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr size); + +Bool +miRRGetScreenInfo (ScreenPtr pScreen); + +#endif /* _RANDRSTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/region.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/region.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/region.h (revision 51223) @@ -0,0 +1,54 @@ +/* $Xorg: region.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef REGION_H +#define REGION_H + +#include "regionstr.h" + +#endif /* REGION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regionstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regionstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regionstr.h (revision 51223) @@ -0,0 +1,412 @@ +/* $XdotOrg: xc/programs/Xserver/include/regionstr.h,v 1.4 2005/06/25 12:39:58 zack Exp $ */ +/* $Xorg: regionstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/regionstr.h,v 1.12tsi Exp $ */ + +#ifndef REGIONSTRUCT_H +#define REGIONSTRUCT_H + +typedef struct _Region RegionRec, *RegionPtr; + +#include "miscstruct.h" + +/* Return values from RectIn() */ + +#define rgnOUT 0 +#define rgnIN 1 +#define rgnPART 2 + +#define NullRegion ((RegionPtr)0) + +/* + * clip region + */ + +typedef struct _RegData { + long size; + long numRects; +/* BoxRec rects[size]; in memory but not explicitly declared */ +} RegDataRec, *RegDataPtr; + +struct _Region { + BoxRec extents; + RegDataPtr data; +}; + +extern BoxRec miEmptyBox; +extern RegDataRec miEmptyData; +extern RegDataRec miBrokenData; + +#define REGION_NIL(reg) ((reg)->data && !(reg)->data->numRects) +/* not a region */ +#define REGION_NAR(reg) ((reg)->data == &miBrokenData) +#define REGION_NUM_RECTS(reg) ((reg)->data ? (reg)->data->numRects : 1) +#define REGION_SIZE(reg) ((reg)->data ? (reg)->data->size : 0) +#define REGION_RECTS(reg) ((reg)->data ? (BoxPtr)((reg)->data + 1) \ + : &(reg)->extents) +#define REGION_BOXPTR(reg) ((BoxPtr)((reg)->data + 1)) +#define REGION_BOX(reg,i) (®ION_BOXPTR(reg)[i]) +#define REGION_TOP(reg) REGION_BOX(reg, (reg)->data->numRects) +#define REGION_END(reg) REGION_BOX(reg, (reg)->data->numRects - 1) +#define REGION_SZOF(n) (sizeof(RegDataRec) + ((n) * sizeof(BoxRec))) + +/* Keith recommends weaning the region code of pScreen argument */ +#define REG_pScreen screenInfo.screens[0] + +#ifdef NEED_SCREEN_REGIONS + +#define REGION_CREATE(_pScreen, _rect, _size) \ + (*(REG_pScreen)->RegionCreate)(_rect, _size) + +#define REGION_INIT(_pScreen, _pReg, _rect, _size) \ + (*(REG_pScreen)->RegionInit)(_pReg, _rect, _size) + +#define REGION_COPY(_pScreen, dst, src) \ + (*(REG_pScreen)->RegionCopy)(dst, src) + +#define REGION_DESTROY(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionDestroy)(_pReg) + +#define REGION_UNINIT(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionUninit)(_pReg) + +#define REGION_INTERSECT(_pScreen, newReg, reg1, reg2) \ + (*(REG_pScreen)->Intersect)(newReg, reg1, reg2) + +#define REGION_UNION(_pScreen, newReg, reg1, reg2) \ + (*(REG_pScreen)->Union)(newReg, reg1, reg2) + +#define REGION_SUBTRACT(_pScreen, newReg, reg1, reg2) \ + (*(REG_pScreen)->Subtract)(newReg, reg1, reg2) + +#define REGION_INVERSE(_pScreen, newReg, reg1, invRect) \ + (*(REG_pScreen)->Inverse)(newReg, reg1, invRect) + +#define REGION_RESET(_pScreen, _pReg, _pBox) \ + (*(REG_pScreen)->RegionReset)(_pReg, _pBox) + +#define REGION_TRANSLATE(_pScreen, _pReg, _x, _y) \ + (*(REG_pScreen)->TranslateRegion)(_pReg, _x, _y) + +#define RECT_IN_REGION(_pScreen, _pReg, prect) \ + (*(REG_pScreen)->RectIn)(_pReg, prect) + +#define POINT_IN_REGION(_pScreen, _pReg, _x, _y, prect) \ + (*(REG_pScreen)->PointInRegion)(_pReg, _x, _y, prect) + +#define REGION_NOTEMPTY(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionNotEmpty)(_pReg) + +#define REGION_EQUAL(_pScreen, _pReg1, _pReg2) \ + (*(REG_pScreen)->RegionEqual)(_pReg1, _pReg2) + +#define REGION_BROKEN(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionBroken)(_pReg) + +#define REGION_BREAK(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionBreak)(_pReg) + +#define REGION_EMPTY(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionEmpty)(_pReg) + +#define REGION_EXTENTS(_pScreen, _pReg) \ + (*(REG_pScreen)->RegionExtents)(_pReg) + +#define REGION_APPEND(_pScreen, dstrgn, rgn) \ + (*(REG_pScreen)->RegionAppend)(dstrgn, rgn) + +#define REGION_VALIDATE(_pScreen, badreg, pOverlap) \ + (*(REG_pScreen)->RegionValidate)(badreg, pOverlap) + +#define BITMAP_TO_REGION(_pScreen, pPix) \ + (*(REG_pScreen)->BitmapToRegion)(pPix) + +#define RECTS_TO_REGION(_pScreen, nrects, prect, ctype) \ + (*(REG_pScreen)->RectsToRegion)(nrects, prect, ctype) + +#else /* !NEED_SCREEN_REGIONS */ + +/* Reference _pScreen macro argument and check its type */ +#define REGION_SCREEN(_pScreen) (void)((REG_pScreen)->myNum) + +#define REGION_CREATE(_pScreen, _rect, _size) \ + (REGION_SCREEN(_pScreen), miRegionCreate(_rect, _size)) + +#define REGION_COPY(_pScreen, dst, src) \ + (REGION_SCREEN(_pScreen), miRegionCopy(dst, src)) + +#define REGION_DESTROY(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionDestroy(_pReg)) + +#define REGION_INTERSECT(_pScreen, newReg, reg1, reg2) \ + (REGION_SCREEN(_pScreen), miIntersect(newReg, reg1, reg2)) + +#define REGION_UNION(_pScreen, newReg, reg1, reg2) \ + (REGION_SCREEN(_pScreen), miUnion(newReg, reg1, reg2)) + +#define REGION_SUBTRACT(_pScreen, newReg, reg1, reg2) \ + (REGION_SCREEN(_pScreen), miSubtract(newReg, reg1, reg2)) + +#define REGION_INVERSE(_pScreen, newReg, reg1, invRect) \ + (REGION_SCREEN(_pScreen), miInverse(newReg, reg1, invRect)) + +#define REGION_TRANSLATE(_pScreen, _pReg, _x, _y) \ + (REGION_SCREEN(_pScreen), miTranslateRegion(_pReg, _x, _y)) + +#define RECT_IN_REGION(_pScreen, _pReg, prect) \ + (REGION_SCREEN(_pScreen), miRectIn(_pReg, prect)) + +#define POINT_IN_REGION(_pScreen, _pReg, _x, _y, prect) \ + (REGION_SCREEN(_pScreen), miPointInRegion(_pReg, _x, _y, prect)) + +#define REGION_APPEND(_pScreen, dstrgn, rgn) \ + (REGION_SCREEN(_pScreen), miRegionAppend(dstrgn, rgn)) + +#define REGION_VALIDATE(_pScreen, badreg, pOverlap) \ + (REGION_SCREEN(_pScreen), miRegionValidate(badreg, pOverlap)) + +#define BITMAP_TO_REGION(_pScreen, pPix) \ + (*(_pScreen)->BitmapToRegion)(pPix) /* no mi version?! */ + +#define RECTS_TO_REGION(_pScreen, nrects, prect, ctype) \ + (REGION_SCREEN(_pScreen), miRectsToRegion(nrects, prect, ctype)) + +#define REGION_EQUAL(_pScreen, _pReg1, _pReg2) \ + (REGION_SCREEN(_pScreen), miRegionEqual(_pReg1, _pReg2)) + +#define REGION_BREAK(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionBreak(_pReg)) + +#ifdef DONT_INLINE_REGION_OPS + +#define REGION_INIT(_pScreen, _pReg, _rect, _size) \ + (REGION_SCREEN(_pScreen), miRegionInit(_pReg, _rect, _size)) + +#define REGION_UNINIT(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionUninit(_pReg)) + +#define REGION_RESET(_pScreen, _pReg, _pBox) \ + (REGION_SCREEN(_pScreen), miRegionReset(_pReg, _pBox)) + +#define REGION_NOTEMPTY(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionNotEmpty(_pReg)) + +#define REGION_BROKEN(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionBroken(_pReg)) + +#define REGION_EMPTY(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionEmpty(_pReg)) + +#define REGION_EXTENTS(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), miRegionExtents(_pReg)) + +#else /* inline certain simple region ops for performance */ + +#define REGION_INIT(_pScreen, _pReg, _rect, _size) \ +{ \ + REGION_SCREEN(_pScreen); \ + if (_rect) \ + { \ + (_pReg)->extents = *(_rect); \ + (_pReg)->data = (RegDataPtr)NULL; \ + } \ + else \ + { \ + (_pReg)->extents = miEmptyBox; \ + if (((_size) > 1) && ((_pReg)->data = \ + (RegDataPtr)xalloc(REGION_SZOF(_size)))) \ + { \ + (_pReg)->data->size = (_size); \ + (_pReg)->data->numRects = 0; \ + } \ + else \ + (_pReg)->data = &miEmptyData; \ + } \ + } + + +#define REGION_UNINIT(_pScreen, _pReg) \ +{ \ + REGION_SCREEN(_pScreen); \ + if ((_pReg)->data && (_pReg)->data->size) { \ + xfree((_pReg)->data); \ + (_pReg)->data = NULL; \ + } \ +} + +#define REGION_RESET(_pScreen, _pReg, _pBox) \ +{ \ + REGION_SCREEN(_pScreen); \ + (_pReg)->extents = *(_pBox); \ + REGION_UNINIT(_pScreen, _pReg); \ + (_pReg)->data = (RegDataPtr)NULL; \ +} + +#define REGION_NOTEMPTY(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), !REGION_NIL(_pReg)) + +#define REGION_BROKEN(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), REGION_NAR(_pReg)) + +#define REGION_EMPTY(_pScreen, _pReg) \ +{ \ + REGION_UNINIT(_pScreen, _pReg); \ + (_pReg)->extents.x2 = (_pReg)->extents.x1; \ + (_pReg)->extents.y2 = (_pReg)->extents.y1; \ + (_pReg)->data = &miEmptyData; \ +} + +#define REGION_EXTENTS(_pScreen, _pReg) \ + (REGION_SCREEN(_pScreen), &(_pReg)->extents) + +#define REGION_NULL(_pScreen, _pReg) \ +{ \ + REGION_SCREEN(_pScreen); \ + (_pReg)->extents = miEmptyBox; \ + (_pReg)->data = &miEmptyData; \ +} + +#endif /* DONT_INLINE_REGION_OPS */ + +#endif /* NEED_SCREEN_REGIONS */ + +#ifndef REGION_NULL +#define REGION_NULL(_pScreen, _pReg) \ + REGION_INIT(_pScreen, _pReg, NullBox, 1) +#endif + +/* moved from mi.h */ + +extern RegionPtr miRegionCreate( + BoxPtr /*rect*/, + int /*size*/); + +extern void miRegionInit( + RegionPtr /*pReg*/, + BoxPtr /*rect*/, + int /*size*/); + +extern void miRegionDestroy( + RegionPtr /*pReg*/); + +extern void miRegionUninit( + RegionPtr /*pReg*/); + +extern Bool miRegionCopy( + RegionPtr /*dst*/, + RegionPtr /*src*/); + +extern Bool miIntersect( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +extern Bool miUnion( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +extern Bool miRegionAppend( + RegionPtr /*dstrgn*/, + RegionPtr /*rgn*/); + +extern Bool miRegionValidate( + RegionPtr /*badreg*/, + Bool * /*pOverlap*/); + +extern RegionPtr miRectsToRegion( + int /*nrects*/, + xRectanglePtr /*prect*/, + int /*ctype*/); + +extern Bool miSubtract( + RegionPtr /*regD*/, + RegionPtr /*regM*/, + RegionPtr /*regS*/); + +extern Bool miInverse( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + BoxPtr /*invRect*/); + +extern int miRectIn( + RegionPtr /*region*/, + BoxPtr /*prect*/); + +extern void miTranslateRegion( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/); + +extern void miRegionReset( + RegionPtr /*pReg*/, + BoxPtr /*pBox*/); + +extern Bool miRegionBreak( + RegionPtr /*pReg*/); + +extern Bool miPointInRegion( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/, + BoxPtr /*box*/); + +extern Bool miRegionEqual( + RegionPtr /*pReg1*/, + RegionPtr /*pReg2*/); + +extern Bool miRegionNotEmpty( + RegionPtr /*pReg*/); + +extern void miRegionEmpty( + RegionPtr /*pReg*/); + +extern BoxPtr miRegionExtents( + RegionPtr /*pReg*/); + +#endif /* REGIONSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/regs.h (revision 51223) @@ -0,0 +1,337 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK +#endif + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* BIG_ENDIAN */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + u32 mode; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ +#endif + u8 intno; + u8 __pad[3]; + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +private - private data pointer +x86 - X86 registers +****************************************************************************/ +typedef struct { + unsigned long mem_base; + unsigned long mem_size; + void* private; + X86EMU_regs x86; + } X86EMU_sysEnv; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +void printk(const char *fmt, ...); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/renderedge.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/renderedge.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/renderedge.h (revision 51223) @@ -0,0 +1,120 @@ +/* + * $Id: renderedge.h,v 1.4 2005/08/24 11:18:33 daniels Exp $ + * + * Copyright © 2004 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RENDEREDGE_H_ +#define _RENDEREDGE_H_ + +#include "picturestr.h" + +#define MAX_ALPHA(n) ((1 << (n)) - 1) +#define N_Y_FRAC(n) ((n) == 1 ? 1 : (1 << ((n)/2)) - 1) +#define N_X_FRAC(n) ((1 << ((n)/2)) + 1) + +#define STEP_Y_SMALL(n) (xFixed1 / N_Y_FRAC(n)) +#define STEP_Y_BIG(n) (xFixed1 - (N_Y_FRAC(n) - 1) * STEP_Y_SMALL(n)) + +#define Y_FRAC_FIRST(n) (STEP_Y_SMALL(n) / 2) +#define Y_FRAC_LAST(n) (Y_FRAC_FIRST(n) + (N_Y_FRAC(n) - 1) * STEP_Y_SMALL(n)) + +#define STEP_X_SMALL(n) (xFixed1 / N_X_FRAC(n)) +#define STEP_X_BIG(n) (xFixed1 - (N_X_FRAC(n) - 1) * STEP_X_SMALL(n)) + +#define X_FRAC_FIRST(n) (STEP_X_SMALL(n) / 2) +#define X_FRAC_LAST(n) (X_FRAC_FIRST(n) + (N_X_FRAC(n) - 1) * STEP_X_SMALL(n)) + +#define RenderSamplesX(x,n) ((n) == 1 ? 0 : (xFixedFrac (x) + X_FRAC_FIRST(n)) / STEP_X_SMALL(n)) + +/* + * An edge structure. This represents a single polygon edge + * and can be quickly stepped across small or large gaps in the + * sample grid + */ + +typedef struct { + xFixed x; + xFixed e; + xFixed stepx; + xFixed signdx; + xFixed dy; + xFixed dx; + + xFixed stepx_small; + xFixed stepx_big; + xFixed dx_small; + xFixed dx_big; +} RenderEdge; + +/* + * Step across a small sample grid gap + */ +#define RenderEdgeStepSmall(edge) { \ + edge->x += edge->stepx_small; \ + edge->e += edge->dx_small; \ + if (edge->e > 0) \ + { \ + edge->e -= edge->dy; \ + edge->x += edge->signdx; \ + } \ +} + +/* + * Step across a large sample grid gap + */ +#define RenderEdgeStepBig(edge) { \ + edge->x += edge->stepx_big; \ + edge->e += edge->dx_big; \ + if (edge->e > 0) \ + { \ + edge->e -= edge->dy; \ + edge->x += edge->signdx; \ + } \ +} + +xFixed +RenderSampleCeilY (xFixed y, int bpp); + +xFixed +RenderSampleFloorY (xFixed y, int bpp); + +void +RenderEdgeStep (RenderEdge *e, int n); + +void +RenderEdgeInit (RenderEdge *e, + int bpp, + xFixed y_start, + xFixed x_top, + xFixed y_top, + xFixed x_bot, + xFixed y_bot); + +void +RenderLineFixedEdgeInit (RenderEdge *e, + int bpp, + xFixed y, + xLineFixed *line, + int x_off, + int y_off); + +#endif /* _RENDEREDGE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/resource.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/resource.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/resource.h (revision 51223) @@ -0,0 +1,274 @@ +/* $Xorg: resource.h,v 1.5 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987, 1989 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/resource.h,v 1.11 2002/03/06 21:14:04 mvojkovi Exp $ */ + +#ifndef RESOURCE_H +#define RESOURCE_H 1 +#include "misc.h" + +/***************************************************************** + * STUFF FOR RESOURCES + *****************************************************************/ + +/* classes for Resource routines */ + +typedef unsigned long RESTYPE; + +#define RC_VANILLA ((RESTYPE)0) +#define RC_CACHED ((RESTYPE)1<<31) +#define RC_DRAWABLE ((RESTYPE)1<<30) +/* Use class RC_NEVERRETAIN for resources that should not be retained + * regardless of the close down mode when the client dies. (A client's + * event selections on objects that it doesn't own are good candidates.) + * Extensions can use this too! + */ +#define RC_NEVERRETAIN ((RESTYPE)1<<29) +#define RC_LASTPREDEF RC_NEVERRETAIN +#define RC_ANY (~(RESTYPE)0) + +/* types for Resource routines */ + +#define RT_WINDOW ((RESTYPE)1|RC_CACHED|RC_DRAWABLE) +#define RT_PIXMAP ((RESTYPE)2|RC_CACHED|RC_DRAWABLE) +#define RT_GC ((RESTYPE)3|RC_CACHED) +#undef RT_FONT +#undef RT_CURSOR +#define RT_FONT ((RESTYPE)4) +#define RT_CURSOR ((RESTYPE)5) +#define RT_COLORMAP ((RESTYPE)6) +#define RT_CMAPENTRY ((RESTYPE)7) +#define RT_OTHERCLIENT ((RESTYPE)8|RC_NEVERRETAIN) +#define RT_PASSIVEGRAB ((RESTYPE)9|RC_NEVERRETAIN) +#define RT_LASTPREDEF ((RESTYPE)9) +#define RT_NONE ((RESTYPE)0) + +/* bits and fields within a resource id */ +#define RESOURCE_AND_CLIENT_COUNT 29 /* 29 bits for XIDs */ +#if MAXCLIENTS == 64 +#define RESOURCE_CLIENT_BITS 6 +#endif +#if MAXCLIENTS == 128 +#define RESOURCE_CLIENT_BITS 7 +#endif +#if MAXCLIENTS == 256 +#define RESOURCE_CLIENT_BITS 8 +#endif +#if MAXCLIENTS == 512 +#define RESOURCE_CLIENT_BITS 9 +#endif +/* client field offset */ +#define CLIENTOFFSET (RESOURCE_AND_CLIENT_COUNT - RESOURCE_CLIENT_BITS) +/* resource field */ +#define RESOURCE_ID_MASK ((1 << CLIENTOFFSET) - 1) +/* client field */ +#define RESOURCE_CLIENT_MASK (((1 << RESOURCE_CLIENT_BITS) - 1) << CLIENTOFFSET) +/* extract the client mask from an XID */ +#define CLIENT_BITS(id) ((id) & RESOURCE_CLIENT_MASK) +/* extract the client id from an XID */ +#define CLIENT_ID(id) ((int)(CLIENT_BITS(id) >> CLIENTOFFSET)) +#define SERVER_BIT (Mask)0x40000000 /* use illegal bit */ + +#ifdef INVALID +#undef INVALID /* needed on HP/UX */ +#endif + +/* Invalid resource id */ +#define INVALID (0) + +#define BAD_RESOURCE 0xe0000000 + +typedef int (*DeleteType)( + pointer /*value*/, + XID /*id*/); + +typedef void (*FindResType)( + pointer /*value*/, + XID /*id*/, + pointer /*cdata*/); + +typedef void (*FindAllRes)( + pointer /*value*/, + XID /*id*/, + RESTYPE /*type*/, + pointer /*cdata*/); + +typedef Bool (*FindComplexResType)( + pointer /*value*/, + XID /*id*/, + pointer /*cdata*/); + +extern RESTYPE CreateNewResourceType( + DeleteType /*deleteFunc*/); + +extern RESTYPE CreateNewResourceClass(void); + +extern Bool InitClientResources( + ClientPtr /*client*/); + +extern XID FakeClientID( + int /*client*/); + +/* Quartz support on Mac OS X uses the CarbonCore + framework whose AddResource function conflicts here. */ +#ifdef __DARWIN__ +#define AddResource Darwin_X_AddResource +#endif +extern Bool AddResource( + XID /*id*/, + RESTYPE /*type*/, + pointer /*value*/); + +extern void FreeResource( + XID /*id*/, + RESTYPE /*skipDeleteFuncType*/); + +extern void FreeResourceByType( + XID /*id*/, + RESTYPE /*type*/, + Bool /*skipFree*/); + +extern Bool ChangeResourceValue( + XID /*id*/, + RESTYPE /*rtype*/, + pointer /*value*/); + +extern void FindClientResourcesByType( + ClientPtr /*client*/, + RESTYPE /*type*/, + FindResType /*func*/, + pointer /*cdata*/); + +extern void FindAllClientResources( + ClientPtr /*client*/, + FindAllRes /*func*/, + pointer /*cdata*/); + +extern void FreeClientNeverRetainResources( + ClientPtr /*client*/); + +extern void FreeClientResources( + ClientPtr /*client*/); + +extern void FreeAllResources(void); + +extern Bool LegalNewID( + XID /*id*/, + ClientPtr /*client*/); + +extern pointer LookupIDByType( + XID /*id*/, + RESTYPE /*rtype*/); + +extern pointer LookupIDByClass( + XID /*id*/, + RESTYPE /*classes*/); + +extern pointer LookupClientResourceComplex( + ClientPtr client, + RESTYPE type, + FindComplexResType func, + pointer cdata); + +/* These are the access modes that can be passed in the last parameter + * to SecurityLookupIDByType/Class. The Security extension doesn't + * currently make much use of these; they're mainly provided as an + * example of what you might need for discretionary access control. + * You can or these values together to indicate multiple modes + * simultaneously. + */ + +#define SecurityUnknownAccess 0 /* don't know intentions */ +#define SecurityReadAccess (1<<0) /* inspecting the object */ +#define SecurityWriteAccess (1<<1) /* changing the object */ +#define SecurityDestroyAccess (1<<2) /* destroying the object */ + +#ifdef XCSECURITY + +extern pointer SecurityLookupIDByType( + ClientPtr /*client*/, + XID /*id*/, + RESTYPE /*rtype*/, + Mask /*access_mode*/); + +extern pointer SecurityLookupIDByClass( + ClientPtr /*client*/, + XID /*id*/, + RESTYPE /*classes*/, + Mask /*access_mode*/); + +#else /* not XCSECURITY */ + +#define SecurityLookupIDByType(client, id, rtype, access_mode) \ + LookupIDByType(id, rtype) + +#define SecurityLookupIDByClass(client, id, classes, access_mode) \ + LookupIDByClass(id, classes) + +#endif /* XCSECURITY */ + +extern void GetXIDRange( + int /*client*/, + Bool /*server*/, + XID * /*minp*/, + XID * /*maxp*/); + +extern unsigned int GetXIDList( + ClientPtr /*client*/, + unsigned int /*count*/, + XID * /*pids*/); + +extern RESTYPE lastResourceType; +extern RESTYPE TypeMask; + +#ifdef XResExtension +extern Atom *ResourceNames; +void RegisterResourceName(RESTYPE type, char* name); +#endif + +#endif /* RESOURCE_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rgb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rgb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rgb.h (revision 51223) @@ -0,0 +1,54 @@ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: rgb.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef RGB_H +#define RGB_H +typedef struct _RGB { + unsigned short red, green, blue; + } RGB; +#endif /* RGB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rlAccel.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rlAccel.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rlAccel.h (revision 51223) @@ -0,0 +1,141 @@ +/* + * Rootless Acceleration Code + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessCommon.c,v 1.4 2003/10/18 00:00:34 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "fb.h" + +/* + * rlBlt.c + */ +void +rlBlt (FbBits *srcLine, + FbStride srcStride, + int srcX, + + ScreenPtr pDstScreen, + FbBits *dstLine, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp, + + Bool reverse, + Bool upsidedown); + +/* + * rlCopy.c + */ +RegionPtr +rlCopyArea (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut); + +/* + * rlFill.c + */ +void +rlFill (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int width, + int height); + +void +rlSolidBoxClipped (DrawablePtr pDrawable, + RegionPtr pClip, + int x1, + int y1, + int x2, + int y2, + FbBits and, + FbBits xor); + +/* + * rlFillRect.c + */ +void +rlPolyFillRect(DrawablePtr pDrawable, + GCPtr pGC, + int nrect, + xRectangle *prect); + +/* + * rlFillSpans.c + */ +void +rlFillSpans (DrawablePtr pDrawable, + GCPtr pGC, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted); + +/* + * rlGlyph.c + */ +void +rlImageGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppciInit, + pointer pglyphBase); + +/* + * rlSolid.c + */ +void +rlSolid (ScreenPtr pScreen, + FbBits *dst, + FbStride dstStride, + int dstX, + int bpp, + + int width, + int height, + + FbBits and, + FbBits xor); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootless.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootless.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootless.h (revision 51223) @@ -0,0 +1,436 @@ +/* + * External interface to generic rootless mode + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootless.h,v 1.7 2004/07/02 01:30:33 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESS_H +#define _ROOTLESS_H + +#include "rootlessConfig.h" +#include "mi.h" +#include "gcstruct.h" + +/* + Each top-level rootless window has a one-to-one correspondence to a physical + on-screen window. The physical window is refered to as a "frame". + */ + +typedef void * RootlessFrameID; + +/* + * RootlessWindowRec + * This structure stores the per-frame data used by the rootless code. + * Each top-level X window has one RootlessWindowRec associated with it. + */ +typedef struct _RootlessWindowRec { + // Position and size includes the window border + // Position is in per-screen coordinates + int x, y; + unsigned int width, height; + unsigned int borderWidth; + + RootlessFrameID wid; // implementation specific frame id + WindowPtr win; // underlying X window + + // Valid only when drawing (ie. is_drawing is set) + char *pixelData; + int bytesPerRow; + + PixmapPtr pixmap; + PixmapPtr oldPixmap; + +#ifdef ROOTLESS_TRACK_DAMAGE + RegionRec damage; +#endif + + unsigned int is_drawing :1; // Currently drawing? + unsigned int is_reorder_pending :1; +} RootlessWindowRec, *RootlessWindowPtr; + + +/* Offset for screen-local to global coordinate transforms */ +#ifdef ROOTLESS_GLOBAL_COORDS +extern int rootlessGlobalOffsetX; +extern int rootlessGlobalOffsetY; +#endif + +/* The minimum number of bytes or pixels for which to use the + implementation's accelerated functions. */ +extern unsigned int rootless_CopyBytes_threshold; +extern unsigned int rootless_FillBytes_threshold; +extern unsigned int rootless_CompositePixels_threshold; +extern unsigned int rootless_CopyWindow_threshold; + +/* Operations used by CompositePixels */ +enum rl_composite_op_enum { + RL_COMPOSITE_SRC = 0, + RL_COMPOSITE_OVER, +}; + +/* Data formats for depth field and composite functions */ +enum rl_depth_enum { + RL_DEPTH_NIL = 0, /* null source when compositing */ + RL_DEPTH_ARGB8888, + RL_DEPTH_RGB555, + RL_DEPTH_A8, /* for masks when compositing */ + RL_DEPTH_INDEX8, +}; + +/* Macro to form the composite function for CompositePixels */ +#define RL_COMPOSITE_FUNCTION(op, src_depth, mask_depth, dest_depth) \ + (((op) << 24) | ((src_depth) << 16) \ + | ((mask_depth) << 8) | ((dest_depth) << 0)) + +/* Gravity for window contents during resizing */ +enum rl_gravity_enum { + RL_GRAVITY_NONE = 0, /* no gravity, fill everything */ + RL_GRAVITY_NORTH_WEST = 1, /* anchor to top-left corner */ + RL_GRAVITY_NORTH_EAST = 2, /* anchor to top-right corner */ + RL_GRAVITY_SOUTH_EAST = 3, /* anchor to bottom-right corner */ + RL_GRAVITY_SOUTH_WEST = 4, /* anchor to bottom-left corner */ +}; + + +/*------------------------------------------ + Rootless Implementation Functions + ------------------------------------------*/ + +/* + * Create a new frame. + * The frame is created unmapped. + * + * pFrame RootlessWindowPtr for this frame should be completely + * initialized before calling except for pFrame->wid, which + * is set by this function. + * pScreen Screen on which to place the new frame + * newX, newY Position of the frame. These will be identical to pFrame-x, + * pFrame->y unless ROOTLESS_GLOBAL_COORDS is set. + * pNewShape Shape for the frame (in frame-local coordinates). NULL for + * unshaped frames. + */ +typedef Bool (*RootlessCreateFrameProc) + (RootlessWindowPtr pFrame, ScreenPtr pScreen, int newX, int newY, + RegionPtr pNewShape); + +/* + * Destroy a frame. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + */ +typedef void (*RootlessDestroyFrameProc) + (RootlessFrameID wid); + +/* + * Move a frame on screen. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + * pScreen Screen to move the new frame to + * newX, newY New position of the frame + */ +typedef void (*RootlessMoveFrameProc) + (RootlessFrameID wid, ScreenPtr pScreen, int newX, int newY); + +/* + * Resize and move a frame. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + * pScreen Screen to move the new frame to + * newX, newY New position of the frame + * newW, newH New size of the frame + * gravity Gravity for window contents (rl_gravity_enum). This is always + * RL_GRAVITY_NONE unless ROOTLESS_RESIZE_GRAVITY is set. + */ +typedef void (*RootlessResizeFrameProc) + (RootlessFrameID wid, ScreenPtr pScreen, + int newX, int newY, unsigned int newW, unsigned int newH, + unsigned int gravity); + +/* + * Change frame ordering (AKA stacking, layering). + * Drawing is stopped before this is called. Unmapped frames are mapped by + * setting their ordering. + * + * wid Frame id + * nextWid Frame id of frame that is now above this one or NULL if this + * frame is at the top. + */ +typedef void (*RootlessRestackFrameProc) + (RootlessFrameID wid, RootlessFrameID nextWid); + +/* + * Change frame's shape. + * Drawing is stopped before this is called. + * + * wid Frame id + * pNewShape New shape for the frame (in frame-local coordinates) + * or NULL if now unshaped. + */ +typedef void (*RootlessReshapeFrameProc) + (RootlessFrameID wid, RegionPtr pNewShape); + +/* + * Unmap a frame. + * + * wid Frame id + */ +typedef void (*RootlessUnmapFrameProc) + (RootlessFrameID wid); + +/* + * Start drawing to a frame. + * Prepare a frame for direct access to its backing buffer. + * + * wid Frame id + * pixelData Address of the backing buffer (returned) + * bytesPerRow Width in bytes of the backing buffer (returned) + */ +typedef void (*RootlessStartDrawingProc) + (RootlessFrameID wid, char **pixelData, int *bytesPerRow); + +/* + * Stop drawing to a frame. + * No drawing to the frame's backing buffer will occur until drawing + * is started again. + * + * wid Frame id + * flush Flush drawing updates for this frame to the screen. This + * will always be FALSE if ROOTLESS_TRACK_DAMAGE is set. + */ +typedef void (*RootlessStopDrawingProc) + (RootlessFrameID wid, Bool flush); + +/* + * Flush drawing updates to the screen. + * Drawing is stopped before this is called. + * + * wid Frame id + * pDamage Region containing all the changed pixels in frame-lcoal + * coordinates. This is clipped to the window's clip. This + * will be NULL if ROOTLESS_TRACK_DAMAGE is not set. + */ +typedef void (*RootlessUpdateRegionProc) + (RootlessFrameID wid, RegionPtr pDamage); + +/* + * Mark damaged rectangles as requiring redisplay to screen. + * This will only be called if ROOTLESS_TRACK_DAMAGE is not set. + * + * wid Frame id + * nrects Number of damaged rectangles + * rects Array of damaged rectangles in frame-local coordinates + * shift_x, Vector to shift rectangles by + * shift_y + */ +typedef void (*RootlessDamageRectsProc) + (RootlessFrameID wid, int nrects, const BoxRec *rects, + int shift_x, int shift_y); + +/* + * Switch the window associated with a frame. (Optional) + * When a framed window is reparented, the frame is resized and set to + * use the new top-level parent. If defined this function will be called + * afterwards for implementation specific bookkeeping. + * + * pFrame Frame whose window has switched + * oldWin Previous window wrapped by this frame + */ +typedef void (*RootlessSwitchWindowProc) + (RootlessWindowPtr pFrame, WindowPtr oldWin); + +/* + * Check if window should be reordered. (Optional) + * The underlying window system may animate windows being ordered in. + * We want them to be mapped but remain ordered out until the animation + * completes. If defined this function will be called to check if a + * framed window should be reordered now. If this function returns + * FALSE, the window will still be mapped from the X11 perspective, but + * the RestackFrame function will not be called for its frame. + * + * pFrame Frame to reorder + */ +typedef Bool (*RootlessDoReorderWindowProc) + (RootlessWindowPtr pFrame); + +/* + * Copy bytes. (Optional) + * Source and destinate may overlap and the right thing should happen. + * + * width Bytes to copy per row + * height Number of rows + * src Source data + * srcRowBytes Width of source in bytes + * dst Destination data + * dstRowBytes Width of destination in bytes + */ +typedef void (*RootlessCopyBytesProc) + (unsigned int width, unsigned int height, + const void *src, unsigned int srcRowBytes, + void *dst, unsigned int dstRowBytes); + +/* + * Fill memory with 32-bit pattern. (Optional) + * + * width Bytes to fill per row + * height Number of rows + * value 32-bit pattern to fill with + * dst Destination data + * dstRowBytes Width of destination in bytes + */ +typedef void (*RootlessFillBytesProc) + (unsigned int width, unsigned int height, unsigned int value, + void *dst, unsigned int dstRowBytes); + +/* + * Composite pixels from source and mask to destination. (Optional) + * + * width, height Size of area to composite to in pizels + * function Composite function built with RL_COMPOSITE_FUNCTION + * src Source data + * srcRowBytes Width of source in bytes (Passing NULL means source + * is a single pixel. + * mask Mask data + * maskRowBytes Width of mask in bytes + * dst Destination data + * dstRowBytes Width of destination in bytes + * + * For src and dst, the first element of the array is the color data. If + * the second element is non-null it implies there is alpha data (which + * may be meshed or planar). Data without alpha is assumed to be opaque. + * + * An X11 error code is returned. + */ +typedef int (*RootlessCompositePixelsProc) + (unsigned int width, unsigned int height, unsigned int function, + void *src[2], unsigned int srcRowBytes[2], + void *mask, unsigned int maskRowBytes, + void *dst[2], unsigned int dstRowBytes[2]); + +/* + * Copy area in frame to another part of frame. (Optional) + * + * wid Frame id + * dstNrects Number of rectangles to copy + * dstRects Array of rectangles to copy + * dx, dy Number of pixels away to copy area + */ +typedef void (*RootlessCopyWindowProc) + (RootlessFrameID wid, int dstNrects, const BoxRec *dstRects, + int dx, int dy); + +/* + * Rootless implementation function list + */ +typedef struct _RootlessFrameProcs { + RootlessCreateFrameProc CreateFrame; + RootlessDestroyFrameProc DestroyFrame; + + RootlessMoveFrameProc MoveFrame; + RootlessResizeFrameProc ResizeFrame; + RootlessRestackFrameProc RestackFrame; + RootlessReshapeFrameProc ReshapeFrame; + RootlessUnmapFrameProc UnmapFrame; + + RootlessStartDrawingProc StartDrawing; + RootlessStopDrawingProc StopDrawing; + RootlessUpdateRegionProc UpdateRegion; +#ifndef ROOTLESS_TRACK_DAMAGE + RootlessDamageRectsProc DamageRects; +#endif + + /* Optional frame functions */ + RootlessSwitchWindowProc SwitchWindow; + RootlessDoReorderWindowProc DoReorderWindow; + + /* Optional acceleration functions */ + RootlessCopyBytesProc CopyBytes; + RootlessFillBytesProc FillBytes; + RootlessCompositePixelsProc CompositePixels; + RootlessCopyWindowProc CopyWindow; +} RootlessFrameProcsRec, *RootlessFrameProcsPtr; + + +/* + * Initialize rootless mode on the given screen. + */ +Bool RootlessInit(ScreenPtr pScreen, RootlessFrameProcsPtr procs); + +/* + * Initialize acceleration for rootless mode on a given screen. + * Note: RootlessAccelInit() must be called before DamageSetup() + * and RootlessInit() must be called afterwards. + */ +Bool RootlessAccelInit(ScreenPtr pScreen); + +/* + * Return the frame ID for the physical window displaying the given window. + * + * create If true and the window has no frame, attempt to create one + */ +RootlessFrameID RootlessFrameForWindow(WindowPtr pWin, Bool create); + +/* + * Return the top-level parent of a window. + * The root is the top-level parent of itself, even though the root is + * not otherwise considered to be a top-level window. + */ +WindowPtr TopLevelParent(WindowPtr pWindow); + +/* + * Prepare a window for direct access to its backing buffer. + */ +void RootlessStartDrawing(WindowPtr pWindow); + +/* + * Finish drawing to a window's backing buffer. + * + * flush If true and ROOTLESS_TRACK_DAMAGE is set, damaged areas + * are flushed to the screen. + */ +void RootlessStopDrawing(WindowPtr pWindow, Bool flush); + +/* + * Alocate a new screen pixmap. + * miCreateScreenResources does not do this properly with a null + * framebuffer pointer. + */ +void RootlessUpdateScreenPixmap(ScreenPtr pScreen); + +/* + * Reposition all windows on a screen to their correct positions. + */ +void RootlessRepositionWindows(ScreenPtr pScreen); + +#endif /* _ROOTLESS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessCommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessCommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessCommon.h (revision 51223) @@ -0,0 +1,261 @@ +/* + * Common internal rootless definitions and code + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * Copyright (c) 2002-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessCommon.h,v 1.5 2004/07/02 01:30:33 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSCOMMON_H +#define _ROOTLESSCOMMON_H + +#include "rootless.h" +#include "fb.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + + +// Debug output, or not. +#ifdef ROOTLESSDEBUG +#define RL_DEBUG_MSG ErrorF +#else +#define RL_DEBUG_MSG(a, ...) +#endif + + +// Global variables +extern int rootlessGCPrivateIndex; +extern int rootlessScreenPrivateIndex; +extern int rootlessWindowPrivateIndex; + + +// RootlessGCRec: private per-gc data +typedef struct { + GCFuncs *originalFuncs; + GCOps *originalOps; +} RootlessGCRec; + + +// RootlessScreenRec: per-screen private data +typedef struct _RootlessScreenRec { + // Rootless implementation functions + RootlessFrameProcsPtr imp; + + // Wrapped screen functions + CreateScreenResourcesProcPtr CreateScreenResources; + CloseScreenProcPtr CloseScreen; + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + RestackWindowProcPtr RestackWindow; + ReparentWindowProcPtr ReparentWindow; + ChangeBorderWidthProcPtr ChangeBorderWidth; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + + CreateGCProcPtr CreateGC; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + GetImageProcPtr GetImage; + SourceValidateProcPtr SourceValidate; + + MarkOverlappedWindowsProcPtr MarkOverlappedWindows; + ValidateTreeProcPtr ValidateTree; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif + +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif + + void *pixmap_data; + unsigned int pixmap_data_size; + + void *redisplay_timer; + unsigned int redisplay_timer_set :1; + unsigned int redisplay_queued :1; + unsigned int redisplay_expired :1; +} RootlessScreenRec, *RootlessScreenPtr; + + +#undef MIN +#define MIN(x,y) ((x) < (y) ? (x) : (y)) +#undef MAX +#define MAX(x,y) ((x) > (y) ? (x) : (y)) + +// "Definition of the Porting Layer for the X11 Sample Server" says +// unwrap and rewrap of screen functions is unnecessary, but +// screen->CreateGC changes after a call to cfbCreateGC. + +#define SCREEN_UNWRAP(screen, fn) \ + screen->fn = SCREENREC(screen)->fn; + +#define SCREEN_WRAP(screen, fn) \ + SCREENREC(screen)->fn = screen->fn; \ + screen->fn = Rootless##fn + + +// Accessors for screen and window privates + +#define SCREENREC(pScreen) \ + ((RootlessScreenRec *)(pScreen)->devPrivates[rootlessScreenPrivateIndex].ptr) + +#define WINREC(pWin) \ + ((RootlessWindowRec *)(pWin)->devPrivates[rootlessWindowPrivateIndex].ptr) + + +// Call a rootless implementation function. +// Many rootless implementation functions are allowed to be NULL. +#define CallFrameProc(pScreen, proc, params) \ + if (SCREENREC(pScreen)->frameProcs.proc) { \ + RL_DEBUG_MSG("calling frame proc " #proc " "); \ + SCREENREC(pScreen)->frameProcs.proc params; \ + } + + +// BoxRec manipulators +// Copied from shadowfb + +#define TRIM_BOX(box, pGC) { \ + BoxPtr extents = &pGC->pCompositeClip->extents;\ + if(box.x1 < extents->x1) box.x1 = extents->x1; \ + if(box.x2 > extents->x2) box.x2 = extents->x2; \ + if(box.y1 < extents->y1) box.y1 = extents->y1; \ + if(box.y2 > extents->y2) box.y2 = extents->y2; \ +} + +#define TRANSLATE_BOX(box, pDraw) { \ + box.x1 += pDraw->x; \ + box.x2 += pDraw->x; \ + box.y1 += pDraw->y; \ + box.y2 += pDraw->y; \ +} + +#define TRIM_AND_TRANSLATE_BOX(box, pDraw, pGC) { \ + TRANSLATE_BOX(box, pDraw); \ + TRIM_BOX(box, pGC); \ +} + +#define BOX_NOT_EMPTY(box) \ + (((box.x2 - box.x1) > 0) && ((box.y2 - box.y1) > 0)) + + +// HUGE_ROOT and NORMAL_ROOT +// We don't want to clip windows to the edge of the screen. +// HUGE_ROOT temporarily makes the root window really big. +// This is needed as a wrapper around any function that calls +// SetWinSize or SetBorderSize which clip a window against its +// parents, including the root. + +extern RegionRec rootlessHugeRoot; + +#define HUGE_ROOT(pWin) \ + do { \ + WindowPtr w = pWin; \ + while (w->parent) \ + w = w->parent; \ + saveRoot = w->winSize; \ + w->winSize = rootlessHugeRoot; \ + } while (0) + +#define NORMAL_ROOT(pWin) \ + do { \ + WindowPtr w = pWin; \ + while (w->parent) \ + w = w->parent; \ + w->winSize = saveRoot; \ + } while (0) + + +// Returns TRUE if this window is a top-level window (i.e. child of the root) +// The root is not a top-level window. +#define IsTopLevel(pWin) \ + ((pWin) && (pWin)->parent && !(pWin)->parent->parent) + +// Returns TRUE if this window is a root window +#define IsRoot(pWin) \ + ((pWin) == WindowTable[(pWin)->drawable.pScreen->myNum]) + + +/* + * SetPixmapBaseToScreen + * Move the given pixmap's base address to where pixel (0, 0) + * would be if the pixmap's actual data started at (x, y). + * Can't access the bits before the first word of the drawable's data in + * rootless mode, so make sure our base address is always 32-bit aligned. + */ +#define SetPixmapBaseToScreen(pix, _x, _y) { \ + PixmapPtr _pPix = (PixmapPtr) (pix); \ + _pPix->devPrivate.ptr = (char *) (_pPix->devPrivate.ptr) - \ + ((int)(_x) * _pPix->drawable.bitsPerPixel/8 + \ + (int)(_y) * _pPix->devKind); \ + if (_pPix->drawable.bitsPerPixel != FB_UNIT) { \ + unsigned _diff = ((unsigned) _pPix->devPrivate.ptr) & \ + (FB_UNIT / CHAR_BIT - 1); \ + _pPix->devPrivate.ptr = (char *) (_pPix->devPrivate.ptr) - \ + _diff; \ + _pPix->drawable.x = _diff / \ + (_pPix->drawable.bitsPerPixel / CHAR_BIT); \ + } \ +} + + +// Returns TRUE if this window is visible inside a frame +// (e.g. it is visible and has a top-level or root parent) +Bool IsFramedWindow(WindowPtr pWin); + +// Routines that cause regions to get redrawn. +// DamageRegion and DamageRect are in global coordinates. +// DamageBox is in window-local coordinates. +void RootlessDamageRegion(WindowPtr pWindow, RegionPtr pRegion); +void RootlessDamageRect(WindowPtr pWindow, int x, int y, int w, int h); +void RootlessDamageBox(WindowPtr pWindow, BoxPtr pBox); +void RootlessRedisplay(WindowPtr pWindow); +void RootlessRedisplayScreen(ScreenPtr pScreen); + +void RootlessQueueRedisplay(ScreenPtr pScreen); + +// Move a window to its proper location on the screen. +void RootlessRepositionWindow(WindowPtr pWin); + +// Move the window to it's correct place in the physical stacking order. +void RootlessReorderWindow(WindowPtr pWin); + +#endif /* _ROOTLESSCOMMON_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessConfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessConfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessConfig.h (revision 51223) @@ -0,0 +1,68 @@ +/* + * Platform specific rootless configuration + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessConfig.h,v 1.1 2003/04/15 01:05:44 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSCONFIG_H +#define _ROOTLESSCONFIG_H + +#ifdef __DARWIN__ + +# define ROOTLESS_ACCEL TRUE +# define ROOTLESS_GLOBAL_COORDS TRUE +# define ROOTLESS_PROTECT_ALPHA TRUE +# define ROOTLESS_REDISPLAY_DELAY 10 +# define ROOTLESS_RESIZE_GRAVITY TRUE +# undef ROOTLESS_TRACK_DAMAGE + +/* Bit mask for alpha channel with a particular number of bits per + pixel. Note that we only care for 32bpp data. Mac OS X uses planar + alpha for 16bpp. */ +# define RootlessAlphaMask(bpp) ((bpp) == 32 ? 0xFF000000 : 0) + +#endif /* __DARWIN__ */ + +#if defined(__CYGWIN__) || defined(WIN32) + +# define ROOTLESS_ACCEL YES +# define ROOTLESS_GLOBAL_COORDS TRUE +# define ROOTLESS_PROTECT_ALPHA NO +# define ROOTLESS_REDISPLAY_DELAY 10 +# undef ROOTLESS_RESIZE_GRAVITY +# undef ROOTLESS_TRACK_DAMAGE +/*# define ROOTLESSDEBUG*/ + +# define RootlessAlphaMask(bpp) ((bpp) == 32 ? 0xFF000000 : 0) + +#endif /* __CYGWIN__ */ + +#endif /* _ROOTLESSCONFIG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessWindow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessWindow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/rootlessWindow.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * Rootless window management + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessWindow.h,v 1.1 2003/04/15 01:05:44 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSWINDOW_H +#define _ROOTLESSWINDOW_H + +#include "rootlessCommon.h" + + +Bool RootlessCreateWindow(WindowPtr pWin); +Bool RootlessDestroyWindow(WindowPtr pWin); + +#ifdef SHAPE +void RootlessSetShape(WindowPtr pWin); +#endif // SHAPE + +Bool RootlessChangeWindowAttributes(WindowPtr pWin, unsigned long vmask); +Bool RootlessPositionWindow(WindowPtr pWin, int x, int y); +Bool RootlessRealizeWindow(WindowPtr pWin); +Bool RootlessUnrealizeWindow(WindowPtr pWin); +void RootlessRestackWindow(WindowPtr pWin, WindowPtr pOldNextSib); +void RootlessCopyWindow(WindowPtr pWin,DDXPointRec ptOldOrg,RegionPtr prgnSrc); +void RootlessMoveWindow(WindowPtr pWin,int x,int y,WindowPtr pSib,VTKind kind); +void RootlessResizeWindow(WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); +void RootlessReparentWindow(WindowPtr pWin, WindowPtr pPriorParent); +void RootlessPaintWindowBackground(WindowPtr pWin, RegionPtr pRegion, + int what); +void RootlessPaintWindowBorder(WindowPtr pWin, RegionPtr pRegion, + int what); +void RootlessChangeBorderWidth(WindowPtr pWin, unsigned int width); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/safeAlpha.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/safeAlpha.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/safeAlpha.h (revision 51223) @@ -0,0 +1,45 @@ +/* + * Replacement functions to protect the alpha channel + */ +/* + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/safeAlpha/safeAlpha.h,v 1.2 2003/10/18 00:00:34 torrey Exp $ */ + +#ifndef _SAFEALPHA_H +#define _SAFEALPHA_H + +#include "picturestr.h" + +void SafeAlphaPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + +#ifdef RENDER +void +SafeAlphaComposite(CARD8 op, PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst, + INT16 xSrc, INT16 ySrc, INT16 xMask, INT16 yMask, + INT16 xDst, INT16 yDst, CARD16 width, CARD16 height); +#endif /* RENDER */ + +#endif /* _SAFEALPHA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sarea.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sarea.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sarea.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/sarea.h,v 1.11 2002/10/30 12:52:03 alanh Exp $ */ +/** + * \file sarea.h + * SAREA definitions. + * + * \author Kevin E. Martin + * \author Jens Owen + * \author Rickard E. (Rik) Faith + */ + +/* + * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/GL/dri/sarea.h,v 1.11 2002/10/30 12:52:03 alanh Exp $ */ + +#ifndef _SAREA_H_ +#define _SAREA_H_ + +#include "xf86drm.h" + +/* SAREA area needs to be at least a page */ +#if defined(__alpha__) +#define SAREA_MAX 0x2000 +#elif defined(__ia64__) +#define SAREA_MAX 0x10000 /* 64kB */ +#else +/* Intel 830M driver needs at least 8k SAREA */ +#define SAREA_MAX 0x2000 +#endif + +#define SAREA_MAX_DRAWABLES 256 + +#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 + +/** + * SAREA per drawable information. + * + * \sa _XF86DRISAREA. + */ +typedef struct _XF86DRISAREADrawable { + unsigned int stamp; + unsigned int flags; +} XF86DRISAREADrawableRec, *XF86DRISAREADrawablePtr; + +/** + * SAREA frame information. + * + * \sa _XF86DRISAREA. + */ +typedef struct _XF86DRISAREAFrame { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; +} XF86DRISAREAFrameRec, *XF86DRISAREAFramePtr; + +/** + * SAREA definition. + */ +typedef struct _XF86DRISAREA { + /** first thing is always the DRM locking structure */ + drmLock lock; + /** \todo Use readers/writer lock for drawable_lock */ + drmLock drawable_lock; + XF86DRISAREADrawableRec drawableTable[SAREA_MAX_DRAWABLES]; + XF86DRISAREAFrameRec frame; + drm_context_t dummy_context; +} XF86DRISAREARec, *XF86DRISAREAPtr; + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sco_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sco_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sco_kbd.h (revision 51223) @@ -0,0 +1,20 @@ +/* $XFree86$ */ +#ifndef SCO_KBD_HDR +#define SCO_KBD_HDR + +typedef struct { + int use_tcs; + int use_kd; + int no_nmap; + int no_emap; + int orig_getsc; + int orig_kbm; + struct termios kbdtty; + keymap_t keymap, noledmap; + uchar_t *sc_mapbuf; + uchar_t *sc_mapbuf2; +} ScoKbdPrivRec, *ScoKbdPrivPtr; + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); +#endif /* SCO_KBD_HDR */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scoasm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scoasm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scoasm.h (revision 51223) @@ -0,0 +1,143 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/scoasm.h,v 3.1 2003/08/24 17:36:49 dawes Exp $ */ + +/* + * Copyright (c) 1996 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * scoasm.h - used to define inline versions of certain functions which + * do NOT appear in sys/inline.h. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if defined(__SCO__) && defined(__USLC__) +#ifndef _SCOASM_HDR_INC +#define _SCOASM_HDR_INC + +asm void outl(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + outl (%dx) +%reg port; mem val; + movl port, %edx + movl val, %eax + outl (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + outl (%dx) +%mem port,val; + movw port, %dx + movl val, %eax + outl (%dx) +} + +asm void outw(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + data16 + outl (%dx) +%reg port; mem val; + movl port, %edx + movw val, %ax + data16 + outl (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + data16 + outl (%dx) +%mem port,val; + movw port, %dx + movw val, %ax + data16 + outl (%dx) +} + +asm void outb(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + outb (%dx) +%reg port; mem val; + movl port, %edx + movb val, %al + outb (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + outb (%dx) +%mem port,val; + movw port, %dx + movb val, %al + outb (%dx) +} + +asm int inl(port) +{ +%reg port; + movl port, %edx + inl (%dx) +%mem port; + movw port, %dx + inl (%dx) +} + +asm int inw(port) +{ +%reg port; + subl %eax, %eax + movl port, %edx + data16 + inl (%dx) +%mem port; + subl %eax, %eax + movw port, %dx + data16 + inl (%dx) +} + +asm int inb(port) +{ +%reg port; + subl %eax, %eax + movl port, %edx + inb (%dx) +%mem port; + subl %eax, %eax + movw port, %dx + inb (%dx) +} + +#endif /* _SCOASM_HDR_INC */ +#endif /* __SCO__ && __USLC__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/screen-cfg.h,v 1.1 2000/04/04 22:37:02 dawes Exp $ + */ + +#include "config.h" +#include "screen.h" + +#ifndef _xf86cfg_screencfg_h +#define _xf86cfg_screencfg_h + +/* + * Prototypes + */ +XtPointer ScreenConfig(XtPointer); +void ScreenDialog(XF86SetupInfo*); + +#endif /* _xf86cfg_screencfg_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screen.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/screen.h,v 1.1 2000/04/04 22:37:02 dawes Exp $ + */ + +#include "xf86config.h" +#include "config.h" + +#ifndef _xf86cfg_screen_h +#define _xf86cfg_screen_h + +/* + * Prototypes + */ +void AddScreen(xf86cfgDevice*, xf86cfgDevice*); +void RemoveScreen(xf86cfgDevice*, xf86cfgDevice*); + +void DrawScreen(Display*, Drawable, int, int, int, int, Bool, int); +void DrawScreenMask(Display*, Drawable, GC, int, int, int, int, int); +void CreateScreenWidget(xf86cfgScreen*); +void SetScreenRotate(xf86cfgScreen*); + +void AdjustScreenUI(void); +void UpdateScreenUI(void); + +#endif /* _xf86cfg_screen_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screenint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screenint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/screenint.h (revision 51223) @@ -0,0 +1,113 @@ +/* $Xorg: screenint.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/screenint.h,v 1.5 2001/12/14 19:59:56 dawes Exp $ */ + +#ifndef SCREENINT_H +#define SCREENINT_H + +#include "misc.h" + +typedef struct _PixmapFormat *PixmapFormatPtr; +typedef struct _Visual *VisualPtr; +typedef struct _Depth *DepthPtr; +typedef struct _Screen *ScreenPtr; + +extern void ResetScreenPrivates(void); + +extern int AllocateScreenPrivateIndex(void); + +extern void ResetWindowPrivates(void); + +extern int AllocateWindowPrivateIndex(void); + +extern Bool AllocateWindowPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +extern void ResetGCPrivates(void); + +extern int AllocateGCPrivateIndex(void); + +extern Bool AllocateGCPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +extern int AddScreen( + Bool (* /*pfnInit*/)( + int /*index*/, + ScreenPtr /*pScreen*/, + int /*argc*/, + char ** /*argv*/), + int /*argc*/, + char** /*argv*/); + +#ifdef PIXPRIV + +extern void ResetPixmapPrivates(void); + +extern int AllocatePixmapPrivateIndex(void); + +extern Bool AllocatePixmapPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +#endif /* PIXPRIV */ + +extern void ResetColormapPrivates(void); + + +typedef struct _ColormapRec *ColormapPtr; +typedef int (*InitCmapPrivFunc)(ColormapPtr, int); + +extern int AllocateColormapPrivateIndex( + InitCmapPrivFunc /* initPrivFunc */); + +#endif /* SCREENINT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scrnintstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scrnintstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/scrnintstr.h (revision 51223) @@ -0,0 +1,733 @@ +/* $Xorg: scrnintstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/scrnintstr.h,v 1.12 2003/04/27 21:31:05 herrb Exp $ */ + +#ifndef SCREENINTSTRUCT_H +#define SCREENINTSTRUCT_H + +#include "screenint.h" +#include "regionstr.h" +#include "bstore.h" +#include "colormap.h" +#include "cursor.h" +#include "validate.h" +#include +#include "dix.h" + +typedef struct _PixmapFormat { + unsigned char depth; + unsigned char bitsPerPixel; + unsigned char scanlinePad; + } PixmapFormatRec; + +typedef struct _Visual { + VisualID vid; + short class; + short bitsPerRGBValue; + short ColormapEntries; + short nplanes;/* = log2 (ColormapEntries). This does not + * imply that the screen has this many planes. + * it may have more or fewer */ + unsigned long redMask, greenMask, blueMask; + int offsetRed, offsetGreen, offsetBlue; + } VisualRec; + +typedef struct _Depth { + unsigned char depth; + short numVids; + VisualID *vids; /* block of visual ids for this depth */ + } DepthRec; + + +/* + * There is a typedef for each screen function pointer so that code that + * needs to declare a screen function pointer (e.g. in a screen private + * or as a local variable) can easily do so and retain full type checking. + */ + +typedef Bool (* CloseScreenProcPtr)( + int /*index*/, + ScreenPtr /*pScreen*/); + +typedef void (* QueryBestSizeProcPtr)( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/); + +typedef Bool (* SaveScreenProcPtr)( + ScreenPtr /*pScreen*/, + int /*on*/); + +typedef void (* GetImageProcPtr)( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/); + +typedef void (* GetSpansProcPtr)( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int* /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/); + +typedef void (* PointerNonInterestBoxProcPtr)( + ScreenPtr /*pScreen*/, + BoxPtr /*pBox*/); + +typedef void (* SourceValidateProcPtr)( + DrawablePtr /*pDrawable*/, + int /*x*/, + int /*y*/, + int /*width*/, + int /*height*/); + +typedef Bool (* CreateWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* DestroyWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* PositionWindowProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/); + +typedef Bool (* ChangeWindowAttributesProcPtr)( + WindowPtr /*pWindow*/, + unsigned long /*mask*/); + +typedef Bool (* RealizeWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* UnrealizeWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef void (* RestackWindowProcPtr)( + WindowPtr /*pWindow*/, + WindowPtr /*pOldNextSib*/); + +typedef int (* ValidateTreeProcPtr)( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/); + +typedef void (* PostValidateTreeProcPtr)( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/); + +typedef void (* WindowExposuresProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgn*/, + RegionPtr /*other_exposed*/); + +typedef void (* PaintWindowProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*pRegion*/, + int /*what*/); + +typedef PaintWindowProcPtr PaintWindowBackgroundProcPtr; +typedef PaintWindowProcPtr PaintWindowBorderProcPtr; + +typedef void (* CopyWindowProcPtr)( + WindowPtr /*pWindow*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/); + +typedef void (* ClearToBackgroundProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/); + +typedef void (* ClipNotifyProcPtr)( + WindowPtr /*pWindow*/, + int /*dx*/, + int /*dy*/); + +typedef PixmapPtr (* CreatePixmapProcPtr)( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/); + +typedef Bool (* DestroyPixmapProcPtr)( + PixmapPtr /*pPixmap*/); + +typedef void (* SaveDoomedAreasProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/); + +typedef RegionPtr (* RestoreAreasProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgnRestore*/); + +typedef void (* ExposeCopyProcPtr)( + WindowPtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + RegionPtr /*prgnExposed*/, + int /*srcx*/, + int /*srcy*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/); + +typedef RegionPtr (* TranslateBackingStoreProcPtr)( + WindowPtr /*pWindow*/, + int /*windx*/, + int /*windy*/, + RegionPtr /*oldClip*/, + int /*oldx*/, + int /*oldy*/); + +typedef RegionPtr (* ClearBackingStoreProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/); + +typedef void (* DrawGuaranteeProcPtr)( + WindowPtr /*pWindow*/, + GCPtr /*pGC*/, + int /*guarantee*/); + +typedef Bool (* RealizeFontProcPtr)( + ScreenPtr /*pScreen*/, + FontPtr /*pFont*/); + +typedef Bool (* UnrealizeFontProcPtr)( + ScreenPtr /*pScreen*/, + FontPtr /*pFont*/); + +typedef void (* ConstrainCursorProcPtr)( + ScreenPtr /*pScreen*/, + BoxPtr /*pBox*/); + +typedef void (* CursorLimitsProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + BoxPtr /*pHotBox*/, + BoxPtr /*pTopLeftBox*/); + +typedef Bool (* DisplayCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef Bool (* RealizeCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef Bool (* UnrealizeCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef void (* RecolorCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + Bool /*displayed*/); + +typedef Bool (* SetCursorPositionProcPtr)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + Bool /*generateEvent*/); + +typedef Bool (* CreateGCProcPtr)( + GCPtr /*pGC*/); + +typedef Bool (* CreateColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* DestroyColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* InstallColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* UninstallColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef int (* ListInstalledColormapsProcPtr) ( + ScreenPtr /*pScreen*/, + XID* /*pmaps */); + +typedef void (* StoreColorsProcPtr)( + ColormapPtr /*pColormap*/, + int /*ndef*/, + xColorItem * /*pdef*/); + +typedef void (* ResolveColorProcPtr)( + unsigned short* /*pred*/, + unsigned short* /*pgreen*/, + unsigned short* /*pblue*/, + VisualPtr /*pVisual*/); + +#ifdef NEED_SCREEN_REGIONS + +typedef RegionPtr (* RegionCreateProcPtr)( + BoxPtr /*rect*/, + int /*size*/); + +typedef void (* RegionInitProcPtr)( + RegionPtr /*pReg*/, + BoxPtr /*rect*/, + int /*size*/); + +typedef Bool (* RegionCopyProcPtr)( + RegionPtr /*dst*/, + RegionPtr /*src*/); + +typedef void (* RegionDestroyProcPtr)( + RegionPtr /*pReg*/); + +typedef void (* RegionUninitProcPtr)( + RegionPtr /*pReg*/); + +typedef Bool (* IntersectProcPtr)( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +typedef Bool (* UnionProcPtr)( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +typedef Bool (* SubtractProcPtr)( + RegionPtr /*regD*/, + RegionPtr /*regM*/, + RegionPtr /*regS*/); + +typedef Bool (* InverseProcPtr)( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + BoxPtr /*invRect*/); + +typedef void (* RegionResetProcPtr)( + RegionPtr /*pReg*/, + BoxPtr /*pBox*/); + +typedef void (* TranslateRegionProcPtr)( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/); + +typedef int (* RectInProcPtr)( + RegionPtr /*region*/, + BoxPtr /*prect*/); + +typedef Bool (* PointInRegionProcPtr)( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/, + BoxPtr /*box*/); + +typedef Bool (* RegionNotEmptyProcPtr)( + RegionPtr /*pReg*/); + +typedef Bool (* RegionEqualProcPtr)( + RegionPtr /*pReg1*/, + RegionPtr /*pReg2*/); + +typedef Bool (* RegionBrokenProcPtr)( + RegionPtr /*pReg*/); + +typedef Bool (* RegionBreakProcPtr)( + RegionPtr /*pReg*/); + +typedef void (* RegionEmptyProcPtr)( + RegionPtr /*pReg*/); + +typedef BoxPtr (* RegionExtentsProcPtr)( + RegionPtr /*pReg*/); + +typedef Bool (* RegionAppendProcPtr)( + RegionPtr /*dstrgn*/, + RegionPtr /*rgn*/); + +typedef Bool (* RegionValidateProcPtr)( + RegionPtr /*badreg*/, + Bool* /*pOverlap*/); + +#endif /* NEED_SCREEN_REGIONS */ + +typedef RegionPtr (* BitmapToRegionProcPtr)( + PixmapPtr /*pPix*/); + +#ifdef NEED_SCREEN_REGIONS + +typedef RegionPtr (* RectsToRegionProcPtr)( + int /*nrects*/, + xRectangle* /*prect*/, + int /*ctype*/); + +#endif /* NEED_SCREEN_REGIONS */ + +typedef void (* SendGraphicsExposeProcPtr)( + ClientPtr /*client*/, + RegionPtr /*pRgn*/, + XID /*drawable*/, + int /*major*/, + int /*minor*/); + +typedef void (* ScreenBlockHandlerProcPtr)( + int /*screenNum*/, + pointer /*blockData*/, + pointer /*pTimeout*/, + pointer /*pReadmask*/); + +typedef void (* ScreenWakeupHandlerProcPtr)( + int /*screenNum*/, + pointer /*wakeupData*/, + unsigned long /*result*/, + pointer /*pReadMask*/); + +typedef Bool (* CreateScreenResourcesProcPtr)( + ScreenPtr /*pScreen*/); + +typedef Bool (* ModifyPixmapHeaderProcPtr)( + PixmapPtr /*pPixmap*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/); + +typedef PixmapPtr (* GetWindowPixmapProcPtr)( + WindowPtr /*pWin*/); + +typedef void (* SetWindowPixmapProcPtr)( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/); + +typedef PixmapPtr (* GetScreenPixmapProcPtr)( + ScreenPtr /*pScreen*/); + +typedef void (* SetScreenPixmapProcPtr)( + PixmapPtr /*pPix*/); + +typedef void (* MarkWindowProcPtr)( + WindowPtr /*pWin*/); + +typedef Bool (* MarkOverlappedWindowsProcPtr)( + WindowPtr /*parent*/, + WindowPtr /*firstChild*/, + WindowPtr * /*pLayerWin*/); + +typedef Bool (* ChangeSaveUnderProcPtr)( + WindowPtr /*pLayerWin*/, + WindowPtr /*firstChild*/); + +typedef void (* PostChangeSaveUnderProcPtr)( + WindowPtr /*pLayerWin*/, + WindowPtr /*firstChild*/); + +typedef void (* MoveWindowProcPtr)( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + WindowPtr /*pSib*/, + VTKind /*kind*/); + +typedef void (* ResizeWindowProcPtr)( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + WindowPtr /*pSib*/ +); + +typedef WindowPtr (* GetLayerWindowProcPtr)( + WindowPtr /*pWin*/ +); + +typedef void (* HandleExposuresProcPtr)( + WindowPtr /*pWin*/); + +typedef void (* ReparentWindowProcPtr)( + WindowPtr /*pWin*/, + WindowPtr /*pPriorParent*/); + +#ifdef SHAPE +typedef void (* SetShapeProcPtr)( + WindowPtr /*pWin*/); +#endif /* SHAPE */ + +typedef void (* ChangeBorderWidthProcPtr)( + WindowPtr /*pWin*/, + unsigned int /*width*/); + +typedef void (* MarkUnrealizedWindowProcPtr)( + WindowPtr /*pChild*/, + WindowPtr /*pWin*/, + Bool /*fromConfigure*/); + +typedef struct _Screen { + int myNum; /* index of this instance in Screens[] */ + ATOM id; + short width, height; + short mmWidth, mmHeight; + short numDepths; + unsigned char rootDepth; + DepthPtr allowedDepths; + unsigned long rootVisual; + unsigned long defColormap; + short minInstalledCmaps, maxInstalledCmaps; + char backingStoreSupport, saveUnderSupport; + unsigned long whitePixel, blackPixel; + unsigned long rgf; /* array of flags; she's -- HUNGARIAN */ + GCPtr GCperDepth[MAXFORMATS+1]; + /* next field is a stipple to use as default in + a GC. we don't build default tiles of all depths + because they are likely to be of a color + different from the default fg pixel, so + we don't win anything by building + a standard one. + */ + PixmapPtr PixmapPerDepth[1]; + pointer devPrivate; + short numVisuals; + VisualPtr visuals; + int WindowPrivateLen; + unsigned *WindowPrivateSizes; + unsigned totalWindowSize; + int GCPrivateLen; + unsigned *GCPrivateSizes; + unsigned totalGCSize; + + /* Random screen procedures */ + + CloseScreenProcPtr CloseScreen; + QueryBestSizeProcPtr QueryBestSize; + SaveScreenProcPtr SaveScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PointerNonInterestBoxProcPtr PointerNonInterestBox; + SourceValidateProcPtr SourceValidate; + + /* Window Procedures */ + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + ValidateTreeProcPtr ValidateTree; + PostValidateTreeProcPtr PostValidateTree; + WindowExposuresProcPtr WindowExposures; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + ClearToBackgroundProcPtr ClearToBackground; + ClipNotifyProcPtr ClipNotify; + RestackWindowProcPtr RestackWindow; + + /* Pixmap procedures */ + + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + + /* Backing store procedures */ + + SaveDoomedAreasProcPtr SaveDoomedAreas; + RestoreAreasProcPtr RestoreAreas; + ExposeCopyProcPtr ExposeCopy; + TranslateBackingStoreProcPtr TranslateBackingStore; + ClearBackingStoreProcPtr ClearBackingStore; + DrawGuaranteeProcPtr DrawGuarantee; + /* + * A read/write copy of the lower level backing store vector is needed now + * that the functions can be wrapped. + */ + BSFuncRec BackingStoreFuncs; + + /* Font procedures */ + + RealizeFontProcPtr RealizeFont; + UnrealizeFontProcPtr UnrealizeFont; + + /* Cursor Procedures */ + + ConstrainCursorProcPtr ConstrainCursor; + CursorLimitsProcPtr CursorLimits; + DisplayCursorProcPtr DisplayCursor; + RealizeCursorProcPtr RealizeCursor; + UnrealizeCursorProcPtr UnrealizeCursor; + RecolorCursorProcPtr RecolorCursor; + SetCursorPositionProcPtr SetCursorPosition; + + /* GC procedures */ + + CreateGCProcPtr CreateGC; + + /* Colormap procedures */ + + CreateColormapProcPtr CreateColormap; + DestroyColormapProcPtr DestroyColormap; + InstallColormapProcPtr InstallColormap; + UninstallColormapProcPtr UninstallColormap; + ListInstalledColormapsProcPtr ListInstalledColormaps; + StoreColorsProcPtr StoreColors; + ResolveColorProcPtr ResolveColor; + + /* Region procedures */ + +#ifdef NEED_SCREEN_REGIONS + RegionCreateProcPtr RegionCreate; + RegionInitProcPtr RegionInit; + RegionCopyProcPtr RegionCopy; + RegionDestroyProcPtr RegionDestroy; + RegionUninitProcPtr RegionUninit; + IntersectProcPtr Intersect; + UnionProcPtr Union; + SubtractProcPtr Subtract; + InverseProcPtr Inverse; + RegionResetProcPtr RegionReset; + TranslateRegionProcPtr TranslateRegion; + RectInProcPtr RectIn; + PointInRegionProcPtr PointInRegion; + RegionNotEmptyProcPtr RegionNotEmpty; + RegionEqualProcPtr RegionEqual; + RegionBrokenProcPtr RegionBroken; + RegionBreakProcPtr RegionBreak; + RegionEmptyProcPtr RegionEmpty; + RegionExtentsProcPtr RegionExtents; + RegionAppendProcPtr RegionAppend; + RegionValidateProcPtr RegionValidate; +#endif /* NEED_SCREEN_REGIONS */ + BitmapToRegionProcPtr BitmapToRegion; +#ifdef NEED_SCREEN_REGIONS + RectsToRegionProcPtr RectsToRegion; +#endif /* NEED_SCREEN_REGIONS */ + SendGraphicsExposeProcPtr SendGraphicsExpose; + + /* os layer procedures */ + + ScreenBlockHandlerProcPtr BlockHandler; + ScreenWakeupHandlerProcPtr WakeupHandler; + + pointer blockData; + pointer wakeupData; + + /* anybody can get a piece of this array */ + DevUnion *devPrivates; + + CreateScreenResourcesProcPtr CreateScreenResources; + ModifyPixmapHeaderProcPtr ModifyPixmapHeader; + + GetWindowPixmapProcPtr GetWindowPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + GetScreenPixmapProcPtr GetScreenPixmap; + SetScreenPixmapProcPtr SetScreenPixmap; + + PixmapPtr pScratchPixmap; /* scratch pixmap "pool" */ + +#ifdef PIXPRIV + int PixmapPrivateLen; + unsigned int *PixmapPrivateSizes; + unsigned int totalPixmapSize; +#endif + + MarkWindowProcPtr MarkWindow; + MarkOverlappedWindowsProcPtr MarkOverlappedWindows; + ChangeSaveUnderProcPtr ChangeSaveUnder; + PostChangeSaveUnderProcPtr PostChangeSaveUnder; + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + GetLayerWindowProcPtr GetLayerWindow; + HandleExposuresProcPtr HandleExposures; + ReparentWindowProcPtr ReparentWindow; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif /* SHAPE */ + + ChangeBorderWidthProcPtr ChangeBorderWidth; + MarkUnrealizedWindowProcPtr MarkUnrealizedWindow; + +} ScreenRec; + +typedef struct _ScreenInfo { + int imageByteOrder; + int bitmapScanlineUnit; + int bitmapScanlinePad; + int bitmapBitOrder; + int numPixmapFormats; + PixmapFormatRec + formats[MAXFORMATS]; + int arraySize; + int numScreens; + ScreenPtr screens[MAXSCREENS]; + int numVideoScreens; +} ScreenInfo; + +extern ScreenInfo screenInfo; + +extern void InitOutput( + ScreenInfo * /*pScreenInfo*/, + int /*argc*/, + char ** /*argv*/); + +#endif /* SCREENINTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selectev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selectev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selectev.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/selectev.h,v 3.1 1996/04/15 11:19:01 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SELECTEV_H +#define SELECTEV_H 1 + +int +SProcXSelectExtensionEvent ( + ClientPtr /* client */ + ); + +int +ProcXSelectExtensionEvent ( + ClientPtr /* client */ + ); + +#endif /* SELECTEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selection.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selection.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/selection.h (revision 51223) @@ -0,0 +1,69 @@ +/* $Xorg: selection.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ + +#ifndef SELECTION_H +#define SELECTION_H 1 + +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#include "dixstruct.h" +/* + * + * Selection data structures + */ + +typedef struct _Selection { + Atom selection; + TimeStamp lastTimeChanged; + Window window; + WindowPtr pWin; + ClientPtr client; +} Selection; + +#endif /* SELECTION_H */ + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sendexev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sendexev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sendexev.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/sendexev.h,v 3.1 1996/04/15 11:19:02 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SENDEXEV_H +#define SENDEXEV_H 1 + +int +SProcXSendExtensionEvent( + ClientPtr /* client */ + ); + +int +ProcXSendExtensionEvent( + ClientPtr /* client */ + ); + +#endif /* SENDEXEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/servermd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/servermd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/servermd.h (revision 51223) @@ -0,0 +1,583 @@ +/* $XFree86: xc/programs/Xserver/include/servermd.h,v 3.56tsi Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: servermd.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* $XdotOrg: xc/programs/Xserver/include/servermd.h,v 1.4 2005/05/21 07:46:38 alanc Exp $ */ + +#ifndef SERVERMD_H +#define SERVERMD_H 1 + +/* + * Machine dependent values: + * GLYPHPADBYTES should be chosen with consideration for the space-time + * trade-off. Padding to 0 bytes means that there is no wasted space + * in the font bitmaps (both on disk and in memory), but that access of + * the bitmaps will cause odd-address memory references. Padding to + * 2 bytes would ensure even address memory references and would + * be suitable for a 68010-class machine, but at the expense of wasted + * space in the font bitmaps. Padding to 4 bytes would be good + * for real 32 bit machines, etc. Be sure that you tell the font + * compiler what kind of padding you want because its defines are + * kept separate from this. See server/include/font.h for how + * GLYPHPADBYTES is used. + * + * Along with this, you should choose an appropriate value for + * GETLEFTBITS_ALIGNMENT, which is used in ddx/mfb/maskbits.h. This + * constant choses what kind of memory references are guarenteed during + * font access; either 1, 2 or 4, for byte, word or longword access, + * respectively. For instance, if you have decided to to have + * GLYPHPADBYTES == 4, then it is pointless for you to have a + * GETLEFTBITS_ALIGNMENT > 1, because the padding of the fonts has already + * guarenteed you that your fonts are longword aligned. On the other + * hand, even if you have chosen GLYPHPADBYTES == 1 to save space, you may + * also decide that the computing involved in aligning the pointer is more + * costly than an odd-address access; you choose GETLEFTBITS_ALIGNMENT == 1. + * + * Next, choose the tuning parameters which are appropriate for your + * hardware; these modify the behaviour of the raw frame buffer code + * in ddx/mfb and ddx/cfb. Defining these incorrectly will not cause + * the server to run incorrectly, but defining these correctly will + * cause some noticeable speed improvements: + * + * AVOID_MEMORY_READ - (8-bit cfb only) + * When stippling pixels on the screen (polytext and pushpixels), + * don't read long words from the display and mask in the + * appropriate values. Rather, perform multiple byte/short/long + * writes as appropriate. This option uses many more instructions + * but runs much faster when the destination is much slower than + * the CPU and at least 1 level of write buffer is availible (2 + * is much better). Defined currently for SPARC and MIPS. + * + * FAST_CONSTANT_OFFSET_MODE - (cfb and mfb) + * This define is used on machines which have no auto-increment + * addressing mode, but do have an effectively free constant-offset + * addressing mode. Currently defined for MIPS and SPARC, even though + * I remember the cg6 as performing better without it (cg3 definitely + * performs better with it). + * + * LARGE_INSTRUCTION_CACHE - + * This define increases the number of times some loops are + * unrolled. On 68020 machines (with 256 bytes of i-cache), + * this define will slow execution down as instructions miss + * the cache frequently. On machines with real i-caches, this + * reduces loop overhead, causing a slight performance improvement. + * Currently defined for MIPS and SPARC + * + * FAST_UNALIGNED_READS - + * For machines with more memory bandwidth than CPU, this + * define uses unaligned reads for 8-bit BitBLT instead of doing + * aligned reads and combining the results with shifts and + * logical-ors. Currently defined for 68020 and vax. + * PLENTIFUL_REGISTERS - + * For machines with > 20 registers. Currently used for + * unrolling the text painting code a bit more. Currently + * defined for MIPS. + * SHARED_IDCACHE - + * For non-Harvard RISC machines, those which share the same + * CPU memory bus for instructions and data. This unrolls some + * solid fill loops which are otherwise best left rolled up. + * Currently defined for SPARC. + */ + +#ifdef vax + +#define IMAGE_BYTE_ORDER LSBFirst /* Values for the VAX only */ +#define BITMAP_BIT_ORDER LSBFirst +#define GLYPHPADBYTES 1 +#define GETLEFTBITS_ALIGNMENT 4 +#define FAST_UNALIGNED_READS + +#endif /* vax */ + +#ifdef __arm32__ + +#define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#define LARGE_INSTRUCTION_CACHE +#define AVOID_MEMORY_READ + +#endif /* __arm32__ */ + +#if defined (hpux) || defined __hppa__ + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 /* to make fb work */ +#define GETLEFTBITS_ALIGNMENT 1 /* PA forces longs to 4 */ + /* byte boundries */ +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* hpux || __hppa__ */ + +#if defined(__powerpc__) || defined(__ppc__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +/* XXX Should this be for Lynx only? */ +#ifdef Lynx +#define BITMAP_SCANLINE_UNIT 8 +#endif + +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define PLENTIFUL_REGISTERS +#define AVOID_MEMORY_READ + +#define FAST_MEMCPY + +#endif /* PowerPC */ + +#if defined(__sh__) + +#if defined(__BIG_ENDIAN__) +# define IMAGE_BYTE_ORDER MSBFirst +# define BITMAP_BIT_ORDER MSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#else +# define IMAGE_BYTE_ORDER LSBFirst +# define BITMAP_BIT_ORDER LSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#endif + +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* SuperH */ + + +#if (defined(sun) && (defined(__sparc) || defined(sparc))) || \ + (defined(__uxp__) && (defined(sparc) || defined(mc68000))) || \ + defined(__sparc__) || defined(__mc68000__) + +#if defined(__sparc) || defined(__sparc__) +# if !defined(sparc) +# define sparc 1 +# endif +#endif + +#if defined(sun386) || defined(sun5) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the SUN only */ +# define BITMAP_BIT_ORDER LSBFirst +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the SUN only */ +# define BITMAP_BIT_ORDER MSBFirst +#endif + +#ifdef sparc +# define AVOID_MEMORY_READ +# define LARGE_INSTRUCTION_CACHE +# define FAST_CONSTANT_OFFSET_MODE +# define SHARED_IDCACHE +#endif + +#ifdef mc68020 +#define FAST_UNALIGNED_READS +#endif + +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#endif /* sun && !(i386 && SVR4) */ + + +#if defined(AIXV3) + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the RISC/6000 */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define PLENTIFUL_REGISTERS +#define AVOID_MEMORY_READ + +#define FAST_MEMCPY +#endif /* AIXV3 */ + +#if defined(ibm032) || defined (ibm) + +#ifdef i386 +# define IMAGE_BYTE_ORDER LSBFirst /* Value for PS/2 only */ +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the RT only*/ +#endif +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 1 +#define GETLEFTBITS_ALIGNMENT 4 +/* ibm pcc doesn't understand pragmas. */ + +#ifdef i386 +#define BITMAP_SCANLINE_UNIT 8 +#endif + +#endif /* ibm */ + +#if defined (M4310) || defined(M4315) || defined(M4317) || defined(M4319) || defined(M4330) + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for Pegasus only */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define FAST_UNALIGNED_READS + +#endif /* tektronix */ + +#ifdef macII + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the MacII only */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +/* might want FAST_UNALIGNED_READS for frame buffers with < 1us latency */ + +#endif /* macII */ + +#if (defined(mips) || defined(__mips)) && !defined(sgi) + +#if defined(MIPSEL) || defined(__MIPSEL__) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the PMAX only */ +# define BITMAP_BIT_ORDER LSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the MIPS only */ +# define BITMAP_BIT_ORDER MSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#endif + +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* mips */ + +#if defined(__alpha) || defined(__alpha__) || defined(__alphaCross) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the Alpha only */ + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define FAST_CONSTANT_OFFSET_MODE +# define LARGE_INSTRUCTION_CACHE +# define PLENTIFUL_REGISTERS + +#endif /* alpha */ + +#if defined (linux) && defined (__s390__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define BITMAP_SCANLINE_UNIT 8 +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_UNALIGNED_READ + +#define FAST_MEMCPY + +#endif /* linux/s390 */ + +#if defined (linux) && defined (__s390x__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define BITMAP_SCANLINE_UNIT 8 +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_UNALIGNED_READ + +#define FAST_MEMCPY +#endif /* linux/s390x */ + + +#if defined(__ia64__) || defined(ia64) +# define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define FAST_CONSTANT_OFFSET_MODE +# define LARGE_INSTRUCTION_CACHE +# define PLENTIFUL_REGISTERS + +#endif /* ia64 */ + +#if defined(__amd64__) || defined(amd64) || defined(__amd64) +# define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define LARGE_INSTRUCTION_CACHE +# define FAST_CONSTANT_OFFSET_MODE +/* ???? */ +# define FAST_UNALIGNED_READS +#endif /* AMD64 */ + +#ifdef stellar + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the stellar only*/ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 4 +#define IMAGE_BUFSIZE (64*1024) +/* + * Use SysV random number generator. + */ +#define random rand + +#endif /* stellar */ + +#ifdef luna + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the OMRON only*/ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#ifndef mc68000 +#define FAST_CONSTANT_OFFSET_MODE +#define AVOID_MEMORY_READ +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS +#endif + +#endif /* luna */ + +#if (defined(SVR4) && defined(i386)) || \ + defined(__alpha__) || defined(__alpha) || \ + defined(__i386__) || defined(__i386) || \ + defined(__UNIXOS2__) || \ + defined(__OS2ELF__) || \ + defined(__QNX__) || \ + defined(__s390x__) || defined(__s390__) + +#ifndef IMAGE_BYTE_ORDER +#define IMAGE_BYTE_ORDER LSBFirst +#endif + +#ifndef BITMAP_BIT_ORDER +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif +#endif + +#ifndef BITMAP_SCANLINE_UNIT +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif +#endif + +#ifndef GLYPHPADBYTES +#define GLYPHPADBYTES 4 +#endif + +#define GETLEFTBITS_ALIGNMENT 1 +#define AVOID_MEMORY_READ +#ifdef XSVGA +#define AVOID_GLYPHBLT +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_MEMCPY +#define NO_ONE_RECT +#endif + +#endif /* SVR4 / BSD / i386 */ + +#if defined (linux) && defined (__mc68000__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define FAST_UNALIGNED_READS +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#endif /* linux/m68k */ + +#ifdef sgi + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif + +/* linux on the Compaq Itsy */ +#if defined(linux) && defined(__arm__) +#define IMAGE_BYTE_ORDER LSBFirst +#define BITMAP_BIT_ORDER LSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#endif + +/* size of buffer to use with GetImage, measured in bytes. There's obviously + * a trade-off between the amount of stack (or whatever ALLOCATE_LOCAL gives + * you) used and the number of times the ddx routine has to be called. + */ +#ifndef IMAGE_BUFSIZE +#define IMAGE_BUFSIZE (64*1024) +#endif + +/* pad scanline to a longword */ +#ifndef BITMAP_SCANLINE_UNIT +#define BITMAP_SCANLINE_UNIT 32 +#endif + +#ifndef BITMAP_SCANLINE_PAD +#define BITMAP_SCANLINE_PAD 32 +#define LOG2_BITMAP_PAD 5 +#define LOG2_BYTES_PER_SCANLINE_PAD 2 +#endif + +/* + * This returns the number of padding units, for depth d and width w. + * For bitmaps this can be calculated with the macros above. + * Other depths require either grovelling over the formats field of the + * screenInfo or hardwired constants. + */ + +typedef struct _PaddingInfo { + int padRoundUp; /* pixels per pad unit - 1 */ + int padPixelsLog2; /* log 2 (pixels per pad unit) */ + int padBytesLog2; /* log 2 (bytes per pad unit) */ + int notPower2; /* bitsPerPixel not a power of 2 */ + int bytesPerPixel; /* only set when notPower2 is TRUE */ + int bitsPerPixel; /* bits per pixel */ +} PaddingInfo; +extern PaddingInfo PixmapWidthPaddingInfo[]; + +/* The only portable way to get the bpp from the depth is to look it up */ +#define BitsPerPixel(d) (PixmapWidthPaddingInfo[d].bitsPerPixel) + +#define PixmapWidthInPadUnits(w, d) \ + (PixmapWidthPaddingInfo[d].notPower2 ? \ + (((int)(w) * PixmapWidthPaddingInfo[d].bytesPerPixel + \ + PixmapWidthPaddingInfo[d].bytesPerPixel) >> \ + PixmapWidthPaddingInfo[d].padBytesLog2) : \ + ((int)((w) + PixmapWidthPaddingInfo[d].padRoundUp) >> \ + PixmapWidthPaddingInfo[d].padPixelsLog2)) + +/* + * Return the number of bytes to which a scanline of the given + * depth and width will be padded. + */ +#define PixmapBytePad(w, d) \ + (PixmapWidthInPadUnits(w, d) << PixmapWidthPaddingInfo[d].padBytesLog2) + +#define BitmapBytePad(w) \ + (((int)((w) + BITMAP_SCANLINE_PAD - 1) >> LOG2_BITMAP_PAD) << LOG2_BYTES_PER_SCANLINE_PAD) + +#define PixmapWidthInPadUnitsProto(w, d) PixmapWidthInPadUnits(w, d) +#define PixmapBytePadProto(w, d) PixmapBytePad(w, d) +#define BitmapBytePadProto(w) BitmapBytePad(w) + +#endif /* SERVERMD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/set.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/set.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/set.h (revision 51223) @@ -0,0 +1,150 @@ +/* $Xorg: set.h,v 1.4 2001/02/09 02:05:27 xorgcvs Exp $ */ + +/* + +Copyright 1995, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86$ */ + +/* + A Set Abstract Data Type (ADT) for the RECORD Extension + David P. Wiggins + 7/25/95 + + The RECORD extension server code needs to maintain sets of numbers + that designate protocol message types. In most cases the interval of + numbers starts at 0 and does not exceed 255, but in a few cases (minor + opcodes of extension requests) the maximum is 65535. This disparity + suggests that a single set representation may not be suitable for all + sets, especially given that server memory is precious. We introduce a + set ADT to hide implementation differences so that multiple + simultaneous set representations can exist. A single interface is + presented to the set user regardless of the implementation in use for + a particular set. + + The existing RECORD SI appears to require only four set operations: + create (given a list of members), destroy, see if a particular number + is a member of the set, and iterate over the members of a set. Though + many more set operations are imaginable, to keep the code space down, + we won't provide any more operations than are needed. + + The following types and functions/macros define the ADT. +*/ + +/* an interval of set members */ +typedef struct { + CARD16 first; + CARD16 last; +} RecordSetInterval; + +typedef struct _RecordSetRec *RecordSetPtr; /* primary set type */ + +typedef void *RecordSetIteratePtr; + +/* table of function pointers for set operations. + set users should never declare a variable of this type. +*/ +typedef struct { + void (*DestroySet)( + RecordSetPtr pSet +); + unsigned long (*IsMemberOfSet)( + RecordSetPtr pSet, + int possible_member +); + RecordSetIteratePtr (*IterateSet)( + RecordSetPtr pSet, + RecordSetIteratePtr pIter, + RecordSetInterval *interval +); +} RecordSetOperations; + +/* "base class" for sets. + set users should never declare a variable of this type. + */ +typedef struct _RecordSetRec { + RecordSetOperations *ops; +} RecordSetRec; + +RecordSetPtr RecordCreateSet( + RecordSetInterval *intervals, + int nintervals, + void *pMem, + int memsize +); +/* + RecordCreateSet creates and returns a new set having members specified + by intervals and nintervals. nintervals is the number of RecordSetInterval + structures pointed to by intervals. The elements belonging to the new + set are determined as follows. For each RecordSetInterval structure, the + elements between first and last inclusive are members of the new set. + If a RecordSetInterval's first field is greater than its last field, the + results are undefined. It is valid to create an empty set (nintervals == + 0). If RecordCreateSet returns NULL, the set could not be created due + to resource constraints. +*/ + +int RecordSetMemoryRequirements( + RecordSetInterval * /*pIntervals*/, + int /*nintervals*/, + int * /*alignment*/ +); + +#define RecordDestroySet(_pSet) \ + /* void */ (*_pSet->ops->DestroySet)(/* RecordSetPtr */ _pSet) +/* + RecordDestroySet frees all resources used by _pSet. _pSet should not be + used after it is destroyed. +*/ + +#define RecordIsMemberOfSet(_pSet, _m) \ + /* unsigned long */ (*_pSet->ops->IsMemberOfSet)(/* RecordSetPtr */ _pSet, \ + /* int */ _m) +/* + RecordIsMemberOfSet returns a non-zero value if _m is a member of + _pSet, else it returns zero. +*/ + +#define RecordIterateSet(_pSet, _pIter, _interval) \ + /* RecordSetIteratePtr */ (*_pSet->ops->IterateSet)(/* RecordSetPtr */ _pSet,\ + /* RecordSetIteratePtr */ _pIter, /* RecordSetInterval */ _interval) +/* + RecordIterateSet returns successive intervals of members of _pSet. If + _pIter is NULL, the first interval of set members is copied into _interval. + The return value should be passed as _pIter in the next call to + RecordIterateSet to obtain the next interval. When the return value is + NULL, there were no more intervals in the set, and nothing is copied into + the _interval parameter. Intervals appear in increasing numerical order + with no overlap between intervals. As such, the list of intervals produced + by RecordIterateSet may not match the list of intervals that were passed + in RecordCreateSet. Typical usage: + + pIter = NULL; + while (pIter = RecordIterateSet(pSet, pIter, &interval)) + { + process interval; + } +*/ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setbmap.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/setbmap.h,v 3.1 1996/04/15 11:19:03 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETBMAP_H +#define SETBMAP_H 1 + +int +SProcXSetDeviceButtonMapping( + ClientPtr /* client */ + ); + +int +ProcXSetDeviceButtonMapping( + ClientPtr /* client */ + ); + +void +SRepXSetDeviceButtonMapping( + ClientPtr /* client */, + int /* size */, + xSetDeviceButtonMappingReply * /* rep */ + ); + +#endif /* SETBMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setdval.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setdval.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setdval.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/setdval.h,v 3.1 1996/04/15 11:19:04 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETDVAL_H +#define SETDVAL_H 1 + +int +SProcXSetDeviceValuators( + ClientPtr /* client */ + ); + +int +ProcXSetDeviceValuators( + ClientPtr /* client */ + ); + +void +SRepXSetDeviceValuators( + ClientPtr /* client */, + int /* size */, + xSetDeviceValuatorsReply * /* rep */ + ); + +#endif /* SETDVAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setfocus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setfocus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setfocus.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/setfocus.h,v 3.1 1996/04/15 11:19:05 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETFOCUS_H +#define SETFOCUS_H 1 + +int +SProcXSetDeviceFocus( + ClientPtr /* client */ + ); + +int +ProcXSetDeviceFocus( + ClientPtr /* client */ + ); + +#endif /* SETFOCUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmmap.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/setmmap.h,v 3.1 1996/04/15 11:19:06 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETMMAP_H +#define SETMMAP_H 1 + +int +SProcXSetDeviceModifierMapping( + ClientPtr /* client */ + ); + +int +ProcXSetDeviceModifierMapping( + ClientPtr /* client */ + ); + +void +SRepXSetDeviceModifierMapping( + ClientPtr /* client */, + int /* size */, + xSetDeviceModifierMappingReply * /* rep */ + ); + +#endif /* SETMMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/setmode.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/Xi/setmode.h,v 3.1 1996/04/15 11:19:07 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETMODE_H +#define SETMODE_H 1 + +int +SProcXSetDeviceMode( + ClientPtr /* client */ + ); + +int +ProcXSetDeviceMode( + ClientPtr /* client */ + ); + +void +SRepXSetDeviceMode( + ClientPtr /* client */, + int /* size */, + xSetDeviceModeReply * /* rep */ + ); + +#endif /* SETMODE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadow.h (revision 51223) @@ -0,0 +1,179 @@ +/* + * $XFree86: xc/programs/Xserver/miext/shadow/shadow.h,v 1.6tsi Exp $ + * + * Copyright © 2000 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SHADOW_H_ +#define _SHADOW_H_ + +#include "scrnintstr.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +typedef struct _shadowBuf *shadowBufPtr; + +typedef void (*ShadowUpdateProc) (ScreenPtr pScreen, + shadowBufPtr pBuf); + +#define SHADOW_WINDOW_RELOCATE 1 +#define SHADOW_WINDOW_READ 2 +#define SHADOW_WINDOW_WRITE 4 + +typedef void *(*ShadowWindowProc) (ScreenPtr pScreen, + CARD32 row, + CARD32 offset, + int mode, + CARD32 *size, + void *closure); + +typedef struct _shadowBuf { + shadowBufPtr pNext; + ShadowUpdateProc update; + ShadowWindowProc window; + RegionRec damage; + PixmapPtr pPixmap; + void *closure; + int randr; +} shadowBufRec; + +/* Match defines from randr extension */ +#define SHADOW_ROTATE_0 1 +#define SHADOW_ROTATE_90 2 +#define SHADOW_ROTATE_180 4 +#define SHADOW_ROTATE_270 8 +#define SHADOW_ROTATE_ALL (SHADOW_ROTATE_0|SHADOW_ROTATE_90|\ + SHADOW_ROTATE_180|SHADOW_ROTATE_270) +#define SHADOW_REFLECT_X 16 +#define SHADOW_REFLECT_Y 32 +#define SHADOW_REFLECT_ALL (SHADOW_REFLECT_X|SHADOW_REFLECT_Y) + +typedef struct _shadowScrPriv { + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + CloseScreenProcPtr CloseScreen; + CreateGCProcPtr CreateGC; + GetImageProcPtr GetImage; +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif + shadowBufPtr pBuf; + BSFuncRec BackingStoreFuncs; +} shadowScrPrivRec, *shadowScrPrivPtr; + +extern int shadowScrPrivateIndex; + +#define shadowGetScrPriv(pScr) ((shadowScrPrivPtr) (pScr)->devPrivates[shadowScrPrivateIndex].ptr) +#define shadowScrPriv(pScr) shadowScrPrivPtr pScrPriv = shadowGetScrPriv(pScr) + +Bool +shadowSetup (ScreenPtr pScreen); + +Bool +shadowAdd (ScreenPtr pScreen, + PixmapPtr pPixmap, + ShadowUpdateProc update, + ShadowWindowProc window, + int randr, + void *closure); + +void +shadowRemove (ScreenPtr pScreen, PixmapPtr pPixmap); + +shadowBufPtr +shadowFindBuf (WindowPtr pWindow); + +Bool +shadowInit (ScreenPtr pScreen, ShadowUpdateProc update, ShadowWindowProc window); + +void * +shadowAlloc (int width, int height, int bpp); + +void +shadowUpdatePacked (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdatePlanar4 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdatePlanar4x8 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotatePacked (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +typedef void (* shadowUpdateProc)(ScreenPtr, shadowBufPtr); + +shadowUpdateProc shadowUpdatePackedWeak(void); +shadowUpdateProc shadowUpdatePlanar4Weak(void); +shadowUpdateProc shadowUpdatePlanar4x8Weak(void); +shadowUpdateProc shadowUpdateRotatePackedWeak(void); + +void +shadowWrapGC (GCPtr pGC); + +void +shadowUnwrapGC (GCPtr pGC); + +#endif /* _SHADOW_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadowfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadowfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shadowfb.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/shadowfb/shadowfb.h,v 1.3 2002/10/16 22:12:54 alanh Exp $ */ + +#ifndef _SHADOWFB_H +#define _SHADOWFB_H + +#include "xf86str.h" + +/* + * User defined callback function. Passed a pointer to the ScrnInfo struct, + * the number of dirty rectangles, and a pointer to the first dirty rectangle + * in the array. + */ +typedef void (*RefreshAreaFuncPtr)(ScrnInfoPtr, int, BoxPtr); + +/* + * ShadowFBInit initializes the shadowfb subsystem. refreshArea is a pointer + * to a user supplied callback function. This function will be called after + * any operation that modifies the framebuffer. The newly dirtied rectangles + * are passed to the callback. + * + * Returns FALSE in the event of an error. + */ +Bool +ShadowFBInit ( + ScreenPtr pScreen, + RefreshAreaFuncPtr refreshArea +); + +/* + * ShadowFBInit2 is a more featureful refinement of the original shadowfb. + * ShadowFBInit2 allows you to specify two callbacks, one to be called + * immediately before an operation that modifies the framebuffer, and another + * to be called immediately after. + * + * Returns FALSE in the event of an error + */ +Bool +ShadowFBInit2 ( + ScreenPtr pScreen, + RefreshAreaFuncPtr preRefreshArea, + RefreshAreaFuncPtr postRefreshArea +); + +#endif /* _SHADOWFB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shrotpack.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shrotpack.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/shrotpack.h (revision 51223) @@ -0,0 +1,186 @@ +/* + * $XFree86: xc/programs/Xserver/miext/shadow/shrotpack.h,v 1.3 2001/05/29 04:54:13 keithp Exp $ + * + * Copyright © 2000 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Thanks to Daniel Chemko for making the 90 and 180 + * orientations work. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include "scrnintstr.h" +#include "windowstr.h" +#include +#include "dixfontstr.h" +#include +#include "mi.h" +#include "regionstr.h" +#include "globals.h" +#include "gcstruct.h" +#include "shadow.h" +#include "fb.h" + +#define DANDEBUG 0 + +#if ROTATE == 270 + +#define SCRLEFT(x,y,w,h) (pScreen->height - ((y) + (h))) +#define SCRY(x,y,w,h) (x) +#define SCRWIDTH(x,y,w,h) (h) +#define FIRSTSHA(x,y,w,h) (((y) + (h) - 1) * shaStride + (x)) +#define STEPDOWN(x,y,w,h) ((w)--) +#define NEXTY(x,y,w,h) ((x)++) +#define SHASTEPX(stride) -(stride) +#define SHASTEPY(stride) (1) + +#elif ROTATE == 90 + +#define SCRLEFT(x,y,w,h) (y) +#define SCRY(x,y,w,h) (pScreen->width - ((x) + (w)) - 1) +#define SCRWIDTH(x,y,w,h) (h) +#define FIRSTSHA(x,y,w,h) ((y) * shaStride + (x + w - 1)) +#define STEPDOWN(x,y,w,h) ((w)--) +#define NEXTY(x,y,w,h) ((void)(x)) +#define SHASTEPX(stride) (stride) +#define SHASTEPY(stride) (-1) + +#elif ROTATE == 180 + +#define SCRLEFT(x,y,w,h) (pScreen->width - ((x) + (w))) +#define SCRY(x,y,w,h) (pScreen->height - ((y) + (h)) - 1) +#define SCRWIDTH(x,y,w,h) (w) +#define FIRSTSHA(x,y,w,h) ((y + h - 1) * shaStride + (x + w - 1)) +#define STEPDOWN(x,y,w,h) ((h)--) +#define NEXTY(x,y,w,h) ((void)(y)) +#define SHASTEPX(stride) (-1) +#define SHASTEPY(stride) -(stride) + +#else + +#define SCRLEFT(x,y,w,h) (x) +#define SCRY(x,y,w,h) (y) +#define SCRWIDTH(x,y,w,h) (w) +#define FIRSTSHA(x,y,w,h) ((y) * shaStride + (x)) +#define STEPDOWN(x,y,w,h) ((h)--) +#define NEXTY(x,y,w,h) ((y)++) +#define SHASTEPX(stride) (1) +#define SHASTEPY(stride) (stride) + +#endif + +void +FUNC (ScreenPtr pScreen, + shadowBufPtr pBuf) +{ + RegionPtr damage = &pBuf->damage; + PixmapPtr pShadow = pBuf->pPixmap; + int nbox = REGION_NUM_RECTS (damage); + BoxPtr pbox = REGION_RECTS (damage); + FbBits *shaBits; + Data *shaBase, *shaLine, *sha; + FbStride shaStride; + int scrBase, scrLine, scr; + int shaBpp; + int shaXoff, shaYoff; /* XXX assumed to be zero */ + int x, y, w, h, width; + int i; + Data *winBase = NULL, *win; + CARD32 winSize; + + fbGetDrawable (&pShadow->drawable, shaBits, shaStride, shaBpp, shaXoff, shaYoff); + shaBase = (Data *) shaBits; + shaStride = shaStride * sizeof (FbBits) / sizeof (Data); +#if (DANDEBUG > 1) + ErrorF ("-> Entering Shadow Update:\r\n |- Origins: pShadow=%x, pScreen=%x, damage=%x\r\n |- Metrics: shaStride=%d, shaBase=%x, shaBpp=%d\r\n | \n", pShadow, pScreen, damage, shaStride, shaBase, shaBpp); +#endif + while (nbox--) + { + x = pbox->x1; + y = pbox->y1; + w = (pbox->x2 - pbox->x1); + h = pbox->y2 - pbox->y1; + +#if (DANDEBUG > 2) + ErrorF (" |-> Redrawing box - Metrics: X=%d, Y=%d, Width=%d, Height=%d\n", x, y, w, h); +#endif + scrLine = SCRLEFT(x,y,w,h); + shaLine = shaBase + FIRSTSHA(x,y,w,h); + + while (STEPDOWN(x,y,w,h)) + { + winSize = 0; + scrBase = 0; + width = SCRWIDTH(x,y,w,h); + scr = scrLine; + sha = shaLine; +#if (DANDEBUG > 3) + ErrorF (" | |-> StepDown - Metrics: width=%d, scr=%x, sha=%x\n", width, scr, sha); +#endif + while (width) + { + /* how much remains in this window */ + i = scrBase + winSize - scr; + if (i <= 0 || scr < scrBase) + { + winBase = (Data *) (*pBuf->window) (pScreen, + SCRY(x,y,w,h), + scr * sizeof (Data), + SHADOW_WINDOW_WRITE, + &winSize, + pBuf->closure); + if(!winBase) + return; + scrBase = scr; + winSize /= sizeof (Data); + i = winSize; +#if(DANDEBUG > 4) + ErrorF (" | | |-> Starting New Line - Metrics: winBase=%x, scrBase=%x, winSize=%d\r\n | | | Xstride=%d, Ystride=%d, w=%d h=%d\n", winBase, scrBase, winSize, SHASTEPX(shaStride), SHASTEPY(shaStride), w, h); +#endif + } + win = winBase + (scr - scrBase); + if (i > width) + i = width; + width -= i; + scr += i; +#if(DANDEBUG > 5) + ErrorF (" | | |-> Writing Line - Metrics: win=%x, sha=%x\n", win, sha); +#endif + while (i--) + { +#if(DANDEBUG > 6) + ErrorF (" | | |-> Writing Pixel - Metrics: win=%x, sha=%d, remaining=%d\n", win, sha, i); +#endif + *win++ = *sha; + sha += SHASTEPX(shaStride); + } /* i */ + } /* width */ + shaLine += SHASTEPY(shaStride); + NEXTY(x,y,w,h); + } /* STEPDOWN */ + pbox++; + } /* nbox */ +} Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/singlesize.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/singlesize.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/singlesize.h (revision 51223) @@ -0,0 +1,87 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _singlesize_h_ +#define _singlesize_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "indirect_size.h" + +extern GLint __glReadPixels_size(GLenum format, GLenum type, + GLint width, GLint height); +extern GLint __glGetTexEnvfv_size(GLenum pname); +extern GLint __glGetTexEnviv_size(GLenum pname); +extern GLint __glGetTexGenfv_size(GLenum pname); +extern GLint __glGetTexGendv_size(GLenum pname); +extern GLint __glGetTexGeniv_size(GLenum pname); +extern GLint __glGetTexParameterfv_size(GLenum pname); +extern GLint __glGetTexParameteriv_size(GLenum pname); +extern GLint __glGetLightfv_size(GLenum pname); +extern GLint __glGetLightiv_size(GLenum pname); +extern GLint __glGetMap_size(GLenum pname, GLenum query); +extern GLint __glGetMapdv_size(GLenum target, GLenum query); +extern GLint __glGetMapfv_size(GLenum target, GLenum query); +extern GLint __glGetMapiv_size(GLenum target, GLenum query); +extern GLint __glGetMaterialfv_size(GLenum pname); +extern GLint __glGetMaterialiv_size(GLenum pname); +extern GLint __glGetPixelMap_size(GLenum map); +extern GLint __glGetPixelMapfv_size(GLenum map); +extern GLint __glGetPixelMapuiv_size(GLenum map); +extern GLint __glGetPixelMapusv_size(GLenum map); +extern GLint __glGet_size(GLenum sq); +extern GLint __glGetDoublev_size(GLenum sq); +extern GLint __glGetFloatv_size(GLenum sq); +extern GLint __glGetIntegerv_size(GLenum sq); +extern GLint __glGetBooleanv_size(GLenum sq); +extern GLint __glGetTexLevelParameterfv_size(GLenum pname); +extern GLint __glGetTexLevelParameteriv_size(GLenum pname); +extern GLint __glGetTexImage_size(GLenum target, GLint level, GLenum format, + GLenum type, GLint width, GLint height, + GLint depth); +extern GLint __glGetColorTableParameterfv_size(GLenum pname); +extern GLint __glGetColorTableParameteriv_size(GLenum pname); +extern GLint __glGetConvolutionParameterfv_size(GLenum pname); +extern GLint __glGetConvolutionParameteriv_size(GLenum pname); +extern GLint __glGetHistogramParameterfv_size(GLenum pname); +extern GLint __glGetHistogramParameteriv_size(GLenum pname); +extern GLint __glGetMinmaxParameterfv_size(GLenum pname); +extern GLint __glGetMinmaxParameteriv_size(GLenum pname); + +#endif /* _singlesize_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/site.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/site.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/site.h (revision 51223) @@ -0,0 +1,139 @@ +/* $Xorg: site.h,v 1.6 2001/02/09 02:05:16 xorgcvs Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/include/site.h,v 1.8 2001/12/19 21:37:35 dawes Exp $ */ + +#ifndef SITE_H +#define SITE_H +/* + * The vendor string identifies the vendor responsible for the + * server executable. + */ +#ifndef VENDOR_STRING +#define VENDOR_STRING "The X.Org Group" +#endif + +/* + * The vendor release number identifies, for the purpose of submitting + * traceable bug reports, the release number of software produced + * by the vendor. + */ +#ifndef VENDOR_RELEASE +#define VENDOR_RELEASE 6600 +#endif + +/* + * The following constants are provided solely as a last line of defense. The + * normal build ALWAYS overrides them using a special rule given in + * server/dix/Imakefile. If you want to change either of these constants, + * you should set the DefaultFontPath or DefaultRGBDatabase configuration + * parameters. + * DO NOT CHANGE THESE VALUES OR THE DIX IMAKEFILE! + */ +#ifndef COMPILEDDEFAULTFONTPATH +#define COMPILEDDEFAULTFONTPATH "/usr/lib/X11/fonts/misc/" +#endif +#ifndef RGB_DB +#define RGB_DB "/usr/lib/X11/rgb" +#endif + +/* + * The following constants contain default values for all of the variables + * that can be initialized on the server command line or in the environment. + */ +#define COMPILEDDEFAULTFONT "fixed" +#define COMPILEDCURSORFONT "cursor" +#ifndef COMPILEDDISPLAYCLASS +#define COMPILEDDISPLAYCLASS "MIT-unspecified" +#endif +#define DEFAULT_TIMEOUT 60 /* seconds */ +#define DEFAULT_KEYBOARD_CLICK 0 +#define DEFAULT_BELL 50 +#define DEFAULT_BELL_PITCH 400 +#define DEFAULT_BELL_DURATION 100 +#ifdef XKB +#define DEFAULT_AUTOREPEAT TRUE +#else +#define DEFAULT_AUTOREPEAT FALSE +#endif +#define DEFAULT_AUTOREPEATS {\ + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\ + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + +#define DEFAULT_LEDS 0x0 /* all off */ +#define DEFAULT_LEDS_MASK 0xffffffff /* 32 */ +#define DEFAULT_INT_RESOLUTION 1000 +#define DEFAULT_INT_MIN_VALUE 0 +#define DEFAULT_INT_MAX_VALUE 100 +#define DEFAULT_INT_DISPLAYED 0 + +#define DEFAULT_PTR_NUMERATOR 2 +#define DEFAULT_PTR_DENOMINATOR 1 +#define DEFAULT_PTR_THRESHOLD 4 + +#define DEFAULT_SCREEN_SAVER_TIME (10 * (60 * 1000)) +#define DEFAULT_SCREEN_SAVER_INTERVAL (10 * (60 * 1000)) +#define DEFAULT_SCREEN_SAVER_BLANKING PreferBlanking +#define DEFAULT_SCREEN_SAVER_EXPOSURES AllowExposures +#ifndef NOLOGOHACK +#define DEFAULT_LOGO_SCREEN_SAVER 1 +#endif +#ifndef DEFAULT_ACCESS_CONTROL +#define DEFAULT_ACCESS_CONTROL TRUE +#endif + +/* Default logging parameters. */ +#ifndef DEFAULT_LOG_VERBOSITY +#define DEFAULT_LOG_VERBOSITY 0 +#endif +#ifndef DEFAULT_LOG_FILE_VERBOSITY +#define DEFAULT_LOG_FILE_VERBOSITY 3 +#endif + +#endif /* SITE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sleepuntil.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sleepuntil.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sleepuntil.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86: xc/programs/Xserver/Xext/sleepuntil.h,v 1.2 2003/11/17 22:20:27 dawes Exp $ */ +/* + * Copyright (C) 2001 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _SLEEPUNTIL_H_ +#define _SLEEPUNTIL_H_ 1 + +#include "dix.h" + +extern int ClientSleepUntil( + ClientPtr client, + TimeStamp *revive, + void (*notifyFunc)( + ClientPtr /* client */, + pointer /* closure */ + ), + pointer Closure +); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/spooler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/spooler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/spooler.h (revision 51223) @@ -0,0 +1,76 @@ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SPOOLER_H +#define SPOOLER_H 1 + +/* $Xorg: spooler.h,v 1.1 2003/09/14 1:19:56 gisburn Exp $ */ +/* +Copyright (c) 2003-2004 Roland Mainz + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +/* + * Define platform-specific default spooler type + */ +#if defined(sun) +#define XPDEFAULTSPOOLERNAMELIST "solaris" +#elif defined(AIXV4) +#define XPDEFAULTSPOOLERNAMELIST "aix4" +#elif defined(hpux) +#define XPDEFAULTSPOOLERNAMELIST "hpux" +#elif defined(__osf__) +#define XPDEFAULTSPOOLERNAMELIST "osf" +#elif defined(__uxp__) +#define XPDEFAULTSPOOLERNAMELIST "uxp" +#elif defined(CSRG_BASED) || defined(linux) +/* ToDo: This should be "cups:bsd" in the future, but for now + * the search order first-bsd-then-cups is better for backwards + * compatibility. + */ +#define XPDEFAULTSPOOLERNAMELIST "bsd:cups" +#else +#define XPDEFAULTSPOOLERNAMELIST "other" +#endif + +typedef struct +{ + const char *name; + const char *list_queues_command; + const char *spool_command; +} XpSpoolerType, *XpSpoolerTypePtr; + +/* prototypes */ +extern XpSpoolerTypePtr XpSpoolerNameToXpSpoolerType(char *name); +extern void XpSetSpoolerTypeNameList(char *namelist); +extern char *XpGetSpoolerTypeNameList(void); + +/* global vars */ +extern XpSpoolerTypePtr spooler_type; +extern XpSpoolerType xpstm[]; + +#endif /* !SPOOLER_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stip68kgnu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stip68kgnu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stip68kgnu.h (revision 51223) @@ -0,0 +1,123 @@ +/* + * $Xorg: stip68kgnu.h,v 1.4 2001/02/09 02:04:39 xorgcvs Exp $ + * +Copyright 1990, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ +/* $XFree86: xc/programs/Xserver/cfb/stip68kgnu.h,v 3.3 2001/01/17 22:36:37 dawes Exp $ */ + +/* + * Stipple stack macro for 68k GCC + */ + +#define STIPPLE(addr,stipple,value,width,count,shift) \ + __asm volatile ( \ + "lea 5f,%/a1\n\ + moveq #28,%/d2\n\ + addl %2,%/d2\n\ + moveq #28,%/d3\n\ + subql #4,%2\n\ + negl %2\n\ +1:\n\ + movel %0,%/a0\n\ + addl %6,%0\n\ + movel %3@+,%/d1\n\ + jeq 3f\n\ + movel %/d1,%/d0\n\ + lsrl %/d2,%/d0\n\ + lsll #5,%/d0\n\ + lsll %2,%/d1\n\ + jmp %/a1@(%/d0:l)\n\ +2:\n\ + addl #4,%/a0\n\ + movel %/d1,%/d0\n\ + lsrl %/d3,%/d0\n\ + lsll #5,%/d0\n\ + lsll #4,%/d1\n\ + jmp %/a1@(%/d0:l)\n\ +5:\n\ + jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x20\n\ + moveb %5,%/a0@(3)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x40\n\ + moveb %5,%/a0@(2)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x60\n\ + movew %5,%/a0@(2)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x80\n\ + moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xa0\n\ + moveb %5,%/a0@(3) ; moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xc0\n\ + movew %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xe0\n\ + movew %5,%/a0@(2) ; moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x100\n\ + moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x120\n\ + moveb %5,%/a0@(3) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x140\n\ + moveb %5,%/a0@(2) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x160\n\ + movew %5,%/a0@(2) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x180\n\ + movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1a0\n\ + moveb %5,%/a0@(3) ; movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1c0\n\ + moveb %5,%/a0@(2) ; movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1e0\n\ + movel %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; \n\ +3: dbra %1,1b ; \n\ +4:\n"\ + : "=a" (addr), /* %0 */ \ + "=d" (count), /* %1 */ \ + "=d" (shift), /* %2 */ \ + "=a" (stipple) /* %3 */ \ + : "0" (addr), /* %4 */ \ + "d" (value), /* %5 */ \ + "a" (width), /* %6 */ \ + "1" (count-1), /* %7 */ \ + "2" (shift), /* %8 */ \ + "3" (stipple) /* %9 */ \ + : /* ctemp */ "d0", \ + /* c */ "d1", \ + /* lshift */ "d2", \ + /* rshift */ "d3", \ + /* atemp */ "a0", \ + /* case */ "a1") Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stubs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stubs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/stubs.h (revision 51223) @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/stubs.h,v 1.2 2000/10/23 21:16:52 tsi Exp $ + */ + +#ifndef _xf86cfg_stubs_h +#define _xf86cfg_stubs_h + +#include + +int ErrorF(const char*, ...); +int VErrorF(const char*, va_list); +#if defined(USE_MODULES) +extern int xf86Verbose; +#endif + +#endif /* _xf86cfg_stubs_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sun_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sun_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sun_kbd.h (revision 51223) @@ -0,0 +1,72 @@ +/* Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, and/or sell copies of the Software, and to permit persons + * to whom the Software is furnished to do so, provided that the above + * copyright notice(s) and this permission notice appear in all copies of + * the Software and that both the above copyright notice(s) and this + * permission notice appear in supporting documentation. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT + * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL + * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING + * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Except as contained in this notice, the name of a copyright holder + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * of the copyright holder. + */ + +#ifndef _XORG_SUN_KBD_H_ +#define _XORG_SUN_KBD_H_ + +/* + * Keyboard common implementation routines shared by "keyboard" driver + * in sun_io.c and "kbd" driver in sun_kbd.c + */ + +typedef struct { + int kbdFD; + const char * devName; + int ktype; /* Keyboard type from KIOCTYPE */ + Bool kbdActive; /* Have we set kbd modes for X? */ + int otranslation; /* Original translation mode */ + int odirect; /* Original "direct" mode setting */ + unsigned char oleds; /* Original LED state */ + const char * strmod; /* Streams module pushed on kbd device */ + const char * audioDevName; /* Audio device path to use for bell + or NULL to use keyboard beeper */ + enum {AB_INITIALIZING, AB_NORMAL} audioState; + const unsigned char *keyMap; +} sunKbdPrivRec, *sunKbdPrivPtr; + +/* sun_kbd.c */ +extern int sunKbdOpen (const char *devName, pointer options); +extern int sunKbdInit (sunKbdPrivPtr priv, int kbdFD, + const char *devName, pointer options); +extern int sunKbdOn (sunKbdPrivPtr priv); +extern int sunKbdOff (sunKbdPrivPtr priv); + +extern void sunKbdSoundBell (sunKbdPrivPtr priv, + int loudness, int pitch, int duration); + +extern void sunKbdSetLeds (sunKbdPrivPtr priv, int leds); +extern int sunKbdGetLeds (sunKbdPrivPtr priv); +extern void sunKbdSetRepeat (sunKbdPrivPtr priv, char rad); + +/* sun_kbdEv.c */ +#include +extern void sunPostKbdEvent (int ktype, Firm_event *event); + +extern const unsigned char *sunGetKbdMapping(int ktype); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swaprep.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swaprep.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swaprep.h (revision 51223) @@ -0,0 +1,322 @@ +/* $XFree86: xc/programs/Xserver/include/swaprep.h,v 3.0 1996/04/15 11:34:34 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef SWAPREP_H +#define SWAPREP_H 1 + +extern void Swap32Write( + ClientPtr /* pClient */, + int /* size */, + CARD32 * /* pbuf */); + +extern void CopySwap32Write( + ClientPtr /* pClient */, + int /* size */, + CARD32 * /* pbuf */); + +extern void CopySwap16Write( + ClientPtr /* pClient */, + int /* size */, + short * /* pbuf */); + +extern void SGenericReply( + ClientPtr /* pClient */, + int /* size */, + xGenericReply * /* pRep */); + +extern void SGetWindowAttributesReply( + ClientPtr /* pClient */, + int /* size */, + xGetWindowAttributesReply * /* pRep */); + +extern void SGetGeometryReply( + ClientPtr /* pClient */, + int /* size */, + xGetGeometryReply * /* pRep */); + +extern void SQueryTreeReply( + ClientPtr /* pClient */, + int /* size */, + xQueryTreeReply * /* pRep */); + +extern void SInternAtomReply( + ClientPtr /* pClient */, + int /* size */, + xInternAtomReply * /* pRep */); + +extern void SGetAtomNameReply( + ClientPtr /* pClient */, + int /* size */, + xGetAtomNameReply * /* pRep */); + +extern void SGetPropertyReply( + ClientPtr /* pClient */, + int /* size */, + xGetPropertyReply * /* pRep */); + +extern void SListPropertiesReply( + ClientPtr /* pClient */, + int /* size */, + xListPropertiesReply * /* pRep */); + +extern void SGetSelectionOwnerReply( + ClientPtr /* pClient */, + int /* size */, + xGetSelectionOwnerReply * /* pRep */); + +extern void SQueryPointerReply( + ClientPtr /* pClient */, + int /* size */, + xQueryPointerReply * /* pRep */); + +extern void SwapTimecoord( + xTimecoord * /* pCoord */); + +extern void SwapTimeCoordWrite( + ClientPtr /* pClient */, + int /* size */, + xTimecoord * /* pRep */); + +extern void SGetMotionEventsReply( + ClientPtr /* pClient */, + int /* size */, + xGetMotionEventsReply * /* pRep */); + +extern void STranslateCoordsReply( + ClientPtr /* pClient */, + int /* size */, + xTranslateCoordsReply * /* pRep */); + +extern void SGetInputFocusReply( + ClientPtr /* pClient */, + int /* size */, + xGetInputFocusReply * /* pRep */); + +extern void SQueryKeymapReply( + ClientPtr /* pClient */, + int /* size */, + xQueryKeymapReply * /* pRep */); + +#ifdef LBX +extern void SwapCharInfo( + xCharInfo * /* pInfo */); +#endif + +#ifdef LBX +extern void SwapFont( + xQueryFontReply * /* pr */, + Bool /* hasGlyphs */); +#endif + +extern void SQueryFontReply( + ClientPtr /* pClient */, + int /* size */, + xQueryFontReply * /* pRep */); + +extern void SQueryTextExtentsReply( + ClientPtr /* pClient */, + int /* size */, + xQueryTextExtentsReply * /* pRep */); + +extern void SListFontsReply( + ClientPtr /* pClient */, + int /* size */, + xListFontsReply * /* pRep */); + +extern void SListFontsWithInfoReply( + ClientPtr /* pClient */, + int /* size */, + xListFontsWithInfoReply * /* pRep */); + +extern void SGetFontPathReply( + ClientPtr /* pClient */, + int /* size */, + xGetFontPathReply * /* pRep */); + +extern void SGetImageReply( + ClientPtr /* pClient */, + int /* size */, + xGetImageReply * /* pRep */); + +extern void SListInstalledColormapsReply( + ClientPtr /* pClient */, + int /* size */, + xListInstalledColormapsReply * /* pRep */); + +extern void SAllocColorReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorReply * /* pRep */); + +extern void SAllocNamedColorReply( + ClientPtr /* pClient */, + int /* size */, + xAllocNamedColorReply * /* pRep */); + +extern void SAllocColorCellsReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorCellsReply * /* pRep */); + +extern void SAllocColorPlanesReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorPlanesReply * /* pRep */); + +extern void SwapRGB( + xrgb * /* prgb */); + +extern void SQColorsExtend( + ClientPtr /* pClient */, + int /* size */, + xrgb * /* prgb */); + +extern void SQueryColorsReply( + ClientPtr /* pClient */, + int /* size */, + xQueryColorsReply * /* pRep */); + +extern void SLookupColorReply( + ClientPtr /* pClient */, + int /* size */, + xLookupColorReply * /* pRep */); + +extern void SQueryBestSizeReply( + ClientPtr /* pClient */, + int /* size */, + xQueryBestSizeReply * /* pRep */); + +extern void SListExtensionsReply( + ClientPtr /* pClient */, + int /* size */, + xListExtensionsReply * /* pRep */); + +extern void SGetKeyboardMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetKeyboardMappingReply * /* pRep */); + +extern void SGetPointerMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetPointerMappingReply * /* pRep */); + +extern void SGetModifierMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetModifierMappingReply * /* pRep */); + +extern void SGetKeyboardControlReply( + ClientPtr /* pClient */, + int /* size */, + xGetKeyboardControlReply * /* pRep */); + +extern void SGetPointerControlReply( + ClientPtr /* pClient */, + int /* size */, + xGetPointerControlReply * /* pRep */); + +extern void SGetScreenSaverReply( + ClientPtr /* pClient */, + int /* size */, + xGetScreenSaverReply * /* pRep */); + +extern void SLHostsExtend( + ClientPtr /* pClient */, + int /* size */, + char * /* buf */); + +extern void SListHostsReply( + ClientPtr /* pClient */, + int /* size */, + xListHostsReply * /* pRep */); + +extern void SErrorEvent( + xError * /* from */, + xError * /* to */); + +extern void SwapConnSetupInfo( + char * /* pInfo */, + char * /* pInfoTBase */); + +extern void WriteSConnectionInfo( + ClientPtr /* pClient */, + unsigned long /* size */, + char * /* pInfo */); + +extern void SwapConnSetup( + xConnSetup * /* pConnSetup */, + xConnSetup * /* pConnSetupT */); + +extern void SwapWinRoot( + xWindowRoot * /* pRoot */, + xWindowRoot * /* pRootT */); + +extern void SwapVisual( + xVisualType * /* pVis */, + xVisualType * /* pVisT */); + +extern void SwapConnSetupPrefix( + xConnSetupPrefix * /* pcspFrom */, + xConnSetupPrefix * /* pcspTo */); + +extern void WriteSConnSetupPrefix( + ClientPtr /* pClient */, + xConnSetupPrefix * /* pcsp */); + +#undef SWAPREP_PROC +#define SWAPREP_PROC(func) void func(xEvent * /* from */, xEvent * /* to */) + +SWAPREP_PROC(SCirculateEvent); +SWAPREP_PROC(SClientMessageEvent); +SWAPREP_PROC(SColormapEvent); +SWAPREP_PROC(SConfigureNotifyEvent); +SWAPREP_PROC(SConfigureRequestEvent); +SWAPREP_PROC(SCreateNotifyEvent); +SWAPREP_PROC(SDestroyNotifyEvent); +SWAPREP_PROC(SEnterLeaveEvent); +SWAPREP_PROC(SExposeEvent); +SWAPREP_PROC(SFocusEvent); +SWAPREP_PROC(SGraphicsExposureEvent); +SWAPREP_PROC(SGravityEvent); +SWAPREP_PROC(SKeyButtonPtrEvent); +SWAPREP_PROC(SKeymapNotifyEvent); +SWAPREP_PROC(SMapNotifyEvent); +SWAPREP_PROC(SMapRequestEvent); +SWAPREP_PROC(SMappingEvent); +SWAPREP_PROC(SNoExposureEvent); +SWAPREP_PROC(SPropertyEvent); +SWAPREP_PROC(SReparentEvent); +SWAPREP_PROC(SResizeRequestEvent); +SWAPREP_PROC(SSelectionClearEvent); +SWAPREP_PROC(SSelectionNotifyEvent); +SWAPREP_PROC(SSelectionRequestEvent); +SWAPREP_PROC(SUnmapNotifyEvent); +SWAPREP_PROC(SVisibilityEvent); + +#undef SWAPREP_PROC + +#endif /* SWAPREP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swapreq.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swapreq.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/swapreq.h (revision 51223) @@ -0,0 +1,120 @@ +/* $XFree86: xc/programs/Xserver/include/swapreq.h,v 1.3 2003/04/27 21:31:05 herrb Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef SWAPREQ_H +#define SWAPREQ_H 1 + +/* The first two are in misc.h */ +#if 0 +extern void SwapLongs ( + CARD32 * /* list */, + unsigned long /* count */); + +extern void SwapShorts ( + short * /* list */, + unsigned long /* count */); +#endif + +extern void SwapColorItem( + xColorItem * /* pItem */); + +extern void SwapConnClientPrefix( + xConnClientPrefix * /* pCCP */); + +#undef SWAPREQ_PROC + +#define SWAPREQ_PROC(func) int func(ClientPtr /* client */) + +SWAPREQ_PROC(SProcAllocColor); +SWAPREQ_PROC(SProcAllocColorCells); +SWAPREQ_PROC(SProcAllocColorPlanes); +SWAPREQ_PROC(SProcAllocNamedColor); +SWAPREQ_PROC(SProcChangeActivePointerGrab); +SWAPREQ_PROC(SProcChangeGC); +SWAPREQ_PROC(SProcChangeHosts); +SWAPREQ_PROC(SProcChangeKeyboardControl); +SWAPREQ_PROC(SProcChangeKeyboardMapping); +SWAPREQ_PROC(SProcChangePointerControl); +SWAPREQ_PROC(SProcChangeProperty); +SWAPREQ_PROC(SProcChangeWindowAttributes); +SWAPREQ_PROC(SProcClearToBackground); +SWAPREQ_PROC(SProcConfigureWindow); +SWAPREQ_PROC(SProcConvertSelection); +SWAPREQ_PROC(SProcCopyArea); +SWAPREQ_PROC(SProcCopyColormapAndFree); +SWAPREQ_PROC(SProcCopyGC); +SWAPREQ_PROC(SProcCopyPlane); +SWAPREQ_PROC(SProcCreateColormap); +SWAPREQ_PROC(SProcCreateCursor); +SWAPREQ_PROC(SProcCreateGC); +SWAPREQ_PROC(SProcCreateGlyphCursor); +SWAPREQ_PROC(SProcCreatePixmap); +SWAPREQ_PROC(SProcCreateWindow); +SWAPREQ_PROC(SProcDeleteProperty); +SWAPREQ_PROC(SProcFillPoly); +SWAPREQ_PROC(SProcFreeColors); +SWAPREQ_PROC(SProcGetImage); +SWAPREQ_PROC(SProcGetMotionEvents); +SWAPREQ_PROC(SProcGetProperty); +SWAPREQ_PROC(SProcGrabButton); +SWAPREQ_PROC(SProcGrabKey); +SWAPREQ_PROC(SProcGrabKeyboard); +SWAPREQ_PROC(SProcGrabPointer); +SWAPREQ_PROC(SProcImageText); +SWAPREQ_PROC(SProcInternAtom); +SWAPREQ_PROC(SProcListFonts); +SWAPREQ_PROC(SProcListFontsWithInfo); +SWAPREQ_PROC(SProcLookupColor); +SWAPREQ_PROC(SProcNoOperation); +SWAPREQ_PROC(SProcOpenFont); +SWAPREQ_PROC(SProcPoly); +SWAPREQ_PROC(SProcPolyText); +SWAPREQ_PROC(SProcPutImage); +SWAPREQ_PROC(SProcQueryBestSize); +SWAPREQ_PROC(SProcQueryColors); +SWAPREQ_PROC(SProcQueryExtension); +SWAPREQ_PROC(SProcRecolorCursor); +SWAPREQ_PROC(SProcReparentWindow); +SWAPREQ_PROC(SProcResourceReq); +SWAPREQ_PROC(SProcRotateProperties); +SWAPREQ_PROC(SProcSendEvent); +SWAPREQ_PROC(SProcSetClipRectangles); +SWAPREQ_PROC(SProcSetDashes); +SWAPREQ_PROC(SProcSetFontPath); +SWAPREQ_PROC(SProcSetInputFocus); +SWAPREQ_PROC(SProcSetScreenSaver); +SWAPREQ_PROC(SProcSetSelectionOwner); +SWAPREQ_PROC(SProcSimpleReq); +SWAPREQ_PROC(SProcStoreColors); +SWAPREQ_PROC(SProcStoreNamedColor); +SWAPREQ_PROC(SProcTranslateCoords); +SWAPREQ_PROC(SProcUngrabButton); +SWAPREQ_PROC(SProcUngrabKey); +SWAPREQ_PROC(SProcWarpPointer); + +#undef SWAPREQ_PROC + +#endif /* SWAPREQ_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sym.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sym.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/sym.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/sym.h,v 1.6 2000/10/24 00:06:55 anderson Exp $ */ + +/* + * + * Copyright 1995,96 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _SYM_H +#define _SYM_H + +/* + * This structure is used to pass in symbol information that is being + * added to the symbol table. + */ + +typedef void (*funcptr) (void); + +typedef struct { + char *symName; + funcptr offset; +} LOOKUP; + +#define SYMFUNC( func ) { #func, (funcptr)&func }, +#define SYMFUNCALIAS( name, func ) { name, (funcptr)&func }, +#define SYMVAR( var ) { #var, (funcptr)&var }, +#define SYMVARALIAS( name, var ) { name, (funcptr)&var }, + +#endif /* _SYM_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda8425.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda8425.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda8425.h (revision 51223) @@ -0,0 +1,53 @@ +#ifndef __TDA8425_H__ +#define __TDA8425_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int mux; + int stereo; + int v_left; + int v_right; + int bass; + int treble; + int src_sel; + Bool mute; + } TDA8425Rec, *TDA8425Ptr; + +#define TDA8425_ADDR_1 0x82 + +/* the third parameter is meant to force detection of tda8425. + This is because tda8425 is write-only and complete implementation + of I2C protocol is not always available. Besides address there is no good + way to autodetect it so we have to _know_ it is there anyway */ + +TDA8425Ptr Detect_tda8425(I2CBusPtr b, I2CSlaveAddr addr,Bool force); +Bool tda8425_init(TDA8425Ptr t); +void tda8425_setaudio(TDA8425Ptr t); +void tda8425_mute(TDA8425Ptr t, Bool mute); + +#define TDA8425SymbolsList \ + "Detect_tda8425", \ + "tda8425_init", \ + "tda8425_setaudio", \ + "tda8425_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda8425 ((TDA8425Ptr (*)(I2CBusPtr, I2CSlaveAddr,Bool))LoaderSymbol("Detect_tda8425")) +#define xf86_tda8425_init ((Bool (*)(TDA8425Ptr))LoaderSymbol("tda8425_init")) +#define xf86_tda8425_setaudio ((void (*)(TDA8425Ptr))LoaderSymbol("tda8425_setaudio")) +#define xf86_tda8425_mute ((void (*)(TDA8425Ptr, Bool))LoaderSymbol("tda8425_mute")) + +#else + +#define xf86_Detect_tda8425 Detect_tda8425 +#define xf86_tda8425_init tda8425_init +#define xf86_tda8425_setaudio tda8425_setaudio +#define xf86_tda8425_mute tda8425_mute + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9850.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9850.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9850.h (revision 51223) @@ -0,0 +1,52 @@ +#ifndef __TDA9850_H__ +#define __TDA9850_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int mux; + int stereo; + int sap; + Bool mute; + Bool sap_mute; + } TDA9850Rec, *TDA9850Ptr; + +#define TDA9850_ADDR_1 0xB4 + +TDA9850Ptr Detect_tda9850(I2CBusPtr b, I2CSlaveAddr addr); +Bool tda9850_init(TDA9850Ptr t); +void tda9850_setaudio(TDA9850Ptr t); +void tda9850_mute(TDA9850Ptr t, Bool mute); +void tda9850_sap_mute(TDA9850Ptr t, Bool sap_mute); +CARD16 tda9850_getstatus(TDA9850Ptr t); + +#define TDA9850SymbolsList \ + "Detect_tda9850", \ + "tda9850_init", \ + "tda9850_setaudio", \ + "tda9850_mute", \ + "tda9850_sap_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda9850 ((TDA9850Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_tda9850")) +#define xf86_tda9850_init ((Bool (*)(TDA9850Ptr))LoaderSymbol("tda9850_init")) +#define xf86_tda9850_setaudio ((void (*)(TDA9850Ptr))LoaderSymbol("tda9850_setaudio")) +#define xf86_tda9850_mute ((void (*)(TDA9850Ptr, Bool))LoaderSymbol("tda9850_mute")) +#define xf86_tda9850_sap_mute ((void (*)(TDA9850Ptr, Bool))LoaderSymbol("tda9850_sap_mute")) +#define xf86_tda9850_getstatus ((CARD16 (*)(TDA9850Ptr))LoaderSymbol("tda9850_getstatus")) + +#else + +#define xf86_Detect_tda9850 Detect_tda9850 +#define xf86_tda9850_init tda9850_init +#define xf86_tda9850_setaudio tda9850_setaudio +#define xf86_tda9850_mute tda9850_mute +#define xf86_tda9850_sap_mute tda9850_sap_mute +#define xf86_tda9850_getstatus tda9850_getstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9885.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9885.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/tda9885.h (revision 51223) @@ -0,0 +1,72 @@ +#ifndef __TDA9885_H__ +#define __TDA9885_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + /* write-only parameters */ + /* B DATA */ + CARD8 sound_trap; + CARD8 auto_mute_fm; + CARD8 carrier_mode; + CARD8 modulation; + CARD8 forced_mute_audio; + CARD8 port1; + CARD8 port2; + /* C DATA */ + CARD8 top_adjustment; + CARD8 deemphasis; + CARD8 audio_gain; + /* E DATA */ + CARD8 standard_sound_carrier; + CARD8 standard_video_if; + CARD8 minimum_gain; + CARD8 gating; + CARD8 vif_agc; + /* read-only values */ + + CARD8 after_reset; + CARD8 afc_status; + CARD8 vif_level; + CARD8 afc_win; + CARD8 fm_carrier; + } TDA9885Rec, *TDA9885Ptr; + +#define TDA9885_ADDR_1 0x86 +#define TDA9885_ADDR_2 0x84 +#define TDA9885_ADDR_3 0x96 +#define TDA9885_ADDR_4 0x94 + +TDA9885Ptr Detect_tda9885(I2CBusPtr b, I2CSlaveAddr addr); +Bool tda9885_init(TDA9885Ptr t); +void tda9885_setparameters(TDA9885Ptr t); +void tda9885_getstatus(TDA9885Ptr t); +void tda9885_dumpstatus(TDA9885Ptr t); + +#define TDA9885SymbolsList \ + "Detect_tda9885", \ + "tda9885_init", \ + "tda9885_setaudio", \ + "tda9885_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda9885 ((TDA9885Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_tda9885")) +#define xf86_tda9885_init ((Bool (*)(TDA9885Ptr))LoaderSymbol("tda9885_init")) +#define xf86_tda9885_setparameters ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_setparameters")) +#define xf86_tda9885_getstatus ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_getstatus")) +#define xf86_tda9885_dumpstatus ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_dumpstatus")) + +#else + +#define xf86_Detect_tda9885 Detect_tda9885 +#define xf86_tda9885_init tda9885_init +#define xf86_tda9885_setparameters tda9885_setparameters +#define xf86_tda9885_getstatus tda9885_getstatus +#define xf86_tda9885_dumpstatus tda9885_dumpstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/types.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/types.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/types.h (revision 51223) @@ -0,0 +1,106 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#ifndef NO_SYS_HEADERS +#include +#endif + +/* + * The following kludge is an attempt to work around typedef conflicts with + * . + */ +#define u8 x86emuu8 +#define u16 x86emuu16 +#define u32 x86emuu32 +#define u64 x86emuu64 +#define s8 x86emus8 +#define s16 x86emus16 +#define s32 x86emus32 +#define s64 x86emus64 +#define uint x86emuuint +#define sint x86emusint + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#undef __HAS_LONG_LONG__ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +/* Taken from Xmd.h */ +#undef NUM32 +#if defined (_LP64) || \ + defined(__alpha) || defined(__alpha__) || \ + defined(__ia64__) || defined(ia64) || \ + defined(__sparc64__) || \ + defined(__s390x__) || \ + (defined(__hppa__) && defined(__LP64)) || \ + defined(__amd64__) || defined(amd64) || \ + (defined(__sgi) && (_MIPS_SZLONG == 64)) +#define NUM32 int +#else +#define NUM32 long +#endif + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned NUM32 u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef NUM32 s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +typedef unsigned int uint; +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#undef NUM32 + +#endif /* __X86EMU_TYPES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/uda1380.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/uda1380.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/uda1380.h (revision 51223) @@ -0,0 +1,93 @@ +/************************************************************************************* + * $Id: uda1380.h,v 1.3 2005/09/24 21:56:00 bogdand Exp $ + * + * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this + * software and associated documentation files (the "Software"), to deal in the Software + * without restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the author shall not be used in advertising or + * otherwise to promote the sale, use or other dealings in this Software without prior written + * authorization from the author. + * + * $Log: uda1380.h,v $ + * Revision 1.3 2005/09/24 21:56:00 bogdand + * Changed the license to a X/MIT one + * + * Revision 1.2 2005/07/01 22:43:11 daniels + * Change all misc.h and os.h references to . + * + * + ************************************************************************************/ + +#ifndef __UDA1380_H__ +#define __UDA1380_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + CARD16 analog_mixer_settings; /* register 0x03 */ + + } UDA1380Rec, *UDA1380Ptr; + +#define UDA1380_ADDR_1 0x30 +#define UDA1380_ADDR_2 0x34 + +UDA1380Ptr Detect_uda1380(I2CBusPtr b, I2CSlaveAddr addr); +Bool uda1380_init(UDA1380Ptr t); +void uda1380_shutdown(UDA1380Ptr t); +void uda1380_setvolume(UDA1380Ptr t, INT32); +void uda1380_mute(UDA1380Ptr t, Bool); +void uda1380_setparameters(UDA1380Ptr t); +void uda1380_getstatus(UDA1380Ptr t); +void uda1380_dumpstatus(UDA1380Ptr t); + +#define UDA1380SymbolsList \ + "Detect_uda1380", \ + "uda1380_init", \ + "uda1380_shutdown", \ + "uda1380_setvolume", \ + "uda1380_mute", \ + "uda1380_setparameters", \ + "uda1380_getstatus", \ + "uda1380_dumpstatus" + +#ifdef XFree86LOADER + +#define xf86_Detect_uda1380 ((UDA1380Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_uda1380")) +#define xf86_uda1380_init ((Bool (*)(UDA1380Ptr))LoaderSymbol("uda1380_init")) +#define xf86_uda1380_shutdown ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_shutdown")) +#define xf86_uda1380_setvolume ((void (*)(UDA1380Ptr, CARD16))LoaderSymbol("uda1380_setvolume")) +#define xf86_uda1380_mute ((void (*)(UDA1380Ptr, Bool))LoaderSymbol("uda1380_mute")) +#define xf86_uda1380_setparameters ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_setparameters")) +#define xf86_uda1380_getstatus ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_getstatus")) +#define xf86_uda1380_dumpstatus ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_dumpstatus")) + +#else + +#define xf86_Detect_uda1380 Detect_uda1380 +#define xf86_uda1380_init uda1380_init +#define xf86_uda1380_shutdown uda1380_shutdown +#define xf86_uda1380_setvolume uda1380_setvolume +#define xf86_uda1380_mute uda1380_mute +#define xf86_uda1380_setparameters uda1380_setparameters +#define xf86_uda1380_getstatus uda1380_getstatus +#define xf86_uda1380_dumpstatus uda1380_dumpstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdev.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/ungrdev.h,v 3.1 1996/04/15 11:19:08 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEV_H +#define UNGRDEV_H 1 + +int +SProcXUngrabDevice( + ClientPtr /* client */ + ); + +int +ProcXUngrabDevice( + ClientPtr /* client */ + ); + +#endif /* UNGRDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevb.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/ungrdevb.h,v 3.1 1996/04/15 11:19:10 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEVB_H +#define UNGRDEVB_H 1 + +int +SProcXUngrabDeviceButton( + ClientPtr /* client */ + ); + +int +ProcXUngrabDeviceButton( + ClientPtr /* client */ + ); + +#endif /* UNGRDEVB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevk.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevk.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/ungrdevk.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/Xi/ungrdevk.h,v 3.1 1996/04/15 11:19:12 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEVK_H +#define UNGRDEVK_H 1 + +int +SProcXUngrabDeviceKey( + ClientPtr /* client */ + ); + +int +ProcXUngrabDeviceKey( + ClientPtr /* client */ + ); + +#endif /* UNGRDEVK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/unpack.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/unpack.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/unpack.h (revision 51223) @@ -0,0 +1,234 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/unpack.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef __GLX_unpack_h__ +#define __GLX_unpack_h__ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#define __GLX_PAD(s) (((s)+3) & (GLuint)~3) + +/* +** Fetch the context-id out of a SingleReq request pointed to by pc. +*/ +#define __GLX_GET_SINGLE_CONTEXT_TAG(pc) (((xGLXSingleReq*)pc)->contextTag) +#define __GLX_GET_VENDPRIV_CONTEXT_TAG(pc) (((xGLXVendorPrivateReq*)pc)->contextTag) + +/* +** Fetch a double from potentially unaligned memory. +*/ +#ifdef __GLX_ALIGN64 +#define __GLX_MEM_COPY(dst,src,n) memcpy(dst,src,n) +#define __GLX_GET_DOUBLE(dst,src) __GLX_MEM_COPY(&dst,src,8) +#else +#define __GLX_GET_DOUBLE(dst,src) (dst) = *((GLdouble*)(src)) +#endif + +extern void __glXMemInit(void); + +extern xGLXSingleReply __glXReply; + +#define __GLX_BEGIN_REPLY(size) \ + __glXReply.length = __GLX_PAD(size) >> 2; \ + __glXReply.type = X_Reply; \ + __glXReply.sequenceNumber = client->sequence; + +#define __GLX_SEND_HEADER() \ + WriteToClient( client, sz_xGLXSingleReply, (char *)&__glXReply); + +#define __GLX_PUT_RETVAL(a) \ + __glXReply.retval = (a); + +#define __GLX_PUT_SIZE(a) \ + __glXReply.size = (a); + +#define __GLX_PUT_RENDERMODE(m) \ + __glXReply.pad3 = (m) + +/* +** Get a buffer to hold returned data, with the given alignment. If we have +** to realloc, allocate size+align, in case the pointer has to be bumped for +** alignment. The answerBuffer should already be aligned. +** +** NOTE: the cast (long)res below assumes a long is large enough to hold a +** pointer. +*/ +#define __GLX_GET_ANSWER_BUFFER(res,cl,size,align) \ + if ((size) > sizeof(answerBuffer)) { \ + int bump; \ + if ((cl)->returnBufSize < (size)+(align)) { \ + (cl)->returnBuf = (GLbyte*)Xrealloc((cl)->returnBuf, \ + (size)+(align)); \ + if (!(cl)->returnBuf) { \ + return BadAlloc; \ + } \ + (cl)->returnBufSize = (size)+(align); \ + } \ + res = (char*)cl->returnBuf; \ + bump = (long)(res) % (align); \ + if (bump) res += (align) - (bump); \ + } else { \ + res = (char *)answerBuffer; \ + } + +#define __GLX_PUT_BYTE() \ + *(GLbyte *)&__glXReply.pad3 = *(GLbyte *)answer + +#define __GLX_PUT_SHORT() \ + *(GLshort *)&__glXReply.pad3 = *(GLshort *)answer + +#define __GLX_PUT_INT() \ + *(GLint *)&__glXReply.pad3 = *(GLint *)answer + +#define __GLX_PUT_FLOAT() \ + *(GLfloat *)&__glXReply.pad3 = *(GLfloat *)answer + +#define __GLX_PUT_DOUBLE() \ + *(GLdouble *)&__glXReply.pad3 = *(GLdouble *)answer + +#define __GLX_SEND_BYTE_ARRAY(len) \ + WriteToClient(client, __GLX_PAD((len)*__GLX_SIZE_INT8), (char *)answer) + +#define __GLX_SEND_SHORT_ARRAY(len) \ + WriteToClient(client, __GLX_PAD((len)*__GLX_SIZE_INT16), (char *)answer) + +#define __GLX_SEND_INT_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_INT32, (char *)answer) + +#define __GLX_SEND_FLOAT_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_FLOAT32, (char *)answer) + +#define __GLX_SEND_DOUBLE_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_FLOAT64, (char *)answer) + + +#define __GLX_SEND_VOID_ARRAY(len) __GLX_SEND_BYTE_ARRAY(len) +#define __GLX_SEND_UBYTE_ARRAY(len) __GLX_SEND_BYTE_ARRAY(len) +#define __GLX_SEND_USHORT_ARRAY(len) __GLX_SEND_SHORT_ARRAY(len) +#define __GLX_SEND_UINT_ARRAY(len) __GLX_SEND_INT_ARRAY(len) + +/* +** PERFORMANCE NOTE: +** Machine dependent optimizations abound here; these swapping macros can +** conceivably be replaced with routines that do the job faster. +*/ +#define __GLX_DECLARE_SWAP_VARIABLES \ + GLbyte sw; \ + GLbyte *swapPC; \ + GLbyte *swapEnd + + +#define __GLX_SWAP_INT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = sw; + +#define __GLX_SWAP_SHORT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = sw; + +#define __GLX_SWAP_DOUBLE(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[7]; \ + ((GLbyte *)(pc))[7] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[6]; \ + ((GLbyte *)(pc))[6] = sw; \ + sw = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = ((GLbyte *)(pc))[5]; \ + ((GLbyte *)(pc))[5] = sw; \ + sw = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = ((GLbyte *)(pc))[4]; \ + ((GLbyte *)(pc))[4] = sw; + +#define __GLX_SWAP_FLOAT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = sw; + +#define __GLX_SWAP_INT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_INT32;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_INT(swapPC); \ + swapPC += __GLX_SIZE_INT32; \ + } + +#define __GLX_SWAP_SHORT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_INT16;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_SHORT(swapPC); \ + swapPC += __GLX_SIZE_INT16; \ + } + +#define __GLX_SWAP_DOUBLE_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_FLOAT64;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_DOUBLE(swapPC); \ + swapPC += __GLX_SIZE_FLOAT64; \ + } + +#define __GLX_SWAP_FLOAT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_FLOAT32;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_FLOAT(swapPC); \ + swapPC += __GLX_SIZE_FLOAT32; \ + } + +#define __GLX_SWAP_REPLY_HEADER() \ + __GLX_SWAP_SHORT(&__glXReply.sequenceNumber); \ + __GLX_SWAP_INT(&__glXReply.length); + +#define __GLX_SWAP_REPLY_RETVAL() \ + __GLX_SWAP_INT(&__glXReply.retval) + +#define __GLX_SWAP_REPLY_SIZE() \ + __GLX_SWAP_INT(&__glXReply.size) + +#endif /* !__GLX_unpack_h__ */ + + + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-common.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-common.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-common.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to common USB support. \see usb-common.c \see usb-mouse.c + * \see usb-keyboard.c \see usb-other.c */ + +#ifndef _USB_COMMON_H_ +#define _USB_COMMON_H_ +typedef enum { + usbMouse, + usbKeyboard, + usbOther +} usbType; + +extern pointer usbCreatePrivate(DeviceIntPtr pDevice); +extern void usbDestroyPrivate(pointer priv); +extern void usbRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + int minButton, + DMXBlockType block); +extern void usbInit(DevicePtr pDev, usbType type); +extern void usbOff(DevicePtr pDev); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-keyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-keyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-keyboard.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB keyboard driver. \see usb-keyboard.c \see usb-common.c */ + +#ifndef _USB_KEYBOARD_H_ +#define _USB_KEYBOARD_H_ +extern void kbdUSBInit(DevicePtr pDev); +extern void kbdUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int kbdUSBOn(DevicePtr pDev); +extern void kbdUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void kbdUSBCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-mouse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-mouse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-mouse.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB mouse driver. \see usb-mouse.c \see usb-common.c */ + +#ifndef _USB_MOU_H_ +#define _USB_MOU_H_ +extern void mouUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void mouUSBInit(DevicePtr pDev); +extern void mouUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int mouUSBOn(DevicePtr pDev); +extern void mouUSBCtrl(DevicePtr pDev, PtrCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-other.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-other.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-other.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB generic driver. \see usb-other.c \see usb-common.c */ + +#ifndef _USB_OTHER_H_ +#define _USB_OTHER_H_ +extern void othUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void othUSBInit(DevicePtr pDev); +extern void othUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int othUSBOn(DevicePtr pDev); +extern void othUSBCtrl(DevicePtr pDev, PtrCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-private.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-private.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb-private.h (revision 51223) @@ -0,0 +1,118 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Private header file for USB support. This file provides + * Linux-specific include files and the definition of the private + * structure. \see usb-common.c \see usb-keyboard.c \see usb-mouse.c + * \see usb-other.c */ + +#ifndef _USB_PRIVATE_H_ +#define _USB_PRIVATE_H_ + +#include "dmxinputinit.h" +#include "inputstr.h" +#include +#include +#include +#include "usb-common.h" + + /* Support for force feedback was + * introduced in Linxu 2.4.10 */ +#ifndef EV_MSC +#define EV_MSC 0x04 +#endif +#ifndef EV_FF +#define EV_FF 0x15 +#endif +#ifndef LED_SLEEP +#define LED_SLEEP 0x05 +#endif +#ifndef LED_SUSPEND +#define LED_SUSPEND 0x06 +#endif +#ifndef LED_MUTE +#define LED_MUTE 0x07 +#endif +#ifndef LED_MISC +#define LED_MISC 0x08 +#endif +#ifndef BTN_DEAD +#define BTN_DEAD 0x12f +#endif +#ifndef BTN_THUMBL +#define BTN_THUMBL 0x13d +#endif +#ifndef BTN_THUMBR +#define BTN_THUMBR 0x13e +#endif +#ifndef MSC_SERIAL +#define MSC_SERIAL 0x00 +#endif +#ifndef MSC_MAX +#define MSC_MAX 0x07 +#endif + + /* Support for older kernels. */ +#ifndef ABS_WHEEL +#define ABS_WHEEL 0x08 +#endif +#ifndef ABS_GAS +#define ABS_GAS 0x09 +#endif +#ifndef ABS_BRAKE +#define ABS_BRAKE 0x0a +#endif + +#define NUM_STATE_ENTRIES (256/32) + +/* Private area for USB devices. */ +typedef struct _myPrivate { + DeviceIntPtr pDevice; /**< Device (mouse or other) */ + int fd; /**< File descriptor */ + unsigned char mask[EV_MAX/8 + 1]; /**< Mask */ + int numRel, numAbs, numLeds; /**< Counts */ + int relmap[DMX_MAX_AXES]; /**< Relative axis map */ + int absmap[DMX_MAX_AXES]; /**< Absolute axis map */ + + CARD32 kbdState[NUM_STATE_ENTRIES]; /**< Keyboard state */ + DeviceIntPtr pKeyboard; /** Keyboard device */ + + int pitch; /**< Bell pitch */ + unsigned long duration; /**< Bell duration */ + + /* FIXME: dmxInput is never initialized */ + DMXInputInfo *dmxInput; /**< For pretty-printing */ +} myPrivate; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usb.h (revision 51223) @@ -0,0 +1,95 @@ +/* $NetBSD: usb.h,v 1.5 1999/07/02 15:46:53 simonb Exp $ */ + +/* + * Copyright (c) 1999 Lennart Augustsson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/libusb/usb.h,v 1.1.2.2 1999/12/03 10:12:43 hohndel Exp $ */ + +#define _DIAGASSERT(e) assert(e) + +typedef struct report_desc *report_desc_t; + +typedef struct hid_data *hid_data_t; + +typedef enum hid_kind { + hid_input, hid_output, hid_feature, hid_collection, hid_endcollection +}hid_kind_t; + +typedef struct hid_item { + /* Global */ + int _usage_page; + int logical_minimum; + int logical_maximum; + int physical_minimum; + int physical_maximum; + int unit_exponent; + int unit; + int report_size; + int report_ID; + int report_count; + /* Local */ + unsigned int usage; + int usage_minimum; + int usage_maximum; + int designator_index; + int designator_minimum; + int designator_maximum; + int string_index; + int string_minimum; + int string_maximum; + int set_delimiter; + /* Misc */ + int collection; + int collevel; + enum hid_kind kind; + unsigned int flags; + /* Absolute data position (bits) */ + unsigned int pos; + /* */ + struct hid_item *next; +} hid_item_t; + +#define HID_PAGE(u) ((u) >> 16) +#define HID_USAGE(u) ((u) & 0xffff) + +/* Obtaining a report descriptor, descr.c: */ +report_desc_t hid_get_report_desc __P((int file)); +void hid_dispose_report_desc __P((report_desc_t)); + +/* Parsing of a HID report descriptor, parse.c: */ +hid_data_t hid_start_parse __P((report_desc_t d, int kindset)); +void hid_end_parse __P((hid_data_t s)); +int hid_get_item __P((hid_data_t s, hid_item_t *h)); +int hid_report_size __P((report_desc_t d, enum hid_kind k, int *idp)); +int hid_locate __P((report_desc_t d, unsigned int usage, enum hid_kind k, hid_item_t *h)); + +/* Conversion to/from usage names, usage.c: */ +char *hid_usage_page __P((int i)); +char *hid_usage_in_page __P((unsigned int u)); +void hid_init __P((char *file)); + +/* Extracting/insertion of data, data.c: */ +int hid_get_data __P((void *p, hid_item_t *h)); +void hid_set_data __P((void *p, hid_item_t *h, int data)); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usbvar.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usbvar.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usbvar.h (revision 51223) @@ -0,0 +1,34 @@ +/* $NetBSD: usbvar.h,v 1.2 1999/05/11 21:15:46 augustss Exp $ */ + +/* + * Copyright (c) 1999 Lennart Augustsson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/libusb/usbvar.h,v 1.1.2.2 1999/12/03 10:12:43 hohndel Exp $ */ + +struct report_desc { + unsigned int size; + unsigned char data[1]; +}; + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_kbd.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XdotOrg$ */ +#ifndef SCO_KBD_HDR +#define SCO_KBD_HDR + +typedef struct { + int orig_kbm; + struct termio kbdtty; + keymap_t keymap, noledmap; + int xq; +} USLKbdPrivRec, *USLKbdPrivPtr; + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); +#endif /* SCO_KBD_HDR */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_xqueue.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_xqueue.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/usl_xqueue.h (revision 51223) @@ -0,0 +1,9 @@ +/* $XdotOrg$ */ + +#ifndef _XF86_USL_XQUEUE_H_ +#define _XF86_USL_XQUEUE_H_ + +extern int XqMseOnOff (InputInfoPtr pInfo, int on); +extern int XqKbdOnOff (InputInfoPtr pInfo, int on); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/validate.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/validate.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/validate.h (revision 51223) @@ -0,0 +1,42 @@ +/* $Xorg: validate.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/include/validate.h,v 1.4 2001/01/17 22:36:58 dawes Exp $ */ + +#ifndef VALIDATE_H +#define VALIDATE_H + +#include "miscstruct.h" +#include "regionstr.h" + +typedef enum { VTOther, VTStack, VTMove, VTUnmap, VTMap, VTBroken } VTKind; + +/* union _Validate is now device dependent; see mivalidate.h for an example */ +typedef union _Validate *ValidatePtr; + +#define UnmapValData ((ValidatePtr)1) + +#endif /* VALIDATE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbe.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbe.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbe.h (revision 51223) @@ -0,0 +1,332 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/vbe/vbe.h,v 1.4 2004/01/07 04:28:06 dawes Exp $ */ + +/* + * XFree86 vbe module + * Copyright 2000 Egbert Eich + * + * The mode query/save/set/restore functions from the vesa driver + * have been moved here. + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * Authors: Paulo César Pereira de Andrade + */ + +#ifndef _VBE_H +#define _VBE_H +#include "xf86int10.h" +#include "xf86DDC.h" + +typedef enum { + DDC_UNCHECKED, + DDC_NONE, + DDC_1, + DDC_2, + DDC_1_2 +} +ddc_lvl; + +typedef struct { + xf86Int10InfoPtr pInt10; + int version; + pointer memory; + int real_mode_base; + int num_pages; + Bool init_int10; + ddc_lvl ddc; + Bool ddc_blank; +} vbeInfoRec, *vbeInfoPtr; + +#define VBE_VERSION_MAJOR(x) *((CARD8*)(&x) + 1) +#define VBE_VERSION_MINOR(x) (CARD8)(x) + +vbeInfoPtr VBEInit(xf86Int10InfoPtr pInt, int entityIndex); +vbeInfoPtr VBEExtendedInit(xf86Int10InfoPtr pInt, int entityIndex, int Flags); +void vbeFree(vbeInfoPtr pVbe); +xf86MonPtr vbeDoEDID(vbeInfoPtr pVbe, pointer pDDCModule); + +#pragma pack(1) + +typedef struct vbeControllerInfoBlock { + CARD8 VbeSignature[4]; + CARD16 VbeVersion; + CARD32 OemStringPtr; + CARD8 Capabilities[4]; + CARD32 VideoModePtr; + CARD16 TotalMem; + CARD16 OemSoftwareRev; + CARD32 OemVendorNamePtr; + CARD32 OemProductNamePtr; + CARD32 OemProductRevPtr; + CARD8 Scratch[222]; + CARD8 OemData[256]; +} vbeControllerInfoRec, *vbeControllerInfoPtr; + +#if defined(__GNUC__) || defined(__USLC__) || defined(__SUNPRO_C) +#pragma pack() /* All GCC versions recognise this syntax */ +#else +#pragma pack(0) +#endif + +#ifndef __GNUC__ +#define __attribute__(a) +#endif + +typedef struct _VbeInfoBlock VbeInfoBlock; +typedef struct _VbeModeInfoBlock VbeModeInfoBlock; +typedef struct _VbeCRTCInfoBlock VbeCRTCInfoBlock; + +/* + * INT 0 + */ + +struct _VbeInfoBlock { + /* VESA 1.2 fields */ + CARD8 VESASignature[4]; /* VESA */ + CARD16 VESAVersion; /* Higher byte major, lower byte minor */ + /*CARD32*/char *OEMStringPtr; /* Pointer to OEM string */ + CARD8 Capabilities[4]; /* Capabilities of the video environment */ + + /*CARD32*/CARD16 *VideoModePtr; /* pointer to supported Super VGA modes */ + + CARD16 TotalMemory; /* Number of 64kb memory blocks on board */ + /* if not VESA 2, 236 scratch bytes follow (256 bytes total size) */ + + /* VESA 2 fields */ + CARD16 OemSoftwareRev; /* VBE implementation Software revision */ + /*CARD32*/char *OemVendorNamePtr; /* Pointer to Vendor Name String */ + /*CARD32*/char *OemProductNamePtr; /* Pointer to Product Name String */ + /*CARD32*/char *OemProductRevPtr; /* Pointer to Product Revision String */ + CARD8 Reserved[222]; /* Reserved for VBE implementation */ + CARD8 OemData[256]; /* Data Area for OEM Strings */ +} __attribute__((packed)); + +/* Return Super VGA Information */ +VbeInfoBlock *VBEGetVBEInfo(vbeInfoPtr pVbe); +void VBEFreeVBEInfo(VbeInfoBlock *block); + +/* + * INT 1 + */ + +struct _VbeModeInfoBlock { + CARD16 ModeAttributes; /* mode attributes */ + CARD8 WinAAttributes; /* window A attributes */ + CARD8 WinBAttributes; /* window B attributes */ + CARD16 WinGranularity; /* window granularity */ + CARD16 WinSize; /* window size */ + CARD16 WinASegment; /* window A start segment */ + CARD16 WinBSegment; /* window B start segment */ + CARD32 WinFuncPtr; /* real mode pointer to window function */ + CARD16 BytesPerScanline; /* bytes per scanline */ + + /* Mandatory information for VBE 1.2 and above */ + CARD16 XResolution; /* horizontal resolution in pixels or characters */ + CARD16 YResolution; /* vertical resolution in pixels or characters */ + CARD8 XCharSize; /* character cell width in pixels */ + CARD8 YCharSize; /* character cell height in pixels */ + CARD8 NumberOfPlanes; /* number of memory planes */ + CARD8 BitsPerPixel; /* bits per pixel */ + CARD8 NumberOfBanks; /* number of banks */ + CARD8 MemoryModel; /* memory model type */ + CARD8 BankSize; /* bank size in KB */ + CARD8 NumberOfImages; /* number of images */ + CARD8 Reserved; /* 1 */ /* reserved for page function */ + + /* Direct color fields (required for direct/6 and YUV/7 memory models) */ + CARD8 RedMaskSize; /* size of direct color red mask in bits */ + CARD8 RedFieldPosition; /* bit position of lsb of red mask */ + CARD8 GreenMaskSize; /* size of direct color green mask in bits */ + CARD8 GreenFieldPosition; /* bit position of lsb of green mask */ + CARD8 BlueMaskSize; /* size of direct color blue mask in bits */ + CARD8 BlueFieldPosition; /* bit position of lsb of blue mask */ + CARD8 RsvdMaskSize; /* size of direct color reserved mask in bits */ + CARD8 RsvdFieldPosition; /* bit position of lsb of reserved mask */ + CARD8 DirectColorModeInfo; /* direct color mode attributes */ + + /* Mandatory information for VBE 2.0 and above */ + CARD32 PhysBasePtr; /* physical address for flat memory frame buffer */ + CARD32 Reserved32; /* 0 */ /* Reserved - always set to 0 */ + CARD16 Reserved16; /* 0 */ /* Reserved - always set to 0 */ + + /* Mandatory information for VBE 3.0 and above */ + CARD16 LinBytesPerScanLine; /* bytes per scan line for linear modes */ + CARD8 BnkNumberOfImagePages; /* number of images for banked modes */ + CARD8 LinNumberOfImagePages; /* number of images for linear modes */ + CARD8 LinRedMaskSize; /* size of direct color red mask (linear modes) */ + CARD8 LinRedFieldPosition; /* bit position of lsb of red mask (linear modes) */ + CARD8 LinGreenMaskSize; /* size of direct color green mask (linear modes) */ + CARD8 LinGreenFieldPosition; /* bit position of lsb of green mask (linear modes) */ + CARD8 LinBlueMaskSize; /* size of direct color blue mask (linear modes) */ + CARD8 LinBlueFieldPosition; /* bit position of lsb of blue mask (linear modes) */ + CARD8 LinRsvdMaskSize; /* size of direct color reserved mask (linear modes) */ + CARD8 LinRsvdFieldPosition; /* bit position of lsb of reserved mask (linear modes) */ + CARD32 MaxPixelClock; /* maximum pixel clock (in Hz) for graphics mode */ + CARD8 Reserved2[189]; /* remainder of VbeModeInfoBlock */ +} __attribute__((packed)); + +/* Return VBE Mode Information */ +VbeModeInfoBlock *VBEGetModeInfo(vbeInfoPtr pVbe, int mode); +void VBEFreeModeInfo(VbeModeInfoBlock *block); + +/* + * INT2 + */ + +#define CRTC_DBLSCAN (1<<0) +#define CRTC_INTERLACE (1<<1) +#define CRTC_NHSYNC (1<<2) +#define CRTC_NVSYNC (1<<3) + +struct _VbeCRTCInfoBlock { + CARD16 HorizontalTotal; /* Horizontal total in pixels */ + CARD16 HorizontalSyncStart; /* Horizontal sync start in pixels */ + CARD16 HorizontalSyncEnd; /* Horizontal sync end in pixels */ + CARD16 VerticalTotal; /* Vertical total in lines */ + CARD16 VerticalSyncStart; /* Vertical sync start in lines */ + CARD16 VerticalSyncEnd; /* Vertical sync end in lines */ + CARD8 Flags; /* Flags (Interlaced, Double Scan etc) */ + CARD32 PixelClock; /* Pixel clock in units of Hz */ + CARD16 RefreshRate; /* Refresh rate in units of 0.01 Hz */ + CARD8 Reserved[40]; /* remainder of ModeInfoBlock */ +} __attribute__((packed)); +/* VbeCRTCInfoBlock is in the VESA 3.0 specs */ + +Bool VBESetVBEMode(vbeInfoPtr pVbe, int mode, VbeCRTCInfoBlock *crtc); + +/* + * INT 3 + */ + +Bool VBEGetVBEMode(vbeInfoPtr pVbe, int *mode); + +/* + * INT 4 + */ + +/* Save/Restore Super VGA video state */ +/* function values are (values stored in VESAPtr): + * 0 := query & allocate amount of memory to save state + * 1 := save state + * 2 := restore state + * + * function 0 called automatically if function 1 called without + * a previous call to function 0. + */ + +typedef enum { + MODE_QUERY, + MODE_SAVE, + MODE_RESTORE +} vbeSaveRestoreFunction; + +Bool +VBESaveRestore(vbeInfoPtr pVbe, vbeSaveRestoreFunction fuction, + pointer *memory, int *size, int *real_mode_pages); + +/* + * INT 5 + */ + +Bool +VBEBankSwitch(vbeInfoPtr pVbe, unsigned int iBank, int window); + +/* + * INT 6 + */ + +typedef enum { + SCANWID_SET, + SCANWID_GET, + SCANWID_SET_BYTES, + SCANWID_GET_MAX +} vbeScanwidthCommand; + +#define VBESetLogicalScanline(pVbe, width) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_SET, width, \ + NULL, NULL, NULL) +#define VBESetLogicalScanlineBytes(pVbe, width) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_SET_BYTES, width, \ + NULL, NULL, NULL) +#define VBEGetLogicalScanline(pVbe, pixels, bytes, max) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_GET, 0, \ + pixels, bytes, max) +#define VBEGetMaxLogicalScanline(pVbe, pixels, bytes, max) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_GET_MAX, 0, \ + pixels, bytes, max) +Bool VBESetGetLogicalScanlineLength(vbeInfoPtr pVbe, + vbeScanwidthCommand command, int width, + int *pixels, int *bytes, int *max); + +/* + * INT 7 + */ + +/* 16 bit code */ +Bool VBESetDisplayStart(vbeInfoPtr pVbe, int x, int y, Bool wait_retrace); +Bool VBEGetDisplayStart(vbeInfoPtr pVbe, int *x, int *y); + +/* + * INT 8 + */ + +/* if bits is 0, then it is a GET */ +int VBESetGetDACPaletteFormat(vbeInfoPtr pVbe, int bits); + +/* + * INT 9 + */ + +/* + * If getting a palette, the data argument is not used. It will return + * the data. + * If setting a palette, it will return the pointer received on success, + * NULL on failure. + */ +CARD32 *VBESetGetPaletteData(vbeInfoPtr pVbe, Bool set, int first, int num, + CARD32 *data, Bool secondary, Bool wait_retrace); +#define VBEFreePaletteData(data) xfree(data) + +/* + * INT A + */ + +typedef struct _VBEpmi { + int seg_tbl; + int tbl_off; + int tbl_len; +} VBEpmi; + +VBEpmi *VBEGetVBEpmi(vbeInfoPtr pVbe); +#define VESAFreeVBEpmi(pmi) xfree(pmi) + +/* high level helper functions */ + +typedef struct _vbeModeInfoRec { + int width; + int height; + int bpp; + int n; + struct _vbeModeInfoRec *next; +} vbeModeInfoRec, *vbeModeInfoPtr; + +vbeModeInfoPtr VBEBuildVbeModeList(vbeInfoPtr pVbe, + VbeInfoBlock *vbe); + +unsigned short VBECalcVbeModeIndex(vbeModeInfoPtr m, + DisplayModePtr mode, int bpp); + +typedef struct { + CARD8 *state; + CARD8 *pstate; + int statePage; + int stateSize; + int stateMode; +} vbeSaveRestoreRec, *vbeSaveRestorePtr; + +void +VBEVesaSaveRestore(vbeInfoPtr pVbe, vbeSaveRestorePtr vbe_sr, + vbeSaveRestoreFunction function); + +int VBEGetPixelClock(vbeInfoPtr pVbe, int mode, int Clock); +Bool VBEDPMSSet(vbeInfoPtr pVbe, int mode); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbeModes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbeModes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vbeModes.h (revision 51223) @@ -0,0 +1,91 @@ +/* + * Copyright © 2002 David Dawes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the author(s) shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * the author(s). + * + * Authors: David Dawes + * + * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/vbe/vbeModes.h,v 1.1 2002/08/06 13:46:28 dawes Exp $ + */ + +#ifndef _VBE_MODES_H + +/* + * This is intended to be stored in the DisplayModeRec's private area. + * It includes all the information necessary to VBE information. + */ +typedef struct _VbeModeInfoData { + int mode; + VbeModeInfoBlock *data; + VbeCRTCInfoBlock *block; +} VbeModeInfoData; + +#define V_DEPTH_1 0x001 +#define V_DEPTH_4 0x002 +#define V_DEPTH_8 0x004 +#define V_DEPTH_15 0x008 +#define V_DEPTH_16 0x010 +#define V_DEPTH_24_24 0x020 +#define V_DEPTH_24_32 0x040 +#define V_DEPTH_24 (V_DEPTH_24_24 | V_DEPTH_24_32) +#define V_DEPTH_30 0x080 +#define V_DEPTH_32 0x100 + +#define VBE_MODE_SUPPORTED(m) (((m)->ModeAttributes & 0x01) != 0) +#define VBE_MODE_COLOR(m) (((m)->ModeAttributes & 0x08) != 0) +#define VBE_MODE_GRAPHICS(m) (((m)->ModeAttributes & 0x10) != 0) +#define VBE_MODE_VGA(m) (((m)->ModeAttributes & 0x40) == 0) +#define VBE_MODE_LINEAR(m) (((m)->ModeAttributes & 0x80) != 0 && \ + ((m)->PhysBasePtr != 0)) + +#define VBE_MODE_USABLE(m, f) (VBE_MODE_SUPPORTED(m) || \ + (f & V_MODETYPE_BAD)) && \ + VBE_MODE_GRAPHICS(m) && \ + (VBE_MODE_VGA(m) || VBE_MODE_LINEAR(m)) + +#define V_MODETYPE_VBE 0x01 +#define V_MODETYPE_VGA 0x02 +#define V_MODETYPE_BAD 0x04 + +extern int VBEFindSupportedDepths(vbeInfoPtr pVbe, VbeInfoBlock *vbe, + int *flags24, int modeTypes); +extern DisplayModePtr VBEGetModePool(ScrnInfoPtr pScrn, vbeInfoPtr pVbe, + VbeInfoBlock *vbe, int modeTypes); +extern void VBESetModeNames(DisplayModePtr pMode); +extern void VBESetModeParameters(ScrnInfoPtr pScrn, vbeInfoPtr pVbe); + + +/* + * Note: These are alternatives to the standard helpers. They should + * usually just wrap the standard helpers. + */ +extern int VBEValidateModes(ScrnInfoPtr scrp, DisplayModePtr availModes, + char **modeNames, ClockRangePtr clockRanges, + int *linePitches, int minPitch, int maxPitch, + int pitchInc, int minHeight, int maxHeight, + int virtualX, int virtualY, int apertureSize, + LookupModeFlags strategy); +extern void VBEPrintModes(ScrnInfoPtr scrp); + +#endif /* VBE_MODES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vdif.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vdif.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vdif.h (revision 51223) @@ -0,0 +1,175 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/vdif.h,v 1.4tsi Exp $ */ + +#ifndef _VDIF_H +#define _VDIF_H + +#define VDIF_MONITOR_MONOCHROME 0 +#define VDIF_MONITOR_COLOR 1 +#define VDIF_VIDEO_TTL 0 +#define VDIF_VIDEO_ANALOG 1 +#define VDIF_VIDEO_ECL 2 +#define VDIF_VIDEO_DECL 3 +#define VDIF_VIDEO_OTHER 4 +#define VDIF_SYNC_SEPARATE 0 +#define VDIF_SYNC_C 1 +#define VDIF_SYNC_CP 2 +#define VDIF_SYNC_G 3 +#define VDIF_SYNC_GP 4 +#define VDIF_SYNC_OTHER 5 +#define VDIF_SCAN_NONINTERLACED 0 +#define VDIF_SCAN_INTERLACED 1 +#define VDIF_SCAN_OTHER 2 +#define VDIF_POLARITY_NEGATIVE 0 +#define VDIF_POLARITY_POSITIVE 1 + +#include + +#undef CARD32 +#define CARD32 unsigned int /* ... on all supported platforms */ + +typedef struct _VDIF { /* Monitor Description: */ + CARD8 VDIFId[4]; /* alway "VDIF" */ + CARD32 FileLength; /* lenght of the whole file */ + CARD32 Checksum; /* sum of all bytes in the file after*/ + /* this field */ + CARD16 VDIFVersion; /* structure version number */ + CARD16 VDIFRevision; /* structure revision number */ + CARD16 Date[3]; /* file date Year/Month/Day */ + CARD16 DateManufactured[3]; /* date Year/Month/Day */ + CARD32 FileRevision; /* file revision string */ + CARD32 Manufacturer; /* ASCII ID of the manufacturer */ + CARD32 ModelNumber; /* ASCII ID of the model */ + CARD32 MinVDIFIndex; /* ASCII ID of Minimum VDIF index */ + CARD32 Version; /* ASCII ID of the model version */ + CARD32 SerialNumber; /* ASCII ID of the serial number */ + CARD8 MonitorType; /* Monochrome or Color */ + CARD8 CRTSize; /* inches */ + CARD8 BorderRed; /* percent */ + CARD8 BorderGreen; /* percent */ + CARD8 BorderBlue; /* percent */ + CARD8 Reserved1; /* padding */ + CARD16 Reserved2; /* padding */ + CARD32 RedPhosphorDecay; /* microseconds */ + CARD32 GreenPhosphorDecay; /* microseconds */ + CARD32 BluePhosphorDecay; /* microseconds */ + CARD16 WhitePoint_x; /* WhitePoint in CIExyY (scale 1000) */ + CARD16 WhitePoint_y; + CARD16 WhitePoint_Y; + CARD16 RedChromaticity_x; /* Red chromaticity in x,y */ + CARD16 RedChromaticity_y; + CARD16 GreenChromaticity_x; /* Green chromaticity in x,y */ + CARD16 GreenChromaticity_y; + CARD16 BlueChromaticity_x; /* Blue chromaticity in x,y */ + CARD16 BlueChromaticity_y; + CARD16 RedGamma; /* Gamme curve exponent (scale 1000) */ + CARD16 GreenGamma; + CARD16 BlueGamma; + CARD32 NumberOperationalLimits; + CARD32 OffsetOperationalLimits; + CARD32 NumberOptions; /* optinal sections (gamma table) */ + CARD32 OffsetOptions; + CARD32 OffsetStringTable; +} xf86VdifRec, *xf86VdifPtr; + +typedef enum { /* Tags for section identification */ + VDIF_OPERATIONAL_LIMITS_TAG = 1, + VDIF_PREADJUSTED_TIMING_TAG, + VDIF_GAMMA_TABLE_TAG +} VDIFScnTag; + +typedef struct _VDIFScnHdr { /* Generic Section Header: */ + CARD32 ScnLength; /* lenght of section */ + CARD32 ScnTag; /* tag for section identification */ +} VDIFScnHdrRec, *VDIFScnHdrPtr; + +typedef struct _VDIFLimits { /* Operational Limits: */ + VDIFScnHdrRec Header; /* common section info */ + CARD16 MaxHorPixel; /* pixels */ + CARD16 MaxVerPixel; /* lines */ + CARD16 MaxHorActiveLength; /* millimeters */ + CARD16 MaxVerActiveHeight; /* millimeters */ + CARD8 VideoType; /* TTL / Analog / ECL / DECL */ + CARD8 SyncType; /* TTL / Analog / ECL / DECL */ + CARD8 SyncConfiguration; /* separate / composite / other */ + CARD8 Reserved1; /* padding */ + CARD16 Reserved2; /* padding */ + CARD16 TerminationResistance; /* */ + CARD16 WhiteLevel; /* millivolts */ + CARD16 BlackLevel; /* millivolts */ + CARD16 BlankLevel; /* millivolts */ + CARD16 SyncLevel; /* millivolts */ + CARD32 MaxPixelClock; /* kiloHertz */ + CARD32 MinHorFrequency; /* Hertz */ + CARD32 MaxHorFrequency; /* Hertz */ + CARD32 MinVerFrequency; /* milliHertz */ + CARD32 MaxVerFrequency; /* milliHertz */ + CARD16 MinHorRetrace; /* nanoseconds */ + CARD16 MinVerRetrace; /* microseconds */ + CARD32 NumberPreadjustedTimings; + CARD32 OffsetNextLimits; +} xf86VdifLimitsRec, *xf86VdifLimitsPtr; + +typedef struct _VDIFTiming { /* Preadjusted Timing: */ + VDIFScnHdrRec Header; /* common section info */ + CARD32 PreadjustedTimingName; /* SVGA/SVPMI mode number */ + CARD16 HorPixel; /* pixels */ + CARD16 VerPixel; /* lines */ + CARD16 HorAddrLength; /* millimeters */ + CARD16 VerAddrHeight; /* millimeters */ + CARD8 PixelWidthRatio; /* gives H:V */ + CARD8 PixelHeightRatio; + CARD8 Reserved1; /* padding */ + CARD8 ScanType; /* noninterlaced / interlaced / other*/ + CARD8 HorSyncPolarity; /* negative / positive */ + CARD8 VerSyncPolarity; /* negative / positive */ + CARD16 CharacterWidth; /* pixels */ + CARD32 PixelClock; /* kiloHertz */ + CARD32 HorFrequency; /* Hertz */ + CARD32 VerFrequency; /* milliHertz */ + CARD32 HorTotalTime; /* nanoseconds */ + CARD32 VerTotalTime; /* microseconds */ + CARD16 HorAddrTime; /* nanoseconds */ + CARD16 HorBlankStart; /* nanoseconds */ + CARD16 HorBlankTime; /* nanoseconds */ + CARD16 HorSyncStart; /* nanoseconds */ + CARD16 HorSyncTime; /* nanoseconds */ + CARD16 VerAddrTime; /* microseconds */ + CARD16 VerBlankStart; /* microseconds */ + CARD16 VerBlankTime; /* microseconds */ + CARD16 VerSyncStart; /* microseconds */ + CARD16 VerSyncTime; /* microseconds */ +} xf86VdifTimingRec, *xf86VdifTimingPtr; + +typedef struct _VDIFGamma { /* Gamma Table: */ + VDIFScnHdrRec Header; /* common section info */ + CARD16 GammaTableEntries; /* count of grays or RGB 3-tuples */ + CARD16 Unused1; +} xf86VdifGammaRec, *xf86VdifGammaPtr; + +/* access macros */ +#define VDIF_OPERATIONAL_LIMITS(vdif) \ +((xf86VdifLimitsPtr)((char*)(vdif) + (vdif)->OffsetOperationalLimits)) +#define VDIF_NEXT_OPERATIONAL_LIMITS(limits) limits = \ + ((xf86VdifLimitsPtr)((char*)(limits) + (limits)->OffsetNextLimits)) +#define VDIF_PREADJUSTED_TIMING(limits) \ +((xf86VdifTimingPtr)((char*)(limits) + (limits)->Header.ScnLength)) +#define VDIF_NEXT_PREADJUSTED_TIMING(timing) timing = \ + ((xf86VdifTimingPtr)((char*)(timing) + (timing)->Header.ScnLength)) +#define VDIF_OPTIONS(vdif) \ + ((VDIFScnHdrPtr)((char*)(vdif) + (vdif)->OffsetOptions)) +#define VDIF_NEXT_OPTIONS(options) options = \ + ((xf86VdifGammaPtr)((char*)(options) + (options)->Header.ScnLength)) +#define VDIF_STRING(vdif, string) \ + ((char*)((char*)vdif + vdif->OffsetStringTable + (string))) + +typedef struct _vdif { + xf86VdifPtr vdif; + xf86VdifLimitsPtr *limits; + xf86VdifTimingPtr *timings; + xf86VdifGammaPtr *gamma; + char * strings; +} xf86vdif, *xf86vdifPtr; + +#undef CARD32 + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaHW.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaHW.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaHW.h (revision 51223) @@ -0,0 +1,237 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.h,v 1.31 2002/04/04 14:05:56 eich Exp $ */ + + +/* + * Copyright (c) 1997,1998 The XFree86 Project, Inc. + * + * Loosely based on code bearing the following copyright: + * + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Author: Dirk Hohndel + */ + +#ifndef _VGAHW_H +#define _VGAHW_H + +#include +#include "misc.h" +#include "input.h" +#include "scrnintstr.h" +#include "colormapst.h" + +#include "xf86str.h" +#include "xf86Pci.h" + +#include "xf86DDC.h" + +#include "globals.h" +#define DPMS_SERVER +#include + +extern int vgaHWGetIndex(void); + +/* + * access macro + */ +#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr)) + +/* Standard VGA registers */ +#define VGA_ATTR_INDEX 0x3C0 +#define VGA_ATTR_DATA_W 0x3C0 +#define VGA_ATTR_DATA_R 0x3C1 +#define VGA_IN_STAT_0 0x3C2 /* read */ +#define VGA_MISC_OUT_W 0x3C2 /* write */ +#define VGA_ENABLE 0x3C3 +#define VGA_SEQ_INDEX 0x3C4 +#define VGA_SEQ_DATA 0x3C5 +#define VGA_DAC_MASK 0x3C6 +#define VGA_DAC_READ_ADDR 0x3C7 +#define VGA_DAC_WRITE_ADDR 0x3C8 +#define VGA_DAC_DATA 0x3C9 +#define VGA_FEATURE_R 0x3CA /* read */ +#define VGA_MISC_OUT_R 0x3CC /* read */ +#define VGA_GRAPH_INDEX 0x3CE +#define VGA_GRAPH_DATA 0x3CF + +#define VGA_IOBASE_MONO 0x3B0 +#define VGA_IOBASE_COLOR 0x3D0 + +#define VGA_CRTC_INDEX_OFFSET 0x04 +#define VGA_CRTC_DATA_OFFSET 0x05 +#define VGA_IN_STAT_1_OFFSET 0x0A /* read */ +#define VGA_FEATURE_W_OFFSET 0x0A /* write */ + +/* default number of VGA registers stored internally */ +#define VGA_NUM_CRTC 25 +#define VGA_NUM_SEQ 5 +#define VGA_NUM_GFX 9 +#define VGA_NUM_ATTR 21 + +/* Flags for vgaHWSave() and vgaHWRestore() */ +#define VGA_SR_MODE 0x01 +#define VGA_SR_FONTS 0x02 +#define VGA_SR_CMAP 0x04 +#define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP) + +/* Defaults for the VGA memory window */ +#define VGA_DEFAULT_PHYS_ADDR 0xA0000 +#define VGA_DEFAULT_MEM_SIZE (64 * 1024) + +/* + * vgaRegRec contains settings of standard VGA registers. + */ +typedef struct { + unsigned char MiscOutReg; /* */ + unsigned char *CRTC; /* Crtc Controller */ + unsigned char *Sequencer; /* Video Sequencer */ + unsigned char *Graphics; /* Video Graphics */ + unsigned char *Attribute; /* Video Atribute */ + unsigned char DAC[768]; /* Internal Colorlookuptable */ + unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */ + unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */ + unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */ + unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */ +} vgaRegRec, *vgaRegPtr; + +typedef struct _vgaHWRec *vgaHWPtr; + +typedef void (*vgaHWWriteIndexProcPtr)(vgaHWPtr hwp, CARD8 indx, CARD8 value); +typedef CARD8 (*vgaHWReadIndexProcPtr)(vgaHWPtr hwp, CARD8 indx); +typedef void (*vgaHWWriteProcPtr)(vgaHWPtr hwp, CARD8 value); +typedef CARD8 (*vgaHWReadProcPtr)(vgaHWPtr hwp); +typedef void (*vgaHWMiscProcPtr)(vgaHWPtr hwp); + + +/* + * vgaHWRec contains per-screen information required by the vgahw module. + * + * Note, the palette referred to by the paletteEnabled, enablePalette and + * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed + * via the first 17 attribute registers and not the main 8-bit palette. + */ +typedef struct _vgaHWRec { + pointer Base; /* Address of "VGA" memory */ + int MapSize; /* Size of "VGA" memory */ + unsigned long MapPhys; /* phys location of VGA mem */ + int IOBase; /* I/O Base address */ + CARD8 * MMIOBase; /* Pointer to MMIO start */ + int MMIOOffset; /* base + offset + vgareg + = mmioreg */ + pointer FontInfo1; /* save area for fonts in + plane 2 */ + pointer FontInfo2; /* save area for fonts in + plane 3 */ + pointer TextInfo; /* save area for text */ + vgaRegRec SavedReg; /* saved registers */ + vgaRegRec ModeReg; /* register settings for + current mode */ + Bool ShowOverscan; + Bool paletteEnabled; + Bool cmapSaved; + ScrnInfoPtr pScrn; + vgaHWWriteIndexProcPtr writeCrtc; + vgaHWReadIndexProcPtr readCrtc; + vgaHWWriteIndexProcPtr writeGr; + vgaHWReadIndexProcPtr readGr; + vgaHWReadProcPtr readST00; + vgaHWReadProcPtr readST01; + vgaHWReadProcPtr readFCR; + vgaHWWriteProcPtr writeFCR; + vgaHWWriteIndexProcPtr writeAttr; + vgaHWReadIndexProcPtr readAttr; + vgaHWWriteIndexProcPtr writeSeq; + vgaHWReadIndexProcPtr readSeq; + vgaHWWriteProcPtr writeMiscOut; + vgaHWReadProcPtr readMiscOut; + vgaHWMiscProcPtr enablePalette; + vgaHWMiscProcPtr disablePalette; + vgaHWWriteProcPtr writeDacMask; + vgaHWReadProcPtr readDacMask; + vgaHWWriteProcPtr writeDacWriteAddr; + vgaHWWriteProcPtr writeDacReadAddr; + vgaHWWriteProcPtr writeDacData; + vgaHWReadProcPtr readDacData; + pointer ddc; + IOADDRESS PIOOffset; /* offset + vgareg + = pioreg */ + vgaHWReadProcPtr readEnable; + vgaHWWriteProcPtr writeEnable; + PCITAG Tag; +} vgaHWRec; + +/* Some macros that VGA drivers can use in their ChipProbe() function */ +#define VGAHW_GET_IOBASE() ((inb(VGA_MISC_OUT_R) & 0x01) ? \ + VGA_IOBASE_COLOR : VGA_IOBASE_MONO) + +#define OVERSCAN 0x11 /* Index of OverScan register */ + +/* Flags that define how overscan correction should take place */ +#define KGA_FIX_OVERSCAN 1 /* overcan correction required */ +#define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */ + /* of next scanline/frame */ +#define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */ + /* to total - 1 */ +#define BIT_PLANE 3 /* Which plane we write to in mono mode */ +#define BITS_PER_GUN 6 +#define COLORMAP_SIZE 256 + +#if defined(__powerpc__) +#define DACDelay(hw) /* No legacy VGA support */ +#else +#define DACDelay(hw) \ + do { \ + (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \ + (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \ + } while (0) +#endif + +/* Function Prototypes */ + +/* vgaHW.c */ + +typedef void vgaHWProtectProc(ScrnInfoPtr, Bool); +typedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool); + +void vgaHWSetStdFuncs(vgaHWPtr hwp); +void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset); +void vgaHWProtect(ScrnInfoPtr pScrn, Bool on); +vgaHWProtectProc *vgaHWProtectWeak(void); +Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode); +void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on); +vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void); +void vgaHWSeqReset(vgaHWPtr hwp, Bool start); +void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags); +void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save, int flags); +Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode); +Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC, int numSequencer, + int numGraphics, int numAttribute); +Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src); +Bool vgaHWGetHWRec(ScrnInfoPtr scrp); +void vgaHWFreeHWRec(ScrnInfoPtr scrp); +Bool vgaHWMapMem(ScrnInfoPtr scrp); +void vgaHWUnmapMem(ScrnInfoPtr scrp); +void vgaHWGetIOBase(vgaHWPtr hwp); +void vgaHWLock(vgaHWPtr hwp); +void vgaHWUnlock(vgaHWPtr hwp); +void vgaHWEnable(vgaHWPtr hwp); +void vgaHWDisable(vgaHWPtr hwp); +void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags); +Bool vgaHWHandleColormaps(ScreenPtr pScreen); +void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed); +CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits, + unsigned int Flags); +CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits, + unsigned int Flags); +Bool vgaHWAllocDefaultRegs(vgaRegPtr regp); + +DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void); +SaveScreenProcPtr vgaHWSaveScreenWeak(void); + +#endif /* _VGAHW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaReg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaReg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaReg.h (revision 51223) @@ -0,0 +1,140 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/vgaReg.h,v 1.3 1999/06/06 08:49:07 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ + +/* $XConsortium: vgaReg.h /main/4 1996/02/21 17:59:02 kaleb $ */ + +#define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value ) +#define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) +#define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) +/* GJA -- deleted RTIO and ATRIO case here, so that a PCIO #define became + * superfluous. + */ +#define SET_INDEXED_REGISTER(RegGroup, Index, Value) \ + (SET_BYTE_REGISTER(RegGroup, Index), \ + SET_BYTE_REGISTER((RegGroup) + 1, Value)) + +/* There is a jumper on the ega to change this to 0x200 instead !! */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if 0 /* This is now a stack variable, as needed */ +#define REGBASE 0x300 +#endif + +#define AttributeIndexRegister REGBASE + 0xC0 +#define AttributeDataWriteRegister REGBASE + 0xC0 +#define AttributeDataReadRegister REGBASE + 0xC1 +#define AttributeRegister AttributeIndexRegister +#define AttributeModeIndex 0x30 +#define OverScanColorIndex 0x31 +#define ColorPlaneEnableIndex 0x32 +#define HorizPelPanIndex 0x33 +#define ColorSelectIndex 0x34 +#ifndef PC98_EGC +#define SetVideoAttributeIndex( index ) \ + SET_INDEX_REGISTER( AttributeIndexRegister, index ) +#define SetVideoAttribute( index, value ) \ + SetVideoAttributeIndex( index ) ; \ + SET_BYTE_REGISTER( AttributeDataWriteRegister, value ) +#endif + + /* Graphics Registers 03CE & 03CF */ +#define GraphicsIndexRegister REGBASE + 0xCE +#define GraphicsDataRegister REGBASE + 0xCF +#define GraphicsRegister GraphicsIndexRegister +#define Set_ResetIndex 0x00 +#define Enb_Set_ResetIndex 0x01 +#define Color_CompareIndex 0x02 +#define Data_RotateIndex 0x03 +#define Read_Map_SelectIndex 0x04 +#define Graphics_ModeIndex 0x05 +#define MiscellaneousIndex 0x06 +#define Color_Dont_CareIndex 0x07 +#define Bit_MaskIndex 0x08 +#ifndef PC98_EGC +#define SetVideoGraphicsIndex( index ) \ + SET_INDEX_REGISTER( GraphicsIndexRegister, index ) +#define SetVideoGraphicsData( value ) \ + SET_INDEX_REGISTER( GraphicsDataRegister, value ) +#define SetVideoGraphics( index, value ) \ + SET_INDEXED_REGISTER( GraphicsRegister, index, value ) +#endif + +/* Sequencer Registers 03C4 & 03C5 */ +#define SequencerIndexRegister REGBASE + 0xC4 +#define SequencerDataRegister REGBASE + 0xC5 +#define SequencerRegister SequencerIndexRegister +#define Seq_ResetIndex 00 +#define Clock_ModeIndex 01 +#define Mask_MapIndex 02 +#define Char_Map_SelectIndex 03 +#define Memory_ModeIndex 04 +#ifndef PC98_EGC +#define SetVideoSequencerIndex( index ) \ + SET_INDEX_REGISTER( SequencerIndexRegister, index ) +#define SetVideoSequencer( index, value ) \ + SET_INDEXED_REGISTER( SequencerRegister, index, value ) +#endif + +/* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */ +/* for the Graphics' Data_Rotate Register */ +#define VGA_ROTATE_FUNC_SHIFT 3 +#define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */ +#define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */ +#define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */ +#define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */ +/* for the Graphics' Graphics_Mode Register */ +#define VGA_READ_MODE_SHIFT 3 +#define VGA_WRITE_MODE_0 0 +#define VGA_WRITE_MODE_1 1 +#define VGA_WRITE_MODE_2 2 +#define VGA_WRITE_MODE_3 3 +#define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT ) +#define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT ) + +#ifdef PC98_EGC +/* I/O port address define for extended EGC */ +#define EGC_PLANE 0x4a0 /* EGC active plane select */ +#define EGC_READ 0x4a2 /* EGC FGC,EGC,Read Plane */ +#define EGC_MODE 0x4a4 /* EGC Mode register & ROP */ +#define EGC_FGC 0x4a6 /* EGC Forground color */ +#define EGC_MASK 0x4a8 /* EGC Mask register */ +#define EGC_BGC 0x4aa /* EGC Background color */ +#define EGC_ADD 0x4ac /* EGC Dest/Source address */ +#define EGC_LENGTH 0x4ae /* EGC Bit length */ + +#define PALETTE_ADD 0xa8 /* Palette address */ +#define PALETTE_GRE 0xaa /* Palette Green */ +#define PALETTE_RED 0xac /* Palette Red */ +#define PALETTE_BLU 0xae /* Palette Blue */ + +#define EGC_AND_MODE 0x2c8c /* (S&P&D)|(~S&D) */ +#define EGC_AND_INV_MODE 0x2c2c /* (S&P&~D)|(~S&D) */ +#define EGC_OR_MODE 0x2cec /* S&(P|D)|(~S&D) */ +#define EGC_OR_INV_MODE 0x2cbc /* S&(P|~D)|(~S&D) */ +#define EGC_XOR_MODE 0x2c6c /* (S&(P&~D|~P&D))|(~S&D) */ +#define EGC_XOR_INV_MODE 0x2c9c /* (S&(P&D)|(~P&~D))|(~S&D) */ +#define EGC_COPY_MODE 0x2cac /* (S&P)|(~S&D) */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaVideo.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaVideo.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vgaVideo.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/vgaVideo.h,v 1.1.2.1 1998/06/27 14:48:54 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ + +/* $XConsortium: vgaVideo.h /main/4 1996/02/21 17:59:14 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "misc.h" /* GJA -- for pointer data type */ +#ifdef lint +#if defined(volatile) +#undef volatile +#endif +#define volatile /**/ +#if defined(const) +#undef const +#endif +#define const /**/ +#if defined(signed) +#undef signed +#endif +#define signed /**/ +#endif + +/* + * References to all pc ( i.e. '286 ) memory in the + * regions used by the [ev]ga server ( the 128K windows ) + * MUST be long-word ( i.e. 32-bit ) reads or writes. + * This definition will change for other memory architectures + * ( e.g. AIX-Rt ) + */ +typedef unsigned char VideoAdapterObject ; +typedef volatile VideoAdapterObject *VideoMemoryPtr ; +typedef volatile VideoAdapterObject *VgaMemoryPtr ; +#if !defined(BITMAP_BIT_ORDER) +#define BITMAP_BIT_ORDER MSBFirst +#endif + +#if !defined(IMAGE_BYTE_ORDER) +#define IMAGE_BYTE_ORDER LSBFirst +#endif + +/* Bit Ordering Macros */ +#if !defined(SCRLEFT8) +#define SCRLEFT8(lw, n) ( (unsigned char) (((unsigned char) lw) << (n)) ) +#endif +#if !defined(SCRRIGHT8) +#define SCRRIGHT8(lw, n) ( (unsigned char) (((unsigned char)lw) >> (n)) ) +#endif +/* These work ONLY on 8-bit wide Quantities !! */ +#define LeftmostBit ( SCRLEFT8( 0xFF, 7 ) & 0xFF ) +#define RightmostBit ( SCRRIGHT8( 0xFF, 7 ) & 0xFF ) + +/* + * [ev]ga video screen defines & macros + */ +#define VGA_BLACK_PIXEL 0 +#define VGA_WHITE_PIXEL 1 + +#define VGA_MAXPLANES 4 +#define VGA_ALLPLANES 0xFL + +#define VIDBASE(pDraw) ((volatile unsigned char *) \ + (((PixmapPtr)(((DrawablePtr)(pDraw))->pScreen->devPrivate))-> \ + devPrivate.ptr)) +#define BYTES_PER_LINE(pDraw) \ + ((int)((PixmapPtr)(((DrawablePtr)(pDraw))->pScreen->devPrivate))->devKind) + +#define ROW_OFFSET( x ) ( ( x ) >> 3 ) +#define BIT_OFFSET( x ) ( ( x ) & 0x7 ) +#define SCREENADDRESS( pWin, x, y ) \ + ( VIDBASE(pWin) + (y) * BYTES_PER_LINE(pWin) + ROW_OFFSET(x) ) + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmode.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/vidmode.h,v 1.1 2000/05/18 16:30:00 dawes Exp $ + */ + +#ifndef _xf86cfg_vidmode_h +#define _xf86cfg_vidmode_h + +#include "xf86config.h" +#include + +/* + * Types + */ +struct _xf86cfgVidMode { + XF86ConfMonitorPtr monitor; + int screen; + int num_infos; + XF86VidModeModeInfo **infos; +}; + +/* + * Prototypes + */ +Bool VideoModeInitialize(void); +void VideoModeConfigureStart(void); +void VideoModeConfigureEnd(void); +void VidmodeRestoreAction(Widget, XEvent*, String*, Cardinal*); +void CancelAddModeAction(Widget, XEvent*, String*, Cardinal*); +void CancelTestModeAction(Widget, XEvent*, String*, Cardinal*); +void InitializeVidmodes(void); + +/* + * Initialization + */ +extern Widget vtune; + +#endif /* _xf86cfg_vidmode_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmodeproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmodeproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/vidmodeproc.h (revision 51223) @@ -0,0 +1,78 @@ +/* $XFree86: xc/programs/Xserver/Xext/vidmodeproc.h,v 1.4 1999/12/13 01:39:40 robin Exp $ */ + +/* Prototypes for DGA functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _VIDMODEPROC_H_ +#define _VIDMODEPROC_H_ + + +typedef enum { + VIDMODE_H_DISPLAY, + VIDMODE_H_SYNCSTART, + VIDMODE_H_SYNCEND, + VIDMODE_H_TOTAL, + VIDMODE_H_SKEW, + VIDMODE_V_DISPLAY, + VIDMODE_V_SYNCSTART, + VIDMODE_V_SYNCEND, + VIDMODE_V_TOTAL, + VIDMODE_FLAGS, + VIDMODE_CLOCK +} VidModeSelectMode; + +typedef enum { + VIDMODE_MON_VENDOR, + VIDMODE_MON_MODEL, + VIDMODE_MON_NHSYNC, + VIDMODE_MON_NVREFRESH, + VIDMODE_MON_HSYNC_LO, + VIDMODE_MON_HSYNC_HI, + VIDMODE_MON_VREFRESH_LO, + VIDMODE_MON_VREFRESH_HI +} VidModeSelectMonitor; + +typedef union { + pointer ptr; + int i; + float f; +} vidMonitorValue; + +void XFree86VidModeExtensionInit(void); + +Bool VidModeAvailable(int scrnIndex); +Bool VidModeGetCurrentModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeGetFirstModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeGetNextModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeDeleteModeline(int scrnIndex, pointer mode); +Bool VidModeZoomViewport(int scrnIndex, int zoom); +Bool VidModeGetViewPort(int scrnIndex, int *x, int *y); +Bool VidModeSetViewPort(int scrnIndex, int x, int y); +Bool VidModeSwitchMode(int scrnIndex, pointer mode); +Bool VidModeLockZoom(int scrnIndex, Bool lock); +Bool VidModeGetMonitor(int scrnIndex, pointer *monitor); +int VidModeGetNumOfClocks(int scrnIndex, Bool *progClock); +Bool VidModeGetClocks(int scrnIndex, int *Clocks); +ModeStatus VidModeCheckModeForMonitor(int scrnIndex, pointer mode); +ModeStatus VidModeCheckModeForDriver(int scrnIndex, pointer mode); +void VidModeSetCrtcForMode(int scrnIndex, pointer mode); +Bool VidModeAddModeline(int scrnIndex, pointer mode); +int VidModeGetDotClock(int scrnIndex, int Clock); +int VidModeGetNumOfModes(int scrnIndex); +Bool VidModeSetGamma(int scrnIndex, float red, float green, float blue); +Bool VidModeGetGamma(int scrnIndex, float *red, float *green, float *blue); +pointer VidModeCreateMode(void); +void VidModeCopyMode(pointer modefrom, pointer modeto); +int VidModeGetModeValue(pointer mode, int valtyp); +void VidModeSetModeValue(pointer mode, int valtyp, int val); +vidMonitorValue VidModeGetMonitorValue(pointer monitor, int valtyp, int indx); +Bool VidModeSetGammaRamp(int, int, CARD16 *, CARD16 *, CARD16 *); +Bool VidModeGetGammaRamp(int, int, CARD16 *, CARD16 *, CARD16 *); +int VidModeGetGammaRampSize(int scrnIndex); + +#endif + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/window.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/window.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/window.h (revision 51223) @@ -0,0 +1,265 @@ +/* $Xorg: window.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef WINDOW_H +#define WINDOW_H + +#include "misc.h" +#include "region.h" +#include "screenint.h" +#include + +#define TOTALLY_OBSCURED 0 +#define UNOBSCURED 1 +#define OBSCURED 2 + +#define VisibilityNotViewable 3 + +/* return values for tree-walking callback procedures */ +#define WT_STOPWALKING 0 +#define WT_WALKCHILDREN 1 +#define WT_DONTWALKCHILDREN 2 +#define WT_NOMATCH 3 +#define NullWindow ((WindowPtr) 0) + +typedef struct _BackingStore *BackingStorePtr; +typedef struct _Window *WindowPtr; + +typedef int (*VisitWindowProcPtr)( + WindowPtr /*pWin*/, + pointer /*data*/); + +extern int TraverseTree( + WindowPtr /*pWin*/, + VisitWindowProcPtr /*func*/, + pointer /*data*/); + +extern int WalkTree( + ScreenPtr /*pScreen*/, + VisitWindowProcPtr /*func*/, + pointer /*data*/); + +extern WindowPtr AllocateWindow( + ScreenPtr /*pScreen*/); + +extern Bool CreateRootWindow( + ScreenPtr /*pScreen*/); + +extern void InitRootWindow( + WindowPtr /*pWin*/); + +extern void ClippedRegionFromBox( + WindowPtr /*pWin*/, + RegionPtr /*Rgn*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/); + +extern WindowPtr RealChildHead( + WindowPtr /*pWin*/); + +extern WindowPtr CreateWindow( + Window /*wid*/, + WindowPtr /*pParent*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + unsigned int /*bw*/, + unsigned int /*class*/, + Mask /*vmask*/, + XID* /*vlist*/, + int /*depth*/, + ClientPtr /*client*/, + VisualID /*visual*/, + int* /*error*/); + +extern int DeleteWindow( + pointer /*pWin*/, + XID /*wid*/); + +extern void DestroySubwindows( + WindowPtr /*pWin*/, + ClientPtr /*client*/); + +/* Quartz support on Mac OS X uses the HIToolbox + framework whose ChangeWindowAttributes function conflicts here. */ +#ifdef __DARWIN__ +#define ChangeWindowAttributes Darwin_X_ChangeWindowAttributes +#endif +extern int ChangeWindowAttributes( + WindowPtr /*pWin*/, + Mask /*vmask*/, + XID* /*vlist*/, + ClientPtr /*client*/); + +/* Quartz support on Mac OS X uses the HIToolbox + framework whose GetWindowAttributes function conflicts here. */ +#ifdef __DARWIN__ +#define GetWindowAttributes(w,c,x) Darwin_X_GetWindowAttributes(w,c,x) +extern void Darwin_X_GetWindowAttributes( +#else +extern void GetWindowAttributes( +#endif + WindowPtr /*pWin*/, + ClientPtr /*client*/, + xGetWindowAttributesReply* /* wa */); + +extern RegionPtr CreateUnclippedWinSize( + WindowPtr /*pWin*/); + +extern void GravityTranslate( + int /*x*/, + int /*y*/, + int /*oldx*/, + int /*oldy*/, + int /*dw*/, + int /*dh*/, + unsigned /*gravity*/, + int* /*destx*/, + int* /*desty*/); + +extern int ConfigureWindow( + WindowPtr /*pWin*/, + Mask /*mask*/, + XID* /*vlist*/, + ClientPtr /*client*/); + +extern int CirculateWindow( + WindowPtr /*pParent*/, + int /*direction*/, + ClientPtr /*client*/); + +extern int ReparentWindow( + WindowPtr /*pWin*/, + WindowPtr /*pParent*/, + int /*x*/, + int /*y*/, + ClientPtr /*client*/); + +extern int MapWindow( + WindowPtr /*pWin*/, + ClientPtr /*client*/); + +extern void MapSubwindows( + WindowPtr /*pParent*/, + ClientPtr /*client*/); + +extern int UnmapWindow( + WindowPtr /*pWin*/, + Bool /*fromConfigure*/); + +extern void UnmapSubwindows( + WindowPtr /*pWin*/); + +extern void HandleSaveSet( + ClientPtr /*client*/); + +extern Bool VisibleBoundingBoxFromPoint( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + BoxPtr /*box*/); + +extern Bool PointInWindowIsVisible( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/); + +extern RegionPtr NotClippedByChildren( + WindowPtr /*pWin*/); + +extern void SendVisibilityNotify( + WindowPtr /*pWin*/); + +extern void SaveScreens( + int /*on*/, + int /*mode*/); + +extern WindowPtr FindWindowWithOptional( + WindowPtr /*w*/); + +extern void CheckWindowOptionalNeed( + WindowPtr /*w*/); + +extern Bool MakeWindowOptional( + WindowPtr /*pWin*/); + +extern void DisposeWindowOptional( + WindowPtr /*pWin*/); + +extern WindowPtr MoveWindowInStack( + WindowPtr /*pWin*/, + WindowPtr /*pNextSib*/); + +void SetWinSize( + WindowPtr /*pWin*/); + +void SetBorderSize( + WindowPtr /*pWin*/); + +void ResizeChildrenWinSize( + WindowPtr /*pWin*/, + int /*dx*/, + int /*dy*/, + int /*dw*/, + int /*dh*/); + +extern void SendShapeNotify( + WindowPtr /* pWin */, + int /* which */ ); + +extern RegionPtr CreateBoundingShape( + WindowPtr /* pWin */ ); + +extern RegionPtr CreateClipShape( + WindowPtr /* pWin */ ); + +#endif /* WINDOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/windowstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/windowstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/windowstr.h (revision 51223) @@ -0,0 +1,234 @@ +/* $Xorg: windowstr.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/windowstr.h,v 1.6 2001/12/14 19:59:57 dawes Exp $ */ + +#ifndef WINDOWSTRUCT_H +#define WINDOWSTRUCT_H + +#include "window.h" +#include "pixmapstr.h" +#include "regionstr.h" +#include "cursor.h" +#include "property.h" +#include "resource.h" /* for ROOT_WINDOW_ID_BASE */ +#include "dix.h" +#include "miscstruct.h" +#include +#include "opaque.h" + +#define GuaranteeNothing 0 +#define GuaranteeVisBack 1 + +#define SameBackground(as, a, bs, b) \ + ((as) == (bs) && ((as) == None || \ + (as) == ParentRelative || \ + SamePixUnion(a,b,as == BackgroundPixel))) + +#define SameBorder(as, a, bs, b) \ + EqualPixUnion(as, a, bs, b) + +typedef struct _WindowOpt { + VisualID visual; /* default: same as parent */ + CursorPtr cursor; /* default: window.cursorNone */ + Colormap colormap; /* default: same as parent */ + Mask dontPropagateMask; /* default: window.dontPropagate */ + Mask otherEventMasks; /* default: 0 */ + struct _OtherClients *otherClients; /* default: NULL */ + struct _GrabRec *passiveGrabs; /* default: NULL */ + PropertyPtr userProps; /* default: NULL */ + unsigned long backingBitPlanes; /* default: ~0L */ + unsigned long backingPixel; /* default: 0 */ +#ifdef SHAPE + RegionPtr boundingShape; /* default: NULL */ + RegionPtr clipShape; /* default: NULL */ + RegionPtr inputShape; /* default: NULL */ +#endif +#ifdef XINPUT + struct _OtherInputMasks *inputMasks; /* default: NULL */ +#endif +} WindowOptRec, *WindowOptPtr; + +#define BackgroundPixel 2L +#define BackgroundPixmap 3L + +typedef struct _Window { + DrawableRec drawable; + WindowPtr parent; /* ancestor chain */ + WindowPtr nextSib; /* next lower sibling */ + WindowPtr prevSib; /* next higher sibling */ + WindowPtr firstChild; /* top-most child */ + WindowPtr lastChild; /* bottom-most child */ + RegionRec clipList; /* clipping rectangle for output */ + RegionRec borderClip; /* NotClippedByChildren + border */ + union _Validate *valdata; + RegionRec winSize; + RegionRec borderSize; + DDXPointRec origin; /* position relative to parent */ + unsigned short borderWidth; + unsigned short deliverableEvents; + Mask eventMask; + PixUnion background; + PixUnion border; + pointer backStorage; /* null when BS disabled */ + WindowOptPtr optional; + unsigned backgroundState:2; /* None, Relative, Pixel, Pixmap */ + unsigned borderIsPixel:1; + unsigned cursorIsNone:1; /* else real cursor (might inherit) */ + unsigned backingStore:2; + unsigned saveUnder:1; + unsigned DIXsaveUnder:1; + unsigned bitGravity:4; + unsigned winGravity:4; + unsigned overrideRedirect:1; + unsigned visibility:2; + unsigned mapped:1; + unsigned realized:1; /* ancestors are all mapped */ + unsigned viewable:1; /* realized && InputOutput */ + unsigned dontPropagate:3;/* index into DontPropagateMasks */ + unsigned forcedBS:1; /* system-supplied backingStore */ +#ifdef NEED_DBE_BUF_BITS +#define DBE_FRONT_BUFFER 1 +#define DBE_BACK_BUFFER 0 + unsigned dstBuffer:1; /* destination buffer for rendering */ + unsigned srcBuffer:1; /* source buffer for rendering */ +#endif +#ifdef COMPOSITE + unsigned redirectDraw:1; /* rendering is redirected from here */ +#endif + DevUnion *devPrivates; +} WindowRec; + +/* + * Ok, a bunch of macros for accessing the optional record + * fields (or filling the appropriate default value) + */ + +extern Mask DontPropagateMasks[]; + +#define wTrackParent(w,field) ((w)->optional ? \ + (w)->optional->field \ + : FindWindowWithOptional(w)->optional->field) +#define wUseDefault(w,field,def) ((w)->optional ? \ + (w)->optional->field \ + : def) + +#define wVisual(w) wTrackParent(w, visual) +#define wCursor(w) ((w)->cursorIsNone ? None : wTrackParent(w, cursor)) +#define wColormap(w) ((w)->drawable.class == InputOnly ? None : wTrackParent(w, colormap)) +#define wDontPropagateMask(w) wUseDefault(w, dontPropagateMask, DontPropagateMasks[(w)->dontPropagate]) +#define wOtherEventMasks(w) wUseDefault(w, otherEventMasks, 0) +#define wOtherClients(w) wUseDefault(w, otherClients, NULL) +#ifdef XINPUT +#define wOtherInputMasks(w) wUseDefault(w, inputMasks, NULL) +#else +#define wOtherInputMasks(w) NULL +#endif +#define wPassiveGrabs(w) wUseDefault(w, passiveGrabs, NULL) +#define wUserProps(w) wUseDefault(w, userProps, NULL) +#define wBackingBitPlanes(w) wUseDefault(w, backingBitPlanes, ~0L) +#define wBackingPixel(w) wUseDefault(w, backingPixel, 0) +#ifdef SHAPE +#define wBoundingShape(w) wUseDefault(w, boundingShape, NULL) +#define wClipShape(w) wUseDefault(w, clipShape, NULL) +#define wInputShape(w) wUseDefault(w, inputShape, NULL) +#endif +#define wClient(w) (clients[CLIENT_ID((w)->drawable.id)]) +#define wBorderWidth(w) ((int) (w)->borderWidth) + +/* true when w needs a border drawn. */ + +#ifdef SHAPE +#define HasBorder(w) ((w)->borderWidth || wClipShape(w)) +#else +#define HasBorder(w) ((w)->borderWidth) +#endif + +typedef struct _ScreenSaverStuff { + WindowPtr pWindow; + XID wid; + char blanked; + Bool (*ExternalScreenSaver)( + ScreenPtr /*pScreen*/, + int /*xstate*/, + Bool /*force*/); +} ScreenSaverStuffRec, *ScreenSaverStuffPtr; + +#define SCREEN_IS_BLANKED 0 +#define SCREEN_ISNT_SAVED 1 +#define SCREEN_IS_TILED 2 +#define SCREEN_IS_BLACK 3 + +#define HasSaverWindow(i) (savedScreenInfo[i].pWindow != NullWindow) + +extern int screenIsSaved; +extern ScreenSaverStuffRec savedScreenInfo[MAXSCREENS]; + +/* + * this is the configuration parameter "NO_BACK_SAVE" + * it means that any existant backing store should not + * be used to implement save unders. + */ + +#ifndef NO_BACK_SAVE +#define DO_SAVE_UNDERS(pWin) ((pWin)->drawable.pScreen->saveUnderSupport ==\ + USE_DIX_SAVE_UNDERS) +/* + * saveUnderSupport is set to this magic value when using DIXsaveUnders + */ + +#define USE_DIX_SAVE_UNDERS 0x40 +#endif + +extern int numSaveUndersViewable; +extern int deltaSaveUndersViewable; + +#ifdef XEVIE +extern WindowPtr xeviewin; +#endif + +#endif /* WINDOWSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/wm3.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/wm3.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/wm3.h (revision 51223) @@ -0,0 +1,81 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/wm3.h,v 1.2 1998/07/25 16:59:46 dawes Exp $ */ + + + + + +/* $XConsortium: wm3.h /main/4 1996/02/21 17:59:24 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "vgaReg.h" + +#ifdef PC98_EGC +#define VGA_ALLPLANES 0xFL +#endif + +/* Do call in Write Mode 3. + * We take care of the possibility that two passes are needed. + */ +#ifndef PC98_EGC +#define DO_WM3(pgc,call) \ + { int _tp, _fg, _bg, _alu; \ + _fg = pgc->fgPixel; _bg = pgc->bgPixel; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + if ( _tp ) { \ + _alu = pgc->alu; \ + pgc->alu = GXinvert; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + pgc->alu = _alu; \ + } \ + pgc->fgPixel = _fg; pgc->bgPixel = _bg; \ + } +#else +#define DO_WM3(pgc,call) \ + { int _tp, _fg, _bg; \ + _fg = pgc->fgPixel; _bg = pgc->bgPixel; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + pgc->fgPixel = _fg; pgc->bgPixel = _bg; \ + } +#endif + +#ifndef PC98_EGC +#define WM3_SET_INK(ink) \ + SetVideoGraphics(Set_ResetIndex, ink) +#else +#define WM3_SET_INK(ink) \ + outw(EGC_FGC, ink) +#endif + +/* GJA -- Move a long word to screen memory. + * The reads into 'dummy' are here to load the VGA latches. + * This is a RMW operation except for trivial cases. + * Notice that we ignore the operation. + */ +#ifdef PC98_EGC +#define UPDRW(destp,src) \ + { volatile unsigned short *_dtmp = \ + (volatile unsigned short *)(destp); \ + unsigned int _stmp = (src); \ + *_dtmp = _stmp; _dtmp++; _stmp >>= 16; \ + *_dtmp = _stmp; } +#else +#define UPDRW(destp,src) \ + { volatile char *_dtmp = (volatile char *)(destp); \ + unsigned int _stmp = (src); \ + volatile int dummy; /* Bit bucket. */ \ + _stmp = ldl_u(&_stmp); \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; } +#endif + +#define UPDRWB(destp,src) \ + { volatile int dummy; /* Bit bucket. */ \ + dummy = *(destp); *(destp) = (src); } Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hash.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hash.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hash.h (revision 51223) @@ -0,0 +1,62 @@ +/* x-hash.h -- basic hash table class + $Id: x-hash.h,v 1.3 2005/07/01 22:43:08 daniels Exp $ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/x-hash.h,v 1.1 2003/04/30 23:15:42 torrey Exp $ */ + +#ifndef X_HASH_H +#define X_HASH_H 1 + +typedef struct x_hash_table_struct x_hash_table; + +typedef int (x_compare_fun) (const void *a, const void *b); +typedef unsigned int (x_hash_fun) (const void *k); +typedef void (x_destroy_fun) (void *x); +typedef void (x_hash_foreach_fun) (void *k, void *v, void *data); + +/* for X_PFX and X_EXTERN */ +#include "x-list.h" + +X_EXTERN x_hash_table *X_PFX (hash_table_new) (x_hash_fun *hash, + x_compare_fun *compare, + x_destroy_fun *key_destroy, + x_destroy_fun *value_destroy); +X_EXTERN void X_PFX (hash_table_free) (x_hash_table *h); + +X_EXTERN unsigned int X_PFX (hash_table_size) (x_hash_table *h); + +X_EXTERN void X_PFX (hash_table_insert) (x_hash_table *h, void *k, void *v); +X_EXTERN void X_PFX (hash_table_replace) (x_hash_table *h, void *k, void *v); +X_EXTERN void X_PFX (hash_table_remove) (x_hash_table *h, void *k); +X_EXTERN void *X_PFX (hash_table_lookup) (x_hash_table *h, + void *k, void **k_ret); +X_EXTERN void X_PFX (hash_table_foreach) (x_hash_table *h, + x_hash_foreach_fun *fun, + void *data); + +#endif /* X_HASH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hook.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hook.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-hook.h (revision 51223) @@ -0,0 +1,44 @@ +/* x-hook.h -- lists of function,data pairs to call. + $Id: x-hook.h,v 1.3 2005/07/01 22:43:08 daniels Exp $ + + Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: $ */ + +#ifndef X_HOOK_H +#define X_HOOK_H 1 + +#include "x-list.h" + +typedef void x_hook_function (void *arg, void *data); + +X_EXTERN x_list *X_PFX (hook_add) (x_list *lst, x_hook_function *fun, void *data); +X_EXTERN x_list *X_PFX (hook_remove) (x_list *lst, x_hook_function *fun, void *data); +X_EXTERN void X_PFX (hook_run) (x_list *lst, void *arg); +X_EXTERN void X_PFX (hook_free) (x_list *lst); + +#endif /* X_HOOK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-list.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-list.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x-list.h (revision 51223) @@ -0,0 +1,79 @@ +/* x-list.h -- simple list type + $Id: x-list.h,v 1.4 2005/07/01 22:43:08 daniels Exp $ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/x-list.h,v 1.1 2003/04/30 23:15:42 torrey Exp $ */ + +#ifndef X_LIST_H +#define X_LIST_H 1 + +/* This is just a cons. */ + +typedef struct x_list_struct x_list; + +struct x_list_struct { + void *data; + x_list *next; +}; + +#ifndef X_PFX +# define X_PFX(x) x_ ## x +#endif + +#ifndef X_EXTERN +# define X_EXTERN __private_extern__ +#endif + +X_EXTERN void X_PFX (list_free_1) (x_list *node); +X_EXTERN x_list *X_PFX (list_prepend) (x_list *lst, void *data); + +X_EXTERN x_list *X_PFX (list_append) (x_list *lst, void *data); +X_EXTERN x_list *X_PFX (list_remove) (x_list *lst, void *data); +X_EXTERN void X_PFX (list_free) (x_list *lst); +X_EXTERN x_list *X_PFX (list_pop) (x_list *lst, void **data_ret); + +X_EXTERN x_list *X_PFX (list_copy) (x_list *lst); +X_EXTERN x_list *X_PFX (list_reverse) (x_list *lst); +X_EXTERN x_list *X_PFX (list_find) (x_list *lst, void *data); +X_EXTERN x_list *X_PFX (list_nth) (x_list *lst, int n); +X_EXTERN x_list *X_PFX (list_filter) (x_list *src, + int (*pred) (void *item, void *data), + void *data); +X_EXTERN x_list *X_PFX (list_map) (x_list *src, + void *(*fun) (void *item, void *data), + void *data); + +X_EXTERN unsigned int X_PFX (list_length) (x_list *lst); +X_EXTERN void X_PFX (list_foreach) (x_list *lst, void (*fun) + (void *data, void *user_data), + void *user_data); + +X_EXTERN x_list *X_PFX (list_sort) (x_list *lst, int (*less) (const void *, + const void *)); + +#endif /* X_LIST_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emu.h (revision 51223) @@ -0,0 +1,198 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK /* Don't pack structs with function pointers! */ +#endif + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef DEBUG +#define HALT_SYS() \ + printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ + X86EMU_halt_sys() +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_SAVE_IP_CS_F 0x000040 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_TRACECALL_REGS_F 0x004000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_EXIT 0x010000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emui.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emui.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/x86emui.h (revision 51223) @@ -0,0 +1,102 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" + +#ifndef NO_SYS_HEADERS +#include +#include +#include +#endif +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaa.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaa.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaa.h (revision 51223) @@ -0,0 +1,1402 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaa.h,v 1.38 2002/10/21 01:54:04 mvojkovi Exp $ */ + +#ifndef _XAA_H +#define _XAA_H + +/* + + ******** OPERATION SPECIFIC FLAGS ********* + + **** solid/dashed line flags **** + +--------- -------- +23 LINE_PATTERN_LSBFIRST_MSBJUSTIFIED +22 LINE_PATTERN_LSBFIRST_LSBJUSTIFIED +21 LINE_PATTERN_MSBFIRST_MSBJUSTIFIED +20 LINE_PATTERN_MSBFIRST_LSBJUSTIFIED +19 LINE_PATTERN_POWER_OF_2_ONLY +18 LINE_LIMIT_COORDS +17 . +16 . +--------- ------- + + **** screen to screen copy flags **** + +--------- -------- +23 ONLY_LEFT_TO_RIGHT_BITBLT +22 ONLY_TWO_BITBLT_DIRECTIONS +21 . +20 . +19 . +18 . +17 . +16 . +--------- ------- + + **** clipping flags **** + +--------- -------- +23 . +22 HARDWARE_CLIP_SCREEN_TO_SCREEN_COLOR_EXPAND +21 HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY +20 HARDWARE_CLIP_MONO_8x8_FILL +19 HARDWARE_CLIP_COLOR_8x8_FILL +18 HARDWARE_CLIP_SOLID_FILL +17 HARDWARE_CLIP_DASHED_LINE +16 HARDWARE_CLIP_SOLID_LINE +--------- ------- + + + **** hardware pattern flags **** + +--------- -------- +23 . +22 . +21 HARDWARE_PATTERN_SCREEN_ORIGIN +20 . +19 . +18 . +17 HARDWARE_PATTERN_PROGRAMMED_ORIGIN +16 HARDWARE_PATTERN_PROGRAMMED_BITS +--------- ------- + + **** write pixmap flags **** + +--------- -------- +23 . +22 . +21 . +20 . +19 . +18 . +17 . +16 CONVERT_32BPP_TO_24BPP +--------- ------- + + + ******** GENERIC FLAGS ********* + +--------- ------- +15 SYNC_AFTER_COLOR_EXPAND +14 CPU_TRANSFER_PAD_QWORD +13 . +12 LEFT_EDGE_CLIPPING_NEGATIVE_X +11 LEFT_EDGE_CLIPPING +10 CPU_TRANSFER_BASE_FIXED + 9 BIT_ORDER_IN_BYTE_MSBFIRST + 8 TRANSPARENCY_GXCOPY_ONLY +--------- ------- + 7 NO_TRANSPARENCY + 6 TRANSPARENCY_ONLY + 5 ROP_NEEDS_SOURCE + 4 TRIPLE_BITS_24BPP + 3 RGB_EQUAL + 2 NO_PLANEMASK + 1 NO_GXCOPY + 0 GXCOPY_ONLY +--------- ------- + + +*/ + +#include "gcstruct.h" +#include "pixmapstr.h" +#include "xf86str.h" +#include "regionstr.h" +#include "xf86fbman.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +/* Flags */ +#define PIXMAP_CACHE 0x00000001 +#define MICROSOFT_ZERO_LINE_BIAS 0x00000002 +#define OFFSCREEN_PIXMAPS 0x00000004 +#define LINEAR_FRAMEBUFFER 0x00000008 + + +/* GC fg, bg, and planemask restrictions */ +#define GXCOPY_ONLY 0x00000001 +#define NO_GXCOPY 0x00000002 +#define NO_PLANEMASK 0x00000004 +#define RGB_EQUAL 0x00000008 +#define TRIPLE_BITS_24BPP 0x00000010 +#define ROP_NEEDS_SOURCE 0x00000020 + +/* transparency restrictions */ +#define TRANSPARENCY_ONLY 0x00000040 +#define NO_TRANSPARENCY 0x00000080 +#define TRANSPARENCY_GXCOPY_ONLY 0x00000100 + +/* bit order restrictions */ +#define BIT_ORDER_IN_BYTE_MSBFIRST 0x00000200 +#define BIT_ORDER_IN_BYTE_LSBFIRST 0x00000000 + +/* transfer base restriction */ +#define CPU_TRANSFER_BASE_FIXED 0x00000400 + +/* skipleft restrictions */ +#define LEFT_EDGE_CLIPPING 0x00000800 +#define LEFT_EDGE_CLIPPING_NEGATIVE_X 0x00001000 + +/* data padding */ +#define CPU_TRANSFER_PAD_DWORD 0x00000000 +#define CPU_TRANSFER_PAD_QWORD 0x00004000 +#define SCANLINE_PAD_DWORD 0x00000000 + +#define SYNC_AFTER_COLOR_EXPAND 0x00008000 +#define SYNC_AFTER_IMAGE_WRITE SYNC_AFTER_COLOR_EXPAND + +/* hardware pattern */ +#define HARDWARE_PATTERN_PROGRAMMED_BITS 0x00010000 +#define HARDWARE_PATTERN_PROGRAMMED_ORIGIN 0x00020000 +#define HARDWARE_PATTERN_SCREEN_ORIGIN 0x00200000 + +/* copyarea flags */ +#define ONLY_TWO_BITBLT_DIRECTIONS 0x00400000 +#define ONLY_LEFT_TO_RIGHT_BITBLT 0x00800000 + +/* line flags */ +#define LINE_PATTERN_LSBFIRST_MSBJUSTIFIED 0x00800000 +#define LINE_PATTERN_LSBFIRST_LSBJUSTIFIED 0x00400000 +#define LINE_PATTERN_MSBFIRST_MSBJUSTIFIED 0x00200000 +#define LINE_PATTERN_MSBFIRST_LSBJUSTIFIED 0x00100000 +#define LINE_PATTERN_POWER_OF_2_ONLY 0x00080000 +#define LINE_LIMIT_COORDS 0x00040000 + +/* clipping flags */ +#define HARDWARE_CLIP_SCREEN_TO_SCREEN_COLOR_EXPAND 0x00400000 +#define HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY 0x00200000 +#define HARDWARE_CLIP_MONO_8x8_FILL 0x00100000 +#define HARDWARE_CLIP_COLOR_8x8_FILL 0x00080000 +#define HARDWARE_CLIP_SOLID_FILL 0x00040000 +#define HARDWARE_CLIP_DASHED_LINE 0x00020000 +#define HARDWARE_CLIP_SOLID_LINE 0x00010000 + +#define HARDWARE_CLIP_LINE 0x00000000 + + +/* image write flags */ +#define CONVERT_32BPP_TO_24BPP 0x00010000 + +/* pixmap cache flags */ +#define CACHE_MONO_8x8 0x00000001 +#define CACHE_COLOR_8x8 0x00000002 +#define DO_NOT_BLIT_STIPPLES 0x00000004 +#define DO_NOT_TILE_MONO_DATA 0x00000008 +#define DO_NOT_TILE_COLOR_DATA 0x00000010 + + +#define DEGREES_0 0 +#define DEGREES_90 1 +#define DEGREES_180 2 +#define DEGREES_270 3 + +#define OMIT_LAST 1 + +/* render flags */ + +#define XAA_RENDER_POWER_OF_2_TILE_ONLY 0x00000008 +#define XAA_RENDER_NO_SRC_ALPHA 0x00000004 +#define XAA_RENDER_IMPRECISE_ONLY 0x00000002 +#define XAA_RENDER_NO_TILE 0x00000001 + +#define XAA_RENDER_REPEAT 0x00000001 + +typedef void (* ValidateGCProcPtr)( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +typedef struct { + unsigned char *bits; + int width; + int height; + int yoff; + int srcwidth; + int start; + int end; +} NonTEGlyphInfo, *NonTEGlyphPtr; + + +typedef struct { + int x; + int y; + int w; + int h; + int orig_w; + int orig_h; + unsigned long serialNumber; + int pat0; + int pat1; + int fg; + int bg; + int trans_color; + DDXPointPtr offsets; + DevUnion devPrivate; +} XAACacheInfoRec, *XAACacheInfoPtr; + + +typedef struct _PixmapLink { + PixmapPtr pPix; + struct _PixmapLink *next; + FBAreaPtr area; +} PixmapLink, *PixmapLinkPtr; + +typedef struct _XAAInfoRec { + ScrnInfoPtr pScrn; + int Flags; + + void (*Sync)( + ScrnInfoPtr pScrn + ); + + /* Restore Accel State is a driver callback that is used + * when another screen on the same device has been active. + * This allows multihead on a single device to work. + * If The entityProp has IS_SHARED_ACCEL defined then this + * function is required. + */ + + void (*RestoreAccelState)( + ScrnInfoPtr pScrn + ); + + /***************** Low Level *****************/ + +/* Blits */ + void (*SetupForScreenToScreenCopy)( + ScrnInfoPtr pScrn, + int xdir, int ydir, + int rop, + unsigned int planemask, + int trans_color + ); + int ScreenToScreenCopyFlags; + + void (*SubsequentScreenToScreenCopy)( + ScrnInfoPtr pScrn, + int xsrc, int ysrc, + int xdst, int ydst, + int w, int h + ); + + +/* Solid fills */ + void (*SetupForSolidFill)( + ScrnInfoPtr pScrn, + int color, + int rop, + unsigned int planemask + ); + int SolidFillFlags; + + void (*SubsequentSolidFillRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h + ); + + void (*SubsequentSolidFillTrap)( + ScrnInfoPtr pScrn, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + + +/* Solid lines */ + + void (*SetupForSolidLine)( + ScrnInfoPtr pScrn, + int color, + int rop, + unsigned int planemask + ); + int SolidLineFlags; + + void (*SubsequentSolidTwoPointLine)( + ScrnInfoPtr pScrn, + int xa, int ya, int xb, int yb, int flags + ); + + void (*SubsequentSolidBresenhamLine)( + ScrnInfoPtr pScrn, + int x, int y, int absmaj, int absmin, int err, int len, int octant + ); + int SolidBresenhamLineErrorTermBits; + + void (*SubsequentSolidHorVertLine)( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir + ); + +/* Dashed lines */ + + void (*SetupForDashedLine)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask, + int length, + unsigned char *pattern + ); + int DashedLineFlags; + int DashPatternMaxLength; + + void (*SubsequentDashedTwoPointLine)( + ScrnInfoPtr pScrn, + int xa, int ya, int xb, int yb, int flags, int phase + ); + + void (*SubsequentDashedBresenhamLine)( + ScrnInfoPtr pScrn, + int x, int y, int absmaj, int absmin, int err, int len, int flags, + int phase + ); + int DashedBresenhamLineErrorTermBits; + +/* Clipper */ + + void (*SetClippingRectangle) ( + ScrnInfoPtr pScrn, + int left, int top, int right, int bottom + ); + int ClippingFlags; + + void (*DisableClipping)(ScrnInfoPtr pScrn); + +/* 8x8 mono pattern fills */ + void (*SetupForMono8x8PatternFill)( + ScrnInfoPtr pScrn, + int patx, int paty, + int fg, int bg, + int rop, + unsigned int planemask + ); + int Mono8x8PatternFillFlags; + + void (*SubsequentMono8x8PatternFillRect)( + ScrnInfoPtr pScrn, + int patx, int paty, + int x, int y, int w, int h + ); + + void (*SubsequentMono8x8PatternFillTrap)( + ScrnInfoPtr pScrn, + int patx, int paty, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + +/* 8x8 color pattern fills */ + + void (*SetupForColor8x8PatternFill)( + ScrnInfoPtr pScrn, + int patx, int paty, + int rop, + unsigned int planemask, + int transparency_color + ); + int Color8x8PatternFillFlags; + + void (*SubsequentColor8x8PatternFillRect)( + ScrnInfoPtr pScrn, + int patx, int paty, + int x, int y, int w, int h + ); + + void (*SubsequentColor8x8PatternFillTrap)( + ScrnInfoPtr pScrn, + int patx, int paty, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + + +/* Color expansion */ + + void (*SetupForCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int CPUToScreenColorExpandFillFlags; + + void (*SubsequentCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + unsigned char *ColorExpandBase; + int ColorExpandRange; + + +/* Scanline color expansion */ + + void (*SetupForScanlineCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int ScanlineCPUToScreenColorExpandFillFlags; + + void (*SubsequentScanlineCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + void (*SubsequentColorExpandScanline)( + ScrnInfoPtr pScrn, + int bufno + ); + + int NumScanlineColorExpandBuffers; + unsigned char **ScanlineColorExpandBuffers; + +/* Screen to screen color expansion */ + + void (*SetupForScreenToScreenColorExpandFill) ( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int ScreenToScreenColorExpandFillFlags; + + void (*SubsequentScreenToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int srcx, int srcy, int skipleft + ); + + +/* Image transfers */ + + void (*SetupForImageWrite)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int ImageWriteFlags; + + void (*SubsequentImageWriteRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + unsigned char *ImageWriteBase; + int ImageWriteRange; + +/* Scanline Image transfers */ + + void (*SetupForScanlineImageWrite)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int ScanlineImageWriteFlags; + + void (*SubsequentScanlineImageWriteRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + void (*SubsequentImageWriteScanline) ( + ScrnInfoPtr pScrn, + int bufno + ); + + int NumScanlineImageWriteBuffers; + unsigned char **ScanlineImageWriteBuffers; + + /* Image Reads - OBSOLETE AND NOT USED */ + + void (*SetupForImageRead) ( + ScrnInfoPtr pScrn, + int bpp, int depth + ); + int ImageReadFlags; + + unsigned char *ImageReadBase; + int ImageReadRange; + + void (*SubsequentImageReadRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h + ); + + + /***************** Mid Level *****************/ + void (*ScreenToScreenBitBlt)( + ScrnInfoPtr pScrn, + int nbox, + DDXPointPtr pptSrc, + BoxPtr pbox, + int xdir, int ydir, + int alu, + unsigned int planmask + ); + int ScreenToScreenBitBltFlags; + + void (*WriteBitmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask + ); + int WriteBitmapFlags; + + void (*FillSolidRects)( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox + ); + int FillSolidRectsFlags; + + void (*FillMono8x8PatternRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg + ); + int FillMono8x8PatternRectsFlags; + + void (*FillColor8x8PatternRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache + ); + int FillColor8x8PatternRectsFlags; + + void (*FillCacheBltRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache + ); + int FillCacheBltRectsFlags; + + void (*FillColorExpandRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillColorExpandRectsFlags; + + void (*FillCacheExpandRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillCacheExpandRectsFlags; + + void (*FillImageWriteRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillImageWriteRectsFlags; + + + void (*FillSolidSpans)( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted + ); + int FillSolidSpansFlags; + + void (*FillMono8x8PatternSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + int pat0, int pat1, + int xorg, int yorg + ); + int FillMono8x8PatternSpansFlags; + + void (*FillColor8x8PatternSpans)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg + ); + int FillColor8x8PatternSpansFlags; + + void (*FillCacheBltSpans)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg + ); + int FillCacheBltSpansFlags; + + void (*FillColorExpandSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillColorExpandSpansFlags; + + void (*FillCacheExpandSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillCacheExpandSpansFlags; + + void (*TEGlyphRenderer)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask + ); + int TEGlyphRendererFlags; + + void (*NonTEGlyphRenderer)( + ScrnInfoPtr pScrn, + int x, int y, int n, + NonTEGlyphPtr glyphs, + BoxPtr pbox, + int fg, int rop, + unsigned int planemask + ); + int NonTEGlyphRendererFlags; + + void (*WritePixmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int WritePixmapFlags; + + void (*ReadPixmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *dst, + int dstwidth, + int bpp, int depth + ); + int ReadPixmapFlags; + + /***************** GC Level *****************/ + RegionPtr (*CopyArea)( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty + ); + int CopyAreaFlags; + + RegionPtr (*CopyPlane)( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty, + unsigned long bitPlane + ); + int CopyPlaneFlags; + + void (*PushPixelsSolid) ( + GCPtr pGC, + PixmapPtr pBitMap, + DrawablePtr pDrawable, + int dx, int dy, + int xOrg, int yOrg + ); + int PushPixelsFlags; + + /** PolyFillRect **/ + + void (*PolyFillRectSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectSolidFlags; + + void (*PolyFillRectStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectStippledFlags; + + void (*PolyFillRectOpaqueStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectOpaqueStippledFlags; + + void (*PolyFillRectTiled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectTiledFlags; + + /** FillSpans **/ + + void (*FillSpansSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansSolidFlags; + + void (*FillSpansStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansStippledFlags; + + void (*FillSpansOpaqueStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansOpaqueStippledFlags; + + void (*FillSpansTiled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansTiledFlags; + + int (*PolyText8TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int PolyText8TEFlags; + + int (*PolyText16TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int PolyText16TEFlags; + + void (*ImageText8TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int ImageText8TEFlags; + + void (*ImageText16TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int ImageText16TEFlags; + + void (*ImageGlyphBltTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int ImageGlyphBltTEFlags; + + void (*PolyGlyphBltTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int PolyGlyphBltTEFlags; + + int (*PolyText8NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int PolyText8NonTEFlags; + + int (*PolyText16NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int PolyText16NonTEFlags; + + void (*ImageText8NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int ImageText8NonTEFlags; + + void (*ImageText16NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int ImageText16NonTEFlags; + + void (*ImageGlyphBltNonTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int ImageGlyphBltNonTEFlags; + + void (*PolyGlyphBltNonTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int PolyGlyphBltNonTEFlags; + + void (*PolyRectangleThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int nRectsInit, + xRectangle *pRectsInit + ); + int PolyRectangleThinSolidFlags; + + void (*PolylinesWideSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesWideSolidFlags; + + void (*PolylinesThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesThinSolidFlags; + + void (*PolySegmentThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + ); + int PolySegmentThinSolidFlags; + + void (*PolylinesThinDashed)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesThinDashedFlags; + + void (*PolySegmentThinDashed)( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + ); + int PolySegmentThinDashedFlags; + + void (*FillPolygonSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonSolidFlags; + + void (*FillPolygonStippled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonStippledFlags; + + void (*FillPolygonOpaqueStippled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonOpaqueStippledFlags; + + void (*FillPolygonTiled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonTiledFlags; + + void (*PolyFillArcSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int narcs, + xArc *parcs + ); + int PolyFillArcSolidFlags; + + void (*PutImage)( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage + ); + int PutImageFlags; + + /* Validation masks */ + + unsigned long FillSpansMask; + ValidateGCProcPtr ValidateFillSpans; + unsigned long SetSpansMask; + ValidateGCProcPtr ValidateSetSpans; + unsigned long PutImageMask; + ValidateGCProcPtr ValidatePutImage; + unsigned long CopyAreaMask; + ValidateGCProcPtr ValidateCopyArea; + unsigned long CopyPlaneMask; + ValidateGCProcPtr ValidateCopyPlane; + unsigned long PolyPointMask; + ValidateGCProcPtr ValidatePolyPoint; + unsigned long PolylinesMask; + ValidateGCProcPtr ValidatePolylines; + unsigned long PolySegmentMask; + ValidateGCProcPtr ValidatePolySegment; + unsigned long PolyRectangleMask; + ValidateGCProcPtr ValidatePolyRectangle; + unsigned long PolyArcMask; + ValidateGCProcPtr ValidatePolyArc; + unsigned long FillPolygonMask; + ValidateGCProcPtr ValidateFillPolygon; + unsigned long PolyFillRectMask; + ValidateGCProcPtr ValidatePolyFillRect; + unsigned long PolyFillArcMask; + ValidateGCProcPtr ValidatePolyFillArc; + unsigned long PolyText8Mask; + ValidateGCProcPtr ValidatePolyText8; + unsigned long PolyText16Mask; + ValidateGCProcPtr ValidatePolyText16; + unsigned long ImageText8Mask; + ValidateGCProcPtr ValidateImageText8; + unsigned long ImageText16Mask; + ValidateGCProcPtr ValidateImageText16; + unsigned long PolyGlyphBltMask; + ValidateGCProcPtr ValidatePolyGlyphBlt; + unsigned long ImageGlyphBltMask; + ValidateGCProcPtr ValidateImageGlyphBlt; + unsigned long PushPixelsMask; + ValidateGCProcPtr ValidatePushPixels; + + void (*ComputeDash)(GCPtr pGC); + + /* Pixmap Cache */ + + int PixmapCacheFlags; + Bool UsingPixmapCache; + Bool CanDoMono8x8; + Bool CanDoColor8x8; + + void (*InitPixmapCache)( + ScreenPtr pScreen, + RegionPtr areas, + pointer data + ); + void (*ClosePixmapCache)( + ScreenPtr pScreen + ); + + int (*StippledFillChooser)(GCPtr pGC); + int (*OpaqueStippledFillChooser)(GCPtr pGC); + int (*TiledFillChooser)(GCPtr pGC); + + int CachePixelGranularity; + int MaxCacheableTileWidth; + int MaxCacheableTileHeight; + int MaxCacheableStippleWidth; + int MaxCacheableStippleHeight; + + XAACacheInfoPtr (*CacheTile)( + ScrnInfoPtr Scrn, PixmapPtr pPix + ); + XAACacheInfoPtr (*CacheStipple)( + ScrnInfoPtr Scrn, PixmapPtr pPix, + int fg, int bg + ); + XAACacheInfoPtr (*CacheMonoStipple)( + ScrnInfoPtr Scrn, PixmapPtr pPix + ); + XAACacheInfoPtr (*CacheMono8x8Pattern)( + ScrnInfoPtr Scrn, int pat0, int pat1 + ); + XAACacheInfoPtr (*CacheColor8x8Pattern)( + ScrnInfoPtr Scrn, PixmapPtr pPix, + int fg, int bg + ); + + + int MonoPatternPitch; + int CacheWidthMono8x8Pattern; + int CacheHeightMono8x8Pattern; + + int ColorPatternPitch; + int CacheWidthColor8x8Pattern; + int CacheHeightColor8x8Pattern; + + int CacheColorExpandDensity; + + void (*WriteBitmapToCache) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg + ); + void (*WritePixmapToCache) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth + ); + void (*WriteMono8x8PatternToCache)( + ScrnInfoPtr pScrn, + XAACacheInfoPtr pCache + ); + void (*WriteColor8x8PatternToCache)( + ScrnInfoPtr pScrn, + PixmapPtr pPix, + XAACacheInfoPtr pCache + ); + + char* PixmapCachePrivate; + + /* Miscellaneous */ + + GC ScratchGC; + int PreAllocSize; + unsigned char *PreAllocMem; + + CharInfoPtr CharInfo[255]; + NonTEGlyphInfo GlyphInfo[255]; + + unsigned int FullPlanemask; /* deprecated */ + + PixmapLinkPtr OffscreenPixmaps; + int maxOffPixWidth; + int maxOffPixHeight; + + XAACacheInfoRec ScratchCacheInfoRec; + + BoxPtr ClipBox; + + Bool NeedToSync; + + char *dgaSaves; + + /* These can be supplied to override the defaults */ + + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + BackingStoreSaveAreasProcPtr SaveAreas; + BackingStoreRestoreAreasProcPtr RestoreAreas; + + unsigned int offscreenDepths; + Bool offscreenDepthsInitialized; + + CARD32 FullPlanemasks[32]; + +#ifdef RENDER + Bool (*Composite) ( + CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height + ); + + Bool (*Glyphs) ( + CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs + ); + + /* The old SetupForCPUToScreenAlphaTexture function is no longer used because + * it doesn't pass in enough information to write a conforming + * implementation. See SetupForCPUToScreenAlphaTexture2. + */ + Bool (*SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags + ); + void (*SubsequentCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height + ); + int CPUToScreenAlphaTextureFlags; + CARD32 * CPUToScreenAlphaTextureFormats; + + /* The old SetupForCPUToScreenTexture function is no longer used because + * it doesn't pass in enough information to write a conforming + * implementation. See SetupForCPUToScreenTexture2. + */ + Bool (*SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texType, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags + ); + void (*SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height + ); + int CPUToScreenTextureFlags; + CARD32 * CPUToScreenTextureFormats; + + +#endif + + /* these were added for 4.3.0 */ + BoxRec SolidLineLimits; + BoxRec DashedLineLimits; + +#ifdef RENDER + /* These were added for X.Org 6.8.0 */ + Bool (*SetupForCPUToScreenAlphaTexture2) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + CARD32 maskFormat, + CARD32 dstFormat, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags + ); + CARD32 *CPUToScreenAlphaTextureDstFormats; + + Bool (*SetupForCPUToScreenTexture2) ( + ScrnInfoPtr pScrn, + int op, + CARD32 srcFormat, + CARD32 dstFormat, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags + ); + CARD32 *CPUToScreenTextureDstFormats; +#endif /* RENDER */ +} XAAInfoRec, *XAAInfoRecPtr; + +#define SET_SYNC_FLAG(infoRec) (infoRec)->NeedToSync = TRUE + + +Bool +XAAInit( + ScreenPtr pScreen, + XAAInfoRecPtr infoRec +); + +XAAInfoRecPtr XAACreateInfoRec(void); + +void +XAADestroyInfoRec( + XAAInfoRecPtr infoRec +); + +typedef void (*DepthChangeFuncPtr) (ScrnInfoPtr pScrn, int depth); + +Bool +XAAInitDualFramebufferOverlay( + ScreenPtr pScreen, + DepthChangeFuncPtr callback +); + +#endif /* _XAA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaaWrapper.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaaWrapper.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaaWrapper.h (revision 51223) @@ -0,0 +1,10 @@ + +#ifndef _XAA_WRAPPER_H +# define _XAA_WRAPPER_H + +typedef void (*SyncFunc)(ScreenPtr); + +Bool xaaSetupWrapper(ScreenPtr pScreen, + XAAInfoRecPtr infoPtr, int depth, SyncFunc *func); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaacexp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaacexp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaacexp.h (revision 51223) @@ -0,0 +1,128 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaacexp.h,v 1.3 2000/01/21 02:30:06 dawes Exp $ */ + + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include + +#ifndef FIXEDBASE +#define CHECKRETURN(b) if(width <= ((b) * 32)) return(base + (b)) +#else +#define CHECKRETURN(b) if(width <= ((b) * 32)) return(base) +#endif + +#if X_BYTE_ORDER == X_BIG_ENDIAN +# define SHIFT_L(value, shift) ((value) >> (shift)) +# define SHIFT_R(value, shift) ((value) << (shift)) +#else +# define SHIFT_L(value, shift) ((value) << (shift)) +# define SHIFT_R(value, shift) ((value) >> (shift)) +#endif + +#ifndef MSBFIRST +# ifdef FIXEDBASE +# define WRITE_IN_BITORDER(dest, offset, data) *(dest) = data; +# else +# define WRITE_IN_BITORDER(dest, offset, data) *(dest + offset) = data; +# endif +#else +# ifdef FIXEDBASE +# define WRITE_IN_BITORDER(dest, offset, data) *(dest) = SWAP_BITS_IN_BYTES(data); +# else +# define WRITE_IN_BITORDER(dest, offset, data) *(dest + offset) = SWAP_BITS_IN_BYTES(data) +# endif +#endif + +#ifdef FIXEDBASE +# ifdef MSBFIRST +# define WRITE_BITS(b) *base = SWAP_BITS_IN_BYTES(b) +# define WRITE_BITS1(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; } +# define WRITE_BITS3(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *base = byte_reversed_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_reversed_expand3[((b) & 0xFF000000) >> 24] << 8; } +# else +# define WRITE_BITS(b) *base = (b) +# define WRITE_BITS1(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; } +# define WRITE_BITS3(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *base = byte_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_expand3[((b) & 0xFF000000) >> 24] << 8; } +# endif +#else +# ifdef MSBFIRST +# define WRITE_BITS(b) *(base++) = SWAP_BITS_IN_BYTES(b) +# define WRITE_BITS1(b) { \ + *(base++) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *(base) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + base += 2; } +# define WRITE_BITS3(b) { \ + *(base) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *(base + 2) = byte_reversed_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_reversed_expand3[((b) & 0xFF000000) >> 24] << 8; \ + base += 3; } +# else +# define WRITE_BITS(b) *(base++) = (b) +# define WRITE_BITS1(b) { \ + *(base++) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *(base) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + base += 2; } +# define WRITE_BITS3(b) { \ + *(base) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *(base + 2) = byte_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_expand3[((b) & 0xFF000000) >> 24] << 8; \ + base += 3; } +# endif +#endif + +#ifdef FIXEDBASE +# ifdef MSBFIRST +# define EXPNAME(x) x##MSBFirstFixedBase +# else +# define EXPNAME(x) x##LSBFirstFixedBase +# endif +#else +# ifdef MSBFIRST +# define EXPNAME(x) x##MSBFirst +# else +# define EXPNAME(x) x##LSBFirst +# endif +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaalocal.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaalocal.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaalocal.h (revision 51223) @@ -0,0 +1,1773 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaalocal.h,v 1.36tsi Exp $ */ + +#ifndef _XAALOCAL_H +#define _XAALOCAL_H + +/* This file is very unorganized ! */ + + +#include "gcstruct.h" +#include "regionstr.h" +#include "xf86fbman.h" +#include "xaa.h" +#include "mi.h" +#ifdef RENDER +#include "picturestr.h" +#endif + +#define GCWhenForced (GCArcMode << 1) + +#define DO_COLOR_8x8 0x00000001 +#define DO_MONO_8x8 0x00000002 +#define DO_CACHE_BLT 0x00000003 +#define DO_COLOR_EXPAND 0x00000004 +#define DO_CACHE_EXPAND 0x00000005 +#define DO_IMAGE_WRITE 0x00000006 +#define DO_PIXMAP_COPY 0x00000007 +#define DO_SOLID 0x00000008 + + +typedef CARD32 * (*GlyphScanlineFuncPtr)( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +typedef CARD32 *(*StippleScanlineProcPtr)(CARD32*, CARD32*, int, int, int); + +typedef void (*RectFuncPtr) (ScrnInfoPtr, int, int, int, int, int, int, + XAACacheInfoPtr); +typedef void (*TrapFuncPtr) (ScrnInfoPtr, int, int, int, int, int, int, + int, int, int, int, int, int, + XAACacheInfoPtr); + + + +typedef struct _XAAScreen { + CreateGCProcPtr CreateGC; + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + WindowExposuresProcPtr WindowExposures; + BSFuncRec BackingStoreFuncs; + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + XAAInfoRecPtr AccelInfoRec; + Bool (*EnterVT)(int, int); + void (*LeaveVT)(int, int); + int (*SetDGAMode)(int, int, DGADevicePtr); + void (*EnableDisableFBAccess)(int, Bool); +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif +} XAAScreenRec, *XAAScreenPtr; + +#define OPS_ARE_PIXMAP 0x00000001 +#define OPS_ARE_ACCEL 0x00000002 + +typedef struct _XAAGC { + GCOps *wrapOps; + GCFuncs *wrapFuncs; + GCOps *XAAOps; + int DashLength; + unsigned char* DashPattern; + unsigned long changes; + unsigned long flags; +} XAAGCRec, *XAAGCPtr; + +#define REDUCIBILITY_CHECKED 0x00000001 +#define REDUCIBLE_TO_8x8 0x00000002 +#define REDUCIBLE_TO_2_COLOR 0x00000004 +#define DIRTY 0x00010000 +#define OFFSCREEN 0x00020000 +#define DGA_PIXMAP 0x00040000 +#define SHARED_PIXMAP 0x00080000 +#define LOCKED_PIXMAP 0x00100000 + +#define REDUCIBILITY_MASK \ + (REDUCIBILITY_CHECKED | REDUCIBLE_TO_8x8 | REDUCIBLE_TO_2_COLOR) + +typedef struct _XAAPixmap { + unsigned long flags; + CARD32 pattern0; + CARD32 pattern1; + int fg; + int bg; + FBAreaPtr offscreenArea; + Bool freeData; +} XAAPixmapRec, *XAAPixmapPtr; + + +Bool +XAACreateGC( + GCPtr pGC +); + +Bool +XAAInitAccel( + ScreenPtr pScreen, + XAAInfoRecPtr infoRec +); + +RegionPtr +XAABitBlt( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + void (*doBitBlt)(DrawablePtr, DrawablePtr, GCPtr, RegionPtr, DDXPointPtr), + unsigned long bitPlane +); + +void +XAAScreenToScreenBitBlt( + ScrnInfoPtr pScrn, + int nbox, + DDXPointPtr pptSrc, + BoxPtr pbox, + int xdir, + int ydir, + int alu, + unsigned int planemask +); + +void +XAADoBitBlt( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAADoImageWrite( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAADoImageRead( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAACopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + + +RegionPtr +XAACopyArea( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty +); + +void +XAAValidateCopyArea( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePutImage( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateCopyPlane( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePushPixels( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateFillSpans( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePolyGlyphBlt( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateImageGlyphBlt( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePolylines( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + + +RegionPtr +XAACopyPlaneColorExpansion( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + unsigned long bitPlane +); + + +void +XAAPushPixelsSolidColorExpansion( + GCPtr pGC, + PixmapPtr pBitMap, + DrawablePtr pDrawable, + int dx, + int dy, + int xOrg, + int yOrg +); + +void +XAAWriteBitmapColorExpandMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + + +void +XAAWriteBitmapScanlineColorExpandMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWritePixmap ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth +); + +void +XAAWritePixmapScanline ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth +); + +typedef void (*ClipAndRenderRectsFunc)(GCPtr, int, BoxPtr, int, int); + + +void +XAAClipAndRenderRects( + GCPtr pGC, + ClipAndRenderRectsFunc func, + int nrectFill, + xRectangle *prectInit, + int xorg, int yorg +); + + +typedef void (*ClipAndRenderSpansFunc)(GCPtr, int, DDXPointPtr, int*, + int, int, int); + +void +XAAClipAndRenderSpans( + GCPtr pGC, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted, + ClipAndRenderSpansFunc func, + int xorg, + int yorg +); + + +void +XAAFillSolidRects( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox +); + +void +XAAFillMono8x8PatternRects( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg +); + +void +XAAFillMono8x8PatternRectsScreenOrigin( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg +); + + +void +XAAFillColor8x8PatternRectsScreenOrigin( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorigin, int yorigin, + XAACacheInfoPtr pCache +); + +void +XAAFillColor8x8PatternRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorigin, int yorigin, + XAACacheInfoPtr pCache +); + +void +XAAFillCacheBltRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache +); + +void +XAAFillCacheExpandRects( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillImageWriteRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAPolyFillRect( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit +); + + +void +XAATEGlyphRendererMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +void +XAATEGlyphRenderer3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +void +XAATEGlyphRendererScanlineMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanline3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanlineLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanline3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +extern CARD32 *(*XAAGlyphScanlineFuncMSBFirstFixedBase[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncMSBFirst[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncLSBFirstFixedBase[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncLSBFirst[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncMSBFirstFixedBase(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncMSBFirst(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncLSBFirstFixedBase(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncLSBFirst(void); + +void +XAAFillColorExpandRectsLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsLSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3LSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsMSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3MSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRectsLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRects3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRectsMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRects3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansLSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3LSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansMSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3MSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpansLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpans3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAPutImage( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage +); + +void +XAAFillScanlineColorExpandSpansMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpans3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + + +extern CARD32 *(*XAAStippleScanlineFuncMSBFirstFixedBase[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncMSBFirst[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncLSBFirstFixedBase[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncLSBFirst[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +StippleScanlineProcPtr *XAAGetStippleScanlineFuncMSBFirstFixedBase(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncMSBFirst(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncLSBFirstFixedBase(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncLSBFirst(void); + +int +XAAPolyText8TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +int +XAAPolyText16TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageText8TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +void +XAAImageText16TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageGlyphBltTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +XAAPolyGlyphBltTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + + +int +XAAPolyText8NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +int +XAAPolyText16NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageText8NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +void +XAAImageText16NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageGlyphBltNonTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +XAAPolyGlyphBltNonTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + + +void XAANonTEGlyphRenderer( + ScrnInfoPtr pScrn, + int x, int y, int n, + NonTEGlyphPtr glyphs, + BoxPtr pbox, + int fg, int rop, + unsigned int planemask +); + +void +XAAFillSolidSpans( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted +); + +void +XAAFillMono8x8PatternSpans( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + int patx, int paty, + int xorg, int yorg +); + +void +XAAFillMono8x8PatternSpansScreenOrigin( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + int patx, int paty, + int xorg, int yorg +); + +void +XAAFillColor8x8PatternSpansScreenOrigin( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + XAACacheInfoPtr, + int xorigin, int yorigin +); + +void +XAAFillColor8x8PatternSpans( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + XAACacheInfoPtr, + int xorigin, int yorigin +); + +void +XAAFillCacheBltSpans( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg +); + +void +XAAFillCacheExpandSpans( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillSpans( + DrawablePtr pDrawable, + GC *pGC, + int nInit, + DDXPointPtr pptInit, + int *pwidth, + int fSorted +); + + +void +XAAInitPixmapCache( + ScreenPtr pScreen, + RegionPtr areas, + pointer data +); + +void +XAAWriteBitmapToCache( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg +); + +void +XAAWriteBitmapToCacheLinear( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg +); + +void +XAAWritePixmapToCache( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth +); + +void +XAAWritePixmapToCacheLinear( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth +); + + +void +XAAPaintWindow( + WindowPtr pWin, + RegionPtr prgn, + int what +); + +void +XAASolidHorVertLineAsRects( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + +void +XAASolidHorVertLineAsTwoPoint( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + +void +XAASolidHorVertLineAsBresenham( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + + +void +XAAPolyRectangleThinSolid( + DrawablePtr pDrawable, + GCPtr pGC, + int nRectsInit, + xRectangle *pRectsInit +); + + +void +XAAPolylinesWideSolid ( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts +); + +void +XAAFillPolygonSolid( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + +void +XAAFillPolygonStippled( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + + +void +XAAFillPolygonTiled( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + + +int +XAAIsEasyPolygon( + DDXPointPtr ptsIn, + int count, + BoxPtr extents, + int origin, + DDXPointPtr *topPoint, + int *topY, int *bottomY, + int shape +); + +void +XAAFillPolygonHelper( + ScrnInfoPtr pScrn, + DDXPointPtr ptsIn, + int count, + DDXPointPtr topPoint, + int y, + int maxy, + int origin, + RectFuncPtr RectFunc, + TrapFuncPtr TrapFunc, + int xorg, + int yorg, + XAACacheInfoPtr pCache +); + +void +XAAPolySegment( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg +); + +void +XAAPolyLines( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit +); + +void +XAAPolySegmentDashed( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg +); + +void +XAAPolyLinesDashed( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit +); + + +void +XAAWriteMono8x8PatternToCache(ScrnInfoPtr pScrn, XAACacheInfoPtr pCache); + +void +XAAWriteColor8x8PatternToCache( + ScrnInfoPtr pScrn, + PixmapPtr pPix, + XAACacheInfoPtr pCache +); + +void +XAARotateMonoPattern( + int *pat0, int *pat1, + int xoffset, int yoffset, + Bool msbfirst +); + +void XAAComputeDash(GCPtr pGC); + +void XAAMoveDWORDS_FixedBase( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +void XAAMoveDWORDS_FixedSrc( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +void XAAMoveDWORDS( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +int +XAAGetRectClipBoxes( + GCPtr pGC, + BoxPtr pboxClippedBase, + int nrectFill, + xRectangle *prectInit +); + +void +XAASetupOverlay8_32Planar(ScreenPtr); + +void +XAAPolyFillArcSolid(DrawablePtr pDraw, GCPtr pGC, int narcs, xArc *parcs); + +XAACacheInfoPtr +XAACacheTile(ScrnInfoPtr Scrn, PixmapPtr pPix); + +XAACacheInfoPtr +XAACacheMonoStipple(ScrnInfoPtr Scrn, PixmapPtr pPix); + +XAACacheInfoPtr +XAACachePlanarMonoStipple(ScrnInfoPtr Scrn, PixmapPtr pPix); + +typedef XAACacheInfoPtr (*XAACachePlanarMonoStippleProc)(ScrnInfoPtr, PixmapPtr); +XAACachePlanarMonoStippleProc XAAGetCachePlanarMonoStipple(void); + +XAACacheInfoPtr +XAACacheStipple(ScrnInfoPtr Scrn, PixmapPtr pPix, int fg, int bg); + +XAACacheInfoPtr +XAACacheMono8x8Pattern(ScrnInfoPtr Scrn, int pat0, int pat1); + +XAACacheInfoPtr +XAACacheColor8x8Pattern(ScrnInfoPtr Scrn, PixmapPtr pPix, int fg, int bg); + +void +XAATileCache(ScrnInfoPtr pScrn, XAACacheInfoPtr pCache, int w, int h); + +void XAAClosePixmapCache(ScreenPtr pScreen); +void XAAInvalidatePixmapCache(ScreenPtr pScreen); + +Bool XAACheckStippleReducibility(PixmapPtr pPixmap); +Bool XAACheckTileReducibility(PixmapPtr pPixmap, Bool checkMono); + +int XAAStippledFillChooser(GCPtr pGC); +int XAAOpaqueStippledFillChooser(GCPtr pGC); +int XAATiledFillChooser(GCPtr pGC); + +void XAAMoveInOffscreenPixmaps(ScreenPtr pScreen); +void XAAMoveOutOffscreenPixmaps(ScreenPtr pScreen); +void XAARemoveAreaCallback(FBAreaPtr area); +void XAAMoveOutOffscreenPixmap(PixmapPtr pPix); +Bool XAAInitStateWrap(ScreenPtr pScreen, XAAInfoRecPtr infoRec); + +#ifdef RENDER +void +XAAComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +Bool +XAADoComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +void +XAAGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +Bool +XAADoGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + + + +/* helpers */ +void +XAA_888_plus_PICT_a8_to_8888 ( + CARD32 color, + CARD8 *alphaPtr, /* in bytes */ + int alphaPitch, + CARD32 *dstPtr, + int dstPitch, /* in dwords */ + int width, + int height +); + +Bool +XAAGetRGBAFromPixel( + CARD32 pixel, + CARD16 *red, + CARD16 *green, + CARD16 *blue, + CARD16 *alpha, + CARD32 format +); + + +Bool +XAAGetPixelFromRGBA ( + CARD32 *pixel, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + CARD32 format +); + +#endif + +/* XXX should be static */ +extern GCOps XAAFallbackOps; +extern GCOps *XAAGetFallbackOps(void); +extern GCFuncs XAAGCFuncs; +extern int XAAScreenIndex; /* XXX DONTUSE */ +extern int XAAGCIndex; /* XXX DONTUSE */ +extern int XAAPixmapIndex; /* XXX DONTUSE */ +extern int XAAGetScreenIndex(void); +extern int XAAGetGCIndex(void); +extern int XAAGetPixmapIndex(void); + +extern unsigned int XAAShiftMasks[32]; + +extern unsigned int byte_expand3[256], byte_reversed_expand3[256]; + +CARD32 XAAReverseBitOrder(CARD32 data); + +#define GET_XAASCREENPTR_FROM_SCREEN(pScreen)\ + (pScreen)->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAASCREENPTR_FROM_GC(pGC)\ + (pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAASCREENPTR_FROM_DRAWABLE(pDraw)\ + (pDraw)->pScreen->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAAINFORECPTR_FROM_SCREEN(pScreen)\ + ((XAAScreenPtr)((pScreen)->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_GC(pGC)\ +((XAAScreenPtr)((pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_DRAWABLE(pDraw)\ +((XAAScreenPtr)((pDraw)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_SCRNINFOPTR(pScrn)\ +((XAAScreenPtr)((pScrn)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define XAA_GET_PIXMAP_PRIVATE(pix)\ + (XAAPixmapPtr)((pix)->devPrivates[XAAGetPixmapIndex()].ptr) + +#define CHECK_RGB_EQUAL(c) (!((((c) >> 8) ^ (c)) & 0xffff)) + +#define CHECK_FG(pGC, flags) \ + (!(flags & RGB_EQUAL) || CHECK_RGB_EQUAL(pGC->fgPixel)) + +#define CHECK_BG(pGC, flags) \ + (!(flags & RGB_EQUAL) || CHECK_RGB_EQUAL(pGC->bgPixel)) + +#define CHECK_ROP(pGC, flags) \ + (!(flags & GXCOPY_ONLY) || (pGC->alu == GXcopy)) + +#define CHECK_ROPSRC(pGC, flags) \ + (!(flags & ROP_NEEDS_SOURCE) || ((pGC->alu != GXclear) && \ + (pGC->alu != GXnoop) && (pGC->alu != GXinvert) && \ + (pGC->alu != GXset))) + +#define CHECK_PLANEMASK(pGC, flags) \ + (!(flags & NO_PLANEMASK) || \ + ((pGC->planemask & infoRec->FullPlanemasks[pGC->depth - 1]) == \ + infoRec->FullPlanemasks[pGC->depth - 1])) + +#define CHECK_COLORS(pGC, flags) \ + (!(flags & RGB_EQUAL) || \ + (CHECK_RGB_EQUAL(pGC->fgPixel) && CHECK_RGB_EQUAL(pGC->bgPixel))) + +#define CHECK_NO_GXCOPY(pGC, flags) \ + ((pGC->alu != GXcopy) || !(flags & NO_GXCOPY) || \ + ((pGC->planemask & infoRec->FullPlanemask) != infoRec->FullPlanemask)) + +#define IS_OFFSCREEN_PIXMAP(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->offscreenArea) + +#define PIXMAP_IS_SHARED(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->flags & SHARED_PIXMAP) + +#define OFFSCREEN_PIXMAP_LOCKED(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->flags & LOCKED_PIXMAP) + +#define XAA_DEPTH_BUG(pGC) \ + ((pGC->depth == 32) && (pGC->bgPixel == 0xffffffff)) + +#define DELIST_OFFSCREEN_PIXMAP(pPix) { \ + PixmapLinkPtr _pLink, _prev; \ + _pLink = infoRec->OffscreenPixmaps; \ + _prev = NULL; \ + while(_pLink) { \ + if(_pLink->pPix == pPix) { \ + if(_prev) _prev->next = _pLink->next; \ + else infoRec->OffscreenPixmaps = _pLink->next; \ + xfree(_pLink); \ + break; \ + } \ + _prev = _pLink; \ + _pLink = _pLink->next; \ + }} + + +#define SWAP_BITS_IN_BYTES(v) \ + (((0x01010101 & (v)) << 7) | ((0x02020202 & (v)) << 5) | \ + ((0x04040404 & (v)) << 3) | ((0x08080808 & (v)) << 1) | \ + ((0x10101010 & (v)) >> 1) | ((0x20202020 & (v)) >> 3) | \ + ((0x40404040 & (v)) >> 5) | ((0x80808080 & (v)) >> 7)) + +/* + * Moved XAAPixmapCachePrivate here from xaaPCache.c, since driver + * replacements for CacheMonoStipple need access to it + */ + +typedef struct { + int Num512x512; + int Current512; + XAACacheInfoPtr Info512; + int Num256x256; + int Current256; + XAACacheInfoPtr Info256; + int Num128x128; + int Current128; + XAACacheInfoPtr Info128; + int NumMono; + int CurrentMono; + XAACacheInfoPtr InfoMono; + int NumColor; + int CurrentColor; + XAACacheInfoPtr InfoColor; + int NumPartial; + int CurrentPartial; + XAACacheInfoPtr InfoPartial; + DDXPointRec MonoOffsets[64]; + DDXPointRec ColorOffsets[64]; +} XAAPixmapCachePrivate, *XAAPixmapCachePrivatePtr; + + +#endif /* _XAALOCAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaarop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaarop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaarop.h (revision 51223) @@ -0,0 +1,313 @@ +/* $XFree86$ */ + +/* + + int XAAHelpSolidROP(ScrnInfoPtr pScrn, int *fg, int pm, int *rop) + + For use with solid fills emulated by solid 8x8 patterns. You + give it the foreground, planemask and X rop and it will replace + the foreground with a new one and the rop with the appropriate + MS triadic raster op. The function will return which components + (S-P) need to be enabled. + + + int XAAHelpPatternROP(ScrnInfoPtr pScrn, int *fg, int *bg, int pm, int *rop) + + For use with 8x8 opaque pattern fills. You give it the foreground, + and background, planemask and X rop and it will replace the + foreground and background with new ones and the rop with the + appropriate MS triadic raster op. The function will return which + components (S-P) need to be enabled. + + + ROP_PAT - Means to enable 8x8 mono patterns (all bits + set for solid patterns). Set the foreground and + background as returned by the function. + + ROP_SRC - Means a source of color == planemask should be used. + + +*/ + +#ifndef _XAAROP_H +#define _XAAROP_H + +#define ROP_DST 0x00000001 +#define ROP_SRC 0x00000002 +#define ROP_PAT 0x00000004 + +#define ROP_0 0x00 +#define ROP_DPSoon 0x01 +#define ROP_DPSona 0x02 +#define ROP_PSon 0x03 +#define ROP_SDPona 0x04 +#define ROP_DPon 0x05 +#define ROP_PDSxnon 0x06 +#define ROP_PDSaon 0x07 +#define ROP_SDPnaa 0x08 +#define ROP_PDSxon 0x09 +#define ROP_DPna 0x0A +#define ROP_PSDnaon 0x0B +#define ROP_SPna 0x0C +#define ROP_PDSnaon 0x0D +#define ROP_PDSonon 0x0E +#define ROP_Pn 0x0F +#define ROP_PDSona 0x10 +#define ROP_DSon 0x11 +#define ROP_SDPxnon 0x12 +#define ROP_SDPaon 0x13 +#define ROP_DPSxnon 0x14 +#define ROP_DPSaon 0x15 +#define ROP_PSDPSanaxx 0x16 +#define ROP_SSPxDSxaxn 0x17 +#define ROP_SPxPDxa 0x18 +#define ROP_SDPSanaxn 0x19 +#define ROP_PDSPaox 0x1A +#define ROP_SDPSxaxn 0x1B +#define ROP_PSDPaox 0x1C +#define ROP_DSPDxaxn 0x1D +#define ROP_PDSox 0x1E +#define ROP_PDSoan 0x1F +#define ROP_DPSnaa 0x20 +#define ROP_SDPxon 0x21 +#define ROP_DSna 0x22 +#define ROP_SPDnaon 0x23 +#define ROP_SPxDSxa 0x24 +#define ROP_PDSPanaxn 0x25 +#define ROP_SDPSaox 0x26 +#define ROP_SDPSxnox 0x27 +#define ROP_DPSxa 0x28 +#define ROP_PSDPSaoxxn 0x29 +#define ROP_DPSana 0x2A +#define ROP_SSPxPDxaxn 0x2B +#define ROP_SPDSoax 0x2C +#define ROP_PSDnox 0x2D +#define ROP_PSDPxox 0x2E +#define ROP_PSDnoan 0x2F +#define ROP_PSna 0x30 +#define ROP_SDPnaon 0x31 +#define ROP_SDPSoox 0x32 +#define ROP_Sn 0x33 +#define ROP_SPDSaox 0x34 +#define ROP_SPDSxnox 0x35 +#define ROP_SDPox 0x36 +#define ROP_SDPoan 0x37 +#define ROP_PSDPoax 0x38 +#define ROP_SPDnox 0x39 +#define ROP_SPDSxox 0x3A +#define ROP_SPDnoan 0x3B +#define ROP_PSx 0x3C +#define ROP_SPDSonox 0x3D +#define ROP_SPDSnaox 0x3E +#define ROP_PSan 0x3F +#define ROP_PSDnaa 0x40 +#define ROP_DPSxon 0x41 +#define ROP_SDxPDxa 0x42 +#define ROP_SPDSanaxn 0x43 +#define ROP_SDna 0x44 +#define ROP_DPSnaon 0x45 +#define ROP_DSPDaox 0x46 +#define ROP_PSDPxaxn 0x47 +#define ROP_SDPxa 0x48 +#define ROP_PDSPDaoxxn 0x49 +#define ROP_DPSDoax 0x4A +#define ROP_PDSnox 0x4B +#define ROP_SDPana 0x4C +#define ROP_SSPxDSxoxn 0x4D +#define ROP_PDSPxox 0x4E +#define ROP_PDSnoan 0x4F +#define ROP_PDna 0x50 +#define ROP_DSPnaon 0x51 +#define ROP_DPSDaox 0x52 +#define ROP_SPDSxaxn 0x53 +#define ROP_DPSonon 0x54 +#define ROP_Dn 0x55 +#define ROP_DPSox 0x56 +#define ROP_DPSoan 0x57 +#define ROP_PDSPoax 0x58 +#define ROP_DPSnox 0x59 +#define ROP_DPx 0x5A +#define ROP_DPSDonox 0x5B +#define ROP_DPSDxox 0x5C +#define ROP_DPSnoan 0x5D +#define ROP_DPSDnaox 0x5E +#define ROP_DPan 0x5F +#define ROP_PDSxa 0x60 +#define ROP_DSPDSaoxxn 0x61 +#define ROP_DSPDoax 0x62 +#define ROP_SDPnox 0x63 +#define ROP_SDPSoax 0x64 +#define ROP_DSPnox 0x65 +#define ROP_DSx 0x66 +#define ROP_SDPSonox 0x67 +#define ROP_DSPDSonoxxn 0x68 +#define ROP_PDSxxn 0x69 +#define ROP_DPSax 0x6A +#define ROP_PSDPSoaxxn 0x6B +#define ROP_SDPax 0x6C +#define ROP_PDSPDoaxxn 0x6D +#define ROP_SDPSnoax 0x6E +#define ROP_PDSxnan 0x6F +#define ROP_PDSana 0x70 +#define ROP_SSDxPDxaxn 0x71 +#define ROP_SDPSxox 0x72 +#define ROP_SDPnoan 0x73 +#define ROP_DSPDxox 0x74 +#define ROP_DSPnoan 0x75 +#define ROP_SDPSnaox 0x76 +#define ROP_DSan 0x77 +#define ROP_PDSax 0x78 +#define ROP_DSPDSoaxxn 0x79 +#define ROP_DPSDnoax 0x7A +#define ROP_SDPxnan 0x7B +#define ROP_SPDSnoax 0x7C +#define ROP_DPSxnan 0x7D +#define ROP_SPxDSxo 0x7E +#define ROP_DPSaan 0x7F +#define ROP_DPSaa 0x80 +#define ROP_SPxDSxon 0x81 +#define ROP_DPSxna 0x82 +#define ROP_SPDSnoaxn 0x83 +#define ROP_SDPxna 0x84 +#define ROP_PDSPnoaxn 0x85 +#define ROP_DSPDSoaxx 0x86 +#define ROP_PDSaxn 0x87 +#define ROP_DSa 0x88 +#define ROP_SDPSnaoxn 0x89 +#define ROP_DSPnoa 0x8A +#define ROP_DSPDxoxn 0x8B +#define ROP_SDPnoa 0x8C +#define ROP_SDPSxoxn 0x8D +#define ROP_SSDxPDxax 0x8E +#define ROP_PDSanan 0x8F +#define ROP_PDSxna 0x90 +#define ROP_SDPSnoaxn 0x91 +#define ROP_DPSDPoaxx 0x92 +#define ROP_SPDaxn 0x93 +#define ROP_PSDPSoaxx 0x94 +#define ROP_DPSaxn 0x95 +#define ROP_DPSxx 0x96 +#define ROP_PSDPSonoxx 0x97 +#define ROP_SDPSonoxn 0x98 +#define ROP_DSxn 0x99 +#define ROP_DPSnax 0x9A +#define ROP_SDPSoaxn 0x9B +#define ROP_SPDnax 0x9C +#define ROP_DSPDoaxn 0x9D +#define ROP_DSPDSaoxx 0x9E +#define ROP_PDSxan 0x9F +#define ROP_DPa 0xA0 +#define ROP_PDSPnaoxn 0xA1 +#define ROP_DPSnoa 0xA2 +#define ROP_DPSDxoxn 0xA3 +#define ROP_PDSPonoxn 0xA4 +#define ROP_PDxn 0xA5 +#define ROP_DSPnax 0xA6 +#define ROP_PDSPoaxn 0xA7 +#define ROP_DPSoa 0xA8 +#define ROP_DPSoxn 0xA9 +#define ROP_D 0xAA +#define ROP_DPSono 0xAB +#define ROP_SPDSxax 0xAC +#define ROP_DPSDaoxn 0xAD +#define ROP_DSPnao 0xAE +#define ROP_DPno 0xAF +#define ROP_PDSnoa 0xB0 +#define ROP_PDSPxoxn 0xB1 +#define ROP_SSPxDSxox 0xB2 +#define ROP_SDPanan 0xB3 +#define ROP_PSDnax 0xB4 +#define ROP_DPSDoaxn 0xB5 +#define ROP_DPSDPaoxx 0xB6 +#define ROP_SDPxan 0xB7 +#define ROP_PSDPxax 0xB8 +#define ROP_DSPDaoxn 0xB9 +#define ROP_DPSnao 0xBA +#define ROP_DSno 0xBB +#define ROP_SPDSanax 0xBC +#define ROP_SDxPDxan 0xBD +#define ROP_DPSxo 0xBE +#define ROP_DPSano 0xBF +#define ROP_Psa 0xC0 +#define ROP_SPDSnaoxn 0xC1 +#define ROP_SPDSonoxn 0xC2 +#define ROP_PSxn 0xC3 +#define ROP_SPDnoa 0xC4 +#define ROP_SPDSxoxn 0xC5 +#define ROP_SDPnax 0xC6 +#define ROP_PSDPoaxn 0xC7 +#define ROP_SDPoa 0xC8 +#define ROP_SPDoxn 0xC9 +#define ROP_DPSDxax 0xCA +#define ROP_SPDSaoxn 0xCB +#define ROP_S 0xCC +#define ROP_SDPono 0xCD +#define ROP_SDPnao 0xCE +#define ROP_SPno 0xCF +#define ROP_PSDnoa 0xD0 +#define ROP_PSDPxoxn 0xD1 +#define ROP_PDSnax 0xD2 +#define ROP_SPDSoaxn 0xD3 +#define ROP_SSPxPDxax 0xD4 +#define ROP_DPSanan 0xD5 +#define ROP_PSDPSaoxx 0xD6 +#define ROP_DPSxan 0xD7 +#define ROP_PDSPxax 0xD8 +#define ROP_SDPSaoxn 0xD9 +#define ROP_DPSDanax 0xDA +#define ROP_SPxDSxan 0xDB +#define ROP_SPDnao 0xDC +#define ROP_SDno 0xDD +#define ROP_SDPxo 0xDE +#define ROP_SDPano 0xDF +#define ROP_PDSoa 0xE0 +#define ROP_PDSoxn 0xE1 +#define ROP_DSPDxax 0xE2 +#define ROP_PSDPaoxn 0xE3 +#define ROP_SDPSxax 0xE4 +#define ROP_PDSPaoxn 0xE5 +#define ROP_SDPSanax 0xE6 +#define ROP_SPxPDxan 0xE7 +#define ROP_SSPxDSxax 0xE8 +#define ROP_DSPDSanaxxn 0xE9 +#define ROP_DPSao 0xEA +#define ROP_DPSxno 0xEB +#define ROP_SDPao 0xEC +#define ROP_SDPxno 0xED +#define ROP_DSo 0xEE +#define ROP_SDPnoo 0xEF +#define ROP_P 0xF0 +#define ROP_PDSono 0xF1 +#define ROP_PDSnao 0xF2 +#define ROP_PSno 0xF3 +#define ROP_PSDnao 0xF4 +#define ROP_PDno 0xF5 +#define ROP_PDSxo 0xF6 +#define ROP_PDSano 0xF7 +#define ROP_PDSao 0xF8 +#define ROP_PDSxno 0xF9 +#define ROP_DPo 0xFA +#define ROP_DPSnoo 0xFB +#define ROP_PSo 0xFC +#define ROP_PSDnoo 0xFD +#define ROP_DPSoo 0xFE +#define ROP_1 0xFF + +#define NO_SRC_ROP(rop) \ + ((rop == GXnoop) || (rop == GXset) || (rop == GXclear) || (rop == GXinvert)) + +int XAAHelpSolidROP(ScrnInfoPtr pScrn, int *fg, int pm, int *rop); +int XAAHelpPatternROP(ScrnInfoPtr pScrn, int *fg, int *bg, int pm, int *rop); + +/* XXX These four should be static, but it breaks the 6.7.0 ABI. */ +extern int XAACopyROP[16]; +extern int XAACopyROP_PM[16]; +extern int XAAPatternROP[16]; +extern int XAAPatternROP_PM[16]; + +extern int XAAGetCopyROP(int i); +extern int XAAGetCopyROP_PM(int i); +extern int XAAGetPatternROP(int i); +extern int XAAGetPatternROP_PM(int i); + +#endif /* _XAAROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaawrap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaawrap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xaawrap.h (revision 51223) @@ -0,0 +1,82 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaawrap.h,v 1.3 1998/10/25 07:12:14 dawes Exp $ */ + +#define XAA_SCREEN_PROLOGUE(pScreen, field)\ + ((pScreen)->field = \ + ((XAAScreenPtr) (pScreen)->devPrivates[XAAGetScreenIndex()].ptr)->field) + +#define XAA_SCREEN_EPILOGUE(pScreen, field, wrapper)\ + ((pScreen)->field = wrapper) + + +#define XAA_GC_FUNC_PROLOGUE(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr) (pGC)->devPrivates[XAAGetGCIndex()].ptr;\ + (pGC)->funcs = pGCPriv->wrapFuncs;\ + if(pGCPriv->flags)\ + (pGC)->ops = pGCPriv->wrapOps + +#define XAA_GC_FUNC_EPILOGUE(pGC)\ + pGCPriv->wrapFuncs = (pGC)->funcs;\ + (pGC)->funcs = &XAAGCFuncs;\ + if(pGCPriv->flags) {\ + pGCPriv->wrapOps = (pGC)->ops;\ + (pGC)->ops = (pGCPriv->flags & OPS_ARE_ACCEL) ? pGCPriv->XAAOps :\ + &XAAPixmapOps;\ + } + + +#define XAA_GC_OP_PROLOGUE(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + GCFuncs *oldFuncs = pGC->funcs;\ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + +#define XAA_GC_OP_PROLOGUE_WITH_RETURN(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + GCFuncs *oldFuncs = pGC->funcs;\ + if(!REGION_NUM_RECTS(pGC->pCompositeClip)) return; \ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + + +#define XAA_GC_OP_EPILOGUE(pGC)\ + pGCPriv->wrapOps = pGC->ops;\ + pGC->funcs = oldFuncs;\ + pGC->ops = pGCPriv->XAAOps + + +#define XAA_PIXMAP_OP_PROLOGUE(pGC, pDraw)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + XAAPixmapPtr pixPriv = XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pDraw));\ + GCFuncs *oldFuncs = pGC->funcs;\ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + + +#define XAA_PIXMAP_OP_EPILOGUE(pGC)\ + pGCPriv->wrapOps = pGC->ops;\ + pGC->funcs = oldFuncs;\ + pGC->ops = &XAAPixmapOps;\ + pixPriv->flags |= DIRTY + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifdef RENDER +#define XAA_RENDER_PROLOGUE(pScreen,field)\ + (GetPictureScreen(pScreen)->field = \ + ((XAAScreenPtr) (pScreen)->devPrivates[XAAGetScreenIndex()].ptr)->field) + +#define XAA_RENDER_EPILOGUE(pScreen, field, wrapper)\ + (GetPictureScreen(pScreen)->field = wrapper) +#endif + +/* This also works fine for drawables */ + +#define SYNC_CHECK(pGC) {\ + XAAInfoRecPtr infoRec =\ +((XAAScreenPtr)((pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec;\ + if(infoRec->NeedToSync) {\ + (*infoRec->Sync)(infoRec->pScrn);\ + infoRec->NeedToSync = FALSE;\ + }} Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf1bpp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf1bpp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf1bpp.h (revision 51223) @@ -0,0 +1,37 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/xf1bpp.h,v 1.2 1998/07/25 16:59:25 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef __XF1BPP_H__ +#define __XF1BPP_H__ + +#define MFB_PROTOTYPES_ONLY +#include "mfbmap.h" +#include "mfb.h" +#include "mfbunmap.h" +#undef MFB_PROTOTYPES_ONLY + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf4bpp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf4bpp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf4bpp.h (revision 51223) @@ -0,0 +1,653 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/xf4bpp.h,v 1.9 2003/11/03 05:11:57 tsi Exp $ */ + +#ifndef __XF4BPP_H__ +#define __XF4BPP_H__ + + +#include "windowstr.h" +#include "gcstruct.h" +#include "colormapst.h" +#include +#ifndef PixelType +#define PixelType CARD32 +#endif + +/* ppcArea.c */ +void xf4bppFillArea( + WindowPtr, + int, + BoxPtr, + GCPtr +); + +/* ppcBStore.c */ +void xf4bppSaveAreas( + PixmapPtr, + RegionPtr, + int, + int, + WindowPtr +); +void xf4bppRestoreAreas( + PixmapPtr, + RegionPtr, + int, + int, + WindowPtr +); + +/* ppcClip.c */ +void xf4bppDestroyClip( + GCPtr +); +void xf4bppChangeClip( + GCPtr, + int, + pointer, + int +); +void xf4bppCopyClip( + GCPtr, + GCPtr +); + +/* ppcCpArea.c */ +RegionPtr xf4bppCopyArea( + DrawablePtr, + DrawablePtr, + GCPtr, + int, + int, + int, + int, + int, + int +); + +/* ppcDepth.c */ +Bool xf4bppDepthOK( + DrawablePtr, + int +); + +/* ppcFillRct.c */ +void xf4bppPolyFillRect( + DrawablePtr, + GCPtr, + int, + xRectangle * +); + +/* ppcWindowFS.c */ +void xf4bppSolidWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppStippleWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppOpStippleWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppTileWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); + +/* xf4bppPixmapFS.c */ +void xf4bppSolidPixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppStipplePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppOpStipplePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppTilePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); + +/* ppcGC.c */ +Bool xf4bppCreateGC( + GCPtr +); +void xf4bppDestroyGC( + GC * +); +void xf4bppValidateGC( + GCPtr, + unsigned long, + DrawablePtr +); + +/* ppcGetSp.c */ +void xf4bppGetSpans( + DrawablePtr, + int, + DDXPointPtr, + int *, + int, + char * +); + +/* ppcImg.c */ +void xf4bppGetImage( + DrawablePtr, + int, + int, + int, + int, + unsigned int, + unsigned long, + char * +); + +/* ppcLine.c */ +void xf4bppScrnZeroLine( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppScrnZeroDash( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppScrnZeroSegs( + DrawablePtr, + GCPtr, + int, + xSegment * +); + +/* ppcPixmap.c */ +PixmapPtr xf4bppCreatePixmap( + ScreenPtr, + int, + int, + int +); +PixmapPtr xf4bppCopyPixmap( + PixmapPtr +); + +/* ppcPntWin.c */ +void xf4bppPaintWindow( + WindowPtr, + RegionPtr, + int +); + +/* ppcPolyPnt.c */ +void xf4bppPolyPoint( + DrawablePtr, + GCPtr, + int, + int, + xPoint * +); + +/* ppcPolyRec.c */ +void xf4bppPolyRectangle( + DrawablePtr, + GCPtr, + int, + xRectangle * +); + +/* ppcQuery.c */ +void xf4bppQueryBestSize( + int, + unsigned short *, + unsigned short *, + ScreenPtr +); + +/* ppcRslvC.c */ +void xf4bppResolveColor( + unsigned short *, + unsigned short *, + unsigned short *, + VisualPtr +); +Bool xf4bppInitializeColormap( + ColormapPtr +); + +/* ppcSetSp.c */ +void xf4bppSetSpans( + DrawablePtr, + GCPtr, + char *, + DDXPointPtr, + int *, + int, + int +); + +/* ppcWindow.c */ +void xf4bppCopyWindow( + WindowPtr, + DDXPointRec, + RegionPtr +); +Bool xf4bppPositionWindow( + WindowPtr, + int, + int +); +Bool xf4bppUnrealizeWindow( + WindowPtr, + int, + int +); +Bool xf4bppDestroyWindow( + WindowPtr +); +Bool xf4bppCreateWindowForXYhardware( + WindowPtr +); + +/* emulOpStip.c */ +void xf4bppOpaqueStipple( + WindowPtr, + PixmapPtr, + unsigned long int, + unsigned long int, + int, + unsigned long int, + int, + int, + int, + int, + int, + int +); + +/* emulRepAre.c */ +void xf4bppReplicateArea( + WindowPtr, + int, + int, + int, + int, + int, + int, + int +); + +/* emulTile.c */ +void xf4bppTileRect( + WindowPtr, + PixmapPtr, + const int, + const unsigned long int, + int, + int, + int, + int, + int, + int +); + +/* vgaGC.c */ +Mask xf4bppChangeWindowGC( + GCPtr, + Mask +); + +/* vgaBitBlt.c */ +void xf4bppBitBlt( + WindowPtr, + int, + int, + int, + int, + int, + int, + int, + int +); + +/* vgaImages.c */ +void xf4bppDrawColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int, + const int, + const unsigned long int +); +void xf4bppReadColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int +); + +/* vgaLine.c */ +void xf4bppHorzLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int +); +void xf4bppVertLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int +); +void xf4bppBresLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int, + int, + int, + int, + int, + int, + unsigned long int +); + +/* vgaStipple.c */ +void xf4bppFillStipple( + WindowPtr, + const PixmapPtr, + unsigned long int, + const int, + unsigned long int, + int, + int, + int, + int, + const int, + const int +); + +/* vgaSolid.c */ +void xf4bppFillSolid( + WindowPtr, + unsigned long int, + const int, + unsigned long int, + int, + const int, + int, + const int +); + +/* offscreen.c */ +void xf4bppOffBitBlt( + WindowPtr, + const int, + const int, + int, + int, + int, + int, + int, + int +); +void xf4bppOffDrawColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int, + const int, + const unsigned long int +); +void xf4bppOffReadColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int +); +void xf4bppOffFillSolid( + WindowPtr, + unsigned long int, + const int, + unsigned long int, + int, + const int, + int, + const int +); +void xf4bppOffDrawMonoImage( + WindowPtr, + unsigned char *, + int, + int, + int, + int, + unsigned long int, + int, + unsigned long int +); +void xf4bppOffFillStipple( + WindowPtr, + const PixmapPtr, + unsigned long int, + const int, + unsigned long int, + int, + int, + int, + int, + const int, + const int +); + +/* mfbimggblt.c */ +void xf4bppImageGlyphBlt( + DrawablePtr, + GCPtr, + int, + int, + unsigned int, + CharInfoPtr *, + pointer +); + +/* wm3.c */ +int wm3_set_regs( + GC * +); + +/* ppcIO.c */ +void xf4bppNeverCalled( + void +); +Bool xf4bppScreenInit( + ScreenPtr, + pointer, + int, + int, + int, + int, + int +); + +/* mfbfillarc.c */ +void xf4bppPolyFillArc( + DrawablePtr, + GCPtr, + int, + xArc * +); + +/* mfbzerarc.c */ +void xf4bppZeroPolyArc( + DrawablePtr, + GCPtr, + int, + xArc * +); + +/* mfbline.c */ +void xf4bppSegmentSS ( + DrawablePtr, + GCPtr, + int, + xSegment * +); +void xf4bppLineSS ( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppSegmentSD ( + DrawablePtr, + GCPtr, + int, + xSegment * +); +void xf4bppLineSD ( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); + +/* mfbbres.c */ +void xf4bppBresS( + PixelType *, + int, + int, + int, + int, + int, + int, + int, + int, + int, + int +); + +/* mfbbresd.c */ +void xf4bppBresD( + DrawablePtr, + int, int, + int *, + unsigned char *, + int, + int *, + int, + PixelType *, + int, int, int, int, int, int, + int, int, + int, int +); + +/* mfbhrzvert.c */ +void xf4bppHorzS( + PixelType *, + int, + int, + int, + int +); +void xf4bppVertS( + PixelType *, + int, + int, + int, + int +); + +#ifdef PC98_EGC + +/* egc_asm.s */ +unsigned char getbits_x( + int, + unsigned int, + pointer, + unsigned int +); +void wcopyr( + pointer, + pointer, + int, + pointer +); +void wcopyl( + pointer, + pointer, + int, + pointer +); +unsigned long int read8Z( + pointer +); + +#endif /* PC98_EGC */ + +#endif /* __XF4BPP_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86.h (revision 51223) @@ -0,0 +1,447 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86.h,v 3.173 2004/01/27 01:31:44 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains declarations for public XFree86 functions and variables, + * and definitions of public macros. + * + * "public" means available to video drivers. + */ + +#ifndef _XF86_H +#define _XF86_H + +#include "xf86str.h" +#include "xf86Opt.h" +#include +#ifndef IN_MODULE +#include +#else +#include "xf86_ansic.h" +#endif +#ifdef RANDR +#include +#endif + +#include "propertyst.h" + +/* General parameters */ +extern int xf86DoConfigure; +extern Bool xf86DoConfigurePass1; +extern int xf86ScreenIndex; /* Index into pScreen.devPrivates */ +extern int xf86CreateRootWindowIndex; /* Index into pScreen.devPrivates */ +extern int xf86PixmapIndex; +extern Bool xf86ResAccessEnter; +extern ScrnInfoPtr *xf86Screens; /* List of pointers to ScrnInfoRecs */ +extern const unsigned char byte_reversed[256]; +extern ScrnInfoPtr xf86CurrentScreen; +extern Bool pciSlotClaimed; +extern Bool isaSlotClaimed; +extern Bool fbSlotClaimed; +#ifdef __sparc__ +extern Bool sbusSlotClaimed; +#endif +extern confDRIRec xf86ConfigDRI; +extern Bool xf86inSuspend; + +#define XF86SCRNINFO(p) ((ScrnInfoPtr)((p)->devPrivates[xf86ScreenIndex].ptr)) + +#define XF86FLIP_PIXELS() \ + do { \ + if (xf86GetFlipPixels()) { \ + pScreen->whitePixel = (pScreen->whitePixel) ? 0 : 1; \ + pScreen->blackPixel = (pScreen->blackPixel) ? 0 : 1; \ + } \ + while (0) + +#define BOOLTOSTRING(b) ((b) ? "TRUE" : "FALSE") + +#define PIX24TOBPP(p) (((p) == Pix24Use24) ? 24 : \ + (((p) == Pix24Use32) ? 32 : 0)) + +/* variables for debugging */ +#ifdef BUILDDEBUG +extern char* xf86p8bit[]; +extern CARD32 xf86DummyVar1; +extern CARD32 xf86DummyVar2; +extern CARD32 xf86DummyVar3; +#endif + +/* Function Prototypes */ +#ifndef _NO_XF86_PROTOTYPES + +/* xf86Bus.c */ + +Bool xf86CheckPciSlot(int bus, int device, int func); +int xf86ClaimPciSlot(int bus, int device, int func, DriverPtr drvp, + int chipset, GDevPtr dev, Bool active); +Bool xf86ParsePciBusString(const char *busID, int *bus, int *device, + int *func); +Bool xf86ComparePciBusString(const char *busID, int bus, int device, int func); +void xf86FormatPciBusNumber(int busnum, char *buffer); +pciVideoPtr *xf86GetPciVideoInfo(void); +pciConfigPtr *xf86GetPciConfigInfo(void); +void xf86SetPciVideo(pciVideoPtr, resType); +void xf86PrintResList(int verb, resPtr list); +resPtr xf86AddRangesToList(resPtr list, resRange *pRange, int entityIndex); +int xf86ClaimIsaSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +int xf86GetIsaInfoForScreen(int scrnIndex); +int xf86GetFbInfoForScreen(int scrnIndex); +Bool xf86ParseIsaBusString(const char *busID); +int xf86ClaimFbSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +int xf86ClaimNoSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +void xf86EnableAccess(ScrnInfoPtr pScrn); +void xf86SetCurrentAccess(Bool Enable, ScrnInfoPtr pScrn); +Bool xf86IsPrimaryPci(pciVideoPtr pPci); +Bool xf86IsPrimaryIsa(void); +int xf86CheckPciGAType(pciVideoPtr pPci); +/* new RAC */ +resPtr xf86AddResToList(resPtr rlist, resRange *Range, int entityIndex); +resPtr xf86JoinResLists(resPtr rlist1, resPtr rlist2); +resPtr xf86DupResList(const resPtr rlist); +void xf86FreeResList(resPtr rlist); +void xf86ClaimFixedResources(resList list, int entityIndex); +Bool xf86DriverHasEntities(DriverPtr drvp); +void xf86AddEntityToScreen(ScrnInfoPtr pScrn, int entityIndex); +void xf86SetEntityInstanceForScreen(ScrnInfoPtr pScrn, int entityIndex, + int instance); +int xf86GetNumEntityInstances(int entityIndex); +GDevPtr xf86GetDevFromEntity(int entityIndex, int instance); +void xf86RemoveEntityFromScreen(ScrnInfoPtr pScrn, int entityIndex); +EntityInfoPtr xf86GetEntityInfo(int entityIndex); +pciVideoPtr xf86GetPciInfoForEntity(int entityIndex); +int xf86GetPciEntity(int bus, int dev, int func); +Bool xf86SetEntityFuncs(int entityIndex, EntityProc init, + EntityProc enter, EntityProc leave, pointer); +void xf86DeallocateResourcesForEntity(int entityIndex, unsigned long type); +resPtr xf86RegisterResources(int entityIndex, resList list, + unsigned long Access); +Bool xf86CheckPciMemBase(pciVideoPtr pPci, memType base); +void xf86SetAccessFuncs(EntityInfoPtr pEnt, xf86SetAccessFuncPtr funcs, + xf86SetAccessFuncPtr oldFuncs); +Bool xf86IsEntityPrimary(int entityIndex); +Bool xf86FixPciResource(int entityIndex, int prt, memType alignment, + unsigned long type); +resPtr xf86ReallocatePciResources(int entityIndex, resPtr pRes); +resPtr xf86SetOperatingState(resList list, int entityIndex, int mask); +void xf86EnterServerState(xf86State state); +resRange xf86GetBlock(unsigned long type, memType size, + memType window_start, memType window_end, + memType align_mask, resPtr avoid); +resRange xf86GetSparse(unsigned long type, memType fixed_bits, + memType decode_mask, memType address_mask, + resPtr avoid); +memType xf86ChkConflict(resRange *rgp, int entityIndex); +Bool xf86IsPciDevPresent(int bus, int dev, int func); +ScrnInfoPtr xf86FindScreenForEntity(int entityIndex); +Bool xf86NoSharedResources(int screenIndex, resType res); +resPtr xf86FindIntersectOfLists(resPtr l1, resPtr l2); +pciVideoPtr xf86FindPciDeviceVendor(CARD16 vendorID, CARD16 deviceID, + char n, pciVideoPtr pvp_exclude); +pciVideoPtr xf86FindPciClass(CARD8 intf, CARD8 subClass, CARD16 class, + char n, pciVideoPtr pvp_exclude); +#ifdef INCLUDE_DEPRECATED +void xf86EnablePciBusMaster(pciVideoPtr pPci, Bool enable); +#endif +void xf86RegisterStateChangeNotificationCallback(xf86StateChangeNotificationCallbackFunc func, pointer arg); +Bool xf86DeregisterStateChangeNotificationCallback(xf86StateChangeNotificationCallbackFunc func); +#ifdef async +Bool xf86QueueAsyncEvent(void (*func)(pointer),pointer arg); +#endif + +int xf86GetLastScrnFlag(int entityIndex); +void xf86SetLastScrnFlag(int entityIndex, int scrnIndex); +Bool xf86IsEntityShared(int entityIndex); +void xf86SetEntityShared(int entityIndex); +Bool xf86IsEntitySharable(int entityIndex); +void xf86SetEntitySharable(int entityIndex); +Bool xf86IsPrimInitDone(int entityIndex); +void xf86SetPrimInitDone(int entityIndex); +void xf86ClearPrimInitDone(int entityIndex); +int xf86AllocateEntityPrivateIndex(void); +DevUnion *xf86GetEntityPrivate(int entityIndex, int privIndex); + +/* xf86Configure.c */ +GDevPtr xf86AddBusDeviceToConfigure(const char *driver, BusType bus, + void *busData, int chipset); +GDevPtr xf86AddDeviceToConfigure(const char *driver, pciVideoPtr pVideo, + int chipset); + +/* xf86Cursor.c */ + +void xf86LockZoom(ScreenPtr pScreen, int lock); +void xf86InitViewport(ScrnInfoPtr pScr); +void xf86SetViewport(ScreenPtr pScreen, int x, int y); +void xf86ZoomViewport(ScreenPtr pScreen, int zoom); +Bool xf86SwitchMode(ScreenPtr pScreen, DisplayModePtr mode); +void *xf86GetPointerScreenFuncs(void); +void xf86InitOrigins(void); +void xf86ReconfigureLayout(void); + +/* xf86DPMS.c */ + +Bool xf86DPMSInit(ScreenPtr pScreen, DPMSSetProcPtr set, int flags); + +/* xf86DGA.c */ + +Bool DGAInit(ScreenPtr pScreen, DGAFunctionPtr funcs, DGAModePtr modes, + int num); +Bool DGAReInitModes(ScreenPtr pScreen, DGAModePtr modes, int num); +xf86SetDGAModeProc xf86SetDGAMode; + +/* xf86Events.c */ + +void SetTimeSinceLastInputEvent(void); +pointer xf86AddInputHandler(int fd, InputHandlerProc proc, pointer data); +int xf86RemoveInputHandler(pointer handler); +void xf86DisableInputHandler(pointer handler); +void xf86EnableInputHandler(pointer handler); +void xf86InterceptSignals(int *signo); +void xf86InterceptSigIll(void (*sigillhandler)(void)); +Bool xf86EnableVTSwitch(Bool new); +Bool xf86CommonSpecialKey(int key, Bool down, int modifiers); +void xf86ProcessActionEvent(ActionEvent action, void *arg); + +/* xf86Helper.c */ + +void xf86AddDriver(DriverPtr driver, pointer module, int flags); +void xf86DeleteDriver(int drvIndex); +ScrnInfoPtr xf86AllocateScreen(DriverPtr drv, int flags); +void xf86DeleteScreen(int scrnIndex, int flags); +int xf86AllocateScrnInfoPrivateIndex(void); +Bool xf86AddPixFormat(ScrnInfoPtr pScrn, int depth, int bpp, int pad); +Bool xf86SetDepthBpp(ScrnInfoPtr scrp, int depth, int bpp, int fbbpp, + int depth24flags); +void xf86PrintDepthBpp(ScrnInfoPtr scrp); +Bool xf86SetWeight(ScrnInfoPtr scrp, rgb weight, rgb mask); +Bool xf86SetDefaultVisual(ScrnInfoPtr scrp, int visual); +Bool xf86SetGamma(ScrnInfoPtr scrp, Gamma newGamma); +void xf86SetDpi(ScrnInfoPtr pScrn, int x, int y); +void xf86SetBlackWhitePixels(ScreenPtr pScreen); +void xf86EnableDisableFBAccess(int scrnIndex, Bool enable); +void xf86VDrvMsgVerb(int scrnIndex, MessageType type, int verb, + const char *format, va_list args); +void xf86DrvMsgVerb(int scrnIndex, MessageType type, int verb, + const char *format, ...) _printf_attribute(4,5); +void xf86DrvMsg(int scrnIndex, MessageType type, const char *format, ...) + _printf_attribute(3,4); +void xf86MsgVerb(MessageType type, int verb, const char *format, ...) + _printf_attribute(3,4); +void xf86Msg(MessageType type, const char *format, ...) _printf_attribute(2,3); +void xf86ErrorFVerb(int verb, const char *format, ...) _printf_attribute(2,3); +void xf86ErrorF(const char *format, ...) _printf_attribute(1,2); +const char *xf86TokenToString(SymTabPtr table, int token); +int xf86StringToToken(SymTabPtr table, const char *string); +void xf86ShowClocks(ScrnInfoPtr scrp, MessageType from); +void xf86PrintChipsets(const char *drvname, const char *drvmsg, + SymTabPtr chips); +int xf86MatchDevice(const char *drivername, GDevPtr **driversectlist); +int xf86MatchPciInstances(const char *driverName, int vendorID, + SymTabPtr chipsets, PciChipsets *PCIchipsets, + GDevPtr *devList, int numDevs, DriverPtr drvp, + int **foundEntities); +int xf86MatchIsaInstances(const char *driverName, SymTabPtr chipsets, + IsaChipsets *ISAchipsets, DriverPtr drvp, + FindIsaDevProc FindIsaDevice, GDevPtr *devList, + int numDevs, int **foundEntities); +void xf86GetClocks(ScrnInfoPtr pScrn, int num, + Bool (*ClockFunc)(ScrnInfoPtr, int), + void (*ProtectRegs)(ScrnInfoPtr, Bool), + void (*BlankScreen)(ScrnInfoPtr, Bool), + IOADDRESS vertsyncreg, int maskval, + int knownclkindex, int knownclkvalue); +void xf86SetPriority(Bool up); +const char *xf86GetVisualName(int visual); +int xf86GetVerbosity(void); +Pix24Flags xf86GetPix24(void); +int xf86GetDepth(void); +rgb xf86GetWeight(void); +Gamma xf86GetGamma(void); +Bool xf86GetFlipPixels(void); +const char *xf86GetServerName(void); +Bool xf86ServerIsExiting(void); +Bool xf86ServerIsResetting(void); +Bool xf86ServerIsInitialising(void); +Bool xf86ServerIsOnlyDetecting(void); +Bool xf86ServerIsOnlyProbing(void); +Bool xf86CaughtSignal(void); +Bool xf86GetVidModeAllowNonLocal(void); +Bool xf86GetVidModeEnabled(void); +Bool xf86GetModInDevAllowNonLocal(void); +Bool xf86GetModInDevEnabled(void); +Bool xf86GetAllowMouseOpenFail(void); +Bool xf86IsPc98(void); +void xf86DisableRandR(void); +CARD32 xf86GetVersion(void); +CARD32 xorgGetVersion(void); +CARD32 xf86GetModuleVersion(pointer module); +pointer xf86LoadDrvSubModule(DriverPtr drv, const char *name); +pointer xf86LoadSubModule(ScrnInfoPtr pScrn, const char *name); +pointer xf86LoadOneModule(char *name, pointer optlist); +void xf86UnloadSubModule(pointer mod); +Bool xf86LoaderCheckSymbol(const char *name); +void xf86LoaderReqSymLists(const char **, ...); +void xf86LoaderReqSymbols(const char *, ...); +void xf86LoaderRefSymLists(const char **, ...); +void xf86LoaderRefSymbols(const char *, ...); +void xf86SetBackingStore(ScreenPtr pScreen); +void xf86SetSilkenMouse(ScreenPtr pScreen); +int xf86NewSerialNumber(WindowPtr p, pointer unused); +pointer xf86FindXvOptions(int scrnIndex, int adapt_index, char *port_name, + char **adaptor_name, pointer *adaptor_options); +void xf86GetOS(const char **name, int *major, int *minor, int *teeny); +ScrnInfoPtr xf86ConfigPciEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex,PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +ScrnInfoPtr xf86ConfigIsaEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +ScrnInfoPtr xf86ConfigFbEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +/* Obsolete! don't use */ +Bool xf86ConfigActivePciEntity(ScrnInfoPtr pScrn, + int entityIndex,PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +/* Obsolete! don't use */ +Bool xf86ConfigActiveIsaEntity(ScrnInfoPtr pScrn, + int entityIndex, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigPciEntityInactive(EntityInfoPtr pEnt, PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigIsaEntityInactive(EntityInfoPtr pEnt, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigFbEntityInactive(EntityInfoPtr pEnt, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +Bool xf86IsScreenPrimary(int scrnIndex); +int xf86RegisterRootWindowProperty(int ScrnIndex, Atom property, Atom type, + int format, unsigned long len, + pointer value); +Bool xf86IsUnblank(int mode); + +#ifdef XFree86LOADER +void xf86AddModuleInfo(ModuleInfoPtr info, pointer module); +void xf86DeleteModuleInfo(int idx); +#endif + +/* xf86Debug.c */ +#ifdef BUILDDEBUG + void xf86Break1(void); +void xf86Break2(void); +void xf86Break3(void); +CARD8 xf86PeekFb8(CARD8 *p); +CARD16 xf86PeekFb16(CARD16 *p); +CARD32 xf86PeekFb32(CARD32 *p); +void xf86PokeFb8(CARD8 *p, CARD8 v); +void xf86PokeFb16(CARD16 *p, CARD16 v); +void xf86PokeFb32(CARD16 *p, CARD32 v); +CARD8 xf86PeekMmio8(pointer Base, unsigned long Offset); +CARD16 xf86PeekMmio16(pointer Base, unsigned long Offset); +CARD32 xf86PeekMmio32(pointer Base, unsigned long Offset); +void xf86PokeMmio8(pointer Base, unsigned long Offset, CARD8 v); +void xf86PokeMmio16(pointer Base, unsigned long Offset, CARD16 v); +void xf86PokeMmio32(pointer Base, unsigned long Offset, CARD32 v); +extern void xf86SPTimestamp(xf86TsPtr* timestamp, char* string); +extern void xf86STimestamp(xf86TsPtr* timestamp); +#endif + +/* xf86Init.c */ + +PixmapFormatPtr xf86GetPixFormat(ScrnInfoPtr pScrn, int depth); +int xf86GetBppFromDepth(ScrnInfoPtr pScrn, int depth); + +/* xf86Mode.c */ + +int xf86GetNearestClock(ScrnInfoPtr scrp, int freq, Bool allowDiv2, + int DivFactor, int MulFactor, int *divider); +const char *xf86ModeStatusToString(ModeStatus status); +ModeStatus xf86LookupMode(ScrnInfoPtr scrp, DisplayModePtr modep, + ClockRangePtr clockRanges, LookupModeFlags strategy); +ModeStatus xf86CheckModeForMonitor(DisplayModePtr mode, MonPtr monitor); +ModeStatus xf86InitialCheckModeForDriver(ScrnInfoPtr scrp, DisplayModePtr mode, + ClockRangePtr clockRanges, + LookupModeFlags strategy, + int maxPitch, int virtualX, + int virtualY); +ModeStatus xf86CheckModeForDriver(ScrnInfoPtr scrp, DisplayModePtr mode, + int flags); +int xf86ValidateModes(ScrnInfoPtr scrp, DisplayModePtr availModes, + char **modeNames, ClockRangePtr clockRanges, + int *linePitches, int minPitch, int maxPitch, + int minHeight, int maxHeight, int pitchInc, + int virtualX, int virtualY, int apertureSize, + LookupModeFlags strategy); +void xf86DeleteMode(DisplayModePtr *modeList, DisplayModePtr mode); +void xf86PruneDriverModes(ScrnInfoPtr scrp); +void xf86SetCrtcForModes(ScrnInfoPtr scrp, int adjustFlags); +void xf86PrintModes(ScrnInfoPtr scrp); +void xf86ShowClockRanges(ScrnInfoPtr scrp, ClockRangePtr clockRanges); + +/* xf86Option.c */ + +void xf86CollectOptions(ScrnInfoPtr pScrn, pointer extraOpts); + + +/* xf86RandR.c */ +#ifdef RANDR +Bool xf86RandRInit (ScreenPtr pScreen); +void xf86RandRSetInitialMode (ScreenPtr pScreen); +Rotation xf86GetRotation(ScreenPtr pScreen); +Bool xf86RandRSetNewVirtualAndDimensions(ScreenPtr pScreen, + int newvirtX, int newvirtY, + int newmmWidth, int newmmHeight, Bool resetMode); +#endif + +/* xf86VidModeExtentionInit.c */ + +Bool VidModeExtensionInit(ScreenPtr pScreen); + +/* xf86Versions.c */ +CARD32 xf86GetBuiltinInterfaceVersion(BuiltinInterface iface, int flag); +Bool xf86RegisterBuiltinInterfaceVersion(BuiltinInterface iface, + CARD32 version, int flags); + + +#endif /* _NO_XF86_PROTOTYPES */ + +#endif /* _XF86_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Axp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Axp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Axp.h (revision 51223) @@ -0,0 +1,36 @@ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_AXP_H_ +#define _XF86_AXP_H_ + +typedef enum { + SYS_NONE, + TSUNAMI, + LCA, + APECS, + T2, + T2_GAMMA, + CIA, + MCPCIA, + JENSEN, + POLARIS, + PYXIS, + PYXIS_CIA, + IRONGATE +} axpDevice; + +typedef struct { + axpDevice id; + unsigned long hae_thresh; + unsigned long hae_mask; + unsigned long size; +} axpParams; + +extern axpParams xf86AXPParams[]; + +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Build.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Build.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Build.h (revision 51223) @@ -0,0 +1,1 @@ +#define BUILD_DATE 20051221 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Bus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Bus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Bus.h (revision 51223) @@ -0,0 +1,162 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Bus.h,v 1.23 2003/08/24 17:36:50 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the bus-related data structures/types. + * Everything contained here is private to xf86Bus.c. In particular the + * video drivers must not include this file. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_BUS_H +#define _XF86_BUS_H + +#include "xf86pciBus.h" +#ifdef __sparc__ +#include "xf86sbusBus.h" +#endif + +typedef struct racInfo { + xf86AccessPtr mem_new; + xf86AccessPtr io_new; + xf86AccessPtr io_mem_new; + xf86SetAccessFuncPtr old; +} AccessFuncRec, *AccessFuncPtr; + + +typedef struct { + DriverPtr driver; + int chipset; + int entityProp; + EntityProc entityInit; + EntityProc entityEnter; + EntityProc entityLeave; + pointer private; + resPtr resources; + Bool active; + Bool inUse; + BusRec bus; + EntityAccessPtr access; + AccessFuncPtr rac; + pointer busAcc; + int lastScrnFlag; + DevUnion * entityPrivates; + int numInstances; + GDevPtr * devices; + IOADDRESS domainIO; +} EntityRec, *EntityPtr; + +/* asynchronous event handling */ +#ifdef async +typedef struct _AsyncQRec { + void (*func)(pointer); + pointer arg; + struct _AsyncQRec *next; +} AsyncQRec, *AsyncQPtr; +#endif + +#define NO_SEPARATE_IO_FROM_MEM 0x0001 +#define NO_SEPARATE_MEM_FROM_IO 0x0002 +#define NEED_VGA_ROUTED 0x0004 +#define NEED_VGA_ROUTED_SETUP 0x0008 +#define NEED_MEM 0x0010 +#define NEED_IO 0x0020 +#define NEED_MEM_SHARED 0x0040 +#define NEED_IO_SHARED 0x0080 +#define ACCEL_IS_SHARABLE 0x0100 +#define IS_SHARED_ACCEL 0x0200 +#define SA_PRIM_INIT_DONE 0x0400 +#define NEED_VGA_MEM 0x1000 +#define NEED_VGA_IO 0x2000 + +#define NEED_SHARED (NEED_MEM_SHARED | NEED_IO_SHARED) + +#define busType bus.type +#define pciBusId bus.id.pci +#define isaBusId bus.id.isa +#define sbusBusId bus.id.sbus + +struct x_BusAccRec; +typedef void (*BusAccProcPtr)(struct x_BusAccRec *ptr); + +typedef struct x_BusAccRec { + BusAccProcPtr set_f; + BusAccProcPtr enable_f; + BusAccProcPtr disable_f; + BusAccProcPtr save_f; + BusAccProcPtr restore_f; + struct x_BusAccRec *current; /* pointer to bridge open on this bus */ + struct x_BusAccRec *primary; /* pointer to the bus connecting to this */ + struct x_BusAccRec *next; /* this links the different buses together */ + BusType type; + BusType busdep_type; + /* Bus-specific fields */ + union { + struct { + int bus; + int primary_bus; + PCITAG acc; + pciBridgesSave save; + } pci; + } busdep; +} BusAccRec, *BusAccPtr; + +/* state change notification callback */ +typedef struct _stateChange { + xf86StateChangeNotificationCallbackFunc func; + pointer arg; + struct _stateChange *next; +} StateChangeNotificationRec, *StateChangeNotificationPtr; + + +extern EntityPtr *xf86Entities; +extern int xf86NumEntities; +extern xf86AccessRec AccessNULL; +extern BusRec primaryBus; +extern resPtr Acc; +extern resPtr osRes; +extern resPtr ResRange; +extern BusAccPtr xf86BusAccInfo; + +int xf86AllocateEntity(void); +BusType StringToBusType(const char* busID, const char **retID); +memType ChkConflict(resRange *rgp, resPtr res, xf86State state); +Bool xf86IsSubsetOf(resRange range, resPtr list); +Bool xf86IsListSubsetOf(resPtr list, resPtr BaseList); +resPtr xf86ExtractTypeFromList(resPtr list, unsigned long type); +resPtr findIntersect(resRange Range, resPtr list); +resPtr xf86FindIntersect(resRange Range, resPtr list); +void RemoveOverlaps(resPtr target, resPtr list, Bool pow2Alignment, + Bool useEstimated); +void xf86ConvertListToHost(int entityIndex, resPtr list); + +#endif /* _XF86_BUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Config.h (revision 51223) @@ -0,0 +1,63 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Config.h,v 1.7 2003/10/08 14:58:27 dawes Exp $ */ + +/* + * Copyright (c) 1997-2000 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86_config_h +#define _xf86_config_h + +#ifdef HAVE_PARSER_DECLS +/* + * global structure that holds the result of parsing the config file + */ +extern XF86ConfigPtr xf86configptr; +#endif + +typedef enum _ConfigStatus { + CONFIG_OK = 0, + CONFIG_PARSE_ERROR, + CONFIG_NOFILE +} ConfigStatus; + +/* + * prototypes + */ +char ** xf86ModulelistFromConfig(pointer **); +char ** xf86DriverlistFromConfig(void); +char ** xf86DriverlistFromCompile(void); +char ** xf86InputDriverlistFromConfig(void); +char ** xf86InputDriverlistFromCompile(void); +Bool xf86BuiltinInputDriver(const char *); +ConfigStatus xf86HandleConfigFile(Bool); + +Bool xf86AutoConfig(void); + +#endif /* _xf86_config_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Cursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Cursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Cursor.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86Cursor.h,v 1.10tsi Exp $ */ + +#ifndef _XF86CURSOR_H +#define _XF86CURSOR_H + +#include "xf86str.h" +#include "mipointer.h" + +typedef struct _xf86CursorInfoRec { + ScrnInfoPtr pScrn; + int Flags; + int MaxWidth; + int MaxHeight; + void (*SetCursorColors)(ScrnInfoPtr pScrn, int bg, int fg); + void (*SetCursorPosition)(ScrnInfoPtr pScrn, int x, int y); + void (*LoadCursorImage)(ScrnInfoPtr pScrn, unsigned char *bits); + void (*HideCursor)(ScrnInfoPtr pScrn); + void (*ShowCursor)(ScrnInfoPtr pScrn); + unsigned char* (*RealizeCursor)(struct _xf86CursorInfoRec *, CursorPtr); + Bool (*UseHWCursor)(ScreenPtr, CursorPtr); + +#ifdef ARGB_CURSOR + Bool (*UseHWCursorARGB) (ScreenPtr, CursorPtr); + void (*LoadCursorARGB) (ScrnInfoPtr, CursorPtr); +#endif + +} xf86CursorInfoRec, *xf86CursorInfoPtr; + +Bool xf86InitCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr); +xf86CursorInfoPtr xf86CreateCursorInfoRec(void); +void xf86DestroyCursorInfoRec(xf86CursorInfoPtr); +void xf86ForceHWCursor (ScreenPtr pScreen, Bool on); + +#define HARDWARE_CURSOR_INVERT_MASK 0x00000001 +#define HARDWARE_CURSOR_AND_SOURCE_WITH_MASK 0x00000002 +#define HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK 0x00000004 +#define HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED 0x00000008 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 0x00000010 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_8 0x00000020 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_16 0x00000040 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_32 0x00000080 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_64 0x00000100 +#define HARDWARE_CURSOR_TRUECOLOR_AT_8BPP 0x00000200 +#define HARDWARE_CURSOR_BIT_ORDER_MSBFIRST 0x00000400 +#define HARDWARE_CURSOR_NIBBLE_SWAPPED 0x00000800 +#define HARDWARE_CURSOR_SHOW_TRANSPARENT 0x00001000 +#define HARDWARE_CURSOR_UPDATE_UNHIDDEN 0x00002000 + +#endif /* _XF86CURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86CursorPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86CursorPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86CursorPriv.h (revision 51223) @@ -0,0 +1,52 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86CursorPriv.h,v 1.4tsi Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86CURSORPRIV_H +#define _XF86CURSORPRIV_H + +#include "xf86Cursor.h" +#include "mipointrst.h" + +typedef struct { + Bool SWCursor; + Bool isUp; + Bool showTransparent; + short HotX; + short HotY; + short x; + short y; + CursorPtr CurrentCursor, CursorToRestore; + xf86CursorInfoPtr CursorInfoPtr; + CloseScreenProcPtr CloseScreen; + RecolorCursorProcPtr RecolorCursor; + InstallColormapProcPtr InstallColormap; + QueryBestSizeProcPtr QueryBestSize; + miPointerSpriteFuncPtr spriteFuncs; + Bool PalettedCursor; + ColormapPtr pInstalledMap; + Bool (*SwitchMode)(int, DisplayModePtr,int); + Bool (*EnterVT)(int, int); + void (*LeaveVT)(int, int); + int (*SetDGAMode)(int, int, DGADevicePtr); + + /* Number of requests to force HW cursor */ + int ForceHWCursorCount; + Bool HWCursorForced; + + pointer transparentData; +} xf86CursorScreenRec, *xf86CursorScreenPtr; + +void xf86SetCursor(ScreenPtr pScreen, CursorPtr pCurs, int x, int y); +void xf86SetTransparentCursor(ScreenPtr pScreen); +void xf86MoveCursor(ScreenPtr pScreen, int x, int y); +void xf86RecolorCursor(ScreenPtr pScreen, CursorPtr pCurs, Bool displayed); +Bool xf86InitHardwareCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr); + +CARD32 xf86ReverseBitOrder(CARD32 data); + +extern int xf86CursorScreenIndex; + +#endif /* _XF86CURSORPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86DDC.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86DDC.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86DDC.h (revision 51223) @@ -0,0 +1,62 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/xf86DDC.h,v 1.10 2000/06/07 22:03:09 tsi Exp $ */ + +/* xf86DDC.h + * + * This file contains all information to interpret a standard EDIC block + * transmitted by a display device via DDC (Display Data Channel). So far + * there is no information to deal with optional EDID blocks. + * DDC is a Trademark of VESA (Video Electronics Standard Association). + * + * Copyright 1998 by Egbert Eich + */ + +#ifndef XF86_DDC_H +# define XF86_DDC_H + +#include "edid.h" +#include "xf86i2c.h" +#include "xf86str.h" + +/* speed up / slow down */ +typedef enum { + DDC_SLOW, + DDC_FAST +} xf86ddcSpeed; + +typedef void (* DDC1SetSpeedProc)(ScrnInfoPtr, xf86ddcSpeed); + +extern xf86MonPtr xf86DoEDID_DDC1( + int scrnIndex, + DDC1SetSpeedProc DDC1SetSpeed, + unsigned int (*DDC1Read)(ScrnInfoPtr) +); + +extern xf86MonPtr xf86DoEDID_DDC2( + int scrnIndex, + I2CBusPtr pBus +); + +extern xf86MonPtr xf86PrintEDID( + xf86MonPtr monPtr +); + +extern xf86MonPtr xf86InterpretEDID( + int screenIndex, Uchar *block +); + +extern xf86vdifPtr xf86InterpretVdif( + CARD8 *c +); + +extern Bool xf86SetDDCproperties( + ScrnInfoPtr pScreen, + xf86MonPtr DDC +); + +extern void xf86print_vdif( + xf86vdifPtr v +); + +#endif + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Date.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Date.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Date.h (revision 51223) @@ -0,0 +1,38 @@ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/xf86Date.h,v 1.4 2004/08/16 22:48:50 kem Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Date.h,v 1.54 2003/12/19 04:52:10 dawes Exp $ */ +/* + * Copyright (c) 2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef XF86_DATE + +#define XF86_DATE "18 December 2003" + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86InPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86InPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86InPriv.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86InPriv.h,v 1.5 2003/08/24 17:36:52 dawes Exp $ */ + +/* + * Copyright (c) 1999 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86InPriv_h +#define _xf86InPriv_h + +/* xf86Globals.c */ +#ifdef XFree86LOADER +extern InputDriverPtr *xf86InputDriverList; +#else +extern InputDriverPtr xf86InputDriverList[]; +#endif +extern int xf86NumInputDrivers; + +/* xf86Xinput.c */ +void xf86ActivateDevice(InputInfoPtr pInfo); + +#endif /* _xf86InPriv_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Keymap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Keymap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Keymap.h (revision 51223) @@ -0,0 +1,455 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Keymap.h,v 3.20 2003/08/24 17:36:53 dawes Exp $ */ + +/* + * Copyright (c) 1994-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * + * For Scancodes see notes in atKeynames.h !!!! + * + */ +/* $XConsortium: xf86Keymap.h /main/14 1996/02/21 17:38:47 kaleb $ */ + +static KeySym map[NUM_KEYCODES * GLYPHS_PER_KEY] = { + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if !defined(__SOL8__) && (!defined(sun) || defined(i386)) + + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_Tab, XK_ISO_Left_Tab,NoSymbol, NoSymbol, + /* 0x10 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1c */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x1d */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x1e */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x28 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x2a */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x2c */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x34 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x35 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x36 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x37 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x38 */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x39 */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x3d */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x3f */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x48 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x49 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x4a */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x4c */ XK_KP_Begin, XK_KP_5, NoSymbol, NoSymbol, + /* 0x4d */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x4e */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x50 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x51 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x52 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x53 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x54 */ XK_Sys_Req, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_less, XK_greater, NoSymbol, NoSymbol, + /* 0x57 */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ XK_Home, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ XK_Up, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ XK_Prior, NoSymbol, NoSymbol, NoSymbol, + /* 0x5c */ XK_Left, NoSymbol, NoSymbol, NoSymbol, + /* 0x5d */ XK_Begin, NoSymbol, NoSymbol, NoSymbol, + /* 0x5e */ XK_Right, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ XK_End, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ XK_Down, NoSymbol, NoSymbol, NoSymbol, + /* 0x61 */ XK_Next, NoSymbol, NoSymbol, NoSymbol, + /* 0x62 */ XK_Insert, NoSymbol, NoSymbol, NoSymbol, + /* 0x63 */ XK_Delete, NoSymbol, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x66 */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x67 */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x69 */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x6a */ XK_Break, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ XK_Meta_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_Meta_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ XK_Menu, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ XK_F13, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ XK_F14, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ XK_F15, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ XK_F16, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ XK_F17, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ XK_backslash, XK_underscore, NoSymbol, NoSymbol, + /* 0x74 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ XK_Henkan, XK_Mode_switch, NoSymbol, NoSymbol, + /* 0x7a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ XK_Muhenkan, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x7e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + +#else /* SunOS */ + +/* Assumes a US English keyboard as default - sorry 'bout that + * + * Hopefully it'll be enough someone can have a sorta working + * keyboard, if they're not using XKB + * + * DWH 9/12/99 + */ + + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x10 */ XK_Tab, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1c */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1d */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x1e */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x28 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x2a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x2c */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x34 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x35 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x36 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x37 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x38 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x39 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x3d */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x3f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x48 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x49 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_Insert, NoSymbol, NoSymbol, NoSymbol, + /* 0x4c */ XK_Delete, NoSymbol, NoSymbol, NoSymbol, + /* 0x4d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_Left, NoSymbol, NoSymbol, NoSymbol, + /* 0x50 */ XK_Home, NoSymbol, NoSymbol, NoSymbol, + /* 0x51 */ XK_End, NoSymbol, NoSymbol, NoSymbol, + /* 0x52 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x53 */ XK_Up, NoSymbol, NoSymbol, NoSymbol, + /* 0x54 */ XK_Down, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ XK_Prior, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_Next, NoSymbol, NoSymbol, NoSymbol, + /* 0x57 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ XK_Right, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x5c */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x5d */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x5e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x61 */ NoSymbol, XK_KP_5, NoSymbol, NoSymbol, + /* 0x62 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x63 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x66 */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x67 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x69 */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x6a */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x74 */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x7a */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x7e */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x7f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + +#endif /* SunOS */ + +}; + +#if !defined(Lynx) && \ + !defined(__UNIXOS2__) && \ + !defined(__mips__) && \ + !defined(linux) && \ + !defined(CSRG_BASED) && \ + !defined(__CYGWIN__) && \ + !defined(__SOL8__) && \ + (!defined(sun) || defined(i386)) + +static KeySym map84[NUM_KEYCODES * GLYPHS_PER_KEY] = { + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_Tab, NoSymbol, NoSymbol, NoSymbol, + /* 0x10 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1c */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x1d */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x1e */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x28 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x2a */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x2c */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x34 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x35 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x36 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x37 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x38 */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x39 */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x3d */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x3f */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x48 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x49 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x4a */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x4c */ NoSymbol, XK_KP_5, NoSymbol, NoSymbol, + /* 0x4d */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x4e */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x50 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x51 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x52 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x53 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x54 */ XK_Sys_Req, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_less, XK_greater, NoSymbol, NoSymbol, + /* 0x57 */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x61 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x62 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x63 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x66 */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x67 */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x69 */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x6a */ XK_Break, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ XK_Meta_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_Meta_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ XK_Menu, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x74 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Module.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Module.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Module.h (revision 51223) @@ -0,0 +1,226 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Module.h,v 1.37 2003/08/24 17:36:54 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains the parts of the loader interface that are visible + * to modules. This is the only loader-related header that modules should + * include. + * + * It should include a bare minimum of other headers. + * + * Longer term, the module/loader code should probably live directly under + * Xserver/. + * + * XXX This file arguably belongs in xfree86/loader/. + */ + +#ifndef _XF86MODULE_H +#define _XF86MODULE_H + +#include "misc.h" +#include "xf86Version.h" +#ifndef NULL +#define NULL ((void *)0) +#endif + +typedef enum { + LD_RESOLV_IFDONE = 0, /* only check if no more + delays pending */ + LD_RESOLV_NOW = 1, /* finish one delay step */ + LD_RESOLV_FORCE = 2 /* force checking... */ +} LoaderResolveOptions; + +#define DEFAULT_LIST ((char *)-1) + +/* This indicates a special module that doesn't have the usual entry point */ +#define EXTERN_MODULE ((pointer)-1) + +/* Built-in ABI classes. These definitions must not be changed. */ +#define ABI_CLASS_NONE NULL +#define ABI_CLASS_ANSIC "X.Org ANSI C Emulation" +#define ABI_CLASS_VIDEODRV "X.Org Video Driver" +#define ABI_CLASS_XINPUT "X.Org XInput driver" +#define ABI_CLASS_EXTENSION "X.Org Server Extension" +#define ABI_CLASS_FONT "X.Org Font Renderer" + +#define ABI_MINOR_MASK 0x0000FFFF +#define ABI_MAJOR_MASK 0xFFFF0000 +#define GET_ABI_MINOR(v) ((v) & ABI_MINOR_MASK) +#define GET_ABI_MAJOR(v) (((v) & ABI_MAJOR_MASK) >> 16) +#define SET_ABI_VERSION(maj, min) \ + ((((maj) << 16) & ABI_MAJOR_MASK) | ((min) & ABI_MINOR_MASK)) + +/* + * ABI versions. Each version has a major and minor revision. Modules + * using lower minor revisions must work with servers of a higher minor + * revision. There is no compatibility between different major revisions. + * Whenever the ABI_ANSIC_VERSION is changed, the others must also be + * changed. The minor revision mask is 0x0000FFFF and the major revision + * mask is 0xFFFF0000. + */ +#define ABI_ANSIC_VERSION SET_ABI_VERSION(0, 2) +#define ABI_VIDEODRV_VERSION SET_ABI_VERSION(0, 8) +#define ABI_XINPUT_VERSION SET_ABI_VERSION(0, 5) +#define ABI_EXTENSION_VERSION SET_ABI_VERSION(0, 2) +#define ABI_FONT_VERSION SET_ABI_VERSION(0, 4) + +#define MODINFOSTRING1 0xef23fdc5 +#define MODINFOSTRING2 0x10dc023a + +#ifndef MODULEVENDORSTRING +#ifndef __OS2ELF__ +#define MODULEVENDORSTRING "X.Org Foundation" +#else +#define MODULEVENDORSTRING "X.Org Foundation - OS2" +#endif +#endif + +/* Error return codes for errmaj. New codes must only be added at the end. */ +typedef enum { + LDR_NOERROR = 0, + LDR_NOMEM, /* memory allocation failed */ + LDR_NOENT, /* Module file does not exist */ + LDR_NOSUBENT, /* pre-requsite file to be sub-loaded does not exist */ + LDR_NOSPACE, /* internal module array full */ + LDR_NOMODOPEN, /* module file could not be opened (check errmin) */ + LDR_UNKTYPE, /* file is not a recognized module type */ + LDR_NOLOAD, /* type specific loader failed */ + LDR_ONCEONLY, /* Module should only be loaded once (not an error) */ + LDR_NOPORTOPEN, /* could not open port (check errmin) */ + LDR_NOHARDWARE, /* could not query/initialize the hardware device */ + LDR_MISMATCH, /* the module didn't match the spec'd requirments */ + LDR_BADUSAGE, /* LoadModule is called with bad arguments */ + LDR_INVALID, /* The module doesn't have a valid ModuleData object */ + LDR_BADOS, /* The module doesn't support the OS */ + LDR_MODSPECIFIC /* A module-specific error in the SetupProc */ +} LoaderErrorCode; + +/* + * Some common module classes. The moduleclass can be used to identify + * that modules loaded are of the correct type. This is a finer + * classification than the ABI classes even though the default set of + * classes have the same names. For example, not all modules that require + * the video driver ABI are themselves video drivers. + */ +#define MOD_CLASS_NONE NULL +#define MOD_CLASS_VIDEODRV "X.Org Video Driver" +#define MOD_CLASS_XINPUT "X.Org XInput Driver" +#define MOD_CLASS_FONT "X.Org Font Renderer" +#define MOD_CLASS_EXTENSION "X.Org Server Extension" + +/* This structure is expected to be returned by the initfunc */ +typedef struct { + const char * modname; /* name of module, e.g. "foo" */ + const char * vendor; /* vendor specific string */ + CARD32 _modinfo1_; /* constant MODINFOSTRING1/2 to find */ + CARD32 _modinfo2_; /* infoarea with a binary editor or sign tool */ + CARD32 xf86version; /* contains XF86_VERSION_CURRENT */ + CARD8 majorversion; /* module-specific major version */ + CARD8 minorversion; /* module-specific minor version */ + CARD16 patchlevel; /* module-specific patch level */ + const char * abiclass; /* ABI class that the module uses */ + CARD32 abiversion; /* ABI version */ + const char * moduleclass; /* module class description */ + CARD32 checksum[4]; /* contains a digital signature of the */ + /* version info structure */ +} XF86ModuleVersionInfo; + +/* + * This structure can be used to callers of LoadModule and LoadSubModule to + * specify version and/or ABI requirements. + */ +typedef struct { + CARD8 majorversion; /* module-specific major version */ + CARD8 minorversion; /* moudle-specific minor version */ + CARD16 patchlevel; /* module-specific patch level */ + const char * abiclass; /* ABI class that the module uses */ + CARD32 abiversion; /* ABI version */ + const char * moduleclass; /* module class */ +} XF86ModReqInfo; + +/* values to indicate unspecified fields in XF86ModReqInfo. */ +#define MAJOR_UNSPEC 0xFF +#define MINOR_UNSPEC 0xFF +#define PATCH_UNSPEC 0xFFFF +#define ABI_VERS_UNSPEC 0xFFFFFFFF + +#define MODULE_VERSION_NUMERIC(maj, min, patch) \ + ((((maj) & 0xFF) << 24) | (((min) & 0xFF) << 16) | (patch & 0xFFFF)) +#define GET_MODULE_MAJOR_VERSION(vers) (((vers) >> 24) & 0xFF) +#define GET_MODULE_MINOR_VERSION(vers) (((vers) >> 16) & 0xFF) +#define GET_MODULE_PATCHLEVEL(vers) ((vers) & 0xFFFF) + +#define INITARGS void + +typedef void (*InitExtension)(INITARGS); + +typedef struct { + InitExtension initFunc; + const char * name; + Bool *disablePtr; + InitExtension setupFunc; + const char ** initDependencies; +} ExtensionModule; + +extern ExtensionModule *ExtensionModuleList; + +/* Prototypes for Loader functions that are exported to modules */ +#ifndef IN_LOADER +/* Prototypes with opaque pointers for use by modules */ +pointer LoadSubModule(pointer, const char *, const char **, + const char **, pointer, const XF86ModReqInfo *, + int *, int *); +void UnloadSubModule(pointer); +void LoadFont(pointer); +void UnloadModule (pointer); +#endif +pointer LoaderSymbol(const char *); +char **LoaderListDirs(const char **, const char **); +void LoaderFreeDirList(char **); +void LoaderErrorMsg(const char *, const char *, int, int); +void LoadExtension(ExtensionModule *, Bool); +void LoaderRefSymLists(const char **, ...); +void LoaderRefSymbols(const char *, ...); +void LoaderReqSymLists(const char **, ...); +void LoaderReqSymbols(const char *, ...); +int LoaderCheckUnresolved(int); +void LoaderGetOS(const char **name, int *major, int *minor, int *teeny); + +typedef pointer (*ModuleSetupProc)(pointer, pointer, int *, int *); +typedef void (*ModuleTearDownProc)(pointer); +#define MODULESETUPPROTO(func) pointer func(pointer, pointer, int*, int*) +#define MODULETEARDOWNPROTO(func) void func(pointer) + +typedef struct { + XF86ModuleVersionInfo * vers; + ModuleSetupProc setup; + ModuleTearDownProc teardown; +} XF86ModuleData; + +#endif /* _XF86STR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSKbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSKbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSKbd.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSKbd.h,v 1.5tsi Exp $ */ +/* + * Copyright (c) 2002-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + * + * Author: Ivan Pascal. + */ + +#include "xf86Xinput.h" + +Bool ATScancode(InputInfoPtr pInfo, int *scanCode); + +/* Public interface to OS-specific keyboard support. */ + +typedef int (*KbdInitProc)(InputInfoPtr pInfo, int what); +typedef int (*KbdOnProc)(InputInfoPtr pInfo, int what); +typedef int (*KbdOffProc)(InputInfoPtr pInfo, int what); +typedef void (*BellProc)(InputInfoPtr pInfo, + int loudness, int pitch, int duration); +typedef void (*SetLedsProc)(InputInfoPtr pInfo, int leds); +typedef int (*GetLedsProc)(InputInfoPtr pInfo); +typedef void (*SetKbdRepeatProc)(InputInfoPtr pInfo, char rad); +typedef void (*KbdGetMappingProc)(InputInfoPtr pInfo, + KeySymsPtr pKeySyms, CARD8* pModMap); +typedef int (*GetSpecialKeyProc)(InputInfoPtr pInfo, int scanCode); +typedef Bool (*SpecialKeyProc)(InputInfoPtr pInfo, + int key, Bool down, int modifiers); +typedef int (*RemapScanCodeProc)(InputInfoPtr pInfo, int *scanCode); +typedef Bool (*OpenKeyboardProc)(InputInfoPtr pInfo); +typedef void (*PostEventProc)(InputInfoPtr pInfo, + unsigned int key, Bool down); +typedef struct { + int begin; + int end; + unsigned char *map; +} TransMapRec, *TransMapPtr; + +typedef struct { + KbdInitProc KbdInit; + KbdOnProc KbdOn; + KbdOffProc KbdOff; + BellProc Bell; + SetLedsProc SetLeds; + GetLedsProc GetLeds; + SetKbdRepeatProc SetKbdRepeat; + KbdGetMappingProc KbdGetMapping; + RemapScanCodeProc RemapScanCode; + GetSpecialKeyProc GetSpecialKey; + SpecialKeyProc SpecialKey; + + OpenKeyboardProc OpenKeyboard; + PostEventProc PostEvent; + + int rate; + int delay; + int bell_pitch; + int bell_duration; + Bool autoRepeat; + unsigned long leds; + unsigned long xledsMask; + unsigned long keyLeds; + int scanPrefix; + Bool vtSwitchSupported; + Bool CustomKeycodes; + Bool noXkb; + Bool isConsole; + TransMapPtr scancodeMap; + TransMapPtr specialMap; + + /* os specific */ + pointer private; + int kbdType; + int consType; + int wsKbdType; + Bool sunKbd; + Bool Panix106; + +} KbdDevRec, *KbdDevPtr; + +typedef enum { + PROT_STD, + PROT_XQUEUE, + PROT_WSCONS, + PROT_USB, + PROT_UNKNOWN_KBD +} KbdProtocolId; + +typedef struct { + const char *name; + KbdProtocolId id; +} KbdProtocolRec; + +Bool xf86OSKbdPreInit(InputInfoPtr pInfo); + +/* Adjust this when the kbd interface changes. */ + +/* + * History: + * + * 1.0.0 - Initial version. + */ + +#define OS_KBD_VERSION_MAJOR 1 +#define OS_KBD_VERSION_MINOR 0 +#define OS_KBD_VERSION_PATCH 0 + +#define OS_KBD_VERSION_CURRENT \ + BUILTIN_INTERFACE_VERSION_NUMERIC(OS_KBD_VERSION_MAJOR, \ + OS_KBD_VERSION_MINOR, \ + OS_KBD_VERSION_PATCH) + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSmouse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSmouse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSmouse.h (revision 51223) @@ -0,0 +1,295 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSmouse.h,v 1.24 2003/11/03 05:11:51 tsi Exp $ */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Public interface to OS-specific mouse support. */ + +#ifndef _XF86OSMOUSE_H_ +#define _XF86OSMOUSE_H_ + +#include "xf86Xinput.h" + +/* Mouse interface classes */ +#define MSE_NONE 0x00 +#define MSE_SERIAL 0x01 /* serial port */ +#define MSE_BUS 0x02 /* old bus mouse */ +#define MSE_PS2 0x04 /* standard read-only PS/2 */ +#define MSE_XPS2 0x08 /* extended PS/2 */ +#define MSE_AUTO 0x10 /* auto-detect (PnP) */ +#define MSE_MISC 0x20 /* The OS layer will identify the + * specific protocol names that are + * supported for this class. */ + +/* Mouse Protocol IDs. */ +typedef enum { + PROT_UNKNOWN = -2, + PROT_UNSUP = -1, /* protocol is not supported */ + PROT_MS = 0, + PROT_MSC, + PROT_MM, + PROT_LOGI, + PROT_LOGIMAN, + PROT_MMHIT, + PROT_GLIDE, + PROT_IMSERIAL, + PROT_THINKING, + PROT_ACECAD, + PROT_VALUMOUSESCROLL, + PROT_PS2, + PROT_GENPS2, + PROT_IMPS2, + PROT_EXPPS2, + PROT_THINKPS2, + PROT_MMPS2, + PROT_GLIDEPS2, + PROT_NETPS2, + PROT_NETSCPS2, + PROT_BM, + PROT_AUTO, + PROT_SYSMOUSE, + PROT_NUMPROTOS /* This must always be last. */ +} MouseProtocolID; + +struct _MouseDevRec; + +typedef int (*GetInterfaceTypesProc)(void); +typedef const char **(*BuiltinNamesProc)(void); +typedef Bool (*CheckProtocolProc)(const char *protocol); +typedef Bool (*BuiltinPreInitProc)(InputInfoPtr pInfo, const char *protocol, + int flags); +typedef const char *(*DefaultProtocolProc)(void); +typedef const char *(*SetupAutoProc)(InputInfoPtr pInfo, int *protoPara); +typedef void (*SetResProc)(InputInfoPtr pInfo, const char* protocol, int rate, + int res); +typedef const char *(*FindDeviceProc)(InputInfoPtr pInfo, const char *protocol, + int flags); +typedef const char *(*GuessProtocolProc)(InputInfoPtr pInfo, int flags); + +/* + * OSMouseInfoRec is used to pass information from the OSMouse layer to the + * OS-independent mouse driver. + */ +typedef struct { + GetInterfaceTypesProc SupportedInterfaces; + BuiltinNamesProc BuiltinNames; + CheckProtocolProc CheckProtocol; + BuiltinPreInitProc PreInit; + DefaultProtocolProc DefaultProtocol; + SetupAutoProc SetupAuto; + SetResProc SetPS2Res; + SetResProc SetBMRes; + SetResProc SetMiscRes; + FindDeviceProc FindDevice; + GuessProtocolProc GuessProtocol; +} OSMouseInfoRec, *OSMouseInfoPtr; + +/* + * SupportedInterfaces: Returns the mouse interface types that the OS support. + * If MSE_MISC is returned, then the BuiltinNames and + * CheckProtocol should be set. + * + * BuiltinNames: Returns the names of the protocols that are fully handled + * in the OS-specific code. These are names that don't appear + * directly in the main "mouse" driver. + * + * CheckProtocol: Checks if the protocol name given is supported by the + * OS. It should return TRUE for both "builtin" protocols and + * protocols of type MSE_MISC that are supported by the OS. + * + * PreInit: The PreInit function for protocols that are builtin. This + * function is passed the protocol name. + * + * DefaultProtocol: Returns the name of a default protocol that should be used + * for the OS when none has been supplied in the config file. + * This should only be set when there is a reasonable default. + * + * SetupAuto: This function can be used to do OS-specific protocol + * auto-detection. It returns the name of the detected protocol, + * or NULL when detection fails. It may also adjust one or more + * of the "protoPara" values for the detected protocol by setting + * then to something other than -1. SetupAuto gets called in two + * ways. The first is before any devices have been opened. This + * can be used when the protocol "Auto" always maps to a single + * protocol type. The second is with the device open, allowing + * OS-specific probing to be done. + * + * SetPS2Res: Set the resolution and sample rate for MSE_PS2 and MSE_XPS2 + * protocol types. + * + * SetBMRes: Set the resolution and sample rate for MSE_BM protocol types. + * + * SetMiscRes: Set the resolution and sample rate for MSE_MISC protocol types. + * + * FindDevice: This function gets called when no Device has been specified + * in the config file. OS-specific methods may be used to guess + * which input device to use. This function is called after the + * pre-open attempts at protocol discovery are done, but before + * the device is open. I.e., after the first SetupAuto() call, + * after the DefaultProtocol() call, but before the PreInit() + * call. Available protocol information may be used in locating + * the default input device. + * + * GuessProtocol: A last resort attempt at guessing the mouse protocol by + * whatever OS-specific means might be available. OS-independent + * things should be in the mouse driver. This function gets + * called after the mouse driver's OS-independent methods have + * failed. + */ + +extern OSMouseInfoPtr xf86OSMouseInit(int flags); + +/* Adjust this when the mouse interface changes. */ + +/* + * History: + * + * 1.0.0 - Everything up to when versioning was started. + * 1.1.0 - FindDevice and GuessProtocol added to OSMouseInfoRec + * 1.2.0 - xisbscale added to MouseDevRec + * + */ + +#define OS_MOUSE_VERSION_MAJOR 1 +#define OS_MOUSE_VERSION_MINOR 2 +#define OS_MOUSE_VERSION_PATCH 0 + +#define OS_MOUSE_VERSION_CURRENT \ + BUILTIN_INTERFACE_VERSION_NUMERIC(OS_MOUSE_VERSION_MAJOR, \ + OS_MOUSE_VERSION_MINOR, \ + OS_MOUSE_VERSION_PATCH) + +#define HAVE_GUESS_PROTOCOL \ + (xf86GetBuiltinInterfaceVersion(BUILTIN_IF_OSMOUSE, 0) >= \ + BUILTIN_INTERFACE_VERSION_NUMERIC(1, 1, 0)) + +#define HAVE_FIND_DEVICE \ + (xf86GetBuiltinInterfaceVersion(BUILTIN_IF_OSMOUSE, 0) >= \ + BUILTIN_INTERFACE_VERSION_NUMERIC(1, 1, 0)) + +/* Z axis mapping */ +#define MSE_NOZMAP 0 +#define MSE_MAPTOX -1 +#define MSE_MAPTOY -2 +#define MSE_MAPTOZ -3 +#define MSE_MAPTOW -4 + +/* Generalize for other axes. */ +#define MSE_NOAXISMAP MSE_NOZMAP + +#define MSE_MAXBUTTONS 24 +#define MSE_DFLTBUTTONS 3 + +/* + * Mouse device record. This is shared by the mouse driver and the OSMouse + * layer. + */ + +typedef void (*checkMovementsProc)(InputInfoPtr,int, int); +typedef void (*autoProbeProc)(InputInfoPtr, Bool, Bool); +typedef Bool (*collectDataProc)(struct _MouseDevRec *, unsigned char); +typedef Bool (*dataGoodProc)(struct _MouseDevRec *); + +typedef void (*PostMseEventProc)(InputInfoPtr pInfo, int buttons, + int dx, int dy, int dz, int dw); +typedef void (*MouseCommonOptProc)(InputInfoPtr pInfo); + +typedef struct _MouseDevRec { + PtrCtrlProcPtr Ctrl; + PostMseEventProc PostEvent; + MouseCommonOptProc CommonOptions; + DeviceIntPtr device; + const char * mseDevice; + const char * protocol; + MouseProtocolID protocolID; + MouseProtocolID oldProtocolID; /* hack */ + int class; + int mseModel; + int baudRate; + int oldBaudRate; + int sampleRate; + int lastButtons; + int threshold; /* acceleration */ + int num; + int den; + int buttons; /* # of buttons */ + int emulateState; /* automata state for 2 button mode */ + Bool emulate3Buttons; + Bool emulate3ButtonsSoft; + int emulate3Timeout;/* Timeout for 3 button emulation */ + Bool chordMiddle; + Bool flipXY; + int invX; + int invY; + int mouseFlags; /* Flags to Clear after opening + * mouse dev */ + int truebuttons; /* (not used) + * Arg to maintain before + * emulate3buttons timer callback */ + int resolution; + int negativeZ; /* button mask */ + int positiveZ; /* button mask */ + int negativeW; /* button mask */ + int positiveW; /* button mask */ + pointer buffer; /* usually an XISBuffer* */ + int protoBufTail; + unsigned char protoBuf[8]; + unsigned char protoPara[8]; + unsigned char inSync; /* driver in sync with datastream */ + pointer mousePriv; /* private area */ + InputInfoPtr pInfo; + int origProtocolID; + const char * origProtocol; + Bool emulate3Pending;/* timer waiting */ + CARD32 emulate3Expires;/* time to fire emulation code */ + Bool emulateWheel; + int wheelInertia; + int wheelButton; + int negativeX; /* Button values. Unlike the Z and */ + int positiveX; /* W equivalents, these are button */ + int negativeY; /* values rather than button masks. */ + int positiveY; + int wheelYDistance; + int wheelXDistance; + Bool autoProbe; + checkMovementsProc checkMovements; + autoProbeProc autoProbeMouse; + collectDataProc collectData; + dataGoodProc dataGood; + int angleOffset; + pointer pDragLock; /* drag lock area */ + int xisbscale; /* buffer size for 1 event */ + int wheelButtonTimeout;/* Timeout for the wheel button emulation */ + CARD32 wheelButtonExpires; + int doubleClickSourceButtonMask; + int doubleClickTargetButton; + int doubleClickTargetButtonMask; + int doubleClickOldSourceState; + int lastMappedButtons; + int buttonMap[MSE_MAXBUTTONS]; +} MouseDevRec, *MouseDevPtr; + +#endif /* _XF86OSMOUSE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86OSpriv.h (revision 51223) @@ -0,0 +1,57 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSpriv.h,v 1.6 2003/08/24 17:37:03 dawes Exp $ */ +/* + * Copyright (c) 1999-2000 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86OSPRIV_H +#define _XF86OSPRIV_H + +typedef pointer (*MapMemProcPtr)(int, unsigned long, unsigned long, int); +typedef void (*UnmapMemProcPtr)(int, pointer, unsigned long); +typedef pointer (*SetWCProcPtr)(int, unsigned long, unsigned long, Bool, + MessageType); +typedef void (*ProtectMemProcPtr)(int, pointer, unsigned long, Bool); +typedef void (*UndoWCProcPtr)(int, pointer); +typedef void (*ReadSideEffectsProcPtr)(int, pointer, unsigned long); + +typedef struct { + Bool initialised; + MapMemProcPtr mapMem; + UnmapMemProcPtr unmapMem; + ProtectMemProcPtr protectMem; + SetWCProcPtr setWC; + UndoWCProcPtr undoWC; + ReadSideEffectsProcPtr readSideEffects; + Bool linearSupported; +} VidMemInfo, *VidMemInfoPtr; + +void xf86OSInitVidMem(VidMemInfoPtr); + +#endif /* _XF86OSPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Opt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Opt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Opt.h (revision 51223) @@ -0,0 +1,114 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Opt.h,v 1.15 2003/10/08 14:30:38 dawes Exp $ */ + +/* + * Copyright (c) 1998-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Option handling things that ModuleSetup procs can use */ + +#ifndef _XF86_OPT_H_ +#define _XF86_OPT_H_ + +typedef struct { + double freq; + int units; +} OptFrequency; + +typedef union { + unsigned long num; + char * str; + double realnum; + Bool bool; + OptFrequency freq; +} ValueUnion; + +typedef enum { + OPTV_NONE = 0, + OPTV_INTEGER, + OPTV_STRING, /* a non-empty string */ + OPTV_ANYSTR, /* Any string, including an empty one */ + OPTV_REAL, + OPTV_BOOLEAN, + OPTV_FREQ +} OptionValueType; + +typedef enum { + OPTUNITS_HZ = 1, + OPTUNITS_KHZ, + OPTUNITS_MHZ +} OptFreqUnits; + +typedef struct { + int token; + const char* name; + OptionValueType type; + ValueUnion value; + Bool found; +} OptionInfoRec, *OptionInfoPtr; + +int xf86SetIntOption(pointer optlist, const char *name, int deflt); +double xf86SetRealOption(pointer optlist, const char *name, double deflt); +char *xf86SetStrOption(pointer optlist, const char *name, char *deflt); +int xf86SetBoolOption(pointer list, const char *name, int deflt ); +int xf86CheckIntOption(pointer optlist, const char *name, int deflt); +double xf86CheckRealOption(pointer optlist, const char *name, double deflt); +char *xf86CheckStrOption(pointer optlist, const char *name, char *deflt); +int xf86CheckBoolOption(pointer list, const char *name, int deflt ); +pointer xf86AddNewOption(pointer head, const char *name, const char *val ); +pointer xf86NewOption(char *name, char *value ); +pointer xf86NextOption(pointer list ); +pointer xf86OptionListCreate(const char **options, int count, int used); +pointer xf86OptionListMerge(pointer head, pointer tail); +void xf86OptionListFree(pointer opt); +char *xf86OptionName(pointer opt); +char *xf86OptionValue(pointer opt); +void xf86OptionListReport(pointer parm); +pointer xf86FindOption(pointer options, const char *name); +char *xf86FindOptionValue(pointer options, const char *name); +void xf86MarkOptionUsed(pointer option); +void xf86MarkOptionUsedByName(pointer options, const char *name); +Bool xf86CheckIfOptionUsed(pointer option); +Bool xf86CheckIfOptionUsedByName(pointer options, const char *name); +void xf86ShowUnusedOptions(int scrnIndex, pointer options); +void xf86ProcessOptions(int scrnIndex, pointer options, OptionInfoPtr optinfo); +OptionInfoPtr xf86TokenToOptinfo(const OptionInfoRec *table, int token); +const char *xf86TokenToOptName(const OptionInfoRec *table, int token); +Bool xf86IsOptionSet(const OptionInfoRec *table, int token); +char *xf86GetOptValString(const OptionInfoRec *table, int token); +Bool xf86GetOptValInteger(const OptionInfoRec *table, int token, int *value); +Bool xf86GetOptValULong(const OptionInfoRec *table, int token, unsigned long *value); +Bool xf86GetOptValReal(const OptionInfoRec *table, int token, double *value); +Bool xf86GetOptValFreq(const OptionInfoRec *table, int token, + OptFreqUnits expectedUnits, double *value); +Bool xf86GetOptValBool(const OptionInfoRec *table, int token, Bool *value); +Bool xf86ReturnOptValBool(const OptionInfoRec *table, int token, Bool def); +int xf86NameCmp(const char *s1, const char *s2); +char *xf86NormalizeName(const char *s); +pointer xf86ReplaceIntOption(pointer optlist, const char *name, const int val); +pointer xf86ReplaceRealOption(pointer optlist, const char *name, const double val); +pointer xf86ReplaceBoolOption(pointer optlist, const char *name, const Bool val); +pointer xf86ReplaceStrOption(pointer optlist, const char *name, const char* val); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Optrec.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Optrec.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Optrec.h (revision 51223) @@ -0,0 +1,113 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86Optrec.h,v 1.11 2003/08/24 17:37:08 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains the Option Record that is passed between the Parser, + * and Module setup procs. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86Optrec_h_ +#define _xf86Optrec_h_ +#include + +/* + * all records that need to be linked lists should contain a GenericList as + * their first field. + */ +typedef struct generic_list_rec +{ + void *next; +} +GenericListRec, *GenericListPtr, *glp; + +/* + * All options are stored using this data type. + */ +typedef struct +{ + GenericListRec list; + char *opt_name; + char *opt_val; + int opt_used; + char *opt_comment; +} +XF86OptionRec, *XF86OptionPtr; + + +XF86OptionPtr xf86addNewOption(XF86OptionPtr head, char *name, char *val); +XF86OptionPtr xf86optionListDup(XF86OptionPtr opt); +void xf86optionListFree(XF86OptionPtr opt); +char *xf86optionName(XF86OptionPtr opt); +char *xf86optionValue(XF86OptionPtr opt); +XF86OptionPtr xf86newOption(char *name, char *value); +XF86OptionPtr xf86nextOption(XF86OptionPtr list); +XF86OptionPtr xf86findOption(XF86OptionPtr list, const char *name); +char *xf86findOptionValue(XF86OptionPtr list, const char *name); +int xf86findOptionBoolean (XF86OptionPtr, const char *, int); +XF86OptionPtr xf86optionListCreate(const char **options, int count, int used); +XF86OptionPtr xf86optionListMerge(XF86OptionPtr head, XF86OptionPtr tail); +char *xf86configStrdup (const char *s); +int xf86nameCompare (const char *s1, const char *s2); +char *xf86uLongToString(unsigned long i); +void xf86debugListOptions(XF86OptionPtr); +XF86OptionPtr xf86parseOption(XF86OptionPtr head); +void xf86printOptionList(FILE *fp, XF86OptionPtr list, int tabs); + + +#endif /* _xf86Optrec_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Parser.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Parser.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Parser.h (revision 51223) @@ -0,0 +1,483 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86Parser.h,v 1.33 2003/10/08 14:58:30 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains the external interfaces for the XFree86 configuration + * file parser. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86Parser_h_ +#define _xf86Parser_h_ + +#include "xf86Optrec.h" + +#define HAVE_PARSER_DECLS + +typedef struct +{ + char *file_logfile; + char *file_rgbpath; + char *file_modulepath; + char *file_inputdevs; + char *file_fontpath; + char *file_comment; +} +XF86ConfFilesRec, *XF86ConfFilesPtr; + +/* Values for load_type */ +#define XF86_LOAD_MODULE 0 +#define XF86_LOAD_DRIVER 1 + +typedef struct +{ + GenericListRec list; + int load_type; + char *load_name; + XF86OptionPtr load_opt; + char *load_comment; +} +XF86LoadRec, *XF86LoadPtr; + +typedef struct +{ + XF86LoadPtr mod_load_lst; + char *mod_comment; +} +XF86ConfModuleRec, *XF86ConfModulePtr; + +#define CONF_IMPLICIT_KEYBOARD "Implicit Core Keyboard" + +#define CONF_IMPLICIT_POINTER "Implicit Core Pointer" + +#define XF86CONF_PHSYNC 0x0001 +#define XF86CONF_NHSYNC 0x0002 +#define XF86CONF_PVSYNC 0x0004 +#define XF86CONF_NVSYNC 0x0008 +#define XF86CONF_INTERLACE 0x0010 +#define XF86CONF_DBLSCAN 0x0020 +#define XF86CONF_CSYNC 0x0040 +#define XF86CONF_PCSYNC 0x0080 +#define XF86CONF_NCSYNC 0x0100 +#define XF86CONF_HSKEW 0x0200 /* hskew provided */ +#define XF86CONF_BCAST 0x0400 +#define XF86CONF_CUSTOM 0x0800 /* timing numbers customized by editor */ +#define XF86CONF_VSCAN 0x1000 + +typedef struct +{ + GenericListRec list; + char *ml_identifier; + int ml_clock; + int ml_hdisplay; + int ml_hsyncstart; + int ml_hsyncend; + int ml_htotal; + int ml_vdisplay; + int ml_vsyncstart; + int ml_vsyncend; + int ml_vtotal; + int ml_vscan; + int ml_flags; + int ml_hskew; + char *ml_comment; +} +XF86ConfModeLineRec, *XF86ConfModeLinePtr; + +typedef struct +{ + GenericListRec list; + char *vp_identifier; + XF86OptionPtr vp_option_lst; + char *vp_comment; +} +XF86ConfVideoPortRec, *XF86ConfVideoPortPtr; + +typedef struct +{ + GenericListRec list; + char *va_identifier; + char *va_vendor; + char *va_board; + char *va_busid; + char *va_driver; + XF86OptionPtr va_option_lst; + XF86ConfVideoPortPtr va_port_lst; + char *va_fwdref; + char *va_comment; +} +XF86ConfVideoAdaptorRec, *XF86ConfVideoAdaptorPtr; + +#define CONF_MAX_HSYNC 8 +#define CONF_MAX_VREFRESH 8 + +typedef struct +{ + float hi, lo; +} +parser_range; + +typedef struct +{ + int red, green, blue; +} +parser_rgb; + +typedef struct +{ + GenericListRec list; + char *modes_identifier; + XF86ConfModeLinePtr mon_modeline_lst; + char *modes_comment; +} +XF86ConfModesRec, *XF86ConfModesPtr; + +typedef struct +{ + GenericListRec list; + char *ml_modes_str; + XF86ConfModesPtr ml_modes; +} +XF86ConfModesLinkRec, *XF86ConfModesLinkPtr; + +typedef struct +{ + GenericListRec list; + char *mon_identifier; + char *mon_vendor; + char *mon_modelname; + int mon_width; /* in mm */ + int mon_height; /* in mm */ + XF86ConfModeLinePtr mon_modeline_lst; + int mon_n_hsync; + parser_range mon_hsync[CONF_MAX_HSYNC]; + int mon_n_vrefresh; + parser_range mon_vrefresh[CONF_MAX_VREFRESH]; + float mon_gamma_red; + float mon_gamma_green; + float mon_gamma_blue; + XF86OptionPtr mon_option_lst; + XF86ConfModesLinkPtr mon_modes_sect_lst; + char *mon_comment; +} +XF86ConfMonitorRec, *XF86ConfMonitorPtr; + +#define CONF_MAXDACSPEEDS 4 +#define CONF_MAXCLOCKS 128 + +typedef struct +{ + GenericListRec list; + char *dev_identifier; + char *dev_vendor; + char *dev_board; + char *dev_chipset; + char *dev_busid; + char *dev_card; + char *dev_driver; + char *dev_ramdac; + int dev_dacSpeeds[CONF_MAXDACSPEEDS]; + int dev_videoram; + int dev_textclockfreq; + unsigned long dev_bios_base; + unsigned long dev_mem_base; + unsigned long dev_io_base; + char *dev_clockchip; + int dev_clocks; + int dev_clock[CONF_MAXCLOCKS]; + int dev_chipid; + int dev_chiprev; + int dev_irq; + int dev_screen; + XF86OptionPtr dev_option_lst; + char *dev_comment; +} +XF86ConfDeviceRec, *XF86ConfDevicePtr; + +typedef struct +{ + GenericListRec list; + char *mode_name; +} +XF86ModeRec, *XF86ModePtr; + +typedef struct +{ + GenericListRec list; + int disp_frameX0; + int disp_frameY0; + int disp_virtualX; + int disp_virtualY; + int disp_depth; + int disp_bpp; + char *disp_visual; + parser_rgb disp_weight; + parser_rgb disp_black; + parser_rgb disp_white; + XF86ModePtr disp_mode_lst; + XF86OptionPtr disp_option_lst; + char *disp_comment; +} +XF86ConfDisplayRec, *XF86ConfDisplayPtr; + +typedef struct +{ + XF86OptionPtr flg_option_lst; + char *flg_comment; +} +XF86ConfFlagsRec, *XF86ConfFlagsPtr; + +typedef struct +{ + GenericListRec list; + char *al_adaptor_str; + XF86ConfVideoAdaptorPtr al_adaptor; +} +XF86ConfAdaptorLinkRec, *XF86ConfAdaptorLinkPtr; + +typedef struct +{ + GenericListRec list; + char *scrn_identifier; + char *scrn_obso_driver; + int scrn_defaultdepth; + int scrn_defaultbpp; + int scrn_defaultfbbpp; + char *scrn_monitor_str; + XF86ConfMonitorPtr scrn_monitor; + char *scrn_device_str; + XF86ConfDevicePtr scrn_device; + XF86ConfAdaptorLinkPtr scrn_adaptor_lst; + XF86ConfDisplayPtr scrn_display_lst; + XF86OptionPtr scrn_option_lst; + char *scrn_comment; +} +XF86ConfScreenRec, *XF86ConfScreenPtr; + +typedef struct +{ + GenericListRec list; + char *inp_identifier; + char *inp_driver; + XF86OptionPtr inp_option_lst; + char *inp_comment; +} +XF86ConfInputRec, *XF86ConfInputPtr; + +typedef struct +{ + GenericListRec list; + XF86ConfInputPtr iref_inputdev; + char *iref_inputdev_str; + XF86OptionPtr iref_option_lst; +} +XF86ConfInputrefRec, *XF86ConfInputrefPtr; + +/* Values for adj_where */ +#define CONF_ADJ_OBSOLETE -1 +#define CONF_ADJ_ABSOLUTE 0 +#define CONF_ADJ_RIGHTOF 1 +#define CONF_ADJ_LEFTOF 2 +#define CONF_ADJ_ABOVE 3 +#define CONF_ADJ_BELOW 4 +#define CONF_ADJ_RELATIVE 5 + +typedef struct +{ + GenericListRec list; + int adj_scrnum; + XF86ConfScreenPtr adj_screen; + char *adj_screen_str; + XF86ConfScreenPtr adj_top; + char *adj_top_str; + XF86ConfScreenPtr adj_bottom; + char *adj_bottom_str; + XF86ConfScreenPtr adj_left; + char *adj_left_str; + XF86ConfScreenPtr adj_right; + char *adj_right_str; + int adj_where; + int adj_x; + int adj_y; + char *adj_refscreen; +} +XF86ConfAdjacencyRec, *XF86ConfAdjacencyPtr; + +typedef struct +{ + GenericListRec list; + char *inactive_device_str; + XF86ConfDevicePtr inactive_device; +} +XF86ConfInactiveRec, *XF86ConfInactivePtr; + +typedef struct +{ + GenericListRec list; + char *lay_identifier; + XF86ConfAdjacencyPtr lay_adjacency_lst; + XF86ConfInactivePtr lay_inactive_lst; + XF86ConfInputrefPtr lay_input_lst; + XF86OptionPtr lay_option_lst; + char *lay_comment; +} +XF86ConfLayoutRec, *XF86ConfLayoutPtr; + +typedef struct +{ + GenericListRec list; + char *vs_name; + char *vs_identifier; + XF86OptionPtr vs_option_lst; + char *vs_comment; +} +XF86ConfVendSubRec, *XF86ConfVendSubPtr; + +typedef struct +{ + GenericListRec list; + char *vnd_identifier; + XF86OptionPtr vnd_option_lst; + XF86ConfVendSubPtr vnd_sub_lst; + char *vnd_comment; +} +XF86ConfVendorRec, *XF86ConfVendorPtr; + +typedef struct +{ + GenericListRec list; + int buf_count; + int buf_size; + char *buf_flags; + char *buf_comment; +} +XF86ConfBuffersRec, *XF86ConfBuffersPtr; + +typedef struct +{ + char *dri_group_name; + int dri_group; + int dri_mode; + XF86ConfBuffersPtr dri_buffers_lst; + char *dri_comment; +} +XF86ConfDRIRec, *XF86ConfDRIPtr; + +typedef struct +{ + XF86OptionPtr ext_option_lst; + char *extensions_comment; +} +XF86ConfExtensionsRec, *XF86ConfExtensionsPtr; + +typedef struct +{ + XF86ConfFilesPtr conf_files; + XF86ConfModulePtr conf_modules; + XF86ConfFlagsPtr conf_flags; + XF86ConfVideoAdaptorPtr conf_videoadaptor_lst; + XF86ConfModesPtr conf_modes_lst; + XF86ConfMonitorPtr conf_monitor_lst; + XF86ConfDevicePtr conf_device_lst; + XF86ConfScreenPtr conf_screen_lst; + XF86ConfInputPtr conf_input_lst; + XF86ConfLayoutPtr conf_layout_lst; + XF86ConfVendorPtr conf_vendor_lst; + XF86ConfDRIPtr conf_dri; + XF86ConfExtensionsPtr conf_extensions; + char *conf_comment; +} +XF86ConfigRec, *XF86ConfigPtr; + +typedef struct +{ + int token; /* id of the token */ + char *name; /* pointer to the LOWERCASED name */ +} +xf86ConfigSymTabRec, *xf86ConfigSymTabPtr; + +/* + * prototypes for public functions + */ +extern const char *xf86openConfigFile (const char *, const char *, + const char *); +extern void xf86setBuiltinConfig(const char *config[]); +extern XF86ConfigPtr xf86readConfigFile (void); +extern void xf86closeConfigFile (void); +extern void xf86freeConfig (XF86ConfigPtr p); +extern int xf86writeConfigFile (const char *, XF86ConfigPtr); +XF86ConfDevicePtr xf86findDevice(const char *ident, XF86ConfDevicePtr p); +XF86ConfLayoutPtr xf86findLayout(const char *name, XF86ConfLayoutPtr list); +XF86ConfMonitorPtr xf86findMonitor(const char *ident, XF86ConfMonitorPtr p); +XF86ConfModesPtr xf86findModes(const char *ident, XF86ConfModesPtr p); +XF86ConfModeLinePtr xf86findModeLine(const char *ident, XF86ConfModeLinePtr p); +XF86ConfScreenPtr xf86findScreen(const char *ident, XF86ConfScreenPtr p); +XF86ConfInputPtr xf86findInput(const char *ident, XF86ConfInputPtr p); +XF86ConfInputPtr xf86findInputByDriver(const char *driver, XF86ConfInputPtr p); +XF86ConfVendorPtr xf86findVendor(const char *name, XF86ConfVendorPtr list); +XF86ConfVideoAdaptorPtr xf86findVideoAdaptor(const char *ident, + XF86ConfVideoAdaptorPtr p); + +GenericListPtr xf86addListItem(GenericListPtr head, GenericListPtr c_new); +int xf86itemNotSublist(GenericListPtr list_1, GenericListPtr list_2); + +int xf86pathIsAbsolute(const char *path); +int xf86pathIsSafe(const char *path); +char *xf86addComment(char *cur, char *add); + +#endif /* _xf86Parser_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Pci.h (revision 51223) @@ -0,0 +1,807 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Pci.h,v 1.39 2003/08/24 17:37:05 dawes Exp $ */ +/* + * Copyright 1998 by Concurrent Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Concurrent Computer + * Corporation not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Concurrent Computer Corporation makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Copyright 1998 by Metro Link Incorporated + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Metro Link + * Incorporated not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Metro Link Incorporated makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * This file is derived in part from the original xf86_PCI.h that included + * following copyright message: + * + * Copyright 1995 by Robin Cutshaw + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains just the public interface to the PCI code. + * Drivers should use this file rather than Pci.h. + */ + +#ifndef _XF86PCI_H +#define _XF86PCI_H 1 +#include +#include +#include "misc.h" + +#define PCI_NOT_FOUND 0xFFFFFFFFU + +/* + * PCI cfg space definitions (e.g. stuff right out of the PCI spec) + */ + +/* Device identification register */ +#define PCI_ID_REG 0x00 + +/* Command and status register */ +#define PCI_CMD_STAT_REG 0x04 +#define PCI_CMD_BASE_REG 0x10 +#define PCI_CMD_BIOS_REG 0x30 +#define PCI_CMD_MASK 0xffff +#define PCI_CMD_IO_ENABLE 0x01 +#define PCI_CMD_MEM_ENABLE 0x02 +#define PCI_CMD_MASTER_ENABLE 0x04 +#define PCI_CMD_SPECIAL_ENABLE 0x08 +#define PCI_CMD_INVALIDATE_ENABLE 0x10 +#define PCI_CMD_PALETTE_ENABLE 0x20 +#define PCI_CMD_PARITY_ENABLE 0x40 +#define PCI_CMD_STEPPING_ENABLE 0x80 +#define PCI_CMD_SERR_ENABLE 0x100 +#define PCI_CMD_BACKTOBACK_ENABLE 0x200 +#define PCI_CMD_BIOS_ENABLE 0x01 + +/* base class */ +#define PCI_CLASS_REG 0x08 +#define PCI_CLASS_MASK 0xff000000 +#define PCI_CLASS_SHIFT 24 +#define PCI_CLASS_EXTRACT(x) \ + (((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT) + +/* base class values */ +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_COMMUNICATIONS 0x07 +#define PCI_CLASS_SYSPERIPH 0x08 +#define PCI_CLASS_INPUT 0x09 +#define PCI_CLASS_DOCKING 0x0a +#define PCI_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_SERIALBUS 0x0c +#define PCI_CLASS_WIRELESS 0x0d +#define PCI_CLASS_I2O 0x0e +#define PCI_CLASS_SATELLITE 0x0f +#define PCI_CLASS_CRYPT 0x10 +#define PCI_CLASS_DATA_ACQUISTION 0x11 +#define PCI_CLASS_UNDEFINED 0xff + +/* sub class */ +#define PCI_SUBCLASS_MASK 0x00ff0000 +#define PCI_SUBCLASS_SHIFT 16 +#define PCI_SUBCLASS_EXTRACT(x) \ + (((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT) + +/* Sub class values */ +/* 0x00 prehistoric subclasses */ +#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 + +/* 0x01 mass storage subclasses */ +#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 +#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 + +/* 0x02 network subclasses */ +#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 +#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 +#define PCI_SUBCLASS_NETWORK_FDDI 0x02 +#define PCI_SUBCLASS_NETWORK_MISC 0x80 + +/* 0x03 display subclasses */ +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 + +/* 0x04 multimedia subclasses */ +#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 +#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 +#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 + +/* 0x05 memory subclasses */ +#define PCI_SUBCLASS_MEMORY_RAM 0x00 +#define PCI_SUBCLASS_MEMORY_FLASH 0x01 +#define PCI_SUBCLASS_MEMORY_MISC 0x80 + +/* 0x06 bridge subclasses */ +#define PCI_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_SUBCLASS_BRIDGE_MC 0x03 +#define PCI_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 +#define PCI_SUBCLASS_BRIDGE_MISC 0x80 +#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01 + +/* 0x07 communications controller subclasses */ +#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 +#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 +#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02 +#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 +#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 + +/* 0x08 generic system peripherals subclasses */ +#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00 +#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01 +#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02 +#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03 +#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04 +#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80 + +/* 0x09 input device subclasses */ +#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 +#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 +#define PCI_SUBCLASS_INPUT_MOUSE 0x02 +#define PCI_SUBCLASS_INPUT_SCANNER 0x03 +#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 +#define PCI_SUBCLASS_INPUT_MISC 0x80 + +/* 0x0a docking station subclasses */ +#define PCI_SUBCLASS_DOCKING_GENERIC 0x00 +#define PCI_SUBCLASS_DOCKING_MISC 0x80 + +/* 0x0b processor subclasses */ +#define PCI_SUBCLASS_PROCESSOR_386 0x00 +#define PCI_SUBCLASS_PROCESSOR_486 0x01 +#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 +#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 +#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 +#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 +#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 + +/* 0x0c serial bus controller subclasses */ +#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00 +#define PCI_SUBCLASS_SERIAL_ACCESS 0x01 +#define PCI_SUBCLASS_SERIAL_SSA 0x02 +#define PCI_SUBCLASS_SERIAL_USB 0x03 +#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04 +#define PCI_SUBCLASS_SERIAL_SMBUS 0x05 + +/* 0x0d wireless controller subclasses */ +#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 +#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01 +#define PCI_SUBCLASS_WIRELESS_RF 0x02 +#define PCI_SUBCLASS_WIRELESS_MISC 0x80 + +/* 0x0e intelligent I/O controller subclasses */ +#define PCI_SUBCLASS_I2O_I2O 0x00 + +/* 0x0f satellite communications controller subclasses */ +#define PCI_SUBCLASS_SATELLITE_TV 0x01 +#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02 +#define PCI_SUBCLASS_SATELLITE_VOICE 0x03 +#define PCI_SUBCLASS_SATELLITE_DATA 0x04 + +/* 0x10 encryption/decryption controller subclasses */ +#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00 +#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10 +#define PCI_SUBCLASS_CRYPT_MISC 0x80 + +/* 0x11 data acquisition and signal processing controller subclasses */ +#define PCI_SUBCLASS_DATAACQ_DPIO 0x00 +#define PCI_SUBCLASS_DATAACQ_MISC 0x80 + + +/* Header */ +#define PCI_HEADER_MISC 0x0c +#define PCI_HEADER_MULTIFUNCTION 0x00800000 + +/* Interrupt configration register */ +#define PCI_INTERRUPT_REG 0x3c +#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 +#define PCI_INTERRUPT_PIN_EXTRACT(x) \ + ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) +#define PCI_INTERRUPT_PIN_NONE 0x00 +#define PCI_INTERRUPT_PIN_A 0x01 +#define PCI_INTERRUPT_PIN_B 0x02 +#define PCI_INTERRUPT_PIN_C 0x03 +#define PCI_INTERRUPT_PIN_D 0x04 + +#define PCI_INTERRUPT_LINE_MASK 0x000000ff +#define PCI_INTERRUPT_LINE_EXTRACT(x) \ + ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) +#define PCI_INTERRUPT_LINE_INSERT(x,v) \ + (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) + +/* Base registers */ +#define PCI_MAP_REG_START 0x10 +#define PCI_MAP_REG_END 0x28 +#define PCI_MAP_ROM_REG 0x30 + +#define PCI_MAP_MEMORY 0x00000000 +#define PCI_MAP_IO 0x00000001 + +#define PCI_MAP_MEMORY_TYPE 0x00000007 +#define PCI_MAP_IO_TYPE 0x00000003 + +#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 +#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 +#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 +#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 +#define PCI_MAP_MEMORY_CACHABLE 0x00000008 +#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e +#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 + +#define PCI_MAP_IO_ATTR_MASK 0x00000003 + +#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) +#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) + +#define PCI_MAP_IS64BITMEM(b) \ + (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT) + +#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) +#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1)) +#define PCIGETMEMORY64(b) \ + (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) + +#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc + +#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) + +#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 +#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 + +#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) + +/* PCI-PCI bridge mapping registers */ +#define PCI_PCI_BRIDGE_BUS_REG 0x18 +#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 +#define PCI_SECONDARY_BUS_MASK 0x0000ff00 +#define PCI_PRIMARY_BUS_MASK 0x000000ff + +#define PCI_PCI_BRIDGE_IO_REG 0x1c +#define PCI_PCI_BRIDGE_MEM_REG 0x20 +#define PCI_PCI_BRIDGE_PMEM_REG 0x24 + +#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00) +#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00) + +#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000) +#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000) + +#define PCI_PCI_BRIDGE_CONTROL_REG 0x3E +#define PCI_PCI_BRIDGE_PARITY_EN 0x01 +#define PCI_PCI_BRIDGE_SERR_EN 0x02 +#define PCI_PCI_BRIDGE_ISA_EN 0x04 +#define PCI_PCI_BRIDGE_VGA_EN 0x08 +#define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20 +#define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40 +#define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80 +/* header type 2 extensions */ +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 + +#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */ +#define PCI_CB_MEM_BASE_0_REG 0x1c +#define PCI_CB_MEM_LIMIT_0_REG 0x20 +#define PCI_CB_MEM_BASE_1_REG 0x24 +#define PCI_CB_MEM_LIMIT_1_REG 0x28 +#define PCI_CB_IO_BASE_0_REG 0x2c +#define PCI_CB_IO_LIMIT_0_REG 0x30 +#define PCI_CB_IO_BASE_1_REG 0x34 +#define PCI_CB_IO_LIMIT_1_REG 0x38 +#define PCI_CB_BRIDGE_CONTROL_REG 0x3E + +#define PCI_CB_IO_RANGE_MASK ~0x03 +#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK) +#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3) + +/* Subsystem identification register */ +#define PCI_SUBSYSTEM_ID_REG 0x2c + +/* User defined cfg space regs */ +#define PCI_REG_USERCONFIG 0x40 +#define PCI_OPTION_REG 0x40 + +/* + * Typedefs, etc... + */ + +/* Primitive Types */ +typedef unsigned long ADDRESS; /* Memory/PCI address */ +typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */ +typedef unsigned long PCITAG; + +/* + * PCI configuration space + */ +typedef struct pci_cfg_regs { + /* start of official PCI config space header */ + union { /* Offset 0x0 - 0x3 */ + CARD32 device_vendor; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 device; + CARD16 vendor; +#else + CARD16 vendor; + CARD16 device; +#endif + } dv; + } dv_id; + + union { /* Offset 0x4 - 0x8 */ + CARD32 status_command; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 status; + CARD16 command; +#else + CARD16 command; + CARD16 status; +#endif + } sc; + } stat_cmd; + + union { /* Offset 0x8 - 0xb */ + CARD32 class_revision; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 base_class; + CARD8 sub_class; + CARD8 prog_if; + CARD8 rev_id; +#else + CARD8 rev_id; + CARD8 prog_if; + CARD8 sub_class; + CARD8 base_class; +#endif + } cr; + } class_rev; + + union { /* Offset 0xc - 0xf */ + CARD32 bist_header_latency_cache; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 bist; + CARD8 header_type; + CARD8 latency_timer; + CARD8 cache_line_size; +#else + CARD8 cache_line_size; + CARD8 latency_timer; + CARD8 header_type; + CARD8 bist; +#endif + } bhlc; + } bhlc; + union { /* Offset 0x10 - 0x3b */ + struct { /* header type 2 */ + CARD32 cg_rsrvd1; /* 0x10 */ +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 secondary_status; /* 0x16 */ + CARD16 cg_rsrvd2; /* 0x14 */ + + union { + CARD32 cg_bus_reg; + struct { + CARD8 latency_timer; /* 0x1b */ + CARD8 subordinate_bus_number; /* 0x1a */ + CARD8 cardbus_bus_number; /* 0x19 */ + CARD8 primary_bus_number; /* 0x18 */ + } cgbr; + } cgbr; +#else + CARD16 cg_rsrvd2; /* 0x14 */ + CARD16 secondary_status; /* 0x16 */ + + union { + CARD32 cg_bus_reg; + struct { + CARD8 primary_bus_number; /* 0x18 */ + CARD8 cardbus_bus_number; /* 0x19 */ + CARD8 subordinate_bus_number; /* 0x1a */ + CARD8 latency_timer; /* 0x1b */ + } cgbr; + } cgbr; +#endif + CARD32 mem_base0; /* 0x1c */ + CARD32 mem_limit0; /* 0x20 */ + CARD32 mem_base1; /* 0x24 */ + CARD32 mem_limit1; /* 0x28 */ + CARD32 io_base0; /* 0x2c */ + CARD32 io_limit0; /* 0x30 */ + CARD32 io_base1; /* 0x34 */ + CARD32 io_limit1; /* 0x38 */ + } cg; + struct { + union { /* Offset 0x10 - 0x27 */ + struct { /* header type 0 */ + CARD32 dv_base0; + CARD32 dv_base1; + CARD32 dv_base2; + CARD32 dv_base3; + CARD32 dv_base4; + CARD32 dv_base5; + } dv; + struct { /* header type 1 */ + CARD32 bg_rsrvd[2]; +#if X_BYTE_ORDER == X_BIG_ENDIAN + union { + CARD32 pp_bus_reg; + struct { + CARD8 secondary_latency_timer; + CARD8 subordinate_bus_number; + CARD8 secondary_bus_number; + CARD8 primary_bus_number; + } ppbr; + } ppbr; + + CARD16 secondary_status; + CARD8 io_limit; + CARD8 io_base; + + CARD16 mem_limit; + CARD16 mem_base; + + CARD16 prefetch_mem_limit; + CARD16 prefetch_mem_base; +#else + union { + CARD32 pp_bus_reg; + struct { + CARD8 primary_bus_number; + CARD8 secondary_bus_number; + CARD8 subordinate_bus_number; + CARD8 secondary_latency_timer; + } ppbr; + } ppbr; + + CARD8 io_base; + CARD8 io_limit; + CARD16 secondary_status; + + CARD16 mem_base; + CARD16 mem_limit; + + CARD16 prefetch_mem_base; + CARD16 prefetch_mem_limit; +#endif + } bg; + } bc; + union { /* Offset 0x28 - 0x2b */ + CARD32 rsvd1; + CARD32 pftch_umem_base; + CARD32 cardbus_cis_ptr; + } um_c_cis; + union { /* Offset 0x2c - 0x2f */ + CARD32 subsys_card_vendor; + CARD32 pftch_umem_limit; + CARD32 rsvd2; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 subsys_card; + CARD16 subsys_vendor; +#else + CARD16 subsys_vendor; + CARD16 subsys_card; +#endif + } ssys; + } um_ssys_id; + union { /* Offset 0x30 - 0x33 */ + CARD32 baserom; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 io_ulimit; + CARD16 io_ubase; +#else + CARD16 io_ubase; + CARD16 io_ulimit; +#endif + } b_u_io; + } uio_rom; + struct { + CARD32 rsvd3; /* Offset 0x34 - 0x37 */ + CARD32 rsvd4; /* Offset 0x38 - 0x3b */ + } rsvd; + } cd; + } cx; + union { /* Offset 0x3c - 0x3f */ + union { /* header type 0 */ + CARD32 max_min_ipin_iline; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 max_lat; + CARD8 min_gnt; + CARD8 int_pin; + CARD8 int_line; +#else + CARD8 int_line; + CARD8 int_pin; + CARD8 min_gnt; + CARD8 max_lat; +#endif + } mmii; + } mmii; + struct { /* header type 1 */ +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 bridge_control; /* upper 8 bits reserved */ + CARD8 rsvd2; + CARD8 rsvd1; +#else + CARD8 rsvd1; + CARD8 rsvd2; + CARD16 bridge_control; /* upper 8 bits reserved */ +#endif + } bctrl; + } bm; + union { /* Offset 0x40 - 0xff */ + CARD32 dwords[48]; + CARD8 bytes[192]; + } devspf; +} pciCfgRegs; + +typedef union pci_cfg_spc { + pciCfgRegs regs; + CARD32 dwords[256/sizeof(CARD32)]; + CARD8 bytes[256/sizeof(CARD8)]; +} pciCfgSpc; + +/* + * Data structure returned by xf86scanpci including contents of + * PCI config space header + */ +typedef struct pci_device { + PCITAG tag; + int busnum; + int devnum; + int funcnum; + pciCfgSpc cfgspc; + int basesize[7]; /* number of bits in base addr allocations */ + Bool minBasesize; + CARD32 listed_class; + pointer businfo; /* pointer to secondary's bus info structure */ + Bool fakeDevice; /* Device added by system chipset support */ +} pciDevice, *pciConfigPtr; + +typedef enum { + PCI_MEM, + PCI_MEM_SIZE, + PCI_MEM_SPARSE_BASE, + PCI_MEM_SPARSE_MASK, + PCI_IO, + PCI_IO_SIZE, + PCI_IO_SPARSE_BASE, + PCI_IO_SPARSE_MASK +} PciAddrType; + +#define pci_device_vendor cfgspc.regs.dv_id.device_vendor +#define pci_vendor cfgspc.regs.dv_id.dv.vendor +#define pci_device cfgspc.regs.dv_id.dv.device +#define pci_status_command cfgspc.regs.stat_cmd.status_command +#define pci_command cfgspc.regs.stat_cmd.sc.command +#define pci_status cfgspc.regs.stat_cmd.sc.status +#define pci_class_revision cfgspc.regs.class_rev.class_revision +#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id +#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if +#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class +#define pci_base_class cfgspc.regs.class_rev.cr.base_class +#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache +#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size +#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer +#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type +#define pci_bist cfgspc.regs.bhlc.bhlc.bist +#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status +#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg +#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number +#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number +#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number +#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer +#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0 +#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0 +#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1 +#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1 +#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0 +#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0 +#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1 +#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1 +#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0 +#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1 +#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2 +#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3 +#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4 +#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5 +#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr +#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor +#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor +#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card +#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom +#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg +#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number +#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number +#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number +#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer +#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base +#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit +#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status +#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base +#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit +#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base +#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit +#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1 +#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2 +#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base +#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit +#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase +#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit +#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line +#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin +#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt +#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat +#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline +#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control +#define pci_user_config cfgspc.regs.devspf.dwords[0] +#define pci_user_config_0 cfgspc.regs.devspf.bytes[0] +#define pci_user_config_1 cfgspc.regs.devspf.bytes[1] +#define pci_user_config_2 cfgspc.regs.devspf.bytes[2] +#define pci_user_config_3 cfgspc.regs.devspf.bytes[3] + +typedef enum { + PCI_BIOS_PC = 0, + PCI_BIOS_OPEN_FIRMARE, + PCI_BIOS_HP_PA_RISC, + PCI_BIOS_OTHER +} PciBiosType; + +/* Public PCI access functions */ +void pciInit(void); +PCITAG pciFindFirst(CARD32 id, CARD32 mask); +PCITAG pciFindNext(void); +CARD32 pciReadLong(PCITAG tag, int offset); +CARD16 pciReadWord(PCITAG tag, int offset); +CARD8 pciReadByte(PCITAG tag, int offset); +void pciWriteLong(PCITAG tag, int offset, CARD32 val); +void pciWriteWord(PCITAG tag, int offset, CARD16 val); +void pciWriteByte(PCITAG tag, int offset, CARD8 val); +void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val); +void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val); +ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr); +ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr); +PCITAG pciTag(int busnum, int devnum, int funcnum); +int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min); +CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg); +pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag, + ADDRESS Base, unsigned long Size); +int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg, + unsigned char *Buf, int Len); +int xf86ReadPciBIOSByType(unsigned long Offset, PCITAG Tag, + int basereg, unsigned char *Buf, + int Len, PciBiosType Type); +int xf86GetAvailablePciBIOSTypes(PCITAG Tag, int basereg, + PciBiosType *Buf); +pciConfigPtr *xf86scanpci(int flags); + +extern int pciNumBuses; + +/* Domain access functions. Some of these probably shouldn't be public */ +int xf86GetPciDomain(PCITAG tag); +pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, + ADDRESS Base, unsigned long Size); +IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, + IOADDRESS Base, unsigned long Size); +int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, + unsigned char *Buf); + +typedef enum { + ROM_BASE_PRESET = -2, + ROM_BASE_BIOS, + ROM_BASE_MEM0 = 0, + ROM_BASE_MEM1, + ROM_BASE_MEM2, + ROM_BASE_MEM3, + ROM_BASE_MEM4, + ROM_BASE_MEM5, + ROM_BASE_FIND +} romBaseSource; + +#endif /* _XF86PCI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciData.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciData.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciData.h (revision 51223) @@ -0,0 +1,80 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86PciData.h,v 1.3 2003/08/24 17:37:10 dawes Exp $ */ + +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_DATA_H_ +#define PCI_DATA_H_ + +#define NOVENDOR 0xFFFF +#define NODEVICE 0xFFFF +#define NOSUBSYS 0xFFFF + +typedef Bool (*ScanPciSetupProcPtr)(void); +typedef void (*ScanPciCloseProcPtr)(void); +typedef int (*ScanPciFindByDeviceProcPtr)( + unsigned short vendor, unsigned short device, + unsigned short svendor, unsigned short subsys, + const char **vname, const char **dname, + const char **svname, const char **sname); +typedef int (*ScanPciFindBySubsysProcPtr)( + unsigned short svendor, unsigned short subsys, + const char **svname, const char **sname); +typedef CARD32 (*ScanPciFindClassBySubsysProcPtr)( + unsigned short vendor, unsigned short subsystem); +typedef CARD32 (*ScanPciFindClassByDeviceProcPtr)( + unsigned short vendor, unsigned short device); + +/* + * Whoever loads this module needs to define these and initialise them + * after loading. + */ +extern ScanPciSetupProcPtr xf86SetupPciIds; +extern ScanPciCloseProcPtr xf86ClosePciIds; +extern ScanPciFindByDeviceProcPtr xf86FindPciNamesByDevice; +extern ScanPciFindBySubsysProcPtr xf86FindPciNamesBySubsys; +extern ScanPciFindClassBySubsysProcPtr xf86FindPciClassBySubsys; +extern ScanPciFindClassByDeviceProcPtr xf86FindPciClassByDevice; + +Bool ScanPciSetupPciIds(void); +void ScanPciClosePciIds(void); +int ScanPciFindPciNamesByDevice(unsigned short vendor, unsigned short device, + unsigned short svendor, unsigned short subsys, + const char **vname, const char **dname, + const char **svname, const char **sname); +int ScanPciFindPciNamesBySubsys(unsigned short svendor, unsigned short subsys, + const char **svname, const char **sname); +CARD32 ScanPciFindPciClassBySubsys(unsigned short vendor, + unsigned short subsystem); +CARD32 ScanPciFindPciClassByDevice(unsigned short vendor, + unsigned short device); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciIds.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciIds.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciIds.h (revision 51223) @@ -0,0 +1,126167 @@ +/* $XdotOrg$ */ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +static const char pci_device_0070_0003[] = "WinTV PVR-250"; +static const char pci_device_0070_0009[] = "WinTV PVR-150"; +static const char pci_device_0070_0801[] = "WinTV PVR-150"; +static const char pci_device_0070_0807[] = "WinTV PVR-150"; +static const char pci_device_0070_4000[] = "WinTV PVR-350"; +static const char pci_device_0070_4001[] = "WinTV PVR-250 (v1)"; +static const char pci_device_0070_4009[] = "WinTV PVR-250"; +static const char pci_device_0070_4800[] = "WinTV PVR-350"; +static const char pci_device_0070_4801[] = "WinTV PVR-250 MCE"; +static const char pci_device_0070_4803[] = "WinTV PVR-250"; +static const char pci_device_0070_8003[] = "WinTV PVR-150"; +static const char pci_device_0070_8801[] = "WinTV PVR-150"; +static const char pci_device_0070_c801[] = "WinTV PVR-150"; +static const char pci_device_0070_e807[] = "WinTV PVR-500 MCE (1st tuner)"; +static const char pci_device_0070_e817[] = "WinTV PVR-500 MCE (2nd tuner)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0071[] = "Nebula Electronics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0095[] = "Silicon Image, Inc. (Wrong ID)"; +static const char pci_device_0095_0680[] = "Ultra ATA/133 IDE RAID CONTROLLER CARD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00a7[] = "Teles AG (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_018a[] = "LevelOne"; +static const char pci_device_018a_0106[] = "FPC-0106TX misprogrammed [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_021b[] = "Compaq Computer Corporation"; +static const char pci_device_021b_8139[] = "HNE-300 (RealTek RTL8139c) [iPaq Networking]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0270[] = "Hauppauge computer works Inc. (Wrong ID)"; +static const char pci_device_0270_0801[] = "WinTV PVR-150"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0291[] = "Davicom Semiconductor, Inc."; +static const char pci_device_0291_8212[] = "DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_02ac[] = "SpeedStream"; +static const char pci_device_02ac_1012[] = "1012 PCMCIA 10/100 Ethernet Card [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0357[] = "TTTech AG"; +static const char pci_device_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0432[] = "SCM Microsystems, Inc."; +static const char pci_device_0432_0001[] = "Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_045e[] = "Microsoft"; +static const char pci_device_045e_006e[] = "MN-510 802.11b wireless USB paddle"; +static const char pci_device_045e_00c2[] = "MN-710 wireless USB paddle"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_04cf[] = "Myson Century, Inc"; +static const char pci_device_04cf_8818[] = "CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05e3[] = "CyberDoor"; +static const char pci_device_05e3_0701[] = "CBD516"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +static const char pci_device_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_067b[] = "Prolific Technology, Inc."; +static const char pci_device_067b_3507[] = "PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0721[] = "Sapphire, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_07e2[] = "ELMEG Communication Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b49[] = "ASCII Corporation"; +static const char pci_device_0b49_064f[] = "Trance Vibrator"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0046[] = "Smart Array 64xx"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409a[] = "Smart Array 641"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409b[] = "Smart Array 642"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409c[] = "Smart Array 6400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409d[] = "Smart Array 6400 EM"; +#endif +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_005a[] = "Remote Insight II board - Lights-Out"; +static const char pci_device_0e11_007c[] = "NC7770 1000BaseTX"; +static const char pci_device_0e11_007d[] = "NC6770 1000BaseTX"; +static const char pci_device_0e11_0085[] = "NC7780 1000BaseTX"; +static const char pci_device_0e11_00b1[] = "Remote Insight II board - PCI device"; +static const char pci_device_0e11_00bb[] = "NC7760"; +static const char pci_device_0e11_00ca[] = "NC7771"; +static const char pci_device_0e11_00cb[] = "NC7781"; +static const char pci_device_0e11_00cf[] = "NC7772"; +static const char pci_device_0e11_00d0[] = "NC7782"; +static const char pci_device_0e11_00d1[] = "NC7783"; +static const char pci_device_0e11_00e3[] = "NC7761"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_4030[] = "SMART-2/P"; +static const char pci_device_0e11_4031[] = "SMART-2SL"; +static const char pci_device_0e11_4032[] = "Smart Array 3200"; +static const char pci_device_0e11_4033[] = "Smart Array 3100ES"; +static const char pci_device_0e11_4034[] = "Smart Array 221"; +static const char pci_device_0e11_4040[] = "Integrated Array"; +static const char pci_device_0e11_4048[] = "Compaq Raid LC2"; +static const char pci_device_0e11_4050[] = "Smart Array 4200"; +static const char pci_device_0e11_4051[] = "Smart Array 4250ES"; +static const char pci_device_0e11_4058[] = "Smart Array 431"; +static const char pci_device_0e11_4070[] = "Smart Array 5300"; +static const char pci_device_0e11_4080[] = "Smart Array 5i"; +static const char pci_device_0e11_4082[] = "Smart Array 532"; +static const char pci_device_0e11_4083[] = "Smart Array 5312"; +static const char pci_device_0e11_4091[] = "Smart Array 6i"; +static const char pci_device_0e11_409a[] = "Smart Array 641"; +static const char pci_device_0e11_409b[] = "Smart Array 642"; +static const char pci_device_0e11_409c[] = "Smart Array 6400"; +static const char pci_device_0e11_409d[] = "Smart Array 6400 EM"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "FibreChannel HBA Tachyon"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10 T PCI UTP"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent Dual 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae43[] = "Netelligent Integrated 10/100 TX UTP"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Netelligent 10/100 TX Embedded UTP"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2 PCI UTP/Coax"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent 10/100 TX UTP"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4080[] = "Smart Array 5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4082[] = "Smart Array 532"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4083[] = "Smart Array 5312"; +#endif +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_b200[] = "Memory Hot-Plug Controller"; +static const char pci_device_0e11_b203[] = "Integrated Lights Out Controller"; +static const char pci_device_0e11_b204[] = "Integrated Lights Out Processor"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "LSI53C810AE PCI to SCSI I/O Processor"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0003_1000_1000[] = "LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide)"; +#endif +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0006_1000_1000[] = "LSI53C860E PCI to Ultra SCSI I/O Processor"; +#endif +static const char pci_device_1000_000a[] = "53c1510"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_1000_1000[] = "LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode)"; +#endif +static const char pci_device_1000_000b[] = "53C896/897"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_0e11_6004[] = "EOB003 Series SCSI host adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1000[] = "LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1010[] = "LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1020[] = "LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_13e9_1000[] = "6221L-4U"; +#endif +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1010[] = "LSI8951U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1020[] = "LSI8952U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3906[] = "DC-390U2B SCSI adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1000[] = "LSI53C876/E PCI to Dual Channel SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1010[] = "LSI22801 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1020[] = "LSI22802 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F/U Ultra Wide SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1050[] = "CT7 mainboard"; +#endif +static const char pci_device_1000_0010[] = "53C1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "RAID LC2 Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_1000_1000[] = "53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode)"; +#endif +static const char pci_device_1000_0012[] = "53c895a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0012_1000_1000[] = "LSI53C895A PCI to Ultra2 SCSI Controller"; +#endif +static const char pci_device_1000_0013[] = "53c875a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0013_1000_1000[] = "LSI53C875A PCI to Ultra SCSI Controller"; +#endif +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1000_1000[] = "LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1000[] = "LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1010[] = "Asus TR-DLS onboard 53C1010-66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_124b_1070[] = "PMC-USCSI3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1300[] = "P017 mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1310[] = "P017 mezzanine (64-bit PMC)"; +#endif +static const char pci_device_1000_0030[] = "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_0e11_00da[] = "ProLiant ML 350"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0123[] = "PowerEdge 2600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_014a[] = "PowerEdge 1750"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_016c[] = "PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_124b_1170[] = "PMC-USCSI320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1734_1052[] = "Primergy RX300 S2"; +#endif +static const char pci_device_1000_0031[] = "53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0032[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0032_1000_1000[] = "LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller"; +#endif +static const char pci_device_1000_0033[] = "1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0040[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0033[] = "MegaRAID SCSI 320-2XR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0066[] = "MegaRAID SCSI 320-2XRWS"; +#endif +static const char pci_device_1000_0041[] = "53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0050[] = "SAS1064 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0054[] = "SAS1068 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0056[] = "SAS1064E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_0058[] = "SAS1068E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005a[] = "SAS1066E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005c[] = "SAS1064A PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_005e[] = "SAS1066 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0060[] = "SAS1078 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0407[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0530[] = "MegaRAID 530 SCSI 320-0X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0531[] = "MegaRAID 531 SCSI 320-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0532[] = "MegaRAID 532 SCSI 320-2X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0530[] = "MegaRAID Intel RAID Controller SRCZCRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0532[] = "MegaRAID Intel RAID Controller SRCU42X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0408[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0001[] = "MegaRAID SCSI 320-1E RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0002[] = "MegaRAID SCSI 320-2E RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1025_004d[] = "MegaRAID ACER ROMB-2E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0001[] = "PowerEdge RAID Controller PERC4e/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0002[] = "PowerEdge RAID Controller PERC4e/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1734_1065[] = "FSC MegaRAID PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_8086_0002[] = "MegaRAID Intel RAID Controller SRCU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0409[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3004[] = "MegaRAID SATA 300-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3008[] = "MegaRAID SATA 300-8X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3008[] = "MegaRAID RAID Controller SRCS28X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3431[] = "MegaRAID RAID Controller Alief SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3499[] = "MegaRAID RAID Controller Harwich SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0621[] = "FC909 Fibre Channel Adapter"; +static const char pci_device_1000_0622[] = "FC929 Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0622_1000_1020[] = "44929 O Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919 Fibre Channel Adapter"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0626_1000_1010[] = "7202-XP-LC Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X Fibre Channel Adapter"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0640[] = "FC949X Fibre Channel Adapter"; +static const char pci_device_1000_0642[] = "FC939X Fibre Channel Adapter"; +static const char pci_device_1000_0646[] = "FC949ES Fibre Channel Adapter"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0804[] = "SA2010"; +static const char pci_device_1000_0805[] = "SA2010ZC"; +static const char pci_device_1000_0806[] = "SA2020"; +static const char pci_device_1000_0807[] = "SA2020ZC"; +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0518[] = "MegaRAID 518 SCSI 320-2 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0520[] = "MegaRAID 520 SCSI 320-1 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0522[] = "MegaRAID 522 i4 133 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0523[] = "MegaRAID SATA 150-6 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_4523[] = "MegaRAID SATA 150-4 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_a520[] = "MegaRAID ZCR SCSI 320-0 Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "MegaRAID 518 DELL PERC 4/DC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "MegaRAID 520 DELL PERC 4/SC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0520[] = "MegaRAIDRAID Controller SRCU41L"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0523[] = "MegaRAID RAID Controller SRCS16"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_3150[] = "M24 1P [Radeon Mobility X600]"; +static const char pci_device_1002_3152[] = "M22 [Radeon Mobility X300]"; +static const char pci_device_1002_3154[] = "M24 1T [FireGL M24 GL]"; +static const char pci_device_1002_3e50[] = "RV380 0x3e50 [Radeon X600]"; +static const char pci_device_1002_3e54[] = "RV380 0x3e54 [FireGL V3200]"; +static const char pci_device_1002_3e70[] = "RV380 [Radeon X600] Secondary"; +static const char pci_device_1002_4136[] = "Radeon IGP 320 M"; +static const char pci_device_1002_4137[] = "Radeon IGP330/340/350"; +static const char pci_device_1002_4144[] = "R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "R300 AE [Radeon 9700 Pro]"; +static const char pci_device_1002_4146[] = "R300 AF [Radeon 9700 Pro]"; +static const char pci_device_1002_4147[] = "R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4148[] = "R350 AH [Radeon 9800]"; +static const char pci_device_1002_4149[] = "R350 AI [Radeon 9800]"; +static const char pci_device_1002_414a[] = "R350 AJ [Radeon 9800]"; +static const char pci_device_1002_414b[] = "R350 AK [Fire GL X2]"; +static const char pci_device_1002_4150[] = "RV350 AP [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0002[] = "R9600 Pro primary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1458_4024[] = "Giga-Byte GV-R96128D Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2064[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2066[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c19[] = "Sapphire Atlantis Radeon 9600 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c29[] = "GC-R9600PRO Primary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_17ee_2002[] = "Radeon 9600 256Mb Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_18bc_0101[] = "GC-R9600PRO Primary"; +#endif +static const char pci_device_1002_4151[] = "RV350 AQ [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4151_1043_c004[] = "A9600SE"; +#endif +static const char pci_device_1002_4152[] = "RV350 AR [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_0002[] = "Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_4772[] = "All-in-Wonder 9600 XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c002[] = "Radeon 9600 XT TVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c01a[] = "A9600XT/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_174b_7c29[] = "Sapphire Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1787_4002[] = "Radeon 9600 XT"; +#endif +static const char pci_device_1002_4153[] = "RV350 AS [Radeon 9550]"; +static const char pci_device_1002_4154[] = "RV350 AT [Fire GL T2]"; +static const char pci_device_1002_4155[] = "RV350 AU [Fire GL T2]"; +static const char pci_device_1002_4156[] = "RV350 AV [Fire GL T2]"; +static const char pci_device_1002_4157[] = "RV350 AW [Fire GL T2]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4164[] = "R300 AD [Radeon 9500 Pro] (Secondary)"; +static const char pci_device_1002_4165[] = "R300 AE [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4166[] = "R300 AF [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4168[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4170[] = "RV350 AP [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1458_4025[] = "Giga-Byte GV-R96128D Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_148c_2067[] = "PowerColor R96A-C3N (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_174b_7c28[] = "GC-R9600PRO Secondary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_17ee_2003[] = "Radeon 9600 256Mb Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_18bc_0100[] = "GC-R9600PRO Secondary"; +#endif +static const char pci_device_1002_4171[] = "RV350 AQ [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4171_1043_c005[] = "A9600SE (Secondary)"; +#endif +static const char pci_device_1002_4172[] = "RV350 AR [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_0003[] = "Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_4773[] = "All-in-Wonder 9600 XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c003[] = "A9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c01b[] = "A9600XT/TD (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_174b_7c28[] = "Sapphire Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1787_4003[] = "Radeon 9600 XT (Secondary)"; +#endif +static const char pci_device_1002_4173[] = "RV350 ? [Radeon 9550] (Secondary)"; +static const char pci_device_1002_4237[] = "Radeon 7000 IGP"; +static const char pci_device_1002_4242[] = "R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4243[] = "R200 BC [Radeon All in Wonder 8500]"; +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_1002_4336[] = "Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_103c_0024[] = "Pavilion ze4400 builtin Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_161f_2029[] = "eMachines M5312 builtin Video"; +#endif +static const char pci_device_1002_4337[] = "Radeon IGP 330M/340M/350M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_1014_053a[] = "ThinkPad R40e (2684-HVG) builtin VGA controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_103c_0850[] = "Radeon IGP 345M"; +#endif +static const char pci_device_1002_4341[] = "IXP150 AC'97 Audio Controller"; +static const char pci_device_1002_4345[] = "EHCI USB Controller"; +static const char pci_device_1002_4347[] = "OHCI USB Controller #1"; +static const char pci_device_1002_4348[] = "OHCI USB Controller #2"; +static const char pci_device_1002_4349[] = "ATI Dual Channel Bus Master PCI IDE Controller"; +static const char pci_device_1002_434d[] = "IXP AC'97 Modem"; +static const char pci_device_1002_4353[] = "ATI SMBus"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4363[] = "ATI SMBus"; +static const char pci_device_1002_436e[] = "ATI 436E Serial ATA Controller"; +static const char pci_device_1002_4370[] = "IXP SB400 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4371[] = "IXP SB400 PCI-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4371_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4372[] = "IXP SB400 SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4373[] = "IXP SB400 USB2 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4374[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4374_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4375[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4376[] = "Standard Dual Channel PCI IDE Controller ATI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4377[] = "IXP SB400 PCI-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4378[] = "ATI SB400 - AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4379[] = "ATI 4379 Serial ATA Controller"; +static const char pci_device_1002_437a[] = "ATI 437A Serial ATA Controller"; +static const char pci_device_1002_4437[] = "Radeon Mobility 7000 IGP"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1734_007a[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0084[] = "Rage 3D Pro AGP 2x XPERT 98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon RV250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon RV250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon RV250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "RV250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "RV250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "RV250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "RV250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "RV250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "RV250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "RV250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "RV250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon RV250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon RV250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4a48[] = "R420 JH [Radeon X800]"; +static const char pci_device_1002_4a49[] = "R420 JI [Radeon X800PRO]"; +static const char pci_device_1002_4a4a[] = "R420 JJ [Radeon X800SE]"; +static const char pci_device_1002_4a4b[] = "R420 JK [Radeon X800]"; +static const char pci_device_1002_4a4c[] = "R420 JL [Radeon X800]"; +static const char pci_device_1002_4a4d[] = "R420 JM [FireGL X3]"; +static const char pci_device_1002_4a4e[] = "M18 JN [Radeon Mobility 9800]"; +static const char pci_device_1002_4a50[] = "R420 JP [Radeon X800XT]"; +static const char pci_device_1002_4a70[] = "R420 [X800XT-PE] (Secondary)"; +static const char pci_device_1002_4b49[] = "R480 [Radeon X850XT]"; +static const char pci_device_1002_4b4b[] = "R480 [Radeon X850Pro]"; +static const char pci_device_1002_4b4c[] = "R481 [Radeon X850XT-PE]"; +static const char pci_device_1002_4b69[] = "R480 [Radeon X850XT secondary]"; +static const char pci_device_1002_4b6b[] = "R480 [Radeon X850Pro] (Secondary)"; +static const char pci_device_1002_4b6c[] = "R481 [Radeon X850XT-PE] Secondary"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e7[] = "Rage LT Pro (Compaq Presario 5240)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c46_1028_00b1[] = "Latitude C600"; +#endif +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b160[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m/A21m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00aa[] = "Latitude CPt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00bb[] = "Latitude CPx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_10e1_10cf[] = "Fujitsu Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_13bd_1019[] = "PC-AR10"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c52_1033_8112[] = "Versa Note VXi"; +#endif +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_0e11_b111[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1509_1930[] = "Medion MD9703"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 Lf [FireGL 9000]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c6e[] = "Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_515e[] = "Radeon ES1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_5965[] = "Radeon ES1000"; +#endif +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1002_0002[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1681_0002[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro]"; +#endif +static const char pci_device_1002_4e46[] = "RV350 NF [Radeon 9600]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e48[] = "Radeon R350 [Radeon 9800 Pro]"; +static const char pci_device_1002_4e49[] = "Radeon R350 [Radeon 9800]"; +static const char pci_device_1002_4e4a[] = "RV350 NJ [Radeon 9800 XT]"; +static const char pci_device_1002_4e4b[] = "R350 NK [Fire GL X2]"; +static const char pci_device_1002_4e50[] = "RV350 [Mobility Radeon 9600 M10]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1734_1055[] = "Amilo M1420W"; +#endif +static const char pci_device_1002_4e51[] = "M10 NQ [Radeon Mobility 9600]"; +static const char pci_device_1002_4e52[] = "RV350 [Mobility Radeon 9600 M10]"; +static const char pci_device_1002_4e53[] = "M10 NS [Radeon Mobility 9600]"; +static const char pci_device_1002_4e54[] = "M10 NT [FireGL Mobility T2]"; +static const char pci_device_1002_4e56[] = "M11 NV [FireGL Mobility T2e]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9500 Pro] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1002_0003[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1681_0003[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary)"; +#endif +static const char pci_device_1002_4e66[] = "RV350 NF [Radeon 9600] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_4e68[] = "Radeon R350 [Radeon 9800 Pro] (Secondary)"; +static const char pci_device_1002_4e69[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4e6a[] = "RV350 NJ [Radeon 9800 XT] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e6a_1002_4e71[] = "ATI Technologies Inc M10 NQ [Radeon Mobility 9600]"; +#endif +static const char pci_device_1002_4e71[] = "M10 NQ [Radeon Mobility 9600] (secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1681_0010[] = "Radeon 8500 [3D Prophet 8500 128Mb]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5154[] = "R200 QT [Radeon 8500]"; +static const char pci_device_1002_5155[] = "R200 QU [Radeon 9100]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_103a[] = "Dell Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7146[] = "RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7c28[] = "Sapphire Radeon VE 7000 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_515e[] = "ES1000"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5346_1002_0048[] = "RAGE 128 16MB VGA TVOUT AMC PAL"; +#endif +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5460[] = "M22 [Radeon Mobility M300]"; +static const char pci_device_1002_5464[] = "M22 [FireGL GL]"; +static const char pci_device_1002_5548[] = "R423 UH [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5549[] = "R423 UI [Radeon X800PRO (PCIE)]"; +static const char pci_device_1002_554a[] = "R423 UJ [Radeon X800LE (PCIE)]"; +static const char pci_device_1002_554b[] = "R423 UK [Radeon X800SE (PCIE)]"; +static const char pci_device_1002_554d[] = "R430 [Radeon X800 XL] (PCIe)"; +static const char pci_device_1002_554f[] = "R430 [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5550[] = "R423 [Fire GL V7100]"; +static const char pci_device_1002_5551[] = "R423 UQ [FireGL V7200 (PCIE)]"; +static const char pci_device_1002_5552[] = "R423 UR [FireGL V5100 (PCIE)]"; +static const char pci_device_1002_5554[] = "R423 UT [FireGL V7100 (PCIE)]"; +static const char pci_device_1002_556b[] = "Radeon R423 UK (PCIE) [X800 SE] (Secondary)"; +static const char pci_device_1002_556d[] = "R430 [Radeon X800 XL] (PCIe) Secondary"; +static const char pci_device_1002_556f[] = "R430 [Radeon X800 (PCIE) Secondary]"; +static const char pci_device_1002_564a[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564b[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_5652[] = "M26 [Radeon Mobility X700]"; +static const char pci_device_1002_5653[] = "Radeon Mobility X700 (PCIE)"; +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_5830[] = "RS300 Host Bridge"; +static const char pci_device_1002_5831[] = "RS300 Host Bridge"; +static const char pci_device_1002_5832[] = "RS300 Host Bridge"; +static const char pci_device_1002_5833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_5834[] = "Radeon 9100 IGP"; +static const char pci_device_1002_5835[] = "RS300M AGP [Radeon Mobility 9100IGP]"; +static const char pci_device_1002_5838[] = "Radeon 9100 IGP AGP Bridge"; +static const char pci_device_1002_5940[] = "RV280 [Radeon 9200 PRO] (Secondary)"; +static const char pci_device_1002_5941[] = "RV280 [Radeon 9200] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_1458_4019[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_174b_7c12[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_17af_200d[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_18bc_0050[] = "GeXcube GC-R9200-C3 (Secondary)"; +#endif +static const char pci_device_1002_5944[] = "RV280 [Radeon 9200 SE (PCI)]"; +static const char pci_device_1002_5950[] = "RS480 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5951[] = "ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge"; +static const char pci_device_1002_5954[] = "RS480 [Radeon Xpress 200G Series]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5954_1002_5954[] = "RV370 [Radeon Xpress 200G Series]"; +#endif +static const char pci_device_1002_5955[] = "ATI Radeon XPRESS 200M 5955 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_1002_5955[] = "RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5960[] = "RV280 [Radeon 9200 PRO]"; +static const char pci_device_1002_5961[] = "RV280 [Radeon 9200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1002_2f72[] = "All-in-Wonder 9200 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1019_4c30[] = "Radeon 9200 VIVO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_12ab_5961[] = "YUAN SMARTVGA Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1458_4018[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_174b_7c13[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_17af_200c[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0050[] = "Radeon 9200 Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0051[] = "GeXcube GC-R9200-C3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0053[] = "Radeon 9200 Game Buster VIVO"; +#endif +static const char pci_device_1002_5962[] = "RV280 [Radeon 9200]"; +static const char pci_device_1002_5964[] = "RV280 [Radeon 9200 SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1043_c006[] = "ASUS Radeon 9200 SE / TD / 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4018[] = "Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_147b_6191[] = "R9200SE-DT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_148c_2073[] = "CN-AG92E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_174b_7c13[] = "Sapphire Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1787_5964[] = "Excalibur 9200SE VIVO 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_17af_2012[] = "Radeon 9200 SE Excalibur"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0170[] = "Sapphire Radeon 9200 SE 128MB Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0173[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5969[] = "ES1000"; +static const char pci_device_1002_5974[] = "RS482 [Radeon Xpress 200]"; +static const char pci_device_1002_5975[] = "RS482 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a34[] = "RS480 PCI-X Root Port"; +static const char pci_device_1002_5a41[] = "RS400 [Radeon Xpress 200]"; +static const char pci_device_1002_5a42[] = "RS400 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a61[] = "RC410 [Radeon Xpress 200]"; +static const char pci_device_1002_5a62[] = "RC410 [Radeon Xpress 200M]"; +static const char pci_device_1002_5b60[] = "RV370 5B60 [Radeon X300 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_002a[] = "Extreme AX300SE-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_032e[] = "Extreme AX300/TD"; +#endif +static const char pci_device_1002_5b62[] = "RV370 5B62 [Radeon X600 (PCIE)]"; +static const char pci_device_1002_5b63[] = "RV370 [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b64[] = "RV370 5B64 [FireGL V3100 (PCIE)]"; +static const char pci_device_1002_5b65[] = "RV370 5B65 [FireGL D1100 (PCIE)]"; +static const char pci_device_1002_5b70[] = "RV370 [Radeon X300SE]"; +static const char pci_device_1002_5b72[] = "Radeon X600(RV380)"; +static const char pci_device_1002_5b73[] = "RV370 secondary [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b74[] = "RV370 5B64 [FireGL V3100 (PCIE)] (Secondary)"; +static const char pci_device_1002_5c61[] = "M9+ 5C61 [Radeon Mobility 9200 (AGP)]"; +static const char pci_device_1002_5c63[] = "M9+ 5C63 [Radeon Mobility 9200 (AGP)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5c63_1002_5c63[] = "Apple iBook G4 2004"; +#endif +static const char pci_device_1002_5d44[] = "RV280 [Radeon 9200 SE] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4019[] = "Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_174b_7c12[] = "Sapphire Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1787_5965[] = "Excalibur 9200SE VIVO 128M (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_17af_2013[] = "Radeon 9200 SE Excalibur (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0171[] = "Radeon 9200 SE 128MB Game Buster (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0172[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5d48[] = "M28 [Radeon Mobility X800XT]"; +static const char pci_device_1002_5d49[] = "M28 [Mobility FireGL V5100]"; +static const char pci_device_1002_5d4a[] = "Mobility Radeon X800"; +static const char pci_device_1002_5d4d[] = "R480 [Radeon X850XT Platinum (PCIE)]"; +static const char pci_device_1002_5d52[] = "R480 [Radeon X850XT (PCIE)] (Primary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b12[] = "PowerColor X850XT PCIe Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b13[] = "PowerColor X850XT PCIe Secondary"; +#endif +static const char pci_device_1002_5d57[] = "R423 5F57 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_5d6d[] = "R480 [Radeon X850XT Platinum (PCIE)] (Secondary)"; +static const char pci_device_1002_5d72[] = "R480 [Radeon X850XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5d77[] = "R423 5F57 [Radeon X800XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5e48[] = "RV410 [FireGL V5000]"; +static const char pci_device_1002_5e49[] = "RV410 [FireGL V3300]"; +static const char pci_device_1002_5e4a[] = "RV410 [Radeon X700XT]"; +static const char pci_device_1002_5e4b[] = "RV410 [Radeon X700 Pro (PCIE)]"; +static const char pci_device_1002_5e4c[] = "RV410 [Radeon X700SE]"; +static const char pci_device_1002_5e4d[] = "RV410 [Radeon X700 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e4d_148c_2116[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5e4f[] = "RV410 [Radeon X700]"; +static const char pci_device_1002_5e6b[] = "RV410 [Radeon X700 Pro (PCIE)] Secondary"; +static const char pci_device_1002_5e6d[] = "RV410 [Radeon X700 (PCIE)] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e6d_148c_2117[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_700f[] = "PCI Bridge [IGP 320M]"; +static const char pci_device_1002_7010[] = "PCI Bridge [IGP 340M]"; +static const char pci_device_1002_7105[] = "R520 [FireGL]"; +static const char pci_device_1002_7109[] = "R520 [Radeon X900]"; +static const char pci_device_1002_7833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_7834[] = "Radeon 9100 PRO IGP"; +static const char pci_device_1002_7835[] = "Radeon Mobility 9200 IGP"; +static const char pci_device_1002_7838[] = "Radeon 9100 IGP PCI/AGP Bridge"; +static const char pci_device_1002_7c37[] = "RV350 AQ [Radeon 9600 SE]"; +static const char pci_device_1002_cab0[] = "AGP Bridge [IGP 320M]"; +static const char pci_device_1002_cab2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +static const char pci_device_1002_cab3[] = "R200 AGP Bridge [Mobility Radeon 7000 IGP]"; +static const char pci_device_1002_cbb2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_103c_0024[] = "Pavilion ze4400 builtin Network"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_1385_f311[] = "FA311 / FA312 (FA311 with WoL HW)"; +#endif +static const char pci_device_100b_0021[] = "PC87200 PCI to ISA Bridge"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0028[] = "Geode GX2 Host Bridge"; +static const char pci_device_100b_002a[] = "CS5535 South Bridge"; +static const char pci_device_100b_002b[] = "CS5535 ISA bridge"; +static const char pci_device_100b_002d[] = "CS5535 IDE"; +static const char pci_device_100b_002e[] = "CS5535 Audio"; +static const char pci_device_100b_002f[] = "CS5535 USB"; +static const char pci_device_100b_0030[] = "Geode GX2 Graphics Processor"; +static const char pci_device_100b_0035[] = "DP83065 [Saturn] 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_0510[] = "SC1100 Bridge"; +static const char pci_device_100b_0511[] = "SC1100 SMI"; +static const char pci_device_100b_0515[] = "SC1100 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "DEFPA"; +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0017[] = "PV-PCI Graphics Controller (ZLXp-L)"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1112[] = "DFE-570TX Quad Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_14cb_0100[] = "LNDL-100N 100Base-TX Ethernet PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX Gigabit Ethernet"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "Hewlett-Packard NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "IP Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0364[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4000[] = "MD 5620 [CLM Data Fax Voice]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_1136[] = "SiXPack 5.1+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "GXT1000 Graphics Adapter"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "SCSI RAID Adapter [ServeRAID]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0031[] = "2 Port Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0031_1014_0031[] = "2721 WAN IOA - 2 Port Sync Serial Adapter"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_0037[] = "82660 CPU to PCI Bridge"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003c[] = "GXT250P/GXT255P Graphics Adapter"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0054[] = "GXT500P/GXT550P Graphics Adapter"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_005e[] = "GXT800P Graphics Adapter"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_008b[] = "EADS PCI to PCI Bridge"; +static const char pci_device_1014_008e[] = "GXT3000P Graphics Adapter"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0091[] = "SSA Adapter"; +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_009f[] = "PCI 4758 Cryptographic Accelerator"; +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_00b7_1092_00b8[] = "FireGL1 AGP 32Mb"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1014_00b8[] = "GXT2000P Graphics Adapter"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0104[] = "Gigabit Ethernet-SX Adapter"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_015e[] = "622Mbps ATM PCI Adapter"; +static const char pci_device_1014_0160[] = "64bit/66MHz PCI ATM 155 MMF"; +static const char pci_device_1014_016e[] = "GXT4000P Graphics Adapter"; +static const char pci_device_1014_0170[] = "GXT6000P Graphics Adapter"; +static const char pci_device_1014_017d[] = "GXT300P Graphics Adapter"; +static const char pci_device_1014_0180[] = "Snipe chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0241[] = "iSeries 2757 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0264[] = "Quad Channel PCI-X U320 SCSI RAID Adapter (2780)"; +#endif +static const char pci_device_1014_0188[] = "EADS-X PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_01c1[] = "64bit/66MHz PCI ATM 155 UTP"; +static const char pci_device_1014_01e6[] = "Cryptographic Accelerator"; +static const char pci_device_1014_01ff[] = "10/100 Mbps Ethernet"; +static const char pci_device_1014_0219[] = "Multiport Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_021a[] = "Dual RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0251[] = "Internal Modem/RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0252[] = "Quad Internal Modem"; +#endif +static const char pci_device_1014_021b[] = "GXT6500P Graphics Adapter"; +static const char pci_device_1014_021c[] = "GXT4500P Graphics Adapter"; +static const char pci_device_1014_0233[] = "GXT135P Graphics Adapter"; +static const char pci_device_1014_0266[] = "PCI-X Dual Channel SCSI"; +static const char pci_device_1014_0268[] = "Gigabit Ethernet-SX Adapter (PCI-X)"; +static const char pci_device_1014_0269[] = "10/100/1000 Base-TX Ethernet Adapter (PCI-X)"; +static const char pci_device_1014_028c[] = "Citrine chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_028d[] = "Dual Channel PCI-X DDR SAS RAID Adapter (572E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02be[] = "Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02c0[] = "Dual Channel PCI-X DDR U320 SCSI Adapter (571A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_030d[] = "PCI-X DDR Auxiliary Cache Adapter (575B)"; +#endif +static const char pci_device_1014_02a1[] = "Calgary PCI-X Host Bridge"; +static const char pci_device_1014_0302[] = "Winnipeg PCI-X Host Bridge"; +static const char pci_device_1014_0314[] = "ZISC 036 Neural accelerator card"; +static const char pci_device_1014_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_4022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_0009[] = "MegaRAID 428 Ultra RAID Controller (rev 03)"; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500/500LC RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0477[] = "MegaRAID 477 Elite 3100 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0494[] = "MegaRAID 494 Elite 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0503[] = "MegaRAID 503 Enterprise 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0511[] = "MegaRAID 511 i4 IDE RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0522[] = "MegaRAID 522 i4133 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_103c_60e7[] = "NetRAID-1M"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 [Athlon64/Opteron] HyperTransport Technology Configuration"; +static const char pci_device_1022_1101[] = "K8 [Athlon64/Opteron] Address Map"; +static const char pci_device_1022_1102[] = "K8 [Athlon64/Opteron] DRAM Controller"; +static const char pci_device_1022_1103[] = "K8 [Athlon64/Opteron] Miscellaneous Control"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1022_2000[] = "PCnet - Fast 79C971"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2702[] = "AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2703[] = "AT-2701FX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2003[] = "Am 1771 MBW [Alchemy]"; +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_208f[] = "CS5536 GeodeLink PCI South Bridge"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700a[] = "AMD-IGR4 AGP Host to PCI Bridge"; +static const char pci_device_1022_700b[] = "AMD-IGR4 PCI to PCI Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X IOAPIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7458[] = "AMD-8132 PCI-X Bridge"; +static const char pci_device_1022_7459[] = "AMD-8132 PCI-X IOAPIC"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7460_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7464_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7468_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_1022_2b80[] = "AMD-8111 IDE [Quartet]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746b_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746d_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_device_1022_756b[] = "AMD-8111 ACPI"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_2001_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +#endif +static const char pci_device_1023_2100[] = "CyberBlade XP4m32"; +static const char pci_device_1023_2200[] = "XGI Volari XP5"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad R30/T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_1025[] = "Travelmate 352TE"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_1671[] = "M1671 Northbridge [ALADDiN-P4]"; +static const char pci_device_1025_1672[] = "Northbridge [CyberALADDiN-P4]"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge 2400"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge 4400"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge 2450"; +#endif +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Access Card III"; +static const char pci_device_1028_0008[] = "Remote Access Card III"; +static const char pci_device_1028_0009[] = "Remote Access Card III: BMC/SMIC device not present"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000c[] = "Embedded Remote Access or ERA/O"; +static const char pci_device_1028_000d[] = "Embedded Remote Access: BMC/SMIC device"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_0010[] = "Remote Access Card 4"; +static const char pci_device_1028_0011[] = "Remote Access Card 4 Daughter Card"; +static const char pci_device_1028_0012[] = "Remote Access Card 4 Daughter Card Virtual UART"; +static const char pci_device_1028_0013[] = "PowerEdge Expandable RAID controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016c[] = "PowerEdge Expandable RAID Controller 4e/Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016d[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016e[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016f[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_0170[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +static const char pci_device_1028_0014[] = "Remote Access Card 4 Daughter Card SMIC interface"; +static const char pci_device_1028_0015[] = "PowerEdge Expandable RAID controller 5"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +static const char pci_device_102a_001f[] = "AHA-2940U2/U2W /7890/7891 SCSI Controllers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_0106[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_102a_00c5[] = "AIC-7899 U160/m SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00c5_1028_00c5[] = "PowerEdge 2550/2650/4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_102a_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0106[] = "PowerEdge 4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0121[] = "PowerEdge 2650"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0100[] = "MGA 1064SG [Mystique]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0525[] = "G400/G450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d43[] = "Millennium G450 32Mb Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0850[] = "Parhelia 256MB AGP 4X"; +#endif +static const char pci_device_102b_0528[] = "Parhelia 8X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1020[] = "Parhelia 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1030[] = "Parhelia 256 MB Dual DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_14e1[] = "Parhelia PCI 256MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_2021[] = "QID Pro"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_2537[] = "Millenium P650/P750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1820[] = "Millennium P750 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1830[] = "Millennium P650 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1c10[] = "QID 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2811[] = "Millennium P650 Low-profile PCI 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2c11[] = "QID Low-profile PCI"; +#endif +static const char pci_device_102b_2538[] = "Millenium P650 PCIe"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_08c7[] = "Millennium P650 PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_0907[] = "Millennium P650 PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1047[] = "Millennium P650 LP PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1087[] = "Millennium P650 LP PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_2538[] = "Parhelia APVe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_3007[] = "QID Low-profile PCIe"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_000a[] = "TX3927 MIPS RISC PCI Controller"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +static const char pci_device_102f_0030[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller"; +static const char pci_device_102f_0031[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL"; +static const char pci_device_102f_0105[] = "TC86C001 [goku-s] IDE"; +static const char pci_device_102f_0106[] = "TC86C001 [goku-s] USB 1.1 Host"; +static const char pci_device_102f_0107[] = "TC86C001 [goku-s] USB Device Controller"; +static const char pci_device_102f_0108[] = "TC86C001 [goku-s] I2C/SIO/GPIO Controller"; +static const char pci_device_102f_0180[] = "TX4927/38 MIPS RISC PCI Controller"; +static const char pci_device_102f_0181[] = "TX4925 MIPS RISC PCI Controller"; +static const char pci_device_102f_0182[] = "TX4937 MIPS RISC PCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0000[] = "Vr4181A USB Host or Function Control Unit"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1033_0035[] = "Hama USB 2.0 CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_14c2_0105[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000a[] = "GlobeTrotter Fusion Quad Lite (PPP data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000b[] = "GlobeTrotter Fusion Quad Lite (GSM data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_807d_0035[] = "PCI-USB2 (OHCI subsystem)"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0072[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a5[] = "VRC4173"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00ce[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00df[] = "Vr4131"; +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_14c2_0205[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_807d_1043[] = "PCI-USB2 (EHCI subsystem)"; +#endif +static const char pci_device_1033_00e7[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00f2[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_00f3[] = "uPD6113x Multimedia Decoder/Processor [EMMA2]"; +static const char pci_device_1033_010c[] = "VR7701"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0003[] = "SiS AGP Port (virtual PCI-to-PCI bridge)"; +static const char pci_device_1039_0004[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_000a[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0016[] = "SiS961/2 SMBus Controller"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0180[] = "RAID bus controller 180 SATA/PATA [SiS]"; +static const char pci_device_1039_0181[] = "SATA"; +static const char pci_device_1039_0182[] = "182 SATA/RAID Controller"; +static const char pci_device_1039_0191[] = "191 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0550[] = "550 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0648[] = "645xx"; +static const char pci_device_1039_0650[] = "650/M650 Host"; +static const char pci_device_1039_0651[] = "651 Host"; +static const char pci_device_1039_0655[] = "655 Host"; +static const char pci_device_1039_0660[] = "660 Host"; +static const char pci_device_1039_0661[] = "661FX/M661FX/M661MX Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0741[] = "741/741GX/M741 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0746[] = "746 Host"; +static const char pci_device_1039_0755[] = "755 Host"; +static const char pci_device_1039_0760[] = "760/M760 Host"; +static const char pci_device_1039_0761[] = "761/M761 Host"; +static const char pci_device_1039_0900[] = "SiS900 PCI Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_0963[] = "SiS963 [MuTIOL Media IO]"; +static const char pci_device_1039_0964[] = "SiS964 [MuTIOL Media IO]"; +static const char pci_device_1039_0965[] = "SiS965 [MuTIOL Media IO]"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "550 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "630/730 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_6306[] = "530/620 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "65x/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_6330[] = "661/741/760/761 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6330_1039_6330[] = "[M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter"; +#endif +static const char pci_device_1039_7001[] = "USB 1.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1462_5470[] = "K7SOM+ 5.2C Motherboard"; +#endif +static const char pci_device_1039_7002[] = "USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "Sound Controller"; +static const char pci_device_1039_7013[] = "AC'97 Modem Controller"; +static const char pci_device_1039_7016[] = "SiS7016 PCI Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +static const char pci_device_1039_7019[] = "SiS7019 Audio Accelerator"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1006[] = "Visualize FX6"; +static const char pci_device_103c_1008[] = "Visualize FX4"; +static const char pci_device_103c_100a[] = "Visualize FX2"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Superdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1301[] = "Diva RMP3"; +#endif +static const char pci_device_103c_1054[] = "PCI Local Bus Adapter"; +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_10f0[] = "rio System Bus Adapter"; +static const char pci_device_103c_10f1[] = "rio I/O Controller"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "zx1 Local Bus Adapter"; +static const char pci_device_103c_127c[] = "sx1000 I/O Controller"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_1291[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_12b4[] = "zx1 QuickSilver AGP8x Local Bus Adapter"; +static const char pci_device_103c_12fa[] = "BCM4306 802.11b/g Wireless LAN Controller"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +static const char pci_device_103c_3080[] = "Pavilion ze2028ea"; +static const char pci_device_103c_3220[] = "Hewlett-Packard Smart Array P600"; +static const char pci_device_103c_3230[] = "Hewlett-Packard Smart Array Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "PC Tech RZ1000"; +static const char pci_device_1042_1001[] = "PC Tech RZ1001"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "ASUSTeK Computer Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_10cf_105e[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1043_4015[] = "v7100 SDRAM [GeForce2 MX]"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +static const char pci_device_1043_4057[] = "v8200 GeForce 3"; +static const char pci_device_1043_8043[] = "v8240 PAL 128M [P4T] Motherboard"; +static const char pci_device_1043_807b[] = "v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI]"; +static const char pci_device_1043_80bb[] = "v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out]"; +static const char pci_device_1043_80c5[] = "nForce3 chipset motherboard [SK8N]"; +static const char pci_device_1043_80df[] = "v9520 Magic/T"; +static const char pci_device_1043_8187[] = "802.11a/b/g Wireless LAN Card"; +static const char pci_device_1043_8188[] = "Tiger Hybrid TV Capture Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Adaptec (formerly DPT)"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3410S Ultra160 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c032[] = "ASR-2005S I2O Zero Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c035[] = "ASR-2010S I2O Zero Channel"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCIAudio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0c60[] = "Gladiac MX"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +static const char pci_device_1048_8901[] = "Gloria XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1048_8901_1048_0935[] = "GLoria XL (Virge)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "STMicroelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0209[] = "STPC Consumer/Industrial North- and Southbridge"; +static const char pci_device_104a_020a[] = "STPC Atlas/ConsumerS/Consumer IIA Northbridge"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_021a[] = "STPC Consumer S Southbridge"; +static const char pci_device_104a_021b[] = "STPC Consumer IIA Southbridge"; +static const char pci_device_104a_0500[] = "ST70137 [Unicorn] ADSL DMT Transceiver"; +static const char pci_device_104a_0564[] = "STPC Client Northbridge"; +static const char pci_device_104a_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +static const char pci_device_104a_55cc[] = "STPC Client Southbridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a34[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a36[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a43[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a44[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_000f[] = "Studio DV500-1394"; +#endif +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_1043_808b[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8025[] = "TSB82AA2 IEEE-1394b Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8025_1458_1000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1043_808d[] = "A7V333 mainboard."; +#endif +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8029[] = "PCI4510 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1071_8160[] = "MIM2900"; +#endif +static const char pci_device_104c_802b[] = "PCI7410,7510,7610 OHCI-Lynx Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_014e[] = "PCI7410,7510,7610 OHCI-Lynx Controller (Dell Latitude D800)"; +#endif +static const char pci_device_104c_802e[] = "PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller"; +static const char pci_device_104c_8031[] = "PCIxx21/x515 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8032[] = "OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8033[] = "PCIxx21 Integrated FlashMedia Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8034[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8035[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Smart Card Controller (SMC)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8035_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_104c_8036[] = "PCI6515 Cardbus Controller"; +static const char pci_device_104c_8038[] = "PCI6515 SmartCard Controller"; +static const char pci_device_104c_8201[] = "PCI1620 Firmware Loading Function"; +static const char pci_device_104c_8204[] = "PCI7410,7510,7610 PCI Firmware Loading Function"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b00[] = "DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b01[] = "DWL-520+ 22Mbps PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_16ab_8501[] = "WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter"; +#endif +static const char pci_device_104c_8401[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_9000[] = "Wireless Interface (of unknown type)"; +static const char pci_device_104c_9066[] = "ACX 111 54Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_104c_9066[] = "Microcom Travel Card WiFi 11g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b04[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b05[] = "DWL-G650+ AirPlusG+ CardBus Wireless LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_13d1_aba0[] = "SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+"; +#endif +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6414 TMS320C6415 TMS320C6416"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_5000[] = "ASI50xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_6400[] = "ASI6400 Cobranet series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_8700[] = "ASI87xx Radio Tuner card"; +#endif +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac16_1014_0092[] = "ThinkPad 600"; +#endif +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_1014_0130[] = "Thinkpad T20/T22/A21m"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_0e11_b121[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_1028_0088[] = "Latitude CPi A400XT"; +#endif +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_ac44[] = "PCI4510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_104c_ac46[] = "PCI4520 PC card Cardbus Controller"; +static const char pci_device_104c_ac47[] = "PCI7510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac4a[] = "PCI7510,7610 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_0e11_004e[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_00b1[] = "Latitude C600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1033_80cd[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1095_10cf[] = "Fujitsu-Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook S-4510/C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac54[] = "PCI1620 PC Card Controller"; +static const char pci_device_104c_ac55[] = "PCI1520 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30/T40"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0528[] = "ThinkPad R40e (2684-HVG) Cardbus Controller"; +#endif +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_5100[] = "ASI51xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6100[] = "ASI61xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6200[] = "ASI62xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_8800[] = "ASI88xx Audio Adapter"; +#endif +static const char pci_device_104c_ac8d[] = "PCI 7620"; +static const char pci_device_104c_ac8e[] = "PCI7420 CardBus Controller"; +static const char pci_device_104c_ac8f[] = "PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8004[] = "DTL-H2500 [Playstation development board]"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1050_9921[] = "W99200F MPEG-1 Video Encoder"; +static const char pci_device_1050_9922[] = "W99200F/W9922PF MPEG-1/2 Video Encoder"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0008[] = "MPC8540"; +static const char pci_device_1057_0009[] = "MPC8560"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "DSP56301 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0101[] = "Transas Radar Imitator Board [RIM]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0102[] = "Transas Radar Imitator Board [RIM-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0202[] = "Transas Radar Integrator Board [RIB-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0611[] = "1 channel CAN bus Controller [CanPci-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0612[] = "2 channels CAN bus Controller [CanPci-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0613[] = "3 channels CAN bus Controller [CanPci-3]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0614[] = "4 channels CAN bus Controller [CanPci-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0621[] = "1 channel CAN bus Controller [CanPci2-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0622[] = "2 channels CAN bus Controller [CanPci2-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0810[] = "Transas VTS Radar Integrator Board [RIB-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4200[] = "ASI4215 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4300[] = "ASI43xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4400[] = "ASI4401 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0010[] = "Darla"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0020[] = "Gina"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0031[] = "Layla rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0040[] = "Darla24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0041[] = "Darla24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0072[] = "Mona rev.2"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/8266/8272"; +static const char pci_device_1057_18c1[] = "MPC8271/MPC8272"; +static const char pci_device_1057_3410[] = "DSP56361 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0060[] = "Layla24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0072[] = "Mona rev.2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0080[] = "Mia rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0081[] = "Mia rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0090[] = "Indigo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00a0[] = "Indigo IO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00b0[] = "Indigo DJ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0100[] = "3G"; +#endif +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_5803[] = "MPC5200"; +static const char pci_device_1057_5806[] = "MCF54 Coldfire"; +static const char pci_device_1057_5808[] = "MPC8220"; +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +static const char pci_device_1057_6405[] = "MPC184 Security Processor (S1 family)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "PDC20265 (FastTrak100 Lite/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3318[] = "PDC20318 (SATA150 TX4)"; +static const char pci_device_105a_3319[] = "PDC20319 (FastTrak S150 TX4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3319_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_105a_3371[] = "PDC20371 (FastTrak S150 TX2plus)"; +static const char pci_device_105a_3373[] = "PDC20378 (FastTrak 378/SATA 378)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1043_80f5[] = "K8V Deluxe/PC-DL Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1462_702e[] = "K8T NEO FIS2R motherboard"; +#endif +static const char pci_device_105a_3375[] = "PDC20375 (SATA150 TX2plus)"; +static const char pci_device_105a_3376[] = "PDC20376 (FastTrak 376)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3376_1043_809e[] = "A7V8X motherboard"; +#endif +static const char pci_device_105a_3515[] = "PDC40719"; +static const char pci_device_105a_3519[] = "PDC40519 (FastTrak TX4200)"; +static const char pci_device_105a_3571[] = "PDC20571 (FastTrak TX2200)"; +static const char pci_device_105a_3574[] = "PDC20579 SATAII 150 IDE Controller"; +static const char pci_device_105a_3577[] = "PDC40779 (SATA 300 779)"; +static const char pci_device_105a_3d17[] = "PDC20718 (SATA 300 TX4)"; +static const char pci_device_105a_3d18[] = "PDC20518/PDC40518 (SATAII 150 TX4)"; +static const char pci_device_105a_3d73[] = "PDC40775 (SATA 300 TX2plus)"; +static const char pci_device_105a_3d75[] = "PDC20575 (SATAII150 TX2plus)"; +static const char pci_device_105a_4d30[] = "PDC20267 (FastTrak100/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "FastTrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "PDC20262 (FastTrak66/Ultra66)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "FastTrak66"; +#endif +static const char pci_device_105a_4d68[] = "PDC20268 (Ultra100 TX2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d69_105a_4d68[] = "Ultra133TX2"; +#endif +static const char pci_device_105a_5275[] = "PDC20276 (MBFastTrak133 Lite)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1043_807e[] = "A7V333 motherboard."; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_1275[] = "MBFastTrak133 Lite (tm) Controller (RAID mode)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1458_b001[] = "MBUltra 133"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "PDC20270 (FastTrak100 LP/TX2/TX4)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6268_105a_4d68[] = "FastTrak100 TX2"; +#endif +static const char pci_device_105a_6269[] = "PDC20271 (FastTrak TX2000)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite)"; +static const char pci_device_105a_6622[] = "PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_6624[] = "PDC20621 [FastTrak SX4100]"; +static const char pci_device_105a_6626[] = "PDC20618 (Ultra 618)"; +static const char pci_device_105a_6629[] = "PDC20619 (FastTrak TX4000)"; +static const char pci_device_105a_7275[] = "PDC20277 (SBFastTrak133 Lite)"; +static const char pci_device_105a_8002[] = "SATAII150 SX8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_105d_0037[] = "Revolution IV-FP AGP (For SGI 1600SW)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_1067_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_1067_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PG"; +static const char pci_device_1069_0020[] = "DAC960LA"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0050[] = "AcceleRAID 352 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0052[] = "AcceleRAID 170 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0054[] = "AcceleRAID 160 support Device"; +#endif +static const char pci_device_1069_b166[] = "AcceleRAID 600/500/400/Sapphire support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0242[] = "iSeries 2872 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0266[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0278[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d3[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d4[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0200[] = "AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0202[] = "AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0204[] = "AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0206[] = "AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0030[] = "eXtremeRAID 3000 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0040[] = "eXtremeRAID 2000 support Device"; +#endif +static const char pci_device_1069_ba57[] = "eXtremeRAID 4000/5000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba57_1069_0072[] = "eXtremeRAID 5000 support Device"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000c[] = "DOS on Mac"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_106b_0031_106b_5811[] = "iBook G4 2004"; +#endif +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_0035[] = "UniNorth 2 PCI"; +static const char pci_device_106b_0036[] = "UniNorth 2 Internal PCI"; +static const char pci_device_106b_003b[] = "UniNorth/Intrepid ATA/100"; +static const char pci_device_106b_003e[] = "KeyLargo/Intrepid Mac I/O"; +static const char pci_device_106b_003f[] = "KeyLargo/Intrepid USB"; +static const char pci_device_106b_0040[] = "K2 KeyLargo USB"; +static const char pci_device_106b_0041[] = "K2 KeyLargo Mac/IO"; +static const char pci_device_106b_0042[] = "K2 FireWire"; +static const char pci_device_106b_0043[] = "K2 ATA/100"; +static const char pci_device_106b_0045[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0046[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0047[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0048[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0049[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_004b[] = "U3 AGP"; +static const char pci_device_106b_004c[] = "K2 GMAC (Sun GEM)"; +static const char pci_device_106b_004f[] = "Shasta Mac I/O"; +static const char pci_device_106b_0050[] = "Shasta IDE"; +static const char pci_device_106b_0051[] = "Shasta (Sun GEM)"; +static const char pci_device_106b_0052[] = "Shasta Firewire"; +static const char pci_device_106b_0053[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0054[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0055[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0058[] = "U3L AGP Bridge"; +static const char pci_device_106b_0059[] = "U3H AGP Bridge"; +static const char pci_device_106b_0066[] = "Intrepid2 AGP Bridge"; +static const char pci_device_106b_0067[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0068[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0069[] = "Intrepid2 ATA/100"; +static const char pci_device_106b_006a[] = "Intrepid2 Firewire"; +static const char pci_device_106b_006b[] = "Intrepid2 GMAC (Sun GEM)"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hynix Semiconductor"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +static const char pci_device_1071_8160[] = "Mitac 8060B Mobile Platform"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280 SCSI Host Adapter"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2200_1077_0002[] = "QLA2200"; +#endif +static const char pci_device_1077_2300[] = "QLA2300 64-bit Fibre Channel Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +static const char pci_device_1077_2322[] = "QLA2322 Fibre Channel Adapter"; +static const char pci_device_1077_2422[] = "QLA2422 Fibre Channel Adapter"; +static const char pci_device_1077_2432[] = "QLA2432 Fibre Channel Adapter"; +static const char pci_device_1077_3010[] = "QLA3010 Network Adapter"; +static const char pci_device_1077_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1077_4010[] = "QLA4010 iSCSI TOE Adapter"; +static const char pci_device_1077_4022[] = "QLA4022 iSCSI TOE Adapter"; +static const char pci_device_1077_6312[] = "QLA6312 Fibre Channel Adapter"; +static const char pci_device_1077_6322[] = "QLA6322 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +static const char pci_device_107d_2134[] = "WinFast 3D S320 II"; +static const char pci_device_107d_2971[] = "[GeForce FX 5900] WinFast A350 TDH MyViVo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_1648[] = "[bge] Gigabit Ethernet"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_8002[] = "Schizo+ PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +static const char pci_device_108e_a801[] = "Tomatillo PCI Bus Module"; +static const char pci_device_108e_abba[] = "Cassini 10/100/1000"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Compro Computer Services, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +static const char pci_device_1091_07a0[] = "Sun Expert3D-Lite Graphics Accelerator"; +static const char pci_device_1091_1091[] = "Sun Expert3D Graphics Accelerator"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1310[] = "PCI-6602"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_14e0[] = "PCI-6110"; +static const char pci_device_1093_14f0[] = "PCI-6111"; +static const char pci_device_1093_17d0[] = "PCI-6503"; +static const char pci_device_1093_1870[] = "PCI-6713"; +static const char pci_device_1093_1880[] = "PCI-6711"; +static const char pci_device_1093_18b0[] = "PCI-6052E"; +static const char pci_device_1093_2410[] = "PCI-6733"; +static const char pci_device_1093_2890[] = "PCI-6036E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_2a70[] = "PCI-6024E"; +static const char pci_device_1093_2a80[] = "PCI-6025E"; +static const char pci_device_1093_2c80[] = "PCI-6035E"; +static const char pci_device_1093_2ca0[] = "PCI-6034E"; +static const char pci_device_1093_70b8[] = "PCI-6251 [M Series - High Speed Multifunction DAQ]"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "Silicon Image, Inc."; +static const char pci_device_1095_0240[] = "Adaptec AAR-1210SA SATA HostRAID Controller"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +static const char pci_device_1095_0649[] = "SiI 0649 Ultra ATA/100 PCI to ATA Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680 Ultra ATA-133 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0680_1095_3680[] = "Winic W-680 (Silicon Image 680 based)"; +#endif +static const char pci_device_1095_3112[] = "SiI 3112 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_3112[] = "SiI 3112 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_6112[] = "SiI 3112 SATARaid Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_9005_0250[] = "SATAConnect 1205SA Host Controller"; +#endif +static const char pci_device_1095_3114[] = "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_3114[] = "SiI 3114 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_6114[] = "SiI 3114 SATARaid Controller"; +#endif +static const char pci_device_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3124_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#endif +static const char pci_device_1095_3132[] = "SiI 3132 Serial ATA Raid II Controller"; +static const char pci_device_1095_3512[] = "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_3512[] = "SiI 3512 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_6512[] = "SiI 3512 SATARaid Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_032e[] = "Bt878 Video Capture"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0002[] = "TV98 Series (TV/No FM/Remote)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0003[] = "AverMedia UltraTV PCI 350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0761[] = "AverTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1822_0001[] = "VisionPlus DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0002[] = "Avermedia PCTV98 Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0761[] = "AVerTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1822_0001[] = "VisionPlus DVB Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_3052[] = "SmartPCI562 56K Modem"; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10a9_0009_10a9_8002[] = "AceNIC Gigabit Ethernet"; +#endif +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_100a[] = "IOC4 I/O controller"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_4001[] = "TIO-CE PCI Express Bridge"; +static const char pci_device_10a9_4002[] = "TIO-CE PCI Express Port"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +static const char pci_device_10a9_8010[] = "Broadcom e-net [SGI IO9/IO10 BaseIO]"; +static const char pci_device_10a9_8018[] = "Broadcom e-net [SGI A330 Server BaseIO]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1042[] = "Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2540[] = "IXXAT CAN-Interface PC-I 04/PCI"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_6540[] = "PCI6540/6466 PCI-PCI bridge (transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6540_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6541[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6541_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6542[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6542_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_8111[] = "PEX 8111 PCI Express-to-PCI Bridge"; +static const char pci_device_10b5_8114[] = "PEX 8114 PCI Express-to-PCI/PCI-X Bridge"; +static const char pci_device_10b5_8516[] = "PEX 8516 Versatile PCI Express Switch"; +static const char pci_device_10b5_8532[] = "PEX 8532 Versatile PCI Express Switch"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2862[] = "Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2906[] = "Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2940[] = "Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2977[] = "IXXAT iPC-I XC16/PCI CAN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2978[] = "SH ARC-PCIu SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3025[] = "Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3068[] = "Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3136[] = "4xS0-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3137[] = "S2M-E1-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1518_0200[] = "Kontron ThinkIO-C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1067[] = "IXXAT CAN i165"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1172[] = "IK220 (Heidenhain)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2221[] = "Alpermann+Velte PCL PCI LV: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH ARC-PCI SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2431[] = "Alpermann+Velte PCL PCI D: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2905[] = "Alpermann+Velte PCI TS: Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "MP9050"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1498_0362[] = "TPMC866 8 Channel Serial Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_2036[] = "OpenSwitch 6 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_3132[] = "OpenSwitch 12 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2696[] = "Innes Corp AM Radcap card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2717[] = "Innes Corp Auricon card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2844[] = "Innes Corp TVS Encoder card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12c7_4001[] = "Intel Dialogic DM/V960-4T1 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12d9_0002[] = "PCI Prosody Card rev 1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0011[] = "PIKA PrimeNet MM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0012[] = "PIKA PrimeNet MM cPCI 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0013[] = "PIKA PrimeNet MM cPCI 8 (without CAS Signaling)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0014[] = "PIKA PrimeNet MM cPCI 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0015[] = "PIKA Daytona MM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0016[] = "PIKA InLine MM"; +#endif +static const char pci_device_10b5_9056[] = "Francois"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9056_10b5_2979[] = "CellinkBlade 11 - CPCI board VoATM AAL1"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10eb[] = "(Agilent) E2777B 83K Series Optical Communication Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10ec[] = "(Agilent) E6978-66442 PCI CIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12d9_0002[] = "PCI Prosody Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12df_4422[] = "4422PCI [Do-All Telemetry Data Aquisition System]"; +#endif +static const char pci_device_10b5_bb04[] = "B&B 3PCIOSD1A Isolated PCI Serial"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_0013[] = "AR5212 802.11abg NIC (3CRDAG675)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_0013_10b7_2031[] = "3CRDAG675 11a/b/g Wireless PCI Adapter"; +#endif +static const char pci_device_10b7_0910[] = "3C910-A01"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +static const char pci_device_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +static const char pci_device_10b7_1700[] = "3c940 10/100/1000Base-T [Marvell]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_1043_80eb[] = "A7V600/P4P800/K8V motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0010[] = "3C940 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0020[] = "3C941 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 HomePNA [Tornado]"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3cCFE575CT CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6000[] = "3CRSHPW796 [OfficeConnect Wireless CardBus]"; +static const char pci_device_10b7_6001[] = "3com 3CRWE154G72 [Office Connect Wireless LAN Adapter]"; +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus [Cyclone]"; +static const char pci_device_10b7_6056[] = "3c556B CardBus [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3cCFE656 CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3cCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3cCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado]"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7770[] = "3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect]"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_80eb[] = "3c940B 10/100/1000Base-T"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 10Mbps Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC Etherlink XL [Cyclone]"; +static const char pci_device_10b7_900a[] = "3c900B-FL 10base-FL [Cyclone]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 Fast EtherLink XL [Cyclone]"; +static const char pci_device_10b7_9058[] = "3c905B Deluxe Etherlink 10/100/BNC [Cyclone]"; +static const char pci_device_10b7_905a[] = "3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0097[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_00fe[] = "Optiplex GX240"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_012a[] = "3C920 Integrated Fast Ethernet Controller [Latitude C640]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10f1_2466[] = "Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller)"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9201_1043_80ab[] = "A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller"; +#endif +static const char pci_device_10b7_9202[] = "3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9210[] = "3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX 910-A01 [tulip]"; +static const char pci_device_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-C 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "EtherLink Server 10/100 Dual Port A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "EtherLink Server 10/100 Dual Port B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990a[] = "3C990SVR [Typhoon Server]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83c170 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "83c175 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_2802[] = "SMC2802W [EZ Connect g]"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0101[] = "CMI8338/C3DX PCI Audio Device"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_0780[] = "Multi-IO Card"; +static const char pci_device_10b9_0782[] = "Multi-IO Card"; +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_1014_053b[] = "ThinkPad R40e (2684-HVG) PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALi M1533 Aladdin IV/V ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1573[] = "PCI to LPC Controller"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1672[] = "M1672 Northbridge [CyberALADDiN-P4]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_1689[] = "M1689 K8 Northbridge [Super K8 Single Chip]"; +static const char pci_device_10b9_1695[] = "M1695 K8 Northbridge [PCI Express and HyperTransport]"; +static const char pci_device_10b9_1697[] = "M1697 HTT Host Bridge"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_3323[] = "M3325 Video/Audio Decoder"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5228[] = "M5228 ALi ATA/RAID Controller"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_050f[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_053d[] = "ThinkPad R40e (2684-HVG) builtin IDE"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_103c_0024[] = "Pavilion ze4400 builtin IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_1014_0540[] = "ThinkPad R40e (2684-HVG) builtin USB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_103c_0024[] = "Pavilion ze4400 builtin USB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_104d_810f[] = "VAIO PCG-U1 USB/OHCI Revision 1.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5246[] = "AGP8X Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_524b[] = "PCI Express Root Port"; +static const char pci_device_10b9_524c[] = "PCI Express Root Port"; +static const char pci_device_10b9_524d[] = "PCI Express Root Port"; +static const char pci_device_10b9_524e[] = "PCI Express Root Port"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5263[] = "M5263 Ethernet Controller"; +static const char pci_device_10b9_5281[] = "ALi M5281 Serial ATA / RAID Host Controller"; +static const char pci_device_10b9_5287[] = "ULi 5287 SATA"; +static const char pci_device_10b9_5288[] = "ULi M5288 SATA"; +static const char pci_device_10b9_5289[] = "ULi 5289 SATA"; +static const char pci_device_10b9_5450[] = "Lucent Technologies Soft Modem AMR"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_053e[] = "ThinkPad R40e (2684-HVG) builtin Audio"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_103c_0024[] = "Pavilion ze4400 builtin Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_10b9_5451[] = "HP Compaq nc4010 (DY885AA#ABN)"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "M5457 AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_1014_0535[] = "ThinkPad R40e (2684-HVG) builtin modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_103c_0024[] = "Pavilion ze4400 builtin Modem Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5461[] = "High Definition Audio/AC'97 Host Controller"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 Power Management Controller [PMU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_0510[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_053c[] = "ThinkPad R40e (2684-HVG) Power Management Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_103c_0024[] = "Pavilion ze4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_10ba_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1028_0088[] = "Latitude CPi A"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_0088[] = "Latitude CPi A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mai Logic Incorporated"; +static const char pci_device_10cc_0660[] = "Articia S Host Bridge"; +static const char pci_device_10cc_0661[] = "Articia S PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Fujitsu Limited."; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0431[] = "MX98715"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8626[] = "Macronix MX86251 + 3Dfx Voodoo Rush"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +static const char pci_device_10dd_0100[] = "Lightning 1200"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c19[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1c[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c21[] = "Synergy II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c28[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c29[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2a[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2b[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c31[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c32[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c33[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c34[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_107d_2134[] = "WinFast 3D S320 II + TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2e[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2f[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c30[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c20[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c21[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3b[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "Pixelview RIVA TNT2 M64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1569_002d[] = "Palit Microsystems Daytona TNT2 M64"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0034[] = "MCP04 SMBus"; +static const char pci_device_10de_0035[] = "MCP04 IDE"; +static const char pci_device_10de_0036[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0037[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_0038[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_003a[] = "MCP04 AC'97 Audio Controller"; +static const char pci_device_10de_003b[] = "MCP04 USB Controller"; +static const char pci_device_10de_003c[] = "MCP04 USB Controller"; +static const char pci_device_10de_003d[] = "MCP04 PCI Bridge"; +static const char pci_device_10de_003e[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0040[] = "nv40 [GeForce 6800 Ultra]"; +static const char pci_device_10de_0041[] = "NV40 [GeForce 6800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0041_1043_817b[] = "V9999 Gamer Edition"; +#endif +static const char pci_device_10de_0042[] = "NV40.2 [GeForce 6800 LE]"; +static const char pci_device_10de_0043[] = "NV40.3"; +static const char pci_device_10de_0045[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0046[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0048[] = "GeForce 6800 XT"; +static const char pci_device_10de_0049[] = "NV40GL"; +static const char pci_device_10de_004e[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_0050[] = "CK804 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0051[] = "CK804 ISA Bridge"; +static const char pci_device_10de_0052[] = "CK804 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0053[] = "CK804 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1458_5002[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0054[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0055[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1043_815a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_0056[] = "CK804 Ethernet Controller"; +static const char pci_device_10de_0057[] = "CK804 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1043_8141[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1458_e000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0058[] = "CK804 AC'97 Modem"; +static const char pci_device_10de_0059[] = "CK804 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_1043_812a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_005a[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005b[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005c[] = "CK804 PCI Bridge"; +static const char pci_device_10de_005d[] = "CK804 PCIE Bridge"; +static const char pci_device_10de_005e[] = "CK804 Memory Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1458_5000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005f[] = "CK804 Memory Controller"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +static const char pci_device_10de_0065[] = "nForce2 IDE"; +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0066_1043_80a7[] = "A7N8X Mainboard onboard nForce2 Ethernet"; +#endif +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +static const char pci_device_10de_006b[] = "nForce Audio Processing Unit"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006b_10de_006b[] = "nForce2 MCP Audio Processing Unit"; +#endif +static const char pci_device_10de_006c[] = "nForce2 External PCI Bridge"; +static const char pci_device_10de_006d[] = "nForce2 PCI Bridge"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +static const char pci_device_10de_0080[] = "MCP2A ISA bridge"; +static const char pci_device_10de_0084[] = "MCP2A SMBus"; +static const char pci_device_10de_0085[] = "MCP2A IDE"; +static const char pci_device_10de_0086[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_0087[] = "MCP2A USB Controller"; +static const char pci_device_10de_0088[] = "MCP2A USB Controller"; +static const char pci_device_10de_008a[] = "MCP2S AC'97 Audio Controller"; +static const char pci_device_10de_008b[] = "MCP2A PCI Bridge"; +static const char pci_device_10de_008c[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_008e[] = "nForce2 Serial ATA Controller"; +static const char pci_device_10de_0091[] = "GeForce 7800 GTX"; +static const char pci_device_10de_0092[] = "GeForce 7800 GT"; +static const char pci_device_10de_0099[] = "GeForce Go 7800 GTX"; +static const char pci_device_10de_009d[] = "Quadro FX 4500"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_00c0[] = "NV41.0"; +static const char pci_device_10de_00c1[] = "NV41.1 [GeForce 6800]"; +static const char pci_device_10de_00c2[] = "NV41.2 [GeForce 6800 LE]"; +static const char pci_device_10de_00c3[] = "GeForce 6800 XT"; +static const char pci_device_10de_00c8[] = "NV41.8 [GeForce Go 6800]"; +static const char pci_device_10de_00c9[] = "NV41.9 [GeForce Go 6800 Ultra]"; +static const char pci_device_10de_00cc[] = "NV41 [Quadro FX Go1400]"; +static const char pci_device_10de_00cd[] = "NV41 [Quadro FX 3450/4000 SDI]"; +static const char pci_device_10de_00ce[] = "NV41GL [Quadro FX 1400]"; +static const char pci_device_10de_00d0[] = "nForce3 LPC Bridge"; +static const char pci_device_10de_00d1[] = "nForce3 Host Bridge"; +static const char pci_device_10de_00d2[] = "nForce3 AGP Bridge"; +static const char pci_device_10de_00d3[] = "CK804 Memory Controller"; +static const char pci_device_10de_00d4[] = "nForce3 SMBus"; +static const char pci_device_10de_00d5[] = "nForce3 IDE"; +static const char pci_device_10de_00d6[] = "nForce3 Ethernet"; +static const char pci_device_10de_00d7[] = "nForce3 USB 1.1"; +static const char pci_device_10de_00d8[] = "nForce3 USB 2.0"; +static const char pci_device_10de_00d9[] = "nForce3 Audio"; +static const char pci_device_10de_00da[] = "nForce3 Audio"; +static const char pci_device_10de_00dd[] = "nForce3 PCI Bridge"; +static const char pci_device_10de_00df[] = "CK8S Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e0[] = "nForce3 250Gb LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e1[] = "nForce3 250Gb Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e2[] = "nForce3 250Gb AGP Host to PCI Bridge"; +static const char pci_device_10de_00e3[] = "CK8S Serial ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e4[] = "nForce 250Gb PCI System Management"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e5[] = "CK8S Parallel ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e6[] = "CK8S Ethernet Controller"; +static const char pci_device_10de_00e7[] = "CK8S USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e8[] = "nForce3 EHCI USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ea[] = "nForce3 250Gb AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ed[] = "nForce3 250Gb PCI-to-PCI Bridge"; +static const char pci_device_10de_00ee[] = "CK8S Serial ATA Controller (v2.5)"; +static const char pci_device_10de_00f0[] = "NV40 [GeForce 6800/GeForce 6800 Ultra]"; +static const char pci_device_10de_00f1[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1043_81a6[] = "N6600GT TD 128M AGP"; +#endif +static const char pci_device_10de_00f2[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f2_1682_211c[] = "GeForce 6600 256MB DDR DUAL DVI TV"; +#endif +static const char pci_device_10de_00f3[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_00f8[] = "NV45GL [Quadro FX 3400/4400]"; +static const char pci_device_10de_00f9[] = "NV40 [GeForce 6800 Ultra/GeForce 6800 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f9_1682_2120[] = "GEFORCE 6800 GT PCI-E"; +#endif +static const char pci_device_10de_00fa[] = "NV36 [GeForce PCX 5750]"; +static const char pci_device_10de_00fb[] = "NV35 [GeForce PCX 5900]"; +static const char pci_device_10de_00fc[] = "NV37GL [Quadro FX 330/GeForce PCX 5300]"; +static const char pci_device_10de_00fd[] = "NV37GL [Quadro FX 330/Quadro NVS280]"; +static const char pci_device_10de_00fe[] = "NV38GL [Quadro FX 1300]"; +static const char pci_device_10de_00ff[] = "NV18 [GeForce PCX 4300]"; +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c41[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c43[] = "ERAZOR X PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c48[] = "Synergy Force"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1048_0c42[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_107d_2822[] = "WinFast GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c40[] = "GLoria II-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c44[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c45[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4a[] = "GLoria II-64 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4b[] = "GLoria II-64 Pro DVII"; +#endif +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c60[] = "Gladiac MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c61[] = "Gladiac 511PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c63[] = "Gladiac 511TV-OUT 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c64[] = "Gladiac 511TV-OUT 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c65[] = "Gladiac 511TWIN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c66[] = "Gladiac 311"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_0091[] = "Dell OEM GeForce 2 MX 400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_00a1[] = "Apple OEM GeForce2 MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX/Go]"; +static const char pci_device_10de_0140[] = "NV43 [GeForce 6600 GT]"; +static const char pci_device_10de_0141[] = "NV43 [GeForce 6600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0141_1458_3124[] = "GV-NX66128DP Turbo Force Edition"; +#endif +static const char pci_device_10de_0142[] = "GeForce 6600 LE"; +static const char pci_device_10de_0144[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0145[] = "NV43 [GeForce 6610 XL]"; +static const char pci_device_10de_0146[] = "NV43 [Geforce Go 6600TE/6200TE]"; +static const char pci_device_10de_0147[] = "GeForce 6700 XL"; +static const char pci_device_10de_0148[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0149[] = "GeForce Go 6600 GT"; +static const char pci_device_10de_014e[] = "NV43GL [Quadro FX 540]"; +static const char pci_device_10de_014f[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c50[] = "Gladiac"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c52[] = "Gladiac-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2842[] = "WinFast GeForce 2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1462_5506[] = "Creative 3D Blaster Geforce2 Titanium"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0160[] = "GeForce 6500"; +static const char pci_device_10de_0161[] = "GeForce 6200 TurboCache(TM)"; +static const char pci_device_10de_0162[] = "GeForce 6200SE TurboCache(TM)"; +static const char pci_device_10de_0163[] = "GeForce 6200 LE"; +static const char pci_device_10de_0164[] = "NV44 [GeForce Go 6200]"; +static const char pci_device_10de_0165[] = "NV44 [Quadro NVS 285]"; +static const char pci_device_10de_0166[] = "GeForce Go 6400"; +static const char pci_device_10de_0167[] = "GeForce Go 6200"; +static const char pci_device_10de_0168[] = "GeForce Go 6400"; +static const char pci_device_10de_0169[] = "GeForce 6250"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10b0_0002[] = "Gainward Pro/600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10de_0008[] = "Apple OEM GeForce4 MX 440"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8852[] = "GeForce4 MX440 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_10de_0177[] = "NV17 [GeForce4 460 Go]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0179_10de_0179[] = "GeForce4 MX (Mac)"; +#endif +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 500 GoGL]"; +static const char pci_device_10de_017d[] = "NV17 [GeForce4 410 Go 16M]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_806f[] = "V9180 Magic"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8880[] = "MS-StarForce GeForce4 MX 440 with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8900[] = "MS-8890 GeForce 4 MX440 AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_9350[] = "MSI Geforce4 MX T8X with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_147b_8f0d[] = "Siluro GF4 MX-8X"; +#endif +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0185[] = "NV18 [GeForce4 MX 4000 AGP 8x]"; +static const char pci_device_10de_0186[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_0187[] = "NV18M [GeForce4 488 Go]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS AGP 8x]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_018c[] = "Quadro NVS 50 PC"; +static const char pci_device_10de_018d[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_01a0[] = "NVCrush11 [GeForce2 MX Integrated Graphics]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b0[] = "nForce Audio"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "nForce AC'97 Modem Controller"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01e0[] = "nForce2 AGP (different version?)"; +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01ea[] = "nForce2 Memory Controller 0"; +static const char pci_device_10de_01eb[] = "nForce2 Memory Controller 1"; +static const char pci_device_10de_01ec[] = "nForce2 Memory Controller 2"; +static const char pci_device_10de_01ed[] = "nForce2 Memory Controller 3"; +static const char pci_device_10de_01ee[] = "nForce2 Memory Controller 4"; +static const char pci_device_10de_01ef[] = "nForce2 Memory Controller 5"; +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1048_0c70[] = "GLADIAC 920"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0211[] = "GeForce 6800"; +static const char pci_device_10de_0212[] = "GeForce 6800 LE"; +static const char pci_device_10de_0215[] = "GeForce 6800 GT"; +static const char pci_device_10de_0221[] = "GeForce 6200"; +static const char pci_device_10de_0240[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0241[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0242[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0243[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0244[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0245[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0246[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0247[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0248[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0249[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024a[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024b[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024c[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024d[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024e[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024f[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0251_1043_8023[] = "v8440 GeForce 4 Ti4400"; +#endif +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0260[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0261[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0262[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0263[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0264[] = "MCP51 SMBus"; +static const char pci_device_10de_0265[] = "MCP51 IDE"; +static const char pci_device_10de_0266[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0267[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0268[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_0269[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_026a[] = "MCP51 MCI"; +static const char pci_device_10de_026b[] = "MCP51 AC97 Audio Controller"; +static const char pci_device_10de_026c[] = "MCP51 High Definition Audio"; +static const char pci_device_10de_026d[] = "MCP51 USB Controller"; +static const char pci_device_10de_026e[] = "MCP51 USB Controller"; +static const char pci_device_10de_026f[] = "MCP51 PCI Bridge"; +static const char pci_device_10de_0270[] = "MCP51 Host Bridge"; +static const char pci_device_10de_0271[] = "MCP51 PMU"; +static const char pci_device_10de_0272[] = "MCP51 Memory Controller 0"; +static const char pci_device_10de_027e[] = "C51 Memory Controller 2"; +static const char pci_device_10de_027f[] = "C51 Memory Controller 3"; +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0286[] = "NV28 [GeForce4 Ti 4200 Go AGP 8x]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_028c[] = "NV28GLM [Quadro4 700 GoGL]"; +static const char pci_device_10de_02a0[] = "NV2A [XGPU]"; +static const char pci_device_10de_02f0[] = "C51 Host Bridge"; +static const char pci_device_10de_02f1[] = "C51 Host Bridge"; +static const char pci_device_10de_02f2[] = "C51 Host Bridge"; +static const char pci_device_10de_02f3[] = "C51 Host Bridge"; +static const char pci_device_10de_02f4[] = "C51 Host Bridge"; +static const char pci_device_10de_02f5[] = "C51 Host Bridge"; +static const char pci_device_10de_02f6[] = "C51 Host Bridge"; +static const char pci_device_10de_02f7[] = "C51 Host Bridge"; +static const char pci_device_10de_02f8[] = "C51 Memory Controller 5"; +static const char pci_device_10de_02f9[] = "C51 Memory Controller 4"; +static const char pci_device_10de_02fa[] = "C51 Memory Controller 0"; +static const char pci_device_10de_02fb[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fc[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fd[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fe[] = "C51 Memory Controller 1"; +static const char pci_device_10de_02ff[] = "C51 Host Bridge"; +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +static const char pci_device_10de_0311[] = "NV31 [GeForce FX 5600 Ultra]"; +static const char pci_device_10de_0312[] = "NV31 [GeForce FX 5600]"; +static const char pci_device_10de_0313[] = "NV31"; +static const char pci_device_10de_0314[] = "GeForce FX 5600SE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0314_1043_814a[] = "V9560XT/TD"; +#endif +static const char pci_device_10de_0316[] = "NV31M"; +static const char pci_device_10de_0317[] = "NV31M Pro"; +static const char pci_device_10de_031a[] = "NV31M [GeForce FX Go5600]"; +static const char pci_device_10de_031b[] = "NV31M [GeForce FX Go5650]"; +static const char pci_device_10de_031c[] = "NVIDIA Quadro FX Go700"; +static const char pci_device_10de_031d[] = "NV31GLM"; +static const char pci_device_10de_031e[] = "NV31GLM Pro"; +static const char pci_device_10de_031f[] = "NV31GLM Pro"; +static const char pci_device_10de_0320[] = "NV34 [GeForce FX 5200]"; +static const char pci_device_10de_0321[] = "NV34 [GeForce FX 5200 Ultra]"; +static const char pci_device_10de_0322[] = "NV34 [GeForce FX 5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9171[] = "MS-8917 (FX5200-T128)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9360[] = "MS-8936 (FX5200-T128)"; +#endif +static const char pci_device_10de_0323[] = "GeForce FX 5200SE"; +static const char pci_device_10de_0324[] = "NV34M [GeForce FX Go5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_10de_0325[] = "NV34M [GeForce FX Go5250]"; +static const char pci_device_10de_0326[] = "NV34 [GeForce FX 5500]"; +static const char pci_device_10de_0327[] = "NV34 [GeForce FX 5100]"; +static const char pci_device_10de_0328[] = "NV34M [GeForce FX Go5200 32M/64M]"; +static const char pci_device_10de_0329[] = "GeForce FX 5200 (Mac)"; +static const char pci_device_10de_032a[] = "NV34GL [Quadro NVS 280 PCI]"; +static const char pci_device_10de_032b[] = "NV34GL [Quadro FX 500/600 PCI]"; +static const char pci_device_10de_032c[] = "NV34GLM [GeForce FX Go 5300]"; +static const char pci_device_10de_032d[] = "NV34 [GeForce FX Go5100]"; +static const char pci_device_10de_032f[] = "NV34GL"; +static const char pci_device_10de_0330[] = "NV35 [GeForce FX 5900 Ultra]"; +static const char pci_device_10de_0331[] = "NV35 [GeForce FX 5900]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0331_1043_8145[] = "V9950GE"; +#endif +static const char pci_device_10de_0332[] = "NV35 [GeForce FX 5900XT]"; +static const char pci_device_10de_0333[] = "NV38 [GeForce FX 5950 Ultra]"; +static const char pci_device_10de_0334[] = "NV35 [GeForce FX 5900ZT]"; +static const char pci_device_10de_0338[] = "NV35GL [Quadro FX 3000]"; +static const char pci_device_10de_033f[] = "NV35GL [Quadro FX 700]"; +static const char pci_device_10de_0341[] = "NV36.1 [GeForce FX 5700 Ultra]"; +static const char pci_device_10de_0342[] = "NV36.2 [GeForce FX 5700]"; +static const char pci_device_10de_0343[] = "NV36 [GeForce FX 5700LE]"; +static const char pci_device_10de_0344[] = "NV36.4 [GeForce FX 5700VE]"; +static const char pci_device_10de_0345[] = "NV36.5"; +static const char pci_device_10de_0347[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0348[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0349[] = "NV36M Pro"; +static const char pci_device_10de_034b[] = "NV36MAP"; +static const char pci_device_10de_034c[] = "NV36 [Quadro FX Go1000]"; +static const char pci_device_10de_034e[] = "NV36GL [Quadro FX 1100]"; +static const char pci_device_10de_034f[] = "NV36GL"; +static const char pci_device_10de_0360[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0361[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0362[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0363[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0364[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0365[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0366[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0367[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0368[] = "MCP55 SMBus"; +static const char pci_device_10de_0369[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036c[] = "MCP55 USB Controller"; +static const char pci_device_10de_036d[] = "MCP55 USB Controller"; +static const char pci_device_10de_036e[] = "MCP55 IDE"; +static const char pci_device_10de_0371[] = "MCP55 High Definition Audio"; +static const char pci_device_10de_0372[] = "MCP55 Ethernet"; +static const char pci_device_10de_0373[] = "MCP55 Ethernet"; +static const char pci_device_10de_037a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_037e[] = "MCP55 SATA Controller"; +static const char pci_device_10de_037f[] = "MCP55 SATA Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Host Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Host Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a1[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a5[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0b5[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d1[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d5[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e1[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e5[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0f5[] = "Neptune LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f701[] = "LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f801[] = "LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f901[] = "LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Host Adapter"; +static const char pci_device_10df_f981[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_f982[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_fa00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fb00[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc10[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc20[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fd00[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fe00[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_ff00[] = "Neptune LightPulse Fibre Channel Host Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0148[] = "Tsi148 [Tempe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +static const char pci_device_10e3_8260[] = "CA91L8200B [Dual PCI PowerSpan II]"; +static const char pci_device_10e3_8261[] = "CA91L8260B [Single PCI PowerSpan II]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +static const char pci_device_10e4_8029[] = "Realtek 8029 Network Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_1072[] = "INES GPIB-PCI (AMCC5920 based)"; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_814c[] = "Fastcom ESCC-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_81e6[] = "Multimedia video controller"; +static const char pci_device_10e8_8291[] = "Fastcom 232/8-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c4[] = "Fastcom 422/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c5[] = "Fastcom 422/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c6[] = "Fastcom IG422/1-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c7[] = "Fastcom IG232/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82ca[] = "Fastcom 232/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +static const char pci_device_10e8_82e2[] = "Fastcom DIO24H-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8851[] = "S5933 on Innes Corp FM Radio Capture card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +static const char pci_device_10ea_5252[] = "CyberPro5252"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_0139[] = "Zonet Zen3200"; +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1043_8109[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1113_ec01[] = "FNC-0107TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1458_e000[] = "GA-7VM400M/7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_14cb_0200[] = "LNR-100 Family 10/100 Base-TX Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1799_5000[] = "F5D5000 PCI Card/Desktop Network PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_9001_1695[] = "Onboard RTL8101L 10/100 MBit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8169[] = "RTL-8169 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1259_c107[] = "CG-LAPCIGT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1458_e000[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1462_702c[] = "K8T NEO 2 motherboard"; +#endif +static const char pci_device_10ec_8180[] = "RTL8180L 802.11b MAC"; +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_0314[] = "Wildcard TE405P/TE410P (1st Gen)"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +static const char pci_device_10ee_3fc6[] = "RME Hammerfall DSP MADI"; +static const char pci_device_10ee_8381[] = "Ellips Santos Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft fuer Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +static const char pci_device_1101_9502[] = "Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8064[] = "SBLive! 5.1 Model SB0100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8065[] = "SBLive! 5.1 Digital Model SB0220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8067[] = "SBLive! 5.1 eMicro 28028"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0058[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_1007[] = "SB0240 Audigy 2 Platinum 6.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_2002[] = "SB Audigy 2 ZS (SB0350)"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_0007[] = "SB Audigy LS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_0007[] = "SBLive! 24bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1001[] = "SB0310 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1002[] = "SB0312 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1006[] = "SB0410 SBLive! 24-bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1462_1009[] = "K8N Diamond"; +#endif +static const char pci_device_1102_0008[] = "SB0400 Audigy2 Value"; +static const char pci_device_1102_100a[] = "SB Live! 5.1 Digital OEM [SB0220], (c) 2003"; +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! MIDI/Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_7005[] = "SB Audigy LS MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1001[] = "SB0310 Audigy LS MIDI/Game port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1002[] = "SB0312 Audigy LS MIDI/Game port"; +#endif +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "Ectiva EV1938"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1033_80e5[] = "SlimTower-Jim (NEC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1071_7150[] = "Mitac 7150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_110a_5938[] = "Siemens Scenic Mobile 510PIII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100c[] = "Ceres-C (Sharp, Intel BX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100d[] = "Sharp, Intel Banister"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100e[] = "TwinHead P09S/P09S3 (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_f6f1[] = "Marlin (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_0e70[] = "P88TE (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_c401[] = "Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b400[] = "G400 - Geo (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b550[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b560[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b700[] = "G700/U700 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b795[] = "G795 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b797[] = "G797 (AlphaTop (Taiwan))"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372/372N"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0003[] = "HPT343 / HPT345 / HPT363 UDMA33"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0004[] = "HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0006[] = "HPT302"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0007[] = "HPT371 UDMA133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0008[] = "HPT374 UDMA/ATA133 RAID Controller"; +#endif +static const char pci_device_1103_0005[] = "HPT372A/372N"; +static const char pci_device_1103_0006[] = "HPT302"; +static const char pci_device_1103_0007[] = "HPT371/371N"; +static const char pci_device_1103_0008[] = "HPT374"; +static const char pci_device_1103_0009[] = "HPT372N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +static const char pci_device_1105_8401[] = "EM8401 REALmagic DVD/MPEG-2 A/V Decoder"; +static const char pci_device_1105_8470[] = "EM8470 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8471[] = "EM8471 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8475[] = "EM8475 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8475_1105_0001[] = "REALmagic X-Card"; +#endif +static const char pci_device_1105_8476[] = "EM8476 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8476_127d_0000[] = "CineView II"; +#endif +static const char pci_device_1105_8485[] = "EM8485 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8486[] = "EM8486 REALmagic DVD/MPEG-4 A/V Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_0238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_0259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_0269[] = "KT880 Host Bridge"; +static const char pci_device_1106_0282[] = "K8T800Pro Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0282_1043_80a3[] = "A8V Deluxe"; +#endif +static const char pci_device_1106_0290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_0296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1019_0987[] = "K7VZA (Rev. 1.0) Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0308[] = "PT894 Host Bridge"; +static const char pci_device_1106_0314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C576MV"; +static const char pci_device_1106_0571[] = "VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_808c[] = "A7V8X / A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80a1[] = "A7V8X-X motherboard rev. 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1849_0571[] = "K7VT2 / K7VT6 motherboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0591[] = "VT8237A SATA 2-Port Controller"; +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0605_1043_802c[] = "CUV4X mainboard"; +#endif +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_802c[] = "CUV4X mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_1208[] = "PT890 Host Bridge"; +static const char pci_device_1106_1238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_1258[] = "PT880 Host Bridge"; +static const char pci_device_1106_1259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_1269[] = "KT880 Host Bridge"; +static const char pci_device_1106_1282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_1290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_1296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_1308[] = "PT894 Host Bridge"; +static const char pci_device_1106_1314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_1571[] = "VT82C576M/VT82C586"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_2204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_2208[] = "PT890 Host Bridge"; +static const char pci_device_1106_2238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_2258[] = "PT880 Host Bridge"; +static const char pci_device_1106_2259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_2269[] = "KT880 Host Bridge"; +static const char pci_device_1106_2282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_2290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_2296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_2308[] = "PT894 Host Bridge"; +static const char pci_device_1106_2314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_287a[] = "VT8251 PCI to PCI Bridge"; +static const char pci_device_1106_287b[] = "VT8251 PCI to PCIE Bridge"; +static const char pci_device_1106_287c[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287d[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287e[] = "VT8251 Ultra VLINK Controller"; +static const char pci_device_1106_3022[] = "CLE266"; +static const char pci_device_1106_3038[] = "VT82xxxxx UHCI USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_8080[] = "A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_808c[] = "VT6202 USB2.0 4 port controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_182d_201d[] = "CN-029 USB2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1849_3038[] = "K7VT6"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_0574_086c[] = "K8N Diamond"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1043_808a[] = "A8V Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1458_1000[] = "GA-7VT600-1394 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_702d[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_971d[] = "MS-6917"; +#endif +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3053[] = "VT6105M [Rhine-III]"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_0097[] = "SoundMax Digital Integrated Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1043_1106[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3300[] = "MS-6330 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233/A/8235/8237 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_8095[] = "A7V8X Motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80b0[] = "A7V600/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX])"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_812a[] = "A8V Deluxe motherboard (Realtek ALC850 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_3059[] = "L7VMM2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4161[] = "K7VT2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1297_c160[] = "FX41 motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_0080[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_3800[] = "KT266 onboard audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1849_9761[] = "K7VT6 motherboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4005_4710[] = "MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_a0a0_01b6[] = "AK77-8XN onboard audio"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_13b9_1421[] = "LD-10/100AL PCI Fast Ethernet Adapter (rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_3005[] = "VT6103"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_300c[] = "Realtek ALC655 sound chip"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1849_3065[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3068[] = "AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3068_1462_309e[] = "MS-6309 Saturn Motherboard"; +#endif +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1849_3099[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80a1[] = "A7V8X-X motherboard rev 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_182d_201d[] = "CN-029 USB 2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1849_3104[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3106_1186_1403[] = "DFE-530TX rev C"; +#endif +static const char pci_device_1106_3108[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3113[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3116[] = "VT8375 [KM266/KL266] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3116_1297_f641[] = "FX41 motherboard"; +#endif +static const char pci_device_1106_3118[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3119[] = "VT6120/VT6121/VT6122 Gigabit Ethernet Adapter"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3147_1043_808c[] = "A7V333 motherboard"; +#endif +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3149[] = "VIA VT6420 SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1043_80ed[] = "A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1458_b003[] = "GA-7VM400AM(F) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1462_7020[] = "K8T Neo 2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1408[] = "KV7"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1849_3149[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3164[] = "VT6410 ATA133 RAID controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1849_3177[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3178[] = "ProSavageDDR P4N333 Host Bridge"; +static const char pci_device_1106_3188[] = "VT8385 [K8T800 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_1043_80a3[] = "K8V Deluxe/K8V-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400/KT600 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1043_807f[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1849_3189[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_3205[] = "VT8378 [KM400/A] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3205_1458_5000[] = "GA-7VM400M Motherboard"; +#endif +static const char pci_device_1106_3208[] = "PT890 Host Bridge"; +static const char pci_device_1106_3213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3218[] = "K8T800M Host Bridge"; +static const char pci_device_1106_3227[] = "VT8237 ISA bridge [KT600/K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1106_3227[] = "DFI KT600-AL Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1458_5001[] = "GA-7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1849_3227[] = "K7VT4 motherboard"; +#endif +static const char pci_device_1106_3238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_3249[] = "VT6421 IDE RAID Controller"; +static const char pci_device_1106_3258[] = "PT880 Host Bridge"; +static const char pci_device_1106_3259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_3269[] = "KT880 Host Bridge"; +static const char pci_device_1106_3282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_3288[] = "VIA High Definition Audio Controller"; +static const char pci_device_1106_3290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_3296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_3337[] = "VT8237A PCI to ISA Bridge"; +static const char pci_device_1106_3349[] = "VT8251 AHCI/SATA 4-Port Controller"; +static const char pci_device_1106_337a[] = "VT8237A PCI to PCI Bridge"; +static const char pci_device_1106_337b[] = "VT8237A PCI to PCIE Bridge"; +static const char pci_device_1106_4149[] = "VIA VT6420 (ATA133) Controller"; +static const char pci_device_1106_4204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_4208[] = "PT890 Host Bridge"; +static const char pci_device_1106_4238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_4258[] = "PT880 Host Bridge"; +static const char pci_device_1106_4259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_4269[] = "KT880 Host Bridge"; +static const char pci_device_1106_4282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_4290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_4296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_4308[] = "PT894 Host Bridge"; +static const char pci_device_1106_4314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_5208[] = "PT890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5238[] = "K8T890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5290[] = "K8M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5308[] = "PT894 I/O APIC Interrupt Controller"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_7204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_7205[] = "VT8378 [S3 UniChrome] Integrated Video"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_7205_1458_d000[] = "Gigabyte GA-7VM400(A)M(F) Motherboard"; +#endif +static const char pci_device_1106_7208[] = "PT890 Host Bridge"; +static const char pci_device_1106_7238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_7258[] = "PT880 Host Bridge"; +static const char pci_device_1106_7259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_7269[] = "KT880 Host Bridge"; +static const char pci_device_1106_7282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_7290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_7296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_7308[] = "PT894 Host Bridge"; +static const char pci_device_1106_7314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_8598_1019_0985[] = "P6VXA Motherboard"; +#endif +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_a208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b113[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b115[] = "VT8363/8365 [KT133/KM133] PCI Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +static const char pci_device_1106_b188[] = "VT8237 PCI bridge [K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_b188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_b198[] = "VT8237 PCI Bridge"; +static const char pci_device_1106_b213[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_c208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d104[] = "VT8237 Integrated Fast Ethernet Controller"; +static const char pci_device_1106_d208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f238[] = "K8T890 PCI to PCI Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_0006[] = "FSC PINC (I/O-APIC)"; +static const char pci_device_110a_0015[] = "FSC Multiprocessor Interrupt Controller"; +static const char pci_device_110a_001d[] = "FSC Copernicus Management Controller"; +static const char pci_device_110a_007b[] = "FSC Remote Service Controller, mailbox device"; +static const char pci_device_110a_007c[] = "FSC Remote Service Controller, shared memory device"; +static const char pci_device_110a_007d[] = "FSC Remote Service Controller, SMIC device"; +static const char pci_device_110a_2101[] = "HST SAPHIR V Primary PCI (ISDN/PMx)"; +static const char pci_device_110a_2102[] = "DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels"; +static const char pci_device_110a_2104[] = "Eicon Diva 2.02 compatible passive ISDN card"; +static const char pci_device_110a_3142[] = "SIMATIC NET CP 5613A1 (Profibus Adapter)"; +static const char pci_device_110a_4021[] = "SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter)"; +static const char pci_device_110a_4029[] = "SIMATIC NET CP 5613A2 (Profibus Adapter)"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_1113_2242[] = "EN2242 10/100 Ethernet Mini-PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "21x4x DEC-Tulip compatible Fast Ethernet"; +static const char pci_device_1113_d301[] = "CPWNA100 (Philips wireless PCMCIA)"; +static const char pci_device_1113_ec02[] = "SMC 1244TX v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +static const char pci_device_1114_0506[] = "at76c506 802.11b Wireless Network Adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6117/6517"; +static const char pci_device_1119_0007[] = "GDT 6127/6527"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557/6557-ECC"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0010[] = "GDT 6115/6515"; +static const char pci_device_1119_0011[] = "GDT 6125/6525"; +static const char pci_device_1119_0012[] = "GDT 6535"; +static const char pci_device_1119_0013[] = "GDT 6555/6555-ECC"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_02ff[] = "GDT MAXRP"; +static const char pci_device_1119_0300[] = "GDT NEWRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +static const char pci_device_111a_1203[] = "SpeedStream 1023 Wireless PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Technology, Inc."; +static const char pci_device_111d_0001[] = "IDT77201/77211 155Mbps ATM SAR Controller [NICStAR]"; +static const char pci_device_111d_0003[] = "IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0004[] = "IDT77V252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0005[] = "IDT77V222 155Mbps ATM MICRO ABR SAR Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +static const char pci_device_112f_0008[] = "PC-CamLink PCI framegrabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_5400[] = "TriMedia TM1000/1100"; +static const char pci_device_1131_5402[] = "TriMedia TM-1300"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_5402_1244_0f00[] = "Fritz!Card DSL"; +#endif +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_102b_48d0[] = "Matrox CronosPlus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1048_226b[] = "ELSA EX-VISION 500TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2001[] = "10MOONS PCI TV CAPTURE CARD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2005[] = "Techcom (India) TV Tuner Card (SSD-TV-670)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_050c[] = "Nagase Sangyo TransGear 3000TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_10ff[] = "AVerMedia DVD EZMaker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2108[] = "AverMedia AverTV/305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2115[] = "AverMedia AverTV Studio 305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_153b_1152[] = "Terratec Cinergy 200 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c100[] = "Compro VideoMate TV PVR/FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_5168_0138[] = "LifeView FlyVIDEO2000"; +#endif +static const char pci_device_1131_7133[] = "SAA7133 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_002b_11bd[] = "Pinnacle PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1019_4cb5[] = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_0210[] = "MiniPCI TV Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4843[] = "ASUS TV-FM 7133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2001[] = "Proteus Pro [philips reference design]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_f31f[] = "Avermedia AVerTV GO 007 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1489_0214[] = "LifeView FlyTV Platinum FM/Genius VideoWonder ProTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1162[] = "Terratec Cinergy 400 mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_185b_c100[] = "Compro VideoMate TV Gold+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0138[] = "LifeView FlyVideo 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0212[] = "LifeView FlyTV Platinum mini"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0214[] = "LifeView FlyTV Platinum"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0306[] = "LifeView FlyDVB-T DUO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0502[] = "LifeView FlyDVB-T Duo CardBus"; +#endif +static const char pci_device_1131_7134[] = "SAA7134 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1019_4cb4[] = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4840[] = "ASUS TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4842[] = "TV-FM Card 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_4e85[] = "SKNet Monster TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_6752[] = "EMPRESS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_7133[] = "AOPEN VA1000 POWER"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002b[] = "Pinnacle PCTV Stereo (saa7134)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002d[] = "Pinnacle PCTV 300i DVB-T + PAL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_2c00[] = "AVerMedia Hybrid+FM (A16A) PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_2c05[] = "AVerMedia DVB-T A777"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70a[] = "Avermedia AVerTV 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70b[] = "AverMedia M156 / Medion 2819"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_d6ee[] = "AVerMedia Cardbus TV/Radio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1142[] = "Terratec Cinergy 400 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1143[] = "Terratec Cinergy 600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1158[] = "Terratec Cinergy 600 TV MK3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1540_9524[] = "ProVideo PV952"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_16be_0003[] = "Medion 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c200[] = "Compro VideoMate Gold+ Pal"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_a006[] = "KNC One TV-Station DVR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_fe01[] = "KNC One TV-Station RDS / Typhoon TV Tuner RDS"; +#endif +static const char pci_device_1131_7135[] = "SAA7135 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_1421_0350[] = "ADS Tech Instant TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_1421_0370[] = "ADS Tech Instant TV (cardbus version)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_5168_0212[] = "LifeView FlyTV Platinum Mini"; +#endif +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_0000[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_ffff[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f56[] = "KNC1 DVB-S Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f60[] = "Fujitsu-Siemens Activy DVB-S Budget Rev AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f61[] = "Activy DVB-S Budget Rev GR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_5f61[] = "Activy DVB-T Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000f[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0000[] = "Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0001[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0002[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0003[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0004[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0006[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0008[] = "Technotrend/Hauppauge DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_000a[] = "Octal/Technotrend DVB-C for iTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1003[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-S DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1004[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-C DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1005[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100c[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100f[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1011[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1013[] = "SATELCO Multimedia DVB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1102[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +static const char pci_device_1131_9730[] = "SAA9730 Integrated Multimedia and Peripheral Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Networks Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "Diva Pro 2.0 S/T"; +static const char pci_device_1133_e002[] = "Diva 2.0 S/T PCI"; +static const char pci_device_1133_e003[] = "Diva Pro 2.0 U"; +static const char pci_device_1133_e004[] = "Diva 2.0 U PCI"; +static const char pci_device_1133_e005[] = "Diva 2.01 S/T PCI"; +static const char pci_device_1133_e006[] = "Diva CT S/T PCI"; +static const char pci_device_1133_e007[] = "Diva CT U PCI"; +static const char pci_device_1133_e008[] = "Diva CT Lite S/T PCI"; +static const char pci_device_1133_e009[] = "Diva CT Lite U PCI"; +static const char pci_device_1133_e00a[] = "Diva ISDN+V.90 PCI"; +static const char pci_device_1133_e00b[] = "Diva 2.02 PCI S/T"; +static const char pci_device_1133_e00c[] = "Diva 2.02 PCI U"; +static const char pci_device_1133_e00d[] = "Diva ISDN Pro 3.0 PCI"; +static const char pci_device_1133_e00e[] = "Diva ISDN+CT S/T PCI Rev 2"; +static const char pci_device_1133_e010[] = "Diva Server BRI-2M PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_110a_0021[] = "Fujitsu Siemens ISDN S0"; +#endif +static const char pci_device_1133_e011[] = "Diva Server BRI S/T Rev 2"; +static const char pci_device_1133_e012[] = "Diva Server 4BRI-8M PCI"; +static const char pci_device_1133_e013[] = "Diva Server 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_1300[] = "Diva Server V-4BRI-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_e013[] = "Diva Server 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e014[] = "Diva Server PRI-30M PCI"; +static const char pci_device_1133_e015[] = "DIVA Server PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e015_1133_e015[] = "Diva Server PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e016[] = "Diva Server Voice 4BRI PCI"; +static const char pci_device_1133_e017[] = "Diva Server Voice 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e017_1133_e017[] = "Diva Server Voice 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_1800[] = "Diva Server V-BRI-2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e019[] = "Diva Server Voice PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e019_1133_e019[] = "Diva Server Voice PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e01a[] = "Diva Server 2FX"; +static const char pci_device_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01b_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e01c[] = "Diva Server PRI Rev 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c01[] = "Diva Server PRI/E1/T1-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c02[] = "Diva Server PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c03[] = "Diva Server PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c04[] = "Diva Server PRI/E1/T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c05[] = "Diva Server V-PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c06[] = "Diva Server V-PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c07[] = "Diva Server PRI/E1/T1-8 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c08[] = "Diva Server PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c09[] = "Diva Server PRI/E1-30 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0a[] = "Diva Server PRI/E1/T1 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0b[] = "Diva Server V-PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0c[] = "Diva Server V-PRI/E1-30 Cornet NQ"; +#endif +static const char pci_device_1133_e01e[] = "Diva Server 2PRI"; +static const char pci_device_1133_e020[] = "Diva Server 4PRI"; +static const char pci_device_1133_e024[] = "Diva Server Analog-4P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_2400[] = "Diva Server V-Analog-4P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_e024[] = "Diva Server Analog-4P"; +#endif +static const char pci_device_1133_e028[] = "Diva Server Analog-8P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_2800[] = "Diva Server V-Analog-8P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_e028[] = "Diva Server Analog-8P"; +#endif +static const char pci_device_1133_e02a[] = "Diva Server IPM-300"; +static const char pci_device_1133_e02c[] = "Diva Server IPM-600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +static const char pci_device_1134_0002[] = "Dual PCI to RapidIO Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +static const char pci_device_1145_f020[] = "NinjaSCSI-32 Sony PCGA-DVD51"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "SysKonnect"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2971[] = "AT-2970LX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970TX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2973[] = "AT-2971SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2974[] = "AT-2971T Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2976[] = "AT-2970LX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970TX/2TX Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1148_4320[] = "SysKonnect SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0121[] = "Marvell RDK-8001 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0221[] = "Marvell RDK-8002 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0321[] = "Marvell RDK-8003 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0421[] = "Marvell RDK-8004 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0621[] = "Marvell RDK-8006 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0721[] = "Marvell RDK-8007 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0821[] = "Marvell RDK-8008 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0921[] = "Marvell RDK-8009 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1121[] = "Marvell RDK-8011 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1221[] = "Marvell RDK-8012 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_3221[] = "SK-9521 V2.0 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "SK-9Dxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_4500[] = "SK-9Mxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_9000[] = "SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45"; +static const char pci_device_1148_9843[] = "[Fujitsu] Gigabit Ethernet"; +static const char pci_device_1148_9e00[] = "SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2100[] = "SK-9E21 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_21d0[] = "SK-9E21D 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2200[] = "SK-9E22 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8100[] = "SK-9E81 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8200[] = "SK-9E82 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9100[] = "SK-9E91 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9200[] = "SK-9E92 Server Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0013[] = "AccelePort Xr"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0028[] = "ClassicBoard 4"; +static const char pci_device_114f_0029[] = "ClassicBoard 8"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p"; +static const char pci_device_114f_0043[] = "AccelePort 4p"; +static const char pci_device_114f_0044[] = "AccelePort 8p"; +static const char pci_device_114f_0045[] = "AccelePort 16p"; +static const char pci_device_114f_004e[] = "AccelePort 32p"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_00b0[] = "Digi Neo 4"; +static const char pci_device_114f_00b1[] = "Digi Neo 8"; +static const char pci_device_114f_00c8[] = "Digi Neo 2 DB9"; +static const char pci_device_114f_00c9[] = "Digi Neo 2 DB9 PRI"; +static const char pci_device_114f_00ca[] = "Digi Neo 2 RJ45"; +static const char pci_device_114f_00cb[] = "Digi Neo 2 RJ45 PRI"; +static const char pci_device_114f_00d0[] = "ClassicBoard 4 422"; +static const char pci_device_114f_00d1[] = "ClassicBoard 8 422"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0182[] = "RealPort2 CardBus Ethernet 10/100 (R2BE-100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_00d4[] = "Mini-PCI K56Flex Modem"; +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "Broadcom"; +static const char pci_device_1166_0000[] = "CMIC-LE"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0006[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-WS Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CMIC-LE Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0036[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0101[] = "CIOB-X2 PCI-X I/O Bridge"; +static const char pci_device_1166_0104[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0110[] = "CIOB-E I/O Bridge with Gigabit Ethernet"; +static const char pci_device_1166_0130[] = "HT1000 PCI-X bridge"; +static const char pci_device_1166_0132[] = "HT1000 PCI-Express bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0201_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0203_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0205[] = "HT1000 Legacy South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0212_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_c134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0214[] = "HT1000 Legacy IDE controller"; +static const char pci_device_1166_0217[] = "CSB6 IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0217_1028_4134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0220_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0221_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0223[] = "HT1000 USB Controller"; +static const char pci_device_1166_0225[] = "CSB5 LPC bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0227_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0230[] = "CSB5 LPC bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0230_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0234[] = "HT1000 LPC Bridge"; +static const char pci_device_1166_0240[] = "K2 SATA"; +static const char pci_device_1166_0241[] = "RAIDCore RC4000"; +static const char pci_device_1166_0242[] = "RAIDCore BC4000"; +static const char pci_device_1166_024a[] = "BCM5785 (HT1000) SATA Native SATA Mode"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0102[] = "Extended IDE Controller"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "CPU to PCI bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0601_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_060a_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC100 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +static const char pci_device_117c_0030[] = "Ultra320 SCSI Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8013[] = "ExpressPCI UL4D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8014[] = "ExpressPCI UL4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1987[] = "Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines )"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_14ef_0220[] = "PCD-RP-220S"; +#endif +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0511[] = "R5C511"; +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_1180_0554[] = "R5C554"; +static const char pci_device_1180_0575[] = "R5C575 SD Bus Host Adapter"; +static const char pci_device_1180_0576[] = "R5C576 SD Bus Host Adapter"; +static const char pci_device_1180_0592[] = "R5C592 Memory Stick Bus Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0811[] = "R5C811"; +static const char pci_device_1180_0822[] = "R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0556[] = "Thinkpad X40"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_01a2[] = "Inspiron 9200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1043_1967[] = "ASUS V6800V"; +#endif +static const char pci_device_1180_0841[] = "R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394"; +static const char pci_device_1180_0852[] = "xD-Picture Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0852_1043_1967[] = "V6800V"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1025[] = "AirPlus Xtreme G DWL-G650 Adapter"; +static const char pci_device_1186_1026[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1043[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1303[] = "DFE-528TX 10/100 Fast Ethernet PCI Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1541[] = "DFE-680TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_2027[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3203[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3300[] = "DWL-510 2.4GHz Wireless PCI Adapter"; +static const char pci_device_1186_3a03[] = "AirPro DWL-A650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a04[] = "AirPro DWL-AB650 Multimode Wireless Cardbus Adapter"; +static const char pci_device_1186_3a05[] = "AirPro DWL-AB520 Multimode Wireless PCI Adapter"; +static const char pci_device_1186_3a07[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_3a08[] = "AirXpert DWL-AG520 Wireless PCI Adapter"; +static const char pci_device_1186_3a10[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a11[] = "AirXpert DWL-AG520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a12[] = "AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +static const char pci_device_1186_3a13[] = "AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a14[] = "AirPremier DWL-AG530 Wireless PCI Adapter"; +static const char pci_device_1186_3a63[] = "AirXpert DWL-AG660 Wireless Cardbus Adapter"; +static const char pci_device_1186_4000[] = "DL2000-based Gigabit Ethernet"; +static const char pci_device_1186_4300[] = "DGE-528T Gigabit Ethernet Adapter"; +static const char pci_device_1186_4c00[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_4c00_1186_4c00[] = "DGE-530T Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1186_8400[] = "D-Link DWL-650+ CardBus PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +static const char pci_device_1191_8060[] = "AEC6712 SCSI"; +static const char pci_device_1191_8080[] = "AEC67160 SCSI"; +static const char pci_device_1191_8081[] = "AEC67160S SCSI"; +static const char pci_device_1191_808a[] = "AEC67162 2-ch. LVD SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +static const char pci_device_1197_010c[] = "CompuScope 82G 8bit 2GS/s Analog Input Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Marvell Technology Group Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_138f[] = "W8300 802.11 Adapter (rev 07)"; +static const char pci_device_11ab_1fa6[] = "Marvell W8300 802.11 Adapter"; +static const char pci_device_11ab_1fa7[] = "88W8310 and 88W8000G [Libertas] 802.11g client chipset"; +static const char pci_device_11ab_1faa[] = "88w8335 [Libertas] 802.11b/g Wireless"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_1faa_1385_4e00[] = "WG511 v2 54MBit/ Wireless PC-Card"; +#endif +static const char pci_device_11ab_4320[] = "88E8001 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_0f38[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_8001[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_173c[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_811a[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_105b_0c19[] = "Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_10b8_b452[] = "EZ Card 1000 (SMC9452TXV.2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0121[] = "Marvell RDK-8001"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0321[] = "Marvell RDK-8003"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_1021[] = "Marvell RDK-8010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_5021[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_9521[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1458_e000[] = "Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_147b_1406[] = "Marvell 88E8001 Gigabit Ethernet Controller (Abit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_15d4_0047[] = "Marvell 88E8001 Gigabit Ethernet Controller (Iwill)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1695_9025[] = "Marvell 88E8001 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_17f2_1c03[] = "Marvell 88E8001 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_270f_2803[] = "Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)"; +#endif +static const char pci_device_11ab_4340[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4341[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4342[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4343[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4344[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4345[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4346[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4347[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4350[] = "88E8035 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1179_0001[] = "Marvell 88E8035 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_11ab_3521[] = "Marvell RDK-8035"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000d[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000f[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0011[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0012[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0016[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0017[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0018[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0019[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001c[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0020[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4351[] = "88E8036 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_107b_4009[] = "Marvell 88E8036 Fast Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_10f7_8338[] = "Marvell 88E8036 Fast Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_0001[] = "Marvell 88E8036 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff00[] = "Marvell 88E8036 Fast Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff10[] = "Marvell 88E8036 Fast Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_11ab_3621[] = "Marvell RDK-8036"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_13d1_ac12[] = "Abocom EFE3K - 10/100 Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_161f_203d[] = "Marvell 88E8036 Fast Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000d[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000f[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0011[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0012[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0016[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0017[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0018[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0019[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001c[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0020[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4352[] = "88E8038 PCI-E Fast Ethernet Controller"; +static const char pci_device_11ab_4360[] = "88E8052 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1043_8134[] = "Marvell 88E8052 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_107b_4009[] = "Marvell 88E8052 Gigabit Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_11ab_5221[] = "Marvell RDK-8052"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1458_e000[] = "Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1462_052c[] = "Marvell 88E8052 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1849_8052[] = "Marvell 88E8052 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_a0a0_0509[] = "Marvell 88E8052 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4361[] = "88E8050 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_107b_3015[] = "Marvell 88E8050 Gigabit Ethernet Controller (Gateway)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_11ab_5021[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3063[] = "D925XCVLK mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3439[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11ab_4362[] = "88E8053 PCI-E Gigabit Ethernet Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_103c_2a0d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1043_8142[] = "Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_109f_3197[] = "Marvell 88E8053 Gigabit Ethernet Controller (Trigem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10f7_8338[] = "Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10fd_a430[] = "Marvell 88E8053 Gigabit Ethernet Controller (SOYO)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_0001[] = "Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff00[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff10[] = "Marvell 88E8053 Gigabit Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_11ab_5321[] = "Marvell RDK-8053"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c240[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c241[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c242[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c243[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c244[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_13d1_ac11[] = "EGE5K - Giga Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1458_e000[] = "Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1462_058c[] = "Marvell 88E8053 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_14c0_0012[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1558_04a0[] = "Marvell 88E8053 Gigabit Ethernet Controller (Clevo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_15bd_1003[] = "Marvell 88E8053 Gigabit Ethernet Controller (DFI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203c[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1695_9029[] = "Marvell 88E8053 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17f2_2c08[] = "Marvell 88E8053 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17ff_0585[] = "Marvell 88E8053 Gigabit Ethernet Controller (Quanta)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1849_8053[] = "Marvell 88E8053 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000c[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0010[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0013[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0014[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0015[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001a[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001d[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001f[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0021[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0022[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_270f_2801[] = "Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_a0a0_0506[] = "Marvell 88E8053 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4363[] = "88E8055 PCI-E Gigabit Ethernet Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_5005[] = "Belkin F5D5005 Gigabit Desktop Network PCI Card"; +static const char pci_device_11ab_5040[] = "MV88SX5040 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5041[] = "MV88SX5041 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5080[] = "MV88SX5080 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5081[] = "MV88SX5081 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_6041[] = "MV88SX6041 4-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6081[] = "MV88SX6081 8-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6460[] = "MV64360/64361/64362 System Controller"; +static const char pci_device_11ab_6480[] = "MV64460/64461/64462 System Controller"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +static const char pci_device_11af_0001[] = "Cinema"; +static const char pci_device_11af_ee40[] = "Digidesign Audiomedia III"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +static const char pci_device_11bd_bede[] = "Pinnacle AV/DV Studio Capture Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Agere Systems"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2203[] = "PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2204[] = "PRO/100+ MiniPCI on Armada E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1033_80a8[] = "Versa Note Vxi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1468_0450[] = "Evo N600c"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_4005_144f[] = "LifeBook C Series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_048c[] = "V.92 56K WinModem"; +static const char pci_device_11c1_048f[] = "V.92 56k WinModem"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_8086_524c[] = "D865PERL mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +static const char pci_device_11c1_8110[] = "T8110 H.100/H.110 TDM switch"; +static const char pci_device_11c1_ab10[] = "WL60010 Wireless LAN MAC"; +static const char pci_device_11c1_ab11[] = "WL60040 Multimode Wireles LAN MAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab12[] = "WaveLAN 11abg Cardbus card (Model 1102)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab13[] = "WaveLAN 11abg MiniPCI card (Model 0512)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab15[] = "WaveLAN 11abg Cardbus card (Model 1106)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab16[] = "WaveLAN 11abg MiniPCI card (Model 0516)"; +#endif +static const char pci_device_11c1_ab20[] = "ORiNOCO PCI Adapter"; +static const char pci_device_11c1_ab21[] = "Agere Wireless PCI Adapter"; +static const char pci_device_11c1_ab30[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab30_14cd_2012[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1535[] = "Blackfin BF535 processor"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +static const char pci_device_11d4_5340[] = "AD1881 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_12f8_8a02[] = "Tekram Video Kit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1de1_9fff[] = "Video Kit C210"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_0001[] = "COM-ON-AIR Dosch&Amand DECT"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 32 port w/external I/F"; +static const char pci_device_11fe_0002[] = "RocketPort 8 port w/external I/F"; +static const char pci_device_11fe_0003[] = "RocketPort 16 port w/external I/F"; +static const char pci_device_11fe_0004[] = "RocketPort 4 port w/quad cable"; +static const char pci_device_11fe_0005[] = "RocketPort 8 port w/octa cable"; +static const char pci_device_11fe_0006[] = "RocketPort 8 port w/RJ11 connectors"; +static const char pci_device_11fe_0007[] = "RocketPort 4 port w/RJ11 connectors"; +static const char pci_device_11fe_0008[] = "RocketPort 8 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_0009[] = "RocketPort 16 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_000a[] = "RocketPort Plus 4 port"; +static const char pci_device_11fe_000b[] = "RocketPort Plus 8 port"; +static const char pci_device_11fe_000c[] = "RocketModem 6 port"; +static const char pci_device_11fe_000d[] = "RocketModem 4-port"; +static const char pci_device_11fe_000e[] = "RocketPort Plus 2 port RS232"; +static const char pci_device_11fe_000f[] = "RocketPort Plus 2 port RS422"; +static const char pci_device_11fe_0801[] = "RocketPort UPCI 32 port w/external I/F"; +static const char pci_device_11fe_0802[] = "RocketPort UPCI 8 port w/external I/F"; +static const char pci_device_11fe_0803[] = "RocketPort UPCI 16 port w/external I/F"; +static const char pci_device_11fe_0805[] = "RocketPort UPCI 8 port w/octa cable"; +static const char pci_device_11fe_080c[] = "RocketModem III 8 port"; +static const char pci_device_11fe_080d[] = "RocketModem III 4 port"; +static const char pci_device_11fe_0812[] = "RocketPort UPCI Plus 8 port RS422"; +static const char pci_device_11fe_0903[] = "RocketPort Compact PCI 16 port w/external I/F"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +static const char pci_device_11ff_0003[] = "AG-5"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 CardBus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 CardBus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 CardBus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 CardBus Controller"; +static const char pci_device_1217_6933[] = "OZ6933/711E1 CardBus/SmartCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ601/6912/711E0 CardBus/SmartCardBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1014_020c[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1217_7110[] = "OZ711Mx 4-in-1 MemoryCardBus Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7112[] = "OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller"; +static const char pci_device_1217_7113[] = "OZ711EC1 SmartCardBus Controller"; +static const char pci_device_1217_7114[] = "OZ711M1/MC1 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7134[] = "OZ711MP1/MS1 MemoryCardBus Controller"; +static const char pci_device_1217_71e2[] = "OZ711E2 SmartCardBus Controller"; +static const char pci_device_1217_7212[] = "OZ711M2 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7213[] = "OZ6933E CardBus Controller"; +static const char pci_device_1217_7223[] = "OZ711M3/MC3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7233[] = "OZ711MP3/MS3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3 2000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0057[] = "Voodoo3 3000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0003[] = "Voodoo5 PCI 5500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +static const char pci_device_1227_0006[] = "Raptor GFX 8P"; +static const char pci_device_1227_0023[] = "Raptor GFX [1100T]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000f[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_1809_0016[] = "Emuzed MAUI-III PCI PVR FM TV"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +static const char pci_device_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +static const char pci_device_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +static const char pci_device_1244_2700[] = "Fritz!Card DSL SL"; +static const char pci_device_1244_2900[] = "Fritz!Card DSL v2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infortrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +static const char pci_device_1259_a117[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a120[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204 Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125b_1400_1186_1100[] = "AX8814X Based PCI Fast Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0101[] = "Saturn 4520P"; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_153b_111b[] = "Terratec 128i PCI"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700/E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_0e11_0098[] = "Evo N600c"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00b1[] = "Latitude C600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Intersil Corporation"; +static const char pci_device_1260_3872[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3872_1468_0202[] = "LAN-Express IEEE 802.11b Wireless LAN"; +#endif +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3700[] = "DWL-520 Wireless PCI Adapter, Rev E1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1385_4105[] = "MA311 802.11b wireless adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_16a5_1601[] = "AIR.mate PC-400 PCI Wireless LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_3886[] = "ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3886_17cf_0037[] = "XG-901 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_3890[] = "ISL3890 [Prism GT/Prism Duette]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2802[] = "SMC2802W Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2835[] = "SMC2835W Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_a835[] = "SMC2835W V2 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_4203[] = "WN4201B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee03[] = "SMC2802W V2 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee08[] = "SMC2835W V3 EU Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1186_3202[] = "DWL-G650 A1 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1259_c104[] = "CG-WLCB54GT Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1385_4800[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_16a5_1605[] = "ALLNET ALL0271 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0014[] = "XG-600 and clones Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0020[] = "XG-900 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +static const char pci_device_1260_ffff[] = "ISL3886IK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +static const char pci_device_126c_1211[] = "10/100BaseTX [RTL81xx]"; +static const char pci_device_126c_126c[] = "802.11b Wireless Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0501[] = "SM501 VoyagerGX Rev. AA"; +static const char pci_device_126f_0510[] = "SM501 VoyagerGX Rev. B"; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0730[] = "SM731 Cougar3DR"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1171[] = "ES1373 [AudioPCI] (also Creative Labs CT5803)"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_8001[] = "CT4751 board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_8001[] = "Sound Blaster 16PCI 4.1ch"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +static const char pci_device_1278_0710[] = "TPE5 PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0060[] = "TM8000 Northbridge"; +static const char pci_device_1279_0061[] = "TM8000 AGP bridge"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1005_127a[] = "AOpen FM56-P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9102[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8211[] = "ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller))"; +static const char pci_device_1283_8212[] = "IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8212_1283_0001[] = "IT/ITE8212 Dual channel ATA RAID controller"; +#endif +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8872[] = "IT8874F PCI Dual Serial Port Controller"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +static const char pci_device_12a3_8105[] = "T8105 H100 Digital Switch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_0000[] = "MPG160/Kuroutoshikou ITVC15-STVLP"; +static const char pci_device_12ab_0002[] = "AU8830 [Vortex2] Based Sound Card With A3D Support"; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +static const char pci_device_12ab_fff3[] = "MPG600/Kuroutoshikou ITVC16-STVLP"; +static const char pci_device_12ab_ffff[] = "MPG600/Kuroutoshikou ITVC16-STVLP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1014_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_10a9_8002[] = "Acenic Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +static const char pci_device_12ae_00fa[] = "Farallon PN9100-T Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "3Com Corp, Modem Division"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +static const char pci_device_12c4_0001[] = "Blue HEAT/PCI 8 (RS232/CL/RJ11)"; +static const char pci_device_12c4_0002[] = "Blue HEAT/PCI 4 (RS232)"; +static const char pci_device_12c4_0003[] = "Blue HEAT/PCI 2 (RS232)"; +static const char pci_device_12c4_0004[] = "Blue HEAT/PCI 8 (UNIV, RS485)"; +static const char pci_device_12c4_0005[] = "Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485)"; +static const char pci_device_12c4_0006[] = "Blue HEAT/PCI 4 (OPTO, RS485)"; +static const char pci_device_12c4_0007[] = "Blue HEAT/PCI 2+2 (RS232/485)"; +static const char pci_device_12c4_0008[] = "Blue HEAT/PCI 2 (OPTO, Tx, RS485)"; +static const char pci_device_12c4_0009[] = "Blue HEAT/PCI 2+6 (RS232/485)"; +static const char pci_device_12c4_000a[] = "Blue HEAT/PCI 8 (Tx, RS485)"; +static const char pci_device_12c4_000b[] = "Blue HEAT/PCI 4 (Tx, RS485)"; +static const char pci_device_12c4_000c[] = "Blue HEAT/PCI 2 (20 MHz, RS485)"; +static const char pci_device_12c4_000d[] = "Blue HEAT/PCI 2 PTM"; +static const char pci_device_12c4_0100[] = "NT960/PCI"; +static const char pci_device_12c4_0201[] = "cPCI Titan - 2 Port"; +static const char pci_device_12c4_0202[] = "cPCI Titan - 4 Port"; +static const char pci_device_12c4_0300[] = "CTI PCI UART 2 (RS232)"; +static const char pci_device_12c4_0301[] = "CTI PCI UART 4 (RS232)"; +static const char pci_device_12c4_0302[] = "CTI PCI UART 8 (RS232)"; +static const char pci_device_12c4_0310[] = "CTI PCI UART 1+1 (RS232/485)"; +static const char pci_device_12c4_0311[] = "CTI PCI UART 2+2 (RS232/485)"; +static const char pci_device_12c4_0312[] = "CTI PCI UART 4+4 (RS232/485)"; +static const char pci_device_12c4_0320[] = "CTI PCI UART 2"; +static const char pci_device_12c4_0321[] = "CTI PCI UART 4"; +static const char pci_device_12c4_0322[] = "CTI PCI UART 8"; +static const char pci_device_12c4_0330[] = "CTI PCI UART 2 (RS485)"; +static const char pci_device_12c4_0331[] = "CTI PCI UART 4 (RS485)"; +static const char pci_device_12c4_0332[] = "CTI PCI UART 8 (RS485)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +static const char pci_device_12d4_0200[] = "T1 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies Inc"; +static const char pci_device_12d5_0003[] = "BSP16"; +static const char pci_device_12d5_1000[] = "BSP15"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +static const char pci_device_12d8_8150[] = "PCI to PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +static const char pci_device_12d9_0002[] = "PCI Prosody"; +static const char pci_device_12d9_0004[] = "cPCI Prosody"; +static const char pci_device_12d9_0005[] = "Aculab E1/T1 PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +static const char pci_device_12de_0200[] = "CryptoSwift CS200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +static const char pci_device_12fb_0001[] = "PMC-MAI"; +static const char pci_device_12fb_00f5[] = "F5 Dakar"; +static const char pci_device_12fb_02ad[] = "PMC-2MAI"; +static const char pci_device_12fb_2adc[] = "ePMC-2ADC"; +static const char pci_device_12fb_3100[] = "PRO-3100"; +static const char pci_device_12fb_3500[] = "PRO-3500"; +static const char pci_device_12fb_4d4f[] = "Modena"; +static const char pci_device_12fb_8120[] = "ePMC-8120"; +static const char pci_device_12fb_da62[] = "Daytona C6201 PCI (Hurricane)"; +static const char pci_device_12fb_db62[] = "Ingliston XBIF"; +static const char pci_device_12fb_dc62[] = "Ingliston PLX9054"; +static const char pci_device_12fb_dd62[] = "Ingliston JTAG/ISP"; +static const char pci_device_12fb_eddc[] = "ePMC-MSDDC"; +static const char pci_device_12fb_fa01[] = "ePMC-FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Measurement Computing"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +static const char pci_device_1307_004d[] = "PCI-QUAD04"; +static const char pci_device_1307_0052[] = "PCI-DAS4020/12"; +static const char pci_device_1307_0054[] = "PCI-DIO96"; +static const char pci_device_1307_005e[] = "PCI-DAS6025"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "Linksys"; +static const char pci_device_1317_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_0985[] = "NC100 Network Everywhere Fast Ethernet 10/100"; +static const char pci_device_1317_1985[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_2850[] = "HSP MicroModem 56"; +static const char pci_device_1317_5120[] = "ADMtek ADM5120 OpenGate System-on-Chip"; +static const char pci_device_1317_8201[] = "ADMtek ADM8211 802.11b Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_10b8_2635[] = "SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_1317_8201[] = "SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card"; +#endif +static const char pci_device_1317_8211[] = "ADMtek ADM8211 802.11b Wireless Interface"; +static const char pci_device_1317_9511[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "GNIC-II PCI Gigabit Ethernet [Hamachi]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0801_1319_1319[] = "FM801 PCI Audio"; +#endif +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0802_1319_1319[] = "FM801 PCI Joystick"; +#endif +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_2081[] = "CyberSerial (8-port) ST16654"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +static const char pci_device_1331_0030[] = "ENP-2611"; +static const char pci_device_1331_8200[] = "82600 Host Bridge"; +static const char pci_device_1331_8201[] = "82600 IDE"; +static const char pci_device_1331_8202[] = "82600 USB"; +static const char pci_device_1331_8210[] = "82600 PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +static const char pci_device_1332_5425[] = "MM-5425CN PCI 64/66 Memory Module with Battery Backup"; +static const char pci_device_1332_6140[] = "MM-6140D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_2189[] = "HSP56 MicroModem"; +static const char pci_device_134d_2486[] = "2304WT V.92 MDC Modem"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7890_134d_0001[] = "PCT789 adapter"; +#endif +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_5101[] = "Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32)"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +static const char pci_device_1360_0101[] = "PCI32 DCF77 Radio Clock"; +static const char pci_device_1360_0102[] = "PCI509 DCF77 Radio Clock"; +static const char pci_device_1360_0103[] = "PCI510 DCF77 Radio Clock"; +static const char pci_device_1360_0201[] = "GPS167PCI GPS Receiver"; +static const char pci_device_1360_0202[] = "GPS168PCI GPS Receiver"; +static const char pci_device_1360_0203[] = "GPS169PCI GPS Receiver"; +static const char pci_device_1360_0301[] = "TCR510PCI IRIG Timecode Reader"; +static const char pci_device_1360_0302[] = "TCR167PCI IRIG Timecode Reader"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +static const char pci_device_136b_ff01[] = "KL5A72002 Motion JPEG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +static const char pci_device_1371_434e[] = "GigaCard Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1371_434e_1371_434e[] = "N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd."; +static const char pci_device_1374_0024[] = "Silicom Dual port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0025[] = "Silicom Quad port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0026[] = "Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0027[] = "Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0029[] = "Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002a[] = "Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002b[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002c[] = "Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002d[] = "Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002e[] = "Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002f[] = "Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0030[] = "Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0031[] = "Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter"; +static const char pci_device_1374_0032[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_0034[] = "Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0035[] = "Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0036[] = "Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0037[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0038[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0039[] = "Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_003a[] = "Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +static const char pci_device_137a_0001[] = "PCI-324 Audiowire Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +static const char pci_device_1382_0001[] = "ARC88 audio recording card"; +static const char pci_device_1382_2008[] = "Prodif 96 Pro sound system"; +static const char pci_device_1382_2088[] = "Marc 8 Midi sound system"; +static const char pci_device_1382_20c8[] = "Marc A sound system"; +static const char pci_device_1382_4008[] = "Marc 2 sound system"; +static const char pci_device_1382_4010[] = "Marc 2 Pro sound system"; +static const char pci_device_1382_4048[] = "Marc 4 MIDI sound system"; +static const char pci_device_1382_4088[] = "Marc 4 Digi sound system"; +static const char pci_device_1382_4248[] = "Marc X sound system"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_0013[] = "WG311T"; +static const char pci_device_1385_311a[] = "GA511 Gigabit Ethernet"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_4105[] = "MA311 802.11b wireless adapter"; +static const char pci_device_1385_4400[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4600[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4601[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4610[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4800[] = "WG511(v1) 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4900[] = "WG311v1 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4a00[] = "WAG311 802.11a/g Wireless PCI Adapter"; +static const char pci_device_1385_4b00[] = "WG511T 108 Mbps Wireless PC Card"; +static const char pci_device_1385_4c00[] = "WG311v2 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4e00[] = "WG511v2 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4f00[] = "WG511U Double 108 Mbps Wireless PC Card"; +static const char pci_device_1385_620a[] = "GA620 Gigabit Ethernet"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630 Gigabit Ethernet"; +static const char pci_device_1385_6b00[] = "WG311v3 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_f004[] = "FA310TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1141[] = "Industrio CP-114"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_16b8[] = "ISDN network Controller [HFC-8S]"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1708[] = "ISDN Adapter (PCI Bus, D, C, ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +static const char pci_device_13a3_001d[] = "7956 Security Processor"; +static const char pci_device_13a3_0020[] = "7955 Security Processor"; +static const char pci_device_13a3_0026[] = "8155 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0152[] = "XR17C/D152 Dual PCI UART"; +static const char pci_device_13a8_0154[] = "XR17C154 Quad UART"; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink Adapter v1"; +static const char pci_device_13c0_0020[] = "SyncLink SCC Adapter"; +static const char pci_device_13c0_0030[] = "SyncLink Multiport Adapter"; +static const char pci_device_13c0_0210[] = "SyncLink Adapter v2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "5xxx/6xxx-series PATA-RAID"; +static const char pci_device_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13c1_1001_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#endif +static const char pci_device_13c1_1002[] = "9xxx-series SATA-RAID"; +static const char pci_device_13c1_1003[] = "9550SX SATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +static const char pci_device_13c6_0520[] = "CEI-520 A429 Card"; +static const char pci_device_13c6_0620[] = "CEI-620 A429 Card"; +static const char pci_device_13c6_0820[] = "CEI-820 A429 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card"; +static const char pci_device_13d0_2200[] = "B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab03[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +static const char pci_device_13d1_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Intraserver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc / IC Plus Corp"; +static const char pci_device_13f0_0200[] = "IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +static const char pci_device_13f0_1023[] = "IC Plus IP1000 Family Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0011[] = "CMI8738"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8035[] = "CUSI-FX motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1681_a000[] = "Gamesurround MUSE XL"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1240[] = "PCI-1240 4-channel stepper motor controller card"; +static const char pci_device_13fe_1600[] = "PCI-1612 4-port RS-232/422/485 PCI communication card"; +static const char pci_device_13fe_1733[] = "PCI-1733 32-channel isolated digital input card"; +static const char pci_device_13fe_1752[] = "PCI-1752"; +static const char pci_device_13fe_1754[] = "PCI-1754"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0110[] = "Lava DSerial-PCI Port A"; +static const char pci_device_1407_0111[] = "Lava DSerial-PCI Port B"; +static const char pci_device_1407_0120[] = "Quattro-PCI A"; +static const char pci_device_1407_0121[] = "Quattro-PCI B"; +static const char pci_device_1407_0180[] = "Lava Octo A"; +static const char pci_device_1407_0181[] = "Lava Octo B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0220[] = "Lava Quattro PCI Ports A/B"; +static const char pci_device_1407_0221[] = "Lava Quattro PCI Ports C/D"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "VIA Technologies Inc."; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24] PCI Multi-Channel I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_1712[] = "Hoontech ST Audio DSP 24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d630[] = "M-Audio Delta 1010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d631[] = "M-Audio Delta DiO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d632[] = "M-Audio Delta 66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d633[] = "M-Audio Delta 44"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d634[] = "M-Audio Delta Audiophile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d635[] = "M-Audio Delta TDIF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d637[] = "M-Audio Delta RBUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d638[] = "M-Audio Delta 410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63b[] = "M-Audio Delta 1010LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63c[] = "Digigram VX442"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1416_1712[] = "Hoontech ST Audio DSP 24 Media 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1115[] = "EWS88 MT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1125[] = "EWS88 MT (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112b[] = "EWS88 D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112c[] = "EWS88 D (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1130[] = "EWX 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1138[] = "DMX 6fire 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1151[] = "PHASE88"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_16ce_1040[] = "Edirol DA-2496"; +#endif +static const char pci_device_1412_1724[] = "VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_1724[] = "AMP Ltd AUDIO2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3630[] = "M-Audio Revolution 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3631[] = "M-Audio Revolution 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1145[] = "Aureon 7.1 Space"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1147[] = "Aureon 5.1 Sky"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1153[] = "Aureon 7.1 Universe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f641[] = "ZNF3-150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f645[] = "ZNF3-250"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2050[] = "CyberPro (4-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2051[] = "CyberSerial 4S Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9510[] = "OX16PCI954 (Quad 16950 UART) function 1 (Disabled)"; +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +static const char pci_device_1415_9523[] = "OX16PCI952 Integrated Parallel Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +static const char pci_device_1420_8002[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part)"; +static const char pci_device_1420_8003[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "Chelsio Communications Inc"; +static const char pci_device_1425_000b[] = "T210 Protocol Engine"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +static const char pci_device_142e_4020[] = "VM2-2 [Video Maker 2] MPEG1/2 Encoder"; +static const char pci_device_142e_4337[] = "VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +static const char pci_device_1432_9130[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "RTD Embedded Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8164[] = "PCI-8164"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +static const char pci_device_1458_0c11[] = "K8NS Pro Mainboard"; +static const char pci_device_1458_e911[] = "GN-WIAG02"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +static const char pci_device_1461_a3ce[] = "AVerMedia M179"; +static const char pci_device_1461_a3cf[] = "AVerMedia M179"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +static const char pci_device_1462_5501[] = "nVidia NV15DDR [GeForce2 Ti]"; +static const char pci_device_1462_6819[] = "Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G]"; +static const char pci_device_1462_6825[] = "PCI Card wireless 11g [PC54G]"; +static const char pci_device_1462_8725[] = "NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter"; +static const char pci_device_1462_9000[] = "NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter"; +static const char pci_device_1462_9110[] = "GeFORCE FX5200"; +static const char pci_device_1462_9119[] = "NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter"; +static const char pci_device_1462_9591[] = "nVidia Corporation NV36 [GeForce FX 5700LE]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +static const char pci_device_146c_1430[] = "FE-1430TX Fast Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +static const char pci_device_1497_1497[] = "SMA Technologie AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +static const char pci_device_1498_21cd[] = "TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_30c8[] = "TPCI200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +static const char pci_device_149d_0001[] = "Video Toaster for PC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "PulsarSRB"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +static const char pci_device_14b9_a505[] = "Cisco Aironet CB20a 802.11a Wireless LAN Adapter"; +static const char pci_device_14b9_a506[] = "Cisco Aironet Mini PCI b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +static const char pci_device_14c1_8043[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alliance Semiconductor Corporation"; +static const char pci_device_14d9_0010[] = "AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon]"; +static const char pci_device_14d9_9000[] = "AS90L10204/10208 HyperTransport to PCI-X Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_0800[] = "Sentry5 Chipcommon I/O Controller"; +static const char pci_device_14e4_0804[] = "Sentry5 PCI Bridge"; +static const char pci_device_14e4_0805[] = "Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_0806[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_080b[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_080f[] = "Sentry5 DDR/SDR RAM Controller"; +static const char pci_device_14e4_0811[] = "Sentry5 External Interface Core"; +static const char pci_device_14e4_0816[] = "BCM3302 Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_1600[] = "NetXtreme BCM5752 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1601[] = "NetXtreme BCM5752M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128a[] = "1000Base-T (PCI) [A7061A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128b[] = "1000Base-SX (PCI) [A7073A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12a4[] = "Core Lan 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12c1[] = "IOX Core Lan 1000Base-T [A7109AX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_1300[] = "Core LAN/SCSI Combo [A6794A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8010[] = "IO9/IO10 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8011[] = "Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8012[] = "Gigabit Ethernet (Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_10a9_8010[] = "SGI IO9 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1734_100b[] = "Primergy RX300"; +#endif +static const char pci_device_14e4_164a[] = "NetXtreme II BCM5706 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3101[] = "NC370T Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164c[] = "NetXtreme II BCM5708 Gigabit Ethernet"; +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1653_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1654[] = "NetXtreme BCM5705_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3100[] = "NC1020 HP ProLiant Gigabit Server Adapter 32 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3226[] = "NC150T 4-port Gigabit Combo Switch & Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1659[] = "NetXtreme BCM5721 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7031[] = "NC320T PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7032[] = "NC320i PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1734_1061[] = "Primergy RX300 S2"; +#endif +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165d_1028_865d[] = "Latitude D400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_165e[] = "NetXtreme BCM5705M_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1668[] = "NetXtreme BCM5714 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1668_103c_7039[] = "NC324i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_166a[] = "NetXtreme BCM5780 Gigabit Ethernet"; +static const char pci_device_14e4_166b[] = "NetXtreme BCM5780S Gigabit Ethernet"; +static const char pci_device_14e4_166e[] = "570x 10/100 Integrated Controller"; +static const char pci_device_14e4_1677[] = "NetXtreme BCM5751 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0182[] = "Latitude D610"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_01ad[] = "Optiplex GX620"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1734_105d[] = "Scenic W620"; +#endif +static const char pci_device_14e4_1678[] = "NetXtreme BCM5715 Gigabit Ethernet"; +static const char pci_device_14e4_167d[] = "NetXtreme BCM5751M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167e[] = "NetXtreme BCM5751F Fast Ethernet PCI Express"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_103c_12bc[] = "HP d530 CMT (DG746A)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_169c[] = "NetXtreme BCM5788 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_169c_103c_308b[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_169d[] = "NetLink BCM5789 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16aa[] = "NetXtreme II BCM5706S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16aa_103c_3102[] = "NC370F Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16ac[] = "NetXtreme II BCM5708S Gigabit Ethernet"; +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702A3 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12c3[] = "Combo FC/GigE-SX [A9782A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12ca[] = "Combo FC/GigE-T [A9784A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_16dd[] = "NetLink BCM5781 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16f7[] = "NetXtreme BCM5753 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fd[] = "NetXtreme BCM5753M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fe[] = "NetXtreme BCM5753F Fast Ethernet PCI Express"; +static const char pci_device_14e4_170c[] = "BCM4401-B0 100Base-TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_170d[] = "NetXtreme BCM5901 100Base-TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170d_1014_0545[] = "ThinkPad R40e (2684-HVG) builtin ethernet controller"; +#endif +static const char pci_device_14e4_170e[] = "NetXtreme BCM5901 100Base-TX"; +static const char pci_device_14e4_3352[] = "BCM3352"; +static const char pci_device_14e4_3360[] = "BCM3360"; +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4303 802.11b Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1028_0407[] = "TrueMobile 1180 Onboard WLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1043_0120[] = "WL-103b Wireless LAN PC Card"; +#endif +static const char pci_device_14e4_4305[] = "BCM4307 V.90 56k Modem"; +static const char pci_device_14e4_4306[] = "BCM4307 Ethernet Controller"; +static const char pci_device_14e4_4307[] = "BCM4307 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4310[] = "BCM4310 Chipcommon I/OController"; +static const char pci_device_14e4_4312[] = "BCM4310 UART"; +static const char pci_device_14e4_4313[] = "BCM4310 Ethernet Controller"; +static const char pci_device_14e4_4315[] = "BCM4310 USB Controller"; +static const char pci_device_14e4_4318[] = "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_103c_1356[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0311[] = "Aspire 3022WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_0449[] = "Gateway 7510GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_4318[] = "WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_16ec_0119[] = "U.S.Robotics Wireless MAXg PC Card"; +#endif +static const char pci_device_14e4_4319[] = "Dell Wireless 1470 DualBand WLAN"; +static const char pci_device_14e4_4320[] = "BCM4306 802.11b/g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0001[] = "TrueMobile 1300 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0003[] = "Wireless 1350 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12fa[] = "Presario R3000 802.11b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1043_100f[] = "WL-100G"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1057_7025[] = "WN825G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_106b_004e[] = "AirPort Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_14e4_4320[] = "Linksys WMP54G PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1737_4320[] = "WPC54G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7001[] = "Belkin F5D7001 High-Speed Mode Wireless G Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7010[] = "Belkin F5D7010 54g Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_185f_1220[] = "Acer TravelMate 290E WLAN Mini-PCI Card"; +#endif +static const char pci_device_14e4_4321[] = "BCM4306 802.11a Wireless LAN Controller"; +static const char pci_device_14e4_4322[] = "BCM4306 UART"; +static const char pci_device_14e4_4324[] = "BCM4309 802.11a/b/g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0001[] = "Truemobile 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0003[] = "Truemobile 1450 MiniPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_4325[] = "BCM43xG 802.11b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0003[] = "Wireless Notebook Adapter MN-720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0004[] = "Wireless PCI Adapter MN-730"; +#endif +static const char pci_device_14e4_4326[] = "BCM4307 Chipcommon I/O Controller?"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_1043_80a8[] = "A7V8X motherboard"; +#endif +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4403[] = "BCM4402 V.90 56k Modem"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4412 10/100BaseT"; +static const char pci_device_14e4_4430[] = "BCM44xx CardBus iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4432[] = "BCM4432 CardBus 10/100BaseT"; +static const char pci_device_14e4_4610[] = "BCM4610 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4611[] = "BCM4610 Sentry5 iLine32 HomePNA 1.0"; +static const char pci_device_14e4_4612[] = "BCM4610 Sentry5 V.90 56k Modem"; +static const char pci_device_14e4_4613[] = "BCM4610 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4614[] = "BCM4610 Sentry5 External Interface"; +static const char pci_device_14e4_4615[] = "BCM4610 Sentry5 USB Controller"; +static const char pci_device_14e4_4704[] = "BCM4704 PCI to SB Bridge"; +static const char pci_device_14e4_4705[] = "BCM4704 Sentry5 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4706[] = "BCM4704 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4707[] = "BCM4704 Sentry5 USB Controller"; +static const char pci_device_14e4_4708[] = "BCM4704 Crypto Accelerator"; +static const char pci_device_14e4_4710[] = "BCM4710 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4711[] = "BCM47xx Sentry5 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4712[] = "BCM47xx V.92 56k modem"; +static const char pci_device_14e4_4713[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4714[] = "BCM47xx Sentry5 External Interface"; +static const char pci_device_14e4_4715[] = "Sentry5 USB Controller"; +static const char pci_device_14e4_4716[] = "BCM47xx Sentry5 USB Host Controller"; +static const char pci_device_14e4_4717[] = "BCM47xx Sentry5 USB Device Controller"; +static const char pci_device_14e4_4718[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_4720[] = "BCM4712 MIPS CPU"; +static const char pci_device_14e4_5365[] = "BCM5365P Sentry5 Host Bridge"; +static const char pci_device_14e4_5600[] = "BCM5600 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5605[] = "BCM5605 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5615[] = "BCM5615 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5625[] = "BCM5625 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5645[] = "BCM5645 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5670[] = "BCM5670 8-Port 10GE Ethernet Switch Fabric"; +static const char pci_device_14e4_5680[] = "BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5690[] = "BCM5690 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5691[] = "BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5692[] = "BCM5692 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +static const char pci_device_14e4_5822[] = "BCM5822 Crypto Accelerator"; +static const char pci_device_14e4_5823[] = "BCM5823 Crypto Accelerator"; +static const char pci_device_14e4_5824[] = "BCM5824 Crypto Accelerator"; +static const char pci_device_14e4_5840[] = "BCM5840 Crypto Accelerator"; +static const char pci_device_14e4_5841[] = "BCM5841 Crypto Accelerator"; +static const char pci_device_14e4_5850[] = "BCM5850 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +static const char pci_device_14ea_ab07[] = "RTL81xx RealTek Ethernet"; +static const char pci_device_14ea_ab08[] = "FNW-3602-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1085[] = "HCF V90 56k Data/Fax/Voice/Spkp PCI Modem"; +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1620[] = "AccessRunner V2 PCI ADSL Arbitration Device"; +static const char pci_device_14f1_1621[] = "AccessRunner V2 PCI ADSL Interface Device"; +static const char pci_device_14f1_1622[] = "AccessRunner V2 PCI ADSL Yukon WAN Adapter"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1811[] = "Conextant MiniPCI Network Adapter"; +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2045_14f1_2045[] = "Generic SoftK56"; +#endif +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_2f02[] = "HSF 56k HSFi Data/Fax"; +static const char pci_device_14f1_2f11[] = "HSF 56k HSFi Modem"; +static const char pci_device_14f1_2f20[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +static const char pci_device_14f1_8800[] = "CX23880/1/2/3 PCI Video and Audio Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9002[] = "Hauppauge Nova-T DVB-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_00f8[] = "ATI TV Wonder Pro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6613[] = "Leadtek Winfast 2000XP Expert"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6620[] = "Leadtek Winfast DV2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d003[] = "IODATA GV-VCP3/PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d035[] = "IODATA GV/BCTV7E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000b[] = "AverTV Studio 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14c7_0107[] = "GDI Black Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0342[] = "Digital-Logic MICROSPACE Entertainment Center (MEC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1540_2580[] = "Provideo PV259"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4811[] = "PixelView"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_a8a6[] = "digitalnow DNTV Live! DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8801[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8801_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +static const char pci_device_14f1_8802[] = "CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8804[] = "CX23880/1/2/3 PCI Video and Audio Decoder [IR Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8804_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +static const char pci_device_14f1_8811[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +static const char pci_device_14f2_0120[] = "EV1000 bridge"; +static const char pci_device_14f2_0121[] = "EV1000 Parallel port"; +static const char pci_device_14f2_0122[] = "EV1000 Serial port"; +static const char pci_device_14f2_0123[] = "EV1000 Keyboard controller"; +static const char pci_device_14f2_0124[] = "EV1000 Mouse controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BroadLogic"; +static const char pci_device_14f3_2030[] = "2030 DVB-S Satellite Reciever"; +static const char pci_device_14f3_2050[] = "2050 DVB-T Terrestrial (Cable) Reciever"; +static const char pci_device_14f3_2060[] = "2060 ATSC Terrestrial (Cable) Reciever"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +static const char pci_device_14f8_2077[] = "TP-240 dual span E1 VoIP PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOLTERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "Quadrics Ltd"; +static const char pci_device_14fc_0000[] = "QsNet Elan3 Network Adapter"; +static const char pci_device_14fc_0001[] = "QsNetII Elan4 Network Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +static const char pci_device_1500_1360[] = "RTL81xx RealTek Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0800[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +static const char pci_device_1516_0891[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +static const char pci_device_151c_0003[] = "Prodif T 2496"; +static const char pci_device_151c_4000[] = "Prodif 88"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0c00[] = "RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0d00[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_1d00[] = "RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2000[] = "RockForceD1 1 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2100[] = "RockForceF1 1 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2200[] = "RockForceD2 2 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2300[] = "RockForceF2 2 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2400[] = "RockForceD4 4 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2500[] = "RockForceF4 4 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2600[] = "RockForceD8 8 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2700[] = "RockForceF8 8 Port V.34 Super-G3 Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_0510[] = "CB710 Memory Card Reader Controller"; +static const char pci_device_1524_0520[] = "FLASH memory: ENE Technology Inc:"; +static const char pci_device_1524_0530[] = "ENE PCI Memory Stick Card Reader Controller"; +static const char pci_device_1524_0550[] = "ENE PCI Secure Digital Card Reader Controller"; +static const char pci_device_1524_0610[] = "PCI Smart Card Reader Controller"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1411[] = "CB-710/2/4 Cardbus Controller"; +static const char pci_device_1524_1412[] = "CB-712/4 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +static const char pci_device_1524_1421[] = "CB-720/2/4 Cardbus Controller"; +static const char pci_device_1524_1422[] = "CB-722/4 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +static const char pci_device_1538_0303[] = "ARS106S Ultra ATA 133/100/66 Host Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +static const char pci_device_153b_1144[] = "Aureon 5.1"; +static const char pci_device_153b_1147[] = "Aureon 5.1 Sky"; +static const char pci_device_153b_1158[] = "Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS Technologies, Inc."; +static const char pci_device_153f_0001[] = "SOC-it 101 System Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "VIVID Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +static const char pci_device_1578_5615[] = "VPMK3 [Video Processor Mk III]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMware Inc"; +static const char pci_device_15ad_0405[] = "[VMware SVGA II] PCI Display Adapter"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +static const char pci_device_15ad_0720[] = "VMware High-Speed Virtual NIC [vmxnet]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technologies"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +static const char pci_device_15b3_5a44[] = "MT23108 InfiniHost"; +static const char pci_device_15b3_5a45[] = "MT23108 [Infinihost HCA Flash Recovery]"; +static const char pci_device_15b3_5a46[] = "MT23108 PCI Bridge"; +static const char pci_device_15b3_5e8d[] = "MT25204 [InfiniHost III Lx HCA Flash Recovery]"; +static const char pci_device_15b3_6274[] = "MT25204 [InfiniHost III Lx HCA]"; +static const char pci_device_15b3_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_15b3_6279[] = "MT25208 [InfiniHost III Ex HCA Flash Recovery]"; +static const char pci_device_15b3_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_1100[] = "E8001-66442 PCI Express CIC"; +static const char pci_device_15bc_2922[] = "64 Bit, 133MHz PCI-X Exerciser & Protocol Checker"; +static const char pci_device_15bc_2928[] = "64 Bit, 66MHz PCI Exerciser & Analyzer"; +static const char pci_device_15bc_2929[] = "64 Bit, 133MHz PCI-X Analyzer & Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +static const char pci_device_15c5_8010[] = "1394b - 1394 Firewire 3-Port Host Adapter Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +static const char pci_device_15e9_1841[] = "ADMA-100 DiscStaQ ATA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +static const char pci_device_15ec_3101[] = "FC3101 Profibus DP 1 Channel PCI"; +static const char pci_device_15ec_5102[] = "FC5102"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_0610[] = "FarSync T1U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0620[] = "FarSync T2U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0640[] = "FarSync T4U (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_1610[] = "FarSync TE1 (T1,E1)"; +static const char pci_device_1619_2610[] = "FarSync DSL-S1 (SHDSL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_161f[] = "Rioworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1626[] = "TDK Semiconductor Corp."; +static const char pci_device_1626_8410[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1637[] = "Linksys"; +static const char pci_device_1637_3874[] = "Linksys 802.11b WMP11 PCI Wireless card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_3052[] = "SmartLink SmartPCI562 56K Modem"; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165f[] = "Linux Media Labs, LLC"; +static const char pci_device_165f_1020[] = "LMLM4 MPEG-4 encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +static const char pci_device_1668_0100[] = "Mini-PCI bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_166d[] = "Broadcom Corporation"; +static const char pci_device_166d_0001[] = "SiByte BCM1125/1125H/1250 System-on-a-Chip PCI"; +static const char pci_device_166d_0002[] = "SiByte BCM1125H/1250 System-on-a-Chip HyperTransport"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1677[] = "Bernecker + Rainer"; +static const char pci_device_1677_104e[] = "5LS172.6 B&R Dual CAN Interface Card"; +static const char pci_device_1677_12d7[] = "5LS172.61 B&R Dual CAN Interface Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167b[] = "ZyDAS Technology Corp."; +static const char pci_device_167b_2102[] = "ZyDAS ZD1202"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_167b_2102_187e_3406[] = "ZyAIR B-122 CardBus 11Mbs Wireless LAN Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +static const char pci_device_1681_0010[] = "Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1682[] = "XFX Pine Group Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1688[] = "CastleNet Technology Inc."; +static const char pci_device_1688_1170[] = "WLAN 802.11b card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_168c[] = "Atheros Communications, Inc."; +static const char pci_device_168c_0007[] = "AR5000 802.11a Wireless Adapter"; +static const char pci_device_168c_0011[] = "AR5210 802.11a NIC"; +static const char pci_device_168c_0012[] = "AR5211 802.11ab NIC"; +static const char pci_device_168c_0013[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1113_d301[] = "Philips CPWNA100 Wireless CardBus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3202[] = "D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3203[] = "DWL-G520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a12[] = "D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a13[] = "D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a14[] = "D-Link AirPremier DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a17[] = "D-Link AirPremier DWL-G680 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a18[] = "D-Link AirPremier DWL-G550 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a63[] = "D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a94[] = "C54C Wireless 801.11g cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1385_4d00[] = "Netgear WG311T Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1458_e911[] = "Gigabyte GN-WIAG02"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_14b7_0a60[] = "8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_0013[] = "WG511T Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1025[] = "DWL-G650B2 Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1027[] = "Netgate NL-3054CB ARIES b/g CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2026[] = "Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2041[] = "Netgate 5354MP Plus ARIES2 b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2042[] = "Netgate 5354MP Plus ARIES2 a/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_16ab_7302[] = "Trust Speedshare Turbo Pro Wireless PCI Adapter"; +#endif +static const char pci_device_168c_001a[] = "AR5005G 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a15[] = "D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a16[] = "D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a23[] = "D-Link AirPlus G DWL-G520+A Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a24[] = "D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_1052[] = "TP-Link TL-WN510G Wireless CardBus Adapter"; +#endif +static const char pci_device_168c_001b[] = "AR5006X 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a19[] = "D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a22[] = "D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter"; +#endif +static const char pci_device_168c_0020[] = "AR5005VL 802.11bg Wireless NIC"; +static const char pci_device_168c_1014[] = "AR5212 802.11abg NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1695[] = "EPoX Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_169c[] = "Netcell Corporation"; +static const char pci_device_169c_0044[] = "Revolution Storage Processing Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16a5[] = "Tekram Technology Co.,Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1100[] = "GL24110P"; +static const char pci_device_16ab_1101[] = "PLX9052 PCMCIA-to-PCI Wireless LAN"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +static const char pci_device_16ab_8501[] = "WL-8305 Wireless LAN PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ae[] = "Safenet Inc"; +static const char pci_device_16ae_1141[] = "SafeXcel-1141"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16af[] = "SparkLAN Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b4[] = "Aspex Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b8[] = "Sonnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c8[] = "Octasic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ca[] = "CENATEK Inc"; +static const char pci_device_16ca_0001[] = "Rocket Drive DL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16cd[] = "Densitron Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ce[] = "Roland Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16df[] = "PIKA Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e3[] = "European Space Agency"; +static const char pci_device_16e3_1e0f[] = "LEON2FT Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_00ff[] = "USR997900 10/100 Mbps PCI Network Card"; +static const char pci_device_16ec_0116[] = "USR997902 10/100/1000 Mbps PCI Network Card"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ed[] = "Sycron N. V."; +static const char pci_device_16ed_1001[] = "UMIO communication card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f3[] = "Jetway Information Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f4[] = "Vweb Corp"; +static const char pci_device_16f4_8000[] = "VW2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1702[] = "Internet Machines Corporation (IMC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave"; +static const char pci_device_170b_0100[] = "NSP2000-SSL crypto accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1725[] = "Vitesse Semiconductor"; +static const char pci_device_1725_7174[] = "VSC7174 PCI/PCI-X Serial ATA Host Bus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +static const char pci_device_172a_13c8[] = "AEP SureWare Runner 1000V3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1734[] = "Fujitsu Siemens Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +static const char pci_device_1737_0013[] = "WMP54G Wireless Pci Card"; +static const char pci_device_1737_0015[] = "WMP54GS Wireless Pci Card"; +static const char pci_device_1737_1032[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0015[] = "EG1032 v2 Instant Gigabit Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0024[] = "EG1032 v3 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_1064[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1064_1737_0016[] = "EG1064 v2 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1737_ab09[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03e9[] = "AC1001 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +static const char pci_device_173b_03eb[] = "AC1003 Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1749[] = "RLX Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174d[] = "WellX Telecom SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175c[] = "AudioScience Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1775[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1797[] = "JumpTec h, GMBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +static const char pci_device_1799_6001[] = "Wireless PCI Card - F5D6001"; +static const char pci_device_1799_6020[] = "Wireless PCMCIA Card - F5D6020"; +static const char pci_device_1799_6060[] = "Wireless PDA Card - F5D6060"; +static const char pci_device_1799_7000[] = "Wireless PCI Card - F5D7000"; +static const char pci_device_1799_7010[] = "BCM4306 802.11b/g Wireless Lan Controller F5D7010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_179c[] = "Data Patterns"; +static const char pci_device_179c_0557[] = "DP-PCI-557 [PCI 1553B]"; +static const char pci_device_179c_0566[] = "DP-PCI-566 [Intelligent PCI 1553B]"; +static const char pci_device_179c_5031[] = "DP-CPCI-5031-Synchro Module"; +static const char pci_device_179c_5121[] = "DP-CPCI-5121-IP Carrier"; +static const char pci_device_179c_5211[] = "DP-CPCI-5211-IP Carrier"; +static const char pci_device_179c_5679[] = "AGE Display Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17a0[] = "Genesys Logic, Inc"; +static const char pci_device_17a0_8033[] = "GL880S USB 1.1 controller"; +static const char pci_device_17a0_8034[] = "GL880S USB 2.0 controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17aa[] = "Lenovo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b3[] = "Hawking Technologies"; +static const char pci_device_17b3_ab08[] = "PN672TX 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b4[] = "Indra Networks, Inc."; +static const char pci_device_17b4_0011[] = "WebEnhance 100 GZIP Compression Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c0[] = "Wistron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c2[] = "Newisys, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cb[] = "Airgo Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cf[] = "Z-Com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d3[] = "Areca Technology Corp."; +static const char pci_device_17d3_1110[] = "ARC-1110 4-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1120[] = "ARC-1120 8-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1130[] = "ARC-1130 12-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1160[] = "ARC-1160 16-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1210[] = "ARC-1210 4-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1220[] = "ARC-1220 8-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1230[] = "ARC-1230 12-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1260[] = "ARC-1260 16-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_5831[] = "Xframe 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d3_5831_103c_12d5[] = "HP PCI-X 133MHz 10GbE SR Fiber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_17d3_5832[] = "Xframe II 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17de[] = "KWorld Computer Co. Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ee[] = "Connect Components Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17f2[] = "Albatron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17fe[] = "Linksys, A Division of Cisco Systems"; +static const char pci_device_17fe_2120[] = "WMP11v4 802.11b PCI card"; +static const char pci_device_17fe_2220[] = "[AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17fe_2220_17fe_2220[] = "WPC54G ver. 4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ff[] = "Benq Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1814[] = "RaLink"; +static const char pci_device_1814_0101[] = "Wireless PCI Adapter RT2400 / RT2460"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1043_0127[] = "WiFi-b add-on Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1462_6828[] = "PC11B2 (MS-6828) Wireless 11b PCI Card"; +#endif +static const char pci_device_1814_0201[] = "RT2500 802.11G Cardbus/mini-PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1043_130f[] = "WL-130g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001e[] = "CWC-854 Wireless-G CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001f[] = "CWM-854 Wireless-G Mini PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_0020[] = "CWP-854 Wireless-G PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e381[] = "GN-WMKG 802.11b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e931[] = "GN-WIKG 802.11b/g mini-PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1462_6835[] = "Wireless 11G CardBus CB54G2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1737_0032[] = "WMP54G 2.0 PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_700a[] = "F5D7000 Wireless G Desktop Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_701a[] = "F5D7010 Wireless G Notebook Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_185f_22a0[] = "CN-WF513 Wireless Cardbus Adapter"; +#endif +static const char pci_device_1814_0401[] = "Ralink RT2600 802.11 MIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1820[] = "InfiniCon Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1822[] = "Twinhan Technology Co. Ltd"; +static const char pci_device_1822_4e35[] = "Mantis DTV PCI Bridge Controller [Ver 1.0]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182d[] = "SiteCom Europe BV"; +static const char pci_device_182d_3069[] = "ISDN PCI DC-105V2"; +static const char pci_device_182d_9790[] = "WL-121 Wireless Network Adapter 100g+ [Ver.3]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1830[] = "Credence Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_183b[] = "MikroM GmbH"; +static const char pci_device_183b_08a7[] = "MVC100 DVI"; +static const char pci_device_183b_08a8[] = "MVC101 SDI"; +static const char pci_device_183b_08a9[] = "MVC102 DVI+Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1849[] = "ASRock Incorporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1854[] = "LG Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185b[] = "Compro Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185f[] = "Wistron NeWeb Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1864[] = "SilverBack"; +static const char pci_device_1864_2110[] = "ISNAP 2110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1867[] = "Topspin Communications"; +static const char pci_device_1867_5a44[] = "MT23108 InfiniHost HCA"; +static const char pci_device_1867_5a45[] = "MT23108 InfiniHost HCA flash recovery"; +static const char pci_device_1867_5a46[] = "MT23108 InfiniHost HCA bridge"; +static const char pci_device_1867_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_1867_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_187e[] = "ZyXEL Communication Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1894[] = "KNC One"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1896[] = "B&B Electronics Manufacturing Company, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18a1[] = "Astute Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ac[] = "DViCO Corporation"; +static const char pci_device_18ac_d500[] = "FusionHDTV 5"; +static const char pci_device_18ac_d810[] = "FusionHDTV 3 Gold"; +static const char pci_device_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18b8[] = "Ammasso"; +static const char pci_device_18b8_b001[] = "AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18bc[] = "Info-Tek Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c8[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c9[] = "ARVOO Engineering BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ca[] = "XGI - Xabre Graphics Inc"; +static const char pci_device_18ca_0020[] = "Volari Z7"; +static const char pci_device_18ca_0040[] = "Volari V3XT/V5/V8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18d2[] = "Sitecom"; +static const char pci_device_18d2_3069[] = "DC-105v2 ISDN controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18dd[] = "Artimi Inc"; +static const char pci_device_18dd_4c6f[] = "Artimi RTMI-100 UWB adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18e6[] = "MPL AG"; +static const char pci_device_18e6_0001[] = "OSCI [Octal Serial Communication Interface]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ec[] = "Cesnet, z.s.p.o."; +static const char pci_device_18ec_c006[] = "COMBO6"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d004[] = "COMBO-2XFP"; +#endif +static const char pci_device_18ec_c045[] = "COMBO6E"; +static const char pci_device_18ec_c050[] = "COMBO-PTM"; +static const char pci_device_18ec_c058[] = "COMBO6X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d004[] = "COMBO-2XFP"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f7[] = "Commtech, Inc."; +static const char pci_device_18f7_0001[] = "Fastcom ESCC-PCI-335"; +static const char pci_device_18f7_0002[] = "Fastcom 422/4-PCI-335"; +static const char pci_device_18f7_0004[] = "Fastcom 422/2-PCI-335"; +static const char pci_device_18f7_0005[] = "Fastcom IGESCC-PCI-ISO/1"; +static const char pci_device_18f7_000a[] = "Fastcom 232/4-PCI-335"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18fb[] = "Resilience Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1924[] = "Level 5 Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_192e[] = "TransDimension"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1931[] = "Option N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1942[] = "ClearSpeed Technology plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1957[] = "Freescale Semiconductor Inc"; +static const char pci_device_1957_0080[] = "MPC8349E"; +static const char pci_device_1957_0081[] = "MPC8349"; +static const char pci_device_1957_0082[] = "MPC8347E TBGA"; +static const char pci_device_1957_0083[] = "MPC8347 TBGA"; +static const char pci_device_1957_0084[] = "MPC8347E PBGA"; +static const char pci_device_1957_0085[] = "MPC8347 PBGA"; +static const char pci_device_1957_0086[] = "MPC8343E"; +static const char pci_device_1957_0087[] = "MPC8343"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1958[] = "Faster Technology, LLC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1966[] = "Orad Hi-Tec Systems"; +static const char pci_device_1966_1975[] = "DVG64 family"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196a[] = "Sensory Networks Inc."; +static const char pci_device_196a_0101[] = "NodalCore C-1000 Content Classification Accelerator"; +static const char pci_device_196a_0102[] = "NodalCore C-2000 Content Classification Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_197b[] = "JMicron Technologies, Inc."; +static const char pci_device_197b_2360[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2363[] = "JMicron 20360/20363 AHCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1989[] = "Montilio Inc."; +static const char pci_device_1989_0001[] = "RapidFile Bridge"; +static const char pci_device_1989_8001[] = "RapidFile"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1993[] = "Innominate Security Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ae[] = "Progeny Systems Corporation"; +static const char pci_device_19ae_0520[] = "4135 HFT Interface Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19d4[] = "Quixant Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc0[] = "Tumsan Oy"; +static const char pci_device_1fc0_0300[] = "E2200 Dual E1/Rawpipe Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc1[] = "PathScale, Inc"; +static const char pci_device_1fc1_000d[] = "InfiniPath HT-400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fce[] = "Cognio Inc."; +static const char pci_device_1fce_0001[] = "Spectrum Analyzer PC Card (SAgE)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0020[] = "HB6 Universal PCI-PCI bridge (transparent mode)"; +static const char pci_device_3388_0021[] = "HB6 Universal PCI-PCI bridge (non-transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1090[] = "Cx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3010[] = "PPCI mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3011[] = "PPCI mezzanine (64-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_4000[] = "PMCCARR1 carrier board"; +#endif +static const char pci_device_3388_0022[] = "HiNT HB4 PCI-PCI Bridge (PCI6150)"; +static const char pci_device_3388_0026[] = "HB2 PCI-PCI Bridge"; +static const char pci_device_3388_101a[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_101b[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3842[] = "eVga.com. Corp."; +static const char pci_device_3842_c370[] = "e-GeFORCE 6600 256 DDR PCI-e"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0002_0000_0000[] = "GLoria L"; +#endif +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0003_0000_0000[] = "GLoria XL"; +#endif +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_0000_0000[] = "GLoria XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0008_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1048_0a42[] = "GLoria XXL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_000d[] = "GLint R4 rev A"; +static const char pci_device_3d3d_0011[] = "GLint R4 rev B"; +static const char pci_device_3d3d_0012[] = "GLint R5 rev A"; +static const char pci_device_3d3d_0013[] = "GLint R5 rev B"; +static const char pci_device_3d3d_0020[] = "VP10 visual processor"; +static const char pci_device_3d3d_0022[] = "VP10 visual processor"; +static const char pci_device_3d3d_0024[] = "VP9 visual processor"; +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_07a1[] = "Wildcat III 6210"; +static const char pci_device_3d3d_07a2[] = "Sun XVR-500 Graphics Accelerator"; +static const char pci_device_3d3d_07a3[] = "Wildcat IV 7210"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4144[] = "Alpha Data"; +static const char pci_device_4144_0044[] = "ADM-XRCIIPro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0016[] = "iTVC16 (CX23416) MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4009[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8003[] = "WinTV PVR 150"; +#endif +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4000[] = "WinTV PVR-350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4001[] = "WinTV PVR-250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3cf[] = "M179"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_494f[] = "ACCES I/O Products, Inc."; +static const char pci_device_494f_10e8[] = "LPCI-COM-8SM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +static const char pci_device_4c53_0000[] = "PLUSTEST device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3000[] = "PLUSTEST card (PC104+)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3001[] = "PLUSTEST card (PMC)"; +#endif +static const char pci_device_4c53_0001[] = "PLUSTEST-MM device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0001_4c53_3002[] = "PLUSTEST-MM card (PMC)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +static const char pci_device_5168_0301[] = "FlyDVB-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8110[] = "Savage 4 LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "Thinkpad T20/T22"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1179_0001[] = "86C584 SuperSavage/IXC Toshiba"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "VT8375 [ProSavage8 KM266/KL266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +static const char pci_device_544c_0350[] = "TL880-based HDTV/ATSC tuner"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +static const char pci_device_5654_3132[] = "OpenSwitch12"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5851[] = "Exacq Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin fuer Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +static const char pci_device_6666_0004[] = "PCCOM2"; +static const char pci_device_6666_0101[] = "PCI 8255/8254 I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7063[] = "pcHDTV"; +static const char pci_device_7063_2000[] = "HD-2000"; +static const char pci_device_7063_3000[] = "HD-3000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_807d[] = "Asustek Computer, Inc."; +#endif +static const char pci_vendor_8086[] = "Intel Corporation"; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145 Fast Ethernet"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0309[] = "80303 I/O Processor PCI-to-PCI Bridge"; +static const char pci_device_8086_030d[] = "80312 I/O Companion Chip PCI-to-PCI Bridge"; +static const char pci_device_8086_0326[] = "6700/6702PXH I/OxAPIC Interrupt Controller A"; +static const char pci_device_8086_0327[] = "6700PXH I/OxAPIC Interrupt Controller B"; +static const char pci_device_8086_0329[] = "6700PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_032a[] = "6700PXH PCI Express-to-PCI Bridge B"; +static const char pci_device_8086_032c[] = "6702PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_0330[] = "80332 [Dobson] I/O processor (A-Segment Bridge)"; +static const char pci_device_8086_0331[] = "80332 [Dobson] I/O processor (A-Segment IOAPIC)"; +static const char pci_device_8086_0332[] = "80332 [Dobson] I/O processor (B-Segment Bridge)"; +static const char pci_device_8086_0333[] = "80332 [Dobson] I/O processor (B-Segment IOAPIC)"; +static const char pci_device_8086_0334[] = "80332 [Dobson] I/O processor (ATU)"; +static const char pci_device_8086_0335[] = "80331 [Lindsay] I/O processor (PCI-X Bridge)"; +static const char pci_device_8086_0336[] = "80331 [Lindsay] I/O processor (ATU)"; +static const char pci_device_8086_0340[] = "41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge)"; +static const char pci_device_8086_0341[] = "41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge)"; +static const char pci_device_8086_0370[] = "80333 Segment-A PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0371[] = "80333 A-Bus IOAPIC"; +static const char pci_device_8086_0372[] = "80333 Segment-B PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0373[] = "80333 B-Bus IOAPIC"; +static const char pci_device_8086_0374[] = "80333 Address Translation Unit"; +static const char pci_device_8086_0482[] = "82375EB/SB PCI to EISA Bridge"; +static const char pci_device_8086_0483[] = "82424TX/ZX [Saturn] CPU to PCI bridge"; +static const char pci_device_8086_0484[] = "82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge"; +static const char pci_device_8086_0486[] = "82425EX/ZX [Aries] PCIset with ISA bridge"; +static const char pci_device_8086_04a3[] = "82434LX/NX [Mercury/Neptune] Processor to PCI bridge"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0500[] = "E8870 Processor bus control"; +static const char pci_device_8086_0501[] = "E8870 Memory controller"; +static const char pci_device_8086_0502[] = "E8870 Scalability Port 0"; +static const char pci_device_8086_0503[] = "E8870 Scalability Port 1"; +static const char pci_device_8086_0510[] = "E8870IO Hub Interface Port 0 registers (8-bit compatibility port)"; +static const char pci_device_8086_0511[] = "E8870IO Hub Interface Port 1 registers"; +static const char pci_device_8086_0512[] = "E8870IO Hub Interface Port 2 registers"; +static const char pci_device_8086_0513[] = "E8870IO Hub Interface Port 3 registers"; +static const char pci_device_8086_0514[] = "E8870IO Hub Interface Port 4 registers"; +static const char pci_device_8086_0515[] = "E8870IO General SIOH registers"; +static const char pci_device_8086_0516[] = "E8870IO RAS registers"; +static const char pci_device_8086_0530[] = "E8870SP Scalability Port 0 registers"; +static const char pci_device_8086_0531[] = "E8870SP Scalability Port 1 registers"; +static const char pci_device_8086_0532[] = "E8870SP Scalability Port 2 registers"; +static const char pci_device_8086_0533[] = "E8870SP Scalability Port 3 registers"; +static const char pci_device_8086_0534[] = "E8870SP Scalability Port 4 registers"; +static const char pci_device_8086_0535[] = "E8870SP Scalability Port 5 registers"; +static const char pci_device_8086_0536[] = "E8870SP Interleave registers 0 and 1"; +static const char pci_device_8086_0537[] = "E8870SP Interleave registers 2 and 3"; +static const char pci_device_8086_0600[] = "RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01af[] = "SRCZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01c1[] = "ICP Vortex GDT8546RZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01f7[] = "SCRU32"; +#endif +static const char pci_device_8086_061f[] = "80303 I/O Processor"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1002[] = "PRO/1000 F Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1028_011c[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_3108[] = "PRO/1000 XT Network Connection"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100a[] = "82540EM Gigabit Ethernet Controller"; +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1028_0123[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1079_891f[] = "82544GC Based Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_8086_110d[] = "82544GC Based Network Connection"; +#endif +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0265[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0267[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_026a[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1024_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_002e[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0151[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_107b_8920[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_028e[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1000[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_0e11_00db[] = "NC7170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1014_027c[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_18fb_7872[] = "RESlink-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1fc1_0026[] = "Niagara 2260 Bypass Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1012[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_101a[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1003[] = "PRO/1000 MF Server Adapter (LX)"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_0e11_00dc[] = "NC6170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1013[] = "82541EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_0013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1013[] = "IBM ThinkCentre Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1113[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1014[] = "82541ER Gigabit Ethernet Controller"; +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_1016[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1014_052c[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_8086_1016[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1017[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1017_8086_1017[] = "PR0/1000 MT Desktop Connection"; +#endif +static const char pci_device_8086_1018[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1018_8086_1018[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1019[] = "82547EI Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_1019[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_e000[] = "Intel Gigabit Ethernet (Kenai II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_1019[] = "PRO/1000 CT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_301f[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_101a[] = "82547EI Gigabit Ethernet Controller (Mobile)"; +static const char pci_device_8086_101d[] = "82546EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101d_8086_1000[] = "PRO/1000 MT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_101e[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1014_0549[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_8086_101e[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1026[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1000[] = "PRO/1000 MT Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1002[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1026[] = "PRO/1000 MT Server Connection"; +#endif +static const char pci_device_8086_1027[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_103c_3103[] = "NC310F PCI-X Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1001[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1002[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1003[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1027[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1028[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1028_8086_1028[] = "PRO/1000 MB Server Adapter"; +#endif +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_813c_104d[] = "Vaio PCG-GRV616G"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1038_0e11_0098[] = "Evo N600c"; +#endif +static const char pci_device_8086_1039[] = "82801DB PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1039_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_103a[] = "82801DB PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801DB PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801DB PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801DB PRO/100 VE (MOB) Ethernet Controller"; +static const char pci_device_8086_103e[] = "82801DB PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1043[] = "PRO/Wireless LAN 2100 3B Mini PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_8086_2527[] = "MIM2000/Centrino"; +#endif +static const char pci_device_8086_1048[] = "PRO/10GbE LR Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a01f[] = "PRO/10GbE LR Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a11f[] = "PRO/10GbE LR Server Adapter"; +#endif +static const char pci_device_8086_1050[] = "82562EZ 10/100 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_728c[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_758c[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3020[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_302f[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_1051[] = "82801EB/ER (ICH5/ICH5R) integrated LAN Controller"; +static const char pci_device_8086_1052[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1053[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_105e[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_105f[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1060[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1064[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_1065[] = "82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1066[] = "82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1067[] = "82562 EM/EX/GX - PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1068[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_1069[] = "82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_106a[] = "82562G - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_106b[] = "82562G - PRO/100 VE Ethernet Controller Mobile"; +static const char pci_device_8086_1075[] = "82547GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_0075[] = "PRO/1000 CT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_1075[] = "PRO/1000 CT Network Connection"; +#endif +static const char pci_device_8086_1076[] = "82541GI/PI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_0076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1176[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1276[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1077[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_0077[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_1077[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1078[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1078_8086_1078[] = "PRO/1000 MT Network Connection"; +#endif +static const char pci_device_8086_1079[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12a6[] = "HP Dual Port 1000Base-T [A9900A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12cf[] = "HP Core Dual Port 1000Base-T [AB352A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1fc1_0027[] = "Niagara 2261 Failover NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_0079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1179[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_117a[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_103c_12a8[] = "HP Dual Port 1000base-SX [A9899A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_107a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_127a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107b[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_007b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_107b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +static const char pci_device_8086_107c[] = "82541PI Gigabit Ethernet Controller"; +static const char pci_device_8086_107d[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107e[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107f[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_1080[] = "FA82537EP 56K V.92 Data/Fax Modem PCI"; +static const char pci_device_8086_1081[] = "Enterprise Southbridge LAN Copper"; +static const char pci_device_8086_1082[] = "Enterprise Southbridge LAN fiber"; +static const char pci_device_8086_1083[] = "Enterprise Southbridge LAN SERDES"; +static const char pci_device_8086_1084[] = "Enterprise Southbridge IDE Redirection"; +static const char pci_device_8086_1085[] = "Enterprise Southbridge Serial Port Redirection"; +static const char pci_device_8086_1086[] = "Enterprise Southbridge IPMI/KCS0"; +static const char pci_device_8086_1087[] = "Enterprise Southbridge UHCI Redirection"; +static const char pci_device_8086_1089[] = "Enterprise Southbridge BT"; +static const char pci_device_8086_108a[] = "82546EB Gigabit Ethernet Controller"; +static const char pci_device_8086_108b[] = "82573V Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108c[] = "82573E Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_1096[] = "Enterprise Southbridge DPT LAN Copper"; +static const char pci_device_8086_1097[] = "Enterprise Southbridge DPT LAN fiber"; +static const char pci_device_8086_1098[] = "Enterprise Southbridge DPT LAN SERDES"; +static const char pci_device_8086_1099[] = "82546GB Quad Port Server Adapter"; +static const char pci_device_8086_109a[] = "82573L Gigabit Ethernet Controller"; +static const char pci_device_8086_1107[] = "PRO/1000 MF Server Adapter (LX)"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4532[] = "D815EEA2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "Intel IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "8255xER/82551IT Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1070[] = "PC6 mainboard"; +#endif +static const char pci_device_8086_1221[] = "82092AA PCI to PCMCIA Bridge"; +static const char pci_device_8086_1222[] = "82092AA IDE Controller"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2500/2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_108e_10cf[] = "EtherExpress PRO/100(B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_110a_008b[] = "82551QM Fast Ethernet Multifuction PCI/CardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_10e0[] = "PSL09 PrPMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3411[] = "SDS2 Mainboard"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB PIIX IDE Interface"; +static const char pci_device_8086_123b[] = "82380PB PCI to PCI Docking Bridge"; +static const char pci_device_8086_123c[] = "82380AB (MISA) Mobile PCI-to-ISA Bridge"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123e[] = "82466GX (IHPC) Integrated Hot-Plug Controller"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "82752 (752) AGP Graphics Accelerator"; +static const char pci_device_8086_124b[] = "82380FB (MPCI2) Mobile Docking Controller"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_4c53_1090[] = "Cx9/Vx9 mainboard"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, HP NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "HP NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1010[] = "CG1-RADIO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1020[] = "CU2-QUARTET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1040[] = "CU1-CHORUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_3100[] = "CX1-BAND"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1a30_1028_010e[] = "Optiplex GX240"; +#endif +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_1a38[] = "Server DMA Controller"; +static const char pci_device_8086_1a48[] = "PRO/10GbE SR Server Adapter"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_110a_0051[] = "Activy 2xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1734_1025[] = "Activy 3xx"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_8086_4532[] = "D815EEA2 mainboard"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2446[] = "82801BA/BAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801 Mobile PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0265[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0267[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_026a[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1179_ff01[] = "PRO/100 VE Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801 PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244e_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA LPC Interface Controller"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1013_5959[] = "Crystal WMD Audio Codec"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_101f_1025[] = "Acer 620 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1179_0001[] = "Toshiba Satellite 1110 Z15 internal Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_248b[] = "82801CA Ultra ATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c1[] = "82801DBL (ICH4-L) IDE Controller"; +static const char pci_device_8086_24c2[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1509_2990[] = "Averatec 5110H laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c3[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24c4[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c5[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_0e11_00b8[] = "Analog Devices Inc. codec [SoundMAX]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1458_a002[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24c6[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_8086_24c7[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24ca[] = "82801DBM (ICH4-M) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24cb[] = "82801DB (ICH4) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24cc[] = "82801DBM (ICH4-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cc_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24cd[] = "82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1509_1968[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24d0[] = "82801EB/ER (ICH5/ICH5R) LPC Interface Bridge"; +static const char pci_device_8086_24d1[] = "82801EB (ICH5) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1043_80a6[] = "P4P800 SE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1458_24d1[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d2[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1458_24d2[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d3[] = "82801EB/ER (ICH5/ICH5R) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1043_80a6[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d4[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d5[] = "82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_12bc[] = "Analog Devices codec [SoundMAX Integrated Digital Audio]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_80f3[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_810f[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1458_a002[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_a000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e001[] = "Desktop Board D865GBF"; +#endif +static const char pci_device_8086_24d6[] = "82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller"; +static const char pci_device_8086_24d7[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24db[] = "82801EB/ER (ICH5/ICH5R) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7580[] = "MSI 875P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_24db[] = "P4C800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24dc[] = "82801EB (ICH5) LPC Interface Bridge"; +static const char pci_device_8086_24dd[] = "82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1458_5006[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24de[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24df[] = "82801ER (ICH5R) SATA Controller"; +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "E7500 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "E7500/E7501 Host RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2543[] = "E7500/E7501 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2544[] = "E7500/E7501 Hub Interface B RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2544_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_2545[] = "E7500/E7501 Hub Interface C PCI-to-PCI Bridge"; +static const char pci_device_8086_2546[] = "E7500/E7501 Hub Interface C RASUM Controller"; +static const char pci_device_8086_2547[] = "E7500/E7501 Hub Interface D PCI-to-PCI Bridge"; +static const char pci_device_8086_2548[] = "E7500/E7501 Hub Interface D RASUM Controller"; +static const char pci_device_8086_254c[] = "E7501 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2550[] = "E7505 Memory Controller Hub"; +static const char pci_device_8086_2551[] = "E7505/E7205 Series RAS Controller"; +static const char pci_device_8086_2552[] = "E7505/E7205 PCI-to-AGP Bridge"; +static const char pci_device_8086_2553[] = "E7505 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2554[] = "E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller"; +static const char pci_device_8086_255d[] = "E7205 Memory Controller Hub"; +static const char pci_device_8086_2560[] = "82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1458_2560[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2570[] = "82865G/PE/P DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1043_80f2[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1458_2570[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +static const char pci_device_8086_2571[] = "82865G/PE/P PCI to AGP Controller"; +static const char pci_device_8086_2572[] = "82865G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1028_019d[] = "Dimension 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1043_80a5[] = "P5P800-MX Mainboard"; +#endif +static const char pci_device_8086_2573[] = "82865G/PE/P PCI to CSA Bridge"; +static const char pci_device_8086_2576[] = "82865G/PE/P Processor to I/O Memory Interface"; +static const char pci_device_8086_2578[] = "82875P/E7210 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1458_2578[] = "GA-8KNXP motherboard (875P)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1462_7580[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_15d9_4580[] = "P4SCE Motherboard"; +#endif +static const char pci_device_8086_2579[] = "82875P Processor to AGP Controller"; +static const char pci_device_8086_257b[] = "82875P/E7210 Processor to PCI to CSA Bridge"; +static const char pci_device_8086_257e[] = "82875P/E7210 Processor to I/O Memory Interface"; +static const char pci_device_8086_2580[] = "915G/P/GV/GL/PL/910GL Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1458_2580[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2581[] = "915G/P/GV/GL/PL/910GL PCI Express Root Port"; +static const char pci_device_8086_2582[] = "82915G/GV/910GL Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1028_1079[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1458_2582[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2584[] = "925X/XE Memory Controller Hub"; +static const char pci_device_8086_2585[] = "925X/XE PCI Express Root Port"; +static const char pci_device_8086_2588[] = "E7220/E7221 Memory Controller Hub"; +static const char pci_device_8086_2589[] = "E7220/E7221 PCI Express Root Port"; +static const char pci_device_8086_258a[] = "E7221 Integrated Graphics Controller"; +static const char pci_device_8086_2590[] = "Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_a304_81b7[] = "Vaio VGN-S3XP"; +#endif +static const char pci_device_8086_2591[] = "Mobile 915GM/PM Express PCI Express Root Port"; +static const char pci_device_8086_2592[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_25a1[] = "6300ESB LPC Interface Controller"; +static const char pci_device_8086_25a2[] = "6300ESB PATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a3[] = "6300ESB SATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a4[] = "6300ESB SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a6[] = "6300ESB AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_4c53_10b0[] = "CL9 mainboard"; +#endif +static const char pci_device_8086_25a7[] = "6300ESB AC'97 Modem Controller"; +static const char pci_device_8086_25a9[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25aa[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ab[] = "6300ESB Watchdog Timer"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ac[] = "6300ESB I/O Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ad[] = "6300ESB USB2 Enhanced Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ae[] = "6300ESB 64-bit PCI-X Bridge"; +static const char pci_device_8086_25b0[] = "6300ESB SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25c0[] = "Workstation Memory Controller Hub"; +static const char pci_device_8086_25d0[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25d4[] = "Server Memory Contoller Hub"; +static const char pci_device_8086_25d8[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25e2[] = "Server PCI Express x4 Port 2"; +static const char pci_device_8086_25e3[] = "Server PCI Express x4 Port 3"; +static const char pci_device_8086_25e4[] = "Server PCI Express x4 Port 4"; +static const char pci_device_8086_25e5[] = "Server PCI Express x4 Port 5"; +static const char pci_device_8086_25e6[] = "Server PCI Express x4 Port 6"; +static const char pci_device_8086_25e7[] = "Server PCI Express x4 Port 7"; +static const char pci_device_8086_25e8[] = "Server AMB Memory Mapped Registers"; +static const char pci_device_8086_25f0[] = "Server Error Reporting Registers"; +static const char pci_device_8086_25f1[] = "Reserved Registers"; +static const char pci_device_8086_25f3[] = "Reserved Registers"; +static const char pci_device_8086_25f5[] = "Server FBD Registers"; +static const char pci_device_8086_25f6[] = "Server FBD Registers"; +static const char pci_device_8086_25f7[] = "Server PCI Express x8 Port 2-3"; +static const char pci_device_8086_25f8[] = "Server PCI Express x8 Port 4-5"; +static const char pci_device_8086_25f9[] = "Server PCI Express x8 Port 6-7"; +static const char pci_device_8086_25fa[] = "Server PCI Express x16 Port 4-7"; +static const char pci_device_8086_2600[] = "E8500/E8501 Hub Interface 1.5"; +static const char pci_device_8086_2601[] = "E8500/E8501 PCI Express x4 Port D"; +static const char pci_device_8086_2602[] = "E8500/E8501 PCI Express x4 Port C0"; +static const char pci_device_8086_2603[] = "E8500/E8501 PCI Express x4 Port C1"; +static const char pci_device_8086_2604[] = "E8500/E8501 PCI Express x4 Port B0"; +static const char pci_device_8086_2605[] = "E8500/E8501 PCI Express x4 Port B1"; +static const char pci_device_8086_2606[] = "E8500/E8501 PCI Express x4 Port A0"; +static const char pci_device_8086_2607[] = "E8500/E8501 PCI Express x4 Port A1"; +static const char pci_device_8086_2608[] = "E8500/E8501 PCI Express x8 Port C"; +static const char pci_device_8086_2609[] = "E8500/E8501 PCI Express x8 Port B"; +static const char pci_device_8086_260a[] = "E8500/E8501 PCI Express x8 Port A"; +static const char pci_device_8086_260c[] = "E8500/E8501 IMI Registers"; +static const char pci_device_8086_2610[] = "E8500/E8501 Front Side Bus, Boot, and Interrupt Registers"; +static const char pci_device_8086_2611[] = "E8500/E8501 Address Mapping Registers"; +static const char pci_device_8086_2612[] = "E8500/E8501 RAS Registers"; +static const char pci_device_8086_2613[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2614[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2615[] = "E8500/E8501 Miscellaneous Registers"; +static const char pci_device_8086_2617[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2618[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2619[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261a[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261b[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261c[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261d[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261e[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2620[] = "E8500/E8501 eXternal Memory Bridge"; +static const char pci_device_8086_2621[] = "E8500/E8501 XMB Miscellaneous Registers"; +static const char pci_device_8086_2622[] = "E8500/E8501 XMB Memory Interleaving Registers"; +static const char pci_device_8086_2623[] = "E8500/E8501 XMB DDR Initialization and Calibration"; +static const char pci_device_8086_2624[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2625[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2626[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2627[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2640[] = "82801FB/FR (ICH6/ICH6R) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2641[] = "82801FBM (ICH6M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2641_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2642[] = "82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge"; +static const char pci_device_8086_2651[] = "82801FB/FW (ICH6/ICH6W) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_8086_4147[] = "D915GAG Motherboard"; +#endif +static const char pci_device_8086_2652[] = "82801FR/FRW (ICH6R/ICH6RW) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2652_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_8086_2653[] = "82801FBM (ICH6M) SATA Controller"; +static const char pci_device_8086_2658[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1458_2558[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2659[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1458_2659[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265b[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1458_5006[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2660[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2660_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2662[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2"; +static const char pci_device_8086_2664[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3"; +static const char pci_device_8086_2666[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4"; +static const char pci_device_8086_2668[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller"; +static const char pci_device_8086_266a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1458_266a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_266c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller"; +static const char pci_device_8086_266d[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_266e[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0182[] = "Latitude D610 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1458_a002[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1734_105a[] = "Scenic W620"; +#endif +static const char pci_device_8086_266f[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1458_266f[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2670[] = "Enterprise Southbridge LPC"; +static const char pci_device_8086_2680[] = "Enterprise Southbridge SATA cc=IDE"; +static const char pci_device_8086_2681[] = "Enterprise Southbridge SATA cc=AHCI"; +static const char pci_device_8086_2682[] = "Enterprise Southbridge SATA cc=RAID"; +static const char pci_device_8086_2683[] = "Enterprise Southbridge SATA cc=RAID"; +static const char pci_device_8086_2688[] = "Enterprise Southbridge UHCI USB #1"; +static const char pci_device_8086_2689[] = "Enterprise Southbridge UHCI USB #2"; +static const char pci_device_8086_268a[] = "Enterprise Southbridge UHCI USB #3"; +static const char pci_device_8086_268b[] = "Enterprise Southbridge UHCI USB #4"; +static const char pci_device_8086_268c[] = "Enterprise Southbridge EHCI USB"; +static const char pci_device_8086_2690[] = "Enterprise Southbridge PCI Express Root Port 1"; +static const char pci_device_8086_2692[] = "Enterprise Southbridge PCI Express Root Port 2"; +static const char pci_device_8086_2694[] = "Enterprise Southbridge PCI Express Root Port 3"; +static const char pci_device_8086_2696[] = "Enterprise Southbridge PCI Express Root Port 4"; +static const char pci_device_8086_2698[] = "Enterprise Southbridge AC '97 Audio"; +static const char pci_device_8086_2699[] = "Enterprise Southbridge AC '97 Modem"; +static const char pci_device_8086_269a[] = "Enterprise Southbridge High Definition Audio"; +static const char pci_device_8086_269b[] = "Enterprise Southbridge SMBus"; +static const char pci_device_8086_269e[] = "Enterprise Southbridge PATA"; +static const char pci_device_8086_2770[] = "945G/P Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2771[] = "945G/P PCI Express Graphics Port"; +static const char pci_device_8086_2772[] = "945G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2772_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2774[] = "955X Memory Controller Hub"; +static const char pci_device_8086_2775[] = "955X PCI Express Graphics Port"; +static const char pci_device_8086_2776[] = "945G Integrated Graphics Controller"; +static const char pci_device_8086_2778[] = "E7230 Memory Controller Hub"; +static const char pci_device_8086_2779[] = "E7230 PCI Express Root Port"; +static const char pci_device_8086_277a[] = "PCI Express Graphics Port"; +static const char pci_device_8086_277c[] = "Memory Controller Hub"; +static const char pci_device_8086_277d[] = "PCI Express Graphics Port"; +static const char pci_device_8086_2782[] = "82915G Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2792[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_27a0[] = "Mobile Memory Controller Hub"; +static const char pci_device_8086_27a1[] = "Mobile PCI Express Graphics Port"; +static const char pci_device_8086_27a2[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_27a6[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_27b0[] = "82801GH (ICH7DH) LPC Interface Bridge"; +static const char pci_device_8086_27b8[] = "82801GB/GR (ICH7 Family) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27b9[] = "82801GBM (ICH7-M) LPC Interface Bridge"; +static const char pci_device_8086_27bd[] = "82801GHM (ICH7-M DH) LPC Interface Bridge"; +static const char pci_device_8086_27c0[] = "82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c1[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=AHCI"; +static const char pci_device_8086_27c3[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=RAID"; +static const char pci_device_8086_27c4[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controllers cc=IDE"; +static const char pci_device_8086_27c5[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controllers cc=AHCI"; +static const char pci_device_8086_27c6[] = "82801GHM (ICH7-M DH) Serial ATA Storage Controllers cc=RAID"; +static const char pci_device_8086_27c8[] = "82801G (ICH7 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c9[] = "82801G (ICH7 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27ca[] = "82801G (ICH7 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cb[] = "82801G (ICH7 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cc[] = "82801G (ICH7 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27d0[] = "82801G (ICH7 Family) PCI Express Port 1"; +static const char pci_device_8086_27d2[] = "82801G (ICH7 Family) PCI Express Port 2"; +static const char pci_device_8086_27d4[] = "82801G (ICH7 Family) PCI Express Port 3"; +static const char pci_device_8086_27d6[] = "82801G (ICH7 Family) PCI Express Port 4"; +static const char pci_device_8086_27d8[] = "82801G (ICH7 Family) High Definition Audio Controller"; +static const char pci_device_8086_27da[] = "82801G (ICH7 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dc[] = "82801G (ICH7 Family) LAN Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27dc_8086_308d[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dd[] = "82801G (ICH7 Family) AC'97 Modem Controller"; +static const char pci_device_8086_27de[] = "82801G (ICH7 Family) AC'97 Audio Controller"; +static const char pci_device_8086_27df[] = "82801G (ICH7 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27e0[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 5"; +static const char pci_device_8086_27e2[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 6"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3200[] = "GD31244 PCI-X SATA HBA"; +static const char pci_device_8086_3340[] = "82855PM Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_0890[] = "nc6000 laptop"; +#endif +static const char pci_device_8086_3341[] = "82855PM Processor to AGP Controller"; +static const char pci_device_8086_3500[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3501[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3504[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_3505[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_350c[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_350d[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_3510[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3511[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3514[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3515[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3518[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3519[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3581[] = "82852/82855 GM/GME/PM/GMV Processor to AGP Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3581_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_3582[] = "82852/855GM Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3584[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3585[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3590[] = "E7520 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1734_103e[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3591[] = "E7525/E7520 Error Reporting Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3592[] = "E7320 Memory Controller Hub"; +static const char pci_device_8086_3593[] = "E7320 Error Reporting Registers"; +static const char pci_device_8086_3594[] = "E7520 DMA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3594_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3595[] = "E7525/E7520/E7320 PCI Express Port A"; +static const char pci_device_8086_3596[] = "E7525/E7520/E7320 PCI Express Port A1"; +static const char pci_device_8086_3597[] = "E7525/E7520 PCI Express Port B"; +static const char pci_device_8086_3598[] = "E7520 PCI Express Port B1"; +static const char pci_device_8086_3599[] = "E7520 PCI Express Port C"; +static const char pci_device_8086_359a[] = "E7520 PCI Express Port C1"; +static const char pci_device_8086_359b[] = "E7525/E7520/E7320 Extended Configuration Registers"; +static const char pci_device_8086_359e[] = "E7525 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_359e_1028_0169[] = "Precision 470"; +#endif +static const char pci_device_8086_4220[] = "PRO/Wireless 2200BG"; +static const char pci_device_8086_4223[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_4224[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7050[] = "Intercast Video Capture Card"; +static const char pci_device_8086_7051[] = "PB 642365-003 (Business Video Conferencing Card)"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7110_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7111_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7112_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7113_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1060[] = "PC7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_8086_4341[] = "Cayman (CA810) Mainboard"; +#endif +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700/E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_15ad_1976[] = "virtualHW v3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_1033_0000[] = "Versa Note Vxi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_1033_80cc[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a2_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "82740 (i740) AGP Graphics Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_8500[] = "IXP4XX Intel Network Processor (IXP420/421/422/425/IXC1100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0ded[] = "mGuard-PCI AV#2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0dee[] = "mGuard-PCI AV#1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0def[] = "mGuard-PCI AV#0"; +#endif +static const char pci_device_8086_9000[] = "IXP2000 Family Network Processor"; +static const char pci_device_8086_9001[] = "IXP2400 Network Processor"; +static const char pci_device_8086_9004[] = "IXP2800 Network Processor"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12d9_000a[] = "PCI VoIP Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8401[] = "TRENDware International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8912[] = "TRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8c4a[] = "Winbond"; +static const char pci_device_8c4a_1980[] = "W89C940 misprogrammed [ne2k]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_0078[] = "AHA-2940U_CN"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7710[] = "ANA-7711F Network Accelerator Card (NAC) - Optical"; +static const char pci_device_9004_7711[] = "ANA-7711C Network Accelerator Card (NAC) - Copper"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8178_9004_7881[] = "AHA-2940UW SCSI Host Adapter"; +#endif +static const char pci_device_9004_8278[] = "AHA-3940U/UW/UWD / AIC-7882U"; +static const char pci_device_9004_8378[] = "AHA-3940U/UW / AIC-7883U"; +static const char pci_device_9004_8478[] = "AHA-2944UW / AIC-7884U"; +static const char pci_device_9004_8578[] = "AHA-3944U/UWD / AIC-7885"; +static const char pci_device_9004_8678[] = "AHA-4944UW / AIC-7886"; +static const char pci_device_9004_8778[] = "AHA-2940UW Pro / AIC-788x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8778_9004_7887[] = "2940UW Pro Ultra-Wide SCSI Controller"; +#endif +static const char pci_device_9004_8878[] = "AHA-2930UW / AIC-7888"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8878_9004_7888[] = "AHA-2930UW SCSI Controller"; +#endif +static const char pci_device_9004_8b78[] = "ABA-1030"; +static const char pci_device_9004_ec78[] = "AHA-4944W/UW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9005[] = "Adaptec"; +static const char pci_device_9005_0010[] = "AHA-2940U2/U2W"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_2180[] = "AHA-2940U2 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_8100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a180[] = "AHA-2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_e100[] = "AHA-2950U2B SCSI Controller"; +#endif +static const char pci_device_9005_0011[] = "AHA-2930U2"; +static const char pci_device_9005_0013[] = "78902"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_0003[] = "AAA-131U2 Array1000 1 Channel RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_000f[] = "AIC7890_ARO"; +#endif +static const char pci_device_9005_001f[] = "AHA-2940U2/U2W / 7890/7891"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_9005_0020[] = "AIC-7890"; +static const char pci_device_9005_002f[] = "AIC-7890"; +static const char pci_device_9005_0030[] = "AIC-7890"; +static const char pci_device_9005_003f[] = "AIC-7890"; +static const char pci_device_9005_0050[] = "AHA-3940U2x/395U2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_f500[] = "AHA-3950U2B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_ffff[] = "AHA-3950U2B"; +#endif +static const char pci_device_9005_0051[] = "AHA-3950U2D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0051_9005_b500[] = "AHA-3950U2D"; +#endif +static const char pci_device_9005_0053[] = "AIC-7896 SCSI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0053_9005_ffff[] = "AIC-7896 SCSI Controller mainboard implementation"; +#endif +static const char pci_device_9005_005f[] = "AIC-7896U2/7897U2"; +static const char pci_device_9005_0080[] = "AIC-7892A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_0e11_e2a0[] = "Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_6220[] = "AHA-29160C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_62a0[] = "29160N Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e220[] = "29160LP Low Profile Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e2a0[] = "29160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0081[] = "AIC-7892B U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0081_9005_62a1[] = "19160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0083[] = "AIC-7892D U160/m"; +static const char pci_device_9005_008f[] = "AIC-7892P U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +static const char pci_device_9005_0092[] = "Adaptec VIDEOH! AVC-2010"; +static const char pci_device_9005_0093[] = "Adaptec VIDEOH! AVC-2410"; +static const char pci_device_9005_00c0[] = "AHA-3960D / AIC-7899A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_0e11_f620[] = "Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_9005_f620[] = "AHA-3960D U160/m"; +#endif +static const char pci_device_9005_00c1[] = "AIC-7899B U160/m"; +static const char pci_device_9005_00c3[] = "AIC-7899D U160/m"; +static const char pci_device_9005_00c5[] = "RAID subsystem HBA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c5_1028_00c5[] = "PowerEdge 2400,2500,2550,4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_10f1_2462[] = "Thunder K7 S2462"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_0241[] = "Serial ATA II RAID 1420SA"; +static const char pci_device_9005_0250[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_0279[] = "ServeRAID-xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_028c[] = "ServeRAID-xx"; +#endif +static const char pci_device_9005_0279[] = "ServeRAID 6M"; +static const char pci_device_9005_0283[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0283_9005_0283[] = "Catapult"; +#endif +static const char pci_device_9005_0284[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0284_9005_0284[] = "Tomcat"; +#endif +static const char pci_device_9005_0285[] = "AAC-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_0e11_0295[] = "SATA 6Ch (Bearcat)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1014_02f2[] = "ServeRAID 8i"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0287[] = "PowerEdge Expandable RAID Controller 320/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0291[] = "CERC SATA RAID 2 PCI SATA 6ch (DellCorsair)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_103c_3227[] = "AAR-2610SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0286[] = "Legend S220 (Legend Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0287[] = "Legend S230 (Legend Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0285[] = "2200S (Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0286[] = "2120S (Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0287[] = "2200S (Vulcan-2m)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0288[] = "3230S (Harrier)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0289[] = "3240S (Tornado)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028a[] = "ASR-2020S PCI-X ZCR (Skyhawk)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028b[] = "ASR-2025S (Terminator)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028e[] = "ASR-2020SA (Skyhawk)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028f[] = "ASR-2025SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0290[] = "AAR-2410SA PCI SATA 4ch (Jaguar II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0292[] = "AAR-2810SA PCI SATA 8ch (Corsair-8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0293[] = "AAR-21610SA PCI SATA 16ch (Corsair-16)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0294[] = "ESD SO-DIMM PCI-X SATA ZCR (Prowler)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0296[] = "ASR-2240S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0297[] = "ASR-4005SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0298[] = "ASR-4000SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0299[] = "ASR-4800SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_029a[] = "ASR-4805SAS"; +#endif +static const char pci_device_9005_0286[] = "AAC-RAID (Rocket)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9540[] = "ServeRAID 8k/8k-l4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9580[] = "ServeRAID 8k/8k-l8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028c[] = "ASR-2230S + ASR-2230SLP PCI-X (Lancer)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028d[] = "ASR-2130S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029b[] = "ASR-2820SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029c[] = "ASR-2620SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029d[] = "ASR-2420SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029e[] = "ICP ICP9024R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029f[] = "ICP ICP9014R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a0[] = "ICP ICP9047MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a1[] = "ICP ICP9087MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a2[] = "ASR-4810SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a3[] = "ICP ICP5085AU"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a4[] = "ICP ICP5085LI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a5[] = "ICP ICP5085BR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a6[] = "ICP9067MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_0800[] = "Callisto"; +#endif +static const char pci_device_9005_0500[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/572D)"; +#endif +static const char pci_device_9005_0503[] = "Scamp chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02bf[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02d5[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571F)"; +#endif +static const char pci_device_9005_0910[] = "AUA-3100B"; +static const char pci_device_9005_091e[] = "AUA-3100B"; +static const char pci_device_9005_8000[] = "ASC-29320A U320"; +static const char pci_device_9005_800f[] = "AIC-7901 U320"; +static const char pci_device_9005_8010[] = "ASC-39320 U320"; +static const char pci_device_9005_8011[] = "ASC-39320D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_0e11_00ac[] = "ASC-39320D U320"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_9005_0041[] = "ASC-39320D U320"; +#endif +static const char pci_device_9005_8012[] = "ASC-29320 U320"; +static const char pci_device_9005_8013[] = "ASC-29320B U320"; +static const char pci_device_9005_8014[] = "ASC-29320LP U320"; +static const char pci_device_9005_8015[] = "ASC-39320B U320"; +static const char pci_device_9005_8016[] = "ASC-39320A U320"; +static const char pci_device_9005_8017[] = "ASC-29320ALP U320"; +static const char pci_device_9005_801c[] = "ASC-39320D U320"; +static const char pci_device_9005_801d[] = "AIC-7902B U320"; +static const char pci_device_9005_801e[] = "AIC-7901A U320"; +static const char pci_device_9005_801f[] = "AIC-7902 U320"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_801f_1734_1011[] = "Primergy RX300"; +#endif +static const char pci_device_9005_8080[] = "ASC-29320A U320 w/HostRAID"; +static const char pci_device_9005_808f[] = "AIC-7901 U320 w/HostRAID"; +static const char pci_device_9005_8090[] = "ASC-39320 U320 w/HostRAID"; +static const char pci_device_9005_8091[] = "ASC-39320D U320 w/HostRAID"; +static const char pci_device_9005_8092[] = "ASC-29320 U320 w/HostRAID"; +static const char pci_device_9005_8093[] = "ASC-29320B U320 w/HostRAID"; +static const char pci_device_9005_8094[] = "ASC-29320LP U320 w/HostRAID"; +static const char pci_device_9005_8095[] = "ASC-39320(B) U320 w/HostRAID"; +static const char pci_device_9005_8096[] = "ASC-39320A U320 w/HostRAID"; +static const char pci_device_9005_8097[] = "ASC-29320ALP U320 w/HostRAID"; +static const char pci_device_9005_809c[] = "ASC-39320D(B) U320 w/HostRAID"; +static const char pci_device_9005_809d[] = "AIC-7902(B) U320 w/HostRAID"; +static const char pci_device_9005_809e[] = "AIC-7901A U320 w/HostRAID"; +static const char pci_device_9005_809f[] = "AIC-7902 U320 w/HostRAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_907f[] = "Atronics"; +static const char pci_device_907f_2015[] = "IDE-2015PL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_919a[] = "Gigapixel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9412[] = "Holtek"; +static const char pci_device_9412_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9699[] = "Omni Media Technology Inc"; +static const char pci_device_9699_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9710[] = "NetMos Technology"; +static const char pci_device_9710_7780[] = "USB IRDA-port"; +static const char pci_device_9710_9805[] = "PCI 1 port parallel adapter"; +static const char pci_device_9710_9815[] = "PCI 9815 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9815_1000_0020[] = "2P0S (2 port parallel adaptor)"; +#endif +static const char pci_device_9710_9835[] = "PCI 9835 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0002[] = "2S (16C550 UART)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0012[] = "1P2S"; +#endif +static const char pci_device_9710_9845[] = "PCI 9845 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0004[] = "0P4S (4 port 16550A serial card)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0006[] = "0P6S (6 port 16550a serial card)"; +#endif +static const char pci_device_9710_9855[] = "PCI 9855 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9855_1000_0014[] = "1P4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9902[] = "Stargen Inc."; +static const char pci_device_9902_0001[] = "SG2010 PCI over Starfabric Bridge"; +static const char pci_device_9902_0002[] = "SG2010 PCI to Starfabric Gateway"; +static const char pci_device_9902_0003[] = "SG1010 Starfabric Switch and PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0a0[] = "AOPEN Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0f1[] = "UNISYS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a200[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a259[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a25b[] = "Hewlett Packard GmbH PL24-MKT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a304[] = "Sony"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a727[] = "3Com Corporation"; +static const char pci_device_a727_0013[] = "3CRPAG175 Wireless PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aa42[] = "Scitex Digital Video"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac1e[] = "Digital Receiver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac3d[] = "Actuality Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aecb[] = "Adrienne Electronics Corporation"; +static const char pci_device_aecb_6250[] = "VITC/LTC Timecode Reader card [PCI-VLTC/RDR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_affe[] = "Sirrix AG security technologies"; +static const char pci_device_affe_dead[] = "Sirrix.PCI4S0 4-port ISDN S0 interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_b1b3[] = "Shiva Europe Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_bd11[] = "Pinnacle Systems, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c001[] = "TSI Telsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0a9[] = "Micron/Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0de[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0fe[] = "Motion Engineering, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ca50[] = "Varian Australia Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cafe[] = "Chrysalis-ITS"; +static const char pci_device_cafe_0003[] = "Luna K3 Hardware Security Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cccc[] = "Catapult Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cddd[] = "Tyzx, Inc."; +static const char pci_device_cddd_0101[] = "DeepSea 1 High Speed Stereo Vision Frame Grabber"; +static const char pci_device_cddd_0200[] = "DeepSea 2 High Speed Stereo Vision Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d161[] = "Digium, Inc."; +static const char pci_device_d161_0205[] = "Wildcard TE205P"; +static const char pci_device_d161_0210[] = "Wildcard TE210P"; +static const char pci_device_d161_0405[] = "Wildcard TE405P (2nd Gen)"; +static const char pci_device_d161_0410[] = "Wildcard TE410P (2nd Gen)"; +static const char pci_device_d161_2400[] = "Wildcard TDM2400P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d4d4[] = "Dy4 Systems Inc"; +static const char pci_device_d4d4_0601[] = "PCI Mezzanine Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d531[] = "I+ME ACTIA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d84d[] = "Exsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_dead[] = "Indigita Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_deaf[] = "Middle Digital Inc."; +static const char pci_device_deaf_9050[] = "PC Weasel Virtual VGA"; +static const char pci_device_deaf_9051[] = "PC Weasel Serial Port"; +static const char pci_device_deaf_9052[] = "PC Weasel Watchdog Timer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e000[] = "Winbond"; +static const char pci_device_e000_e000[] = "W89C940"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e159[] = "Tiger Jet Network Inc."; +static const char pci_device_e159_0001[] = "Tiger3XX Modem/ISDN interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0001[] = "128k ISDN-S/T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0003[] = "128k ISDN-U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_00a7_0001[] = "TELES.S0/PCI 2.x ISDN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_6159_0001[] = "Digium Wildcard T100P T1/PRI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_79fe_0001[] = "Digium Wildcard TE110P T1/E1 Interface"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_8086_0003[] = "Digium X100P/X101P analogue PSTN FXO interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_b1b9_0001[] = "Digium Wildcard TDM400P REV I 4-port POTS interface"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_b1b9_0003[] = "Digium Wildcard TDM400P REV I 4-port POTS interface"; +#endif +static const char pci_device_e159_0002[] = "Tiger100APC ISDN chipset"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e4bf[] = "EKF Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e55e[] = "Essence Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea01[] = "Eagle Technology"; +static const char pci_device_ea01_000a[] = "PCI-773 Temperature Card"; +static const char pci_device_ea01_0032[] = "PCI-730 & PC104P-30 Card"; +static const char pci_device_ea01_003e[] = "PCI-762 Opto-Isolator Card"; +static const char pci_device_ea01_0041[] = "PCI-763 Reed Relay Card"; +static const char pci_device_ea01_0043[] = "PCI-769 Opto-Isolator Reed Relay Combo Card"; +static const char pci_device_ea01_0046[] = "PCI-766 Analog Output Card"; +static const char pci_device_ea01_0052[] = "PCI-703 Analog I/O Card"; +static const char pci_device_ea01_0800[] = "PCI-800 Digital I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea60[] = "RME"; +static const char pci_device_ea60_9896[] = "Digi32"; +static const char pci_device_ea60_9897[] = "Digi32 Pro"; +static const char pci_device_ea60_9898[] = "Digi32/8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eabb[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eace[] = "Endace Measurement Systems, Ltd"; +static const char pci_device_eace_3100[] = "DAG 3.10 OC-3/OC-12"; +static const char pci_device_eace_3200[] = "DAG 3.2x OC-3/OC-12"; +static const char pci_device_eace_320e[] = "DAG 3.2E Fast Ethernet"; +static const char pci_device_eace_340e[] = "DAG 3.4E Fast Ethernet"; +static const char pci_device_eace_341e[] = "DAG 3.41E Fast Ethernet"; +static const char pci_device_eace_3500[] = "DAG 3.5 OC-3/OC-12"; +static const char pci_device_eace_351c[] = "DAG 3.5ECM Fast Ethernet"; +static const char pci_device_eace_4100[] = "DAG 4.10 OC-48"; +static const char pci_device_eace_4110[] = "DAG 4.11 OC-48"; +static const char pci_device_eace_4220[] = "DAG 4.2 OC-48"; +static const char pci_device_eace_422e[] = "DAG 4.2E Dual Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ec80[] = "Belkin Corporation"; +static const char pci_device_ec80_ec00[] = "F5D6000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ecc0[] = "Echo Digital Audio Corporation"; +#endif +static const char pci_vendor_edd8[] = "ARK Logic Inc"; +static const char pci_device_edd8_a091[] = "1000PV [Stingray]"; +static const char pci_device_edd8_a099[] = "2000PV [Stingray]"; +static const char pci_device_edd8_a0a1[] = "2000MT"; +static const char pci_device_edd8_a0a9[] = "2000MI"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_f1d0[] = "AJA Video"; +static const char pci_device_f1d0_c0fe[] = "Xena HS/HD-R"; +static const char pci_device_f1d0_c0ff[] = "Kona/Xena 2"; +static const char pci_device_f1d0_cafe[] = "Kona SD"; +static const char pci_device_f1d0_cfee[] = "Xena LS/SD-22-DA/SD-DA"; +static const char pci_device_f1d0_dcaf[] = "Kona HD"; +static const char pci_device_f1d0_dfee[] = "Xena HD-DA"; +static const char pci_device_f1d0_efac[] = "Xena SD-MM/SD-22-MM"; +static const char pci_device_f1d0_facd[] = "Xena HD-MM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fa57[] = "Interagon AS"; +static const char pci_device_fa57_0001[] = "PMC [Pattern Matching Chip]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_febd[] = "Ultraview Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_feda[] = "Broadcom Inc"; +static const char pci_device_feda_a0fa[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_feda_a10e[] = "BCM4230 iLine10 HomePNA 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fede[] = "Fedetec Inc."; +static const char pci_device_fede_0003[] = "TABIC PCI v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffd[] = "XenSource, Inc."; +static const char pci_device_fffd_0101[] = "PCI Event Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffe[] = "VMWare Inc"; +static const char pci_device_fffe_0405[] = "Virtual SVGA 4.0"; +static const char pci_device_fffe_0710[] = "Virtual SVGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ffff[] = "Illegal Vendor ID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409a = + {0x0e11, 0x409a, pci_subsys_0e11_0046_0e11_409a, 0}; +#undef pci_ss_info_0e11_409a +#define pci_ss_info_0e11_409a pci_ss_info_0e11_0046_0e11_409a +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409b = + {0x0e11, 0x409b, pci_subsys_0e11_0046_0e11_409b, 0}; +#undef pci_ss_info_0e11_409b +#define pci_ss_info_0e11_409b pci_ss_info_0e11_0046_0e11_409b +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409c = + {0x0e11, 0x409c, pci_subsys_0e11_0046_0e11_409c, 0}; +#undef pci_ss_info_0e11_409c +#define pci_ss_info_0e11_409c pci_ss_info_0e11_0046_0e11_409c +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409d = + {0x0e11, 0x409d, pci_subsys_0e11_0046_0e11_409d, 0}; +#undef pci_ss_info_0e11_409d +#define pci_ss_info_0e11_409d pci_ss_info_0e11_0046_0e11_409d +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4080 = + {0x0e11, 0x4080, pci_subsys_0e11_b178_0e11_4080, 0}; +#undef pci_ss_info_0e11_4080 +#define pci_ss_info_0e11_4080 pci_ss_info_0e11_b178_0e11_4080 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4082 = + {0x0e11, 0x4082, pci_subsys_0e11_b178_0e11_4082, 0}; +#undef pci_ss_info_0e11_4082 +#define pci_ss_info_0e11_4082 pci_ss_info_0e11_b178_0e11_4082 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4083 = + {0x0e11, 0x4083, pci_subsys_0e11_b178_0e11_4083, 0}; +#undef pci_ss_info_0e11_4083 +#define pci_ss_info_0e11_4083 pci_ss_info_0e11_b178_0e11_4083 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0003_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0003_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0003_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0006_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0006_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0006_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000a_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000a_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000a_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000b_0e11_6004 = + {0x0e11, 0x6004, pci_subsys_1000_000b_0e11_6004, 0}; +#undef pci_ss_info_0e11_6004 +#define pci_ss_info_0e11_6004 pci_ss_info_1000_000b_0e11_6004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000b_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000b_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000b_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000b_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000b_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000b_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000b_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_1000_000b_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_1000_000b_13e9_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000c_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000c_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000c_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000c_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3906 = + {0x1de1, 0x3906, pci_subsys_1000_000c_1de1_3906, 0}; +#undef pci_ss_info_1de1_3906 +#define pci_ss_info_1de1_3906 pci_ss_info_1000_000c_1de1_3906 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000f_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000f_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000f_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000f_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000f_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000f_1000_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1000_000f_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1000_000f_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1000_000f_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1000_000f_4c53_1050 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0010_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0010_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0010_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0012_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0012_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0012_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0013_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0013_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0013_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0020_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0020_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0021_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0021_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0021_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0021_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0021_124b_1070 = + {0x124b, 0x1070, pci_subsys_1000_0021_124b_1070, 0}; +#undef pci_ss_info_124b_1070 +#define pci_ss_info_124b_1070 pci_ss_info_1000_0021_124b_1070 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1000_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1000_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1300 = + {0x4c53, 0x1300, pci_subsys_1000_0021_4c53_1300, 0}; +#undef pci_ss_info_4c53_1300 +#define pci_ss_info_4c53_1300 pci_ss_info_1000_0021_4c53_1300 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1310 = + {0x4c53, 0x1310, pci_subsys_1000_0021_4c53_1310, 0}; +#undef pci_ss_info_4c53_1310 +#define pci_ss_info_4c53_1310 pci_ss_info_1000_0021_4c53_1310 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_0e11_00da = + {0x0e11, 0x00da, pci_subsys_1000_0030_0e11_00da, 0}; +#undef pci_ss_info_0e11_00da +#define pci_ss_info_0e11_00da pci_ss_info_1000_0030_0e11_00da +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0123 = + {0x1028, 0x0123, pci_subsys_1000_0030_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_1000_0030_1028_0123 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_014a = + {0x1028, 0x014a, pci_subsys_1000_0030_1028_014a, 0}; +#undef pci_ss_info_1028_014a +#define pci_ss_info_1028_014a pci_ss_info_1000_0030_1028_014a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_016c = + {0x1028, 0x016c, pci_subsys_1000_0030_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1000_0030_1028_016c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0183 = + {0x1028, 0x0183, pci_subsys_1000_0030_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_1000_0030_1028_0183 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0030_124b_1170 = + {0x124b, 0x1170, pci_subsys_1000_0030_124b_1170, 0}; +#undef pci_ss_info_124b_1170 +#define pci_ss_info_124b_1170 pci_ss_info_1000_0030_124b_1170 +static const pciSubsystemInfo pci_ss_info_1000_0030_1734_1052 = + {0x1734, 0x1052, pci_subsys_1000_0030_1734_1052, 0}; +#undef pci_ss_info_1734_1052 +#define pci_ss_info_1734_1052 pci_ss_info_1000_0030_1734_1052 +static const pciSubsystemInfo pci_ss_info_1000_0032_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0032_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0032_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0033 = + {0x1000, 0x0033, pci_subsys_1000_0040_1000_0033, 0}; +#undef pci_ss_info_1000_0033 +#define pci_ss_info_1000_0033 pci_ss_info_1000_0040_1000_0033 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0066 = + {0x1000, 0x0066, pci_subsys_1000_0040_1000_0066, 0}; +#undef pci_ss_info_1000_0066 +#define pci_ss_info_1000_0066 pci_ss_info_1000_0040_1000_0066 +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0530 = + {0x1000, 0x0530, pci_subsys_1000_0407_1000_0530, 0}; +#undef pci_ss_info_1000_0530 +#define pci_ss_info_1000_0530 pci_ss_info_1000_0407_1000_0530 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0531 = + {0x1000, 0x0531, pci_subsys_1000_0407_1000_0531, 0}; +#undef pci_ss_info_1000_0531 +#define pci_ss_info_1000_0531 pci_ss_info_1000_0407_1000_0531 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0532 = + {0x1000, 0x0532, pci_subsys_1000_0407_1000_0532, 0}; +#undef pci_ss_info_1000_0532 +#define pci_ss_info_1000_0532 pci_ss_info_1000_0407_1000_0532 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_0407_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_0407_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_0407_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_0407_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0530 = + {0x8086, 0x0530, pci_subsys_1000_0407_8086_0530, 0}; +#undef pci_ss_info_8086_0530 +#define pci_ss_info_8086_0530 pci_ss_info_1000_0407_8086_0530 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0532 = + {0x8086, 0x0532, pci_subsys_1000_0407_8086_0532, 0}; +#undef pci_ss_info_8086_0532 +#define pci_ss_info_8086_0532 pci_ss_info_1000_0407_8086_0532 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0001 = + {0x1000, 0x0001, pci_subsys_1000_0408_1000_0001, 0}; +#undef pci_ss_info_1000_0001 +#define pci_ss_info_1000_0001 pci_ss_info_1000_0408_1000_0001 +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0002 = + {0x1000, 0x0002, pci_subsys_1000_0408_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_1000_0408_1000_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1025_004d = + {0x1025, 0x004d, pci_subsys_1000_0408_1025_004d, 0}; +#undef pci_ss_info_1025_004d +#define pci_ss_info_1025_004d pci_ss_info_1000_0408_1025_004d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0001 = + {0x1028, 0x0001, pci_subsys_1000_0408_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1000_0408_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0002 = + {0x1028, 0x0002, pci_subsys_1000_0408_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1000_0408_1028_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1734_1065 = + {0x1734, 0x1065, pci_subsys_1000_0408_1734_1065, 0}; +#undef pci_ss_info_1734_1065 +#define pci_ss_info_1734_1065 pci_ss_info_1000_0408_1734_1065 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_8086_0002 = + {0x8086, 0x0002, pci_subsys_1000_0408_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_1000_0408_8086_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3004 = + {0x1000, 0x3004, pci_subsys_1000_0409_1000_3004, 0}; +#undef pci_ss_info_1000_3004 +#define pci_ss_info_1000_3004 pci_ss_info_1000_0409_1000_3004 +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3008 = + {0x1000, 0x3008, pci_subsys_1000_0409_1000_3008, 0}; +#undef pci_ss_info_1000_3008 +#define pci_ss_info_1000_3008 pci_ss_info_1000_0409_1000_3008 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3008 = + {0x8086, 0x3008, pci_subsys_1000_0409_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_1000_0409_8086_3008 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3431 = + {0x8086, 0x3431, pci_subsys_1000_0409_8086_3431, 0}; +#undef pci_ss_info_8086_3431 +#define pci_ss_info_8086_3431 pci_ss_info_1000_0409_8086_3431 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3499 = + {0x8086, 0x3499, pci_subsys_1000_0409_8086_3499, 0}; +#undef pci_ss_info_8086_3499 +#define pci_ss_info_8086_3499 pci_ss_info_1000_0409_8086_3499 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0622_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_0622_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_0622_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_0626_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0626_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0626_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0518 = + {0x1000, 0x0518, pci_subsys_1000_1960_1000_0518, 0}; +#undef pci_ss_info_1000_0518 +#define pci_ss_info_1000_0518 pci_ss_info_1000_1960_1000_0518 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0520 = + {0x1000, 0x0520, pci_subsys_1000_1960_1000_0520, 0}; +#undef pci_ss_info_1000_0520 +#define pci_ss_info_1000_0520 pci_ss_info_1000_1960_1000_0520 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0522 = + {0x1000, 0x0522, pci_subsys_1000_1960_1000_0522, 0}; +#undef pci_ss_info_1000_0522 +#define pci_ss_info_1000_0522 pci_ss_info_1000_1960_1000_0522 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0523 = + {0x1000, 0x0523, pci_subsys_1000_1960_1000_0523, 0}; +#undef pci_ss_info_1000_0523 +#define pci_ss_info_1000_0523 pci_ss_info_1000_1960_1000_0523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_4523 = + {0x1000, 0x4523, pci_subsys_1000_1960_1000_4523, 0}; +#undef pci_ss_info_1000_4523 +#define pci_ss_info_1000_4523 pci_ss_info_1000_1960_1000_4523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_a520 = + {0x1000, 0xa520, pci_subsys_1000_1960_1000_a520, 0}; +#undef pci_ss_info_1000_a520 +#define pci_ss_info_1000_a520 pci_ss_info_1000_1960_1000_a520 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_1960_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_1960_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0520 = + {0x8086, 0x0520, pci_subsys_1000_1960_8086_0520, 0}; +#undef pci_ss_info_8086_0520 +#define pci_ss_info_8086_0520 pci_ss_info_1000_1960_8086_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0523 = + {0x8086, 0x0523, pci_subsys_1000_1960_8086_0523, 0}; +#undef pci_ss_info_8086_0523 +#define pci_ss_info_8086_0523 pci_ss_info_1000_1960_8086_0523 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4150_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4150_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4150_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4150_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4150_1458_4024 = + {0x1458, 0x4024, pci_subsys_1002_4150_1458_4024, 0}; +#undef pci_ss_info_1458_4024 +#define pci_ss_info_1458_4024 pci_ss_info_1002_4150_1458_4024 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2064 = + {0x148c, 0x2064, pci_subsys_1002_4150_148c_2064, 0}; +#undef pci_ss_info_148c_2064 +#define pci_ss_info_148c_2064 pci_ss_info_1002_4150_148c_2064 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2066 = + {0x148c, 0x2066, pci_subsys_1002_4150_148c_2066, 0}; +#undef pci_ss_info_148c_2066 +#define pci_ss_info_148c_2066 pci_ss_info_1002_4150_148c_2066 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c19 = + {0x174b, 0x7c19, pci_subsys_1002_4150_174b_7c19, 0}; +#undef pci_ss_info_174b_7c19 +#define pci_ss_info_174b_7c19 pci_ss_info_1002_4150_174b_7c19 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4150_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4150_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4150_17ee_2002 = + {0x17ee, 0x2002, pci_subsys_1002_4150_17ee_2002, 0}; +#undef pci_ss_info_17ee_2002 +#define pci_ss_info_17ee_2002 pci_ss_info_1002_4150_17ee_2002 +static const pciSubsystemInfo pci_ss_info_1002_4150_18bc_0101 = + {0x18bc, 0x0101, pci_subsys_1002_4150_18bc_0101, 0}; +#undef pci_ss_info_18bc_0101 +#define pci_ss_info_18bc_0101 pci_ss_info_1002_4150_18bc_0101 +static const pciSubsystemInfo pci_ss_info_1002_4151_1043_c004 = + {0x1043, 0xc004, pci_subsys_1002_4151_1043_c004, 0}; +#undef pci_ss_info_1043_c004 +#define pci_ss_info_1043_c004 pci_ss_info_1002_4151_1043_c004 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4152_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4152_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_4772 = + {0x1002, 0x4772, pci_subsys_1002_4152_1002_4772, 0}; +#undef pci_ss_info_1002_4772 +#define pci_ss_info_1002_4772 pci_ss_info_1002_4152_1002_4772 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c002 = + {0x1043, 0xc002, pci_subsys_1002_4152_1043_c002, 0}; +#undef pci_ss_info_1043_c002 +#define pci_ss_info_1043_c002 pci_ss_info_1002_4152_1043_c002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c01a = + {0x1043, 0xc01a, pci_subsys_1002_4152_1043_c01a, 0}; +#undef pci_ss_info_1043_c01a +#define pci_ss_info_1043_c01a pci_ss_info_1002_4152_1043_c01a +static const pciSubsystemInfo pci_ss_info_1002_4152_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4152_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4152_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4152_1787_4002 = + {0x1787, 0x4002, pci_subsys_1002_4152_1787_4002, 0}; +#undef pci_ss_info_1787_4002 +#define pci_ss_info_1787_4002 pci_ss_info_1002_4152_1787_4002 +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4170_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4170_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4170_1458_4025 = + {0x1458, 0x4025, pci_subsys_1002_4170_1458_4025, 0}; +#undef pci_ss_info_1458_4025 +#define pci_ss_info_1458_4025 pci_ss_info_1002_4170_1458_4025 +static const pciSubsystemInfo pci_ss_info_1002_4170_148c_2067 = + {0x148c, 0x2067, pci_subsys_1002_4170_148c_2067, 0}; +#undef pci_ss_info_148c_2067 +#define pci_ss_info_148c_2067 pci_ss_info_1002_4170_148c_2067 +static const pciSubsystemInfo pci_ss_info_1002_4170_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4170_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4170_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4170_17ee_2003 = + {0x17ee, 0x2003, pci_subsys_1002_4170_17ee_2003, 0}; +#undef pci_ss_info_17ee_2003 +#define pci_ss_info_17ee_2003 pci_ss_info_1002_4170_17ee_2003 +static const pciSubsystemInfo pci_ss_info_1002_4170_18bc_0100 = + {0x18bc, 0x0100, pci_subsys_1002_4170_18bc_0100, 0}; +#undef pci_ss_info_18bc_0100 +#define pci_ss_info_18bc_0100 pci_ss_info_1002_4170_18bc_0100 +static const pciSubsystemInfo pci_ss_info_1002_4171_1043_c005 = + {0x1043, 0xc005, pci_subsys_1002_4171_1043_c005, 0}; +#undef pci_ss_info_1043_c005 +#define pci_ss_info_1043_c005 pci_ss_info_1002_4171_1043_c005 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4172_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4172_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_4773 = + {0x1002, 0x4773, pci_subsys_1002_4172_1002_4773, 0}; +#undef pci_ss_info_1002_4773 +#define pci_ss_info_1002_4773 pci_ss_info_1002_4172_1002_4773 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c003 = + {0x1043, 0xc003, pci_subsys_1002_4172_1043_c003, 0}; +#undef pci_ss_info_1043_c003 +#define pci_ss_info_1043_c003 pci_ss_info_1002_4172_1043_c003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c01b = + {0x1043, 0xc01b, pci_subsys_1002_4172_1043_c01b, 0}; +#undef pci_ss_info_1043_c01b +#define pci_ss_info_1043_c01b pci_ss_info_1002_4172_1043_c01b +static const pciSubsystemInfo pci_ss_info_1002_4172_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4172_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4172_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4172_1787_4003 = + {0x1787, 0x4003, pci_subsys_1002_4172_1787_4003, 0}; +#undef pci_ss_info_1787_4003 +#define pci_ss_info_1787_4003 pci_ss_info_1002_4172_1787_4003 +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4336_1002_4336 = + {0x1002, 0x4336, pci_subsys_1002_4336_1002_4336, 0}; +#undef pci_ss_info_1002_4336 +#define pci_ss_info_1002_4336 pci_ss_info_1002_4336_1002_4336 +static const pciSubsystemInfo pci_ss_info_1002_4336_103c_0024 = + {0x103c, 0x0024, pci_subsys_1002_4336_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_1002_4336_103c_0024 +static const pciSubsystemInfo pci_ss_info_1002_4336_161f_2029 = + {0x161f, 0x2029, pci_subsys_1002_4336_161f_2029, 0}; +#undef pci_ss_info_161f_2029 +#define pci_ss_info_161f_2029 pci_ss_info_1002_4336_161f_2029 +static const pciSubsystemInfo pci_ss_info_1002_4337_1014_053a = + {0x1014, 0x053a, pci_subsys_1002_4337_1014_053a, 0}; +#undef pci_ss_info_1014_053a +#define pci_ss_info_1014_053a pci_ss_info_1002_4337_1014_053a +static const pciSubsystemInfo pci_ss_info_1002_4337_103c_0850 = + {0x103c, 0x0850, pci_subsys_1002_4337_103c_0850, 0}; +#undef pci_ss_info_103c_0850 +#define pci_ss_info_103c_0850 pci_ss_info_1002_4337_103c_0850 +static const pciSubsystemInfo pci_ss_info_1002_4370_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4370_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4370_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4371_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4371_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4371_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4372_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4372_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4372_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4373_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4373_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4373_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4374_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4374_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4374_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4375_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4375_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4375_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4376_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4376_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4376_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4377_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4377_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4377_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4378_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4378_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4378_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00ce = + {0x1028, 0x00ce, pci_subsys_1002_4752_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_1002_4752_1028_00ce +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1002_4752_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1002_4752_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_0134 = + {0x1028, 0x0134, pci_subsys_1002_4752_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_1002_4752_1028_0134 +static const pciSubsystemInfo pci_ss_info_1002_4752_1734_007a = + {0x1734, 0x007a, pci_subsys_1002_4752_1734_007a, 0}; +#undef pci_ss_info_1734_007a +#define pci_ss_info_1734_007a pci_ss_info_1002_4752_1734_007a +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3411 = + {0x8086, 0x3411, pci_subsys_1002_4752_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_1002_4752_8086_3411 +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3427 = + {0x8086, 0x3427, pci_subsys_1002_4752_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_1002_4752_8086_3427 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_475a_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_475a_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e7 = + {0x0e11, 0xb0e7, pci_subsys_1002_4c42_0e11_b0e7, 0}; +#undef pci_ss_info_0e11_b0e7 +#define pci_ss_info_0e11_b0e7 pci_ss_info_1002_4c42_0e11_b0e7 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c46_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_1002_4c46_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_1002_4c46_1028_00b1 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b160 = + {0x0e11, 0xb160, pci_subsys_1002_4c4d_0e11_b160, 0}; +#undef pci_ss_info_0e11_b160 +#define pci_ss_info_0e11_b160 pci_ss_info_1002_4c4d_0e11_b160 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00aa = + {0x1028, 0x00aa, pci_subsys_1002_4c4d_1028_00aa, 0}; +#undef pci_ss_info_1028_00aa +#define pci_ss_info_1028_00aa pci_ss_info_1002_4c4d_1028_00aa +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00bb = + {0x1028, 0x00bb, pci_subsys_1002_4c4d_1028_00bb, 0}; +#undef pci_ss_info_1028_00bb +#define pci_ss_info_1028_00bb pci_ss_info_1002_4c4d_1028_00bb +static const pciSubsystemInfo pci_ss_info_1002_4c4d_10e1_10cf = + {0x10e1, 0x10cf, pci_subsys_1002_4c4d_10e1_10cf, 0}; +#undef pci_ss_info_10e1_10cf +#define pci_ss_info_10e1_10cf pci_ss_info_1002_4c4d_10e1_10cf +static const pciSubsystemInfo pci_ss_info_1002_4c4d_13bd_1019 = + {0x13bd, 0x1019, pci_subsys_1002_4c4d_13bd_1019, 0}; +#undef pci_ss_info_13bd_1019 +#define pci_ss_info_13bd_1019 pci_ss_info_1002_4c4d_13bd_1019 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c52_1033_8112 = + {0x1033, 0x8112, pci_subsys_1002_4c52_1033_8112, 0}; +#undef pci_ss_info_1033_8112 +#define pci_ss_info_1033_8112 pci_ss_info_1002_4c52_1033_8112 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_012a = + {0x1028, 0x012a, pci_subsys_1002_4c57_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_1002_4c57_1028_012a +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c59_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c59_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1509_1930 = + {0x1509, 0x1930, pci_subsys_1002_4c59_1509_1930, 0}; +#undef pci_ss_info_1509_1930 +#define pci_ss_info_1509_1930 pci_ss_info_1002_4c59_1509_1930 +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_515e = + {0x1002, 0x515e, pci_subsys_1002_4e44_1002_515e, 0}; +#undef pci_ss_info_1002_515e +#define pci_ss_info_1002_515e pci_ss_info_1002_4e44_1002_515e +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_5965 = + {0x1002, 0x5965, pci_subsys_1002_4e44_1002_5965, 0}; +#undef pci_ss_info_1002_5965 +#define pci_ss_info_1002_5965 pci_ss_info_1002_4e44_1002_5965 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4e45_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4e45_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1681_0002 = + {0x1681, 0x0002, pci_subsys_1002_4e45_1681_0002, 0}; +#undef pci_ss_info_1681_0002 +#define pci_ss_info_1681_0002 pci_ss_info_1002_4e45_1681_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1025_005a = + {0x1025, 0x005a, pci_subsys_1002_4e50_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1002_4e50_1025_005a +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_088c = + {0x103c, 0x088c, pci_subsys_1002_4e50_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1002_4e50_103c_088c +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_0890 = + {0x103c, 0x0890, pci_subsys_1002_4e50_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1002_4e50_103c_0890 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1734_1055 = + {0x1734, 0x1055, pci_subsys_1002_4e50_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_1002_4e50_1734_1055 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4e65_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4e65_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1681_0003 = + {0x1681, 0x0003, pci_subsys_1002_4e65_1681_0003, 0}; +#undef pci_ss_info_1681_0003 +#define pci_ss_info_1681_0003 pci_ss_info_1002_4e65_1681_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e6a_1002_4e71 = + {0x1002, 0x4e71, pci_subsys_1002_4e6a_1002_4e71, 0}; +#undef pci_ss_info_1002_4e71 +#define pci_ss_info_1002_4e71 pci_ss_info_1002_4e6a_1002_4e71 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_1681_0010 = + {0x1681, 0x0010, pci_subsys_1002_514c_1681_0010, 0}; +#undef pci_ss_info_1681_0010 +#define pci_ss_info_1681_0010 pci_ss_info_1002_514c_1681_0010 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_103a = + {0x1002, 0x103a, pci_subsys_1002_5157_1002_103a, 0}; +#undef pci_ss_info_1002_103a +#define pci_ss_info_1002_103a pci_ss_info_1002_5157_1002_103a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7146 = + {0x174b, 0x7146, pci_subsys_1002_5157_174b_7146, 0}; +#undef pci_ss_info_174b_7146 +#define pci_ss_info_174b_7146 pci_ss_info_1002_5157_174b_7146 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1028_019a = + {0x1028, 0x019a, pci_subsys_1002_5159_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_1002_5159_1028_019a +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_5159_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_5159_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_5346_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5346_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5346_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5941_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5941_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5941_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5941_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5941_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5941_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5941_17af_200d = + {0x17af, 0x200d, pci_subsys_1002_5941_17af_200d, 0}; +#undef pci_ss_info_17af_200d +#define pci_ss_info_17af_200d pci_ss_info_1002_5941_17af_200d +static const pciSubsystemInfo pci_ss_info_1002_5941_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5941_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5941_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5950_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5950_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5950_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5954_1002_5954 = + {0x1002, 0x5954, pci_subsys_1002_5954_1002_5954, 0}; +#undef pci_ss_info_1002_5954 +#define pci_ss_info_1002_5954 pci_ss_info_1002_5954_1002_5954 +static const pciSubsystemInfo pci_ss_info_1002_5955_1002_5955 = + {0x1002, 0x5955, pci_subsys_1002_5955_1002_5955, 0}; +#undef pci_ss_info_1002_5955 +#define pci_ss_info_1002_5955 pci_ss_info_1002_5955_1002_5955 +static const pciSubsystemInfo pci_ss_info_1002_5955_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5955_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5955_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5961_1002_2f72 = + {0x1002, 0x2f72, pci_subsys_1002_5961_1002_2f72, 0}; +#undef pci_ss_info_1002_2f72 +#define pci_ss_info_1002_2f72 pci_ss_info_1002_5961_1002_2f72 +static const pciSubsystemInfo pci_ss_info_1002_5961_1019_4c30 = + {0x1019, 0x4c30, pci_subsys_1002_5961_1019_4c30, 0}; +#undef pci_ss_info_1019_4c30 +#define pci_ss_info_1019_4c30 pci_ss_info_1002_5961_1019_4c30 +static const pciSubsystemInfo pci_ss_info_1002_5961_12ab_5961 = + {0x12ab, 0x5961, pci_subsys_1002_5961_12ab_5961, 0}; +#undef pci_ss_info_12ab_5961 +#define pci_ss_info_12ab_5961 pci_ss_info_1002_5961_12ab_5961 +static const pciSubsystemInfo pci_ss_info_1002_5961_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5961_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5961_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5961_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5961_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5961_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5961_17af_200c = + {0x17af, 0x200c, pci_subsys_1002_5961_17af_200c, 0}; +#undef pci_ss_info_17af_200c +#define pci_ss_info_17af_200c pci_ss_info_1002_5961_17af_200c +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5961_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5961_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0051 = + {0x18bc, 0x0051, pci_subsys_1002_5961_18bc_0051, 0}; +#undef pci_ss_info_18bc_0051 +#define pci_ss_info_18bc_0051 pci_ss_info_1002_5961_18bc_0051 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0053 = + {0x18bc, 0x0053, pci_subsys_1002_5961_18bc_0053, 0}; +#undef pci_ss_info_18bc_0053 +#define pci_ss_info_18bc_0053 pci_ss_info_1002_5961_18bc_0053 +static const pciSubsystemInfo pci_ss_info_1002_5964_1043_c006 = + {0x1043, 0xc006, pci_subsys_1002_5964_1043_c006, 0}; +#undef pci_ss_info_1043_c006 +#define pci_ss_info_1043_c006 pci_ss_info_1002_5964_1043_c006 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5964_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5964_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5964_147b_6191 = + {0x147b, 0x6191, pci_subsys_1002_5964_147b_6191, 0}; +#undef pci_ss_info_147b_6191 +#define pci_ss_info_147b_6191 pci_ss_info_1002_5964_147b_6191 +static const pciSubsystemInfo pci_ss_info_1002_5964_148c_2073 = + {0x148c, 0x2073, pci_subsys_1002_5964_148c_2073, 0}; +#undef pci_ss_info_148c_2073 +#define pci_ss_info_148c_2073 pci_ss_info_1002_5964_148c_2073 +static const pciSubsystemInfo pci_ss_info_1002_5964_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5964_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5964_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5964_1787_5964 = + {0x1787, 0x5964, pci_subsys_1002_5964_1787_5964, 0}; +#undef pci_ss_info_1787_5964 +#define pci_ss_info_1787_5964 pci_ss_info_1002_5964_1787_5964 +static const pciSubsystemInfo pci_ss_info_1002_5964_17af_2012 = + {0x17af, 0x2012, pci_subsys_1002_5964_17af_2012, 0}; +#undef pci_ss_info_17af_2012 +#define pci_ss_info_17af_2012 pci_ss_info_1002_5964_17af_2012 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0170 = + {0x18bc, 0x0170, pci_subsys_1002_5964_18bc_0170, 0}; +#undef pci_ss_info_18bc_0170 +#define pci_ss_info_18bc_0170 pci_ss_info_1002_5964_18bc_0170 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0173 = + {0x18bc, 0x0173, pci_subsys_1002_5964_18bc_0173, 0}; +#undef pci_ss_info_18bc_0173 +#define pci_ss_info_18bc_0173 pci_ss_info_1002_5964_18bc_0173 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_002a = + {0x1043, 0x002a, pci_subsys_1002_5b60_1043_002a, 0}; +#undef pci_ss_info_1043_002a +#define pci_ss_info_1043_002a pci_ss_info_1002_5b60_1043_002a +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_032e = + {0x1043, 0x032e, pci_subsys_1002_5b60_1043_032e, 0}; +#undef pci_ss_info_1043_032e +#define pci_ss_info_1043_032e pci_ss_info_1002_5b60_1043_032e +static const pciSubsystemInfo pci_ss_info_1002_5c63_1002_5c63 = + {0x1002, 0x5c63, pci_subsys_1002_5c63_1002_5c63, 0}; +#undef pci_ss_info_1002_5c63 +#define pci_ss_info_1002_5c63 pci_ss_info_1002_5c63_1002_5c63 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5d44_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5d44_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5d44_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5d44_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5d44_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1787_5965 = + {0x1787, 0x5965, pci_subsys_1002_5d44_1787_5965, 0}; +#undef pci_ss_info_1787_5965 +#define pci_ss_info_1787_5965 pci_ss_info_1002_5d44_1787_5965 +static const pciSubsystemInfo pci_ss_info_1002_5d44_17af_2013 = + {0x17af, 0x2013, pci_subsys_1002_5d44_17af_2013, 0}; +#undef pci_ss_info_17af_2013 +#define pci_ss_info_17af_2013 pci_ss_info_1002_5d44_17af_2013 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0171 = + {0x18bc, 0x0171, pci_subsys_1002_5d44_18bc_0171, 0}; +#undef pci_ss_info_18bc_0171 +#define pci_ss_info_18bc_0171 pci_ss_info_1002_5d44_18bc_0171 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0172 = + {0x18bc, 0x0172, pci_subsys_1002_5d44_18bc_0172, 0}; +#undef pci_ss_info_18bc_0172 +#define pci_ss_info_18bc_0172 pci_ss_info_1002_5d44_18bc_0172 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b12 = + {0x1002, 0x0b12, pci_subsys_1002_5d52_1002_0b12, 0}; +#undef pci_ss_info_1002_0b12 +#define pci_ss_info_1002_0b12 pci_ss_info_1002_5d52_1002_0b12 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b13 = + {0x1002, 0x0b13, pci_subsys_1002_5d52_1002_0b13, 0}; +#undef pci_ss_info_1002_0b13 +#define pci_ss_info_1002_0b13 pci_ss_info_1002_5d52_1002_0b13 +static const pciSubsystemInfo pci_ss_info_1002_5e4d_148c_2116 = + {0x148c, 0x2116, pci_subsys_1002_5e4d_148c_2116, 0}; +#undef pci_ss_info_148c_2116 +#define pci_ss_info_148c_2116 pci_ss_info_1002_5e4d_148c_2116 +static const pciSubsystemInfo pci_ss_info_1002_5e6d_148c_2117 = + {0x148c, 0x2117, pci_subsys_1002_5e6d_148c_2117, 0}; +#undef pci_ss_info_148c_2117 +#define pci_ss_info_148c_2117 pci_ss_info_1002_5e6d_148c_2117 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_100b_0020_103c_0024 = + {0x103c, 0x0024, pci_subsys_100b_0020_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_100b_0020_103c_0024 +static const pciSubsystemInfo pci_ss_info_100b_0020_1385_f311 = + {0x1385, 0xf311, pci_subsys_100b_0020_1385_f311, 0}; +#undef pci_ss_info_1385_f311 +#define pci_ss_info_1385_f311 pci_ss_info_100b_0020_1385_f311 +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0019_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0019_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_14cb_0100 = + {0x14cb, 0x0100, pci_subsys_1011_0019_14cb_0100, 0}; +#undef pci_ss_info_14cb_0100 +#define pci_ss_info_14cb_0100 pci_ss_info_1011_0019_14cb_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1011_0046_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1011_0046_4c53_1050 +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_1011_0046_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_1011_0046_4c53_1051 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0364 = + {0x9005, 0x0364, pci_subsys_1011_0046_9005_0364, 0}; +#undef pci_ss_info_9005_0364 +#define pci_ss_info_9005_0364 pci_ss_info_1011_0046_9005_0364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_1136 = + {0x153b, 0x1136, pci_subsys_1013_6003_153b_1136, 0}; +#undef pci_ss_info_153b_1136 +#define pci_ss_info_153b_1136 pci_ss_info_1013_6003_153b_1136 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_0031_1014_0031 = + {0x1014, 0x0031, pci_subsys_1014_0031_1014_0031, 0}; +#undef pci_ss_info_1014_0031 +#define pci_ss_info_1014_0031 pci_ss_info_1014_0031_1014_0031 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +#endif +static const pciSubsystemInfo pci_ss_info_1014_00b7_1092_00b8 = + {0x1092, 0x00b8, pci_subsys_1014_00b7_1092_00b8, 0}; +#undef pci_ss_info_1092_00b8 +#define pci_ss_info_1092_00b8 pci_ss_info_1014_00b7_1092_00b8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0241 = + {0x1014, 0x0241, pci_subsys_1014_0180_1014_0241, 0}; +#undef pci_ss_info_1014_0241 +#define pci_ss_info_1014_0241 pci_ss_info_1014_0180_1014_0241 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0264 = + {0x1014, 0x0264, pci_subsys_1014_0180_1014_0264, 0}; +#undef pci_ss_info_1014_0264 +#define pci_ss_info_1014_0264 pci_ss_info_1014_0180_1014_0264 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_021a = + {0x1014, 0x021a, pci_subsys_1014_0219_1014_021a, 0}; +#undef pci_ss_info_1014_021a +#define pci_ss_info_1014_021a pci_ss_info_1014_0219_1014_021a +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0251 = + {0x1014, 0x0251, pci_subsys_1014_0219_1014_0251, 0}; +#undef pci_ss_info_1014_0251 +#define pci_ss_info_1014_0251 pci_ss_info_1014_0219_1014_0251 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0252 = + {0x1014, 0x0252, pci_subsys_1014_0219_1014_0252, 0}; +#undef pci_ss_info_1014_0252 +#define pci_ss_info_1014_0252 pci_ss_info_1014_0219_1014_0252 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_028d = + {0x1014, 0x028d, pci_subsys_1014_028c_1014_028d, 0}; +#undef pci_ss_info_1014_028d +#define pci_ss_info_1014_028d pci_ss_info_1014_028c_1014_028d +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02be = + {0x1014, 0x02be, pci_subsys_1014_028c_1014_02be, 0}; +#undef pci_ss_info_1014_02be +#define pci_ss_info_1014_02be pci_ss_info_1014_028c_1014_02be +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02c0 = + {0x1014, 0x02c0, pci_subsys_1014_028c_1014_02c0, 0}; +#undef pci_ss_info_1014_02c0 +#define pci_ss_info_1014_02c0 pci_ss_info_1014_028c_1014_02c0 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_030d = + {0x1014, 0x030d, pci_subsys_1014_028c_1014_030d, 0}; +#undef pci_ss_info_1014_030d +#define pci_ss_info_1014_030d pci_ss_info_1014_028c_1014_030d +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0477 = + {0x101e, 0x0477, pci_subsys_101e_1960_101e_0477, 0}; +#undef pci_ss_info_101e_0477 +#define pci_ss_info_101e_0477 pci_ss_info_101e_1960_101e_0477 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0494 = + {0x101e, 0x0494, pci_subsys_101e_1960_101e_0494, 0}; +#undef pci_ss_info_101e_0494 +#define pci_ss_info_101e_0494 pci_ss_info_101e_1960_101e_0494 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0503 = + {0x101e, 0x0503, pci_subsys_101e_1960_101e_0503, 0}; +#undef pci_ss_info_101e_0503 +#define pci_ss_info_101e_0503 pci_ss_info_101e_1960_101e_0503 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0511 = + {0x101e, 0x0511, pci_subsys_101e_1960_101e_0511, 0}; +#undef pci_ss_info_101e_0511 +#define pci_ss_info_101e_0511 pci_ss_info_101e_1960_101e_0511 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0522 = + {0x101e, 0x0522, pci_subsys_101e_1960_101e_0522, 0}; +#undef pci_ss_info_101e_0522 +#define pci_ss_info_101e_0522 pci_ss_info_101e_1960_101e_0522 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_103c_60e7 = + {0x103c, 0x60e7, pci_subsys_101e_1960_103c_60e7, 0}; +#undef pci_ss_info_103c_60e7 +#define pci_ss_info_103c_60e7 pci_ss_info_101e_1960_103c_60e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_1022_2000 = + {0x1022, 0x2000, pci_subsys_1022_2000_1022_2000, 0}; +#undef pci_ss_info_1022_2000 +#define pci_ss_info_1022_2000 pci_ss_info_1022_2000_1022_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2702 = + {0x1259, 0x2702, pci_subsys_1022_2000_1259_2702, 0}; +#undef pci_ss_info_1259_2702 +#define pci_ss_info_1259_2702 pci_ss_info_1022_2000_1259_2702 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2703 = + {0x1259, 0x2703, pci_subsys_1022_2000_1259_2703, 0}; +#undef pci_ss_info_1259_2703 +#define pci_ss_info_1259_2703 pci_ss_info_1022_2000_1259_2703 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1022_2000_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1022_2000_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_1022_2000_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_1022_2000_4c53_1010 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_1022_2000_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_1022_2000_4c53_1020 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_1022_2000_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_1022_2000_4c53_1030 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_1022_2000_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_1022_2000_4c53_1040 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_1022_2000_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_1022_2000_4c53_1060 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7460_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7460_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7460_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7464_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7464_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7464_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7468_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7468_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7468_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7469_1022_2b80 = + {0x1022, 0x2b80, pci_subsys_1022_7469_1022_2b80, 0}; +#undef pci_ss_info_1022_2b80 +#define pci_ss_info_1022_2b80 pci_ss_info_1022_7469_1022_2b80 +static const pciSubsystemInfo pci_ss_info_1022_7469_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7469_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7469_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746b_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746b_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746b_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746d_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746d_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746d_161f_3017 +static const pciSubsystemInfo pci_ss_info_1023_2001_122d_1400 = + {0x122d, 0x1400, pci_subsys_1023_2001_122d_1400, 0}; +#undef pci_ss_info_122d_1400 +#define pci_ss_info_122d_1400 pci_ss_info_1023_2001_122d_1400 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_1025 = + {0x1014, 0x1025, pci_subsys_1023_8620_1014_1025, 0}; +#undef pci_ss_info_1014_1025 +#define pci_ss_info_1014_1025 pci_ss_info_1023_8620_1014_1025 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016c = + {0x1028, 0x016c, pci_subsys_1028_0013_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1028_0013_1028_016c +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016d = + {0x1028, 0x016d, pci_subsys_1028_0013_1028_016d, 0}; +#undef pci_ss_info_1028_016d +#define pci_ss_info_1028_016d pci_ss_info_1028_0013_1028_016d +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016e = + {0x1028, 0x016e, pci_subsys_1028_0013_1028_016e, 0}; +#undef pci_ss_info_1028_016e +#define pci_ss_info_1028_016e pci_ss_info_1028_0013_1028_016e +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016f = + {0x1028, 0x016f, pci_subsys_1028_0013_1028_016f, 0}; +#undef pci_ss_info_1028_016f +#define pci_ss_info_1028_016f pci_ss_info_1028_0013_1028_016f +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_0170 = + {0x1028, 0x0170, pci_subsys_1028_0013_1028_0170, 0}; +#undef pci_ss_info_1028_0170 +#define pci_ss_info_1028_0170 pci_ss_info_1028_0013_1028_0170 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_102a_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_102a_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_0106 = + {0x9005, 0x0106, pci_subsys_102a_001f_9005_0106, 0}; +#undef pci_ss_info_9005_0106 +#define pci_ss_info_9005_0106 pci_ss_info_102a_001f_9005_0106 +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_102a_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_102a_001f_9005_a180 +#endif +static const pciSubsystemInfo pci_ss_info_102a_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_102a_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_102a_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0106 = + {0x1028, 0x0106, pci_subsys_102a_00cf_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_102a_00cf_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0121 = + {0x1028, 0x0121, pci_subsys_102a_00cf_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_102a_00cf_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d43 = + {0x102b, 0x0d43, pci_subsys_102b_0525_102b_0d43, 0}; +#undef pci_ss_info_102b_0d43 +#define pci_ss_info_102b_0d43 pci_ss_info_102b_0525_102b_0d43 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0850 = + {0x102b, 0x0850, pci_subsys_102b_0527_102b_0850, 0}; +#undef pci_ss_info_102b_0850 +#define pci_ss_info_102b_0850 pci_ss_info_102b_0527_102b_0850 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1020 = + {0x102b, 0x1020, pci_subsys_102b_0528_102b_1020, 0}; +#undef pci_ss_info_102b_1020 +#define pci_ss_info_102b_1020 pci_ss_info_102b_0528_102b_1020 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1030 = + {0x102b, 0x1030, pci_subsys_102b_0528_102b_1030, 0}; +#undef pci_ss_info_102b_1030 +#define pci_ss_info_102b_1030 pci_ss_info_102b_0528_102b_1030 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_14e1 = + {0x102b, 0x14e1, pci_subsys_102b_0528_102b_14e1, 0}; +#undef pci_ss_info_102b_14e1 +#define pci_ss_info_102b_14e1 pci_ss_info_102b_0528_102b_14e1 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_2021 = + {0x102b, 0x2021, pci_subsys_102b_0528_102b_2021, 0}; +#undef pci_ss_info_102b_2021 +#define pci_ss_info_102b_2021 pci_ss_info_102b_0528_102b_2021 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1820 = + {0x102b, 0x1820, pci_subsys_102b_2537_102b_1820, 0}; +#undef pci_ss_info_102b_1820 +#define pci_ss_info_102b_1820 pci_ss_info_102b_2537_102b_1820 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1830 = + {0x102b, 0x1830, pci_subsys_102b_2537_102b_1830, 0}; +#undef pci_ss_info_102b_1830 +#define pci_ss_info_102b_1830 pci_ss_info_102b_2537_102b_1830 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1c10 = + {0x102b, 0x1c10, pci_subsys_102b_2537_102b_1c10, 0}; +#undef pci_ss_info_102b_1c10 +#define pci_ss_info_102b_1c10 pci_ss_info_102b_2537_102b_1c10 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2811 = + {0x102b, 0x2811, pci_subsys_102b_2537_102b_2811, 0}; +#undef pci_ss_info_102b_2811 +#define pci_ss_info_102b_2811 pci_ss_info_102b_2537_102b_2811 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2c11 = + {0x102b, 0x2c11, pci_subsys_102b_2537_102b_2c11, 0}; +#undef pci_ss_info_102b_2c11 +#define pci_ss_info_102b_2c11 pci_ss_info_102b_2537_102b_2c11 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_08c7 = + {0x102b, 0x08c7, pci_subsys_102b_2538_102b_08c7, 0}; +#undef pci_ss_info_102b_08c7 +#define pci_ss_info_102b_08c7 pci_ss_info_102b_2538_102b_08c7 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_0907 = + {0x102b, 0x0907, pci_subsys_102b_2538_102b_0907, 0}; +#undef pci_ss_info_102b_0907 +#define pci_ss_info_102b_0907 pci_ss_info_102b_2538_102b_0907 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1047 = + {0x102b, 0x1047, pci_subsys_102b_2538_102b_1047, 0}; +#undef pci_ss_info_102b_1047 +#define pci_ss_info_102b_1047 pci_ss_info_102b_2538_102b_1047 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1087 = + {0x102b, 0x1087, pci_subsys_102b_2538_102b_1087, 0}; +#undef pci_ss_info_102b_1087 +#define pci_ss_info_102b_1087 pci_ss_info_102b_2538_102b_1087 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_2538 = + {0x102b, 0x2538, pci_subsys_102b_2538_102b_2538, 0}; +#undef pci_ss_info_102b_2538 +#define pci_ss_info_102b_2538 pci_ss_info_102b_2538_102b_2538 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_3007 = + {0x102b, 0x3007, pci_subsys_102b_2538_102b_3007, 0}; +#undef pci_ss_info_102b_3007 +#define pci_ss_info_102b_3007 pci_ss_info_102b_2538_102b_3007 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_00c0_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_00c0_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_102c_00c0_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_102c_00c0_4c53_1010 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_102c_00c0_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_102c_00c0_4c53_1020 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_102c_00c0_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_102c_00c0_4c53_1030 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_00c0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_00c0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_00c0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_00c0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +static const pciSubsystemInfo pci_ss_info_102c_00e5_1179_0001 = + {0x1179, 0x0001, pci_subsys_102c_00e5_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_102c_00e5_1179_0001 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_0c30_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_0c30_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_0c30_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_0c30_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_0c30_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_0c30_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_102c_0c30_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_102c_0c30_4c53_1080 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1033_0035 = + {0x1033, 0x0035, pci_subsys_1033_0035_1033_0035, 0}; +#undef pci_ss_info_1033_0035 +#define pci_ss_info_1033_0035 pci_ss_info_1033_0035_1033_0035 +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_14c2_0105 = + {0x14c2, 0x0105, pci_subsys_1033_0035_14c2_0105, 0}; +#undef pci_ss_info_14c2_0105 +#define pci_ss_info_14c2_0105 pci_ss_info_1033_0035_14c2_0105 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000a = + {0x1931, 0x000a, pci_subsys_1033_0035_1931_000a, 0}; +#undef pci_ss_info_1931_000a +#define pci_ss_info_1931_000a pci_ss_info_1033_0035_1931_000a +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000b = + {0x1931, 0x000b, pci_subsys_1033_0035_1931_000b, 0}; +#undef pci_ss_info_1931_000b +#define pci_ss_info_1931_000b pci_ss_info_1033_0035_1931_000b +static const pciSubsystemInfo pci_ss_info_1033_0035_807d_0035 = + {0x807d, 0x0035, pci_subsys_1033_0035_807d_0035, 0}; +#undef pci_ss_info_807d_0035 +#define pci_ss_info_807d_0035 pci_ss_info_1033_0035_807d_0035 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_14c2_0205 = + {0x14c2, 0x0205, pci_subsys_1033_00e0_14c2_0205, 0}; +#undef pci_ss_info_14c2_0205 +#define pci_ss_info_14c2_0205 pci_ss_info_1033_00e0_14c2_0205 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1033_00e0_807d_1043 = + {0x807d, 0x1043, pci_subsys_1033_00e0_807d_1043, 0}; +#undef pci_ss_info_807d_1043 +#define pci_ss_info_807d_1043 pci_ss_info_1033_00e0_807d_1043 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_0900_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_0900_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_0900_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_0900_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_0900_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_5513_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_5513_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_5513_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6300_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_6300_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_6300_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_6330_1039_6330 = + {0x1039, 0x6330, pci_subsys_1039_6330_1039_6330, 0}; +#undef pci_ss_info_1039_6330 +#define pci_ss_info_1039_6330 pci_ss_info_1039_6330_1039_6330 +static const pciSubsystemInfo pci_ss_info_1039_7001_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_7001_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_7001_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7001_1462_5470 = + {0x1462, 0x5470, pci_subsys_1039_7001_1462_5470, 0}; +#undef pci_ss_info_1462_5470 +#define pci_ss_info_1462_5470 pci_ss_info_1039_7001_1462_5470 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1301 = + {0x103c, 0x1301, pci_subsys_103c_1048_103c_1301, 0}; +#undef pci_ss_info_103c_1301 +#define pci_ss_info_103c_1301 pci_ss_info_103c_1048_103c_1301 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1704 = + {0x0675, 0x1704, pci_subsys_1043_0675_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1043_0675_0675_1704 +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1707 = + {0x0675, 0x1707, pci_subsys_1043_0675_0675_1707, 0}; +#undef pci_ss_info_0675_1707 +#define pci_ss_info_0675_1707 pci_ss_info_1043_0675_0675_1707 +static const pciSubsystemInfo pci_ss_info_1043_0675_10cf_105e = + {0x10cf, 0x105e, pci_subsys_1043_0675_10cf_105e, 0}; +#undef pci_ss_info_10cf_105e +#define pci_ss_info_10cf_105e pci_ss_info_1043_0675_10cf_105e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c032 = + {0x1044, 0xc032, pci_subsys_1044_a511_1044_c032, 0}; +#undef pci_ss_info_1044_c032 +#define pci_ss_info_1044_c032 pci_ss_info_1044_a511_1044_c032 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c035 = + {0x1044, 0xc035, pci_subsys_1044_a511_1044_c035, 0}; +#undef pci_ss_info_1044_c035 +#define pci_ss_info_1044_c035 pci_ss_info_1044_a511_1044_c035 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1048_8901_1048_0935 = + {0x1048, 0x0935, pci_subsys_1048_8901_1048_0935, 0}; +#undef pci_ss_info_1048_0935 +#define pci_ss_info_1048_0935 pci_ss_info_1048_8901_1048_0935 +#endif +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a34 = + {0x1048, 0x0a34, pci_subsys_104c_3d07_1048_0a34, 0}; +#undef pci_ss_info_1048_0a34 +#define pci_ss_info_1048_0a34 pci_ss_info_104c_3d07_1048_0a34 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a36 = + {0x1048, 0x0a36, pci_subsys_104c_3d07_1048_0a36, 0}; +#undef pci_ss_info_1048_0a36 +#define pci_ss_info_1048_0a36 pci_ss_info_104c_3d07_1048_0a36 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a43 = + {0x1048, 0x0a43, pci_subsys_104c_3d07_1048_0a43, 0}; +#undef pci_ss_info_1048_0a43 +#define pci_ss_info_1048_0a43 pci_ss_info_104c_3d07_1048_0a43 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a44 = + {0x1048, 0x0a44, pci_subsys_104c_3d07_1048_0a44, 0}; +#undef pci_ss_info_1048_0a44 +#define pci_ss_info_1048_0a44 pci_ss_info_104c_3d07_1048_0a44 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_000f = + {0x11bd, 0x000f, pci_subsys_104c_8020_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_104c_8020_11bd_000f +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8023_103c_088c = + {0x103c, 0x088c, pci_subsys_104c_8023_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_104c_8023_103c_088c +static const pciSubsystemInfo pci_ss_info_104c_8023_1043_808b = + {0x1043, 0x808b, pci_subsys_104c_8023_1043_808b, 0}; +#undef pci_ss_info_1043_808b +#define pci_ss_info_1043_808b pci_ss_info_104c_8023_1043_808b +static const pciSubsystemInfo pci_ss_info_104c_8025_1458_1000 = + {0x1458, 0x1000, pci_subsys_104c_8025_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_104c_8025_1458_1000 +static const pciSubsystemInfo pci_ss_info_104c_8026_1043_808d = + {0x1043, 0x808d, pci_subsys_104c_8026_1043_808d, 0}; +#undef pci_ss_info_1043_808d +#define pci_ss_info_1043_808d pci_ss_info_104c_8026_1043_808d +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_8029_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_8029_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_8029_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_8029_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_8029_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_8029_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_8029_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_802b_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_802b_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_802b_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_802b_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8031_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8031_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8031_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8031_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8032_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8032_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8032_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8032_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8033_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8033_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8033_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8033_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8034_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8034_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8034_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8034_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8035_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8035_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8035_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_8204_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_8204_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_8204_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_8204_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b00 = + {0x1186, 0x3b00, pci_subsys_104c_8400_1186_3b00, 0}; +#undef pci_ss_info_1186_3b00 +#define pci_ss_info_1186_3b00 pci_ss_info_104c_8400_1186_3b00 +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b01 = + {0x1186, 0x3b01, pci_subsys_104c_8400_1186_3b01, 0}; +#undef pci_ss_info_1186_3b01 +#define pci_ss_info_1186_3b01 pci_ss_info_104c_8400_1186_3b01 +static const pciSubsystemInfo pci_ss_info_104c_8400_16ab_8501 = + {0x16ab, 0x8501, pci_subsys_104c_8400_16ab_8501, 0}; +#undef pci_ss_info_16ab_8501 +#define pci_ss_info_16ab_8501 pci_ss_info_104c_8400_16ab_8501 +static const pciSubsystemInfo pci_ss_info_104c_9066_104c_9066 = + {0x104c, 0x9066, pci_subsys_104c_9066_104c_9066, 0}; +#undef pci_ss_info_104c_9066 +#define pci_ss_info_104c_9066 pci_ss_info_104c_9066_104c_9066 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b04 = + {0x1186, 0x3b04, pci_subsys_104c_9066_1186_3b04, 0}; +#undef pci_ss_info_1186_3b04 +#define pci_ss_info_1186_3b04 pci_ss_info_104c_9066_1186_3b04 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b05 = + {0x1186, 0x3b05, pci_subsys_104c_9066_1186_3b05, 0}; +#undef pci_ss_info_1186_3b05 +#define pci_ss_info_1186_3b05 pci_ss_info_104c_9066_1186_3b05 +static const pciSubsystemInfo pci_ss_info_104c_9066_13d1_aba0 = + {0x13d1, 0xaba0, pci_subsys_104c_9066_13d1_aba0, 0}; +#undef pci_ss_info_13d1_aba0 +#define pci_ss_info_13d1_aba0 pci_ss_info_104c_9066_13d1_aba0 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_5000 = + {0x175c, 0x5000, pci_subsys_104c_a106_175c_5000, 0}; +#undef pci_ss_info_175c_5000 +#define pci_ss_info_175c_5000 pci_ss_info_104c_a106_175c_5000 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_6400 = + {0x175c, 0x6400, pci_subsys_104c_a106_175c_6400, 0}; +#undef pci_ss_info_175c_6400 +#define pci_ss_info_175c_6400 pci_ss_info_104c_a106_175c_6400 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_8700 = + {0x175c, 0x8700, pci_subsys_104c_a106_175c_8700, 0}; +#undef pci_ss_info_175c_8700 +#define pci_ss_info_175c_8700 pci_ss_info_104c_a106_175c_8700 +static const pciSubsystemInfo pci_ss_info_104c_ac16_1014_0092 = + {0x1014, 0x0092, pci_subsys_104c_ac16_1014_0092, 0}; +#undef pci_ss_info_1014_0092 +#define pci_ss_info_1014_0092 pci_ss_info_104c_ac16_1014_0092 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_1014_0130 = + {0x1014, 0x0130, pci_subsys_104c_ac1b_1014_0130, 0}; +#undef pci_ss_info_1014_0130 +#define pci_ss_info_1014_0130 pci_ss_info_104c_ac1b_1014_0130 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_0e11_b121 = + {0x0e11, 0xb121, pci_subsys_104c_ac1c_0e11_b121, 0}; +#undef pci_ss_info_0e11_b121 +#define pci_ss_info_0e11_b121 pci_ss_info_104c_ac1c_0e11_b121 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_1028_0088 = + {0x1028, 0x0088, pci_subsys_104c_ac1c_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_104c_ac1c_1028_0088 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_ac44_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_ac44_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_ac44_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_ac44_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_ac44_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_ac44_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac47_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac47_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac47_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac47_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac4a_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac4a_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac4a_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac4a_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac51_0e11_004e = + {0x0e11, 0x004e, pci_subsys_104c_ac51_0e11_004e, 0}; +#undef pci_ss_info_0e11_004e +#define pci_ss_info_0e11_004e pci_ss_info_104c_ac51_0e11_004e +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_104c_ac51_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_104c_ac51_1028_00b1 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_012a = + {0x1028, 0x012a, pci_subsys_104c_ac51_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_104c_ac51_1028_012a +static const pciSubsystemInfo pci_ss_info_104c_ac51_1033_80cd = + {0x1033, 0x80cd, pci_subsys_104c_ac51_1033_80cd, 0}; +#undef pci_ss_info_1033_80cd +#define pci_ss_info_1033_80cd pci_ss_info_104c_ac51_1033_80cd +static const pciSubsystemInfo pci_ss_info_104c_ac51_1095_10cf = + {0x1095, 0x10cf, pci_subsys_104c_ac51_1095_10cf, 0}; +#undef pci_ss_info_1095_10cf +#define pci_ss_info_1095_10cf pci_ss_info_104c_ac51_1095_10cf +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0528 = + {0x1014, 0x0528, pci_subsys_104c_ac56_1014_0528, 0}; +#undef pci_ss_info_1014_0528 +#define pci_ss_info_1014_0528 pci_ss_info_104c_ac56_1014_0528 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_5100 = + {0x175c, 0x5100, pci_subsys_104c_ac60_175c_5100, 0}; +#undef pci_ss_info_175c_5100 +#define pci_ss_info_175c_5100 pci_ss_info_104c_ac60_175c_5100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6100 = + {0x175c, 0x6100, pci_subsys_104c_ac60_175c_6100, 0}; +#undef pci_ss_info_175c_6100 +#define pci_ss_info_175c_6100 pci_ss_info_104c_ac60_175c_6100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6200 = + {0x175c, 0x6200, pci_subsys_104c_ac60_175c_6200, 0}; +#undef pci_ss_info_175c_6200 +#define pci_ss_info_175c_6200 pci_ss_info_104c_ac60_175c_6200 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_8800 = + {0x175c, 0x8800, pci_subsys_104c_ac60_175c_8800, 0}; +#undef pci_ss_info_175c_8800 +#define pci_ss_info_175c_8800 pci_ss_info_104c_ac60_175c_8800 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1702 = + {0x1043, 0x1702, pci_subsys_1050_6692_1043_1702, 0}; +#undef pci_ss_info_1043_1702 +#define pci_ss_info_1043_1702 pci_ss_info_1050_6692_1043_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1703 = + {0x1043, 0x1703, pci_subsys_1050_6692_1043_1703, 0}; +#undef pci_ss_info_1043_1703 +#define pci_ss_info_1043_1703 pci_ss_info_1050_6692_1043_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1707 = + {0x1043, 0x1707, pci_subsys_1050_6692_1043_1707, 0}; +#undef pci_ss_info_1043_1707 +#define pci_ss_info_1043_1707 pci_ss_info_1050_6692_1043_1707 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1702 = + {0x144f, 0x1702, pci_subsys_1050_6692_144f_1702, 0}; +#undef pci_ss_info_144f_1702 +#define pci_ss_info_144f_1702 pci_ss_info_1050_6692_144f_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1703 = + {0x144f, 0x1703, pci_subsys_1050_6692_144f_1703, 0}; +#undef pci_ss_info_144f_1703 +#define pci_ss_info_144f_1703 pci_ss_info_1050_6692_144f_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1707 = + {0x144f, 0x1707, pci_subsys_1050_6692_144f_1707, 0}; +#undef pci_ss_info_144f_1707 +#define pci_ss_info_144f_1707 pci_ss_info_1050_6692_144f_1707 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0101 = + {0x14fb, 0x0101, pci_subsys_1057_1801_14fb_0101, 0}; +#undef pci_ss_info_14fb_0101 +#define pci_ss_info_14fb_0101 pci_ss_info_1057_1801_14fb_0101 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0102 = + {0x14fb, 0x0102, pci_subsys_1057_1801_14fb_0102, 0}; +#undef pci_ss_info_14fb_0102 +#define pci_ss_info_14fb_0102 pci_ss_info_1057_1801_14fb_0102 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0202 = + {0x14fb, 0x0202, pci_subsys_1057_1801_14fb_0202, 0}; +#undef pci_ss_info_14fb_0202 +#define pci_ss_info_14fb_0202 pci_ss_info_1057_1801_14fb_0202 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0611 = + {0x14fb, 0x0611, pci_subsys_1057_1801_14fb_0611, 0}; +#undef pci_ss_info_14fb_0611 +#define pci_ss_info_14fb_0611 pci_ss_info_1057_1801_14fb_0611 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0612 = + {0x14fb, 0x0612, pci_subsys_1057_1801_14fb_0612, 0}; +#undef pci_ss_info_14fb_0612 +#define pci_ss_info_14fb_0612 pci_ss_info_1057_1801_14fb_0612 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0613 = + {0x14fb, 0x0613, pci_subsys_1057_1801_14fb_0613, 0}; +#undef pci_ss_info_14fb_0613 +#define pci_ss_info_14fb_0613 pci_ss_info_1057_1801_14fb_0613 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0614 = + {0x14fb, 0x0614, pci_subsys_1057_1801_14fb_0614, 0}; +#undef pci_ss_info_14fb_0614 +#define pci_ss_info_14fb_0614 pci_ss_info_1057_1801_14fb_0614 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0621 = + {0x14fb, 0x0621, pci_subsys_1057_1801_14fb_0621, 0}; +#undef pci_ss_info_14fb_0621 +#define pci_ss_info_14fb_0621 pci_ss_info_1057_1801_14fb_0621 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0622 = + {0x14fb, 0x0622, pci_subsys_1057_1801_14fb_0622, 0}; +#undef pci_ss_info_14fb_0622 +#define pci_ss_info_14fb_0622 pci_ss_info_1057_1801_14fb_0622 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0810 = + {0x14fb, 0x0810, pci_subsys_1057_1801_14fb_0810, 0}; +#undef pci_ss_info_14fb_0810 +#define pci_ss_info_14fb_0810 pci_ss_info_1057_1801_14fb_0810 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4200 = + {0x175c, 0x4200, pci_subsys_1057_1801_175c_4200, 0}; +#undef pci_ss_info_175c_4200 +#define pci_ss_info_175c_4200 pci_ss_info_1057_1801_175c_4200 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4300 = + {0x175c, 0x4300, pci_subsys_1057_1801_175c_4300, 0}; +#undef pci_ss_info_175c_4300 +#define pci_ss_info_175c_4300 pci_ss_info_1057_1801_175c_4300 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4400 = + {0x175c, 0x4400, pci_subsys_1057_1801_175c_4400, 0}; +#undef pci_ss_info_175c_4400 +#define pci_ss_info_175c_4400 pci_ss_info_1057_1801_175c_4400 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0010 = + {0xecc0, 0x0010, pci_subsys_1057_1801_ecc0_0010, 0}; +#undef pci_ss_info_ecc0_0010 +#define pci_ss_info_ecc0_0010 pci_ss_info_1057_1801_ecc0_0010 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0020 = + {0xecc0, 0x0020, pci_subsys_1057_1801_ecc0_0020, 0}; +#undef pci_ss_info_ecc0_0020 +#define pci_ss_info_ecc0_0020 pci_ss_info_1057_1801_ecc0_0020 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0031 = + {0xecc0, 0x0031, pci_subsys_1057_1801_ecc0_0031, 0}; +#undef pci_ss_info_ecc0_0031 +#define pci_ss_info_ecc0_0031 pci_ss_info_1057_1801_ecc0_0031 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0040 = + {0xecc0, 0x0040, pci_subsys_1057_1801_ecc0_0040, 0}; +#undef pci_ss_info_ecc0_0040 +#define pci_ss_info_ecc0_0040 pci_ss_info_1057_1801_ecc0_0040 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0041 = + {0xecc0, 0x0041, pci_subsys_1057_1801_ecc0_0041, 0}; +#undef pci_ss_info_ecc0_0041 +#define pci_ss_info_ecc0_0041 pci_ss_info_1057_1801_ecc0_0041 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_1801_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_1801_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_1801_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_1801_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_1801_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_1801_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_1801_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_1801_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_1801_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_1801_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_3410_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_3410_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_3410_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_3410_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0060 = + {0xecc0, 0x0060, pci_subsys_1057_3410_ecc0_0060, 0}; +#undef pci_ss_info_ecc0_0060 +#define pci_ss_info_ecc0_0060 pci_ss_info_1057_3410_ecc0_0060 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_3410_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_3410_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_3410_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_3410_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_3410_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_3410_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0080 = + {0xecc0, 0x0080, pci_subsys_1057_3410_ecc0_0080, 0}; +#undef pci_ss_info_ecc0_0080 +#define pci_ss_info_ecc0_0080 pci_ss_info_1057_3410_ecc0_0080 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0081 = + {0xecc0, 0x0081, pci_subsys_1057_3410_ecc0_0081, 0}; +#undef pci_ss_info_ecc0_0081 +#define pci_ss_info_ecc0_0081 pci_ss_info_1057_3410_ecc0_0081 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0090 = + {0xecc0, 0x0090, pci_subsys_1057_3410_ecc0_0090, 0}; +#undef pci_ss_info_ecc0_0090 +#define pci_ss_info_ecc0_0090 pci_ss_info_1057_3410_ecc0_0090 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00a0 = + {0xecc0, 0x00a0, pci_subsys_1057_3410_ecc0_00a0, 0}; +#undef pci_ss_info_ecc0_00a0 +#define pci_ss_info_ecc0_00a0 pci_ss_info_1057_3410_ecc0_00a0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00b0 = + {0xecc0, 0x00b0, pci_subsys_1057_3410_ecc0_00b0, 0}; +#undef pci_ss_info_ecc0_00b0 +#define pci_ss_info_ecc0_00b0 pci_ss_info_1057_3410_ecc0_00b0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0100 = + {0xecc0, 0x0100, pci_subsys_1057_3410_ecc0_0100, 0}; +#undef pci_ss_info_ecc0_0100 +#define pci_ss_info_ecc0_0100 pci_ss_info_1057_3410_ecc0_0100 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +#endif +static const pciSubsystemInfo pci_ss_info_105a_3319_8086_3427 = + {0x8086, 0x3427, pci_subsys_105a_3319_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_105a_3319_8086_3427 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_3373_1043_80f5 = + {0x1043, 0x80f5, pci_subsys_105a_3373_1043_80f5, 0}; +#undef pci_ss_info_1043_80f5 +#define pci_ss_info_1043_80f5 pci_ss_info_105a_3373_1043_80f5 +static const pciSubsystemInfo pci_ss_info_105a_3373_1462_702e = + {0x1462, 0x702e, pci_subsys_105a_3373_1462_702e, 0}; +#undef pci_ss_info_1462_702e +#define pci_ss_info_1462_702e pci_ss_info_105a_3373_1462_702e +static const pciSubsystemInfo pci_ss_info_105a_3376_1043_809e = + {0x1043, 0x809e, pci_subsys_105a_3376_1043_809e, 0}; +#undef pci_ss_info_1043_809e +#define pci_ss_info_1043_809e pci_ss_info_105a_3376_1043_809e +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_4d69_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d69_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d69_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_1043_807e = + {0x1043, 0x807e, pci_subsys_105a_5275_1043_807e, 0}; +#undef pci_ss_info_1043_807e +#define pci_ss_info_1043_807e pci_ss_info_105a_5275_1043_807e +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_1275 = + {0x105a, 0x1275, pci_subsys_105a_5275_105a_1275, 0}; +#undef pci_ss_info_105a_1275 +#define pci_ss_info_105a_1275 pci_ss_info_105a_5275_105a_1275 +static const pciSubsystemInfo pci_ss_info_105a_5275_1458_b001 = + {0x1458, 0xb001, pci_subsys_105a_5275_1458_b001, 0}; +#undef pci_ss_info_1458_b001 +#define pci_ss_info_1458_b001 pci_ss_info_105a_5275_1458_b001 +static const pciSubsystemInfo pci_ss_info_105a_6268_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_6268_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_6268_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_5348_105d_0037 = + {0x105d, 0x0037, pci_subsys_105d_5348_105d_0037, 0}; +#undef pci_ss_info_105d_0037 +#define pci_ss_info_105d_0037 pci_ss_info_105d_5348_105d_0037 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0050 = + {0x1069, 0x0050, pci_subsys_1069_0050_1069_0050, 0}; +#undef pci_ss_info_1069_0050 +#define pci_ss_info_1069_0050 pci_ss_info_1069_0050_1069_0050 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0052 = + {0x1069, 0x0052, pci_subsys_1069_0050_1069_0052, 0}; +#undef pci_ss_info_1069_0052 +#define pci_ss_info_1069_0052 pci_ss_info_1069_0050_1069_0052 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0054 = + {0x1069, 0x0054, pci_subsys_1069_0050_1069_0054, 0}; +#undef pci_ss_info_1069_0054 +#define pci_ss_info_1069_0054 pci_ss_info_1069_0050_1069_0054 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0242 = + {0x1014, 0x0242, pci_subsys_1069_b166_1014_0242, 0}; +#undef pci_ss_info_1014_0242 +#define pci_ss_info_1014_0242 pci_ss_info_1069_b166_1014_0242 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0266 = + {0x1014, 0x0266, pci_subsys_1069_b166_1014_0266, 0}; +#undef pci_ss_info_1014_0266 +#define pci_ss_info_1014_0266 pci_ss_info_1069_b166_1014_0266 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0278 = + {0x1014, 0x0278, pci_subsys_1069_b166_1014_0278, 0}; +#undef pci_ss_info_1014_0278 +#define pci_ss_info_1014_0278 pci_ss_info_1069_b166_1014_0278 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d3 = + {0x1014, 0x02d3, pci_subsys_1069_b166_1014_02d3, 0}; +#undef pci_ss_info_1014_02d3 +#define pci_ss_info_1014_02d3 pci_ss_info_1069_b166_1014_02d3 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d4 = + {0x1014, 0x02d4, pci_subsys_1069_b166_1014_02d4, 0}; +#undef pci_ss_info_1014_02d4 +#define pci_ss_info_1014_02d4 pci_ss_info_1069_b166_1014_02d4 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0200 = + {0x1069, 0x0200, pci_subsys_1069_b166_1069_0200, 0}; +#undef pci_ss_info_1069_0200 +#define pci_ss_info_1069_0200 pci_ss_info_1069_b166_1069_0200 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0202 = + {0x1069, 0x0202, pci_subsys_1069_b166_1069_0202, 0}; +#undef pci_ss_info_1069_0202 +#define pci_ss_info_1069_0202 pci_ss_info_1069_b166_1069_0202 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0204 = + {0x1069, 0x0204, pci_subsys_1069_b166_1069_0204, 0}; +#undef pci_ss_info_1069_0204 +#define pci_ss_info_1069_0204 pci_ss_info_1069_b166_1069_0204 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0206 = + {0x1069, 0x0206, pci_subsys_1069_b166_1069_0206, 0}; +#undef pci_ss_info_1069_0206 +#define pci_ss_info_1069_0206 pci_ss_info_1069_b166_1069_0206 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0030 = + {0x1069, 0x0030, pci_subsys_1069_ba56_1069_0030, 0}; +#undef pci_ss_info_1069_0030 +#define pci_ss_info_1069_0030 pci_ss_info_1069_ba56_1069_0030 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0040 = + {0x1069, 0x0040, pci_subsys_1069_ba56_1069_0040, 0}; +#undef pci_ss_info_1069_0040 +#define pci_ss_info_1069_0040 pci_ss_info_1069_ba56_1069_0040 +static const pciSubsystemInfo pci_ss_info_1069_ba57_1069_0072 = + {0x1069, 0x0072, pci_subsys_1069_ba57_1069_0072, 0}; +#undef pci_ss_info_1069_0072 +#define pci_ss_info_1069_0072 pci_ss_info_1069_ba57_1069_0072 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_106b_0031_106b_5811 = + {0x106b, 0x5811, pci_subsys_106b_0031_106b_5811, 0}; +#undef pci_ss_info_106b_5811 +#define pci_ss_info_106b_5811 pci_ss_info_106b_0031_106b_5811 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +static const pciSubsystemInfo pci_ss_info_1077_2200_1077_0002 = + {0x1077, 0x0002, pci_subsys_1077_2200_1077_0002, 0}; +#undef pci_ss_info_1077_0002 +#define pci_ss_info_1077_0002 pci_ss_info_1077_2200_1077_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +static const pciSubsystemInfo pci_ss_info_1095_0680_1095_3680 = + {0x1095, 0x3680, pci_subsys_1095_0680_1095_3680, 0}; +#undef pci_ss_info_1095_3680 +#define pci_ss_info_1095_3680 pci_ss_info_1095_0680_1095_3680 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_3112 = + {0x1095, 0x3112, pci_subsys_1095_3112_1095_3112, 0}; +#undef pci_ss_info_1095_3112 +#define pci_ss_info_1095_3112 pci_ss_info_1095_3112_1095_3112 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_6112 = + {0x1095, 0x6112, pci_subsys_1095_3112_1095_6112, 0}; +#undef pci_ss_info_1095_6112 +#define pci_ss_info_1095_6112 pci_ss_info_1095_3112_1095_6112 +static const pciSubsystemInfo pci_ss_info_1095_3112_9005_0250 = + {0x9005, 0x0250, pci_subsys_1095_3112_9005_0250, 0}; +#undef pci_ss_info_9005_0250 +#define pci_ss_info_9005_0250 pci_ss_info_1095_3112_9005_0250 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_3114 = + {0x1095, 0x3114, pci_subsys_1095_3114_1095_3114, 0}; +#undef pci_ss_info_1095_3114 +#define pci_ss_info_1095_3114 pci_ss_info_1095_3114_1095_3114 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_6114 = + {0x1095, 0x6114, pci_subsys_1095_3114_1095_6114, 0}; +#undef pci_ss_info_1095_6114 +#define pci_ss_info_1095_6114 pci_ss_info_1095_3114_1095_6114 +static const pciSubsystemInfo pci_ss_info_1095_3124_1095_3124 = + {0x1095, 0x3124, pci_subsys_1095_3124_1095_3124, 0}; +#undef pci_ss_info_1095_3124 +#define pci_ss_info_1095_3124 pci_ss_info_1095_3124_1095_3124 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_3512 = + {0x1095, 0x3512, pci_subsys_1095_3512_1095_3512, 0}; +#undef pci_ss_info_1095_3512 +#define pci_ss_info_1095_3512 pci_ss_info_1095_3512_1095_3512 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_6512 = + {0x1095, 0x6512, pci_subsys_1095_3512_1095_6512, 0}; +#undef pci_ss_info_1095_6512 +#define pci_ss_info_1095_6512 pci_ss_info_1095_3512_1095_6512 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_036e_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_036e_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_036e_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_036e_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0003 = + {0x1461, 0x0003, pci_subsys_109e_036e_1461_0003, 0}; +#undef pci_ss_info_1461_0003 +#define pci_ss_info_1461_0003 pci_ss_info_109e_036e_1461_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_036e_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_036e_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_036e_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_036e_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_036e_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_036e_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_036e_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_036e_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_036e_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_0878_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_0878_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_0878_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_0878_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_0878_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_0878_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_0878_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_0878_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_0878_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_0878_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_0878_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_0878_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_0878_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10a9_0009_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_10a9_0009_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_10a9_0009_10a9_8002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_6540_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6540_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6540_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6541_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6541_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6541_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6542_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6542_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6542_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2862 = + {0x10b5, 0x2862, pci_subsys_10b5_9030_10b5_2862, 0}; +#undef pci_ss_info_10b5_2862 +#define pci_ss_info_10b5_2862 pci_ss_info_10b5_9030_10b5_2862 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2906 = + {0x10b5, 0x2906, pci_subsys_10b5_9030_10b5_2906, 0}; +#undef pci_ss_info_10b5_2906 +#define pci_ss_info_10b5_2906 pci_ss_info_10b5_9030_10b5_2906 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2940 = + {0x10b5, 0x2940, pci_subsys_10b5_9030_10b5_2940, 0}; +#undef pci_ss_info_10b5_2940 +#define pci_ss_info_10b5_2940 pci_ss_info_10b5_9030_10b5_2940 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2977 = + {0x10b5, 0x2977, pci_subsys_10b5_9030_10b5_2977, 0}; +#undef pci_ss_info_10b5_2977 +#define pci_ss_info_10b5_2977 pci_ss_info_10b5_9030_10b5_2977 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2978 = + {0x10b5, 0x2978, pci_subsys_10b5_9030_10b5_2978, 0}; +#undef pci_ss_info_10b5_2978 +#define pci_ss_info_10b5_2978 pci_ss_info_10b5_9030_10b5_2978 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3025 = + {0x10b5, 0x3025, pci_subsys_10b5_9030_10b5_3025, 0}; +#undef pci_ss_info_10b5_3025 +#define pci_ss_info_10b5_3025 pci_ss_info_10b5_9030_10b5_3025 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3068 = + {0x10b5, 0x3068, pci_subsys_10b5_9030_10b5_3068, 0}; +#undef pci_ss_info_10b5_3068 +#define pci_ss_info_10b5_3068 pci_ss_info_10b5_9030_10b5_3068 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3136 = + {0x1397, 0x3136, pci_subsys_10b5_9030_1397_3136, 0}; +#undef pci_ss_info_1397_3136 +#define pci_ss_info_1397_3136 pci_ss_info_10b5_9030_1397_3136 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3137 = + {0x1397, 0x3137, pci_subsys_10b5_9030_1397_3137, 0}; +#undef pci_ss_info_1397_3137 +#define pci_ss_info_1397_3137 pci_ss_info_10b5_9030_1397_3137 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1518_0200 = + {0x1518, 0x0200, pci_subsys_10b5_9030_1518_0200, 0}; +#undef pci_ss_info_1518_0200 +#define pci_ss_info_1518_0200 pci_ss_info_10b5_9030_1518_0200 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1067 = + {0x10b5, 0x1067, pci_subsys_10b5_9050_10b5_1067, 0}; +#undef pci_ss_info_10b5_1067 +#define pci_ss_info_10b5_1067 pci_ss_info_10b5_9050_10b5_1067 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1172 = + {0x10b5, 0x1172, pci_subsys_10b5_9050_10b5_1172, 0}; +#undef pci_ss_info_10b5_1172 +#define pci_ss_info_10b5_1172 pci_ss_info_10b5_9050_10b5_1172 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2221 = + {0x10b5, 0x2221, pci_subsys_10b5_9050_10b5_2221, 0}; +#undef pci_ss_info_10b5_2221 +#define pci_ss_info_10b5_2221 pci_ss_info_10b5_9050_10b5_2221 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2431 = + {0x10b5, 0x2431, pci_subsys_10b5_9050_10b5_2431, 0}; +#undef pci_ss_info_10b5_2431 +#define pci_ss_info_10b5_2431 pci_ss_info_10b5_9050_10b5_2431 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2905 = + {0x10b5, 0x2905, pci_subsys_10b5_9050_10b5_2905, 0}; +#undef pci_ss_info_10b5_2905 +#define pci_ss_info_10b5_2905 pci_ss_info_10b5_9050_10b5_2905 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1498_0362 = + {0x1498, 0x0362, pci_subsys_10b5_9050_1498_0362, 0}; +#undef pci_ss_info_1498_0362 +#define pci_ss_info_1498_0362 pci_ss_info_10b5_9050_1498_0362 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_2036 = + {0x5654, 0x2036, pci_subsys_10b5_9050_5654_2036, 0}; +#undef pci_ss_info_5654_2036 +#define pci_ss_info_5654_2036 pci_ss_info_10b5_9050_5654_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_3132 = + {0x5654, 0x3132, pci_subsys_10b5_9050_5654_3132, 0}; +#undef pci_ss_info_5654_3132 +#define pci_ss_info_5654_3132 pci_ss_info_10b5_9050_5654_3132 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2696 = + {0x10b5, 0x2696, pci_subsys_10b5_9054_10b5_2696, 0}; +#undef pci_ss_info_10b5_2696 +#define pci_ss_info_10b5_2696 pci_ss_info_10b5_9054_10b5_2696 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2717 = + {0x10b5, 0x2717, pci_subsys_10b5_9054_10b5_2717, 0}; +#undef pci_ss_info_10b5_2717 +#define pci_ss_info_10b5_2717 pci_ss_info_10b5_9054_10b5_2717 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2844 = + {0x10b5, 0x2844, pci_subsys_10b5_9054_10b5_2844, 0}; +#undef pci_ss_info_10b5_2844 +#define pci_ss_info_10b5_2844 pci_ss_info_10b5_9054_10b5_2844 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12c7_4001 = + {0x12c7, 0x4001, pci_subsys_10b5_9054_12c7_4001, 0}; +#undef pci_ss_info_12c7_4001 +#define pci_ss_info_12c7_4001 pci_ss_info_10b5_9054_12c7_4001 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9054_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9054_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0011 = + {0x16df, 0x0011, pci_subsys_10b5_9054_16df_0011, 0}; +#undef pci_ss_info_16df_0011 +#define pci_ss_info_16df_0011 pci_ss_info_10b5_9054_16df_0011 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0012 = + {0x16df, 0x0012, pci_subsys_10b5_9054_16df_0012, 0}; +#undef pci_ss_info_16df_0012 +#define pci_ss_info_16df_0012 pci_ss_info_10b5_9054_16df_0012 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0013 = + {0x16df, 0x0013, pci_subsys_10b5_9054_16df_0013, 0}; +#undef pci_ss_info_16df_0013 +#define pci_ss_info_16df_0013 pci_ss_info_10b5_9054_16df_0013 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0014 = + {0x16df, 0x0014, pci_subsys_10b5_9054_16df_0014, 0}; +#undef pci_ss_info_16df_0014 +#define pci_ss_info_16df_0014 pci_ss_info_10b5_9054_16df_0014 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0015 = + {0x16df, 0x0015, pci_subsys_10b5_9054_16df_0015, 0}; +#undef pci_ss_info_16df_0015 +#define pci_ss_info_16df_0015 pci_ss_info_10b5_9054_16df_0015 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0016 = + {0x16df, 0x0016, pci_subsys_10b5_9054_16df_0016, 0}; +#undef pci_ss_info_16df_0016 +#define pci_ss_info_16df_0016 pci_ss_info_10b5_9054_16df_0016 +static const pciSubsystemInfo pci_ss_info_10b5_9056_10b5_2979 = + {0x10b5, 0x2979, pci_subsys_10b5_9056_10b5_2979, 0}; +#undef pci_ss_info_10b5_2979 +#define pci_ss_info_10b5_2979 pci_ss_info_10b5_9056_10b5_2979 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10eb = + {0x103c, 0x10eb, pci_subsys_10b5_9080_103c_10eb, 0}; +#undef pci_ss_info_103c_10eb +#define pci_ss_info_103c_10eb pci_ss_info_10b5_9080_103c_10eb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10ec = + {0x103c, 0x10ec, pci_subsys_10b5_9080_103c_10ec, 0}; +#undef pci_ss_info_103c_10ec +#define pci_ss_info_103c_10ec pci_ss_info_10b5_9080_103c_10ec +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9080_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9080_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12df_4422 = + {0x12df, 0x4422, pci_subsys_10b5_9080_12df_4422, 0}; +#undef pci_ss_info_12df_4422 +#define pci_ss_info_12df_4422 pci_ss_info_10b5_9080_12df_4422 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_0013_10b7_2031 = + {0x10b7, 0x2031, pci_subsys_10b7_0013_10b7_2031, 0}; +#undef pci_ss_info_10b7_2031 +#define pci_ss_info_10b7_2031 pci_ss_info_10b7_0013_10b7_2031 +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_1700_1043_80eb = + {0x1043, 0x80eb, pci_subsys_10b7_1700_1043_80eb, 0}; +#undef pci_ss_info_1043_80eb +#define pci_ss_info_1043_80eb pci_ss_info_10b7_1700_1043_80eb +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0010 = + {0x10b7, 0x0010, pci_subsys_10b7_1700_10b7_0010, 0}; +#undef pci_ss_info_10b7_0010 +#define pci_ss_info_10b7_0010 pci_ss_info_10b7_1700_10b7_0010 +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0020 = + {0x10b7, 0x0020, pci_subsys_10b7_1700_10b7_0020, 0}; +#undef pci_ss_info_10b7_0020 +#define pci_ss_info_10b7_0020 pci_ss_info_10b7_1700_10b7_0020 +static const pciSubsystemInfo pci_ss_info_10b7_1700_147b_1407 = + {0x147b, 0x1407, pci_subsys_10b7_1700_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_10b7_1700_147b_1407 +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9200_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9200_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_00fe = + {0x1028, 0x00fe, pci_subsys_10b7_9200_1028_00fe, 0}; +#undef pci_ss_info_1028_00fe +#define pci_ss_info_1028_00fe pci_ss_info_10b7_9200_1028_00fe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_012a = + {0x1028, 0x012a, pci_subsys_10b7_9200_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_10b7_9200_1028_012a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10f1_2466 = + {0x10f1, 0x2466, pci_subsys_10b7_9200_10f1_2466, 0}; +#undef pci_ss_info_10f1_2466 +#define pci_ss_info_10f1_2466 pci_ss_info_10b7_9200_10f1_2466 +static const pciSubsystemInfo pci_ss_info_10b7_9201_1043_80ab = + {0x1043, 0x80ab, pci_subsys_10b7_9201_1043_80ab, 0}; +#undef pci_ss_info_1043_80ab +#define pci_ss_info_1043_80ab pci_ss_info_10b7_9201_1043_80ab +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_1014_053b = + {0x1014, 0x053b, pci_subsys_10b9_1533_1014_053b, 0}; +#undef pci_ss_info_1014_053b +#define pci_ss_info_1014_053b pci_ss_info_10b9_1533_1014_053b +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_050f = + {0x1014, 0x050f, pci_subsys_10b9_5229_1014_050f, 0}; +#undef pci_ss_info_1014_050f +#define pci_ss_info_1014_050f pci_ss_info_10b9_5229_1014_050f +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_053d = + {0x1014, 0x053d, pci_subsys_10b9_5229_1014_053d, 0}; +#undef pci_ss_info_1014_053d +#define pci_ss_info_1014_053d pci_ss_info_10b9_5229_1014_053d +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5229_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5229_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5229_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5237_1014_0540 = + {0x1014, 0x0540, pci_subsys_10b9_5237_1014_0540, 0}; +#undef pci_ss_info_1014_0540 +#define pci_ss_info_1014_0540 pci_ss_info_10b9_5237_1014_0540 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5237_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5237_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_104d_810f = + {0x104d, 0x810f, pci_subsys_10b9_5237_104d_810f, 0}; +#undef pci_ss_info_104d_810f +#define pci_ss_info_104d_810f pci_ss_info_10b9_5237_104d_810f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_053e = + {0x1014, 0x053e, pci_subsys_10b9_5451_1014_053e, 0}; +#undef pci_ss_info_1014_053e +#define pci_ss_info_1014_053e pci_ss_info_10b9_5451_1014_053e +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5451_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5451_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5451_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_10b9_5451 = + {0x10b9, 0x5451, pci_subsys_10b9_5451_10b9_5451, 0}; +#undef pci_ss_info_10b9_5451 +#define pci_ss_info_10b9_5451 pci_ss_info_10b9_5451_10b9_5451 +static const pciSubsystemInfo pci_ss_info_10b9_5457_1014_0535 = + {0x1014, 0x0535, pci_subsys_10b9_5457_1014_0535, 0}; +#undef pci_ss_info_1014_0535 +#define pci_ss_info_1014_0535 pci_ss_info_10b9_5457_1014_0535 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5457_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5457_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5457_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_0510 = + {0x1014, 0x0510, pci_subsys_10b9_7101_1014_0510, 0}; +#undef pci_ss_info_1014_0510 +#define pci_ss_info_1014_0510 pci_ss_info_10b9_7101_1014_0510 +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_053c = + {0x1014, 0x053c, pci_subsys_10b9_7101_1014_053c, 0}; +#undef pci_ss_info_1014_053c +#define pci_ss_info_1014_053c pci_ss_info_10b9_7101_1014_053c +#endif +static const pciSubsystemInfo pci_ss_info_10b9_7101_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_7101_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_7101_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_0005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_0005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_8005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_8005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c19 = + {0x1048, 0x0c19, pci_subsys_10de_0020_1048_0c19, 0}; +#undef pci_ss_info_1048_0c19 +#define pci_ss_info_1048_0c19 pci_ss_info_10de_0020_1048_0c19 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1c = + {0x1048, 0x0c1c, pci_subsys_10de_0020_1048_0c1c, 0}; +#undef pci_ss_info_1048_0c1c +#define pci_ss_info_1048_0c1c pci_ss_info_10de_0020_1048_0c1c +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_0028_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_0028_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c28 = + {0x1048, 0x0c28, pci_subsys_10de_0028_1048_0c28, 0}; +#undef pci_ss_info_1048_0c28 +#define pci_ss_info_1048_0c28 pci_ss_info_10de_0028_1048_0c28 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c29 = + {0x1048, 0x0c29, pci_subsys_10de_0028_1048_0c29, 0}; +#undef pci_ss_info_1048_0c29 +#define pci_ss_info_1048_0c29 pci_ss_info_10de_0028_1048_0c29 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2a = + {0x1048, 0x0c2a, pci_subsys_10de_0028_1048_0c2a, 0}; +#undef pci_ss_info_1048_0c2a +#define pci_ss_info_1048_0c2a pci_ss_info_10de_0028_1048_0c2a +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2b = + {0x1048, 0x0c2b, pci_subsys_10de_0028_1048_0c2b, 0}; +#undef pci_ss_info_1048_0c2b +#define pci_ss_info_1048_0c2b pci_ss_info_10de_0028_1048_0c2b +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c31 = + {0x1048, 0x0c31, pci_subsys_10de_0028_1048_0c31, 0}; +#undef pci_ss_info_1048_0c31 +#define pci_ss_info_1048_0c31 pci_ss_info_10de_0028_1048_0c31 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c32 = + {0x1048, 0x0c32, pci_subsys_10de_0028_1048_0c32, 0}; +#undef pci_ss_info_1048_0c32 +#define pci_ss_info_1048_0c32 pci_ss_info_10de_0028_1048_0c32 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c33 = + {0x1048, 0x0c33, pci_subsys_10de_0028_1048_0c33, 0}; +#undef pci_ss_info_1048_0c33 +#define pci_ss_info_1048_0c33 pci_ss_info_10de_0028_1048_0c33 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c34 = + {0x1048, 0x0c34, pci_subsys_10de_0028_1048_0c34, 0}; +#undef pci_ss_info_1048_0c34 +#define pci_ss_info_1048_0c34 pci_ss_info_10de_0028_1048_0c34 +static const pciSubsystemInfo pci_ss_info_10de_0028_107d_2134 = + {0x107d, 0x2134, pci_subsys_10de_0028_107d_2134, 0}; +#undef pci_ss_info_107d_2134 +#define pci_ss_info_107d_2134 pci_ss_info_10de_0028_107d_2134 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2e = + {0x1048, 0x0c2e, pci_subsys_10de_0029_1048_0c2e, 0}; +#undef pci_ss_info_1048_0c2e +#define pci_ss_info_1048_0c2e pci_ss_info_10de_0029_1048_0c2e +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2f = + {0x1048, 0x0c2f, pci_subsys_10de_0029_1048_0c2f, 0}; +#undef pci_ss_info_1048_0c2f +#define pci_ss_info_1048_0c2f pci_ss_info_10de_0029_1048_0c2f +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c30 = + {0x1048, 0x0c30, pci_subsys_10de_0029_1048_0c30, 0}; +#undef pci_ss_info_1048_0c30 +#define pci_ss_info_1048_0c30 pci_ss_info_10de_0029_1048_0c30 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c20 = + {0x1048, 0x0c20, pci_subsys_10de_002c_1048_0c20, 0}; +#undef pci_ss_info_1048_0c20 +#define pci_ss_info_1048_0c20 pci_ss_info_10de_002c_1048_0c20 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_002c_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_002c_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3b = + {0x1048, 0x0c3b, pci_subsys_10de_002d_1048_0c3b, 0}; +#undef pci_ss_info_1048_0c3b +#define pci_ss_info_1048_0c3b pci_ss_info_10de_002d_1048_0c3b +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_002d_1569_002d = + {0x1569, 0x002d, pci_subsys_10de_002d_1569_002d, 0}; +#undef pci_ss_info_1569_002d +#define pci_ss_info_1569_002d pci_ss_info_10de_002d_1569_002d +static const pciSubsystemInfo pci_ss_info_10de_0041_1043_817b = + {0x1043, 0x817b, pci_subsys_10de_0041_1043_817b, 0}; +#undef pci_ss_info_1043_817b +#define pci_ss_info_1043_817b pci_ss_info_10de_0041_1043_817b +static const pciSubsystemInfo pci_ss_info_10de_0050_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0050_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0050_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0050_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0050_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0050_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0050_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0050_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0050_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0052_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0052_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0052_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0052_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0052_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0052_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0052_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0052_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0052_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0053_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0053_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0053_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0053_1458_5002 = + {0x1458, 0x5002, pci_subsys_10de_0053_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_10de_0053_1458_5002 +static const pciSubsystemInfo pci_ss_info_10de_0053_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0053_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0053_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0054_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0054_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0054_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0055_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0055_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0055_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0057_1043_8141 = + {0x1043, 0x8141, pci_subsys_10de_0057_1043_8141, 0}; +#undef pci_ss_info_1043_8141 +#define pci_ss_info_1043_8141 pci_ss_info_10de_0057_1043_8141 +static const pciSubsystemInfo pci_ss_info_10de_0057_1458_e000 = + {0x1458, 0xe000, pci_subsys_10de_0057_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10de_0057_1458_e000 +static const pciSubsystemInfo pci_ss_info_10de_0057_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0057_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0057_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0059_1043_812a = + {0x1043, 0x812a, pci_subsys_10de_0059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_10de_0059_1043_812a +static const pciSubsystemInfo pci_ss_info_10de_005a_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005a_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005a_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005a_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005a_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005a_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005a_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005a_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005a_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005b_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005b_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005b_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005b_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005b_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005b_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005b_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005b_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005b_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005e_1458_5000 = + {0x1458, 0x5000, pci_subsys_10de_005e_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_10de_005e_1458_5000 +static const pciSubsystemInfo pci_ss_info_10de_005e_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005e_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005e_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0066_1043_80a7 = + {0x1043, 0x80a7, pci_subsys_10de_0066_1043_80a7, 0}; +#undef pci_ss_info_1043_80a7 +#define pci_ss_info_1043_80a7 pci_ss_info_10de_0066_1043_80a7 +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_006b_10de_006b = + {0x10de, 0x006b, pci_subsys_10de_006b_10de_006b, 0}; +#undef pci_ss_info_10de_006b +#define pci_ss_info_10de_006b pci_ss_info_10de_006b_10de_006b +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_00df_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00df_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00df_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e0_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e0_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e0_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e1_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e1_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e1_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e3_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e3_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e3_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e4_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e4_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e4_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e5_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e5_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e5_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e7_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e7_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e7_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e8_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e8_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e8_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00ea_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00ea_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00ea_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00f1_1043_81a6 = + {0x1043, 0x81a6, pci_subsys_10de_00f1_1043_81a6, 0}; +#undef pci_ss_info_1043_81a6 +#define pci_ss_info_1043_81a6 pci_ss_info_10de_00f1_1043_81a6 +static const pciSubsystemInfo pci_ss_info_10de_00f2_1682_211c = + {0x1682, 0x211c, pci_subsys_10de_00f2_1682_211c, 0}; +#undef pci_ss_info_1682_211c +#define pci_ss_info_1682_211c pci_ss_info_10de_00f2_1682_211c +static const pciSubsystemInfo pci_ss_info_10de_00f9_1682_2120 = + {0x1682, 0x2120, pci_subsys_10de_00f9_1682_2120, 0}; +#undef pci_ss_info_1682_2120 +#define pci_ss_info_1682_2120 pci_ss_info_10de_00f9_1682_2120 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c41 = + {0x1048, 0x0c41, pci_subsys_10de_0100_1048_0c41, 0}; +#undef pci_ss_info_1048_0c41 +#define pci_ss_info_1048_0c41 pci_ss_info_10de_0100_1048_0c41 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c43 = + {0x1048, 0x0c43, pci_subsys_10de_0100_1048_0c43, 0}; +#undef pci_ss_info_1048_0c43 +#define pci_ss_info_1048_0c43 pci_ss_info_10de_0100_1048_0c43 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c48 = + {0x1048, 0x0c48, pci_subsys_10de_0100_1048_0c48, 0}; +#undef pci_ss_info_1048_0c48 +#define pci_ss_info_1048_0c48 pci_ss_info_10de_0100_1048_0c48 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1048_0c42 = + {0x1048, 0x0c42, pci_subsys_10de_0101_1048_0c42, 0}; +#undef pci_ss_info_1048_0c42 +#define pci_ss_info_1048_0c42 pci_ss_info_10de_0101_1048_0c42 +static const pciSubsystemInfo pci_ss_info_10de_0101_107d_2822 = + {0x107d, 0x2822, pci_subsys_10de_0101_107d_2822, 0}; +#undef pci_ss_info_107d_2822 +#define pci_ss_info_107d_2822 pci_ss_info_10de_0101_107d_2822 +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c40 = + {0x1048, 0x0c40, pci_subsys_10de_0103_1048_0c40, 0}; +#undef pci_ss_info_1048_0c40 +#define pci_ss_info_1048_0c40 pci_ss_info_10de_0103_1048_0c40 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c44 = + {0x1048, 0x0c44, pci_subsys_10de_0103_1048_0c44, 0}; +#undef pci_ss_info_1048_0c44 +#define pci_ss_info_1048_0c44 pci_ss_info_10de_0103_1048_0c44 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c45 = + {0x1048, 0x0c45, pci_subsys_10de_0103_1048_0c45, 0}; +#undef pci_ss_info_1048_0c45 +#define pci_ss_info_1048_0c45 pci_ss_info_10de_0103_1048_0c45 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4a = + {0x1048, 0x0c4a, pci_subsys_10de_0103_1048_0c4a, 0}; +#undef pci_ss_info_1048_0c4a +#define pci_ss_info_1048_0c4a pci_ss_info_10de_0103_1048_0c4a +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4b = + {0x1048, 0x0c4b, pci_subsys_10de_0103_1048_0c4b, 0}; +#undef pci_ss_info_1048_0c4b +#define pci_ss_info_1048_0c4b pci_ss_info_10de_0103_1048_0c4b +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c60 = + {0x1048, 0x0c60, pci_subsys_10de_0110_1048_0c60, 0}; +#undef pci_ss_info_1048_0c60 +#define pci_ss_info_1048_0c60 pci_ss_info_10de_0110_1048_0c60 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c61 = + {0x1048, 0x0c61, pci_subsys_10de_0110_1048_0c61, 0}; +#undef pci_ss_info_1048_0c61 +#define pci_ss_info_1048_0c61 pci_ss_info_10de_0110_1048_0c61 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c63 = + {0x1048, 0x0c63, pci_subsys_10de_0110_1048_0c63, 0}; +#undef pci_ss_info_1048_0c63 +#define pci_ss_info_1048_0c63 pci_ss_info_10de_0110_1048_0c63 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c64 = + {0x1048, 0x0c64, pci_subsys_10de_0110_1048_0c64, 0}; +#undef pci_ss_info_1048_0c64 +#define pci_ss_info_1048_0c64 pci_ss_info_10de_0110_1048_0c64 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c65 = + {0x1048, 0x0c65, pci_subsys_10de_0110_1048_0c65, 0}; +#undef pci_ss_info_1048_0c65 +#define pci_ss_info_1048_0c65 pci_ss_info_10de_0110_1048_0c65 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c66 = + {0x1048, 0x0c66, pci_subsys_10de_0110_1048_0c66, 0}; +#undef pci_ss_info_1048_0c66 +#define pci_ss_info_1048_0c66 pci_ss_info_10de_0110_1048_0c66 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_0091 = + {0x10de, 0x0091, pci_subsys_10de_0110_10de_0091, 0}; +#undef pci_ss_info_10de_0091 +#define pci_ss_info_10de_0091 pci_ss_info_10de_0110_10de_0091 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_00a1 = + {0x10de, 0x00a1, pci_subsys_10de_0110_10de_00a1, 0}; +#undef pci_ss_info_10de_00a1 +#define pci_ss_info_10de_00a1 pci_ss_info_10de_0110_10de_00a1 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0141_1458_3124 = + {0x1458, 0x3124, pci_subsys_10de_0141_1458_3124, 0}; +#undef pci_ss_info_1458_3124 +#define pci_ss_info_1458_3124 pci_ss_info_10de_0141_1458_3124 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c50 = + {0x1048, 0x0c50, pci_subsys_10de_0150_1048_0c50, 0}; +#undef pci_ss_info_1048_0c50 +#define pci_ss_info_1048_0c50 pci_ss_info_10de_0150_1048_0c50 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c52 = + {0x1048, 0x0c52, pci_subsys_10de_0150_1048_0c52, 0}; +#undef pci_ss_info_1048_0c52 +#define pci_ss_info_1048_0c52 pci_ss_info_10de_0150_1048_0c52 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2842 = + {0x107d, 0x2842, pci_subsys_10de_0150_107d_2842, 0}; +#undef pci_ss_info_107d_2842 +#define pci_ss_info_107d_2842 pci_ss_info_10de_0150_107d_2842 +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0151_1462_5506 = + {0x1462, 0x5506, pci_subsys_10de_0151_1462_5506, 0}; +#undef pci_ss_info_1462_5506 +#define pci_ss_info_1462_5506 pci_ss_info_10de_0151_1462_5506 +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_10b0_0002 = + {0x10b0, 0x0002, pci_subsys_10de_0171_10b0_0002, 0}; +#undef pci_ss_info_10b0_0002 +#define pci_ss_info_10b0_0002 pci_ss_info_10de_0171_10b0_0002 +static const pciSubsystemInfo pci_ss_info_10de_0171_10de_0008 = + {0x10de, 0x0008, pci_subsys_10de_0171_10de_0008, 0}; +#undef pci_ss_info_10de_0008 +#define pci_ss_info_10de_0008 pci_ss_info_10de_0171_10de_0008 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8852 = + {0x1462, 0x8852, pci_subsys_10de_0171_1462_8852, 0}; +#undef pci_ss_info_1462_8852 +#define pci_ss_info_1462_8852 pci_ss_info_10de_0171_1462_8852 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0176_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_10de_0176_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_10de_0176_4c53_1090 +static const pciSubsystemInfo pci_ss_info_10de_0179_10de_0179 = + {0x10de, 0x0179, pci_subsys_10de_0179_10de_0179, 0}; +#undef pci_ss_info_10de_0179 +#define pci_ss_info_10de_0179 pci_ss_info_10de_0179_10de_0179 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_806f = + {0x1043, 0x806f, pci_subsys_10de_0181_1043_806f, 0}; +#undef pci_ss_info_1043_806f +#define pci_ss_info_1043_806f pci_ss_info_10de_0181_1043_806f +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8880 = + {0x1462, 0x8880, pci_subsys_10de_0181_1462_8880, 0}; +#undef pci_ss_info_1462_8880 +#define pci_ss_info_1462_8880 pci_ss_info_10de_0181_1462_8880 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8900 = + {0x1462, 0x8900, pci_subsys_10de_0181_1462_8900, 0}; +#undef pci_ss_info_1462_8900 +#define pci_ss_info_1462_8900 pci_ss_info_10de_0181_1462_8900 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_9350 = + {0x1462, 0x9350, pci_subsys_10de_0181_1462_9350, 0}; +#undef pci_ss_info_1462_9350 +#define pci_ss_info_1462_9350 pci_ss_info_10de_0181_1462_9350 +static const pciSubsystemInfo pci_ss_info_10de_0181_147b_8f0d = + {0x147b, 0x8f0d, pci_subsys_10de_0181_147b_8f0d, 0}; +#undef pci_ss_info_147b_8f0d +#define pci_ss_info_147b_8f0d pci_ss_info_10de_0181_147b_8f0d +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0200_1048_0c70 = + {0x1048, 0x0c70, pci_subsys_10de_0200_1048_0c70, 0}; +#undef pci_ss_info_1048_0c70 +#define pci_ss_info_1048_0c70 pci_ss_info_10de_0200_1048_0c70 +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0251_1043_8023 = + {0x1043, 0x8023, pci_subsys_10de_0251_1043_8023, 0}; +#undef pci_ss_info_1043_8023 +#define pci_ss_info_1043_8023 pci_ss_info_10de_0251_1043_8023 +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +static const pciSubsystemInfo pci_ss_info_10de_0314_1043_814a = + {0x1043, 0x814a, pci_subsys_10de_0314_1043_814a, 0}; +#undef pci_ss_info_1043_814a +#define pci_ss_info_1043_814a pci_ss_info_10de_0314_1043_814a +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9171 = + {0x1462, 0x9171, pci_subsys_10de_0322_1462_9171, 0}; +#undef pci_ss_info_1462_9171 +#define pci_ss_info_1462_9171 pci_ss_info_10de_0322_1462_9171 +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9360 = + {0x1462, 0x9360, pci_subsys_10de_0322_1462_9360, 0}; +#undef pci_ss_info_1462_9360 +#define pci_ss_info_1462_9360 pci_ss_info_10de_0322_1462_9360 +static const pciSubsystemInfo pci_ss_info_10de_0324_1028_0196 = + {0x1028, 0x0196, pci_subsys_10de_0324_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_10de_0324_1028_0196 +static const pciSubsystemInfo pci_ss_info_10de_0324_1071_8160 = + {0x1071, 0x8160, pci_subsys_10de_0324_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10de_0324_1071_8160 +static const pciSubsystemInfo pci_ss_info_10de_0331_1043_8145 = + {0x1043, 0x8145, pci_subsys_10de_0331_1043_8145, 0}; +#undef pci_ss_info_1043_8145 +#define pci_ss_info_1043_8145 pci_ss_info_10de_0331_1043_8145 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +static const pciSubsystemInfo pci_ss_info_10ec_8139_0357_000a = + {0x0357, 0x000a, pci_subsys_10ec_8139_0357_000a, 0}; +#undef pci_ss_info_0357_000a +#define pci_ss_info_0357_000a pci_ss_info_10ec_8139_0357_000a +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_005a = + {0x1025, 0x005a, pci_subsys_10ec_8139_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_10ec_8139_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_1043_8109 = + {0x1043, 0x8109, pci_subsys_10ec_8139_1043_8109, 0}; +#undef pci_ss_info_1043_8109 +#define pci_ss_info_1043_8109 pci_ss_info_10ec_8139_1043_8109 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1071_8160 = + {0x1071, 0x8160, pci_subsys_10ec_8139_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10ec_8139_1071_8160 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1113_ec01 = + {0x1113, 0xec01, pci_subsys_10ec_8139_1113_ec01, 0}; +#undef pci_ss_info_1113_ec01 +#define pci_ss_info_1113_ec01 pci_ss_info_10ec_8139_1113_ec01 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8139_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8139_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_14cb_0200 = + {0x14cb, 0x0200, pci_subsys_10ec_8139_14cb_0200, 0}; +#undef pci_ss_info_14cb_0200 +#define pci_ss_info_14cb_0200 pci_ss_info_10ec_8139_14cb_0200 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1799_5000 = + {0x1799, 0x5000, pci_subsys_10ec_8139_1799_5000, 0}; +#undef pci_ss_info_1799_5000 +#define pci_ss_info_1799_5000 pci_ss_info_10ec_8139_1799_5000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_9001_1695 = + {0x9001, 0x1695, pci_subsys_10ec_8139_9001_1695, 0}; +#undef pci_ss_info_9001_1695 +#define pci_ss_info_9001_1695 pci_ss_info_10ec_8139_9001_1695 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1259_c107 = + {0x1259, 0xc107, pci_subsys_10ec_8169_1259_c107, 0}; +#undef pci_ss_info_1259_c107 +#define pci_ss_info_1259_c107 pci_ss_info_10ec_8169_1259_c107 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +static const pciSubsystemInfo pci_ss_info_10ec_8169_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8169_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8169_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1462_702c = + {0x1462, 0x702c, pci_subsys_10ec_8169_1462_702c, 0}; +#undef pci_ss_info_1462_702c +#define pci_ss_info_1462_702c pci_ss_info_10ec_8169_1462_702c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8064 = + {0x1102, 0x8064, pci_subsys_1102_0002_1102_8064, 0}; +#undef pci_ss_info_1102_8064 +#define pci_ss_info_1102_8064 pci_ss_info_1102_0002_1102_8064 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8065 = + {0x1102, 0x8065, pci_subsys_1102_0002_1102_8065, 0}; +#undef pci_ss_info_1102_8065 +#define pci_ss_info_1102_8065 pci_ss_info_1102_0002_1102_8065 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8067 = + {0x1102, 0x8067, pci_subsys_1102_0002_1102_8067, 0}; +#undef pci_ss_info_1102_8067 +#define pci_ss_info_1102_8067 pci_ss_info_1102_0002_1102_8067 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0058 = + {0x1102, 0x0058, pci_subsys_1102_0004_1102_0058, 0}; +#undef pci_ss_info_1102_0058 +#define pci_ss_info_1102_0058 pci_ss_info_1102_0004_1102_0058 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_1007 = + {0x1102, 0x1007, pci_subsys_1102_0004_1102_1007, 0}; +#undef pci_ss_info_1102_1007 +#define pci_ss_info_1102_1007 pci_ss_info_1102_0004_1102_1007 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_2002 = + {0x1102, 0x2002, pci_subsys_1102_0004_1102_2002, 0}; +#undef pci_ss_info_1102_2002 +#define pci_ss_info_1102_2002 pci_ss_info_1102_0004_1102_2002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_0007 = + {0x1102, 0x0007, pci_subsys_1102_0007_1102_0007, 0}; +#undef pci_ss_info_1102_0007 +#define pci_ss_info_1102_0007 pci_ss_info_1102_0007_1102_0007 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_0007_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_0007_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_0007_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_0007_1102_1002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1006 = + {0x1102, 0x1006, pci_subsys_1102_0007_1102_1006, 0}; +#undef pci_ss_info_1102_1006 +#define pci_ss_info_1102_1006 pci_ss_info_1102_0007_1102_1006 +static const pciSubsystemInfo pci_ss_info_1102_0007_1462_1009 = + {0x1462, 0x1009, pci_subsys_1102_0007_1462_1009, 0}; +#undef pci_ss_info_1462_1009 +#define pci_ss_info_1462_1009 pci_ss_info_1102_0007_1462_1009 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_7005_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_7005_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_7005_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_7005_1102_1002 +#endif +static const pciSubsystemInfo pci_ss_info_1102_8938_1033_80e5 = + {0x1033, 0x80e5, pci_subsys_1102_8938_1033_80e5, 0}; +#undef pci_ss_info_1033_80e5 +#define pci_ss_info_1033_80e5 pci_ss_info_1102_8938_1033_80e5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_8938_1071_7150 = + {0x1071, 0x7150, pci_subsys_1102_8938_1071_7150, 0}; +#undef pci_ss_info_1071_7150 +#define pci_ss_info_1071_7150 pci_ss_info_1102_8938_1071_7150 +static const pciSubsystemInfo pci_ss_info_1102_8938_110a_5938 = + {0x110a, 0x5938, pci_subsys_1102_8938_110a_5938, 0}; +#undef pci_ss_info_110a_5938 +#define pci_ss_info_110a_5938 pci_ss_info_1102_8938_110a_5938 +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100c = + {0x13bd, 0x100c, pci_subsys_1102_8938_13bd_100c, 0}; +#undef pci_ss_info_13bd_100c +#define pci_ss_info_13bd_100c pci_ss_info_1102_8938_13bd_100c +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100d = + {0x13bd, 0x100d, pci_subsys_1102_8938_13bd_100d, 0}; +#undef pci_ss_info_13bd_100d +#define pci_ss_info_13bd_100d pci_ss_info_1102_8938_13bd_100d +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100e = + {0x13bd, 0x100e, pci_subsys_1102_8938_13bd_100e, 0}; +#undef pci_ss_info_13bd_100e +#define pci_ss_info_13bd_100e pci_ss_info_1102_8938_13bd_100e +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_f6f1 = + {0x13bd, 0xf6f1, pci_subsys_1102_8938_13bd_f6f1, 0}; +#undef pci_ss_info_13bd_f6f1 +#define pci_ss_info_13bd_f6f1 pci_ss_info_1102_8938_13bd_f6f1 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_0e70 = + {0x14ff, 0x0e70, pci_subsys_1102_8938_14ff_0e70, 0}; +#undef pci_ss_info_14ff_0e70 +#define pci_ss_info_14ff_0e70 pci_ss_info_1102_8938_14ff_0e70 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_c401 = + {0x14ff, 0xc401, pci_subsys_1102_8938_14ff_c401, 0}; +#undef pci_ss_info_14ff_c401 +#define pci_ss_info_14ff_c401 pci_ss_info_1102_8938_14ff_c401 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b400 = + {0x156d, 0xb400, pci_subsys_1102_8938_156d_b400, 0}; +#undef pci_ss_info_156d_b400 +#define pci_ss_info_156d_b400 pci_ss_info_1102_8938_156d_b400 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b550 = + {0x156d, 0xb550, pci_subsys_1102_8938_156d_b550, 0}; +#undef pci_ss_info_156d_b550 +#define pci_ss_info_156d_b550 pci_ss_info_1102_8938_156d_b550 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b560 = + {0x156d, 0xb560, pci_subsys_1102_8938_156d_b560, 0}; +#undef pci_ss_info_156d_b560 +#define pci_ss_info_156d_b560 pci_ss_info_1102_8938_156d_b560 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b700 = + {0x156d, 0xb700, pci_subsys_1102_8938_156d_b700, 0}; +#undef pci_ss_info_156d_b700 +#define pci_ss_info_156d_b700 pci_ss_info_1102_8938_156d_b700 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b795 = + {0x156d, 0xb795, pci_subsys_1102_8938_156d_b795, 0}; +#undef pci_ss_info_156d_b795 +#define pci_ss_info_156d_b795 pci_ss_info_1102_8938_156d_b795 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b797 = + {0x156d, 0xb797, pci_subsys_1102_8938_156d_b797, 0}; +#undef pci_ss_info_156d_b797 +#define pci_ss_info_156d_b797 pci_ss_info_1102_8938_156d_b797 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0003 = + {0x1103, 0x0003, pci_subsys_1103_0004_1103_0003, 0}; +#undef pci_ss_info_1103_0003 +#define pci_ss_info_1103_0003 pci_ss_info_1103_0004_1103_0003 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0004 = + {0x1103, 0x0004, pci_subsys_1103_0004_1103_0004, 0}; +#undef pci_ss_info_1103_0004 +#define pci_ss_info_1103_0004 pci_ss_info_1103_0004_1103_0004 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0006 = + {0x1103, 0x0006, pci_subsys_1103_0004_1103_0006, 0}; +#undef pci_ss_info_1103_0006 +#define pci_ss_info_1103_0006 pci_ss_info_1103_0004_1103_0006 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0007 = + {0x1103, 0x0007, pci_subsys_1103_0004_1103_0007, 0}; +#undef pci_ss_info_1103_0007 +#define pci_ss_info_1103_0007 pci_ss_info_1103_0004_1103_0007 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0008 = + {0x1103, 0x0008, pci_subsys_1103_0004_1103_0008, 0}; +#undef pci_ss_info_1103_0008 +#define pci_ss_info_1103_0008 pci_ss_info_1103_0004_1103_0008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1105_8475_1105_0001 = + {0x1105, 0x0001, pci_subsys_1105_8475_1105_0001, 0}; +#undef pci_ss_info_1105_0001 +#define pci_ss_info_1105_0001 pci_ss_info_1105_8475_1105_0001 +static const pciSubsystemInfo pci_ss_info_1105_8476_127d_0000 = + {0x127d, 0x0000, pci_subsys_1105_8476_127d_0000, 0}; +#undef pci_ss_info_127d_0000 +#define pci_ss_info_127d_0000 pci_ss_info_1105_8476_127d_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_0282_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_0282_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_0282_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_0305_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_0305_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_0305_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0571_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0571_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_0571_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_0571_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_0571_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_0571_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_0571_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_0571_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_0571_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_0571_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_0571_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_0571_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0571_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_0571_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_0571_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_0571_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_0571_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_0571_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_0571_1849_0571 = + {0x1849, 0x0571, pci_subsys_1106_0571_1849_0571, 0}; +#undef pci_ss_info_1849_0571 +#define pci_ss_info_1849_0571 pci_ss_info_1106_0571_1849_0571 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0605_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0605_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0605_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0686_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0686_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0686_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0686_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0691_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0691_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3038_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3038_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3038_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3038_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_8080 = + {0x1043, 0x8080, pci_subsys_1106_3038_1043_8080, 0}; +#undef pci_ss_info_1043_8080 +#define pci_ss_info_1043_8080 pci_ss_info_1106_3038_1043_8080 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3038_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3038_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3038_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3038_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3038_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3038_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3038_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3038_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3038_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3038_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3038_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3038_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3038_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3038_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3038_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3038_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3038_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3038_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3038_1849_3038 = + {0x1849, 0x3038, pci_subsys_1106_3038_1849_3038, 0}; +#undef pci_ss_info_1849_3038 +#define pci_ss_info_1849_3038 pci_ss_info_1106_3038_1849_3038 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3044_0574_086c = + {0x0574, 0x086c, pci_subsys_1106_3044_0574_086c, 0}; +#undef pci_ss_info_0574_086c +#define pci_ss_info_0574_086c pci_ss_info_1106_3044_0574_086c +#endif +static const pciSubsystemInfo pci_ss_info_1106_3044_1025_005a = + {0x1025, 0x005a, pci_subsys_1106_3044_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1106_3044_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3044_1043_808a = + {0x1043, 0x808a, pci_subsys_1106_3044_1043_808a, 0}; +#undef pci_ss_info_1043_808a +#define pci_ss_info_1043_808a pci_ss_info_1106_3044_1043_808a +static const pciSubsystemInfo pci_ss_info_1106_3044_1458_1000 = + {0x1458, 0x1000, pci_subsys_1106_3044_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_1106_3044_1458_1000 +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_702d = + {0x1462, 0x702d, pci_subsys_1106_3044_1462_702d, 0}; +#undef pci_ss_info_1462_702d +#define pci_ss_info_1462_702d pci_ss_info_1106_3044_1462_702d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_971d = + {0x1462, 0x971d, pci_subsys_1106_3044_1462_971d, 0}; +#undef pci_ss_info_1462_971d +#define pci_ss_info_1462_971d pci_ss_info_1106_3044_1462_971d +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3057_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3057_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3057_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3057_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_0097 = + {0x0e11, 0x0097, pci_subsys_1106_3058_0e11_0097, 0}; +#undef pci_ss_info_0e11_0097 +#define pci_ss_info_0e11_0097 pci_ss_info_1106_3058_0e11_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3058_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3058_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3058_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3058_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3058_1043_1106 = + {0x1043, 0x1106, pci_subsys_1106_3058_1043_1106, 0}; +#undef pci_ss_info_1043_1106 +#define pci_ss_info_1043_1106 pci_ss_info_1106_3058_1043_1106 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3300 = + {0x1462, 0x3300, pci_subsys_1106_3058_1462_3300, 0}; +#undef pci_ss_info_1462_3300 +#define pci_ss_info_1462_3300 pci_ss_info_1106_3058_1462_3300 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3059_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3059_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_8095 = + {0x1043, 0x8095, pci_subsys_1106_3059_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_1106_3059_1043_8095 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3059_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3059_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80b0 = + {0x1043, 0x80b0, pci_subsys_1106_3059_1043_80b0, 0}; +#undef pci_ss_info_1043_80b0 +#define pci_ss_info_1043_80b0 pci_ss_info_1106_3059_1043_80b0 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_812a = + {0x1043, 0x812a, pci_subsys_1106_3059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_1106_3059_1043_812a +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_3059 = + {0x1106, 0x3059, pci_subsys_1106_3059_1106_3059, 0}; +#undef pci_ss_info_1106_3059 +#define pci_ss_info_1106_3059 pci_ss_info_1106_3059_1106_3059 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4161 = + {0x1106, 0x4161, pci_subsys_1106_3059_1106_4161, 0}; +#undef pci_ss_info_1106_4161 +#define pci_ss_info_1106_4161 pci_ss_info_1106_3059_1106_4161 +static const pciSubsystemInfo pci_ss_info_1106_3059_1297_c160 = + {0x1297, 0xc160, pci_subsys_1106_3059_1297_c160, 0}; +#undef pci_ss_info_1297_c160 +#define pci_ss_info_1297_c160 pci_ss_info_1106_3059_1297_c160 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_0080 = + {0x1462, 0x0080, pci_subsys_1106_3059_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_1106_3059_1462_0080 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_3800 = + {0x1462, 0x3800, pci_subsys_1106_3059_1462_3800, 0}; +#undef pci_ss_info_1462_3800 +#define pci_ss_info_1462_3800 pci_ss_info_1106_3059_1462_3800 +static const pciSubsystemInfo pci_ss_info_1106_3059_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3059_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3059_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3059_1849_9761 = + {0x1849, 0x9761, pci_subsys_1106_3059_1849_9761, 0}; +#undef pci_ss_info_1849_9761 +#define pci_ss_info_1849_9761 pci_ss_info_1106_3059_1849_9761 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3059_4005_4710 = + {0x4005, 0x4710, pci_subsys_1106_3059_4005_4710, 0}; +#undef pci_ss_info_4005_4710 +#define pci_ss_info_4005_4710 pci_ss_info_1106_3059_4005_4710 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3059_a0a0_01b6 = + {0xa0a0, 0x01b6, pci_subsys_1106_3059_a0a0_01b6, 0}; +#undef pci_ss_info_a0a0_01b6 +#define pci_ss_info_a0a0_01b6 pci_ss_info_1106_3059_a0a0_01b6 +static const pciSubsystemInfo pci_ss_info_1106_3065_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3065_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3065_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3065_13b9_1421 = + {0x13b9, 0x1421, pci_subsys_1106_3065_13b9_1421, 0}; +#undef pci_ss_info_13b9_1421 +#define pci_ss_info_13b9_1421 pci_ss_info_1106_3065_13b9_1421 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_3005 = + {0x1695, 0x3005, pci_subsys_1106_3065_1695_3005, 0}; +#undef pci_ss_info_1695_3005 +#define pci_ss_info_1695_3005 pci_ss_info_1106_3065_1695_3005 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_300c = + {0x1695, 0x300c, pci_subsys_1106_3065_1695_300c, 0}; +#undef pci_ss_info_1695_300c +#define pci_ss_info_1695_300c pci_ss_info_1106_3065_1695_300c +static const pciSubsystemInfo pci_ss_info_1106_3065_1849_3065 = + {0x1849, 0x3065, pci_subsys_1106_3065_1849_3065, 0}; +#undef pci_ss_info_1849_3065 +#define pci_ss_info_1849_3065 pci_ss_info_1106_3065_1849_3065 +static const pciSubsystemInfo pci_ss_info_1106_3068_1462_309e = + {0x1462, 0x309e, pci_subsys_1106_3068_1462_309e, 0}; +#undef pci_ss_info_1462_309e +#define pci_ss_info_1462_309e pci_ss_info_1106_3068_1462_309e +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3099_1849_3099 = + {0x1849, 0x3099, pci_subsys_1106_3099_1849_3099, 0}; +#undef pci_ss_info_1849_3099 +#define pci_ss_info_1849_3099 pci_ss_info_1106_3099_1849_3099 +static const pciSubsystemInfo pci_ss_info_1106_3104_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3104_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3104_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3104_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3104_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3104_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3104_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3104_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3104_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3104_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3104_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3104_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3104_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3104_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3104_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3104_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3104_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3104_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3104_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3104_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3104_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3104_1849_3104 = + {0x1849, 0x3104, pci_subsys_1106_3104_1849_3104, 0}; +#undef pci_ss_info_1849_3104 +#define pci_ss_info_1849_3104 pci_ss_info_1106_3104_1849_3104 +static const pciSubsystemInfo pci_ss_info_1106_3106_1186_1403 = + {0x1186, 0x1403, pci_subsys_1106_3106_1186_1403, 0}; +#undef pci_ss_info_1186_1403 +#define pci_ss_info_1186_1403 pci_ss_info_1106_3106_1186_1403 +static const pciSubsystemInfo pci_ss_info_1106_3116_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3116_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3116_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3147_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3147_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3147_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3149_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3149_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3149_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3149_1458_b003 = + {0x1458, 0xb003, pci_subsys_1106_3149_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_1106_3149_1458_b003 +static const pciSubsystemInfo pci_ss_info_1106_3149_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3149_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3149_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3149_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3149_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1408 = + {0x147b, 0x1408, pci_subsys_1106_3149_147b_1408, 0}; +#undef pci_ss_info_147b_1408 +#define pci_ss_info_147b_1408 pci_ss_info_1106_3149_147b_1408 +static const pciSubsystemInfo pci_ss_info_1106_3149_1849_3149 = + {0x1849, 0x3149, pci_subsys_1106_3149_1849_3149, 0}; +#undef pci_ss_info_1849_3149 +#define pci_ss_info_1849_3149 pci_ss_info_1106_3149_1849_3149 +static const pciSubsystemInfo pci_ss_info_1106_3164_1462_7028 = + {0x1462, 0x7028, pci_subsys_1106_3164_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_1106_3164_1462_7028 +static const pciSubsystemInfo pci_ss_info_1106_3177_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3177_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3177_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3177_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3177_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3177_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3177_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3177_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3177_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3177_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3177_1849_3177 = + {0x1849, 0x3177, pci_subsys_1106_3177_1849_3177, 0}; +#undef pci_ss_info_1849_3177 +#define pci_ss_info_1849_3177 pci_ss_info_1106_3177_1849_3177 +static const pciSubsystemInfo pci_ss_info_1106_3188_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_3188_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_3188_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_3188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3188_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3189_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3189_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3189_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3189_1849_3189 = + {0x1849, 0x3189, pci_subsys_1106_3189_1849_3189, 0}; +#undef pci_ss_info_1849_3189 +#define pci_ss_info_1849_3189 pci_ss_info_1106_3189_1849_3189 +static const pciSubsystemInfo pci_ss_info_1106_3205_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3205_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3205_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3227_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3227_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3227_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3227_1106_3227 = + {0x1106, 0x3227, pci_subsys_1106_3227_1106_3227, 0}; +#undef pci_ss_info_1106_3227 +#define pci_ss_info_1106_3227 pci_ss_info_1106_3227_1106_3227 +static const pciSubsystemInfo pci_ss_info_1106_3227_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3227_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3227_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3227_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3227_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3227_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3227_1849_3227 = + {0x1849, 0x3227, pci_subsys_1106_3227_1849_3227, 0}; +#undef pci_ss_info_1849_3227 +#define pci_ss_info_1849_3227 pci_ss_info_1106_3227_1849_3227 +static const pciSubsystemInfo pci_ss_info_1106_7205_1458_d000 = + {0x1458, 0xd000, pci_subsys_1106_7205_1458_d000, 0}; +#undef pci_ss_info_1458_d000 +#define pci_ss_info_1458_d000 pci_ss_info_1106_7205_1458_d000 +static const pciSubsystemInfo pci_ss_info_1106_8598_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_8598_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_8598_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_b188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_b188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_b188_147b_1407 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_1113_2242 = + {0x1113, 0x2242, pci_subsys_1113_1216_1113_2242, 0}; +#undef pci_ss_info_1113_2242 +#define pci_ss_info_1113_2242 pci_ss_info_1113_1216_1113_2242 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_5402_1244_0f00 = + {0x1244, 0x0f00, pci_subsys_1131_5402_1244_0f00, 0}; +#undef pci_ss_info_1244_0f00 +#define pci_ss_info_1244_0f00 pci_ss_info_1131_5402_1244_0f00 +#endif +static const pciSubsystemInfo pci_ss_info_1131_7130_102b_48d0 = + {0x102b, 0x48d0, pci_subsys_1131_7130_102b_48d0, 0}; +#undef pci_ss_info_102b_48d0 +#define pci_ss_info_102b_48d0 pci_ss_info_1131_7130_102b_48d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7130_1048_226b = + {0x1048, 0x226b, pci_subsys_1131_7130_1048_226b, 0}; +#undef pci_ss_info_1048_226b +#define pci_ss_info_1048_226b pci_ss_info_1131_7130_1048_226b +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7130_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7130_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2005 = + {0x1131, 0x2005, pci_subsys_1131_7130_1131_2005, 0}; +#undef pci_ss_info_1131_2005 +#define pci_ss_info_1131_2005 pci_ss_info_1131_7130_1131_2005 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_050c = + {0x1461, 0x050c, pci_subsys_1131_7130_1461_050c, 0}; +#undef pci_ss_info_1461_050c +#define pci_ss_info_1461_050c pci_ss_info_1131_7130_1461_050c +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_10ff = + {0x1461, 0x10ff, pci_subsys_1131_7130_1461_10ff, 0}; +#undef pci_ss_info_1461_10ff +#define pci_ss_info_1461_10ff pci_ss_info_1131_7130_1461_10ff +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2108 = + {0x1461, 0x2108, pci_subsys_1131_7130_1461_2108, 0}; +#undef pci_ss_info_1461_2108 +#define pci_ss_info_1461_2108 pci_ss_info_1131_7130_1461_2108 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2115 = + {0x1461, 0x2115, pci_subsys_1131_7130_1461_2115, 0}; +#undef pci_ss_info_1461_2115 +#define pci_ss_info_1461_2115 pci_ss_info_1131_7130_1461_2115 +static const pciSubsystemInfo pci_ss_info_1131_7130_153b_1152 = + {0x153b, 0x1152, pci_subsys_1131_7130_153b_1152, 0}; +#undef pci_ss_info_153b_1152 +#define pci_ss_info_153b_1152 pci_ss_info_1131_7130_153b_1152 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7130_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7130_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7130_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7130_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7130_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_002b_11bd = + {0x002b, 0x11bd, pci_subsys_1131_7133_002b_11bd, 0}; +#undef pci_ss_info_002b_11bd +#define pci_ss_info_002b_11bd pci_ss_info_1131_7133_002b_11bd +static const pciSubsystemInfo pci_ss_info_1131_7133_1019_4cb5 = + {0x1019, 0x4cb5, pci_subsys_1131_7133_1019_4cb5, 0}; +#undef pci_ss_info_1019_4cb5 +#define pci_ss_info_1019_4cb5 pci_ss_info_1131_7133_1019_4cb5 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7133_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7133_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4843 = + {0x1043, 0x4843, pci_subsys_1131_7133_1043_4843, 0}; +#undef pci_ss_info_1043_4843 +#define pci_ss_info_1043_4843 pci_ss_info_1131_7133_1043_4843 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7133_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7133_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_f31f = + {0x1461, 0xf31f, pci_subsys_1131_7133_1461_f31f, 0}; +#undef pci_ss_info_1461_f31f +#define pci_ss_info_1461_f31f pci_ss_info_1131_7133_1461_f31f +static const pciSubsystemInfo pci_ss_info_1131_7133_1489_0214 = + {0x1489, 0x0214, pci_subsys_1131_7133_1489_0214, 0}; +#undef pci_ss_info_1489_0214 +#define pci_ss_info_1489_0214 pci_ss_info_1131_7133_1489_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1162 = + {0x153b, 0x1162, pci_subsys_1131_7133_153b_1162, 0}; +#undef pci_ss_info_153b_1162 +#define pci_ss_info_153b_1162 pci_ss_info_1131_7133_153b_1162 +static const pciSubsystemInfo pci_ss_info_1131_7133_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7133_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7133_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7133_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7133_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0212 = + {0x5168, 0x0212, pci_subsys_1131_7133_5168_0212, 0}; +#undef pci_ss_info_5168_0212 +#define pci_ss_info_5168_0212 pci_ss_info_1131_7133_5168_0212 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0214 = + {0x5168, 0x0214, pci_subsys_1131_7133_5168_0214, 0}; +#undef pci_ss_info_5168_0214 +#define pci_ss_info_5168_0214 pci_ss_info_1131_7133_5168_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0306 = + {0x5168, 0x0306, pci_subsys_1131_7133_5168_0306, 0}; +#undef pci_ss_info_5168_0306 +#define pci_ss_info_5168_0306 pci_ss_info_1131_7133_5168_0306 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0502 = + {0x5168, 0x0502, pci_subsys_1131_7133_5168_0502, 0}; +#undef pci_ss_info_5168_0502 +#define pci_ss_info_5168_0502 pci_ss_info_1131_7133_5168_0502 +static const pciSubsystemInfo pci_ss_info_1131_7134_1019_4cb4 = + {0x1019, 0x4cb4, pci_subsys_1131_7134_1019_4cb4, 0}; +#undef pci_ss_info_1019_4cb4 +#define pci_ss_info_1019_4cb4 pci_ss_info_1131_7134_1019_4cb4 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4840 = + {0x1043, 0x4840, pci_subsys_1131_7134_1043_4840, 0}; +#undef pci_ss_info_1043_4840 +#define pci_ss_info_1043_4840 pci_ss_info_1131_7134_1043_4840 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4842 = + {0x1043, 0x4842, pci_subsys_1131_7134_1043_4842, 0}; +#undef pci_ss_info_1043_4842 +#define pci_ss_info_1043_4842 pci_ss_info_1131_7134_1043_4842 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_4e85 = + {0x1131, 0x4e85, pci_subsys_1131_7134_1131_4e85, 0}; +#undef pci_ss_info_1131_4e85 +#define pci_ss_info_1131_4e85 pci_ss_info_1131_7134_1131_4e85 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_6752 = + {0x1131, 0x6752, pci_subsys_1131_7134_1131_6752, 0}; +#undef pci_ss_info_1131_6752 +#define pci_ss_info_1131_6752 pci_ss_info_1131_7134_1131_6752 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_7133 = + {0x1131, 0x7133, pci_subsys_1131_7134_1131_7133, 0}; +#undef pci_ss_info_1131_7133 +#define pci_ss_info_1131_7133 pci_ss_info_1131_7134_1131_7133 +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7134_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7134_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002d = + {0x11bd, 0x002d, pci_subsys_1131_7134_11bd_002d, 0}; +#undef pci_ss_info_11bd_002d +#define pci_ss_info_11bd_002d pci_ss_info_1131_7134_11bd_002d +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_2c00 = + {0x1461, 0x2c00, pci_subsys_1131_7134_1461_2c00, 0}; +#undef pci_ss_info_1461_2c00 +#define pci_ss_info_1461_2c00 pci_ss_info_1131_7134_1461_2c00 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_2c05 = + {0x1461, 0x2c05, pci_subsys_1131_7134_1461_2c05, 0}; +#undef pci_ss_info_1461_2c05 +#define pci_ss_info_1461_2c05 pci_ss_info_1131_7134_1461_2c05 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70a = + {0x1461, 0xa70a, pci_subsys_1131_7134_1461_a70a, 0}; +#undef pci_ss_info_1461_a70a +#define pci_ss_info_1461_a70a pci_ss_info_1131_7134_1461_a70a +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70b = + {0x1461, 0xa70b, pci_subsys_1131_7134_1461_a70b, 0}; +#undef pci_ss_info_1461_a70b +#define pci_ss_info_1461_a70b pci_ss_info_1131_7134_1461_a70b +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_d6ee = + {0x1461, 0xd6ee, pci_subsys_1131_7134_1461_d6ee, 0}; +#undef pci_ss_info_1461_d6ee +#define pci_ss_info_1461_d6ee pci_ss_info_1131_7134_1461_d6ee +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1142 = + {0x153b, 0x1142, pci_subsys_1131_7134_153b_1142, 0}; +#undef pci_ss_info_153b_1142 +#define pci_ss_info_153b_1142 pci_ss_info_1131_7134_153b_1142 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1143 = + {0x153b, 0x1143, pci_subsys_1131_7134_153b_1143, 0}; +#undef pci_ss_info_153b_1143 +#define pci_ss_info_153b_1143 pci_ss_info_1131_7134_153b_1143 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1158 = + {0x153b, 0x1158, pci_subsys_1131_7134_153b_1158, 0}; +#undef pci_ss_info_153b_1158 +#define pci_ss_info_153b_1158 pci_ss_info_1131_7134_153b_1158 +static const pciSubsystemInfo pci_ss_info_1131_7134_1540_9524 = + {0x1540, 0x9524, pci_subsys_1131_7134_1540_9524, 0}; +#undef pci_ss_info_1540_9524 +#define pci_ss_info_1540_9524 pci_ss_info_1131_7134_1540_9524 +static const pciSubsystemInfo pci_ss_info_1131_7134_16be_0003 = + {0x16be, 0x0003, pci_subsys_1131_7134_16be_0003, 0}; +#undef pci_ss_info_16be_0003 +#define pci_ss_info_16be_0003 pci_ss_info_1131_7134_16be_0003 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c200 = + {0x185b, 0xc200, pci_subsys_1131_7134_185b_c200, 0}; +#undef pci_ss_info_185b_c200 +#define pci_ss_info_185b_c200 pci_ss_info_1131_7134_185b_c200 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_a006 = + {0x1894, 0xa006, pci_subsys_1131_7134_1894_a006, 0}; +#undef pci_ss_info_1894_a006 +#define pci_ss_info_1894_a006 pci_ss_info_1131_7134_1894_a006 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_fe01 = + {0x1894, 0xfe01, pci_subsys_1131_7134_1894_fe01, 0}; +#undef pci_ss_info_1894_fe01 +#define pci_ss_info_1894_fe01 pci_ss_info_1131_7134_1894_fe01 +static const pciSubsystemInfo pci_ss_info_1131_7135_1421_0350 = + {0x1421, 0x0350, pci_subsys_1131_7135_1421_0350, 0}; +#undef pci_ss_info_1421_0350 +#define pci_ss_info_1421_0350 pci_ss_info_1131_7135_1421_0350 +static const pciSubsystemInfo pci_ss_info_1131_7135_1421_0370 = + {0x1421, 0x0370, pci_subsys_1131_7135_1421_0370, 0}; +#undef pci_ss_info_1421_0370 +#define pci_ss_info_1421_0370 pci_ss_info_1131_7135_1421_0370 +static const pciSubsystemInfo pci_ss_info_1131_7135_5168_0212 = + {0x5168, 0x0212, pci_subsys_1131_7135_5168_0212, 0}; +#undef pci_ss_info_5168_0212 +#define pci_ss_info_5168_0212 pci_ss_info_1131_7135_5168_0212 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_0000 = + {0x110a, 0x0000, pci_subsys_1131_7146_110a_0000, 0}; +#undef pci_ss_info_110a_0000 +#define pci_ss_info_110a_0000 pci_ss_info_1131_7146_110a_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_ffff = + {0x110a, 0xffff, pci_subsys_1131_7146_110a_ffff, 0}; +#undef pci_ss_info_110a_ffff +#define pci_ss_info_110a_ffff pci_ss_info_1131_7146_110a_ffff +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f56 = + {0x1131, 0x4f56, pci_subsys_1131_7146_1131_4f56, 0}; +#undef pci_ss_info_1131_4f56 +#define pci_ss_info_1131_4f56 pci_ss_info_1131_7146_1131_4f56 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f60 = + {0x1131, 0x4f60, pci_subsys_1131_7146_1131_4f60, 0}; +#undef pci_ss_info_1131_4f60 +#define pci_ss_info_1131_4f60 pci_ss_info_1131_7146_1131_4f60 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f61 = + {0x1131, 0x4f61, pci_subsys_1131_7146_1131_4f61, 0}; +#undef pci_ss_info_1131_4f61 +#define pci_ss_info_1131_4f61 pci_ss_info_1131_7146_1131_4f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_5f61 = + {0x1131, 0x5f61, pci_subsys_1131_7146_1131_5f61, 0}; +#undef pci_ss_info_1131_5f61 +#define pci_ss_info_1131_5f61 pci_ss_info_1131_7146_1131_5f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000f = + {0x11bd, 0x000f, pci_subsys_1131_7146_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_1131_7146_11bd_000f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_1131_7146_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_1131_7146_13c2_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0001 = + {0x13c2, 0x0001, pci_subsys_1131_7146_13c2_0001, 0}; +#undef pci_ss_info_13c2_0001 +#define pci_ss_info_13c2_0001 pci_ss_info_1131_7146_13c2_0001 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0002 = + {0x13c2, 0x0002, pci_subsys_1131_7146_13c2_0002, 0}; +#undef pci_ss_info_13c2_0002 +#define pci_ss_info_13c2_0002 pci_ss_info_1131_7146_13c2_0002 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0003 = + {0x13c2, 0x0003, pci_subsys_1131_7146_13c2_0003, 0}; +#undef pci_ss_info_13c2_0003 +#define pci_ss_info_13c2_0003 pci_ss_info_1131_7146_13c2_0003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0004 = + {0x13c2, 0x0004, pci_subsys_1131_7146_13c2_0004, 0}; +#undef pci_ss_info_13c2_0004 +#define pci_ss_info_13c2_0004 pci_ss_info_1131_7146_13c2_0004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0006 = + {0x13c2, 0x0006, pci_subsys_1131_7146_13c2_0006, 0}; +#undef pci_ss_info_13c2_0006 +#define pci_ss_info_13c2_0006 pci_ss_info_1131_7146_13c2_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0008 = + {0x13c2, 0x0008, pci_subsys_1131_7146_13c2_0008, 0}; +#undef pci_ss_info_13c2_0008 +#define pci_ss_info_13c2_0008 pci_ss_info_1131_7146_13c2_0008 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_000a = + {0x13c2, 0x000a, pci_subsys_1131_7146_13c2_000a, 0}; +#undef pci_ss_info_13c2_000a +#define pci_ss_info_13c2_000a pci_ss_info_1131_7146_13c2_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1003 = + {0x13c2, 0x1003, pci_subsys_1131_7146_13c2_1003, 0}; +#undef pci_ss_info_13c2_1003 +#define pci_ss_info_13c2_1003 pci_ss_info_1131_7146_13c2_1003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1004 = + {0x13c2, 0x1004, pci_subsys_1131_7146_13c2_1004, 0}; +#undef pci_ss_info_13c2_1004 +#define pci_ss_info_13c2_1004 pci_ss_info_1131_7146_13c2_1004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1005 = + {0x13c2, 0x1005, pci_subsys_1131_7146_13c2_1005, 0}; +#undef pci_ss_info_13c2_1005 +#define pci_ss_info_13c2_1005 pci_ss_info_1131_7146_13c2_1005 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100c = + {0x13c2, 0x100c, pci_subsys_1131_7146_13c2_100c, 0}; +#undef pci_ss_info_13c2_100c +#define pci_ss_info_13c2_100c pci_ss_info_1131_7146_13c2_100c +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100f = + {0x13c2, 0x100f, pci_subsys_1131_7146_13c2_100f, 0}; +#undef pci_ss_info_13c2_100f +#define pci_ss_info_13c2_100f pci_ss_info_1131_7146_13c2_100f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1011 = + {0x13c2, 0x1011, pci_subsys_1131_7146_13c2_1011, 0}; +#undef pci_ss_info_13c2_1011 +#define pci_ss_info_13c2_1011 pci_ss_info_1131_7146_13c2_1011 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1013 = + {0x13c2, 0x1013, pci_subsys_1131_7146_13c2_1013, 0}; +#undef pci_ss_info_13c2_1013 +#define pci_ss_info_13c2_1013 pci_ss_info_1131_7146_13c2_1013 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1102 = + {0x13c2, 0x1102, pci_subsys_1131_7146_13c2_1102, 0}; +#undef pci_ss_info_13c2_1102 +#define pci_ss_info_13c2_1102 pci_ss_info_1131_7146_13c2_1102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e010_110a_0021 = + {0x110a, 0x0021, pci_subsys_1133_e010_110a_0021, 0}; +#undef pci_ss_info_110a_0021 +#define pci_ss_info_110a_0021 pci_ss_info_1133_e010_110a_0021 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_1300 = + {0x1133, 0x1300, pci_subsys_1133_e013_1133_1300, 0}; +#undef pci_ss_info_1133_1300 +#define pci_ss_info_1133_1300 pci_ss_info_1133_e013_1133_1300 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_e013 = + {0x1133, 0xe013, pci_subsys_1133_e013_1133_e013, 0}; +#undef pci_ss_info_1133_e013 +#define pci_ss_info_1133_e013 pci_ss_info_1133_e013_1133_e013 +static const pciSubsystemInfo pci_ss_info_1133_e015_1133_e015 = + {0x1133, 0xe015, pci_subsys_1133_e015_1133_e015, 0}; +#undef pci_ss_info_1133_e015 +#define pci_ss_info_1133_e015 pci_ss_info_1133_e015_1133_e015 +static const pciSubsystemInfo pci_ss_info_1133_e017_1133_e017 = + {0x1133, 0xe017, pci_subsys_1133_e017_1133_e017, 0}; +#undef pci_ss_info_1133_e017 +#define pci_ss_info_1133_e017 pci_ss_info_1133_e017_1133_e017 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_1800 = + {0x1133, 0x1800, pci_subsys_1133_e018_1133_1800, 0}; +#undef pci_ss_info_1133_1800 +#define pci_ss_info_1133_1800 pci_ss_info_1133_e018_1133_1800 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_e018 = + {0x1133, 0xe018, pci_subsys_1133_e018_1133_e018, 0}; +#undef pci_ss_info_1133_e018 +#define pci_ss_info_1133_e018 pci_ss_info_1133_e018_1133_e018 +static const pciSubsystemInfo pci_ss_info_1133_e019_1133_e019 = + {0x1133, 0xe019, pci_subsys_1133_e019_1133_e019, 0}; +#undef pci_ss_info_1133_e019 +#define pci_ss_info_1133_e019 pci_ss_info_1133_e019_1133_e019 +static const pciSubsystemInfo pci_ss_info_1133_e01b_1133_e01b = + {0x1133, 0xe01b, pci_subsys_1133_e01b_1133_e01b, 0}; +#undef pci_ss_info_1133_e01b +#define pci_ss_info_1133_e01b pci_ss_info_1133_e01b_1133_e01b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c01 = + {0x1133, 0x1c01, pci_subsys_1133_e01c_1133_1c01, 0}; +#undef pci_ss_info_1133_1c01 +#define pci_ss_info_1133_1c01 pci_ss_info_1133_e01c_1133_1c01 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c02 = + {0x1133, 0x1c02, pci_subsys_1133_e01c_1133_1c02, 0}; +#undef pci_ss_info_1133_1c02 +#define pci_ss_info_1133_1c02 pci_ss_info_1133_e01c_1133_1c02 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c03 = + {0x1133, 0x1c03, pci_subsys_1133_e01c_1133_1c03, 0}; +#undef pci_ss_info_1133_1c03 +#define pci_ss_info_1133_1c03 pci_ss_info_1133_e01c_1133_1c03 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c04 = + {0x1133, 0x1c04, pci_subsys_1133_e01c_1133_1c04, 0}; +#undef pci_ss_info_1133_1c04 +#define pci_ss_info_1133_1c04 pci_ss_info_1133_e01c_1133_1c04 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c05 = + {0x1133, 0x1c05, pci_subsys_1133_e01c_1133_1c05, 0}; +#undef pci_ss_info_1133_1c05 +#define pci_ss_info_1133_1c05 pci_ss_info_1133_e01c_1133_1c05 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c06 = + {0x1133, 0x1c06, pci_subsys_1133_e01c_1133_1c06, 0}; +#undef pci_ss_info_1133_1c06 +#define pci_ss_info_1133_1c06 pci_ss_info_1133_e01c_1133_1c06 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c07 = + {0x1133, 0x1c07, pci_subsys_1133_e01c_1133_1c07, 0}; +#undef pci_ss_info_1133_1c07 +#define pci_ss_info_1133_1c07 pci_ss_info_1133_e01c_1133_1c07 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c08 = + {0x1133, 0x1c08, pci_subsys_1133_e01c_1133_1c08, 0}; +#undef pci_ss_info_1133_1c08 +#define pci_ss_info_1133_1c08 pci_ss_info_1133_e01c_1133_1c08 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c09 = + {0x1133, 0x1c09, pci_subsys_1133_e01c_1133_1c09, 0}; +#undef pci_ss_info_1133_1c09 +#define pci_ss_info_1133_1c09 pci_ss_info_1133_e01c_1133_1c09 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0a = + {0x1133, 0x1c0a, pci_subsys_1133_e01c_1133_1c0a, 0}; +#undef pci_ss_info_1133_1c0a +#define pci_ss_info_1133_1c0a pci_ss_info_1133_e01c_1133_1c0a +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0b = + {0x1133, 0x1c0b, pci_subsys_1133_e01c_1133_1c0b, 0}; +#undef pci_ss_info_1133_1c0b +#define pci_ss_info_1133_1c0b pci_ss_info_1133_e01c_1133_1c0b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0c = + {0x1133, 0x1c0c, pci_subsys_1133_e01c_1133_1c0c, 0}; +#undef pci_ss_info_1133_1c0c +#define pci_ss_info_1133_1c0c pci_ss_info_1133_e01c_1133_1c0c +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_2400 = + {0x1133, 0x2400, pci_subsys_1133_e024_1133_2400, 0}; +#undef pci_ss_info_1133_2400 +#define pci_ss_info_1133_2400 pci_ss_info_1133_e024_1133_2400 +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_e024 = + {0x1133, 0xe024, pci_subsys_1133_e024_1133_e024, 0}; +#undef pci_ss_info_1133_e024 +#define pci_ss_info_1133_e024 pci_ss_info_1133_e024_1133_e024 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_2800 = + {0x1133, 0x2800, pci_subsys_1133_e028_1133_2800, 0}; +#undef pci_ss_info_1133_2800 +#define pci_ss_info_1133_2800 pci_ss_info_1133_e028_1133_2800 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_e028 = + {0x1133, 0xe028, pci_subsys_1133_e028_1133_e028, 0}; +#undef pci_ss_info_1133_e028 +#define pci_ss_info_1133_e028 pci_ss_info_1133_e028_1133_e028 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2971 = + {0x1259, 0x2971, pci_subsys_1148_4300_1259_2971, 0}; +#undef pci_ss_info_1259_2971 +#define pci_ss_info_1259_2971 pci_ss_info_1148_4300_1259_2971 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2973 = + {0x1259, 0x2973, pci_subsys_1148_4300_1259_2973, 0}; +#undef pci_ss_info_1259_2973 +#define pci_ss_info_1259_2973 pci_ss_info_1148_4300_1259_2973 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2974 = + {0x1259, 0x2974, pci_subsys_1148_4300_1259_2974, 0}; +#undef pci_ss_info_1259_2974 +#define pci_ss_info_1259_2974 pci_ss_info_1148_4300_1259_2974 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2976 = + {0x1259, 0x2976, pci_subsys_1148_4300_1259_2976, 0}; +#undef pci_ss_info_1259_2976 +#define pci_ss_info_1259_2976 pci_ss_info_1148_4300_1259_2976 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0121 = + {0x1148, 0x0121, pci_subsys_1148_4320_1148_0121, 0}; +#undef pci_ss_info_1148_0121 +#define pci_ss_info_1148_0121 pci_ss_info_1148_4320_1148_0121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0221 = + {0x1148, 0x0221, pci_subsys_1148_4320_1148_0221, 0}; +#undef pci_ss_info_1148_0221 +#define pci_ss_info_1148_0221 pci_ss_info_1148_4320_1148_0221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0321 = + {0x1148, 0x0321, pci_subsys_1148_4320_1148_0321, 0}; +#undef pci_ss_info_1148_0321 +#define pci_ss_info_1148_0321 pci_ss_info_1148_4320_1148_0321 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0421 = + {0x1148, 0x0421, pci_subsys_1148_4320_1148_0421, 0}; +#undef pci_ss_info_1148_0421 +#define pci_ss_info_1148_0421 pci_ss_info_1148_4320_1148_0421 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0621 = + {0x1148, 0x0621, pci_subsys_1148_4320_1148_0621, 0}; +#undef pci_ss_info_1148_0621 +#define pci_ss_info_1148_0621 pci_ss_info_1148_4320_1148_0621 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0721 = + {0x1148, 0x0721, pci_subsys_1148_4320_1148_0721, 0}; +#undef pci_ss_info_1148_0721 +#define pci_ss_info_1148_0721 pci_ss_info_1148_4320_1148_0721 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0821 = + {0x1148, 0x0821, pci_subsys_1148_4320_1148_0821, 0}; +#undef pci_ss_info_1148_0821 +#define pci_ss_info_1148_0821 pci_ss_info_1148_4320_1148_0821 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0921 = + {0x1148, 0x0921, pci_subsys_1148_4320_1148_0921, 0}; +#undef pci_ss_info_1148_0921 +#define pci_ss_info_1148_0921 pci_ss_info_1148_4320_1148_0921 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1121 = + {0x1148, 0x1121, pci_subsys_1148_4320_1148_1121, 0}; +#undef pci_ss_info_1148_1121 +#define pci_ss_info_1148_1121 pci_ss_info_1148_4320_1148_1121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1221 = + {0x1148, 0x1221, pci_subsys_1148_4320_1148_1221, 0}; +#undef pci_ss_info_1148_1221 +#define pci_ss_info_1148_1221 pci_ss_info_1148_4320_1148_1221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_3221 = + {0x1148, 0x3221, pci_subsys_1148_4320_1148_3221, 0}; +#undef pci_ss_info_1148_3221 +#define pci_ss_info_1148_3221 pci_ss_info_1148_4320_1148_3221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2100 = + {0x1148, 0x2100, pci_subsys_1148_9e00_1148_2100, 0}; +#undef pci_ss_info_1148_2100 +#define pci_ss_info_1148_2100 pci_ss_info_1148_9e00_1148_2100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_21d0 = + {0x1148, 0x21d0, pci_subsys_1148_9e00_1148_21d0, 0}; +#undef pci_ss_info_1148_21d0 +#define pci_ss_info_1148_21d0 pci_ss_info_1148_9e00_1148_21d0 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2200 = + {0x1148, 0x2200, pci_subsys_1148_9e00_1148_2200, 0}; +#undef pci_ss_info_1148_2200 +#define pci_ss_info_1148_2200 pci_ss_info_1148_9e00_1148_2200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8100 = + {0x1148, 0x8100, pci_subsys_1148_9e00_1148_8100, 0}; +#undef pci_ss_info_1148_8100 +#define pci_ss_info_1148_8100 pci_ss_info_1148_9e00_1148_8100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8200 = + {0x1148, 0x8200, pci_subsys_1148_9e00_1148_8200, 0}; +#undef pci_ss_info_1148_8200 +#define pci_ss_info_1148_8200 pci_ss_info_1148_9e00_1148_8200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9100 = + {0x1148, 0x9100, pci_subsys_1148_9e00_1148_9100, 0}; +#undef pci_ss_info_1148_9100 +#define pci_ss_info_1148_9100 pci_ss_info_1148_9e00_1148_9100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9200 = + {0x1148, 0x9200, pci_subsys_1148_9e00_1148_9200, 0}; +#undef pci_ss_info_1148_9200 +#define pci_ss_info_1148_9200 pci_ss_info_1148_9e00_1148_9200 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0003_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0003_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0201_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0201_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0201_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0203_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0203_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0203_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0212_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0212_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0212_4c53_1080 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_c134 = + {0x1028, 0xc134, pci_subsys_1166_0213_1028_c134, 0}; +#undef pci_ss_info_1028_c134 +#define pci_ss_info_1028_c134 pci_ss_info_1166_0213_1028_c134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0213_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0213_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0213_1734_1012 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0217_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0217_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0217_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0220_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0220_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0220_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0221_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0221_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0221_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0227_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0227_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0227_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0230_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0230_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0230_4c53_1080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0601_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0601_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0601_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_060a_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_060a_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_060a_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8013 = + {0x117c, 0x8013, pci_subsys_117c_0030_117c_8013, 0}; +#undef pci_ss_info_117c_8013 +#define pci_ss_info_117c_8013 pci_ss_info_117c_0030_117c_8013 +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8014 = + {0x117c, 0x8014, pci_subsys_117c_0030_117c_8014, 0}; +#undef pci_ss_info_117c_8014 +#define pci_ss_info_117c_8014 pci_ss_info_117c_0030_117c_8014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0476_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0476_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0476_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0476_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1987 = + {0x1043, 0x1987, pci_subsys_1180_0476_1043_1987, 0}; +#undef pci_ss_info_1043_1987 +#define pci_ss_info_1043_1987 pci_ss_info_1180_0476_1043_1987 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_14ef_0220 = + {0x14ef, 0x0220, pci_subsys_1180_0476_14ef_0220, 0}; +#undef pci_ss_info_14ef_0220 +#define pci_ss_info_14ef_0220 pci_ss_info_1180_0476_14ef_0220 +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0522_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0522_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0522_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +static const pciSubsystemInfo pci_ss_info_1180_0592_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0592_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0592_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0556 = + {0x1014, 0x0556, pci_subsys_1180_0822_1014_0556, 0}; +#undef pci_ss_info_1014_0556 +#define pci_ss_info_1014_0556 pci_ss_info_1180_0822_1014_0556 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0822_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0822_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_01a2 = + {0x1028, 0x01a2, pci_subsys_1180_0822_1028_01a2, 0}; +#undef pci_ss_info_1028_01a2 +#define pci_ss_info_1028_01a2 pci_ss_info_1180_0822_1028_01a2 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0822_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0822_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0822_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0852_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0852_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0852_1043_1967 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1303 = + {0x1186, 0x1303, pci_subsys_1186_1300_1186_1303, 0}; +#undef pci_ss_info_1186_1303 +#define pci_ss_info_1186_1303 pci_ss_info_1186_1300_1186_1303 +static const pciSubsystemInfo pci_ss_info_1186_4c00_1186_4c00 = + {0x1186, 0x4c00, pci_subsys_1186_4c00_1186_4c00, 0}; +#undef pci_ss_info_1186_4c00 +#define pci_ss_info_1186_4c00 pci_ss_info_1186_4c00_1186_4c00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_1faa_1385_4e00 = + {0x1385, 0x4e00, pci_subsys_11ab_1faa_1385_4e00, 0}; +#undef pci_ss_info_1385_4e00 +#define pci_ss_info_1385_4e00 pci_ss_info_11ab_1faa_1385_4e00 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_0f38 = + {0x1019, 0x0f38, pci_subsys_11ab_4320_1019_0f38, 0}; +#undef pci_ss_info_1019_0f38 +#define pci_ss_info_1019_0f38 pci_ss_info_11ab_4320_1019_0f38 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_8001 = + {0x1019, 0x8001, pci_subsys_11ab_4320_1019_8001, 0}; +#undef pci_ss_info_1019_8001 +#define pci_ss_info_1019_8001 pci_ss_info_11ab_4320_1019_8001 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_173c = + {0x1043, 0x173c, pci_subsys_11ab_4320_1043_173c, 0}; +#undef pci_ss_info_1043_173c +#define pci_ss_info_1043_173c pci_ss_info_11ab_4320_1043_173c +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_811a = + {0x1043, 0x811a, pci_subsys_11ab_4320_1043_811a, 0}; +#undef pci_ss_info_1043_811a +#define pci_ss_info_1043_811a pci_ss_info_11ab_4320_1043_811a +static const pciSubsystemInfo pci_ss_info_11ab_4320_105b_0c19 = + {0x105b, 0x0c19, pci_subsys_11ab_4320_105b_0c19, 0}; +#undef pci_ss_info_105b_0c19 +#define pci_ss_info_105b_0c19 pci_ss_info_11ab_4320_105b_0c19 +static const pciSubsystemInfo pci_ss_info_11ab_4320_10b8_b452 = + {0x10b8, 0xb452, pci_subsys_11ab_4320_10b8_b452, 0}; +#undef pci_ss_info_10b8_b452 +#define pci_ss_info_10b8_b452 pci_ss_info_11ab_4320_10b8_b452 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0121 = + {0x11ab, 0x0121, pci_subsys_11ab_4320_11ab_0121, 0}; +#undef pci_ss_info_11ab_0121 +#define pci_ss_info_11ab_0121 pci_ss_info_11ab_4320_11ab_0121 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0321 = + {0x11ab, 0x0321, pci_subsys_11ab_4320_11ab_0321, 0}; +#undef pci_ss_info_11ab_0321 +#define pci_ss_info_11ab_0321 pci_ss_info_11ab_4320_11ab_0321 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_1021 = + {0x11ab, 0x1021, pci_subsys_11ab_4320_11ab_1021, 0}; +#undef pci_ss_info_11ab_1021 +#define pci_ss_info_11ab_1021 pci_ss_info_11ab_4320_11ab_1021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4320_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4320_11ab_5021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_9521 = + {0x11ab, 0x9521, pci_subsys_11ab_4320_11ab_9521, 0}; +#undef pci_ss_info_11ab_9521 +#define pci_ss_info_11ab_9521 pci_ss_info_11ab_4320_11ab_9521 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4320_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4320_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4320_147b_1406 = + {0x147b, 0x1406, pci_subsys_11ab_4320_147b_1406, 0}; +#undef pci_ss_info_147b_1406 +#define pci_ss_info_147b_1406 pci_ss_info_11ab_4320_147b_1406 +static const pciSubsystemInfo pci_ss_info_11ab_4320_15d4_0047 = + {0x15d4, 0x0047, pci_subsys_11ab_4320_15d4_0047, 0}; +#undef pci_ss_info_15d4_0047 +#define pci_ss_info_15d4_0047 pci_ss_info_11ab_4320_15d4_0047 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1695_9025 = + {0x1695, 0x9025, pci_subsys_11ab_4320_1695_9025, 0}; +#undef pci_ss_info_1695_9025 +#define pci_ss_info_1695_9025 pci_ss_info_11ab_4320_1695_9025 +static const pciSubsystemInfo pci_ss_info_11ab_4320_17f2_1c03 = + {0x17f2, 0x1c03, pci_subsys_11ab_4320_17f2_1c03, 0}; +#undef pci_ss_info_17f2_1c03 +#define pci_ss_info_17f2_1c03 pci_ss_info_11ab_4320_17f2_1c03 +static const pciSubsystemInfo pci_ss_info_11ab_4320_270f_2803 = + {0x270f, 0x2803, pci_subsys_11ab_4320_270f_2803, 0}; +#undef pci_ss_info_270f_2803 +#define pci_ss_info_270f_2803 pci_ss_info_11ab_4320_270f_2803 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4350_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4350_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4350_11ab_3521 = + {0x11ab, 0x3521, pci_subsys_11ab_4350_11ab_3521, 0}; +#undef pci_ss_info_11ab_3521 +#define pci_ss_info_11ab_3521 pci_ss_info_11ab_4350_11ab_3521 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4350_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4350_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4350_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4350_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4350_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4350_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4350_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4350_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4350_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4350_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4350_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4350_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4350_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4350_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4350_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4350_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4350_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4350_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4350_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4350_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4350_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4350_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4350_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4350_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4351_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4351_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4351_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4351_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4351_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4351_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4351_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4351_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4351_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4351_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4351_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4351_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4351_11ab_3621 = + {0x11ab, 0x3621, pci_subsys_11ab_4351_11ab_3621, 0}; +#undef pci_ss_info_11ab_3621 +#define pci_ss_info_11ab_3621 pci_ss_info_11ab_4351_11ab_3621 +static const pciSubsystemInfo pci_ss_info_11ab_4351_13d1_ac12 = + {0x13d1, 0xac12, pci_subsys_11ab_4351_13d1_ac12, 0}; +#undef pci_ss_info_13d1_ac12 +#define pci_ss_info_13d1_ac12 pci_ss_info_11ab_4351_13d1_ac12 +static const pciSubsystemInfo pci_ss_info_11ab_4351_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4351_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4351_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4351_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4351_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4351_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4351_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4351_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4351_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4351_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4351_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4351_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4351_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4351_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4351_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4351_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4351_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4351_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4351_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4351_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4351_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4351_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4351_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4351_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4351_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4351_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4351_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1043_8134 = + {0x1043, 0x8134, pci_subsys_11ab_4360_1043_8134, 0}; +#undef pci_ss_info_1043_8134 +#define pci_ss_info_1043_8134 pci_ss_info_11ab_4360_1043_8134 +static const pciSubsystemInfo pci_ss_info_11ab_4360_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4360_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4360_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4360_11ab_5221 = + {0x11ab, 0x5221, pci_subsys_11ab_4360_11ab_5221, 0}; +#undef pci_ss_info_11ab_5221 +#define pci_ss_info_11ab_5221 pci_ss_info_11ab_4360_11ab_5221 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4360_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4360_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1462_052c = + {0x1462, 0x052c, pci_subsys_11ab_4360_1462_052c, 0}; +#undef pci_ss_info_1462_052c +#define pci_ss_info_1462_052c pci_ss_info_11ab_4360_1462_052c +static const pciSubsystemInfo pci_ss_info_11ab_4360_1849_8052 = + {0x1849, 0x8052, pci_subsys_11ab_4360_1849_8052, 0}; +#undef pci_ss_info_1849_8052 +#define pci_ss_info_1849_8052 pci_ss_info_11ab_4360_1849_8052 +static const pciSubsystemInfo pci_ss_info_11ab_4360_a0a0_0509 = + {0xa0a0, 0x0509, pci_subsys_11ab_4360_a0a0_0509, 0}; +#undef pci_ss_info_a0a0_0509 +#define pci_ss_info_a0a0_0509 pci_ss_info_11ab_4360_a0a0_0509 +static const pciSubsystemInfo pci_ss_info_11ab_4361_107b_3015 = + {0x107b, 0x3015, pci_subsys_11ab_4361_107b_3015, 0}; +#undef pci_ss_info_107b_3015 +#define pci_ss_info_107b_3015 pci_ss_info_11ab_4361_107b_3015 +static const pciSubsystemInfo pci_ss_info_11ab_4361_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4361_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4361_11ab_5021 +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3063 = + {0x8086, 0x3063, pci_subsys_11ab_4361_8086_3063, 0}; +#undef pci_ss_info_8086_3063 +#define pci_ss_info_8086_3063 pci_ss_info_11ab_4361_8086_3063 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3439 = + {0x8086, 0x3439, pci_subsys_11ab_4361_8086_3439, 0}; +#undef pci_ss_info_8086_3439 +#define pci_ss_info_8086_3439 pci_ss_info_11ab_4361_8086_3439 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4362_103c_2a0d = + {0x103c, 0x2a0d, pci_subsys_11ab_4362_103c_2a0d, 0}; +#undef pci_ss_info_103c_2a0d +#define pci_ss_info_103c_2a0d pci_ss_info_11ab_4362_103c_2a0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_4362_1043_8142 = + {0x1043, 0x8142, pci_subsys_11ab_4362_1043_8142, 0}; +#undef pci_ss_info_1043_8142 +#define pci_ss_info_1043_8142 pci_ss_info_11ab_4362_1043_8142 +static const pciSubsystemInfo pci_ss_info_11ab_4362_109f_3197 = + {0x109f, 0x3197, pci_subsys_11ab_4362_109f_3197, 0}; +#undef pci_ss_info_109f_3197 +#define pci_ss_info_109f_3197 pci_ss_info_11ab_4362_109f_3197 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4362_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4362_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10fd_a430 = + {0x10fd, 0xa430, pci_subsys_11ab_4362_10fd_a430, 0}; +#undef pci_ss_info_10fd_a430 +#define pci_ss_info_10fd_a430 pci_ss_info_11ab_4362_10fd_a430 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4362_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4362_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4362_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4362_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4362_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4362_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4362_11ab_5321 = + {0x11ab, 0x5321, pci_subsys_11ab_4362_11ab_5321, 0}; +#undef pci_ss_info_11ab_5321 +#define pci_ss_info_11ab_5321 pci_ss_info_11ab_4362_11ab_5321 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c240 = + {0x1297, 0xc240, pci_subsys_11ab_4362_1297_c240, 0}; +#undef pci_ss_info_1297_c240 +#define pci_ss_info_1297_c240 pci_ss_info_11ab_4362_1297_c240 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c241 = + {0x1297, 0xc241, pci_subsys_11ab_4362_1297_c241, 0}; +#undef pci_ss_info_1297_c241 +#define pci_ss_info_1297_c241 pci_ss_info_11ab_4362_1297_c241 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c242 = + {0x1297, 0xc242, pci_subsys_11ab_4362_1297_c242, 0}; +#undef pci_ss_info_1297_c242 +#define pci_ss_info_1297_c242 pci_ss_info_11ab_4362_1297_c242 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c243 = + {0x1297, 0xc243, pci_subsys_11ab_4362_1297_c243, 0}; +#undef pci_ss_info_1297_c243 +#define pci_ss_info_1297_c243 pci_ss_info_11ab_4362_1297_c243 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c244 = + {0x1297, 0xc244, pci_subsys_11ab_4362_1297_c244, 0}; +#undef pci_ss_info_1297_c244 +#define pci_ss_info_1297_c244 pci_ss_info_11ab_4362_1297_c244 +static const pciSubsystemInfo pci_ss_info_11ab_4362_13d1_ac11 = + {0x13d1, 0xac11, pci_subsys_11ab_4362_13d1_ac11, 0}; +#undef pci_ss_info_13d1_ac11 +#define pci_ss_info_13d1_ac11 pci_ss_info_11ab_4362_13d1_ac11 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4362_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4362_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1462_058c = + {0x1462, 0x058c, pci_subsys_11ab_4362_1462_058c, 0}; +#undef pci_ss_info_1462_058c +#define pci_ss_info_1462_058c pci_ss_info_11ab_4362_1462_058c +static const pciSubsystemInfo pci_ss_info_11ab_4362_14c0_0012 = + {0x14c0, 0x0012, pci_subsys_11ab_4362_14c0_0012, 0}; +#undef pci_ss_info_14c0_0012 +#define pci_ss_info_14c0_0012 pci_ss_info_11ab_4362_14c0_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1558_04a0 = + {0x1558, 0x04a0, pci_subsys_11ab_4362_1558_04a0, 0}; +#undef pci_ss_info_1558_04a0 +#define pci_ss_info_1558_04a0 pci_ss_info_11ab_4362_1558_04a0 +static const pciSubsystemInfo pci_ss_info_11ab_4362_15bd_1003 = + {0x15bd, 0x1003, pci_subsys_11ab_4362_15bd_1003, 0}; +#undef pci_ss_info_15bd_1003 +#define pci_ss_info_15bd_1003 pci_ss_info_11ab_4362_15bd_1003 +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203c = + {0x161f, 0x203c, pci_subsys_11ab_4362_161f_203c, 0}; +#undef pci_ss_info_161f_203c +#define pci_ss_info_161f_203c pci_ss_info_11ab_4362_161f_203c +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4362_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4362_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1695_9029 = + {0x1695, 0x9029, pci_subsys_11ab_4362_1695_9029, 0}; +#undef pci_ss_info_1695_9029 +#define pci_ss_info_1695_9029 pci_ss_info_11ab_4362_1695_9029 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17f2_2c08 = + {0x17f2, 0x2c08, pci_subsys_11ab_4362_17f2_2c08, 0}; +#undef pci_ss_info_17f2_2c08 +#define pci_ss_info_17f2_2c08 pci_ss_info_11ab_4362_17f2_2c08 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17ff_0585 = + {0x17ff, 0x0585, pci_subsys_11ab_4362_17ff_0585, 0}; +#undef pci_ss_info_17ff_0585 +#define pci_ss_info_17ff_0585 pci_ss_info_11ab_4362_17ff_0585 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1849_8053 = + {0x1849, 0x8053, pci_subsys_11ab_4362_1849_8053, 0}; +#undef pci_ss_info_1849_8053 +#define pci_ss_info_1849_8053 pci_ss_info_11ab_4362_1849_8053 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000b = + {0x1854, 0x000b, pci_subsys_11ab_4362_1854_000b, 0}; +#undef pci_ss_info_1854_000b +#define pci_ss_info_1854_000b pci_ss_info_11ab_4362_1854_000b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000c = + {0x1854, 0x000c, pci_subsys_11ab_4362_1854_000c, 0}; +#undef pci_ss_info_1854_000c +#define pci_ss_info_1854_000c pci_ss_info_11ab_4362_1854_000c +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0010 = + {0x1854, 0x0010, pci_subsys_11ab_4362_1854_0010, 0}; +#undef pci_ss_info_1854_0010 +#define pci_ss_info_1854_0010 pci_ss_info_11ab_4362_1854_0010 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0013 = + {0x1854, 0x0013, pci_subsys_11ab_4362_1854_0013, 0}; +#undef pci_ss_info_1854_0013 +#define pci_ss_info_1854_0013 pci_ss_info_11ab_4362_1854_0013 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0014 = + {0x1854, 0x0014, pci_subsys_11ab_4362_1854_0014, 0}; +#undef pci_ss_info_1854_0014 +#define pci_ss_info_1854_0014 pci_ss_info_11ab_4362_1854_0014 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0015 = + {0x1854, 0x0015, pci_subsys_11ab_4362_1854_0015, 0}; +#undef pci_ss_info_1854_0015 +#define pci_ss_info_1854_0015 pci_ss_info_11ab_4362_1854_0015 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001a = + {0x1854, 0x001a, pci_subsys_11ab_4362_1854_001a, 0}; +#undef pci_ss_info_1854_001a +#define pci_ss_info_1854_001a pci_ss_info_11ab_4362_1854_001a +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001b = + {0x1854, 0x001b, pci_subsys_11ab_4362_1854_001b, 0}; +#undef pci_ss_info_1854_001b +#define pci_ss_info_1854_001b pci_ss_info_11ab_4362_1854_001b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001d = + {0x1854, 0x001d, pci_subsys_11ab_4362_1854_001d, 0}; +#undef pci_ss_info_1854_001d +#define pci_ss_info_1854_001d pci_ss_info_11ab_4362_1854_001d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001f = + {0x1854, 0x001f, pci_subsys_11ab_4362_1854_001f, 0}; +#undef pci_ss_info_1854_001f +#define pci_ss_info_1854_001f pci_ss_info_11ab_4362_1854_001f +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0021 = + {0x1854, 0x0021, pci_subsys_11ab_4362_1854_0021, 0}; +#undef pci_ss_info_1854_0021 +#define pci_ss_info_1854_0021 pci_ss_info_11ab_4362_1854_0021 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0022 = + {0x1854, 0x0022, pci_subsys_11ab_4362_1854_0022, 0}; +#undef pci_ss_info_1854_0022 +#define pci_ss_info_1854_0022 pci_ss_info_11ab_4362_1854_0022 +static const pciSubsystemInfo pci_ss_info_11ab_4362_270f_2801 = + {0x270f, 0x2801, pci_subsys_11ab_4362_270f_2801, 0}; +#undef pci_ss_info_270f_2801 +#define pci_ss_info_270f_2801 pci_ss_info_11ab_4362_270f_2801 +static const pciSubsystemInfo pci_ss_info_11ab_4362_a0a0_0506 = + {0xa0a0, 0x0506, pci_subsys_11ab_4362_a0a0_0506, 0}; +#undef pci_ss_info_a0a0_0506 +#define pci_ss_info_a0a0_0506 pci_ss_info_11ab_4362_a0a0_0506 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2203 = + {0x8086, 0x2203, pci_subsys_11c1_0445_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_11c1_0445_8086_2203 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2204 = + {0x8086, 0x2204, pci_subsys_11c1_0445_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_11c1_0445_8086_2204 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_1033_80a8 = + {0x1033, 0x80a8, pci_subsys_11c1_0450_1033_80a8, 0}; +#undef pci_ss_info_1033_80a8 +#define pci_ss_info_1033_80a8 pci_ss_info_11c1_0450_1033_80a8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_1468_0450 = + {0x1468, 0x0450, pci_subsys_11c1_0450_1468_0450, 0}; +#undef pci_ss_info_1468_0450 +#define pci_ss_info_1468_0450 pci_ss_info_11c1_0450_1468_0450 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_4005_144f = + {0x4005, 0x144f, pci_subsys_11c1_0450_4005_144f, 0}; +#undef pci_ss_info_4005_144f +#define pci_ss_info_4005_144f pci_ss_info_11c1_0450_4005_144f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_5811_8086_524c = + {0x8086, 0x524c, pci_subsys_11c1_5811_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_11c1_5811_8086_524c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab12 = + {0x11c1, 0xab12, pci_subsys_11c1_ab11_11c1_ab12, 0}; +#undef pci_ss_info_11c1_ab12 +#define pci_ss_info_11c1_ab12 pci_ss_info_11c1_ab11_11c1_ab12 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab13 = + {0x11c1, 0xab13, pci_subsys_11c1_ab11_11c1_ab13, 0}; +#undef pci_ss_info_11c1_ab13 +#define pci_ss_info_11c1_ab13 pci_ss_info_11c1_ab11_11c1_ab13 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab15 = + {0x11c1, 0xab15, pci_subsys_11c1_ab11_11c1_ab15, 0}; +#undef pci_ss_info_11c1_ab15 +#define pci_ss_info_11c1_ab15 pci_ss_info_11c1_ab11_11c1_ab15 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab16 = + {0x11c1, 0xab16, pci_subsys_11c1_ab11_11c1_ab16, 0}; +#undef pci_ss_info_11c1_ab16 +#define pci_ss_info_11c1_ab16 pci_ss_info_11c1_ab11_11c1_ab16 +static const pciSubsystemInfo pci_ss_info_11c1_ab30_14cd_2012 = + {0x14cd, 0x2012, pci_subsys_11c1_ab30_14cd_2012, 0}; +#undef pci_ss_info_14cd_2012 +#define pci_ss_info_14cd_2012 pci_ss_info_11c1_ab30_14cd_2012 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_12f8_8a02 = + {0x12f8, 0x8a02, pci_subsys_11de_6057_12f8_8a02, 0}; +#undef pci_ss_info_12f8_8a02 +#define pci_ss_info_12f8_8a02 pci_ss_info_11de_6057_12f8_8a02 +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +static const pciSubsystemInfo pci_ss_info_11de_6120_1de1_9fff = + {0x1de1, 0x9fff, pci_subsys_11de_6120_1de1_9fff, 0}; +#undef pci_ss_info_1de1_9fff +#define pci_ss_info_1de1_9fff pci_ss_info_11de_6120_1de1_9fff +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1014_020c = + {0x1014, 0x020c, pci_subsys_1217_6972_1014_020c, 0}; +#undef pci_ss_info_1014_020c +#define pci_ss_info_1014_020c pci_ss_info_1217_6972_1014_020c +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7110_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7110_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7110_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7110_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7223_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7223_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7223_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7223_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0057 = + {0x121a, 0x0057, pci_subsys_121a_0005_121a_0057, 0}; +#undef pci_ss_info_121a_0057 +#define pci_ss_info_121a_0057 pci_ss_info_121a_0005_121a_0057 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0009_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0009_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000f = + {0x11bd, 0x000f, pci_subsys_123f_8120_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_123f_8120_11bd_000f +static const pciSubsystemInfo pci_ss_info_123f_8120_1809_0016 = + {0x1809, 0x0016, pci_subsys_123f_8120_1809_0016, 0}; +#undef pci_ss_info_1809_0016 +#define pci_ss_info_1809_0016 pci_ss_info_123f_8120_1809_0016 +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125b_1400_1186_1100 = + {0x1186, 0x1100, pci_subsys_125b_1400_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_125b_1400_1186_1100 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +static const pciSubsystemInfo pci_ss_info_125d_1969_153b_111b = + {0x153b, 0x111b, pci_subsys_125d_1969_153b_111b, 0}; +#undef pci_ss_info_153b_111b +#define pci_ss_info_153b_111b pci_ss_info_125d_1969_153b_111b +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_125d_1988_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_125d_1988_0e11_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_125d_1998_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_125d_1998_1028_00b1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3872_1468_0202 = + {0x1468, 0x0202, pci_subsys_1260_3872_1468_0202, 0}; +#undef pci_ss_info_1468_0202 +#define pci_ss_info_1468_0202 pci_ss_info_1260_3872_1468_0202 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3700 = + {0x1186, 0x3700, pci_subsys_1260_3873_1186_3700, 0}; +#undef pci_ss_info_1186_3700 +#define pci_ss_info_1186_3700 pci_ss_info_1260_3873_1186_3700 +static const pciSubsystemInfo pci_ss_info_1260_3873_1385_4105 = + {0x1385, 0x4105, pci_subsys_1260_3873_1385_4105, 0}; +#undef pci_ss_info_1385_4105 +#define pci_ss_info_1385_4105 pci_ss_info_1260_3873_1385_4105 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_16a5_1601 = + {0x16a5, 0x1601, pci_subsys_1260_3873_16a5_1601, 0}; +#undef pci_ss_info_16a5_1601 +#define pci_ss_info_16a5_1601 pci_ss_info_1260_3873_16a5_1601 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3886_17cf_0037 = + {0x17cf, 0x0037, pci_subsys_1260_3886_17cf_0037, 0}; +#undef pci_ss_info_17cf_0037 +#define pci_ss_info_17cf_0037 pci_ss_info_1260_3886_17cf_0037 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2802 = + {0x10b8, 0x2802, pci_subsys_1260_3890_10b8_2802, 0}; +#undef pci_ss_info_10b8_2802 +#define pci_ss_info_10b8_2802 pci_ss_info_1260_3890_10b8_2802 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2835 = + {0x10b8, 0x2835, pci_subsys_1260_3890_10b8_2835, 0}; +#undef pci_ss_info_10b8_2835 +#define pci_ss_info_10b8_2835 pci_ss_info_1260_3890_10b8_2835 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_a835 = + {0x10b8, 0xa835, pci_subsys_1260_3890_10b8_a835, 0}; +#undef pci_ss_info_10b8_a835 +#define pci_ss_info_10b8_a835 pci_ss_info_1260_3890_10b8_a835 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_4203 = + {0x1113, 0x4203, pci_subsys_1260_3890_1113_4203, 0}; +#undef pci_ss_info_1113_4203 +#define pci_ss_info_1113_4203 pci_ss_info_1260_3890_1113_4203 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee03 = + {0x1113, 0xee03, pci_subsys_1260_3890_1113_ee03, 0}; +#undef pci_ss_info_1113_ee03 +#define pci_ss_info_1113_ee03 pci_ss_info_1260_3890_1113_ee03 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee08 = + {0x1113, 0xee08, pci_subsys_1260_3890_1113_ee08, 0}; +#undef pci_ss_info_1113_ee08 +#define pci_ss_info_1113_ee08 pci_ss_info_1260_3890_1113_ee08 +static const pciSubsystemInfo pci_ss_info_1260_3890_1186_3202 = + {0x1186, 0x3202, pci_subsys_1260_3890_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_1260_3890_1186_3202 +static const pciSubsystemInfo pci_ss_info_1260_3890_1259_c104 = + {0x1259, 0xc104, pci_subsys_1260_3890_1259_c104, 0}; +#undef pci_ss_info_1259_c104 +#define pci_ss_info_1259_c104 pci_ss_info_1260_3890_1259_c104 +static const pciSubsystemInfo pci_ss_info_1260_3890_1385_4800 = + {0x1385, 0x4800, pci_subsys_1260_3890_1385_4800, 0}; +#undef pci_ss_info_1385_4800 +#define pci_ss_info_1385_4800 pci_ss_info_1260_3890_1385_4800 +static const pciSubsystemInfo pci_ss_info_1260_3890_16a5_1605 = + {0x16a5, 0x1605, pci_subsys_1260_3890_16a5_1605, 0}; +#undef pci_ss_info_16a5_1605 +#define pci_ss_info_16a5_1605 pci_ss_info_1260_3890_16a5_1605 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0014 = + {0x17cf, 0x0014, pci_subsys_1260_3890_17cf_0014, 0}; +#undef pci_ss_info_17cf_0014 +#define pci_ss_info_17cf_0014 pci_ss_info_1260_3890_17cf_0014 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0020 = + {0x17cf, 0x0020, pci_subsys_1260_3890_17cf_0020, 0}; +#undef pci_ss_info_17cf_0020 +#define pci_ss_info_17cf_0020 pci_ss_info_1260_3890_17cf_0020 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_1371_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_1371_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4541 = + {0x8086, 0x4541, pci_subsys_1274_1371_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_1274_1371_8086_4541 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_5880_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_5880_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1005_127a = + {0x1005, 0x127a, pci_subsys_127a_1005_1005_127a, 0}; +#undef pci_ss_info_1005_127a +#define pci_ss_info_1005_127a pci_ss_info_127a_1005_1005_127a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1283_8212_1283_0001 = + {0x1283, 0x0001, pci_subsys_1283_8212_1283_0001, 0}; +#undef pci_ss_info_1283_0001 +#define pci_ss_info_1283_0001 pci_ss_info_1283_8212_1283_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_1014_0104 = + {0x1014, 0x0104, pci_subsys_12ae_0001_1014_0104, 0}; +#undef pci_ss_info_1014_0104 +#define pci_ss_info_1014_0104 pci_ss_info_12ae_0001_1014_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_12ae_0002_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_12ae_0002_10a9_8002 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1317_8201_10b8_2635 = + {0x10b8, 0x2635, pci_subsys_1317_8201_10b8_2635, 0}; +#undef pci_ss_info_10b8_2635 +#define pci_ss_info_10b8_2635 pci_ss_info_1317_8201_10b8_2635 +static const pciSubsystemInfo pci_ss_info_1317_8201_1317_8201 = + {0x1317, 0x8201, pci_subsys_1317_8201_1317_8201, 0}; +#undef pci_ss_info_1317_8201 +#define pci_ss_info_1317_8201 pci_ss_info_1317_8201_1317_8201 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1319_0801_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0801_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0801_1319_1319 +static const pciSubsystemInfo pci_ss_info_1319_0802_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0802_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0802_1319_1319 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7890_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7890_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7890_134d_0001 +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1371_434e_1371_434e = + {0x1371, 0x434e, pci_subsys_1371_434e_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_1371_434e_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1704 = + {0x0675, 0x1704, pci_subsys_1397_2bd0_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1397_2bd0_0675_1704 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1708 = + {0x0675, 0x1708, pci_subsys_1397_2bd0_0675_1708, 0}; +#undef pci_ss_info_0675_1708 +#define pci_ss_info_0675_1708 pci_ss_info_1397_2bd0_0675_1708 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13c1_1001_13c1_1001 = + {0x13c1, 0x1001, pci_subsys_13c1_1001_13c1_1001, 0}; +#undef pci_ss_info_13c1_1001 +#define pci_ss_info_13c1_1001 pci_ss_info_13c1_1001_13c1_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8035 = + {0x1043, 0x8035, pci_subsys_13f6_0111_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_13f6_0111_1043_8035 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1681_a000 = + {0x1681, 0xa000, pci_subsys_13f6_0111_1681_a000, 0}; +#undef pci_ss_info_1681_a000 +#define pci_ss_info_1681_a000 pci_ss_info_13f6_0111_1681_a000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_1712 = + {0x1412, 0x1712, pci_subsys_1412_1712_1412_1712, 0}; +#undef pci_ss_info_1412_1712 +#define pci_ss_info_1412_1712 pci_ss_info_1412_1712_1412_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d630 = + {0x1412, 0xd630, pci_subsys_1412_1712_1412_d630, 0}; +#undef pci_ss_info_1412_d630 +#define pci_ss_info_1412_d630 pci_ss_info_1412_1712_1412_d630 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d631 = + {0x1412, 0xd631, pci_subsys_1412_1712_1412_d631, 0}; +#undef pci_ss_info_1412_d631 +#define pci_ss_info_1412_d631 pci_ss_info_1412_1712_1412_d631 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d632 = + {0x1412, 0xd632, pci_subsys_1412_1712_1412_d632, 0}; +#undef pci_ss_info_1412_d632 +#define pci_ss_info_1412_d632 pci_ss_info_1412_1712_1412_d632 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d633 = + {0x1412, 0xd633, pci_subsys_1412_1712_1412_d633, 0}; +#undef pci_ss_info_1412_d633 +#define pci_ss_info_1412_d633 pci_ss_info_1412_1712_1412_d633 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d634 = + {0x1412, 0xd634, pci_subsys_1412_1712_1412_d634, 0}; +#undef pci_ss_info_1412_d634 +#define pci_ss_info_1412_d634 pci_ss_info_1412_1712_1412_d634 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d635 = + {0x1412, 0xd635, pci_subsys_1412_1712_1412_d635, 0}; +#undef pci_ss_info_1412_d635 +#define pci_ss_info_1412_d635 pci_ss_info_1412_1712_1412_d635 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d637 = + {0x1412, 0xd637, pci_subsys_1412_1712_1412_d637, 0}; +#undef pci_ss_info_1412_d637 +#define pci_ss_info_1412_d637 pci_ss_info_1412_1712_1412_d637 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d638 = + {0x1412, 0xd638, pci_subsys_1412_1712_1412_d638, 0}; +#undef pci_ss_info_1412_d638 +#define pci_ss_info_1412_d638 pci_ss_info_1412_1712_1412_d638 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63b = + {0x1412, 0xd63b, pci_subsys_1412_1712_1412_d63b, 0}; +#undef pci_ss_info_1412_d63b +#define pci_ss_info_1412_d63b pci_ss_info_1412_1712_1412_d63b +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63c = + {0x1412, 0xd63c, pci_subsys_1412_1712_1412_d63c, 0}; +#undef pci_ss_info_1412_d63c +#define pci_ss_info_1412_d63c pci_ss_info_1412_1712_1412_d63c +static const pciSubsystemInfo pci_ss_info_1412_1712_1416_1712 = + {0x1416, 0x1712, pci_subsys_1412_1712_1416_1712, 0}; +#undef pci_ss_info_1416_1712 +#define pci_ss_info_1416_1712 pci_ss_info_1412_1712_1416_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1115 = + {0x153b, 0x1115, pci_subsys_1412_1712_153b_1115, 0}; +#undef pci_ss_info_153b_1115 +#define pci_ss_info_153b_1115 pci_ss_info_1412_1712_153b_1115 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1125 = + {0x153b, 0x1125, pci_subsys_1412_1712_153b_1125, 0}; +#undef pci_ss_info_153b_1125 +#define pci_ss_info_153b_1125 pci_ss_info_1412_1712_153b_1125 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112b = + {0x153b, 0x112b, pci_subsys_1412_1712_153b_112b, 0}; +#undef pci_ss_info_153b_112b +#define pci_ss_info_153b_112b pci_ss_info_1412_1712_153b_112b +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112c = + {0x153b, 0x112c, pci_subsys_1412_1712_153b_112c, 0}; +#undef pci_ss_info_153b_112c +#define pci_ss_info_153b_112c pci_ss_info_1412_1712_153b_112c +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1130 = + {0x153b, 0x1130, pci_subsys_1412_1712_153b_1130, 0}; +#undef pci_ss_info_153b_1130 +#define pci_ss_info_153b_1130 pci_ss_info_1412_1712_153b_1130 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1138 = + {0x153b, 0x1138, pci_subsys_1412_1712_153b_1138, 0}; +#undef pci_ss_info_153b_1138 +#define pci_ss_info_153b_1138 pci_ss_info_1412_1712_153b_1138 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1151 = + {0x153b, 0x1151, pci_subsys_1412_1712_153b_1151, 0}; +#undef pci_ss_info_153b_1151 +#define pci_ss_info_153b_1151 pci_ss_info_1412_1712_153b_1151 +static const pciSubsystemInfo pci_ss_info_1412_1712_16ce_1040 = + {0x16ce, 0x1040, pci_subsys_1412_1712_16ce_1040, 0}; +#undef pci_ss_info_16ce_1040 +#define pci_ss_info_16ce_1040 pci_ss_info_1412_1712_16ce_1040 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_1724 = + {0x1412, 0x1724, pci_subsys_1412_1724_1412_1724, 0}; +#undef pci_ss_info_1412_1724 +#define pci_ss_info_1412_1724 pci_ss_info_1412_1724_1412_1724 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3630 = + {0x1412, 0x3630, pci_subsys_1412_1724_1412_3630, 0}; +#undef pci_ss_info_1412_3630 +#define pci_ss_info_1412_3630 pci_ss_info_1412_1724_1412_3630 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3631 = + {0x1412, 0x3631, pci_subsys_1412_1724_1412_3631, 0}; +#undef pci_ss_info_1412_3631 +#define pci_ss_info_1412_3631 pci_ss_info_1412_1724_1412_3631 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1145 = + {0x153b, 0x1145, pci_subsys_1412_1724_153b_1145, 0}; +#undef pci_ss_info_153b_1145 +#define pci_ss_info_153b_1145 pci_ss_info_1412_1724_153b_1145 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1147 = + {0x153b, 0x1147, pci_subsys_1412_1724_153b_1147, 0}; +#undef pci_ss_info_153b_1147 +#define pci_ss_info_153b_1147 pci_ss_info_1412_1724_153b_1147 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1153 = + {0x153b, 0x1153, pci_subsys_1412_1724_153b_1153, 0}; +#undef pci_ss_info_153b_1153 +#define pci_ss_info_153b_1153 pci_ss_info_1412_1724_153b_1153 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f641 = + {0x270f, 0xf641, pci_subsys_1412_1724_270f_f641, 0}; +#undef pci_ss_info_270f_f641 +#define pci_ss_info_270f_f641 pci_ss_info_1412_1724_270f_f641 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f645 = + {0x270f, 0xf645, pci_subsys_1412_1724_270f_f645, 0}; +#undef pci_ss_info_270f_f645 +#define pci_ss_info_270f_f645 pci_ss_info_1412_1724_270f_f645 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2050 = + {0x131f, 0x2050, pci_subsys_1415_9501_131f_2050, 0}; +#undef pci_ss_info_131f_2050 +#define pci_ss_info_131f_2050 pci_ss_info_1415_9501_131f_2050 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2051 = + {0x131f, 0x2051, pci_subsys_1415_9501_131f_2051, 0}; +#undef pci_ss_info_131f_2051 +#define pci_ss_info_131f_2051 pci_ss_info_1415_9501_131f_2051 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128a = + {0x103c, 0x128a, pci_subsys_14e4_1645_103c_128a, 0}; +#undef pci_ss_info_103c_128a +#define pci_ss_info_103c_128a pci_ss_info_14e4_1645_103c_128a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128b = + {0x103c, 0x128b, pci_subsys_14e4_1645_103c_128b, 0}; +#undef pci_ss_info_103c_128b +#define pci_ss_info_103c_128b pci_ss_info_14e4_1645_103c_128b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12a4 = + {0x103c, 0x12a4, pci_subsys_14e4_1645_103c_12a4, 0}; +#undef pci_ss_info_103c_12a4 +#define pci_ss_info_103c_12a4 pci_ss_info_14e4_1645_103c_12a4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12c1 = + {0x103c, 0x12c1, pci_subsys_14e4_1645_103c_12c1, 0}; +#undef pci_ss_info_103c_12c1 +#define pci_ss_info_103c_12c1 pci_ss_info_14e4_1645_103c_12c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_1300 = + {0x103c, 0x1300, pci_subsys_14e4_1645_103c_1300, 0}; +#undef pci_ss_info_103c_1300 +#define pci_ss_info_103c_1300 pci_ss_info_14e4_1645_103c_1300 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1645_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1645_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8011 = + {0x10a9, 0x8011, pci_subsys_14e4_1645_10a9_8011, 0}; +#undef pci_ss_info_10a9_8011 +#define pci_ss_info_10a9_8011 pci_ss_info_14e4_1645_10a9_8011 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8012 = + {0x10a9, 0x8012, pci_subsys_14e4_1645_10a9_8012, 0}; +#undef pci_ss_info_10a9_8012 +#define pci_ss_info_10a9_8012 pci_ss_info_14e4_1645_10a9_8012 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1647_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1647_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1734_100b = + {0x1734, 0x100b, pci_subsys_14e4_1648_1734_100b, 0}; +#undef pci_ss_info_1734_100b +#define pci_ss_info_1734_100b pci_ss_info_14e4_1648_1734_100b +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3101 = + {0x103c, 0x3101, pci_subsys_14e4_164a_103c_3101, 0}; +#undef pci_ss_info_103c_3101 +#define pci_ss_info_103c_3101 pci_ss_info_14e4_164a_103c_3101 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1653_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1653_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1653_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1654_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1654_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3100 = + {0x103c, 0x3100, pci_subsys_14e4_1654_103c_3100, 0}; +#undef pci_ss_info_103c_3100 +#define pci_ss_info_103c_3100 pci_ss_info_14e4_1654_103c_3100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3226 = + {0x103c, 0x3226, pci_subsys_14e4_1654_103c_3226, 0}; +#undef pci_ss_info_103c_3226 +#define pci_ss_info_103c_3226 pci_ss_info_14e4_1654_103c_3226 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7031 = + {0x103c, 0x7031, pci_subsys_14e4_1659_103c_7031, 0}; +#undef pci_ss_info_103c_7031 +#define pci_ss_info_103c_7031 pci_ss_info_14e4_1659_103c_7031 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7032 = + {0x103c, 0x7032, pci_subsys_14e4_1659_103c_7032, 0}; +#undef pci_ss_info_103c_7032 +#define pci_ss_info_103c_7032 pci_ss_info_14e4_1659_103c_7032 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1734_1061 = + {0x1734, 0x1061, pci_subsys_14e4_1659_1734_1061, 0}; +#undef pci_ss_info_1734_1061 +#define pci_ss_info_1734_1061 pci_ss_info_14e4_1659_1734_1061 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165d_1028_865d = + {0x1028, 0x865d, pci_subsys_14e4_165d_1028_865d, 0}; +#undef pci_ss_info_1028_865d +#define pci_ss_info_1028_865d pci_ss_info_14e4_165d_1028_865d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_088c = + {0x103c, 0x088c, pci_subsys_14e4_165e_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_14e4_165e_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_0890 = + {0x103c, 0x0890, pci_subsys_14e4_165e_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_14e4_165e_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_165e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_165e_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1668_103c_7039 = + {0x103c, 0x7039, pci_subsys_14e4_1668_103c_7039, 0}; +#undef pci_ss_info_103c_7039 +#define pci_ss_info_103c_7039 pci_ss_info_14e4_1668_103c_7039 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0179 = + {0x1028, 0x0179, pci_subsys_14e4_1677_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_14e4_1677_1028_0179 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0182 = + {0x1028, 0x0182, pci_subsys_14e4_1677_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_14e4_1677_1028_0182 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_01ad = + {0x1028, 0x01ad, pci_subsys_14e4_1677_1028_01ad, 0}; +#undef pci_ss_info_1028_01ad +#define pci_ss_info_1028_01ad pci_ss_info_14e4_1677_1028_01ad +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1677_1734_105d = + {0x1734, 0x105d, pci_subsys_14e4_1677_1734_105d, 0}; +#undef pci_ss_info_1734_105d +#define pci_ss_info_1734_105d pci_ss_info_14e4_1677_1734_105d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1696_103c_12bc = + {0x103c, 0x12bc, pci_subsys_14e4_1696_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_14e4_1696_103c_12bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_169c_103c_308b = + {0x103c, 0x308b, pci_subsys_14e4_169c_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_14e4_169c_103c_308b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16aa_103c_3102 = + {0x103c, 0x3102, pci_subsys_14e4_16aa_103c_3102, 0}; +#undef pci_ss_info_103c_3102 +#define pci_ss_info_103c_3102 pci_ss_info_14e4_16aa_103c_3102 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16c7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16c7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16c7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16c7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12c3 = + {0x103c, 0x12c3, pci_subsys_14e4_16c7_103c_12c3, 0}; +#undef pci_ss_info_103c_12c3 +#define pci_ss_info_103c_12c3 pci_ss_info_14e4_16c7_103c_12c3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12ca = + {0x103c, 0x12ca, pci_subsys_14e4_16c7_103c_12ca, 0}; +#undef pci_ss_info_103c_12ca +#define pci_ss_info_103c_12ca pci_ss_info_14e4_16c7_103c_12ca +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0188 = + {0x1028, 0x0188, pci_subsys_14e4_170c_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_14e4_170c_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0196 = + {0x1028, 0x0196, pci_subsys_14e4_170c_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_14e4_170c_1028_0196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_170c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_170c_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_170d_1014_0545 = + {0x1014, 0x0545, pci_subsys_14e4_170d_1014_0545, 0}; +#undef pci_ss_info_1014_0545 +#define pci_ss_info_1014_0545 pci_ss_info_14e4_170d_1014_0545 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4301_1028_0407 = + {0x1028, 0x0407, pci_subsys_14e4_4301_1028_0407, 0}; +#undef pci_ss_info_1028_0407 +#define pci_ss_info_1028_0407 pci_ss_info_14e4_4301_1028_0407 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4301_1043_0120 = + {0x1043, 0x0120, pci_subsys_14e4_4301_1043_0120, 0}; +#undef pci_ss_info_1043_0120 +#define pci_ss_info_1043_0120 pci_ss_info_14e4_4301_1043_0120 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4318_103c_1356 = + {0x103c, 0x1356, pci_subsys_14e4_4318_103c_1356, 0}; +#undef pci_ss_info_103c_1356 +#define pci_ss_info_103c_1356 pci_ss_info_14e4_4318_103c_1356 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0311 = + {0x1468, 0x0311, pci_subsys_14e4_4318_1468_0311, 0}; +#undef pci_ss_info_1468_0311 +#define pci_ss_info_1468_0311 pci_ss_info_14e4_4318_1468_0311 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_0449 = + {0x14e4, 0x0449, pci_subsys_14e4_4318_14e4_0449, 0}; +#undef pci_ss_info_14e4_0449 +#define pci_ss_info_14e4_0449 pci_ss_info_14e4_4318_14e4_0449 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_4318 = + {0x14e4, 0x4318, pci_subsys_14e4_4318_14e4_4318, 0}; +#undef pci_ss_info_14e4_4318 +#define pci_ss_info_14e4_4318 pci_ss_info_14e4_4318_14e4_4318 +static const pciSubsystemInfo pci_ss_info_14e4_4318_16ec_0119 = + {0x16ec, 0x0119, pci_subsys_14e4_4318_16ec_0119, 0}; +#undef pci_ss_info_16ec_0119 +#define pci_ss_info_16ec_0119 pci_ss_info_14e4_4318_16ec_0119 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4320_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4320_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4320_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4320_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12fa = + {0x103c, 0x12fa, pci_subsys_14e4_4320_103c_12fa, 0}; +#undef pci_ss_info_103c_12fa +#define pci_ss_info_103c_12fa pci_ss_info_14e4_4320_103c_12fa +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_1043_100f = + {0x1043, 0x100f, pci_subsys_14e4_4320_1043_100f, 0}; +#undef pci_ss_info_1043_100f +#define pci_ss_info_1043_100f pci_ss_info_14e4_4320_1043_100f +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1057_7025 = + {0x1057, 0x7025, pci_subsys_14e4_4320_1057_7025, 0}; +#undef pci_ss_info_1057_7025 +#define pci_ss_info_1057_7025 pci_ss_info_14e4_4320_1057_7025 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_106b_004e = + {0x106b, 0x004e, pci_subsys_14e4_4320_106b_004e, 0}; +#undef pci_ss_info_106b_004e +#define pci_ss_info_106b_004e pci_ss_info_14e4_4320_106b_004e +static const pciSubsystemInfo pci_ss_info_14e4_4320_14e4_4320 = + {0x14e4, 0x4320, pci_subsys_14e4_4320_14e4_4320, 0}; +#undef pci_ss_info_14e4_4320 +#define pci_ss_info_14e4_4320 pci_ss_info_14e4_4320_14e4_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1737_4320 = + {0x1737, 0x4320, pci_subsys_14e4_4320_1737_4320, 0}; +#undef pci_ss_info_1737_4320 +#define pci_ss_info_1737_4320 pci_ss_info_14e4_4320_1737_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7001 = + {0x1799, 0x7001, pci_subsys_14e4_4320_1799_7001, 0}; +#undef pci_ss_info_1799_7001 +#define pci_ss_info_1799_7001 pci_ss_info_14e4_4320_1799_7001 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7010 = + {0x1799, 0x7010, pci_subsys_14e4_4320_1799_7010, 0}; +#undef pci_ss_info_1799_7010 +#define pci_ss_info_1799_7010 pci_ss_info_14e4_4320_1799_7010 +static const pciSubsystemInfo pci_ss_info_14e4_4320_185f_1220 = + {0x185f, 0x1220, pci_subsys_14e4_4320_185f_1220, 0}; +#undef pci_ss_info_185f_1220 +#define pci_ss_info_185f_1220 pci_ss_info_14e4_4320_185f_1220 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4324_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4324_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4324_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4324_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0003 = + {0x1414, 0x0003, pci_subsys_14e4_4325_1414_0003, 0}; +#undef pci_ss_info_1414_0003 +#define pci_ss_info_1414_0003 pci_ss_info_14e4_4325_1414_0003 +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0004 = + {0x1414, 0x0004, pci_subsys_14e4_4325_1414_0004, 0}; +#undef pci_ss_info_1414_0004 +#define pci_ss_info_1414_0004 pci_ss_info_14e4_4325_1414_0004 +static const pciSubsystemInfo pci_ss_info_14e4_4401_1043_80a8 = + {0x1043, 0x80a8, pci_subsys_14e4_4401_1043_80a8, 0}; +#undef pci_ss_info_1043_80a8 +#define pci_ss_info_1043_80a8 pci_ss_info_14e4_4401_1043_80a8 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2045_14f1_2045 = + {0x14f1, 0x2045, pci_subsys_14f1_2045_14f1_2045, 0}; +#undef pci_ss_info_14f1_2045 +#define pci_ss_info_14f1_2045 pci_ss_info_14f1_2045_14f1_2045 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8800_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8800_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8800_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8800_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8800_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8800_0070_9002 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_00f8 = + {0x1002, 0x00f8, pci_subsys_14f1_8800_1002_00f8, 0}; +#undef pci_ss_info_1002_00f8 +#define pci_ss_info_1002_00f8 pci_ss_info_14f1_8800_1002_00f8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_8800_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8800_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8800_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6613 = + {0x107d, 0x6613, pci_subsys_14f1_8800_107d_6613, 0}; +#undef pci_ss_info_107d_6613 +#define pci_ss_info_107d_6613 pci_ss_info_14f1_8800_107d_6613 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6620 = + {0x107d, 0x6620, pci_subsys_14f1_8800_107d_6620, 0}; +#undef pci_ss_info_107d_6620 +#define pci_ss_info_107d_6620 pci_ss_info_14f1_8800_107d_6620 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8800_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8800_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d003 = + {0x10fc, 0xd003, pci_subsys_14f1_8800_10fc_d003, 0}; +#undef pci_ss_info_10fc_d003 +#define pci_ss_info_10fc_d003 pci_ss_info_14f1_8800_10fc_d003 +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d035 = + {0x10fc, 0xd035, pci_subsys_14f1_8800_10fc_d035, 0}; +#undef pci_ss_info_10fc_d035 +#define pci_ss_info_10fc_d035 pci_ss_info_14f1_8800_10fc_d035 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000b = + {0x1461, 0x000b, pci_subsys_14f1_8800_1461_000b, 0}; +#undef pci_ss_info_1461_000b +#define pci_ss_info_1461_000b pci_ss_info_14f1_8800_1461_000b +static const pciSubsystemInfo pci_ss_info_14f1_8800_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8800_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8800_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14c7_0107 = + {0x14c7, 0x0107, pci_subsys_14f1_8800_14c7_0107, 0}; +#undef pci_ss_info_14c7_0107 +#define pci_ss_info_14c7_0107 pci_ss_info_14f1_8800_14c7_0107 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8800_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8800_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0342 = + {0x14f1, 0x0342, pci_subsys_14f1_8800_14f1_0342, 0}; +#undef pci_ss_info_14f1_0342 +#define pci_ss_info_14f1_0342 pci_ss_info_14f1_8800_14f1_0342 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1540_2580 = + {0x1540, 0x2580, pci_subsys_14f1_8800_1540_2580, 0}; +#undef pci_ss_info_1540_2580 +#define pci_ss_info_1540_2580 pci_ss_info_14f1_8800_1540_2580 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4811 = + {0x1554, 0x4811, pci_subsys_14f1_8800_1554_4811, 0}; +#undef pci_ss_info_1554_4811 +#define pci_ss_info_1554_4811 pci_ss_info_14f1_8800_1554_4811 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8800_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8800_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8800_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8800_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_a8a6 = + {0x17de, 0xa8a6, pci_subsys_14f1_8800_17de_a8a6, 0}; +#undef pci_ss_info_17de_a8a6 +#define pci_ss_info_17de_a8a6 pci_ss_info_14f1_8800_17de_a8a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8800_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8800_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8800_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8800_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8800_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8800_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8800_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8800_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8800_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8800_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8800_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8800_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8800_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8801_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8801_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8801_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8802_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8802_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8802_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8802_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8802_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8802_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8802_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8802_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8802_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8802_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8802_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8802_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8802_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8802_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8802_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8802_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8802_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8802_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8802_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8802_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8802_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8802_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8802_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8802_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8802_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8802_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8802_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8802_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8802_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8802_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8804_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8804_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8804_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8811_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8811_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8811_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8811_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8811_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8811_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8811_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8811_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8811_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8811_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8811_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8811_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8811_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8811_18ac_db00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0c00 = + {0x1522, 0x0c00, pci_subsys_1522_0100_1522_0c00, 0}; +#undef pci_ss_info_1522_0c00 +#define pci_ss_info_1522_0c00 pci_ss_info_1522_0100_1522_0c00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0d00 = + {0x1522, 0x0d00, pci_subsys_1522_0100_1522_0d00, 0}; +#undef pci_ss_info_1522_0d00 +#define pci_ss_info_1522_0d00 pci_ss_info_1522_0100_1522_0d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_1d00 = + {0x1522, 0x1d00, pci_subsys_1522_0100_1522_1d00, 0}; +#undef pci_ss_info_1522_1d00 +#define pci_ss_info_1522_1d00 pci_ss_info_1522_0100_1522_1d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2000 = + {0x1522, 0x2000, pci_subsys_1522_0100_1522_2000, 0}; +#undef pci_ss_info_1522_2000 +#define pci_ss_info_1522_2000 pci_ss_info_1522_0100_1522_2000 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2100 = + {0x1522, 0x2100, pci_subsys_1522_0100_1522_2100, 0}; +#undef pci_ss_info_1522_2100 +#define pci_ss_info_1522_2100 pci_ss_info_1522_0100_1522_2100 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2200 = + {0x1522, 0x2200, pci_subsys_1522_0100_1522_2200, 0}; +#undef pci_ss_info_1522_2200 +#define pci_ss_info_1522_2200 pci_ss_info_1522_0100_1522_2200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2300 = + {0x1522, 0x2300, pci_subsys_1522_0100_1522_2300, 0}; +#undef pci_ss_info_1522_2300 +#define pci_ss_info_1522_2300 pci_ss_info_1522_0100_1522_2300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2400 = + {0x1522, 0x2400, pci_subsys_1522_0100_1522_2400, 0}; +#undef pci_ss_info_1522_2400 +#define pci_ss_info_1522_2400 pci_ss_info_1522_0100_1522_2400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2500 = + {0x1522, 0x2500, pci_subsys_1522_0100_1522_2500, 0}; +#undef pci_ss_info_1522_2500 +#define pci_ss_info_1522_2500 pci_ss_info_1522_0100_1522_2500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2600 = + {0x1522, 0x2600, pci_subsys_1522_0100_1522_2600, 0}; +#undef pci_ss_info_1522_2600 +#define pci_ss_info_1522_2600 pci_ss_info_1522_0100_1522_2600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2700 = + {0x1522, 0x2700, pci_subsys_1522_0100_1522_2700, 0}; +#undef pci_ss_info_1522_2700 +#define pci_ss_info_1522_2700 pci_ss_info_1522_0100_1522_2700 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_005a = + {0x1025, 0x005a, pci_subsys_1524_1410_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1524_1410_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_167b_2102_187e_3406 = + {0x187e, 0x3406, pci_subsys_167b_2102_187e_3406, 0}; +#undef pci_ss_info_187e_3406 +#define pci_ss_info_187e_3406 pci_ss_info_167b_2102_187e_3406 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_168c_0013_1113_d301 = + {0x1113, 0xd301, pci_subsys_168c_0013_1113_d301, 0}; +#undef pci_ss_info_1113_d301 +#define pci_ss_info_1113_d301 pci_ss_info_168c_0013_1113_d301 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3202 = + {0x1186, 0x3202, pci_subsys_168c_0013_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_168c_0013_1186_3202 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3203 = + {0x1186, 0x3203, pci_subsys_168c_0013_1186_3203, 0}; +#undef pci_ss_info_1186_3203 +#define pci_ss_info_1186_3203 pci_ss_info_168c_0013_1186_3203 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a12 = + {0x1186, 0x3a12, pci_subsys_168c_0013_1186_3a12, 0}; +#undef pci_ss_info_1186_3a12 +#define pci_ss_info_1186_3a12 pci_ss_info_168c_0013_1186_3a12 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a13 = + {0x1186, 0x3a13, pci_subsys_168c_0013_1186_3a13, 0}; +#undef pci_ss_info_1186_3a13 +#define pci_ss_info_1186_3a13 pci_ss_info_168c_0013_1186_3a13 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a14 = + {0x1186, 0x3a14, pci_subsys_168c_0013_1186_3a14, 0}; +#undef pci_ss_info_1186_3a14 +#define pci_ss_info_1186_3a14 pci_ss_info_168c_0013_1186_3a14 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a17 = + {0x1186, 0x3a17, pci_subsys_168c_0013_1186_3a17, 0}; +#undef pci_ss_info_1186_3a17 +#define pci_ss_info_1186_3a17 pci_ss_info_168c_0013_1186_3a17 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a18 = + {0x1186, 0x3a18, pci_subsys_168c_0013_1186_3a18, 0}; +#undef pci_ss_info_1186_3a18 +#define pci_ss_info_1186_3a18 pci_ss_info_168c_0013_1186_3a18 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a63 = + {0x1186, 0x3a63, pci_subsys_168c_0013_1186_3a63, 0}; +#undef pci_ss_info_1186_3a63 +#define pci_ss_info_1186_3a63 pci_ss_info_168c_0013_1186_3a63 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a94 = + {0x1186, 0x3a94, pci_subsys_168c_0013_1186_3a94, 0}; +#undef pci_ss_info_1186_3a94 +#define pci_ss_info_1186_3a94 pci_ss_info_168c_0013_1186_3a94 +static const pciSubsystemInfo pci_ss_info_168c_0013_1385_4d00 = + {0x1385, 0x4d00, pci_subsys_168c_0013_1385_4d00, 0}; +#undef pci_ss_info_1385_4d00 +#define pci_ss_info_1385_4d00 pci_ss_info_168c_0013_1385_4d00 +static const pciSubsystemInfo pci_ss_info_168c_0013_1458_e911 = + {0x1458, 0xe911, pci_subsys_168c_0013_1458_e911, 0}; +#undef pci_ss_info_1458_e911 +#define pci_ss_info_1458_e911 pci_ss_info_168c_0013_1458_e911 +static const pciSubsystemInfo pci_ss_info_168c_0013_14b7_0a60 = + {0x14b7, 0x0a60, pci_subsys_168c_0013_14b7_0a60, 0}; +#undef pci_ss_info_14b7_0a60 +#define pci_ss_info_14b7_0a60 pci_ss_info_168c_0013_14b7_0a60 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_0013 = + {0x168c, 0x0013, pci_subsys_168c_0013_168c_0013, 0}; +#undef pci_ss_info_168c_0013 +#define pci_ss_info_168c_0013 pci_ss_info_168c_0013_168c_0013 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1025 = + {0x168c, 0x1025, pci_subsys_168c_0013_168c_1025, 0}; +#undef pci_ss_info_168c_1025 +#define pci_ss_info_168c_1025 pci_ss_info_168c_0013_168c_1025 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1027 = + {0x168c, 0x1027, pci_subsys_168c_0013_168c_1027, 0}; +#undef pci_ss_info_168c_1027 +#define pci_ss_info_168c_1027 pci_ss_info_168c_0013_168c_1027 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2026 = + {0x168c, 0x2026, pci_subsys_168c_0013_168c_2026, 0}; +#undef pci_ss_info_168c_2026 +#define pci_ss_info_168c_2026 pci_ss_info_168c_0013_168c_2026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2041 = + {0x168c, 0x2041, pci_subsys_168c_0013_168c_2041, 0}; +#undef pci_ss_info_168c_2041 +#define pci_ss_info_168c_2041 pci_ss_info_168c_0013_168c_2041 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2042 = + {0x168c, 0x2042, pci_subsys_168c_0013_168c_2042, 0}; +#undef pci_ss_info_168c_2042 +#define pci_ss_info_168c_2042 pci_ss_info_168c_0013_168c_2042 +static const pciSubsystemInfo pci_ss_info_168c_0013_16ab_7302 = + {0x16ab, 0x7302, pci_subsys_168c_0013_16ab_7302, 0}; +#undef pci_ss_info_16ab_7302 +#define pci_ss_info_16ab_7302 pci_ss_info_168c_0013_16ab_7302 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a15 = + {0x1186, 0x3a15, pci_subsys_168c_001a_1186_3a15, 0}; +#undef pci_ss_info_1186_3a15 +#define pci_ss_info_1186_3a15 pci_ss_info_168c_001a_1186_3a15 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a16 = + {0x1186, 0x3a16, pci_subsys_168c_001a_1186_3a16, 0}; +#undef pci_ss_info_1186_3a16 +#define pci_ss_info_1186_3a16 pci_ss_info_168c_001a_1186_3a16 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a23 = + {0x1186, 0x3a23, pci_subsys_168c_001a_1186_3a23, 0}; +#undef pci_ss_info_1186_3a23 +#define pci_ss_info_1186_3a23 pci_ss_info_168c_001a_1186_3a23 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a24 = + {0x1186, 0x3a24, pci_subsys_168c_001a_1186_3a24, 0}; +#undef pci_ss_info_1186_3a24 +#define pci_ss_info_1186_3a24 pci_ss_info_168c_001a_1186_3a24 +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_1052 = + {0x168c, 0x1052, pci_subsys_168c_001a_168c_1052, 0}; +#undef pci_ss_info_168c_1052 +#define pci_ss_info_168c_1052 pci_ss_info_168c_001a_168c_1052 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a19 = + {0x1186, 0x3a19, pci_subsys_168c_001b_1186_3a19, 0}; +#undef pci_ss_info_1186_3a19 +#define pci_ss_info_1186_3a19 pci_ss_info_168c_001b_1186_3a19 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a22 = + {0x1186, 0x3a22, pci_subsys_168c_001b_1186_3a22, 0}; +#undef pci_ss_info_1186_3a22 +#define pci_ss_info_1186_3a22 pci_ss_info_168c_001b_1186_3a22 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0015 = + {0x1737, 0x0015, pci_subsys_1737_1032_1737_0015, 0}; +#undef pci_ss_info_1737_0015 +#define pci_ss_info_1737_0015 pci_ss_info_1737_1032_1737_0015 +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0024 = + {0x1737, 0x0024, pci_subsys_1737_1032_1737_0024, 0}; +#undef pci_ss_info_1737_0024 +#define pci_ss_info_1737_0024 pci_ss_info_1737_1032_1737_0024 +static const pciSubsystemInfo pci_ss_info_1737_1064_1737_0016 = + {0x1737, 0x0016, pci_subsys_1737_1064_1737_0016, 0}; +#undef pci_ss_info_1737_0016 +#define pci_ss_info_1737_0016 pci_ss_info_1737_1064_1737_0016 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_17d3_5831_103c_12d5 = + {0x103c, 0x12d5, pci_subsys_17d3_5831_103c_12d5, 0}; +#undef pci_ss_info_103c_12d5 +#define pci_ss_info_103c_12d5 pci_ss_info_17d3_5831_103c_12d5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17fe_2220_17fe_2220 = + {0x17fe, 0x2220, pci_subsys_17fe_2220_17fe_2220, 0}; +#undef pci_ss_info_17fe_2220 +#define pci_ss_info_17fe_2220 pci_ss_info_17fe_2220_17fe_2220 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1814_0101_1043_0127 = + {0x1043, 0x0127, pci_subsys_1814_0101_1043_0127, 0}; +#undef pci_ss_info_1043_0127 +#define pci_ss_info_1043_0127 pci_ss_info_1814_0101_1043_0127 +static const pciSubsystemInfo pci_ss_info_1814_0101_1462_6828 = + {0x1462, 0x6828, pci_subsys_1814_0101_1462_6828, 0}; +#undef pci_ss_info_1462_6828 +#define pci_ss_info_1462_6828 pci_ss_info_1814_0101_1462_6828 +static const pciSubsystemInfo pci_ss_info_1814_0201_1043_130f = + {0x1043, 0x130f, pci_subsys_1814_0201_1043_130f, 0}; +#undef pci_ss_info_1043_130f +#define pci_ss_info_1043_130f pci_ss_info_1814_0201_1043_130f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001e = + {0x1371, 0x001e, pci_subsys_1814_0201_1371_001e, 0}; +#undef pci_ss_info_1371_001e +#define pci_ss_info_1371_001e pci_ss_info_1814_0201_1371_001e +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001f = + {0x1371, 0x001f, pci_subsys_1814_0201_1371_001f, 0}; +#undef pci_ss_info_1371_001f +#define pci_ss_info_1371_001f pci_ss_info_1814_0201_1371_001f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_0020 = + {0x1371, 0x0020, pci_subsys_1814_0201_1371_0020, 0}; +#undef pci_ss_info_1371_0020 +#define pci_ss_info_1371_0020 pci_ss_info_1814_0201_1371_0020 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e381 = + {0x1458, 0xe381, pci_subsys_1814_0201_1458_e381, 0}; +#undef pci_ss_info_1458_e381 +#define pci_ss_info_1458_e381 pci_ss_info_1814_0201_1458_e381 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e931 = + {0x1458, 0xe931, pci_subsys_1814_0201_1458_e931, 0}; +#undef pci_ss_info_1458_e931 +#define pci_ss_info_1458_e931 pci_ss_info_1814_0201_1458_e931 +static const pciSubsystemInfo pci_ss_info_1814_0201_1462_6835 = + {0x1462, 0x6835, pci_subsys_1814_0201_1462_6835, 0}; +#undef pci_ss_info_1462_6835 +#define pci_ss_info_1462_6835 pci_ss_info_1814_0201_1462_6835 +static const pciSubsystemInfo pci_ss_info_1814_0201_1737_0032 = + {0x1737, 0x0032, pci_subsys_1814_0201_1737_0032, 0}; +#undef pci_ss_info_1737_0032 +#define pci_ss_info_1737_0032 pci_ss_info_1814_0201_1737_0032 +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_700a = + {0x1799, 0x700a, pci_subsys_1814_0201_1799_700a, 0}; +#undef pci_ss_info_1799_700a +#define pci_ss_info_1799_700a pci_ss_info_1814_0201_1799_700a +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_701a = + {0x1799, 0x701a, pci_subsys_1814_0201_1799_701a, 0}; +#undef pci_ss_info_1799_701a +#define pci_ss_info_1799_701a pci_ss_info_1814_0201_1799_701a +static const pciSubsystemInfo pci_ss_info_1814_0201_185f_22a0 = + {0x185f, 0x22a0, pci_subsys_1814_0201_185f_22a0, 0}; +#undef pci_ss_info_185f_22a0 +#define pci_ss_info_185f_22a0 pci_ss_info_1814_0201_185f_22a0 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c006_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c006_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c006_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c006_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c006_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c006_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c006_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c006_18ec_d004 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c058_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c058_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c058_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c058_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c058_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c058_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c058_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c058_18ec_d004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_3388_0021_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_3388_0021_4c53_1050 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_3388_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_3388_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_3388_0021_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_3388_0021_4c53_1090 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_3388_0021_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_3388_0021_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3010 = + {0x4c53, 0x3010, pci_subsys_3388_0021_4c53_3010, 0}; +#undef pci_ss_info_4c53_3010 +#define pci_ss_info_4c53_3010 pci_ss_info_3388_0021_4c53_3010 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3011 = + {0x4c53, 0x3011, pci_subsys_3388_0021_4c53_3011, 0}; +#undef pci_ss_info_4c53_3011 +#define pci_ss_info_4c53_3011 pci_ss_info_3388_0021_4c53_3011 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_4000 = + {0x4c53, 0x4000, pci_subsys_3388_0021_4c53_4000, 0}; +#undef pci_ss_info_4c53_4000 +#define pci_ss_info_4c53_4000 pci_ss_info_3388_0021_4c53_4000 +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0002_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0002_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0002_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0003_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0003_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0003_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0006_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0006_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0006_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0006_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0008_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0008_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0008_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0009_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0009_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_3d3d_0009_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_3d3d_0009_13e9_1000 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4009 = + {0x0070, 0x4009, pci_subsys_4444_0016_0070_4009, 0}; +#undef pci_ss_info_0070_4009 +#define pci_ss_info_0070_4009 pci_ss_info_4444_0016_0070_4009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8003 = + {0x0070, 0x8003, pci_subsys_4444_0016_0070_8003, 0}; +#undef pci_ss_info_0070_8003 +#define pci_ss_info_0070_8003 pci_ss_info_4444_0016_0070_8003 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4000 = + {0x0070, 0x4000, pci_subsys_4444_0803_0070_4000, 0}; +#undef pci_ss_info_0070_4000 +#define pci_ss_info_0070_4000 pci_ss_info_4444_0803_0070_4000 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0803_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0803_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3cf = + {0x1461, 0xa3cf, pci_subsys_4444_0803_1461_a3cf, 0}; +#undef pci_ss_info_1461_a3cf +#define pci_ss_info_1461_a3cf pci_ss_info_4444_0803_1461_a3cf +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3000 = + {0x4c53, 0x3000, pci_subsys_4c53_0000_4c53_3000, 0}; +#undef pci_ss_info_4c53_3000 +#define pci_ss_info_4c53_3000 pci_ss_info_4c53_0000_4c53_3000 +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3001 = + {0x4c53, 0x3001, pci_subsys_4c53_0000_4c53_3001, 0}; +#undef pci_ss_info_4c53_3001 +#define pci_ss_info_4c53_3001 pci_ss_info_4c53_0000_4c53_3001 +static const pciSubsystemInfo pci_ss_info_4c53_0001_4c53_3002 = + {0x4c53, 0x3002, pci_subsys_4c53_0001_4c53_3002, 0}; +#undef pci_ss_info_4c53_3002 +#define pci_ss_info_4c53_3002 pci_ss_info_4c53_0001_4c53_3002 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8110 = + {0x1033, 0x8110, pci_subsys_5333_8a22_1033_8110, 0}; +#undef pci_ss_info_1033_8110 +#define pci_ss_info_1033_8110 pci_ss_info_5333_8a22_1033_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c12_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c12_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c12_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01af = + {0x8086, 0x01af, pci_subsys_8086_0600_8086_01af, 0}; +#undef pci_ss_info_8086_01af +#define pci_ss_info_8086_01af pci_ss_info_8086_0600_8086_01af +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01c1 = + {0x8086, 0x01c1, pci_subsys_8086_0600_8086_01c1, 0}; +#undef pci_ss_info_8086_01c1 +#define pci_ss_info_8086_01c1 pci_ss_info_8086_0600_8086_01c1 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01f7 = + {0x8086, 0x01f7, pci_subsys_8086_0600_8086_01f7, 0}; +#undef pci_ss_info_8086_01f7 +#define pci_ss_info_8086_01f7 pci_ss_info_8086_0600_8086_01f7 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1001_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1001_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_1008_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_1008_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_1008_1028_011c = + {0x1028, 0x011c, pci_subsys_8086_1008_1028_011c, 0}; +#undef pci_ss_info_1028_011c +#define pci_ss_info_1028_011c pci_ss_info_8086_1008_1028_011c +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_3108 = + {0x8086, 0x3108, pci_subsys_8086_1008_8086_3108, 0}; +#undef pci_ss_info_8086_3108 +#define pci_ss_info_8086_3108 pci_ss_info_8086_1008_8086_3108 +static const pciSubsystemInfo pci_ss_info_8086_1009_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1009_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1009_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100d_1028_0123 = + {0x1028, 0x0123, pci_subsys_8086_100d_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_8086_100d_1028_0123 +static const pciSubsystemInfo pci_ss_info_8086_100d_1079_891f = + {0x1079, 0x891f, pci_subsys_8086_100d_1079_891f, 0}; +#undef pci_ss_info_1079_891f +#define pci_ss_info_1079_891f pci_ss_info_8086_100d_1079_891f +static const pciSubsystemInfo pci_ss_info_8086_100d_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_100d_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_100d_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_100d_8086_110d = + {0x8086, 0x110d, pci_subsys_8086_100d_8086_110d, 0}; +#undef pci_ss_info_8086_110d +#define pci_ss_info_8086_110d pci_ss_info_8086_100d_8086_110d +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_100e_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_100e_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_100e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_100e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_100e_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_100e_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_100e_1024_0134 = + {0x1024, 0x0134, pci_subsys_8086_100e_1024_0134, 0}; +#undef pci_ss_info_1024_0134 +#define pci_ss_info_1024_0134 pci_ss_info_8086_100e_1024_0134 +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_002e = + {0x1028, 0x002e, pci_subsys_8086_100e_1028_002e, 0}; +#undef pci_ss_info_1028_002e +#define pci_ss_info_1028_002e pci_ss_info_8086_100e_1028_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0151 = + {0x1028, 0x0151, pci_subsys_8086_100e_1028_0151, 0}; +#undef pci_ss_info_1028_0151 +#define pci_ss_info_1028_0151 pci_ss_info_8086_100e_1028_0151 +static const pciSubsystemInfo pci_ss_info_8086_100e_107b_8920 = + {0x107b, 0x8920, pci_subsys_8086_100e_107b_8920, 0}; +#undef pci_ss_info_107b_8920 +#define pci_ss_info_107b_8920 pci_ss_info_8086_100e_107b_8920 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_100e_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_100e_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_100e_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_100e_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_100f_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_100f_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_028e = + {0x1014, 0x028e, pci_subsys_8086_100f_1014_028e, 0}; +#undef pci_ss_info_1014_028e +#define pci_ss_info_1014_028e pci_ss_info_8086_100f_1014_028e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_100f_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_100f_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_0e11_00db = + {0x0e11, 0x00db, pci_subsys_8086_1010_0e11_00db, 0}; +#undef pci_ss_info_0e11_00db +#define pci_ss_info_0e11_00db pci_ss_info_8086_1010_0e11_00db +static const pciSubsystemInfo pci_ss_info_8086_1010_1014_027c = + {0x1014, 0x027c, pci_subsys_8086_1010_1014_027c, 0}; +#undef pci_ss_info_1014_027c +#define pci_ss_info_1014_027c pci_ss_info_8086_1010_1014_027c +static const pciSubsystemInfo pci_ss_info_8086_1010_18fb_7872 = + {0x18fb, 0x7872, pci_subsys_8086_1010_18fb_7872, 0}; +#undef pci_ss_info_18fb_7872 +#define pci_ss_info_18fb_7872 pci_ss_info_8086_1010_18fb_7872 +static const pciSubsystemInfo pci_ss_info_8086_1010_1fc1_0026 = + {0x1fc1, 0x0026, pci_subsys_8086_1010_1fc1_0026, 0}; +#undef pci_ss_info_1fc1_0026 +#define pci_ss_info_1fc1_0026 pci_ss_info_8086_1010_1fc1_0026 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1010_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1010_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_1010_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_1010_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1010_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1010_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_1010_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_1010_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_1010_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_1010_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_1011_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1011_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1011_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1011_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1011_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1012_0e11_00dc = + {0x0e11, 0x00dc, pci_subsys_8086_1012_0e11_00dc, 0}; +#undef pci_ss_info_0e11_00dc +#define pci_ss_info_0e11_00dc pci_ss_info_8086_1012_0e11_00dc +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1013_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1013_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1013_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1013_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1113 = + {0x8086, 0x1113, pci_subsys_8086_1013_8086_1113, 0}; +#undef pci_ss_info_8086_1113 +#define pci_ss_info_8086_1113 pci_ss_info_8086_1013_8086_1113 +static const pciSubsystemInfo pci_ss_info_8086_1016_1014_052c = + {0x1014, 0x052c, pci_subsys_8086_1016_1014_052c, 0}; +#undef pci_ss_info_1014_052c +#define pci_ss_info_1014_052c pci_ss_info_8086_1016_1014_052c +static const pciSubsystemInfo pci_ss_info_8086_1016_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1016_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1016_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1016_8086_1016 = + {0x8086, 0x1016, pci_subsys_8086_1016_8086_1016, 0}; +#undef pci_ss_info_8086_1016 +#define pci_ss_info_8086_1016 pci_ss_info_8086_1016_8086_1016 +static const pciSubsystemInfo pci_ss_info_8086_1017_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1017_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1017_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1018_8086_1018 = + {0x8086, 0x1018, pci_subsys_8086_1018_8086_1018, 0}; +#undef pci_ss_info_8086_1018 +#define pci_ss_info_8086_1018 pci_ss_info_8086_1018_8086_1018 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_1019 = + {0x1458, 0x1019, pci_subsys_8086_1019_1458_1019, 0}; +#undef pci_ss_info_1458_1019 +#define pci_ss_info_1458_1019 pci_ss_info_8086_1019_1458_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_e000 = + {0x1458, 0xe000, pci_subsys_8086_1019_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_8086_1019_1458_e000 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_1019 = + {0x8086, 0x1019, pci_subsys_8086_1019_8086_1019, 0}; +#undef pci_ss_info_8086_1019 +#define pci_ss_info_8086_1019 pci_ss_info_8086_1019_8086_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_301f = + {0x8086, 0x301f, pci_subsys_8086_1019_8086_301f, 0}; +#undef pci_ss_info_8086_301f +#define pci_ss_info_8086_301f pci_ss_info_8086_1019_8086_301f +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1019_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1019_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_101d_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_101d_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_101d_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_101e_1014_0549 = + {0x1014, 0x0549, pci_subsys_8086_101e_1014_0549, 0}; +#undef pci_ss_info_1014_0549 +#define pci_ss_info_1014_0549 pci_ss_info_8086_101e_1014_0549 +static const pciSubsystemInfo pci_ss_info_8086_101e_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_101e_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_101e_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_101e_8086_101e = + {0x8086, 0x101e, pci_subsys_8086_101e_8086_101e, 0}; +#undef pci_ss_info_8086_101e +#define pci_ss_info_8086_101e pci_ss_info_8086_101e_8086_101e +static const pciSubsystemInfo pci_ss_info_8086_1026_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_1026_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_1026_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1026_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1026_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1026_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1026_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1026_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1026_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1026 = + {0x8086, 0x1026, pci_subsys_8086_1026_8086_1026, 0}; +#undef pci_ss_info_8086_1026 +#define pci_ss_info_8086_1026 pci_ss_info_8086_1026_8086_1026 +static const pciSubsystemInfo pci_ss_info_8086_1027_103c_3103 = + {0x103c, 0x3103, pci_subsys_8086_1027_103c_3103, 0}; +#undef pci_ss_info_103c_3103 +#define pci_ss_info_103c_3103 pci_ss_info_8086_1027_103c_3103 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1027_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1027_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1027_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1027_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1027_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1027_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1027 = + {0x8086, 0x1027, pci_subsys_8086_1027_8086_1027, 0}; +#undef pci_ss_info_8086_1027 +#define pci_ss_info_8086_1027 pci_ss_info_8086_1027_8086_1027 +static const pciSubsystemInfo pci_ss_info_8086_1028_8086_1028 = + {0x8086, 0x1028, pci_subsys_8086_1028_8086_1028, 0}; +#undef pci_ss_info_8086_1028 +#define pci_ss_info_8086_1028 pci_ss_info_8086_1028_8086_1028 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1031_813c_104d = + {0x813c, 0x104d, pci_subsys_8086_1031_813c_104d, 0}; +#undef pci_ss_info_813c_104d +#define pci_ss_info_813c_104d pci_ss_info_8086_1031_813c_104d +static const pciSubsystemInfo pci_ss_info_8086_1038_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_8086_1038_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_8086_1038_0e11_0098 +static const pciSubsystemInfo pci_ss_info_8086_1039_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_1039_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_1039_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1043_8086_2527 = + {0x8086, 0x2527, pci_subsys_8086_1043_8086_2527, 0}; +#undef pci_ss_info_8086_2527 +#define pci_ss_info_8086_2527 pci_ss_info_8086_1043_8086_2527 +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a01f = + {0x8086, 0xa01f, pci_subsys_8086_1048_8086_a01f, 0}; +#undef pci_ss_info_8086_a01f +#define pci_ss_info_8086_a01f pci_ss_info_8086_1048_8086_a01f +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a11f = + {0x8086, 0xa11f, pci_subsys_8086_1048_8086_a11f, 0}; +#undef pci_ss_info_8086_a11f +#define pci_ss_info_8086_a11f pci_ss_info_8086_1048_8086_a11f +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_728c = + {0x1462, 0x728c, pci_subsys_8086_1050_1462_728c, 0}; +#undef pci_ss_info_1462_728c +#define pci_ss_info_1462_728c pci_ss_info_8086_1050_1462_728c +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_758c = + {0x1462, 0x758c, pci_subsys_8086_1050_1462_758c, 0}; +#undef pci_ss_info_1462_758c +#define pci_ss_info_1462_758c pci_ss_info_8086_1050_1462_758c +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3020 = + {0x8086, 0x3020, pci_subsys_8086_1050_8086_3020, 0}; +#undef pci_ss_info_8086_3020 +#define pci_ss_info_8086_3020 pci_ss_info_8086_1050_8086_3020 +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_302f = + {0x8086, 0x302f, pci_subsys_8086_1050_8086_302f, 0}; +#undef pci_ss_info_8086_302f +#define pci_ss_info_8086_302f pci_ss_info_8086_1050_8086_302f +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1050_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1050_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_1075_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1075_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1075_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_0075 = + {0x8086, 0x0075, pci_subsys_8086_1075_8086_0075, 0}; +#undef pci_ss_info_8086_0075 +#define pci_ss_info_8086_0075 pci_ss_info_8086_1075_8086_0075 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_1075 = + {0x8086, 0x1075, pci_subsys_8086_1075_8086_1075, 0}; +#undef pci_ss_info_8086_1075 +#define pci_ss_info_8086_1075 pci_ss_info_8086_1075_8086_1075 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1076_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1076_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_1076_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_1076_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_0076 = + {0x8086, 0x0076, pci_subsys_8086_1076_8086_0076, 0}; +#undef pci_ss_info_8086_0076 +#define pci_ss_info_8086_0076 pci_ss_info_8086_1076_8086_0076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1076 = + {0x8086, 0x1076, pci_subsys_8086_1076_8086_1076, 0}; +#undef pci_ss_info_8086_1076 +#define pci_ss_info_8086_1076 pci_ss_info_8086_1076_8086_1076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1176 = + {0x8086, 0x1176, pci_subsys_8086_1076_8086_1176, 0}; +#undef pci_ss_info_8086_1176 +#define pci_ss_info_8086_1176 pci_ss_info_8086_1076_8086_1176 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1276 = + {0x8086, 0x1276, pci_subsys_8086_1076_8086_1276, 0}; +#undef pci_ss_info_8086_1276 +#define pci_ss_info_8086_1276 pci_ss_info_8086_1076_8086_1276 +static const pciSubsystemInfo pci_ss_info_8086_1077_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1077_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1077_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_0077 = + {0x8086, 0x0077, pci_subsys_8086_1077_8086_0077, 0}; +#undef pci_ss_info_8086_0077 +#define pci_ss_info_8086_0077 pci_ss_info_8086_1077_8086_0077 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_1077 = + {0x8086, 0x1077, pci_subsys_8086_1077_8086_1077, 0}; +#undef pci_ss_info_8086_1077 +#define pci_ss_info_8086_1077 pci_ss_info_8086_1077_8086_1077 +static const pciSubsystemInfo pci_ss_info_8086_1078_8086_1078 = + {0x8086, 0x1078, pci_subsys_8086_1078_8086_1078, 0}; +#undef pci_ss_info_8086_1078 +#define pci_ss_info_8086_1078 pci_ss_info_8086_1078_8086_1078 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12a6 = + {0x103c, 0x12a6, pci_subsys_8086_1079_103c_12a6, 0}; +#undef pci_ss_info_103c_12a6 +#define pci_ss_info_103c_12a6 pci_ss_info_8086_1079_103c_12a6 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12cf = + {0x103c, 0x12cf, pci_subsys_8086_1079_103c_12cf, 0}; +#undef pci_ss_info_103c_12cf +#define pci_ss_info_103c_12cf pci_ss_info_8086_1079_103c_12cf +static const pciSubsystemInfo pci_ss_info_8086_1079_1fc1_0027 = + {0x1fc1, 0x0027, pci_subsys_8086_1079_1fc1_0027, 0}; +#undef pci_ss_info_1fc1_0027 +#define pci_ss_info_1fc1_0027 pci_ss_info_8086_1079_1fc1_0027 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1079_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1079_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_1079_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_1079_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_0079 = + {0x8086, 0x0079, pci_subsys_8086_1079_8086_0079, 0}; +#undef pci_ss_info_8086_0079 +#define pci_ss_info_8086_0079 pci_ss_info_8086_1079_8086_0079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1079 = + {0x8086, 0x1079, pci_subsys_8086_1079_8086_1079, 0}; +#undef pci_ss_info_8086_1079 +#define pci_ss_info_8086_1079 pci_ss_info_8086_1079_8086_1079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1179 = + {0x8086, 0x1179, pci_subsys_8086_1079_8086_1179, 0}; +#undef pci_ss_info_8086_1179 +#define pci_ss_info_8086_1179 pci_ss_info_8086_1079_8086_1179 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_117a = + {0x8086, 0x117a, pci_subsys_8086_1079_8086_117a, 0}; +#undef pci_ss_info_8086_117a +#define pci_ss_info_8086_117a pci_ss_info_8086_1079_8086_117a +static const pciSubsystemInfo pci_ss_info_8086_107a_103c_12a8 = + {0x103c, 0x12a8, pci_subsys_8086_107a_103c_12a8, 0}; +#undef pci_ss_info_103c_12a8 +#define pci_ss_info_103c_12a8 pci_ss_info_8086_107a_103c_12a8 +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_107a = + {0x8086, 0x107a, pci_subsys_8086_107a_8086_107a, 0}; +#undef pci_ss_info_8086_107a +#define pci_ss_info_8086_107a pci_ss_info_8086_107a_8086_107a +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_127a = + {0x8086, 0x127a, pci_subsys_8086_107a_8086_127a, 0}; +#undef pci_ss_info_8086_127a +#define pci_ss_info_8086_127a pci_ss_info_8086_107a_8086_127a +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_007b = + {0x8086, 0x007b, pci_subsys_8086_107b_8086_007b, 0}; +#undef pci_ss_info_8086_007b +#define pci_ss_info_8086_007b pci_ss_info_8086_107b_8086_007b +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_107b = + {0x8086, 0x107b, pci_subsys_8086_107b_8086_107b, 0}; +#undef pci_ss_info_8086_107b +#define pci_ss_info_8086_107b pci_ss_info_8086_107b_8086_107b +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1130_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1130_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1130_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1130_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1132_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1132_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_1132_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_1132_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1132_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1132_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_1209_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_1209_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_1209_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_1209_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1070 = + {0x4c53, 0x1070, pci_subsys_8086_1209_4c53_1070, 0}; +#undef pci_ss_info_4c53_1070 +#define pci_ss_info_4c53_1070 pci_ss_info_8086_1209_4c53_1070 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_00ce = + {0x1028, 0x00ce, pci_subsys_8086_1229_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_8086_1229_1028_00ce +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_108e_10cf = + {0x108e, 0x10cf, pci_subsys_8086_1229_108e_10cf, 0}; +#undef pci_ss_info_108e_10cf +#define pci_ss_info_108e_10cf pci_ss_info_8086_1229_108e_10cf +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_110a_008b = + {0x110a, 0x008b, pci_subsys_8086_1229_110a_008b, 0}; +#undef pci_ss_info_110a_008b +#define pci_ss_info_110a_008b pci_ss_info_8086_1229_110a_008b +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_8086_1229_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_8086_1229_13e9_1000 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1229_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1229_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_1229_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_1229_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3411 = + {0x8086, 0x3411, pci_subsys_8086_1229_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_8086_1229_8086_3411 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1461_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1461_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1461_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_8086_1960_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_8086_1960_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_8086_1960_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_8086_1960_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1040 = + {0xe4bf, 0x1040, pci_subsys_8086_1960_e4bf_1040, 0}; +#undef pci_ss_info_e4bf_1040 +#define pci_ss_info_e4bf_1040 pci_ss_info_8086_1960_e4bf_1040 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_3100 = + {0xe4bf, 0x3100, pci_subsys_8086_1960_e4bf_3100, 0}; +#undef pci_ss_info_e4bf_3100 +#define pci_ss_info_e4bf_3100 pci_ss_info_8086_1960_e4bf_3100 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1a30_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_1a30_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_1a30_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_110a_0051 = + {0x110a, 0x0051, pci_subsys_8086_2415_110a_0051, 0}; +#undef pci_ss_info_110a_0051 +#define pci_ss_info_110a_0051 pci_ss_info_8086_2415_110a_0051 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2415_1734_1025 = + {0x1734, 0x1025, pci_subsys_8086_2415_1734_1025, 0}; +#undef pci_ss_info_1734_1025 +#define pci_ss_info_1734_1025 pci_ss_info_8086_2415_1734_1025 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2442_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2442_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2442_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2442_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2442_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2442_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2442_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2442_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2442_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2443_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2443_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2443_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2443_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2443_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2443_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2444_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2444_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2444_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2444_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2444_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2444_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2444_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2445_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2445_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2448_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2448_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2448_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2448_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_2448_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_2448_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_2449_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_2449_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2449_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2449_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_2449_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_2449_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1179_ff01 = + {0x1179, 0xff01, pci_subsys_8086_2449_1179_ff01, 0}; +#undef pci_ss_info_1179_ff01 +#define pci_ss_info_1179_ff01 pci_ss_info_8086_2449_1179_ff01 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_244b_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_244b_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_244b_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_244b_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_244b_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_244b_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_244e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_244e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_244e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2482_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2482_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2482_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2482_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2482_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_2482_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_2482_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2484_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2484_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1013_5959 = + {0x1013, 0x5959, pci_subsys_8086_2485_1013_5959, 0}; +#undef pci_ss_info_1013_5959 +#define pci_ss_info_1013_5959 pci_ss_info_8086_2485_1013_5959 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_101f_1025 = + {0x101f, 0x1025, pci_subsys_8086_2486_101f_1025, 0}; +#undef pci_ss_info_101f_1025 +#define pci_ss_info_101f_1025 pci_ss_info_8086_2486_101f_1025 +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_2486_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_2486_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2487_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2487_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_248a_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_248a_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_248a_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_248a_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c0_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c0_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c2_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c2_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c2_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c2_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c2_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c2_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c2_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c2_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c2_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c2_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c2_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c2_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c2_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c2_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c2_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c2_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c2_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c2_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c2_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c2_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c2_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c2_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c2_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c2_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c2_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c2_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c3_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c3_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c3_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c3_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c3_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c3_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c3_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c3_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c3_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c3_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c3_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c3_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c3_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24c3_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24c3_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c3_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c3_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c3_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c3_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c3_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c4_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c4_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c4_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c4_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c4_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c4_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c4_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c4_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c4_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c4_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c4_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c4_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c4_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c4_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c4_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c4_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c4_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c4_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c4_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c4_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c4_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c4_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c4_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c5_0e11_00b8 = + {0x0e11, 0x00b8, pci_subsys_8086_24c5_0e11_00b8, 0}; +#undef pci_ss_info_0e11_00b8 +#define pci_ss_info_0e11_00b8 pci_ss_info_8086_24c5_0e11_00b8 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c5_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c5_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c5_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c5_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24c5_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24c5_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c5_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c5_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c5_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c5_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c5_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c5_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c5_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c5_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c5_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c5_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24c5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24c5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c5_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c5_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c6_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c6_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c6_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c6_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c6_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c6_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c6_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c6_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c6_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c6_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c6_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c7_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c7_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c7_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c7_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c7_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c7_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c7_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c7_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c7_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c7_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c7_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c7_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c7_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c7_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c7_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c7_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c7_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c7_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c7_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c7_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c7_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c7_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c7_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c7_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24ca_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24ca_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24ca_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24ca_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24ca_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24ca_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24ca_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24ca_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24ca_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24ca_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24ca_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24ca_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24ca_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24ca_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24ca_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24ca_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24ca_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cb_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cb_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cb_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cb_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24cb_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24cb_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cb_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cb_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24cc_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cc_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cc_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cd_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cd_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24cd_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24cd_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cd_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cd_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24cd_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24cd_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24cd_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24cd_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24cd_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24cd_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24cd_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24cd_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24cd_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24cd_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24cd_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24cd_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1509_1968 = + {0x1509, 0x1968, pci_subsys_8086_24cd_1509_1968, 0}; +#undef pci_ss_info_1509_1968 +#define pci_ss_info_1509_1968 pci_ss_info_8086_24cd_1509_1968 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cd_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cd_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cd_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cd_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d1_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d1_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d1_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d1_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d1_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d1_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d1_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d1_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d1_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d1_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1458_24d1 = + {0x1458, 0x24d1, pci_subsys_8086_24d1_1458_24d1, 0}; +#undef pci_ss_info_1458_24d1 +#define pci_ss_info_1458_24d1 pci_ss_info_8086_24d1_1458_24d1 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d1_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d1_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d1_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d1_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d1_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d1_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d1_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d1_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d1_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d1_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d1_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d2_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d2_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d2_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d2_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d2_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d2_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d2_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d2_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d2_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d2_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d2_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d2_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d2_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d2_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d2_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d2_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d2_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d2_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d2_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d2_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d2_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d2_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d2_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d2_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d2_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d2_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d3_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d3_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d3_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d3_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d3_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d3_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d3_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d3_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d3_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d3_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d3_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d3_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d3_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d3_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d3_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d3_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d3_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d4_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d4_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d4_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d4_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d4_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d4_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d4_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d4_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d4_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d4_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d4_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d4_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d4_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d4_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d4_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d4_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d4_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d4_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d4_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d4_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d4_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d4_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d4_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d4_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d4_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d4_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d5_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d5_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d5_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d5_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d5_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_80f3 = + {0x1043, 0x80f3, pci_subsys_8086_24d5_1043_80f3, 0}; +#undef pci_ss_info_1043_80f3 +#define pci_ss_info_1043_80f3 pci_ss_info_8086_24d5_1043_80f3 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_810f = + {0x1043, 0x810f, pci_subsys_8086_24d5_1043_810f, 0}; +#undef pci_ss_info_1043_810f +#define pci_ss_info_1043_810f pci_ss_info_8086_24d5_1043_810f +static const pciSubsystemInfo pci_ss_info_8086_24d5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24d5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24d5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d5_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d5_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_a000 = + {0x8086, 0xa000, pci_subsys_8086_24d5_8086_a000, 0}; +#undef pci_ss_info_8086_a000 +#define pci_ss_info_8086_a000 pci_ss_info_8086_24d5_8086_a000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e000 = + {0x8086, 0xe000, pci_subsys_8086_24d5_8086_e000, 0}; +#undef pci_ss_info_8086_e000 +#define pci_ss_info_8086_e000 pci_ss_info_8086_24d5_8086_e000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e001 = + {0x8086, 0xe001, pci_subsys_8086_24d5_8086_e001, 0}; +#undef pci_ss_info_8086_e001 +#define pci_ss_info_8086_e001 pci_ss_info_8086_24d5_8086_e001 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d7_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d7_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d7_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d7_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d7_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d7_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d7_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d7_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d7_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d7_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d7_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d7_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d7_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d7_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d7_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d7_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d7_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d7_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d7_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d7_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d7_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d7_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d7_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d7_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24db_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24db_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24db_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24db_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24db_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24db_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24db_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24db_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24db_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24db_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24db_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24db_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24db_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24db_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_24db_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_24db_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_24db_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24db_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24db_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24db_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24db_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24db_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_24db = + {0x8086, 0x24db, pci_subsys_8086_24db_8086_24db, 0}; +#undef pci_ss_info_8086_24db +#define pci_ss_info_8086_24db pci_ss_info_8086_24db_8086_24db +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24db_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24db_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24db_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24db_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24db_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24db_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24dd_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24dd_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24dd_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24dd_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24dd_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24dd_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24dd_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24dd_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24dd_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24dd_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24dd_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_24dd_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_24dd_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24dd_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24dd_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24dd_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24dd_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24dd_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24dd_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24dd_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24dd_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24de_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24de_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24de_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24de_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24de_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24de_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24de_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24de_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24de_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24de_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24de_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24de_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24de_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24de_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24de_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24de_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24de_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24de_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24de_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24de_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24de_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24de_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24de_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24de_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2541_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2541_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_2541_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2541_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2541_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2544_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2544_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2544_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_254c_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_254c_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_254c_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_254c_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2560_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_2560_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_2560_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_2560_1458_2560 = + {0x1458, 0x2560, pci_subsys_8086_2560_1458_2560, 0}; +#undef pci_ss_info_1458_2560 +#define pci_ss_info_1458_2560 pci_ss_info_8086_2560_1458_2560 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_2562_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2562_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2562_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2570_1043_80f2 = + {0x1043, 0x80f2, pci_subsys_8086_2570_1043_80f2, 0}; +#undef pci_ss_info_1043_80f2 +#define pci_ss_info_1043_80f2 pci_ss_info_8086_2570_1043_80f2 +static const pciSubsystemInfo pci_ss_info_8086_2570_1458_2570 = + {0x1458, 0x2570, pci_subsys_8086_2570_1458_2570, 0}; +#undef pci_ss_info_1458_2570 +#define pci_ss_info_1458_2570 pci_ss_info_8086_2570_1458_2570 +static const pciSubsystemInfo pci_ss_info_8086_2572_1028_019d = + {0x1028, 0x019d, pci_subsys_8086_2572_1028_019d, 0}; +#undef pci_ss_info_1028_019d +#define pci_ss_info_1028_019d pci_ss_info_8086_2572_1028_019d +static const pciSubsystemInfo pci_ss_info_8086_2572_1043_80a5 = + {0x1043, 0x80a5, pci_subsys_8086_2572_1043_80a5, 0}; +#undef pci_ss_info_1043_80a5 +#define pci_ss_info_1043_80a5 pci_ss_info_8086_2572_1043_80a5 +static const pciSubsystemInfo pci_ss_info_8086_2578_1458_2578 = + {0x1458, 0x2578, pci_subsys_8086_2578_1458_2578, 0}; +#undef pci_ss_info_1458_2578 +#define pci_ss_info_1458_2578 pci_ss_info_8086_2578_1458_2578 +static const pciSubsystemInfo pci_ss_info_8086_2578_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_2578_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_2578_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_2578_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_2578_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_2578_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1458_2580 = + {0x1458, 0x2580, pci_subsys_8086_2580_1458_2580, 0}; +#undef pci_ss_info_1458_2580 +#define pci_ss_info_1458_2580 pci_ss_info_8086_2580_1458_2580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2580_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2580_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2580_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2580_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2580_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2582_1028_1079 = + {0x1028, 0x1079, pci_subsys_8086_2582_1028_1079, 0}; +#undef pci_ss_info_1028_1079 +#define pci_ss_info_1028_1079 pci_ss_info_8086_2582_1028_1079 +static const pciSubsystemInfo pci_ss_info_8086_2582_1458_2582 = + {0x1458, 0x2582, pci_subsys_8086_2582_1458_2582, 0}; +#undef pci_ss_info_1458_2582 +#define pci_ss_info_1458_2582 pci_ss_info_8086_2582_1458_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2582_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2582_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2590_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2590_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2590_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2590_a304_81b7 = + {0xa304, 0x81b7, pci_subsys_8086_2590_a304_81b7, 0}; +#undef pci_ss_info_a304_81b7 +#define pci_ss_info_a304_81b7 pci_ss_info_8086_2590_a304_81b7 +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2592_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2592_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2592_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2592_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2592_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a2_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a2_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a2_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a2_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a3_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a3_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a3_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a3_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a3_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a3_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a4_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a4_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a4_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a4_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a4_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a4_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a6_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a6_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a6_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a9_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a9_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a9_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a9_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a9_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a9_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25aa_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25aa_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25aa_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25aa_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ab_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ab_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ab_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ab_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ab_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ab_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ac_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ac_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ac_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ac_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ac_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ac_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ad_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ad_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ad_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ad_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ad_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ad_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25b0_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25b0_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25b0_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25b0_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_2640_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2640_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2640_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2640_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2640_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2640_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2641_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2641_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2641_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2651_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2651_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2651_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2651_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2651_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2651_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2651_8086_4147 = + {0x8086, 0x4147, pci_subsys_8086_2651_8086_4147, 0}; +#undef pci_ss_info_8086_4147 +#define pci_ss_info_8086_4147 pci_ss_info_8086_2651_8086_4147 +static const pciSubsystemInfo pci_ss_info_8086_2652_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2652_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2652_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2658_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2658_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2658_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2658_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2658_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2658_1458_2558 = + {0x1458, 0x2558, pci_subsys_8086_2658_1458_2558, 0}; +#undef pci_ss_info_1458_2558 +#define pci_ss_info_1458_2558 pci_ss_info_8086_2658_1458_2558 +static const pciSubsystemInfo pci_ss_info_8086_2658_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2658_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2658_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2658_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2658_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2659_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2659_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2659_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2659_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2659_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2659_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2659_1458_2659 = + {0x1458, 0x2659, pci_subsys_8086_2659_1458_2659, 0}; +#undef pci_ss_info_1458_2659 +#define pci_ss_info_1458_2659 pci_ss_info_8086_2659_1458_2659 +static const pciSubsystemInfo pci_ss_info_8086_2659_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2659_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2659_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2659_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2659_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2659_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265a_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265a_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265a_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265a_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265a_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265a_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265b_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265b_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265b_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265b_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265b_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265b_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265b_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265b_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265b_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265b_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265b_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265b_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265b_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265b_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265b_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265c_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265c_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265c_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265c_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265c_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_265c_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_265c_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_265c_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265c_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265c_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265c_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265c_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265c_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2660_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2660_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2660_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266a_1458_266a = + {0x1458, 0x266a, pci_subsys_8086_266a_1458_266a, 0}; +#undef pci_ss_info_1458_266a +#define pci_ss_info_1458_266a pci_ss_info_8086_266a_1458_266a +static const pciSubsystemInfo pci_ss_info_8086_266a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_266d_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266d_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266d_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266e_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266e_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_266e_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_266e_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0188 = + {0x1028, 0x0188, pci_subsys_8086_266e_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_8086_266e_1028_0188 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266e_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_266e_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_266e_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_266e_1734_105a = + {0x1734, 0x105a, pci_subsys_8086_266e_1734_105a, 0}; +#undef pci_ss_info_1734_105a +#define pci_ss_info_1734_105a pci_ss_info_8086_266e_1734_105a +static const pciSubsystemInfo pci_ss_info_8086_266f_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266f_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266f_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266f_1458_266f = + {0x1458, 0x266f, pci_subsys_8086_266f_1458_266f, 0}; +#undef pci_ss_info_1458_266f +#define pci_ss_info_1458_266f pci_ss_info_8086_266f_1458_266f +static const pciSubsystemInfo pci_ss_info_8086_266f_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266f_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266f_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266f_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266f_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266f_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2770_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2770_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2770_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2772_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2772_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2772_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2782_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2782_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2782_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2792_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2792_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2792_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2792_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2792_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2792_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_27b8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27b8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27b8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c0_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c0_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c0_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c9_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c9_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c9_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27ca_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27ca_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27ca_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cb_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cb_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cb_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cc_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cc_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cc_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27da_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27da_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27da_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27dc_8086_308d = + {0x8086, 0x308d, pci_subsys_8086_27dc_8086_308d, 0}; +#undef pci_ss_info_8086_308d +#define pci_ss_info_8086_308d pci_ss_info_8086_27dc_8086_308d +static const pciSubsystemInfo pci_ss_info_8086_27df_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27df_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27df_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_3340_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_3340_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_3340_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_3340_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_3340_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_3340_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_3340_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_3575_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_3575_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_3575_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3580_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3580_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3580_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3580_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3580_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3580_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3580_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3580_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3580_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3580_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3580_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3580_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3580_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3581_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3581_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3581_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3582_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3582_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3582_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3582_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3582_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3582_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3582_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3582_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3584_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3584_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3584_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3584_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3584_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3584_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3584_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3584_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3584_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3584_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3584_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3584_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3584_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3585_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3585_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3585_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3585_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3585_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3585_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3585_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3585_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3585_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3585_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3585_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3585_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3585_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3590_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_3590_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_3590_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_3590_1734_103e = + {0x1734, 0x103e, pci_subsys_8086_3590_1734_103e, 0}; +#undef pci_ss_info_1734_103e +#define pci_ss_info_1734_103e pci_ss_info_8086_3590_1734_103e +static const pciSubsystemInfo pci_ss_info_8086_3590_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3590_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3590_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3591_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_3591_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_3591_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_3591_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3591_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3591_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3594_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3594_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3594_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_359e_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_359e_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_359e_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7110_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7110_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7110_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7111_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7111_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7111_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7112_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7112_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7112_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7113_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7113_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7113_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7120_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7120_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7120_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7120_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7121_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7121_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7121_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7121_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_8086_4341 = + {0x8086, 0x4341, pci_subsys_8086_7121_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_8086_7121_8086_4341 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7190_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7190_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_7190_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_7190_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_7190_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_7190_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7192_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_7192_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_7192_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7194_1033_0000 = + {0x1033, 0x0000, pci_subsys_8086_7194_1033_0000, 0}; +#undef pci_ss_info_1033_0000 +#define pci_ss_info_1033_0000 pci_ss_info_8086_7194_1033_0000 +static const pciSubsystemInfo pci_ss_info_8086_7194_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_7194_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_7194_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_7195_1033_80cc = + {0x1033, 0x80cc, pci_subsys_8086_7195_1033_80cc, 0}; +#undef pci_ss_info_1033_80cc +#define pci_ss_info_1033_80cc pci_ss_info_8086_7195_1033_80cc +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_71a0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_71a0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_71a0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_71a0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_71a2_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_71a2_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_71a2_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0ded = + {0x1993, 0x0ded, pci_subsys_8086_8500_1993_0ded, 0}; +#undef pci_ss_info_1993_0ded +#define pci_ss_info_1993_0ded pci_ss_info_8086_8500_1993_0ded +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0dee = + {0x1993, 0x0dee, pci_subsys_8086_8500_1993_0dee, 0}; +#undef pci_ss_info_1993_0dee +#define pci_ss_info_1993_0dee pci_ss_info_8086_8500_1993_0dee +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0def = + {0x1993, 0x0def, pci_subsys_8086_8500_1993_0def, 0}; +#undef pci_ss_info_1993_0def +#define pci_ss_info_1993_0def pci_ss_info_8086_8500_1993_0def +static const pciSubsystemInfo pci_ss_info_8086_b555_12d9_000a = + {0x12d9, 0x000a, pci_subsys_8086_b555_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_8086_b555_12d9_000a +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_b555_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_b555_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_b555_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_b555_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +static const pciSubsystemInfo pci_ss_info_9004_8178_9004_7881 = + {0x9004, 0x7881, pci_subsys_9004_8178_9004_7881, 0}; +#undef pci_ss_info_9004_7881 +#define pci_ss_info_9004_7881 pci_ss_info_9004_8178_9004_7881 +static const pciSubsystemInfo pci_ss_info_9004_8778_9004_7887 = + {0x9004, 0x7887, pci_subsys_9004_8778_9004_7887, 0}; +#undef pci_ss_info_9004_7887 +#define pci_ss_info_9004_7887 pci_ss_info_9004_8778_9004_7887 +static const pciSubsystemInfo pci_ss_info_9004_8878_9004_7888 = + {0x9004, 0x7888, pci_subsys_9004_8878_9004_7888, 0}; +#undef pci_ss_info_9004_7888 +#define pci_ss_info_9004_7888 pci_ss_info_9004_8878_9004_7888 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_2180 = + {0x9005, 0x2180, pci_subsys_9005_0010_9005_2180, 0}; +#undef pci_ss_info_9005_2180 +#define pci_ss_info_9005_2180 pci_ss_info_9005_0010_9005_2180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_8100 = + {0x9005, 0x8100, pci_subsys_9005_0010_9005_8100, 0}; +#undef pci_ss_info_9005_8100 +#define pci_ss_info_9005_8100 pci_ss_info_9005_0010_9005_8100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a100 = + {0x9005, 0xa100, pci_subsys_9005_0010_9005_a100, 0}; +#undef pci_ss_info_9005_a100 +#define pci_ss_info_9005_a100 pci_ss_info_9005_0010_9005_a100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_0010_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_0010_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_e100 = + {0x9005, 0xe100, pci_subsys_9005_0010_9005_e100, 0}; +#undef pci_ss_info_9005_e100 +#define pci_ss_info_9005_e100 pci_ss_info_9005_0010_9005_e100 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_0003 = + {0x9005, 0x0003, pci_subsys_9005_0013_9005_0003, 0}; +#undef pci_ss_info_9005_0003 +#define pci_ss_info_9005_0003 pci_ss_info_9005_0013_9005_0003 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_0013_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_0013_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_001f_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_f500 = + {0x9005, 0xf500, pci_subsys_9005_0050_9005_f500, 0}; +#undef pci_ss_info_9005_f500 +#define pci_ss_info_9005_f500 pci_ss_info_9005_0050_9005_f500 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0050_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0050_9005_ffff +static const pciSubsystemInfo pci_ss_info_9005_0051_9005_b500 = + {0x9005, 0xb500, pci_subsys_9005_0051_9005_b500, 0}; +#undef pci_ss_info_9005_b500 +#define pci_ss_info_9005_b500 pci_ss_info_9005_0051_9005_b500 +static const pciSubsystemInfo pci_ss_info_9005_0053_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0053_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0053_9005_ffff +#endif +static const pciSubsystemInfo pci_ss_info_9005_0080_0e11_e2a0 = + {0x0e11, 0xe2a0, pci_subsys_9005_0080_0e11_e2a0, 0}; +#undef pci_ss_info_0e11_e2a0 +#define pci_ss_info_0e11_e2a0 pci_ss_info_9005_0080_0e11_e2a0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_6220 = + {0x9005, 0x6220, pci_subsys_9005_0080_9005_6220, 0}; +#undef pci_ss_info_9005_6220 +#define pci_ss_info_9005_6220 pci_ss_info_9005_0080_9005_6220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_62a0 = + {0x9005, 0x62a0, pci_subsys_9005_0080_9005_62a0, 0}; +#undef pci_ss_info_9005_62a0 +#define pci_ss_info_9005_62a0 pci_ss_info_9005_0080_9005_62a0 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e220 = + {0x9005, 0xe220, pci_subsys_9005_0080_9005_e220, 0}; +#undef pci_ss_info_9005_e220 +#define pci_ss_info_9005_e220 pci_ss_info_9005_0080_9005_e220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e2a0 = + {0x9005, 0xe2a0, pci_subsys_9005_0080_9005_e2a0, 0}; +#undef pci_ss_info_9005_e2a0 +#define pci_ss_info_9005_e2a0 pci_ss_info_9005_0080_9005_e2a0 +static const pciSubsystemInfo pci_ss_info_9005_0081_9005_62a1 = + {0x9005, 0x62a1, pci_subsys_9005_0081_9005_62a1, 0}; +#undef pci_ss_info_9005_62a1 +#define pci_ss_info_9005_62a1 pci_ss_info_9005_0081_9005_62a1 +static const pciSubsystemInfo pci_ss_info_9005_008f_1179_0001 = + {0x1179, 0x0001, pci_subsys_9005_008f_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_9005_008f_1179_0001 +static const pciSubsystemInfo pci_ss_info_9005_008f_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_008f_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_008f_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c0_0e11_f620 = + {0x0e11, 0xf620, pci_subsys_9005_00c0_0e11_f620, 0}; +#undef pci_ss_info_0e11_f620 +#define pci_ss_info_0e11_f620 pci_ss_info_9005_00c0_0e11_f620 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00c0_9005_f620 = + {0x9005, 0xf620, pci_subsys_9005_00c0_9005_f620, 0}; +#undef pci_ss_info_9005_f620 +#define pci_ss_info_9005_f620 pci_ss_info_9005_00c0_9005_f620 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_9005_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_9005_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00ce = + {0x1028, 0x00ce, pci_subsys_9005_00cf_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_9005_00cf_1028_00ce +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_9005_00cf_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_9005_00cf_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_9005_00cf_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_9005_00cf_1028_00d9 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00cf_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_9005_00cf_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_9005_00cf_10f1_2462 +static const pciSubsystemInfo pci_ss_info_9005_00cf_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_00cf_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_00cf_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_8086_3411 = + {0x8086, 0x3411, pci_subsys_9005_00cf_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_9005_00cf_8086_3411 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_0279 = + {0x1014, 0x0279, pci_subsys_9005_0250_1014_0279, 0}; +#undef pci_ss_info_1014_0279 +#define pci_ss_info_1014_0279 pci_ss_info_9005_0250_1014_0279 +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_028c = + {0x1014, 0x028c, pci_subsys_9005_0250_1014_028c, 0}; +#undef pci_ss_info_1014_028c +#define pci_ss_info_1014_028c pci_ss_info_9005_0250_1014_028c +static const pciSubsystemInfo pci_ss_info_9005_0283_9005_0283 = + {0x9005, 0x0283, pci_subsys_9005_0283_9005_0283, 0}; +#undef pci_ss_info_9005_0283 +#define pci_ss_info_9005_0283 pci_ss_info_9005_0283_9005_0283 +static const pciSubsystemInfo pci_ss_info_9005_0284_9005_0284 = + {0x9005, 0x0284, pci_subsys_9005_0284_9005_0284, 0}; +#undef pci_ss_info_9005_0284 +#define pci_ss_info_9005_0284 pci_ss_info_9005_0284_9005_0284 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_0e11_0295 = + {0x0e11, 0x0295, pci_subsys_9005_0285_0e11_0295, 0}; +#undef pci_ss_info_0e11_0295 +#define pci_ss_info_0e11_0295 pci_ss_info_9005_0285_0e11_0295 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_1014_02f2 = + {0x1014, 0x02f2, pci_subsys_9005_0285_1014_02f2, 0}; +#undef pci_ss_info_1014_02f2 +#define pci_ss_info_1014_02f2 pci_ss_info_9005_0285_1014_02f2 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0287 = + {0x1028, 0x0287, pci_subsys_9005_0285_1028_0287, 0}; +#undef pci_ss_info_1028_0287 +#define pci_ss_info_1028_0287 pci_ss_info_9005_0285_1028_0287 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0291 = + {0x1028, 0x0291, pci_subsys_9005_0285_1028_0291, 0}; +#undef pci_ss_info_1028_0291 +#define pci_ss_info_1028_0291 pci_ss_info_9005_0285_1028_0291 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_103c_3227 = + {0x103c, 0x3227, pci_subsys_9005_0285_103c_3227, 0}; +#undef pci_ss_info_103c_3227 +#define pci_ss_info_103c_3227 pci_ss_info_9005_0285_103c_3227 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0286 = + {0x17aa, 0x0286, pci_subsys_9005_0285_17aa_0286, 0}; +#undef pci_ss_info_17aa_0286 +#define pci_ss_info_17aa_0286 pci_ss_info_9005_0285_17aa_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0287 = + {0x17aa, 0x0287, pci_subsys_9005_0285_17aa_0287, 0}; +#undef pci_ss_info_17aa_0287 +#define pci_ss_info_17aa_0287 pci_ss_info_9005_0285_17aa_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0285 = + {0x9005, 0x0285, pci_subsys_9005_0285_9005_0285, 0}; +#undef pci_ss_info_9005_0285 +#define pci_ss_info_9005_0285 pci_ss_info_9005_0285_9005_0285 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0286 = + {0x9005, 0x0286, pci_subsys_9005_0285_9005_0286, 0}; +#undef pci_ss_info_9005_0286 +#define pci_ss_info_9005_0286 pci_ss_info_9005_0285_9005_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0287 = + {0x9005, 0x0287, pci_subsys_9005_0285_9005_0287, 0}; +#undef pci_ss_info_9005_0287 +#define pci_ss_info_9005_0287 pci_ss_info_9005_0285_9005_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0288 = + {0x9005, 0x0288, pci_subsys_9005_0285_9005_0288, 0}; +#undef pci_ss_info_9005_0288 +#define pci_ss_info_9005_0288 pci_ss_info_9005_0285_9005_0288 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0289 = + {0x9005, 0x0289, pci_subsys_9005_0285_9005_0289, 0}; +#undef pci_ss_info_9005_0289 +#define pci_ss_info_9005_0289 pci_ss_info_9005_0285_9005_0289 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028a = + {0x9005, 0x028a, pci_subsys_9005_0285_9005_028a, 0}; +#undef pci_ss_info_9005_028a +#define pci_ss_info_9005_028a pci_ss_info_9005_0285_9005_028a +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028b = + {0x9005, 0x028b, pci_subsys_9005_0285_9005_028b, 0}; +#undef pci_ss_info_9005_028b +#define pci_ss_info_9005_028b pci_ss_info_9005_0285_9005_028b +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028e = + {0x9005, 0x028e, pci_subsys_9005_0285_9005_028e, 0}; +#undef pci_ss_info_9005_028e +#define pci_ss_info_9005_028e pci_ss_info_9005_0285_9005_028e +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028f = + {0x9005, 0x028f, pci_subsys_9005_0285_9005_028f, 0}; +#undef pci_ss_info_9005_028f +#define pci_ss_info_9005_028f pci_ss_info_9005_0285_9005_028f +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0290 = + {0x9005, 0x0290, pci_subsys_9005_0285_9005_0290, 0}; +#undef pci_ss_info_9005_0290 +#define pci_ss_info_9005_0290 pci_ss_info_9005_0285_9005_0290 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0292 = + {0x9005, 0x0292, pci_subsys_9005_0285_9005_0292, 0}; +#undef pci_ss_info_9005_0292 +#define pci_ss_info_9005_0292 pci_ss_info_9005_0285_9005_0292 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0293 = + {0x9005, 0x0293, pci_subsys_9005_0285_9005_0293, 0}; +#undef pci_ss_info_9005_0293 +#define pci_ss_info_9005_0293 pci_ss_info_9005_0285_9005_0293 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0294 = + {0x9005, 0x0294, pci_subsys_9005_0285_9005_0294, 0}; +#undef pci_ss_info_9005_0294 +#define pci_ss_info_9005_0294 pci_ss_info_9005_0285_9005_0294 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0296 = + {0x9005, 0x0296, pci_subsys_9005_0285_9005_0296, 0}; +#undef pci_ss_info_9005_0296 +#define pci_ss_info_9005_0296 pci_ss_info_9005_0285_9005_0296 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0297 = + {0x9005, 0x0297, pci_subsys_9005_0285_9005_0297, 0}; +#undef pci_ss_info_9005_0297 +#define pci_ss_info_9005_0297 pci_ss_info_9005_0285_9005_0297 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0298 = + {0x9005, 0x0298, pci_subsys_9005_0285_9005_0298, 0}; +#undef pci_ss_info_9005_0298 +#define pci_ss_info_9005_0298 pci_ss_info_9005_0285_9005_0298 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0299 = + {0x9005, 0x0299, pci_subsys_9005_0285_9005_0299, 0}; +#undef pci_ss_info_9005_0299 +#define pci_ss_info_9005_0299 pci_ss_info_9005_0285_9005_0299 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_029a = + {0x9005, 0x029a, pci_subsys_9005_0285_9005_029a, 0}; +#undef pci_ss_info_9005_029a +#define pci_ss_info_9005_029a pci_ss_info_9005_0285_9005_029a +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9540 = + {0x1014, 0x9540, pci_subsys_9005_0286_1014_9540, 0}; +#undef pci_ss_info_1014_9540 +#define pci_ss_info_1014_9540 pci_ss_info_9005_0286_1014_9540 +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9580 = + {0x1014, 0x9580, pci_subsys_9005_0286_1014_9580, 0}; +#undef pci_ss_info_1014_9580 +#define pci_ss_info_1014_9580 pci_ss_info_9005_0286_1014_9580 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028c = + {0x9005, 0x028c, pci_subsys_9005_0286_9005_028c, 0}; +#undef pci_ss_info_9005_028c +#define pci_ss_info_9005_028c pci_ss_info_9005_0286_9005_028c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028d = + {0x9005, 0x028d, pci_subsys_9005_0286_9005_028d, 0}; +#undef pci_ss_info_9005_028d +#define pci_ss_info_9005_028d pci_ss_info_9005_0286_9005_028d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029b = + {0x9005, 0x029b, pci_subsys_9005_0286_9005_029b, 0}; +#undef pci_ss_info_9005_029b +#define pci_ss_info_9005_029b pci_ss_info_9005_0286_9005_029b +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029c = + {0x9005, 0x029c, pci_subsys_9005_0286_9005_029c, 0}; +#undef pci_ss_info_9005_029c +#define pci_ss_info_9005_029c pci_ss_info_9005_0286_9005_029c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029d = + {0x9005, 0x029d, pci_subsys_9005_0286_9005_029d, 0}; +#undef pci_ss_info_9005_029d +#define pci_ss_info_9005_029d pci_ss_info_9005_0286_9005_029d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029e = + {0x9005, 0x029e, pci_subsys_9005_0286_9005_029e, 0}; +#undef pci_ss_info_9005_029e +#define pci_ss_info_9005_029e pci_ss_info_9005_0286_9005_029e +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029f = + {0x9005, 0x029f, pci_subsys_9005_0286_9005_029f, 0}; +#undef pci_ss_info_9005_029f +#define pci_ss_info_9005_029f pci_ss_info_9005_0286_9005_029f +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a0 = + {0x9005, 0x02a0, pci_subsys_9005_0286_9005_02a0, 0}; +#undef pci_ss_info_9005_02a0 +#define pci_ss_info_9005_02a0 pci_ss_info_9005_0286_9005_02a0 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a1 = + {0x9005, 0x02a1, pci_subsys_9005_0286_9005_02a1, 0}; +#undef pci_ss_info_9005_02a1 +#define pci_ss_info_9005_02a1 pci_ss_info_9005_0286_9005_02a1 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a2 = + {0x9005, 0x02a2, pci_subsys_9005_0286_9005_02a2, 0}; +#undef pci_ss_info_9005_02a2 +#define pci_ss_info_9005_02a2 pci_ss_info_9005_0286_9005_02a2 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a3 = + {0x9005, 0x02a3, pci_subsys_9005_0286_9005_02a3, 0}; +#undef pci_ss_info_9005_02a3 +#define pci_ss_info_9005_02a3 pci_ss_info_9005_0286_9005_02a3 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a4 = + {0x9005, 0x02a4, pci_subsys_9005_0286_9005_02a4, 0}; +#undef pci_ss_info_9005_02a4 +#define pci_ss_info_9005_02a4 pci_ss_info_9005_0286_9005_02a4 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a5 = + {0x9005, 0x02a5, pci_subsys_9005_0286_9005_02a5, 0}; +#undef pci_ss_info_9005_02a5 +#define pci_ss_info_9005_02a5 pci_ss_info_9005_0286_9005_02a5 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a6 = + {0x9005, 0x02a6, pci_subsys_9005_0286_9005_02a6, 0}; +#undef pci_ss_info_9005_02a6 +#define pci_ss_info_9005_02a6 pci_ss_info_9005_0286_9005_02a6 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_0800 = + {0x9005, 0x0800, pci_subsys_9005_0286_9005_0800, 0}; +#undef pci_ss_info_9005_0800 +#define pci_ss_info_9005_0800 pci_ss_info_9005_0286_9005_0800 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_9005_0500_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_9005_0500_1014_02c1 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_9005_0500_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_9005_0500_1014_02c2 +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02bf = + {0x1014, 0x02bf, pci_subsys_9005_0503_1014_02bf, 0}; +#undef pci_ss_info_1014_02bf +#define pci_ss_info_1014_02bf pci_ss_info_9005_0503_1014_02bf +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02d5 = + {0x1014, 0x02d5, pci_subsys_9005_0503_1014_02d5, 0}; +#undef pci_ss_info_1014_02d5 +#define pci_ss_info_1014_02d5 pci_ss_info_9005_0503_1014_02d5 +#endif +static const pciSubsystemInfo pci_ss_info_9005_8011_0e11_00ac = + {0x0e11, 0x00ac, pci_subsys_9005_8011_0e11_00ac, 0}; +#undef pci_ss_info_0e11_00ac +#define pci_ss_info_0e11_00ac pci_ss_info_9005_8011_0e11_00ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_8011_9005_0041 = + {0x9005, 0x0041, pci_subsys_9005_8011_9005_0041, 0}; +#undef pci_ss_info_9005_0041 +#define pci_ss_info_9005_0041 pci_ss_info_9005_8011_9005_0041 +static const pciSubsystemInfo pci_ss_info_9005_801f_1734_1011 = + {0x1734, 0x1011, pci_subsys_9005_801f_1734_1011, 0}; +#undef pci_ss_info_1734_1011 +#define pci_ss_info_1734_1011 pci_ss_info_9005_801f_1734_1011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9710_9815_1000_0020 = + {0x1000, 0x0020, pci_subsys_9710_9815_1000_0020, 0}; +#undef pci_ss_info_1000_0020 +#define pci_ss_info_1000_0020 pci_ss_info_9710_9815_1000_0020 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0002 = + {0x1000, 0x0002, pci_subsys_9710_9835_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_9710_9835_1000_0002 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0012 = + {0x1000, 0x0012, pci_subsys_9710_9835_1000_0012, 0}; +#undef pci_ss_info_1000_0012 +#define pci_ss_info_1000_0012 pci_ss_info_9710_9835_1000_0012 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0004 = + {0x1000, 0x0004, pci_subsys_9710_9845_1000_0004, 0}; +#undef pci_ss_info_1000_0004 +#define pci_ss_info_1000_0004 pci_ss_info_9710_9845_1000_0004 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0006 = + {0x1000, 0x0006, pci_subsys_9710_9845_1000_0006, 0}; +#undef pci_ss_info_1000_0006 +#define pci_ss_info_1000_0006 pci_ss_info_9710_9845_1000_0006 +static const pciSubsystemInfo pci_ss_info_9710_9855_1000_0014 = + {0x1000, 0x0014, pci_subsys_9710_9855_1000_0014, 0}; +#undef pci_ss_info_1000_0014 +#define pci_ss_info_1000_0014 pci_ss_info_9710_9855_1000_0014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0001 = + {0x0059, 0x0001, pci_subsys_e159_0001_0059_0001, 0}; +#undef pci_ss_info_0059_0001 +#define pci_ss_info_0059_0001 pci_ss_info_e159_0001_0059_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0003 = + {0x0059, 0x0003, pci_subsys_e159_0001_0059_0003, 0}; +#undef pci_ss_info_0059_0003 +#define pci_ss_info_0059_0003 pci_ss_info_e159_0001_0059_0003 +static const pciSubsystemInfo pci_ss_info_e159_0001_00a7_0001 = + {0x00a7, 0x0001, pci_subsys_e159_0001_00a7_0001, 0}; +#undef pci_ss_info_00a7_0001 +#define pci_ss_info_00a7_0001 pci_ss_info_e159_0001_00a7_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_6159_0001 = + {0x6159, 0x0001, pci_subsys_e159_0001_6159_0001, 0}; +#undef pci_ss_info_6159_0001 +#define pci_ss_info_6159_0001 pci_ss_info_e159_0001_6159_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_79fe_0001 = + {0x79fe, 0x0001, pci_subsys_e159_0001_79fe_0001, 0}; +#undef pci_ss_info_79fe_0001 +#define pci_ss_info_79fe_0001 pci_ss_info_e159_0001_79fe_0001 +#endif +static const pciSubsystemInfo pci_ss_info_e159_0001_8086_0003 = + {0x8086, 0x0003, pci_subsys_e159_0001_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_e159_0001_8086_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_b1b9_0001 = + {0xb1b9, 0x0001, pci_subsys_e159_0001_b1b9_0001, 0}; +#undef pci_ss_info_b1b9_0001 +#define pci_ss_info_b1b9_0001 pci_ss_info_e159_0001_b1b9_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_b1b9_0003 = + {0xb1b9, 0x0003, pci_subsys_e159_0001_b1b9_0003, 0}; +#undef pci_ss_info_b1b9_0003 +#define pci_ss_info_b1b9_0003 pci_ss_info_e159_0001_b1b9_0003 +#endif +#define pci_ss_list_0070_0003 NULL +#define pci_ss_list_0070_0009 NULL +#define pci_ss_list_0070_0801 NULL +#define pci_ss_list_0070_0807 NULL +#define pci_ss_list_0070_4000 NULL +#define pci_ss_list_0070_4001 NULL +#define pci_ss_list_0070_4009 NULL +#define pci_ss_list_0070_4800 NULL +#define pci_ss_list_0070_4801 NULL +#define pci_ss_list_0070_4803 NULL +#define pci_ss_list_0070_8003 NULL +#define pci_ss_list_0070_8801 NULL +#define pci_ss_list_0070_c801 NULL +#define pci_ss_list_0070_e807 NULL +#define pci_ss_list_0070_e817 NULL +#define pci_ss_list_0095_0680 NULL +#define pci_ss_list_018a_0106 NULL +#define pci_ss_list_021b_8139 NULL +#define pci_ss_list_0270_0801 NULL +#define pci_ss_list_0291_8212 NULL +#define pci_ss_list_02ac_1012 NULL +#define pci_ss_list_0357_000a NULL +#define pci_ss_list_0432_0001 NULL +#define pci_ss_list_045e_006e NULL +#define pci_ss_list_045e_00c2 NULL +#define pci_ss_list_04cf_8818 NULL +#define pci_ss_list_05e3_0701 NULL +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_0675_1703 NULL +#define pci_ss_list_0675_1704 NULL +#define pci_ss_list_067b_3507 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0b49_064f NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_0046[] = { + &pci_ss_info_0e11_0046_0e11_409a, + &pci_ss_info_0e11_0046_0e11_409b, + &pci_ss_info_0e11_0046_0e11_409c, + &pci_ss_info_0e11_0046_0e11_409d, + NULL +}; +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_005a NULL +#define pci_ss_list_0e11_007c NULL +#define pci_ss_list_0e11_007d NULL +#define pci_ss_list_0e11_0085 NULL +#define pci_ss_list_0e11_00b1 NULL +#define pci_ss_list_0e11_00bb NULL +#define pci_ss_list_0e11_00ca NULL +#define pci_ss_list_0e11_00cb NULL +#define pci_ss_list_0e11_00cf NULL +#define pci_ss_list_0e11_00d0 NULL +#define pci_ss_list_0e11_00d1 NULL +#define pci_ss_list_0e11_00e3 NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_4030 NULL +#define pci_ss_list_0e11_4031 NULL +#define pci_ss_list_0e11_4032 NULL +#define pci_ss_list_0e11_4033 NULL +#define pci_ss_list_0e11_4034 NULL +#define pci_ss_list_0e11_4040 NULL +#define pci_ss_list_0e11_4048 NULL +#define pci_ss_list_0e11_4050 NULL +#define pci_ss_list_0e11_4051 NULL +#define pci_ss_list_0e11_4058 NULL +#define pci_ss_list_0e11_4070 NULL +#define pci_ss_list_0e11_4080 NULL +#define pci_ss_list_0e11_4082 NULL +#define pci_ss_list_0e11_4083 NULL +#define pci_ss_list_0e11_4091 NULL +#define pci_ss_list_0e11_409a NULL +#define pci_ss_list_0e11_409b NULL +#define pci_ss_list_0e11_409c NULL +#define pci_ss_list_0e11_409d NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_b178[] = { + &pci_ss_info_0e11_b178_0e11_4080, + &pci_ss_info_0e11_b178_0e11_4082, + &pci_ss_info_0e11_b178_0e11_4083, + NULL +}; +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_b200 NULL +#define pci_ss_list_0e11_b203 NULL +#define pci_ss_list_0e11_b204 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0003[] = { + &pci_ss_info_1000_0003_1000_1000, + NULL +}; +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0006[] = { + &pci_ss_info_1000_0006_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000a[] = { + &pci_ss_info_1000_000a_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000b[] = { + &pci_ss_info_1000_000b_0e11_6004, + &pci_ss_info_1000_000b_1000_1000, + &pci_ss_info_1000_000b_1000_1010, + &pci_ss_info_1000_000b_1000_1020, + &pci_ss_info_1000_000b_13e9_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1000_1010, + &pci_ss_info_1000_000c_1000_1020, + &pci_ss_info_1000_000c_1de1_3906, + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1000_1000, + &pci_ss_info_1000_000f_1000_1010, + &pci_ss_info_1000_000f_1000_1020, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1de1_3904, + &pci_ss_info_1000_000f_4c53_1000, + &pci_ss_info_1000_000f_4c53_1050, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + &pci_ss_info_1000_0010_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0012[] = { + &pci_ss_info_1000_0012_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0013[] = { + &pci_ss_info_1000_0013_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1000_1000, + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0021[] = { + &pci_ss_info_1000_0021_1000_1000, + &pci_ss_info_1000_0021_1000_1010, + &pci_ss_info_1000_0021_124b_1070, + &pci_ss_info_1000_0021_4c53_1080, + &pci_ss_info_1000_0021_4c53_1300, + &pci_ss_info_1000_0021_4c53_1310, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_0e11_00da, + &pci_ss_info_1000_0030_1028_0123, + &pci_ss_info_1000_0030_1028_014a, + &pci_ss_info_1000_0030_1028_016c, + &pci_ss_info_1000_0030_1028_0183, + &pci_ss_info_1000_0030_1028_1010, + &pci_ss_info_1000_0030_124b_1170, + &pci_ss_info_1000_0030_1734_1052, + NULL +}; +#define pci_ss_list_1000_0031 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0032[] = { + &pci_ss_info_1000_0032_1000_1000, + NULL +}; +#define pci_ss_list_1000_0033 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0040[] = { + &pci_ss_info_1000_0040_1000_0033, + &pci_ss_info_1000_0040_1000_0066, + NULL +}; +#define pci_ss_list_1000_0041 NULL +#define pci_ss_list_1000_0050 NULL +#define pci_ss_list_1000_0054 NULL +#define pci_ss_list_1000_0056 NULL +#define pci_ss_list_1000_0058 NULL +#define pci_ss_list_1000_005a NULL +#define pci_ss_list_1000_005c NULL +#define pci_ss_list_1000_005e NULL +#define pci_ss_list_1000_0060 NULL +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0407[] = { + &pci_ss_info_1000_0407_1000_0530, + &pci_ss_info_1000_0407_1000_0531, + &pci_ss_info_1000_0407_1000_0532, + &pci_ss_info_1000_0407_1028_0531, + &pci_ss_info_1000_0407_1028_0533, + &pci_ss_info_1000_0407_8086_0530, + &pci_ss_info_1000_0407_8086_0532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0408[] = { + &pci_ss_info_1000_0408_1000_0001, + &pci_ss_info_1000_0408_1000_0002, + &pci_ss_info_1000_0408_1025_004d, + &pci_ss_info_1000_0408_1028_0001, + &pci_ss_info_1000_0408_1028_0002, + &pci_ss_info_1000_0408_1734_1065, + &pci_ss_info_1000_0408_8086_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0409[] = { + &pci_ss_info_1000_0409_1000_3004, + &pci_ss_info_1000_0409_1000_3008, + &pci_ss_info_1000_0409_8086_3008, + &pci_ss_info_1000_0409_8086_3431, + &pci_ss_info_1000_0409_8086_3499, + NULL +}; +#define pci_ss_list_1000_0621 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0622[] = { + &pci_ss_info_1000_0622_1000_1020, + NULL +}; +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0626[] = { + &pci_ss_info_1000_0626_1000_1010, + NULL +}; +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0640 NULL +#define pci_ss_list_1000_0642 NULL +#define pci_ss_list_1000_0646 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0804 NULL +#define pci_ss_list_1000_0805 NULL +#define pci_ss_list_1000_0806 NULL +#define pci_ss_list_1000_0807 NULL +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1000_0518, + &pci_ss_info_1000_1960_1000_0520, + &pci_ss_info_1000_1960_1000_0522, + &pci_ss_info_1000_1960_1000_0523, + &pci_ss_info_1000_1960_1000_4523, + &pci_ss_info_1000_1960_1000_a520, + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + &pci_ss_info_1000_1960_1028_0533, + &pci_ss_info_1000_1960_8086_0520, + &pci_ss_info_1000_1960_8086_0523, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_3150 NULL +#define pci_ss_list_1002_3152 NULL +#define pci_ss_list_1002_3154 NULL +#define pci_ss_list_1002_3e50 NULL +#define pci_ss_list_1002_3e54 NULL +#define pci_ss_list_1002_3e70 NULL +#define pci_ss_list_1002_4136 NULL +#define pci_ss_list_1002_4137 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4148 NULL +#define pci_ss_list_1002_4149 NULL +#define pci_ss_list_1002_414a NULL +#define pci_ss_list_1002_414b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4150[] = { + &pci_ss_info_1002_4150_1002_0002, + &pci_ss_info_1002_4150_1002_0003, + &pci_ss_info_1002_4150_1458_4024, + &pci_ss_info_1002_4150_148c_2064, + &pci_ss_info_1002_4150_148c_2066, + &pci_ss_info_1002_4150_174b_7c19, + &pci_ss_info_1002_4150_174b_7c29, + &pci_ss_info_1002_4150_17ee_2002, + &pci_ss_info_1002_4150_18bc_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4151[] = { + &pci_ss_info_1002_4151_1043_c004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4152[] = { + &pci_ss_info_1002_4152_1002_0002, + &pci_ss_info_1002_4152_1002_4772, + &pci_ss_info_1002_4152_1043_c002, + &pci_ss_info_1002_4152_1043_c01a, + &pci_ss_info_1002_4152_174b_7c29, + &pci_ss_info_1002_4152_1787_4002, + NULL +}; +#define pci_ss_list_1002_4153 NULL +#define pci_ss_list_1002_4154 NULL +#define pci_ss_list_1002_4155 NULL +#define pci_ss_list_1002_4156 NULL +#define pci_ss_list_1002_4157 NULL +#define pci_ss_list_1002_4158 NULL +#define pci_ss_list_1002_4164 NULL +#define pci_ss_list_1002_4165 NULL +#define pci_ss_list_1002_4166 NULL +#define pci_ss_list_1002_4168 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4170[] = { + &pci_ss_info_1002_4170_1002_0003, + &pci_ss_info_1002_4170_1458_4025, + &pci_ss_info_1002_4170_148c_2067, + &pci_ss_info_1002_4170_174b_7c28, + &pci_ss_info_1002_4170_17ee_2003, + &pci_ss_info_1002_4170_18bc_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4171[] = { + &pci_ss_info_1002_4171_1043_c005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4172[] = { + &pci_ss_info_1002_4172_1002_0003, + &pci_ss_info_1002_4172_1002_4773, + &pci_ss_info_1002_4172_1043_c003, + &pci_ss_info_1002_4172_1043_c01b, + &pci_ss_info_1002_4172_174b_7c28, + &pci_ss_info_1002_4172_1787_4003, + NULL +}; +#define pci_ss_list_1002_4173 NULL +#define pci_ss_list_1002_4237 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4243 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4336[] = { + &pci_ss_info_1002_4336_1002_4336, + &pci_ss_info_1002_4336_103c_0024, + &pci_ss_info_1002_4336_161f_2029, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4337[] = { + &pci_ss_info_1002_4337_1014_053a, + &pci_ss_info_1002_4337_103c_0850, + NULL +}; +#define pci_ss_list_1002_4341 NULL +#define pci_ss_list_1002_4345 NULL +#define pci_ss_list_1002_4347 NULL +#define pci_ss_list_1002_4348 NULL +#define pci_ss_list_1002_4349 NULL +#define pci_ss_list_1002_434d NULL +#define pci_ss_list_1002_4353 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4363 NULL +#define pci_ss_list_1002_436e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4370[] = { + &pci_ss_info_1002_4370_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4371[] = { + &pci_ss_info_1002_4371_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4372[] = { + &pci_ss_info_1002_4372_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4373[] = { + &pci_ss_info_1002_4373_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4374[] = { + &pci_ss_info_1002_4374_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4375[] = { + &pci_ss_info_1002_4375_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4376[] = { + &pci_ss_info_1002_4376_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4377[] = { + &pci_ss_info_1002_4377_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4378[] = { + &pci_ss_info_1002_4378_103c_308b, + NULL +}; +#define pci_ss_list_1002_4379 NULL +#define pci_ss_list_1002_437a NULL +#define pci_ss_list_1002_4437 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00ce, + &pci_ss_info_1002_4752_1028_00d1, + &pci_ss_info_1002_4752_1028_00d9, + &pci_ss_info_1002_4752_1028_0134, + &pci_ss_info_1002_4752_1734_007a, + &pci_ss_info_1002_4752_8086_3411, + &pci_ss_info_1002_4752_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0084, + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +#define pci_ss_list_1002_4a48 NULL +#define pci_ss_list_1002_4a49 NULL +#define pci_ss_list_1002_4a4a NULL +#define pci_ss_list_1002_4a4b NULL +#define pci_ss_list_1002_4a4c NULL +#define pci_ss_list_1002_4a4d NULL +#define pci_ss_list_1002_4a4e NULL +#define pci_ss_list_1002_4a50 NULL +#define pci_ss_list_1002_4a70 NULL +#define pci_ss_list_1002_4b49 NULL +#define pci_ss_list_1002_4b4b NULL +#define pci_ss_list_1002_4b4c NULL +#define pci_ss_list_1002_4b69 NULL +#define pci_ss_list_1002_4b6b NULL +#define pci_ss_list_1002_4b6c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e7, + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c46[] = { + &pci_ss_info_1002_4c46_1028_00b1, + NULL +}; +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_0e11_b160, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + &pci_ss_info_1002_4c4d_1028_00aa, + &pci_ss_info_1002_4c4d_1028_00bb, + &pci_ss_info_1002_4c4d_10e1_10cf, + &pci_ss_info_1002_4c4d_13bd_1019, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c52[] = { + &pci_ss_info_1002_4c52_1033_8112, + NULL +}; +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_1028_012a, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_0e11_b111, + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + &pci_ss_info_1002_4c59_1509_1930, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4c6e NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e44[] = { + &pci_ss_info_1002_4e44_1002_515e, + &pci_ss_info_1002_4e44_1002_5965, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4e45[] = { + &pci_ss_info_1002_4e45_1002_0002, + &pci_ss_info_1002_4e45_1681_0002, + NULL +}; +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e48 NULL +#define pci_ss_list_1002_4e49 NULL +#define pci_ss_list_1002_4e4a NULL +#define pci_ss_list_1002_4e4b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e50[] = { + &pci_ss_info_1002_4e50_1025_005a, + &pci_ss_info_1002_4e50_103c_088c, + &pci_ss_info_1002_4e50_103c_0890, + &pci_ss_info_1002_4e50_1734_1055, + NULL +}; +#define pci_ss_list_1002_4e51 NULL +#define pci_ss_list_1002_4e52 NULL +#define pci_ss_list_1002_4e53 NULL +#define pci_ss_list_1002_4e54 NULL +#define pci_ss_list_1002_4e56 NULL +#define pci_ss_list_1002_4e64 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e65[] = { + &pci_ss_info_1002_4e65_1002_0003, + &pci_ss_info_1002_4e65_1681_0003, + NULL +}; +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_4e68 NULL +#define pci_ss_list_1002_4e69 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e6a[] = { + &pci_ss_info_1002_4e6a_1002_4e71, + NULL +}; +#define pci_ss_list_1002_4e71 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_1681_0010, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +#define pci_ss_list_1002_5154 NULL +#define pci_ss_list_1002_5155 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1002_103a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7146, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1028_019a, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_174b_7c28, + &pci_ss_info_1002_5159_1787_0202, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_515e NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5346[] = { + &pci_ss_info_1002_5346_1002_0048, + NULL +}; +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +#define pci_ss_list_1002_5460 NULL +#define pci_ss_list_1002_5464 NULL +#define pci_ss_list_1002_5548 NULL +#define pci_ss_list_1002_5549 NULL +#define pci_ss_list_1002_554a NULL +#define pci_ss_list_1002_554b NULL +#define pci_ss_list_1002_554d NULL +#define pci_ss_list_1002_554f NULL +#define pci_ss_list_1002_5550 NULL +#define pci_ss_list_1002_5551 NULL +#define pci_ss_list_1002_5552 NULL +#define pci_ss_list_1002_5554 NULL +#define pci_ss_list_1002_556b NULL +#define pci_ss_list_1002_556d NULL +#define pci_ss_list_1002_556f NULL +#define pci_ss_list_1002_564a NULL +#define pci_ss_list_1002_564b NULL +#define pci_ss_list_1002_5652 NULL +#define pci_ss_list_1002_5653 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_5830 NULL +#define pci_ss_list_1002_5831 NULL +#define pci_ss_list_1002_5832 NULL +#define pci_ss_list_1002_5833 NULL +#define pci_ss_list_1002_5834 NULL +#define pci_ss_list_1002_5835 NULL +#define pci_ss_list_1002_5838 NULL +#define pci_ss_list_1002_5940 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5941[] = { + &pci_ss_info_1002_5941_1458_4019, + &pci_ss_info_1002_5941_174b_7c12, + &pci_ss_info_1002_5941_17af_200d, + &pci_ss_info_1002_5941_18bc_0050, + NULL +}; +#define pci_ss_list_1002_5944 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5950[] = { + &pci_ss_info_1002_5950_103c_308b, + NULL +}; +#define pci_ss_list_1002_5951 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5954[] = { + &pci_ss_info_1002_5954_1002_5954, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5955[] = { + &pci_ss_info_1002_5955_1002_5955, + &pci_ss_info_1002_5955_103c_308b, + NULL +}; +#define pci_ss_list_1002_5960 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5961[] = { + &pci_ss_info_1002_5961_1002_2f72, + &pci_ss_info_1002_5961_1019_4c30, + &pci_ss_info_1002_5961_12ab_5961, + &pci_ss_info_1002_5961_1458_4018, + &pci_ss_info_1002_5961_174b_7c13, + &pci_ss_info_1002_5961_17af_200c, + &pci_ss_info_1002_5961_18bc_0050, + &pci_ss_info_1002_5961_18bc_0051, + &pci_ss_info_1002_5961_18bc_0053, + NULL +}; +#define pci_ss_list_1002_5962 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5964[] = { + &pci_ss_info_1002_5964_1043_c006, + &pci_ss_info_1002_5964_1458_4018, + &pci_ss_info_1002_5964_147b_6191, + &pci_ss_info_1002_5964_148c_2073, + &pci_ss_info_1002_5964_174b_7c13, + &pci_ss_info_1002_5964_1787_5964, + &pci_ss_info_1002_5964_17af_2012, + &pci_ss_info_1002_5964_18bc_0170, + &pci_ss_info_1002_5964_18bc_0173, + NULL +}; +#define pci_ss_list_1002_5969 NULL +#define pci_ss_list_1002_5974 NULL +#define pci_ss_list_1002_5975 NULL +#define pci_ss_list_1002_5a34 NULL +#define pci_ss_list_1002_5a41 NULL +#define pci_ss_list_1002_5a42 NULL +#define pci_ss_list_1002_5a61 NULL +#define pci_ss_list_1002_5a62 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b60[] = { + &pci_ss_info_1002_5b60_1043_002a, + &pci_ss_info_1002_5b60_1043_032e, + NULL +}; +#define pci_ss_list_1002_5b62 NULL +#define pci_ss_list_1002_5b63 NULL +#define pci_ss_list_1002_5b64 NULL +#define pci_ss_list_1002_5b65 NULL +#define pci_ss_list_1002_5b70 NULL +#define pci_ss_list_1002_5b72 NULL +#define pci_ss_list_1002_5b73 NULL +#define pci_ss_list_1002_5b74 NULL +#define pci_ss_list_1002_5c61 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5c63[] = { + &pci_ss_info_1002_5c63_1002_5c63, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5d44[] = { + &pci_ss_info_1002_5d44_1458_4019, + &pci_ss_info_1002_5d44_174b_7c12, + &pci_ss_info_1002_5d44_1787_5965, + &pci_ss_info_1002_5d44_17af_2013, + &pci_ss_info_1002_5d44_18bc_0171, + &pci_ss_info_1002_5d44_18bc_0172, + NULL +}; +#define pci_ss_list_1002_5d48 NULL +#define pci_ss_list_1002_5d49 NULL +#define pci_ss_list_1002_5d4a NULL +#define pci_ss_list_1002_5d4d NULL +static const pciSubsystemInfo *pci_ss_list_1002_5d52[] = { + &pci_ss_info_1002_5d52_1002_0b12, + &pci_ss_info_1002_5d52_1002_0b13, + NULL +}; +#define pci_ss_list_1002_5d57 NULL +#define pci_ss_list_1002_5d6d NULL +#define pci_ss_list_1002_5d72 NULL +#define pci_ss_list_1002_5d77 NULL +#define pci_ss_list_1002_5e48 NULL +#define pci_ss_list_1002_5e49 NULL +#define pci_ss_list_1002_5e4a NULL +#define pci_ss_list_1002_5e4b NULL +#define pci_ss_list_1002_5e4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e4d[] = { + &pci_ss_info_1002_5e4d_148c_2116, + NULL +}; +#define pci_ss_list_1002_5e4f NULL +#define pci_ss_list_1002_5e6b NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e6d[] = { + &pci_ss_info_1002_5e6d_148c_2117, + NULL +}; +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1002_7010 NULL +#define pci_ss_list_1002_7105 NULL +#define pci_ss_list_1002_7109 NULL +#define pci_ss_list_1002_7833 NULL +#define pci_ss_list_1002_7834 NULL +#define pci_ss_list_1002_7835 NULL +#define pci_ss_list_1002_7838 NULL +#define pci_ss_list_1002_7c37 NULL +#define pci_ss_list_1002_cab0 NULL +#define pci_ss_list_1002_cab2 NULL +#define pci_ss_list_1002_cab3 NULL +#define pci_ss_list_1002_cbb2 NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +static const pciSubsystemInfo *pci_ss_list_100b_0020[] = { + &pci_ss_info_100b_0020_103c_0024, + &pci_ss_info_100b_0020_1385_f311, + NULL +}; +#define pci_ss_list_100b_0021 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0028 NULL +#define pci_ss_list_100b_002a NULL +#define pci_ss_list_100b_002b NULL +#define pci_ss_list_100b_002d NULL +#define pci_ss_list_100b_002e NULL +#define pci_ss_list_100b_002f NULL +#define pci_ss_list_100b_0030 NULL +#define pci_ss_list_100b_0035 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_0510 NULL +#define pci_ss_list_100b_0511 NULL +#define pci_ss_list_100b_0515 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +#define pci_ss_list_1011_000f NULL +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +#define pci_ss_list_1011_0017 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1186_1112, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_14cb_0100, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_4c53_1050, + &pci_ss_info_1011_0046_4c53_1051, + &pci_ss_info_1011_0046_9005_0364, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4000 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_153b_1136, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0031[] = { + &pci_ss_info_1014_0031_1014_0031, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_0037 NULL +#define pci_ss_list_1014_003a NULL +#define pci_ss_list_1014_003c NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0054 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_005e NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +#define pci_ss_list_1014_008b NULL +#define pci_ss_list_1014_008e NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0091 NULL +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_009f NULL +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1014_00b7[] = { + &pci_ss_info_1014_00b7_1092_00b8, + NULL +}; +#define pci_ss_list_1014_00b8 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0104 NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_015e NULL +#define pci_ss_list_1014_0160 NULL +#define pci_ss_list_1014_016e NULL +#define pci_ss_list_1014_0170 NULL +#define pci_ss_list_1014_017d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0180[] = { + &pci_ss_info_1014_0180_1014_0241, + &pci_ss_info_1014_0180_1014_0264, + NULL +}; +#define pci_ss_list_1014_0188 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_01c1 NULL +#define pci_ss_list_1014_01e6 NULL +#define pci_ss_list_1014_01ff NULL +static const pciSubsystemInfo *pci_ss_list_1014_0219[] = { + &pci_ss_info_1014_0219_1014_021a, + &pci_ss_info_1014_0219_1014_0251, + &pci_ss_info_1014_0219_1014_0252, + NULL +}; +#define pci_ss_list_1014_021b NULL +#define pci_ss_list_1014_021c NULL +#define pci_ss_list_1014_0233 NULL +#define pci_ss_list_1014_0266 NULL +#define pci_ss_list_1014_0268 NULL +#define pci_ss_list_1014_0269 NULL +static const pciSubsystemInfo *pci_ss_list_1014_028c[] = { + &pci_ss_info_1014_028c_1014_028d, + &pci_ss_info_1014_028c_1014_02be, + &pci_ss_info_1014_028c_1014_02c0, + &pci_ss_info_1014_028c_1014_030d, + NULL +}; +#define pci_ss_list_1014_02a1 NULL +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_0314 NULL +#define pci_ss_list_1014_3022 NULL +#define pci_ss_list_1014_4022 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#define pci_ss_list_101e_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0477, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_101e_0494, + &pci_ss_info_101e_1960_101e_0503, + &pci_ss_info_101e_1960_101e_0511, + &pci_ss_info_101e_1960_101e_0522, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + &pci_ss_info_101e_1960_103c_60e7, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_1022_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + &pci_ss_info_1022_2000_1259_2702, + &pci_ss_info_1022_2000_1259_2703, + &pci_ss_info_1022_2000_4c53_1000, + &pci_ss_info_1022_2000_4c53_1010, + &pci_ss_info_1022_2000_4c53_1020, + &pci_ss_info_1022_2000_4c53_1030, + &pci_ss_info_1022_2000_4c53_1040, + &pci_ss_info_1022_2000_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2003 NULL +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_208f NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700a NULL +#define pci_ss_list_1022_700b NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7458 NULL +#define pci_ss_list_1022_7459 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7460[] = { + &pci_ss_info_1022_7460_161f_3017, + NULL +}; +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7464[] = { + &pci_ss_info_1022_7464_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7468[] = { + &pci_ss_info_1022_7468_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7469[] = { + &pci_ss_info_1022_7469_1022_2b80, + &pci_ss_info_1022_7469_161f_3017, + NULL +}; +#define pci_ss_list_1022_746a NULL +static const pciSubsystemInfo *pci_ss_list_1022_746b[] = { + &pci_ss_info_1022_746b_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_746d[] = { + &pci_ss_info_1022_746d_161f_3017, + NULL +}; +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1022_756b NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +static const pciSubsystemInfo *pci_ss_list_1023_2001[] = { + &pci_ss_info_1023_2001_122d_1400, + NULL +}; +#define pci_ss_list_1023_2100 NULL +#define pci_ss_list_1023_2200 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + &pci_ss_info_1023_8620_1014_1025, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_1671 NULL +#define pci_ss_list_1025_1672 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +#define pci_ss_list_1028_0009 NULL +#define pci_ss_list_1028_000a NULL +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000d NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_1028_0010 NULL +#define pci_ss_list_1028_0011 NULL +#define pci_ss_list_1028_0012 NULL +static const pciSubsystemInfo *pci_ss_list_1028_0013[] = { + &pci_ss_info_1028_0013_1028_016c, + &pci_ss_info_1028_0013_1028_016d, + &pci_ss_info_1028_0013_1028_016e, + &pci_ss_info_1028_0013_1028_016f, + &pci_ss_info_1028_0013_1028_0170, + NULL +}; +#define pci_ss_list_1028_0014 NULL +#define pci_ss_list_1028_0015 NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102a_001f[] = { + &pci_ss_info_102a_001f_9005_000f, + &pci_ss_info_102a_001f_9005_0106, + &pci_ss_info_102a_001f_9005_a180, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00c5[] = { + &pci_ss_info_102a_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00cf[] = { + &pci_ss_info_102a_00cf_1028_0106, + &pci_ss_info_102a_00cf_1028_0121, + NULL +}; +#endif +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0100 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0d43, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + &pci_ss_info_102b_0527_102b_0850, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0528[] = { + &pci_ss_info_102b_0528_102b_1020, + &pci_ss_info_102b_0528_102b_1030, + &pci_ss_info_102b_0528_102b_14e1, + &pci_ss_info_102b_0528_102b_2021, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2537[] = { + &pci_ss_info_102b_2537_102b_1820, + &pci_ss_info_102b_2537_102b_1830, + &pci_ss_info_102b_2537_102b_1c10, + &pci_ss_info_102b_2537_102b_2811, + &pci_ss_info_102b_2537_102b_2c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2538[] = { + &pci_ss_info_102b_2538_102b_08c7, + &pci_ss_info_102b_2538_102b_0907, + &pci_ss_info_102b_2538_102b_1047, + &pci_ss_info_102b_2538_102b_1087, + &pci_ss_info_102b_2538_102b_2538, + &pci_ss_info_102b_2538_102b_3007, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + &pci_ss_info_102c_00c0_4c53_1000, + &pci_ss_info_102c_00c0_4c53_1010, + &pci_ss_info_102c_00c0_4c53_1020, + &pci_ss_info_102c_00c0_4c53_1030, + &pci_ss_info_102c_00c0_4c53_1050, + &pci_ss_info_102c_00c0_4c53_1051, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + &pci_ss_info_102c_00e5_1179_0001, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_102c_0c30[] = { + &pci_ss_info_102c_0c30_4c53_1000, + &pci_ss_info_102c_0c30_4c53_1050, + &pci_ss_info_102c_0c30_4c53_1051, + &pci_ss_info_102c_0c30_4c53_1080, + NULL +}; +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#define pci_ss_list_102f_000a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#define pci_ss_list_102f_0030 NULL +#define pci_ss_list_102f_0031 NULL +#define pci_ss_list_102f_0105 NULL +#define pci_ss_list_102f_0106 NULL +#define pci_ss_list_102f_0107 NULL +#define pci_ss_list_102f_0108 NULL +#define pci_ss_list_102f_0180 NULL +#define pci_ss_list_102f_0181 NULL +#define pci_ss_list_102f_0182 NULL +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0000 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1033_0035, + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_14c2_0105, + &pci_ss_info_1033_0035_1799_0001, + &pci_ss_info_1033_0035_1931_000a, + &pci_ss_info_1033_0035_1931_000b, + &pci_ss_info_1033_0035_807d_0035, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +#define pci_ss_list_1033_0072 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a5 NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +#define pci_ss_list_1033_00ce NULL +#define pci_ss_list_1033_00df NULL +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_14c2_0205, + &pci_ss_info_1033_00e0_1799_0002, + &pci_ss_info_1033_00e0_807d_1043, + NULL +}; +#define pci_ss_list_1033_00e7 NULL +#define pci_ss_list_1033_00f2 NULL +#define pci_ss_list_1033_00f3 NULL +#define pci_ss_list_1033_010c NULL +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0003 NULL +#define pci_ss_list_1039_0004 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_000a NULL +#define pci_ss_list_1039_0016 NULL +#define pci_ss_list_1039_0018 NULL +#define pci_ss_list_1039_0180 NULL +#define pci_ss_list_1039_0181 NULL +#define pci_ss_list_1039_0182 NULL +#define pci_ss_list_1039_0191 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0550 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0648 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0655 NULL +#define pci_ss_list_1039_0660 NULL +#define pci_ss_list_1039_0661 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0741 NULL +#define pci_ss_list_1039_0745 NULL +#define pci_ss_list_1039_0746 NULL +#define pci_ss_list_1039_0755 NULL +#define pci_ss_list_1039_0760 NULL +#define pci_ss_list_1039_0761 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1019_0a14, + &pci_ss_info_1039_0900_1039_0900, + &pci_ss_info_1039_0900_1043_8035, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_0963 NULL +#define pci_ss_list_1039_0964 NULL +#define pci_ss_list_1039_0965 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + &pci_ss_info_1039_5513_1043_8035, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + &pci_ss_info_1039_6300_1043_8035, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6330[] = { + &pci_ss_info_1039_6330_1039_6330, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1019_0a14, + &pci_ss_info_1039_7001_1039_7000, + &pci_ss_info_1039_7001_1462_5470, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +#define pci_ss_list_1039_7012 NULL +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_1039_7019 NULL +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1006 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_100a NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + &pci_ss_info_103c_1048_103c_1301, + NULL +}; +#define pci_ss_list_103c_1054 NULL +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_10f0 NULL +#define pci_ss_list_103c_10f1 NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_127c NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_1291 NULL +#define pci_ss_list_103c_12b4 NULL +#define pci_ss_list_103c_12fa NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_103c_3080 NULL +#define pci_ss_list_103c_3220 NULL +#define pci_ss_list_103c_3230 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043_0675[] = { + &pci_ss_info_1043_0675_0675_1704, + &pci_ss_info_1043_0675_0675_1707, + &pci_ss_info_1043_0675_10cf_105e, + NULL +}; +#define pci_ss_list_1043_4015 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1043_4057 NULL +#define pci_ss_list_1043_8043 NULL +#define pci_ss_list_1043_807b NULL +#define pci_ss_list_1043_80bb NULL +#define pci_ss_list_1043_80c5 NULL +#define pci_ss_list_1043_80df NULL +#define pci_ss_list_1043_8187 NULL +#define pci_ss_list_1043_8188 NULL +#endif +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1044_a511[] = { + &pci_ss_info_1044_a511_1044_c032, + &pci_ss_info_1044_a511_1044_c035, + NULL +}; +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0c60 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048_8901[] = { + &pci_ss_info_1048_8901_1048_0935, + NULL +}; +#endif +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0209 NULL +#define pci_ss_list_104a_020a NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_021a NULL +#define pci_ss_list_104a_021b NULL +#define pci_ss_list_104a_0500 NULL +#define pci_ss_list_104a_0564 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104a_55cc NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a34, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_1048_0a36, + &pci_ss_info_104c_3d07_1048_0a43, + &pci_ss_info_104c_3d07_1048_0a44, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8020[] = { + &pci_ss_info_104c_8020_11bd_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8023[] = { + &pci_ss_info_104c_8023_103c_088c, + &pci_ss_info_104c_8023_1043_808b, + NULL +}; +#define pci_ss_list_104c_8024 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8025[] = { + &pci_ss_info_104c_8025_1458_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8026[] = { + &pci_ss_info_104c_8026_1043_808d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8029[] = { + &pci_ss_info_104c_8029_1028_0163, + &pci_ss_info_104c_8029_1028_0196, + &pci_ss_info_104c_8029_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_802b[] = { + &pci_ss_info_104c_802b_1028_0139, + &pci_ss_info_104c_802b_1028_014e, + NULL +}; +#define pci_ss_list_104c_802e NULL +static const pciSubsystemInfo *pci_ss_list_104c_8031[] = { + &pci_ss_info_104c_8031_103c_099c, + &pci_ss_info_104c_8031_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8032[] = { + &pci_ss_info_104c_8032_103c_099c, + &pci_ss_info_104c_8032_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8033[] = { + &pci_ss_info_104c_8033_103c_099c, + &pci_ss_info_104c_8033_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8034[] = { + &pci_ss_info_104c_8034_103c_099c, + &pci_ss_info_104c_8034_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8035[] = { + &pci_ss_info_104c_8035_103c_099c, + NULL +}; +#define pci_ss_list_104c_8036 NULL +#define pci_ss_list_104c_8038 NULL +#define pci_ss_list_104c_8201 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8204[] = { + &pci_ss_info_104c_8204_1028_0139, + &pci_ss_info_104c_8204_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8400[] = { + &pci_ss_info_104c_8400_1186_3b00, + &pci_ss_info_104c_8400_1186_3b01, + &pci_ss_info_104c_8400_16ab_8501, + NULL +}; +#define pci_ss_list_104c_8401 NULL +#define pci_ss_list_104c_9000 NULL +static const pciSubsystemInfo *pci_ss_list_104c_9066[] = { + &pci_ss_info_104c_9066_104c_9066, + &pci_ss_info_104c_9066_1186_3b04, + &pci_ss_info_104c_9066_1186_3b05, + &pci_ss_info_104c_9066_13d1_aba0, + NULL +}; +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +static const pciSubsystemInfo *pci_ss_list_104c_a106[] = { + &pci_ss_info_104c_a106_175c_5000, + &pci_ss_info_104c_a106_175c_6400, + &pci_ss_info_104c_a106_175c_8700, + NULL +}; +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac16[] = { + &pci_ss_info_104c_ac16_1014_0092, + NULL +}; +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + &pci_ss_info_104c_ac1b_1014_0130, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac1c[] = { + &pci_ss_info_104c_ac1c_0e11_b121, + &pci_ss_info_104c_ac1c_1028_0088, + NULL +}; +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac44[] = { + &pci_ss_info_104c_ac44_1028_0163, + &pci_ss_info_104c_ac44_1028_0196, + &pci_ss_info_104c_ac44_1071_8160, + NULL +}; +#define pci_ss_list_104c_ac46 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac47[] = { + &pci_ss_info_104c_ac47_1028_0139, + &pci_ss_info_104c_ac47_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac4a[] = { + &pci_ss_info_104c_ac4a_1028_0139, + &pci_ss_info_104c_ac4a_1028_014e, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_0e11_004e, + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_1028_00b1, + &pci_ss_info_104c_ac51_1028_012a, + &pci_ss_info_104c_ac51_1033_80cd, + &pci_ss_info_104c_ac51_1095_10cf, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +#define pci_ss_list_104c_ac54 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac56[] = { + &pci_ss_info_104c_ac56_1014_0528, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac60[] = { + &pci_ss_info_104c_ac60_175c_5100, + &pci_ss_info_104c_ac60_175c_6100, + &pci_ss_info_104c_ac60_175c_6200, + &pci_ss_info_104c_ac60_175c_8800, + NULL +}; +#define pci_ss_list_104c_ac8d NULL +#define pci_ss_list_104c_ac8e NULL +#define pci_ss_list_104c_ac8f NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8004 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +static const pciSubsystemInfo *pci_ss_list_1050_6692[] = { + &pci_ss_info_1050_6692_1043_1702, + &pci_ss_info_1050_6692_1043_1703, + &pci_ss_info_1050_6692_1043_1707, + &pci_ss_info_1050_6692_144f_1702, + &pci_ss_info_1050_6692_144f_1703, + &pci_ss_info_1050_6692_144f_1707, + NULL +}; +#define pci_ss_list_1050_9921 NULL +#define pci_ss_list_1050_9922 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0008 NULL +#define pci_ss_list_1057_0009 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_14fb_0101, + &pci_ss_info_1057_1801_14fb_0102, + &pci_ss_info_1057_1801_14fb_0202, + &pci_ss_info_1057_1801_14fb_0611, + &pci_ss_info_1057_1801_14fb_0612, + &pci_ss_info_1057_1801_14fb_0613, + &pci_ss_info_1057_1801_14fb_0614, + &pci_ss_info_1057_1801_14fb_0621, + &pci_ss_info_1057_1801_14fb_0622, + &pci_ss_info_1057_1801_14fb_0810, + &pci_ss_info_1057_1801_175c_4200, + &pci_ss_info_1057_1801_175c_4300, + &pci_ss_info_1057_1801_175c_4400, + &pci_ss_info_1057_1801_ecc0_0010, + &pci_ss_info_1057_1801_ecc0_0020, + &pci_ss_info_1057_1801_ecc0_0030, + &pci_ss_info_1057_1801_ecc0_0031, + &pci_ss_info_1057_1801_ecc0_0040, + &pci_ss_info_1057_1801_ecc0_0041, + &pci_ss_info_1057_1801_ecc0_0050, + &pci_ss_info_1057_1801_ecc0_0051, + &pci_ss_info_1057_1801_ecc0_0070, + &pci_ss_info_1057_1801_ecc0_0071, + &pci_ss_info_1057_1801_ecc0_0072, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_18c1 NULL +static const pciSubsystemInfo *pci_ss_list_1057_3410[] = { + &pci_ss_info_1057_3410_ecc0_0050, + &pci_ss_info_1057_3410_ecc0_0051, + &pci_ss_info_1057_3410_ecc0_0060, + &pci_ss_info_1057_3410_ecc0_0070, + &pci_ss_info_1057_3410_ecc0_0071, + &pci_ss_info_1057_3410_ecc0_0072, + &pci_ss_info_1057_3410_ecc0_0080, + &pci_ss_info_1057_3410_ecc0_0081, + &pci_ss_info_1057_3410_ecc0_0090, + &pci_ss_info_1057_3410_ecc0_00a0, + &pci_ss_info_1057_3410_ecc0_00b0, + &pci_ss_info_1057_3410_ecc0_0100, + NULL +}; +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_5803 NULL +#define pci_ss_list_1057_5806 NULL +#define pci_ss_list_1057_5808 NULL +#define pci_ss_list_1057_6400 NULL +#define pci_ss_list_1057_6405 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3318 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3319[] = { + &pci_ss_info_105a_3319_8086_3427, + NULL +}; +#define pci_ss_list_105a_3371 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3373[] = { + &pci_ss_info_105a_3373_1043_80f5, + &pci_ss_info_105a_3373_1462_702e, + NULL +}; +#define pci_ss_list_105a_3375 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3376[] = { + &pci_ss_info_105a_3376_1043_809e, + NULL +}; +#define pci_ss_list_105a_3515 NULL +#define pci_ss_list_105a_3519 NULL +#define pci_ss_list_105a_3571 NULL +#define pci_ss_list_105a_3574 NULL +#define pci_ss_list_105a_3577 NULL +#define pci_ss_list_105a_3d17 NULL +#define pci_ss_list_105a_3d18 NULL +#define pci_ss_list_105a_3d73 NULL +#define pci_ss_list_105a_3d75 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d69[] = { + &pci_ss_info_105a_4d69_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_1043_807e, + &pci_ss_info_105a_5275_105a_0275, + &pci_ss_info_105a_5275_105a_1275, + &pci_ss_info_105a_5275_1458_b001, + NULL +}; +#define pci_ss_list_105a_5300 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6268[] = { + &pci_ss_info_105a_6268_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_6622 NULL +#define pci_ss_list_105a_6624 NULL +#define pci_ss_list_105a_6626 NULL +#define pci_ss_list_105a_6629 NULL +#define pci_ss_list_105a_7275 NULL +#define pci_ss_list_105a_8002 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_5348[] = { + &pci_ss_info_105d_5348_105d_0037, + NULL +}; +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_0301 NULL +#define pci_ss_list_1067_0304 NULL +#define pci_ss_list_1067_0308 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069_0050[] = { + &pci_ss_info_1069_0050_1069_0050, + &pci_ss_info_1069_0050_1069_0052, + &pci_ss_info_1069_0050_1069_0054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_b166[] = { + &pci_ss_info_1069_b166_1014_0242, + &pci_ss_info_1069_b166_1014_0266, + &pci_ss_info_1069_b166_1014_0278, + &pci_ss_info_1069_b166_1014_02d3, + &pci_ss_info_1069_b166_1014_02d4, + &pci_ss_info_1069_b166_1069_0200, + &pci_ss_info_1069_b166_1069_0202, + &pci_ss_info_1069_b166_1069_0204, + &pci_ss_info_1069_b166_1069_0206, + NULL +}; +#define pci_ss_list_1069_ba55 NULL +static const pciSubsystemInfo *pci_ss_list_1069_ba56[] = { + &pci_ss_info_1069_ba56_1069_0030, + &pci_ss_info_1069_ba56_1069_0040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_ba57[] = { + &pci_ss_info_1069_ba57_1069_0072, + NULL +}; +#endif +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000c NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b_0031[] = { + &pci_ss_info_106b_0031_106b_5811, + NULL +}; +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_0035 NULL +#define pci_ss_list_106b_0036 NULL +#define pci_ss_list_106b_003b NULL +#define pci_ss_list_106b_003e NULL +#define pci_ss_list_106b_003f NULL +#define pci_ss_list_106b_0040 NULL +#define pci_ss_list_106b_0041 NULL +#define pci_ss_list_106b_0042 NULL +#define pci_ss_list_106b_0043 NULL +#define pci_ss_list_106b_0045 NULL +#define pci_ss_list_106b_0046 NULL +#define pci_ss_list_106b_0047 NULL +#define pci_ss_list_106b_0048 NULL +#define pci_ss_list_106b_0049 NULL +#define pci_ss_list_106b_004b NULL +#define pci_ss_list_106b_004c NULL +#define pci_ss_list_106b_004f NULL +#define pci_ss_list_106b_0050 NULL +#define pci_ss_list_106b_0051 NULL +#define pci_ss_list_106b_0052 NULL +#define pci_ss_list_106b_0053 NULL +#define pci_ss_list_106b_0054 NULL +#define pci_ss_list_106b_0055 NULL +#define pci_ss_list_106b_0058 NULL +#define pci_ss_list_106b_0059 NULL +#define pci_ss_list_106b_0066 NULL +#define pci_ss_list_106b_0067 NULL +#define pci_ss_list_106b_0068 NULL +#define pci_ss_list_106b_0069 NULL +#define pci_ss_list_106b_006a NULL +#define pci_ss_list_106b_006b NULL +#define pci_ss_list_106b_1645 NULL +#endif +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1071_8160 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1077_2200[] = { + &pci_ss_info_1077_2200_1077_0002, + NULL +}; +#define pci_ss_list_1077_2300 NULL +#define pci_ss_list_1077_2312 NULL +#define pci_ss_list_1077_2322 NULL +#define pci_ss_list_1077_2422 NULL +#define pci_ss_list_1077_2432 NULL +#define pci_ss_list_1077_3010 NULL +#define pci_ss_list_1077_3022 NULL +#define pci_ss_list_1077_4010 NULL +#define pci_ss_list_1077_4022 NULL +#define pci_ss_list_1077_6312 NULL +#define pci_ss_list_1077_6322 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107d_2134 NULL +#define pci_ss_list_107d_2971 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_1648 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_8002 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_108e_a801 NULL +#define pci_ss_list_108e_abba NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1091_07a0 NULL +#define pci_ss_list_1091_1091 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1310 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_14e0 NULL +#define pci_ss_list_1093_14f0 NULL +#define pci_ss_list_1093_17d0 NULL +#define pci_ss_list_1093_1870 NULL +#define pci_ss_list_1093_1880 NULL +#define pci_ss_list_1093_18b0 NULL +#define pci_ss_list_1093_2410 NULL +#define pci_ss_list_1093_2890 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_2a70 NULL +#define pci_ss_list_1093_2a80 NULL +#define pci_ss_list_1093_2c80 NULL +#define pci_ss_list_1093_2ca0 NULL +#define pci_ss_list_1093_70b8 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0240 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#define pci_ss_list_1095_0648 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0680[] = { + &pci_ss_info_1095_0680_1095_3680, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3112[] = { + &pci_ss_info_1095_3112_1095_3112, + &pci_ss_info_1095_3112_1095_6112, + &pci_ss_info_1095_3112_9005_0250, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3114[] = { + &pci_ss_info_1095_3114_1095_3114, + &pci_ss_info_1095_3114_1095_6114, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3124[] = { + &pci_ss_info_1095_3124_1095_3124, + NULL +}; +#define pci_ss_list_1095_3132 NULL +static const pciSubsystemInfo *pci_ss_list_1095_3512[] = { + &pci_ss_info_1095_3512_1095_3512, + &pci_ss_info_1095_3512_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_032e NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_0071_0101, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0002, + &pci_ss_info_109e_036e_1461_0003, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_1461_0761, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1822_0001, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_18ac_d500, + &pci_ss_info_109e_036e_270f_fc00, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_0071_0101, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0002, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_1461_0761, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_1822_0001, + &pci_ss_info_109e_0878_18ac_d500, + &pci_ss_info_109e_0878_270f_fc00, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_3052 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9_0009[] = { + &pci_ss_info_10a9_0009_10a9_8002, + NULL +}; +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_100a NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_4001 NULL +#define pci_ss_list_10a9_4002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#define pci_ss_list_10a9_8010 NULL +#define pci_ss_list_10a9_8018 NULL +#endif +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1042 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2540 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_6540[] = { + &pci_ss_info_10b5_6540_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6541[] = { + &pci_ss_info_10b5_6541_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6542[] = { + &pci_ss_info_10b5_6542_4c53_10e0, + NULL +}; +#define pci_ss_list_10b5_8111 NULL +#define pci_ss_list_10b5_8114 NULL +#define pci_ss_list_10b5_8516 NULL +#define pci_ss_list_10b5_8532 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_10b5_2862, + &pci_ss_info_10b5_9030_10b5_2906, + &pci_ss_info_10b5_9030_10b5_2940, + &pci_ss_info_10b5_9030_10b5_2977, + &pci_ss_info_10b5_9030_10b5_2978, + &pci_ss_info_10b5_9030_10b5_3025, + &pci_ss_info_10b5_9030_10b5_3068, + &pci_ss_info_10b5_9030_1397_3136, + &pci_ss_info_10b5_9030_1397_3137, + &pci_ss_info_10b5_9030_1518_0200, + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_1067, + &pci_ss_info_10b5_9050_10b5_1172, + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2221, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_2431, + &pci_ss_info_10b5_9050_10b5_2905, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1498_0362, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_2036, + &pci_ss_info_10b5_9050_5654_3132, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + &pci_ss_info_10b5_9054_10b5_2696, + &pci_ss_info_10b5_9054_10b5_2717, + &pci_ss_info_10b5_9054_10b5_2844, + &pci_ss_info_10b5_9054_12c7_4001, + &pci_ss_info_10b5_9054_12d9_0002, + &pci_ss_info_10b5_9054_16df_0011, + &pci_ss_info_10b5_9054_16df_0012, + &pci_ss_info_10b5_9054_16df_0013, + &pci_ss_info_10b5_9054_16df_0014, + &pci_ss_info_10b5_9054_16df_0015, + &pci_ss_info_10b5_9054_16df_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9056[] = { + &pci_ss_info_10b5_9056_10b5_2979, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_103c_10eb, + &pci_ss_info_10b5_9080_103c_10ec, + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + &pci_ss_info_10b5_9080_12d9_0002, + &pci_ss_info_10b5_9080_12df_4422, + NULL +}; +#define pci_ss_list_10b5_bb04 NULL +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_0013[] = { + &pci_ss_info_10b7_0013_10b7_2031, + NULL +}; +#define pci_ss_list_10b7_0910 NULL +#define pci_ss_list_10b7_1006 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_1201 NULL +#define pci_ss_list_10b7_1202 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1700[] = { + &pci_ss_info_10b7_1700_1043_80eb, + &pci_ss_info_10b7_1700_10b7_0010, + &pci_ss_info_10b7_1700_10b7_0020, + &pci_ss_info_10b7_1700_147b_1407, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6000 NULL +#define pci_ss_list_10b7_6001 NULL +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7770 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_80eb NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_1028_0097, + &pci_ss_info_10b7_9200_1028_00fe, + &pci_ss_info_10b7_9200_1028_012a, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + &pci_ss_info_10b7_9200_10f1_2466, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9201[] = { + &pci_ss_info_10b7_9201_1043_80ab, + NULL +}; +#define pci_ss_list_10b7_9202 NULL +#define pci_ss_list_10b7_9210 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990a NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_2802 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +#define pci_ss_list_10b9_0101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_0780 NULL +#define pci_ss_list_10b9_0782 NULL +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_1014_053b, + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1573 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1672 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_1689 NULL +#define pci_ss_list_10b9_1695 NULL +#define pci_ss_list_10b9_1697 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_3323 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +#define pci_ss_list_10b9_5228 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1014_050f, + &pci_ss_info_10b9_5229_1014_053d, + &pci_ss_info_10b9_5229_103c_0024, + &pci_ss_info_10b9_5229_1043_8053, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5237[] = { + &pci_ss_info_10b9_5237_1014_0540, + &pci_ss_info_10b9_5237_103c_0024, + &pci_ss_info_10b9_5237_104d_810f, + NULL +}; +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5246 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_524b NULL +#define pci_ss_list_10b9_524c NULL +#define pci_ss_list_10b9_524d NULL +#define pci_ss_list_10b9_524e NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +#define pci_ss_list_10b9_5263 NULL +#define pci_ss_list_10b9_5281 NULL +#define pci_ss_list_10b9_5287 NULL +#define pci_ss_list_10b9_5288 NULL +#define pci_ss_list_10b9_5289 NULL +#define pci_ss_list_10b9_5450 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + &pci_ss_info_10b9_5451_1014_053e, + &pci_ss_info_10b9_5451_103c_0024, + &pci_ss_info_10b9_5451_10b9_5451, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5457[] = { + &pci_ss_info_10b9_5457_1014_0535, + &pci_ss_info_10b9_5457_103c_0024, + NULL +}; +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5461 NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_1014_0510, + &pci_ss_info_10b9_7101_1014_053c, + &pci_ss_info_10b9_7101_103c_0024, + NULL +}; +#endif +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10ba_0304 NULL +#define pci_ss_list_10ba_0308 NULL +#define pci_ss_list_10ba_1002 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + &pci_ss_info_10c8_0005_1028_0088, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_0088, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cc_0660 NULL +#define pci_ss_list_10cc_0661 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0431 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8626 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10dd_0100 NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c19, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1048_0c1c, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1048_0c21, + &pci_ss_info_10de_0028_1048_0c28, + &pci_ss_info_10de_0028_1048_0c29, + &pci_ss_info_10de_0028_1048_0c2a, + &pci_ss_info_10de_0028_1048_0c2b, + &pci_ss_info_10de_0028_1048_0c31, + &pci_ss_info_10de_0028_1048_0c32, + &pci_ss_info_10de_0028_1048_0c33, + &pci_ss_info_10de_0028_1048_0c34, + &pci_ss_info_10de_0028_107d_2134, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1048_0c2e, + &pci_ss_info_10de_0029_1048_0c2f, + &pci_ss_info_10de_0029_1048_0c30, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1048_0c20, + &pci_ss_info_10de_002c_1048_0c21, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_1048_0c3b, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + &pci_ss_info_10de_002d_1569_002d, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +#define pci_ss_list_10de_0034 NULL +#define pci_ss_list_10de_0035 NULL +#define pci_ss_list_10de_0036 NULL +#define pci_ss_list_10de_0037 NULL +#define pci_ss_list_10de_0038 NULL +#define pci_ss_list_10de_003a NULL +#define pci_ss_list_10de_003b NULL +#define pci_ss_list_10de_003c NULL +#define pci_ss_list_10de_003d NULL +#define pci_ss_list_10de_003e NULL +#define pci_ss_list_10de_0040 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0041[] = { + &pci_ss_info_10de_0041_1043_817b, + NULL +}; +#define pci_ss_list_10de_0042 NULL +#define pci_ss_list_10de_0043 NULL +#define pci_ss_list_10de_0045 NULL +#define pci_ss_list_10de_0046 NULL +#define pci_ss_list_10de_0048 NULL +#define pci_ss_list_10de_0049 NULL +#define pci_ss_list_10de_004e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0050[] = { + &pci_ss_info_10de_0050_1043_815a, + &pci_ss_info_10de_0050_1458_0c11, + &pci_ss_info_10de_0050_1462_7100, + NULL +}; +#define pci_ss_list_10de_0051 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0052[] = { + &pci_ss_info_10de_0052_1043_815a, + &pci_ss_info_10de_0052_1458_0c11, + &pci_ss_info_10de_0052_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0053[] = { + &pci_ss_info_10de_0053_1043_815a, + &pci_ss_info_10de_0053_1458_5002, + &pci_ss_info_10de_0053_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0054[] = { + &pci_ss_info_10de_0054_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0055[] = { + &pci_ss_info_10de_0055_1043_815a, + NULL +}; +#define pci_ss_list_10de_0056 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0057[] = { + &pci_ss_info_10de_0057_1043_8141, + &pci_ss_info_10de_0057_1458_e000, + &pci_ss_info_10de_0057_1462_7100, + NULL +}; +#define pci_ss_list_10de_0058 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0059[] = { + &pci_ss_info_10de_0059_1043_812a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005a[] = { + &pci_ss_info_10de_005a_1043_815a, + &pci_ss_info_10de_005a_1458_5004, + &pci_ss_info_10de_005a_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005b[] = { + &pci_ss_info_10de_005b_1043_815a, + &pci_ss_info_10de_005b_1458_5004, + &pci_ss_info_10de_005b_1462_7100, + NULL +}; +#define pci_ss_list_10de_005c NULL +#define pci_ss_list_10de_005d NULL +static const pciSubsystemInfo *pci_ss_list_10de_005e[] = { + &pci_ss_info_10de_005e_1458_5000, + &pci_ss_info_10de_005e_1462_7100, + NULL +}; +#define pci_ss_list_10de_005f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + NULL +}; +#define pci_ss_list_10de_0064 NULL +#define pci_ss_list_10de_0065 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0066[] = { + &pci_ss_info_10de_0066_1043_80a7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + NULL +}; +#define pci_ss_list_10de_006a NULL +static const pciSubsystemInfo *pci_ss_list_10de_006b[] = { + &pci_ss_info_10de_006b_10de_006b, + NULL +}; +#define pci_ss_list_10de_006c NULL +#define pci_ss_list_10de_006d NULL +#define pci_ss_list_10de_006e NULL +#define pci_ss_list_10de_0080 NULL +#define pci_ss_list_10de_0084 NULL +#define pci_ss_list_10de_0085 NULL +#define pci_ss_list_10de_0086 NULL +#define pci_ss_list_10de_0087 NULL +#define pci_ss_list_10de_0088 NULL +#define pci_ss_list_10de_008a NULL +#define pci_ss_list_10de_008b NULL +#define pci_ss_list_10de_008c NULL +#define pci_ss_list_10de_008e NULL +#define pci_ss_list_10de_0091 NULL +#define pci_ss_list_10de_0092 NULL +#define pci_ss_list_10de_0099 NULL +#define pci_ss_list_10de_009d NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +#define pci_ss_list_10de_00c0 NULL +#define pci_ss_list_10de_00c1 NULL +#define pci_ss_list_10de_00c2 NULL +#define pci_ss_list_10de_00c3 NULL +#define pci_ss_list_10de_00c8 NULL +#define pci_ss_list_10de_00c9 NULL +#define pci_ss_list_10de_00cc NULL +#define pci_ss_list_10de_00cd NULL +#define pci_ss_list_10de_00ce NULL +#define pci_ss_list_10de_00d0 NULL +#define pci_ss_list_10de_00d1 NULL +#define pci_ss_list_10de_00d2 NULL +#define pci_ss_list_10de_00d3 NULL +#define pci_ss_list_10de_00d4 NULL +#define pci_ss_list_10de_00d5 NULL +#define pci_ss_list_10de_00d6 NULL +#define pci_ss_list_10de_00d7 NULL +#define pci_ss_list_10de_00d8 NULL +#define pci_ss_list_10de_00d9 NULL +#define pci_ss_list_10de_00da NULL +#define pci_ss_list_10de_00dd NULL +static const pciSubsystemInfo *pci_ss_list_10de_00df[] = { + &pci_ss_info_10de_00df_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e0[] = { + &pci_ss_info_10de_00e0_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e1[] = { + &pci_ss_info_10de_00e1_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e2 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e3[] = { + &pci_ss_info_10de_00e3_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e4[] = { + &pci_ss_info_10de_00e4_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e5[] = { + &pci_ss_info_10de_00e5_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e6 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e7[] = { + &pci_ss_info_10de_00e7_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e8[] = { + &pci_ss_info_10de_00e8_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00ea[] = { + &pci_ss_info_10de_00ea_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00ed NULL +#define pci_ss_list_10de_00ee NULL +#define pci_ss_list_10de_00f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f1[] = { + &pci_ss_info_10de_00f1_1043_81a6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00f2[] = { + &pci_ss_info_10de_00f2_1682_211c, + NULL +}; +#define pci_ss_list_10de_00f3 NULL +#define pci_ss_list_10de_00f8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f9[] = { + &pci_ss_info_10de_00f9_1682_2120, + NULL +}; +#define pci_ss_list_10de_00fa NULL +#define pci_ss_list_10de_00fb NULL +#define pci_ss_list_10de_00fc NULL +#define pci_ss_list_10de_00fd NULL +#define pci_ss_list_10de_00fe NULL +#define pci_ss_list_10de_00ff NULL +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1048_0c41, + &pci_ss_info_10de_0100_1048_0c43, + &pci_ss_info_10de_0100_1048_0c48, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1048_0c42, + &pci_ss_info_10de_0101_107d_2822, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0103[] = { + &pci_ss_info_10de_0103_1048_0c40, + &pci_ss_info_10de_0103_1048_0c44, + &pci_ss_info_10de_0103_1048_0c45, + &pci_ss_info_10de_0103_1048_0c4a, + &pci_ss_info_10de_0103_1048_0c4b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1048_0c60, + &pci_ss_info_10de_0110_1048_0c61, + &pci_ss_info_10de_0110_1048_0c63, + &pci_ss_info_10de_0110_1048_0c64, + &pci_ss_info_10de_0110_1048_0c65, + &pci_ss_info_10de_0110_1048_0c66, + &pci_ss_info_10de_0110_10de_0091, + &pci_ss_info_10de_0110_10de_00a1, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +#define pci_ss_list_10de_0140 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0141[] = { + &pci_ss_info_10de_0141_1458_3124, + NULL +}; +#define pci_ss_list_10de_0142 NULL +#define pci_ss_list_10de_0144 NULL +#define pci_ss_list_10de_0145 NULL +#define pci_ss_list_10de_0146 NULL +#define pci_ss_list_10de_0147 NULL +#define pci_ss_list_10de_0148 NULL +#define pci_ss_list_10de_0149 NULL +#define pci_ss_list_10de_014e NULL +#define pci_ss_list_10de_014f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_1048_0c50, + &pci_ss_info_10de_0150_1048_0c52, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_107d_2842, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + &pci_ss_info_10de_0151_1462_5506, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0160 NULL +#define pci_ss_list_10de_0161 NULL +#define pci_ss_list_10de_0162 NULL +#define pci_ss_list_10de_0163 NULL +#define pci_ss_list_10de_0164 NULL +#define pci_ss_list_10de_0165 NULL +#define pci_ss_list_10de_0166 NULL +#define pci_ss_list_10de_0167 NULL +#define pci_ss_list_10de_0168 NULL +#define pci_ss_list_10de_0169 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_10b0_0002, + &pci_ss_info_10de_0171_10de_0008, + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_1462_8852, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0176[] = { + &pci_ss_info_10de_0176_4c53_1090, + NULL +}; +#define pci_ss_list_10de_0177 NULL +#define pci_ss_list_10de_0178 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0179[] = { + &pci_ss_info_10de_0179_10de_0179, + NULL +}; +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_017d NULL +static const pciSubsystemInfo *pci_ss_list_10de_0181[] = { + &pci_ss_info_10de_0181_1043_806f, + &pci_ss_info_10de_0181_1462_8880, + &pci_ss_info_10de_0181_1462_8900, + &pci_ss_info_10de_0181_1462_9350, + &pci_ss_info_10de_0181_147b_8f0d, + NULL +}; +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0185 NULL +#define pci_ss_list_10de_0186 NULL +#define pci_ss_list_10de_0187 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_018c NULL +#define pci_ss_list_10de_018d NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b0 NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +#define pci_ss_list_10de_01e0 NULL +#define pci_ss_list_10de_01e8 NULL +#define pci_ss_list_10de_01ea NULL +#define pci_ss_list_10de_01eb NULL +#define pci_ss_list_10de_01ec NULL +#define pci_ss_list_10de_01ed NULL +#define pci_ss_list_10de_01ee NULL +#define pci_ss_list_10de_01ef NULL +#define pci_ss_list_10de_01f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + &pci_ss_info_10de_0200_1048_0c70, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0211 NULL +#define pci_ss_list_10de_0212 NULL +#define pci_ss_list_10de_0215 NULL +#define pci_ss_list_10de_0221 NULL +#define pci_ss_list_10de_0240 NULL +#define pci_ss_list_10de_0241 NULL +#define pci_ss_list_10de_0242 NULL +#define pci_ss_list_10de_0243 NULL +#define pci_ss_list_10de_0244 NULL +#define pci_ss_list_10de_0245 NULL +#define pci_ss_list_10de_0246 NULL +#define pci_ss_list_10de_0247 NULL +#define pci_ss_list_10de_0248 NULL +#define pci_ss_list_10de_0249 NULL +#define pci_ss_list_10de_024a NULL +#define pci_ss_list_10de_024b NULL +#define pci_ss_list_10de_024c NULL +#define pci_ss_list_10de_024d NULL +#define pci_ss_list_10de_024e NULL +#define pci_ss_list_10de_024f NULL +#define pci_ss_list_10de_0250 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0251[] = { + &pci_ss_info_10de_0251_1043_8023, + NULL +}; +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +#define pci_ss_list_10de_0260 NULL +#define pci_ss_list_10de_0261 NULL +#define pci_ss_list_10de_0262 NULL +#define pci_ss_list_10de_0263 NULL +#define pci_ss_list_10de_0264 NULL +#define pci_ss_list_10de_0265 NULL +#define pci_ss_list_10de_0266 NULL +#define pci_ss_list_10de_0267 NULL +#define pci_ss_list_10de_0268 NULL +#define pci_ss_list_10de_0269 NULL +#define pci_ss_list_10de_026a NULL +#define pci_ss_list_10de_026b NULL +#define pci_ss_list_10de_026c NULL +#define pci_ss_list_10de_026d NULL +#define pci_ss_list_10de_026e NULL +#define pci_ss_list_10de_026f NULL +#define pci_ss_list_10de_0270 NULL +#define pci_ss_list_10de_0271 NULL +#define pci_ss_list_10de_0272 NULL +#define pci_ss_list_10de_027e NULL +#define pci_ss_list_10de_027f NULL +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0286 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_028c NULL +#define pci_ss_list_10de_02a0 NULL +#define pci_ss_list_10de_02f0 NULL +#define pci_ss_list_10de_02f1 NULL +#define pci_ss_list_10de_02f2 NULL +#define pci_ss_list_10de_02f3 NULL +#define pci_ss_list_10de_02f4 NULL +#define pci_ss_list_10de_02f5 NULL +#define pci_ss_list_10de_02f6 NULL +#define pci_ss_list_10de_02f7 NULL +#define pci_ss_list_10de_02f8 NULL +#define pci_ss_list_10de_02f9 NULL +#define pci_ss_list_10de_02fa NULL +#define pci_ss_list_10de_02fb NULL +#define pci_ss_list_10de_02fc NULL +#define pci_ss_list_10de_02fd NULL +#define pci_ss_list_10de_02fe NULL +#define pci_ss_list_10de_02ff NULL +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10de_0311 NULL +#define pci_ss_list_10de_0312 NULL +#define pci_ss_list_10de_0313 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0314[] = { + &pci_ss_info_10de_0314_1043_814a, + NULL +}; +#define pci_ss_list_10de_0316 NULL +#define pci_ss_list_10de_0317 NULL +#define pci_ss_list_10de_031a NULL +#define pci_ss_list_10de_031b NULL +#define pci_ss_list_10de_031c NULL +#define pci_ss_list_10de_031d NULL +#define pci_ss_list_10de_031e NULL +#define pci_ss_list_10de_031f NULL +#define pci_ss_list_10de_0320 NULL +#define pci_ss_list_10de_0321 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0322[] = { + &pci_ss_info_10de_0322_1462_9171, + &pci_ss_info_10de_0322_1462_9360, + NULL +}; +#define pci_ss_list_10de_0323 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0324[] = { + &pci_ss_info_10de_0324_1028_0196, + &pci_ss_info_10de_0324_1071_8160, + NULL +}; +#define pci_ss_list_10de_0325 NULL +#define pci_ss_list_10de_0326 NULL +#define pci_ss_list_10de_0327 NULL +#define pci_ss_list_10de_0328 NULL +#define pci_ss_list_10de_0329 NULL +#define pci_ss_list_10de_032a NULL +#define pci_ss_list_10de_032b NULL +#define pci_ss_list_10de_032c NULL +#define pci_ss_list_10de_032d NULL +#define pci_ss_list_10de_032f NULL +#define pci_ss_list_10de_0330 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0331[] = { + &pci_ss_info_10de_0331_1043_8145, + NULL +}; +#define pci_ss_list_10de_0332 NULL +#define pci_ss_list_10de_0333 NULL +#define pci_ss_list_10de_0334 NULL +#define pci_ss_list_10de_0338 NULL +#define pci_ss_list_10de_033f NULL +#define pci_ss_list_10de_0341 NULL +#define pci_ss_list_10de_0342 NULL +#define pci_ss_list_10de_0343 NULL +#define pci_ss_list_10de_0344 NULL +#define pci_ss_list_10de_0345 NULL +#define pci_ss_list_10de_0347 NULL +#define pci_ss_list_10de_0348 NULL +#define pci_ss_list_10de_0349 NULL +#define pci_ss_list_10de_034b NULL +#define pci_ss_list_10de_034c NULL +#define pci_ss_list_10de_034e NULL +#define pci_ss_list_10de_034f NULL +#define pci_ss_list_10de_0360 NULL +#define pci_ss_list_10de_0361 NULL +#define pci_ss_list_10de_0362 NULL +#define pci_ss_list_10de_0363 NULL +#define pci_ss_list_10de_0364 NULL +#define pci_ss_list_10de_0365 NULL +#define pci_ss_list_10de_0366 NULL +#define pci_ss_list_10de_0367 NULL +#define pci_ss_list_10de_0368 NULL +#define pci_ss_list_10de_0369 NULL +#define pci_ss_list_10de_036a NULL +#define pci_ss_list_10de_036c NULL +#define pci_ss_list_10de_036d NULL +#define pci_ss_list_10de_036e NULL +#define pci_ss_list_10de_0371 NULL +#define pci_ss_list_10de_0372 NULL +#define pci_ss_list_10de_0373 NULL +#define pci_ss_list_10de_037a NULL +#define pci_ss_list_10de_037e NULL +#define pci_ss_list_10de_037f NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f0a1 NULL +#define pci_ss_list_10df_f0a5 NULL +#define pci_ss_list_10df_f0b5 NULL +#define pci_ss_list_10df_f0d1 NULL +#define pci_ss_list_10df_f0d5 NULL +#define pci_ss_list_10df_f0e1 NULL +#define pci_ss_list_10df_f0e5 NULL +#define pci_ss_list_10df_f0f5 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f701 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f801 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f901 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10df_f981 NULL +#define pci_ss_list_10df_f982 NULL +#define pci_ss_list_10df_fa00 NULL +#define pci_ss_list_10df_fb00 NULL +#define pci_ss_list_10df_fc00 NULL +#define pci_ss_list_10df_fc10 NULL +#define pci_ss_list_10df_fc20 NULL +#define pci_ss_list_10df_fd00 NULL +#define pci_ss_list_10df_fe00 NULL +#define pci_ss_list_10df_ff00 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0148 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e3_8260 NULL +#define pci_ss_list_10e3_8261 NULL +#define pci_ss_list_10e4_8029 NULL +#define pci_ss_list_10e8_1072 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_814c NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_81e6 NULL +#define pci_ss_list_10e8_8291 NULL +#define pci_ss_list_10e8_82c4 NULL +#define pci_ss_list_10e8_82c5 NULL +#define pci_ss_list_10e8_82c6 NULL +#define pci_ss_list_10e8_82c7 NULL +#define pci_ss_list_10e8_82ca NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10e8_82e2 NULL +#define pci_ss_list_10e8_8851 NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10ea_5252 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#define pci_ss_list_10ec_0139 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_0357_000a, + &pci_ss_info_10ec_8139_1025_005a, + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_1043_8109, + &pci_ss_info_10ec_8139_1071_8160, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1113_ec01, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_1458_e000, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_14cb_0200, + &pci_ss_info_10ec_8139_1799_5000, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_9001_1695, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1259_c107, + &pci_ss_info_10ec_8169_1371_434e, + &pci_ss_info_10ec_8169_1458_e000, + &pci_ss_info_10ec_8169_1462_702c, + NULL +}; +#define pci_ss_list_10ec_8180 NULL +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_0314 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ee_3fc6 NULL +#define pci_ss_list_10ee_8381 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#define pci_ss_list_1101_9502 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + &pci_ss_info_1102_0002_1102_8064, + &pci_ss_info_1102_0002_1102_8065, + &pci_ss_info_1102_0002_1102_8067, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + &pci_ss_info_1102_0004_1102_0058, + &pci_ss_info_1102_0004_1102_1007, + &pci_ss_info_1102_0004_1102_2002, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_0007[] = { + &pci_ss_info_1102_0007_1102_0007, + &pci_ss_info_1102_0007_1102_1001, + &pci_ss_info_1102_0007_1102_1002, + &pci_ss_info_1102_0007_1102_1006, + &pci_ss_info_1102_0007_1462_1009, + NULL +}; +#define pci_ss_list_1102_0008 NULL +#define pci_ss_list_1102_100a NULL +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +static const pciSubsystemInfo *pci_ss_list_1102_7005[] = { + &pci_ss_info_1102_7005_1102_1001, + &pci_ss_info_1102_7005_1102_1002, + NULL +}; +#define pci_ss_list_1102_8064 NULL +static const pciSubsystemInfo *pci_ss_list_1102_8938[] = { + &pci_ss_info_1102_8938_1033_80e5, + &pci_ss_info_1102_8938_1071_7150, + &pci_ss_info_1102_8938_110a_5938, + &pci_ss_info_1102_8938_13bd_100c, + &pci_ss_info_1102_8938_13bd_100d, + &pci_ss_info_1102_8938_13bd_100e, + &pci_ss_info_1102_8938_13bd_f6f1, + &pci_ss_info_1102_8938_14ff_0e70, + &pci_ss_info_1102_8938_14ff_c401, + &pci_ss_info_1102_8938_156d_b400, + &pci_ss_info_1102_8938_156d_b550, + &pci_ss_info_1102_8938_156d_b560, + &pci_ss_info_1102_8938_156d_b700, + &pci_ss_info_1102_8938_156d_b795, + &pci_ss_info_1102_8938_156d_b797, + NULL +}; +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0003, + &pci_ss_info_1103_0004_1103_0004, + &pci_ss_info_1103_0004_1103_0005, + &pci_ss_info_1103_0004_1103_0006, + &pci_ss_info_1103_0004_1103_0007, + &pci_ss_info_1103_0004_1103_0008, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#define pci_ss_list_1103_0009 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1105_8401 NULL +#define pci_ss_list_1105_8470 NULL +#define pci_ss_list_1105_8471 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105_8475[] = { + &pci_ss_info_1105_8475_1105_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1105_8476[] = { + &pci_ss_info_1105_8476_127d_0000, + NULL +}; +#define pci_ss_list_1105_8485 NULL +#define pci_ss_list_1105_8486 NULL +#endif +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +#define pci_ss_list_1106_0204 NULL +#define pci_ss_list_1106_0238 NULL +#define pci_ss_list_1106_0259 NULL +#define pci_ss_list_1106_0269 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106_0282[] = { + &pci_ss_info_1106_0282_1043_80a3, + NULL +}; +#define pci_ss_list_1106_0290 NULL +#define pci_ss_list_1106_0296 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1019_0987, + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0308 NULL +#define pci_ss_list_1106_0314 NULL +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1019_0985, + &pci_ss_info_1106_0571_1019_0a81, + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1043_808c, + &pci_ss_info_1106_0571_1043_80a1, + &pci_ss_info_1106_0571_1043_80ed, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1297_f641, + &pci_ss_info_1106_0571_1458_5002, + &pci_ss_info_1106_0571_1462_7020, + &pci_ss_info_1106_0571_147b_1407, + &pci_ss_info_1106_0571_1849_0571, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0591 NULL +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0605[] = { + &pci_ss_info_1106_0605_1043_802c, + NULL +}; +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1019_0985, + &pci_ss_info_1106_0686_1043_802c, + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1019_0985, + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1204 NULL +#define pci_ss_list_1106_1208 NULL +#define pci_ss_list_1106_1238 NULL +#define pci_ss_list_1106_1258 NULL +#define pci_ss_list_1106_1259 NULL +#define pci_ss_list_1106_1269 NULL +#define pci_ss_list_1106_1282 NULL +#define pci_ss_list_1106_1290 NULL +#define pci_ss_list_1106_1296 NULL +#define pci_ss_list_1106_1308 NULL +#define pci_ss_list_1106_1314 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +#define pci_ss_list_1106_2204 NULL +#define pci_ss_list_1106_2208 NULL +#define pci_ss_list_1106_2238 NULL +#define pci_ss_list_1106_2258 NULL +#define pci_ss_list_1106_2259 NULL +#define pci_ss_list_1106_2269 NULL +#define pci_ss_list_1106_2282 NULL +#define pci_ss_list_1106_2290 NULL +#define pci_ss_list_1106_2296 NULL +#define pci_ss_list_1106_2308 NULL +#define pci_ss_list_1106_2314 NULL +#define pci_ss_list_1106_287a NULL +#define pci_ss_list_1106_287b NULL +#define pci_ss_list_1106_287c NULL +#define pci_ss_list_1106_287d NULL +#define pci_ss_list_1106_287e NULL +#define pci_ss_list_1106_3022 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1019_0985, + &pci_ss_info_1106_3038_1019_0a81, + &pci_ss_info_1106_3038_1043_8080, + &pci_ss_info_1106_3038_1043_808c, + &pci_ss_info_1106_3038_1043_80a1, + &pci_ss_info_1106_3038_1043_80ed, + &pci_ss_info_1106_3038_1179_0001, + &pci_ss_info_1106_3038_1458_5004, + &pci_ss_info_1106_3038_1462_7020, + &pci_ss_info_1106_3038_147b_1407, + &pci_ss_info_1106_3038_182d_201d, + &pci_ss_info_1106_3038_1849_3038, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3044[] = { + &pci_ss_info_1106_3044_0574_086c, + &pci_ss_info_1106_3044_1025_005a, + &pci_ss_info_1106_3044_1043_808a, + &pci_ss_info_1106_3044_1458_1000, + &pci_ss_info_1106_3044_1462_702d, + &pci_ss_info_1106_3044_1462_971d, + NULL +}; +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +#define pci_ss_list_1106_3053 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1019_0985, + &pci_ss_info_1106_3057_1019_0987, + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_0097, + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1019_0985, + &pci_ss_info_1106_3058_1019_0987, + &pci_ss_info_1106_3058_1043_1106, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_1462_3300, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1019_0a81, + &pci_ss_info_1106_3059_1043_8095, + &pci_ss_info_1106_3059_1043_80a1, + &pci_ss_info_1106_3059_1043_80b0, + &pci_ss_info_1106_3059_1043_812a, + &pci_ss_info_1106_3059_1106_3059, + &pci_ss_info_1106_3059_1106_4161, + &pci_ss_info_1106_3059_1297_c160, + &pci_ss_info_1106_3059_1458_a002, + &pci_ss_info_1106_3059_1462_0080, + &pci_ss_info_1106_3059_1462_3800, + &pci_ss_info_1106_3059_147b_1407, + &pci_ss_info_1106_3059_1849_9761, + &pci_ss_info_1106_3059_4005_4710, + &pci_ss_info_1106_3059_a0a0_01b6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1043_80a1, + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + &pci_ss_info_1106_3065_13b9_1421, + &pci_ss_info_1106_3065_1695_3005, + &pci_ss_info_1106_3065_1695_300c, + &pci_ss_info_1106_3065_1849_3065, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3068[] = { + &pci_ss_info_1106_3068_1462_309e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + &pci_ss_info_1106_3099_1849_3099, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1019_0a81, + &pci_ss_info_1106_3104_1043_808c, + &pci_ss_info_1106_3104_1043_80a1, + &pci_ss_info_1106_3104_1043_80ed, + &pci_ss_info_1106_3104_1297_f641, + &pci_ss_info_1106_3104_1458_5004, + &pci_ss_info_1106_3104_1462_7020, + &pci_ss_info_1106_3104_147b_1407, + &pci_ss_info_1106_3104_182d_201d, + &pci_ss_info_1106_3104_1849_3104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3106[] = { + &pci_ss_info_1106_3106_1186_1403, + NULL +}; +#define pci_ss_list_1106_3108 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3113 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3116[] = { + &pci_ss_info_1106_3116_1297_f641, + NULL +}; +#define pci_ss_list_1106_3118 NULL +#define pci_ss_list_1106_3119 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3147[] = { + &pci_ss_info_1106_3147_1043_808c, + NULL +}; +#define pci_ss_list_1106_3148 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3149[] = { + &pci_ss_info_1106_3149_1043_80ed, + &pci_ss_info_1106_3149_1458_b003, + &pci_ss_info_1106_3149_1462_7020, + &pci_ss_info_1106_3149_147b_1407, + &pci_ss_info_1106_3149_147b_1408, + &pci_ss_info_1106_3149_1849_3149, + NULL +}; +#define pci_ss_list_1106_3156 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3164[] = { + &pci_ss_info_1106_3164_1462_7028, + NULL +}; +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1019_0a81, + &pci_ss_info_1106_3177_1043_808c, + &pci_ss_info_1106_3177_1043_80a1, + &pci_ss_info_1106_3177_1297_f641, + &pci_ss_info_1106_3177_1458_5001, + &pci_ss_info_1106_3177_1849_3177, + NULL +}; +#define pci_ss_list_1106_3178 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3188[] = { + &pci_ss_info_1106_3188_1043_80a3, + &pci_ss_info_1106_3188_147b_1407, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1043_807f, + &pci_ss_info_1106_3189_1458_5000, + &pci_ss_info_1106_3189_1849_3189, + NULL +}; +#define pci_ss_list_1106_3204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3205[] = { + &pci_ss_info_1106_3205_1458_5000, + NULL +}; +#define pci_ss_list_1106_3208 NULL +#define pci_ss_list_1106_3213 NULL +#define pci_ss_list_1106_3218 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3227[] = { + &pci_ss_info_1106_3227_1043_80ed, + &pci_ss_info_1106_3227_1106_3227, + &pci_ss_info_1106_3227_1458_5001, + &pci_ss_info_1106_3227_147b_1407, + &pci_ss_info_1106_3227_1849_3227, + NULL +}; +#define pci_ss_list_1106_3238 NULL +#define pci_ss_list_1106_3249 NULL +#define pci_ss_list_1106_3258 NULL +#define pci_ss_list_1106_3259 NULL +#define pci_ss_list_1106_3269 NULL +#define pci_ss_list_1106_3282 NULL +#define pci_ss_list_1106_3288 NULL +#define pci_ss_list_1106_3290 NULL +#define pci_ss_list_1106_3296 NULL +#define pci_ss_list_1106_3337 NULL +#define pci_ss_list_1106_3349 NULL +#define pci_ss_list_1106_337a NULL +#define pci_ss_list_1106_337b NULL +#define pci_ss_list_1106_4149 NULL +#define pci_ss_list_1106_4204 NULL +#define pci_ss_list_1106_4208 NULL +#define pci_ss_list_1106_4238 NULL +#define pci_ss_list_1106_4258 NULL +#define pci_ss_list_1106_4259 NULL +#define pci_ss_list_1106_4269 NULL +#define pci_ss_list_1106_4282 NULL +#define pci_ss_list_1106_4290 NULL +#define pci_ss_list_1106_4296 NULL +#define pci_ss_list_1106_4308 NULL +#define pci_ss_list_1106_4314 NULL +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_5208 NULL +#define pci_ss_list_1106_5238 NULL +#define pci_ss_list_1106_5290 NULL +#define pci_ss_list_1106_5308 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_7204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_7205[] = { + &pci_ss_info_1106_7205_1458_d000, + NULL +}; +#define pci_ss_list_1106_7208 NULL +#define pci_ss_list_1106_7238 NULL +#define pci_ss_list_1106_7258 NULL +#define pci_ss_list_1106_7259 NULL +#define pci_ss_list_1106_7269 NULL +#define pci_ss_list_1106_7282 NULL +#define pci_ss_list_1106_7290 NULL +#define pci_ss_list_1106_7296 NULL +#define pci_ss_list_1106_7308 NULL +#define pci_ss_list_1106_7314 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +static const pciSubsystemInfo *pci_ss_list_1106_8598[] = { + &pci_ss_info_1106_8598_1019_0985, + NULL +}; +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_a208 NULL +#define pci_ss_list_1106_a238 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b113 NULL +#define pci_ss_list_1106_b115 NULL +#define pci_ss_list_1106_b168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_b188[] = { + &pci_ss_info_1106_b188_147b_1407, + NULL +}; +#define pci_ss_list_1106_b198 NULL +#define pci_ss_list_1106_b213 NULL +#define pci_ss_list_1106_c208 NULL +#define pci_ss_list_1106_c238 NULL +#define pci_ss_list_1106_d104 NULL +#define pci_ss_list_1106_d208 NULL +#define pci_ss_list_1106_d213 NULL +#define pci_ss_list_1106_d238 NULL +#define pci_ss_list_1106_e208 NULL +#define pci_ss_list_1106_e238 NULL +#define pci_ss_list_1106_f208 NULL +#define pci_ss_list_1106_f238 NULL +#endif +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_0006 NULL +#define pci_ss_list_110a_0015 NULL +#define pci_ss_list_110a_001d NULL +#define pci_ss_list_110a_007b NULL +#define pci_ss_list_110a_007c NULL +#define pci_ss_list_110a_007d NULL +#define pci_ss_list_110a_2101 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_2104 NULL +#define pci_ss_list_110a_3142 NULL +#define pci_ss_list_110a_4021 NULL +#define pci_ss_list_110a_4029 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_1113_2242, + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#define pci_ss_list_1113_d301 NULL +#define pci_ss_list_1113_ec02 NULL +#endif +#define pci_ss_list_1114_0506 NULL +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0010 NULL +#define pci_ss_list_1119_0011 NULL +#define pci_ss_list_1119_0012 NULL +#define pci_ss_list_1119_0013 NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_02ff NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#define pci_ss_list_111a_1203 NULL +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111d_0004 NULL +#define pci_ss_list_111d_0005 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_112f_0008 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_5400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_5402[] = { + &pci_ss_info_1131_5402_1244_0f00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7130[] = { + &pci_ss_info_1131_7130_102b_48d0, + &pci_ss_info_1131_7130_1048_226b, + &pci_ss_info_1131_7130_1131_2001, + &pci_ss_info_1131_7130_1131_2005, + &pci_ss_info_1131_7130_1461_050c, + &pci_ss_info_1131_7130_1461_10ff, + &pci_ss_info_1131_7130_1461_2108, + &pci_ss_info_1131_7130_1461_2115, + &pci_ss_info_1131_7130_153b_1152, + &pci_ss_info_1131_7130_185b_c100, + &pci_ss_info_1131_7130_5168_0138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7133[] = { + &pci_ss_info_1131_7133_002b_11bd, + &pci_ss_info_1131_7133_1019_4cb5, + &pci_ss_info_1131_7133_1043_0210, + &pci_ss_info_1131_7133_1043_4843, + &pci_ss_info_1131_7133_1131_2001, + &pci_ss_info_1131_7133_1461_f31f, + &pci_ss_info_1131_7133_1489_0214, + &pci_ss_info_1131_7133_153b_1162, + &pci_ss_info_1131_7133_185b_c100, + &pci_ss_info_1131_7133_5168_0138, + &pci_ss_info_1131_7133_5168_0212, + &pci_ss_info_1131_7133_5168_0214, + &pci_ss_info_1131_7133_5168_0306, + &pci_ss_info_1131_7133_5168_0502, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7134[] = { + &pci_ss_info_1131_7134_1019_4cb4, + &pci_ss_info_1131_7134_1043_4840, + &pci_ss_info_1131_7134_1043_4842, + &pci_ss_info_1131_7134_1131_4e85, + &pci_ss_info_1131_7134_1131_6752, + &pci_ss_info_1131_7134_1131_7133, + &pci_ss_info_1131_7134_11bd_002b, + &pci_ss_info_1131_7134_11bd_002d, + &pci_ss_info_1131_7134_1461_2c00, + &pci_ss_info_1131_7134_1461_2c05, + &pci_ss_info_1131_7134_1461_a70a, + &pci_ss_info_1131_7134_1461_a70b, + &pci_ss_info_1131_7134_1461_d6ee, + &pci_ss_info_1131_7134_153b_1142, + &pci_ss_info_1131_7134_153b_1143, + &pci_ss_info_1131_7134_153b_1158, + &pci_ss_info_1131_7134_1540_9524, + &pci_ss_info_1131_7134_16be_0003, + &pci_ss_info_1131_7134_185b_c200, + &pci_ss_info_1131_7134_1894_a006, + &pci_ss_info_1131_7134_1894_fe01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7135[] = { + &pci_ss_info_1131_7135_1421_0350, + &pci_ss_info_1131_7135_1421_0370, + &pci_ss_info_1131_7135_5168_0212, + NULL +}; +#define pci_ss_list_1131_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_110a_0000, + &pci_ss_info_1131_7146_110a_ffff, + &pci_ss_info_1131_7146_1131_4f56, + &pci_ss_info_1131_7146_1131_4f60, + &pci_ss_info_1131_7146_1131_4f61, + &pci_ss_info_1131_7146_1131_5f61, + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + &pci_ss_info_1131_7146_11bd_000f, + &pci_ss_info_1131_7146_13c2_0000, + &pci_ss_info_1131_7146_13c2_0001, + &pci_ss_info_1131_7146_13c2_0002, + &pci_ss_info_1131_7146_13c2_0003, + &pci_ss_info_1131_7146_13c2_0004, + &pci_ss_info_1131_7146_13c2_0006, + &pci_ss_info_1131_7146_13c2_0008, + &pci_ss_info_1131_7146_13c2_000a, + &pci_ss_info_1131_7146_13c2_1003, + &pci_ss_info_1131_7146_13c2_1004, + &pci_ss_info_1131_7146_13c2_1005, + &pci_ss_info_1131_7146_13c2_100c, + &pci_ss_info_1131_7146_13c2_100f, + &pci_ss_info_1131_7146_13c2_1011, + &pci_ss_info_1131_7146_13c2_1013, + &pci_ss_info_1131_7146_13c2_1102, + NULL +}; +#define pci_ss_list_1131_9730 NULL +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#define pci_ss_list_1133_e001 NULL +#define pci_ss_list_1133_e002 NULL +#define pci_ss_list_1133_e003 NULL +#define pci_ss_list_1133_e004 NULL +#define pci_ss_list_1133_e005 NULL +#define pci_ss_list_1133_e006 NULL +#define pci_ss_list_1133_e007 NULL +#define pci_ss_list_1133_e008 NULL +#define pci_ss_list_1133_e009 NULL +#define pci_ss_list_1133_e00a NULL +#define pci_ss_list_1133_e00b NULL +#define pci_ss_list_1133_e00c NULL +#define pci_ss_list_1133_e00d NULL +#define pci_ss_list_1133_e00e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_110a_0021, + NULL +}; +#define pci_ss_list_1133_e011 NULL +#define pci_ss_list_1133_e012 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e013[] = { + &pci_ss_info_1133_e013_1133_1300, + &pci_ss_info_1133_e013_1133_e013, + NULL +}; +#define pci_ss_list_1133_e014 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e015[] = { + &pci_ss_info_1133_e015_1133_e015, + NULL +}; +#define pci_ss_list_1133_e016 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e017[] = { + &pci_ss_info_1133_e017_1133_e017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e018[] = { + &pci_ss_info_1133_e018_1133_1800, + &pci_ss_info_1133_e018_1133_e018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e019[] = { + &pci_ss_info_1133_e019_1133_e019, + NULL +}; +#define pci_ss_list_1133_e01a NULL +static const pciSubsystemInfo *pci_ss_list_1133_e01b[] = { + &pci_ss_info_1133_e01b_1133_e01b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e01c[] = { + &pci_ss_info_1133_e01c_1133_1c01, + &pci_ss_info_1133_e01c_1133_1c02, + &pci_ss_info_1133_e01c_1133_1c03, + &pci_ss_info_1133_e01c_1133_1c04, + &pci_ss_info_1133_e01c_1133_1c05, + &pci_ss_info_1133_e01c_1133_1c06, + &pci_ss_info_1133_e01c_1133_1c07, + &pci_ss_info_1133_e01c_1133_1c08, + &pci_ss_info_1133_e01c_1133_1c09, + &pci_ss_info_1133_e01c_1133_1c0a, + &pci_ss_info_1133_e01c_1133_1c0b, + &pci_ss_info_1133_e01c_1133_1c0c, + NULL +}; +#define pci_ss_list_1133_e01e NULL +#define pci_ss_list_1133_e020 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e024[] = { + &pci_ss_info_1133_e024_1133_2400, + &pci_ss_info_1133_e024_1133_e024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e028[] = { + &pci_ss_info_1133_e028_1133_2800, + &pci_ss_info_1133_e028_1133_e028, + NULL +}; +#define pci_ss_list_1133_e02a NULL +#define pci_ss_list_1133_e02c NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1134_0002 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#define pci_ss_list_1145_f020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2971, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2973, + &pci_ss_info_1148_4300_1259_2974, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2976, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_0121, + &pci_ss_info_1148_4320_1148_0221, + &pci_ss_info_1148_4320_1148_0321, + &pci_ss_info_1148_4320_1148_0421, + &pci_ss_info_1148_4320_1148_0621, + &pci_ss_info_1148_4320_1148_0721, + &pci_ss_info_1148_4320_1148_0821, + &pci_ss_info_1148_4320_1148_0921, + &pci_ss_info_1148_4320_1148_1121, + &pci_ss_info_1148_4320_1148_1221, + &pci_ss_info_1148_4320_1148_3221, + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#define pci_ss_list_1148_4500 NULL +#define pci_ss_list_1148_9000 NULL +#define pci_ss_list_1148_9843 NULL +static const pciSubsystemInfo *pci_ss_list_1148_9e00[] = { + &pci_ss_info_1148_9e00_1148_2100, + &pci_ss_info_1148_9e00_1148_21d0, + &pci_ss_info_1148_9e00_1148_2200, + &pci_ss_info_1148_9e00_1148_8100, + &pci_ss_info_1148_9e00_1148_8200, + &pci_ss_info_1148_9e00_1148_9100, + &pci_ss_info_1148_9e00_1148_9200, + NULL +}; +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0013 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0028 NULL +#define pci_ss_list_114f_0029 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0043 NULL +#define pci_ss_list_114f_0044 NULL +#define pci_ss_list_114f_0045 NULL +#define pci_ss_list_114f_004e NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_00b0 NULL +#define pci_ss_list_114f_00b1 NULL +#define pci_ss_list_114f_00c8 NULL +#define pci_ss_list_114f_00c9 NULL +#define pci_ss_list_114f_00ca NULL +#define pci_ss_list_114f_00cb NULL +#define pci_ss_list_114f_00d0 NULL +#define pci_ss_list_114f_00d1 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_0182, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +#define pci_ss_list_115d_00d4 NULL +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0000 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0006 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0036 NULL +#define pci_ss_list_1166_0101 NULL +#define pci_ss_list_1166_0104 NULL +#define pci_ss_list_1166_0110 NULL +#define pci_ss_list_1166_0130 NULL +#define pci_ss_list_1166_0132 NULL +#define pci_ss_list_1166_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166_0201[] = { + &pci_ss_info_1166_0201_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0203[] = { + &pci_ss_info_1166_0203_1734_1012, + NULL +}; +#define pci_ss_list_1166_0205 NULL +#define pci_ss_list_1166_0211 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0212[] = { + &pci_ss_info_1166_0212_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0213[] = { + &pci_ss_info_1166_0213_1028_c134, + &pci_ss_info_1166_0213_1734_1012, + NULL +}; +#define pci_ss_list_1166_0214 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0217[] = { + &pci_ss_info_1166_0217_1028_4134, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0220[] = { + &pci_ss_info_1166_0220_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0221[] = { + &pci_ss_info_1166_0221_1734_1012, + NULL +}; +#define pci_ss_list_1166_0223 NULL +#define pci_ss_list_1166_0225 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0227[] = { + &pci_ss_info_1166_0227_1734_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0230[] = { + &pci_ss_info_1166_0230_4c53_1080, + NULL +}; +#define pci_ss_list_1166_0234 NULL +#define pci_ss_list_1166_0240 NULL +#define pci_ss_list_1166_0241 NULL +#define pci_ss_list_1166_0242 NULL +#define pci_ss_list_1166_024a NULL +#endif +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0102 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0601[] = { + &pci_ss_info_1179_0601_1179_0001, + NULL +}; +#define pci_ss_list_1179_0603 NULL +static const pciSubsystemInfo *pci_ss_list_1179_060a[] = { + &pci_ss_info_1179_060a_1179_0001, + NULL +}; +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c_0030[] = { + &pci_ss_info_117c_0030_117c_8013, + &pci_ss_info_117c_0030_117c_8014, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_1028_0188, + &pci_ss_info_1180_0476_1043_1967, + &pci_ss_info_1180_0476_1043_1987, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + &pci_ss_info_1180_0476_14ef_0220, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +#define pci_ss_list_1180_0511 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + &pci_ss_info_1180_0522_1043_1967, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + NULL +}; +#define pci_ss_list_1180_0554 NULL +#define pci_ss_list_1180_0575 NULL +#define pci_ss_list_1180_0576 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0592[] = { + &pci_ss_info_1180_0592_1043_1967, + NULL +}; +#define pci_ss_list_1180_0811 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0822[] = { + &pci_ss_info_1180_0822_1014_0556, + &pci_ss_info_1180_0822_1028_0188, + &pci_ss_info_1180_0822_1028_01a2, + &pci_ss_info_1180_0822_1043_1967, + NULL +}; +#define pci_ss_list_1180_0841 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0852[] = { + &pci_ss_info_1180_0852_1043_1967, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +#define pci_ss_list_1186_1025 NULL +#define pci_ss_list_1186_1026 NULL +#define pci_ss_list_1186_1043 NULL +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + &pci_ss_info_1186_1300_1186_1303, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1541 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_2027 NULL +#define pci_ss_list_1186_3203 NULL +#define pci_ss_list_1186_3300 NULL +#define pci_ss_list_1186_3a03 NULL +#define pci_ss_list_1186_3a04 NULL +#define pci_ss_list_1186_3a05 NULL +#define pci_ss_list_1186_3a07 NULL +#define pci_ss_list_1186_3a08 NULL +#define pci_ss_list_1186_3a10 NULL +#define pci_ss_list_1186_3a11 NULL +#define pci_ss_list_1186_3a12 NULL +#define pci_ss_list_1186_3a13 NULL +#define pci_ss_list_1186_3a14 NULL +#define pci_ss_list_1186_3a63 NULL +#define pci_ss_list_1186_4000 NULL +#define pci_ss_list_1186_4300 NULL +static const pciSubsystemInfo *pci_ss_list_1186_4c00[] = { + &pci_ss_info_1186_4c00_1186_4c00, + NULL +}; +#define pci_ss_list_1186_8400 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1191_8060 NULL +#define pci_ss_list_1191_8080 NULL +#define pci_ss_list_1191_8081 NULL +#define pci_ss_list_1191_808a NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_1197_010c NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_138f NULL +#define pci_ss_list_11ab_1fa6 NULL +#define pci_ss_list_11ab_1fa7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab_1faa[] = { + &pci_ss_info_11ab_1faa_1385_4e00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4320[] = { + &pci_ss_info_11ab_4320_1019_0f38, + &pci_ss_info_11ab_4320_1019_8001, + &pci_ss_info_11ab_4320_1043_173c, + &pci_ss_info_11ab_4320_1043_811a, + &pci_ss_info_11ab_4320_105b_0c19, + &pci_ss_info_11ab_4320_10b8_b452, + &pci_ss_info_11ab_4320_11ab_0121, + &pci_ss_info_11ab_4320_11ab_0321, + &pci_ss_info_11ab_4320_11ab_1021, + &pci_ss_info_11ab_4320_11ab_5021, + &pci_ss_info_11ab_4320_11ab_9521, + &pci_ss_info_11ab_4320_1458_e000, + &pci_ss_info_11ab_4320_147b_1406, + &pci_ss_info_11ab_4320_15d4_0047, + &pci_ss_info_11ab_4320_1695_9025, + &pci_ss_info_11ab_4320_17f2_1c03, + &pci_ss_info_11ab_4320_270f_2803, + NULL +}; +#define pci_ss_list_11ab_4340 NULL +#define pci_ss_list_11ab_4341 NULL +#define pci_ss_list_11ab_4342 NULL +#define pci_ss_list_11ab_4343 NULL +#define pci_ss_list_11ab_4344 NULL +#define pci_ss_list_11ab_4345 NULL +#define pci_ss_list_11ab_4346 NULL +#define pci_ss_list_11ab_4347 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4350[] = { + &pci_ss_info_11ab_4350_1179_0001, + &pci_ss_info_11ab_4350_11ab_3521, + &pci_ss_info_11ab_4350_1854_000d, + &pci_ss_info_11ab_4350_1854_000e, + &pci_ss_info_11ab_4350_1854_000f, + &pci_ss_info_11ab_4350_1854_0011, + &pci_ss_info_11ab_4350_1854_0012, + &pci_ss_info_11ab_4350_1854_0016, + &pci_ss_info_11ab_4350_1854_0017, + &pci_ss_info_11ab_4350_1854_0018, + &pci_ss_info_11ab_4350_1854_0019, + &pci_ss_info_11ab_4350_1854_001c, + &pci_ss_info_11ab_4350_1854_001e, + &pci_ss_info_11ab_4350_1854_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4351[] = { + &pci_ss_info_11ab_4351_107b_4009, + &pci_ss_info_11ab_4351_10f7_8338, + &pci_ss_info_11ab_4351_1179_0001, + &pci_ss_info_11ab_4351_1179_ff00, + &pci_ss_info_11ab_4351_1179_ff10, + &pci_ss_info_11ab_4351_11ab_3621, + &pci_ss_info_11ab_4351_13d1_ac12, + &pci_ss_info_11ab_4351_161f_203d, + &pci_ss_info_11ab_4351_1854_000d, + &pci_ss_info_11ab_4351_1854_000e, + &pci_ss_info_11ab_4351_1854_000f, + &pci_ss_info_11ab_4351_1854_0011, + &pci_ss_info_11ab_4351_1854_0012, + &pci_ss_info_11ab_4351_1854_0016, + &pci_ss_info_11ab_4351_1854_0017, + &pci_ss_info_11ab_4351_1854_0018, + &pci_ss_info_11ab_4351_1854_0019, + &pci_ss_info_11ab_4351_1854_001c, + &pci_ss_info_11ab_4351_1854_001e, + &pci_ss_info_11ab_4351_1854_0020, + NULL +}; +#define pci_ss_list_11ab_4352 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4360[] = { + &pci_ss_info_11ab_4360_1043_8134, + &pci_ss_info_11ab_4360_107b_4009, + &pci_ss_info_11ab_4360_11ab_5221, + &pci_ss_info_11ab_4360_1458_e000, + &pci_ss_info_11ab_4360_1462_052c, + &pci_ss_info_11ab_4360_1849_8052, + &pci_ss_info_11ab_4360_a0a0_0509, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4361[] = { + &pci_ss_info_11ab_4361_107b_3015, + &pci_ss_info_11ab_4361_11ab_5021, + &pci_ss_info_11ab_4361_8086_3063, + &pci_ss_info_11ab_4361_8086_3439, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4362[] = { + &pci_ss_info_11ab_4362_103c_2a0d, + &pci_ss_info_11ab_4362_1043_8142, + &pci_ss_info_11ab_4362_109f_3197, + &pci_ss_info_11ab_4362_10f7_8338, + &pci_ss_info_11ab_4362_10fd_a430, + &pci_ss_info_11ab_4362_1179_0001, + &pci_ss_info_11ab_4362_1179_ff00, + &pci_ss_info_11ab_4362_1179_ff10, + &pci_ss_info_11ab_4362_11ab_5321, + &pci_ss_info_11ab_4362_1297_c240, + &pci_ss_info_11ab_4362_1297_c241, + &pci_ss_info_11ab_4362_1297_c242, + &pci_ss_info_11ab_4362_1297_c243, + &pci_ss_info_11ab_4362_1297_c244, + &pci_ss_info_11ab_4362_13d1_ac11, + &pci_ss_info_11ab_4362_1458_e000, + &pci_ss_info_11ab_4362_1462_058c, + &pci_ss_info_11ab_4362_14c0_0012, + &pci_ss_info_11ab_4362_1558_04a0, + &pci_ss_info_11ab_4362_15bd_1003, + &pci_ss_info_11ab_4362_161f_203c, + &pci_ss_info_11ab_4362_161f_203d, + &pci_ss_info_11ab_4362_1695_9029, + &pci_ss_info_11ab_4362_17f2_2c08, + &pci_ss_info_11ab_4362_17ff_0585, + &pci_ss_info_11ab_4362_1849_8053, + &pci_ss_info_11ab_4362_1854_000b, + &pci_ss_info_11ab_4362_1854_000c, + &pci_ss_info_11ab_4362_1854_0010, + &pci_ss_info_11ab_4362_1854_0013, + &pci_ss_info_11ab_4362_1854_0014, + &pci_ss_info_11ab_4362_1854_0015, + &pci_ss_info_11ab_4362_1854_001a, + &pci_ss_info_11ab_4362_1854_001b, + &pci_ss_info_11ab_4362_1854_001d, + &pci_ss_info_11ab_4362_1854_001f, + &pci_ss_info_11ab_4362_1854_0021, + &pci_ss_info_11ab_4362_1854_0022, + &pci_ss_info_11ab_4362_270f_2801, + &pci_ss_info_11ab_4362_a0a0_0506, + NULL +}; +#define pci_ss_list_11ab_4363 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_5005 NULL +#define pci_ss_list_11ab_5040 NULL +#define pci_ss_list_11ab_5041 NULL +#define pci_ss_list_11ab_5080 NULL +#define pci_ss_list_11ab_5081 NULL +#define pci_ss_list_11ab_6041 NULL +#define pci_ss_list_11ab_6081 NULL +#define pci_ss_list_11ab_6460 NULL +#define pci_ss_list_11ab_6480 NULL +#define pci_ss_list_11ab_f003 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11af_0001 NULL +#define pci_ss_list_11af_ee40 NULL +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#define pci_ss_list_11bd_bede NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0445[] = { + &pci_ss_info_11c1_0445_8086_2203, + &pci_ss_info_11c1_0445_8086_2204, + NULL +}; +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_1033_80a8, + &pci_ss_info_11c1_0450_144f_4005, + &pci_ss_info_11c1_0450_1468_0450, + &pci_ss_info_11c1_0450_4005_144f, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_048c NULL +#define pci_ss_list_11c1_048f NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_8086_524c, + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +#define pci_ss_list_11c1_8110 NULL +#define pci_ss_list_11c1_ab10 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab11[] = { + &pci_ss_info_11c1_ab11_11c1_ab12, + &pci_ss_info_11c1_ab11_11c1_ab13, + &pci_ss_info_11c1_ab11_11c1_ab15, + &pci_ss_info_11c1_ab11_11c1_ab16, + NULL +}; +#define pci_ss_list_11c1_ab20 NULL +#define pci_ss_list_11c1_ab21 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab30[] = { + &pci_ss_info_11c1_ab30_14cd_2012, + NULL +}; +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1535 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d4_5340 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_12f8_8a02, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + &pci_ss_info_11de_6120_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_11e3_0001 NULL +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_000d NULL +#define pci_ss_list_11fe_000e NULL +#define pci_ss_list_11fe_000f NULL +#define pci_ss_list_11fe_0801 NULL +#define pci_ss_list_11fe_0802 NULL +#define pci_ss_list_11fe_0803 NULL +#define pci_ss_list_11fe_0805 NULL +#define pci_ss_list_11fe_080c NULL +#define pci_ss_list_11fe_080d NULL +#define pci_ss_list_11fe_0812 NULL +#define pci_ss_list_11fe_0903 NULL +#define pci_ss_list_11fe_8015 NULL +#define pci_ss_list_11ff_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1014_020c, + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_7110[] = { + &pci_ss_info_1217_7110_103c_088c, + &pci_ss_info_1217_7110_103c_0890, + NULL +}; +#define pci_ss_list_1217_7112 NULL +#define pci_ss_list_1217_7113 NULL +#define pci_ss_list_1217_7114 NULL +#define pci_ss_list_1217_7134 NULL +#define pci_ss_list_1217_71e2 NULL +#define pci_ss_list_1217_7212 NULL +#define pci_ss_list_1217_7213 NULL +static const pciSubsystemInfo *pci_ss_list_1217_7223[] = { + &pci_ss_info_1217_7223_103c_088c, + &pci_ss_info_1217_7223_103c_0890, + NULL +}; +#define pci_ss_list_1217_7233 NULL +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0057, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0003, + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_1227_0006 NULL +#define pci_ss_list_1227_0023 NULL +#define pci_ss_list_122d_1206 NULL +#define pci_ss_list_122d_1400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + &pci_ss_info_123f_8120_11bd_000f, + &pci_ss_info_123f_8120_1809_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#define pci_ss_list_1242_6562 NULL +#define pci_ss_list_1242_656a NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#define pci_ss_list_1244_2700 NULL +#define pci_ss_list_1244_2900 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_1259_a117 NULL +#define pci_ss_list_1259_a120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125b_1400[] = { + &pci_ss_info_125b_1400_1186_1100, + NULL +}; +#endif +#define pci_ss_list_125c_0101 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + &pci_ss_info_125d_1969_153b_111b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_0e11_0098, + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00b1, + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3872[] = { + &pci_ss_info_1260_3872_1468_0202, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1186_3700, + &pci_ss_info_1260_3873_1385_4105, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_16a5_1601, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3886[] = { + &pci_ss_info_1260_3886_17cf_0037, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3890[] = { + &pci_ss_info_1260_3890_10b8_2802, + &pci_ss_info_1260_3890_10b8_2835, + &pci_ss_info_1260_3890_10b8_a835, + &pci_ss_info_1260_3890_1113_4203, + &pci_ss_info_1260_3890_1113_ee03, + &pci_ss_info_1260_3890_1113_ee08, + &pci_ss_info_1260_3890_1186_3202, + &pci_ss_info_1260_3890_1259_c104, + &pci_ss_info_1260_3890_1385_4800, + &pci_ss_info_1260_3890_16a5_1605, + &pci_ss_info_1260_3890_17cf_0014, + &pci_ss_info_1260_3890_17cf_0020, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +#define pci_ss_list_1260_ffff NULL +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126c_1211 NULL +#define pci_ss_list_126c_126c NULL +#define pci_ss_list_126f_0501 NULL +#define pci_ss_list_126f_0510 NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0730 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#define pci_ss_list_1274_1171 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1274_8001, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4541, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1274_8001, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1278_0710 NULL +#define pci_ss_list_1279_0060 NULL +#define pci_ss_list_1279_0061 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1005_127a, + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#define pci_ss_list_1283_8211 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283_8212[] = { + &pci_ss_info_1283_8212_1283_0001, + NULL +}; +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8872 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#endif +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12a3_8105 NULL +#define pci_ss_list_12ab_0000 NULL +#define pci_ss_list_12ab_0002 NULL +#define pci_ss_list_12ab_3000 NULL +#define pci_ss_list_12ab_fff3 NULL +#define pci_ss_list_12ab_ffff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_1014_0104, + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_10a9_8002, + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#define pci_ss_list_12ae_00fa NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c4_0001 NULL +#define pci_ss_list_12c4_0002 NULL +#define pci_ss_list_12c4_0003 NULL +#define pci_ss_list_12c4_0004 NULL +#define pci_ss_list_12c4_0005 NULL +#define pci_ss_list_12c4_0006 NULL +#define pci_ss_list_12c4_0007 NULL +#define pci_ss_list_12c4_0008 NULL +#define pci_ss_list_12c4_0009 NULL +#define pci_ss_list_12c4_000a NULL +#define pci_ss_list_12c4_000b NULL +#define pci_ss_list_12c4_000c NULL +#define pci_ss_list_12c4_000d NULL +#define pci_ss_list_12c4_0100 NULL +#define pci_ss_list_12c4_0201 NULL +#define pci_ss_list_12c4_0202 NULL +#define pci_ss_list_12c4_0300 NULL +#define pci_ss_list_12c4_0301 NULL +#define pci_ss_list_12c4_0302 NULL +#define pci_ss_list_12c4_0310 NULL +#define pci_ss_list_12c4_0311 NULL +#define pci_ss_list_12c4_0312 NULL +#define pci_ss_list_12c4_0320 NULL +#define pci_ss_list_12c4_0321 NULL +#define pci_ss_list_12c4_0322 NULL +#define pci_ss_list_12c4_0330 NULL +#define pci_ss_list_12c4_0331 NULL +#define pci_ss_list_12c4_0332 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12d4_0200 NULL +#define pci_ss_list_12d5_0003 NULL +#define pci_ss_list_12d5_1000 NULL +#define pci_ss_list_12d8_8150 NULL +#define pci_ss_list_12d9_0002 NULL +#define pci_ss_list_12d9_0004 NULL +#define pci_ss_list_12d9_0005 NULL +#define pci_ss_list_12de_0200 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_12fb_0001 NULL +#define pci_ss_list_12fb_00f5 NULL +#define pci_ss_list_12fb_02ad NULL +#define pci_ss_list_12fb_2adc NULL +#define pci_ss_list_12fb_3100 NULL +#define pci_ss_list_12fb_3500 NULL +#define pci_ss_list_12fb_4d4f NULL +#define pci_ss_list_12fb_8120 NULL +#define pci_ss_list_12fb_da62 NULL +#define pci_ss_list_12fb_db62 NULL +#define pci_ss_list_12fb_dc62 NULL +#define pci_ss_list_12fb_dd62 NULL +#define pci_ss_list_12fb_eddc NULL +#define pci_ss_list_12fb_fa01 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#define pci_ss_list_1307_004d NULL +#define pci_ss_list_1307_0052 NULL +#define pci_ss_list_1307_0054 NULL +#define pci_ss_list_1307_005e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#define pci_ss_list_1317_0985 NULL +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1317_2850 NULL +#define pci_ss_list_1317_5120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317_8201[] = { + &pci_ss_info_1317_8201_10b8_2635, + &pci_ss_info_1317_8201_1317_8201, + NULL +}; +#define pci_ss_list_1317_8211 NULL +#define pci_ss_list_1317_9511 NULL +#endif +#define pci_ss_list_1318_0911 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319_0801[] = { + &pci_ss_info_1319_0801_1319_1319, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1319_0802[] = { + &pci_ss_info_1319_0802_1319_1319, + NULL +}; +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#endif +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#define pci_ss_list_131f_2081 NULL +#endif +#define pci_ss_list_1331_0030 NULL +#define pci_ss_list_1331_8200 NULL +#define pci_ss_list_1331_8201 NULL +#define pci_ss_list_1331_8202 NULL +#define pci_ss_list_1331_8210 NULL +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_1332_5425 NULL +#define pci_ss_list_1332_6140 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_2189 NULL +#define pci_ss_list_134d_2486 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7890[] = { + &pci_ss_info_134d_7890_134d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_5101 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1360_0101 NULL +#define pci_ss_list_1360_0102 NULL +#define pci_ss_list_1360_0103 NULL +#define pci_ss_list_1360_0201 NULL +#define pci_ss_list_1360_0202 NULL +#define pci_ss_list_1360_0203 NULL +#define pci_ss_list_1360_0301 NULL +#define pci_ss_list_1360_0302 NULL +#define pci_ss_list_136b_ff01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371_434e[] = { + &pci_ss_info_1371_434e_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1374_0024 NULL +#define pci_ss_list_1374_0025 NULL +#define pci_ss_list_1374_0026 NULL +#define pci_ss_list_1374_0027 NULL +#define pci_ss_list_1374_0029 NULL +#define pci_ss_list_1374_002a NULL +#define pci_ss_list_1374_002b NULL +#define pci_ss_list_1374_002c NULL +#define pci_ss_list_1374_002d NULL +#define pci_ss_list_1374_002e NULL +#define pci_ss_list_1374_002f NULL +#define pci_ss_list_1374_0030 NULL +#define pci_ss_list_1374_0031 NULL +#define pci_ss_list_1374_0032 NULL +#define pci_ss_list_1374_0034 NULL +#define pci_ss_list_1374_0035 NULL +#define pci_ss_list_1374_0036 NULL +#define pci_ss_list_1374_0037 NULL +#define pci_ss_list_1374_0038 NULL +#define pci_ss_list_1374_0039 NULL +#define pci_ss_list_1374_003a NULL +#define pci_ss_list_137a_0001 NULL +#define pci_ss_list_1382_0001 NULL +#define pci_ss_list_1382_2008 NULL +#define pci_ss_list_1382_2088 NULL +#define pci_ss_list_1382_20c8 NULL +#define pci_ss_list_1382_4008 NULL +#define pci_ss_list_1382_4010 NULL +#define pci_ss_list_1382_4048 NULL +#define pci_ss_list_1382_4088 NULL +#define pci_ss_list_1382_4248 NULL +#define pci_ss_list_1385_0013 NULL +#define pci_ss_list_1385_311a NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_4105 NULL +#define pci_ss_list_1385_4400 NULL +#define pci_ss_list_1385_4600 NULL +#define pci_ss_list_1385_4601 NULL +#define pci_ss_list_1385_4610 NULL +#define pci_ss_list_1385_4800 NULL +#define pci_ss_list_1385_4900 NULL +#define pci_ss_list_1385_4a00 NULL +#define pci_ss_list_1385_4b00 NULL +#define pci_ss_list_1385_4c00 NULL +#define pci_ss_list_1385_4e00 NULL +#define pci_ss_list_1385_4f00 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_6b00 NULL +#define pci_ss_list_1385_f004 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1141 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#define pci_ss_list_1397_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_0675_1704, + &pci_ss_info_1397_2bd0_0675_1708, + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a3_001d NULL +#define pci_ss_list_13a3_0020 NULL +#define pci_ss_list_13a3_0026 NULL +#define pci_ss_list_13a8_0152 NULL +#define pci_ss_list_13a8_0154 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c0_0020 NULL +#define pci_ss_list_13c0_0030 NULL +#define pci_ss_list_13c0_0210 NULL +#define pci_ss_list_13c1_1000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1_1001[] = { + &pci_ss_info_13c1_1001_13c1_1001, + NULL +}; +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13c1_1003 NULL +#endif +#define pci_ss_list_13c6_0520 NULL +#define pci_ss_list_13c6_0620 NULL +#define pci_ss_list_13c6_0820 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d0_2200 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab03 NULL +#define pci_ss_list_13d1_ab06 NULL +#define pci_ss_list_13d1_ab08 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13f0_0200 NULL +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f0_1023 NULL +#define pci_ss_list_13f4_1401 NULL +#define pci_ss_list_13f6_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8035, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + &pci_ss_info_13f6_0111_1681_a000, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1240 NULL +#define pci_ss_list_13fe_1600 NULL +#define pci_ss_list_13fe_1733 NULL +#define pci_ss_list_13fe_1752 NULL +#define pci_ss_list_13fe_1754 NULL +#define pci_ss_list_13fe_1756 NULL +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0110 NULL +#define pci_ss_list_1407_0111 NULL +#define pci_ss_list_1407_0120 NULL +#define pci_ss_list_1407_0121 NULL +#define pci_ss_list_1407_0180 NULL +#define pci_ss_list_1407_0181 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0220 NULL +#define pci_ss_list_1407_0221 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412_1712[] = { + &pci_ss_info_1412_1712_1412_1712, + &pci_ss_info_1412_1712_1412_d630, + &pci_ss_info_1412_1712_1412_d631, + &pci_ss_info_1412_1712_1412_d632, + &pci_ss_info_1412_1712_1412_d633, + &pci_ss_info_1412_1712_1412_d634, + &pci_ss_info_1412_1712_1412_d635, + &pci_ss_info_1412_1712_1412_d637, + &pci_ss_info_1412_1712_1412_d638, + &pci_ss_info_1412_1712_1412_d63b, + &pci_ss_info_1412_1712_1412_d63c, + &pci_ss_info_1412_1712_1416_1712, + &pci_ss_info_1412_1712_153b_1115, + &pci_ss_info_1412_1712_153b_1125, + &pci_ss_info_1412_1712_153b_112b, + &pci_ss_info_1412_1712_153b_112c, + &pci_ss_info_1412_1712_153b_1130, + &pci_ss_info_1412_1712_153b_1138, + &pci_ss_info_1412_1712_153b_1151, + &pci_ss_info_1412_1712_16ce_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1412_1724[] = { + &pci_ss_info_1412_1724_1412_1724, + &pci_ss_info_1412_1724_1412_3630, + &pci_ss_info_1412_1724_1412_3631, + &pci_ss_info_1412_1724_153b_1145, + &pci_ss_info_1412_1724_153b_1147, + &pci_ss_info_1412_1724_153b_1153, + &pci_ss_info_1412_1724_270f_f641, + &pci_ss_info_1412_1724_270f_f645, + NULL +}; +#endif +#define pci_ss_list_1415_8403 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_131f_2050, + &pci_ss_info_1415_9501_131f_2051, + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +#define pci_ss_list_1415_9510 NULL +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9521 NULL +#define pci_ss_list_1415_9523 NULL +#endif +#define pci_ss_list_1420_8002 NULL +#define pci_ss_list_1420_8003 NULL +#define pci_ss_list_1425_000b NULL +#define pci_ss_list_142e_4020 NULL +#define pci_ss_list_142e_4337 NULL +#define pci_ss_list_1432_9130 NULL +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8164 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_1458_0c11 NULL +#define pci_ss_list_1458_e911 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_1461_a3ce NULL +#define pci_ss_list_1461_a3cf NULL +#define pci_ss_list_1462_5501 NULL +#define pci_ss_list_1462_6819 NULL +#define pci_ss_list_1462_6825 NULL +#define pci_ss_list_1462_8725 NULL +#define pci_ss_list_1462_9000 NULL +#define pci_ss_list_1462_9110 NULL +#define pci_ss_list_1462_9119 NULL +#define pci_ss_list_1462_9591 NULL +#define pci_ss_list_146c_1430 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_1497_1497 NULL +#define pci_ss_list_1498_21cd NULL +#define pci_ss_list_1498_30c8 NULL +#define pci_ss_list_149d_0001 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14b9_a505 NULL +#define pci_ss_list_14b9_a506 NULL +#define pci_ss_list_14c1_8043 NULL +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14d9_0010 NULL +#define pci_ss_list_14d9_9000 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#define pci_ss_list_14e4_0800 NULL +#define pci_ss_list_14e4_0804 NULL +#define pci_ss_list_14e4_0805 NULL +#define pci_ss_list_14e4_0806 NULL +#define pci_ss_list_14e4_080b NULL +#define pci_ss_list_14e4_080f NULL +#define pci_ss_list_14e4_0811 NULL +#define pci_ss_list_14e4_0816 NULL +#define pci_ss_list_14e4_1600 NULL +#define pci_ss_list_14e4_1601 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_103c_128a, + &pci_ss_info_14e4_1645_103c_128b, + &pci_ss_info_14e4_1645_103c_12a4, + &pci_ss_info_14e4_1645_103c_12c1, + &pci_ss_info_14e4_1645_103c_1300, + &pci_ss_info_14e4_1645_10a9_8010, + &pci_ss_info_14e4_1645_10a9_8011, + &pci_ss_info_14e4_1645_10a9_8012, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_10a9_8010, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + &pci_ss_info_14e4_1648_1734_100b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164a[] = { + &pci_ss_info_14e4_164a_103c_3101, + NULL +}; +#define pci_ss_list_14e4_164c NULL +#define pci_ss_list_14e4_164d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1653[] = { + &pci_ss_info_14e4_1653_0e11_00e3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1654[] = { + &pci_ss_info_14e4_1654_0e11_00e3, + &pci_ss_info_14e4_1654_103c_3100, + &pci_ss_info_14e4_1654_103c_3226, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1659[] = { + &pci_ss_info_14e4_1659_103c_7031, + &pci_ss_info_14e4_1659_103c_7032, + &pci_ss_info_14e4_1659_1734_1061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165d[] = { + &pci_ss_info_14e4_165d_1028_865d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165e[] = { + &pci_ss_info_14e4_165e_103c_088c, + &pci_ss_info_14e4_165e_103c_0890, + &pci_ss_info_14e4_165e_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1668[] = { + &pci_ss_info_14e4_1668_103c_7039, + NULL +}; +#define pci_ss_list_14e4_166a NULL +#define pci_ss_list_14e4_166b NULL +#define pci_ss_list_14e4_166e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1677[] = { + &pci_ss_info_14e4_1677_1028_0179, + &pci_ss_info_14e4_1677_1028_0182, + &pci_ss_info_14e4_1677_1028_01ad, + &pci_ss_info_14e4_1677_1734_105d, + NULL +}; +#define pci_ss_list_14e4_1678 NULL +#define pci_ss_list_14e4_167d NULL +#define pci_ss_list_14e4_167e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_103c_12bc, + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_169c[] = { + &pci_ss_info_14e4_169c_103c_308b, + NULL +}; +#define pci_ss_list_14e4_169d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16aa[] = { + &pci_ss_info_14e4_16aa_103c_3102, + NULL +}; +#define pci_ss_list_14e4_16ac NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_0e11_00ca, + &pci_ss_info_14e4_16c7_0e11_00cb, + &pci_ss_info_14e4_16c7_103c_12c3, + &pci_ss_info_14e4_16c7_103c_12ca, + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_16dd NULL +#define pci_ss_list_14e4_16f7 NULL +#define pci_ss_list_14e4_16fd NULL +#define pci_ss_list_14e4_16fe NULL +static const pciSubsystemInfo *pci_ss_list_14e4_170c[] = { + &pci_ss_info_14e4_170c_1028_0188, + &pci_ss_info_14e4_170c_1028_0196, + &pci_ss_info_14e4_170c_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_170d[] = { + &pci_ss_info_14e4_170d_1014_0545, + NULL +}; +#define pci_ss_list_14e4_170e NULL +#define pci_ss_list_14e4_3352 NULL +#define pci_ss_list_14e4_3360 NULL +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4301[] = { + &pci_ss_info_14e4_4301_1028_0407, + &pci_ss_info_14e4_4301_1043_0120, + NULL +}; +#define pci_ss_list_14e4_4305 NULL +#define pci_ss_list_14e4_4306 NULL +#define pci_ss_list_14e4_4307 NULL +#define pci_ss_list_14e4_4310 NULL +#define pci_ss_list_14e4_4312 NULL +#define pci_ss_list_14e4_4313 NULL +#define pci_ss_list_14e4_4315 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4318[] = { + &pci_ss_info_14e4_4318_103c_1356, + &pci_ss_info_14e4_4318_1468_0311, + &pci_ss_info_14e4_4318_14e4_0449, + &pci_ss_info_14e4_4318_14e4_4318, + &pci_ss_info_14e4_4318_16ec_0119, + NULL +}; +#define pci_ss_list_14e4_4319 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4320[] = { + &pci_ss_info_14e4_4320_1028_0001, + &pci_ss_info_14e4_4320_1028_0003, + &pci_ss_info_14e4_4320_103c_12fa, + &pci_ss_info_14e4_4320_1043_100f, + &pci_ss_info_14e4_4320_1057_7025, + &pci_ss_info_14e4_4320_106b_004e, + &pci_ss_info_14e4_4320_14e4_4320, + &pci_ss_info_14e4_4320_1737_4320, + &pci_ss_info_14e4_4320_1799_7001, + &pci_ss_info_14e4_4320_1799_7010, + &pci_ss_info_14e4_4320_185f_1220, + NULL +}; +#define pci_ss_list_14e4_4321 NULL +#define pci_ss_list_14e4_4322 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4324[] = { + &pci_ss_info_14e4_4324_1028_0001, + &pci_ss_info_14e4_4324_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_4325[] = { + &pci_ss_info_14e4_4325_1414_0003, + &pci_ss_info_14e4_4325_1414_0004, + NULL +}; +#define pci_ss_list_14e4_4326 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4401[] = { + &pci_ss_info_14e4_4401_1043_80a8, + NULL +}; +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4403 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_4430 NULL +#define pci_ss_list_14e4_4432 NULL +#define pci_ss_list_14e4_4610 NULL +#define pci_ss_list_14e4_4611 NULL +#define pci_ss_list_14e4_4612 NULL +#define pci_ss_list_14e4_4613 NULL +#define pci_ss_list_14e4_4614 NULL +#define pci_ss_list_14e4_4615 NULL +#define pci_ss_list_14e4_4704 NULL +#define pci_ss_list_14e4_4705 NULL +#define pci_ss_list_14e4_4706 NULL +#define pci_ss_list_14e4_4707 NULL +#define pci_ss_list_14e4_4708 NULL +#define pci_ss_list_14e4_4710 NULL +#define pci_ss_list_14e4_4711 NULL +#define pci_ss_list_14e4_4712 NULL +#define pci_ss_list_14e4_4713 NULL +#define pci_ss_list_14e4_4714 NULL +#define pci_ss_list_14e4_4715 NULL +#define pci_ss_list_14e4_4716 NULL +#define pci_ss_list_14e4_4717 NULL +#define pci_ss_list_14e4_4718 NULL +#define pci_ss_list_14e4_4720 NULL +#define pci_ss_list_14e4_5365 NULL +#define pci_ss_list_14e4_5600 NULL +#define pci_ss_list_14e4_5605 NULL +#define pci_ss_list_14e4_5615 NULL +#define pci_ss_list_14e4_5625 NULL +#define pci_ss_list_14e4_5645 NULL +#define pci_ss_list_14e4_5670 NULL +#define pci_ss_list_14e4_5680 NULL +#define pci_ss_list_14e4_5690 NULL +#define pci_ss_list_14e4_5691 NULL +#define pci_ss_list_14e4_5692 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#define pci_ss_list_14e4_5822 NULL +#define pci_ss_list_14e4_5823 NULL +#define pci_ss_list_14e4_5824 NULL +#define pci_ss_list_14e4_5840 NULL +#define pci_ss_list_14e4_5841 NULL +#define pci_ss_list_14e4_5850 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14ea_ab07 NULL +#define pci_ss_list_14ea_ab08 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1085 NULL +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +#define pci_ss_list_14f1_1620 NULL +#define pci_ss_list_14f1_1621 NULL +#define pci_ss_list_14f1_1622 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +#define pci_ss_list_14f1_1811 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2045[] = { + &pci_ss_info_14f1_2045_14f1_2045, + NULL +}; +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_2f02 NULL +#define pci_ss_list_14f1_2f11 NULL +#define pci_ss_list_14f1_2f20 NULL +#define pci_ss_list_14f1_8234 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_8800[] = { + &pci_ss_info_14f1_8800_0070_2801, + &pci_ss_info_14f1_8800_0070_3401, + &pci_ss_info_14f1_8800_0070_9002, + &pci_ss_info_14f1_8800_1002_00f8, + &pci_ss_info_14f1_8800_1043_4823, + &pci_ss_info_14f1_8800_107d_6613, + &pci_ss_info_14f1_8800_107d_6620, + &pci_ss_info_14f1_8800_107d_663c, + &pci_ss_info_14f1_8800_10fc_d003, + &pci_ss_info_14f1_8800_10fc_d035, + &pci_ss_info_14f1_8800_1461_000b, + &pci_ss_info_14f1_8800_1462_8606, + &pci_ss_info_14f1_8800_14c7_0107, + &pci_ss_info_14f1_8800_14f1_0187, + &pci_ss_info_14f1_8800_14f1_0342, + &pci_ss_info_14f1_8800_1540_2580, + &pci_ss_info_14f1_8800_1554_4811, + &pci_ss_info_14f1_8800_17de_08a1, + &pci_ss_info_14f1_8800_17de_08a6, + &pci_ss_info_14f1_8800_17de_a8a6, + &pci_ss_info_14f1_8800_18ac_d500, + &pci_ss_info_14f1_8800_18ac_d810, + &pci_ss_info_14f1_8800_18ac_d820, + &pci_ss_info_14f1_8800_18ac_db00, + &pci_ss_info_14f1_8800_18ac_db10, + &pci_ss_info_14f1_8800_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8801[] = { + &pci_ss_info_14f1_8801_0070_2801, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8802[] = { + &pci_ss_info_14f1_8802_0070_2801, + &pci_ss_info_14f1_8802_0070_9002, + &pci_ss_info_14f1_8802_1043_4823, + &pci_ss_info_14f1_8802_107d_663c, + &pci_ss_info_14f1_8802_14f1_0187, + &pci_ss_info_14f1_8802_17de_08a1, + &pci_ss_info_14f1_8802_17de_08a6, + &pci_ss_info_14f1_8802_18ac_d500, + &pci_ss_info_14f1_8802_18ac_d810, + &pci_ss_info_14f1_8802_18ac_d820, + &pci_ss_info_14f1_8802_18ac_db00, + &pci_ss_info_14f1_8802_18ac_db10, + &pci_ss_info_14f1_8802_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8804[] = { + &pci_ss_info_14f1_8804_0070_9002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8811[] = { + &pci_ss_info_14f1_8811_0070_3401, + &pci_ss_info_14f1_8811_1462_8606, + &pci_ss_info_14f1_8811_18ac_d500, + &pci_ss_info_14f1_8811_18ac_d810, + &pci_ss_info_14f1_8811_18ac_d820, + &pci_ss_info_14f1_8811_18ac_db00, + NULL +}; +#endif +#define pci_ss_list_14f2_0120 NULL +#define pci_ss_list_14f2_0121 NULL +#define pci_ss_list_14f2_0122 NULL +#define pci_ss_list_14f2_0123 NULL +#define pci_ss_list_14f2_0124 NULL +#define pci_ss_list_14f3_2030 NULL +#define pci_ss_list_14f3_2050 NULL +#define pci_ss_list_14f3_2060 NULL +#define pci_ss_list_14f8_2077 NULL +#define pci_ss_list_14fc_0000 NULL +#define pci_ss_list_14fc_0001 NULL +#define pci_ss_list_1500_1360 NULL +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#define pci_ss_list_1516_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#define pci_ss_list_1516_0891 NULL +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151c_0003 NULL +#define pci_ss_list_151c_4000 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + &pci_ss_info_1522_0100_1522_0c00, + &pci_ss_info_1522_0100_1522_0d00, + &pci_ss_info_1522_0100_1522_1d00, + &pci_ss_info_1522_0100_1522_2000, + &pci_ss_info_1522_0100_1522_2100, + &pci_ss_info_1522_0100_1522_2200, + &pci_ss_info_1522_0100_1522_2300, + &pci_ss_info_1522_0100_1522_2400, + &pci_ss_info_1522_0100_1522_2500, + &pci_ss_info_1522_0100_1522_2600, + &pci_ss_info_1522_0100_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1524_0510 NULL +#define pci_ss_list_1524_0520 NULL +#define pci_ss_list_1524_0530 NULL +#define pci_ss_list_1524_0550 NULL +#define pci_ss_list_1524_0610 NULL +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1524_1410[] = { + &pci_ss_info_1524_1410_1025_005a, + NULL +}; +#define pci_ss_list_1524_1411 NULL +#define pci_ss_list_1524_1412 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1524_1421 NULL +#define pci_ss_list_1524_1422 NULL +#endif +#define pci_ss_list_1538_0303 NULL +#define pci_ss_list_153b_1144 NULL +#define pci_ss_list_153b_1147 NULL +#define pci_ss_list_153b_1158 NULL +#define pci_ss_list_153f_0001 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_1578_5615 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0405 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15ad_0720 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15b3_5a44 NULL +#define pci_ss_list_15b3_5a45 NULL +#define pci_ss_list_15b3_5a46 NULL +#define pci_ss_list_15b3_5e8d NULL +#define pci_ss_list_15b3_6274 NULL +#define pci_ss_list_15b3_6278 NULL +#define pci_ss_list_15b3_6279 NULL +#define pci_ss_list_15b3_6282 NULL +#define pci_ss_list_15bc_1100 NULL +#define pci_ss_list_15bc_2922 NULL +#define pci_ss_list_15bc_2928 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c5_8010 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_15e9_1841 NULL +#define pci_ss_list_15ec_3101 NULL +#define pci_ss_list_15ec_5102 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1619_0610 NULL +#define pci_ss_list_1619_0620 NULL +#define pci_ss_list_1619_0640 NULL +#define pci_ss_list_1619_1610 NULL +#define pci_ss_list_1619_2610 NULL +#define pci_ss_list_1626_8410 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1637_3874 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_3052 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_165f_1020 NULL +#define pci_ss_list_1668_0100 NULL +#define pci_ss_list_166d_0001 NULL +#define pci_ss_list_166d_0002 NULL +#define pci_ss_list_1677_104e NULL +#define pci_ss_list_1677_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_167b_2102[] = { + &pci_ss_info_167b_2102_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1681_0010 NULL +#define pci_ss_list_1688_1170 NULL +#define pci_ss_list_168c_0007 NULL +#define pci_ss_list_168c_0011 NULL +#define pci_ss_list_168c_0012 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c_0013[] = { + &pci_ss_info_168c_0013_1113_d301, + &pci_ss_info_168c_0013_1186_3202, + &pci_ss_info_168c_0013_1186_3203, + &pci_ss_info_168c_0013_1186_3a12, + &pci_ss_info_168c_0013_1186_3a13, + &pci_ss_info_168c_0013_1186_3a14, + &pci_ss_info_168c_0013_1186_3a17, + &pci_ss_info_168c_0013_1186_3a18, + &pci_ss_info_168c_0013_1186_3a63, + &pci_ss_info_168c_0013_1186_3a94, + &pci_ss_info_168c_0013_1385_4d00, + &pci_ss_info_168c_0013_1458_e911, + &pci_ss_info_168c_0013_14b7_0a60, + &pci_ss_info_168c_0013_168c_0013, + &pci_ss_info_168c_0013_168c_1025, + &pci_ss_info_168c_0013_168c_1027, + &pci_ss_info_168c_0013_168c_2026, + &pci_ss_info_168c_0013_168c_2041, + &pci_ss_info_168c_0013_168c_2042, + &pci_ss_info_168c_0013_16ab_7302, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001a[] = { + &pci_ss_info_168c_001a_1186_3a15, + &pci_ss_info_168c_001a_1186_3a16, + &pci_ss_info_168c_001a_1186_3a23, + &pci_ss_info_168c_001a_1186_3a24, + &pci_ss_info_168c_001a_168c_1052, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001b[] = { + &pci_ss_info_168c_001b_1186_3a19, + &pci_ss_info_168c_001b_1186_3a22, + NULL +}; +#define pci_ss_list_168c_0020 NULL +#define pci_ss_list_168c_1014 NULL +#endif +#define pci_ss_list_169c_0044 NULL +#define pci_ss_list_16ab_1100 NULL +#define pci_ss_list_16ab_1101 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ab_8501 NULL +#define pci_ss_list_16ae_1141 NULL +#define pci_ss_list_16ca_0001 NULL +#define pci_ss_list_16e3_1e0f NULL +#define pci_ss_list_16ec_00ff NULL +#define pci_ss_list_16ec_0116 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_16ed_1001 NULL +#define pci_ss_list_16f4_8000 NULL +#define pci_ss_list_170b_0100 NULL +#define pci_ss_list_1725_7174 NULL +#define pci_ss_list_172a_13c8 NULL +#define pci_ss_list_1737_0013 NULL +#define pci_ss_list_1737_0015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737_1032[] = { + &pci_ss_info_1737_1032_1737_0015, + &pci_ss_info_1737_1032_1737_0024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1737_1064[] = { + &pci_ss_info_1737_1064_1737_0016, + NULL +}; +#define pci_ss_list_1737_ab08 NULL +#define pci_ss_list_1737_ab09 NULL +#endif +#define pci_ss_list_173b_03e8 NULL +#define pci_ss_list_173b_03e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#define pci_ss_list_173b_03eb NULL +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_1799_6001 NULL +#define pci_ss_list_1799_6020 NULL +#define pci_ss_list_1799_6060 NULL +#define pci_ss_list_1799_7000 NULL +#define pci_ss_list_1799_7010 NULL +#define pci_ss_list_179c_0557 NULL +#define pci_ss_list_179c_0566 NULL +#define pci_ss_list_179c_5031 NULL +#define pci_ss_list_179c_5121 NULL +#define pci_ss_list_179c_5211 NULL +#define pci_ss_list_179c_5679 NULL +#define pci_ss_list_17a0_8033 NULL +#define pci_ss_list_17a0_8034 NULL +#define pci_ss_list_17b3_ab08 NULL +#define pci_ss_list_17b4_0011 NULL +#define pci_ss_list_17cc_2280 NULL +#define pci_ss_list_17d3_1110 NULL +#define pci_ss_list_17d3_1120 NULL +#define pci_ss_list_17d3_1130 NULL +#define pci_ss_list_17d3_1160 NULL +#define pci_ss_list_17d3_1210 NULL +#define pci_ss_list_17d3_1220 NULL +#define pci_ss_list_17d3_1230 NULL +#define pci_ss_list_17d3_1260 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17d3_5831[] = { + &pci_ss_info_17d3_5831_103c_12d5, + NULL +}; +#define pci_ss_list_17d3_5832 NULL +#endif +#define pci_ss_list_17fe_2120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe_2220[] = { + &pci_ss_info_17fe_2220_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1814_0101[] = { + &pci_ss_info_1814_0101_1043_0127, + &pci_ss_info_1814_0101_1462_6828, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0201[] = { + &pci_ss_info_1814_0201_1043_130f, + &pci_ss_info_1814_0201_1371_001e, + &pci_ss_info_1814_0201_1371_001f, + &pci_ss_info_1814_0201_1371_0020, + &pci_ss_info_1814_0201_1458_e381, + &pci_ss_info_1814_0201_1458_e931, + &pci_ss_info_1814_0201_1462_6835, + &pci_ss_info_1814_0201_1737_0032, + &pci_ss_info_1814_0201_1799_700a, + &pci_ss_info_1814_0201_1799_701a, + &pci_ss_info_1814_0201_185f_22a0, + NULL +}; +#define pci_ss_list_1814_0401 NULL +#endif +#define pci_ss_list_1822_4e35 NULL +#define pci_ss_list_182d_3069 NULL +#define pci_ss_list_182d_9790 NULL +#define pci_ss_list_183b_08a7 NULL +#define pci_ss_list_183b_08a8 NULL +#define pci_ss_list_183b_08a9 NULL +#define pci_ss_list_1864_2110 NULL +#define pci_ss_list_1867_5a44 NULL +#define pci_ss_list_1867_5a45 NULL +#define pci_ss_list_1867_5a46 NULL +#define pci_ss_list_1867_6278 NULL +#define pci_ss_list_1867_6282 NULL +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_18ac_d500 NULL +#define pci_ss_list_18ac_d810 NULL +#define pci_ss_list_18ac_d820 NULL +#define pci_ss_list_18b8_b001 NULL +#define pci_ss_list_18ca_0020 NULL +#define pci_ss_list_18ca_0040 NULL +#define pci_ss_list_18d2_3069 NULL +#define pci_ss_list_18dd_4c6f NULL +#define pci_ss_list_18e6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec_c006[] = { + &pci_ss_info_18ec_c006_18ec_d001, + &pci_ss_info_18ec_c006_18ec_d002, + &pci_ss_info_18ec_c006_18ec_d003, + &pci_ss_info_18ec_c006_18ec_d004, + NULL +}; +#define pci_ss_list_18ec_c045 NULL +#define pci_ss_list_18ec_c050 NULL +static const pciSubsystemInfo *pci_ss_list_18ec_c058[] = { + &pci_ss_info_18ec_c058_18ec_d001, + &pci_ss_info_18ec_c058_18ec_d002, + &pci_ss_info_18ec_c058_18ec_d003, + &pci_ss_info_18ec_c058_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7_0001 NULL +#define pci_ss_list_18f7_0002 NULL +#define pci_ss_list_18f7_0004 NULL +#define pci_ss_list_18f7_0005 NULL +#define pci_ss_list_18f7_000a NULL +#define pci_ss_list_1957_0080 NULL +#define pci_ss_list_1957_0081 NULL +#define pci_ss_list_1957_0082 NULL +#define pci_ss_list_1957_0083 NULL +#define pci_ss_list_1957_0084 NULL +#define pci_ss_list_1957_0085 NULL +#define pci_ss_list_1957_0086 NULL +#define pci_ss_list_1957_0087 NULL +#define pci_ss_list_1966_1975 NULL +#define pci_ss_list_196a_0101 NULL +#define pci_ss_list_196a_0102 NULL +#define pci_ss_list_197b_2360 NULL +#define pci_ss_list_197b_2363 NULL +#define pci_ss_list_1989_0001 NULL +#define pci_ss_list_1989_8001 NULL +#define pci_ss_list_19ae_0520 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_1fc0_0300 NULL +#define pci_ss_list_1fc1_000d NULL +#define pci_ss_list_1fce_0001 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_0021[] = { + &pci_ss_info_3388_0021_4c53_1050, + &pci_ss_info_3388_0021_4c53_1080, + &pci_ss_info_3388_0021_4c53_1090, + &pci_ss_info_3388_0021_4c53_10a0, + &pci_ss_info_3388_0021_4c53_3010, + &pci_ss_info_3388_0021_4c53_3011, + &pci_ss_info_3388_0021_4c53_4000, + NULL +}; +#define pci_ss_list_3388_0022 NULL +#define pci_ss_list_3388_0026 NULL +#define pci_ss_list_3388_101a NULL +#define pci_ss_list_3388_101b NULL +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3842_c370 NULL +#define pci_ss_list_3d3d_0001 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0002[] = { + &pci_ss_info_3d3d_0002_0000_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0003[] = { + &pci_ss_info_3d3d_0003_0000_0000, + NULL +}; +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0006[] = { + &pci_ss_info_3d3d_0006_0000_0000, + &pci_ss_info_3d3d_0006_1048_0a42, + NULL +}; +#define pci_ss_list_3d3d_0007 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0008[] = { + &pci_ss_info_3d3d_0008_1048_0a42, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_1048_0a42, + &pci_ss_info_3d3d_0009_13e9_1000, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_000d NULL +#define pci_ss_list_3d3d_0011 NULL +#define pci_ss_list_3d3d_0012 NULL +#define pci_ss_list_3d3d_0013 NULL +#define pci_ss_list_3d3d_0020 NULL +#define pci_ss_list_3d3d_0022 NULL +#define pci_ss_list_3d3d_0024 NULL +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_07a1 NULL +#define pci_ss_list_3d3d_07a2 NULL +#define pci_ss_list_3d3d_07a3 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_4144_0044 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4444_0016[] = { + &pci_ss_info_4444_0016_0070_4009, + &pci_ss_info_4444_0016_0070_8003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4444_0803[] = { + &pci_ss_info_4444_0803_0070_4000, + &pci_ss_info_4444_0803_0070_4001, + &pci_ss_info_4444_0803_1461_a3cf, + NULL +}; +#endif +#define pci_ss_list_4916_1960 NULL +#define pci_ss_list_494f_10e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53_0000[] = { + &pci_ss_info_4c53_0000_4c53_3000, + &pci_ss_info_4c53_0000_4c53_3001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4c53_0001[] = { + &pci_ss_info_4c53_0001_4c53_3002, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5168_0301 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_1033_8110, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + &pci_ss_info_5333_8c12_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_544c_0350 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_5654_3132 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_6666_0004 NULL +#define pci_ss_list_6666_0101 NULL +#define pci_ss_list_7063_2000 NULL +#define pci_ss_list_7063_3000 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0309 NULL +#define pci_ss_list_8086_030d NULL +#define pci_ss_list_8086_0326 NULL +#define pci_ss_list_8086_0327 NULL +#define pci_ss_list_8086_0329 NULL +#define pci_ss_list_8086_032a NULL +#define pci_ss_list_8086_032c NULL +#define pci_ss_list_8086_0330 NULL +#define pci_ss_list_8086_0331 NULL +#define pci_ss_list_8086_0332 NULL +#define pci_ss_list_8086_0333 NULL +#define pci_ss_list_8086_0334 NULL +#define pci_ss_list_8086_0335 NULL +#define pci_ss_list_8086_0336 NULL +#define pci_ss_list_8086_0340 NULL +#define pci_ss_list_8086_0341 NULL +#define pci_ss_list_8086_0370 NULL +#define pci_ss_list_8086_0371 NULL +#define pci_ss_list_8086_0372 NULL +#define pci_ss_list_8086_0373 NULL +#define pci_ss_list_8086_0374 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0500 NULL +#define pci_ss_list_8086_0501 NULL +#define pci_ss_list_8086_0502 NULL +#define pci_ss_list_8086_0503 NULL +#define pci_ss_list_8086_0510 NULL +#define pci_ss_list_8086_0511 NULL +#define pci_ss_list_8086_0512 NULL +#define pci_ss_list_8086_0513 NULL +#define pci_ss_list_8086_0514 NULL +#define pci_ss_list_8086_0515 NULL +#define pci_ss_list_8086_0516 NULL +#define pci_ss_list_8086_0530 NULL +#define pci_ss_list_8086_0531 NULL +#define pci_ss_list_8086_0532 NULL +#define pci_ss_list_8086_0533 NULL +#define pci_ss_list_8086_0534 NULL +#define pci_ss_list_8086_0535 NULL +#define pci_ss_list_8086_0536 NULL +#define pci_ss_list_8086_0537 NULL +static const pciSubsystemInfo *pci_ss_list_8086_0600[] = { + &pci_ss_info_8086_0600_8086_01af, + &pci_ss_info_8086_0600_8086_01c1, + &pci_ss_info_8086_0600_8086_01f7, + NULL +}; +#define pci_ss_list_8086_061f NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1002, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_1014_0269, + &pci_ss_info_8086_1008_1028_011c, + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + &pci_ss_info_8086_1008_8086_3108, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_1014_0268, + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +#define pci_ss_list_8086_100a NULL +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100d[] = { + &pci_ss_info_8086_100d_1028_0123, + &pci_ss_info_8086_100d_1079_891f, + &pci_ss_info_8086_100d_4c53_1080, + &pci_ss_info_8086_100d_8086_110d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_1014_0265, + &pci_ss_info_8086_100e_1014_0267, + &pci_ss_info_8086_100e_1014_026a, + &pci_ss_info_8086_100e_1024_0134, + &pci_ss_info_8086_100e_1028_002e, + &pci_ss_info_8086_100e_1028_0151, + &pci_ss_info_8086_100e_107b_8920, + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + &pci_ss_info_8086_100e_8086_1376, + &pci_ss_info_8086_100e_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_1014_0269, + &pci_ss_info_8086_100f_1014_028e, + &pci_ss_info_8086_100f_8086_1000, + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_0e11_00db, + &pci_ss_info_8086_1010_1014_027c, + &pci_ss_info_8086_1010_18fb_7872, + &pci_ss_info_8086_1010_1fc1_0026, + &pci_ss_info_8086_1010_4c53_1080, + &pci_ss_info_8086_1010_4c53_10a0, + &pci_ss_info_8086_1010_8086_1011, + &pci_ss_info_8086_1010_8086_1012, + &pci_ss_info_8086_1010_8086_101a, + &pci_ss_info_8086_1010_8086_3424, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_1014_0268, + &pci_ss_info_8086_1011_8086_1002, + &pci_ss_info_8086_1011_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_0e11_00dc, + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1013[] = { + &pci_ss_info_8086_1013_8086_0013, + &pci_ss_info_8086_1013_8086_1013, + &pci_ss_info_8086_1013_8086_1113, + NULL +}; +#define pci_ss_list_8086_1014 NULL +#define pci_ss_list_8086_1015 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1016[] = { + &pci_ss_info_8086_1016_1014_052c, + &pci_ss_info_8086_1016_1179_0001, + &pci_ss_info_8086_1016_8086_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1017[] = { + &pci_ss_info_8086_1017_8086_1017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1018[] = { + &pci_ss_info_8086_1018_8086_1018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1019[] = { + &pci_ss_info_8086_1019_1458_1019, + &pci_ss_info_8086_1019_1458_e000, + &pci_ss_info_8086_1019_8086_1019, + &pci_ss_info_8086_1019_8086_301f, + &pci_ss_info_8086_1019_8086_3427, + NULL +}; +#define pci_ss_list_8086_101a NULL +static const pciSubsystemInfo *pci_ss_list_8086_101d[] = { + &pci_ss_info_8086_101d_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101e[] = { + &pci_ss_info_8086_101e_1014_0549, + &pci_ss_info_8086_101e_1179_0001, + &pci_ss_info_8086_101e_8086_101e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1026[] = { + &pci_ss_info_8086_1026_1028_0169, + &pci_ss_info_8086_1026_8086_1000, + &pci_ss_info_8086_1026_8086_1001, + &pci_ss_info_8086_1026_8086_1002, + &pci_ss_info_8086_1026_8086_1026, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1027[] = { + &pci_ss_info_8086_1027_103c_3103, + &pci_ss_info_8086_1027_8086_1001, + &pci_ss_info_8086_1027_8086_1002, + &pci_ss_info_8086_1027_8086_1003, + &pci_ss_info_8086_1027_8086_1027, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1028[] = { + &pci_ss_info_8086_1028_8086_1028, + NULL +}; +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + &pci_ss_info_8086_1031_813c_104d, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1038[] = { + &pci_ss_info_8086_1038_0e11_0098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1039[] = { + &pci_ss_info_8086_1039_1014_0267, + NULL +}; +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +#define pci_ss_list_8086_103d NULL +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1043[] = { + &pci_ss_info_8086_1043_8086_2527, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1048[] = { + &pci_ss_info_8086_1048_8086_a01f, + &pci_ss_info_8086_1048_8086_a11f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1050[] = { + &pci_ss_info_8086_1050_1462_728c, + &pci_ss_info_8086_1050_1462_758c, + &pci_ss_info_8086_1050_8086_3020, + &pci_ss_info_8086_1050_8086_302f, + &pci_ss_info_8086_1050_8086_3427, + NULL +}; +#define pci_ss_list_8086_1051 NULL +#define pci_ss_list_8086_1052 NULL +#define pci_ss_list_8086_1053 NULL +#define pci_ss_list_8086_1059 NULL +#define pci_ss_list_8086_105e NULL +#define pci_ss_list_8086_105f NULL +#define pci_ss_list_8086_1060 NULL +#define pci_ss_list_8086_1064 NULL +#define pci_ss_list_8086_1065 NULL +#define pci_ss_list_8086_1066 NULL +#define pci_ss_list_8086_1067 NULL +#define pci_ss_list_8086_1068 NULL +#define pci_ss_list_8086_1069 NULL +#define pci_ss_list_8086_106a NULL +#define pci_ss_list_8086_106b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1075[] = { + &pci_ss_info_8086_1075_1028_0165, + &pci_ss_info_8086_1075_8086_0075, + &pci_ss_info_8086_1075_8086_1075, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1076[] = { + &pci_ss_info_8086_1076_1028_0165, + &pci_ss_info_8086_1076_1028_019a, + &pci_ss_info_8086_1076_8086_0076, + &pci_ss_info_8086_1076_8086_1076, + &pci_ss_info_8086_1076_8086_1176, + &pci_ss_info_8086_1076_8086_1276, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1077[] = { + &pci_ss_info_8086_1077_1179_0001, + &pci_ss_info_8086_1077_8086_0077, + &pci_ss_info_8086_1077_8086_1077, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1078[] = { + &pci_ss_info_8086_1078_8086_1078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1079[] = { + &pci_ss_info_8086_1079_103c_12a6, + &pci_ss_info_8086_1079_103c_12cf, + &pci_ss_info_8086_1079_1fc1_0027, + &pci_ss_info_8086_1079_4c53_1090, + &pci_ss_info_8086_1079_4c53_10b0, + &pci_ss_info_8086_1079_8086_0079, + &pci_ss_info_8086_1079_8086_1079, + &pci_ss_info_8086_1079_8086_1179, + &pci_ss_info_8086_1079_8086_117a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107a[] = { + &pci_ss_info_8086_107a_103c_12a8, + &pci_ss_info_8086_107a_8086_107a, + &pci_ss_info_8086_107a_8086_127a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107b[] = { + &pci_ss_info_8086_107b_8086_007b, + &pci_ss_info_8086_107b_8086_107b, + NULL +}; +#define pci_ss_list_8086_107c NULL +#define pci_ss_list_8086_107d NULL +#define pci_ss_list_8086_107e NULL +#define pci_ss_list_8086_107f NULL +#define pci_ss_list_8086_1080 NULL +#define pci_ss_list_8086_1081 NULL +#define pci_ss_list_8086_1082 NULL +#define pci_ss_list_8086_1083 NULL +#define pci_ss_list_8086_1084 NULL +#define pci_ss_list_8086_1085 NULL +#define pci_ss_list_8086_1086 NULL +#define pci_ss_list_8086_1087 NULL +#define pci_ss_list_8086_1089 NULL +#define pci_ss_list_8086_108a NULL +#define pci_ss_list_8086_108b NULL +#define pci_ss_list_8086_108c NULL +#define pci_ss_list_8086_1096 NULL +#define pci_ss_list_8086_1097 NULL +#define pci_ss_list_8086_1098 NULL +#define pci_ss_list_8086_1099 NULL +#define pci_ss_list_8086_109a NULL +#define pci_ss_list_8086_1107 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + &pci_ss_info_8086_1130_8086_4532, + &pci_ss_info_8086_1130_8086_4557, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + &pci_ss_info_8086_1132_8086_4532, + &pci_ss_info_8086_1132_8086_4541, + &pci_ss_info_8086_1132_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1209[] = { + &pci_ss_info_8086_1209_4c53_1050, + &pci_ss_info_8086_1209_4c53_1051, + &pci_ss_info_8086_1209_4c53_1070, + NULL +}; +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1028_00ce, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_108e_10cf, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_110a_008b, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_13e9_1000, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_4c53_1080, + &pci_ss_info_8086_1229_4c53_10e0, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + &pci_ss_info_8086_1229_8086_3411, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123e NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + &pci_ss_info_8086_1461_4c53_1090, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + &pci_ss_info_8086_1960_e4bf_1010, + &pci_ss_info_8086_1960_e4bf_1020, + &pci_ss_info_8086_1960_e4bf_1040, + &pci_ss_info_8086_1960_e4bf_3100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1a30[] = { + &pci_ss_info_8086_1a30_1028_010e, + NULL +}; +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_1a38 NULL +#define pci_ss_list_8086_1a48 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_110a_0051, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + &pci_ss_info_8086_2415_1734_1025, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_1028_010e, + &pci_ss_info_8086_2442_1043_8027, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + &pci_ss_info_8086_2442_8086_4532, + &pci_ss_info_8086_2442_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1028_010e, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + &pci_ss_info_8086_2443_8086_4532, + &pci_ss_info_8086_2443_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_1028_010e, + &pci_ss_info_8086_2444_1043_8027, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + &pci_ss_info_8086_2444_8086_4532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + &pci_ss_info_8086_2445_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2448[] = { + &pci_ss_info_8086_2448_103c_099c, + &pci_ss_info_8086_2448_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_1014_0265, + &pci_ss_info_8086_2449_1014_0267, + &pci_ss_info_8086_2449_1014_026a, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1179_ff01, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1028_010e, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + &pci_ss_info_8086_244b_8086_4532, + &pci_ss_info_8086_244b_8086_4557, + NULL +}; +#define pci_ss_list_8086_244c NULL +static const pciSubsystemInfo *pci_ss_list_8086_244e[] = { + &pci_ss_info_8086_244e_1014_0267, + NULL +}; +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_0e11_0030, + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + &pci_ss_info_8086_2482_8086_3424, + &pci_ss_info_8086_2482_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_0e11_0030, + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1013_5959, + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_101f_1025, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_1179_0001, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_0e11_0030, + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_0e11_0030, + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + &pci_ss_info_8086_248a_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1014_0267, + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1014_0267, + &pci_ss_info_8086_24c2_1025_005a, + &pci_ss_info_8086_24c2_1028_0126, + &pci_ss_info_8086_24c2_1028_0163, + &pci_ss_info_8086_24c2_1028_0196, + &pci_ss_info_8086_24c2_103c_088c, + &pci_ss_info_8086_24c2_103c_0890, + &pci_ss_info_8086_24c2_1071_8160, + &pci_ss_info_8086_24c2_1462_5800, + &pci_ss_info_8086_24c2_1509_2990, + &pci_ss_info_8086_24c2_1734_1055, + &pci_ss_info_8086_24c2_4c53_1090, + &pci_ss_info_8086_24c2_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1014_0267, + &pci_ss_info_8086_24c3_1025_005a, + &pci_ss_info_8086_24c3_1028_0126, + &pci_ss_info_8086_24c3_103c_088c, + &pci_ss_info_8086_24c3_103c_0890, + &pci_ss_info_8086_24c3_1071_8160, + &pci_ss_info_8086_24c3_1458_24c2, + &pci_ss_info_8086_24c3_1462_5800, + &pci_ss_info_8086_24c3_1734_1055, + &pci_ss_info_8086_24c3_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1014_0267, + &pci_ss_info_8086_24c4_1025_005a, + &pci_ss_info_8086_24c4_1028_0126, + &pci_ss_info_8086_24c4_1028_0163, + &pci_ss_info_8086_24c4_1028_0196, + &pci_ss_info_8086_24c4_103c_088c, + &pci_ss_info_8086_24c4_103c_0890, + &pci_ss_info_8086_24c4_1071_8160, + &pci_ss_info_8086_24c4_1462_5800, + &pci_ss_info_8086_24c4_1509_2990, + &pci_ss_info_8086_24c4_4c53_1090, + &pci_ss_info_8086_24c4_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_0e11_00b8, + &pci_ss_info_8086_24c5_1014_0267, + &pci_ss_info_8086_24c5_1025_005a, + &pci_ss_info_8086_24c5_1028_0139, + &pci_ss_info_8086_24c5_1028_0163, + &pci_ss_info_8086_24c5_1028_0196, + &pci_ss_info_8086_24c5_103c_088c, + &pci_ss_info_8086_24c5_103c_0890, + &pci_ss_info_8086_24c5_1071_8160, + &pci_ss_info_8086_24c5_1458_a002, + &pci_ss_info_8086_24c5_1462_5800, + &pci_ss_info_8086_24c5_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c6[] = { + &pci_ss_info_8086_24c6_1025_005a, + &pci_ss_info_8086_24c6_1028_0196, + &pci_ss_info_8086_24c6_103c_088c, + &pci_ss_info_8086_24c6_103c_0890, + &pci_ss_info_8086_24c6_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1014_0267, + &pci_ss_info_8086_24c7_1025_005a, + &pci_ss_info_8086_24c7_1028_0126, + &pci_ss_info_8086_24c7_1028_0163, + &pci_ss_info_8086_24c7_1028_0196, + &pci_ss_info_8086_24c7_103c_088c, + &pci_ss_info_8086_24c7_103c_0890, + &pci_ss_info_8086_24c7_1071_8160, + &pci_ss_info_8086_24c7_1462_5800, + &pci_ss_info_8086_24c7_1509_2990, + &pci_ss_info_8086_24c7_4c53_1090, + &pci_ss_info_8086_24c7_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24ca[] = { + &pci_ss_info_8086_24ca_1025_005a, + &pci_ss_info_8086_24ca_1028_0163, + &pci_ss_info_8086_24ca_1028_0196, + &pci_ss_info_8086_24ca_103c_088c, + &pci_ss_info_8086_24ca_103c_0890, + &pci_ss_info_8086_24ca_1071_8160, + &pci_ss_info_8086_24ca_1734_1055, + &pci_ss_info_8086_24ca_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1014_0267, + &pci_ss_info_8086_24cb_1028_0126, + &pci_ss_info_8086_24cb_1458_24c2, + &pci_ss_info_8086_24cb_1462_5800, + &pci_ss_info_8086_24cb_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cc[] = { + &pci_ss_info_8086_24cc_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1014_0267, + &pci_ss_info_8086_24cd_1025_005a, + &pci_ss_info_8086_24cd_1028_0126, + &pci_ss_info_8086_24cd_1028_0139, + &pci_ss_info_8086_24cd_1028_0163, + &pci_ss_info_8086_24cd_1028_0196, + &pci_ss_info_8086_24cd_103c_088c, + &pci_ss_info_8086_24cd_103c_0890, + &pci_ss_info_8086_24cd_1071_8160, + &pci_ss_info_8086_24cd_1462_3981, + &pci_ss_info_8086_24cd_1509_1968, + &pci_ss_info_8086_24cd_1734_1055, + &pci_ss_info_8086_24cd_4c53_1090, + NULL +}; +#define pci_ss_list_8086_24d0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d1[] = { + &pci_ss_info_8086_24d1_1028_0169, + &pci_ss_info_8086_24d1_1028_019a, + &pci_ss_info_8086_24d1_103c_12bc, + &pci_ss_info_8086_24d1_1043_80a6, + &pci_ss_info_8086_24d1_1458_24d1, + &pci_ss_info_8086_24d1_1462_7280, + &pci_ss_info_8086_24d1_15d9_4580, + &pci_ss_info_8086_24d1_8086_3427, + &pci_ss_info_8086_24d1_8086_4246, + &pci_ss_info_8086_24d1_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d2[] = { + &pci_ss_info_8086_24d2_1028_0169, + &pci_ss_info_8086_24d2_1028_0183, + &pci_ss_info_8086_24d2_1028_019a, + &pci_ss_info_8086_24d2_103c_12bc, + &pci_ss_info_8086_24d2_1043_80a6, + &pci_ss_info_8086_24d2_1458_24d2, + &pci_ss_info_8086_24d2_1462_7280, + &pci_ss_info_8086_24d2_15d9_4580, + &pci_ss_info_8086_24d2_1734_101c, + &pci_ss_info_8086_24d2_8086_3427, + &pci_ss_info_8086_24d2_8086_4246, + &pci_ss_info_8086_24d2_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d3[] = { + &pci_ss_info_8086_24d3_1028_0169, + &pci_ss_info_8086_24d3_1043_80a6, + &pci_ss_info_8086_24d3_1458_24d2, + &pci_ss_info_8086_24d3_1462_7280, + &pci_ss_info_8086_24d3_15d9_4580, + &pci_ss_info_8086_24d3_1734_101c, + &pci_ss_info_8086_24d3_8086_3427, + &pci_ss_info_8086_24d3_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d4[] = { + &pci_ss_info_8086_24d4_1028_0169, + &pci_ss_info_8086_24d4_1028_0183, + &pci_ss_info_8086_24d4_1028_019a, + &pci_ss_info_8086_24d4_103c_12bc, + &pci_ss_info_8086_24d4_1043_80a6, + &pci_ss_info_8086_24d4_1458_24d2, + &pci_ss_info_8086_24d4_1462_7280, + &pci_ss_info_8086_24d4_15d9_4580, + &pci_ss_info_8086_24d4_1734_101c, + &pci_ss_info_8086_24d4_8086_3427, + &pci_ss_info_8086_24d4_8086_4246, + &pci_ss_info_8086_24d4_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d5[] = { + &pci_ss_info_8086_24d5_1028_0169, + &pci_ss_info_8086_24d5_103c_12bc, + &pci_ss_info_8086_24d5_1043_80f3, + &pci_ss_info_8086_24d5_1043_810f, + &pci_ss_info_8086_24d5_1458_a002, + &pci_ss_info_8086_24d5_1462_7280, + &pci_ss_info_8086_24d5_8086_a000, + &pci_ss_info_8086_24d5_8086_e000, + &pci_ss_info_8086_24d5_8086_e001, + NULL +}; +#define pci_ss_list_8086_24d6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d7[] = { + &pci_ss_info_8086_24d7_1028_0169, + &pci_ss_info_8086_24d7_1028_0183, + &pci_ss_info_8086_24d7_103c_12bc, + &pci_ss_info_8086_24d7_1043_80a6, + &pci_ss_info_8086_24d7_1458_24d2, + &pci_ss_info_8086_24d7_1462_7280, + &pci_ss_info_8086_24d7_15d9_4580, + &pci_ss_info_8086_24d7_1734_101c, + &pci_ss_info_8086_24d7_8086_3427, + &pci_ss_info_8086_24d7_8086_4246, + &pci_ss_info_8086_24d7_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24db[] = { + &pci_ss_info_8086_24db_1028_0169, + &pci_ss_info_8086_24db_1028_019a, + &pci_ss_info_8086_24db_103c_12bc, + &pci_ss_info_8086_24db_1043_80a6, + &pci_ss_info_8086_24db_1458_24d2, + &pci_ss_info_8086_24db_1462_7280, + &pci_ss_info_8086_24db_1462_7580, + &pci_ss_info_8086_24db_15d9_4580, + &pci_ss_info_8086_24db_1734_101c, + &pci_ss_info_8086_24db_8086_24db, + &pci_ss_info_8086_24db_8086_3427, + &pci_ss_info_8086_24db_8086_4246, + &pci_ss_info_8086_24db_8086_524c, + NULL +}; +#define pci_ss_list_8086_24dc NULL +static const pciSubsystemInfo *pci_ss_list_8086_24dd[] = { + &pci_ss_info_8086_24dd_1028_0169, + &pci_ss_info_8086_24dd_1028_0183, + &pci_ss_info_8086_24dd_1028_019a, + &pci_ss_info_8086_24dd_103c_12bc, + &pci_ss_info_8086_24dd_1043_80a6, + &pci_ss_info_8086_24dd_1458_5006, + &pci_ss_info_8086_24dd_1462_7280, + &pci_ss_info_8086_24dd_8086_3427, + &pci_ss_info_8086_24dd_8086_4246, + &pci_ss_info_8086_24dd_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24de[] = { + &pci_ss_info_8086_24de_1028_0169, + &pci_ss_info_8086_24de_1043_80a6, + &pci_ss_info_8086_24de_1458_24d2, + &pci_ss_info_8086_24de_1462_7280, + &pci_ss_info_8086_24de_15d9_4580, + &pci_ss_info_8086_24de_1734_101c, + &pci_ss_info_8086_24de_8086_3427, + &pci_ss_info_8086_24de_8086_4246, + &pci_ss_info_8086_24de_8086_524c, + NULL +}; +#define pci_ss_list_8086_24df NULL +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + &pci_ss_info_8086_2541_4c53_1090, + &pci_ss_info_8086_2541_8086_3424, + NULL +}; +#define pci_ss_list_8086_2543 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2544[] = { + &pci_ss_info_8086_2544_4c53_1090, + NULL +}; +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_254c[] = { + &pci_ss_info_8086_254c_4c53_1090, + &pci_ss_info_8086_254c_8086_3424, + NULL +}; +#define pci_ss_list_8086_2550 NULL +#define pci_ss_list_8086_2551 NULL +#define pci_ss_list_8086_2552 NULL +#define pci_ss_list_8086_2553 NULL +#define pci_ss_list_8086_2554 NULL +#define pci_ss_list_8086_255d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1028_0126, + &pci_ss_info_8086_2560_1458_2560, + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2562[] = { + &pci_ss_info_8086_2562_1014_0267, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2570[] = { + &pci_ss_info_8086_2570_1043_80f2, + &pci_ss_info_8086_2570_1458_2570, + NULL +}; +#define pci_ss_list_8086_2571 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2572[] = { + &pci_ss_info_8086_2572_1028_019d, + &pci_ss_info_8086_2572_1043_80a5, + NULL +}; +#define pci_ss_list_8086_2573 NULL +#define pci_ss_list_8086_2576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2578[] = { + &pci_ss_info_8086_2578_1458_2578, + &pci_ss_info_8086_2578_1462_7580, + &pci_ss_info_8086_2578_15d9_4580, + NULL +}; +#define pci_ss_list_8086_2579 NULL +#define pci_ss_list_8086_257b NULL +#define pci_ss_list_8086_257e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2580[] = { + &pci_ss_info_8086_2580_1458_2580, + &pci_ss_info_8086_2580_1462_7028, + &pci_ss_info_8086_2580_1734_105b, + NULL +}; +#define pci_ss_list_8086_2581 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2582[] = { + &pci_ss_info_8086_2582_1028_1079, + &pci_ss_info_8086_2582_1458_2582, + &pci_ss_info_8086_2582_1734_105b, + NULL +}; +#define pci_ss_list_8086_2584 NULL +#define pci_ss_list_8086_2585 NULL +#define pci_ss_list_8086_2588 NULL +#define pci_ss_list_8086_2589 NULL +#define pci_ss_list_8086_258a NULL +static const pciSubsystemInfo *pci_ss_list_8086_2590[] = { + &pci_ss_info_8086_2590_103c_099c, + &pci_ss_info_8086_2590_a304_81b7, + NULL +}; +#define pci_ss_list_8086_2591 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2592[] = { + &pci_ss_info_8086_2592_103c_099c, + &pci_ss_info_8086_2592_1043_1881, + NULL +}; +#define pci_ss_list_8086_25a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a2[] = { + &pci_ss_info_8086_25a2_4c53_10b0, + &pci_ss_info_8086_25a2_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a3[] = { + &pci_ss_info_8086_25a3_4c53_10b0, + &pci_ss_info_8086_25a3_4c53_10d0, + &pci_ss_info_8086_25a3_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a4[] = { + &pci_ss_info_8086_25a4_4c53_10b0, + &pci_ss_info_8086_25a4_4c53_10d0, + &pci_ss_info_8086_25a4_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a6[] = { + &pci_ss_info_8086_25a6_4c53_10b0, + NULL +}; +#define pci_ss_list_8086_25a7 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a9[] = { + &pci_ss_info_8086_25a9_4c53_10b0, + &pci_ss_info_8086_25a9_4c53_10d0, + &pci_ss_info_8086_25a9_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25aa[] = { + &pci_ss_info_8086_25aa_4c53_10b0, + &pci_ss_info_8086_25aa_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ab[] = { + &pci_ss_info_8086_25ab_4c53_10b0, + &pci_ss_info_8086_25ab_4c53_10d0, + &pci_ss_info_8086_25ab_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ac[] = { + &pci_ss_info_8086_25ac_4c53_10b0, + &pci_ss_info_8086_25ac_4c53_10d0, + &pci_ss_info_8086_25ac_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ad[] = { + &pci_ss_info_8086_25ad_4c53_10b0, + &pci_ss_info_8086_25ad_4c53_10d0, + &pci_ss_info_8086_25ad_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25ae NULL +static const pciSubsystemInfo *pci_ss_list_8086_25b0[] = { + &pci_ss_info_8086_25b0_4c53_10d0, + &pci_ss_info_8086_25b0_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25c0 NULL +#define pci_ss_list_8086_25d0 NULL +#define pci_ss_list_8086_25d4 NULL +#define pci_ss_list_8086_25d8 NULL +#define pci_ss_list_8086_25e2 NULL +#define pci_ss_list_8086_25e3 NULL +#define pci_ss_list_8086_25e4 NULL +#define pci_ss_list_8086_25e5 NULL +#define pci_ss_list_8086_25e6 NULL +#define pci_ss_list_8086_25e7 NULL +#define pci_ss_list_8086_25e8 NULL +#define pci_ss_list_8086_25f0 NULL +#define pci_ss_list_8086_25f1 NULL +#define pci_ss_list_8086_25f3 NULL +#define pci_ss_list_8086_25f5 NULL +#define pci_ss_list_8086_25f6 NULL +#define pci_ss_list_8086_25f7 NULL +#define pci_ss_list_8086_25f8 NULL +#define pci_ss_list_8086_25f9 NULL +#define pci_ss_list_8086_25fa NULL +#define pci_ss_list_8086_2600 NULL +#define pci_ss_list_8086_2601 NULL +#define pci_ss_list_8086_2602 NULL +#define pci_ss_list_8086_2603 NULL +#define pci_ss_list_8086_2604 NULL +#define pci_ss_list_8086_2605 NULL +#define pci_ss_list_8086_2606 NULL +#define pci_ss_list_8086_2607 NULL +#define pci_ss_list_8086_2608 NULL +#define pci_ss_list_8086_2609 NULL +#define pci_ss_list_8086_260a NULL +#define pci_ss_list_8086_260c NULL +#define pci_ss_list_8086_2610 NULL +#define pci_ss_list_8086_2611 NULL +#define pci_ss_list_8086_2612 NULL +#define pci_ss_list_8086_2613 NULL +#define pci_ss_list_8086_2614 NULL +#define pci_ss_list_8086_2615 NULL +#define pci_ss_list_8086_2617 NULL +#define pci_ss_list_8086_2618 NULL +#define pci_ss_list_8086_2619 NULL +#define pci_ss_list_8086_261a NULL +#define pci_ss_list_8086_261b NULL +#define pci_ss_list_8086_261c NULL +#define pci_ss_list_8086_261d NULL +#define pci_ss_list_8086_261e NULL +#define pci_ss_list_8086_2620 NULL +#define pci_ss_list_8086_2621 NULL +#define pci_ss_list_8086_2622 NULL +#define pci_ss_list_8086_2623 NULL +#define pci_ss_list_8086_2624 NULL +#define pci_ss_list_8086_2625 NULL +#define pci_ss_list_8086_2626 NULL +#define pci_ss_list_8086_2627 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2640[] = { + &pci_ss_info_8086_2640_1462_7028, + &pci_ss_info_8086_2640_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2641[] = { + &pci_ss_info_8086_2641_103c_099c, + NULL +}; +#define pci_ss_list_8086_2642 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2651[] = { + &pci_ss_info_8086_2651_1028_0179, + &pci_ss_info_8086_2651_1734_105c, + &pci_ss_info_8086_2651_8086_4147, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2652[] = { + &pci_ss_info_8086_2652_1462_7028, + NULL +}; +#define pci_ss_list_8086_2653 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2658[] = { + &pci_ss_info_8086_2658_1028_0179, + &pci_ss_info_8086_2658_103c_099c, + &pci_ss_info_8086_2658_1458_2558, + &pci_ss_info_8086_2658_1462_7028, + &pci_ss_info_8086_2658_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2659[] = { + &pci_ss_info_8086_2659_1028_0179, + &pci_ss_info_8086_2659_103c_099c, + &pci_ss_info_8086_2659_1458_2659, + &pci_ss_info_8086_2659_1462_7028, + &pci_ss_info_8086_2659_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265a[] = { + &pci_ss_info_8086_265a_1028_0179, + &pci_ss_info_8086_265a_103c_099c, + &pci_ss_info_8086_265a_1458_265a, + &pci_ss_info_8086_265a_1462_7028, + &pci_ss_info_8086_265a_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265b[] = { + &pci_ss_info_8086_265b_1028_0179, + &pci_ss_info_8086_265b_103c_099c, + &pci_ss_info_8086_265b_1458_265a, + &pci_ss_info_8086_265b_1462_7028, + &pci_ss_info_8086_265b_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265c[] = { + &pci_ss_info_8086_265c_1028_0179, + &pci_ss_info_8086_265c_103c_099c, + &pci_ss_info_8086_265c_1458_5006, + &pci_ss_info_8086_265c_1462_7028, + &pci_ss_info_8086_265c_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2660[] = { + &pci_ss_info_8086_2660_103c_099c, + NULL +}; +#define pci_ss_list_8086_2662 NULL +#define pci_ss_list_8086_2664 NULL +#define pci_ss_list_8086_2666 NULL +#define pci_ss_list_8086_2668 NULL +static const pciSubsystemInfo *pci_ss_list_8086_266a[] = { + &pci_ss_info_8086_266a_1028_0179, + &pci_ss_info_8086_266a_1458_266a, + &pci_ss_info_8086_266a_1462_7028, + &pci_ss_info_8086_266a_1734_105c, + NULL +}; +#define pci_ss_list_8086_266c NULL +static const pciSubsystemInfo *pci_ss_list_8086_266d[] = { + &pci_ss_info_8086_266d_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266e[] = { + &pci_ss_info_8086_266e_1028_0179, + &pci_ss_info_8086_266e_1028_0182, + &pci_ss_info_8086_266e_1028_0188, + &pci_ss_info_8086_266e_103c_099c, + &pci_ss_info_8086_266e_1458_a002, + &pci_ss_info_8086_266e_1734_105a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266f[] = { + &pci_ss_info_8086_266f_103c_099c, + &pci_ss_info_8086_266f_1458_266f, + &pci_ss_info_8086_266f_1462_7028, + &pci_ss_info_8086_266f_1734_105c, + NULL +}; +#define pci_ss_list_8086_2670 NULL +#define pci_ss_list_8086_2680 NULL +#define pci_ss_list_8086_2681 NULL +#define pci_ss_list_8086_2682 NULL +#define pci_ss_list_8086_2683 NULL +#define pci_ss_list_8086_2688 NULL +#define pci_ss_list_8086_2689 NULL +#define pci_ss_list_8086_268a NULL +#define pci_ss_list_8086_268b NULL +#define pci_ss_list_8086_268c NULL +#define pci_ss_list_8086_2690 NULL +#define pci_ss_list_8086_2692 NULL +#define pci_ss_list_8086_2694 NULL +#define pci_ss_list_8086_2696 NULL +#define pci_ss_list_8086_2698 NULL +#define pci_ss_list_8086_2699 NULL +#define pci_ss_list_8086_269a NULL +#define pci_ss_list_8086_269b NULL +#define pci_ss_list_8086_269e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2770[] = { + &pci_ss_info_8086_2770_8086_544e, + NULL +}; +#define pci_ss_list_8086_2771 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2772[] = { + &pci_ss_info_8086_2772_8086_544e, + NULL +}; +#define pci_ss_list_8086_2774 NULL +#define pci_ss_list_8086_2775 NULL +#define pci_ss_list_8086_2776 NULL +#define pci_ss_list_8086_2778 NULL +#define pci_ss_list_8086_2779 NULL +#define pci_ss_list_8086_277a NULL +#define pci_ss_list_8086_277c NULL +#define pci_ss_list_8086_277d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2782[] = { + &pci_ss_info_8086_2782_1734_105b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2792[] = { + &pci_ss_info_8086_2792_103c_099c, + &pci_ss_info_8086_2792_1043_1881, + NULL +}; +#define pci_ss_list_8086_27a0 NULL +#define pci_ss_list_8086_27a1 NULL +#define pci_ss_list_8086_27a2 NULL +#define pci_ss_list_8086_27a6 NULL +#define pci_ss_list_8086_27b0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27b8[] = { + &pci_ss_info_8086_27b8_8086_544e, + NULL +}; +#define pci_ss_list_8086_27b9 NULL +#define pci_ss_list_8086_27bd NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c0[] = { + &pci_ss_info_8086_27c0_8086_544e, + NULL +}; +#define pci_ss_list_8086_27c1 NULL +#define pci_ss_list_8086_27c3 NULL +#define pci_ss_list_8086_27c4 NULL +#define pci_ss_list_8086_27c5 NULL +#define pci_ss_list_8086_27c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c8[] = { + &pci_ss_info_8086_27c8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27c9[] = { + &pci_ss_info_8086_27c9_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27ca[] = { + &pci_ss_info_8086_27ca_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cb[] = { + &pci_ss_info_8086_27cb_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cc[] = { + &pci_ss_info_8086_27cc_8086_544e, + NULL +}; +#define pci_ss_list_8086_27d0 NULL +#define pci_ss_list_8086_27d2 NULL +#define pci_ss_list_8086_27d4 NULL +#define pci_ss_list_8086_27d6 NULL +#define pci_ss_list_8086_27d8 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27da[] = { + &pci_ss_info_8086_27da_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27dc[] = { + &pci_ss_info_8086_27dc_8086_308d, + NULL +}; +#define pci_ss_list_8086_27dd NULL +#define pci_ss_list_8086_27de NULL +static const pciSubsystemInfo *pci_ss_list_8086_27df[] = { + &pci_ss_info_8086_27df_8086_544e, + NULL +}; +#define pci_ss_list_8086_27e0 NULL +#define pci_ss_list_8086_27e2 NULL +#define pci_ss_list_8086_3092 NULL +#define pci_ss_list_8086_3200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3340[] = { + &pci_ss_info_8086_3340_1025_005a, + &pci_ss_info_8086_3340_103c_088c, + &pci_ss_info_8086_3340_103c_0890, + NULL +}; +#define pci_ss_list_8086_3341 NULL +#define pci_ss_list_8086_3500 NULL +#define pci_ss_list_8086_3501 NULL +#define pci_ss_list_8086_3504 NULL +#define pci_ss_list_8086_3505 NULL +#define pci_ss_list_8086_350c NULL +#define pci_ss_list_8086_350d NULL +#define pci_ss_list_8086_3510 NULL +#define pci_ss_list_8086_3511 NULL +#define pci_ss_list_8086_3514 NULL +#define pci_ss_list_8086_3515 NULL +#define pci_ss_list_8086_3518 NULL +#define pci_ss_list_8086_3519 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_0e11_0030, + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3580[] = { + &pci_ss_info_8086_3580_1028_0139, + &pci_ss_info_8086_3580_1028_0163, + &pci_ss_info_8086_3580_1028_0196, + &pci_ss_info_8086_3580_1734_1055, + &pci_ss_info_8086_3580_4c53_10b0, + &pci_ss_info_8086_3580_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3581[] = { + &pci_ss_info_8086_3581_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3582[] = { + &pci_ss_info_8086_3582_1028_0139, + &pci_ss_info_8086_3582_1028_0163, + &pci_ss_info_8086_3582_4c53_10b0, + &pci_ss_info_8086_3582_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3584[] = { + &pci_ss_info_8086_3584_1028_0139, + &pci_ss_info_8086_3584_1028_0163, + &pci_ss_info_8086_3584_1028_0196, + &pci_ss_info_8086_3584_1734_1055, + &pci_ss_info_8086_3584_4c53_10b0, + &pci_ss_info_8086_3584_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3585[] = { + &pci_ss_info_8086_3585_1028_0139, + &pci_ss_info_8086_3585_1028_0163, + &pci_ss_info_8086_3585_1028_0196, + &pci_ss_info_8086_3585_1734_1055, + &pci_ss_info_8086_3585_4c53_10b0, + &pci_ss_info_8086_3585_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3590[] = { + &pci_ss_info_8086_3590_1028_019a, + &pci_ss_info_8086_3590_1734_103e, + &pci_ss_info_8086_3590_4c53_10d0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3591[] = { + &pci_ss_info_8086_3591_1028_0169, + &pci_ss_info_8086_3591_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3592 NULL +#define pci_ss_list_8086_3593 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3594[] = { + &pci_ss_info_8086_3594_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3595 NULL +#define pci_ss_list_8086_3596 NULL +#define pci_ss_list_8086_3597 NULL +#define pci_ss_list_8086_3598 NULL +#define pci_ss_list_8086_3599 NULL +#define pci_ss_list_8086_359a NULL +#define pci_ss_list_8086_359b NULL +static const pciSubsystemInfo *pci_ss_list_8086_359e[] = { + &pci_ss_info_8086_359e_1028_0169, + NULL +}; +#define pci_ss_list_8086_4220 NULL +#define pci_ss_list_8086_4223 NULL +#define pci_ss_list_8086_4224 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7050 NULL +#define pci_ss_list_8086_7051 NULL +#define pci_ss_list_8086_7100 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7110[] = { + &pci_ss_info_8086_7110_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7111[] = { + &pci_ss_info_8086_7111_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7112[] = { + &pci_ss_info_8086_7112_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7113[] = { + &pci_ss_info_8086_7113_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7120[] = { + &pci_ss_info_8086_7120_4c53_1040, + &pci_ss_info_8086_7120_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7121[] = { + &pci_ss_info_8086_7121_4c53_1040, + &pci_ss_info_8086_7121_4c53_1060, + &pci_ss_info_8086_7121_8086_4341, + NULL +}; +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1179_0001, + &pci_ss_info_8086_7190_15ad_1976, + &pci_ss_info_8086_7190_4c53_1050, + &pci_ss_info_8086_7190_4c53_1051, + NULL +}; +#define pci_ss_list_8086_7191 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + &pci_ss_info_8086_7192_4c53_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7194[] = { + &pci_ss_info_8086_7194_1033_0000, + &pci_ss_info_8086_7194_4c53_10a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_1033_80cc, + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a0[] = { + &pci_ss_info_8086_71a0_4c53_1050, + &pci_ss_info_8086_71a0_4c53_1051, + NULL +}; +#define pci_ss_list_8086_71a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a2[] = { + &pci_ss_info_8086_71a2_4c53_1000, + NULL +}; +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +static const pciSubsystemInfo *pci_ss_list_8086_8500[] = { + &pci_ss_info_8086_8500_1993_0ded, + &pci_ss_info_8086_8500_1993_0dee, + &pci_ss_info_8086_8500_1993_0def, + NULL +}; +#define pci_ss_list_8086_9000 NULL +#define pci_ss_list_8086_9001 NULL +#define pci_ss_list_8086_9004 NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_12d9_000a, + &pci_ss_info_8086_b555_4c53_1050, + &pci_ss_info_8086_b555_4c53_1051, + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8c4a_1980 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_0078 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7710 NULL +#define pci_ss_list_9004_7711 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8178[] = { + &pci_ss_info_9004_8178_9004_7881, + NULL +}; +#define pci_ss_list_9004_8278 NULL +#define pci_ss_list_9004_8378 NULL +#define pci_ss_list_9004_8478 NULL +#define pci_ss_list_9004_8578 NULL +#define pci_ss_list_9004_8678 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8778[] = { + &pci_ss_info_9004_8778_9004_7887, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8878[] = { + &pci_ss_info_9004_8878_9004_7888, + NULL +}; +#define pci_ss_list_9004_8b78 NULL +#define pci_ss_list_9004_ec78 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005_0010[] = { + &pci_ss_info_9005_0010_9005_2180, + &pci_ss_info_9005_0010_9005_8100, + &pci_ss_info_9005_0010_9005_a100, + &pci_ss_info_9005_0010_9005_a180, + &pci_ss_info_9005_0010_9005_e100, + NULL +}; +#define pci_ss_list_9005_0011 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0013[] = { + &pci_ss_info_9005_0013_9005_0003, + &pci_ss_info_9005_0013_9005_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_001f[] = { + &pci_ss_info_9005_001f_9005_000f, + &pci_ss_info_9005_001f_9005_a180, + NULL +}; +#define pci_ss_list_9005_0020 NULL +#define pci_ss_list_9005_002f NULL +#define pci_ss_list_9005_0030 NULL +#define pci_ss_list_9005_003f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0050[] = { + &pci_ss_info_9005_0050_9005_f500, + &pci_ss_info_9005_0050_9005_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0051[] = { + &pci_ss_info_9005_0051_9005_b500, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0053[] = { + &pci_ss_info_9005_0053_9005_ffff, + NULL +}; +#define pci_ss_list_9005_005f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0080[] = { + &pci_ss_info_9005_0080_0e11_e2a0, + &pci_ss_info_9005_0080_9005_6220, + &pci_ss_info_9005_0080_9005_62a0, + &pci_ss_info_9005_0080_9005_e220, + &pci_ss_info_9005_0080_9005_e2a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0081[] = { + &pci_ss_info_9005_0081_9005_62a1, + NULL +}; +#define pci_ss_list_9005_0083 NULL +static const pciSubsystemInfo *pci_ss_list_9005_008f[] = { + &pci_ss_info_9005_008f_1179_0001, + &pci_ss_info_9005_008f_15d9_9005, + NULL +}; +#define pci_ss_list_9005_0092 NULL +#define pci_ss_list_9005_0093 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c0[] = { + &pci_ss_info_9005_00c0_0e11_f620, + &pci_ss_info_9005_00c0_9005_f620, + NULL +}; +#define pci_ss_list_9005_00c1 NULL +#define pci_ss_list_9005_00c3 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c5[] = { + &pci_ss_info_9005_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00cf[] = { + &pci_ss_info_9005_00cf_1028_00ce, + &pci_ss_info_9005_00cf_1028_00d1, + &pci_ss_info_9005_00cf_1028_00d9, + &pci_ss_info_9005_00cf_10f1_2462, + &pci_ss_info_9005_00cf_15d9_9005, + &pci_ss_info_9005_00cf_8086_3411, + NULL +}; +#define pci_ss_list_9005_0241 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0250[] = { + &pci_ss_info_9005_0250_1014_0279, + &pci_ss_info_9005_0250_1014_028c, + NULL +}; +#define pci_ss_list_9005_0279 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0283[] = { + &pci_ss_info_9005_0283_9005_0283, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0284[] = { + &pci_ss_info_9005_0284_9005_0284, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0285[] = { + &pci_ss_info_9005_0285_0e11_0295, + &pci_ss_info_9005_0285_1014_02f2, + &pci_ss_info_9005_0285_1028_0287, + &pci_ss_info_9005_0285_1028_0291, + &pci_ss_info_9005_0285_103c_3227, + &pci_ss_info_9005_0285_17aa_0286, + &pci_ss_info_9005_0285_17aa_0287, + &pci_ss_info_9005_0285_9005_0285, + &pci_ss_info_9005_0285_9005_0286, + &pci_ss_info_9005_0285_9005_0287, + &pci_ss_info_9005_0285_9005_0288, + &pci_ss_info_9005_0285_9005_0289, + &pci_ss_info_9005_0285_9005_028a, + &pci_ss_info_9005_0285_9005_028b, + &pci_ss_info_9005_0285_9005_028e, + &pci_ss_info_9005_0285_9005_028f, + &pci_ss_info_9005_0285_9005_0290, + &pci_ss_info_9005_0285_9005_0292, + &pci_ss_info_9005_0285_9005_0293, + &pci_ss_info_9005_0285_9005_0294, + &pci_ss_info_9005_0285_9005_0296, + &pci_ss_info_9005_0285_9005_0297, + &pci_ss_info_9005_0285_9005_0298, + &pci_ss_info_9005_0285_9005_0299, + &pci_ss_info_9005_0285_9005_029a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0286[] = { + &pci_ss_info_9005_0286_1014_9540, + &pci_ss_info_9005_0286_1014_9580, + &pci_ss_info_9005_0286_9005_028c, + &pci_ss_info_9005_0286_9005_028d, + &pci_ss_info_9005_0286_9005_029b, + &pci_ss_info_9005_0286_9005_029c, + &pci_ss_info_9005_0286_9005_029d, + &pci_ss_info_9005_0286_9005_029e, + &pci_ss_info_9005_0286_9005_029f, + &pci_ss_info_9005_0286_9005_02a0, + &pci_ss_info_9005_0286_9005_02a1, + &pci_ss_info_9005_0286_9005_02a2, + &pci_ss_info_9005_0286_9005_02a3, + &pci_ss_info_9005_0286_9005_02a4, + &pci_ss_info_9005_0286_9005_02a5, + &pci_ss_info_9005_0286_9005_02a6, + &pci_ss_info_9005_0286_9005_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0500[] = { + &pci_ss_info_9005_0500_1014_02c1, + &pci_ss_info_9005_0500_1014_02c2, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0503[] = { + &pci_ss_info_9005_0503_1014_02bf, + &pci_ss_info_9005_0503_1014_02d5, + NULL +}; +#define pci_ss_list_9005_0910 NULL +#define pci_ss_list_9005_091e NULL +#define pci_ss_list_9005_8000 NULL +#define pci_ss_list_9005_800f NULL +#define pci_ss_list_9005_8010 NULL +static const pciSubsystemInfo *pci_ss_list_9005_8011[] = { + &pci_ss_info_9005_8011_0e11_00ac, + &pci_ss_info_9005_8011_9005_0041, + NULL +}; +#define pci_ss_list_9005_8012 NULL +#define pci_ss_list_9005_8013 NULL +#define pci_ss_list_9005_8014 NULL +#define pci_ss_list_9005_8015 NULL +#define pci_ss_list_9005_8016 NULL +#define pci_ss_list_9005_8017 NULL +#define pci_ss_list_9005_801c NULL +#define pci_ss_list_9005_801d NULL +#define pci_ss_list_9005_801e NULL +static const pciSubsystemInfo *pci_ss_list_9005_801f[] = { + &pci_ss_info_9005_801f_1734_1011, + NULL +}; +#define pci_ss_list_9005_8080 NULL +#define pci_ss_list_9005_808f NULL +#define pci_ss_list_9005_8090 NULL +#define pci_ss_list_9005_8091 NULL +#define pci_ss_list_9005_8092 NULL +#define pci_ss_list_9005_8093 NULL +#define pci_ss_list_9005_8094 NULL +#define pci_ss_list_9005_8095 NULL +#define pci_ss_list_9005_8096 NULL +#define pci_ss_list_9005_8097 NULL +#define pci_ss_list_9005_809c NULL +#define pci_ss_list_9005_809d NULL +#define pci_ss_list_9005_809e NULL +#define pci_ss_list_9005_809f NULL +#endif +#define pci_ss_list_907f_2015 NULL +#define pci_ss_list_9412_6565 NULL +#define pci_ss_list_9699_6565 NULL +#define pci_ss_list_9710_7780 NULL +#define pci_ss_list_9710_9805 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9710_9815[] = { + &pci_ss_info_9710_9815_1000_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9835[] = { + &pci_ss_info_9710_9835_1000_0002, + &pci_ss_info_9710_9835_1000_0012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9845[] = { + &pci_ss_info_9710_9845_1000_0004, + &pci_ss_info_9710_9845_1000_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9855[] = { + &pci_ss_info_9710_9855_1000_0014, + NULL +}; +#endif +#define pci_ss_list_9902_0001 NULL +#define pci_ss_list_9902_0002 NULL +#define pci_ss_list_9902_0003 NULL +#define pci_ss_list_a727_0013 NULL +#define pci_ss_list_aecb_6250 NULL +#define pci_ss_list_affe_dead NULL +#define pci_ss_list_cafe_0003 NULL +#define pci_ss_list_cddd_0101 NULL +#define pci_ss_list_cddd_0200 NULL +#define pci_ss_list_d161_0205 NULL +#define pci_ss_list_d161_0210 NULL +#define pci_ss_list_d161_0405 NULL +#define pci_ss_list_d161_0410 NULL +#define pci_ss_list_d161_2400 NULL +#define pci_ss_list_d4d4_0601 NULL +#define pci_ss_list_deaf_9050 NULL +#define pci_ss_list_deaf_9051 NULL +#define pci_ss_list_deaf_9052 NULL +#define pci_ss_list_e000_e000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e159_0001[] = { + &pci_ss_info_e159_0001_0059_0001, + &pci_ss_info_e159_0001_0059_0003, + &pci_ss_info_e159_0001_00a7_0001, + &pci_ss_info_e159_0001_6159_0001, + &pci_ss_info_e159_0001_79fe_0001, + &pci_ss_info_e159_0001_8086_0003, + &pci_ss_info_e159_0001_b1b9_0001, + &pci_ss_info_e159_0001_b1b9_0003, + NULL +}; +#define pci_ss_list_e159_0002 NULL +#endif +#define pci_ss_list_ea01_000a NULL +#define pci_ss_list_ea01_0032 NULL +#define pci_ss_list_ea01_003e NULL +#define pci_ss_list_ea01_0041 NULL +#define pci_ss_list_ea01_0043 NULL +#define pci_ss_list_ea01_0046 NULL +#define pci_ss_list_ea01_0052 NULL +#define pci_ss_list_ea01_0800 NULL +#define pci_ss_list_ea60_9896 NULL +#define pci_ss_list_ea60_9897 NULL +#define pci_ss_list_ea60_9898 NULL +#define pci_ss_list_eace_3100 NULL +#define pci_ss_list_eace_3200 NULL +#define pci_ss_list_eace_320e NULL +#define pci_ss_list_eace_340e NULL +#define pci_ss_list_eace_341e NULL +#define pci_ss_list_eace_3500 NULL +#define pci_ss_list_eace_351c NULL +#define pci_ss_list_eace_4100 NULL +#define pci_ss_list_eace_4110 NULL +#define pci_ss_list_eace_4220 NULL +#define pci_ss_list_eace_422e NULL +#define pci_ss_list_ec80_ec00 NULL +#define pci_ss_list_edd8_a091 NULL +#define pci_ss_list_edd8_a099 NULL +#define pci_ss_list_edd8_a0a1 NULL +#define pci_ss_list_edd8_a0a9 NULL +#define pci_ss_list_f1d0_c0fe NULL +#define pci_ss_list_f1d0_c0ff NULL +#define pci_ss_list_f1d0_cafe NULL +#define pci_ss_list_f1d0_cfee NULL +#define pci_ss_list_f1d0_dcaf NULL +#define pci_ss_list_f1d0_dfee NULL +#define pci_ss_list_f1d0_efac NULL +#define pci_ss_list_f1d0_facd NULL +#define pci_ss_list_fa57_0001 NULL +#define pci_ss_list_feda_a0fa NULL +#define pci_ss_list_feda_a10e NULL +#define pci_ss_list_fede_0003 NULL +#define pci_ss_list_fffd_0101 NULL +#define pci_ss_list_fffe_0405 NULL +#define pci_ss_list_fffe_0710 NULL +#ifdef INIT_VENDOR_SUBSYS_INFO +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0000[] = { + &pci_ss_info_0000_0000, + NULL +}; +#endif +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0059[] = { + &pci_ss_info_0059_0001, + &pci_ss_info_0059_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_2801, + &pci_ss_info_0070_3401, + &pci_ss_info_0070_4000, + &pci_ss_info_0070_4001, + &pci_ss_info_0070_4009, + &pci_ss_info_0070_8003, + &pci_ss_info_0070_9002, + &pci_ss_info_0070_ff01, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0071[] = { + &pci_ss_info_0071_0101, + NULL +}; +#endif +#define pci_ss_list_0095 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_00a7[] = { + &pci_ss_info_00a7_0001, + NULL +}; +#endif +#define pci_ss_list_0100 NULL +#define pci_ss_list_018a NULL +#define pci_ss_list_021b NULL +#define pci_ss_list_0270 NULL +#define pci_ss_list_0291 NULL +#define pci_ss_list_02ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0357[] = { + &pci_ss_info_0357_000a, + NULL +}; +#endif +#define pci_ss_list_0432 NULL +#define pci_ss_list_045e NULL +#define pci_ss_list_04cf NULL +#define pci_ss_list_05e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0675[] = { + &pci_ss_info_0675_1704, + &pci_ss_info_0675_1707, + &pci_ss_info_0675_1708, + NULL +}; +#endif +#define pci_ss_list_067b NULL +#define pci_ss_list_0721 NULL +#define pci_ss_list_07e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +#define pci_ss_list_0b49 NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0030, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_004e, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0097, + &pci_ss_info_0e11_0098, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00ac, + &pci_ss_info_0e11_00b8, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_00da, + &pci_ss_info_0e11_00db, + &pci_ss_info_0e11_00dc, + &pci_ss_info_0e11_00e3, + &pci_ss_info_0e11_0295, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_4080, + &pci_ss_info_0e11_4082, + &pci_ss_info_0e11_4083, + &pci_ss_info_0e11_409a, + &pci_ss_info_0e11_409b, + &pci_ss_info_0e11_409c, + &pci_ss_info_0e11_409d, + &pci_ss_info_0e11_6004, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e7, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b121, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b160, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + &pci_ss_info_0e11_e2a0, + &pci_ss_info_0e11_f620, + NULL +}; +#define pci_ss_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_0001, + &pci_ss_info_1000_0002, + &pci_ss_info_1000_0004, + &pci_ss_info_1000_0006, + &pci_ss_info_1000_0012, + &pci_ss_info_1000_0014, + &pci_ss_info_1000_0020, + &pci_ss_info_1000_0033, + &pci_ss_info_1000_0066, + &pci_ss_info_1000_0518, + &pci_ss_info_1000_0520, + &pci_ss_info_1000_0522, + &pci_ss_info_1000_0523, + &pci_ss_info_1000_0530, + &pci_ss_info_1000_0531, + &pci_ss_info_1000_0532, + &pci_ss_info_1000_1000, + &pci_ss_info_1000_1010, + &pci_ss_info_1000_1020, + &pci_ss_info_1000_3004, + &pci_ss_info_1000_3008, + &pci_ss_info_1000_4523, + &pci_ss_info_1000_a520, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_00f8, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_0b12, + &pci_ss_info_1002_0b13, + &pci_ss_info_1002_103a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_2f72, + &pci_ss_info_1002_4336, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4772, + &pci_ss_info_1002_4773, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_4e71, + &pci_ss_info_1002_515e, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_5954, + &pci_ss_info_1002_5955, + &pci_ss_info_1002_5965, + &pci_ss_info_1002_5c63, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1005[] = { + &pci_ss_info_1005_127a, + NULL +}; +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + &pci_ss_info_1013_5959, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_0031, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0092, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0104, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0130, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020c, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021a, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0241, + &pci_ss_info_1014_0242, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0251, + &pci_ss_info_1014_0252, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0264, + &pci_ss_info_1014_0265, + &pci_ss_info_1014_0266, + &pci_ss_info_1014_0267, + &pci_ss_info_1014_0268, + &pci_ss_info_1014_0269, + &pci_ss_info_1014_026a, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0278, + &pci_ss_info_1014_0279, + &pci_ss_info_1014_027c, + &pci_ss_info_1014_028c, + &pci_ss_info_1014_028d, + &pci_ss_info_1014_028e, + &pci_ss_info_1014_02be, + &pci_ss_info_1014_02bf, + &pci_ss_info_1014_02c0, + &pci_ss_info_1014_02c1, + &pci_ss_info_1014_02c2, + &pci_ss_info_1014_02d3, + &pci_ss_info_1014_02d4, + &pci_ss_info_1014_02d5, + &pci_ss_info_1014_02f2, + &pci_ss_info_1014_030d, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_050f, + &pci_ss_info_1014_0510, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_0528, + &pci_ss_info_1014_052c, + &pci_ss_info_1014_0535, + &pci_ss_info_1014_053a, + &pci_ss_info_1014_053b, + &pci_ss_info_1014_053c, + &pci_ss_info_1014_053d, + &pci_ss_info_1014_053e, + &pci_ss_info_1014_0540, + &pci_ss_info_1014_0545, + &pci_ss_info_1014_0549, + &pci_ss_info_1014_0556, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_1025, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9540, + &pci_ss_info_1014_9580, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_0985, + &pci_ss_info_1019_0987, + &pci_ss_info_1019_0a14, + &pci_ss_info_1019_0a81, + &pci_ss_info_1019_0f38, + &pci_ss_info_1019_4c30, + &pci_ss_info_1019_4cb4, + &pci_ss_info_1019_4cb5, + &pci_ss_info_1019_7018, + &pci_ss_info_1019_8001, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0477, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0494, + &pci_ss_info_101e_0503, + &pci_ss_info_101e_0511, + &pci_ss_info_101e_0522, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101f[] = { + &pci_ss_info_101f_1025, + NULL +}; +#endif +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +static const pciSubsystemInfo *pci_ss_list_1022[] = { + &pci_ss_info_1022_2000, + &pci_ss_info_1022_2b80, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1024[] = { + &pci_ss_info_1024_0134, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_004d, + &pci_ss_info_1025_005a, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_002e, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00aa, + &pci_ss_info_1028_00b1, + &pci_ss_info_1028_00bb, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00ce, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_00fe, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_010e, + &pci_ss_info_1028_011c, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0123, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_012a, + &pci_ss_info_1028_0134, + &pci_ss_info_1028_0139, + &pci_ss_info_1028_014a, + &pci_ss_info_1028_014e, + &pci_ss_info_1028_0151, + &pci_ss_info_1028_0163, + &pci_ss_info_1028_0165, + &pci_ss_info_1028_0169, + &pci_ss_info_1028_016c, + &pci_ss_info_1028_016d, + &pci_ss_info_1028_016e, + &pci_ss_info_1028_016f, + &pci_ss_info_1028_0170, + &pci_ss_info_1028_0179, + &pci_ss_info_1028_0182, + &pci_ss_info_1028_0183, + &pci_ss_info_1028_0188, + &pci_ss_info_1028_0196, + &pci_ss_info_1028_019a, + &pci_ss_info_1028_019d, + &pci_ss_info_1028_01a2, + &pci_ss_info_1028_01ad, + &pci_ss_info_1028_0287, + &pci_ss_info_1028_0291, + &pci_ss_info_1028_0407, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_0533, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1079, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_4134, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_865d, + &pci_ss_info_1028_c082, + &pci_ss_info_1028_c134, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0850, + &pci_ss_info_102b_08c7, + &pci_ss_info_102b_0907, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0d43, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1020, + &pci_ss_info_102b_1030, + &pci_ss_info_102b_1047, + &pci_ss_info_102b_1087, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_14e1, + &pci_ss_info_102b_1820, + &pci_ss_info_102b_1830, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1c10, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2021, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2538, + &pci_ss_info_102b_2811, + &pci_ss_info_102b_2c11, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3007, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48d0, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_0000, + &pci_ss_info_1033_0035, + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80a8, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + &pci_ss_info_1033_80cc, + &pci_ss_info_1033_80cd, + &pci_ss_info_1033_80e5, + &pci_ss_info_1033_8110, + &pci_ss_info_1033_8112, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_6330, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_0024, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_0850, + &pci_ss_info_103c_088c, + &pci_ss_info_103c_0890, + &pci_ss_info_103c_099c, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_10eb, + &pci_ss_info_103c_10ec, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + &pci_ss_info_103c_128a, + &pci_ss_info_103c_128b, + &pci_ss_info_103c_12a4, + &pci_ss_info_103c_12a6, + &pci_ss_info_103c_12a8, + &pci_ss_info_103c_12bc, + &pci_ss_info_103c_12c1, + &pci_ss_info_103c_12c3, + &pci_ss_info_103c_12ca, + &pci_ss_info_103c_12cf, + &pci_ss_info_103c_12d5, + &pci_ss_info_103c_12fa, + &pci_ss_info_103c_1300, + &pci_ss_info_103c_1301, + &pci_ss_info_103c_1356, + &pci_ss_info_103c_2a0d, + &pci_ss_info_103c_308b, + &pci_ss_info_103c_3100, + &pci_ss_info_103c_3101, + &pci_ss_info_103c_3102, + &pci_ss_info_103c_3103, + &pci_ss_info_103c_3226, + &pci_ss_info_103c_3227, + &pci_ss_info_103c_60e7, + &pci_ss_info_103c_7031, + &pci_ss_info_103c_7032, + &pci_ss_info_103c_7039, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_002a, + &pci_ss_info_1043_0120, + &pci_ss_info_1043_0127, + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0210, + &pci_ss_info_1043_032e, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_100f, + &pci_ss_info_1043_1106, + &pci_ss_info_1043_130f, + &pci_ss_info_1043_1702, + &pci_ss_info_1043_1703, + &pci_ss_info_1043_1707, + &pci_ss_info_1043_173c, + &pci_ss_info_1043_1881, + &pci_ss_info_1043_1967, + &pci_ss_info_1043_1987, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_4823, + &pci_ss_info_1043_4840, + &pci_ss_info_1043_4842, + &pci_ss_info_1043_4843, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8023, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_802c, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_8035, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_806f, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807e, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_8080, + &pci_ss_info_1043_808a, + &pci_ss_info_1043_808b, + &pci_ss_info_1043_808c, + &pci_ss_info_1043_808d, + &pci_ss_info_1043_8095, + &pci_ss_info_1043_809e, + &pci_ss_info_1043_80a1, + &pci_ss_info_1043_80a3, + &pci_ss_info_1043_80a5, + &pci_ss_info_1043_80a6, + &pci_ss_info_1043_80a7, + &pci_ss_info_1043_80a8, + &pci_ss_info_1043_80ab, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80b0, + &pci_ss_info_1043_80e2, + &pci_ss_info_1043_80eb, + &pci_ss_info_1043_80ed, + &pci_ss_info_1043_80f2, + &pci_ss_info_1043_80f3, + &pci_ss_info_1043_80f5, + &pci_ss_info_1043_8109, + &pci_ss_info_1043_810f, + &pci_ss_info_1043_811a, + &pci_ss_info_1043_812a, + &pci_ss_info_1043_8134, + &pci_ss_info_1043_8141, + &pci_ss_info_1043_8142, + &pci_ss_info_1043_8145, + &pci_ss_info_1043_814a, + &pci_ss_info_1043_815a, + &pci_ss_info_1043_817b, + &pci_ss_info_1043_81a6, + &pci_ss_info_1043_c002, + &pci_ss_info_1043_c003, + &pci_ss_info_1043_c004, + &pci_ss_info_1043_c005, + &pci_ss_info_1043_c006, + &pci_ss_info_1043_c01a, + &pci_ss_info_1043_c01b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c032, + &pci_ss_info_1044_c035, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0935, + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a34, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0a36, + &pci_ss_info_1048_0a42, + &pci_ss_info_1048_0a43, + &pci_ss_info_1048_0a44, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c19, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c1c, + &pci_ss_info_1048_0c20, + &pci_ss_info_1048_0c21, + &pci_ss_info_1048_0c28, + &pci_ss_info_1048_0c29, + &pci_ss_info_1048_0c2a, + &pci_ss_info_1048_0c2b, + &pci_ss_info_1048_0c2e, + &pci_ss_info_1048_0c2f, + &pci_ss_info_1048_0c30, + &pci_ss_info_1048_0c31, + &pci_ss_info_1048_0c32, + &pci_ss_info_1048_0c33, + &pci_ss_info_1048_0c34, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c3b, + &pci_ss_info_1048_0c40, + &pci_ss_info_1048_0c41, + &pci_ss_info_1048_0c42, + &pci_ss_info_1048_0c43, + &pci_ss_info_1048_0c44, + &pci_ss_info_1048_0c45, + &pci_ss_info_1048_0c48, + &pci_ss_info_1048_0c4a, + &pci_ss_info_1048_0c4b, + &pci_ss_info_1048_0c50, + &pci_ss_info_1048_0c52, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_0c60, + &pci_ss_info_1048_0c61, + &pci_ss_info_1048_0c63, + &pci_ss_info_1048_0c64, + &pci_ss_info_1048_0c65, + &pci_ss_info_1048_0c66, + &pci_ss_info_1048_0c70, + &pci_ss_info_1048_1500, + &pci_ss_info_1048_226b, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +#define pci_ss_list_104a NULL +#define pci_ss_list_104b NULL +static const pciSubsystemInfo *pci_ss_list_104c[] = { + &pci_ss_info_104c_9066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_810f, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + &pci_ss_info_1057_7025, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_1275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105b[] = { + &pci_ss_info_105b_0c19, + NULL +}; +#endif +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_0037, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + &pci_ss_info_1069_0030, + &pci_ss_info_1069_0040, + &pci_ss_info_1069_0050, + &pci_ss_info_1069_0052, + &pci_ss_info_1069_0054, + &pci_ss_info_1069_0072, + &pci_ss_info_1069_0200, + &pci_ss_info_1069_0202, + &pci_ss_info_1069_0204, + &pci_ss_info_1069_0206, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b[] = { + &pci_ss_info_106b_004e, + &pci_ss_info_106b_5811, + NULL +}; +#endif +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1071[] = { + &pci_ss_info_1071_7150, + &pci_ss_info_1071_8160, + NULL +}; +#endif +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + &pci_ss_info_1077_0002, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1079[] = { + &pci_ss_info_1079_891f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_3015, + &pci_ss_info_107b_4009, + &pci_ss_info_107b_5350, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + &pci_ss_info_107b_8920, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2134, + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2822, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2842, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + &pci_ss_info_107d_6613, + &pci_ss_info_107d_6620, + &pci_ss_info_107d_663c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_108e[] = { + &pci_ss_info_108e_10cf, + NULL +}; +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_00b8, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + &pci_ss_info_1095_10cf, + &pci_ss_info_1095_3112, + &pci_ss_info_1095_3114, + &pci_ss_info_1095_3124, + &pci_ss_info_1095_3512, + &pci_ss_info_1095_3680, + &pci_ss_info_1095_6112, + &pci_ss_info_1095_6114, + &pci_ss_info_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + &pci_ss_info_109f_3197, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9[] = { + &pci_ss_info_10a9_8002, + &pci_ss_info_10a9_8010, + &pci_ss_info_10a9_8011, + &pci_ss_info_10a9_8012, + NULL +}; +#endif +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + &pci_ss_info_10b0_0002, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_1067, + &pci_ss_info_10b5_1172, + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2221, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2431, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_2696, + &pci_ss_info_10b5_2717, + &pci_ss_info_10b5_2844, + &pci_ss_info_10b5_2862, + &pci_ss_info_10b5_2905, + &pci_ss_info_10b5_2906, + &pci_ss_info_10b5_2940, + &pci_ss_info_10b5_2977, + &pci_ss_info_10b5_2978, + &pci_ss_info_10b5_2979, + &pci_ss_info_10b5_3025, + &pci_ss_info_10b5_3068, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_0010, + &pci_ss_info_10b7_0020, + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2031, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_2635, + &pci_ss_info_10b8_2802, + &pci_ss_info_10b8_2835, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + &pci_ss_info_10b8_a835, + &pci_ss_info_10b8_b452, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_5451, + &pci_ss_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105e, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_0008, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + &pci_ss_info_10de_006b, + &pci_ss_info_10de_0091, + &pci_ss_info_10de_00a1, + &pci_ss_info_10de_0179, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + &pci_ss_info_10e1_10cf, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + &pci_ss_info_10f1_2466, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + &pci_ss_info_10f7_8338, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fc[] = { + &pci_ss_info_10fc_d003, + &pci_ss_info_10fc_d035, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fd[] = { + &pci_ss_info_10fd_a430, + NULL +}; +#endif +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0007, + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_0058, + &pci_ss_info_1102_1001, + &pci_ss_info_1102_1002, + &pci_ss_info_1102_1006, + &pci_ss_info_1102_1007, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_2002, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + &pci_ss_info_1102_8064, + &pci_ss_info_1102_8065, + &pci_ss_info_1102_8067, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0003, + &pci_ss_info_1103_0004, + &pci_ss_info_1103_0005, + &pci_ss_info_1103_0006, + &pci_ss_info_1103_0007, + &pci_ss_info_1103_0008, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105[] = { + &pci_ss_info_1105_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_3059, + &pci_ss_info_1106_3227, + &pci_ss_info_1106_4161, + &pci_ss_info_1106_4511, + NULL +}; +#endif +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0000, + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0021, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_0051, + &pci_ss_info_110a_008b, + &pci_ss_info_110a_5938, + &pci_ss_info_110a_8005, + &pci_ss_info_110a_ffff, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_2242, + &pci_ss_info_1113_4203, + &pci_ss_info_1113_9211, + &pci_ss_info_1113_d301, + &pci_ss_info_1113_ec01, + &pci_ss_info_1113_ee03, + &pci_ss_info_1113_ee08, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131[] = { + &pci_ss_info_1131_2001, + &pci_ss_info_1131_2005, + &pci_ss_info_1131_4e85, + &pci_ss_info_1131_4f56, + &pci_ss_info_1131_4f60, + &pci_ss_info_1131_4f61, + &pci_ss_info_1131_5f61, + &pci_ss_info_1131_6752, + &pci_ss_info_1131_7133, + NULL +}; +#endif +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_1300, + &pci_ss_info_1133_1800, + &pci_ss_info_1133_1c01, + &pci_ss_info_1133_1c02, + &pci_ss_info_1133_1c03, + &pci_ss_info_1133_1c04, + &pci_ss_info_1133_1c05, + &pci_ss_info_1133_1c06, + &pci_ss_info_1133_1c07, + &pci_ss_info_1133_1c08, + &pci_ss_info_1133_1c09, + &pci_ss_info_1133_1c0a, + &pci_ss_info_1133_1c0b, + &pci_ss_info_1133_1c0c, + &pci_ss_info_1133_2400, + &pci_ss_info_1133_2800, + &pci_ss_info_1133_e013, + &pci_ss_info_1133_e015, + &pci_ss_info_1133_e017, + &pci_ss_info_1133_e018, + &pci_ss_info_1133_e019, + &pci_ss_info_1133_e01b, + &pci_ss_info_1133_e024, + &pci_ss_info_1133_e028, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_0121, + &pci_ss_info_1148_0221, + &pci_ss_info_1148_0321, + &pci_ss_info_1148_0421, + &pci_ss_info_1148_0621, + &pci_ss_info_1148_0721, + &pci_ss_info_1148_0821, + &pci_ss_info_1148_0921, + &pci_ss_info_1148_1121, + &pci_ss_info_1148_1221, + &pci_ss_info_1148_2100, + &pci_ss_info_1148_21d0, + &pci_ss_info_1148_2200, + &pci_ss_info_1148_3221, + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_8100, + &pci_ss_info_1148_8200, + &pci_ss_info_1148_9100, + &pci_ss_info_1148_9200, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#define pci_ss_list_1154 NULL +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + &pci_ss_info_1179_ff01, + &pci_ss_info_1179_ff10, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c[] = { + &pci_ss_info_117c_8013, + &pci_ss_info_117c_8014, + NULL +}; +#endif +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1303, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_1403, + &pci_ss_info_1186_3202, + &pci_ss_info_1186_3203, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_3700, + &pci_ss_info_1186_3a12, + &pci_ss_info_1186_3a13, + &pci_ss_info_1186_3a14, + &pci_ss_info_1186_3a15, + &pci_ss_info_1186_3a16, + &pci_ss_info_1186_3a17, + &pci_ss_info_1186_3a18, + &pci_ss_info_1186_3a19, + &pci_ss_info_1186_3a22, + &pci_ss_info_1186_3a23, + &pci_ss_info_1186_3a24, + &pci_ss_info_1186_3a63, + &pci_ss_info_1186_3a94, + &pci_ss_info_1186_3b00, + &pci_ss_info_1186_3b01, + &pci_ss_info_1186_3b04, + &pci_ss_info_1186_3b05, + &pci_ss_info_1186_4c00, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#define pci_ss_list_1195 NULL +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab[] = { + &pci_ss_info_11ab_0121, + &pci_ss_info_11ab_0321, + &pci_ss_info_11ab_1021, + &pci_ss_info_11ab_3521, + &pci_ss_info_11ab_3621, + &pci_ss_info_11ab_5021, + &pci_ss_info_11ab_5221, + &pci_ss_info_11ab_5321, + &pci_ss_info_11ab_9521, + NULL +}; +#endif +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_000f, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + &pci_ss_info_11bd_002b, + &pci_ss_info_11bd_002d, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + &pci_ss_info_11c1_ab12, + &pci_ss_info_11c1_ab13, + &pci_ss_info_11c1_ab15, + &pci_ss_info_11c1_ab16, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0057, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_1400, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + &pci_ss_info_1244_0f00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_1070, + &pci_ss_info_124b_1170, + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2702, + &pci_ss_info_1259_2703, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2971, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2973, + &pci_ss_info_1259_2974, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2976, + &pci_ss_info_1259_2977, + &pci_ss_info_1259_c104, + &pci_ss_info_1259_c107, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#define pci_ss_list_1260 NULL +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + &pci_ss_info_1274_8001, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127d[] = { + &pci_ss_info_127d_0000, + NULL +}; +#endif +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283[] = { + &pci_ss_info_1283_0001, + NULL +}; +#endif +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1297[] = { + &pci_ss_info_1297_c160, + &pci_ss_info_1297_c240, + &pci_ss_info_1297_c241, + &pci_ss_info_1297_c242, + &pci_ss_info_1297_c243, + &pci_ss_info_1297_c244, + &pci_ss_info_1297_f641, + NULL +}; +#endif +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ab[] = { + &pci_ss_info_12ab_5961, + NULL +}; +#endif +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#define pci_ss_list_12c4 NULL +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c7[] = { + &pci_ss_info_12c7_4001, + NULL +}; +#endif +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_0002, + &pci_ss_info_12d9_000a, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12df[] = { + &pci_ss_info_12df_4422, + NULL +}; +#endif +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12f8[] = { + &pci_ss_info_12f8_8a02, + NULL +}; +#endif +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317[] = { + &pci_ss_info_1317_8201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319[] = { + &pci_ss_info_1319_1319, + NULL +}; +#endif +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + &pci_ss_info_131f_2050, + &pci_ss_info_131f_2051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#define pci_ss_list_1351 NULL +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_001e, + &pci_ss_info_1371_001f, + &pci_ss_info_1371_0020, + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_4105, + &pci_ss_info_1385_4800, + &pci_ss_info_1385_4d00, + &pci_ss_info_1385_4e00, + &pci_ss_info_1385_f004, + &pci_ss_info_1385_f311, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + &pci_ss_info_1397_3136, + &pci_ss_info_1397_3137, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13b9[] = { + &pci_ss_info_13b9_1421, + NULL +}; +#endif +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13bd[] = { + &pci_ss_info_13bd_100c, + &pci_ss_info_13bd_100d, + &pci_ss_info_13bd_100e, + &pci_ss_info_13bd_1019, + &pci_ss_info_13bd_f6f1, + NULL +}; +#endif +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1[] = { + &pci_ss_info_13c1_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c2[] = { + &pci_ss_info_13c2_0000, + &pci_ss_info_13c2_0001, + &pci_ss_info_13c2_0002, + &pci_ss_info_13c2_0003, + &pci_ss_info_13c2_0004, + &pci_ss_info_13c2_0006, + &pci_ss_info_13c2_0008, + &pci_ss_info_13c2_000a, + &pci_ss_info_13c2_1003, + &pci_ss_info_13c2_1004, + &pci_ss_info_13c2_1005, + &pci_ss_info_13c2_100c, + &pci_ss_info_13c2_100f, + &pci_ss_info_13c2_1011, + &pci_ss_info_13c2_1013, + &pci_ss_info_13c2_1102, + NULL +}; +#endif +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + &pci_ss_info_13d1_aba0, + &pci_ss_info_13d1_ac11, + &pci_ss_info_13d1_ac12, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + &pci_ss_info_13e9_1000, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412[] = { + &pci_ss_info_1412_1712, + &pci_ss_info_1412_1724, + &pci_ss_info_1412_3630, + &pci_ss_info_1412_3631, + &pci_ss_info_1412_d630, + &pci_ss_info_1412_d631, + &pci_ss_info_1412_d632, + &pci_ss_info_1412_d633, + &pci_ss_info_1412_d634, + &pci_ss_info_1412_d635, + &pci_ss_info_1412_d637, + &pci_ss_info_1412_d638, + &pci_ss_info_1412_d63b, + &pci_ss_info_1412_d63c, + NULL +}; +#endif +#define pci_ss_list_1413 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1414[] = { + &pci_ss_info_1414_0003, + &pci_ss_info_1414_0004, + NULL +}; +#endif +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_1712, + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1421[] = { + &pci_ss_info_1421_0350, + &pci_ss_info_1421_0370, + NULL +}; +#endif +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#define pci_ss_list_1435 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_1702, + &pci_ss_info_144f_1703, + &pci_ss_info_144f_1707, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_0c11, + &pci_ss_info_1458_1000, + &pci_ss_info_1458_1019, + &pci_ss_info_1458_24c2, + &pci_ss_info_1458_24d1, + &pci_ss_info_1458_24d2, + &pci_ss_info_1458_2558, + &pci_ss_info_1458_2560, + &pci_ss_info_1458_2570, + &pci_ss_info_1458_2578, + &pci_ss_info_1458_2580, + &pci_ss_info_1458_2582, + &pci_ss_info_1458_2659, + &pci_ss_info_1458_265a, + &pci_ss_info_1458_266a, + &pci_ss_info_1458_266f, + &pci_ss_info_1458_3124, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_4018, + &pci_ss_info_1458_4019, + &pci_ss_info_1458_4024, + &pci_ss_info_1458_4025, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_5006, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + &pci_ss_info_1458_b001, + &pci_ss_info_1458_b003, + &pci_ss_info_1458_d000, + &pci_ss_info_1458_e000, + &pci_ss_info_1458_e381, + &pci_ss_info_1458_e911, + &pci_ss_info_1458_e931, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0002, + &pci_ss_info_1461_0003, + &pci_ss_info_1461_0004, + &pci_ss_info_1461_000b, + &pci_ss_info_1461_050c, + &pci_ss_info_1461_0761, + &pci_ss_info_1461_10ff, + &pci_ss_info_1461_2108, + &pci_ss_info_1461_2115, + &pci_ss_info_1461_2c00, + &pci_ss_info_1461_2c05, + &pci_ss_info_1461_a3cf, + &pci_ss_info_1461_a70a, + &pci_ss_info_1461_a70b, + &pci_ss_info_1461_d6ee, + &pci_ss_info_1461_f31f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_0080, + &pci_ss_info_1462_052c, + &pci_ss_info_1462_058c, + &pci_ss_info_1462_1009, + &pci_ss_info_1462_3091, + &pci_ss_info_1462_309e, + &pci_ss_info_1462_3300, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3800, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5470, + &pci_ss_info_1462_5506, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6828, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6835, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_7020, + &pci_ss_info_1462_7028, + &pci_ss_info_1462_702c, + &pci_ss_info_1462_702d, + &pci_ss_info_1462_702e, + &pci_ss_info_1462_7100, + &pci_ss_info_1462_7280, + &pci_ss_info_1462_728c, + &pci_ss_info_1462_7580, + &pci_ss_info_1462_758c, + &pci_ss_info_1462_8606, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + &pci_ss_info_1462_8852, + &pci_ss_info_1462_8880, + &pci_ss_info_1462_8900, + &pci_ss_info_1462_9171, + &pci_ss_info_1462_9350, + &pci_ss_info_1462_9360, + &pci_ss_info_1462_971d, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0202, + &pci_ss_info_1468_0311, + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_0450, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#define pci_ss_list_1471 NULL +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_1406, + &pci_ss_info_147b_1407, + &pci_ss_info_147b_1408, + &pci_ss_info_147b_1c0b, + &pci_ss_info_147b_6191, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_8f0d, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_0214, + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + &pci_ss_info_148c_2064, + &pci_ss_info_148c_2066, + &pci_ss_info_148c_2067, + &pci_ss_info_148c_2073, + &pci_ss_info_148c_2116, + &pci_ss_info_148c_2117, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1498[] = { + &pci_ss_info_1498_0362, + NULL +}; +#endif +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14b7[] = { + &pci_ss_info_14b7_0a60, + NULL +}; +#endif +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + &pci_ss_info_14c0_0012, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c2[] = { + &pci_ss_info_14c2_0105, + &pci_ss_info_14c2_0205, + NULL +}; +#endif +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c7[] = { + &pci_ss_info_14c7_0107, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cb[] = { + &pci_ss_info_14cb_0100, + &pci_ss_info_14cb_0200, + NULL +}; +#endif +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2012, + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_0449, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_4318, + &pci_ss_info_14e4_4320, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ef[] = { + &pci_ss_info_14ef_0220, + NULL +}; +#endif +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0187, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0342, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_2045, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fb[] = { + &pci_ss_info_14fb_0101, + &pci_ss_info_14fb_0102, + &pci_ss_info_14fb_0202, + &pci_ss_info_14fb_0611, + &pci_ss_info_14fb_0612, + &pci_ss_info_14fb_0613, + &pci_ss_info_14fb_0614, + &pci_ss_info_14fb_0621, + &pci_ss_info_14fb_0622, + &pci_ss_info_14fb_0810, + NULL +}; +#endif +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_0e70, + &pci_ss_info_14ff_1100, + &pci_ss_info_14ff_c401, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_1930, + &pci_ss_info_1509_1968, + &pci_ss_info_1509_2990, + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#define pci_ss_list_1517 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1518[] = { + &pci_ss_info_1518_0200, + NULL +}; +#endif +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + &pci_ss_info_1522_0c00, + &pci_ss_info_1522_0d00, + &pci_ss_info_1522_1d00, + &pci_ss_info_1522_2000, + &pci_ss_info_1522_2100, + &pci_ss_info_1522_2200, + &pci_ss_info_1522_2300, + &pci_ss_info_1522_2400, + &pci_ss_info_1522_2500, + &pci_ss_info_1522_2600, + &pci_ss_info_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_153b[] = { + &pci_ss_info_153b_1115, + &pci_ss_info_153b_111b, + &pci_ss_info_153b_1125, + &pci_ss_info_153b_112b, + &pci_ss_info_153b_112c, + &pci_ss_info_153b_1130, + &pci_ss_info_153b_1136, + &pci_ss_info_153b_1138, + &pci_ss_info_153b_1142, + &pci_ss_info_153b_1143, + &pci_ss_info_153b_1145, + &pci_ss_info_153b_1147, + &pci_ss_info_153b_1151, + &pci_ss_info_153b_1152, + &pci_ss_info_153b_1153, + &pci_ss_info_153b_1158, + &pci_ss_info_153b_1162, + NULL +}; +#endif +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1540[] = { + &pci_ss_info_1540_2580, + &pci_ss_info_1540_9524, + NULL +}; +#endif +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + &pci_ss_info_1554_4811, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_04a0, + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_002d, + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_156d[] = { + &pci_ss_info_156d_b400, + &pci_ss_info_156d_b550, + &pci_ss_info_156d_b560, + &pci_ss_info_156d_b700, + &pci_ss_info_156d_b795, + &pci_ss_info_156d_b797, + NULL +}; +#endif +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +static const pciSubsystemInfo *pci_ss_list_15ad[] = { + &pci_ss_info_15ad_1976, + NULL +}; +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15bd[] = { + &pci_ss_info_15bd_1003, + NULL +}; +#endif +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d4[] = { + &pci_ss_info_15d4_0047, + NULL +}; +#endif +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_4580, + &pci_ss_info_15d9_9005, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#define pci_ss_list_1601 NULL +#define pci_ss_list_1602 NULL +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#define pci_ss_list_1612 NULL +#define pci_ss_list_1619 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_161f[] = { + &pci_ss_info_161f_2029, + &pci_ss_info_161f_203c, + &pci_ss_info_161f_203d, + &pci_ss_info_161f_3017, + NULL +}; +#endif +#define pci_ss_list_1626 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1637 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_165f NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#define pci_ss_list_166d NULL +#define pci_ss_list_1677 NULL +#define pci_ss_list_167b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0002, + &pci_ss_info_1681_0003, + &pci_ss_info_1681_0010, + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a000, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1682[] = { + &pci_ss_info_1682_211c, + &pci_ss_info_1682_2120, + NULL +}; +#endif +#define pci_ss_list_1688 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c[] = { + &pci_ss_info_168c_0013, + &pci_ss_info_168c_1025, + &pci_ss_info_168c_1027, + &pci_ss_info_168c_1052, + &pci_ss_info_168c_2026, + &pci_ss_info_168c_2041, + &pci_ss_info_168c_2042, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1695[] = { + &pci_ss_info_1695_3005, + &pci_ss_info_1695_300c, + &pci_ss_info_1695_9025, + &pci_ss_info_1695_9029, + NULL +}; +#endif +#define pci_ss_list_169c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16a5[] = { + &pci_ss_info_16a5_1601, + &pci_ss_info_16a5_1605, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ab[] = { + &pci_ss_info_16ab_7302, + &pci_ss_info_16ab_8501, + NULL +}; +#endif +#define pci_ss_list_16ae NULL +#define pci_ss_list_16af NULL +#define pci_ss_list_16b4 NULL +#define pci_ss_list_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_0003, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16c8 NULL +#define pci_ss_list_16ca NULL +#define pci_ss_list_16cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ce[] = { + &pci_ss_info_16ce_1040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16df[] = { + &pci_ss_info_16df_0011, + &pci_ss_info_16df_0012, + &pci_ss_info_16df_0013, + &pci_ss_info_16df_0014, + &pci_ss_info_16df_0015, + &pci_ss_info_16df_0016, + NULL +}; +#endif +#define pci_ss_list_16e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ec[] = { + &pci_ss_info_16ec_0119, + NULL +}; +#endif +#define pci_ss_list_16ed NULL +#define pci_ss_list_16f3 NULL +#define pci_ss_list_16f4 NULL +#define pci_ss_list_16f6 NULL +#define pci_ss_list_1702 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#define pci_ss_list_1725 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1734[] = { + &pci_ss_info_1734_007a, + &pci_ss_info_1734_100b, + &pci_ss_info_1734_1011, + &pci_ss_info_1734_1012, + &pci_ss_info_1734_101c, + &pci_ss_info_1734_1025, + &pci_ss_info_1734_103e, + &pci_ss_info_1734_1052, + &pci_ss_info_1734_1055, + &pci_ss_info_1734_105a, + &pci_ss_info_1734_105b, + &pci_ss_info_1734_105c, + &pci_ss_info_1734_105d, + &pci_ss_info_1734_1061, + &pci_ss_info_1734_1065, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_0015, + &pci_ss_info_1737_0016, + &pci_ss_info_1737_0024, + &pci_ss_info_1737_0032, + &pci_ss_info_1737_3874, + &pci_ss_info_1737_4320, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#define pci_ss_list_1749 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7146, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + &pci_ss_info_174b_7c12, + &pci_ss_info_174b_7c13, + &pci_ss_info_174b_7c19, + &pci_ss_info_174b_7c28, + &pci_ss_info_174b_7c29, + NULL +}; +#endif +#define pci_ss_list_174d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_175c[] = { + &pci_ss_info_175c_4200, + &pci_ss_info_175c_4300, + &pci_ss_info_175c_4400, + &pci_ss_info_175c_5000, + &pci_ss_info_175c_5100, + &pci_ss_info_175c_6100, + &pci_ss_info_175c_6200, + &pci_ss_info_175c_6400, + &pci_ss_info_175c_8700, + &pci_ss_info_175c_8800, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#define pci_ss_list_1775 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + &pci_ss_info_1787_4002, + &pci_ss_info_1787_4003, + &pci_ss_info_1787_5964, + &pci_ss_info_1787_5965, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#define pci_ss_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + &pci_ss_info_1799_5000, + &pci_ss_info_1799_7001, + &pci_ss_info_1799_700a, + &pci_ss_info_1799_7010, + &pci_ss_info_1799_701a, + NULL +}; +#endif +#define pci_ss_list_179c NULL +#define pci_ss_list_17a0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17aa[] = { + &pci_ss_info_17aa_0286, + &pci_ss_info_17aa_0287, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + &pci_ss_info_17af_200c, + &pci_ss_info_17af_200d, + &pci_ss_info_17af_2012, + &pci_ss_info_17af_2013, + NULL +}; +#endif +#define pci_ss_list_17b3 NULL +#define pci_ss_list_17b4 NULL +#define pci_ss_list_17c0 NULL +#define pci_ss_list_17c2 NULL +#define pci_ss_list_17cb NULL +#define pci_ss_list_17cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17cf[] = { + &pci_ss_info_17cf_0014, + &pci_ss_info_17cf_0020, + &pci_ss_info_17cf_0037, + NULL +}; +#endif +#define pci_ss_list_17d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17de[] = { + &pci_ss_info_17de_08a1, + &pci_ss_info_17de_08a6, + &pci_ss_info_17de_a8a6, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ee[] = { + &pci_ss_info_17ee_2002, + &pci_ss_info_17ee_2003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17f2[] = { + &pci_ss_info_17f2_1c03, + &pci_ss_info_17f2_2c08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe[] = { + &pci_ss_info_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ff[] = { + &pci_ss_info_17ff_0585, + NULL +}; +#endif +#define pci_ss_list_1813 NULL +#define pci_ss_list_1814 NULL +#define pci_ss_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1822[] = { + &pci_ss_info_1822_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_182d[] = { + &pci_ss_info_182d_201d, + NULL +}; +#endif +#define pci_ss_list_1830 NULL +#define pci_ss_list_183b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1849[] = { + &pci_ss_info_1849_0571, + &pci_ss_info_1849_3038, + &pci_ss_info_1849_3065, + &pci_ss_info_1849_3099, + &pci_ss_info_1849_3104, + &pci_ss_info_1849_3149, + &pci_ss_info_1849_3177, + &pci_ss_info_1849_3189, + &pci_ss_info_1849_3227, + &pci_ss_info_1849_8052, + &pci_ss_info_1849_8053, + &pci_ss_info_1849_9761, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1854[] = { + &pci_ss_info_1854_000b, + &pci_ss_info_1854_000c, + &pci_ss_info_1854_000d, + &pci_ss_info_1854_000e, + &pci_ss_info_1854_000f, + &pci_ss_info_1854_0010, + &pci_ss_info_1854_0011, + &pci_ss_info_1854_0012, + &pci_ss_info_1854_0013, + &pci_ss_info_1854_0014, + &pci_ss_info_1854_0015, + &pci_ss_info_1854_0016, + &pci_ss_info_1854_0017, + &pci_ss_info_1854_0018, + &pci_ss_info_1854_0019, + &pci_ss_info_1854_001a, + &pci_ss_info_1854_001b, + &pci_ss_info_1854_001c, + &pci_ss_info_1854_001d, + &pci_ss_info_1854_001e, + &pci_ss_info_1854_001f, + &pci_ss_info_1854_0020, + &pci_ss_info_1854_0021, + &pci_ss_info_1854_0022, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185b[] = { + &pci_ss_info_185b_c100, + &pci_ss_info_185b_c200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185f[] = { + &pci_ss_info_185f_1220, + &pci_ss_info_185f_22a0, + NULL +}; +#endif +#define pci_ss_list_1864 NULL +#define pci_ss_list_1867 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_187e[] = { + &pci_ss_info_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1894[] = { + &pci_ss_info_1894_a006, + &pci_ss_info_1894_fe01, + NULL +}; +#endif +#define pci_ss_list_1896 NULL +#define pci_ss_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ac[] = { + &pci_ss_info_18ac_d500, + &pci_ss_info_18ac_d810, + &pci_ss_info_18ac_d820, + &pci_ss_info_18ac_db00, + &pci_ss_info_18ac_db10, + NULL +}; +#endif +#define pci_ss_list_18b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18bc[] = { + &pci_ss_info_18bc_0050, + &pci_ss_info_18bc_0051, + &pci_ss_info_18bc_0053, + &pci_ss_info_18bc_0100, + &pci_ss_info_18bc_0101, + &pci_ss_info_18bc_0170, + &pci_ss_info_18bc_0171, + &pci_ss_info_18bc_0172, + &pci_ss_info_18bc_0173, + NULL +}; +#endif +#define pci_ss_list_18c8 NULL +#define pci_ss_list_18c9 NULL +#define pci_ss_list_18ca NULL +#define pci_ss_list_18d2 NULL +#define pci_ss_list_18dd NULL +#define pci_ss_list_18e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec[] = { + &pci_ss_info_18ec_d001, + &pci_ss_info_18ec_d002, + &pci_ss_info_18ec_d003, + &pci_ss_info_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18fb[] = { + &pci_ss_info_18fb_7872, + NULL +}; +#endif +#define pci_ss_list_1924 NULL +#define pci_ss_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1931[] = { + &pci_ss_info_1931_000a, + &pci_ss_info_1931_000b, + NULL +}; +#endif +#define pci_ss_list_1942 NULL +#define pci_ss_list_1957 NULL +#define pci_ss_list_1958 NULL +#define pci_ss_list_1966 NULL +#define pci_ss_list_196a NULL +#define pci_ss_list_197b NULL +#define pci_ss_list_1989 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1993[] = { + &pci_ss_info_1993_0ded, + &pci_ss_info_1993_0dee, + &pci_ss_info_1993_0def, + NULL +}; +#endif +#define pci_ss_list_19ae NULL +#define pci_ss_list_19d4 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3906, + &pci_ss_info_1de1_3907, + &pci_ss_info_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_1fc0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1fc1[] = { + &pci_ss_info_1fc1_0026, + &pci_ss_info_1fc1_0027, + NULL +}; +#endif +#define pci_ss_list_1fce NULL +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_2801, + &pci_ss_info_270f_2803, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + &pci_ss_info_270f_f641, + &pci_ss_info_270f_f645, + &pci_ss_info_270f_fc00, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_3842 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_144f, + &pci_ss_info_4005_4000, + &pci_ss_info_4005_4710, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_4144 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_494f NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53[] = { + &pci_ss_info_4c53_1000, + &pci_ss_info_4c53_1010, + &pci_ss_info_4c53_1020, + &pci_ss_info_4c53_1030, + &pci_ss_info_4c53_1040, + &pci_ss_info_4c53_1050, + &pci_ss_info_4c53_1051, + &pci_ss_info_4c53_1060, + &pci_ss_info_4c53_1070, + &pci_ss_info_4c53_1080, + &pci_ss_info_4c53_1090, + &pci_ss_info_4c53_10a0, + &pci_ss_info_4c53_10b0, + &pci_ss_info_4c53_10d0, + &pci_ss_info_4c53_10e0, + &pci_ss_info_4c53_1300, + &pci_ss_info_4c53_1310, + &pci_ss_info_4c53_3000, + &pci_ss_info_4c53_3001, + &pci_ss_info_4c53_3002, + &pci_ss_info_4c53_3010, + &pci_ss_info_4c53_3011, + &pci_ss_info_4c53_4000, + NULL +}; +#endif +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5168[] = { + &pci_ss_info_5168_0138, + &pci_ss_info_5168_0212, + &pci_ss_info_5168_0214, + &pci_ss_info_5168_0306, + &pci_ss_info_5168_0502, + NULL +}; +#endif +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_2036, + &pci_ss_info_5654_3132, + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_5851 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_7063[] = { + &pci_ss_info_7063_3000, + NULL +}; +#endif +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_807d[] = { + &pci_ss_info_807d_0035, + &pci_ss_info_807d_1043, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_0075, + &pci_ss_info_8086_0076, + &pci_ss_info_8086_0077, + &pci_ss_info_8086_0079, + &pci_ss_info_8086_007b, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_01af, + &pci_ss_info_8086_01c1, + &pci_ss_info_8086_01f7, + &pci_ss_info_8086_0520, + &pci_ss_info_8086_0523, + &pci_ss_info_8086_0530, + &pci_ss_info_8086_0532, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1016, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1018, + &pci_ss_info_8086_1019, + &pci_ss_info_8086_101a, + &pci_ss_info_8086_101e, + &pci_ss_info_8086_1026, + &pci_ss_info_8086_1027, + &pci_ss_info_8086_1028, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_1075, + &pci_ss_info_8086_1076, + &pci_ss_info_8086_1077, + &pci_ss_info_8086_1078, + &pci_ss_info_8086_1079, + &pci_ss_info_8086_107a, + &pci_ss_info_8086_107b, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_110d, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1113, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_1176, + &pci_ss_info_8086_1179, + &pci_ss_info_8086_117a, + &pci_ss_info_8086_1276, + &pci_ss_info_8086_127a, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1376, + &pci_ss_info_8086_1476, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_24db, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_2527, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_301f, + &pci_ss_info_8086_3020, + &pci_ss_info_8086_302f, + &pci_ss_info_8086_3063, + &pci_ss_info_8086_308d, + &pci_ss_info_8086_3108, + &pci_ss_info_8086_3411, + &pci_ss_info_8086_3424, + &pci_ss_info_8086_3427, + &pci_ss_info_8086_3431, + &pci_ss_info_8086_3439, + &pci_ss_info_8086_3499, + &pci_ss_info_8086_4147, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4246, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4532, + &pci_ss_info_8086_4541, + &pci_ss_info_8086_4557, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_524c, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_544e, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + &pci_ss_info_8086_a000, + &pci_ss_info_8086_a01f, + &pci_ss_info_8086_a11f, + &pci_ss_info_8086_e000, + &pci_ss_info_8086_e001, + NULL +}; +#define pci_ss_list_8401 NULL +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8912 NULL +#define pci_ss_list_8c4a NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7881, + &pci_ss_info_9004_7887, + &pci_ss_info_9004_7888, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005[] = { + &pci_ss_info_9005_0003, + &pci_ss_info_9005_000f, + &pci_ss_info_9005_0041, + &pci_ss_info_9005_0106, + &pci_ss_info_9005_0250, + &pci_ss_info_9005_0283, + &pci_ss_info_9005_0284, + &pci_ss_info_9005_0285, + &pci_ss_info_9005_0286, + &pci_ss_info_9005_0287, + &pci_ss_info_9005_0288, + &pci_ss_info_9005_0289, + &pci_ss_info_9005_028a, + &pci_ss_info_9005_028b, + &pci_ss_info_9005_028c, + &pci_ss_info_9005_028d, + &pci_ss_info_9005_028e, + &pci_ss_info_9005_028f, + &pci_ss_info_9005_0290, + &pci_ss_info_9005_0292, + &pci_ss_info_9005_0293, + &pci_ss_info_9005_0294, + &pci_ss_info_9005_0296, + &pci_ss_info_9005_0297, + &pci_ss_info_9005_0298, + &pci_ss_info_9005_0299, + &pci_ss_info_9005_029a, + &pci_ss_info_9005_029b, + &pci_ss_info_9005_029c, + &pci_ss_info_9005_029d, + &pci_ss_info_9005_029e, + &pci_ss_info_9005_029f, + &pci_ss_info_9005_02a0, + &pci_ss_info_9005_02a1, + &pci_ss_info_9005_02a2, + &pci_ss_info_9005_02a3, + &pci_ss_info_9005_02a4, + &pci_ss_info_9005_02a5, + &pci_ss_info_9005_02a6, + &pci_ss_info_9005_0364, + &pci_ss_info_9005_0365, + &pci_ss_info_9005_0800, + &pci_ss_info_9005_1364, + &pci_ss_info_9005_1365, + &pci_ss_info_9005_2180, + &pci_ss_info_9005_6220, + &pci_ss_info_9005_62a0, + &pci_ss_info_9005_62a1, + &pci_ss_info_9005_8100, + &pci_ss_info_9005_a100, + &pci_ss_info_9005_a180, + &pci_ss_info_9005_b500, + &pci_ss_info_9005_e100, + &pci_ss_info_9005_e220, + &pci_ss_info_9005_e2a0, + &pci_ss_info_9005_f500, + &pci_ss_info_9005_f620, + &pci_ss_info_9005_ffff, + NULL +}; +#endif +#define pci_ss_list_907f NULL +#define pci_ss_list_919a NULL +#define pci_ss_list_9412 NULL +#define pci_ss_list_9699 NULL +#define pci_ss_list_9710 NULL +#define pci_ss_list_9902 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a0a0[] = { + &pci_ss_info_a0a0_0007, + &pci_ss_info_a0a0_0022, + &pci_ss_info_a0a0_01b6, + &pci_ss_info_a0a0_0506, + &pci_ss_info_a0a0_0509, + NULL +}; +#endif +#define pci_ss_list_a0f1 NULL +#define pci_ss_list_a200 NULL +#define pci_ss_list_a259 NULL +#define pci_ss_list_a25b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a304[] = { + &pci_ss_info_a304_81b7, + NULL +}; +#endif +#define pci_ss_list_a727 NULL +#define pci_ss_list_aa42 NULL +#define pci_ss_list_ac1e NULL +#define pci_ss_list_ac3d NULL +#define pci_ss_list_aecb NULL +#define pci_ss_list_affe NULL +#define pci_ss_list_b1b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_bd11[] = { + &pci_ss_info_bd11_1200, + NULL +}; +#endif +#define pci_ss_list_c001 NULL +#define pci_ss_list_c0a9 NULL +#define pci_ss_list_c0de NULL +#define pci_ss_list_c0fe NULL +#define pci_ss_list_ca50 NULL +#define pci_ss_list_cafe NULL +#define pci_ss_list_cccc NULL +#define pci_ss_list_cddd NULL +#define pci_ss_list_d161 NULL +#define pci_ss_list_d4d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d531[] = { + &pci_ss_info_d531_c002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d84d[] = { + &pci_ss_info_d84d_4006, + &pci_ss_info_d84d_4008, + &pci_ss_info_d84d_4014, + &pci_ss_info_d84d_4018, + &pci_ss_info_d84d_4025, + &pci_ss_info_d84d_4027, + &pci_ss_info_d84d_4028, + &pci_ss_info_d84d_4036, + &pci_ss_info_d84d_4037, + &pci_ss_info_d84d_4038, + &pci_ss_info_d84d_4052, + &pci_ss_info_d84d_4053, + &pci_ss_info_d84d_4055, + &pci_ss_info_d84d_4058, + &pci_ss_info_d84d_4065, + &pci_ss_info_d84d_4068, + &pci_ss_info_d84d_4078, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_dead[] = { + &pci_ss_info_dead_0800, + NULL +}; +#endif +#define pci_ss_list_deaf NULL +#define pci_ss_list_e000 NULL +#define pci_ss_list_e159 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e4bf[] = { + &pci_ss_info_e4bf_1000, + &pci_ss_info_e4bf_1010, + &pci_ss_info_e4bf_1020, + &pci_ss_info_e4bf_1040, + &pci_ss_info_e4bf_3100, + NULL +}; +#endif +#define pci_ss_list_e55e NULL +#define pci_ss_list_ea01 NULL +#define pci_ss_list_ea60 NULL +#define pci_ss_list_eabb NULL +#define pci_ss_list_eace NULL +#define pci_ss_list_ec80 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_ecc0[] = { + &pci_ss_info_ecc0_0010, + &pci_ss_info_ecc0_0020, + &pci_ss_info_ecc0_0030, + &pci_ss_info_ecc0_0031, + &pci_ss_info_ecc0_0040, + &pci_ss_info_ecc0_0041, + &pci_ss_info_ecc0_0050, + &pci_ss_info_ecc0_0051, + &pci_ss_info_ecc0_0060, + &pci_ss_info_ecc0_0070, + &pci_ss_info_ecc0_0071, + &pci_ss_info_ecc0_0072, + &pci_ss_info_ecc0_0080, + &pci_ss_info_ecc0_0081, + &pci_ss_info_ecc0_0090, + &pci_ss_info_ecc0_00a0, + &pci_ss_info_ecc0_00b0, + &pci_ss_info_ecc0_0100, + NULL +}; +#endif +#define pci_ss_list_edd8 NULL +#define pci_ss_list_f1d0 NULL +#define pci_ss_list_fa57 NULL +#define pci_ss_list_febd NULL +#define pci_ss_list_feda NULL +#define pci_ss_list_fede NULL +#define pci_ss_list_fffd NULL +#define pci_ss_list_fffe NULL +#define pci_ss_list_ffff NULL +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0070_0003 = { + 0x0003, pci_device_0070_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0009 = { + 0x0009, pci_device_0070_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0801 = { + 0x0801, pci_device_0070_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0807 = { + 0x0807, pci_device_0070_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4000 = { + 0x4000, pci_device_0070_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4001 = { + 0x4001, pci_device_0070_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4009 = { + 0x4009, pci_device_0070_4009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4800 = { + 0x4800, pci_device_0070_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4801 = { + 0x4801, pci_device_0070_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4803 = { + 0x4803, pci_device_0070_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_8003 = { + 0x8003, pci_device_0070_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_8801 = { + 0x8801, pci_device_0070_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_c801 = { + 0xc801, pci_device_0070_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_e807 = { + 0xe807, pci_device_0070_e807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_e807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_e817 = { + 0xe817, pci_device_0070_e817, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_e817, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0095_0680 = { + 0x0680, pci_device_0095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0095_0680, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_018a_0106 = { + 0x0106, pci_device_018a_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_018a_0106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_021b_8139 = { + 0x8139, pci_device_021b_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_021b_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0270_0801 = { + 0x0801, pci_device_0270_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0270_0801, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0291_8212 = { + 0x8212, pci_device_0291_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0291_8212, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_02ac_1012 = { + 0x1012, pci_device_02ac_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_02ac_1012, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0357_000a = { + 0x000a, pci_device_0357_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0357_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0432_0001 = { + 0x0001, pci_device_0432_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0432_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_045e_006e = { + 0x006e, pci_device_045e_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_045e_00c2 = { + 0x00c2, pci_device_045e_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_00c2, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_04cf_8818 = { + 0x8818, pci_device_04cf_8818, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_04cf_8818, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05e3_0701 = { + 0x0701, pci_device_05e3_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05e3_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1703 = { + 0x1703, pci_device_0675_1703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1703, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1704 = { + 0x1704, pci_device_0675_1704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_067b_3507 = { + 0x3507, pci_device_067b_3507, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_3507, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b49_064f = { + 0x064f, pci_device_0b49_064f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b49_064f, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0046 = { + 0x0046, pci_device_0e11_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_005a = { + 0x005a, pci_device_0e11_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007c = { + 0x007c, pci_device_0e11_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007d = { + 0x007d, pci_device_0e11_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0085 = { + 0x0085, pci_device_0e11_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00b1 = { + 0x00b1, pci_device_0e11_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00bb = { + 0x00bb, pci_device_0e11_00bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00ca = { + 0x00ca, pci_device_0e11_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cb = { + 0x00cb, pci_device_0e11_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cf = { + 0x00cf, pci_device_0e11_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d0 = { + 0x00d0, pci_device_0e11_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d1 = { + 0x00d1, pci_device_0e11_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00e3 = { + 0x00e3, pci_device_0e11_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4030 = { + 0x4030, pci_device_0e11_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4031 = { + 0x4031, pci_device_0e11_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4032 = { + 0x4032, pci_device_0e11_4032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4033 = { + 0x4033, pci_device_0e11_4033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4034 = { + 0x4034, pci_device_0e11_4034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4040 = { + 0x4040, pci_device_0e11_4040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4048 = { + 0x4048, pci_device_0e11_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4050 = { + 0x4050, pci_device_0e11_4050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4051 = { + 0x4051, pci_device_0e11_4051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4058 = { + 0x4058, pci_device_0e11_4058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4070 = { + 0x4070, pci_device_0e11_4070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4080 = { + 0x4080, pci_device_0e11_4080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4082 = { + 0x4082, pci_device_0e11_4082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4083 = { + 0x4083, pci_device_0e11_4083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4091 = { + 0x4091, pci_device_0e11_4091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409a = { + 0x409a, pci_device_0e11_409a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409b = { + 0x409b, pci_device_0e11_409b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409c = { + 0x409c, pci_device_0e11_409c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409d = { + 0x409d, pci_device_0e11_409d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b200 = { + 0xb200, pci_device_0e11_b200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b203 = { + 0xb203, pci_device_0e11_b203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b204 = { + 0xb204, pci_device_0e11_b204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0031 = { + 0x0031, pci_device_1000_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0032 = { + 0x0032, pci_device_1000_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0033 = { + 0x0033, pci_device_1000_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0041 = { + 0x0041, pci_device_1000_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0050 = { + 0x0050, pci_device_1000_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0054 = { + 0x0054, pci_device_1000_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0056 = { + 0x0056, pci_device_1000_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0058 = { + 0x0058, pci_device_1000_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005a = { + 0x005a, pci_device_1000_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005c = { + 0x005c, pci_device_1000_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005e = { + 0x005e, pci_device_1000_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0060 = { + 0x0060, pci_device_1000_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0407 = { + 0x0407, pci_device_1000_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0408 = { + 0x0408, pci_device_1000_0408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0409 = { + 0x0409, pci_device_1000_0409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0640 = { + 0x0640, pci_device_1000_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0642 = { + 0x0642, pci_device_1000_0642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0646 = { + 0x0646, pci_device_1000_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0804 = { + 0x0804, pci_device_1000_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0805 = { + 0x0805, pci_device_1000_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0806 = { + 0x0806, pci_device_1000_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0807 = { + 0x0807, pci_device_1000_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_3150 = { + 0x3150, pci_device_1002_3150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3152 = { + 0x3152, pci_device_1002_3152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3154 = { + 0x3154, pci_device_1002_3154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e50 = { + 0x3e50, pci_device_1002_3e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e54 = { + 0x3e54, pci_device_1002_3e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e70 = { + 0x3e70, pci_device_1002_3e70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4136 = { + 0x4136, pci_device_1002_4136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4137 = { + 0x4137, pci_device_1002_4137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4148 = { + 0x4148, pci_device_1002_4148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4149 = { + 0x4149, pci_device_1002_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414a = { + 0x414a, pci_device_1002_414a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414b = { + 0x414b, pci_device_1002_414b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4150 = { + 0x4150, pci_device_1002_4150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4151 = { + 0x4151, pci_device_1002_4151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4152 = { + 0x4152, pci_device_1002_4152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4153 = { + 0x4153, pci_device_1002_4153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4154 = { + 0x4154, pci_device_1002_4154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4155 = { + 0x4155, pci_device_1002_4155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4156 = { + 0x4156, pci_device_1002_4156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4157 = { + 0x4157, pci_device_1002_4157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4164 = { + 0x4164, pci_device_1002_4164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4165 = { + 0x4165, pci_device_1002_4165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4166 = { + 0x4166, pci_device_1002_4166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4168 = { + 0x4168, pci_device_1002_4168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4170 = { + 0x4170, pci_device_1002_4170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4171 = { + 0x4171, pci_device_1002_4171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4172 = { + 0x4172, pci_device_1002_4172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4173 = { + 0x4173, pci_device_1002_4173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4237 = { + 0x4237, pci_device_1002_4237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4243 = { + 0x4243, pci_device_1002_4243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4341 = { + 0x4341, pci_device_1002_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4345 = { + 0x4345, pci_device_1002_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4347 = { + 0x4347, pci_device_1002_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4348 = { + 0x4348, pci_device_1002_4348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4349 = { + 0x4349, pci_device_1002_4349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_434d = { + 0x434d, pci_device_1002_434d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_434d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4353 = { + 0x4353, pci_device_1002_4353, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4353, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4363 = { + 0x4363, pci_device_1002_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_436e = { + 0x436e, pci_device_1002_436e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_436e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4370 = { + 0x4370, pci_device_1002_4370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4371 = { + 0x4371, pci_device_1002_4371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4372 = { + 0x4372, pci_device_1002_4372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4373 = { + 0x4373, pci_device_1002_4373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4374 = { + 0x4374, pci_device_1002_4374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4375 = { + 0x4375, pci_device_1002_4375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4376 = { + 0x4376, pci_device_1002_4376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4377 = { + 0x4377, pci_device_1002_4377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4378 = { + 0x4378, pci_device_1002_4378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4379 = { + 0x4379, pci_device_1002_4379, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4379, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437a = { + 0x437a, pci_device_1002_437a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4437 = { + 0x4437, pci_device_1002_4437, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4437, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a48 = { + 0x4a48, pci_device_1002_4a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a49 = { + 0x4a49, pci_device_1002_4a49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4a = { + 0x4a4a, pci_device_1002_4a4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4b = { + 0x4a4b, pci_device_1002_4a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4c = { + 0x4a4c, pci_device_1002_4a4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4d = { + 0x4a4d, pci_device_1002_4a4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4e = { + 0x4a4e, pci_device_1002_4a4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a50 = { + 0x4a50, pci_device_1002_4a50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a70 = { + 0x4a70, pci_device_1002_4a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b49 = { + 0x4b49, pci_device_1002_4b49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4b = { + 0x4b4b, pci_device_1002_4b4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4c = { + 0x4b4c, pci_device_1002_4b4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b69 = { + 0x4b69, pci_device_1002_4b69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6b = { + 0x4b6b, pci_device_1002_4b6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6c = { + 0x4b6c, pci_device_1002_4b6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c6e = { + 0x4c6e, pci_device_1002_4c6e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c6e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e48 = { + 0x4e48, pci_device_1002_4e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e49 = { + 0x4e49, pci_device_1002_4e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4a = { + 0x4e4a, pci_device_1002_4e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4b = { + 0x4e4b, pci_device_1002_4e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e50 = { + 0x4e50, pci_device_1002_4e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e51 = { + 0x4e51, pci_device_1002_4e51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e52 = { + 0x4e52, pci_device_1002_4e52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e53 = { + 0x4e53, pci_device_1002_4e53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e54 = { + 0x4e54, pci_device_1002_4e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e56 = { + 0x4e56, pci_device_1002_4e56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e68 = { + 0x4e68, pci_device_1002_4e68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e69 = { + 0x4e69, pci_device_1002_4e69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e6a = { + 0x4e6a, pci_device_1002_4e6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e71 = { + 0x4e71, pci_device_1002_4e71, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e71, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5154 = { + 0x5154, pci_device_1002_5154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5155 = { + 0x5155, pci_device_1002_5155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515e = { + 0x515e, pci_device_1002_515e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5460 = { + 0x5460, pci_device_1002_5460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5464 = { + 0x5464, pci_device_1002_5464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5548 = { + 0x5548, pci_device_1002_5548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5549 = { + 0x5549, pci_device_1002_5549, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5549, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554a = { + 0x554a, pci_device_1002_554a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554b = { + 0x554b, pci_device_1002_554b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554d = { + 0x554d, pci_device_1002_554d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554f = { + 0x554f, pci_device_1002_554f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5550 = { + 0x5550, pci_device_1002_5550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5551 = { + 0x5551, pci_device_1002_5551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5552 = { + 0x5552, pci_device_1002_5552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5554 = { + 0x5554, pci_device_1002_5554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556b = { + 0x556b, pci_device_1002_556b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556d = { + 0x556d, pci_device_1002_556d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556f = { + 0x556f, pci_device_1002_556f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564a = { + 0x564a, pci_device_1002_564a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564b = { + 0x564b, pci_device_1002_564b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5652 = { + 0x5652, pci_device_1002_5652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5653 = { + 0x5653, pci_device_1002_5653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5830 = { + 0x5830, pci_device_1002_5830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5831 = { + 0x5831, pci_device_1002_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5832 = { + 0x5832, pci_device_1002_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5833 = { + 0x5833, pci_device_1002_5833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5834 = { + 0x5834, pci_device_1002_5834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5835 = { + 0x5835, pci_device_1002_5835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5838 = { + 0x5838, pci_device_1002_5838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5940 = { + 0x5940, pci_device_1002_5940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5941 = { + 0x5941, pci_device_1002_5941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5944 = { + 0x5944, pci_device_1002_5944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5950 = { + 0x5950, pci_device_1002_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5951 = { + 0x5951, pci_device_1002_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5954 = { + 0x5954, pci_device_1002_5954, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5954, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5955 = { + 0x5955, pci_device_1002_5955, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5955, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5960 = { + 0x5960, pci_device_1002_5960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5961 = { + 0x5961, pci_device_1002_5961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5962 = { + 0x5962, pci_device_1002_5962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5964 = { + 0x5964, pci_device_1002_5964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5969 = { + 0x5969, pci_device_1002_5969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5974 = { + 0x5974, pci_device_1002_5974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5975 = { + 0x5975, pci_device_1002_5975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a34 = { + 0x5a34, pci_device_1002_5a34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a41 = { + 0x5a41, pci_device_1002_5a41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a42 = { + 0x5a42, pci_device_1002_5a42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a61 = { + 0x5a61, pci_device_1002_5a61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a62 = { + 0x5a62, pci_device_1002_5a62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b60 = { + 0x5b60, pci_device_1002_5b60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b62 = { + 0x5b62, pci_device_1002_5b62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b63 = { + 0x5b63, pci_device_1002_5b63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b64 = { + 0x5b64, pci_device_1002_5b64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b65 = { + 0x5b65, pci_device_1002_5b65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b70 = { + 0x5b70, pci_device_1002_5b70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b72 = { + 0x5b72, pci_device_1002_5b72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b73 = { + 0x5b73, pci_device_1002_5b73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b74 = { + 0x5b74, pci_device_1002_5b74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c61 = { + 0x5c61, pci_device_1002_5c61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c63 = { + 0x5c63, pci_device_1002_5c63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d44 = { + 0x5d44, pci_device_1002_5d44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d48 = { + 0x5d48, pci_device_1002_5d48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d49 = { + 0x5d49, pci_device_1002_5d49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4a = { + 0x5d4a, pci_device_1002_5d4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4d = { + 0x5d4d, pci_device_1002_5d4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d52 = { + 0x5d52, pci_device_1002_5d52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d57 = { + 0x5d57, pci_device_1002_5d57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6d = { + 0x5d6d, pci_device_1002_5d6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d72 = { + 0x5d72, pci_device_1002_5d72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d77 = { + 0x5d77, pci_device_1002_5d77, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d77, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e48 = { + 0x5e48, pci_device_1002_5e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e49 = { + 0x5e49, pci_device_1002_5e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4a = { + 0x5e4a, pci_device_1002_5e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4b = { + 0x5e4b, pci_device_1002_5e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4c = { + 0x5e4c, pci_device_1002_5e4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4d = { + 0x5e4d, pci_device_1002_5e4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4f = { + 0x5e4f, pci_device_1002_5e4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6b = { + 0x5e6b, pci_device_1002_5e6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6d = { + 0x5e6d, pci_device_1002_5e6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7010 = { + 0x7010, pci_device_1002_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7105 = { + 0x7105, pci_device_1002_7105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7109 = { + 0x7109, pci_device_1002_7109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7833 = { + 0x7833, pci_device_1002_7833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7834 = { + 0x7834, pci_device_1002_7834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7835 = { + 0x7835, pci_device_1002_7835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7838 = { + 0x7838, pci_device_1002_7838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7c37 = { + 0x7c37, pci_device_1002_7c37, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7c37, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab0 = { + 0xcab0, pci_device_1002_cab0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab2 = { + 0xcab2, pci_device_1002_cab2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab3 = { + 0xcab3, pci_device_1002_cab3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cbb2 = { + 0xcbb2, pci_device_1002_cbb2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cbb2, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0021 = { + 0x0021, pci_device_100b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0028 = { + 0x0028, pci_device_100b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002a = { + 0x002a, pci_device_100b_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002b = { + 0x002b, pci_device_100b_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002d = { + 0x002d, pci_device_100b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002e = { + 0x002e, pci_device_100b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002f = { + 0x002f, pci_device_100b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0030 = { + 0x0030, pci_device_100b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0035 = { + 0x0035, pci_device_100b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0510 = { + 0x0510, pci_device_100b_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0511 = { + 0x0511, pci_device_100b_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0515 = { + 0x0515, pci_device_100b_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0017 = { + 0x0017, pci_device_1011_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4000 = { + 0x4000, pci_device_1013_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0031 = { + 0x0031, pci_device_1014_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0037 = { + 0x0037, pci_device_1014_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003c = { + 0x003c, pci_device_1014_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0054 = { + 0x0054, pci_device_1014_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005e = { + 0x005e, pci_device_1014_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008b = { + 0x008b, pci_device_1014_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008e = { + 0x008e, pci_device_1014_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0091 = { + 0x0091, pci_device_1014_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_009f = { + 0x009f, pci_device_1014_009f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_009f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b8 = { + 0x00b8, pci_device_1014_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0104 = { + 0x0104, pci_device_1014_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_015e = { + 0x015e, pci_device_1014_015e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_015e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0160 = { + 0x0160, pci_device_1014_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_016e = { + 0x016e, pci_device_1014_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0170 = { + 0x0170, pci_device_1014_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_017d = { + 0x017d, pci_device_1014_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0180 = { + 0x0180, pci_device_1014_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0188 = { + 0x0188, pci_device_1014_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01c1 = { + 0x01c1, pci_device_1014_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01e6 = { + 0x01e6, pci_device_1014_01e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01ff = { + 0x01ff, pci_device_1014_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0219 = { + 0x0219, pci_device_1014_0219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021b = { + 0x021b, pci_device_1014_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021c = { + 0x021c, pci_device_1014_021c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0233 = { + 0x0233, pci_device_1014_0233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0266 = { + 0x0266, pci_device_1014_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0268 = { + 0x0268, pci_device_1014_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0269 = { + 0x0269, pci_device_1014_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_028c = { + 0x028c, pci_device_1014_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02a1 = { + 0x02a1, pci_device_1014_02a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0314 = { + 0x0314, pci_device_1014_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_3022 = { + 0x3022, pci_device_1014_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_4022 = { + 0x4022, pci_device_1014_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_0009 = { + 0x0009, pci_device_101e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2003 = { + 0x2003, pci_device_1022_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_208f = { + 0x208f, pci_device_1022_208f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_208f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700a = { + 0x700a, pci_device_1022_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700b = { + 0x700b, pci_device_1022_700b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7458 = { + 0x7458, pci_device_1022_7458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7459 = { + 0x7459, pci_device_1022_7459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_756b = { + 0x756b, pci_device_1022_756b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_756b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2100 = { + 0x2100, pci_device_1023_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2200 = { + 0x2200, pci_device_1023_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1671 = { + 0x1671, pci_device_1025_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1672 = { + 0x1672, pci_device_1025_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0009 = { + 0x0009, pci_device_1028_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000d = { + 0x000d, pci_device_1028_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0010 = { + 0x0010, pci_device_1028_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0011 = { + 0x0011, pci_device_1028_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0012 = { + 0x0012, pci_device_1028_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0013 = { + 0x0013, pci_device_1028_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0014 = { + 0x0014, pci_device_1028_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0015 = { + 0x0015, pci_device_1028_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0015, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_001f = { + 0x001f, pci_device_102a_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00c5 = { + 0x00c5, pci_device_102a_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00cf = { + 0x00cf, pci_device_102a_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00cf, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0100 = { + 0x0100, pci_device_102b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0528 = { + 0x0528, pci_device_102b_0528, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0528, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2537 = { + 0x2537, pci_device_102b_2537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2538 = { + 0x2538, pci_device_102b_2538, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2538, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_000a = { + 0x000a, pci_device_102f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0030 = { + 0x0030, pci_device_102f_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0031 = { + 0x0031, pci_device_102f_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0105 = { + 0x0105, pci_device_102f_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0106 = { + 0x0106, pci_device_102f_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0107 = { + 0x0107, pci_device_102f_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0108 = { + 0x0108, pci_device_102f_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0180 = { + 0x0180, pci_device_102f_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0181 = { + 0x0181, pci_device_102f_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0182 = { + 0x0182, pci_device_102f_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0182, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0000 = { + 0x0000, pci_device_1033_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0072 = { + 0x0072, pci_device_1033_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a5 = { + 0x00a5, pci_device_1033_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00ce = { + 0x00ce, pci_device_1033_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00df = { + 0x00df, pci_device_1033_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e7 = { + 0x00e7, pci_device_1033_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f2 = { + 0x00f2, pci_device_1033_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f3 = { + 0x00f3, pci_device_1033_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_010c = { + 0x010c, pci_device_1033_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_010c, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0003 = { + 0x0003, pci_device_1039_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0004 = { + 0x0004, pci_device_1039_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_000a = { + 0x000a, pci_device_1039_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0016 = { + 0x0016, pci_device_1039_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0180 = { + 0x0180, pci_device_1039_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0181 = { + 0x0181, pci_device_1039_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0182 = { + 0x0182, pci_device_1039_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0191 = { + 0x0191, pci_device_1039_0191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0550 = { + 0x0550, pci_device_1039_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0648 = { + 0x0648, pci_device_1039_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0655 = { + 0x0655, pci_device_1039_0655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0660 = { + 0x0660, pci_device_1039_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0661 = { + 0x0661, pci_device_1039_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0661, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0741 = { + 0x0741, pci_device_1039_0741, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0741, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0746 = { + 0x0746, pci_device_1039_0746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0755 = { + 0x0755, pci_device_1039_0755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0760 = { + 0x0760, pci_device_1039_0760, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0760, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0761 = { + 0x0761, pci_device_1039_0761, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0761, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0963 = { + 0x0963, pci_device_1039_0963, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0963, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0964 = { + 0x0964, pci_device_1039_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0965 = { + 0x0965, pci_device_1039_0965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6330 = { + 0x6330, pci_device_1039_6330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7019 = { + 0x7019, pci_device_1039_7019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1006 = { + 0x1006, pci_device_103c_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_100a = { + 0x100a, pci_device_103c_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1054 = { + 0x1054, pci_device_103c_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f0 = { + 0x10f0, pci_device_103c_10f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f1 = { + 0x10f1, pci_device_103c_10f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127c = { + 0x127c, pci_device_103c_127c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1291 = { + 0x1291, pci_device_103c_1291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12b4 = { + 0x12b4, pci_device_103c_12b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12fa = { + 0x12fa, pci_device_103c_12fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3080 = { + 0x3080, pci_device_103c_3080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3220 = { + 0x3220, pci_device_103c_3220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3230 = { + 0x3230, pci_device_103c_3230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3230, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4015 = { + 0x4015, pci_device_1043_4015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4057 = { + 0x4057, pci_device_1043_4057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8043 = { + 0x8043, pci_device_1043_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_807b = { + 0x807b, pci_device_1043_807b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_807b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80bb = { + 0x80bb, pci_device_1043_80bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80c5 = { + 0x80c5, pci_device_1043_80c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80df = { + 0x80df, pci_device_1043_80df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8187 = { + 0x8187, pci_device_1043_8187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8188 = { + 0x8188, pci_device_1043_8188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8188, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0c60 = { + 0x0c60, pci_device_1048_0c60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0c60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_8901 = { + 0x8901, pci_device_1048_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_8901, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0209 = { + 0x0209, pci_device_104a_0209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_020a = { + 0x020a, pci_device_104a_020a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_020a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021a = { + 0x021a, pci_device_104a_021a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021b = { + 0x021b, pci_device_104a_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0500 = { + 0x0500, pci_device_104a_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0564 = { + 0x0564, pci_device_104a_0564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_55cc = { + 0x55cc, pci_device_104a_55cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_55cc, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8025 = { + 0x8025, pci_device_104c_8025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8029 = { + 0x8029, pci_device_104c_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802b = { + 0x802b, pci_device_104c_802b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802e = { + 0x802e, pci_device_104c_802e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8031 = { + 0x8031, pci_device_104c_8031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8032 = { + 0x8032, pci_device_104c_8032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8033 = { + 0x8033, pci_device_104c_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8034 = { + 0x8034, pci_device_104c_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8035 = { + 0x8035, pci_device_104c_8035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8036 = { + 0x8036, pci_device_104c_8036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8038 = { + 0x8038, pci_device_104c_8038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8201 = { + 0x8201, pci_device_104c_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8204 = { + 0x8204, pci_device_104c_8204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8401 = { + 0x8401, pci_device_104c_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9000 = { + 0x9000, pci_device_104c_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9066 = { + 0x9066, pci_device_104c_9066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac44 = { + 0xac44, pci_device_104c_ac44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac46 = { + 0xac46, pci_device_104c_ac46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac47 = { + 0xac47, pci_device_104c_ac47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac4a = { + 0xac4a, pci_device_104c_ac4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac54 = { + 0xac54, pci_device_104c_ac54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8d = { + 0xac8d, pci_device_104c_ac8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8e = { + 0xac8e, pci_device_104c_ac8e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8f = { + 0xac8f, pci_device_104c_ac8f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8004 = { + 0x8004, pci_device_104d_8004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9921 = { + 0x9921, pci_device_1050_9921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9922 = { + 0x9922, pci_device_1050_9922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0008 = { + 0x0008, pci_device_1057_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0009 = { + 0x0009, pci_device_1057_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c1 = { + 0x18c1, pci_device_1057_18c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3410 = { + 0x3410, pci_device_1057_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5803 = { + 0x5803, pci_device_1057_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5806 = { + 0x5806, pci_device_1057_5806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5808 = { + 0x5808, pci_device_1057_5808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6405 = { + 0x6405, pci_device_1057_6405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6405, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3318 = { + 0x3318, pci_device_105a_3318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3319 = { + 0x3319, pci_device_105a_3319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3371 = { + 0x3371, pci_device_105a_3371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3373 = { + 0x3373, pci_device_105a_3373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3375 = { + 0x3375, pci_device_105a_3375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3515 = { + 0x3515, pci_device_105a_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3519 = { + 0x3519, pci_device_105a_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3571 = { + 0x3571, pci_device_105a_3571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3574 = { + 0x3574, pci_device_105a_3574, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3574, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3577 = { + 0x3577, pci_device_105a_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d17 = { + 0x3d17, pci_device_105a_3d17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d18 = { + 0x3d18, pci_device_105a_3d18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d73 = { + 0x3d73, pci_device_105a_3d73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d75 = { + 0x3d75, pci_device_105a_3d75, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d75, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6622 = { + 0x6622, pci_device_105a_6622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6624 = { + 0x6624, pci_device_105a_6624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6626 = { + 0x6626, pci_device_105a_6626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6629 = { + 0x6629, pci_device_105a_6629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8002 = { + 0x8002, pci_device_105a_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_0301 = { + 0x0301, pci_device_1067_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0304 = { + 0x0304, pci_device_1067_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0308 = { + 0x0308, pci_device_1067_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0020 = { + 0x0020, pci_device_1069_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_b166 = { + 0xb166, pci_device_1069_b166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_b166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba57 = { + 0xba57, pci_device_1069_ba57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba57, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000c = { + 0x000c, pci_device_106b_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0035 = { + 0x0035, pci_device_106b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0036 = { + 0x0036, pci_device_106b_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003b = { + 0x003b, pci_device_106b_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003e = { + 0x003e, pci_device_106b_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003f = { + 0x003f, pci_device_106b_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0040 = { + 0x0040, pci_device_106b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0041 = { + 0x0041, pci_device_106b_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0042 = { + 0x0042, pci_device_106b_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0043 = { + 0x0043, pci_device_106b_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0045 = { + 0x0045, pci_device_106b_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0046 = { + 0x0046, pci_device_106b_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0047 = { + 0x0047, pci_device_106b_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0048 = { + 0x0048, pci_device_106b_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0049 = { + 0x0049, pci_device_106b_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004b = { + 0x004b, pci_device_106b_004b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004c = { + 0x004c, pci_device_106b_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004f = { + 0x004f, pci_device_106b_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0050 = { + 0x0050, pci_device_106b_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0051 = { + 0x0051, pci_device_106b_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0052 = { + 0x0052, pci_device_106b_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0053 = { + 0x0053, pci_device_106b_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0054 = { + 0x0054, pci_device_106b_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0055 = { + 0x0055, pci_device_106b_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0058 = { + 0x0058, pci_device_106b_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0059 = { + 0x0059, pci_device_106b_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0066 = { + 0x0066, pci_device_106b_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0067 = { + 0x0067, pci_device_106b_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0068 = { + 0x0068, pci_device_106b_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0069 = { + 0x0069, pci_device_106b_0069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006a = { + 0x006a, pci_device_106b_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006b = { + 0x006b, pci_device_106b_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1071_8160 = { + 0x8160, pci_device_1071_8160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1071_8160, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2322 = { + 0x2322, pci_device_1077_2322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2422 = { + 0x2422, pci_device_1077_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2432 = { + 0x2432, pci_device_1077_2432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3010 = { + 0x3010, pci_device_1077_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3022 = { + 0x3022, pci_device_1077_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4010 = { + 0x4010, pci_device_1077_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4022 = { + 0x4022, pci_device_1077_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6312 = { + 0x6312, pci_device_1077_6312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6322 = { + 0x6322, pci_device_1077_6322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6322, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2134 = { + 0x2134, pci_device_107d_2134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2971 = { + 0x2971, pci_device_107d_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2971, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1648 = { + 0x1648, pci_device_108e_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8002 = { + 0x8002, pci_device_108e_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a801 = { + 0xa801, pci_device_108e_a801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_abba = { + 0xabba, pci_device_108e_abba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_abba, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_07a0 = { + 0x07a0, pci_device_1091_07a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_07a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_1091 = { + 0x1091, pci_device_1091_1091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_1091, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1310 = { + 0x1310, pci_device_1093_1310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14e0 = { + 0x14e0, pci_device_1093_14e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14f0 = { + 0x14f0, pci_device_1093_14f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_17d0 = { + 0x17d0, pci_device_1093_17d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_17d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1870 = { + 0x1870, pci_device_1093_1870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1880 = { + 0x1880, pci_device_1093_1880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_18b0 = { + 0x18b0, pci_device_1093_18b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_18b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2410 = { + 0x2410, pci_device_1093_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2890 = { + 0x2890, pci_device_1093_2890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a70 = { + 0x2a70, pci_device_1093_2a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a80 = { + 0x2a80, pci_device_1093_2a80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2c80 = { + 0x2c80, pci_device_1093_2c80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2c80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2ca0 = { + 0x2ca0, pci_device_1093_2ca0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2ca0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70b8 = { + 0x70b8, pci_device_1093_70b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0240 = { + 0x0240, pci_device_1095_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3114 = { + 0x3114, pci_device_1095_3114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3124 = { + 0x3124, pci_device_1095_3124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3132 = { + 0x3132, pci_device_1095_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3512 = { + 0x3512, pci_device_1095_3512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3512, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_032e = { + 0x032e, pci_device_109e_032e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_032e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_3052 = { + 0x3052, pci_device_10a5_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_100a = { + 0x100a, pci_device_10a9_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4001 = { + 0x4001, pci_device_10a9_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4002 = { + 0x4002, pci_device_10a9_4002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8010 = { + 0x8010, pci_device_10a9_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8018 = { + 0x8018, pci_device_10a9_8018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1042 = { + 0x1042, pci_device_10b5_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2540 = { + 0x2540, pci_device_10b5_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6540 = { + 0x6540, pci_device_10b5_6540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6541 = { + 0x6541, pci_device_10b5_6541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6542 = { + 0x6542, pci_device_10b5_6542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8111 = { + 0x8111, pci_device_10b5_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8114 = { + 0x8114, pci_device_10b5_8114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8516 = { + 0x8516, pci_device_10b5_8516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8532 = { + 0x8532, pci_device_10b5_8532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9056 = { + 0x9056, pci_device_10b5_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_bb04 = { + 0xbb04, pci_device_10b5_bb04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_bb04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0013 = { + 0x0013, pci_device_10b7_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0910 = { + 0x0910, pci_device_10b7_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1201 = { + 0x1201, pci_device_10b7_1201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1202 = { + 0x1202, pci_device_10b7_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1700 = { + 0x1700, pci_device_10b7_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6000 = { + 0x6000, pci_device_10b7_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6001 = { + 0x6001, pci_device_10b7_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7770 = { + 0x7770, pci_device_10b7_7770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_80eb = { + 0x80eb, pci_device_10b7_80eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_80eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9202 = { + 0x9202, pci_device_10b7_9202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9210 = { + 0x9210, pci_device_10b7_9210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990a = { + 0x990a, pci_device_10b7_990a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_2802 = { + 0x2802, pci_device_10b8_2802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_2802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b9_0101 = { + 0x0101, pci_device_10b9_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0780 = { + 0x0780, pci_device_10b9_0780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0782 = { + 0x0782, pci_device_10b9_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1573 = { + 0x1573, pci_device_10b9_1573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1672 = { + 0x1672, pci_device_10b9_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1689 = { + 0x1689, pci_device_10b9_1689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1695 = { + 0x1695, pci_device_10b9_1695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1695, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1697 = { + 0x1697, pci_device_10b9_1697, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1697, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3323 = { + 0x3323, pci_device_10b9_3323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5228 = { + 0x5228, pci_device_10b9_5228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5246 = { + 0x5246, pci_device_10b9_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524b = { + 0x524b, pci_device_10b9_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524c = { + 0x524c, pci_device_10b9_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524d = { + 0x524d, pci_device_10b9_524d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524e = { + 0x524e, pci_device_10b9_524e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5263 = { + 0x5263, pci_device_10b9_5263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5281 = { + 0x5281, pci_device_10b9_5281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5287 = { + 0x5287, pci_device_10b9_5287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5288 = { + 0x5288, pci_device_10b9_5288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5289 = { + 0x5289, pci_device_10b9_5289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5450 = { + 0x5450, pci_device_10b9_5450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5461 = { + 0x5461, pci_device_10b9_5461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0304 = { + 0x0304, pci_device_10ba_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0308 = { + 0x0308, pci_device_10ba_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_1002 = { + 0x1002, pci_device_10ba_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cc_0660 = { + 0x0660, pci_device_10cc_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cc_0661 = { + 0x0661, pci_device_10cc_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0661, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0431 = { + 0x0431, pci_device_10d9_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8626 = { + 0x8626, pci_device_10d9_8626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dd_0100 = { + 0x0100, pci_device_10dd_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dd_0100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0034 = { + 0x0034, pci_device_10de_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0035 = { + 0x0035, pci_device_10de_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0036 = { + 0x0036, pci_device_10de_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0037 = { + 0x0037, pci_device_10de_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0038 = { + 0x0038, pci_device_10de_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003a = { + 0x003a, pci_device_10de_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003b = { + 0x003b, pci_device_10de_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003c = { + 0x003c, pci_device_10de_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003d = { + 0x003d, pci_device_10de_003d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003e = { + 0x003e, pci_device_10de_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0040 = { + 0x0040, pci_device_10de_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0041 = { + 0x0041, pci_device_10de_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0042 = { + 0x0042, pci_device_10de_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0043 = { + 0x0043, pci_device_10de_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0045 = { + 0x0045, pci_device_10de_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0046 = { + 0x0046, pci_device_10de_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0048 = { + 0x0048, pci_device_10de_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0049 = { + 0x0049, pci_device_10de_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004e = { + 0x004e, pci_device_10de_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0050 = { + 0x0050, pci_device_10de_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0051 = { + 0x0051, pci_device_10de_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0052 = { + 0x0052, pci_device_10de_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0053 = { + 0x0053, pci_device_10de_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0054 = { + 0x0054, pci_device_10de_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0055 = { + 0x0055, pci_device_10de_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0056 = { + 0x0056, pci_device_10de_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0057 = { + 0x0057, pci_device_10de_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0058 = { + 0x0058, pci_device_10de_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0059 = { + 0x0059, pci_device_10de_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005a = { + 0x005a, pci_device_10de_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005b = { + 0x005b, pci_device_10de_005b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005c = { + 0x005c, pci_device_10de_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005d = { + 0x005d, pci_device_10de_005d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005e = { + 0x005e, pci_device_10de_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005f = { + 0x005f, pci_device_10de_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006c = { + 0x006c, pci_device_10de_006c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006d = { + 0x006d, pci_device_10de_006d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0080 = { + 0x0080, pci_device_10de_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0084 = { + 0x0084, pci_device_10de_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0085 = { + 0x0085, pci_device_10de_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0086 = { + 0x0086, pci_device_10de_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0087 = { + 0x0087, pci_device_10de_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0088 = { + 0x0088, pci_device_10de_0088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008a = { + 0x008a, pci_device_10de_008a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008b = { + 0x008b, pci_device_10de_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008c = { + 0x008c, pci_device_10de_008c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008e = { + 0x008e, pci_device_10de_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0091 = { + 0x0091, pci_device_10de_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0092 = { + 0x0092, pci_device_10de_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0099 = { + 0x0099, pci_device_10de_0099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_009d = { + 0x009d, pci_device_10de_009d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_009d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c0 = { + 0x00c0, pci_device_10de_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c1 = { + 0x00c1, pci_device_10de_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c2 = { + 0x00c2, pci_device_10de_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c3 = { + 0x00c3, pci_device_10de_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c8 = { + 0x00c8, pci_device_10de_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c9 = { + 0x00c9, pci_device_10de_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cc = { + 0x00cc, pci_device_10de_00cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cd = { + 0x00cd, pci_device_10de_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ce = { + 0x00ce, pci_device_10de_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d0 = { + 0x00d0, pci_device_10de_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d1 = { + 0x00d1, pci_device_10de_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d2 = { + 0x00d2, pci_device_10de_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d3 = { + 0x00d3, pci_device_10de_00d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d4 = { + 0x00d4, pci_device_10de_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d5 = { + 0x00d5, pci_device_10de_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d6 = { + 0x00d6, pci_device_10de_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d7 = { + 0x00d7, pci_device_10de_00d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d8 = { + 0x00d8, pci_device_10de_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d9 = { + 0x00d9, pci_device_10de_00d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00da = { + 0x00da, pci_device_10de_00da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00dd = { + 0x00dd, pci_device_10de_00dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00df = { + 0x00df, pci_device_10de_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e0 = { + 0x00e0, pci_device_10de_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e1 = { + 0x00e1, pci_device_10de_00e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e2 = { + 0x00e2, pci_device_10de_00e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e3 = { + 0x00e3, pci_device_10de_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e4 = { + 0x00e4, pci_device_10de_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e5 = { + 0x00e5, pci_device_10de_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e6 = { + 0x00e6, pci_device_10de_00e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e7 = { + 0x00e7, pci_device_10de_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e8 = { + 0x00e8, pci_device_10de_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ea = { + 0x00ea, pci_device_10de_00ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ed = { + 0x00ed, pci_device_10de_00ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ee = { + 0x00ee, pci_device_10de_00ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f0 = { + 0x00f0, pci_device_10de_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f1 = { + 0x00f1, pci_device_10de_00f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f2 = { + 0x00f2, pci_device_10de_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f3 = { + 0x00f3, pci_device_10de_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f8 = { + 0x00f8, pci_device_10de_00f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f9 = { + 0x00f9, pci_device_10de_00f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fa = { + 0x00fa, pci_device_10de_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fb = { + 0x00fb, pci_device_10de_00fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fc = { + 0x00fc, pci_device_10de_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fd = { + 0x00fd, pci_device_10de_00fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fe = { + 0x00fe, pci_device_10de_00fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ff = { + 0x00ff, pci_device_10de_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0140 = { + 0x0140, pci_device_10de_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0141 = { + 0x0141, pci_device_10de_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0142 = { + 0x0142, pci_device_10de_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0144 = { + 0x0144, pci_device_10de_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0145 = { + 0x0145, pci_device_10de_0145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0146 = { + 0x0146, pci_device_10de_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0147 = { + 0x0147, pci_device_10de_0147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0148 = { + 0x0148, pci_device_10de_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0149 = { + 0x0149, pci_device_10de_0149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014e = { + 0x014e, pci_device_10de_014e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014f = { + 0x014f, pci_device_10de_014f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0160 = { + 0x0160, pci_device_10de_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0161 = { + 0x0161, pci_device_10de_0161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0162 = { + 0x0162, pci_device_10de_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0163 = { + 0x0163, pci_device_10de_0163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0164 = { + 0x0164, pci_device_10de_0164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0165 = { + 0x0165, pci_device_10de_0165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0166 = { + 0x0166, pci_device_10de_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0167 = { + 0x0167, pci_device_10de_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0168 = { + 0x0168, pci_device_10de_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0169 = { + 0x0169, pci_device_10de_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0177 = { + 0x0177, pci_device_10de_0177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017d = { + 0x017d, pci_device_10de_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0185 = { + 0x0185, pci_device_10de_0185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0186 = { + 0x0186, pci_device_10de_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0187 = { + 0x0187, pci_device_10de_0187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018c = { + 0x018c, pci_device_10de_018c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018d = { + 0x018d, pci_device_10de_018d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b0 = { + 0x01b0, pci_device_10de_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e0 = { + 0x01e0, pci_device_10de_01e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ea = { + 0x01ea, pci_device_10de_01ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01eb = { + 0x01eb, pci_device_10de_01eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ec = { + 0x01ec, pci_device_10de_01ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ed = { + 0x01ed, pci_device_10de_01ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ee = { + 0x01ee, pci_device_10de_01ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ef = { + 0x01ef, pci_device_10de_01ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0211 = { + 0x0211, pci_device_10de_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0212 = { + 0x0212, pci_device_10de_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0215 = { + 0x0215, pci_device_10de_0215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0221 = { + 0x0221, pci_device_10de_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0240 = { + 0x0240, pci_device_10de_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0241 = { + 0x0241, pci_device_10de_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0242 = { + 0x0242, pci_device_10de_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0243 = { + 0x0243, pci_device_10de_0243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0244 = { + 0x0244, pci_device_10de_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0245 = { + 0x0245, pci_device_10de_0245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0246 = { + 0x0246, pci_device_10de_0246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0247 = { + 0x0247, pci_device_10de_0247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0248 = { + 0x0248, pci_device_10de_0248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0249 = { + 0x0249, pci_device_10de_0249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024a = { + 0x024a, pci_device_10de_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024b = { + 0x024b, pci_device_10de_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024c = { + 0x024c, pci_device_10de_024c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024d = { + 0x024d, pci_device_10de_024d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024e = { + 0x024e, pci_device_10de_024e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024f = { + 0x024f, pci_device_10de_024f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0260 = { + 0x0260, pci_device_10de_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0261 = { + 0x0261, pci_device_10de_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0262 = { + 0x0262, pci_device_10de_0262, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0262, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0263 = { + 0x0263, pci_device_10de_0263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0264 = { + 0x0264, pci_device_10de_0264, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0264, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0265 = { + 0x0265, pci_device_10de_0265, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0265, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0266 = { + 0x0266, pci_device_10de_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0267 = { + 0x0267, pci_device_10de_0267, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0267, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0268 = { + 0x0268, pci_device_10de_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0269 = { + 0x0269, pci_device_10de_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026a = { + 0x026a, pci_device_10de_026a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026b = { + 0x026b, pci_device_10de_026b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026c = { + 0x026c, pci_device_10de_026c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026d = { + 0x026d, pci_device_10de_026d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026e = { + 0x026e, pci_device_10de_026e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026f = { + 0x026f, pci_device_10de_026f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0270 = { + 0x0270, pci_device_10de_0270, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0270, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0271 = { + 0x0271, pci_device_10de_0271, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0271, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0272 = { + 0x0272, pci_device_10de_0272, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0272, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027e = { + 0x027e, pci_device_10de_027e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027f = { + 0x027f, pci_device_10de_027f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0286 = { + 0x0286, pci_device_10de_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_028c = { + 0x028c, pci_device_10de_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02a0 = { + 0x02a0, pci_device_10de_02a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f0 = { + 0x02f0, pci_device_10de_02f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f1 = { + 0x02f1, pci_device_10de_02f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f2 = { + 0x02f2, pci_device_10de_02f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f3 = { + 0x02f3, pci_device_10de_02f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f4 = { + 0x02f4, pci_device_10de_02f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f5 = { + 0x02f5, pci_device_10de_02f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f6 = { + 0x02f6, pci_device_10de_02f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f7 = { + 0x02f7, pci_device_10de_02f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f8 = { + 0x02f8, pci_device_10de_02f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f9 = { + 0x02f9, pci_device_10de_02f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fa = { + 0x02fa, pci_device_10de_02fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fb = { + 0x02fb, pci_device_10de_02fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fc = { + 0x02fc, pci_device_10de_02fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fd = { + 0x02fd, pci_device_10de_02fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fe = { + 0x02fe, pci_device_10de_02fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02ff = { + 0x02ff, pci_device_10de_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0311 = { + 0x0311, pci_device_10de_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0312 = { + 0x0312, pci_device_10de_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0313 = { + 0x0313, pci_device_10de_0313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0314 = { + 0x0314, pci_device_10de_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0316 = { + 0x0316, pci_device_10de_0316, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0316, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0317 = { + 0x0317, pci_device_10de_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0317, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031a = { + 0x031a, pci_device_10de_031a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031b = { + 0x031b, pci_device_10de_031b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031c = { + 0x031c, pci_device_10de_031c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031d = { + 0x031d, pci_device_10de_031d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031e = { + 0x031e, pci_device_10de_031e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031f = { + 0x031f, pci_device_10de_031f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0320 = { + 0x0320, pci_device_10de_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0321 = { + 0x0321, pci_device_10de_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0322 = { + 0x0322, pci_device_10de_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0323 = { + 0x0323, pci_device_10de_0323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0324 = { + 0x0324, pci_device_10de_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0325 = { + 0x0325, pci_device_10de_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0326 = { + 0x0326, pci_device_10de_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0327 = { + 0x0327, pci_device_10de_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0328 = { + 0x0328, pci_device_10de_0328, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0328, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0329 = { + 0x0329, pci_device_10de_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032a = { + 0x032a, pci_device_10de_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032b = { + 0x032b, pci_device_10de_032b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032c = { + 0x032c, pci_device_10de_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032d = { + 0x032d, pci_device_10de_032d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032f = { + 0x032f, pci_device_10de_032f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0330 = { + 0x0330, pci_device_10de_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0331 = { + 0x0331, pci_device_10de_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0332 = { + 0x0332, pci_device_10de_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0333 = { + 0x0333, pci_device_10de_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0334 = { + 0x0334, pci_device_10de_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0338 = { + 0x0338, pci_device_10de_0338, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0338, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_033f = { + 0x033f, pci_device_10de_033f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_033f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0341 = { + 0x0341, pci_device_10de_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0342 = { + 0x0342, pci_device_10de_0342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0343 = { + 0x0343, pci_device_10de_0343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0344 = { + 0x0344, pci_device_10de_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0345 = { + 0x0345, pci_device_10de_0345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0347 = { + 0x0347, pci_device_10de_0347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0348 = { + 0x0348, pci_device_10de_0348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0349 = { + 0x0349, pci_device_10de_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034b = { + 0x034b, pci_device_10de_034b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034c = { + 0x034c, pci_device_10de_034c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034e = { + 0x034e, pci_device_10de_034e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034f = { + 0x034f, pci_device_10de_034f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0360 = { + 0x0360, pci_device_10de_0360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0361 = { + 0x0361, pci_device_10de_0361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0362 = { + 0x0362, pci_device_10de_0362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0363 = { + 0x0363, pci_device_10de_0363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0364 = { + 0x0364, pci_device_10de_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0365 = { + 0x0365, pci_device_10de_0365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0366 = { + 0x0366, pci_device_10de_0366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0367 = { + 0x0367, pci_device_10de_0367, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0367, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0368 = { + 0x0368, pci_device_10de_0368, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0368, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0369 = { + 0x0369, pci_device_10de_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036a = { + 0x036a, pci_device_10de_036a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036c = { + 0x036c, pci_device_10de_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036d = { + 0x036d, pci_device_10de_036d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036e = { + 0x036e, pci_device_10de_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0371 = { + 0x0371, pci_device_10de_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0372 = { + 0x0372, pci_device_10de_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0373 = { + 0x0373, pci_device_10de_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037a = { + 0x037a, pci_device_10de_037a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037e = { + 0x037e, pci_device_10de_037e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037f = { + 0x037f, pci_device_10de_037f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a1 = { + 0xf0a1, pci_device_10df_f0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a5 = { + 0xf0a5, pci_device_10df_f0a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0b5 = { + 0xf0b5, pci_device_10df_f0b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d1 = { + 0xf0d1, pci_device_10df_f0d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d5 = { + 0xf0d5, pci_device_10df_f0d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e1 = { + 0xf0e1, pci_device_10df_f0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e5 = { + 0xf0e5, pci_device_10df_f0e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0f5 = { + 0xf0f5, pci_device_10df_f0f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f701 = { + 0xf701, pci_device_10df_f701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f801 = { + 0xf801, pci_device_10df_f801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f901 = { + 0xf901, pci_device_10df_f901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f981 = { + 0xf981, pci_device_10df_f981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f982 = { + 0xf982, pci_device_10df_f982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fa00 = { + 0xfa00, pci_device_10df_fa00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fa00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fb00 = { + 0xfb00, pci_device_10df_fb00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fb00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc00 = { + 0xfc00, pci_device_10df_fc00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc10 = { + 0xfc10, pci_device_10df_fc10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc20 = { + 0xfc20, pci_device_10df_fc20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fd00 = { + 0xfd00, pci_device_10df_fd00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fd00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fe00 = { + 0xfe00, pci_device_10df_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_ff00 = { + 0xff00, pci_device_10df_ff00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_ff00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0148 = { + 0x0148, pci_device_10e3_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8260 = { + 0x8260, pci_device_10e3_8260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8261 = { + 0x8261, pci_device_10e3_8261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8261, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e4_8029 = { + 0x8029, pci_device_10e4_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e4_8029, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_1072 = { + 0x1072, pci_device_10e8_1072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_1072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_814c = { + 0x814c, pci_device_10e8_814c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_814c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_81e6 = { + 0x81e6, pci_device_10e8_81e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_81e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8291 = { + 0x8291, pci_device_10e8_8291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c4 = { + 0x82c4, pci_device_10e8_82c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c5 = { + 0x82c5, pci_device_10e8_82c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c6 = { + 0x82c6, pci_device_10e8_82c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c7 = { + 0x82c7, pci_device_10e8_82c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82ca = { + 0x82ca, pci_device_10e8_82ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82e2 = { + 0x82e2, pci_device_10e8_82e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8851 = { + 0x8851, pci_device_10e8_8851, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8851, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5252 = { + 0x5252, pci_device_10ea_5252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5252, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_0139 = { + 0x0139, pci_device_10ec_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8180 = { + 0x8180, pci_device_10ec_8180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_0314 = { + 0x0314, pci_device_10ee_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc6 = { + 0x3fc6, pci_device_10ee_3fc6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_8381 = { + 0x8381, pci_device_10ee_8381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_8381, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9502 = { + 0x9502, pci_device_1101_9502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9502, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0x0401 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0007 = { + 0x0007, pci_device_1102_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0008 = { + 0x0008, pci_device_1102_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_100a = { + 0x100a, pci_device_1102_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7005 = { + 0x7005, pci_device_1102_7005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0009 = { + 0x0009, pci_device_1103_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0009, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8401 = { + 0x8401, pci_device_1105_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8470 = { + 0x8470, pci_device_1105_8470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8471 = { + 0x8471, pci_device_1105_8471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8475 = { + 0x8475, pci_device_1105_8475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8476 = { + 0x8476, pci_device_1105_8476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8485 = { + 0x8485, pci_device_1105_8485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8486 = { + 0x8486, pci_device_1105_8486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8486, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0204 = { + 0x0204, pci_device_1106_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0238 = { + 0x0238, pci_device_1106_0238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0259 = { + 0x0259, pci_device_1106_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0269 = { + 0x0269, pci_device_1106_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0282 = { + 0x0282, pci_device_1106_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0290 = { + 0x0290, pci_device_1106_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0296 = { + 0x0296, pci_device_1106_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0308 = { + 0x0308, pci_device_1106_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0314 = { + 0x0314, pci_device_1106_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0591 = { + 0x0591, pci_device_1106_0591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1204 = { + 0x1204, pci_device_1106_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1208 = { + 0x1208, pci_device_1106_1208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1238 = { + 0x1238, pci_device_1106_1238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1258 = { + 0x1258, pci_device_1106_1258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1259 = { + 0x1259, pci_device_1106_1259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1269 = { + 0x1269, pci_device_1106_1269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1282 = { + 0x1282, pci_device_1106_1282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1290 = { + 0x1290, pci_device_1106_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1296 = { + 0x1296, pci_device_1106_1296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1308 = { + 0x1308, pci_device_1106_1308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1314 = { + 0x1314, pci_device_1106_1314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2204 = { + 0x2204, pci_device_1106_2204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2208 = { + 0x2208, pci_device_1106_2208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2238 = { + 0x2238, pci_device_1106_2238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2258 = { + 0x2258, pci_device_1106_2258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2259 = { + 0x2259, pci_device_1106_2259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2269 = { + 0x2269, pci_device_1106_2269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2282 = { + 0x2282, pci_device_1106_2282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2290 = { + 0x2290, pci_device_1106_2290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2296 = { + 0x2296, pci_device_1106_2296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2308 = { + 0x2308, pci_device_1106_2308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2314 = { + 0x2314, pci_device_1106_2314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287a = { + 0x287a, pci_device_1106_287a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287b = { + 0x287b, pci_device_1106_287b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287c = { + 0x287c, pci_device_1106_287c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287d = { + 0x287d, pci_device_1106_287d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287e = { + 0x287e, pci_device_1106_287e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3022 = { + 0x3022, pci_device_1106_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3053 = { + 0x3053, pci_device_1106_3053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3108 = { + 0x3108, pci_device_1106_3108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3113 = { + 0x3113, pci_device_1106_3113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3118 = { + 0x3118, pci_device_1106_3118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3119 = { + 0x3119, pci_device_1106_3119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3149 = { + 0x3149, pci_device_1106_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3164 = { + 0x3164, pci_device_1106_3164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3178 = { + 0x3178, pci_device_1106_3178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3188 = { + 0x3188, pci_device_1106_3188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3204 = { + 0x3204, pci_device_1106_3204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3205 = { + 0x3205, pci_device_1106_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3208 = { + 0x3208, pci_device_1106_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3213 = { + 0x3213, pci_device_1106_3213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3218 = { + 0x3218, pci_device_1106_3218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3227 = { + 0x3227, pci_device_1106_3227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3238 = { + 0x3238, pci_device_1106_3238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3249 = { + 0x3249, pci_device_1106_3249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3258 = { + 0x3258, pci_device_1106_3258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3259 = { + 0x3259, pci_device_1106_3259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3269 = { + 0x3269, pci_device_1106_3269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3282 = { + 0x3282, pci_device_1106_3282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3288 = { + 0x3288, pci_device_1106_3288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3290 = { + 0x3290, pci_device_1106_3290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3296 = { + 0x3296, pci_device_1106_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3337 = { + 0x3337, pci_device_1106_3337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3349 = { + 0x3349, pci_device_1106_3349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337a = { + 0x337a, pci_device_1106_337a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337b = { + 0x337b, pci_device_1106_337b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4149 = { + 0x4149, pci_device_1106_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4204 = { + 0x4204, pci_device_1106_4204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4208 = { + 0x4208, pci_device_1106_4208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4238 = { + 0x4238, pci_device_1106_4238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4258 = { + 0x4258, pci_device_1106_4258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4259 = { + 0x4259, pci_device_1106_4259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4269 = { + 0x4269, pci_device_1106_4269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4282 = { + 0x4282, pci_device_1106_4282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4290 = { + 0x4290, pci_device_1106_4290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4296 = { + 0x4296, pci_device_1106_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4308 = { + 0x4308, pci_device_1106_4308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4314 = { + 0x4314, pci_device_1106_4314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5208 = { + 0x5208, pci_device_1106_5208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5238 = { + 0x5238, pci_device_1106_5238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5290 = { + 0x5290, pci_device_1106_5290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5308 = { + 0x5308, pci_device_1106_5308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7204 = { + 0x7204, pci_device_1106_7204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7205 = { + 0x7205, pci_device_1106_7205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7208 = { + 0x7208, pci_device_1106_7208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7238 = { + 0x7238, pci_device_1106_7238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7258 = { + 0x7258, pci_device_1106_7258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7259 = { + 0x7259, pci_device_1106_7259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7269 = { + 0x7269, pci_device_1106_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7282 = { + 0x7282, pci_device_1106_7282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7290 = { + 0x7290, pci_device_1106_7290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7296 = { + 0x7296, pci_device_1106_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7308 = { + 0x7308, pci_device_1106_7308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7314 = { + 0x7314, pci_device_1106_7314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a208 = { + 0xa208, pci_device_1106_a208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a238 = { + 0xa238, pci_device_1106_a238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b113 = { + 0xb113, pci_device_1106_b113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b115 = { + 0xb115, pci_device_1106_b115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b188 = { + 0xb188, pci_device_1106_b188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b198 = { + 0xb198, pci_device_1106_b198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b213 = { + 0xb213, pci_device_1106_b213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c208 = { + 0xc208, pci_device_1106_c208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c238 = { + 0xc238, pci_device_1106_c238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d104 = { + 0xd104, pci_device_1106_d104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d208 = { + 0xd208, pci_device_1106_d208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d213 = { + 0xd213, pci_device_1106_d213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d238 = { + 0xd238, pci_device_1106_d238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e208 = { + 0xe208, pci_device_1106_e208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e238 = { + 0xe238, pci_device_1106_e238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f208 = { + 0xf208, pci_device_1106_f208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f238 = { + 0xf238, pci_device_1106_f238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f238, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0006 = { + 0x0006, pci_device_110a_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0015 = { + 0x0015, pci_device_110a_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_001d = { + 0x001d, pci_device_110a_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007b = { + 0x007b, pci_device_110a_007b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007c = { + 0x007c, pci_device_110a_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007d = { + 0x007d, pci_device_110a_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2101 = { + 0x2101, pci_device_110a_2101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2104 = { + 0x2104, pci_device_110a_2104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_3142 = { + 0x3142, pci_device_110a_3142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_3142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4021 = { + 0x4021, pci_device_110a_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4029 = { + 0x4029, pci_device_110a_4029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_d301 = { + 0xd301, pci_device_1113_d301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_d301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_ec02 = { + 0xec02, pci_device_1113_ec02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_ec02, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1114_0506 = { + 0x0506, pci_device_1114_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1114_0506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0010 = { + 0x0010, pci_device_1119_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0011 = { + 0x0011, pci_device_1119_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0012 = { + 0x0012, pci_device_1119_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0013 = { + 0x0013, pci_device_1119_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_02ff = { + 0x02ff, pci_device_1119_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_1203 = { + 0x1203, pci_device_111a_1203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_1203, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0004 = { + 0x0004, pci_device_111d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0005 = { + 0x0005, pci_device_111d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0008 = { + 0x0008, pci_device_112f_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5400 = { + 0x5400, pci_device_1131_5400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5402 = { + 0x5402, pci_device_1131_5402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7135 = { + 0x7135, pci_device_1131_7135, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7135, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_9730 = { + 0x9730, pci_device_1131_9730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_9730, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e006 = { + 0xe006, pci_device_1133_e006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e007 = { + 0xe007, pci_device_1133_e007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e008 = { + 0xe008, pci_device_1133_e008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e009 = { + 0xe009, pci_device_1133_e009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00a = { + 0xe00a, pci_device_1133_e00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00c = { + 0xe00c, pci_device_1133_e00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00d = { + 0xe00d, pci_device_1133_e00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00e = { + 0xe00e, pci_device_1133_e00e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e011 = { + 0xe011, pci_device_1133_e011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e013 = { + 0xe013, pci_device_1133_e013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e015 = { + 0xe015, pci_device_1133_e015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e016 = { + 0xe016, pci_device_1133_e016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e017 = { + 0xe017, pci_device_1133_e017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e019 = { + 0xe019, pci_device_1133_e019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01a = { + 0xe01a, pci_device_1133_e01a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01b = { + 0xe01b, pci_device_1133_e01b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01c = { + 0xe01c, pci_device_1133_e01c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01e = { + 0xe01e, pci_device_1133_e01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e020 = { + 0xe020, pci_device_1133_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e024 = { + 0xe024, pci_device_1133_e024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e028 = { + 0xe028, pci_device_1133_e028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02a = { + 0xe02a, pci_device_1133_e02a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02c = { + 0xe02c, pci_device_1133_e02c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1134_0002 = { + 0x0002, pci_device_1134_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f020 = { + 0xf020, pci_device_1145_f020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4500 = { + 0x4500, pci_device_1148_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9000 = { + 0x9000, pci_device_1148_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9843 = { + 0x9843, pci_device_1148_9843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9e00 = { + 0x9e00, pci_device_1148_9e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9e00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0013 = { + 0x0013, pci_device_114f_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0028 = { + 0x0028, pci_device_114f_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0029 = { + 0x0029, pci_device_114f_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0043 = { + 0x0043, pci_device_114f_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0044 = { + 0x0044, pci_device_114f_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0045 = { + 0x0045, pci_device_114f_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_004e = { + 0x004e, pci_device_114f_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b0 = { + 0x00b0, pci_device_114f_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b1 = { + 0x00b1, pci_device_114f_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c8 = { + 0x00c8, pci_device_114f_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c9 = { + 0x00c9, pci_device_114f_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00ca = { + 0x00ca, pci_device_114f_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00cb = { + 0x00cb, pci_device_114f_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d0 = { + 0x00d0, pci_device_114f_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d1 = { + 0x00d1, pci_device_114f_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_00d4 = { + 0x00d4, pci_device_115d_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0000 = { + 0x0000, pci_device_1166_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0006 = { + 0x0006, pci_device_1166_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0036 = { + 0x0036, pci_device_1166_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0101 = { + 0x0101, pci_device_1166_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0104 = { + 0x0104, pci_device_1166_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0110 = { + 0x0110, pci_device_1166_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0130 = { + 0x0130, pci_device_1166_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0132 = { + 0x0132, pci_device_1166_0132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0205 = { + 0x0205, pci_device_1166_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0214 = { + 0x0214, pci_device_1166_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0217 = { + 0x0217, pci_device_1166_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0223 = { + 0x0223, pci_device_1166_0223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0230 = { + 0x0230, pci_device_1166_0230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0234 = { + 0x0234, pci_device_1166_0234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0240 = { + 0x0240, pci_device_1166_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0241 = { + 0x0241, pci_device_1166_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0242 = { + 0x0242, pci_device_1166_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024a = { + 0x024a, pci_device_1166_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0102 = { + 0x0102, pci_device_1179_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_117c_0030 = { + 0x0030, pci_device_117c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_117c_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0511 = { + 0x0511, pci_device_1180_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0554 = { + 0x0554, pci_device_1180_0554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0575 = { + 0x0575, pci_device_1180_0575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0576 = { + 0x0576, pci_device_1180_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0592 = { + 0x0592, pci_device_1180_0592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0811 = { + 0x0811, pci_device_1180_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0822 = { + 0x0822, pci_device_1180_0822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0841 = { + 0x0841, pci_device_1180_0841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0852 = { + 0x0852, pci_device_1180_0852, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0852, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1025 = { + 0x1025, pci_device_1186_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1026 = { + 0x1026, pci_device_1186_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1043 = { + 0x1043, pci_device_1186_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1541 = { + 0x1541, pci_device_1186_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_2027 = { + 0x2027, pci_device_1186_2027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_2027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3203 = { + 0x3203, pci_device_1186_3203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3300 = { + 0x3300, pci_device_1186_3300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a03 = { + 0x3a03, pci_device_1186_3a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a04 = { + 0x3a04, pci_device_1186_3a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a05 = { + 0x3a05, pci_device_1186_3a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a07 = { + 0x3a07, pci_device_1186_3a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a08 = { + 0x3a08, pci_device_1186_3a08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a10 = { + 0x3a10, pci_device_1186_3a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a11 = { + 0x3a11, pci_device_1186_3a11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a12 = { + 0x3a12, pci_device_1186_3a12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a13 = { + 0x3a13, pci_device_1186_3a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a14 = { + 0x3a14, pci_device_1186_3a14, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a14, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a63 = { + 0x3a63, pci_device_1186_3a63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4300 = { + 0x4300, pci_device_1186_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4c00 = { + 0x4c00, pci_device_1186_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_8400 = { + 0x8400, pci_device_1186_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_8400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8060 = { + 0x8060, pci_device_1191_8060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8080 = { + 0x8080, pci_device_1191_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8081 = { + 0x8081, pci_device_1191_8081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_808a = { + 0x808a, pci_device_1191_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_808a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1197_010c = { + 0x010c, pci_device_1197_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1197_010c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_138f = { + 0x138f, pci_device_11ab_138f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_138f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa6 = { + 0x1fa6, pci_device_11ab_1fa6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa7 = { + 0x1fa7, pci_device_11ab_1fa7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1faa = { + 0x1faa, pci_device_11ab_1faa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1faa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4320 = { + 0x4320, pci_device_11ab_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4340 = { + 0x4340, pci_device_11ab_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4341 = { + 0x4341, pci_device_11ab_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4342 = { + 0x4342, pci_device_11ab_4342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4343 = { + 0x4343, pci_device_11ab_4343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4344 = { + 0x4344, pci_device_11ab_4344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4345 = { + 0x4345, pci_device_11ab_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4346 = { + 0x4346, pci_device_11ab_4346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4347 = { + 0x4347, pci_device_11ab_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4350 = { + 0x4350, pci_device_11ab_4350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4351 = { + 0x4351, pci_device_11ab_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4352 = { + 0x4352, pci_device_11ab_4352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4360 = { + 0x4360, pci_device_11ab_4360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4361 = { + 0x4361, pci_device_11ab_4361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4362 = { + 0x4362, pci_device_11ab_4362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4363 = { + 0x4363, pci_device_11ab_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5005 = { + 0x5005, pci_device_11ab_5005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5040 = { + 0x5040, pci_device_11ab_5040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5041 = { + 0x5041, pci_device_11ab_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5080 = { + 0x5080, pci_device_11ab_5080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5081 = { + 0x5081, pci_device_11ab_5081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6041 = { + 0x6041, pci_device_11ab_6041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6081 = { + 0x6081, pci_device_11ab_6081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6460 = { + 0x6460, pci_device_11ab_6460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6480 = { + 0x6480, pci_device_11ab_6480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11af_0001 = { + 0x0001, pci_device_11af_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11af_ee40 = { + 0xee40, pci_device_11af_ee40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_ee40, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bd_bede = { + 0xbede, pci_device_11bd_bede, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_bede, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048c = { + 0x048c, pci_device_11c1_048c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048f = { + 0x048f, pci_device_11c1_048f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_8110 = { + 0x8110, pci_device_11c1_8110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_8110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab10 = { + 0xab10, pci_device_11c1_ab10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab11 = { + 0xab11, pci_device_11c1_ab11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab20 = { + 0xab20, pci_device_11c1_ab20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab21 = { + 0xab21, pci_device_11c1_ab21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab30 = { + 0xab30, pci_device_11c1_ab30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab30, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1535 = { + 0x1535, pci_device_11d4_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_5340 = { + 0x5340, pci_device_11d4_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_5340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_0001 = { + 0x0001, pci_device_11e3_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000d = { + 0x000d, pci_device_11fe_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000e = { + 0x000e, pci_device_11fe_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000f = { + 0x000f, pci_device_11fe_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0801 = { + 0x0801, pci_device_11fe_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0802 = { + 0x0802, pci_device_11fe_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0803 = { + 0x0803, pci_device_11fe_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0805 = { + 0x0805, pci_device_11fe_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080c = { + 0x080c, pci_device_11fe_080c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080d = { + 0x080d, pci_device_11fe_080d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0812 = { + 0x0812, pci_device_11fe_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0903 = { + 0x0903, pci_device_11fe_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ff_0003 = { + 0x0003, pci_device_11ff_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ff_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7110 = { + 0x7110, pci_device_1217_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7112 = { + 0x7112, pci_device_1217_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7113 = { + 0x7113, pci_device_1217_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7114 = { + 0x7114, pci_device_1217_7114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7134 = { + 0x7134, pci_device_1217_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_71e2 = { + 0x71e2, pci_device_1217_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7212 = { + 0x7212, pci_device_1217_7212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7213 = { + 0x7213, pci_device_1217_7213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7223 = { + 0x7223, pci_device_1217_7223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7233 = { + 0x7233, pci_device_1217_7233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7233, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1227_0006 = { + 0x0006, pci_device_1227_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1227_0023 = { + 0x0023, pci_device_1227_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_1400 = { + 0x1400, pci_device_122d_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_6562 = { + 0x6562, pci_device_1242_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_656a = { + 0x656a, pci_device_1242_656a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_656a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2700 = { + 0x2700, pci_device_1244_2700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2900 = { + 0x2900, pci_device_1244_2900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2900, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a117 = { + 0xa117, pci_device_1259_a117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a117, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a120 = { + 0xa120, pci_device_1259_a120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0101 = { + 0x0101, pci_device_125c_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3872 = { + 0x3872, pci_device_1260_3872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3886 = { + 0x3886, pci_device_1260_3886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3890 = { + 0x3890, pci_device_1260_3890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_ffff = { + 0xffff, pci_device_1260_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_126c_1211 = { + 0x1211, pci_device_126c_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126c_126c = { + 0x126c, pci_device_126c_126c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_126c, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0501 = { + 0x0501, pci_device_126f_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0510 = { + 0x0510, pci_device_126f_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0730 = { + 0x0730, pci_device_126f_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1171 = { + 0x1171, pci_device_1274_1171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1278_0710 = { + 0x0710, pci_device_1278_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0710, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0060 = { + 0x0060, pci_device_1279_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0061 = { + 0x0061, pci_device_1279_0061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8211 = { + 0x8211, pci_device_1283_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8212 = { + 0x8212, pci_device_1283_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8872 = { + 0x8872, pci_device_1283_8872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12a3_8105 = { + 0x8105, pci_device_12a3_8105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12a3_8105, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_0000 = { + 0x0000, pci_device_12ab_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_0002 = { + 0x0002, pci_device_12ab_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_fff3 = { + 0xfff3, pci_device_12ab_fff3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_fff3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_ffff = { + 0xffff, pci_device_12ab_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_00fa = { + 0x00fa, pci_device_12ae_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_00fa, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c4_0001 = { + 0x0001, pci_device_12c4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0002 = { + 0x0002, pci_device_12c4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0003 = { + 0x0003, pci_device_12c4_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0004 = { + 0x0004, pci_device_12c4_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0005 = { + 0x0005, pci_device_12c4_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0006 = { + 0x0006, pci_device_12c4_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0007 = { + 0x0007, pci_device_12c4_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0008 = { + 0x0008, pci_device_12c4_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0009 = { + 0x0009, pci_device_12c4_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000a = { + 0x000a, pci_device_12c4_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000b = { + 0x000b, pci_device_12c4_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000c = { + 0x000c, pci_device_12c4_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000d = { + 0x000d, pci_device_12c4_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0100 = { + 0x0100, pci_device_12c4_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0201 = { + 0x0201, pci_device_12c4_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0202 = { + 0x0202, pci_device_12c4_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0300 = { + 0x0300, pci_device_12c4_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0301 = { + 0x0301, pci_device_12c4_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0302 = { + 0x0302, pci_device_12c4_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0310 = { + 0x0310, pci_device_12c4_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0311 = { + 0x0311, pci_device_12c4_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0312 = { + 0x0312, pci_device_12c4_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0320 = { + 0x0320, pci_device_12c4_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0321 = { + 0x0321, pci_device_12c4_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0322 = { + 0x0322, pci_device_12c4_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0330 = { + 0x0330, pci_device_12c4_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0331 = { + 0x0331, pci_device_12c4_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0332 = { + 0x0332, pci_device_12c4_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0332, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d4_0200 = { + 0x0200, pci_device_12d4_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d4_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d5_0003 = { + 0x0003, pci_device_12d5_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d5_1000 = { + 0x1000, pci_device_12d5_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_1000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d8_8150 = { + 0x8150, pci_device_12d8_8150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d8_8150, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d9_0002 = { + 0x0002, pci_device_12d9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0004 = { + 0x0004, pci_device_12d9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0005 = { + 0x0005, pci_device_12d9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12de_0200 = { + 0x0200, pci_device_12de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12de_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12fb_0001 = { + 0x0001, pci_device_12fb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_00f5 = { + 0x00f5, pci_device_12fb_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_02ad = { + 0x02ad, pci_device_12fb_02ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_02ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_2adc = { + 0x2adc, pci_device_12fb_2adc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_2adc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3100 = { + 0x3100, pci_device_12fb_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3500 = { + 0x3500, pci_device_12fb_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_4d4f = { + 0x4d4f, pci_device_12fb_4d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_4d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_8120 = { + 0x8120, pci_device_12fb_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_da62 = { + 0xda62, pci_device_12fb_da62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_da62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_db62 = { + 0xdb62, pci_device_12fb_db62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_db62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dc62 = { + 0xdc62, pci_device_12fb_dc62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dc62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dd62 = { + 0xdd62, pci_device_12fb_dd62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dd62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_eddc = { + 0xeddc, pci_device_12fb_eddc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_eddc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_fa01 = { + 0xfa01, pci_device_12fb_fa01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_fa01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004d = { + 0x004d, pci_device_1307_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0052 = { + 0x0052, pci_device_1307_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0054 = { + 0x0054, pci_device_1307_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_005e = { + 0x005e, pci_device_1307_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_005e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_2850 = { + 0x2850, pci_device_1317_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_5120 = { + 0x5120, pci_device_1317_5120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_5120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8201 = { + 0x8201, pci_device_1317_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8211 = { + 0x8211, pci_device_1317_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_9511 = { + 0x9511, pci_device_1317_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2081 = { + 0x2081, pci_device_131f_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2081, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1331_0030 = { + 0x0030, pci_device_1331_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8200 = { + 0x8200, pci_device_1331_8200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8201 = { + 0x8201, pci_device_1331_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8202 = { + 0x8202, pci_device_1331_8202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8210 = { + 0x8210, pci_device_1331_8210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_5425 = { + 0x5425, pci_device_1332_5425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_6140 = { + 0x6140, pci_device_1332_6140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_6140, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_2189 = { + 0x2189, pci_device_134d_2189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_2486 = { + 0x2486, pci_device_134d_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_5101 = { + 0x5101, pci_device_135e_5101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_5101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1360_0101 = { + 0x0101, pci_device_1360_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0102 = { + 0x0102, pci_device_1360_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0103 = { + 0x0103, pci_device_1360_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0201 = { + 0x0201, pci_device_1360_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0202 = { + 0x0202, pci_device_1360_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0203 = { + 0x0203, pci_device_1360_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0301 = { + 0x0301, pci_device_1360_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0302 = { + 0x0302, pci_device_1360_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0302, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136b_ff01 = { + 0xff01, pci_device_136b_ff01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136b_ff01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1371_434e = { + 0x434e, pci_device_1371_434e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1371_434e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1374_0024 = { + 0x0024, pci_device_1374_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0025 = { + 0x0025, pci_device_1374_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0026 = { + 0x0026, pci_device_1374_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0027 = { + 0x0027, pci_device_1374_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0029 = { + 0x0029, pci_device_1374_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002a = { + 0x002a, pci_device_1374_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002b = { + 0x002b, pci_device_1374_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002c = { + 0x002c, pci_device_1374_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002d = { + 0x002d, pci_device_1374_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002e = { + 0x002e, pci_device_1374_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002f = { + 0x002f, pci_device_1374_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0030 = { + 0x0030, pci_device_1374_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0031 = { + 0x0031, pci_device_1374_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0032 = { + 0x0032, pci_device_1374_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0034 = { + 0x0034, pci_device_1374_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0035 = { + 0x0035, pci_device_1374_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0036 = { + 0x0036, pci_device_1374_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0037 = { + 0x0037, pci_device_1374_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0038 = { + 0x0038, pci_device_1374_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0039 = { + 0x0039, pci_device_1374_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_003a = { + 0x003a, pci_device_1374_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_003a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_137a_0001 = { + 0x0001, pci_device_137a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_137a_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1382_0001 = { + 0x0001, pci_device_1382_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2008 = { + 0x2008, pci_device_1382_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2088 = { + 0x2088, pci_device_1382_2088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_20c8 = { + 0x20c8, pci_device_1382_20c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_20c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4008 = { + 0x4008, pci_device_1382_4008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4010 = { + 0x4010, pci_device_1382_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4048 = { + 0x4048, pci_device_1382_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4088 = { + 0x4088, pci_device_1382_4088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4248 = { + 0x4248, pci_device_1382_4248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4248, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_0013 = { + 0x0013, pci_device_1385_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_311a = { + 0x311a, pci_device_1385_311a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_311a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4105 = { + 0x4105, pci_device_1385_4105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4400 = { + 0x4400, pci_device_1385_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4600 = { + 0x4600, pci_device_1385_4600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4601 = { + 0x4601, pci_device_1385_4601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4610 = { + 0x4610, pci_device_1385_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4800 = { + 0x4800, pci_device_1385_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4900 = { + 0x4900, pci_device_1385_4900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4a00 = { + 0x4a00, pci_device_1385_4a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4b00 = { + 0x4b00, pci_device_1385_4b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4c00 = { + 0x4c00, pci_device_1385_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4e00 = { + 0x4e00, pci_device_1385_4e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4f00 = { + 0x4f00, pci_device_1385_4f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6b00 = { + 0x6b00, pci_device_1385_6b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f004 = { + 0xf004, pci_device_1385_f004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1141 = { + 0x1141, pci_device_1393_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_16b8 = { + 0x16b8, pci_device_1397_16b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_16b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_001d = { + 0x001d, pci_device_13a3_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0020 = { + 0x0020, pci_device_13a3_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0026 = { + 0x0026, pci_device_13a3_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0026, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0152 = { + 0x0152, pci_device_13a8_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0154 = { + 0x0154, pci_device_13a8_0154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0020 = { + 0x0020, pci_device_13c0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0030 = { + 0x0030, pci_device_13c0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0210 = { + 0x0210, pci_device_13c0_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1003 = { + 0x1003, pci_device_13c1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c6_0520 = { + 0x0520, pci_device_13c6_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0620 = { + 0x0620, pci_device_13c6_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0820 = { + 0x0820, pci_device_13c6_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d0_2200 = { + 0x2200, pci_device_13d0_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab03 = { + 0xab03, pci_device_13d1_ab03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab08 = { + 0xab08, pci_device_13d1_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0200 = { + 0x0200, pci_device_13f0_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_1023 = { + 0x1023, pci_device_13f0_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_1023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0011 = { + 0x0011, pci_device_13f6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1240 = { + 0x1240, pci_device_13fe_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1600 = { + 0x1600, pci_device_13fe_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1733 = { + 0x1733, pci_device_13fe_1733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1752 = { + 0x1752, pci_device_13fe_1752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1754 = { + 0x1754, pci_device_13fe_1754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0110 = { + 0x0110, pci_device_1407_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0111 = { + 0x0111, pci_device_1407_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0120 = { + 0x0120, pci_device_1407_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0121 = { + 0x0121, pci_device_1407_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0180 = { + 0x0180, pci_device_1407_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0181 = { + 0x0181, pci_device_1407_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0220 = { + 0x0220, pci_device_1407_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0221 = { + 0x0221, pci_device_1407_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9510 = { + 0x9510, pci_device_1415_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9523 = { + 0x9523, pci_device_1415_9523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9523, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1420_8002 = { + 0x8002, pci_device_1420_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1420_8003 = { + 0x8003, pci_device_1420_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1425_000b = { + 0x000b, pci_device_1425_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1425_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_142e_4020 = { + 0x4020, pci_device_142e_4020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_142e_4337 = { + 0x4337, pci_device_142e_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4337, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1432_9130 = { + 0x9130, pci_device_1432_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1432_9130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8164 = { + 0x8164, pci_device_144a_8164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1458_0c11 = { + 0x0c11, pci_device_1458_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1458_e911 = { + 0xe911, pci_device_1458_e911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_e911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1461_a3ce = { + 0xa3ce, pci_device_1461_a3ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_a3ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1461_a3cf = { + 0xa3cf, pci_device_1461_a3cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_a3cf, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1462_5501 = { + 0x5501, pci_device_1462_5501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_5501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6819 = { + 0x6819, pci_device_1462_6819, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6819, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6825 = { + 0x6825, pci_device_1462_6825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_8725 = { + 0x8725, pci_device_1462_8725, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_8725, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9000 = { + 0x9000, pci_device_1462_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9110 = { + 0x9110, pci_device_1462_9110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9119 = { + 0x9119, pci_device_1462_9119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9591 = { + 0x9591, pci_device_1462_9591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9591, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_146c_1430 = { + 0x1430, pci_device_146c_1430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_146c_1430, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1497_1497 = { + 0x1497, pci_device_1497_1497, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1497_1497, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1498_21cd = { + 0x21cd, pci_device_1498_21cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_30c8 = { + 0x30c8, pci_device_1498_30c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_30c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_149d_0001 = { + 0x0001, pci_device_149d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_149d_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a505 = { + 0xa505, pci_device_14b9_a505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a506 = { + 0xa506, pci_device_14b9_a506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14c1_8043 = { + 0x8043, pci_device_14c1_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_8043, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d9_0010 = { + 0x0010, pci_device_14d9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d9_9000 = { + 0x9000, pci_device_14d9_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_9000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_0800 = { + 0x0800, pci_device_14e4_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0804 = { + 0x0804, pci_device_14e4_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0805 = { + 0x0805, pci_device_14e4_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0806 = { + 0x0806, pci_device_14e4_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080b = { + 0x080b, pci_device_14e4_080b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080f = { + 0x080f, pci_device_14e4_080f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0811 = { + 0x0811, pci_device_14e4_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0816 = { + 0x0816, pci_device_14e4_0816, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0816, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1600 = { + 0x1600, pci_device_14e4_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1601 = { + 0x1601, pci_device_14e4_1601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164a = { + 0x164a, pci_device_14e4_164a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164c = { + 0x164c, pci_device_14e4_164c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1654 = { + 0x1654, pci_device_14e4_1654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1659 = { + 0x1659, pci_device_14e4_1659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165e = { + 0x165e, pci_device_14e4_165e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1668 = { + 0x1668, pci_device_14e4_1668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166a = { + 0x166a, pci_device_14e4_166a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166b = { + 0x166b, pci_device_14e4_166b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166e = { + 0x166e, pci_device_14e4_166e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1677 = { + 0x1677, pci_device_14e4_1677, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1677, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1678 = { + 0x1678, pci_device_14e4_1678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167d = { + 0x167d, pci_device_14e4_167d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167e = { + 0x167e, pci_device_14e4_167e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169c = { + 0x169c, pci_device_14e4_169c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169d = { + 0x169d, pci_device_14e4_169d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16aa = { + 0x16aa, pci_device_14e4_16aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16ac = { + 0x16ac, pci_device_14e4_16ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16dd = { + 0x16dd, pci_device_14e4_16dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16f7 = { + 0x16f7, pci_device_14e4_16f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fd = { + 0x16fd, pci_device_14e4_16fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fe = { + 0x16fe, pci_device_14e4_16fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170c = { + 0x170c, pci_device_14e4_170c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170d = { + 0x170d, pci_device_14e4_170d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170e = { + 0x170e, pci_device_14e4_170e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3352 = { + 0x3352, pci_device_14e4_3352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3360 = { + 0x3360, pci_device_14e4_3360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4305 = { + 0x4305, pci_device_14e4_4305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4306 = { + 0x4306, pci_device_14e4_4306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4307 = { + 0x4307, pci_device_14e4_4307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4310 = { + 0x4310, pci_device_14e4_4310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4312 = { + 0x4312, pci_device_14e4_4312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4313 = { + 0x4313, pci_device_14e4_4313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4315 = { + 0x4315, pci_device_14e4_4315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4318 = { + 0x4318, pci_device_14e4_4318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4319 = { + 0x4319, pci_device_14e4_4319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4320 = { + 0x4320, pci_device_14e4_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4321 = { + 0x4321, pci_device_14e4_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4322 = { + 0x4322, pci_device_14e4_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4324 = { + 0x4324, pci_device_14e4_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4325 = { + 0x4325, pci_device_14e4_4325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4326 = { + 0x4326, pci_device_14e4_4326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4403 = { + 0x4403, pci_device_14e4_4403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4430 = { + 0x4430, pci_device_14e4_4430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4432 = { + 0x4432, pci_device_14e4_4432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4610 = { + 0x4610, pci_device_14e4_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4611 = { + 0x4611, pci_device_14e4_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4612 = { + 0x4612, pci_device_14e4_4612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4613 = { + 0x4613, pci_device_14e4_4613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4614 = { + 0x4614, pci_device_14e4_4614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4615 = { + 0x4615, pci_device_14e4_4615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4704 = { + 0x4704, pci_device_14e4_4704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4704, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4705 = { + 0x4705, pci_device_14e4_4705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4705, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4706 = { + 0x4706, pci_device_14e4_4706, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4706, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4707 = { + 0x4707, pci_device_14e4_4707, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4707, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4708 = { + 0x4708, pci_device_14e4_4708, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4708, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4710 = { + 0x4710, pci_device_14e4_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4711 = { + 0x4711, pci_device_14e4_4711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4712 = { + 0x4712, pci_device_14e4_4712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4713 = { + 0x4713, pci_device_14e4_4713, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4713, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4714 = { + 0x4714, pci_device_14e4_4714, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4714, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4715 = { + 0x4715, pci_device_14e4_4715, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4715, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4716 = { + 0x4716, pci_device_14e4_4716, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4716, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4717 = { + 0x4717, pci_device_14e4_4717, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4717, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4718 = { + 0x4718, pci_device_14e4_4718, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4718, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4720 = { + 0x4720, pci_device_14e4_4720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5365 = { + 0x5365, pci_device_14e4_5365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5600 = { + 0x5600, pci_device_14e4_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5605 = { + 0x5605, pci_device_14e4_5605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5615 = { + 0x5615, pci_device_14e4_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5625 = { + 0x5625, pci_device_14e4_5625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5645 = { + 0x5645, pci_device_14e4_5645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5670 = { + 0x5670, pci_device_14e4_5670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5680 = { + 0x5680, pci_device_14e4_5680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5690 = { + 0x5690, pci_device_14e4_5690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5691 = { + 0x5691, pci_device_14e4_5691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5692 = { + 0x5692, pci_device_14e4_5692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5822 = { + 0x5822, pci_device_14e4_5822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5823 = { + 0x5823, pci_device_14e4_5823, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5823, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5824 = { + 0x5824, pci_device_14e4_5824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5840 = { + 0x5840, pci_device_14e4_5840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5841 = { + 0x5841, pci_device_14e4_5841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5850 = { + 0x5850, pci_device_14e4_5850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5850, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab07 = { + 0xab07, pci_device_14ea_ab07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab08 = { + 0xab08, pci_device_14ea_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1085 = { + 0x1085, pci_device_14f1_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1620 = { + 0x1620, pci_device_14f1_1620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1621 = { + 0x1621, pci_device_14f1_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1622 = { + 0x1622, pci_device_14f1_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1811 = { + 0x1811, pci_device_14f1_1811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f02 = { + 0x2f02, pci_device_14f1_2f02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f11 = { + 0x2f11, pci_device_14f1_2f11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f20 = { + 0x2f20, pci_device_14f1_2f20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8800 = { + 0x8800, pci_device_14f1_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8801 = { + 0x8801, pci_device_14f1_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8802 = { + 0x8802, pci_device_14f1_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8804 = { + 0x8804, pci_device_14f1_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8811 = { + 0x8811, pci_device_14f1_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f2_0120 = { + 0x0120, pci_device_14f2_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0121 = { + 0x0121, pci_device_14f2_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0122 = { + 0x0122, pci_device_14f2_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0123 = { + 0x0123, pci_device_14f2_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0124 = { + 0x0124, pci_device_14f2_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0124, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f3_2030 = { + 0x2030, pci_device_14f3_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2050 = { + 0x2050, pci_device_14f3_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2060 = { + 0x2060, pci_device_14f3_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2060, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f8_2077 = { + 0x2077, pci_device_14f8_2077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f8_2077, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14fc_0000 = { + 0x0000, pci_device_14fc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0001 = { + 0x0001, pci_device_14fc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1500_1360 = { + 0x1360, pci_device_1500_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1500_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0800 = { + 0x0800, pci_device_1516_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0891 = { + 0x0891, pci_device_1516_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151c_0003 = { + 0x0003, pci_device_151c_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151c_4000 = { + 0x4000, pci_device_151c_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_0510 = { + 0x0510, pci_device_1524_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0520 = { + 0x0520, pci_device_1524_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0530 = { + 0x0530, pci_device_1524_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0550 = { + 0x0550, pci_device_1524_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0610 = { + 0x0610, pci_device_1524_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1411 = { + 0x1411, pci_device_1524_1411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1412 = { + 0x1412, pci_device_1524_1412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1421 = { + 0x1421, pci_device_1524_1421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1422 = { + 0x1422, pci_device_1524_1422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1422, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1538_0303 = { + 0x0303, pci_device_1538_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1538_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153b_1144 = { + 0x1144, pci_device_153b_1144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1147 = { + 0x1147, pci_device_153b_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1158 = { + 0x1158, pci_device_153b_1158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153f_0001 = { + 0x0001, pci_device_153f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1578_5615 = { + 0x5615, pci_device_1578_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1578_5615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0405 = { + 0x0405, pci_device_15ad_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0720 = { + 0x0720, pci_device_15ad_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0720, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a44 = { + 0x5a44, pci_device_15b3_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a45 = { + 0x5a45, pci_device_15b3_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a46 = { + 0x5a46, pci_device_15b3_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5e8d = { + 0x5e8d, pci_device_15b3_5e8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5e8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6274 = { + 0x6274, pci_device_15b3_6274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6278 = { + 0x6278, pci_device_15b3_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6279 = { + 0x6279, pci_device_15b3_6279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6282 = { + 0x6282, pci_device_15b3_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_1100 = { + 0x1100, pci_device_15bc_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2922 = { + 0x2922, pci_device_15bc_2922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2928 = { + 0x2928, pci_device_15bc_2928, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2928, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c5_8010 = { + 0x8010, pci_device_15c5_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c5_8010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e9_1841 = { + 0x1841, pci_device_15e9_1841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e9_1841, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15ec_3101 = { + 0x3101, pci_device_15ec_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ec_5102 = { + 0x5102, pci_device_15ec_5102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_5102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0610 = { + 0x0610, pci_device_1619_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0620 = { + 0x0620, pci_device_1619_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0640 = { + 0x0640, pci_device_1619_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_1610 = { + 0x1610, pci_device_1619_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_2610 = { + 0x2610, pci_device_1619_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_2610, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1626_8410 = { + 0x8410, pci_device_1626_8410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1626_8410, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1637_3874 = { + 0x3874, pci_device_1637_3874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1637_3874, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_3052 = { + 0x3052, pci_device_163c_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165f_1020 = { + 0x1020, pci_device_165f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165f_1020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1668_0100 = { + 0x0100, pci_device_1668_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1668_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_166d_0001 = { + 0x0001, pci_device_166d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_166d_0002 = { + 0x0002, pci_device_166d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1677_104e = { + 0x104e, pci_device_1677_104e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_104e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_12d7 = { + 0x12d7, pci_device_1677_12d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_12d7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167b_2102 = { + 0x2102, pci_device_167b_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167b_2102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1681_0010 = { + 0x0010, pci_device_1681_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1681_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1688_1170 = { + 0x1170, pci_device_1688_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1688_1170, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_168c_0007 = { + 0x0007, pci_device_168c_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0011 = { + 0x0011, pci_device_168c_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0012 = { + 0x0012, pci_device_168c_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0013 = { + 0x0013, pci_device_168c_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001a = { + 0x001a, pci_device_168c_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001b = { + 0x001b, pci_device_168c_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0020 = { + 0x0020, pci_device_168c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_1014 = { + 0x1014, pci_device_168c_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_1014, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_169c_0044 = { + 0x0044, pci_device_169c_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_169c_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1100 = { + 0x1100, pci_device_16ab_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1101 = { + 0x1101, pci_device_16ab_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_8501 = { + 0x8501, pci_device_16ab_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_8501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ae_1141 = { + 0x1141, pci_device_16ae_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ae_1141, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ca_0001 = { + 0x0001, pci_device_16ca_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ca_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e3_1e0f = { + 0x1e0f, pci_device_16e3_1e0f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e3_1e0f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_00ff = { + 0x00ff, pci_device_16ec_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_0116 = { + 0x0116, pci_device_16ec_0116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_0116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ed_1001 = { + 0x1001, pci_device_16ed_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ed_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16f4_8000 = { + 0x8000, pci_device_16f4_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16f4_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_170b_0100 = { + 0x0100, pci_device_170b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_170b_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1725_7174 = { + 0x7174, pci_device_1725_7174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1725_7174, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_172a_13c8 = { + 0x13c8, pci_device_172a_13c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_172a_13c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1737_0013 = { + 0x0013, pci_device_1737_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_0015 = { + 0x0015, pci_device_1737_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1032 = { + 0x1032, pci_device_1737_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1064 = { + 0x1064, pci_device_1737_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab08 = { + 0xab08, pci_device_1737_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab09 = { + 0xab09, pci_device_1737_ab09, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab09, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03e9 = { + 0x03e9, pci_device_173b_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03eb = { + 0x03eb, pci_device_173b_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03eb, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1799_6001 = { + 0x6001, pci_device_1799_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6020 = { + 0x6020, pci_device_1799_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6060 = { + 0x6060, pci_device_1799_6060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7000 = { + 0x7000, pci_device_1799_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7010 = { + 0x7010, pci_device_1799_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_179c_0557 = { + 0x0557, pci_device_179c_0557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_0566 = { + 0x0566, pci_device_179c_0566, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0566, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5031 = { + 0x5031, pci_device_179c_5031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5121 = { + 0x5121, pci_device_179c_5121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5211 = { + 0x5211, pci_device_179c_5211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5679 = { + 0x5679, pci_device_179c_5679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5679, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17a0_8033 = { + 0x8033, pci_device_17a0_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17a0_8034 = { + 0x8034, pci_device_17a0_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8034, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b3_ab08 = { + 0xab08, pci_device_17b3_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b3_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b4_0011 = { + 0x0011, pci_device_17b4_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b4_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d3_1110 = { + 0x1110, pci_device_17d3_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1120 = { + 0x1120, pci_device_17d3_1120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1130 = { + 0x1130, pci_device_17d3_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1160 = { + 0x1160, pci_device_17d3_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1210 = { + 0x1210, pci_device_17d3_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1220 = { + 0x1220, pci_device_17d3_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1230 = { + 0x1230, pci_device_17d3_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1260 = { + 0x1260, pci_device_17d3_1260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_5831 = { + 0x5831, pci_device_17d3_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_5832 = { + 0x5832, pci_device_17d3_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_5832, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17fe_2120 = { + 0x2120, pci_device_17fe_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17fe_2220 = { + 0x2220, pci_device_17fe_2220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1814_0101 = { + 0x0101, pci_device_1814_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0201 = { + 0x0201, pci_device_1814_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0401 = { + 0x0401, pci_device_1814_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1822_4e35 = { + 0x4e35, pci_device_1822_4e35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1822_4e35, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182d_3069 = { + 0x3069, pci_device_182d_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_3069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_182d_9790 = { + 0x9790, pci_device_182d_9790, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_9790, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_183b_08a7 = { + 0x08a7, pci_device_183b_08a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a8 = { + 0x08a8, pci_device_183b_08a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a9 = { + 0x08a9, pci_device_183b_08a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a9, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1864_2110 = { + 0x2110, pci_device_1864_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1864_2110, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1867_5a44 = { + 0x5a44, pci_device_1867_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a45 = { + 0x5a45, pci_device_1867_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a46 = { + 0x5a46, pci_device_1867_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6278 = { + 0x6278, pci_device_1867_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6282 = { + 0x6282, pci_device_1867_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ac_d500 = { + 0xd500, pci_device_18ac_d500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d810 = { + 0xd810, pci_device_18ac_d810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d820 = { + 0xd820, pci_device_18ac_d820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18b8_b001 = { + 0xb001, pci_device_18b8_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18b8_b001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ca_0020 = { + 0x0020, pci_device_18ca_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ca_0040 = { + 0x0040, pci_device_18ca_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18d2_3069 = { + 0x3069, pci_device_18d2_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18d2_3069, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18dd_4c6f = { + 0x4c6f, pci_device_18dd_4c6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18dd_4c6f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18e6_0001 = { + 0x0001, pci_device_18e6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18e6_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ec_c006 = { + 0xc006, pci_device_18ec_c006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c045 = { + 0xc045, pci_device_18ec_c045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c050 = { + 0xc050, pci_device_18ec_c050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c058 = { + 0xc058, pci_device_18ec_c058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c058, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f7_0001 = { + 0x0001, pci_device_18f7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0002 = { + 0x0002, pci_device_18f7_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0004 = { + 0x0004, pci_device_18f7_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0005 = { + 0x0005, pci_device_18f7_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_000a = { + 0x000a, pci_device_18f7_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1957_0080 = { + 0x0080, pci_device_1957_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0081 = { + 0x0081, pci_device_1957_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0082 = { + 0x0082, pci_device_1957_0082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0083 = { + 0x0083, pci_device_1957_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0084 = { + 0x0084, pci_device_1957_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0085 = { + 0x0085, pci_device_1957_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0086 = { + 0x0086, pci_device_1957_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0087 = { + 0x0087, pci_device_1957_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0087, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1966_1975 = { + 0x1975, pci_device_1966_1975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1966_1975, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_196a_0101 = { + 0x0101, pci_device_196a_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_196a_0102 = { + 0x0102, pci_device_196a_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_197b_2360 = { + 0x2360, pci_device_197b_2360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2363 = { + 0x2363, pci_device_197b_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2363, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1989_0001 = { + 0x0001, pci_device_1989_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1989_8001 = { + 0x8001, pci_device_1989_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ae_0520 = { + 0x0520, pci_device_19ae_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ae_0520, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc0_0300 = { + 0x0300, pci_device_1fc0_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc0_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc1_000d = { + 0x000d, pci_device_1fc1_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_000d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fce_0001 = { + 0x0001, pci_device_1fce_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fce_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0020 = { + 0x0020, pci_device_3388_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0022 = { + 0x0022, pci_device_3388_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0026 = { + 0x0026, pci_device_3388_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101a = { + 0x101a, pci_device_3388_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101b = { + 0x101b, pci_device_3388_101b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3842_c370 = { + 0xc370, pci_device_3842_c370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3842_c370, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000d = { + 0x000d, pci_device_3d3d_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0011 = { + 0x0011, pci_device_3d3d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0012 = { + 0x0012, pci_device_3d3d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0013 = { + 0x0013, pci_device_3d3d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0020 = { + 0x0020, pci_device_3d3d_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0022 = { + 0x0022, pci_device_3d3d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0024 = { + 0x0024, pci_device_3d3d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a1 = { + 0x07a1, pci_device_3d3d_07a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a2 = { + 0x07a2, pci_device_3d3d_07a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a3 = { + 0x07a3, pci_device_3d3d_07a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4144_0044 = { + 0x0044, pci_device_4144_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4144_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0016 = { + 0x0016, pci_device_4444_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_494f_10e8 = { + 0x10e8, pci_device_494f_10e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_494f_10e8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4c53_0000 = { + 0x0000, pci_device_4c53_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4c53_0001 = { + 0x0001, pci_device_4c53_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5168_0301 = { + 0x0301, pci_device_5168_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_544c_0350 = { + 0x0350, pci_device_544c_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_544c_0350, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5654_3132 = { + 0x3132, pci_device_5654_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5654_3132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0004 = { + 0x0004, pci_device_6666_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0101 = { + 0x0101, pci_device_6666_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_7063_2000 = { + 0x2000, pci_device_7063_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_3000 = { + 0x3000, pci_device_7063_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0309 = { + 0x0309, pci_device_8086_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_030d = { + 0x030d, pci_device_8086_030d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_030d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0326 = { + 0x0326, pci_device_8086_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0327 = { + 0x0327, pci_device_8086_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0329 = { + 0x0329, pci_device_8086_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032a = { + 0x032a, pci_device_8086_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032c = { + 0x032c, pci_device_8086_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0330 = { + 0x0330, pci_device_8086_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0331 = { + 0x0331, pci_device_8086_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0332 = { + 0x0332, pci_device_8086_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0333 = { + 0x0333, pci_device_8086_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0334 = { + 0x0334, pci_device_8086_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0335 = { + 0x0335, pci_device_8086_0335, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0335, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0336 = { + 0x0336, pci_device_8086_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0340 = { + 0x0340, pci_device_8086_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0341 = { + 0x0341, pci_device_8086_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0370 = { + 0x0370, pci_device_8086_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0371 = { + 0x0371, pci_device_8086_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0372 = { + 0x0372, pci_device_8086_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0373 = { + 0x0373, pci_device_8086_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0374 = { + 0x0374, pci_device_8086_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0500 = { + 0x0500, pci_device_8086_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0501 = { + 0x0501, pci_device_8086_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0502 = { + 0x0502, pci_device_8086_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0503 = { + 0x0503, pci_device_8086_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0510 = { + 0x0510, pci_device_8086_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0511 = { + 0x0511, pci_device_8086_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0512 = { + 0x0512, pci_device_8086_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0513 = { + 0x0513, pci_device_8086_0513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0514 = { + 0x0514, pci_device_8086_0514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0515 = { + 0x0515, pci_device_8086_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0516 = { + 0x0516, pci_device_8086_0516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0530 = { + 0x0530, pci_device_8086_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0531 = { + 0x0531, pci_device_8086_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0532 = { + 0x0532, pci_device_8086_0532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0533 = { + 0x0533, pci_device_8086_0533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0534 = { + 0x0534, pci_device_8086_0534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0535 = { + 0x0535, pci_device_8086_0535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0536 = { + 0x0536, pci_device_8086_0536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0537 = { + 0x0537, pci_device_8086_0537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_061f = { + 0x061f, pci_device_8086_061f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_061f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100a = { + 0x100a, pci_device_8086_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1013 = { + 0x1013, pci_device_8086_1013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1014 = { + 0x1014, pci_device_8086_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1016 = { + 0x1016, pci_device_8086_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1017 = { + 0x1017, pci_device_8086_1017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1018 = { + 0x1018, pci_device_8086_1018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1019 = { + 0x1019, pci_device_8086_1019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101a = { + 0x101a, pci_device_8086_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101d = { + 0x101d, pci_device_8086_101d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101e = { + 0x101e, pci_device_8086_101e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1026 = { + 0x1026, pci_device_8086_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1027 = { + 0x1027, pci_device_8086_1027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1028 = { + 0x1028, pci_device_8086_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1043 = { + 0x1043, pci_device_8086_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1048 = { + 0x1048, pci_device_8086_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1050 = { + 0x1050, pci_device_8086_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1051 = { + 0x1051, pci_device_8086_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1052 = { + 0x1052, pci_device_8086_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1053 = { + 0x1053, pci_device_8086_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105e = { + 0x105e, pci_device_8086_105e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105f = { + 0x105f, pci_device_8086_105f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1060 = { + 0x1060, pci_device_8086_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1064 = { + 0x1064, pci_device_8086_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1065 = { + 0x1065, pci_device_8086_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1066 = { + 0x1066, pci_device_8086_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1067 = { + 0x1067, pci_device_8086_1067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1068 = { + 0x1068, pci_device_8086_1068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1069 = { + 0x1069, pci_device_8086_1069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106a = { + 0x106a, pci_device_8086_106a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106b = { + 0x106b, pci_device_8086_106b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1075 = { + 0x1075, pci_device_8086_1075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1076 = { + 0x1076, pci_device_8086_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1077 = { + 0x1077, pci_device_8086_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1078 = { + 0x1078, pci_device_8086_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1079 = { + 0x1079, pci_device_8086_1079, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1079, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107a = { + 0x107a, pci_device_8086_107a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107b = { + 0x107b, pci_device_8086_107b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107c = { + 0x107c, pci_device_8086_107c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107d = { + 0x107d, pci_device_8086_107d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107e = { + 0x107e, pci_device_8086_107e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107f = { + 0x107f, pci_device_8086_107f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1080 = { + 0x1080, pci_device_8086_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1081 = { + 0x1081, pci_device_8086_1081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1082 = { + 0x1082, pci_device_8086_1082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1083 = { + 0x1083, pci_device_8086_1083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1084 = { + 0x1084, pci_device_8086_1084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1085 = { + 0x1085, pci_device_8086_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1086 = { + 0x1086, pci_device_8086_1086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1087 = { + 0x1087, pci_device_8086_1087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1089 = { + 0x1089, pci_device_8086_1089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108a = { + 0x108a, pci_device_8086_108a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108b = { + 0x108b, pci_device_8086_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108c = { + 0x108c, pci_device_8086_108c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1096 = { + 0x1096, pci_device_8086_1096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1097 = { + 0x1097, pci_device_8086_1097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1098 = { + 0x1098, pci_device_8086_1098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1099 = { + 0x1099, pci_device_8086_1099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109a = { + 0x109a, pci_device_8086_109a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1107 = { + 0x1107, pci_device_8086_1107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123e = { + 0x123e, pci_device_8086_123e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a38 = { + 0x1a38, pci_device_8086_1a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a48 = { + 0x1a48, pci_device_8086_1a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c1 = { + 0x24c1, pci_device_8086_24c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24ca = { + 0x24ca, pci_device_8086_24ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cc = { + 0x24cc, pci_device_8086_24cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d0 = { + 0x24d0, pci_device_8086_24d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d1 = { + 0x24d1, pci_device_8086_24d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d2 = { + 0x24d2, pci_device_8086_24d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d3 = { + 0x24d3, pci_device_8086_24d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d4 = { + 0x24d4, pci_device_8086_24d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d5 = { + 0x24d5, pci_device_8086_24d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d6 = { + 0x24d6, pci_device_8086_24d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d7 = { + 0x24d7, pci_device_8086_24d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24db = { + 0x24db, pci_device_8086_24db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dc = { + 0x24dc, pci_device_8086_24dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dd = { + 0x24dd, pci_device_8086_24dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24de = { + 0x24de, pci_device_8086_24de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24df = { + 0x24df, pci_device_8086_24df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_254c = { + 0x254c, pci_device_8086_254c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_254c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2550 = { + 0x2550, pci_device_8086_2550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2551 = { + 0x2551, pci_device_8086_2551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2552 = { + 0x2552, pci_device_8086_2552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2553 = { + 0x2553, pci_device_8086_2553, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2553, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2554 = { + 0x2554, pci_device_8086_2554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_255d = { + 0x255d, pci_device_8086_255d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_255d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2571 = { + 0x2571, pci_device_8086_2571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2573 = { + 0x2573, pci_device_8086_2573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2576 = { + 0x2576, pci_device_8086_2576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2578 = { + 0x2578, pci_device_8086_2578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2579 = { + 0x2579, pci_device_8086_2579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257b = { + 0x257b, pci_device_8086_257b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257e = { + 0x257e, pci_device_8086_257e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2580 = { + 0x2580, pci_device_8086_2580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2581 = { + 0x2581, pci_device_8086_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2582 = { + 0x2582, pci_device_8086_2582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2584 = { + 0x2584, pci_device_8086_2584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2585 = { + 0x2585, pci_device_8086_2585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2588 = { + 0x2588, pci_device_8086_2588, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2588, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2589 = { + 0x2589, pci_device_8086_2589, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2589, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_258a = { + 0x258a, pci_device_8086_258a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_258a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2590 = { + 0x2590, pci_device_8086_2590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2591 = { + 0x2591, pci_device_8086_2591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2592 = { + 0x2592, pci_device_8086_2592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a1 = { + 0x25a1, pci_device_8086_25a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a2 = { + 0x25a2, pci_device_8086_25a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a3 = { + 0x25a3, pci_device_8086_25a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a4 = { + 0x25a4, pci_device_8086_25a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a6 = { + 0x25a6, pci_device_8086_25a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a7 = { + 0x25a7, pci_device_8086_25a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a9 = { + 0x25a9, pci_device_8086_25a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25aa = { + 0x25aa, pci_device_8086_25aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ab = { + 0x25ab, pci_device_8086_25ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ac = { + 0x25ac, pci_device_8086_25ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ad = { + 0x25ad, pci_device_8086_25ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ae = { + 0x25ae, pci_device_8086_25ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25b0 = { + 0x25b0, pci_device_8086_25b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25c0 = { + 0x25c0, pci_device_8086_25c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d0 = { + 0x25d0, pci_device_8086_25d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d4 = { + 0x25d4, pci_device_8086_25d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d8 = { + 0x25d8, pci_device_8086_25d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e2 = { + 0x25e2, pci_device_8086_25e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e3 = { + 0x25e3, pci_device_8086_25e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e4 = { + 0x25e4, pci_device_8086_25e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e5 = { + 0x25e5, pci_device_8086_25e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e6 = { + 0x25e6, pci_device_8086_25e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e7 = { + 0x25e7, pci_device_8086_25e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e8 = { + 0x25e8, pci_device_8086_25e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f0 = { + 0x25f0, pci_device_8086_25f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f1 = { + 0x25f1, pci_device_8086_25f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f3 = { + 0x25f3, pci_device_8086_25f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f5 = { + 0x25f5, pci_device_8086_25f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f6 = { + 0x25f6, pci_device_8086_25f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f7 = { + 0x25f7, pci_device_8086_25f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f8 = { + 0x25f8, pci_device_8086_25f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f9 = { + 0x25f9, pci_device_8086_25f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25fa = { + 0x25fa, pci_device_8086_25fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2600 = { + 0x2600, pci_device_8086_2600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2601 = { + 0x2601, pci_device_8086_2601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2602 = { + 0x2602, pci_device_8086_2602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2603 = { + 0x2603, pci_device_8086_2603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2604 = { + 0x2604, pci_device_8086_2604, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2604, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2605 = { + 0x2605, pci_device_8086_2605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2606 = { + 0x2606, pci_device_8086_2606, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2606, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2607 = { + 0x2607, pci_device_8086_2607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2608 = { + 0x2608, pci_device_8086_2608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2609 = { + 0x2609, pci_device_8086_2609, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2609, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260a = { + 0x260a, pci_device_8086_260a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260c = { + 0x260c, pci_device_8086_260c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2610 = { + 0x2610, pci_device_8086_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2611 = { + 0x2611, pci_device_8086_2611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2612 = { + 0x2612, pci_device_8086_2612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2613 = { + 0x2613, pci_device_8086_2613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2614 = { + 0x2614, pci_device_8086_2614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2615 = { + 0x2615, pci_device_8086_2615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2617 = { + 0x2617, pci_device_8086_2617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2618 = { + 0x2618, pci_device_8086_2618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2619 = { + 0x2619, pci_device_8086_2619, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2619, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261a = { + 0x261a, pci_device_8086_261a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261b = { + 0x261b, pci_device_8086_261b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261c = { + 0x261c, pci_device_8086_261c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261d = { + 0x261d, pci_device_8086_261d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261e = { + 0x261e, pci_device_8086_261e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2620 = { + 0x2620, pci_device_8086_2620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2621 = { + 0x2621, pci_device_8086_2621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2622 = { + 0x2622, pci_device_8086_2622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2623 = { + 0x2623, pci_device_8086_2623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2624 = { + 0x2624, pci_device_8086_2624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2625 = { + 0x2625, pci_device_8086_2625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2626 = { + 0x2626, pci_device_8086_2626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2627 = { + 0x2627, pci_device_8086_2627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2640 = { + 0x2640, pci_device_8086_2640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2641 = { + 0x2641, pci_device_8086_2641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2642 = { + 0x2642, pci_device_8086_2642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2651 = { + 0x2651, pci_device_8086_2651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2652 = { + 0x2652, pci_device_8086_2652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2653 = { + 0x2653, pci_device_8086_2653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2658 = { + 0x2658, pci_device_8086_2658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2659 = { + 0x2659, pci_device_8086_2659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265a = { + 0x265a, pci_device_8086_265a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265b = { + 0x265b, pci_device_8086_265b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265c = { + 0x265c, pci_device_8086_265c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2660 = { + 0x2660, pci_device_8086_2660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2662 = { + 0x2662, pci_device_8086_2662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2664 = { + 0x2664, pci_device_8086_2664, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2664, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2666 = { + 0x2666, pci_device_8086_2666, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2666, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2668 = { + 0x2668, pci_device_8086_2668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266a = { + 0x266a, pci_device_8086_266a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266c = { + 0x266c, pci_device_8086_266c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266d = { + 0x266d, pci_device_8086_266d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266e = { + 0x266e, pci_device_8086_266e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266f = { + 0x266f, pci_device_8086_266f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2670 = { + 0x2670, pci_device_8086_2670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2680 = { + 0x2680, pci_device_8086_2680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2681 = { + 0x2681, pci_device_8086_2681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2682 = { + 0x2682, pci_device_8086_2682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2683 = { + 0x2683, pci_device_8086_2683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2688 = { + 0x2688, pci_device_8086_2688, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2688, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2689 = { + 0x2689, pci_device_8086_2689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268a = { + 0x268a, pci_device_8086_268a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268b = { + 0x268b, pci_device_8086_268b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268c = { + 0x268c, pci_device_8086_268c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2690 = { + 0x2690, pci_device_8086_2690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2692 = { + 0x2692, pci_device_8086_2692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2694 = { + 0x2694, pci_device_8086_2694, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2694, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2696 = { + 0x2696, pci_device_8086_2696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2698 = { + 0x2698, pci_device_8086_2698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2699 = { + 0x2699, pci_device_8086_2699, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2699, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269a = { + 0x269a, pci_device_8086_269a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269b = { + 0x269b, pci_device_8086_269b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269e = { + 0x269e, pci_device_8086_269e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2770 = { + 0x2770, pci_device_8086_2770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2771 = { + 0x2771, pci_device_8086_2771, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2771, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2772 = { + 0x2772, pci_device_8086_2772, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2772, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2774 = { + 0x2774, pci_device_8086_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2775 = { + 0x2775, pci_device_8086_2775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2776 = { + 0x2776, pci_device_8086_2776, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2776, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2778 = { + 0x2778, pci_device_8086_2778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2779 = { + 0x2779, pci_device_8086_2779, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2779, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277a = { + 0x277a, pci_device_8086_277a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277c = { + 0x277c, pci_device_8086_277c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277d = { + 0x277d, pci_device_8086_277d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2782 = { + 0x2782, pci_device_8086_2782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2792 = { + 0x2792, pci_device_8086_2792, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2792, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a0 = { + 0x27a0, pci_device_8086_27a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a1 = { + 0x27a1, pci_device_8086_27a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a2 = { + 0x27a2, pci_device_8086_27a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a6 = { + 0x27a6, pci_device_8086_27a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b0 = { + 0x27b0, pci_device_8086_27b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b8 = { + 0x27b8, pci_device_8086_27b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b9 = { + 0x27b9, pci_device_8086_27b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27bd = { + 0x27bd, pci_device_8086_27bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c0 = { + 0x27c0, pci_device_8086_27c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c1 = { + 0x27c1, pci_device_8086_27c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c3 = { + 0x27c3, pci_device_8086_27c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c4 = { + 0x27c4, pci_device_8086_27c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c5 = { + 0x27c5, pci_device_8086_27c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c6 = { + 0x27c6, pci_device_8086_27c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c8 = { + 0x27c8, pci_device_8086_27c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c9 = { + 0x27c9, pci_device_8086_27c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27ca = { + 0x27ca, pci_device_8086_27ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cb = { + 0x27cb, pci_device_8086_27cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cc = { + 0x27cc, pci_device_8086_27cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d0 = { + 0x27d0, pci_device_8086_27d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d2 = { + 0x27d2, pci_device_8086_27d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d4 = { + 0x27d4, pci_device_8086_27d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d6 = { + 0x27d6, pci_device_8086_27d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d8 = { + 0x27d8, pci_device_8086_27d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27da = { + 0x27da, pci_device_8086_27da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dc = { + 0x27dc, pci_device_8086_27dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dd = { + 0x27dd, pci_device_8086_27dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27de = { + 0x27de, pci_device_8086_27de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27df = { + 0x27df, pci_device_8086_27df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e0 = { + 0x27e0, pci_device_8086_27e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e2 = { + 0x27e2, pci_device_8086_27e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3200 = { + 0x3200, pci_device_8086_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3340 = { + 0x3340, pci_device_8086_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3341 = { + 0x3341, pci_device_8086_3341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3500 = { + 0x3500, pci_device_8086_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3501 = { + 0x3501, pci_device_8086_3501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3504 = { + 0x3504, pci_device_8086_3504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3505 = { + 0x3505, pci_device_8086_3505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350c = { + 0x350c, pci_device_8086_350c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350d = { + 0x350d, pci_device_8086_350d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3510 = { + 0x3510, pci_device_8086_3510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3511 = { + 0x3511, pci_device_8086_3511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3514 = { + 0x3514, pci_device_8086_3514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3515 = { + 0x3515, pci_device_8086_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3518 = { + 0x3518, pci_device_8086_3518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3519 = { + 0x3519, pci_device_8086_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3581 = { + 0x3581, pci_device_8086_3581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3584 = { + 0x3584, pci_device_8086_3584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3585 = { + 0x3585, pci_device_8086_3585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3590 = { + 0x3590, pci_device_8086_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3591 = { + 0x3591, pci_device_8086_3591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3592 = { + 0x3592, pci_device_8086_3592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3593 = { + 0x3593, pci_device_8086_3593, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3593, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3594 = { + 0x3594, pci_device_8086_3594, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3594, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3595 = { + 0x3595, pci_device_8086_3595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3596 = { + 0x3596, pci_device_8086_3596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3597 = { + 0x3597, pci_device_8086_3597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3598 = { + 0x3598, pci_device_8086_3598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3599 = { + 0x3599, pci_device_8086_3599, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3599, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359a = { + 0x359a, pci_device_8086_359a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359b = { + 0x359b, pci_device_8086_359b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359e = { + 0x359e, pci_device_8086_359e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4220 = { + 0x4220, pci_device_8086_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4223 = { + 0x4223, pci_device_8086_4223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4224 = { + 0x4224, pci_device_8086_4224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7050 = { + 0x7050, pci_device_8086_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7051 = { + 0x7051, pci_device_8086_7051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_8500 = { + 0x8500, pci_device_8086_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9000 = { + 0x9000, pci_device_8086_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9001 = { + 0x9001, pci_device_8086_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9004 = { + 0x9004, pci_device_8086_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8c4a_1980 = { + 0x1980, pci_device_8c4a_1980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8c4a_1980, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_0078 = { + 0x0078, pci_device_9004_0078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_0078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7710 = { + 0x7710, pci_device_9004_7710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7711 = { + 0x7711, pci_device_9004_7711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8278 = { + 0x8278, pci_device_9004_8278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8378 = { + 0x8378, pci_device_9004_8378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8478 = { + 0x8478, pci_device_9004_8478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8578 = { + 0x8578, pci_device_9004_8578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8678 = { + 0x8678, pci_device_9004_8678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8778 = { + 0x8778, pci_device_9004_8778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8878 = { + 0x8878, pci_device_9004_8878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8b78 = { + 0x8b78, pci_device_9004_8b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_ec78 = { + 0xec78, pci_device_9004_ec78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_ec78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9005_0010 = { + 0x0010, pci_device_9005_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0011 = { + 0x0011, pci_device_9005_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0013 = { + 0x0013, pci_device_9005_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_001f = { + 0x001f, pci_device_9005_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0020 = { + 0x0020, pci_device_9005_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_002f = { + 0x002f, pci_device_9005_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0030 = { + 0x0030, pci_device_9005_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_003f = { + 0x003f, pci_device_9005_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0050 = { + 0x0050, pci_device_9005_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0051 = { + 0x0051, pci_device_9005_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0053 = { + 0x0053, pci_device_9005_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_005f = { + 0x005f, pci_device_9005_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0080 = { + 0x0080, pci_device_9005_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0081 = { + 0x0081, pci_device_9005_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0083 = { + 0x0083, pci_device_9005_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_008f = { + 0x008f, pci_device_9005_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0092 = { + 0x0092, pci_device_9005_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0093 = { + 0x0093, pci_device_9005_0093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c0 = { + 0x00c0, pci_device_9005_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c1 = { + 0x00c1, pci_device_9005_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c3 = { + 0x00c3, pci_device_9005_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c5 = { + 0x00c5, pci_device_9005_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00cf = { + 0x00cf, pci_device_9005_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0241 = { + 0x0241, pci_device_9005_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0250 = { + 0x0250, pci_device_9005_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0279 = { + 0x0279, pci_device_9005_0279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0283 = { + 0x0283, pci_device_9005_0283, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0283, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0284 = { + 0x0284, pci_device_9005_0284, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0284, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0285 = { + 0x0285, pci_device_9005_0285, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0285, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0286 = { + 0x0286, pci_device_9005_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0500 = { + 0x0500, pci_device_9005_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0503 = { + 0x0503, pci_device_9005_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0910 = { + 0x0910, pci_device_9005_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_091e = { + 0x091e, pci_device_9005_091e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_091e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8000 = { + 0x8000, pci_device_9005_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_800f = { + 0x800f, pci_device_9005_800f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_800f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8010 = { + 0x8010, pci_device_9005_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8011 = { + 0x8011, pci_device_9005_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8012 = { + 0x8012, pci_device_9005_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8013 = { + 0x8013, pci_device_9005_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8014 = { + 0x8014, pci_device_9005_8014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8015 = { + 0x8015, pci_device_9005_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8016 = { + 0x8016, pci_device_9005_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8017 = { + 0x8017, pci_device_9005_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801c = { + 0x801c, pci_device_9005_801c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801d = { + 0x801d, pci_device_9005_801d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801e = { + 0x801e, pci_device_9005_801e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801f = { + 0x801f, pci_device_9005_801f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8080 = { + 0x8080, pci_device_9005_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_808f = { + 0x808f, pci_device_9005_808f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_808f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8090 = { + 0x8090, pci_device_9005_8090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8091 = { + 0x8091, pci_device_9005_8091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8092 = { + 0x8092, pci_device_9005_8092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8093 = { + 0x8093, pci_device_9005_8093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8094 = { + 0x8094, pci_device_9005_8094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8095 = { + 0x8095, pci_device_9005_8095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8096 = { + 0x8096, pci_device_9005_8096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8097 = { + 0x8097, pci_device_9005_8097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809c = { + 0x809c, pci_device_9005_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809d = { + 0x809d, pci_device_9005_809d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809e = { + 0x809e, pci_device_9005_809e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809f = { + 0x809f, pci_device_9005_809f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_907f_2015 = { + 0x2015, pci_device_907f_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_907f_2015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9412_6565 = { + 0x6565, pci_device_9412_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9412_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9699_6565 = { + 0x6565, pci_device_9699_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9699_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9710_7780 = { + 0x7780, pci_device_9710_7780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_7780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9805 = { + 0x9805, pci_device_9710_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9815 = { + 0x9815, pci_device_9710_9815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9835 = { + 0x9835, pci_device_9710_9835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9845 = { + 0x9845, pci_device_9710_9845, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9845, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9855 = { + 0x9855, pci_device_9710_9855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9855, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9902_0001 = { + 0x0001, pci_device_9902_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0002 = { + 0x0002, pci_device_9902_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0003 = { + 0x0003, pci_device_9902_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_a727_0013 = { + 0x0013, pci_device_a727_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_a727_0013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_aecb_6250 = { + 0x6250, pci_device_aecb_6250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_aecb_6250, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_affe_dead = { + 0xdead, pci_device_affe_dead, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_affe_dead, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cafe_0003 = { + 0x0003, pci_device_cafe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cafe_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cddd_0101 = { + 0x0101, pci_device_cddd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_cddd_0200 = { + 0x0200, pci_device_cddd_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d161_0205 = { + 0x0205, pci_device_d161_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0210 = { + 0x0210, pci_device_d161_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0405 = { + 0x0405, pci_device_d161_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0410 = { + 0x0410, pci_device_d161_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_2400 = { + 0x2400, pci_device_d161_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d4d4_0601 = { + 0x0601, pci_device_d4d4_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d4d4_0601, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_deaf_9050 = { + 0x9050, pci_device_deaf_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9051 = { + 0x9051, pci_device_deaf_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9052 = { + 0x9052, pci_device_deaf_9052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9052, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e000_e000 = { + 0xe000, pci_device_e000_e000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e000_e000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e159_0001 = { + 0x0001, pci_device_e159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_e159_0002 = { + 0x0002, pci_device_e159_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea01_000a = { + 0x000a, pci_device_ea01_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0032 = { + 0x0032, pci_device_ea01_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_003e = { + 0x003e, pci_device_ea01_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0041 = { + 0x0041, pci_device_ea01_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0043 = { + 0x0043, pci_device_ea01_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0046 = { + 0x0046, pci_device_ea01_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0052 = { + 0x0052, pci_device_ea01_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0800 = { + 0x0800, pci_device_ea01_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea60_9896 = { + 0x9896, pci_device_ea60_9896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9897 = { + 0x9897, pci_device_ea60_9897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9898 = { + 0x9898, pci_device_ea60_9898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_eace_3100 = { + 0x3100, pci_device_eace_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3200 = { + 0x3200, pci_device_eace_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_320e = { + 0x320e, pci_device_eace_320e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_320e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_340e = { + 0x340e, pci_device_eace_340e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_340e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_341e = { + 0x341e, pci_device_eace_341e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_341e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3500 = { + 0x3500, pci_device_eace_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_351c = { + 0x351c, pci_device_eace_351c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_351c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4100 = { + 0x4100, pci_device_eace_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4110 = { + 0x4110, pci_device_eace_4110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4220 = { + 0x4220, pci_device_eace_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_422e = { + 0x422e, pci_device_eace_422e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_422e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ec80_ec00 = { + 0xec00, pci_device_ec80_ec00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ec80_ec00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_edd8_a091 = { + 0xa091, pci_device_edd8_a091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a099 = { + 0xa099, pci_device_edd8_a099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a1 = { + 0xa0a1, pci_device_edd8_a0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a9 = { + 0xa0a9, pci_device_edd8_a0a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a9, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_f1d0_c0fe = { + 0xc0fe, pci_device_f1d0_c0fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_c0ff = { + 0xc0ff, pci_device_f1d0_c0ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cafe = { + 0xcafe, pci_device_f1d0_cafe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cafe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cfee = { + 0xcfee, pci_device_f1d0_cfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dcaf = { + 0xdcaf, pci_device_f1d0_dcaf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dcaf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dfee = { + 0xdfee, pci_device_f1d0_dfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_efac = { + 0xefac, pci_device_f1d0_efac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_efac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_facd = { + 0xfacd, pci_device_f1d0_facd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_facd, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fa57_0001 = { + 0x0001, pci_device_fa57_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fa57_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_feda_a0fa = { + 0xa0fa, pci_device_feda_a0fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a0fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_feda_a10e = { + 0xa10e, pci_device_feda_a10e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a10e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fede_0003 = { + 0x0003, pci_device_fede_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fede_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffd_0101 = { + 0x0101, pci_device_fffd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffd_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffe_0405 = { + 0x0405, pci_device_fffe_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_fffe_0710 = { + 0x0710, pci_device_fffe_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0710, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0070[] = { + &pci_dev_info_0070_0003, + &pci_dev_info_0070_0009, + &pci_dev_info_0070_0801, + &pci_dev_info_0070_0807, + &pci_dev_info_0070_4000, + &pci_dev_info_0070_4001, + &pci_dev_info_0070_4009, + &pci_dev_info_0070_4800, + &pci_dev_info_0070_4801, + &pci_dev_info_0070_4803, + &pci_dev_info_0070_8003, + &pci_dev_info_0070_8801, + &pci_dev_info_0070_c801, + &pci_dev_info_0070_e807, + &pci_dev_info_0070_e817, + NULL +}; +#endif +#define pci_dev_list_0071 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0095[] = { + &pci_dev_info_0095_0680, + NULL +}; +#endif +#define pci_dev_list_00a7 NULL +#define pci_dev_list_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_018a[] = { + &pci_dev_info_018a_0106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_021b[] = { + &pci_dev_info_021b_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0270[] = { + &pci_dev_info_0270_0801, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0291[] = { + &pci_dev_info_0291_8212, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_02ac[] = { + &pci_dev_info_02ac_1012, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0357[] = { + &pci_dev_info_0357_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0432[] = { + &pci_dev_info_0432_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_045e[] = { + &pci_dev_info_045e_006e, + &pci_dev_info_045e_00c2, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_04cf[] = { + &pci_dev_info_04cf_8818, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05e3[] = { + &pci_dev_info_05e3_0701, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + &pci_dev_info_0675_1703, + &pci_dev_info_0675_1704, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_067b[] = { + &pci_dev_info_067b_3507, + NULL +}; +#endif +#define pci_dev_list_0721 NULL +#define pci_dev_list_07e2 NULL +#define pci_dev_list_0925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b49[] = { + &pci_dev_info_0b49_064f, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0046, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_005a, + &pci_dev_info_0e11_007c, + &pci_dev_info_0e11_007d, + &pci_dev_info_0e11_0085, + &pci_dev_info_0e11_00b1, + &pci_dev_info_0e11_00bb, + &pci_dev_info_0e11_00ca, + &pci_dev_info_0e11_00cb, + &pci_dev_info_0e11_00cf, + &pci_dev_info_0e11_00d0, + &pci_dev_info_0e11_00d1, + &pci_dev_info_0e11_00e3, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_4030, + &pci_dev_info_0e11_4031, + &pci_dev_info_0e11_4032, + &pci_dev_info_0e11_4033, + &pci_dev_info_0e11_4034, + &pci_dev_info_0e11_4040, + &pci_dev_info_0e11_4048, + &pci_dev_info_0e11_4050, + &pci_dev_info_0e11_4051, + &pci_dev_info_0e11_4058, + &pci_dev_info_0e11_4070, + &pci_dev_info_0e11_4080, + &pci_dev_info_0e11_4082, + &pci_dev_info_0e11_4083, + &pci_dev_info_0e11_4091, + &pci_dev_info_0e11_409a, + &pci_dev_info_0e11_409b, + &pci_dev_info_0e11_409c, + &pci_dev_info_0e11_409d, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_b200, + &pci_dev_info_0e11_b203, + &pci_dev_info_0e11_b204, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0031, + &pci_dev_info_1000_0032, + &pci_dev_info_1000_0033, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_0041, + &pci_dev_info_1000_0050, + &pci_dev_info_1000_0054, + &pci_dev_info_1000_0056, + &pci_dev_info_1000_0058, + &pci_dev_info_1000_005a, + &pci_dev_info_1000_005c, + &pci_dev_info_1000_005e, + &pci_dev_info_1000_0060, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0407, + &pci_dev_info_1000_0408, + &pci_dev_info_1000_0409, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0640, + &pci_dev_info_1000_0642, + &pci_dev_info_1000_0646, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0804, + &pci_dev_info_1000_0805, + &pci_dev_info_1000_0806, + &pci_dev_info_1000_0807, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_3150, + &pci_dev_info_1002_3152, + &pci_dev_info_1002_3154, + &pci_dev_info_1002_3e50, + &pci_dev_info_1002_3e54, + &pci_dev_info_1002_3e70, + &pci_dev_info_1002_4136, + &pci_dev_info_1002_4137, + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4148, + &pci_dev_info_1002_4149, + &pci_dev_info_1002_414a, + &pci_dev_info_1002_414b, + &pci_dev_info_1002_4150, + &pci_dev_info_1002_4151, + &pci_dev_info_1002_4152, + &pci_dev_info_1002_4153, + &pci_dev_info_1002_4154, + &pci_dev_info_1002_4155, + &pci_dev_info_1002_4156, + &pci_dev_info_1002_4157, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4164, + &pci_dev_info_1002_4165, + &pci_dev_info_1002_4166, + &pci_dev_info_1002_4168, + &pci_dev_info_1002_4170, + &pci_dev_info_1002_4171, + &pci_dev_info_1002_4172, + &pci_dev_info_1002_4173, + &pci_dev_info_1002_4237, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4243, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4341, + &pci_dev_info_1002_4345, + &pci_dev_info_1002_4347, + &pci_dev_info_1002_4348, + &pci_dev_info_1002_4349, + &pci_dev_info_1002_434d, + &pci_dev_info_1002_4353, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4363, + &pci_dev_info_1002_436e, + &pci_dev_info_1002_4370, + &pci_dev_info_1002_4371, + &pci_dev_info_1002_4372, + &pci_dev_info_1002_4373, + &pci_dev_info_1002_4374, + &pci_dev_info_1002_4375, + &pci_dev_info_1002_4376, + &pci_dev_info_1002_4377, + &pci_dev_info_1002_4378, + &pci_dev_info_1002_4379, + &pci_dev_info_1002_437a, + &pci_dev_info_1002_4437, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4a48, + &pci_dev_info_1002_4a49, + &pci_dev_info_1002_4a4a, + &pci_dev_info_1002_4a4b, + &pci_dev_info_1002_4a4c, + &pci_dev_info_1002_4a4d, + &pci_dev_info_1002_4a4e, + &pci_dev_info_1002_4a50, + &pci_dev_info_1002_4a70, + &pci_dev_info_1002_4b49, + &pci_dev_info_1002_4b4b, + &pci_dev_info_1002_4b4c, + &pci_dev_info_1002_4b69, + &pci_dev_info_1002_4b6b, + &pci_dev_info_1002_4b6c, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4c6e, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e48, + &pci_dev_info_1002_4e49, + &pci_dev_info_1002_4e4a, + &pci_dev_info_1002_4e4b, + &pci_dev_info_1002_4e50, + &pci_dev_info_1002_4e51, + &pci_dev_info_1002_4e52, + &pci_dev_info_1002_4e53, + &pci_dev_info_1002_4e54, + &pci_dev_info_1002_4e56, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_4e68, + &pci_dev_info_1002_4e69, + &pci_dev_info_1002_4e6a, + &pci_dev_info_1002_4e71, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5154, + &pci_dev_info_1002_5155, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_515e, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5460, + &pci_dev_info_1002_5464, + &pci_dev_info_1002_5548, + &pci_dev_info_1002_5549, + &pci_dev_info_1002_554a, + &pci_dev_info_1002_554b, + &pci_dev_info_1002_554d, + &pci_dev_info_1002_554f, + &pci_dev_info_1002_5550, + &pci_dev_info_1002_5551, + &pci_dev_info_1002_5552, + &pci_dev_info_1002_5554, + &pci_dev_info_1002_556b, + &pci_dev_info_1002_556d, + &pci_dev_info_1002_556f, + &pci_dev_info_1002_564a, + &pci_dev_info_1002_564b, + &pci_dev_info_1002_5652, + &pci_dev_info_1002_5653, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_5830, + &pci_dev_info_1002_5831, + &pci_dev_info_1002_5832, + &pci_dev_info_1002_5833, + &pci_dev_info_1002_5834, + &pci_dev_info_1002_5835, + &pci_dev_info_1002_5838, + &pci_dev_info_1002_5940, + &pci_dev_info_1002_5941, + &pci_dev_info_1002_5944, + &pci_dev_info_1002_5950, + &pci_dev_info_1002_5951, + &pci_dev_info_1002_5954, + &pci_dev_info_1002_5955, + &pci_dev_info_1002_5960, + &pci_dev_info_1002_5961, + &pci_dev_info_1002_5962, + &pci_dev_info_1002_5964, + &pci_dev_info_1002_5969, + &pci_dev_info_1002_5974, + &pci_dev_info_1002_5975, + &pci_dev_info_1002_5a34, + &pci_dev_info_1002_5a41, + &pci_dev_info_1002_5a42, + &pci_dev_info_1002_5a61, + &pci_dev_info_1002_5a62, + &pci_dev_info_1002_5b60, + &pci_dev_info_1002_5b62, + &pci_dev_info_1002_5b63, + &pci_dev_info_1002_5b64, + &pci_dev_info_1002_5b65, + &pci_dev_info_1002_5b70, + &pci_dev_info_1002_5b72, + &pci_dev_info_1002_5b73, + &pci_dev_info_1002_5b74, + &pci_dev_info_1002_5c61, + &pci_dev_info_1002_5c63, + &pci_dev_info_1002_5d44, + &pci_dev_info_1002_5d48, + &pci_dev_info_1002_5d49, + &pci_dev_info_1002_5d4a, + &pci_dev_info_1002_5d4d, + &pci_dev_info_1002_5d52, + &pci_dev_info_1002_5d57, + &pci_dev_info_1002_5d6d, + &pci_dev_info_1002_5d72, + &pci_dev_info_1002_5d77, + &pci_dev_info_1002_5e48, + &pci_dev_info_1002_5e49, + &pci_dev_info_1002_5e4a, + &pci_dev_info_1002_5e4b, + &pci_dev_info_1002_5e4c, + &pci_dev_info_1002_5e4d, + &pci_dev_info_1002_5e4f, + &pci_dev_info_1002_5e6b, + &pci_dev_info_1002_5e6d, + &pci_dev_info_1002_700f, + &pci_dev_info_1002_7010, + &pci_dev_info_1002_7105, + &pci_dev_info_1002_7109, + &pci_dev_info_1002_7833, + &pci_dev_info_1002_7834, + &pci_dev_info_1002_7835, + &pci_dev_info_1002_7838, + &pci_dev_info_1002_7c37, + &pci_dev_info_1002_cab0, + &pci_dev_info_1002_cab2, + &pci_dev_info_1002_cab3, + &pci_dev_info_1002_cbb2, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0021, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0028, + &pci_dev_info_100b_002a, + &pci_dev_info_100b_002b, + &pci_dev_info_100b_002d, + &pci_dev_info_100b_002e, + &pci_dev_info_100b_002f, + &pci_dev_info_100b_0030, + &pci_dev_info_100b_0035, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_0510, + &pci_dev_info_100b_0511, + &pci_dev_info_100b_0515, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0017, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4000, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0031, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_0037, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003c, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0054, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_005e, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_008b, + &pci_dev_info_1014_008e, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0091, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_009f, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00b8, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0104, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_015e, + &pci_dev_info_1014_0160, + &pci_dev_info_1014_016e, + &pci_dev_info_1014_0170, + &pci_dev_info_1014_017d, + &pci_dev_info_1014_0180, + &pci_dev_info_1014_0188, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_01c1, + &pci_dev_info_1014_01e6, + &pci_dev_info_1014_01ff, + &pci_dev_info_1014_0219, + &pci_dev_info_1014_021b, + &pci_dev_info_1014_021c, + &pci_dev_info_1014_0233, + &pci_dev_info_1014_0266, + &pci_dev_info_1014_0268, + &pci_dev_info_1014_0269, + &pci_dev_info_1014_028c, + &pci_dev_info_1014_02a1, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_0314, + &pci_dev_info_1014_3022, + &pci_dev_info_1014_4022, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_0009, + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2003, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_208f, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700a, + &pci_dev_info_1022_700b, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7458, + &pci_dev_info_1022_7459, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + &pci_dev_info_1022_756b, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_2100, + &pci_dev_info_1023_2200, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_1671, + &pci_dev_info_1025_1672, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_0009, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000d, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + &pci_dev_info_1028_0010, + &pci_dev_info_1028_0011, + &pci_dev_info_1028_0012, + &pci_dev_info_1028_0013, + &pci_dev_info_1028_0014, + &pci_dev_info_1028_0015, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + &pci_dev_info_102a_001f, + &pci_dev_info_102a_00c5, + &pci_dev_info_102a_00cf, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0100, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0528, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_2537, + &pci_dev_info_102b_2538, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_000a, + &pci_dev_info_102f_0020, + &pci_dev_info_102f_0030, + &pci_dev_info_102f_0031, + &pci_dev_info_102f_0105, + &pci_dev_info_102f_0106, + &pci_dev_info_102f_0107, + &pci_dev_info_102f_0108, + &pci_dev_info_102f_0180, + &pci_dev_info_102f_0181, + &pci_dev_info_102f_0182, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0000, + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0072, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a5, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00ce, + &pci_dev_info_1033_00df, + &pci_dev_info_1033_00e0, + &pci_dev_info_1033_00e7, + &pci_dev_info_1033_00f2, + &pci_dev_info_1033_00f3, + &pci_dev_info_1033_010c, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0003, + &pci_dev_info_1039_0004, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_000a, + &pci_dev_info_1039_0016, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0180, + &pci_dev_info_1039_0181, + &pci_dev_info_1039_0182, + &pci_dev_info_1039_0191, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0550, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0648, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0655, + &pci_dev_info_1039_0660, + &pci_dev_info_1039_0661, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0741, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0746, + &pci_dev_info_1039_0755, + &pci_dev_info_1039_0760, + &pci_dev_info_1039_0761, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_0963, + &pci_dev_info_1039_0964, + &pci_dev_info_1039_0965, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_6330, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + &pci_dev_info_1039_7019, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1006, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_100a, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1054, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_10f0, + &pci_dev_info_103c_10f1, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_127c, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_1291, + &pci_dev_info_103c_12b4, + &pci_dev_info_103c_12fa, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + &pci_dev_info_103c_3080, + &pci_dev_info_103c_3220, + &pci_dev_info_103c_3230, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_4015, + &pci_dev_info_1043_4021, + &pci_dev_info_1043_4057, + &pci_dev_info_1043_8043, + &pci_dev_info_1043_807b, + &pci_dev_info_1043_80bb, + &pci_dev_info_1043_80c5, + &pci_dev_info_1043_80df, + &pci_dev_info_1043_8187, + &pci_dev_info_1043_8188, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0c60, + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + &pci_dev_info_1048_8901, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0209, + &pci_dev_info_104a_020a, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_021a, + &pci_dev_info_104a_021b, + &pci_dev_info_104a_0500, + &pci_dev_info_104a_0564, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + &pci_dev_info_104a_55cc, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8025, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8029, + &pci_dev_info_104c_802b, + &pci_dev_info_104c_802e, + &pci_dev_info_104c_8031, + &pci_dev_info_104c_8032, + &pci_dev_info_104c_8033, + &pci_dev_info_104c_8034, + &pci_dev_info_104c_8035, + &pci_dev_info_104c_8036, + &pci_dev_info_104c_8038, + &pci_dev_info_104c_8201, + &pci_dev_info_104c_8204, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_8401, + &pci_dev_info_104c_9000, + &pci_dev_info_104c_9066, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac44, + &pci_dev_info_104c_ac46, + &pci_dev_info_104c_ac47, + &pci_dev_info_104c_ac4a, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac54, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_ac8d, + &pci_dev_info_104c_ac8e, + &pci_dev_info_104c_ac8f, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8004, + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9921, + &pci_dev_info_1050_9922, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0008, + &pci_dev_info_1057_0009, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_18c1, + &pci_dev_info_1057_3410, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_5803, + &pci_dev_info_1057_5806, + &pci_dev_info_1057_5808, + &pci_dev_info_1057_6400, + &pci_dev_info_1057_6405, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3318, + &pci_dev_info_105a_3319, + &pci_dev_info_105a_3371, + &pci_dev_info_105a_3373, + &pci_dev_info_105a_3375, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_3515, + &pci_dev_info_105a_3519, + &pci_dev_info_105a_3571, + &pci_dev_info_105a_3574, + &pci_dev_info_105a_3577, + &pci_dev_info_105a_3d17, + &pci_dev_info_105a_3d18, + &pci_dev_info_105a_3d73, + &pci_dev_info_105a_3d75, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_6622, + &pci_dev_info_105a_6624, + &pci_dev_info_105a_6626, + &pci_dev_info_105a_6629, + &pci_dev_info_105a_7275, + &pci_dev_info_105a_8002, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_0301, + &pci_dev_info_1067_0304, + &pci_dev_info_1067_0308, + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0020, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_b166, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + &pci_dev_info_1069_ba57, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000c, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_0035, + &pci_dev_info_106b_0036, + &pci_dev_info_106b_003b, + &pci_dev_info_106b_003e, + &pci_dev_info_106b_003f, + &pci_dev_info_106b_0040, + &pci_dev_info_106b_0041, + &pci_dev_info_106b_0042, + &pci_dev_info_106b_0043, + &pci_dev_info_106b_0045, + &pci_dev_info_106b_0046, + &pci_dev_info_106b_0047, + &pci_dev_info_106b_0048, + &pci_dev_info_106b_0049, + &pci_dev_info_106b_004b, + &pci_dev_info_106b_004c, + &pci_dev_info_106b_004f, + &pci_dev_info_106b_0050, + &pci_dev_info_106b_0051, + &pci_dev_info_106b_0052, + &pci_dev_info_106b_0053, + &pci_dev_info_106b_0054, + &pci_dev_info_106b_0055, + &pci_dev_info_106b_0058, + &pci_dev_info_106b_0059, + &pci_dev_info_106b_0066, + &pci_dev_info_106b_0067, + &pci_dev_info_106b_0068, + &pci_dev_info_106b_0069, + &pci_dev_info_106b_006a, + &pci_dev_info_106b_006b, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1071[] = { + &pci_dev_info_1071_8160, + NULL +}; +#endif +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + &pci_dev_info_1077_2322, + &pci_dev_info_1077_2422, + &pci_dev_info_1077_2432, + &pci_dev_info_1077_3010, + &pci_dev_info_1077_3022, + &pci_dev_info_1077_4010, + &pci_dev_info_1077_4022, + &pci_dev_info_1077_6312, + &pci_dev_info_1077_6322, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + &pci_dev_info_107d_2134, + &pci_dev_info_107d_2971, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_1648, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_8002, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + &pci_dev_info_108e_a801, + &pci_dev_info_108e_abba, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + &pci_dev_info_1091_07a0, + &pci_dev_info_1091_1091, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1310, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_14e0, + &pci_dev_info_1093_14f0, + &pci_dev_info_1093_17d0, + &pci_dev_info_1093_1870, + &pci_dev_info_1093_1880, + &pci_dev_info_1093_18b0, + &pci_dev_info_1093_2410, + &pci_dev_info_1093_2890, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_2a70, + &pci_dev_info_1093_2a80, + &pci_dev_info_1093_2c80, + &pci_dev_info_1093_2ca0, + &pci_dev_info_1093_70b8, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0240, + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + &pci_dev_info_1095_3114, + &pci_dev_info_1095_3124, + &pci_dev_info_1095_3132, + &pci_dev_info_1095_3512, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_032e, + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_3052, + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_100a, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_4001, + &pci_dev_info_10a9_4002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + &pci_dev_info_10a9_8010, + &pci_dev_info_10a9_8018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1042, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2540, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_6540, + &pci_dev_info_10b5_6541, + &pci_dev_info_10b5_6542, + &pci_dev_info_10b5_8111, + &pci_dev_info_10b5_8114, + &pci_dev_info_10b5_8516, + &pci_dev_info_10b5_8532, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9056, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + &pci_dev_info_10b5_bb04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_0013, + &pci_dev_info_10b7_0910, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_1201, + &pci_dev_info_10b7_1202, + &pci_dev_info_10b7_1700, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6000, + &pci_dev_info_10b7_6001, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7770, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_80eb, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9202, + &pci_dev_info_10b7_9210, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990a, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_2802, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0101, + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_0780, + &pci_dev_info_10b9_0782, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1573, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1672, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_1689, + &pci_dev_info_10b9_1695, + &pci_dev_info_10b9_1697, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_3323, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5228, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5246, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_524b, + &pci_dev_info_10b9_524c, + &pci_dev_info_10b9_524d, + &pci_dev_info_10b9_524e, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5263, + &pci_dev_info_10b9_5281, + &pci_dev_info_10b9_5287, + &pci_dev_info_10b9_5288, + &pci_dev_info_10b9_5289, + &pci_dev_info_10b9_5450, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5461, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + &pci_dev_info_10ba_0304, + &pci_dev_info_10ba_0308, + &pci_dev_info_10ba_1002, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cc[] = { + &pci_dev_info_10cc_0660, + &pci_dev_info_10cc_0661, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0431, + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8626, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dd[] = { + &pci_dev_info_10dd_0100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0034, + &pci_dev_info_10de_0035, + &pci_dev_info_10de_0036, + &pci_dev_info_10de_0037, + &pci_dev_info_10de_0038, + &pci_dev_info_10de_003a, + &pci_dev_info_10de_003b, + &pci_dev_info_10de_003c, + &pci_dev_info_10de_003d, + &pci_dev_info_10de_003e, + &pci_dev_info_10de_0040, + &pci_dev_info_10de_0041, + &pci_dev_info_10de_0042, + &pci_dev_info_10de_0043, + &pci_dev_info_10de_0045, + &pci_dev_info_10de_0046, + &pci_dev_info_10de_0048, + &pci_dev_info_10de_0049, + &pci_dev_info_10de_004e, + &pci_dev_info_10de_0050, + &pci_dev_info_10de_0051, + &pci_dev_info_10de_0052, + &pci_dev_info_10de_0053, + &pci_dev_info_10de_0054, + &pci_dev_info_10de_0055, + &pci_dev_info_10de_0056, + &pci_dev_info_10de_0057, + &pci_dev_info_10de_0058, + &pci_dev_info_10de_0059, + &pci_dev_info_10de_005a, + &pci_dev_info_10de_005b, + &pci_dev_info_10de_005c, + &pci_dev_info_10de_005d, + &pci_dev_info_10de_005e, + &pci_dev_info_10de_005f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006c, + &pci_dev_info_10de_006d, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_0080, + &pci_dev_info_10de_0084, + &pci_dev_info_10de_0085, + &pci_dev_info_10de_0086, + &pci_dev_info_10de_0087, + &pci_dev_info_10de_0088, + &pci_dev_info_10de_008a, + &pci_dev_info_10de_008b, + &pci_dev_info_10de_008c, + &pci_dev_info_10de_008e, + &pci_dev_info_10de_0091, + &pci_dev_info_10de_0092, + &pci_dev_info_10de_0099, + &pci_dev_info_10de_009d, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_00c0, + &pci_dev_info_10de_00c1, + &pci_dev_info_10de_00c2, + &pci_dev_info_10de_00c3, + &pci_dev_info_10de_00c8, + &pci_dev_info_10de_00c9, + &pci_dev_info_10de_00cc, + &pci_dev_info_10de_00cd, + &pci_dev_info_10de_00ce, + &pci_dev_info_10de_00d0, + &pci_dev_info_10de_00d1, + &pci_dev_info_10de_00d2, + &pci_dev_info_10de_00d3, + &pci_dev_info_10de_00d4, + &pci_dev_info_10de_00d5, + &pci_dev_info_10de_00d6, + &pci_dev_info_10de_00d7, + &pci_dev_info_10de_00d8, + &pci_dev_info_10de_00d9, + &pci_dev_info_10de_00da, + &pci_dev_info_10de_00dd, + &pci_dev_info_10de_00df, + &pci_dev_info_10de_00e0, + &pci_dev_info_10de_00e1, + &pci_dev_info_10de_00e2, + &pci_dev_info_10de_00e3, + &pci_dev_info_10de_00e4, + &pci_dev_info_10de_00e5, + &pci_dev_info_10de_00e6, + &pci_dev_info_10de_00e7, + &pci_dev_info_10de_00e8, + &pci_dev_info_10de_00ea, + &pci_dev_info_10de_00ed, + &pci_dev_info_10de_00ee, + &pci_dev_info_10de_00f0, + &pci_dev_info_10de_00f1, + &pci_dev_info_10de_00f2, + &pci_dev_info_10de_00f3, + &pci_dev_info_10de_00f8, + &pci_dev_info_10de_00f9, + &pci_dev_info_10de_00fa, + &pci_dev_info_10de_00fb, + &pci_dev_info_10de_00fc, + &pci_dev_info_10de_00fd, + &pci_dev_info_10de_00fe, + &pci_dev_info_10de_00ff, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0140, + &pci_dev_info_10de_0141, + &pci_dev_info_10de_0142, + &pci_dev_info_10de_0144, + &pci_dev_info_10de_0145, + &pci_dev_info_10de_0146, + &pci_dev_info_10de_0147, + &pci_dev_info_10de_0148, + &pci_dev_info_10de_0149, + &pci_dev_info_10de_014e, + &pci_dev_info_10de_014f, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0160, + &pci_dev_info_10de_0161, + &pci_dev_info_10de_0162, + &pci_dev_info_10de_0163, + &pci_dev_info_10de_0164, + &pci_dev_info_10de_0165, + &pci_dev_info_10de_0166, + &pci_dev_info_10de_0167, + &pci_dev_info_10de_0168, + &pci_dev_info_10de_0169, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0177, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_017d, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0185, + &pci_dev_info_10de_0186, + &pci_dev_info_10de_0187, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_018c, + &pci_dev_info_10de_018d, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b0, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01e0, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01ea, + &pci_dev_info_10de_01eb, + &pci_dev_info_10de_01ec, + &pci_dev_info_10de_01ed, + &pci_dev_info_10de_01ee, + &pci_dev_info_10de_01ef, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0211, + &pci_dev_info_10de_0212, + &pci_dev_info_10de_0215, + &pci_dev_info_10de_0221, + &pci_dev_info_10de_0240, + &pci_dev_info_10de_0241, + &pci_dev_info_10de_0242, + &pci_dev_info_10de_0243, + &pci_dev_info_10de_0244, + &pci_dev_info_10de_0245, + &pci_dev_info_10de_0246, + &pci_dev_info_10de_0247, + &pci_dev_info_10de_0248, + &pci_dev_info_10de_0249, + &pci_dev_info_10de_024a, + &pci_dev_info_10de_024b, + &pci_dev_info_10de_024c, + &pci_dev_info_10de_024d, + &pci_dev_info_10de_024e, + &pci_dev_info_10de_024f, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0260, + &pci_dev_info_10de_0261, + &pci_dev_info_10de_0262, + &pci_dev_info_10de_0263, + &pci_dev_info_10de_0264, + &pci_dev_info_10de_0265, + &pci_dev_info_10de_0266, + &pci_dev_info_10de_0267, + &pci_dev_info_10de_0268, + &pci_dev_info_10de_0269, + &pci_dev_info_10de_026a, + &pci_dev_info_10de_026b, + &pci_dev_info_10de_026c, + &pci_dev_info_10de_026d, + &pci_dev_info_10de_026e, + &pci_dev_info_10de_026f, + &pci_dev_info_10de_0270, + &pci_dev_info_10de_0271, + &pci_dev_info_10de_0272, + &pci_dev_info_10de_027e, + &pci_dev_info_10de_027f, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0286, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_028c, + &pci_dev_info_10de_02a0, + &pci_dev_info_10de_02f0, + &pci_dev_info_10de_02f1, + &pci_dev_info_10de_02f2, + &pci_dev_info_10de_02f3, + &pci_dev_info_10de_02f4, + &pci_dev_info_10de_02f5, + &pci_dev_info_10de_02f6, + &pci_dev_info_10de_02f7, + &pci_dev_info_10de_02f8, + &pci_dev_info_10de_02f9, + &pci_dev_info_10de_02fa, + &pci_dev_info_10de_02fb, + &pci_dev_info_10de_02fc, + &pci_dev_info_10de_02fd, + &pci_dev_info_10de_02fe, + &pci_dev_info_10de_02ff, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + &pci_dev_info_10de_0311, + &pci_dev_info_10de_0312, + &pci_dev_info_10de_0313, + &pci_dev_info_10de_0314, + &pci_dev_info_10de_0316, + &pci_dev_info_10de_0317, + &pci_dev_info_10de_031a, + &pci_dev_info_10de_031b, + &pci_dev_info_10de_031c, + &pci_dev_info_10de_031d, + &pci_dev_info_10de_031e, + &pci_dev_info_10de_031f, + &pci_dev_info_10de_0320, + &pci_dev_info_10de_0321, + &pci_dev_info_10de_0322, + &pci_dev_info_10de_0323, + &pci_dev_info_10de_0324, + &pci_dev_info_10de_0325, + &pci_dev_info_10de_0326, + &pci_dev_info_10de_0327, + &pci_dev_info_10de_0328, + &pci_dev_info_10de_0329, + &pci_dev_info_10de_032a, + &pci_dev_info_10de_032b, + &pci_dev_info_10de_032c, + &pci_dev_info_10de_032d, + &pci_dev_info_10de_032f, + &pci_dev_info_10de_0330, + &pci_dev_info_10de_0331, + &pci_dev_info_10de_0332, + &pci_dev_info_10de_0333, + &pci_dev_info_10de_0334, + &pci_dev_info_10de_0338, + &pci_dev_info_10de_033f, + &pci_dev_info_10de_0341, + &pci_dev_info_10de_0342, + &pci_dev_info_10de_0343, + &pci_dev_info_10de_0344, + &pci_dev_info_10de_0345, + &pci_dev_info_10de_0347, + &pci_dev_info_10de_0348, + &pci_dev_info_10de_0349, + &pci_dev_info_10de_034b, + &pci_dev_info_10de_034c, + &pci_dev_info_10de_034e, + &pci_dev_info_10de_034f, + &pci_dev_info_10de_0360, + &pci_dev_info_10de_0361, + &pci_dev_info_10de_0362, + &pci_dev_info_10de_0363, + &pci_dev_info_10de_0364, + &pci_dev_info_10de_0365, + &pci_dev_info_10de_0366, + &pci_dev_info_10de_0367, + &pci_dev_info_10de_0368, + &pci_dev_info_10de_0369, + &pci_dev_info_10de_036a, + &pci_dev_info_10de_036c, + &pci_dev_info_10de_036d, + &pci_dev_info_10de_036e, + &pci_dev_info_10de_0371, + &pci_dev_info_10de_0372, + &pci_dev_info_10de_0373, + &pci_dev_info_10de_037a, + &pci_dev_info_10de_037e, + &pci_dev_info_10de_037f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f0a1, + &pci_dev_info_10df_f0a5, + &pci_dev_info_10df_f0b5, + &pci_dev_info_10df_f0d1, + &pci_dev_info_10df_f0d5, + &pci_dev_info_10df_f0e1, + &pci_dev_info_10df_f0e5, + &pci_dev_info_10df_f0f5, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f701, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f801, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f901, + &pci_dev_info_10df_f980, + &pci_dev_info_10df_f981, + &pci_dev_info_10df_f982, + &pci_dev_info_10df_fa00, + &pci_dev_info_10df_fb00, + &pci_dev_info_10df_fc00, + &pci_dev_info_10df_fc10, + &pci_dev_info_10df_fc20, + &pci_dev_info_10df_fd00, + &pci_dev_info_10df_fe00, + &pci_dev_info_10df_ff00, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0148, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + &pci_dev_info_10e3_8260, + &pci_dev_info_10e3_8261, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e4[] = { + &pci_dev_info_10e4_8029, + NULL +}; +#endif +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_1072, + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_814c, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_81e6, + &pci_dev_info_10e8_8291, + &pci_dev_info_10e8_82c4, + &pci_dev_info_10e8_82c5, + &pci_dev_info_10e8_82c6, + &pci_dev_info_10e8_82c7, + &pci_dev_info_10e8_82ca, + &pci_dev_info_10e8_82db, + &pci_dev_info_10e8_82e2, + &pci_dev_info_10e8_8851, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + &pci_dev_info_10ea_5252, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_0139, + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8180, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_0314, + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + &pci_dev_info_10ee_3fc6, + &pci_dev_info_10ee_8381, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#define pci_dev_list_10f1 NULL +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + &pci_dev_info_1101_9502, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_0007, + &pci_dev_info_1102_0008, + &pci_dev_info_1102_100a, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_7005, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + &pci_dev_info_1103_0009, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + &pci_dev_info_1105_8401, + &pci_dev_info_1105_8470, + &pci_dev_info_1105_8471, + &pci_dev_info_1105_8475, + &pci_dev_info_1105_8476, + &pci_dev_info_1105_8485, + &pci_dev_info_1105_8486, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0204, + &pci_dev_info_1106_0238, + &pci_dev_info_1106_0259, + &pci_dev_info_1106_0269, + &pci_dev_info_1106_0282, + &pci_dev_info_1106_0290, + &pci_dev_info_1106_0296, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0308, + &pci_dev_info_1106_0314, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0591, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1204, + &pci_dev_info_1106_1208, + &pci_dev_info_1106_1238, + &pci_dev_info_1106_1258, + &pci_dev_info_1106_1259, + &pci_dev_info_1106_1269, + &pci_dev_info_1106_1282, + &pci_dev_info_1106_1290, + &pci_dev_info_1106_1296, + &pci_dev_info_1106_1308, + &pci_dev_info_1106_1314, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_2204, + &pci_dev_info_1106_2208, + &pci_dev_info_1106_2238, + &pci_dev_info_1106_2258, + &pci_dev_info_1106_2259, + &pci_dev_info_1106_2269, + &pci_dev_info_1106_2282, + &pci_dev_info_1106_2290, + &pci_dev_info_1106_2296, + &pci_dev_info_1106_2308, + &pci_dev_info_1106_2314, + &pci_dev_info_1106_287a, + &pci_dev_info_1106_287b, + &pci_dev_info_1106_287c, + &pci_dev_info_1106_287d, + &pci_dev_info_1106_287e, + &pci_dev_info_1106_3022, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3053, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3108, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3113, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3118, + &pci_dev_info_1106_3119, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3149, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3164, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3178, + &pci_dev_info_1106_3188, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_3204, + &pci_dev_info_1106_3205, + &pci_dev_info_1106_3208, + &pci_dev_info_1106_3213, + &pci_dev_info_1106_3218, + &pci_dev_info_1106_3227, + &pci_dev_info_1106_3238, + &pci_dev_info_1106_3249, + &pci_dev_info_1106_3258, + &pci_dev_info_1106_3259, + &pci_dev_info_1106_3269, + &pci_dev_info_1106_3282, + &pci_dev_info_1106_3288, + &pci_dev_info_1106_3290, + &pci_dev_info_1106_3296, + &pci_dev_info_1106_3337, + &pci_dev_info_1106_3349, + &pci_dev_info_1106_337a, + &pci_dev_info_1106_337b, + &pci_dev_info_1106_4149, + &pci_dev_info_1106_4204, + &pci_dev_info_1106_4208, + &pci_dev_info_1106_4238, + &pci_dev_info_1106_4258, + &pci_dev_info_1106_4259, + &pci_dev_info_1106_4269, + &pci_dev_info_1106_4282, + &pci_dev_info_1106_4290, + &pci_dev_info_1106_4296, + &pci_dev_info_1106_4308, + &pci_dev_info_1106_4314, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_5208, + &pci_dev_info_1106_5238, + &pci_dev_info_1106_5290, + &pci_dev_info_1106_5308, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_7204, + &pci_dev_info_1106_7205, + &pci_dev_info_1106_7208, + &pci_dev_info_1106_7238, + &pci_dev_info_1106_7258, + &pci_dev_info_1106_7259, + &pci_dev_info_1106_7269, + &pci_dev_info_1106_7282, + &pci_dev_info_1106_7290, + &pci_dev_info_1106_7296, + &pci_dev_info_1106_7308, + &pci_dev_info_1106_7314, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_a208, + &pci_dev_info_1106_a238, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b113, + &pci_dev_info_1106_b115, + &pci_dev_info_1106_b168, + &pci_dev_info_1106_b188, + &pci_dev_info_1106_b198, + &pci_dev_info_1106_b213, + &pci_dev_info_1106_c208, + &pci_dev_info_1106_c238, + &pci_dev_info_1106_d104, + &pci_dev_info_1106_d208, + &pci_dev_info_1106_d213, + &pci_dev_info_1106_d238, + &pci_dev_info_1106_e208, + &pci_dev_info_1106_e238, + &pci_dev_info_1106_f208, + &pci_dev_info_1106_f238, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_0006, + &pci_dev_info_110a_0015, + &pci_dev_info_110a_001d, + &pci_dev_info_110a_007b, + &pci_dev_info_110a_007c, + &pci_dev_info_110a_007d, + &pci_dev_info_110a_2101, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_2104, + &pci_dev_info_110a_3142, + &pci_dev_info_110a_4021, + &pci_dev_info_110a_4029, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + &pci_dev_info_1113_d301, + &pci_dev_info_1113_ec02, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1114[] = { + &pci_dev_info_1114_0506, + NULL +}; +#endif +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0010, + &pci_dev_info_1119_0011, + &pci_dev_info_1119_0012, + &pci_dev_info_1119_0013, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_02ff, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + &pci_dev_info_111a_1203, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + &pci_dev_info_111d_0004, + &pci_dev_info_111d_0005, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#define pci_dev_list_1124 NULL +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + &pci_dev_info_112f_0008, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_5400, + &pci_dev_info_1131_5402, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7135, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + &pci_dev_info_1131_9730, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e006, + &pci_dev_info_1133_e007, + &pci_dev_info_1133_e008, + &pci_dev_info_1133_e009, + &pci_dev_info_1133_e00a, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e00c, + &pci_dev_info_1133_e00d, + &pci_dev_info_1133_e00e, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e011, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e013, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e015, + &pci_dev_info_1133_e016, + &pci_dev_info_1133_e017, + &pci_dev_info_1133_e018, + &pci_dev_info_1133_e019, + &pci_dev_info_1133_e01a, + &pci_dev_info_1133_e01b, + &pci_dev_info_1133_e01c, + &pci_dev_info_1133_e01e, + &pci_dev_info_1133_e020, + &pci_dev_info_1133_e024, + &pci_dev_info_1133_e028, + &pci_dev_info_1133_e02a, + &pci_dev_info_1133_e02c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + &pci_dev_info_1134_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + &pci_dev_info_1145_f020, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + &pci_dev_info_1148_4500, + &pci_dev_info_1148_9000, + &pci_dev_info_1148_9843, + &pci_dev_info_1148_9e00, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0013, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0028, + &pci_dev_info_114f_0029, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0043, + &pci_dev_info_114f_0044, + &pci_dev_info_114f_0045, + &pci_dev_info_114f_004e, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_00b0, + &pci_dev_info_114f_00b1, + &pci_dev_info_114f_00c8, + &pci_dev_info_114f_00c9, + &pci_dev_info_114f_00ca, + &pci_dev_info_114f_00cb, + &pci_dev_info_114f_00d0, + &pci_dev_info_114f_00d1, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_00d4, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0000, + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0006, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0036, + &pci_dev_info_1166_0101, + &pci_dev_info_1166_0104, + &pci_dev_info_1166_0110, + &pci_dev_info_1166_0130, + &pci_dev_info_1166_0132, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0205, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0214, + &pci_dev_info_1166_0217, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0223, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + &pci_dev_info_1166_0230, + &pci_dev_info_1166_0234, + &pci_dev_info_1166_0240, + &pci_dev_info_1166_0241, + &pci_dev_info_1166_0242, + &pci_dev_info_1166_024a, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0102, + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_117c[] = { + &pci_dev_info_117c_0030, + NULL +}; +#endif +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0511, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + &pci_dev_info_1180_0554, + &pci_dev_info_1180_0575, + &pci_dev_info_1180_0576, + &pci_dev_info_1180_0592, + &pci_dev_info_1180_0811, + &pci_dev_info_1180_0822, + &pci_dev_info_1180_0841, + &pci_dev_info_1180_0852, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1025, + &pci_dev_info_1186_1026, + &pci_dev_info_1186_1043, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1541, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_2027, + &pci_dev_info_1186_3203, + &pci_dev_info_1186_3300, + &pci_dev_info_1186_3a03, + &pci_dev_info_1186_3a04, + &pci_dev_info_1186_3a05, + &pci_dev_info_1186_3a07, + &pci_dev_info_1186_3a08, + &pci_dev_info_1186_3a10, + &pci_dev_info_1186_3a11, + &pci_dev_info_1186_3a12, + &pci_dev_info_1186_3a13, + &pci_dev_info_1186_3a14, + &pci_dev_info_1186_3a63, + &pci_dev_info_1186_4000, + &pci_dev_info_1186_4300, + &pci_dev_info_1186_4c00, + &pci_dev_info_1186_8400, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + &pci_dev_info_1191_8060, + &pci_dev_info_1191_8080, + &pci_dev_info_1191_8081, + &pci_dev_info_1191_808a, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1197[] = { + &pci_dev_info_1197_010c, + NULL +}; +#endif +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_138f, + &pci_dev_info_11ab_1fa6, + &pci_dev_info_11ab_1fa7, + &pci_dev_info_11ab_1faa, + &pci_dev_info_11ab_4320, + &pci_dev_info_11ab_4340, + &pci_dev_info_11ab_4341, + &pci_dev_info_11ab_4342, + &pci_dev_info_11ab_4343, + &pci_dev_info_11ab_4344, + &pci_dev_info_11ab_4345, + &pci_dev_info_11ab_4346, + &pci_dev_info_11ab_4347, + &pci_dev_info_11ab_4350, + &pci_dev_info_11ab_4351, + &pci_dev_info_11ab_4352, + &pci_dev_info_11ab_4360, + &pci_dev_info_11ab_4361, + &pci_dev_info_11ab_4362, + &pci_dev_info_11ab_4363, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_5005, + &pci_dev_info_11ab_5040, + &pci_dev_info_11ab_5041, + &pci_dev_info_11ab_5080, + &pci_dev_info_11ab_5081, + &pci_dev_info_11ab_6041, + &pci_dev_info_11ab_6081, + &pci_dev_info_11ab_6460, + &pci_dev_info_11ab_6480, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11af[] = { + &pci_dev_info_11af_0001, + &pci_dev_info_11af_ee40, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bd[] = { + &pci_dev_info_11bd_bede, + NULL +}; +#endif +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_048c, + &pci_dev_info_11c1_048f, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + &pci_dev_info_11c1_8110, + &pci_dev_info_11c1_ab10, + &pci_dev_info_11c1_ab11, + &pci_dev_info_11c1_ab20, + &pci_dev_info_11c1_ab21, + &pci_dev_info_11c1_ab30, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1535, + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + &pci_dev_info_11d4_5340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_0001, + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_000d, + &pci_dev_info_11fe_000e, + &pci_dev_info_11fe_000f, + &pci_dev_info_11fe_0801, + &pci_dev_info_11fe_0802, + &pci_dev_info_11fe_0803, + &pci_dev_info_11fe_0805, + &pci_dev_info_11fe_080c, + &pci_dev_info_11fe_080d, + &pci_dev_info_11fe_0812, + &pci_dev_info_11fe_0903, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ff[] = { + &pci_dev_info_11ff_0003, + NULL +}; +#endif +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + &pci_dev_info_1217_7110, + &pci_dev_info_1217_7112, + &pci_dev_info_1217_7113, + &pci_dev_info_1217_7114, + &pci_dev_info_1217_7134, + &pci_dev_info_1217_71e2, + &pci_dev_info_1217_7212, + &pci_dev_info_1217_7213, + &pci_dev_info_1217_7223, + &pci_dev_info_1217_7233, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#define pci_dev_list_121e NULL +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1227[] = { + &pci_dev_info_1227_0006, + &pci_dev_info_1227_0023, + NULL +}; +#endif +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_1400, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + &pci_dev_info_1242_6562, + &pci_dev_info_1242_656a, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + &pci_dev_info_1244_2700, + &pci_dev_info_1244_2900, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + &pci_dev_info_1259_a117, + &pci_dev_info_1259_a120, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0101, + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3872, + &pci_dev_info_1260_3873, + &pci_dev_info_1260_3886, + &pci_dev_info_1260_3890, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + &pci_dev_info_1260_ffff, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_126c[] = { + &pci_dev_info_126c_1211, + &pci_dev_info_126c_126c, + NULL +}; +#endif +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0501, + &pci_dev_info_126f_0510, + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0730, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1171, + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + &pci_dev_info_1278_0710, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0060, + &pci_dev_info_1279_0061, + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8211, + &pci_dev_info_1283_8212, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8872, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12a3[] = { + &pci_dev_info_12a3_8105, + NULL +}; +#endif +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_0000, + &pci_dev_info_12ab_0002, + &pci_dev_info_12ab_3000, + &pci_dev_info_12ab_fff3, + &pci_dev_info_12ab_ffff, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + &pci_dev_info_12ae_00fa, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c4[] = { + &pci_dev_info_12c4_0001, + &pci_dev_info_12c4_0002, + &pci_dev_info_12c4_0003, + &pci_dev_info_12c4_0004, + &pci_dev_info_12c4_0005, + &pci_dev_info_12c4_0006, + &pci_dev_info_12c4_0007, + &pci_dev_info_12c4_0008, + &pci_dev_info_12c4_0009, + &pci_dev_info_12c4_000a, + &pci_dev_info_12c4_000b, + &pci_dev_info_12c4_000c, + &pci_dev_info_12c4_000d, + &pci_dev_info_12c4_0100, + &pci_dev_info_12c4_0201, + &pci_dev_info_12c4_0202, + &pci_dev_info_12c4_0300, + &pci_dev_info_12c4_0301, + &pci_dev_info_12c4_0302, + &pci_dev_info_12c4_0310, + &pci_dev_info_12c4_0311, + &pci_dev_info_12c4_0312, + &pci_dev_info_12c4_0320, + &pci_dev_info_12c4_0321, + &pci_dev_info_12c4_0322, + &pci_dev_info_12c4_0330, + &pci_dev_info_12c4_0331, + &pci_dev_info_12c4_0332, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d4[] = { + &pci_dev_info_12d4_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d5[] = { + &pci_dev_info_12d5_0003, + &pci_dev_info_12d5_1000, + NULL +}; +#endif +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d8[] = { + &pci_dev_info_12d8_8150, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d9[] = { + &pci_dev_info_12d9_0002, + &pci_dev_info_12d9_0004, + &pci_dev_info_12d9_0005, + NULL +}; +#endif +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12de[] = { + &pci_dev_info_12de_0200, + NULL +}; +#endif +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12fb[] = { + &pci_dev_info_12fb_0001, + &pci_dev_info_12fb_00f5, + &pci_dev_info_12fb_02ad, + &pci_dev_info_12fb_2adc, + &pci_dev_info_12fb_3100, + &pci_dev_info_12fb_3500, + &pci_dev_info_12fb_4d4f, + &pci_dev_info_12fb_8120, + &pci_dev_info_12fb_da62, + &pci_dev_info_12fb_db62, + &pci_dev_info_12fb_dc62, + &pci_dev_info_12fb_dd62, + &pci_dev_info_12fb_eddc, + &pci_dev_info_12fb_fa01, + NULL +}; +#endif +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + &pci_dev_info_1307_004d, + &pci_dev_info_1307_0052, + &pci_dev_info_1307_0054, + &pci_dev_info_1307_005e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + &pci_dev_info_1317_2850, + &pci_dev_info_1317_5120, + &pci_dev_info_1317_8201, + &pci_dev_info_1317_8211, + &pci_dev_info_1317_9511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + &pci_dev_info_131f_2081, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1331[] = { + &pci_dev_info_1331_0030, + &pci_dev_info_1331_8200, + &pci_dev_info_1331_8201, + &pci_dev_info_1331_8202, + &pci_dev_info_1331_8210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + &pci_dev_info_1332_5425, + &pci_dev_info_1332_6140, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_2189, + &pci_dev_info_134d_2486, + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_5101, + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1360[] = { + &pci_dev_info_1360_0101, + &pci_dev_info_1360_0102, + &pci_dev_info_1360_0103, + &pci_dev_info_1360_0201, + &pci_dev_info_1360_0202, + &pci_dev_info_1360_0203, + &pci_dev_info_1360_0301, + &pci_dev_info_1360_0302, + NULL +}; +#endif +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#define pci_dev_list_136a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136b[] = { + &pci_dev_info_136b_ff01, + NULL +}; +#endif +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1371[] = { + &pci_dev_info_1371_434e, + NULL +}; +#endif +#define pci_dev_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1374[] = { + &pci_dev_info_1374_0024, + &pci_dev_info_1374_0025, + &pci_dev_info_1374_0026, + &pci_dev_info_1374_0027, + &pci_dev_info_1374_0029, + &pci_dev_info_1374_002a, + &pci_dev_info_1374_002b, + &pci_dev_info_1374_002c, + &pci_dev_info_1374_002d, + &pci_dev_info_1374_002e, + &pci_dev_info_1374_002f, + &pci_dev_info_1374_0030, + &pci_dev_info_1374_0031, + &pci_dev_info_1374_0032, + &pci_dev_info_1374_0034, + &pci_dev_info_1374_0035, + &pci_dev_info_1374_0036, + &pci_dev_info_1374_0037, + &pci_dev_info_1374_0038, + &pci_dev_info_1374_0039, + &pci_dev_info_1374_003a, + NULL +}; +#endif +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_137a[] = { + &pci_dev_info_137a_0001, + NULL +}; +#endif +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1382[] = { + &pci_dev_info_1382_0001, + &pci_dev_info_1382_2008, + &pci_dev_info_1382_2088, + &pci_dev_info_1382_20c8, + &pci_dev_info_1382_4008, + &pci_dev_info_1382_4010, + &pci_dev_info_1382_4048, + &pci_dev_info_1382_4088, + &pci_dev_info_1382_4248, + NULL +}; +#endif +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_0013, + &pci_dev_info_1385_311a, + &pci_dev_info_1385_4100, + &pci_dev_info_1385_4105, + &pci_dev_info_1385_4400, + &pci_dev_info_1385_4600, + &pci_dev_info_1385_4601, + &pci_dev_info_1385_4610, + &pci_dev_info_1385_4800, + &pci_dev_info_1385_4900, + &pci_dev_info_1385_4a00, + &pci_dev_info_1385_4b00, + &pci_dev_info_1385_4c00, + &pci_dev_info_1385_4e00, + &pci_dev_info_1385_4f00, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_6b00, + &pci_dev_info_1385_f004, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1141, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_16b8, + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + &pci_dev_info_13a3_001d, + &pci_dev_info_13a3_0020, + &pci_dev_info_13a3_0026, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0152, + &pci_dev_info_13a8_0154, + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + &pci_dev_info_13c0_0020, + &pci_dev_info_13c0_0030, + &pci_dev_info_13c0_0210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + &pci_dev_info_13c1_1003, + NULL +}; +#endif +#define pci_dev_list_13c2 NULL +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c6[] = { + &pci_dev_info_13c6_0520, + &pci_dev_info_13c6_0620, + &pci_dev_info_13c6_0820, + NULL +}; +#endif +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + &pci_dev_info_13d0_2200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab03, + &pci_dev_info_13d1_ab06, + &pci_dev_info_13d1_ab08, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#define pci_dev_list_13ec NULL +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0200, + &pci_dev_info_13f0_0201, + &pci_dev_info_13f0_1023, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0011, + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1240, + &pci_dev_info_13fe_1600, + &pci_dev_info_13fe_1733, + &pci_dev_info_13fe_1752, + &pci_dev_info_13fe_1754, + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0110, + &pci_dev_info_1407_0111, + &pci_dev_info_1407_0120, + &pci_dev_info_1407_0121, + &pci_dev_info_1407_0180, + &pci_dev_info_1407_0181, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0220, + &pci_dev_info_1407_0221, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9510, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9521, + &pci_dev_info_1415_9523, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1420[] = { + &pci_dev_info_1420_8002, + &pci_dev_info_1420_8003, + NULL +}; +#endif +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1425[] = { + &pci_dev_info_1425_000b, + NULL +}; +#endif +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_142e[] = { + &pci_dev_info_142e_4020, + &pci_dev_info_142e_4337, + NULL +}; +#endif +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1432[] = { + &pci_dev_info_1432_9130, + NULL +}; +#endif +#define pci_dev_list_1433 NULL +#define pci_dev_list_1435 NULL +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8164, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#define pci_dev_list_144d NULL +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1458[] = { + &pci_dev_info_1458_0c11, + &pci_dev_info_1458_e911, + NULL +}; +#endif +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1461[] = { + &pci_dev_info_1461_a3ce, + &pci_dev_info_1461_a3cf, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1462[] = { + &pci_dev_info_1462_5501, + &pci_dev_info_1462_6819, + &pci_dev_info_1462_6825, + &pci_dev_info_1462_8725, + &pci_dev_info_1462_9000, + &pci_dev_info_1462_9110, + &pci_dev_info_1462_9119, + &pci_dev_info_1462_9591, + NULL +}; +#endif +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_146c[] = { + &pci_dev_info_146c_1430, + NULL +}; +#endif +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1497[] = { + &pci_dev_info_1497_1497, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1498[] = { + &pci_dev_info_1498_21cd, + &pci_dev_info_1498_30c8, + NULL +}; +#endif +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_149d[] = { + &pci_dev_info_149d_0001, + NULL +}; +#endif +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + &pci_dev_info_14b9_a505, + &pci_dev_info_14b9_a506, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#define pci_dev_list_14bc NULL +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14c1[] = { + &pci_dev_info_14c1_8043, + NULL +}; +#endif +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d9[] = { + &pci_dev_info_14d9_0010, + &pci_dev_info_14d9_9000, + NULL +}; +#endif +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_0800, + &pci_dev_info_14e4_0804, + &pci_dev_info_14e4_0805, + &pci_dev_info_14e4_0806, + &pci_dev_info_14e4_080b, + &pci_dev_info_14e4_080f, + &pci_dev_info_14e4_0811, + &pci_dev_info_14e4_0816, + &pci_dev_info_14e4_1600, + &pci_dev_info_14e4_1601, + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164a, + &pci_dev_info_14e4_164c, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_1654, + &pci_dev_info_14e4_1659, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_165e, + &pci_dev_info_14e4_1668, + &pci_dev_info_14e4_166a, + &pci_dev_info_14e4_166b, + &pci_dev_info_14e4_166e, + &pci_dev_info_14e4_1677, + &pci_dev_info_14e4_1678, + &pci_dev_info_14e4_167d, + &pci_dev_info_14e4_167e, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_169c, + &pci_dev_info_14e4_169d, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16aa, + &pci_dev_info_14e4_16ac, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_16dd, + &pci_dev_info_14e4_16f7, + &pci_dev_info_14e4_16fd, + &pci_dev_info_14e4_16fe, + &pci_dev_info_14e4_170c, + &pci_dev_info_14e4_170d, + &pci_dev_info_14e4_170e, + &pci_dev_info_14e4_3352, + &pci_dev_info_14e4_3360, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4305, + &pci_dev_info_14e4_4306, + &pci_dev_info_14e4_4307, + &pci_dev_info_14e4_4310, + &pci_dev_info_14e4_4312, + &pci_dev_info_14e4_4313, + &pci_dev_info_14e4_4315, + &pci_dev_info_14e4_4318, + &pci_dev_info_14e4_4319, + &pci_dev_info_14e4_4320, + &pci_dev_info_14e4_4321, + &pci_dev_info_14e4_4322, + &pci_dev_info_14e4_4324, + &pci_dev_info_14e4_4325, + &pci_dev_info_14e4_4326, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4403, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_4430, + &pci_dev_info_14e4_4432, + &pci_dev_info_14e4_4610, + &pci_dev_info_14e4_4611, + &pci_dev_info_14e4_4612, + &pci_dev_info_14e4_4613, + &pci_dev_info_14e4_4614, + &pci_dev_info_14e4_4615, + &pci_dev_info_14e4_4704, + &pci_dev_info_14e4_4705, + &pci_dev_info_14e4_4706, + &pci_dev_info_14e4_4707, + &pci_dev_info_14e4_4708, + &pci_dev_info_14e4_4710, + &pci_dev_info_14e4_4711, + &pci_dev_info_14e4_4712, + &pci_dev_info_14e4_4713, + &pci_dev_info_14e4_4714, + &pci_dev_info_14e4_4715, + &pci_dev_info_14e4_4716, + &pci_dev_info_14e4_4717, + &pci_dev_info_14e4_4718, + &pci_dev_info_14e4_4720, + &pci_dev_info_14e4_5365, + &pci_dev_info_14e4_5600, + &pci_dev_info_14e4_5605, + &pci_dev_info_14e4_5615, + &pci_dev_info_14e4_5625, + &pci_dev_info_14e4_5645, + &pci_dev_info_14e4_5670, + &pci_dev_info_14e4_5680, + &pci_dev_info_14e4_5690, + &pci_dev_info_14e4_5691, + &pci_dev_info_14e4_5692, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + &pci_dev_info_14e4_5822, + &pci_dev_info_14e4_5823, + &pci_dev_info_14e4_5824, + &pci_dev_info_14e4_5840, + &pci_dev_info_14e4_5841, + &pci_dev_info_14e4_5850, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + &pci_dev_info_14ea_ab07, + &pci_dev_info_14ea_ab08, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1085, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1620, + &pci_dev_info_14f1_1621, + &pci_dev_info_14f1_1622, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1811, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_2f02, + &pci_dev_info_14f1_2f11, + &pci_dev_info_14f1_2f20, + &pci_dev_info_14f1_8234, + &pci_dev_info_14f1_8800, + &pci_dev_info_14f1_8801, + &pci_dev_info_14f1_8802, + &pci_dev_info_14f1_8804, + &pci_dev_info_14f1_8811, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f2[] = { + &pci_dev_info_14f2_0120, + &pci_dev_info_14f2_0121, + &pci_dev_info_14f2_0122, + &pci_dev_info_14f2_0123, + &pci_dev_info_14f2_0124, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f3[] = { + &pci_dev_info_14f3_2030, + &pci_dev_info_14f3_2050, + &pci_dev_info_14f3_2060, + NULL +}; +#endif +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f8[] = { + &pci_dev_info_14f8_2077, + NULL +}; +#endif +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14fc[] = { + &pci_dev_info_14fc_0000, + &pci_dev_info_14fc_0001, + NULL +}; +#endif +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1500[] = { + &pci_dev_info_1500_1360, + NULL +}; +#endif +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0800, + &pci_dev_info_1516_0803, + &pci_dev_info_1516_0891, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151c[] = { + &pci_dev_info_151c_0003, + &pci_dev_info_151c_4000, + NULL +}; +#endif +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_0510, + &pci_dev_info_1524_0520, + &pci_dev_info_1524_0530, + &pci_dev_info_1524_0550, + &pci_dev_info_1524_0610, + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1411, + &pci_dev_info_1524_1412, + &pci_dev_info_1524_1420, + &pci_dev_info_1524_1421, + &pci_dev_info_1524_1422, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#define pci_dev_list_1532 NULL +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1538[] = { + &pci_dev_info_1538_0303, + NULL +}; +#endif +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153b[] = { + &pci_dev_info_153b_1144, + &pci_dev_info_153b_1147, + &pci_dev_info_153b_1158, + NULL +}; +#endif +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153f[] = { + &pci_dev_info_153f_0001, + NULL +}; +#endif +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#define pci_dev_list_1542 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1578[] = { + &pci_dev_info_1578_5615, + NULL +}; +#endif +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0405, + &pci_dev_info_15ad_0710, + &pci_dev_info_15ad_0720, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + &pci_dev_info_15b3_5a44, + &pci_dev_info_15b3_5a45, + &pci_dev_info_15b3_5a46, + &pci_dev_info_15b3_5e8d, + &pci_dev_info_15b3_6274, + &pci_dev_info_15b3_6278, + &pci_dev_info_15b3_6279, + &pci_dev_info_15b3_6282, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_1100, + &pci_dev_info_15bc_2922, + &pci_dev_info_15bc_2928, + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c5[] = { + &pci_dev_info_15c5_8010, + NULL +}; +#endif +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e9[] = { + &pci_dev_info_15e9_1841, + NULL +}; +#endif +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15ec[] = { + &pci_dev_info_15ec_3101, + &pci_dev_info_15ec_5102, + NULL +}; +#endif +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + &pci_dev_info_1619_0610, + &pci_dev_info_1619_0620, + &pci_dev_info_1619_0640, + &pci_dev_info_1619_1610, + &pci_dev_info_1619_2610, + NULL +}; +#endif +#define pci_dev_list_161f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1626[] = { + &pci_dev_info_1626_8410, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1637[] = { + &pci_dev_info_1637_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_3052, + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165f[] = { + &pci_dev_info_165f_1020, + NULL +}; +#endif +#define pci_dev_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1668[] = { + &pci_dev_info_1668_0100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_166d[] = { + &pci_dev_info_166d_0001, + &pci_dev_info_166d_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1677[] = { + &pci_dev_info_1677_104e, + &pci_dev_info_1677_12d7, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167b[] = { + &pci_dev_info_167b_2102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1681[] = { + &pci_dev_info_1681_0010, + NULL +}; +#endif +#define pci_dev_list_1682 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1688[] = { + &pci_dev_info_1688_1170, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_168c[] = { + &pci_dev_info_168c_0007, + &pci_dev_info_168c_0011, + &pci_dev_info_168c_0012, + &pci_dev_info_168c_0013, + &pci_dev_info_168c_001a, + &pci_dev_info_168c_001b, + &pci_dev_info_168c_0020, + &pci_dev_info_168c_1014, + NULL +}; +#endif +#define pci_dev_list_1695 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_169c[] = { + &pci_dev_info_169c_0044, + NULL +}; +#endif +#define pci_dev_list_16a5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1100, + &pci_dev_info_16ab_1101, + &pci_dev_info_16ab_1102, + &pci_dev_info_16ab_8501, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ae[] = { + &pci_dev_info_16ae_1141, + NULL +}; +#endif +#define pci_dev_list_16af NULL +#define pci_dev_list_16b4 NULL +#define pci_dev_list_16b8 NULL +#define pci_dev_list_16be NULL +#define pci_dev_list_16c8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ca[] = { + &pci_dev_info_16ca_0001, + NULL +}; +#endif +#define pci_dev_list_16cd NULL +#define pci_dev_list_16ce NULL +#define pci_dev_list_16df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e3[] = { + &pci_dev_info_16e3_1e0f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_00ff, + &pci_dev_info_16ec_0116, + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ed[] = { + &pci_dev_info_16ed_1001, + NULL +}; +#endif +#define pci_dev_list_16f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16f4[] = { + &pci_dev_info_16f4_8000, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1702 NULL +#define pci_dev_list_1705 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_170b[] = { + &pci_dev_info_170b_0100, + NULL +}; +#endif +#define pci_dev_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1725[] = { + &pci_dev_info_1725_7174, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_172a[] = { + &pci_dev_info_172a_13c8, + NULL +}; +#endif +#define pci_dev_list_1734 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1737[] = { + &pci_dev_info_1737_0013, + &pci_dev_info_1737_0015, + &pci_dev_info_1737_1032, + &pci_dev_info_1737_1064, + &pci_dev_info_1737_ab08, + &pci_dev_info_1737_ab09, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03e9, + &pci_dev_info_173b_03ea, + &pci_dev_info_173b_03eb, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_1749 NULL +#define pci_dev_list_174b NULL +#define pci_dev_list_174d NULL +#define pci_dev_list_175c NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1775 NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1799[] = { + &pci_dev_info_1799_6001, + &pci_dev_info_1799_6020, + &pci_dev_info_1799_6060, + &pci_dev_info_1799_7000, + &pci_dev_info_1799_7010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_179c[] = { + &pci_dev_info_179c_0557, + &pci_dev_info_179c_0566, + &pci_dev_info_179c_5031, + &pci_dev_info_179c_5121, + &pci_dev_info_179c_5211, + &pci_dev_info_179c_5679, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17a0[] = { + &pci_dev_info_17a0_8033, + &pci_dev_info_17a0_8034, + NULL +}; +#endif +#define pci_dev_list_17aa NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b3[] = { + &pci_dev_info_17b3_ab08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b4[] = { + &pci_dev_info_17b4_0011, + NULL +}; +#endif +#define pci_dev_list_17c0 NULL +#define pci_dev_list_17c2 NULL +#define pci_dev_list_17cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#define pci_dev_list_17cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d3[] = { + &pci_dev_info_17d3_1110, + &pci_dev_info_17d3_1120, + &pci_dev_info_17d3_1130, + &pci_dev_info_17d3_1160, + &pci_dev_info_17d3_1210, + &pci_dev_info_17d3_1220, + &pci_dev_info_17d3_1230, + &pci_dev_info_17d3_1260, + &pci_dev_info_17d3_5831, + &pci_dev_info_17d3_5832, + NULL +}; +#endif +#define pci_dev_list_17de NULL +#define pci_dev_list_17ee NULL +#define pci_dev_list_17f2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17fe[] = { + &pci_dev_info_17fe_2120, + &pci_dev_info_17fe_2220, + NULL +}; +#endif +#define pci_dev_list_17ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1814[] = { + &pci_dev_info_1814_0101, + &pci_dev_info_1814_0201, + &pci_dev_info_1814_0401, + NULL +}; +#endif +#define pci_dev_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1822[] = { + &pci_dev_info_1822_4e35, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182d[] = { + &pci_dev_info_182d_3069, + &pci_dev_info_182d_9790, + NULL +}; +#endif +#define pci_dev_list_1830 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_183b[] = { + &pci_dev_info_183b_08a7, + &pci_dev_info_183b_08a8, + &pci_dev_info_183b_08a9, + NULL +}; +#endif +#define pci_dev_list_1849 NULL +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#define pci_dev_list_1854 NULL +#define pci_dev_list_185b NULL +#define pci_dev_list_185f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1864[] = { + &pci_dev_info_1864_2110, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1867[] = { + &pci_dev_info_1867_5a44, + &pci_dev_info_1867_5a45, + &pci_dev_info_1867_5a46, + &pci_dev_info_1867_6278, + &pci_dev_info_1867_6282, + NULL +}; +#endif +#define pci_dev_list_187e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#define pci_dev_list_1894 NULL +#define pci_dev_list_1896 NULL +#define pci_dev_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ac[] = { + &pci_dev_info_18ac_d500, + &pci_dev_info_18ac_d810, + &pci_dev_info_18ac_d820, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18b8[] = { + &pci_dev_info_18b8_b001, + NULL +}; +#endif +#define pci_dev_list_18bc NULL +#define pci_dev_list_18c8 NULL +#define pci_dev_list_18c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ca[] = { + &pci_dev_info_18ca_0020, + &pci_dev_info_18ca_0040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18d2[] = { + &pci_dev_info_18d2_3069, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18dd[] = { + &pci_dev_info_18dd_4c6f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18e6[] = { + &pci_dev_info_18e6_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ec[] = { + &pci_dev_info_18ec_c006, + &pci_dev_info_18ec_c045, + &pci_dev_info_18ec_c050, + &pci_dev_info_18ec_c058, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f7[] = { + &pci_dev_info_18f7_0001, + &pci_dev_info_18f7_0002, + &pci_dev_info_18f7_0004, + &pci_dev_info_18f7_0005, + &pci_dev_info_18f7_000a, + NULL +}; +#endif +#define pci_dev_list_18fb NULL +#define pci_dev_list_1924 NULL +#define pci_dev_list_192e NULL +#define pci_dev_list_1931 NULL +#define pci_dev_list_1942 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1957[] = { + &pci_dev_info_1957_0080, + &pci_dev_info_1957_0081, + &pci_dev_info_1957_0082, + &pci_dev_info_1957_0083, + &pci_dev_info_1957_0084, + &pci_dev_info_1957_0085, + &pci_dev_info_1957_0086, + &pci_dev_info_1957_0087, + NULL +}; +#endif +#define pci_dev_list_1958 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1966[] = { + &pci_dev_info_1966_1975, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_196a[] = { + &pci_dev_info_196a_0101, + &pci_dev_info_196a_0102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_197b[] = { + &pci_dev_info_197b_2360, + &pci_dev_info_197b_2363, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1989[] = { + &pci_dev_info_1989_0001, + &pci_dev_info_1989_8001, + NULL +}; +#endif +#define pci_dev_list_1993 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ae[] = { + &pci_dev_info_19ae_0520, + NULL +}; +#endif +#define pci_dev_list_19d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc0[] = { + &pci_dev_info_1fc0_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc1[] = { + &pci_dev_info_1fc1_000d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fce[] = { + &pci_dev_info_1fce_0001, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0020, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_0022, + &pci_dev_info_3388_0026, + &pci_dev_info_3388_101a, + &pci_dev_info_3388_101b, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3842[] = { + &pci_dev_info_3842_c370, + NULL +}; +#endif +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_000d, + &pci_dev_info_3d3d_0011, + &pci_dev_info_3d3d_0012, + &pci_dev_info_3d3d_0013, + &pci_dev_info_3d3d_0020, + &pci_dev_info_3d3d_0022, + &pci_dev_info_3d3d_0024, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_07a1, + &pci_dev_info_3d3d_07a2, + &pci_dev_info_3d3d_07a3, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4144[] = { + &pci_dev_info_4144_0044, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0016, + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_494f[] = { + &pci_dev_info_494f_10e8, + NULL +}; +#endif +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4c53[] = { + &pci_dev_info_4c53_0000, + &pci_dev_info_4c53_0001, + NULL +}; +#endif +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5168[] = { + &pci_dev_info_5168_0301, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_544c[] = { + &pci_dev_info_544c_0350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5654[] = { + &pci_dev_info_5654_3132, + NULL +}; +#endif +#define pci_dev_list_5700 NULL +#define pci_dev_list_5851 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + &pci_dev_info_6666_0004, + &pci_dev_info_6666_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_7063[] = { + &pci_dev_info_7063_2000, + &pci_dev_info_7063_3000, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +#define pci_dev_list_807d NULL +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0309, + &pci_dev_info_8086_030d, + &pci_dev_info_8086_0326, + &pci_dev_info_8086_0327, + &pci_dev_info_8086_0329, + &pci_dev_info_8086_032a, + &pci_dev_info_8086_032c, + &pci_dev_info_8086_0330, + &pci_dev_info_8086_0331, + &pci_dev_info_8086_0332, + &pci_dev_info_8086_0333, + &pci_dev_info_8086_0334, + &pci_dev_info_8086_0335, + &pci_dev_info_8086_0336, + &pci_dev_info_8086_0340, + &pci_dev_info_8086_0341, + &pci_dev_info_8086_0370, + &pci_dev_info_8086_0371, + &pci_dev_info_8086_0372, + &pci_dev_info_8086_0373, + &pci_dev_info_8086_0374, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0500, + &pci_dev_info_8086_0501, + &pci_dev_info_8086_0502, + &pci_dev_info_8086_0503, + &pci_dev_info_8086_0510, + &pci_dev_info_8086_0511, + &pci_dev_info_8086_0512, + &pci_dev_info_8086_0513, + &pci_dev_info_8086_0514, + &pci_dev_info_8086_0515, + &pci_dev_info_8086_0516, + &pci_dev_info_8086_0530, + &pci_dev_info_8086_0531, + &pci_dev_info_8086_0532, + &pci_dev_info_8086_0533, + &pci_dev_info_8086_0534, + &pci_dev_info_8086_0535, + &pci_dev_info_8086_0536, + &pci_dev_info_8086_0537, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_061f, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100a, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1013, + &pci_dev_info_8086_1014, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1016, + &pci_dev_info_8086_1017, + &pci_dev_info_8086_1018, + &pci_dev_info_8086_1019, + &pci_dev_info_8086_101a, + &pci_dev_info_8086_101d, + &pci_dev_info_8086_101e, + &pci_dev_info_8086_1026, + &pci_dev_info_8086_1027, + &pci_dev_info_8086_1028, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1043, + &pci_dev_info_8086_1048, + &pci_dev_info_8086_1050, + &pci_dev_info_8086_1051, + &pci_dev_info_8086_1052, + &pci_dev_info_8086_1053, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_105e, + &pci_dev_info_8086_105f, + &pci_dev_info_8086_1060, + &pci_dev_info_8086_1064, + &pci_dev_info_8086_1065, + &pci_dev_info_8086_1066, + &pci_dev_info_8086_1067, + &pci_dev_info_8086_1068, + &pci_dev_info_8086_1069, + &pci_dev_info_8086_106a, + &pci_dev_info_8086_106b, + &pci_dev_info_8086_1075, + &pci_dev_info_8086_1076, + &pci_dev_info_8086_1077, + &pci_dev_info_8086_1078, + &pci_dev_info_8086_1079, + &pci_dev_info_8086_107a, + &pci_dev_info_8086_107b, + &pci_dev_info_8086_107c, + &pci_dev_info_8086_107d, + &pci_dev_info_8086_107e, + &pci_dev_info_8086_107f, + &pci_dev_info_8086_1080, + &pci_dev_info_8086_1081, + &pci_dev_info_8086_1082, + &pci_dev_info_8086_1083, + &pci_dev_info_8086_1084, + &pci_dev_info_8086_1085, + &pci_dev_info_8086_1086, + &pci_dev_info_8086_1087, + &pci_dev_info_8086_1089, + &pci_dev_info_8086_108a, + &pci_dev_info_8086_108b, + &pci_dev_info_8086_108c, + &pci_dev_info_8086_1096, + &pci_dev_info_8086_1097, + &pci_dev_info_8086_1098, + &pci_dev_info_8086_1099, + &pci_dev_info_8086_109a, + &pci_dev_info_8086_1107, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123e, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_1a38, + &pci_dev_info_8086_1a48, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c1, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24ca, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cc, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_24d0, + &pci_dev_info_8086_24d1, + &pci_dev_info_8086_24d2, + &pci_dev_info_8086_24d3, + &pci_dev_info_8086_24d4, + &pci_dev_info_8086_24d5, + &pci_dev_info_8086_24d6, + &pci_dev_info_8086_24d7, + &pci_dev_info_8086_24db, + &pci_dev_info_8086_24dc, + &pci_dev_info_8086_24dd, + &pci_dev_info_8086_24de, + &pci_dev_info_8086_24df, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_254c, + &pci_dev_info_8086_2550, + &pci_dev_info_8086_2551, + &pci_dev_info_8086_2552, + &pci_dev_info_8086_2553, + &pci_dev_info_8086_2554, + &pci_dev_info_8086_255d, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2571, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_2573, + &pci_dev_info_8086_2576, + &pci_dev_info_8086_2578, + &pci_dev_info_8086_2579, + &pci_dev_info_8086_257b, + &pci_dev_info_8086_257e, + &pci_dev_info_8086_2580, + &pci_dev_info_8086_2581, + &pci_dev_info_8086_2582, + &pci_dev_info_8086_2584, + &pci_dev_info_8086_2585, + &pci_dev_info_8086_2588, + &pci_dev_info_8086_2589, + &pci_dev_info_8086_258a, + &pci_dev_info_8086_2590, + &pci_dev_info_8086_2591, + &pci_dev_info_8086_2592, + &pci_dev_info_8086_25a1, + &pci_dev_info_8086_25a2, + &pci_dev_info_8086_25a3, + &pci_dev_info_8086_25a4, + &pci_dev_info_8086_25a6, + &pci_dev_info_8086_25a7, + &pci_dev_info_8086_25a9, + &pci_dev_info_8086_25aa, + &pci_dev_info_8086_25ab, + &pci_dev_info_8086_25ac, + &pci_dev_info_8086_25ad, + &pci_dev_info_8086_25ae, + &pci_dev_info_8086_25b0, + &pci_dev_info_8086_25c0, + &pci_dev_info_8086_25d0, + &pci_dev_info_8086_25d4, + &pci_dev_info_8086_25d8, + &pci_dev_info_8086_25e2, + &pci_dev_info_8086_25e3, + &pci_dev_info_8086_25e4, + &pci_dev_info_8086_25e5, + &pci_dev_info_8086_25e6, + &pci_dev_info_8086_25e7, + &pci_dev_info_8086_25e8, + &pci_dev_info_8086_25f0, + &pci_dev_info_8086_25f1, + &pci_dev_info_8086_25f3, + &pci_dev_info_8086_25f5, + &pci_dev_info_8086_25f6, + &pci_dev_info_8086_25f7, + &pci_dev_info_8086_25f8, + &pci_dev_info_8086_25f9, + &pci_dev_info_8086_25fa, + &pci_dev_info_8086_2600, + &pci_dev_info_8086_2601, + &pci_dev_info_8086_2602, + &pci_dev_info_8086_2603, + &pci_dev_info_8086_2604, + &pci_dev_info_8086_2605, + &pci_dev_info_8086_2606, + &pci_dev_info_8086_2607, + &pci_dev_info_8086_2608, + &pci_dev_info_8086_2609, + &pci_dev_info_8086_260a, + &pci_dev_info_8086_260c, + &pci_dev_info_8086_2610, + &pci_dev_info_8086_2611, + &pci_dev_info_8086_2612, + &pci_dev_info_8086_2613, + &pci_dev_info_8086_2614, + &pci_dev_info_8086_2615, + &pci_dev_info_8086_2617, + &pci_dev_info_8086_2618, + &pci_dev_info_8086_2619, + &pci_dev_info_8086_261a, + &pci_dev_info_8086_261b, + &pci_dev_info_8086_261c, + &pci_dev_info_8086_261d, + &pci_dev_info_8086_261e, + &pci_dev_info_8086_2620, + &pci_dev_info_8086_2621, + &pci_dev_info_8086_2622, + &pci_dev_info_8086_2623, + &pci_dev_info_8086_2624, + &pci_dev_info_8086_2625, + &pci_dev_info_8086_2626, + &pci_dev_info_8086_2627, + &pci_dev_info_8086_2640, + &pci_dev_info_8086_2641, + &pci_dev_info_8086_2642, + &pci_dev_info_8086_2651, + &pci_dev_info_8086_2652, + &pci_dev_info_8086_2653, + &pci_dev_info_8086_2658, + &pci_dev_info_8086_2659, + &pci_dev_info_8086_265a, + &pci_dev_info_8086_265b, + &pci_dev_info_8086_265c, + &pci_dev_info_8086_2660, + &pci_dev_info_8086_2662, + &pci_dev_info_8086_2664, + &pci_dev_info_8086_2666, + &pci_dev_info_8086_2668, + &pci_dev_info_8086_266a, + &pci_dev_info_8086_266c, + &pci_dev_info_8086_266d, + &pci_dev_info_8086_266e, + &pci_dev_info_8086_266f, + &pci_dev_info_8086_2670, + &pci_dev_info_8086_2680, + &pci_dev_info_8086_2681, + &pci_dev_info_8086_2682, + &pci_dev_info_8086_2683, + &pci_dev_info_8086_2688, + &pci_dev_info_8086_2689, + &pci_dev_info_8086_268a, + &pci_dev_info_8086_268b, + &pci_dev_info_8086_268c, + &pci_dev_info_8086_2690, + &pci_dev_info_8086_2692, + &pci_dev_info_8086_2694, + &pci_dev_info_8086_2696, + &pci_dev_info_8086_2698, + &pci_dev_info_8086_2699, + &pci_dev_info_8086_269a, + &pci_dev_info_8086_269b, + &pci_dev_info_8086_269e, + &pci_dev_info_8086_2770, + &pci_dev_info_8086_2771, + &pci_dev_info_8086_2772, + &pci_dev_info_8086_2774, + &pci_dev_info_8086_2775, + &pci_dev_info_8086_2776, + &pci_dev_info_8086_2778, + &pci_dev_info_8086_2779, + &pci_dev_info_8086_277a, + &pci_dev_info_8086_277c, + &pci_dev_info_8086_277d, + &pci_dev_info_8086_2782, + &pci_dev_info_8086_2792, + &pci_dev_info_8086_27a0, + &pci_dev_info_8086_27a1, + &pci_dev_info_8086_27a2, + &pci_dev_info_8086_27a6, + &pci_dev_info_8086_27b0, + &pci_dev_info_8086_27b8, + &pci_dev_info_8086_27b9, + &pci_dev_info_8086_27bd, + &pci_dev_info_8086_27c0, + &pci_dev_info_8086_27c1, + &pci_dev_info_8086_27c3, + &pci_dev_info_8086_27c4, + &pci_dev_info_8086_27c5, + &pci_dev_info_8086_27c6, + &pci_dev_info_8086_27c8, + &pci_dev_info_8086_27c9, + &pci_dev_info_8086_27ca, + &pci_dev_info_8086_27cb, + &pci_dev_info_8086_27cc, + &pci_dev_info_8086_27d0, + &pci_dev_info_8086_27d2, + &pci_dev_info_8086_27d4, + &pci_dev_info_8086_27d6, + &pci_dev_info_8086_27d8, + &pci_dev_info_8086_27da, + &pci_dev_info_8086_27dc, + &pci_dev_info_8086_27dd, + &pci_dev_info_8086_27de, + &pci_dev_info_8086_27df, + &pci_dev_info_8086_27e0, + &pci_dev_info_8086_27e2, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3200, + &pci_dev_info_8086_3340, + &pci_dev_info_8086_3341, + &pci_dev_info_8086_3500, + &pci_dev_info_8086_3501, + &pci_dev_info_8086_3504, + &pci_dev_info_8086_3505, + &pci_dev_info_8086_350c, + &pci_dev_info_8086_350d, + &pci_dev_info_8086_3510, + &pci_dev_info_8086_3511, + &pci_dev_info_8086_3514, + &pci_dev_info_8086_3515, + &pci_dev_info_8086_3518, + &pci_dev_info_8086_3519, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3581, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_3584, + &pci_dev_info_8086_3585, + &pci_dev_info_8086_3590, + &pci_dev_info_8086_3591, + &pci_dev_info_8086_3592, + &pci_dev_info_8086_3593, + &pci_dev_info_8086_3594, + &pci_dev_info_8086_3595, + &pci_dev_info_8086_3596, + &pci_dev_info_8086_3597, + &pci_dev_info_8086_3598, + &pci_dev_info_8086_3599, + &pci_dev_info_8086_359a, + &pci_dev_info_8086_359b, + &pci_dev_info_8086_359e, + &pci_dev_info_8086_4220, + &pci_dev_info_8086_4223, + &pci_dev_info_8086_4224, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7050, + &pci_dev_info_8086_7051, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_8500, + &pci_dev_info_8086_9000, + &pci_dev_info_8086_9001, + &pci_dev_info_8086_9004, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + NULL +}; +#define pci_dev_list_8401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8912 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8c4a[] = { + &pci_dev_info_8c4a_1980, + NULL +}; +#endif +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_0078, + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7710, + &pci_dev_info_9004_7711, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + &pci_dev_info_9004_8278, + &pci_dev_info_9004_8378, + &pci_dev_info_9004_8478, + &pci_dev_info_9004_8578, + &pci_dev_info_9004_8678, + &pci_dev_info_9004_8778, + &pci_dev_info_9004_8878, + &pci_dev_info_9004_8b78, + &pci_dev_info_9004_ec78, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9005[] = { + &pci_dev_info_9005_0010, + &pci_dev_info_9005_0011, + &pci_dev_info_9005_0013, + &pci_dev_info_9005_001f, + &pci_dev_info_9005_0020, + &pci_dev_info_9005_002f, + &pci_dev_info_9005_0030, + &pci_dev_info_9005_003f, + &pci_dev_info_9005_0050, + &pci_dev_info_9005_0051, + &pci_dev_info_9005_0053, + &pci_dev_info_9005_005f, + &pci_dev_info_9005_0080, + &pci_dev_info_9005_0081, + &pci_dev_info_9005_0083, + &pci_dev_info_9005_008f, + &pci_dev_info_9005_0092, + &pci_dev_info_9005_0093, + &pci_dev_info_9005_00c0, + &pci_dev_info_9005_00c1, + &pci_dev_info_9005_00c3, + &pci_dev_info_9005_00c5, + &pci_dev_info_9005_00cf, + &pci_dev_info_9005_0241, + &pci_dev_info_9005_0250, + &pci_dev_info_9005_0279, + &pci_dev_info_9005_0283, + &pci_dev_info_9005_0284, + &pci_dev_info_9005_0285, + &pci_dev_info_9005_0286, + &pci_dev_info_9005_0500, + &pci_dev_info_9005_0503, + &pci_dev_info_9005_0910, + &pci_dev_info_9005_091e, + &pci_dev_info_9005_8000, + &pci_dev_info_9005_800f, + &pci_dev_info_9005_8010, + &pci_dev_info_9005_8011, + &pci_dev_info_9005_8012, + &pci_dev_info_9005_8013, + &pci_dev_info_9005_8014, + &pci_dev_info_9005_8015, + &pci_dev_info_9005_8016, + &pci_dev_info_9005_8017, + &pci_dev_info_9005_801c, + &pci_dev_info_9005_801d, + &pci_dev_info_9005_801e, + &pci_dev_info_9005_801f, + &pci_dev_info_9005_8080, + &pci_dev_info_9005_808f, + &pci_dev_info_9005_8090, + &pci_dev_info_9005_8091, + &pci_dev_info_9005_8092, + &pci_dev_info_9005_8093, + &pci_dev_info_9005_8094, + &pci_dev_info_9005_8095, + &pci_dev_info_9005_8096, + &pci_dev_info_9005_8097, + &pci_dev_info_9005_809c, + &pci_dev_info_9005_809d, + &pci_dev_info_9005_809e, + &pci_dev_info_9005_809f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_907f[] = { + &pci_dev_info_907f_2015, + NULL +}; +#endif +#define pci_dev_list_919a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9412[] = { + &pci_dev_info_9412_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9699[] = { + &pci_dev_info_9699_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9710[] = { + &pci_dev_info_9710_7780, + &pci_dev_info_9710_9805, + &pci_dev_info_9710_9815, + &pci_dev_info_9710_9835, + &pci_dev_info_9710_9845, + &pci_dev_info_9710_9855, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9902[] = { + &pci_dev_info_9902_0001, + &pci_dev_info_9902_0002, + &pci_dev_info_9902_0003, + NULL +}; +#endif +#define pci_dev_list_a0a0 NULL +#define pci_dev_list_a0f1 NULL +#define pci_dev_list_a200 NULL +#define pci_dev_list_a259 NULL +#define pci_dev_list_a25b NULL +#define pci_dev_list_a304 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_a727[] = { + &pci_dev_info_a727_0013, + NULL +}; +#endif +#define pci_dev_list_aa42 NULL +#define pci_dev_list_ac1e NULL +#define pci_dev_list_ac3d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_aecb[] = { + &pci_dev_info_aecb_6250, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_affe[] = { + &pci_dev_info_affe_dead, + NULL +}; +#endif +#define pci_dev_list_b1b3 NULL +#define pci_dev_list_bd11 NULL +#define pci_dev_list_c001 NULL +#define pci_dev_list_c0a9 NULL +#define pci_dev_list_c0de NULL +#define pci_dev_list_c0fe NULL +#define pci_dev_list_ca50 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cafe[] = { + &pci_dev_info_cafe_0003, + NULL +}; +#endif +#define pci_dev_list_cccc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cddd[] = { + &pci_dev_info_cddd_0101, + &pci_dev_info_cddd_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d161[] = { + &pci_dev_info_d161_0205, + &pci_dev_info_d161_0210, + &pci_dev_info_d161_0405, + &pci_dev_info_d161_0410, + &pci_dev_info_d161_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d4d4[] = { + &pci_dev_info_d4d4_0601, + NULL +}; +#endif +#define pci_dev_list_d531 NULL +#define pci_dev_list_d84d NULL +#define pci_dev_list_dead NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_deaf[] = { + &pci_dev_info_deaf_9050, + &pci_dev_info_deaf_9051, + &pci_dev_info_deaf_9052, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e000[] = { + &pci_dev_info_e000_e000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e159[] = { + &pci_dev_info_e159_0001, + &pci_dev_info_e159_0002, + NULL +}; +#endif +#define pci_dev_list_e4bf NULL +#define pci_dev_list_e55e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea01[] = { + &pci_dev_info_ea01_000a, + &pci_dev_info_ea01_0032, + &pci_dev_info_ea01_003e, + &pci_dev_info_ea01_0041, + &pci_dev_info_ea01_0043, + &pci_dev_info_ea01_0046, + &pci_dev_info_ea01_0052, + &pci_dev_info_ea01_0800, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea60[] = { + &pci_dev_info_ea60_9896, + &pci_dev_info_ea60_9897, + &pci_dev_info_ea60_9898, + NULL +}; +#endif +#define pci_dev_list_eabb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_eace[] = { + &pci_dev_info_eace_3100, + &pci_dev_info_eace_3200, + &pci_dev_info_eace_320e, + &pci_dev_info_eace_340e, + &pci_dev_info_eace_341e, + &pci_dev_info_eace_3500, + &pci_dev_info_eace_351c, + &pci_dev_info_eace_4100, + &pci_dev_info_eace_4110, + &pci_dev_info_eace_4220, + &pci_dev_info_eace_422e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ec80[] = { + &pci_dev_info_ec80_ec00, + NULL +}; +#endif +#define pci_dev_list_ecc0 NULL +static const pciDeviceInfo *pci_dev_list_edd8[] = { + &pci_dev_info_edd8_a091, + &pci_dev_info_edd8_a099, + &pci_dev_info_edd8_a0a1, + &pci_dev_info_edd8_a0a9, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_f1d0[] = { + &pci_dev_info_f1d0_c0fe, + &pci_dev_info_f1d0_c0ff, + &pci_dev_info_f1d0_cafe, + &pci_dev_info_f1d0_cfee, + &pci_dev_info_f1d0_dcaf, + &pci_dev_info_f1d0_dfee, + &pci_dev_info_f1d0_efac, + &pci_dev_info_f1d0_facd, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fa57[] = { + &pci_dev_info_fa57_0001, + NULL +}; +#endif +#define pci_dev_list_febd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_feda[] = { + &pci_dev_info_feda_a0fa, + &pci_dev_info_feda_a10e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fede[] = { + &pci_dev_info_fede_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffd[] = { + &pci_dev_info_fffd_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffe[] = { + &pci_dev_info_fffe_0405, + &pci_dev_info_fffe_0710, + NULL +}; +#endif +#define pci_dev_list_ffff NULL + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_dev_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_dev_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_dev_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_dev_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_dev_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_dev_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_dev_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_dev_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_dev_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_dev_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_dev_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_dev_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_dev_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_dev_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_dev_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_dev_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_dev_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_dev_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_dev_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_dev_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_dev_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_dev_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_dev_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_dev_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_dev_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_dev_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_dev_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_dev_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_dev_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_dev_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_dev_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_dev_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_dev_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_dev_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_dev_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_dev_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_dev_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_dev_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_dev_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_dev_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_dev_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_dev_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_dev_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_dev_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_dev_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_dev_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_dev_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_dev_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_dev_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_dev_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_dev_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_dev_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_dev_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_dev_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_dev_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_dev_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_dev_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_dev_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_dev_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_dev_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_dev_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_dev_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_dev_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_dev_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_dev_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_dev_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_dev_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_dev_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_dev_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_dev_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_dev_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_dev_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_dev_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_dev_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_dev_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_dev_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_dev_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_dev_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_dev_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_dev_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_dev_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_dev_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_dev_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_dev_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_dev_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_dev_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_dev_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_dev_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_dev_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_dev_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_dev_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_dev_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_dev_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_dev_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_dev_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_dev_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_dev_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_dev_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_dev_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_dev_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_dev_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_dev_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_dev_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_dev_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_dev_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_dev_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_dev_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_dev_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_dev_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_dev_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_dev_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_dev_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_dev_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_dev_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_dev_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_dev_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_dev_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_dev_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_dev_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_dev_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_dev_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_dev_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_dev_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_dev_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_dev_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_dev_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_dev_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_dev_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_dev_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_dev_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_dev_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_dev_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_dev_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_dev_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_dev_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_dev_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_dev_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_dev_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_dev_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_dev_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_dev_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_dev_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_dev_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_dev_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_dev_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_dev_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_dev_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_dev_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_dev_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_dev_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_dev_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_dev_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_dev_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_dev_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_dev_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_dev_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_dev_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_dev_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_dev_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_dev_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_dev_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_dev_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_dev_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_dev_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_dev_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_dev_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_dev_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_dev_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_dev_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_dev_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_dev_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_dev_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_dev_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_ss_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_ss_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_ss_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_ss_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_ss_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_ss_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_ss_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_ss_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_ss_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_ss_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_ss_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_ss_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_ss_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_ss_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_ss_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_ss_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_ss_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_ss_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_ss_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_ss_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_ss_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_ss_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_ss_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_ss_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_ss_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_ss_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_ss_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_ss_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_ss_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_ss_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_ss_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_ss_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_ss_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_ss_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_ss_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_ss_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_ss_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_ss_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_ss_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_ss_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_ss_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_ss_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_ss_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_ss_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_ss_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_ss_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_ss_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_ss_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_ss_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_ss_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_ss_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_ss_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_ss_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_ss_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_ss_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_ss_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_ss_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_ss_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_ss_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_ss_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_ss_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_ss_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_ss_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_ss_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_ss_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_ss_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_ss_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_ss_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_ss_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_ss_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_ss_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_ss_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_ss_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_ss_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_ss_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_ss_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_ss_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_ss_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_ss_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_ss_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_ss_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_ss_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_ss_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_ss_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_ss_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_ss_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_ss_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_ss_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_ss_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_ss_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_ss_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_ss_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_ss_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_ss_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_ss_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_ss_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_ss_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_ss_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_ss_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_ss_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_ss_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_ss_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_ss_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_ss_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_ss_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_ss_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_ss_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_ss_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_ss_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_ss_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_ss_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_ss_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_ss_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_ss_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_ss_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_ss_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_ss_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_ss_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_ss_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_ss_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_ss_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_ss_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_ss_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_ss_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_ss_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_ss_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_ss_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_ss_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_ss_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_ss_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_ss_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_ss_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_ss_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_ss_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_ss_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_ss_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_ss_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_ss_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_ss_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_ss_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_ss_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_ss_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_ss_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_ss_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_ss_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_ss_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_ss_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_ss_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_ss_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_ss_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_ss_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_ss_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_ss_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_ss_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_ss_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_ss_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_ss_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_ss_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_ss_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_ss_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_ss_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_ss_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_ss_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_ss_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_ss_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_ss_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_ss_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_ss_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_ss_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_ss_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_ss_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_ss_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_ss_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciInfo.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciInfo.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciInfo.h (revision 51223) @@ -0,0 +1,726 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.156 2003/10/30 15:26:33 tsi Exp $ */ + +/* + * Copyright (c) 1995-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains macros for the PCI Vendor and Device IDs for video + * cards plus a few other things that are needed in drivers or elsewhere. + * This information is used in several ways: + * 1. It is used by drivers and/or other code. + * 2. It is used by the pciid2c.pl script to determine what vendor data to + * include in the pcidata module that the X server loads. + * 3. A side-effect of 2. affects how config-generation works for + * otherwise "unknown" cards. + * + * Don't add entries here for vendors that don't make video cards, + * or for non-video devices unless they're needed by a driver or elsewhere. + * A comprehensive set of PCI vendor, device and subsystem data is + * auto-generated from the ../etc/pci.ids file using the pciids2c.pl script, + * and is used in both the scanpci module and the scanpci utility. Don't + * modify the pci.ids file. If new/corrected entries are required, add them + * to ../etc/extrapci.ids. + */ + +#ifndef _XF86_PCIINFO_H +#define _XF86_PCIINFO_H + +/* PCI Pseudo Vendor */ +#define PCI_VENDOR_GENERIC 0x00FF + +#define PCI_VENDOR_REAL3D 0x003D +#define PCI_VENDOR_COMPAQ 0x0E11 +#define PCI_VENDOR_ATI 0x1002 +#define PCI_VENDOR_AVANCE 0x1005 +#define PCI_VENDOR_TSENG 0x100C +#define PCI_VENDOR_NS 0x100B +#define PCI_VENDOR_WEITEK 0x100E +#define PCI_VENDOR_VIDEOLOGIC 0x1010 +#define PCI_VENDOR_DIGITAL 0x1011 +#define PCI_VENDOR_CIRRUS 0x1013 +#define PCI_VENDOR_AMD 0x1022 +#define PCI_VENDOR_TRIDENT 0x1023 +#define PCI_VENDOR_ALI 0x1025 +#define PCI_VENDOR_DELL 0x1028 +#define PCI_VENDOR_MATROX 0x102B +#define PCI_VENDOR_CHIPSTECH 0x102C +#define PCI_VENDOR_MIRO 0x1031 +#define PCI_VENDOR_NEC 0x1033 +#define PCI_VENDOR_SIS 0x1039 +#define PCI_VENDOR_HP 0x103C +#define PCI_VENDOR_SGS 0x104A +#define PCI_VENDOR_TI 0x104C +#define PCI_VENDOR_SONY 0x104D +#define PCI_VENDOR_OAK 0x104E +#define PCI_VENDOR_MOTOROLA 0x1057 +#define PCI_VENDOR_NUMNINE 0x105D +#define PCI_VENDOR_CYRIX 0x1078 +#define PCI_VENDOR_SUN 0x108E +#define PCI_VENDOR_DIAMOND 0x1092 +#define PCI_VENDOR_BROOKTREE 0x109E +#define PCI_VENDOR_NEOMAGIC 0x10C8 +#define PCI_VENDOR_NVIDIA 0x10DE +#define PCI_VENDOR_IMS 0x10E0 +#define PCI_VENDOR_INTEGRAPHICS 0x10EA +#define PCI_VENDOR_ALLIANCE 0x1142 +#define PCI_VENDOR_RENDITION 0x1163 +#define PCI_VENDOR_3DFX 0x121A +#define PCI_VENDOR_SMI 0x126F +#define PCI_VENDOR_TRITECH 0x1292 +#define PCI_VENDOR_NVIDIA_SGS 0x12D2 +#define PCI_VENDOR_VMWARE 0x15AD +#define PCI_VENDOR_3DLABS 0x3D3D +#define PCI_VENDOR_AVANCE_2 0x4005 +#define PCI_VENDOR_HERCULES 0x4843 +#define PCI_VENDOR_S3 0x5333 +#define PCI_VENDOR_INTEL 0x8086 +#define PCI_VENDOR_ARK 0xEDD8 + + +/* Generic */ +#define PCI_CHIP_VGA 0x0000 +#define PCI_CHIP_8514 0x0001 + +/* Real 3D */ +#define PCI_CHIP_I740_PCI 0x00D1 + +/* Compaq */ +#define PCI_CHIP_QV1280 0x3033 + +/* ATI */ +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_4155 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_4A4F 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_R481_4B49 0x4B49 +#define PCI_CHIP_R481_4B4A 0x4B4A +#define PCI_CHIP_R481_4B4B 0x4B4B +#define PCI_CHIP_R481_4B4C 0x4B4C +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R430_554C 0x554C +#define PCI_CHIP_R430_554D 0x554D +#define PCI_CHIP_R430_554E 0x554E +#define PCI_CHIP_R430_554F 0x554F +#define PCI_CHIP_R423_5550 0x5550 +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_RV410_564A 0x564A +#define PCI_CHIP_RV410_564B 0x564B +#define PCI_CHIP_RV410_5652 0x5652 +#define PCI_CHIP_RV410_5653 0x5653 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RS480_5954 0x5954 +#define PCI_CHIP_RS480_5955 0x5955 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RS482_5974 0x5974 +#define PCI_CHIP_RS482_5975 0x5975 +#define PCI_CHIP_RS400_5A41 0x5A41 +#define PCI_CHIP_RS400_5A42 0x5A42 +#define PCI_CHIP_RC410_5A61 0x5A61 +#define PCI_CHIP_RC410_5A62 0x5A62 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R430_5D48 0x5D48 +#define PCI_CHIP_R430_5D49 0x5D49 +#define PCI_CHIP_R430_5D4A 0x5D4A +#define PCI_CHIP_R480_5D4C 0x5D4C +#define PCI_CHIP_R480_5D4D 0x5D4D +#define PCI_CHIP_R480_5D4E 0x5D4E +#define PCI_CHIP_R480_5D4F 0x5D4F +#define PCI_CHIP_R480_5D50 0x5D50 +#define PCI_CHIP_R480_5D52 0x5D52 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RV410_5E48 0x5E48 +#define PCI_CHIP_RV410_5E4A 0x5E4A +#define PCI_CHIP_RV410_5E4B 0x5E4B +#define PCI_CHIP_RV410_5E4C 0x5E4C +#define PCI_CHIP_RV410_5E4D 0x5E4D +#define PCI_CHIP_RV410_5E4F 0x5E4F +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + +/* Avance Logic */ +#define PCI_CHIP_ALG2064 0x2064 +#define PCI_CHIP_ALG2301 0x2301 +#define PCI_CHIP_ALG2501 0x2501 + +/* Tseng */ +#define PCI_CHIP_ET4000_W32P_A 0x3202 +#define PCI_CHIP_ET4000_W32P_B 0x3205 +#define PCI_CHIP_ET4000_W32P_D 0x3206 +#define PCI_CHIP_ET4000_W32P_C 0x3207 +#define PCI_CHIP_ET6000 0x3208 +#define PCI_CHIP_ET6300 0x4702 + +/* Weitek */ +#define PCI_CHIP_P9000 0x9001 +#define PCI_CHIP_P9100 0x9100 + +/* Digital */ +#define PCI_CHIP_DC21050 0x0001 +#define PCI_CHIP_DEC21030 0x0004 +#define PCI_CHIP_TGA2 0x000D + +/* Cirrus Logic */ +#define PCI_CHIP_GD7548 0x0038 +#define PCI_CHIP_GD7555 0x0040 +#define PCI_CHIP_GD5430 0x00A0 +#define PCI_CHIP_GD5434_4 0x00A4 +#define PCI_CHIP_GD5434_8 0x00A8 +#define PCI_CHIP_GD5436 0x00AC +#define PCI_CHIP_GD5446 0x00B8 +#define PCI_CHIP_GD5480 0x00BC +#define PCI_CHIP_GD5462 0x00D0 +#define PCI_CHIP_GD5464 0x00D4 +#define PCI_CHIP_GD5464BD 0x00D5 +#define PCI_CHIP_GD5465 0x00D6 +#define PCI_CHIP_6729 0x1100 +#define PCI_CHIP_6832 0x1110 +#define PCI_CHIP_GD7542 0x1200 +#define PCI_CHIP_GD7543 0x1202 +#define PCI_CHIP_GD7541 0x1204 + +/* AMD */ +#define PCI_CHIP_AMD761 0x700E + +/* Trident */ +#define PCI_CHIP_2100 0x2100 +#define PCI_CHIP_8400 0x8400 +#define PCI_CHIP_8420 0x8420 +#define PCI_CHIP_8500 0x8500 +#define PCI_CHIP_8520 0x8520 +#define PCI_CHIP_8600 0x8600 +#define PCI_CHIP_8620 0x8620 +#define PCI_CHIP_8820 0x8820 +#define PCI_CHIP_9320 0x9320 +#define PCI_CHIP_9388 0x9388 +#define PCI_CHIP_9397 0x9397 +#define PCI_CHIP_939A 0x939A +#define PCI_CHIP_9420 0x9420 +#define PCI_CHIP_9440 0x9440 +#define PCI_CHIP_9520 0x9520 +#define PCI_CHIP_9525 0x9525 +#define PCI_CHIP_9540 0x9540 +#define PCI_CHIP_9660 0x9660 +#define PCI_CHIP_9750 0x9750 +#define PCI_CHIP_9850 0x9850 +#define PCI_CHIP_9880 0x9880 +#define PCI_CHIP_9910 0x9910 + +/* ALI */ +#define PCI_CHIP_M1435 0x1435 + +/* Matrox */ +#define PCI_CHIP_MGA2085 0x0518 +#define PCI_CHIP_MGA2064 0x0519 +#define PCI_CHIP_MGA1064 0x051A +#define PCI_CHIP_MGA2164 0x051B +#define PCI_CHIP_MGA2164_AGP 0x051F +#define PCI_CHIP_MGAG200_PCI 0x0520 +#define PCI_CHIP_MGAG200 0x0521 +#define PCI_CHIP_MGAG400 0x0525 +#define PCI_CHIP_MGAG550 0x2527 +#define PCI_CHIP_IMPRESSION 0x0D10 +#define PCI_CHIP_MGAG100_PCI 0x1000 +#define PCI_CHIP_MGAG100 0x1001 + +#define PCI_CARD_G400_TH 0x2179 +#define PCI_CARD_MILL_G200_SD 0xFF00 +#define PCI_CARD_PROD_G100_SD 0xFF01 +#define PCI_CARD_MYST_G200_SD 0xFF02 +#define PCI_CARD_MILL_G200_SG 0xFF03 +#define PCI_CARD_MARV_G200_SD 0xFF04 + +/* Chips & Tech */ +#define PCI_CHIP_65545 0x00D8 +#define PCI_CHIP_65548 0x00DC +#define PCI_CHIP_65550 0x00E0 +#define PCI_CHIP_65554 0x00E4 +#define PCI_CHIP_65555 0x00E5 +#define PCI_CHIP_68554 0x00F4 +#define PCI_CHIP_69000 0x00C0 +#define PCI_CHIP_69030 0x0C30 + +/* Miro */ +#define PCI_CHIP_ZR36050 0x5601 + +/* NEC */ +#define PCI_CHIP_POWER_VR 0x0046 + +/* SiS */ +#define PCI_CHIP_SG86C201 0x0001 +#define PCI_CHIP_SG86C202 0x0002 +#define PCI_CHIP_SG85C503 0x0008 +#define PCI_CHIP_SIS5597 0x0200 +/* Agregado por Carlos Duclos & Manuel Jander */ +#define PCI_CHIP_SIS82C204 0x0204 +#define PCI_CHIP_SG86C205 0x0205 +#define PCI_CHIP_SG86C215 0x0215 +#define PCI_CHIP_SG86C225 0x0225 +#define PCI_CHIP_85C501 0x0406 +#define PCI_CHIP_85C496 0x0496 +#define PCI_CHIP_85C601 0x0601 +#define PCI_CHIP_85C5107 0x5107 +#define PCI_CHIP_85C5511 0x5511 +#define PCI_CHIP_85C5513 0x5513 +#define PCI_CHIP_SIS5571 0x5571 +#define PCI_CHIP_SIS5597_2 0x5597 +#define PCI_CHIP_SIS530 0x6306 +#define PCI_CHIP_SIS6326 0x6326 +#define PCI_CHIP_SIS7001 0x7001 +#define PCI_CHIP_SIS300 0x0300 +#define PCI_CHIP_SIS315H 0x0310 +#define PCI_CHIP_SIS315PRO 0x0325 +#define PCI_CHIP_SIS330 0x0330 +#define PCI_CHIP_SIS630 0x6300 +#define PCI_CHIP_SIS540 0x5300 +#define PCI_CHIP_SIS550 0x5315 +#define PCI_CHIP_SIS650 0x6325 +#define PCI_CHIP_SIS730 0x7300 + +/* Hewlett-Packard */ +#define PCI_CHIP_ELROY 0x1054 +#define PCI_CHIP_ZX1_SBA 0x1229 +#define PCI_CHIP_ZX1_IOC 0x122A +#define PCI_CHIP_ZX1_LBA 0x122E /* a.k.a. Mercury */ +#define PCI_CHIP_ZX1_AGP8 0x12B4 /* a.k.a. QuickSilver */ +#define PCI_CHIP_ZX2_LBA 0x12EE +#define PCI_CHIP_ZX2_SBA 0x4030 +#define PCI_CHIP_ZX2_IOC 0x4031 + +/* SGS */ +#define PCI_CHIP_STG2000 0x0008 +#define PCI_CHIP_STG1764 0x0009 +#define PCI_CHIP_KYROII 0x0010 + +/* Texas Instruments */ +#define PCI_CHIP_TI_PERMEDIA 0x3D04 +#define PCI_CHIP_TI_PERMEDIA2 0x3D07 + +/* Oak */ +#define PCI_CHIP_OTI107 0x0107 + +/* Number Nine */ +#define PCI_CHIP_I128 0x2309 +#define PCI_CHIP_I128_2 0x2339 +#define PCI_CHIP_I128_T2R 0x493D +#define PCI_CHIP_I128_T2R4 0x5348 + +/* Sun */ +#define PCI_CHIP_EBUS 0x1000 +#define PCI_CHIP_HAPPY_MEAL 0x1001 +#define PCI_CHIP_SIMBA 0x5000 +#define PCI_CHIP_PSYCHO 0x8000 +#define PCI_CHIP_SCHIZO 0x8001 +#define PCI_CHIP_SABRE 0xA000 +#define PCI_CHIP_HUMMINGBIRD 0xA001 + +/* BrookTree */ +#define PCI_CHIP_BT848 0x0350 +#define PCI_CHIP_BT849 0x0351 + +/* NVIDIA */ +#define PCI_CHIP_NV1 0x0008 +#define PCI_CHIP_DAC64 0x0009 +#define PCI_CHIP_TNT 0x0020 +#define PCI_CHIP_TNT2 0x0028 +#define PCI_CHIP_UTNT2 0x0029 +#define PCI_CHIP_VTNT2 0x002C +#define PCI_CHIP_UVTNT2 0x002D +#define PCI_CHIP_ITNT2 0x00A0 +#define PCI_CHIP_GEFORCE_256 0x0100 +#define PCI_CHIP_GEFORCE_DDR 0x0101 +#define PCI_CHIP_QUADRO 0x0103 +#define PCI_CHIP_GEFORCE2_MX 0x0110 +#define PCI_CHIP_GEFORCE2_MX_100 0x0111 +#define PCI_CHIP_GEFORCE2_GO 0x0112 +#define PCI_CHIP_QUADRO2_MXR 0x0113 +#define PCI_CHIP_GEFORCE2_GTS 0x0150 +#define PCI_CHIP_GEFORCE2_TI 0x0151 +#define PCI_CHIP_GEFORCE2_ULTRA 0x0152 +#define PCI_CHIP_QUADRO2_PRO 0x0153 +#define PCI_CHIP_GEFORCE4_MX_460 0x0170 +#define PCI_CHIP_GEFORCE4_MX_440 0x0171 +#define PCI_CHIP_GEFORCE4_MX_420 0x0172 +#define PCI_CHIP_GEFORCE4_440_GO 0x0174 +#define PCI_CHIP_GEFORCE4_420_GO 0x0175 +#define PCI_CHIP_GEFORCE4_420_GO_M32 0x0176 +#define PCI_CHIP_QUADRO4_500XGL 0x0178 +#define PCI_CHIP_GEFORCE4_440_GO_M64 0x0179 +#define PCI_CHIP_QUADRO4_200 0x017A +#define PCI_CHIP_QUADRO4_550XGL 0x017B +#define PCI_CHIP_QUADRO4_500_GOGL 0x017C +#define PCI_CHIP_IGEFORCE2 0x01A0 +#define PCI_CHIP_GEFORCE3 0x0200 +#define PCI_CHIP_GEFORCE3_TI_200 0x0201 +#define PCI_CHIP_GEFORCE3_TI_500 0x0202 +#define PCI_CHIP_QUADRO_DCC 0x0203 +#define PCI_CHIP_GEFORCE4_TI_4600 0x0250 +#define PCI_CHIP_GEFORCE4_TI_4400 0x0251 +#define PCI_CHIP_GEFORCE4_TI_4200 0x0253 +#define PCI_CHIP_QUADRO4_900XGL 0x0258 +#define PCI_CHIP_QUADRO4_750XGL 0x0259 +#define PCI_CHIP_QUADRO4_700XGL 0x025B + +/* NVIDIA & SGS */ +#define PCI_CHIP_RIVA128 0x0018 + +/* IMS */ +#define PCI_CHIP_IMSTT128 0x9128 +#define PCI_CHIP_IMSTT3D 0x9135 + +/* Alliance Semiconductor */ +#define PCI_CHIP_AP6410 0x3210 +#define PCI_CHIP_AP6422 0x6422 +#define PCI_CHIP_AT24 0x6424 +#define PCI_CHIP_AT3D 0x643D + +/* 3dfx Interactive */ +#define PCI_CHIP_VOODOO_GRAPHICS 0x0001 +#define PCI_CHIP_VOODOO2 0x0002 +#define PCI_CHIP_BANSHEE 0x0003 +#define PCI_CHIP_VOODOO3 0x0005 +#define PCI_CHIP_VOODOO5 0x0009 + +#define PCI_CARD_VOODOO3_2000 0x0036 +#define PCI_CARD_VOODOO3_3000 0x003A + +/* Rendition */ +#define PCI_CHIP_V1000 0x0001 +#define PCI_CHIP_V2x00 0x2000 + +/* 3Dlabs */ +#define PCI_CHIP_300SX 0x0001 +#define PCI_CHIP_500TX 0x0002 +#define PCI_CHIP_DELTA 0x0003 +#define PCI_CHIP_PERMEDIA 0x0004 +#define PCI_CHIP_MX 0x0006 +#define PCI_CHIP_PERMEDIA2 0x0007 +#define PCI_CHIP_GAMMA 0x0008 +#define PCI_CHIP_PERMEDIA2V 0x0009 +#define PCI_CHIP_PERMEDIA3 0x000A +#define PCI_CHIP_PERMEDIA4 0x000C +#define PCI_CHIP_R4 0x000D +#define PCI_CHIP_GAMMA2 0x000E +#define PCI_CHIP_R4ALT 0x0011 + +/* S3 */ +#define PCI_CHIP_PLATO 0x0551 +#define PCI_CHIP_VIRGE 0x5631 +#define PCI_CHIP_TRIO 0x8811 +#define PCI_CHIP_AURORA64VP 0x8812 +#define PCI_CHIP_TRIO64UVP 0x8814 +#define PCI_CHIP_VIRGE_VX 0x883D +#define PCI_CHIP_868 0x8880 +#define PCI_CHIP_928 0x88B0 +#define PCI_CHIP_864_0 0x88C0 +#define PCI_CHIP_864_1 0x88C1 +#define PCI_CHIP_964_0 0x88D0 +#define PCI_CHIP_964_1 0x88D1 +#define PCI_CHIP_968 0x88F0 +#define PCI_CHIP_TRIO64V2_DXGX 0x8901 +#define PCI_CHIP_PLATO_PX 0x8902 +#define PCI_CHIP_Trio3D 0x8904 +#define PCI_CHIP_VIRGE_DXGX 0x8A01 +#define PCI_CHIP_VIRGE_GX2 0x8A10 +#define PCI_CHIP_Trio3D_2X 0x8A13 +#define PCI_CHIP_SAVAGE3D 0x8A20 +#define PCI_CHIP_SAVAGE3D_MV 0x8A21 +#define PCI_CHIP_SAVAGE4 0x8A22 +#define PCI_CHIP_PROSAVAGE_PM 0x8A25 +#define PCI_CHIP_PROSAVAGE_KM 0x8A26 +#define PCI_CHIP_VIRGE_MX 0x8C01 +#define PCI_CHIP_VIRGE_MXPLUS 0x8C02 +#define PCI_CHIP_VIRGE_MXP 0x8C03 +#define PCI_CHIP_SAVAGE_MX_MV 0x8C10 +#define PCI_CHIP_SAVAGE_MX 0x8C11 +#define PCI_CHIP_SAVAGE_IX_MV 0x8C12 +#define PCI_CHIP_SAVAGE_IX 0x8C13 +#define PCI_CHIP_SUPSAV_MX128 0x8C22 +#define PCI_CHIP_SUPSAV_MX64 0x8C24 +#define PCI_CHIP_SUPSAV_MX64C 0x8C26 +#define PCI_CHIP_SUPSAV_IX128SDR 0x8C2A +#define PCI_CHIP_SUPSAV_IX128DDR 0x8C2B +#define PCI_CHIP_SUPSAV_IX64SDR 0x8C2C +#define PCI_CHIP_SUPSAV_IX64DDR 0x8C2D +#define PCI_CHIP_SUPSAV_IXCSDR 0x8C2E +#define PCI_CHIP_SUPSAV_IXCDDR 0x8C2F +#define PCI_CHIP_S3TWISTER_P 0x8D01 +#define PCI_CHIP_S3TWISTER_K 0x8D02 +#define PCI_CHIP_PROSAVAGE_DDR 0x8D03 +#define PCI_CHIP_PROSAVAGE_DDRK 0x8D04 +#define PCI_CHIP_SAVAGE2000 0x9102 + +/* ARK Logic */ +#define PCI_CHIP_1000PV 0xA091 +#define PCI_CHIP_2000PV 0xA099 +#define PCI_CHIP_2000MT 0xA0A1 +#define PCI_CHIP_2000MI 0xA0A9 + +/* Tritech Microelectronics */ +#define PCI_CHIP_TR25202 0xFC02 + +/* Neomagic */ +#define PCI_CHIP_NM2070 0x0001 +#define PCI_CHIP_NM2090 0x0002 +#define PCI_CHIP_NM2093 0x0003 +#define PCI_CHIP_NM2097 0x0083 +#define PCI_CHIP_NM2160 0x0004 +#define PCI_CHIP_NM2200 0x0005 +#define PCI_CHIP_NM2230 0x0025 +#define PCI_CHIP_NM2360 0x0006 +#define PCI_CHIP_NM2380 0x0016 + +/* Intel */ +#define PCI_CHIP_I815_BRIDGE 0x1130 +#define PCI_CHIP_I815 0x1132 +#define PCI_CHIP_82801_P2P 0x244E +#define PCI_CHIP_845_G_BRIDGE 0x2560 +#define PCI_CHIP_845_G 0x2562 +#define PCI_CHIP_I830_M_BRIDGE 0x3575 +#define PCI_CHIP_I830_M 0x3577 +#define PCI_CHIP_I810_BRIDGE 0x7120 +#define PCI_CHIP_I810 0x7121 +#define PCI_CHIP_I810_DC100_BRIDGE 0x7122 +#define PCI_CHIP_I810_DC100 0x7123 +#define PCI_CHIP_I810_E_BRIDGE 0x7124 +#define PCI_CHIP_I810_E 0x7125 +#define PCI_CHIP_I740_AGP 0x7800 +#define PCI_CHIP_460GX_PXB 0x84CB +#define PCI_CHIP_460GX_SAC 0x84E0 +#define PCI_CHIP_460GX_GXB_2 0x84E2 /* PCI function 2 */ +#define PCI_CHIP_460GX_WXB 0x84E6 +#define PCI_CHIP_460GX_GXB_1 0x84EA /* PCI function 1 */ + +/* Silicon Motion Inc. */ +#define PCI_CHIP_SMI910 0x0910 +#define PCI_CHIP_SMI810 0x0810 +#define PCI_CHIP_SMI820 0x0820 +#define PCI_CHIP_SMI710 0x0710 +#define PCI_CHIP_SMI712 0x0712 +#define PCI_CHIP_SMI720 0x0720 +#define PCI_CHIP_SMI731 0x0730 + +/* VMware */ +#define PCI_CHIP_VMWARE0405 0x0405 +#define PCI_CHIP_VMWARE0710 0x0710 + +#endif /* _XF86_PCIINFO_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStdIds.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStdIds.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStdIds.h (revision 51223) @@ -0,0 +1,126167 @@ +/* $XdotOrg$ */ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +static const char pci_device_0070_0003[] = "WinTV PVR-250"; +static const char pci_device_0070_0009[] = "WinTV PVR-150"; +static const char pci_device_0070_0801[] = "WinTV PVR-150"; +static const char pci_device_0070_0807[] = "WinTV PVR-150"; +static const char pci_device_0070_4000[] = "WinTV PVR-350"; +static const char pci_device_0070_4001[] = "WinTV PVR-250 (v1)"; +static const char pci_device_0070_4009[] = "WinTV PVR-250"; +static const char pci_device_0070_4800[] = "WinTV PVR-350"; +static const char pci_device_0070_4801[] = "WinTV PVR-250 MCE"; +static const char pci_device_0070_4803[] = "WinTV PVR-250"; +static const char pci_device_0070_8003[] = "WinTV PVR-150"; +static const char pci_device_0070_8801[] = "WinTV PVR-150"; +static const char pci_device_0070_c801[] = "WinTV PVR-150"; +static const char pci_device_0070_e807[] = "WinTV PVR-500 MCE (1st tuner)"; +static const char pci_device_0070_e817[] = "WinTV PVR-500 MCE (2nd tuner)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0071[] = "Nebula Electronics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0095[] = "Silicon Image, Inc. (Wrong ID)"; +static const char pci_device_0095_0680[] = "Ultra ATA/133 IDE RAID CONTROLLER CARD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00a7[] = "Teles AG (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_018a[] = "LevelOne"; +static const char pci_device_018a_0106[] = "FPC-0106TX misprogrammed [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_021b[] = "Compaq Computer Corporation"; +static const char pci_device_021b_8139[] = "HNE-300 (RealTek RTL8139c) [iPaq Networking]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0270[] = "Hauppauge computer works Inc. (Wrong ID)"; +static const char pci_device_0270_0801[] = "WinTV PVR-150"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0291[] = "Davicom Semiconductor, Inc."; +static const char pci_device_0291_8212[] = "DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_02ac[] = "SpeedStream"; +static const char pci_device_02ac_1012[] = "1012 PCMCIA 10/100 Ethernet Card [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0357[] = "TTTech AG"; +static const char pci_device_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0432[] = "SCM Microsystems, Inc."; +static const char pci_device_0432_0001[] = "Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_045e[] = "Microsoft"; +static const char pci_device_045e_006e[] = "MN-510 802.11b wireless USB paddle"; +static const char pci_device_045e_00c2[] = "MN-710 wireless USB paddle"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_04cf[] = "Myson Century, Inc"; +static const char pci_device_04cf_8818[] = "CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05e3[] = "CyberDoor"; +static const char pci_device_05e3_0701[] = "CBD516"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +static const char pci_device_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_067b[] = "Prolific Technology, Inc."; +static const char pci_device_067b_3507[] = "PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0721[] = "Sapphire, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_07e2[] = "ELMEG Communication Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b49[] = "ASCII Corporation"; +static const char pci_device_0b49_064f[] = "Trance Vibrator"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0046[] = "Smart Array 64xx"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409a[] = "Smart Array 641"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409b[] = "Smart Array 642"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409c[] = "Smart Array 6400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409d[] = "Smart Array 6400 EM"; +#endif +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_005a[] = "Remote Insight II board - Lights-Out"; +static const char pci_device_0e11_007c[] = "NC7770 1000BaseTX"; +static const char pci_device_0e11_007d[] = "NC6770 1000BaseTX"; +static const char pci_device_0e11_0085[] = "NC7780 1000BaseTX"; +static const char pci_device_0e11_00b1[] = "Remote Insight II board - PCI device"; +static const char pci_device_0e11_00bb[] = "NC7760"; +static const char pci_device_0e11_00ca[] = "NC7771"; +static const char pci_device_0e11_00cb[] = "NC7781"; +static const char pci_device_0e11_00cf[] = "NC7772"; +static const char pci_device_0e11_00d0[] = "NC7782"; +static const char pci_device_0e11_00d1[] = "NC7783"; +static const char pci_device_0e11_00e3[] = "NC7761"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_4030[] = "SMART-2/P"; +static const char pci_device_0e11_4031[] = "SMART-2SL"; +static const char pci_device_0e11_4032[] = "Smart Array 3200"; +static const char pci_device_0e11_4033[] = "Smart Array 3100ES"; +static const char pci_device_0e11_4034[] = "Smart Array 221"; +static const char pci_device_0e11_4040[] = "Integrated Array"; +static const char pci_device_0e11_4048[] = "Compaq Raid LC2"; +static const char pci_device_0e11_4050[] = "Smart Array 4200"; +static const char pci_device_0e11_4051[] = "Smart Array 4250ES"; +static const char pci_device_0e11_4058[] = "Smart Array 431"; +static const char pci_device_0e11_4070[] = "Smart Array 5300"; +static const char pci_device_0e11_4080[] = "Smart Array 5i"; +static const char pci_device_0e11_4082[] = "Smart Array 532"; +static const char pci_device_0e11_4083[] = "Smart Array 5312"; +static const char pci_device_0e11_4091[] = "Smart Array 6i"; +static const char pci_device_0e11_409a[] = "Smart Array 641"; +static const char pci_device_0e11_409b[] = "Smart Array 642"; +static const char pci_device_0e11_409c[] = "Smart Array 6400"; +static const char pci_device_0e11_409d[] = "Smart Array 6400 EM"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "FibreChannel HBA Tachyon"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10 T PCI UTP"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent Dual 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae43[] = "Netelligent Integrated 10/100 TX UTP"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Netelligent 10/100 TX Embedded UTP"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2 PCI UTP/Coax"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent 10/100 TX UTP"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4080[] = "Smart Array 5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4082[] = "Smart Array 532"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4083[] = "Smart Array 5312"; +#endif +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_b200[] = "Memory Hot-Plug Controller"; +static const char pci_device_0e11_b203[] = "Integrated Lights Out Controller"; +static const char pci_device_0e11_b204[] = "Integrated Lights Out Processor"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "LSI53C810AE PCI to SCSI I/O Processor"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0003_1000_1000[] = "LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide)"; +#endif +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0006_1000_1000[] = "LSI53C860E PCI to Ultra SCSI I/O Processor"; +#endif +static const char pci_device_1000_000a[] = "53c1510"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_1000_1000[] = "LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode)"; +#endif +static const char pci_device_1000_000b[] = "53C896/897"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_0e11_6004[] = "EOB003 Series SCSI host adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1000[] = "LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1010[] = "LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1020[] = "LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_13e9_1000[] = "6221L-4U"; +#endif +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1010[] = "LSI8951U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1020[] = "LSI8952U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3906[] = "DC-390U2B SCSI adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1000[] = "LSI53C876/E PCI to Dual Channel SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1010[] = "LSI22801 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1020[] = "LSI22802 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F/U Ultra Wide SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1050[] = "CT7 mainboard"; +#endif +static const char pci_device_1000_0010[] = "53C1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "RAID LC2 Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_1000_1000[] = "53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode)"; +#endif +static const char pci_device_1000_0012[] = "53c895a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0012_1000_1000[] = "LSI53C895A PCI to Ultra2 SCSI Controller"; +#endif +static const char pci_device_1000_0013[] = "53c875a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0013_1000_1000[] = "LSI53C875A PCI to Ultra SCSI Controller"; +#endif +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1000_1000[] = "LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1000[] = "LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1010[] = "Asus TR-DLS onboard 53C1010-66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_124b_1070[] = "PMC-USCSI3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1300[] = "P017 mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1310[] = "P017 mezzanine (64-bit PMC)"; +#endif +static const char pci_device_1000_0030[] = "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_0e11_00da[] = "ProLiant ML 350"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0123[] = "PowerEdge 2600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_014a[] = "PowerEdge 1750"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_016c[] = "PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_124b_1170[] = "PMC-USCSI320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1734_1052[] = "Primergy RX300 S2"; +#endif +static const char pci_device_1000_0031[] = "53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0032[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0032_1000_1000[] = "LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller"; +#endif +static const char pci_device_1000_0033[] = "1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0040[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0033[] = "MegaRAID SCSI 320-2XR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0066[] = "MegaRAID SCSI 320-2XRWS"; +#endif +static const char pci_device_1000_0041[] = "53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0050[] = "SAS1064 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0054[] = "SAS1068 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0056[] = "SAS1064E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_0058[] = "SAS1068E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005a[] = "SAS1066E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005c[] = "SAS1064A PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_005e[] = "SAS1066 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0060[] = "SAS1078 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0407[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0530[] = "MegaRAID 530 SCSI 320-0X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0531[] = "MegaRAID 531 SCSI 320-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0532[] = "MegaRAID 532 SCSI 320-2X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0530[] = "MegaRAID Intel RAID Controller SRCZCRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0532[] = "MegaRAID Intel RAID Controller SRCU42X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0408[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0001[] = "MegaRAID SCSI 320-1E RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0002[] = "MegaRAID SCSI 320-2E RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1025_004d[] = "MegaRAID ACER ROMB-2E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0001[] = "PowerEdge RAID Controller PERC4e/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0002[] = "PowerEdge RAID Controller PERC4e/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1734_1065[] = "FSC MegaRAID PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_8086_0002[] = "MegaRAID Intel RAID Controller SRCU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0409[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3004[] = "MegaRAID SATA 300-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3008[] = "MegaRAID SATA 300-8X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3008[] = "MegaRAID RAID Controller SRCS28X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3431[] = "MegaRAID RAID Controller Alief SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3499[] = "MegaRAID RAID Controller Harwich SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0621[] = "FC909 Fibre Channel Adapter"; +static const char pci_device_1000_0622[] = "FC929 Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0622_1000_1020[] = "44929 O Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919 Fibre Channel Adapter"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0626_1000_1010[] = "7202-XP-LC Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X Fibre Channel Adapter"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0640[] = "FC949X Fibre Channel Adapter"; +static const char pci_device_1000_0642[] = "FC939X Fibre Channel Adapter"; +static const char pci_device_1000_0646[] = "FC949ES Fibre Channel Adapter"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0804[] = "SA2010"; +static const char pci_device_1000_0805[] = "SA2010ZC"; +static const char pci_device_1000_0806[] = "SA2020"; +static const char pci_device_1000_0807[] = "SA2020ZC"; +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0518[] = "MegaRAID 518 SCSI 320-2 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0520[] = "MegaRAID 520 SCSI 320-1 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0522[] = "MegaRAID 522 i4 133 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0523[] = "MegaRAID SATA 150-6 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_4523[] = "MegaRAID SATA 150-4 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_a520[] = "MegaRAID ZCR SCSI 320-0 Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "MegaRAID 518 DELL PERC 4/DC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "MegaRAID 520 DELL PERC 4/SC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0520[] = "MegaRAIDRAID Controller SRCU41L"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0523[] = "MegaRAID RAID Controller SRCS16"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_3150[] = "M24 1P [Radeon Mobility X600]"; +static const char pci_device_1002_3152[] = "M22 [Radeon Mobility X300]"; +static const char pci_device_1002_3154[] = "M24 1T [FireGL M24 GL]"; +static const char pci_device_1002_3e50[] = "RV380 0x3e50 [Radeon X600]"; +static const char pci_device_1002_3e54[] = "RV380 0x3e54 [FireGL V3200]"; +static const char pci_device_1002_3e70[] = "RV380 [Radeon X600] Secondary"; +static const char pci_device_1002_4136[] = "Radeon IGP 320 M"; +static const char pci_device_1002_4137[] = "Radeon IGP330/340/350"; +static const char pci_device_1002_4144[] = "R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "R300 AE [Radeon 9700 Pro]"; +static const char pci_device_1002_4146[] = "R300 AF [Radeon 9700 Pro]"; +static const char pci_device_1002_4147[] = "R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4148[] = "R350 AH [Radeon 9800]"; +static const char pci_device_1002_4149[] = "R350 AI [Radeon 9800]"; +static const char pci_device_1002_414a[] = "R350 AJ [Radeon 9800]"; +static const char pci_device_1002_414b[] = "R350 AK [Fire GL X2]"; +static const char pci_device_1002_4150[] = "RV350 AP [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0002[] = "R9600 Pro primary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1458_4024[] = "Giga-Byte GV-R96128D Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2064[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2066[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c19[] = "Sapphire Atlantis Radeon 9600 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c29[] = "GC-R9600PRO Primary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_17ee_2002[] = "Radeon 9600 256Mb Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_18bc_0101[] = "GC-R9600PRO Primary"; +#endif +static const char pci_device_1002_4151[] = "RV350 AQ [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4151_1043_c004[] = "A9600SE"; +#endif +static const char pci_device_1002_4152[] = "RV350 AR [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_0002[] = "Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_4772[] = "All-in-Wonder 9600 XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c002[] = "Radeon 9600 XT TVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c01a[] = "A9600XT/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_174b_7c29[] = "Sapphire Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1787_4002[] = "Radeon 9600 XT"; +#endif +static const char pci_device_1002_4153[] = "RV350 AS [Radeon 9550]"; +static const char pci_device_1002_4154[] = "RV350 AT [Fire GL T2]"; +static const char pci_device_1002_4155[] = "RV350 AU [Fire GL T2]"; +static const char pci_device_1002_4156[] = "RV350 AV [Fire GL T2]"; +static const char pci_device_1002_4157[] = "RV350 AW [Fire GL T2]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4164[] = "R300 AD [Radeon 9500 Pro] (Secondary)"; +static const char pci_device_1002_4165[] = "R300 AE [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4166[] = "R300 AF [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4168[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4170[] = "RV350 AP [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1458_4025[] = "Giga-Byte GV-R96128D Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_148c_2067[] = "PowerColor R96A-C3N (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_174b_7c28[] = "GC-R9600PRO Secondary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_17ee_2003[] = "Radeon 9600 256Mb Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_18bc_0100[] = "GC-R9600PRO Secondary"; +#endif +static const char pci_device_1002_4171[] = "RV350 AQ [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4171_1043_c005[] = "A9600SE (Secondary)"; +#endif +static const char pci_device_1002_4172[] = "RV350 AR [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_0003[] = "Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_4773[] = "All-in-Wonder 9600 XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c003[] = "A9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c01b[] = "A9600XT/TD (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_174b_7c28[] = "Sapphire Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1787_4003[] = "Radeon 9600 XT (Secondary)"; +#endif +static const char pci_device_1002_4173[] = "RV350 ? [Radeon 9550] (Secondary)"; +static const char pci_device_1002_4237[] = "Radeon 7000 IGP"; +static const char pci_device_1002_4242[] = "R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4243[] = "R200 BC [Radeon All in Wonder 8500]"; +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_1002_4336[] = "Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_103c_0024[] = "Pavilion ze4400 builtin Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_161f_2029[] = "eMachines M5312 builtin Video"; +#endif +static const char pci_device_1002_4337[] = "Radeon IGP 330M/340M/350M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_1014_053a[] = "ThinkPad R40e (2684-HVG) builtin VGA controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_103c_0850[] = "Radeon IGP 345M"; +#endif +static const char pci_device_1002_4341[] = "IXP150 AC'97 Audio Controller"; +static const char pci_device_1002_4345[] = "EHCI USB Controller"; +static const char pci_device_1002_4347[] = "OHCI USB Controller #1"; +static const char pci_device_1002_4348[] = "OHCI USB Controller #2"; +static const char pci_device_1002_4349[] = "ATI Dual Channel Bus Master PCI IDE Controller"; +static const char pci_device_1002_434d[] = "IXP AC'97 Modem"; +static const char pci_device_1002_4353[] = "ATI SMBus"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4363[] = "ATI SMBus"; +static const char pci_device_1002_436e[] = "ATI 436E Serial ATA Controller"; +static const char pci_device_1002_4370[] = "IXP SB400 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4371[] = "IXP SB400 PCI-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4371_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4372[] = "IXP SB400 SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4373[] = "IXP SB400 USB2 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4374[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4374_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4375[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4376[] = "Standard Dual Channel PCI IDE Controller ATI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4377[] = "IXP SB400 PCI-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4378[] = "ATI SB400 - AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4379[] = "ATI 4379 Serial ATA Controller"; +static const char pci_device_1002_437a[] = "ATI 437A Serial ATA Controller"; +static const char pci_device_1002_4437[] = "Radeon Mobility 7000 IGP"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1734_007a[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0084[] = "Rage 3D Pro AGP 2x XPERT 98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon RV250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon RV250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon RV250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "RV250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "RV250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "RV250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "RV250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "RV250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "RV250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "RV250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "RV250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon RV250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon RV250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4a48[] = "R420 JH [Radeon X800]"; +static const char pci_device_1002_4a49[] = "R420 JI [Radeon X800PRO]"; +static const char pci_device_1002_4a4a[] = "R420 JJ [Radeon X800SE]"; +static const char pci_device_1002_4a4b[] = "R420 JK [Radeon X800]"; +static const char pci_device_1002_4a4c[] = "R420 JL [Radeon X800]"; +static const char pci_device_1002_4a4d[] = "R420 JM [FireGL X3]"; +static const char pci_device_1002_4a4e[] = "M18 JN [Radeon Mobility 9800]"; +static const char pci_device_1002_4a50[] = "R420 JP [Radeon X800XT]"; +static const char pci_device_1002_4a70[] = "R420 [X800XT-PE] (Secondary)"; +static const char pci_device_1002_4b49[] = "R480 [Radeon X850XT]"; +static const char pci_device_1002_4b4b[] = "R480 [Radeon X850Pro]"; +static const char pci_device_1002_4b4c[] = "R481 [Radeon X850XT-PE]"; +static const char pci_device_1002_4b69[] = "R480 [Radeon X850XT secondary]"; +static const char pci_device_1002_4b6b[] = "R480 [Radeon X850Pro] (Secondary)"; +static const char pci_device_1002_4b6c[] = "R481 [Radeon X850XT-PE] Secondary"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e7[] = "Rage LT Pro (Compaq Presario 5240)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c46_1028_00b1[] = "Latitude C600"; +#endif +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b160[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m/A21m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00aa[] = "Latitude CPt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00bb[] = "Latitude CPx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_10e1_10cf[] = "Fujitsu Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_13bd_1019[] = "PC-AR10"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c52_1033_8112[] = "Versa Note VXi"; +#endif +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_0e11_b111[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1509_1930[] = "Medion MD9703"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 Lf [FireGL 9000]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c6e[] = "Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_515e[] = "Radeon ES1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_5965[] = "Radeon ES1000"; +#endif +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1002_0002[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1681_0002[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro]"; +#endif +static const char pci_device_1002_4e46[] = "RV350 NF [Radeon 9600]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e48[] = "Radeon R350 [Radeon 9800 Pro]"; +static const char pci_device_1002_4e49[] = "Radeon R350 [Radeon 9800]"; +static const char pci_device_1002_4e4a[] = "RV350 NJ [Radeon 9800 XT]"; +static const char pci_device_1002_4e4b[] = "R350 NK [Fire GL X2]"; +static const char pci_device_1002_4e50[] = "RV350 [Mobility Radeon 9600 M10]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1734_1055[] = "Amilo M1420W"; +#endif +static const char pci_device_1002_4e51[] = "M10 NQ [Radeon Mobility 9600]"; +static const char pci_device_1002_4e52[] = "RV350 [Mobility Radeon 9600 M10]"; +static const char pci_device_1002_4e53[] = "M10 NS [Radeon Mobility 9600]"; +static const char pci_device_1002_4e54[] = "M10 NT [FireGL Mobility T2]"; +static const char pci_device_1002_4e56[] = "M11 NV [FireGL Mobility T2e]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9500 Pro] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1002_0003[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1681_0003[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary)"; +#endif +static const char pci_device_1002_4e66[] = "RV350 NF [Radeon 9600] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_4e68[] = "Radeon R350 [Radeon 9800 Pro] (Secondary)"; +static const char pci_device_1002_4e69[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4e6a[] = "RV350 NJ [Radeon 9800 XT] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e6a_1002_4e71[] = "ATI Technologies Inc M10 NQ [Radeon Mobility 9600]"; +#endif +static const char pci_device_1002_4e71[] = "M10 NQ [Radeon Mobility 9600] (secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1681_0010[] = "Radeon 8500 [3D Prophet 8500 128Mb]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5154[] = "R200 QT [Radeon 8500]"; +static const char pci_device_1002_5155[] = "R200 QU [Radeon 9100]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_103a[] = "Dell Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7146[] = "RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7c28[] = "Sapphire Radeon VE 7000 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_515e[] = "ES1000"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5346_1002_0048[] = "RAGE 128 16MB VGA TVOUT AMC PAL"; +#endif +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5460[] = "M22 [Radeon Mobility M300]"; +static const char pci_device_1002_5464[] = "M22 [FireGL GL]"; +static const char pci_device_1002_5548[] = "R423 UH [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5549[] = "R423 UI [Radeon X800PRO (PCIE)]"; +static const char pci_device_1002_554a[] = "R423 UJ [Radeon X800LE (PCIE)]"; +static const char pci_device_1002_554b[] = "R423 UK [Radeon X800SE (PCIE)]"; +static const char pci_device_1002_554d[] = "R430 [Radeon X800 XL] (PCIe)"; +static const char pci_device_1002_554f[] = "R430 [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5550[] = "R423 [Fire GL V7100]"; +static const char pci_device_1002_5551[] = "R423 UQ [FireGL V7200 (PCIE)]"; +static const char pci_device_1002_5552[] = "R423 UR [FireGL V5100 (PCIE)]"; +static const char pci_device_1002_5554[] = "R423 UT [FireGL V7100 (PCIE)]"; +static const char pci_device_1002_556b[] = "Radeon R423 UK (PCIE) [X800 SE] (Secondary)"; +static const char pci_device_1002_556d[] = "R430 [Radeon X800 XL] (PCIe) Secondary"; +static const char pci_device_1002_556f[] = "R430 [Radeon X800 (PCIE) Secondary]"; +static const char pci_device_1002_564a[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564b[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_5652[] = "M26 [Radeon Mobility X700]"; +static const char pci_device_1002_5653[] = "Radeon Mobility X700 (PCIE)"; +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_5830[] = "RS300 Host Bridge"; +static const char pci_device_1002_5831[] = "RS300 Host Bridge"; +static const char pci_device_1002_5832[] = "RS300 Host Bridge"; +static const char pci_device_1002_5833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_5834[] = "Radeon 9100 IGP"; +static const char pci_device_1002_5835[] = "RS300M AGP [Radeon Mobility 9100IGP]"; +static const char pci_device_1002_5838[] = "Radeon 9100 IGP AGP Bridge"; +static const char pci_device_1002_5940[] = "RV280 [Radeon 9200 PRO] (Secondary)"; +static const char pci_device_1002_5941[] = "RV280 [Radeon 9200] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_1458_4019[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_174b_7c12[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_17af_200d[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_18bc_0050[] = "GeXcube GC-R9200-C3 (Secondary)"; +#endif +static const char pci_device_1002_5944[] = "RV280 [Radeon 9200 SE (PCI)]"; +static const char pci_device_1002_5950[] = "RS480 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5951[] = "ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge"; +static const char pci_device_1002_5954[] = "RS480 [Radeon Xpress 200G Series]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5954_1002_5954[] = "RV370 [Radeon Xpress 200G Series]"; +#endif +static const char pci_device_1002_5955[] = "ATI Radeon XPRESS 200M 5955 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_1002_5955[] = "RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5960[] = "RV280 [Radeon 9200 PRO]"; +static const char pci_device_1002_5961[] = "RV280 [Radeon 9200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1002_2f72[] = "All-in-Wonder 9200 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1019_4c30[] = "Radeon 9200 VIVO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_12ab_5961[] = "YUAN SMARTVGA Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1458_4018[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_174b_7c13[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_17af_200c[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0050[] = "Radeon 9200 Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0051[] = "GeXcube GC-R9200-C3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0053[] = "Radeon 9200 Game Buster VIVO"; +#endif +static const char pci_device_1002_5962[] = "RV280 [Radeon 9200]"; +static const char pci_device_1002_5964[] = "RV280 [Radeon 9200 SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1043_c006[] = "ASUS Radeon 9200 SE / TD / 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4018[] = "Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_147b_6191[] = "R9200SE-DT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_148c_2073[] = "CN-AG92E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_174b_7c13[] = "Sapphire Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1787_5964[] = "Excalibur 9200SE VIVO 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_17af_2012[] = "Radeon 9200 SE Excalibur"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0170[] = "Sapphire Radeon 9200 SE 128MB Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0173[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5969[] = "ES1000"; +static const char pci_device_1002_5974[] = "RS482 [Radeon Xpress 200]"; +static const char pci_device_1002_5975[] = "RS482 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a34[] = "RS480 PCI-X Root Port"; +static const char pci_device_1002_5a41[] = "RS400 [Radeon Xpress 200]"; +static const char pci_device_1002_5a42[] = "RS400 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a61[] = "RC410 [Radeon Xpress 200]"; +static const char pci_device_1002_5a62[] = "RC410 [Radeon Xpress 200M]"; +static const char pci_device_1002_5b60[] = "RV370 5B60 [Radeon X300 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_002a[] = "Extreme AX300SE-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_032e[] = "Extreme AX300/TD"; +#endif +static const char pci_device_1002_5b62[] = "RV370 5B62 [Radeon X600 (PCIE)]"; +static const char pci_device_1002_5b63[] = "RV370 [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b64[] = "RV370 5B64 [FireGL V3100 (PCIE)]"; +static const char pci_device_1002_5b65[] = "RV370 5B65 [FireGL D1100 (PCIE)]"; +static const char pci_device_1002_5b70[] = "RV370 [Radeon X300SE]"; +static const char pci_device_1002_5b72[] = "Radeon X600(RV380)"; +static const char pci_device_1002_5b73[] = "RV370 secondary [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b74[] = "RV370 5B64 [FireGL V3100 (PCIE)] (Secondary)"; +static const char pci_device_1002_5c61[] = "M9+ 5C61 [Radeon Mobility 9200 (AGP)]"; +static const char pci_device_1002_5c63[] = "M9+ 5C63 [Radeon Mobility 9200 (AGP)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5c63_1002_5c63[] = "Apple iBook G4 2004"; +#endif +static const char pci_device_1002_5d44[] = "RV280 [Radeon 9200 SE] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4019[] = "Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_174b_7c12[] = "Sapphire Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1787_5965[] = "Excalibur 9200SE VIVO 128M (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_17af_2013[] = "Radeon 9200 SE Excalibur (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0171[] = "Radeon 9200 SE 128MB Game Buster (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0172[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5d48[] = "M28 [Radeon Mobility X800XT]"; +static const char pci_device_1002_5d49[] = "M28 [Mobility FireGL V5100]"; +static const char pci_device_1002_5d4a[] = "Mobility Radeon X800"; +static const char pci_device_1002_5d4d[] = "R480 [Radeon X850XT Platinum (PCIE)]"; +static const char pci_device_1002_5d52[] = "R480 [Radeon X850XT (PCIE)] (Primary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b12[] = "PowerColor X850XT PCIe Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b13[] = "PowerColor X850XT PCIe Secondary"; +#endif +static const char pci_device_1002_5d57[] = "R423 5F57 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_5d6d[] = "R480 [Radeon X850XT Platinum (PCIE)] (Secondary)"; +static const char pci_device_1002_5d72[] = "R480 [Radeon X850XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5d77[] = "R423 5F57 [Radeon X800XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5e48[] = "RV410 [FireGL V5000]"; +static const char pci_device_1002_5e49[] = "RV410 [FireGL V3300]"; +static const char pci_device_1002_5e4a[] = "RV410 [Radeon X700XT]"; +static const char pci_device_1002_5e4b[] = "RV410 [Radeon X700 Pro (PCIE)]"; +static const char pci_device_1002_5e4c[] = "RV410 [Radeon X700SE]"; +static const char pci_device_1002_5e4d[] = "RV410 [Radeon X700 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e4d_148c_2116[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5e4f[] = "RV410 [Radeon X700]"; +static const char pci_device_1002_5e6b[] = "RV410 [Radeon X700 Pro (PCIE)] Secondary"; +static const char pci_device_1002_5e6d[] = "RV410 [Radeon X700 (PCIE)] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e6d_148c_2117[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_700f[] = "PCI Bridge [IGP 320M]"; +static const char pci_device_1002_7010[] = "PCI Bridge [IGP 340M]"; +static const char pci_device_1002_7105[] = "R520 [FireGL]"; +static const char pci_device_1002_7109[] = "R520 [Radeon X900]"; +static const char pci_device_1002_7833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_7834[] = "Radeon 9100 PRO IGP"; +static const char pci_device_1002_7835[] = "Radeon Mobility 9200 IGP"; +static const char pci_device_1002_7838[] = "Radeon 9100 IGP PCI/AGP Bridge"; +static const char pci_device_1002_7c37[] = "RV350 AQ [Radeon 9600 SE]"; +static const char pci_device_1002_cab0[] = "AGP Bridge [IGP 320M]"; +static const char pci_device_1002_cab2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +static const char pci_device_1002_cab3[] = "R200 AGP Bridge [Mobility Radeon 7000 IGP]"; +static const char pci_device_1002_cbb2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_103c_0024[] = "Pavilion ze4400 builtin Network"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_1385_f311[] = "FA311 / FA312 (FA311 with WoL HW)"; +#endif +static const char pci_device_100b_0021[] = "PC87200 PCI to ISA Bridge"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0028[] = "Geode GX2 Host Bridge"; +static const char pci_device_100b_002a[] = "CS5535 South Bridge"; +static const char pci_device_100b_002b[] = "CS5535 ISA bridge"; +static const char pci_device_100b_002d[] = "CS5535 IDE"; +static const char pci_device_100b_002e[] = "CS5535 Audio"; +static const char pci_device_100b_002f[] = "CS5535 USB"; +static const char pci_device_100b_0030[] = "Geode GX2 Graphics Processor"; +static const char pci_device_100b_0035[] = "DP83065 [Saturn] 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_0510[] = "SC1100 Bridge"; +static const char pci_device_100b_0511[] = "SC1100 SMI"; +static const char pci_device_100b_0515[] = "SC1100 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "DEFPA"; +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0017[] = "PV-PCI Graphics Controller (ZLXp-L)"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1112[] = "DFE-570TX Quad Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_14cb_0100[] = "LNDL-100N 100Base-TX Ethernet PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX Gigabit Ethernet"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "Hewlett-Packard NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "IP Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0364[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4000[] = "MD 5620 [CLM Data Fax Voice]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_1136[] = "SiXPack 5.1+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "GXT1000 Graphics Adapter"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "SCSI RAID Adapter [ServeRAID]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0031[] = "2 Port Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0031_1014_0031[] = "2721 WAN IOA - 2 Port Sync Serial Adapter"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_0037[] = "82660 CPU to PCI Bridge"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003c[] = "GXT250P/GXT255P Graphics Adapter"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0054[] = "GXT500P/GXT550P Graphics Adapter"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_005e[] = "GXT800P Graphics Adapter"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_008b[] = "EADS PCI to PCI Bridge"; +static const char pci_device_1014_008e[] = "GXT3000P Graphics Adapter"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0091[] = "SSA Adapter"; +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_009f[] = "PCI 4758 Cryptographic Accelerator"; +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_00b7_1092_00b8[] = "FireGL1 AGP 32Mb"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1014_00b8[] = "GXT2000P Graphics Adapter"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0104[] = "Gigabit Ethernet-SX Adapter"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_015e[] = "622Mbps ATM PCI Adapter"; +static const char pci_device_1014_0160[] = "64bit/66MHz PCI ATM 155 MMF"; +static const char pci_device_1014_016e[] = "GXT4000P Graphics Adapter"; +static const char pci_device_1014_0170[] = "GXT6000P Graphics Adapter"; +static const char pci_device_1014_017d[] = "GXT300P Graphics Adapter"; +static const char pci_device_1014_0180[] = "Snipe chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0241[] = "iSeries 2757 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0264[] = "Quad Channel PCI-X U320 SCSI RAID Adapter (2780)"; +#endif +static const char pci_device_1014_0188[] = "EADS-X PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_01c1[] = "64bit/66MHz PCI ATM 155 UTP"; +static const char pci_device_1014_01e6[] = "Cryptographic Accelerator"; +static const char pci_device_1014_01ff[] = "10/100 Mbps Ethernet"; +static const char pci_device_1014_0219[] = "Multiport Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_021a[] = "Dual RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0251[] = "Internal Modem/RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0252[] = "Quad Internal Modem"; +#endif +static const char pci_device_1014_021b[] = "GXT6500P Graphics Adapter"; +static const char pci_device_1014_021c[] = "GXT4500P Graphics Adapter"; +static const char pci_device_1014_0233[] = "GXT135P Graphics Adapter"; +static const char pci_device_1014_0266[] = "PCI-X Dual Channel SCSI"; +static const char pci_device_1014_0268[] = "Gigabit Ethernet-SX Adapter (PCI-X)"; +static const char pci_device_1014_0269[] = "10/100/1000 Base-TX Ethernet Adapter (PCI-X)"; +static const char pci_device_1014_028c[] = "Citrine chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_028d[] = "Dual Channel PCI-X DDR SAS RAID Adapter (572E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02be[] = "Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02c0[] = "Dual Channel PCI-X DDR U320 SCSI Adapter (571A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_030d[] = "PCI-X DDR Auxiliary Cache Adapter (575B)"; +#endif +static const char pci_device_1014_02a1[] = "Calgary PCI-X Host Bridge"; +static const char pci_device_1014_0302[] = "Winnipeg PCI-X Host Bridge"; +static const char pci_device_1014_0314[] = "ZISC 036 Neural accelerator card"; +static const char pci_device_1014_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_4022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_0009[] = "MegaRAID 428 Ultra RAID Controller (rev 03)"; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500/500LC RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0477[] = "MegaRAID 477 Elite 3100 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0494[] = "MegaRAID 494 Elite 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0503[] = "MegaRAID 503 Enterprise 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0511[] = "MegaRAID 511 i4 IDE RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0522[] = "MegaRAID 522 i4133 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_103c_60e7[] = "NetRAID-1M"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 [Athlon64/Opteron] HyperTransport Technology Configuration"; +static const char pci_device_1022_1101[] = "K8 [Athlon64/Opteron] Address Map"; +static const char pci_device_1022_1102[] = "K8 [Athlon64/Opteron] DRAM Controller"; +static const char pci_device_1022_1103[] = "K8 [Athlon64/Opteron] Miscellaneous Control"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1022_2000[] = "PCnet - Fast 79C971"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2702[] = "AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2703[] = "AT-2701FX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2003[] = "Am 1771 MBW [Alchemy]"; +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_208f[] = "CS5536 GeodeLink PCI South Bridge"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700a[] = "AMD-IGR4 AGP Host to PCI Bridge"; +static const char pci_device_1022_700b[] = "AMD-IGR4 PCI to PCI Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X IOAPIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7458[] = "AMD-8132 PCI-X Bridge"; +static const char pci_device_1022_7459[] = "AMD-8132 PCI-X IOAPIC"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7460_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7464_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7468_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_1022_2b80[] = "AMD-8111 IDE [Quartet]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746b_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746d_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_device_1022_756b[] = "AMD-8111 ACPI"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_2001_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +#endif +static const char pci_device_1023_2100[] = "CyberBlade XP4m32"; +static const char pci_device_1023_2200[] = "XGI Volari XP5"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad R30/T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_1025[] = "Travelmate 352TE"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_1671[] = "M1671 Northbridge [ALADDiN-P4]"; +static const char pci_device_1025_1672[] = "Northbridge [CyberALADDiN-P4]"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge 2400"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge 4400"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge 2450"; +#endif +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Access Card III"; +static const char pci_device_1028_0008[] = "Remote Access Card III"; +static const char pci_device_1028_0009[] = "Remote Access Card III: BMC/SMIC device not present"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000c[] = "Embedded Remote Access or ERA/O"; +static const char pci_device_1028_000d[] = "Embedded Remote Access: BMC/SMIC device"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_0010[] = "Remote Access Card 4"; +static const char pci_device_1028_0011[] = "Remote Access Card 4 Daughter Card"; +static const char pci_device_1028_0012[] = "Remote Access Card 4 Daughter Card Virtual UART"; +static const char pci_device_1028_0013[] = "PowerEdge Expandable RAID controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016c[] = "PowerEdge Expandable RAID Controller 4e/Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016d[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016e[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016f[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_0170[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +static const char pci_device_1028_0014[] = "Remote Access Card 4 Daughter Card SMIC interface"; +static const char pci_device_1028_0015[] = "PowerEdge Expandable RAID controller 5"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +static const char pci_device_102a_001f[] = "AHA-2940U2/U2W /7890/7891 SCSI Controllers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_0106[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_102a_00c5[] = "AIC-7899 U160/m SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00c5_1028_00c5[] = "PowerEdge 2550/2650/4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_102a_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0106[] = "PowerEdge 4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0121[] = "PowerEdge 2650"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0100[] = "MGA 1064SG [Mystique]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0525[] = "G400/G450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d43[] = "Millennium G450 32Mb Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0850[] = "Parhelia 256MB AGP 4X"; +#endif +static const char pci_device_102b_0528[] = "Parhelia 8X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1020[] = "Parhelia 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1030[] = "Parhelia 256 MB Dual DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_14e1[] = "Parhelia PCI 256MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_2021[] = "QID Pro"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_2537[] = "Millenium P650/P750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1820[] = "Millennium P750 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1830[] = "Millennium P650 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1c10[] = "QID 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2811[] = "Millennium P650 Low-profile PCI 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2c11[] = "QID Low-profile PCI"; +#endif +static const char pci_device_102b_2538[] = "Millenium P650 PCIe"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_08c7[] = "Millennium P650 PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_0907[] = "Millennium P650 PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1047[] = "Millennium P650 LP PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1087[] = "Millennium P650 LP PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_2538[] = "Parhelia APVe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_3007[] = "QID Low-profile PCIe"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_000a[] = "TX3927 MIPS RISC PCI Controller"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +static const char pci_device_102f_0030[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller"; +static const char pci_device_102f_0031[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL"; +static const char pci_device_102f_0105[] = "TC86C001 [goku-s] IDE"; +static const char pci_device_102f_0106[] = "TC86C001 [goku-s] USB 1.1 Host"; +static const char pci_device_102f_0107[] = "TC86C001 [goku-s] USB Device Controller"; +static const char pci_device_102f_0108[] = "TC86C001 [goku-s] I2C/SIO/GPIO Controller"; +static const char pci_device_102f_0180[] = "TX4927/38 MIPS RISC PCI Controller"; +static const char pci_device_102f_0181[] = "TX4925 MIPS RISC PCI Controller"; +static const char pci_device_102f_0182[] = "TX4937 MIPS RISC PCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0000[] = "Vr4181A USB Host or Function Control Unit"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1033_0035[] = "Hama USB 2.0 CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_14c2_0105[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000a[] = "GlobeTrotter Fusion Quad Lite (PPP data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000b[] = "GlobeTrotter Fusion Quad Lite (GSM data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_807d_0035[] = "PCI-USB2 (OHCI subsystem)"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0072[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a5[] = "VRC4173"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00ce[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00df[] = "Vr4131"; +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_14c2_0205[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_807d_1043[] = "PCI-USB2 (EHCI subsystem)"; +#endif +static const char pci_device_1033_00e7[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00f2[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_00f3[] = "uPD6113x Multimedia Decoder/Processor [EMMA2]"; +static const char pci_device_1033_010c[] = "VR7701"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0003[] = "SiS AGP Port (virtual PCI-to-PCI bridge)"; +static const char pci_device_1039_0004[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_000a[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0016[] = "SiS961/2 SMBus Controller"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0180[] = "RAID bus controller 180 SATA/PATA [SiS]"; +static const char pci_device_1039_0181[] = "SATA"; +static const char pci_device_1039_0182[] = "182 SATA/RAID Controller"; +static const char pci_device_1039_0191[] = "191 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0550[] = "550 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0648[] = "645xx"; +static const char pci_device_1039_0650[] = "650/M650 Host"; +static const char pci_device_1039_0651[] = "651 Host"; +static const char pci_device_1039_0655[] = "655 Host"; +static const char pci_device_1039_0660[] = "660 Host"; +static const char pci_device_1039_0661[] = "661FX/M661FX/M661MX Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0741[] = "741/741GX/M741 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0746[] = "746 Host"; +static const char pci_device_1039_0755[] = "755 Host"; +static const char pci_device_1039_0760[] = "760/M760 Host"; +static const char pci_device_1039_0761[] = "761/M761 Host"; +static const char pci_device_1039_0900[] = "SiS900 PCI Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_0963[] = "SiS963 [MuTIOL Media IO]"; +static const char pci_device_1039_0964[] = "SiS964 [MuTIOL Media IO]"; +static const char pci_device_1039_0965[] = "SiS965 [MuTIOL Media IO]"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "550 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "630/730 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_6306[] = "530/620 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "65x/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_6330[] = "661/741/760/761 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6330_1039_6330[] = "[M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter"; +#endif +static const char pci_device_1039_7001[] = "USB 1.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1462_5470[] = "K7SOM+ 5.2C Motherboard"; +#endif +static const char pci_device_1039_7002[] = "USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "Sound Controller"; +static const char pci_device_1039_7013[] = "AC'97 Modem Controller"; +static const char pci_device_1039_7016[] = "SiS7016 PCI Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +static const char pci_device_1039_7019[] = "SiS7019 Audio Accelerator"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1006[] = "Visualize FX6"; +static const char pci_device_103c_1008[] = "Visualize FX4"; +static const char pci_device_103c_100a[] = "Visualize FX2"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Superdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1301[] = "Diva RMP3"; +#endif +static const char pci_device_103c_1054[] = "PCI Local Bus Adapter"; +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_10f0[] = "rio System Bus Adapter"; +static const char pci_device_103c_10f1[] = "rio I/O Controller"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "zx1 Local Bus Adapter"; +static const char pci_device_103c_127c[] = "sx1000 I/O Controller"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_1291[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_12b4[] = "zx1 QuickSilver AGP8x Local Bus Adapter"; +static const char pci_device_103c_12fa[] = "BCM4306 802.11b/g Wireless LAN Controller"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +static const char pci_device_103c_3080[] = "Pavilion ze2028ea"; +static const char pci_device_103c_3220[] = "Hewlett-Packard Smart Array P600"; +static const char pci_device_103c_3230[] = "Hewlett-Packard Smart Array Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "PC Tech RZ1000"; +static const char pci_device_1042_1001[] = "PC Tech RZ1001"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "ASUSTeK Computer Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_10cf_105e[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1043_4015[] = "v7100 SDRAM [GeForce2 MX]"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +static const char pci_device_1043_4057[] = "v8200 GeForce 3"; +static const char pci_device_1043_8043[] = "v8240 PAL 128M [P4T] Motherboard"; +static const char pci_device_1043_807b[] = "v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI]"; +static const char pci_device_1043_80bb[] = "v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out]"; +static const char pci_device_1043_80c5[] = "nForce3 chipset motherboard [SK8N]"; +static const char pci_device_1043_80df[] = "v9520 Magic/T"; +static const char pci_device_1043_8187[] = "802.11a/b/g Wireless LAN Card"; +static const char pci_device_1043_8188[] = "Tiger Hybrid TV Capture Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Adaptec (formerly DPT)"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3410S Ultra160 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c032[] = "ASR-2005S I2O Zero Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c035[] = "ASR-2010S I2O Zero Channel"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCIAudio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0c60[] = "Gladiac MX"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +static const char pci_device_1048_8901[] = "Gloria XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1048_8901_1048_0935[] = "GLoria XL (Virge)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "STMicroelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0209[] = "STPC Consumer/Industrial North- and Southbridge"; +static const char pci_device_104a_020a[] = "STPC Atlas/ConsumerS/Consumer IIA Northbridge"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_021a[] = "STPC Consumer S Southbridge"; +static const char pci_device_104a_021b[] = "STPC Consumer IIA Southbridge"; +static const char pci_device_104a_0500[] = "ST70137 [Unicorn] ADSL DMT Transceiver"; +static const char pci_device_104a_0564[] = "STPC Client Northbridge"; +static const char pci_device_104a_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +static const char pci_device_104a_55cc[] = "STPC Client Southbridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a34[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a36[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a43[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a44[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_000f[] = "Studio DV500-1394"; +#endif +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_1043_808b[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8025[] = "TSB82AA2 IEEE-1394b Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8025_1458_1000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1043_808d[] = "A7V333 mainboard."; +#endif +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8029[] = "PCI4510 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1071_8160[] = "MIM2900"; +#endif +static const char pci_device_104c_802b[] = "PCI7410,7510,7610 OHCI-Lynx Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_014e[] = "PCI7410,7510,7610 OHCI-Lynx Controller (Dell Latitude D800)"; +#endif +static const char pci_device_104c_802e[] = "PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller"; +static const char pci_device_104c_8031[] = "PCIxx21/x515 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8032[] = "OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8033[] = "PCIxx21 Integrated FlashMedia Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8034[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8035[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Smart Card Controller (SMC)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8035_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_104c_8036[] = "PCI6515 Cardbus Controller"; +static const char pci_device_104c_8038[] = "PCI6515 SmartCard Controller"; +static const char pci_device_104c_8201[] = "PCI1620 Firmware Loading Function"; +static const char pci_device_104c_8204[] = "PCI7410,7510,7610 PCI Firmware Loading Function"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b00[] = "DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b01[] = "DWL-520+ 22Mbps PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_16ab_8501[] = "WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter"; +#endif +static const char pci_device_104c_8401[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_9000[] = "Wireless Interface (of unknown type)"; +static const char pci_device_104c_9066[] = "ACX 111 54Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_104c_9066[] = "Microcom Travel Card WiFi 11g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b04[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b05[] = "DWL-G650+ AirPlusG+ CardBus Wireless LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_13d1_aba0[] = "SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+"; +#endif +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6414 TMS320C6415 TMS320C6416"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_5000[] = "ASI50xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_6400[] = "ASI6400 Cobranet series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_8700[] = "ASI87xx Radio Tuner card"; +#endif +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac16_1014_0092[] = "ThinkPad 600"; +#endif +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_1014_0130[] = "Thinkpad T20/T22/A21m"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_0e11_b121[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_1028_0088[] = "Latitude CPi A400XT"; +#endif +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_ac44[] = "PCI4510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_104c_ac46[] = "PCI4520 PC card Cardbus Controller"; +static const char pci_device_104c_ac47[] = "PCI7510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac4a[] = "PCI7510,7610 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_0e11_004e[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_00b1[] = "Latitude C600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1033_80cd[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1095_10cf[] = "Fujitsu-Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook S-4510/C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac54[] = "PCI1620 PC Card Controller"; +static const char pci_device_104c_ac55[] = "PCI1520 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30/T40"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0528[] = "ThinkPad R40e (2684-HVG) Cardbus Controller"; +#endif +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_5100[] = "ASI51xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6100[] = "ASI61xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6200[] = "ASI62xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_8800[] = "ASI88xx Audio Adapter"; +#endif +static const char pci_device_104c_ac8d[] = "PCI 7620"; +static const char pci_device_104c_ac8e[] = "PCI7420 CardBus Controller"; +static const char pci_device_104c_ac8f[] = "PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8004[] = "DTL-H2500 [Playstation development board]"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1050_9921[] = "W99200F MPEG-1 Video Encoder"; +static const char pci_device_1050_9922[] = "W99200F/W9922PF MPEG-1/2 Video Encoder"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0008[] = "MPC8540"; +static const char pci_device_1057_0009[] = "MPC8560"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "DSP56301 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0101[] = "Transas Radar Imitator Board [RIM]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0102[] = "Transas Radar Imitator Board [RIM-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0202[] = "Transas Radar Integrator Board [RIB-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0611[] = "1 channel CAN bus Controller [CanPci-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0612[] = "2 channels CAN bus Controller [CanPci-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0613[] = "3 channels CAN bus Controller [CanPci-3]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0614[] = "4 channels CAN bus Controller [CanPci-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0621[] = "1 channel CAN bus Controller [CanPci2-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0622[] = "2 channels CAN bus Controller [CanPci2-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0810[] = "Transas VTS Radar Integrator Board [RIB-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4200[] = "ASI4215 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4300[] = "ASI43xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4400[] = "ASI4401 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0010[] = "Darla"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0020[] = "Gina"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0031[] = "Layla rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0040[] = "Darla24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0041[] = "Darla24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0072[] = "Mona rev.2"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/8266/8272"; +static const char pci_device_1057_18c1[] = "MPC8271/MPC8272"; +static const char pci_device_1057_3410[] = "DSP56361 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0060[] = "Layla24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0072[] = "Mona rev.2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0080[] = "Mia rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0081[] = "Mia rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0090[] = "Indigo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00a0[] = "Indigo IO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00b0[] = "Indigo DJ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0100[] = "3G"; +#endif +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_5803[] = "MPC5200"; +static const char pci_device_1057_5806[] = "MCF54 Coldfire"; +static const char pci_device_1057_5808[] = "MPC8220"; +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +static const char pci_device_1057_6405[] = "MPC184 Security Processor (S1 family)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "PDC20265 (FastTrak100 Lite/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3318[] = "PDC20318 (SATA150 TX4)"; +static const char pci_device_105a_3319[] = "PDC20319 (FastTrak S150 TX4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3319_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_105a_3371[] = "PDC20371 (FastTrak S150 TX2plus)"; +static const char pci_device_105a_3373[] = "PDC20378 (FastTrak 378/SATA 378)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1043_80f5[] = "K8V Deluxe/PC-DL Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1462_702e[] = "K8T NEO FIS2R motherboard"; +#endif +static const char pci_device_105a_3375[] = "PDC20375 (SATA150 TX2plus)"; +static const char pci_device_105a_3376[] = "PDC20376 (FastTrak 376)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3376_1043_809e[] = "A7V8X motherboard"; +#endif +static const char pci_device_105a_3515[] = "PDC40719"; +static const char pci_device_105a_3519[] = "PDC40519 (FastTrak TX4200)"; +static const char pci_device_105a_3571[] = "PDC20571 (FastTrak TX2200)"; +static const char pci_device_105a_3574[] = "PDC20579 SATAII 150 IDE Controller"; +static const char pci_device_105a_3577[] = "PDC40779 (SATA 300 779)"; +static const char pci_device_105a_3d17[] = "PDC20718 (SATA 300 TX4)"; +static const char pci_device_105a_3d18[] = "PDC20518/PDC40518 (SATAII 150 TX4)"; +static const char pci_device_105a_3d73[] = "PDC40775 (SATA 300 TX2plus)"; +static const char pci_device_105a_3d75[] = "PDC20575 (SATAII150 TX2plus)"; +static const char pci_device_105a_4d30[] = "PDC20267 (FastTrak100/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "FastTrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "PDC20262 (FastTrak66/Ultra66)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "FastTrak66"; +#endif +static const char pci_device_105a_4d68[] = "PDC20268 (Ultra100 TX2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d69_105a_4d68[] = "Ultra133TX2"; +#endif +static const char pci_device_105a_5275[] = "PDC20276 (MBFastTrak133 Lite)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1043_807e[] = "A7V333 motherboard."; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_1275[] = "MBFastTrak133 Lite (tm) Controller (RAID mode)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1458_b001[] = "MBUltra 133"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "PDC20270 (FastTrak100 LP/TX2/TX4)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6268_105a_4d68[] = "FastTrak100 TX2"; +#endif +static const char pci_device_105a_6269[] = "PDC20271 (FastTrak TX2000)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite)"; +static const char pci_device_105a_6622[] = "PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_6624[] = "PDC20621 [FastTrak SX4100]"; +static const char pci_device_105a_6626[] = "PDC20618 (Ultra 618)"; +static const char pci_device_105a_6629[] = "PDC20619 (FastTrak TX4000)"; +static const char pci_device_105a_7275[] = "PDC20277 (SBFastTrak133 Lite)"; +static const char pci_device_105a_8002[] = "SATAII150 SX8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_105d_0037[] = "Revolution IV-FP AGP (For SGI 1600SW)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_1067_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_1067_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PG"; +static const char pci_device_1069_0020[] = "DAC960LA"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0050[] = "AcceleRAID 352 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0052[] = "AcceleRAID 170 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0054[] = "AcceleRAID 160 support Device"; +#endif +static const char pci_device_1069_b166[] = "AcceleRAID 600/500/400/Sapphire support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0242[] = "iSeries 2872 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0266[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0278[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d3[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d4[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0200[] = "AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0202[] = "AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0204[] = "AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0206[] = "AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0030[] = "eXtremeRAID 3000 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0040[] = "eXtremeRAID 2000 support Device"; +#endif +static const char pci_device_1069_ba57[] = "eXtremeRAID 4000/5000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba57_1069_0072[] = "eXtremeRAID 5000 support Device"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000c[] = "DOS on Mac"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_106b_0031_106b_5811[] = "iBook G4 2004"; +#endif +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_0035[] = "UniNorth 2 PCI"; +static const char pci_device_106b_0036[] = "UniNorth 2 Internal PCI"; +static const char pci_device_106b_003b[] = "UniNorth/Intrepid ATA/100"; +static const char pci_device_106b_003e[] = "KeyLargo/Intrepid Mac I/O"; +static const char pci_device_106b_003f[] = "KeyLargo/Intrepid USB"; +static const char pci_device_106b_0040[] = "K2 KeyLargo USB"; +static const char pci_device_106b_0041[] = "K2 KeyLargo Mac/IO"; +static const char pci_device_106b_0042[] = "K2 FireWire"; +static const char pci_device_106b_0043[] = "K2 ATA/100"; +static const char pci_device_106b_0045[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0046[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0047[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0048[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0049[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_004b[] = "U3 AGP"; +static const char pci_device_106b_004c[] = "K2 GMAC (Sun GEM)"; +static const char pci_device_106b_004f[] = "Shasta Mac I/O"; +static const char pci_device_106b_0050[] = "Shasta IDE"; +static const char pci_device_106b_0051[] = "Shasta (Sun GEM)"; +static const char pci_device_106b_0052[] = "Shasta Firewire"; +static const char pci_device_106b_0053[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0054[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0055[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0058[] = "U3L AGP Bridge"; +static const char pci_device_106b_0059[] = "U3H AGP Bridge"; +static const char pci_device_106b_0066[] = "Intrepid2 AGP Bridge"; +static const char pci_device_106b_0067[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0068[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0069[] = "Intrepid2 ATA/100"; +static const char pci_device_106b_006a[] = "Intrepid2 Firewire"; +static const char pci_device_106b_006b[] = "Intrepid2 GMAC (Sun GEM)"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hynix Semiconductor"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +static const char pci_device_1071_8160[] = "Mitac 8060B Mobile Platform"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280 SCSI Host Adapter"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2200_1077_0002[] = "QLA2200"; +#endif +static const char pci_device_1077_2300[] = "QLA2300 64-bit Fibre Channel Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +static const char pci_device_1077_2322[] = "QLA2322 Fibre Channel Adapter"; +static const char pci_device_1077_2422[] = "QLA2422 Fibre Channel Adapter"; +static const char pci_device_1077_2432[] = "QLA2432 Fibre Channel Adapter"; +static const char pci_device_1077_3010[] = "QLA3010 Network Adapter"; +static const char pci_device_1077_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1077_4010[] = "QLA4010 iSCSI TOE Adapter"; +static const char pci_device_1077_4022[] = "QLA4022 iSCSI TOE Adapter"; +static const char pci_device_1077_6312[] = "QLA6312 Fibre Channel Adapter"; +static const char pci_device_1077_6322[] = "QLA6322 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +static const char pci_device_107d_2134[] = "WinFast 3D S320 II"; +static const char pci_device_107d_2971[] = "[GeForce FX 5900] WinFast A350 TDH MyViVo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_1648[] = "[bge] Gigabit Ethernet"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_8002[] = "Schizo+ PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +static const char pci_device_108e_a801[] = "Tomatillo PCI Bus Module"; +static const char pci_device_108e_abba[] = "Cassini 10/100/1000"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Compro Computer Services, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +static const char pci_device_1091_07a0[] = "Sun Expert3D-Lite Graphics Accelerator"; +static const char pci_device_1091_1091[] = "Sun Expert3D Graphics Accelerator"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1310[] = "PCI-6602"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_14e0[] = "PCI-6110"; +static const char pci_device_1093_14f0[] = "PCI-6111"; +static const char pci_device_1093_17d0[] = "PCI-6503"; +static const char pci_device_1093_1870[] = "PCI-6713"; +static const char pci_device_1093_1880[] = "PCI-6711"; +static const char pci_device_1093_18b0[] = "PCI-6052E"; +static const char pci_device_1093_2410[] = "PCI-6733"; +static const char pci_device_1093_2890[] = "PCI-6036E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_2a70[] = "PCI-6024E"; +static const char pci_device_1093_2a80[] = "PCI-6025E"; +static const char pci_device_1093_2c80[] = "PCI-6035E"; +static const char pci_device_1093_2ca0[] = "PCI-6034E"; +static const char pci_device_1093_70b8[] = "PCI-6251 [M Series - High Speed Multifunction DAQ]"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "Silicon Image, Inc."; +static const char pci_device_1095_0240[] = "Adaptec AAR-1210SA SATA HostRAID Controller"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +static const char pci_device_1095_0649[] = "SiI 0649 Ultra ATA/100 PCI to ATA Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680 Ultra ATA-133 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0680_1095_3680[] = "Winic W-680 (Silicon Image 680 based)"; +#endif +static const char pci_device_1095_3112[] = "SiI 3112 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_3112[] = "SiI 3112 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_6112[] = "SiI 3112 SATARaid Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_9005_0250[] = "SATAConnect 1205SA Host Controller"; +#endif +static const char pci_device_1095_3114[] = "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_3114[] = "SiI 3114 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_6114[] = "SiI 3114 SATARaid Controller"; +#endif +static const char pci_device_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3124_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#endif +static const char pci_device_1095_3132[] = "SiI 3132 Serial ATA Raid II Controller"; +static const char pci_device_1095_3512[] = "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_3512[] = "SiI 3512 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_6512[] = "SiI 3512 SATARaid Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_032e[] = "Bt878 Video Capture"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0002[] = "TV98 Series (TV/No FM/Remote)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0003[] = "AverMedia UltraTV PCI 350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0761[] = "AverTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1822_0001[] = "VisionPlus DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0002[] = "Avermedia PCTV98 Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0761[] = "AVerTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1822_0001[] = "VisionPlus DVB Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_3052[] = "SmartPCI562 56K Modem"; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10a9_0009_10a9_8002[] = "AceNIC Gigabit Ethernet"; +#endif +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_100a[] = "IOC4 I/O controller"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_4001[] = "TIO-CE PCI Express Bridge"; +static const char pci_device_10a9_4002[] = "TIO-CE PCI Express Port"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +static const char pci_device_10a9_8010[] = "Broadcom e-net [SGI IO9/IO10 BaseIO]"; +static const char pci_device_10a9_8018[] = "Broadcom e-net [SGI A330 Server BaseIO]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1042[] = "Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2540[] = "IXXAT CAN-Interface PC-I 04/PCI"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_6540[] = "PCI6540/6466 PCI-PCI bridge (transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6540_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6541[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6541_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6542[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6542_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_8111[] = "PEX 8111 PCI Express-to-PCI Bridge"; +static const char pci_device_10b5_8114[] = "PEX 8114 PCI Express-to-PCI/PCI-X Bridge"; +static const char pci_device_10b5_8516[] = "PEX 8516 Versatile PCI Express Switch"; +static const char pci_device_10b5_8532[] = "PEX 8532 Versatile PCI Express Switch"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2862[] = "Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2906[] = "Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2940[] = "Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2977[] = "IXXAT iPC-I XC16/PCI CAN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2978[] = "SH ARC-PCIu SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3025[] = "Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3068[] = "Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3136[] = "4xS0-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3137[] = "S2M-E1-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1518_0200[] = "Kontron ThinkIO-C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1067[] = "IXXAT CAN i165"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1172[] = "IK220 (Heidenhain)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2221[] = "Alpermann+Velte PCL PCI LV: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH ARC-PCI SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2431[] = "Alpermann+Velte PCL PCI D: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2905[] = "Alpermann+Velte PCI TS: Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "MP9050"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1498_0362[] = "TPMC866 8 Channel Serial Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_2036[] = "OpenSwitch 6 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_3132[] = "OpenSwitch 12 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2696[] = "Innes Corp AM Radcap card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2717[] = "Innes Corp Auricon card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2844[] = "Innes Corp TVS Encoder card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12c7_4001[] = "Intel Dialogic DM/V960-4T1 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12d9_0002[] = "PCI Prosody Card rev 1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0011[] = "PIKA PrimeNet MM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0012[] = "PIKA PrimeNet MM cPCI 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0013[] = "PIKA PrimeNet MM cPCI 8 (without CAS Signaling)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0014[] = "PIKA PrimeNet MM cPCI 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0015[] = "PIKA Daytona MM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0016[] = "PIKA InLine MM"; +#endif +static const char pci_device_10b5_9056[] = "Francois"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9056_10b5_2979[] = "CellinkBlade 11 - CPCI board VoATM AAL1"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10eb[] = "(Agilent) E2777B 83K Series Optical Communication Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10ec[] = "(Agilent) E6978-66442 PCI CIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12d9_0002[] = "PCI Prosody Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12df_4422[] = "4422PCI [Do-All Telemetry Data Aquisition System]"; +#endif +static const char pci_device_10b5_bb04[] = "B&B 3PCIOSD1A Isolated PCI Serial"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_0013[] = "AR5212 802.11abg NIC (3CRDAG675)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_0013_10b7_2031[] = "3CRDAG675 11a/b/g Wireless PCI Adapter"; +#endif +static const char pci_device_10b7_0910[] = "3C910-A01"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +static const char pci_device_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +static const char pci_device_10b7_1700[] = "3c940 10/100/1000Base-T [Marvell]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_1043_80eb[] = "A7V600/P4P800/K8V motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0010[] = "3C940 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0020[] = "3C941 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 HomePNA [Tornado]"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3cCFE575CT CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6000[] = "3CRSHPW796 [OfficeConnect Wireless CardBus]"; +static const char pci_device_10b7_6001[] = "3com 3CRWE154G72 [Office Connect Wireless LAN Adapter]"; +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus [Cyclone]"; +static const char pci_device_10b7_6056[] = "3c556B CardBus [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3cCFE656 CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3cCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3cCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado]"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7770[] = "3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect]"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_80eb[] = "3c940B 10/100/1000Base-T"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 10Mbps Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC Etherlink XL [Cyclone]"; +static const char pci_device_10b7_900a[] = "3c900B-FL 10base-FL [Cyclone]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 Fast EtherLink XL [Cyclone]"; +static const char pci_device_10b7_9058[] = "3c905B Deluxe Etherlink 10/100/BNC [Cyclone]"; +static const char pci_device_10b7_905a[] = "3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0097[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_00fe[] = "Optiplex GX240"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_012a[] = "3C920 Integrated Fast Ethernet Controller [Latitude C640]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10f1_2466[] = "Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller)"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9201_1043_80ab[] = "A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller"; +#endif +static const char pci_device_10b7_9202[] = "3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9210[] = "3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX 910-A01 [tulip]"; +static const char pci_device_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-C 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "EtherLink Server 10/100 Dual Port A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "EtherLink Server 10/100 Dual Port B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990a[] = "3C990SVR [Typhoon Server]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83c170 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "83c175 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_2802[] = "SMC2802W [EZ Connect g]"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0101[] = "CMI8338/C3DX PCI Audio Device"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_0780[] = "Multi-IO Card"; +static const char pci_device_10b9_0782[] = "Multi-IO Card"; +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_1014_053b[] = "ThinkPad R40e (2684-HVG) PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALi M1533 Aladdin IV/V ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1573[] = "PCI to LPC Controller"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1672[] = "M1672 Northbridge [CyberALADDiN-P4]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_1689[] = "M1689 K8 Northbridge [Super K8 Single Chip]"; +static const char pci_device_10b9_1695[] = "M1695 K8 Northbridge [PCI Express and HyperTransport]"; +static const char pci_device_10b9_1697[] = "M1697 HTT Host Bridge"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_3323[] = "M3325 Video/Audio Decoder"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5228[] = "M5228 ALi ATA/RAID Controller"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_050f[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_053d[] = "ThinkPad R40e (2684-HVG) builtin IDE"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_103c_0024[] = "Pavilion ze4400 builtin IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_1014_0540[] = "ThinkPad R40e (2684-HVG) builtin USB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_103c_0024[] = "Pavilion ze4400 builtin USB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_104d_810f[] = "VAIO PCG-U1 USB/OHCI Revision 1.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5246[] = "AGP8X Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_524b[] = "PCI Express Root Port"; +static const char pci_device_10b9_524c[] = "PCI Express Root Port"; +static const char pci_device_10b9_524d[] = "PCI Express Root Port"; +static const char pci_device_10b9_524e[] = "PCI Express Root Port"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5263[] = "M5263 Ethernet Controller"; +static const char pci_device_10b9_5281[] = "ALi M5281 Serial ATA / RAID Host Controller"; +static const char pci_device_10b9_5287[] = "ULi 5287 SATA"; +static const char pci_device_10b9_5288[] = "ULi M5288 SATA"; +static const char pci_device_10b9_5289[] = "ULi 5289 SATA"; +static const char pci_device_10b9_5450[] = "Lucent Technologies Soft Modem AMR"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_053e[] = "ThinkPad R40e (2684-HVG) builtin Audio"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_103c_0024[] = "Pavilion ze4400 builtin Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_10b9_5451[] = "HP Compaq nc4010 (DY885AA#ABN)"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "M5457 AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_1014_0535[] = "ThinkPad R40e (2684-HVG) builtin modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_103c_0024[] = "Pavilion ze4400 builtin Modem Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5461[] = "High Definition Audio/AC'97 Host Controller"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 Power Management Controller [PMU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_0510[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_053c[] = "ThinkPad R40e (2684-HVG) Power Management Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_103c_0024[] = "Pavilion ze4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_10ba_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1028_0088[] = "Latitude CPi A"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_0088[] = "Latitude CPi A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mai Logic Incorporated"; +static const char pci_device_10cc_0660[] = "Articia S Host Bridge"; +static const char pci_device_10cc_0661[] = "Articia S PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Fujitsu Limited."; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0431[] = "MX98715"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8626[] = "Macronix MX86251 + 3Dfx Voodoo Rush"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +static const char pci_device_10dd_0100[] = "Lightning 1200"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c19[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1c[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c21[] = "Synergy II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c28[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c29[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2a[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2b[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c31[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c32[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c33[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c34[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_107d_2134[] = "WinFast 3D S320 II + TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2e[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2f[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c30[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c20[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c21[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3b[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "Pixelview RIVA TNT2 M64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1569_002d[] = "Palit Microsystems Daytona TNT2 M64"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0034[] = "MCP04 SMBus"; +static const char pci_device_10de_0035[] = "MCP04 IDE"; +static const char pci_device_10de_0036[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0037[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_0038[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_003a[] = "MCP04 AC'97 Audio Controller"; +static const char pci_device_10de_003b[] = "MCP04 USB Controller"; +static const char pci_device_10de_003c[] = "MCP04 USB Controller"; +static const char pci_device_10de_003d[] = "MCP04 PCI Bridge"; +static const char pci_device_10de_003e[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0040[] = "nv40 [GeForce 6800 Ultra]"; +static const char pci_device_10de_0041[] = "NV40 [GeForce 6800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0041_1043_817b[] = "V9999 Gamer Edition"; +#endif +static const char pci_device_10de_0042[] = "NV40.2 [GeForce 6800 LE]"; +static const char pci_device_10de_0043[] = "NV40.3"; +static const char pci_device_10de_0045[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0046[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0048[] = "GeForce 6800 XT"; +static const char pci_device_10de_0049[] = "NV40GL"; +static const char pci_device_10de_004e[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_0050[] = "CK804 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0051[] = "CK804 ISA Bridge"; +static const char pci_device_10de_0052[] = "CK804 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0053[] = "CK804 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1458_5002[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0054[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0055[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1043_815a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_0056[] = "CK804 Ethernet Controller"; +static const char pci_device_10de_0057[] = "CK804 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1043_8141[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1458_e000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0058[] = "CK804 AC'97 Modem"; +static const char pci_device_10de_0059[] = "CK804 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_1043_812a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_005a[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005b[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005c[] = "CK804 PCI Bridge"; +static const char pci_device_10de_005d[] = "CK804 PCIE Bridge"; +static const char pci_device_10de_005e[] = "CK804 Memory Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1458_5000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005f[] = "CK804 Memory Controller"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +static const char pci_device_10de_0065[] = "nForce2 IDE"; +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0066_1043_80a7[] = "A7N8X Mainboard onboard nForce2 Ethernet"; +#endif +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +static const char pci_device_10de_006b[] = "nForce Audio Processing Unit"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006b_10de_006b[] = "nForce2 MCP Audio Processing Unit"; +#endif +static const char pci_device_10de_006c[] = "nForce2 External PCI Bridge"; +static const char pci_device_10de_006d[] = "nForce2 PCI Bridge"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +static const char pci_device_10de_0080[] = "MCP2A ISA bridge"; +static const char pci_device_10de_0084[] = "MCP2A SMBus"; +static const char pci_device_10de_0085[] = "MCP2A IDE"; +static const char pci_device_10de_0086[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_0087[] = "MCP2A USB Controller"; +static const char pci_device_10de_0088[] = "MCP2A USB Controller"; +static const char pci_device_10de_008a[] = "MCP2S AC'97 Audio Controller"; +static const char pci_device_10de_008b[] = "MCP2A PCI Bridge"; +static const char pci_device_10de_008c[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_008e[] = "nForce2 Serial ATA Controller"; +static const char pci_device_10de_0091[] = "GeForce 7800 GTX"; +static const char pci_device_10de_0092[] = "GeForce 7800 GT"; +static const char pci_device_10de_0099[] = "GeForce Go 7800 GTX"; +static const char pci_device_10de_009d[] = "Quadro FX 4500"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_00c0[] = "NV41.0"; +static const char pci_device_10de_00c1[] = "NV41.1 [GeForce 6800]"; +static const char pci_device_10de_00c2[] = "NV41.2 [GeForce 6800 LE]"; +static const char pci_device_10de_00c3[] = "GeForce 6800 XT"; +static const char pci_device_10de_00c8[] = "NV41.8 [GeForce Go 6800]"; +static const char pci_device_10de_00c9[] = "NV41.9 [GeForce Go 6800 Ultra]"; +static const char pci_device_10de_00cc[] = "NV41 [Quadro FX Go1400]"; +static const char pci_device_10de_00cd[] = "NV41 [Quadro FX 3450/4000 SDI]"; +static const char pci_device_10de_00ce[] = "NV41GL [Quadro FX 1400]"; +static const char pci_device_10de_00d0[] = "nForce3 LPC Bridge"; +static const char pci_device_10de_00d1[] = "nForce3 Host Bridge"; +static const char pci_device_10de_00d2[] = "nForce3 AGP Bridge"; +static const char pci_device_10de_00d3[] = "CK804 Memory Controller"; +static const char pci_device_10de_00d4[] = "nForce3 SMBus"; +static const char pci_device_10de_00d5[] = "nForce3 IDE"; +static const char pci_device_10de_00d6[] = "nForce3 Ethernet"; +static const char pci_device_10de_00d7[] = "nForce3 USB 1.1"; +static const char pci_device_10de_00d8[] = "nForce3 USB 2.0"; +static const char pci_device_10de_00d9[] = "nForce3 Audio"; +static const char pci_device_10de_00da[] = "nForce3 Audio"; +static const char pci_device_10de_00dd[] = "nForce3 PCI Bridge"; +static const char pci_device_10de_00df[] = "CK8S Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e0[] = "nForce3 250Gb LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e1[] = "nForce3 250Gb Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e2[] = "nForce3 250Gb AGP Host to PCI Bridge"; +static const char pci_device_10de_00e3[] = "CK8S Serial ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e4[] = "nForce 250Gb PCI System Management"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e5[] = "CK8S Parallel ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e6[] = "CK8S Ethernet Controller"; +static const char pci_device_10de_00e7[] = "CK8S USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e8[] = "nForce3 EHCI USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ea[] = "nForce3 250Gb AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ed[] = "nForce3 250Gb PCI-to-PCI Bridge"; +static const char pci_device_10de_00ee[] = "CK8S Serial ATA Controller (v2.5)"; +static const char pci_device_10de_00f0[] = "NV40 [GeForce 6800/GeForce 6800 Ultra]"; +static const char pci_device_10de_00f1[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1043_81a6[] = "N6600GT TD 128M AGP"; +#endif +static const char pci_device_10de_00f2[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f2_1682_211c[] = "GeForce 6600 256MB DDR DUAL DVI TV"; +#endif +static const char pci_device_10de_00f3[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_00f8[] = "NV45GL [Quadro FX 3400/4400]"; +static const char pci_device_10de_00f9[] = "NV40 [GeForce 6800 Ultra/GeForce 6800 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f9_1682_2120[] = "GEFORCE 6800 GT PCI-E"; +#endif +static const char pci_device_10de_00fa[] = "NV36 [GeForce PCX 5750]"; +static const char pci_device_10de_00fb[] = "NV35 [GeForce PCX 5900]"; +static const char pci_device_10de_00fc[] = "NV37GL [Quadro FX 330/GeForce PCX 5300]"; +static const char pci_device_10de_00fd[] = "NV37GL [Quadro FX 330/Quadro NVS280]"; +static const char pci_device_10de_00fe[] = "NV38GL [Quadro FX 1300]"; +static const char pci_device_10de_00ff[] = "NV18 [GeForce PCX 4300]"; +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c41[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c43[] = "ERAZOR X PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c48[] = "Synergy Force"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1048_0c42[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_107d_2822[] = "WinFast GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c40[] = "GLoria II-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c44[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c45[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4a[] = "GLoria II-64 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4b[] = "GLoria II-64 Pro DVII"; +#endif +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c60[] = "Gladiac MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c61[] = "Gladiac 511PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c63[] = "Gladiac 511TV-OUT 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c64[] = "Gladiac 511TV-OUT 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c65[] = "Gladiac 511TWIN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c66[] = "Gladiac 311"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_0091[] = "Dell OEM GeForce 2 MX 400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_00a1[] = "Apple OEM GeForce2 MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX/Go]"; +static const char pci_device_10de_0140[] = "NV43 [GeForce 6600 GT]"; +static const char pci_device_10de_0141[] = "NV43 [GeForce 6600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0141_1458_3124[] = "GV-NX66128DP Turbo Force Edition"; +#endif +static const char pci_device_10de_0142[] = "GeForce 6600 LE"; +static const char pci_device_10de_0144[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0145[] = "NV43 [GeForce 6610 XL]"; +static const char pci_device_10de_0146[] = "NV43 [Geforce Go 6600TE/6200TE]"; +static const char pci_device_10de_0147[] = "GeForce 6700 XL"; +static const char pci_device_10de_0148[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0149[] = "GeForce Go 6600 GT"; +static const char pci_device_10de_014e[] = "NV43GL [Quadro FX 540]"; +static const char pci_device_10de_014f[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c50[] = "Gladiac"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c52[] = "Gladiac-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2842[] = "WinFast GeForce 2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1462_5506[] = "Creative 3D Blaster Geforce2 Titanium"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0160[] = "GeForce 6500"; +static const char pci_device_10de_0161[] = "GeForce 6200 TurboCache(TM)"; +static const char pci_device_10de_0162[] = "GeForce 6200SE TurboCache(TM)"; +static const char pci_device_10de_0163[] = "GeForce 6200 LE"; +static const char pci_device_10de_0164[] = "NV44 [GeForce Go 6200]"; +static const char pci_device_10de_0165[] = "NV44 [Quadro NVS 285]"; +static const char pci_device_10de_0166[] = "GeForce Go 6400"; +static const char pci_device_10de_0167[] = "GeForce Go 6200"; +static const char pci_device_10de_0168[] = "GeForce Go 6400"; +static const char pci_device_10de_0169[] = "GeForce 6250"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10b0_0002[] = "Gainward Pro/600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10de_0008[] = "Apple OEM GeForce4 MX 440"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8852[] = "GeForce4 MX440 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_10de_0177[] = "NV17 [GeForce4 460 Go]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0179_10de_0179[] = "GeForce4 MX (Mac)"; +#endif +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 500 GoGL]"; +static const char pci_device_10de_017d[] = "NV17 [GeForce4 410 Go 16M]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_806f[] = "V9180 Magic"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8880[] = "MS-StarForce GeForce4 MX 440 with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8900[] = "MS-8890 GeForce 4 MX440 AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_9350[] = "MSI Geforce4 MX T8X with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_147b_8f0d[] = "Siluro GF4 MX-8X"; +#endif +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0185[] = "NV18 [GeForce4 MX 4000 AGP 8x]"; +static const char pci_device_10de_0186[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_0187[] = "NV18M [GeForce4 488 Go]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS AGP 8x]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_018c[] = "Quadro NVS 50 PC"; +static const char pci_device_10de_018d[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_01a0[] = "NVCrush11 [GeForce2 MX Integrated Graphics]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b0[] = "nForce Audio"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "nForce AC'97 Modem Controller"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01e0[] = "nForce2 AGP (different version?)"; +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01ea[] = "nForce2 Memory Controller 0"; +static const char pci_device_10de_01eb[] = "nForce2 Memory Controller 1"; +static const char pci_device_10de_01ec[] = "nForce2 Memory Controller 2"; +static const char pci_device_10de_01ed[] = "nForce2 Memory Controller 3"; +static const char pci_device_10de_01ee[] = "nForce2 Memory Controller 4"; +static const char pci_device_10de_01ef[] = "nForce2 Memory Controller 5"; +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1048_0c70[] = "GLADIAC 920"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0211[] = "GeForce 6800"; +static const char pci_device_10de_0212[] = "GeForce 6800 LE"; +static const char pci_device_10de_0215[] = "GeForce 6800 GT"; +static const char pci_device_10de_0221[] = "GeForce 6200"; +static const char pci_device_10de_0240[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0241[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0242[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0243[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0244[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0245[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0246[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0247[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0248[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0249[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024a[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024b[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024c[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024d[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024e[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024f[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0251_1043_8023[] = "v8440 GeForce 4 Ti4400"; +#endif +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0260[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0261[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0262[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0263[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0264[] = "MCP51 SMBus"; +static const char pci_device_10de_0265[] = "MCP51 IDE"; +static const char pci_device_10de_0266[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0267[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0268[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_0269[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_026a[] = "MCP51 MCI"; +static const char pci_device_10de_026b[] = "MCP51 AC97 Audio Controller"; +static const char pci_device_10de_026c[] = "MCP51 High Definition Audio"; +static const char pci_device_10de_026d[] = "MCP51 USB Controller"; +static const char pci_device_10de_026e[] = "MCP51 USB Controller"; +static const char pci_device_10de_026f[] = "MCP51 PCI Bridge"; +static const char pci_device_10de_0270[] = "MCP51 Host Bridge"; +static const char pci_device_10de_0271[] = "MCP51 PMU"; +static const char pci_device_10de_0272[] = "MCP51 Memory Controller 0"; +static const char pci_device_10de_027e[] = "C51 Memory Controller 2"; +static const char pci_device_10de_027f[] = "C51 Memory Controller 3"; +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0286[] = "NV28 [GeForce4 Ti 4200 Go AGP 8x]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_028c[] = "NV28GLM [Quadro4 700 GoGL]"; +static const char pci_device_10de_02a0[] = "NV2A [XGPU]"; +static const char pci_device_10de_02f0[] = "C51 Host Bridge"; +static const char pci_device_10de_02f1[] = "C51 Host Bridge"; +static const char pci_device_10de_02f2[] = "C51 Host Bridge"; +static const char pci_device_10de_02f3[] = "C51 Host Bridge"; +static const char pci_device_10de_02f4[] = "C51 Host Bridge"; +static const char pci_device_10de_02f5[] = "C51 Host Bridge"; +static const char pci_device_10de_02f6[] = "C51 Host Bridge"; +static const char pci_device_10de_02f7[] = "C51 Host Bridge"; +static const char pci_device_10de_02f8[] = "C51 Memory Controller 5"; +static const char pci_device_10de_02f9[] = "C51 Memory Controller 4"; +static const char pci_device_10de_02fa[] = "C51 Memory Controller 0"; +static const char pci_device_10de_02fb[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fc[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fd[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fe[] = "C51 Memory Controller 1"; +static const char pci_device_10de_02ff[] = "C51 Host Bridge"; +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +static const char pci_device_10de_0311[] = "NV31 [GeForce FX 5600 Ultra]"; +static const char pci_device_10de_0312[] = "NV31 [GeForce FX 5600]"; +static const char pci_device_10de_0313[] = "NV31"; +static const char pci_device_10de_0314[] = "GeForce FX 5600SE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0314_1043_814a[] = "V9560XT/TD"; +#endif +static const char pci_device_10de_0316[] = "NV31M"; +static const char pci_device_10de_0317[] = "NV31M Pro"; +static const char pci_device_10de_031a[] = "NV31M [GeForce FX Go5600]"; +static const char pci_device_10de_031b[] = "NV31M [GeForce FX Go5650]"; +static const char pci_device_10de_031c[] = "NVIDIA Quadro FX Go700"; +static const char pci_device_10de_031d[] = "NV31GLM"; +static const char pci_device_10de_031e[] = "NV31GLM Pro"; +static const char pci_device_10de_031f[] = "NV31GLM Pro"; +static const char pci_device_10de_0320[] = "NV34 [GeForce FX 5200]"; +static const char pci_device_10de_0321[] = "NV34 [GeForce FX 5200 Ultra]"; +static const char pci_device_10de_0322[] = "NV34 [GeForce FX 5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9171[] = "MS-8917 (FX5200-T128)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9360[] = "MS-8936 (FX5200-T128)"; +#endif +static const char pci_device_10de_0323[] = "GeForce FX 5200SE"; +static const char pci_device_10de_0324[] = "NV34M [GeForce FX Go5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_10de_0325[] = "NV34M [GeForce FX Go5250]"; +static const char pci_device_10de_0326[] = "NV34 [GeForce FX 5500]"; +static const char pci_device_10de_0327[] = "NV34 [GeForce FX 5100]"; +static const char pci_device_10de_0328[] = "NV34M [GeForce FX Go5200 32M/64M]"; +static const char pci_device_10de_0329[] = "GeForce FX 5200 (Mac)"; +static const char pci_device_10de_032a[] = "NV34GL [Quadro NVS 280 PCI]"; +static const char pci_device_10de_032b[] = "NV34GL [Quadro FX 500/600 PCI]"; +static const char pci_device_10de_032c[] = "NV34GLM [GeForce FX Go 5300]"; +static const char pci_device_10de_032d[] = "NV34 [GeForce FX Go5100]"; +static const char pci_device_10de_032f[] = "NV34GL"; +static const char pci_device_10de_0330[] = "NV35 [GeForce FX 5900 Ultra]"; +static const char pci_device_10de_0331[] = "NV35 [GeForce FX 5900]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0331_1043_8145[] = "V9950GE"; +#endif +static const char pci_device_10de_0332[] = "NV35 [GeForce FX 5900XT]"; +static const char pci_device_10de_0333[] = "NV38 [GeForce FX 5950 Ultra]"; +static const char pci_device_10de_0334[] = "NV35 [GeForce FX 5900ZT]"; +static const char pci_device_10de_0338[] = "NV35GL [Quadro FX 3000]"; +static const char pci_device_10de_033f[] = "NV35GL [Quadro FX 700]"; +static const char pci_device_10de_0341[] = "NV36.1 [GeForce FX 5700 Ultra]"; +static const char pci_device_10de_0342[] = "NV36.2 [GeForce FX 5700]"; +static const char pci_device_10de_0343[] = "NV36 [GeForce FX 5700LE]"; +static const char pci_device_10de_0344[] = "NV36.4 [GeForce FX 5700VE]"; +static const char pci_device_10de_0345[] = "NV36.5"; +static const char pci_device_10de_0347[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0348[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0349[] = "NV36M Pro"; +static const char pci_device_10de_034b[] = "NV36MAP"; +static const char pci_device_10de_034c[] = "NV36 [Quadro FX Go1000]"; +static const char pci_device_10de_034e[] = "NV36GL [Quadro FX 1100]"; +static const char pci_device_10de_034f[] = "NV36GL"; +static const char pci_device_10de_0360[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0361[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0362[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0363[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0364[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0365[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0366[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0367[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0368[] = "MCP55 SMBus"; +static const char pci_device_10de_0369[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036c[] = "MCP55 USB Controller"; +static const char pci_device_10de_036d[] = "MCP55 USB Controller"; +static const char pci_device_10de_036e[] = "MCP55 IDE"; +static const char pci_device_10de_0371[] = "MCP55 High Definition Audio"; +static const char pci_device_10de_0372[] = "MCP55 Ethernet"; +static const char pci_device_10de_0373[] = "MCP55 Ethernet"; +static const char pci_device_10de_037a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_037e[] = "MCP55 SATA Controller"; +static const char pci_device_10de_037f[] = "MCP55 SATA Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Host Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Host Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a1[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a5[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0b5[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d1[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d5[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e1[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e5[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0f5[] = "Neptune LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f701[] = "LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f801[] = "LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f901[] = "LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Host Adapter"; +static const char pci_device_10df_f981[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_f982[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_fa00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fb00[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc10[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc20[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fd00[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fe00[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_ff00[] = "Neptune LightPulse Fibre Channel Host Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0148[] = "Tsi148 [Tempe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +static const char pci_device_10e3_8260[] = "CA91L8200B [Dual PCI PowerSpan II]"; +static const char pci_device_10e3_8261[] = "CA91L8260B [Single PCI PowerSpan II]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +static const char pci_device_10e4_8029[] = "Realtek 8029 Network Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_1072[] = "INES GPIB-PCI (AMCC5920 based)"; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_814c[] = "Fastcom ESCC-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_81e6[] = "Multimedia video controller"; +static const char pci_device_10e8_8291[] = "Fastcom 232/8-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c4[] = "Fastcom 422/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c5[] = "Fastcom 422/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c6[] = "Fastcom IG422/1-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c7[] = "Fastcom IG232/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82ca[] = "Fastcom 232/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +static const char pci_device_10e8_82e2[] = "Fastcom DIO24H-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8851[] = "S5933 on Innes Corp FM Radio Capture card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +static const char pci_device_10ea_5252[] = "CyberPro5252"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_0139[] = "Zonet Zen3200"; +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1043_8109[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1113_ec01[] = "FNC-0107TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1458_e000[] = "GA-7VM400M/7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_14cb_0200[] = "LNR-100 Family 10/100 Base-TX Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1799_5000[] = "F5D5000 PCI Card/Desktop Network PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_9001_1695[] = "Onboard RTL8101L 10/100 MBit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8169[] = "RTL-8169 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1259_c107[] = "CG-LAPCIGT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1458_e000[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1462_702c[] = "K8T NEO 2 motherboard"; +#endif +static const char pci_device_10ec_8180[] = "RTL8180L 802.11b MAC"; +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_0314[] = "Wildcard TE405P/TE410P (1st Gen)"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +static const char pci_device_10ee_3fc6[] = "RME Hammerfall DSP MADI"; +static const char pci_device_10ee_8381[] = "Ellips Santos Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft fuer Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +static const char pci_device_1101_9502[] = "Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8064[] = "SBLive! 5.1 Model SB0100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8065[] = "SBLive! 5.1 Digital Model SB0220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8067[] = "SBLive! 5.1 eMicro 28028"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0058[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_1007[] = "SB0240 Audigy 2 Platinum 6.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_2002[] = "SB Audigy 2 ZS (SB0350)"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_0007[] = "SB Audigy LS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_0007[] = "SBLive! 24bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1001[] = "SB0310 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1002[] = "SB0312 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1006[] = "SB0410 SBLive! 24-bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1462_1009[] = "K8N Diamond"; +#endif +static const char pci_device_1102_0008[] = "SB0400 Audigy2 Value"; +static const char pci_device_1102_100a[] = "SB Live! 5.1 Digital OEM [SB0220], (c) 2003"; +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! MIDI/Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_7005[] = "SB Audigy LS MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1001[] = "SB0310 Audigy LS MIDI/Game port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1002[] = "SB0312 Audigy LS MIDI/Game port"; +#endif +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "Ectiva EV1938"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1033_80e5[] = "SlimTower-Jim (NEC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1071_7150[] = "Mitac 7150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_110a_5938[] = "Siemens Scenic Mobile 510PIII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100c[] = "Ceres-C (Sharp, Intel BX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100d[] = "Sharp, Intel Banister"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100e[] = "TwinHead P09S/P09S3 (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_f6f1[] = "Marlin (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_0e70[] = "P88TE (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_c401[] = "Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b400[] = "G400 - Geo (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b550[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b560[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b700[] = "G700/U700 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b795[] = "G795 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b797[] = "G797 (AlphaTop (Taiwan))"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372/372N"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0003[] = "HPT343 / HPT345 / HPT363 UDMA33"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0004[] = "HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0006[] = "HPT302"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0007[] = "HPT371 UDMA133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0008[] = "HPT374 UDMA/ATA133 RAID Controller"; +#endif +static const char pci_device_1103_0005[] = "HPT372A/372N"; +static const char pci_device_1103_0006[] = "HPT302"; +static const char pci_device_1103_0007[] = "HPT371/371N"; +static const char pci_device_1103_0008[] = "HPT374"; +static const char pci_device_1103_0009[] = "HPT372N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +static const char pci_device_1105_8401[] = "EM8401 REALmagic DVD/MPEG-2 A/V Decoder"; +static const char pci_device_1105_8470[] = "EM8470 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8471[] = "EM8471 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8475[] = "EM8475 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8475_1105_0001[] = "REALmagic X-Card"; +#endif +static const char pci_device_1105_8476[] = "EM8476 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8476_127d_0000[] = "CineView II"; +#endif +static const char pci_device_1105_8485[] = "EM8485 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8486[] = "EM8486 REALmagic DVD/MPEG-4 A/V Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_0238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_0259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_0269[] = "KT880 Host Bridge"; +static const char pci_device_1106_0282[] = "K8T800Pro Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0282_1043_80a3[] = "A8V Deluxe"; +#endif +static const char pci_device_1106_0290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_0296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1019_0987[] = "K7VZA (Rev. 1.0) Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0308[] = "PT894 Host Bridge"; +static const char pci_device_1106_0314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C576MV"; +static const char pci_device_1106_0571[] = "VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_808c[] = "A7V8X / A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80a1[] = "A7V8X-X motherboard rev. 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1849_0571[] = "K7VT2 / K7VT6 motherboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0591[] = "VT8237A SATA 2-Port Controller"; +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0605_1043_802c[] = "CUV4X mainboard"; +#endif +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_802c[] = "CUV4X mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_1208[] = "PT890 Host Bridge"; +static const char pci_device_1106_1238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_1258[] = "PT880 Host Bridge"; +static const char pci_device_1106_1259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_1269[] = "KT880 Host Bridge"; +static const char pci_device_1106_1282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_1290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_1296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_1308[] = "PT894 Host Bridge"; +static const char pci_device_1106_1314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_1571[] = "VT82C576M/VT82C586"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_2204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_2208[] = "PT890 Host Bridge"; +static const char pci_device_1106_2238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_2258[] = "PT880 Host Bridge"; +static const char pci_device_1106_2259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_2269[] = "KT880 Host Bridge"; +static const char pci_device_1106_2282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_2290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_2296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_2308[] = "PT894 Host Bridge"; +static const char pci_device_1106_2314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_287a[] = "VT8251 PCI to PCI Bridge"; +static const char pci_device_1106_287b[] = "VT8251 PCI to PCIE Bridge"; +static const char pci_device_1106_287c[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287d[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287e[] = "VT8251 Ultra VLINK Controller"; +static const char pci_device_1106_3022[] = "CLE266"; +static const char pci_device_1106_3038[] = "VT82xxxxx UHCI USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_8080[] = "A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_808c[] = "VT6202 USB2.0 4 port controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_182d_201d[] = "CN-029 USB2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1849_3038[] = "K7VT6"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_0574_086c[] = "K8N Diamond"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1043_808a[] = "A8V Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1458_1000[] = "GA-7VT600-1394 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_702d[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_971d[] = "MS-6917"; +#endif +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3053[] = "VT6105M [Rhine-III]"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_0097[] = "SoundMax Digital Integrated Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1043_1106[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3300[] = "MS-6330 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233/A/8235/8237 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_8095[] = "A7V8X Motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80b0[] = "A7V600/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX])"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_812a[] = "A8V Deluxe motherboard (Realtek ALC850 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_3059[] = "L7VMM2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4161[] = "K7VT2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1297_c160[] = "FX41 motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_0080[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_3800[] = "KT266 onboard audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1849_9761[] = "K7VT6 motherboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4005_4710[] = "MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_a0a0_01b6[] = "AK77-8XN onboard audio"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_13b9_1421[] = "LD-10/100AL PCI Fast Ethernet Adapter (rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_3005[] = "VT6103"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_300c[] = "Realtek ALC655 sound chip"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1849_3065[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3068[] = "AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3068_1462_309e[] = "MS-6309 Saturn Motherboard"; +#endif +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1849_3099[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80a1[] = "A7V8X-X motherboard rev 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_182d_201d[] = "CN-029 USB 2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1849_3104[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3106_1186_1403[] = "DFE-530TX rev C"; +#endif +static const char pci_device_1106_3108[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3113[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3116[] = "VT8375 [KM266/KL266] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3116_1297_f641[] = "FX41 motherboard"; +#endif +static const char pci_device_1106_3118[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3119[] = "VT6120/VT6121/VT6122 Gigabit Ethernet Adapter"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3147_1043_808c[] = "A7V333 motherboard"; +#endif +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3149[] = "VIA VT6420 SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1043_80ed[] = "A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1458_b003[] = "GA-7VM400AM(F) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1462_7020[] = "K8T Neo 2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1408[] = "KV7"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1849_3149[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3164[] = "VT6410 ATA133 RAID controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1849_3177[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3178[] = "ProSavageDDR P4N333 Host Bridge"; +static const char pci_device_1106_3188[] = "VT8385 [K8T800 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_1043_80a3[] = "K8V Deluxe/K8V-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400/KT600 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1043_807f[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1849_3189[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_3205[] = "VT8378 [KM400/A] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3205_1458_5000[] = "GA-7VM400M Motherboard"; +#endif +static const char pci_device_1106_3208[] = "PT890 Host Bridge"; +static const char pci_device_1106_3213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3218[] = "K8T800M Host Bridge"; +static const char pci_device_1106_3227[] = "VT8237 ISA bridge [KT600/K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1106_3227[] = "DFI KT600-AL Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1458_5001[] = "GA-7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1849_3227[] = "K7VT4 motherboard"; +#endif +static const char pci_device_1106_3238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_3249[] = "VT6421 IDE RAID Controller"; +static const char pci_device_1106_3258[] = "PT880 Host Bridge"; +static const char pci_device_1106_3259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_3269[] = "KT880 Host Bridge"; +static const char pci_device_1106_3282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_3288[] = "VIA High Definition Audio Controller"; +static const char pci_device_1106_3290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_3296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_3337[] = "VT8237A PCI to ISA Bridge"; +static const char pci_device_1106_3349[] = "VT8251 AHCI/SATA 4-Port Controller"; +static const char pci_device_1106_337a[] = "VT8237A PCI to PCI Bridge"; +static const char pci_device_1106_337b[] = "VT8237A PCI to PCIE Bridge"; +static const char pci_device_1106_4149[] = "VIA VT6420 (ATA133) Controller"; +static const char pci_device_1106_4204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_4208[] = "PT890 Host Bridge"; +static const char pci_device_1106_4238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_4258[] = "PT880 Host Bridge"; +static const char pci_device_1106_4259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_4269[] = "KT880 Host Bridge"; +static const char pci_device_1106_4282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_4290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_4296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_4308[] = "PT894 Host Bridge"; +static const char pci_device_1106_4314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_5208[] = "PT890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5238[] = "K8T890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5290[] = "K8M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5308[] = "PT894 I/O APIC Interrupt Controller"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_7204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_7205[] = "VT8378 [S3 UniChrome] Integrated Video"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_7205_1458_d000[] = "Gigabyte GA-7VM400(A)M(F) Motherboard"; +#endif +static const char pci_device_1106_7208[] = "PT890 Host Bridge"; +static const char pci_device_1106_7238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_7258[] = "PT880 Host Bridge"; +static const char pci_device_1106_7259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_7269[] = "KT880 Host Bridge"; +static const char pci_device_1106_7282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_7290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_7296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_7308[] = "PT894 Host Bridge"; +static const char pci_device_1106_7314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_8598_1019_0985[] = "P6VXA Motherboard"; +#endif +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_a208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b113[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b115[] = "VT8363/8365 [KT133/KM133] PCI Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +static const char pci_device_1106_b188[] = "VT8237 PCI bridge [K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_b188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_b198[] = "VT8237 PCI Bridge"; +static const char pci_device_1106_b213[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_c208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d104[] = "VT8237 Integrated Fast Ethernet Controller"; +static const char pci_device_1106_d208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f238[] = "K8T890 PCI to PCI Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_0006[] = "FSC PINC (I/O-APIC)"; +static const char pci_device_110a_0015[] = "FSC Multiprocessor Interrupt Controller"; +static const char pci_device_110a_001d[] = "FSC Copernicus Management Controller"; +static const char pci_device_110a_007b[] = "FSC Remote Service Controller, mailbox device"; +static const char pci_device_110a_007c[] = "FSC Remote Service Controller, shared memory device"; +static const char pci_device_110a_007d[] = "FSC Remote Service Controller, SMIC device"; +static const char pci_device_110a_2101[] = "HST SAPHIR V Primary PCI (ISDN/PMx)"; +static const char pci_device_110a_2102[] = "DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels"; +static const char pci_device_110a_2104[] = "Eicon Diva 2.02 compatible passive ISDN card"; +static const char pci_device_110a_3142[] = "SIMATIC NET CP 5613A1 (Profibus Adapter)"; +static const char pci_device_110a_4021[] = "SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter)"; +static const char pci_device_110a_4029[] = "SIMATIC NET CP 5613A2 (Profibus Adapter)"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_1113_2242[] = "EN2242 10/100 Ethernet Mini-PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "21x4x DEC-Tulip compatible Fast Ethernet"; +static const char pci_device_1113_d301[] = "CPWNA100 (Philips wireless PCMCIA)"; +static const char pci_device_1113_ec02[] = "SMC 1244TX v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +static const char pci_device_1114_0506[] = "at76c506 802.11b Wireless Network Adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6117/6517"; +static const char pci_device_1119_0007[] = "GDT 6127/6527"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557/6557-ECC"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0010[] = "GDT 6115/6515"; +static const char pci_device_1119_0011[] = "GDT 6125/6525"; +static const char pci_device_1119_0012[] = "GDT 6535"; +static const char pci_device_1119_0013[] = "GDT 6555/6555-ECC"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_02ff[] = "GDT MAXRP"; +static const char pci_device_1119_0300[] = "GDT NEWRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +static const char pci_device_111a_1203[] = "SpeedStream 1023 Wireless PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Technology, Inc."; +static const char pci_device_111d_0001[] = "IDT77201/77211 155Mbps ATM SAR Controller [NICStAR]"; +static const char pci_device_111d_0003[] = "IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0004[] = "IDT77V252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0005[] = "IDT77V222 155Mbps ATM MICRO ABR SAR Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +static const char pci_device_112f_0008[] = "PC-CamLink PCI framegrabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_5400[] = "TriMedia TM1000/1100"; +static const char pci_device_1131_5402[] = "TriMedia TM-1300"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_5402_1244_0f00[] = "Fritz!Card DSL"; +#endif +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_102b_48d0[] = "Matrox CronosPlus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1048_226b[] = "ELSA EX-VISION 500TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2001[] = "10MOONS PCI TV CAPTURE CARD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2005[] = "Techcom (India) TV Tuner Card (SSD-TV-670)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_050c[] = "Nagase Sangyo TransGear 3000TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_10ff[] = "AVerMedia DVD EZMaker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2108[] = "AverMedia AverTV/305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2115[] = "AverMedia AverTV Studio 305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_153b_1152[] = "Terratec Cinergy 200 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c100[] = "Compro VideoMate TV PVR/FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_5168_0138[] = "LifeView FlyVIDEO2000"; +#endif +static const char pci_device_1131_7133[] = "SAA7133 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_002b_11bd[] = "Pinnacle PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1019_4cb5[] = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_0210[] = "MiniPCI TV Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4843[] = "ASUS TV-FM 7133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2001[] = "Proteus Pro [philips reference design]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_f31f[] = "Avermedia AVerTV GO 007 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1489_0214[] = "LifeView FlyTV Platinum FM/Genius VideoWonder ProTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1162[] = "Terratec Cinergy 400 mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_185b_c100[] = "Compro VideoMate TV Gold+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0138[] = "LifeView FlyVideo 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0212[] = "LifeView FlyTV Platinum mini"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0214[] = "LifeView FlyTV Platinum"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0306[] = "LifeView FlyDVB-T DUO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0502[] = "LifeView FlyDVB-T Duo CardBus"; +#endif +static const char pci_device_1131_7134[] = "SAA7134 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1019_4cb4[] = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4840[] = "ASUS TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4842[] = "TV-FM Card 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_4e85[] = "SKNet Monster TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_6752[] = "EMPRESS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_7133[] = "AOPEN VA1000 POWER"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002b[] = "Pinnacle PCTV Stereo (saa7134)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002d[] = "Pinnacle PCTV 300i DVB-T + PAL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_2c00[] = "AVerMedia Hybrid+FM (A16A) PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_2c05[] = "AVerMedia DVB-T A777"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70a[] = "Avermedia AVerTV 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70b[] = "AverMedia M156 / Medion 2819"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_d6ee[] = "AVerMedia Cardbus TV/Radio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1142[] = "Terratec Cinergy 400 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1143[] = "Terratec Cinergy 600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1158[] = "Terratec Cinergy 600 TV MK3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1540_9524[] = "ProVideo PV952"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_16be_0003[] = "Medion 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c200[] = "Compro VideoMate Gold+ Pal"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_a006[] = "KNC One TV-Station DVR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_fe01[] = "KNC One TV-Station RDS / Typhoon TV Tuner RDS"; +#endif +static const char pci_device_1131_7135[] = "SAA7135 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_1421_0350[] = "ADS Tech Instant TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_1421_0370[] = "ADS Tech Instant TV (cardbus version)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7135_5168_0212[] = "LifeView FlyTV Platinum Mini"; +#endif +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_0000[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_ffff[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f56[] = "KNC1 DVB-S Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f60[] = "Fujitsu-Siemens Activy DVB-S Budget Rev AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f61[] = "Activy DVB-S Budget Rev GR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_5f61[] = "Activy DVB-T Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000f[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0000[] = "Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0001[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0002[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0003[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0004[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0006[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0008[] = "Technotrend/Hauppauge DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_000a[] = "Octal/Technotrend DVB-C for iTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1003[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-S DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1004[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-C DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1005[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100c[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100f[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1011[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1013[] = "SATELCO Multimedia DVB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1102[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +static const char pci_device_1131_9730[] = "SAA9730 Integrated Multimedia and Peripheral Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Networks Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "Diva Pro 2.0 S/T"; +static const char pci_device_1133_e002[] = "Diva 2.0 S/T PCI"; +static const char pci_device_1133_e003[] = "Diva Pro 2.0 U"; +static const char pci_device_1133_e004[] = "Diva 2.0 U PCI"; +static const char pci_device_1133_e005[] = "Diva 2.01 S/T PCI"; +static const char pci_device_1133_e006[] = "Diva CT S/T PCI"; +static const char pci_device_1133_e007[] = "Diva CT U PCI"; +static const char pci_device_1133_e008[] = "Diva CT Lite S/T PCI"; +static const char pci_device_1133_e009[] = "Diva CT Lite U PCI"; +static const char pci_device_1133_e00a[] = "Diva ISDN+V.90 PCI"; +static const char pci_device_1133_e00b[] = "Diva 2.02 PCI S/T"; +static const char pci_device_1133_e00c[] = "Diva 2.02 PCI U"; +static const char pci_device_1133_e00d[] = "Diva ISDN Pro 3.0 PCI"; +static const char pci_device_1133_e00e[] = "Diva ISDN+CT S/T PCI Rev 2"; +static const char pci_device_1133_e010[] = "Diva Server BRI-2M PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_110a_0021[] = "Fujitsu Siemens ISDN S0"; +#endif +static const char pci_device_1133_e011[] = "Diva Server BRI S/T Rev 2"; +static const char pci_device_1133_e012[] = "Diva Server 4BRI-8M PCI"; +static const char pci_device_1133_e013[] = "Diva Server 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_1300[] = "Diva Server V-4BRI-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_e013[] = "Diva Server 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e014[] = "Diva Server PRI-30M PCI"; +static const char pci_device_1133_e015[] = "DIVA Server PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e015_1133_e015[] = "Diva Server PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e016[] = "Diva Server Voice 4BRI PCI"; +static const char pci_device_1133_e017[] = "Diva Server Voice 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e017_1133_e017[] = "Diva Server Voice 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_1800[] = "Diva Server V-BRI-2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e019[] = "Diva Server Voice PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e019_1133_e019[] = "Diva Server Voice PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e01a[] = "Diva Server 2FX"; +static const char pci_device_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01b_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e01c[] = "Diva Server PRI Rev 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c01[] = "Diva Server PRI/E1/T1-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c02[] = "Diva Server PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c03[] = "Diva Server PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c04[] = "Diva Server PRI/E1/T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c05[] = "Diva Server V-PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c06[] = "Diva Server V-PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c07[] = "Diva Server PRI/E1/T1-8 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c08[] = "Diva Server PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c09[] = "Diva Server PRI/E1-30 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0a[] = "Diva Server PRI/E1/T1 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0b[] = "Diva Server V-PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0c[] = "Diva Server V-PRI/E1-30 Cornet NQ"; +#endif +static const char pci_device_1133_e01e[] = "Diva Server 2PRI"; +static const char pci_device_1133_e020[] = "Diva Server 4PRI"; +static const char pci_device_1133_e024[] = "Diva Server Analog-4P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_2400[] = "Diva Server V-Analog-4P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_e024[] = "Diva Server Analog-4P"; +#endif +static const char pci_device_1133_e028[] = "Diva Server Analog-8P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_2800[] = "Diva Server V-Analog-8P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_e028[] = "Diva Server Analog-8P"; +#endif +static const char pci_device_1133_e02a[] = "Diva Server IPM-300"; +static const char pci_device_1133_e02c[] = "Diva Server IPM-600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +static const char pci_device_1134_0002[] = "Dual PCI to RapidIO Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +static const char pci_device_1145_f020[] = "NinjaSCSI-32 Sony PCGA-DVD51"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "SysKonnect"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2971[] = "AT-2970LX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970TX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2973[] = "AT-2971SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2974[] = "AT-2971T Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2976[] = "AT-2970LX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970TX/2TX Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1148_4320[] = "SysKonnect SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0121[] = "Marvell RDK-8001 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0221[] = "Marvell RDK-8002 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0321[] = "Marvell RDK-8003 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0421[] = "Marvell RDK-8004 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0621[] = "Marvell RDK-8006 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0721[] = "Marvell RDK-8007 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0821[] = "Marvell RDK-8008 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0921[] = "Marvell RDK-8009 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1121[] = "Marvell RDK-8011 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1221[] = "Marvell RDK-8012 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_3221[] = "SK-9521 V2.0 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "SK-9Dxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_4500[] = "SK-9Mxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_9000[] = "SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45"; +static const char pci_device_1148_9843[] = "[Fujitsu] Gigabit Ethernet"; +static const char pci_device_1148_9e00[] = "SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2100[] = "SK-9E21 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_21d0[] = "SK-9E21D 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2200[] = "SK-9E22 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8100[] = "SK-9E81 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8200[] = "SK-9E82 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9100[] = "SK-9E91 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9200[] = "SK-9E92 Server Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0013[] = "AccelePort Xr"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0028[] = "ClassicBoard 4"; +static const char pci_device_114f_0029[] = "ClassicBoard 8"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p"; +static const char pci_device_114f_0043[] = "AccelePort 4p"; +static const char pci_device_114f_0044[] = "AccelePort 8p"; +static const char pci_device_114f_0045[] = "AccelePort 16p"; +static const char pci_device_114f_004e[] = "AccelePort 32p"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_00b0[] = "Digi Neo 4"; +static const char pci_device_114f_00b1[] = "Digi Neo 8"; +static const char pci_device_114f_00c8[] = "Digi Neo 2 DB9"; +static const char pci_device_114f_00c9[] = "Digi Neo 2 DB9 PRI"; +static const char pci_device_114f_00ca[] = "Digi Neo 2 RJ45"; +static const char pci_device_114f_00cb[] = "Digi Neo 2 RJ45 PRI"; +static const char pci_device_114f_00d0[] = "ClassicBoard 4 422"; +static const char pci_device_114f_00d1[] = "ClassicBoard 8 422"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0182[] = "RealPort2 CardBus Ethernet 10/100 (R2BE-100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_00d4[] = "Mini-PCI K56Flex Modem"; +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "Broadcom"; +static const char pci_device_1166_0000[] = "CMIC-LE"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0006[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-WS Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CMIC-LE Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0036[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0101[] = "CIOB-X2 PCI-X I/O Bridge"; +static const char pci_device_1166_0104[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0110[] = "CIOB-E I/O Bridge with Gigabit Ethernet"; +static const char pci_device_1166_0130[] = "HT1000 PCI-X bridge"; +static const char pci_device_1166_0132[] = "HT1000 PCI-Express bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0201_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0203_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0205[] = "HT1000 Legacy South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0212_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_c134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0214[] = "HT1000 Legacy IDE controller"; +static const char pci_device_1166_0217[] = "CSB6 IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0217_1028_4134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0220_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0221_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0223[] = "HT1000 USB Controller"; +static const char pci_device_1166_0225[] = "CSB5 LPC bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0227_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0230[] = "CSB5 LPC bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0230_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0234[] = "HT1000 LPC Bridge"; +static const char pci_device_1166_0240[] = "K2 SATA"; +static const char pci_device_1166_0241[] = "RAIDCore RC4000"; +static const char pci_device_1166_0242[] = "RAIDCore BC4000"; +static const char pci_device_1166_024a[] = "BCM5785 (HT1000) SATA Native SATA Mode"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0102[] = "Extended IDE Controller"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "CPU to PCI bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0601_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_060a_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC100 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +static const char pci_device_117c_0030[] = "Ultra320 SCSI Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8013[] = "ExpressPCI UL4D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8014[] = "ExpressPCI UL4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1987[] = "Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines )"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_14ef_0220[] = "PCD-RP-220S"; +#endif +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0511[] = "R5C511"; +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_1180_0554[] = "R5C554"; +static const char pci_device_1180_0575[] = "R5C575 SD Bus Host Adapter"; +static const char pci_device_1180_0576[] = "R5C576 SD Bus Host Adapter"; +static const char pci_device_1180_0592[] = "R5C592 Memory Stick Bus Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0811[] = "R5C811"; +static const char pci_device_1180_0822[] = "R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0556[] = "Thinkpad X40"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_01a2[] = "Inspiron 9200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1043_1967[] = "ASUS V6800V"; +#endif +static const char pci_device_1180_0841[] = "R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394"; +static const char pci_device_1180_0852[] = "xD-Picture Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0852_1043_1967[] = "V6800V"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1025[] = "AirPlus Xtreme G DWL-G650 Adapter"; +static const char pci_device_1186_1026[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1043[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1303[] = "DFE-528TX 10/100 Fast Ethernet PCI Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1541[] = "DFE-680TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_2027[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3203[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3300[] = "DWL-510 2.4GHz Wireless PCI Adapter"; +static const char pci_device_1186_3a03[] = "AirPro DWL-A650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a04[] = "AirPro DWL-AB650 Multimode Wireless Cardbus Adapter"; +static const char pci_device_1186_3a05[] = "AirPro DWL-AB520 Multimode Wireless PCI Adapter"; +static const char pci_device_1186_3a07[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_3a08[] = "AirXpert DWL-AG520 Wireless PCI Adapter"; +static const char pci_device_1186_3a10[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a11[] = "AirXpert DWL-AG520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a12[] = "AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +static const char pci_device_1186_3a13[] = "AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a14[] = "AirPremier DWL-AG530 Wireless PCI Adapter"; +static const char pci_device_1186_3a63[] = "AirXpert DWL-AG660 Wireless Cardbus Adapter"; +static const char pci_device_1186_4000[] = "DL2000-based Gigabit Ethernet"; +static const char pci_device_1186_4300[] = "DGE-528T Gigabit Ethernet Adapter"; +static const char pci_device_1186_4c00[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_4c00_1186_4c00[] = "DGE-530T Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1186_8400[] = "D-Link DWL-650+ CardBus PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +static const char pci_device_1191_8060[] = "AEC6712 SCSI"; +static const char pci_device_1191_8080[] = "AEC67160 SCSI"; +static const char pci_device_1191_8081[] = "AEC67160S SCSI"; +static const char pci_device_1191_808a[] = "AEC67162 2-ch. LVD SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +static const char pci_device_1197_010c[] = "CompuScope 82G 8bit 2GS/s Analog Input Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Marvell Technology Group Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_138f[] = "W8300 802.11 Adapter (rev 07)"; +static const char pci_device_11ab_1fa6[] = "Marvell W8300 802.11 Adapter"; +static const char pci_device_11ab_1fa7[] = "88W8310 and 88W8000G [Libertas] 802.11g client chipset"; +static const char pci_device_11ab_1faa[] = "88w8335 [Libertas] 802.11b/g Wireless"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_1faa_1385_4e00[] = "WG511 v2 54MBit/ Wireless PC-Card"; +#endif +static const char pci_device_11ab_4320[] = "88E8001 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_0f38[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_8001[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_173c[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_811a[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_105b_0c19[] = "Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_10b8_b452[] = "EZ Card 1000 (SMC9452TXV.2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0121[] = "Marvell RDK-8001"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0321[] = "Marvell RDK-8003"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_1021[] = "Marvell RDK-8010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_5021[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_9521[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1458_e000[] = "Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_147b_1406[] = "Marvell 88E8001 Gigabit Ethernet Controller (Abit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_15d4_0047[] = "Marvell 88E8001 Gigabit Ethernet Controller (Iwill)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1695_9025[] = "Marvell 88E8001 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_17f2_1c03[] = "Marvell 88E8001 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_270f_2803[] = "Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)"; +#endif +static const char pci_device_11ab_4340[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4341[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4342[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4343[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4344[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4345[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4346[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4347[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4350[] = "88E8035 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1179_0001[] = "Marvell 88E8035 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_11ab_3521[] = "Marvell RDK-8035"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000d[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000f[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0011[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0012[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0016[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0017[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0018[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0019[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001c[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0020[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4351[] = "88E8036 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_107b_4009[] = "Marvell 88E8036 Fast Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_10f7_8338[] = "Marvell 88E8036 Fast Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_0001[] = "Marvell 88E8036 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff00[] = "Marvell 88E8036 Fast Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff10[] = "Marvell 88E8036 Fast Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_11ab_3621[] = "Marvell RDK-8036"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_13d1_ac12[] = "Abocom EFE3K - 10/100 Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_161f_203d[] = "Marvell 88E8036 Fast Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000d[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000f[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0011[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0012[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0016[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0017[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0018[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0019[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001c[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0020[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4352[] = "88E8038 PCI-E Fast Ethernet Controller"; +static const char pci_device_11ab_4360[] = "88E8052 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1043_8134[] = "Marvell 88E8052 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_107b_4009[] = "Marvell 88E8052 Gigabit Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_11ab_5221[] = "Marvell RDK-8052"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1458_e000[] = "Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1462_052c[] = "Marvell 88E8052 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1849_8052[] = "Marvell 88E8052 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_a0a0_0509[] = "Marvell 88E8052 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4361[] = "88E8050 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_107b_3015[] = "Marvell 88E8050 Gigabit Ethernet Controller (Gateway)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_11ab_5021[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3063[] = "D925XCVLK mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3439[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11ab_4362[] = "88E8053 PCI-E Gigabit Ethernet Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_103c_2a0d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1043_8142[] = "Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_109f_3197[] = "Marvell 88E8053 Gigabit Ethernet Controller (Trigem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10f7_8338[] = "Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10fd_a430[] = "Marvell 88E8053 Gigabit Ethernet Controller (SOYO)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_0001[] = "Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff00[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff10[] = "Marvell 88E8053 Gigabit Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_11ab_5321[] = "Marvell RDK-8053"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c240[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c241[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c242[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c243[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c244[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_13d1_ac11[] = "EGE5K - Giga Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1458_e000[] = "Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1462_058c[] = "Marvell 88E8053 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_14c0_0012[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1558_04a0[] = "Marvell 88E8053 Gigabit Ethernet Controller (Clevo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_15bd_1003[] = "Marvell 88E8053 Gigabit Ethernet Controller (DFI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203c[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1695_9029[] = "Marvell 88E8053 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17f2_2c08[] = "Marvell 88E8053 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17ff_0585[] = "Marvell 88E8053 Gigabit Ethernet Controller (Quanta)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1849_8053[] = "Marvell 88E8053 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000c[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0010[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0013[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0014[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0015[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001a[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001d[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001f[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0021[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0022[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_270f_2801[] = "Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_a0a0_0506[] = "Marvell 88E8053 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4363[] = "88E8055 PCI-E Gigabit Ethernet Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_5005[] = "Belkin F5D5005 Gigabit Desktop Network PCI Card"; +static const char pci_device_11ab_5040[] = "MV88SX5040 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5041[] = "MV88SX5041 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5080[] = "MV88SX5080 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5081[] = "MV88SX5081 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_6041[] = "MV88SX6041 4-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6081[] = "MV88SX6081 8-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6460[] = "MV64360/64361/64362 System Controller"; +static const char pci_device_11ab_6480[] = "MV64460/64461/64462 System Controller"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +static const char pci_device_11af_0001[] = "Cinema"; +static const char pci_device_11af_ee40[] = "Digidesign Audiomedia III"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +static const char pci_device_11bd_bede[] = "Pinnacle AV/DV Studio Capture Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Agere Systems"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2203[] = "PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2204[] = "PRO/100+ MiniPCI on Armada E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1033_80a8[] = "Versa Note Vxi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1468_0450[] = "Evo N600c"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_4005_144f[] = "LifeBook C Series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_048c[] = "V.92 56K WinModem"; +static const char pci_device_11c1_048f[] = "V.92 56k WinModem"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_8086_524c[] = "D865PERL mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +static const char pci_device_11c1_8110[] = "T8110 H.100/H.110 TDM switch"; +static const char pci_device_11c1_ab10[] = "WL60010 Wireless LAN MAC"; +static const char pci_device_11c1_ab11[] = "WL60040 Multimode Wireles LAN MAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab12[] = "WaveLAN 11abg Cardbus card (Model 1102)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab13[] = "WaveLAN 11abg MiniPCI card (Model 0512)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab15[] = "WaveLAN 11abg Cardbus card (Model 1106)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab16[] = "WaveLAN 11abg MiniPCI card (Model 0516)"; +#endif +static const char pci_device_11c1_ab20[] = "ORiNOCO PCI Adapter"; +static const char pci_device_11c1_ab21[] = "Agere Wireless PCI Adapter"; +static const char pci_device_11c1_ab30[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab30_14cd_2012[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1535[] = "Blackfin BF535 processor"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +static const char pci_device_11d4_5340[] = "AD1881 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_12f8_8a02[] = "Tekram Video Kit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1de1_9fff[] = "Video Kit C210"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_0001[] = "COM-ON-AIR Dosch&Amand DECT"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 32 port w/external I/F"; +static const char pci_device_11fe_0002[] = "RocketPort 8 port w/external I/F"; +static const char pci_device_11fe_0003[] = "RocketPort 16 port w/external I/F"; +static const char pci_device_11fe_0004[] = "RocketPort 4 port w/quad cable"; +static const char pci_device_11fe_0005[] = "RocketPort 8 port w/octa cable"; +static const char pci_device_11fe_0006[] = "RocketPort 8 port w/RJ11 connectors"; +static const char pci_device_11fe_0007[] = "RocketPort 4 port w/RJ11 connectors"; +static const char pci_device_11fe_0008[] = "RocketPort 8 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_0009[] = "RocketPort 16 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_000a[] = "RocketPort Plus 4 port"; +static const char pci_device_11fe_000b[] = "RocketPort Plus 8 port"; +static const char pci_device_11fe_000c[] = "RocketModem 6 port"; +static const char pci_device_11fe_000d[] = "RocketModem 4-port"; +static const char pci_device_11fe_000e[] = "RocketPort Plus 2 port RS232"; +static const char pci_device_11fe_000f[] = "RocketPort Plus 2 port RS422"; +static const char pci_device_11fe_0801[] = "RocketPort UPCI 32 port w/external I/F"; +static const char pci_device_11fe_0802[] = "RocketPort UPCI 8 port w/external I/F"; +static const char pci_device_11fe_0803[] = "RocketPort UPCI 16 port w/external I/F"; +static const char pci_device_11fe_0805[] = "RocketPort UPCI 8 port w/octa cable"; +static const char pci_device_11fe_080c[] = "RocketModem III 8 port"; +static const char pci_device_11fe_080d[] = "RocketModem III 4 port"; +static const char pci_device_11fe_0812[] = "RocketPort UPCI Plus 8 port RS422"; +static const char pci_device_11fe_0903[] = "RocketPort Compact PCI 16 port w/external I/F"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +static const char pci_device_11ff_0003[] = "AG-5"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 CardBus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 CardBus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 CardBus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 CardBus Controller"; +static const char pci_device_1217_6933[] = "OZ6933/711E1 CardBus/SmartCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ601/6912/711E0 CardBus/SmartCardBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1014_020c[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1217_7110[] = "OZ711Mx 4-in-1 MemoryCardBus Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7112[] = "OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller"; +static const char pci_device_1217_7113[] = "OZ711EC1 SmartCardBus Controller"; +static const char pci_device_1217_7114[] = "OZ711M1/MC1 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7134[] = "OZ711MP1/MS1 MemoryCardBus Controller"; +static const char pci_device_1217_71e2[] = "OZ711E2 SmartCardBus Controller"; +static const char pci_device_1217_7212[] = "OZ711M2 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7213[] = "OZ6933E CardBus Controller"; +static const char pci_device_1217_7223[] = "OZ711M3/MC3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7233[] = "OZ711MP3/MS3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3 2000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0057[] = "Voodoo3 3000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0003[] = "Voodoo5 PCI 5500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +static const char pci_device_1227_0006[] = "Raptor GFX 8P"; +static const char pci_device_1227_0023[] = "Raptor GFX [1100T]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000f[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_1809_0016[] = "Emuzed MAUI-III PCI PVR FM TV"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +static const char pci_device_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +static const char pci_device_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +static const char pci_device_1244_2700[] = "Fritz!Card DSL SL"; +static const char pci_device_1244_2900[] = "Fritz!Card DSL v2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infortrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +static const char pci_device_1259_a117[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a120[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204 Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125b_1400_1186_1100[] = "AX8814X Based PCI Fast Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0101[] = "Saturn 4520P"; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_153b_111b[] = "Terratec 128i PCI"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700/E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_0e11_0098[] = "Evo N600c"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00b1[] = "Latitude C600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Intersil Corporation"; +static const char pci_device_1260_3872[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3872_1468_0202[] = "LAN-Express IEEE 802.11b Wireless LAN"; +#endif +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3700[] = "DWL-520 Wireless PCI Adapter, Rev E1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1385_4105[] = "MA311 802.11b wireless adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_16a5_1601[] = "AIR.mate PC-400 PCI Wireless LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_3886[] = "ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3886_17cf_0037[] = "XG-901 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_3890[] = "ISL3890 [Prism GT/Prism Duette]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2802[] = "SMC2802W Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2835[] = "SMC2835W Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_a835[] = "SMC2835W V2 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_4203[] = "WN4201B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee03[] = "SMC2802W V2 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee08[] = "SMC2835W V3 EU Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1186_3202[] = "DWL-G650 A1 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1259_c104[] = "CG-WLCB54GT Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1385_4800[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_16a5_1605[] = "ALLNET ALL0271 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0014[] = "XG-600 and clones Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0020[] = "XG-900 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +static const char pci_device_1260_ffff[] = "ISL3886IK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +static const char pci_device_126c_1211[] = "10/100BaseTX [RTL81xx]"; +static const char pci_device_126c_126c[] = "802.11b Wireless Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0501[] = "SM501 VoyagerGX Rev. AA"; +static const char pci_device_126f_0510[] = "SM501 VoyagerGX Rev. B"; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0730[] = "SM731 Cougar3DR"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1171[] = "ES1373 [AudioPCI] (also Creative Labs CT5803)"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_8001[] = "CT4751 board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_8001[] = "Sound Blaster 16PCI 4.1ch"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +static const char pci_device_1278_0710[] = "TPE5 PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0060[] = "TM8000 Northbridge"; +static const char pci_device_1279_0061[] = "TM8000 AGP bridge"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1005_127a[] = "AOpen FM56-P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9102[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8211[] = "ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller))"; +static const char pci_device_1283_8212[] = "IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8212_1283_0001[] = "IT/ITE8212 Dual channel ATA RAID controller"; +#endif +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8872[] = "IT8874F PCI Dual Serial Port Controller"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +static const char pci_device_12a3_8105[] = "T8105 H100 Digital Switch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_0000[] = "MPG160/Kuroutoshikou ITVC15-STVLP"; +static const char pci_device_12ab_0002[] = "AU8830 [Vortex2] Based Sound Card With A3D Support"; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +static const char pci_device_12ab_fff3[] = "MPG600/Kuroutoshikou ITVC16-STVLP"; +static const char pci_device_12ab_ffff[] = "MPG600/Kuroutoshikou ITVC16-STVLP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1014_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_10a9_8002[] = "Acenic Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +static const char pci_device_12ae_00fa[] = "Farallon PN9100-T Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "3Com Corp, Modem Division"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +static const char pci_device_12c4_0001[] = "Blue HEAT/PCI 8 (RS232/CL/RJ11)"; +static const char pci_device_12c4_0002[] = "Blue HEAT/PCI 4 (RS232)"; +static const char pci_device_12c4_0003[] = "Blue HEAT/PCI 2 (RS232)"; +static const char pci_device_12c4_0004[] = "Blue HEAT/PCI 8 (UNIV, RS485)"; +static const char pci_device_12c4_0005[] = "Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485)"; +static const char pci_device_12c4_0006[] = "Blue HEAT/PCI 4 (OPTO, RS485)"; +static const char pci_device_12c4_0007[] = "Blue HEAT/PCI 2+2 (RS232/485)"; +static const char pci_device_12c4_0008[] = "Blue HEAT/PCI 2 (OPTO, Tx, RS485)"; +static const char pci_device_12c4_0009[] = "Blue HEAT/PCI 2+6 (RS232/485)"; +static const char pci_device_12c4_000a[] = "Blue HEAT/PCI 8 (Tx, RS485)"; +static const char pci_device_12c4_000b[] = "Blue HEAT/PCI 4 (Tx, RS485)"; +static const char pci_device_12c4_000c[] = "Blue HEAT/PCI 2 (20 MHz, RS485)"; +static const char pci_device_12c4_000d[] = "Blue HEAT/PCI 2 PTM"; +static const char pci_device_12c4_0100[] = "NT960/PCI"; +static const char pci_device_12c4_0201[] = "cPCI Titan - 2 Port"; +static const char pci_device_12c4_0202[] = "cPCI Titan - 4 Port"; +static const char pci_device_12c4_0300[] = "CTI PCI UART 2 (RS232)"; +static const char pci_device_12c4_0301[] = "CTI PCI UART 4 (RS232)"; +static const char pci_device_12c4_0302[] = "CTI PCI UART 8 (RS232)"; +static const char pci_device_12c4_0310[] = "CTI PCI UART 1+1 (RS232/485)"; +static const char pci_device_12c4_0311[] = "CTI PCI UART 2+2 (RS232/485)"; +static const char pci_device_12c4_0312[] = "CTI PCI UART 4+4 (RS232/485)"; +static const char pci_device_12c4_0320[] = "CTI PCI UART 2"; +static const char pci_device_12c4_0321[] = "CTI PCI UART 4"; +static const char pci_device_12c4_0322[] = "CTI PCI UART 8"; +static const char pci_device_12c4_0330[] = "CTI PCI UART 2 (RS485)"; +static const char pci_device_12c4_0331[] = "CTI PCI UART 4 (RS485)"; +static const char pci_device_12c4_0332[] = "CTI PCI UART 8 (RS485)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +static const char pci_device_12d4_0200[] = "T1 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies Inc"; +static const char pci_device_12d5_0003[] = "BSP16"; +static const char pci_device_12d5_1000[] = "BSP15"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +static const char pci_device_12d8_8150[] = "PCI to PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +static const char pci_device_12d9_0002[] = "PCI Prosody"; +static const char pci_device_12d9_0004[] = "cPCI Prosody"; +static const char pci_device_12d9_0005[] = "Aculab E1/T1 PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +static const char pci_device_12de_0200[] = "CryptoSwift CS200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +static const char pci_device_12fb_0001[] = "PMC-MAI"; +static const char pci_device_12fb_00f5[] = "F5 Dakar"; +static const char pci_device_12fb_02ad[] = "PMC-2MAI"; +static const char pci_device_12fb_2adc[] = "ePMC-2ADC"; +static const char pci_device_12fb_3100[] = "PRO-3100"; +static const char pci_device_12fb_3500[] = "PRO-3500"; +static const char pci_device_12fb_4d4f[] = "Modena"; +static const char pci_device_12fb_8120[] = "ePMC-8120"; +static const char pci_device_12fb_da62[] = "Daytona C6201 PCI (Hurricane)"; +static const char pci_device_12fb_db62[] = "Ingliston XBIF"; +static const char pci_device_12fb_dc62[] = "Ingliston PLX9054"; +static const char pci_device_12fb_dd62[] = "Ingliston JTAG/ISP"; +static const char pci_device_12fb_eddc[] = "ePMC-MSDDC"; +static const char pci_device_12fb_fa01[] = "ePMC-FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Measurement Computing"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +static const char pci_device_1307_004d[] = "PCI-QUAD04"; +static const char pci_device_1307_0052[] = "PCI-DAS4020/12"; +static const char pci_device_1307_0054[] = "PCI-DIO96"; +static const char pci_device_1307_005e[] = "PCI-DAS6025"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "Linksys"; +static const char pci_device_1317_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_0985[] = "NC100 Network Everywhere Fast Ethernet 10/100"; +static const char pci_device_1317_1985[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_2850[] = "HSP MicroModem 56"; +static const char pci_device_1317_5120[] = "ADMtek ADM5120 OpenGate System-on-Chip"; +static const char pci_device_1317_8201[] = "ADMtek ADM8211 802.11b Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_10b8_2635[] = "SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_1317_8201[] = "SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card"; +#endif +static const char pci_device_1317_8211[] = "ADMtek ADM8211 802.11b Wireless Interface"; +static const char pci_device_1317_9511[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "GNIC-II PCI Gigabit Ethernet [Hamachi]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0801_1319_1319[] = "FM801 PCI Audio"; +#endif +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0802_1319_1319[] = "FM801 PCI Joystick"; +#endif +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_2081[] = "CyberSerial (8-port) ST16654"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +static const char pci_device_1331_0030[] = "ENP-2611"; +static const char pci_device_1331_8200[] = "82600 Host Bridge"; +static const char pci_device_1331_8201[] = "82600 IDE"; +static const char pci_device_1331_8202[] = "82600 USB"; +static const char pci_device_1331_8210[] = "82600 PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +static const char pci_device_1332_5425[] = "MM-5425CN PCI 64/66 Memory Module with Battery Backup"; +static const char pci_device_1332_6140[] = "MM-6140D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_2189[] = "HSP56 MicroModem"; +static const char pci_device_134d_2486[] = "2304WT V.92 MDC Modem"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7890_134d_0001[] = "PCT789 adapter"; +#endif +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_5101[] = "Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32)"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +static const char pci_device_1360_0101[] = "PCI32 DCF77 Radio Clock"; +static const char pci_device_1360_0102[] = "PCI509 DCF77 Radio Clock"; +static const char pci_device_1360_0103[] = "PCI510 DCF77 Radio Clock"; +static const char pci_device_1360_0201[] = "GPS167PCI GPS Receiver"; +static const char pci_device_1360_0202[] = "GPS168PCI GPS Receiver"; +static const char pci_device_1360_0203[] = "GPS169PCI GPS Receiver"; +static const char pci_device_1360_0301[] = "TCR510PCI IRIG Timecode Reader"; +static const char pci_device_1360_0302[] = "TCR167PCI IRIG Timecode Reader"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +static const char pci_device_136b_ff01[] = "KL5A72002 Motion JPEG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +static const char pci_device_1371_434e[] = "GigaCard Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1371_434e_1371_434e[] = "N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd."; +static const char pci_device_1374_0024[] = "Silicom Dual port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0025[] = "Silicom Quad port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0026[] = "Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0027[] = "Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0029[] = "Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002a[] = "Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002b[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002c[] = "Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002d[] = "Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002e[] = "Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002f[] = "Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0030[] = "Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0031[] = "Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter"; +static const char pci_device_1374_0032[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_0034[] = "Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0035[] = "Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0036[] = "Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0037[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0038[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0039[] = "Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_003a[] = "Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +static const char pci_device_137a_0001[] = "PCI-324 Audiowire Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +static const char pci_device_1382_0001[] = "ARC88 audio recording card"; +static const char pci_device_1382_2008[] = "Prodif 96 Pro sound system"; +static const char pci_device_1382_2088[] = "Marc 8 Midi sound system"; +static const char pci_device_1382_20c8[] = "Marc A sound system"; +static const char pci_device_1382_4008[] = "Marc 2 sound system"; +static const char pci_device_1382_4010[] = "Marc 2 Pro sound system"; +static const char pci_device_1382_4048[] = "Marc 4 MIDI sound system"; +static const char pci_device_1382_4088[] = "Marc 4 Digi sound system"; +static const char pci_device_1382_4248[] = "Marc X sound system"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_0013[] = "WG311T"; +static const char pci_device_1385_311a[] = "GA511 Gigabit Ethernet"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_4105[] = "MA311 802.11b wireless adapter"; +static const char pci_device_1385_4400[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4600[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4601[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4610[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4800[] = "WG511(v1) 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4900[] = "WG311v1 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4a00[] = "WAG311 802.11a/g Wireless PCI Adapter"; +static const char pci_device_1385_4b00[] = "WG511T 108 Mbps Wireless PC Card"; +static const char pci_device_1385_4c00[] = "WG311v2 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4e00[] = "WG511v2 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4f00[] = "WG511U Double 108 Mbps Wireless PC Card"; +static const char pci_device_1385_620a[] = "GA620 Gigabit Ethernet"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630 Gigabit Ethernet"; +static const char pci_device_1385_6b00[] = "WG311v3 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_f004[] = "FA310TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1141[] = "Industrio CP-114"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_16b8[] = "ISDN network Controller [HFC-8S]"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1708[] = "ISDN Adapter (PCI Bus, D, C, ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +static const char pci_device_13a3_001d[] = "7956 Security Processor"; +static const char pci_device_13a3_0020[] = "7955 Security Processor"; +static const char pci_device_13a3_0026[] = "8155 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0152[] = "XR17C/D152 Dual PCI UART"; +static const char pci_device_13a8_0154[] = "XR17C154 Quad UART"; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink Adapter v1"; +static const char pci_device_13c0_0020[] = "SyncLink SCC Adapter"; +static const char pci_device_13c0_0030[] = "SyncLink Multiport Adapter"; +static const char pci_device_13c0_0210[] = "SyncLink Adapter v2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "5xxx/6xxx-series PATA-RAID"; +static const char pci_device_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13c1_1001_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#endif +static const char pci_device_13c1_1002[] = "9xxx-series SATA-RAID"; +static const char pci_device_13c1_1003[] = "9550SX SATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +static const char pci_device_13c6_0520[] = "CEI-520 A429 Card"; +static const char pci_device_13c6_0620[] = "CEI-620 A429 Card"; +static const char pci_device_13c6_0820[] = "CEI-820 A429 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card"; +static const char pci_device_13d0_2200[] = "B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab03[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +static const char pci_device_13d1_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Intraserver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc / IC Plus Corp"; +static const char pci_device_13f0_0200[] = "IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +static const char pci_device_13f0_1023[] = "IC Plus IP1000 Family Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0011[] = "CMI8738"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8035[] = "CUSI-FX motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1681_a000[] = "Gamesurround MUSE XL"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1240[] = "PCI-1240 4-channel stepper motor controller card"; +static const char pci_device_13fe_1600[] = "PCI-1612 4-port RS-232/422/485 PCI communication card"; +static const char pci_device_13fe_1733[] = "PCI-1733 32-channel isolated digital input card"; +static const char pci_device_13fe_1752[] = "PCI-1752"; +static const char pci_device_13fe_1754[] = "PCI-1754"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0110[] = "Lava DSerial-PCI Port A"; +static const char pci_device_1407_0111[] = "Lava DSerial-PCI Port B"; +static const char pci_device_1407_0120[] = "Quattro-PCI A"; +static const char pci_device_1407_0121[] = "Quattro-PCI B"; +static const char pci_device_1407_0180[] = "Lava Octo A"; +static const char pci_device_1407_0181[] = "Lava Octo B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0220[] = "Lava Quattro PCI Ports A/B"; +static const char pci_device_1407_0221[] = "Lava Quattro PCI Ports C/D"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "VIA Technologies Inc."; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24] PCI Multi-Channel I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_1712[] = "Hoontech ST Audio DSP 24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d630[] = "M-Audio Delta 1010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d631[] = "M-Audio Delta DiO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d632[] = "M-Audio Delta 66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d633[] = "M-Audio Delta 44"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d634[] = "M-Audio Delta Audiophile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d635[] = "M-Audio Delta TDIF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d637[] = "M-Audio Delta RBUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d638[] = "M-Audio Delta 410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63b[] = "M-Audio Delta 1010LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63c[] = "Digigram VX442"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1416_1712[] = "Hoontech ST Audio DSP 24 Media 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1115[] = "EWS88 MT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1125[] = "EWS88 MT (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112b[] = "EWS88 D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112c[] = "EWS88 D (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1130[] = "EWX 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1138[] = "DMX 6fire 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1151[] = "PHASE88"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_16ce_1040[] = "Edirol DA-2496"; +#endif +static const char pci_device_1412_1724[] = "VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_1724[] = "AMP Ltd AUDIO2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3630[] = "M-Audio Revolution 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3631[] = "M-Audio Revolution 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1145[] = "Aureon 7.1 Space"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1147[] = "Aureon 5.1 Sky"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1153[] = "Aureon 7.1 Universe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f641[] = "ZNF3-150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f645[] = "ZNF3-250"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2050[] = "CyberPro (4-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2051[] = "CyberSerial 4S Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9510[] = "OX16PCI954 (Quad 16950 UART) function 1 (Disabled)"; +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +static const char pci_device_1415_9523[] = "OX16PCI952 Integrated Parallel Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +static const char pci_device_1420_8002[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part)"; +static const char pci_device_1420_8003[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "Chelsio Communications Inc"; +static const char pci_device_1425_000b[] = "T210 Protocol Engine"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +static const char pci_device_142e_4020[] = "VM2-2 [Video Maker 2] MPEG1/2 Encoder"; +static const char pci_device_142e_4337[] = "VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +static const char pci_device_1432_9130[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "RTD Embedded Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8164[] = "PCI-8164"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +static const char pci_device_1458_0c11[] = "K8NS Pro Mainboard"; +static const char pci_device_1458_e911[] = "GN-WIAG02"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +static const char pci_device_1461_a3ce[] = "AVerMedia M179"; +static const char pci_device_1461_a3cf[] = "AVerMedia M179"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +static const char pci_device_1462_5501[] = "nVidia NV15DDR [GeForce2 Ti]"; +static const char pci_device_1462_6819[] = "Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G]"; +static const char pci_device_1462_6825[] = "PCI Card wireless 11g [PC54G]"; +static const char pci_device_1462_8725[] = "NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter"; +static const char pci_device_1462_9000[] = "NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter"; +static const char pci_device_1462_9110[] = "GeFORCE FX5200"; +static const char pci_device_1462_9119[] = "NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter"; +static const char pci_device_1462_9591[] = "nVidia Corporation NV36 [GeForce FX 5700LE]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +static const char pci_device_146c_1430[] = "FE-1430TX Fast Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +static const char pci_device_1497_1497[] = "SMA Technologie AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +static const char pci_device_1498_21cd[] = "TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_30c8[] = "TPCI200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +static const char pci_device_149d_0001[] = "Video Toaster for PC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "PulsarSRB"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +static const char pci_device_14b9_a505[] = "Cisco Aironet CB20a 802.11a Wireless LAN Adapter"; +static const char pci_device_14b9_a506[] = "Cisco Aironet Mini PCI b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +static const char pci_device_14c1_8043[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alliance Semiconductor Corporation"; +static const char pci_device_14d9_0010[] = "AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon]"; +static const char pci_device_14d9_9000[] = "AS90L10204/10208 HyperTransport to PCI-X Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_0800[] = "Sentry5 Chipcommon I/O Controller"; +static const char pci_device_14e4_0804[] = "Sentry5 PCI Bridge"; +static const char pci_device_14e4_0805[] = "Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_0806[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_080b[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_080f[] = "Sentry5 DDR/SDR RAM Controller"; +static const char pci_device_14e4_0811[] = "Sentry5 External Interface Core"; +static const char pci_device_14e4_0816[] = "BCM3302 Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_1600[] = "NetXtreme BCM5752 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1601[] = "NetXtreme BCM5752M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128a[] = "1000Base-T (PCI) [A7061A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128b[] = "1000Base-SX (PCI) [A7073A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12a4[] = "Core Lan 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12c1[] = "IOX Core Lan 1000Base-T [A7109AX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_1300[] = "Core LAN/SCSI Combo [A6794A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8010[] = "IO9/IO10 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8011[] = "Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8012[] = "Gigabit Ethernet (Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_10a9_8010[] = "SGI IO9 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1734_100b[] = "Primergy RX300"; +#endif +static const char pci_device_14e4_164a[] = "NetXtreme II BCM5706 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3101[] = "NC370T Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164c[] = "NetXtreme II BCM5708 Gigabit Ethernet"; +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1653_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1654[] = "NetXtreme BCM5705_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3100[] = "NC1020 HP ProLiant Gigabit Server Adapter 32 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3226[] = "NC150T 4-port Gigabit Combo Switch & Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1659[] = "NetXtreme BCM5721 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7031[] = "NC320T PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7032[] = "NC320i PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1734_1061[] = "Primergy RX300 S2"; +#endif +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165d_1028_865d[] = "Latitude D400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_165e[] = "NetXtreme BCM5705M_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1668[] = "NetXtreme BCM5714 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1668_103c_7039[] = "NC324i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_166a[] = "NetXtreme BCM5780 Gigabit Ethernet"; +static const char pci_device_14e4_166b[] = "NetXtreme BCM5780S Gigabit Ethernet"; +static const char pci_device_14e4_166e[] = "570x 10/100 Integrated Controller"; +static const char pci_device_14e4_1677[] = "NetXtreme BCM5751 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0182[] = "Latitude D610"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_01ad[] = "Optiplex GX620"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1734_105d[] = "Scenic W620"; +#endif +static const char pci_device_14e4_1678[] = "NetXtreme BCM5715 Gigabit Ethernet"; +static const char pci_device_14e4_167d[] = "NetXtreme BCM5751M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167e[] = "NetXtreme BCM5751F Fast Ethernet PCI Express"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_103c_12bc[] = "HP d530 CMT (DG746A)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_169c[] = "NetXtreme BCM5788 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_169c_103c_308b[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_169d[] = "NetLink BCM5789 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16aa[] = "NetXtreme II BCM5706S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16aa_103c_3102[] = "NC370F Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16ac[] = "NetXtreme II BCM5708S Gigabit Ethernet"; +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702A3 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12c3[] = "Combo FC/GigE-SX [A9782A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12ca[] = "Combo FC/GigE-T [A9784A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_16dd[] = "NetLink BCM5781 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16f7[] = "NetXtreme BCM5753 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fd[] = "NetXtreme BCM5753M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fe[] = "NetXtreme BCM5753F Fast Ethernet PCI Express"; +static const char pci_device_14e4_170c[] = "BCM4401-B0 100Base-TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_170d[] = "NetXtreme BCM5901 100Base-TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170d_1014_0545[] = "ThinkPad R40e (2684-HVG) builtin ethernet controller"; +#endif +static const char pci_device_14e4_170e[] = "NetXtreme BCM5901 100Base-TX"; +static const char pci_device_14e4_3352[] = "BCM3352"; +static const char pci_device_14e4_3360[] = "BCM3360"; +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4303 802.11b Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1028_0407[] = "TrueMobile 1180 Onboard WLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1043_0120[] = "WL-103b Wireless LAN PC Card"; +#endif +static const char pci_device_14e4_4305[] = "BCM4307 V.90 56k Modem"; +static const char pci_device_14e4_4306[] = "BCM4307 Ethernet Controller"; +static const char pci_device_14e4_4307[] = "BCM4307 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4310[] = "BCM4310 Chipcommon I/OController"; +static const char pci_device_14e4_4312[] = "BCM4310 UART"; +static const char pci_device_14e4_4313[] = "BCM4310 Ethernet Controller"; +static const char pci_device_14e4_4315[] = "BCM4310 USB Controller"; +static const char pci_device_14e4_4318[] = "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_103c_1356[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0311[] = "Aspire 3022WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_0449[] = "Gateway 7510GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_4318[] = "WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_16ec_0119[] = "U.S.Robotics Wireless MAXg PC Card"; +#endif +static const char pci_device_14e4_4319[] = "Dell Wireless 1470 DualBand WLAN"; +static const char pci_device_14e4_4320[] = "BCM4306 802.11b/g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0001[] = "TrueMobile 1300 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0003[] = "Wireless 1350 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12fa[] = "Presario R3000 802.11b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1043_100f[] = "WL-100G"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1057_7025[] = "WN825G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_106b_004e[] = "AirPort Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_14e4_4320[] = "Linksys WMP54G PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1737_4320[] = "WPC54G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7001[] = "Belkin F5D7001 High-Speed Mode Wireless G Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7010[] = "Belkin F5D7010 54g Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_185f_1220[] = "Acer TravelMate 290E WLAN Mini-PCI Card"; +#endif +static const char pci_device_14e4_4321[] = "BCM4306 802.11a Wireless LAN Controller"; +static const char pci_device_14e4_4322[] = "BCM4306 UART"; +static const char pci_device_14e4_4324[] = "BCM4309 802.11a/b/g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0001[] = "Truemobile 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0003[] = "Truemobile 1450 MiniPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_4325[] = "BCM43xG 802.11b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0003[] = "Wireless Notebook Adapter MN-720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0004[] = "Wireless PCI Adapter MN-730"; +#endif +static const char pci_device_14e4_4326[] = "BCM4307 Chipcommon I/O Controller?"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_1043_80a8[] = "A7V8X motherboard"; +#endif +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4403[] = "BCM4402 V.90 56k Modem"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4412 10/100BaseT"; +static const char pci_device_14e4_4430[] = "BCM44xx CardBus iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4432[] = "BCM4432 CardBus 10/100BaseT"; +static const char pci_device_14e4_4610[] = "BCM4610 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4611[] = "BCM4610 Sentry5 iLine32 HomePNA 1.0"; +static const char pci_device_14e4_4612[] = "BCM4610 Sentry5 V.90 56k Modem"; +static const char pci_device_14e4_4613[] = "BCM4610 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4614[] = "BCM4610 Sentry5 External Interface"; +static const char pci_device_14e4_4615[] = "BCM4610 Sentry5 USB Controller"; +static const char pci_device_14e4_4704[] = "BCM4704 PCI to SB Bridge"; +static const char pci_device_14e4_4705[] = "BCM4704 Sentry5 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4706[] = "BCM4704 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4707[] = "BCM4704 Sentry5 USB Controller"; +static const char pci_device_14e4_4708[] = "BCM4704 Crypto Accelerator"; +static const char pci_device_14e4_4710[] = "BCM4710 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4711[] = "BCM47xx Sentry5 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4712[] = "BCM47xx V.92 56k modem"; +static const char pci_device_14e4_4713[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4714[] = "BCM47xx Sentry5 External Interface"; +static const char pci_device_14e4_4715[] = "Sentry5 USB Controller"; +static const char pci_device_14e4_4716[] = "BCM47xx Sentry5 USB Host Controller"; +static const char pci_device_14e4_4717[] = "BCM47xx Sentry5 USB Device Controller"; +static const char pci_device_14e4_4718[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_4720[] = "BCM4712 MIPS CPU"; +static const char pci_device_14e4_5365[] = "BCM5365P Sentry5 Host Bridge"; +static const char pci_device_14e4_5600[] = "BCM5600 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5605[] = "BCM5605 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5615[] = "BCM5615 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5625[] = "BCM5625 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5645[] = "BCM5645 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5670[] = "BCM5670 8-Port 10GE Ethernet Switch Fabric"; +static const char pci_device_14e4_5680[] = "BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5690[] = "BCM5690 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5691[] = "BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5692[] = "BCM5692 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +static const char pci_device_14e4_5822[] = "BCM5822 Crypto Accelerator"; +static const char pci_device_14e4_5823[] = "BCM5823 Crypto Accelerator"; +static const char pci_device_14e4_5824[] = "BCM5824 Crypto Accelerator"; +static const char pci_device_14e4_5840[] = "BCM5840 Crypto Accelerator"; +static const char pci_device_14e4_5841[] = "BCM5841 Crypto Accelerator"; +static const char pci_device_14e4_5850[] = "BCM5850 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +static const char pci_device_14ea_ab07[] = "RTL81xx RealTek Ethernet"; +static const char pci_device_14ea_ab08[] = "FNW-3602-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1085[] = "HCF V90 56k Data/Fax/Voice/Spkp PCI Modem"; +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1620[] = "AccessRunner V2 PCI ADSL Arbitration Device"; +static const char pci_device_14f1_1621[] = "AccessRunner V2 PCI ADSL Interface Device"; +static const char pci_device_14f1_1622[] = "AccessRunner V2 PCI ADSL Yukon WAN Adapter"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1811[] = "Conextant MiniPCI Network Adapter"; +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2045_14f1_2045[] = "Generic SoftK56"; +#endif +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_2f02[] = "HSF 56k HSFi Data/Fax"; +static const char pci_device_14f1_2f11[] = "HSF 56k HSFi Modem"; +static const char pci_device_14f1_2f20[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +static const char pci_device_14f1_8800[] = "CX23880/1/2/3 PCI Video and Audio Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9002[] = "Hauppauge Nova-T DVB-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_00f8[] = "ATI TV Wonder Pro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6613[] = "Leadtek Winfast 2000XP Expert"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6620[] = "Leadtek Winfast DV2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d003[] = "IODATA GV-VCP3/PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d035[] = "IODATA GV/BCTV7E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000b[] = "AverTV Studio 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14c7_0107[] = "GDI Black Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0342[] = "Digital-Logic MICROSPACE Entertainment Center (MEC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1540_2580[] = "Provideo PV259"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4811[] = "PixelView"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_a8a6[] = "digitalnow DNTV Live! DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8801[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8801_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +static const char pci_device_14f1_8802[] = "CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8804[] = "CX23880/1/2/3 PCI Video and Audio Decoder [IR Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8804_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +static const char pci_device_14f1_8811[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +static const char pci_device_14f2_0120[] = "EV1000 bridge"; +static const char pci_device_14f2_0121[] = "EV1000 Parallel port"; +static const char pci_device_14f2_0122[] = "EV1000 Serial port"; +static const char pci_device_14f2_0123[] = "EV1000 Keyboard controller"; +static const char pci_device_14f2_0124[] = "EV1000 Mouse controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BroadLogic"; +static const char pci_device_14f3_2030[] = "2030 DVB-S Satellite Reciever"; +static const char pci_device_14f3_2050[] = "2050 DVB-T Terrestrial (Cable) Reciever"; +static const char pci_device_14f3_2060[] = "2060 ATSC Terrestrial (Cable) Reciever"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +static const char pci_device_14f8_2077[] = "TP-240 dual span E1 VoIP PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOLTERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "Quadrics Ltd"; +static const char pci_device_14fc_0000[] = "QsNet Elan3 Network Adapter"; +static const char pci_device_14fc_0001[] = "QsNetII Elan4 Network Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +static const char pci_device_1500_1360[] = "RTL81xx RealTek Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0800[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +static const char pci_device_1516_0891[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +static const char pci_device_151c_0003[] = "Prodif T 2496"; +static const char pci_device_151c_4000[] = "Prodif 88"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0c00[] = "RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0d00[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_1d00[] = "RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2000[] = "RockForceD1 1 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2100[] = "RockForceF1 1 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2200[] = "RockForceD2 2 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2300[] = "RockForceF2 2 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2400[] = "RockForceD4 4 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2500[] = "RockForceF4 4 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2600[] = "RockForceD8 8 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2700[] = "RockForceF8 8 Port V.34 Super-G3 Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_0510[] = "CB710 Memory Card Reader Controller"; +static const char pci_device_1524_0520[] = "FLASH memory: ENE Technology Inc:"; +static const char pci_device_1524_0530[] = "ENE PCI Memory Stick Card Reader Controller"; +static const char pci_device_1524_0550[] = "ENE PCI Secure Digital Card Reader Controller"; +static const char pci_device_1524_0610[] = "PCI Smart Card Reader Controller"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1411[] = "CB-710/2/4 Cardbus Controller"; +static const char pci_device_1524_1412[] = "CB-712/4 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +static const char pci_device_1524_1421[] = "CB-720/2/4 Cardbus Controller"; +static const char pci_device_1524_1422[] = "CB-722/4 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +static const char pci_device_1538_0303[] = "ARS106S Ultra ATA 133/100/66 Host Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +static const char pci_device_153b_1144[] = "Aureon 5.1"; +static const char pci_device_153b_1147[] = "Aureon 5.1 Sky"; +static const char pci_device_153b_1158[] = "Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS Technologies, Inc."; +static const char pci_device_153f_0001[] = "SOC-it 101 System Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "VIVID Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +static const char pci_device_1578_5615[] = "VPMK3 [Video Processor Mk III]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMware Inc"; +static const char pci_device_15ad_0405[] = "[VMware SVGA II] PCI Display Adapter"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +static const char pci_device_15ad_0720[] = "VMware High-Speed Virtual NIC [vmxnet]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technologies"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +static const char pci_device_15b3_5a44[] = "MT23108 InfiniHost"; +static const char pci_device_15b3_5a45[] = "MT23108 [Infinihost HCA Flash Recovery]"; +static const char pci_device_15b3_5a46[] = "MT23108 PCI Bridge"; +static const char pci_device_15b3_5e8d[] = "MT25204 [InfiniHost III Lx HCA Flash Recovery]"; +static const char pci_device_15b3_6274[] = "MT25204 [InfiniHost III Lx HCA]"; +static const char pci_device_15b3_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_15b3_6279[] = "MT25208 [InfiniHost III Ex HCA Flash Recovery]"; +static const char pci_device_15b3_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_1100[] = "E8001-66442 PCI Express CIC"; +static const char pci_device_15bc_2922[] = "64 Bit, 133MHz PCI-X Exerciser & Protocol Checker"; +static const char pci_device_15bc_2928[] = "64 Bit, 66MHz PCI Exerciser & Analyzer"; +static const char pci_device_15bc_2929[] = "64 Bit, 133MHz PCI-X Analyzer & Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +static const char pci_device_15c5_8010[] = "1394b - 1394 Firewire 3-Port Host Adapter Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +static const char pci_device_15e9_1841[] = "ADMA-100 DiscStaQ ATA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +static const char pci_device_15ec_3101[] = "FC3101 Profibus DP 1 Channel PCI"; +static const char pci_device_15ec_5102[] = "FC5102"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_0610[] = "FarSync T1U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0620[] = "FarSync T2U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0640[] = "FarSync T4U (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_1610[] = "FarSync TE1 (T1,E1)"; +static const char pci_device_1619_2610[] = "FarSync DSL-S1 (SHDSL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_161f[] = "Rioworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1626[] = "TDK Semiconductor Corp."; +static const char pci_device_1626_8410[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1637[] = "Linksys"; +static const char pci_device_1637_3874[] = "Linksys 802.11b WMP11 PCI Wireless card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_3052[] = "SmartLink SmartPCI562 56K Modem"; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165f[] = "Linux Media Labs, LLC"; +static const char pci_device_165f_1020[] = "LMLM4 MPEG-4 encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +static const char pci_device_1668_0100[] = "Mini-PCI bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_166d[] = "Broadcom Corporation"; +static const char pci_device_166d_0001[] = "SiByte BCM1125/1125H/1250 System-on-a-Chip PCI"; +static const char pci_device_166d_0002[] = "SiByte BCM1125H/1250 System-on-a-Chip HyperTransport"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1677[] = "Bernecker + Rainer"; +static const char pci_device_1677_104e[] = "5LS172.6 B&R Dual CAN Interface Card"; +static const char pci_device_1677_12d7[] = "5LS172.61 B&R Dual CAN Interface Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167b[] = "ZyDAS Technology Corp."; +static const char pci_device_167b_2102[] = "ZyDAS ZD1202"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_167b_2102_187e_3406[] = "ZyAIR B-122 CardBus 11Mbs Wireless LAN Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +static const char pci_device_1681_0010[] = "Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1682[] = "XFX Pine Group Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1688[] = "CastleNet Technology Inc."; +static const char pci_device_1688_1170[] = "WLAN 802.11b card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_168c[] = "Atheros Communications, Inc."; +static const char pci_device_168c_0007[] = "AR5000 802.11a Wireless Adapter"; +static const char pci_device_168c_0011[] = "AR5210 802.11a NIC"; +static const char pci_device_168c_0012[] = "AR5211 802.11ab NIC"; +static const char pci_device_168c_0013[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1113_d301[] = "Philips CPWNA100 Wireless CardBus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3202[] = "D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3203[] = "DWL-G520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a12[] = "D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a13[] = "D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a14[] = "D-Link AirPremier DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a17[] = "D-Link AirPremier DWL-G680 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a18[] = "D-Link AirPremier DWL-G550 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a63[] = "D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a94[] = "C54C Wireless 801.11g cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1385_4d00[] = "Netgear WG311T Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1458_e911[] = "Gigabyte GN-WIAG02"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_14b7_0a60[] = "8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_0013[] = "WG511T Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1025[] = "DWL-G650B2 Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1027[] = "Netgate NL-3054CB ARIES b/g CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2026[] = "Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2041[] = "Netgate 5354MP Plus ARIES2 b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2042[] = "Netgate 5354MP Plus ARIES2 a/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_16ab_7302[] = "Trust Speedshare Turbo Pro Wireless PCI Adapter"; +#endif +static const char pci_device_168c_001a[] = "AR5005G 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a15[] = "D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a16[] = "D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a23[] = "D-Link AirPlus G DWL-G520+A Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a24[] = "D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_1052[] = "TP-Link TL-WN510G Wireless CardBus Adapter"; +#endif +static const char pci_device_168c_001b[] = "AR5006X 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a19[] = "D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a22[] = "D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter"; +#endif +static const char pci_device_168c_0020[] = "AR5005VL 802.11bg Wireless NIC"; +static const char pci_device_168c_1014[] = "AR5212 802.11abg NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1695[] = "EPoX Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_169c[] = "Netcell Corporation"; +static const char pci_device_169c_0044[] = "Revolution Storage Processing Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16a5[] = "Tekram Technology Co.,Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1100[] = "GL24110P"; +static const char pci_device_16ab_1101[] = "PLX9052 PCMCIA-to-PCI Wireless LAN"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +static const char pci_device_16ab_8501[] = "WL-8305 Wireless LAN PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ae[] = "Safenet Inc"; +static const char pci_device_16ae_1141[] = "SafeXcel-1141"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16af[] = "SparkLAN Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b4[] = "Aspex Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b8[] = "Sonnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c8[] = "Octasic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ca[] = "CENATEK Inc"; +static const char pci_device_16ca_0001[] = "Rocket Drive DL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16cd[] = "Densitron Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ce[] = "Roland Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16df[] = "PIKA Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e3[] = "European Space Agency"; +static const char pci_device_16e3_1e0f[] = "LEON2FT Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_00ff[] = "USR997900 10/100 Mbps PCI Network Card"; +static const char pci_device_16ec_0116[] = "USR997902 10/100/1000 Mbps PCI Network Card"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ed[] = "Sycron N. V."; +static const char pci_device_16ed_1001[] = "UMIO communication card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f3[] = "Jetway Information Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f4[] = "Vweb Corp"; +static const char pci_device_16f4_8000[] = "VW2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1702[] = "Internet Machines Corporation (IMC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave"; +static const char pci_device_170b_0100[] = "NSP2000-SSL crypto accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1725[] = "Vitesse Semiconductor"; +static const char pci_device_1725_7174[] = "VSC7174 PCI/PCI-X Serial ATA Host Bus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +static const char pci_device_172a_13c8[] = "AEP SureWare Runner 1000V3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1734[] = "Fujitsu Siemens Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +static const char pci_device_1737_0013[] = "WMP54G Wireless Pci Card"; +static const char pci_device_1737_0015[] = "WMP54GS Wireless Pci Card"; +static const char pci_device_1737_1032[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0015[] = "EG1032 v2 Instant Gigabit Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0024[] = "EG1032 v3 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_1064[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1064_1737_0016[] = "EG1064 v2 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1737_ab09[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03e9[] = "AC1001 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +static const char pci_device_173b_03eb[] = "AC1003 Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1749[] = "RLX Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174d[] = "WellX Telecom SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175c[] = "AudioScience Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1775[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1797[] = "JumpTec h, GMBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +static const char pci_device_1799_6001[] = "Wireless PCI Card - F5D6001"; +static const char pci_device_1799_6020[] = "Wireless PCMCIA Card - F5D6020"; +static const char pci_device_1799_6060[] = "Wireless PDA Card - F5D6060"; +static const char pci_device_1799_7000[] = "Wireless PCI Card - F5D7000"; +static const char pci_device_1799_7010[] = "BCM4306 802.11b/g Wireless Lan Controller F5D7010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_179c[] = "Data Patterns"; +static const char pci_device_179c_0557[] = "DP-PCI-557 [PCI 1553B]"; +static const char pci_device_179c_0566[] = "DP-PCI-566 [Intelligent PCI 1553B]"; +static const char pci_device_179c_5031[] = "DP-CPCI-5031-Synchro Module"; +static const char pci_device_179c_5121[] = "DP-CPCI-5121-IP Carrier"; +static const char pci_device_179c_5211[] = "DP-CPCI-5211-IP Carrier"; +static const char pci_device_179c_5679[] = "AGE Display Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17a0[] = "Genesys Logic, Inc"; +static const char pci_device_17a0_8033[] = "GL880S USB 1.1 controller"; +static const char pci_device_17a0_8034[] = "GL880S USB 2.0 controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17aa[] = "Lenovo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b3[] = "Hawking Technologies"; +static const char pci_device_17b3_ab08[] = "PN672TX 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b4[] = "Indra Networks, Inc."; +static const char pci_device_17b4_0011[] = "WebEnhance 100 GZIP Compression Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c0[] = "Wistron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c2[] = "Newisys, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cb[] = "Airgo Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cf[] = "Z-Com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d3[] = "Areca Technology Corp."; +static const char pci_device_17d3_1110[] = "ARC-1110 4-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1120[] = "ARC-1120 8-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1130[] = "ARC-1130 12-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1160[] = "ARC-1160 16-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1210[] = "ARC-1210 4-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1220[] = "ARC-1220 8-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1230[] = "ARC-1230 12-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1260[] = "ARC-1260 16-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_5831[] = "Xframe 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d3_5831_103c_12d5[] = "HP PCI-X 133MHz 10GbE SR Fiber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_17d3_5832[] = "Xframe II 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17de[] = "KWorld Computer Co. Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ee[] = "Connect Components Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17f2[] = "Albatron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17fe[] = "Linksys, A Division of Cisco Systems"; +static const char pci_device_17fe_2120[] = "WMP11v4 802.11b PCI card"; +static const char pci_device_17fe_2220[] = "[AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17fe_2220_17fe_2220[] = "WPC54G ver. 4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ff[] = "Benq Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1814[] = "RaLink"; +static const char pci_device_1814_0101[] = "Wireless PCI Adapter RT2400 / RT2460"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1043_0127[] = "WiFi-b add-on Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1462_6828[] = "PC11B2 (MS-6828) Wireless 11b PCI Card"; +#endif +static const char pci_device_1814_0201[] = "RT2500 802.11G Cardbus/mini-PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1043_130f[] = "WL-130g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001e[] = "CWC-854 Wireless-G CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001f[] = "CWM-854 Wireless-G Mini PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_0020[] = "CWP-854 Wireless-G PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e381[] = "GN-WMKG 802.11b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e931[] = "GN-WIKG 802.11b/g mini-PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1462_6835[] = "Wireless 11G CardBus CB54G2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1737_0032[] = "WMP54G 2.0 PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_700a[] = "F5D7000 Wireless G Desktop Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_701a[] = "F5D7010 Wireless G Notebook Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_185f_22a0[] = "CN-WF513 Wireless Cardbus Adapter"; +#endif +static const char pci_device_1814_0401[] = "Ralink RT2600 802.11 MIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1820[] = "InfiniCon Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1822[] = "Twinhan Technology Co. Ltd"; +static const char pci_device_1822_4e35[] = "Mantis DTV PCI Bridge Controller [Ver 1.0]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182d[] = "SiteCom Europe BV"; +static const char pci_device_182d_3069[] = "ISDN PCI DC-105V2"; +static const char pci_device_182d_9790[] = "WL-121 Wireless Network Adapter 100g+ [Ver.3]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1830[] = "Credence Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_183b[] = "MikroM GmbH"; +static const char pci_device_183b_08a7[] = "MVC100 DVI"; +static const char pci_device_183b_08a8[] = "MVC101 SDI"; +static const char pci_device_183b_08a9[] = "MVC102 DVI+Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1849[] = "ASRock Incorporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1854[] = "LG Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185b[] = "Compro Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185f[] = "Wistron NeWeb Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1864[] = "SilverBack"; +static const char pci_device_1864_2110[] = "ISNAP 2110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1867[] = "Topspin Communications"; +static const char pci_device_1867_5a44[] = "MT23108 InfiniHost HCA"; +static const char pci_device_1867_5a45[] = "MT23108 InfiniHost HCA flash recovery"; +static const char pci_device_1867_5a46[] = "MT23108 InfiniHost HCA bridge"; +static const char pci_device_1867_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_1867_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_187e[] = "ZyXEL Communication Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1894[] = "KNC One"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1896[] = "B&B Electronics Manufacturing Company, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18a1[] = "Astute Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ac[] = "DViCO Corporation"; +static const char pci_device_18ac_d500[] = "FusionHDTV 5"; +static const char pci_device_18ac_d810[] = "FusionHDTV 3 Gold"; +static const char pci_device_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18b8[] = "Ammasso"; +static const char pci_device_18b8_b001[] = "AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18bc[] = "Info-Tek Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c8[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c9[] = "ARVOO Engineering BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ca[] = "XGI - Xabre Graphics Inc"; +static const char pci_device_18ca_0020[] = "Volari Z7"; +static const char pci_device_18ca_0040[] = "Volari V3XT/V5/V8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18d2[] = "Sitecom"; +static const char pci_device_18d2_3069[] = "DC-105v2 ISDN controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18dd[] = "Artimi Inc"; +static const char pci_device_18dd_4c6f[] = "Artimi RTMI-100 UWB adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18e6[] = "MPL AG"; +static const char pci_device_18e6_0001[] = "OSCI [Octal Serial Communication Interface]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ec[] = "Cesnet, z.s.p.o."; +static const char pci_device_18ec_c006[] = "COMBO6"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d004[] = "COMBO-2XFP"; +#endif +static const char pci_device_18ec_c045[] = "COMBO6E"; +static const char pci_device_18ec_c050[] = "COMBO-PTM"; +static const char pci_device_18ec_c058[] = "COMBO6X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d004[] = "COMBO-2XFP"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f7[] = "Commtech, Inc."; +static const char pci_device_18f7_0001[] = "Fastcom ESCC-PCI-335"; +static const char pci_device_18f7_0002[] = "Fastcom 422/4-PCI-335"; +static const char pci_device_18f7_0004[] = "Fastcom 422/2-PCI-335"; +static const char pci_device_18f7_0005[] = "Fastcom IGESCC-PCI-ISO/1"; +static const char pci_device_18f7_000a[] = "Fastcom 232/4-PCI-335"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18fb[] = "Resilience Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1924[] = "Level 5 Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_192e[] = "TransDimension"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1931[] = "Option N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1942[] = "ClearSpeed Technology plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1957[] = "Freescale Semiconductor Inc"; +static const char pci_device_1957_0080[] = "MPC8349E"; +static const char pci_device_1957_0081[] = "MPC8349"; +static const char pci_device_1957_0082[] = "MPC8347E TBGA"; +static const char pci_device_1957_0083[] = "MPC8347 TBGA"; +static const char pci_device_1957_0084[] = "MPC8347E PBGA"; +static const char pci_device_1957_0085[] = "MPC8347 PBGA"; +static const char pci_device_1957_0086[] = "MPC8343E"; +static const char pci_device_1957_0087[] = "MPC8343"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1958[] = "Faster Technology, LLC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1966[] = "Orad Hi-Tec Systems"; +static const char pci_device_1966_1975[] = "DVG64 family"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196a[] = "Sensory Networks Inc."; +static const char pci_device_196a_0101[] = "NodalCore C-1000 Content Classification Accelerator"; +static const char pci_device_196a_0102[] = "NodalCore C-2000 Content Classification Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_197b[] = "JMicron Technologies, Inc."; +static const char pci_device_197b_2360[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2363[] = "JMicron 20360/20363 AHCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1989[] = "Montilio Inc."; +static const char pci_device_1989_0001[] = "RapidFile Bridge"; +static const char pci_device_1989_8001[] = "RapidFile"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1993[] = "Innominate Security Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ae[] = "Progeny Systems Corporation"; +static const char pci_device_19ae_0520[] = "4135 HFT Interface Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19d4[] = "Quixant Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc0[] = "Tumsan Oy"; +static const char pci_device_1fc0_0300[] = "E2200 Dual E1/Rawpipe Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc1[] = "PathScale, Inc"; +static const char pci_device_1fc1_000d[] = "InfiniPath HT-400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fce[] = "Cognio Inc."; +static const char pci_device_1fce_0001[] = "Spectrum Analyzer PC Card (SAgE)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0020[] = "HB6 Universal PCI-PCI bridge (transparent mode)"; +static const char pci_device_3388_0021[] = "HB6 Universal PCI-PCI bridge (non-transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1090[] = "Cx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3010[] = "PPCI mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3011[] = "PPCI mezzanine (64-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_4000[] = "PMCCARR1 carrier board"; +#endif +static const char pci_device_3388_0022[] = "HiNT HB4 PCI-PCI Bridge (PCI6150)"; +static const char pci_device_3388_0026[] = "HB2 PCI-PCI Bridge"; +static const char pci_device_3388_101a[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_101b[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3842[] = "eVga.com. Corp."; +static const char pci_device_3842_c370[] = "e-GeFORCE 6600 256 DDR PCI-e"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0002_0000_0000[] = "GLoria L"; +#endif +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0003_0000_0000[] = "GLoria XL"; +#endif +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_0000_0000[] = "GLoria XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0008_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1048_0a42[] = "GLoria XXL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_000d[] = "GLint R4 rev A"; +static const char pci_device_3d3d_0011[] = "GLint R4 rev B"; +static const char pci_device_3d3d_0012[] = "GLint R5 rev A"; +static const char pci_device_3d3d_0013[] = "GLint R5 rev B"; +static const char pci_device_3d3d_0020[] = "VP10 visual processor"; +static const char pci_device_3d3d_0022[] = "VP10 visual processor"; +static const char pci_device_3d3d_0024[] = "VP9 visual processor"; +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_07a1[] = "Wildcat III 6210"; +static const char pci_device_3d3d_07a2[] = "Sun XVR-500 Graphics Accelerator"; +static const char pci_device_3d3d_07a3[] = "Wildcat IV 7210"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4144[] = "Alpha Data"; +static const char pci_device_4144_0044[] = "ADM-XRCIIPro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0016[] = "iTVC16 (CX23416) MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4009[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8003[] = "WinTV PVR 150"; +#endif +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4000[] = "WinTV PVR-350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4001[] = "WinTV PVR-250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3cf[] = "M179"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_494f[] = "ACCES I/O Products, Inc."; +static const char pci_device_494f_10e8[] = "LPCI-COM-8SM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +static const char pci_device_4c53_0000[] = "PLUSTEST device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3000[] = "PLUSTEST card (PC104+)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3001[] = "PLUSTEST card (PMC)"; +#endif +static const char pci_device_4c53_0001[] = "PLUSTEST-MM device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0001_4c53_3002[] = "PLUSTEST-MM card (PMC)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +static const char pci_device_5168_0301[] = "FlyDVB-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8110[] = "Savage 4 LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "Thinkpad T20/T22"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1179_0001[] = "86C584 SuperSavage/IXC Toshiba"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "VT8375 [ProSavage8 KM266/KL266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +static const char pci_device_544c_0350[] = "TL880-based HDTV/ATSC tuner"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +static const char pci_device_5654_3132[] = "OpenSwitch12"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5851[] = "Exacq Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin fuer Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +static const char pci_device_6666_0004[] = "PCCOM2"; +static const char pci_device_6666_0101[] = "PCI 8255/8254 I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7063[] = "pcHDTV"; +static const char pci_device_7063_2000[] = "HD-2000"; +static const char pci_device_7063_3000[] = "HD-3000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_807d[] = "Asustek Computer, Inc."; +#endif +static const char pci_vendor_8086[] = "Intel Corporation"; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145 Fast Ethernet"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0309[] = "80303 I/O Processor PCI-to-PCI Bridge"; +static const char pci_device_8086_030d[] = "80312 I/O Companion Chip PCI-to-PCI Bridge"; +static const char pci_device_8086_0326[] = "6700/6702PXH I/OxAPIC Interrupt Controller A"; +static const char pci_device_8086_0327[] = "6700PXH I/OxAPIC Interrupt Controller B"; +static const char pci_device_8086_0329[] = "6700PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_032a[] = "6700PXH PCI Express-to-PCI Bridge B"; +static const char pci_device_8086_032c[] = "6702PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_0330[] = "80332 [Dobson] I/O processor (A-Segment Bridge)"; +static const char pci_device_8086_0331[] = "80332 [Dobson] I/O processor (A-Segment IOAPIC)"; +static const char pci_device_8086_0332[] = "80332 [Dobson] I/O processor (B-Segment Bridge)"; +static const char pci_device_8086_0333[] = "80332 [Dobson] I/O processor (B-Segment IOAPIC)"; +static const char pci_device_8086_0334[] = "80332 [Dobson] I/O processor (ATU)"; +static const char pci_device_8086_0335[] = "80331 [Lindsay] I/O processor (PCI-X Bridge)"; +static const char pci_device_8086_0336[] = "80331 [Lindsay] I/O processor (ATU)"; +static const char pci_device_8086_0340[] = "41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge)"; +static const char pci_device_8086_0341[] = "41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge)"; +static const char pci_device_8086_0370[] = "80333 Segment-A PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0371[] = "80333 A-Bus IOAPIC"; +static const char pci_device_8086_0372[] = "80333 Segment-B PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0373[] = "80333 B-Bus IOAPIC"; +static const char pci_device_8086_0374[] = "80333 Address Translation Unit"; +static const char pci_device_8086_0482[] = "82375EB/SB PCI to EISA Bridge"; +static const char pci_device_8086_0483[] = "82424TX/ZX [Saturn] CPU to PCI bridge"; +static const char pci_device_8086_0484[] = "82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge"; +static const char pci_device_8086_0486[] = "82425EX/ZX [Aries] PCIset with ISA bridge"; +static const char pci_device_8086_04a3[] = "82434LX/NX [Mercury/Neptune] Processor to PCI bridge"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0500[] = "E8870 Processor bus control"; +static const char pci_device_8086_0501[] = "E8870 Memory controller"; +static const char pci_device_8086_0502[] = "E8870 Scalability Port 0"; +static const char pci_device_8086_0503[] = "E8870 Scalability Port 1"; +static const char pci_device_8086_0510[] = "E8870IO Hub Interface Port 0 registers (8-bit compatibility port)"; +static const char pci_device_8086_0511[] = "E8870IO Hub Interface Port 1 registers"; +static const char pci_device_8086_0512[] = "E8870IO Hub Interface Port 2 registers"; +static const char pci_device_8086_0513[] = "E8870IO Hub Interface Port 3 registers"; +static const char pci_device_8086_0514[] = "E8870IO Hub Interface Port 4 registers"; +static const char pci_device_8086_0515[] = "E8870IO General SIOH registers"; +static const char pci_device_8086_0516[] = "E8870IO RAS registers"; +static const char pci_device_8086_0530[] = "E8870SP Scalability Port 0 registers"; +static const char pci_device_8086_0531[] = "E8870SP Scalability Port 1 registers"; +static const char pci_device_8086_0532[] = "E8870SP Scalability Port 2 registers"; +static const char pci_device_8086_0533[] = "E8870SP Scalability Port 3 registers"; +static const char pci_device_8086_0534[] = "E8870SP Scalability Port 4 registers"; +static const char pci_device_8086_0535[] = "E8870SP Scalability Port 5 registers"; +static const char pci_device_8086_0536[] = "E8870SP Interleave registers 0 and 1"; +static const char pci_device_8086_0537[] = "E8870SP Interleave registers 2 and 3"; +static const char pci_device_8086_0600[] = "RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01af[] = "SRCZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01c1[] = "ICP Vortex GDT8546RZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01f7[] = "SCRU32"; +#endif +static const char pci_device_8086_061f[] = "80303 I/O Processor"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1002[] = "PRO/1000 F Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1028_011c[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_3108[] = "PRO/1000 XT Network Connection"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100a[] = "82540EM Gigabit Ethernet Controller"; +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1028_0123[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1079_891f[] = "82544GC Based Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_8086_110d[] = "82544GC Based Network Connection"; +#endif +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0265[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0267[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_026a[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1024_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_002e[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0151[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_107b_8920[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_028e[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1000[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_0e11_00db[] = "NC7170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1014_027c[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_18fb_7872[] = "RESlink-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1fc1_0026[] = "Niagara 2260 Bypass Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1012[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_101a[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1003[] = "PRO/1000 MF Server Adapter (LX)"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_0e11_00dc[] = "NC6170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1013[] = "82541EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_0013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1013[] = "IBM ThinkCentre Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1113[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1014[] = "82541ER Gigabit Ethernet Controller"; +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_1016[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1014_052c[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_8086_1016[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1017[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1017_8086_1017[] = "PR0/1000 MT Desktop Connection"; +#endif +static const char pci_device_8086_1018[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1018_8086_1018[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1019[] = "82547EI Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_1019[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_e000[] = "Intel Gigabit Ethernet (Kenai II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_1019[] = "PRO/1000 CT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_301f[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_101a[] = "82547EI Gigabit Ethernet Controller (Mobile)"; +static const char pci_device_8086_101d[] = "82546EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101d_8086_1000[] = "PRO/1000 MT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_101e[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1014_0549[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_8086_101e[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1026[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1000[] = "PRO/1000 MT Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1002[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1026[] = "PRO/1000 MT Server Connection"; +#endif +static const char pci_device_8086_1027[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_103c_3103[] = "NC310F PCI-X Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1001[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1002[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1003[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1027[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1028[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1028_8086_1028[] = "PRO/1000 MB Server Adapter"; +#endif +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_813c_104d[] = "Vaio PCG-GRV616G"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1038_0e11_0098[] = "Evo N600c"; +#endif +static const char pci_device_8086_1039[] = "82801DB PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1039_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_103a[] = "82801DB PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801DB PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801DB PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801DB PRO/100 VE (MOB) Ethernet Controller"; +static const char pci_device_8086_103e[] = "82801DB PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1043[] = "PRO/Wireless LAN 2100 3B Mini PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_8086_2527[] = "MIM2000/Centrino"; +#endif +static const char pci_device_8086_1048[] = "PRO/10GbE LR Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a01f[] = "PRO/10GbE LR Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a11f[] = "PRO/10GbE LR Server Adapter"; +#endif +static const char pci_device_8086_1050[] = "82562EZ 10/100 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_728c[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_758c[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3020[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_302f[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_1051[] = "82801EB/ER (ICH5/ICH5R) integrated LAN Controller"; +static const char pci_device_8086_1052[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1053[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_105e[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_105f[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1060[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1064[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_1065[] = "82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1066[] = "82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1067[] = "82562 EM/EX/GX - PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1068[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_1069[] = "82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_106a[] = "82562G - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_106b[] = "82562G - PRO/100 VE Ethernet Controller Mobile"; +static const char pci_device_8086_1075[] = "82547GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_0075[] = "PRO/1000 CT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_1075[] = "PRO/1000 CT Network Connection"; +#endif +static const char pci_device_8086_1076[] = "82541GI/PI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_0076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1176[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1276[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1077[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_0077[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_1077[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1078[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1078_8086_1078[] = "PRO/1000 MT Network Connection"; +#endif +static const char pci_device_8086_1079[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12a6[] = "HP Dual Port 1000Base-T [A9900A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12cf[] = "HP Core Dual Port 1000Base-T [AB352A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1fc1_0027[] = "Niagara 2261 Failover NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_0079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1179[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_117a[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_103c_12a8[] = "HP Dual Port 1000base-SX [A9899A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_107a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_127a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107b[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_007b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_107b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +static const char pci_device_8086_107c[] = "82541PI Gigabit Ethernet Controller"; +static const char pci_device_8086_107d[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107e[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107f[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_1080[] = "FA82537EP 56K V.92 Data/Fax Modem PCI"; +static const char pci_device_8086_1081[] = "Enterprise Southbridge LAN Copper"; +static const char pci_device_8086_1082[] = "Enterprise Southbridge LAN fiber"; +static const char pci_device_8086_1083[] = "Enterprise Southbridge LAN SERDES"; +static const char pci_device_8086_1084[] = "Enterprise Southbridge IDE Redirection"; +static const char pci_device_8086_1085[] = "Enterprise Southbridge Serial Port Redirection"; +static const char pci_device_8086_1086[] = "Enterprise Southbridge IPMI/KCS0"; +static const char pci_device_8086_1087[] = "Enterprise Southbridge UHCI Redirection"; +static const char pci_device_8086_1089[] = "Enterprise Southbridge BT"; +static const char pci_device_8086_108a[] = "82546EB Gigabit Ethernet Controller"; +static const char pci_device_8086_108b[] = "82573V Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108c[] = "82573E Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_1096[] = "Enterprise Southbridge DPT LAN Copper"; +static const char pci_device_8086_1097[] = "Enterprise Southbridge DPT LAN fiber"; +static const char pci_device_8086_1098[] = "Enterprise Southbridge DPT LAN SERDES"; +static const char pci_device_8086_1099[] = "82546GB Quad Port Server Adapter"; +static const char pci_device_8086_109a[] = "82573L Gigabit Ethernet Controller"; +static const char pci_device_8086_1107[] = "PRO/1000 MF Server Adapter (LX)"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4532[] = "D815EEA2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "Intel IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "8255xER/82551IT Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1070[] = "PC6 mainboard"; +#endif +static const char pci_device_8086_1221[] = "82092AA PCI to PCMCIA Bridge"; +static const char pci_device_8086_1222[] = "82092AA IDE Controller"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2500/2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_108e_10cf[] = "EtherExpress PRO/100(B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_110a_008b[] = "82551QM Fast Ethernet Multifuction PCI/CardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_10e0[] = "PSL09 PrPMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3411[] = "SDS2 Mainboard"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB PIIX IDE Interface"; +static const char pci_device_8086_123b[] = "82380PB PCI to PCI Docking Bridge"; +static const char pci_device_8086_123c[] = "82380AB (MISA) Mobile PCI-to-ISA Bridge"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123e[] = "82466GX (IHPC) Integrated Hot-Plug Controller"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "82752 (752) AGP Graphics Accelerator"; +static const char pci_device_8086_124b[] = "82380FB (MPCI2) Mobile Docking Controller"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_4c53_1090[] = "Cx9/Vx9 mainboard"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, HP NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "HP NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1010[] = "CG1-RADIO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1020[] = "CU2-QUARTET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1040[] = "CU1-CHORUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_3100[] = "CX1-BAND"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1a30_1028_010e[] = "Optiplex GX240"; +#endif +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_1a38[] = "Server DMA Controller"; +static const char pci_device_8086_1a48[] = "PRO/10GbE SR Server Adapter"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_110a_0051[] = "Activy 2xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1734_1025[] = "Activy 3xx"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_8086_4532[] = "D815EEA2 mainboard"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2446[] = "82801BA/BAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801 Mobile PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0265[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0267[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_026a[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1179_ff01[] = "PRO/100 VE Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801 PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244e_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA LPC Interface Controller"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1013_5959[] = "Crystal WMD Audio Codec"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_101f_1025[] = "Acer 620 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1179_0001[] = "Toshiba Satellite 1110 Z15 internal Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_248b[] = "82801CA Ultra ATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c1[] = "82801DBL (ICH4-L) IDE Controller"; +static const char pci_device_8086_24c2[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1509_2990[] = "Averatec 5110H laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c3[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24c4[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c5[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_0e11_00b8[] = "Analog Devices Inc. codec [SoundMAX]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1458_a002[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24c6[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_8086_24c7[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24ca[] = "82801DBM (ICH4-M) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24cb[] = "82801DB (ICH4) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24cc[] = "82801DBM (ICH4-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cc_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24cd[] = "82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1509_1968[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24d0[] = "82801EB/ER (ICH5/ICH5R) LPC Interface Bridge"; +static const char pci_device_8086_24d1[] = "82801EB (ICH5) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1043_80a6[] = "P4P800 SE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1458_24d1[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d2[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1458_24d2[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d3[] = "82801EB/ER (ICH5/ICH5R) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1043_80a6[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d4[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d5[] = "82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_12bc[] = "Analog Devices codec [SoundMAX Integrated Digital Audio]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_80f3[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_810f[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1458_a002[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_a000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e001[] = "Desktop Board D865GBF"; +#endif +static const char pci_device_8086_24d6[] = "82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller"; +static const char pci_device_8086_24d7[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24db[] = "82801EB/ER (ICH5/ICH5R) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7580[] = "MSI 875P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_24db[] = "P4C800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24dc[] = "82801EB (ICH5) LPC Interface Bridge"; +static const char pci_device_8086_24dd[] = "82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1458_5006[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24de[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24df[] = "82801ER (ICH5R) SATA Controller"; +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "E7500 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "E7500/E7501 Host RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2543[] = "E7500/E7501 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2544[] = "E7500/E7501 Hub Interface B RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2544_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_2545[] = "E7500/E7501 Hub Interface C PCI-to-PCI Bridge"; +static const char pci_device_8086_2546[] = "E7500/E7501 Hub Interface C RASUM Controller"; +static const char pci_device_8086_2547[] = "E7500/E7501 Hub Interface D PCI-to-PCI Bridge"; +static const char pci_device_8086_2548[] = "E7500/E7501 Hub Interface D RASUM Controller"; +static const char pci_device_8086_254c[] = "E7501 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2550[] = "E7505 Memory Controller Hub"; +static const char pci_device_8086_2551[] = "E7505/E7205 Series RAS Controller"; +static const char pci_device_8086_2552[] = "E7505/E7205 PCI-to-AGP Bridge"; +static const char pci_device_8086_2553[] = "E7505 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2554[] = "E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller"; +static const char pci_device_8086_255d[] = "E7205 Memory Controller Hub"; +static const char pci_device_8086_2560[] = "82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1458_2560[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2570[] = "82865G/PE/P DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1043_80f2[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1458_2570[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +static const char pci_device_8086_2571[] = "82865G/PE/P PCI to AGP Controller"; +static const char pci_device_8086_2572[] = "82865G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1028_019d[] = "Dimension 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1043_80a5[] = "P5P800-MX Mainboard"; +#endif +static const char pci_device_8086_2573[] = "82865G/PE/P PCI to CSA Bridge"; +static const char pci_device_8086_2576[] = "82865G/PE/P Processor to I/O Memory Interface"; +static const char pci_device_8086_2578[] = "82875P/E7210 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1458_2578[] = "GA-8KNXP motherboard (875P)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1462_7580[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_15d9_4580[] = "P4SCE Motherboard"; +#endif +static const char pci_device_8086_2579[] = "82875P Processor to AGP Controller"; +static const char pci_device_8086_257b[] = "82875P/E7210 Processor to PCI to CSA Bridge"; +static const char pci_device_8086_257e[] = "82875P/E7210 Processor to I/O Memory Interface"; +static const char pci_device_8086_2580[] = "915G/P/GV/GL/PL/910GL Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1458_2580[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2581[] = "915G/P/GV/GL/PL/910GL PCI Express Root Port"; +static const char pci_device_8086_2582[] = "82915G/GV/910GL Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1028_1079[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1458_2582[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2584[] = "925X/XE Memory Controller Hub"; +static const char pci_device_8086_2585[] = "925X/XE PCI Express Root Port"; +static const char pci_device_8086_2588[] = "E7220/E7221 Memory Controller Hub"; +static const char pci_device_8086_2589[] = "E7220/E7221 PCI Express Root Port"; +static const char pci_device_8086_258a[] = "E7221 Integrated Graphics Controller"; +static const char pci_device_8086_2590[] = "Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_a304_81b7[] = "Vaio VGN-S3XP"; +#endif +static const char pci_device_8086_2591[] = "Mobile 915GM/PM Express PCI Express Root Port"; +static const char pci_device_8086_2592[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_25a1[] = "6300ESB LPC Interface Controller"; +static const char pci_device_8086_25a2[] = "6300ESB PATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a3[] = "6300ESB SATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a4[] = "6300ESB SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a6[] = "6300ESB AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_4c53_10b0[] = "CL9 mainboard"; +#endif +static const char pci_device_8086_25a7[] = "6300ESB AC'97 Modem Controller"; +static const char pci_device_8086_25a9[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25aa[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ab[] = "6300ESB Watchdog Timer"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ac[] = "6300ESB I/O Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ad[] = "6300ESB USB2 Enhanced Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ae[] = "6300ESB 64-bit PCI-X Bridge"; +static const char pci_device_8086_25b0[] = "6300ESB SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25c0[] = "Workstation Memory Controller Hub"; +static const char pci_device_8086_25d0[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25d4[] = "Server Memory Contoller Hub"; +static const char pci_device_8086_25d8[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25e2[] = "Server PCI Express x4 Port 2"; +static const char pci_device_8086_25e3[] = "Server PCI Express x4 Port 3"; +static const char pci_device_8086_25e4[] = "Server PCI Express x4 Port 4"; +static const char pci_device_8086_25e5[] = "Server PCI Express x4 Port 5"; +static const char pci_device_8086_25e6[] = "Server PCI Express x4 Port 6"; +static const char pci_device_8086_25e7[] = "Server PCI Express x4 Port 7"; +static const char pci_device_8086_25e8[] = "Server AMB Memory Mapped Registers"; +static const char pci_device_8086_25f0[] = "Server Error Reporting Registers"; +static const char pci_device_8086_25f1[] = "Reserved Registers"; +static const char pci_device_8086_25f3[] = "Reserved Registers"; +static const char pci_device_8086_25f5[] = "Server FBD Registers"; +static const char pci_device_8086_25f6[] = "Server FBD Registers"; +static const char pci_device_8086_25f7[] = "Server PCI Express x8 Port 2-3"; +static const char pci_device_8086_25f8[] = "Server PCI Express x8 Port 4-5"; +static const char pci_device_8086_25f9[] = "Server PCI Express x8 Port 6-7"; +static const char pci_device_8086_25fa[] = "Server PCI Express x16 Port 4-7"; +static const char pci_device_8086_2600[] = "E8500/E8501 Hub Interface 1.5"; +static const char pci_device_8086_2601[] = "E8500/E8501 PCI Express x4 Port D"; +static const char pci_device_8086_2602[] = "E8500/E8501 PCI Express x4 Port C0"; +static const char pci_device_8086_2603[] = "E8500/E8501 PCI Express x4 Port C1"; +static const char pci_device_8086_2604[] = "E8500/E8501 PCI Express x4 Port B0"; +static const char pci_device_8086_2605[] = "E8500/E8501 PCI Express x4 Port B1"; +static const char pci_device_8086_2606[] = "E8500/E8501 PCI Express x4 Port A0"; +static const char pci_device_8086_2607[] = "E8500/E8501 PCI Express x4 Port A1"; +static const char pci_device_8086_2608[] = "E8500/E8501 PCI Express x8 Port C"; +static const char pci_device_8086_2609[] = "E8500/E8501 PCI Express x8 Port B"; +static const char pci_device_8086_260a[] = "E8500/E8501 PCI Express x8 Port A"; +static const char pci_device_8086_260c[] = "E8500/E8501 IMI Registers"; +static const char pci_device_8086_2610[] = "E8500/E8501 Front Side Bus, Boot, and Interrupt Registers"; +static const char pci_device_8086_2611[] = "E8500/E8501 Address Mapping Registers"; +static const char pci_device_8086_2612[] = "E8500/E8501 RAS Registers"; +static const char pci_device_8086_2613[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2614[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2615[] = "E8500/E8501 Miscellaneous Registers"; +static const char pci_device_8086_2617[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2618[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2619[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261a[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261b[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261c[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261d[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261e[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2620[] = "E8500/E8501 eXternal Memory Bridge"; +static const char pci_device_8086_2621[] = "E8500/E8501 XMB Miscellaneous Registers"; +static const char pci_device_8086_2622[] = "E8500/E8501 XMB Memory Interleaving Registers"; +static const char pci_device_8086_2623[] = "E8500/E8501 XMB DDR Initialization and Calibration"; +static const char pci_device_8086_2624[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2625[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2626[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2627[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2640[] = "82801FB/FR (ICH6/ICH6R) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2641[] = "82801FBM (ICH6M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2641_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2642[] = "82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge"; +static const char pci_device_8086_2651[] = "82801FB/FW (ICH6/ICH6W) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_8086_4147[] = "D915GAG Motherboard"; +#endif +static const char pci_device_8086_2652[] = "82801FR/FRW (ICH6R/ICH6RW) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2652_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_8086_2653[] = "82801FBM (ICH6M) SATA Controller"; +static const char pci_device_8086_2658[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1458_2558[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2659[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1458_2659[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265b[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1458_5006[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2660[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2660_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2662[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2"; +static const char pci_device_8086_2664[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3"; +static const char pci_device_8086_2666[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4"; +static const char pci_device_8086_2668[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller"; +static const char pci_device_8086_266a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1458_266a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_266c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller"; +static const char pci_device_8086_266d[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_266e[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0182[] = "Latitude D610 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1458_a002[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1734_105a[] = "Scenic W620"; +#endif +static const char pci_device_8086_266f[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1458_266f[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2670[] = "Enterprise Southbridge LPC"; +static const char pci_device_8086_2680[] = "Enterprise Southbridge SATA cc=IDE"; +static const char pci_device_8086_2681[] = "Enterprise Southbridge SATA cc=AHCI"; +static const char pci_device_8086_2682[] = "Enterprise Southbridge SATA cc=RAID"; +static const char pci_device_8086_2683[] = "Enterprise Southbridge SATA cc=RAID"; +static const char pci_device_8086_2688[] = "Enterprise Southbridge UHCI USB #1"; +static const char pci_device_8086_2689[] = "Enterprise Southbridge UHCI USB #2"; +static const char pci_device_8086_268a[] = "Enterprise Southbridge UHCI USB #3"; +static const char pci_device_8086_268b[] = "Enterprise Southbridge UHCI USB #4"; +static const char pci_device_8086_268c[] = "Enterprise Southbridge EHCI USB"; +static const char pci_device_8086_2690[] = "Enterprise Southbridge PCI Express Root Port 1"; +static const char pci_device_8086_2692[] = "Enterprise Southbridge PCI Express Root Port 2"; +static const char pci_device_8086_2694[] = "Enterprise Southbridge PCI Express Root Port 3"; +static const char pci_device_8086_2696[] = "Enterprise Southbridge PCI Express Root Port 4"; +static const char pci_device_8086_2698[] = "Enterprise Southbridge AC '97 Audio"; +static const char pci_device_8086_2699[] = "Enterprise Southbridge AC '97 Modem"; +static const char pci_device_8086_269a[] = "Enterprise Southbridge High Definition Audio"; +static const char pci_device_8086_269b[] = "Enterprise Southbridge SMBus"; +static const char pci_device_8086_269e[] = "Enterprise Southbridge PATA"; +static const char pci_device_8086_2770[] = "945G/P Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2771[] = "945G/P PCI Express Graphics Port"; +static const char pci_device_8086_2772[] = "945G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2772_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2774[] = "955X Memory Controller Hub"; +static const char pci_device_8086_2775[] = "955X PCI Express Graphics Port"; +static const char pci_device_8086_2776[] = "945G Integrated Graphics Controller"; +static const char pci_device_8086_2778[] = "E7230 Memory Controller Hub"; +static const char pci_device_8086_2779[] = "E7230 PCI Express Root Port"; +static const char pci_device_8086_277a[] = "PCI Express Graphics Port"; +static const char pci_device_8086_277c[] = "Memory Controller Hub"; +static const char pci_device_8086_277d[] = "PCI Express Graphics Port"; +static const char pci_device_8086_2782[] = "82915G Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2792[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_27a0[] = "Mobile Memory Controller Hub"; +static const char pci_device_8086_27a1[] = "Mobile PCI Express Graphics Port"; +static const char pci_device_8086_27a2[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_27a6[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_27b0[] = "82801GH (ICH7DH) LPC Interface Bridge"; +static const char pci_device_8086_27b8[] = "82801GB/GR (ICH7 Family) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27b9[] = "82801GBM (ICH7-M) LPC Interface Bridge"; +static const char pci_device_8086_27bd[] = "82801GHM (ICH7-M DH) LPC Interface Bridge"; +static const char pci_device_8086_27c0[] = "82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c1[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=AHCI"; +static const char pci_device_8086_27c3[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controllers cc=RAID"; +static const char pci_device_8086_27c4[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controllers cc=IDE"; +static const char pci_device_8086_27c5[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controllers cc=AHCI"; +static const char pci_device_8086_27c6[] = "82801GHM (ICH7-M DH) Serial ATA Storage Controllers cc=RAID"; +static const char pci_device_8086_27c8[] = "82801G (ICH7 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c9[] = "82801G (ICH7 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27ca[] = "82801G (ICH7 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cb[] = "82801G (ICH7 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cc[] = "82801G (ICH7 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27d0[] = "82801G (ICH7 Family) PCI Express Port 1"; +static const char pci_device_8086_27d2[] = "82801G (ICH7 Family) PCI Express Port 2"; +static const char pci_device_8086_27d4[] = "82801G (ICH7 Family) PCI Express Port 3"; +static const char pci_device_8086_27d6[] = "82801G (ICH7 Family) PCI Express Port 4"; +static const char pci_device_8086_27d8[] = "82801G (ICH7 Family) High Definition Audio Controller"; +static const char pci_device_8086_27da[] = "82801G (ICH7 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dc[] = "82801G (ICH7 Family) LAN Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27dc_8086_308d[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dd[] = "82801G (ICH7 Family) AC'97 Modem Controller"; +static const char pci_device_8086_27de[] = "82801G (ICH7 Family) AC'97 Audio Controller"; +static const char pci_device_8086_27df[] = "82801G (ICH7 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27e0[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 5"; +static const char pci_device_8086_27e2[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 6"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3200[] = "GD31244 PCI-X SATA HBA"; +static const char pci_device_8086_3340[] = "82855PM Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_0890[] = "nc6000 laptop"; +#endif +static const char pci_device_8086_3341[] = "82855PM Processor to AGP Controller"; +static const char pci_device_8086_3500[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3501[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3504[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_3505[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_350c[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_350d[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_3510[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3511[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3514[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3515[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3518[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3519[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3581[] = "82852/82855 GM/GME/PM/GMV Processor to AGP Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3581_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_3582[] = "82852/855GM Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3584[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3585[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3590[] = "E7520 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1734_103e[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3591[] = "E7525/E7520 Error Reporting Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3592[] = "E7320 Memory Controller Hub"; +static const char pci_device_8086_3593[] = "E7320 Error Reporting Registers"; +static const char pci_device_8086_3594[] = "E7520 DMA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3594_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3595[] = "E7525/E7520/E7320 PCI Express Port A"; +static const char pci_device_8086_3596[] = "E7525/E7520/E7320 PCI Express Port A1"; +static const char pci_device_8086_3597[] = "E7525/E7520 PCI Express Port B"; +static const char pci_device_8086_3598[] = "E7520 PCI Express Port B1"; +static const char pci_device_8086_3599[] = "E7520 PCI Express Port C"; +static const char pci_device_8086_359a[] = "E7520 PCI Express Port C1"; +static const char pci_device_8086_359b[] = "E7525/E7520/E7320 Extended Configuration Registers"; +static const char pci_device_8086_359e[] = "E7525 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_359e_1028_0169[] = "Precision 470"; +#endif +static const char pci_device_8086_4220[] = "PRO/Wireless 2200BG"; +static const char pci_device_8086_4223[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_4224[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7050[] = "Intercast Video Capture Card"; +static const char pci_device_8086_7051[] = "PB 642365-003 (Business Video Conferencing Card)"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7110_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7111_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7112_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7113_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1060[] = "PC7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_8086_4341[] = "Cayman (CA810) Mainboard"; +#endif +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700/E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_15ad_1976[] = "virtualHW v3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_1033_0000[] = "Versa Note Vxi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_1033_80cc[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a2_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "82740 (i740) AGP Graphics Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_8500[] = "IXP4XX Intel Network Processor (IXP420/421/422/425/IXC1100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0ded[] = "mGuard-PCI AV#2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0dee[] = "mGuard-PCI AV#1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0def[] = "mGuard-PCI AV#0"; +#endif +static const char pci_device_8086_9000[] = "IXP2000 Family Network Processor"; +static const char pci_device_8086_9001[] = "IXP2400 Network Processor"; +static const char pci_device_8086_9004[] = "IXP2800 Network Processor"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12d9_000a[] = "PCI VoIP Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8401[] = "TRENDware International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8912[] = "TRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8c4a[] = "Winbond"; +static const char pci_device_8c4a_1980[] = "W89C940 misprogrammed [ne2k]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_0078[] = "AHA-2940U_CN"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7710[] = "ANA-7711F Network Accelerator Card (NAC) - Optical"; +static const char pci_device_9004_7711[] = "ANA-7711C Network Accelerator Card (NAC) - Copper"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8178_9004_7881[] = "AHA-2940UW SCSI Host Adapter"; +#endif +static const char pci_device_9004_8278[] = "AHA-3940U/UW/UWD / AIC-7882U"; +static const char pci_device_9004_8378[] = "AHA-3940U/UW / AIC-7883U"; +static const char pci_device_9004_8478[] = "AHA-2944UW / AIC-7884U"; +static const char pci_device_9004_8578[] = "AHA-3944U/UWD / AIC-7885"; +static const char pci_device_9004_8678[] = "AHA-4944UW / AIC-7886"; +static const char pci_device_9004_8778[] = "AHA-2940UW Pro / AIC-788x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8778_9004_7887[] = "2940UW Pro Ultra-Wide SCSI Controller"; +#endif +static const char pci_device_9004_8878[] = "AHA-2930UW / AIC-7888"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8878_9004_7888[] = "AHA-2930UW SCSI Controller"; +#endif +static const char pci_device_9004_8b78[] = "ABA-1030"; +static const char pci_device_9004_ec78[] = "AHA-4944W/UW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9005[] = "Adaptec"; +static const char pci_device_9005_0010[] = "AHA-2940U2/U2W"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_2180[] = "AHA-2940U2 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_8100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a180[] = "AHA-2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_e100[] = "AHA-2950U2B SCSI Controller"; +#endif +static const char pci_device_9005_0011[] = "AHA-2930U2"; +static const char pci_device_9005_0013[] = "78902"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_0003[] = "AAA-131U2 Array1000 1 Channel RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_000f[] = "AIC7890_ARO"; +#endif +static const char pci_device_9005_001f[] = "AHA-2940U2/U2W / 7890/7891"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_9005_0020[] = "AIC-7890"; +static const char pci_device_9005_002f[] = "AIC-7890"; +static const char pci_device_9005_0030[] = "AIC-7890"; +static const char pci_device_9005_003f[] = "AIC-7890"; +static const char pci_device_9005_0050[] = "AHA-3940U2x/395U2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_f500[] = "AHA-3950U2B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_ffff[] = "AHA-3950U2B"; +#endif +static const char pci_device_9005_0051[] = "AHA-3950U2D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0051_9005_b500[] = "AHA-3950U2D"; +#endif +static const char pci_device_9005_0053[] = "AIC-7896 SCSI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0053_9005_ffff[] = "AIC-7896 SCSI Controller mainboard implementation"; +#endif +static const char pci_device_9005_005f[] = "AIC-7896U2/7897U2"; +static const char pci_device_9005_0080[] = "AIC-7892A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_0e11_e2a0[] = "Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_6220[] = "AHA-29160C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_62a0[] = "29160N Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e220[] = "29160LP Low Profile Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e2a0[] = "29160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0081[] = "AIC-7892B U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0081_9005_62a1[] = "19160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0083[] = "AIC-7892D U160/m"; +static const char pci_device_9005_008f[] = "AIC-7892P U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +static const char pci_device_9005_0092[] = "Adaptec VIDEOH! AVC-2010"; +static const char pci_device_9005_0093[] = "Adaptec VIDEOH! AVC-2410"; +static const char pci_device_9005_00c0[] = "AHA-3960D / AIC-7899A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_0e11_f620[] = "Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_9005_f620[] = "AHA-3960D U160/m"; +#endif +static const char pci_device_9005_00c1[] = "AIC-7899B U160/m"; +static const char pci_device_9005_00c3[] = "AIC-7899D U160/m"; +static const char pci_device_9005_00c5[] = "RAID subsystem HBA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c5_1028_00c5[] = "PowerEdge 2400,2500,2550,4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_10f1_2462[] = "Thunder K7 S2462"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_0241[] = "Serial ATA II RAID 1420SA"; +static const char pci_device_9005_0250[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_0279[] = "ServeRAID-xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_028c[] = "ServeRAID-xx"; +#endif +static const char pci_device_9005_0279[] = "ServeRAID 6M"; +static const char pci_device_9005_0283[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0283_9005_0283[] = "Catapult"; +#endif +static const char pci_device_9005_0284[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0284_9005_0284[] = "Tomcat"; +#endif +static const char pci_device_9005_0285[] = "AAC-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_0e11_0295[] = "SATA 6Ch (Bearcat)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1014_02f2[] = "ServeRAID 8i"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0287[] = "PowerEdge Expandable RAID Controller 320/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0291[] = "CERC SATA RAID 2 PCI SATA 6ch (DellCorsair)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_103c_3227[] = "AAR-2610SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0286[] = "Legend S220 (Legend Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0287[] = "Legend S230 (Legend Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0285[] = "2200S (Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0286[] = "2120S (Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0287[] = "2200S (Vulcan-2m)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0288[] = "3230S (Harrier)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0289[] = "3240S (Tornado)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028a[] = "ASR-2020S PCI-X ZCR (Skyhawk)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028b[] = "ASR-2025S (Terminator)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028e[] = "ASR-2020SA (Skyhawk)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028f[] = "ASR-2025SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0290[] = "AAR-2410SA PCI SATA 4ch (Jaguar II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0292[] = "AAR-2810SA PCI SATA 8ch (Corsair-8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0293[] = "AAR-21610SA PCI SATA 16ch (Corsair-16)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0294[] = "ESD SO-DIMM PCI-X SATA ZCR (Prowler)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0296[] = "ASR-2240S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0297[] = "ASR-4005SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0298[] = "ASR-4000SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0299[] = "ASR-4800SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_029a[] = "ASR-4805SAS"; +#endif +static const char pci_device_9005_0286[] = "AAC-RAID (Rocket)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9540[] = "ServeRAID 8k/8k-l4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9580[] = "ServeRAID 8k/8k-l8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028c[] = "ASR-2230S + ASR-2230SLP PCI-X (Lancer)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028d[] = "ASR-2130S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029b[] = "ASR-2820SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029c[] = "ASR-2620SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029d[] = "ASR-2420SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029e[] = "ICP ICP9024R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029f[] = "ICP ICP9014R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a0[] = "ICP ICP9047MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a1[] = "ICP ICP9087MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a2[] = "ASR-4810SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a3[] = "ICP ICP5085AU"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a4[] = "ICP ICP5085LI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a5[] = "ICP ICP5085BR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a6[] = "ICP9067MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_0800[] = "Callisto"; +#endif +static const char pci_device_9005_0500[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/572D)"; +#endif +static const char pci_device_9005_0503[] = "Scamp chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02bf[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02d5[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571F)"; +#endif +static const char pci_device_9005_0910[] = "AUA-3100B"; +static const char pci_device_9005_091e[] = "AUA-3100B"; +static const char pci_device_9005_8000[] = "ASC-29320A U320"; +static const char pci_device_9005_800f[] = "AIC-7901 U320"; +static const char pci_device_9005_8010[] = "ASC-39320 U320"; +static const char pci_device_9005_8011[] = "ASC-39320D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_0e11_00ac[] = "ASC-39320D U320"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_9005_0041[] = "ASC-39320D U320"; +#endif +static const char pci_device_9005_8012[] = "ASC-29320 U320"; +static const char pci_device_9005_8013[] = "ASC-29320B U320"; +static const char pci_device_9005_8014[] = "ASC-29320LP U320"; +static const char pci_device_9005_8015[] = "ASC-39320B U320"; +static const char pci_device_9005_8016[] = "ASC-39320A U320"; +static const char pci_device_9005_8017[] = "ASC-29320ALP U320"; +static const char pci_device_9005_801c[] = "ASC-39320D U320"; +static const char pci_device_9005_801d[] = "AIC-7902B U320"; +static const char pci_device_9005_801e[] = "AIC-7901A U320"; +static const char pci_device_9005_801f[] = "AIC-7902 U320"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_801f_1734_1011[] = "Primergy RX300"; +#endif +static const char pci_device_9005_8080[] = "ASC-29320A U320 w/HostRAID"; +static const char pci_device_9005_808f[] = "AIC-7901 U320 w/HostRAID"; +static const char pci_device_9005_8090[] = "ASC-39320 U320 w/HostRAID"; +static const char pci_device_9005_8091[] = "ASC-39320D U320 w/HostRAID"; +static const char pci_device_9005_8092[] = "ASC-29320 U320 w/HostRAID"; +static const char pci_device_9005_8093[] = "ASC-29320B U320 w/HostRAID"; +static const char pci_device_9005_8094[] = "ASC-29320LP U320 w/HostRAID"; +static const char pci_device_9005_8095[] = "ASC-39320(B) U320 w/HostRAID"; +static const char pci_device_9005_8096[] = "ASC-39320A U320 w/HostRAID"; +static const char pci_device_9005_8097[] = "ASC-29320ALP U320 w/HostRAID"; +static const char pci_device_9005_809c[] = "ASC-39320D(B) U320 w/HostRAID"; +static const char pci_device_9005_809d[] = "AIC-7902(B) U320 w/HostRAID"; +static const char pci_device_9005_809e[] = "AIC-7901A U320 w/HostRAID"; +static const char pci_device_9005_809f[] = "AIC-7902 U320 w/HostRAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_907f[] = "Atronics"; +static const char pci_device_907f_2015[] = "IDE-2015PL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_919a[] = "Gigapixel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9412[] = "Holtek"; +static const char pci_device_9412_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9699[] = "Omni Media Technology Inc"; +static const char pci_device_9699_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9710[] = "NetMos Technology"; +static const char pci_device_9710_7780[] = "USB IRDA-port"; +static const char pci_device_9710_9805[] = "PCI 1 port parallel adapter"; +static const char pci_device_9710_9815[] = "PCI 9815 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9815_1000_0020[] = "2P0S (2 port parallel adaptor)"; +#endif +static const char pci_device_9710_9835[] = "PCI 9835 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0002[] = "2S (16C550 UART)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0012[] = "1P2S"; +#endif +static const char pci_device_9710_9845[] = "PCI 9845 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0004[] = "0P4S (4 port 16550A serial card)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0006[] = "0P6S (6 port 16550a serial card)"; +#endif +static const char pci_device_9710_9855[] = "PCI 9855 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9855_1000_0014[] = "1P4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9902[] = "Stargen Inc."; +static const char pci_device_9902_0001[] = "SG2010 PCI over Starfabric Bridge"; +static const char pci_device_9902_0002[] = "SG2010 PCI to Starfabric Gateway"; +static const char pci_device_9902_0003[] = "SG1010 Starfabric Switch and PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0a0[] = "AOPEN Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0f1[] = "UNISYS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a200[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a259[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a25b[] = "Hewlett Packard GmbH PL24-MKT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a304[] = "Sony"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a727[] = "3Com Corporation"; +static const char pci_device_a727_0013[] = "3CRPAG175 Wireless PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aa42[] = "Scitex Digital Video"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac1e[] = "Digital Receiver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac3d[] = "Actuality Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aecb[] = "Adrienne Electronics Corporation"; +static const char pci_device_aecb_6250[] = "VITC/LTC Timecode Reader card [PCI-VLTC/RDR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_affe[] = "Sirrix AG security technologies"; +static const char pci_device_affe_dead[] = "Sirrix.PCI4S0 4-port ISDN S0 interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_b1b3[] = "Shiva Europe Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_bd11[] = "Pinnacle Systems, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c001[] = "TSI Telsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0a9[] = "Micron/Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0de[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0fe[] = "Motion Engineering, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ca50[] = "Varian Australia Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cafe[] = "Chrysalis-ITS"; +static const char pci_device_cafe_0003[] = "Luna K3 Hardware Security Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cccc[] = "Catapult Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cddd[] = "Tyzx, Inc."; +static const char pci_device_cddd_0101[] = "DeepSea 1 High Speed Stereo Vision Frame Grabber"; +static const char pci_device_cddd_0200[] = "DeepSea 2 High Speed Stereo Vision Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d161[] = "Digium, Inc."; +static const char pci_device_d161_0205[] = "Wildcard TE205P"; +static const char pci_device_d161_0210[] = "Wildcard TE210P"; +static const char pci_device_d161_0405[] = "Wildcard TE405P (2nd Gen)"; +static const char pci_device_d161_0410[] = "Wildcard TE410P (2nd Gen)"; +static const char pci_device_d161_2400[] = "Wildcard TDM2400P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d4d4[] = "Dy4 Systems Inc"; +static const char pci_device_d4d4_0601[] = "PCI Mezzanine Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d531[] = "I+ME ACTIA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d84d[] = "Exsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_dead[] = "Indigita Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_deaf[] = "Middle Digital Inc."; +static const char pci_device_deaf_9050[] = "PC Weasel Virtual VGA"; +static const char pci_device_deaf_9051[] = "PC Weasel Serial Port"; +static const char pci_device_deaf_9052[] = "PC Weasel Watchdog Timer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e000[] = "Winbond"; +static const char pci_device_e000_e000[] = "W89C940"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e159[] = "Tiger Jet Network Inc."; +static const char pci_device_e159_0001[] = "Tiger3XX Modem/ISDN interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0001[] = "128k ISDN-S/T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0003[] = "128k ISDN-U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_00a7_0001[] = "TELES.S0/PCI 2.x ISDN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_6159_0001[] = "Digium Wildcard T100P T1/PRI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_79fe_0001[] = "Digium Wildcard TE110P T1/E1 Interface"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_8086_0003[] = "Digium X100P/X101P analogue PSTN FXO interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_b1b9_0001[] = "Digium Wildcard TDM400P REV I 4-port POTS interface"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_b1b9_0003[] = "Digium Wildcard TDM400P REV I 4-port POTS interface"; +#endif +static const char pci_device_e159_0002[] = "Tiger100APC ISDN chipset"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e4bf[] = "EKF Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e55e[] = "Essence Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea01[] = "Eagle Technology"; +static const char pci_device_ea01_000a[] = "PCI-773 Temperature Card"; +static const char pci_device_ea01_0032[] = "PCI-730 & PC104P-30 Card"; +static const char pci_device_ea01_003e[] = "PCI-762 Opto-Isolator Card"; +static const char pci_device_ea01_0041[] = "PCI-763 Reed Relay Card"; +static const char pci_device_ea01_0043[] = "PCI-769 Opto-Isolator Reed Relay Combo Card"; +static const char pci_device_ea01_0046[] = "PCI-766 Analog Output Card"; +static const char pci_device_ea01_0052[] = "PCI-703 Analog I/O Card"; +static const char pci_device_ea01_0800[] = "PCI-800 Digital I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea60[] = "RME"; +static const char pci_device_ea60_9896[] = "Digi32"; +static const char pci_device_ea60_9897[] = "Digi32 Pro"; +static const char pci_device_ea60_9898[] = "Digi32/8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eabb[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eace[] = "Endace Measurement Systems, Ltd"; +static const char pci_device_eace_3100[] = "DAG 3.10 OC-3/OC-12"; +static const char pci_device_eace_3200[] = "DAG 3.2x OC-3/OC-12"; +static const char pci_device_eace_320e[] = "DAG 3.2E Fast Ethernet"; +static const char pci_device_eace_340e[] = "DAG 3.4E Fast Ethernet"; +static const char pci_device_eace_341e[] = "DAG 3.41E Fast Ethernet"; +static const char pci_device_eace_3500[] = "DAG 3.5 OC-3/OC-12"; +static const char pci_device_eace_351c[] = "DAG 3.5ECM Fast Ethernet"; +static const char pci_device_eace_4100[] = "DAG 4.10 OC-48"; +static const char pci_device_eace_4110[] = "DAG 4.11 OC-48"; +static const char pci_device_eace_4220[] = "DAG 4.2 OC-48"; +static const char pci_device_eace_422e[] = "DAG 4.2E Dual Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ec80[] = "Belkin Corporation"; +static const char pci_device_ec80_ec00[] = "F5D6000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ecc0[] = "Echo Digital Audio Corporation"; +#endif +static const char pci_vendor_edd8[] = "ARK Logic Inc"; +static const char pci_device_edd8_a091[] = "1000PV [Stingray]"; +static const char pci_device_edd8_a099[] = "2000PV [Stingray]"; +static const char pci_device_edd8_a0a1[] = "2000MT"; +static const char pci_device_edd8_a0a9[] = "2000MI"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_f1d0[] = "AJA Video"; +static const char pci_device_f1d0_c0fe[] = "Xena HS/HD-R"; +static const char pci_device_f1d0_c0ff[] = "Kona/Xena 2"; +static const char pci_device_f1d0_cafe[] = "Kona SD"; +static const char pci_device_f1d0_cfee[] = "Xena LS/SD-22-DA/SD-DA"; +static const char pci_device_f1d0_dcaf[] = "Kona HD"; +static const char pci_device_f1d0_dfee[] = "Xena HD-DA"; +static const char pci_device_f1d0_efac[] = "Xena SD-MM/SD-22-MM"; +static const char pci_device_f1d0_facd[] = "Xena HD-MM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fa57[] = "Interagon AS"; +static const char pci_device_fa57_0001[] = "PMC [Pattern Matching Chip]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_febd[] = "Ultraview Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_feda[] = "Broadcom Inc"; +static const char pci_device_feda_a0fa[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_feda_a10e[] = "BCM4230 iLine10 HomePNA 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fede[] = "Fedetec Inc."; +static const char pci_device_fede_0003[] = "TABIC PCI v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffd[] = "XenSource, Inc."; +static const char pci_device_fffd_0101[] = "PCI Event Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffe[] = "VMWare Inc"; +static const char pci_device_fffe_0405[] = "Virtual SVGA 4.0"; +static const char pci_device_fffe_0710[] = "Virtual SVGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ffff[] = "Illegal Vendor ID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409a = + {0x0e11, 0x409a, pci_subsys_0e11_0046_0e11_409a, 0}; +#undef pci_ss_info_0e11_409a +#define pci_ss_info_0e11_409a pci_ss_info_0e11_0046_0e11_409a +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409b = + {0x0e11, 0x409b, pci_subsys_0e11_0046_0e11_409b, 0}; +#undef pci_ss_info_0e11_409b +#define pci_ss_info_0e11_409b pci_ss_info_0e11_0046_0e11_409b +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409c = + {0x0e11, 0x409c, pci_subsys_0e11_0046_0e11_409c, 0}; +#undef pci_ss_info_0e11_409c +#define pci_ss_info_0e11_409c pci_ss_info_0e11_0046_0e11_409c +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409d = + {0x0e11, 0x409d, pci_subsys_0e11_0046_0e11_409d, 0}; +#undef pci_ss_info_0e11_409d +#define pci_ss_info_0e11_409d pci_ss_info_0e11_0046_0e11_409d +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4080 = + {0x0e11, 0x4080, pci_subsys_0e11_b178_0e11_4080, 0}; +#undef pci_ss_info_0e11_4080 +#define pci_ss_info_0e11_4080 pci_ss_info_0e11_b178_0e11_4080 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4082 = + {0x0e11, 0x4082, pci_subsys_0e11_b178_0e11_4082, 0}; +#undef pci_ss_info_0e11_4082 +#define pci_ss_info_0e11_4082 pci_ss_info_0e11_b178_0e11_4082 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4083 = + {0x0e11, 0x4083, pci_subsys_0e11_b178_0e11_4083, 0}; +#undef pci_ss_info_0e11_4083 +#define pci_ss_info_0e11_4083 pci_ss_info_0e11_b178_0e11_4083 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0003_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0003_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0003_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0006_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0006_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0006_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000a_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000a_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000a_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000b_0e11_6004 = + {0x0e11, 0x6004, pci_subsys_1000_000b_0e11_6004, 0}; +#undef pci_ss_info_0e11_6004 +#define pci_ss_info_0e11_6004 pci_ss_info_1000_000b_0e11_6004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000b_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000b_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000b_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000b_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000b_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000b_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000b_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_1000_000b_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_1000_000b_13e9_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000c_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000c_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000c_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000c_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3906 = + {0x1de1, 0x3906, pci_subsys_1000_000c_1de1_3906, 0}; +#undef pci_ss_info_1de1_3906 +#define pci_ss_info_1de1_3906 pci_ss_info_1000_000c_1de1_3906 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000f_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000f_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000f_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000f_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000f_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000f_1000_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1000_000f_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1000_000f_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1000_000f_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1000_000f_4c53_1050 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0010_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0010_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0010_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0012_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0012_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0012_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0013_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0013_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0013_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0020_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0020_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0021_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0021_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0021_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0021_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0021_124b_1070 = + {0x124b, 0x1070, pci_subsys_1000_0021_124b_1070, 0}; +#undef pci_ss_info_124b_1070 +#define pci_ss_info_124b_1070 pci_ss_info_1000_0021_124b_1070 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1000_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1000_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1300 = + {0x4c53, 0x1300, pci_subsys_1000_0021_4c53_1300, 0}; +#undef pci_ss_info_4c53_1300 +#define pci_ss_info_4c53_1300 pci_ss_info_1000_0021_4c53_1300 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1310 = + {0x4c53, 0x1310, pci_subsys_1000_0021_4c53_1310, 0}; +#undef pci_ss_info_4c53_1310 +#define pci_ss_info_4c53_1310 pci_ss_info_1000_0021_4c53_1310 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_0e11_00da = + {0x0e11, 0x00da, pci_subsys_1000_0030_0e11_00da, 0}; +#undef pci_ss_info_0e11_00da +#define pci_ss_info_0e11_00da pci_ss_info_1000_0030_0e11_00da +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0123 = + {0x1028, 0x0123, pci_subsys_1000_0030_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_1000_0030_1028_0123 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_014a = + {0x1028, 0x014a, pci_subsys_1000_0030_1028_014a, 0}; +#undef pci_ss_info_1028_014a +#define pci_ss_info_1028_014a pci_ss_info_1000_0030_1028_014a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_016c = + {0x1028, 0x016c, pci_subsys_1000_0030_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1000_0030_1028_016c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0183 = + {0x1028, 0x0183, pci_subsys_1000_0030_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_1000_0030_1028_0183 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0030_124b_1170 = + {0x124b, 0x1170, pci_subsys_1000_0030_124b_1170, 0}; +#undef pci_ss_info_124b_1170 +#define pci_ss_info_124b_1170 pci_ss_info_1000_0030_124b_1170 +static const pciSubsystemInfo pci_ss_info_1000_0030_1734_1052 = + {0x1734, 0x1052, pci_subsys_1000_0030_1734_1052, 0}; +#undef pci_ss_info_1734_1052 +#define pci_ss_info_1734_1052 pci_ss_info_1000_0030_1734_1052 +static const pciSubsystemInfo pci_ss_info_1000_0032_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0032_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0032_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0033 = + {0x1000, 0x0033, pci_subsys_1000_0040_1000_0033, 0}; +#undef pci_ss_info_1000_0033 +#define pci_ss_info_1000_0033 pci_ss_info_1000_0040_1000_0033 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0066 = + {0x1000, 0x0066, pci_subsys_1000_0040_1000_0066, 0}; +#undef pci_ss_info_1000_0066 +#define pci_ss_info_1000_0066 pci_ss_info_1000_0040_1000_0066 +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0530 = + {0x1000, 0x0530, pci_subsys_1000_0407_1000_0530, 0}; +#undef pci_ss_info_1000_0530 +#define pci_ss_info_1000_0530 pci_ss_info_1000_0407_1000_0530 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0531 = + {0x1000, 0x0531, pci_subsys_1000_0407_1000_0531, 0}; +#undef pci_ss_info_1000_0531 +#define pci_ss_info_1000_0531 pci_ss_info_1000_0407_1000_0531 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0532 = + {0x1000, 0x0532, pci_subsys_1000_0407_1000_0532, 0}; +#undef pci_ss_info_1000_0532 +#define pci_ss_info_1000_0532 pci_ss_info_1000_0407_1000_0532 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_0407_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_0407_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_0407_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_0407_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0530 = + {0x8086, 0x0530, pci_subsys_1000_0407_8086_0530, 0}; +#undef pci_ss_info_8086_0530 +#define pci_ss_info_8086_0530 pci_ss_info_1000_0407_8086_0530 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0532 = + {0x8086, 0x0532, pci_subsys_1000_0407_8086_0532, 0}; +#undef pci_ss_info_8086_0532 +#define pci_ss_info_8086_0532 pci_ss_info_1000_0407_8086_0532 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0001 = + {0x1000, 0x0001, pci_subsys_1000_0408_1000_0001, 0}; +#undef pci_ss_info_1000_0001 +#define pci_ss_info_1000_0001 pci_ss_info_1000_0408_1000_0001 +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0002 = + {0x1000, 0x0002, pci_subsys_1000_0408_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_1000_0408_1000_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1025_004d = + {0x1025, 0x004d, pci_subsys_1000_0408_1025_004d, 0}; +#undef pci_ss_info_1025_004d +#define pci_ss_info_1025_004d pci_ss_info_1000_0408_1025_004d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0001 = + {0x1028, 0x0001, pci_subsys_1000_0408_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1000_0408_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0002 = + {0x1028, 0x0002, pci_subsys_1000_0408_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1000_0408_1028_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1734_1065 = + {0x1734, 0x1065, pci_subsys_1000_0408_1734_1065, 0}; +#undef pci_ss_info_1734_1065 +#define pci_ss_info_1734_1065 pci_ss_info_1000_0408_1734_1065 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_8086_0002 = + {0x8086, 0x0002, pci_subsys_1000_0408_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_1000_0408_8086_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3004 = + {0x1000, 0x3004, pci_subsys_1000_0409_1000_3004, 0}; +#undef pci_ss_info_1000_3004 +#define pci_ss_info_1000_3004 pci_ss_info_1000_0409_1000_3004 +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3008 = + {0x1000, 0x3008, pci_subsys_1000_0409_1000_3008, 0}; +#undef pci_ss_info_1000_3008 +#define pci_ss_info_1000_3008 pci_ss_info_1000_0409_1000_3008 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3008 = + {0x8086, 0x3008, pci_subsys_1000_0409_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_1000_0409_8086_3008 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3431 = + {0x8086, 0x3431, pci_subsys_1000_0409_8086_3431, 0}; +#undef pci_ss_info_8086_3431 +#define pci_ss_info_8086_3431 pci_ss_info_1000_0409_8086_3431 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3499 = + {0x8086, 0x3499, pci_subsys_1000_0409_8086_3499, 0}; +#undef pci_ss_info_8086_3499 +#define pci_ss_info_8086_3499 pci_ss_info_1000_0409_8086_3499 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0622_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_0622_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_0622_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_0626_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0626_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0626_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0518 = + {0x1000, 0x0518, pci_subsys_1000_1960_1000_0518, 0}; +#undef pci_ss_info_1000_0518 +#define pci_ss_info_1000_0518 pci_ss_info_1000_1960_1000_0518 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0520 = + {0x1000, 0x0520, pci_subsys_1000_1960_1000_0520, 0}; +#undef pci_ss_info_1000_0520 +#define pci_ss_info_1000_0520 pci_ss_info_1000_1960_1000_0520 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0522 = + {0x1000, 0x0522, pci_subsys_1000_1960_1000_0522, 0}; +#undef pci_ss_info_1000_0522 +#define pci_ss_info_1000_0522 pci_ss_info_1000_1960_1000_0522 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0523 = + {0x1000, 0x0523, pci_subsys_1000_1960_1000_0523, 0}; +#undef pci_ss_info_1000_0523 +#define pci_ss_info_1000_0523 pci_ss_info_1000_1960_1000_0523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_4523 = + {0x1000, 0x4523, pci_subsys_1000_1960_1000_4523, 0}; +#undef pci_ss_info_1000_4523 +#define pci_ss_info_1000_4523 pci_ss_info_1000_1960_1000_4523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_a520 = + {0x1000, 0xa520, pci_subsys_1000_1960_1000_a520, 0}; +#undef pci_ss_info_1000_a520 +#define pci_ss_info_1000_a520 pci_ss_info_1000_1960_1000_a520 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_1960_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_1960_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0520 = + {0x8086, 0x0520, pci_subsys_1000_1960_8086_0520, 0}; +#undef pci_ss_info_8086_0520 +#define pci_ss_info_8086_0520 pci_ss_info_1000_1960_8086_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0523 = + {0x8086, 0x0523, pci_subsys_1000_1960_8086_0523, 0}; +#undef pci_ss_info_8086_0523 +#define pci_ss_info_8086_0523 pci_ss_info_1000_1960_8086_0523 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4150_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4150_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4150_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4150_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4150_1458_4024 = + {0x1458, 0x4024, pci_subsys_1002_4150_1458_4024, 0}; +#undef pci_ss_info_1458_4024 +#define pci_ss_info_1458_4024 pci_ss_info_1002_4150_1458_4024 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2064 = + {0x148c, 0x2064, pci_subsys_1002_4150_148c_2064, 0}; +#undef pci_ss_info_148c_2064 +#define pci_ss_info_148c_2064 pci_ss_info_1002_4150_148c_2064 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2066 = + {0x148c, 0x2066, pci_subsys_1002_4150_148c_2066, 0}; +#undef pci_ss_info_148c_2066 +#define pci_ss_info_148c_2066 pci_ss_info_1002_4150_148c_2066 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c19 = + {0x174b, 0x7c19, pci_subsys_1002_4150_174b_7c19, 0}; +#undef pci_ss_info_174b_7c19 +#define pci_ss_info_174b_7c19 pci_ss_info_1002_4150_174b_7c19 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4150_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4150_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4150_17ee_2002 = + {0x17ee, 0x2002, pci_subsys_1002_4150_17ee_2002, 0}; +#undef pci_ss_info_17ee_2002 +#define pci_ss_info_17ee_2002 pci_ss_info_1002_4150_17ee_2002 +static const pciSubsystemInfo pci_ss_info_1002_4150_18bc_0101 = + {0x18bc, 0x0101, pci_subsys_1002_4150_18bc_0101, 0}; +#undef pci_ss_info_18bc_0101 +#define pci_ss_info_18bc_0101 pci_ss_info_1002_4150_18bc_0101 +static const pciSubsystemInfo pci_ss_info_1002_4151_1043_c004 = + {0x1043, 0xc004, pci_subsys_1002_4151_1043_c004, 0}; +#undef pci_ss_info_1043_c004 +#define pci_ss_info_1043_c004 pci_ss_info_1002_4151_1043_c004 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4152_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4152_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_4772 = + {0x1002, 0x4772, pci_subsys_1002_4152_1002_4772, 0}; +#undef pci_ss_info_1002_4772 +#define pci_ss_info_1002_4772 pci_ss_info_1002_4152_1002_4772 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c002 = + {0x1043, 0xc002, pci_subsys_1002_4152_1043_c002, 0}; +#undef pci_ss_info_1043_c002 +#define pci_ss_info_1043_c002 pci_ss_info_1002_4152_1043_c002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c01a = + {0x1043, 0xc01a, pci_subsys_1002_4152_1043_c01a, 0}; +#undef pci_ss_info_1043_c01a +#define pci_ss_info_1043_c01a pci_ss_info_1002_4152_1043_c01a +static const pciSubsystemInfo pci_ss_info_1002_4152_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4152_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4152_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4152_1787_4002 = + {0x1787, 0x4002, pci_subsys_1002_4152_1787_4002, 0}; +#undef pci_ss_info_1787_4002 +#define pci_ss_info_1787_4002 pci_ss_info_1002_4152_1787_4002 +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4170_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4170_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4170_1458_4025 = + {0x1458, 0x4025, pci_subsys_1002_4170_1458_4025, 0}; +#undef pci_ss_info_1458_4025 +#define pci_ss_info_1458_4025 pci_ss_info_1002_4170_1458_4025 +static const pciSubsystemInfo pci_ss_info_1002_4170_148c_2067 = + {0x148c, 0x2067, pci_subsys_1002_4170_148c_2067, 0}; +#undef pci_ss_info_148c_2067 +#define pci_ss_info_148c_2067 pci_ss_info_1002_4170_148c_2067 +static const pciSubsystemInfo pci_ss_info_1002_4170_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4170_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4170_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4170_17ee_2003 = + {0x17ee, 0x2003, pci_subsys_1002_4170_17ee_2003, 0}; +#undef pci_ss_info_17ee_2003 +#define pci_ss_info_17ee_2003 pci_ss_info_1002_4170_17ee_2003 +static const pciSubsystemInfo pci_ss_info_1002_4170_18bc_0100 = + {0x18bc, 0x0100, pci_subsys_1002_4170_18bc_0100, 0}; +#undef pci_ss_info_18bc_0100 +#define pci_ss_info_18bc_0100 pci_ss_info_1002_4170_18bc_0100 +static const pciSubsystemInfo pci_ss_info_1002_4171_1043_c005 = + {0x1043, 0xc005, pci_subsys_1002_4171_1043_c005, 0}; +#undef pci_ss_info_1043_c005 +#define pci_ss_info_1043_c005 pci_ss_info_1002_4171_1043_c005 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4172_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4172_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_4773 = + {0x1002, 0x4773, pci_subsys_1002_4172_1002_4773, 0}; +#undef pci_ss_info_1002_4773 +#define pci_ss_info_1002_4773 pci_ss_info_1002_4172_1002_4773 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c003 = + {0x1043, 0xc003, pci_subsys_1002_4172_1043_c003, 0}; +#undef pci_ss_info_1043_c003 +#define pci_ss_info_1043_c003 pci_ss_info_1002_4172_1043_c003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c01b = + {0x1043, 0xc01b, pci_subsys_1002_4172_1043_c01b, 0}; +#undef pci_ss_info_1043_c01b +#define pci_ss_info_1043_c01b pci_ss_info_1002_4172_1043_c01b +static const pciSubsystemInfo pci_ss_info_1002_4172_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4172_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4172_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4172_1787_4003 = + {0x1787, 0x4003, pci_subsys_1002_4172_1787_4003, 0}; +#undef pci_ss_info_1787_4003 +#define pci_ss_info_1787_4003 pci_ss_info_1002_4172_1787_4003 +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4336_1002_4336 = + {0x1002, 0x4336, pci_subsys_1002_4336_1002_4336, 0}; +#undef pci_ss_info_1002_4336 +#define pci_ss_info_1002_4336 pci_ss_info_1002_4336_1002_4336 +static const pciSubsystemInfo pci_ss_info_1002_4336_103c_0024 = + {0x103c, 0x0024, pci_subsys_1002_4336_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_1002_4336_103c_0024 +static const pciSubsystemInfo pci_ss_info_1002_4336_161f_2029 = + {0x161f, 0x2029, pci_subsys_1002_4336_161f_2029, 0}; +#undef pci_ss_info_161f_2029 +#define pci_ss_info_161f_2029 pci_ss_info_1002_4336_161f_2029 +static const pciSubsystemInfo pci_ss_info_1002_4337_1014_053a = + {0x1014, 0x053a, pci_subsys_1002_4337_1014_053a, 0}; +#undef pci_ss_info_1014_053a +#define pci_ss_info_1014_053a pci_ss_info_1002_4337_1014_053a +static const pciSubsystemInfo pci_ss_info_1002_4337_103c_0850 = + {0x103c, 0x0850, pci_subsys_1002_4337_103c_0850, 0}; +#undef pci_ss_info_103c_0850 +#define pci_ss_info_103c_0850 pci_ss_info_1002_4337_103c_0850 +static const pciSubsystemInfo pci_ss_info_1002_4370_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4370_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4370_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4371_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4371_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4371_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4372_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4372_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4372_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4373_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4373_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4373_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4374_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4374_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4374_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4375_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4375_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4375_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4376_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4376_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4376_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4377_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4377_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4377_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4378_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4378_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4378_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00ce = + {0x1028, 0x00ce, pci_subsys_1002_4752_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_1002_4752_1028_00ce +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1002_4752_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1002_4752_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_0134 = + {0x1028, 0x0134, pci_subsys_1002_4752_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_1002_4752_1028_0134 +static const pciSubsystemInfo pci_ss_info_1002_4752_1734_007a = + {0x1734, 0x007a, pci_subsys_1002_4752_1734_007a, 0}; +#undef pci_ss_info_1734_007a +#define pci_ss_info_1734_007a pci_ss_info_1002_4752_1734_007a +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3411 = + {0x8086, 0x3411, pci_subsys_1002_4752_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_1002_4752_8086_3411 +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3427 = + {0x8086, 0x3427, pci_subsys_1002_4752_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_1002_4752_8086_3427 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_475a_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_475a_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e7 = + {0x0e11, 0xb0e7, pci_subsys_1002_4c42_0e11_b0e7, 0}; +#undef pci_ss_info_0e11_b0e7 +#define pci_ss_info_0e11_b0e7 pci_ss_info_1002_4c42_0e11_b0e7 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c46_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_1002_4c46_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_1002_4c46_1028_00b1 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b160 = + {0x0e11, 0xb160, pci_subsys_1002_4c4d_0e11_b160, 0}; +#undef pci_ss_info_0e11_b160 +#define pci_ss_info_0e11_b160 pci_ss_info_1002_4c4d_0e11_b160 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00aa = + {0x1028, 0x00aa, pci_subsys_1002_4c4d_1028_00aa, 0}; +#undef pci_ss_info_1028_00aa +#define pci_ss_info_1028_00aa pci_ss_info_1002_4c4d_1028_00aa +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00bb = + {0x1028, 0x00bb, pci_subsys_1002_4c4d_1028_00bb, 0}; +#undef pci_ss_info_1028_00bb +#define pci_ss_info_1028_00bb pci_ss_info_1002_4c4d_1028_00bb +static const pciSubsystemInfo pci_ss_info_1002_4c4d_10e1_10cf = + {0x10e1, 0x10cf, pci_subsys_1002_4c4d_10e1_10cf, 0}; +#undef pci_ss_info_10e1_10cf +#define pci_ss_info_10e1_10cf pci_ss_info_1002_4c4d_10e1_10cf +static const pciSubsystemInfo pci_ss_info_1002_4c4d_13bd_1019 = + {0x13bd, 0x1019, pci_subsys_1002_4c4d_13bd_1019, 0}; +#undef pci_ss_info_13bd_1019 +#define pci_ss_info_13bd_1019 pci_ss_info_1002_4c4d_13bd_1019 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c52_1033_8112 = + {0x1033, 0x8112, pci_subsys_1002_4c52_1033_8112, 0}; +#undef pci_ss_info_1033_8112 +#define pci_ss_info_1033_8112 pci_ss_info_1002_4c52_1033_8112 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_012a = + {0x1028, 0x012a, pci_subsys_1002_4c57_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_1002_4c57_1028_012a +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c59_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c59_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1509_1930 = + {0x1509, 0x1930, pci_subsys_1002_4c59_1509_1930, 0}; +#undef pci_ss_info_1509_1930 +#define pci_ss_info_1509_1930 pci_ss_info_1002_4c59_1509_1930 +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_515e = + {0x1002, 0x515e, pci_subsys_1002_4e44_1002_515e, 0}; +#undef pci_ss_info_1002_515e +#define pci_ss_info_1002_515e pci_ss_info_1002_4e44_1002_515e +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_5965 = + {0x1002, 0x5965, pci_subsys_1002_4e44_1002_5965, 0}; +#undef pci_ss_info_1002_5965 +#define pci_ss_info_1002_5965 pci_ss_info_1002_4e44_1002_5965 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4e45_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4e45_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1681_0002 = + {0x1681, 0x0002, pci_subsys_1002_4e45_1681_0002, 0}; +#undef pci_ss_info_1681_0002 +#define pci_ss_info_1681_0002 pci_ss_info_1002_4e45_1681_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1025_005a = + {0x1025, 0x005a, pci_subsys_1002_4e50_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1002_4e50_1025_005a +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_088c = + {0x103c, 0x088c, pci_subsys_1002_4e50_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1002_4e50_103c_088c +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_0890 = + {0x103c, 0x0890, pci_subsys_1002_4e50_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1002_4e50_103c_0890 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1734_1055 = + {0x1734, 0x1055, pci_subsys_1002_4e50_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_1002_4e50_1734_1055 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4e65_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4e65_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1681_0003 = + {0x1681, 0x0003, pci_subsys_1002_4e65_1681_0003, 0}; +#undef pci_ss_info_1681_0003 +#define pci_ss_info_1681_0003 pci_ss_info_1002_4e65_1681_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e6a_1002_4e71 = + {0x1002, 0x4e71, pci_subsys_1002_4e6a_1002_4e71, 0}; +#undef pci_ss_info_1002_4e71 +#define pci_ss_info_1002_4e71 pci_ss_info_1002_4e6a_1002_4e71 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_1681_0010 = + {0x1681, 0x0010, pci_subsys_1002_514c_1681_0010, 0}; +#undef pci_ss_info_1681_0010 +#define pci_ss_info_1681_0010 pci_ss_info_1002_514c_1681_0010 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_103a = + {0x1002, 0x103a, pci_subsys_1002_5157_1002_103a, 0}; +#undef pci_ss_info_1002_103a +#define pci_ss_info_1002_103a pci_ss_info_1002_5157_1002_103a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7146 = + {0x174b, 0x7146, pci_subsys_1002_5157_174b_7146, 0}; +#undef pci_ss_info_174b_7146 +#define pci_ss_info_174b_7146 pci_ss_info_1002_5157_174b_7146 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1028_019a = + {0x1028, 0x019a, pci_subsys_1002_5159_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_1002_5159_1028_019a +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_5159_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_5159_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_5346_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5346_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5346_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5941_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5941_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5941_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5941_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5941_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5941_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5941_17af_200d = + {0x17af, 0x200d, pci_subsys_1002_5941_17af_200d, 0}; +#undef pci_ss_info_17af_200d +#define pci_ss_info_17af_200d pci_ss_info_1002_5941_17af_200d +static const pciSubsystemInfo pci_ss_info_1002_5941_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5941_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5941_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5950_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5950_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5950_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5954_1002_5954 = + {0x1002, 0x5954, pci_subsys_1002_5954_1002_5954, 0}; +#undef pci_ss_info_1002_5954 +#define pci_ss_info_1002_5954 pci_ss_info_1002_5954_1002_5954 +static const pciSubsystemInfo pci_ss_info_1002_5955_1002_5955 = + {0x1002, 0x5955, pci_subsys_1002_5955_1002_5955, 0}; +#undef pci_ss_info_1002_5955 +#define pci_ss_info_1002_5955 pci_ss_info_1002_5955_1002_5955 +static const pciSubsystemInfo pci_ss_info_1002_5955_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5955_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5955_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5961_1002_2f72 = + {0x1002, 0x2f72, pci_subsys_1002_5961_1002_2f72, 0}; +#undef pci_ss_info_1002_2f72 +#define pci_ss_info_1002_2f72 pci_ss_info_1002_5961_1002_2f72 +static const pciSubsystemInfo pci_ss_info_1002_5961_1019_4c30 = + {0x1019, 0x4c30, pci_subsys_1002_5961_1019_4c30, 0}; +#undef pci_ss_info_1019_4c30 +#define pci_ss_info_1019_4c30 pci_ss_info_1002_5961_1019_4c30 +static const pciSubsystemInfo pci_ss_info_1002_5961_12ab_5961 = + {0x12ab, 0x5961, pci_subsys_1002_5961_12ab_5961, 0}; +#undef pci_ss_info_12ab_5961 +#define pci_ss_info_12ab_5961 pci_ss_info_1002_5961_12ab_5961 +static const pciSubsystemInfo pci_ss_info_1002_5961_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5961_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5961_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5961_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5961_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5961_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5961_17af_200c = + {0x17af, 0x200c, pci_subsys_1002_5961_17af_200c, 0}; +#undef pci_ss_info_17af_200c +#define pci_ss_info_17af_200c pci_ss_info_1002_5961_17af_200c +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5961_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5961_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0051 = + {0x18bc, 0x0051, pci_subsys_1002_5961_18bc_0051, 0}; +#undef pci_ss_info_18bc_0051 +#define pci_ss_info_18bc_0051 pci_ss_info_1002_5961_18bc_0051 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0053 = + {0x18bc, 0x0053, pci_subsys_1002_5961_18bc_0053, 0}; +#undef pci_ss_info_18bc_0053 +#define pci_ss_info_18bc_0053 pci_ss_info_1002_5961_18bc_0053 +static const pciSubsystemInfo pci_ss_info_1002_5964_1043_c006 = + {0x1043, 0xc006, pci_subsys_1002_5964_1043_c006, 0}; +#undef pci_ss_info_1043_c006 +#define pci_ss_info_1043_c006 pci_ss_info_1002_5964_1043_c006 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5964_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5964_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5964_147b_6191 = + {0x147b, 0x6191, pci_subsys_1002_5964_147b_6191, 0}; +#undef pci_ss_info_147b_6191 +#define pci_ss_info_147b_6191 pci_ss_info_1002_5964_147b_6191 +static const pciSubsystemInfo pci_ss_info_1002_5964_148c_2073 = + {0x148c, 0x2073, pci_subsys_1002_5964_148c_2073, 0}; +#undef pci_ss_info_148c_2073 +#define pci_ss_info_148c_2073 pci_ss_info_1002_5964_148c_2073 +static const pciSubsystemInfo pci_ss_info_1002_5964_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5964_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5964_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5964_1787_5964 = + {0x1787, 0x5964, pci_subsys_1002_5964_1787_5964, 0}; +#undef pci_ss_info_1787_5964 +#define pci_ss_info_1787_5964 pci_ss_info_1002_5964_1787_5964 +static const pciSubsystemInfo pci_ss_info_1002_5964_17af_2012 = + {0x17af, 0x2012, pci_subsys_1002_5964_17af_2012, 0}; +#undef pci_ss_info_17af_2012 +#define pci_ss_info_17af_2012 pci_ss_info_1002_5964_17af_2012 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0170 = + {0x18bc, 0x0170, pci_subsys_1002_5964_18bc_0170, 0}; +#undef pci_ss_info_18bc_0170 +#define pci_ss_info_18bc_0170 pci_ss_info_1002_5964_18bc_0170 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0173 = + {0x18bc, 0x0173, pci_subsys_1002_5964_18bc_0173, 0}; +#undef pci_ss_info_18bc_0173 +#define pci_ss_info_18bc_0173 pci_ss_info_1002_5964_18bc_0173 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_002a = + {0x1043, 0x002a, pci_subsys_1002_5b60_1043_002a, 0}; +#undef pci_ss_info_1043_002a +#define pci_ss_info_1043_002a pci_ss_info_1002_5b60_1043_002a +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_032e = + {0x1043, 0x032e, pci_subsys_1002_5b60_1043_032e, 0}; +#undef pci_ss_info_1043_032e +#define pci_ss_info_1043_032e pci_ss_info_1002_5b60_1043_032e +static const pciSubsystemInfo pci_ss_info_1002_5c63_1002_5c63 = + {0x1002, 0x5c63, pci_subsys_1002_5c63_1002_5c63, 0}; +#undef pci_ss_info_1002_5c63 +#define pci_ss_info_1002_5c63 pci_ss_info_1002_5c63_1002_5c63 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5d44_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5d44_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5d44_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5d44_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5d44_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1787_5965 = + {0x1787, 0x5965, pci_subsys_1002_5d44_1787_5965, 0}; +#undef pci_ss_info_1787_5965 +#define pci_ss_info_1787_5965 pci_ss_info_1002_5d44_1787_5965 +static const pciSubsystemInfo pci_ss_info_1002_5d44_17af_2013 = + {0x17af, 0x2013, pci_subsys_1002_5d44_17af_2013, 0}; +#undef pci_ss_info_17af_2013 +#define pci_ss_info_17af_2013 pci_ss_info_1002_5d44_17af_2013 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0171 = + {0x18bc, 0x0171, pci_subsys_1002_5d44_18bc_0171, 0}; +#undef pci_ss_info_18bc_0171 +#define pci_ss_info_18bc_0171 pci_ss_info_1002_5d44_18bc_0171 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0172 = + {0x18bc, 0x0172, pci_subsys_1002_5d44_18bc_0172, 0}; +#undef pci_ss_info_18bc_0172 +#define pci_ss_info_18bc_0172 pci_ss_info_1002_5d44_18bc_0172 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b12 = + {0x1002, 0x0b12, pci_subsys_1002_5d52_1002_0b12, 0}; +#undef pci_ss_info_1002_0b12 +#define pci_ss_info_1002_0b12 pci_ss_info_1002_5d52_1002_0b12 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b13 = + {0x1002, 0x0b13, pci_subsys_1002_5d52_1002_0b13, 0}; +#undef pci_ss_info_1002_0b13 +#define pci_ss_info_1002_0b13 pci_ss_info_1002_5d52_1002_0b13 +static const pciSubsystemInfo pci_ss_info_1002_5e4d_148c_2116 = + {0x148c, 0x2116, pci_subsys_1002_5e4d_148c_2116, 0}; +#undef pci_ss_info_148c_2116 +#define pci_ss_info_148c_2116 pci_ss_info_1002_5e4d_148c_2116 +static const pciSubsystemInfo pci_ss_info_1002_5e6d_148c_2117 = + {0x148c, 0x2117, pci_subsys_1002_5e6d_148c_2117, 0}; +#undef pci_ss_info_148c_2117 +#define pci_ss_info_148c_2117 pci_ss_info_1002_5e6d_148c_2117 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_100b_0020_103c_0024 = + {0x103c, 0x0024, pci_subsys_100b_0020_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_100b_0020_103c_0024 +static const pciSubsystemInfo pci_ss_info_100b_0020_1385_f311 = + {0x1385, 0xf311, pci_subsys_100b_0020_1385_f311, 0}; +#undef pci_ss_info_1385_f311 +#define pci_ss_info_1385_f311 pci_ss_info_100b_0020_1385_f311 +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0019_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0019_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_14cb_0100 = + {0x14cb, 0x0100, pci_subsys_1011_0019_14cb_0100, 0}; +#undef pci_ss_info_14cb_0100 +#define pci_ss_info_14cb_0100 pci_ss_info_1011_0019_14cb_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1011_0046_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1011_0046_4c53_1050 +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_1011_0046_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_1011_0046_4c53_1051 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0364 = + {0x9005, 0x0364, pci_subsys_1011_0046_9005_0364, 0}; +#undef pci_ss_info_9005_0364 +#define pci_ss_info_9005_0364 pci_ss_info_1011_0046_9005_0364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_1136 = + {0x153b, 0x1136, pci_subsys_1013_6003_153b_1136, 0}; +#undef pci_ss_info_153b_1136 +#define pci_ss_info_153b_1136 pci_ss_info_1013_6003_153b_1136 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_0031_1014_0031 = + {0x1014, 0x0031, pci_subsys_1014_0031_1014_0031, 0}; +#undef pci_ss_info_1014_0031 +#define pci_ss_info_1014_0031 pci_ss_info_1014_0031_1014_0031 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +#endif +static const pciSubsystemInfo pci_ss_info_1014_00b7_1092_00b8 = + {0x1092, 0x00b8, pci_subsys_1014_00b7_1092_00b8, 0}; +#undef pci_ss_info_1092_00b8 +#define pci_ss_info_1092_00b8 pci_ss_info_1014_00b7_1092_00b8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0241 = + {0x1014, 0x0241, pci_subsys_1014_0180_1014_0241, 0}; +#undef pci_ss_info_1014_0241 +#define pci_ss_info_1014_0241 pci_ss_info_1014_0180_1014_0241 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0264 = + {0x1014, 0x0264, pci_subsys_1014_0180_1014_0264, 0}; +#undef pci_ss_info_1014_0264 +#define pci_ss_info_1014_0264 pci_ss_info_1014_0180_1014_0264 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_021a = + {0x1014, 0x021a, pci_subsys_1014_0219_1014_021a, 0}; +#undef pci_ss_info_1014_021a +#define pci_ss_info_1014_021a pci_ss_info_1014_0219_1014_021a +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0251 = + {0x1014, 0x0251, pci_subsys_1014_0219_1014_0251, 0}; +#undef pci_ss_info_1014_0251 +#define pci_ss_info_1014_0251 pci_ss_info_1014_0219_1014_0251 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0252 = + {0x1014, 0x0252, pci_subsys_1014_0219_1014_0252, 0}; +#undef pci_ss_info_1014_0252 +#define pci_ss_info_1014_0252 pci_ss_info_1014_0219_1014_0252 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_028d = + {0x1014, 0x028d, pci_subsys_1014_028c_1014_028d, 0}; +#undef pci_ss_info_1014_028d +#define pci_ss_info_1014_028d pci_ss_info_1014_028c_1014_028d +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02be = + {0x1014, 0x02be, pci_subsys_1014_028c_1014_02be, 0}; +#undef pci_ss_info_1014_02be +#define pci_ss_info_1014_02be pci_ss_info_1014_028c_1014_02be +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02c0 = + {0x1014, 0x02c0, pci_subsys_1014_028c_1014_02c0, 0}; +#undef pci_ss_info_1014_02c0 +#define pci_ss_info_1014_02c0 pci_ss_info_1014_028c_1014_02c0 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_030d = + {0x1014, 0x030d, pci_subsys_1014_028c_1014_030d, 0}; +#undef pci_ss_info_1014_030d +#define pci_ss_info_1014_030d pci_ss_info_1014_028c_1014_030d +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0477 = + {0x101e, 0x0477, pci_subsys_101e_1960_101e_0477, 0}; +#undef pci_ss_info_101e_0477 +#define pci_ss_info_101e_0477 pci_ss_info_101e_1960_101e_0477 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0494 = + {0x101e, 0x0494, pci_subsys_101e_1960_101e_0494, 0}; +#undef pci_ss_info_101e_0494 +#define pci_ss_info_101e_0494 pci_ss_info_101e_1960_101e_0494 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0503 = + {0x101e, 0x0503, pci_subsys_101e_1960_101e_0503, 0}; +#undef pci_ss_info_101e_0503 +#define pci_ss_info_101e_0503 pci_ss_info_101e_1960_101e_0503 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0511 = + {0x101e, 0x0511, pci_subsys_101e_1960_101e_0511, 0}; +#undef pci_ss_info_101e_0511 +#define pci_ss_info_101e_0511 pci_ss_info_101e_1960_101e_0511 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0522 = + {0x101e, 0x0522, pci_subsys_101e_1960_101e_0522, 0}; +#undef pci_ss_info_101e_0522 +#define pci_ss_info_101e_0522 pci_ss_info_101e_1960_101e_0522 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_103c_60e7 = + {0x103c, 0x60e7, pci_subsys_101e_1960_103c_60e7, 0}; +#undef pci_ss_info_103c_60e7 +#define pci_ss_info_103c_60e7 pci_ss_info_101e_1960_103c_60e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_1022_2000 = + {0x1022, 0x2000, pci_subsys_1022_2000_1022_2000, 0}; +#undef pci_ss_info_1022_2000 +#define pci_ss_info_1022_2000 pci_ss_info_1022_2000_1022_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2702 = + {0x1259, 0x2702, pci_subsys_1022_2000_1259_2702, 0}; +#undef pci_ss_info_1259_2702 +#define pci_ss_info_1259_2702 pci_ss_info_1022_2000_1259_2702 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2703 = + {0x1259, 0x2703, pci_subsys_1022_2000_1259_2703, 0}; +#undef pci_ss_info_1259_2703 +#define pci_ss_info_1259_2703 pci_ss_info_1022_2000_1259_2703 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1022_2000_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1022_2000_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_1022_2000_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_1022_2000_4c53_1010 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_1022_2000_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_1022_2000_4c53_1020 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_1022_2000_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_1022_2000_4c53_1030 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_1022_2000_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_1022_2000_4c53_1040 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_1022_2000_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_1022_2000_4c53_1060 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7460_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7460_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7460_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7464_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7464_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7464_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7468_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7468_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7468_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7469_1022_2b80 = + {0x1022, 0x2b80, pci_subsys_1022_7469_1022_2b80, 0}; +#undef pci_ss_info_1022_2b80 +#define pci_ss_info_1022_2b80 pci_ss_info_1022_7469_1022_2b80 +static const pciSubsystemInfo pci_ss_info_1022_7469_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7469_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7469_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746b_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746b_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746b_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746d_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746d_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746d_161f_3017 +static const pciSubsystemInfo pci_ss_info_1023_2001_122d_1400 = + {0x122d, 0x1400, pci_subsys_1023_2001_122d_1400, 0}; +#undef pci_ss_info_122d_1400 +#define pci_ss_info_122d_1400 pci_ss_info_1023_2001_122d_1400 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_1025 = + {0x1014, 0x1025, pci_subsys_1023_8620_1014_1025, 0}; +#undef pci_ss_info_1014_1025 +#define pci_ss_info_1014_1025 pci_ss_info_1023_8620_1014_1025 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016c = + {0x1028, 0x016c, pci_subsys_1028_0013_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1028_0013_1028_016c +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016d = + {0x1028, 0x016d, pci_subsys_1028_0013_1028_016d, 0}; +#undef pci_ss_info_1028_016d +#define pci_ss_info_1028_016d pci_ss_info_1028_0013_1028_016d +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016e = + {0x1028, 0x016e, pci_subsys_1028_0013_1028_016e, 0}; +#undef pci_ss_info_1028_016e +#define pci_ss_info_1028_016e pci_ss_info_1028_0013_1028_016e +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016f = + {0x1028, 0x016f, pci_subsys_1028_0013_1028_016f, 0}; +#undef pci_ss_info_1028_016f +#define pci_ss_info_1028_016f pci_ss_info_1028_0013_1028_016f +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_0170 = + {0x1028, 0x0170, pci_subsys_1028_0013_1028_0170, 0}; +#undef pci_ss_info_1028_0170 +#define pci_ss_info_1028_0170 pci_ss_info_1028_0013_1028_0170 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_102a_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_102a_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_0106 = + {0x9005, 0x0106, pci_subsys_102a_001f_9005_0106, 0}; +#undef pci_ss_info_9005_0106 +#define pci_ss_info_9005_0106 pci_ss_info_102a_001f_9005_0106 +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_102a_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_102a_001f_9005_a180 +#endif +static const pciSubsystemInfo pci_ss_info_102a_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_102a_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_102a_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0106 = + {0x1028, 0x0106, pci_subsys_102a_00cf_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_102a_00cf_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0121 = + {0x1028, 0x0121, pci_subsys_102a_00cf_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_102a_00cf_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d43 = + {0x102b, 0x0d43, pci_subsys_102b_0525_102b_0d43, 0}; +#undef pci_ss_info_102b_0d43 +#define pci_ss_info_102b_0d43 pci_ss_info_102b_0525_102b_0d43 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0850 = + {0x102b, 0x0850, pci_subsys_102b_0527_102b_0850, 0}; +#undef pci_ss_info_102b_0850 +#define pci_ss_info_102b_0850 pci_ss_info_102b_0527_102b_0850 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1020 = + {0x102b, 0x1020, pci_subsys_102b_0528_102b_1020, 0}; +#undef pci_ss_info_102b_1020 +#define pci_ss_info_102b_1020 pci_ss_info_102b_0528_102b_1020 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1030 = + {0x102b, 0x1030, pci_subsys_102b_0528_102b_1030, 0}; +#undef pci_ss_info_102b_1030 +#define pci_ss_info_102b_1030 pci_ss_info_102b_0528_102b_1030 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_14e1 = + {0x102b, 0x14e1, pci_subsys_102b_0528_102b_14e1, 0}; +#undef pci_ss_info_102b_14e1 +#define pci_ss_info_102b_14e1 pci_ss_info_102b_0528_102b_14e1 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_2021 = + {0x102b, 0x2021, pci_subsys_102b_0528_102b_2021, 0}; +#undef pci_ss_info_102b_2021 +#define pci_ss_info_102b_2021 pci_ss_info_102b_0528_102b_2021 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1820 = + {0x102b, 0x1820, pci_subsys_102b_2537_102b_1820, 0}; +#undef pci_ss_info_102b_1820 +#define pci_ss_info_102b_1820 pci_ss_info_102b_2537_102b_1820 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1830 = + {0x102b, 0x1830, pci_subsys_102b_2537_102b_1830, 0}; +#undef pci_ss_info_102b_1830 +#define pci_ss_info_102b_1830 pci_ss_info_102b_2537_102b_1830 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1c10 = + {0x102b, 0x1c10, pci_subsys_102b_2537_102b_1c10, 0}; +#undef pci_ss_info_102b_1c10 +#define pci_ss_info_102b_1c10 pci_ss_info_102b_2537_102b_1c10 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2811 = + {0x102b, 0x2811, pci_subsys_102b_2537_102b_2811, 0}; +#undef pci_ss_info_102b_2811 +#define pci_ss_info_102b_2811 pci_ss_info_102b_2537_102b_2811 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2c11 = + {0x102b, 0x2c11, pci_subsys_102b_2537_102b_2c11, 0}; +#undef pci_ss_info_102b_2c11 +#define pci_ss_info_102b_2c11 pci_ss_info_102b_2537_102b_2c11 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_08c7 = + {0x102b, 0x08c7, pci_subsys_102b_2538_102b_08c7, 0}; +#undef pci_ss_info_102b_08c7 +#define pci_ss_info_102b_08c7 pci_ss_info_102b_2538_102b_08c7 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_0907 = + {0x102b, 0x0907, pci_subsys_102b_2538_102b_0907, 0}; +#undef pci_ss_info_102b_0907 +#define pci_ss_info_102b_0907 pci_ss_info_102b_2538_102b_0907 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1047 = + {0x102b, 0x1047, pci_subsys_102b_2538_102b_1047, 0}; +#undef pci_ss_info_102b_1047 +#define pci_ss_info_102b_1047 pci_ss_info_102b_2538_102b_1047 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1087 = + {0x102b, 0x1087, pci_subsys_102b_2538_102b_1087, 0}; +#undef pci_ss_info_102b_1087 +#define pci_ss_info_102b_1087 pci_ss_info_102b_2538_102b_1087 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_2538 = + {0x102b, 0x2538, pci_subsys_102b_2538_102b_2538, 0}; +#undef pci_ss_info_102b_2538 +#define pci_ss_info_102b_2538 pci_ss_info_102b_2538_102b_2538 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_3007 = + {0x102b, 0x3007, pci_subsys_102b_2538_102b_3007, 0}; +#undef pci_ss_info_102b_3007 +#define pci_ss_info_102b_3007 pci_ss_info_102b_2538_102b_3007 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_00c0_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_00c0_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_102c_00c0_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_102c_00c0_4c53_1010 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_102c_00c0_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_102c_00c0_4c53_1020 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_102c_00c0_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_102c_00c0_4c53_1030 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_00c0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_00c0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_00c0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_00c0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +static const pciSubsystemInfo pci_ss_info_102c_00e5_1179_0001 = + {0x1179, 0x0001, pci_subsys_102c_00e5_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_102c_00e5_1179_0001 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_0c30_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_0c30_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_0c30_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_0c30_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_0c30_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_0c30_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_102c_0c30_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_102c_0c30_4c53_1080 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1033_0035 = + {0x1033, 0x0035, pci_subsys_1033_0035_1033_0035, 0}; +#undef pci_ss_info_1033_0035 +#define pci_ss_info_1033_0035 pci_ss_info_1033_0035_1033_0035 +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_14c2_0105 = + {0x14c2, 0x0105, pci_subsys_1033_0035_14c2_0105, 0}; +#undef pci_ss_info_14c2_0105 +#define pci_ss_info_14c2_0105 pci_ss_info_1033_0035_14c2_0105 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000a = + {0x1931, 0x000a, pci_subsys_1033_0035_1931_000a, 0}; +#undef pci_ss_info_1931_000a +#define pci_ss_info_1931_000a pci_ss_info_1033_0035_1931_000a +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000b = + {0x1931, 0x000b, pci_subsys_1033_0035_1931_000b, 0}; +#undef pci_ss_info_1931_000b +#define pci_ss_info_1931_000b pci_ss_info_1033_0035_1931_000b +static const pciSubsystemInfo pci_ss_info_1033_0035_807d_0035 = + {0x807d, 0x0035, pci_subsys_1033_0035_807d_0035, 0}; +#undef pci_ss_info_807d_0035 +#define pci_ss_info_807d_0035 pci_ss_info_1033_0035_807d_0035 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_14c2_0205 = + {0x14c2, 0x0205, pci_subsys_1033_00e0_14c2_0205, 0}; +#undef pci_ss_info_14c2_0205 +#define pci_ss_info_14c2_0205 pci_ss_info_1033_00e0_14c2_0205 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1033_00e0_807d_1043 = + {0x807d, 0x1043, pci_subsys_1033_00e0_807d_1043, 0}; +#undef pci_ss_info_807d_1043 +#define pci_ss_info_807d_1043 pci_ss_info_1033_00e0_807d_1043 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_0900_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_0900_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_0900_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_0900_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_0900_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_5513_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_5513_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_5513_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6300_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_6300_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_6300_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_6330_1039_6330 = + {0x1039, 0x6330, pci_subsys_1039_6330_1039_6330, 0}; +#undef pci_ss_info_1039_6330 +#define pci_ss_info_1039_6330 pci_ss_info_1039_6330_1039_6330 +static const pciSubsystemInfo pci_ss_info_1039_7001_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_7001_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_7001_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7001_1462_5470 = + {0x1462, 0x5470, pci_subsys_1039_7001_1462_5470, 0}; +#undef pci_ss_info_1462_5470 +#define pci_ss_info_1462_5470 pci_ss_info_1039_7001_1462_5470 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1301 = + {0x103c, 0x1301, pci_subsys_103c_1048_103c_1301, 0}; +#undef pci_ss_info_103c_1301 +#define pci_ss_info_103c_1301 pci_ss_info_103c_1048_103c_1301 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1704 = + {0x0675, 0x1704, pci_subsys_1043_0675_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1043_0675_0675_1704 +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1707 = + {0x0675, 0x1707, pci_subsys_1043_0675_0675_1707, 0}; +#undef pci_ss_info_0675_1707 +#define pci_ss_info_0675_1707 pci_ss_info_1043_0675_0675_1707 +static const pciSubsystemInfo pci_ss_info_1043_0675_10cf_105e = + {0x10cf, 0x105e, pci_subsys_1043_0675_10cf_105e, 0}; +#undef pci_ss_info_10cf_105e +#define pci_ss_info_10cf_105e pci_ss_info_1043_0675_10cf_105e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c032 = + {0x1044, 0xc032, pci_subsys_1044_a511_1044_c032, 0}; +#undef pci_ss_info_1044_c032 +#define pci_ss_info_1044_c032 pci_ss_info_1044_a511_1044_c032 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c035 = + {0x1044, 0xc035, pci_subsys_1044_a511_1044_c035, 0}; +#undef pci_ss_info_1044_c035 +#define pci_ss_info_1044_c035 pci_ss_info_1044_a511_1044_c035 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1048_8901_1048_0935 = + {0x1048, 0x0935, pci_subsys_1048_8901_1048_0935, 0}; +#undef pci_ss_info_1048_0935 +#define pci_ss_info_1048_0935 pci_ss_info_1048_8901_1048_0935 +#endif +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a34 = + {0x1048, 0x0a34, pci_subsys_104c_3d07_1048_0a34, 0}; +#undef pci_ss_info_1048_0a34 +#define pci_ss_info_1048_0a34 pci_ss_info_104c_3d07_1048_0a34 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a36 = + {0x1048, 0x0a36, pci_subsys_104c_3d07_1048_0a36, 0}; +#undef pci_ss_info_1048_0a36 +#define pci_ss_info_1048_0a36 pci_ss_info_104c_3d07_1048_0a36 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a43 = + {0x1048, 0x0a43, pci_subsys_104c_3d07_1048_0a43, 0}; +#undef pci_ss_info_1048_0a43 +#define pci_ss_info_1048_0a43 pci_ss_info_104c_3d07_1048_0a43 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a44 = + {0x1048, 0x0a44, pci_subsys_104c_3d07_1048_0a44, 0}; +#undef pci_ss_info_1048_0a44 +#define pci_ss_info_1048_0a44 pci_ss_info_104c_3d07_1048_0a44 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_000f = + {0x11bd, 0x000f, pci_subsys_104c_8020_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_104c_8020_11bd_000f +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8023_103c_088c = + {0x103c, 0x088c, pci_subsys_104c_8023_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_104c_8023_103c_088c +static const pciSubsystemInfo pci_ss_info_104c_8023_1043_808b = + {0x1043, 0x808b, pci_subsys_104c_8023_1043_808b, 0}; +#undef pci_ss_info_1043_808b +#define pci_ss_info_1043_808b pci_ss_info_104c_8023_1043_808b +static const pciSubsystemInfo pci_ss_info_104c_8025_1458_1000 = + {0x1458, 0x1000, pci_subsys_104c_8025_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_104c_8025_1458_1000 +static const pciSubsystemInfo pci_ss_info_104c_8026_1043_808d = + {0x1043, 0x808d, pci_subsys_104c_8026_1043_808d, 0}; +#undef pci_ss_info_1043_808d +#define pci_ss_info_1043_808d pci_ss_info_104c_8026_1043_808d +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_8029_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_8029_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_8029_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_8029_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_8029_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_8029_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_8029_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_802b_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_802b_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_802b_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_802b_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8031_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8031_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8031_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8031_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8032_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8032_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8032_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8032_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8033_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8033_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8033_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8033_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8034_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8034_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8034_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8034_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8035_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8035_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8035_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_8204_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_8204_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_8204_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_8204_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b00 = + {0x1186, 0x3b00, pci_subsys_104c_8400_1186_3b00, 0}; +#undef pci_ss_info_1186_3b00 +#define pci_ss_info_1186_3b00 pci_ss_info_104c_8400_1186_3b00 +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b01 = + {0x1186, 0x3b01, pci_subsys_104c_8400_1186_3b01, 0}; +#undef pci_ss_info_1186_3b01 +#define pci_ss_info_1186_3b01 pci_ss_info_104c_8400_1186_3b01 +static const pciSubsystemInfo pci_ss_info_104c_8400_16ab_8501 = + {0x16ab, 0x8501, pci_subsys_104c_8400_16ab_8501, 0}; +#undef pci_ss_info_16ab_8501 +#define pci_ss_info_16ab_8501 pci_ss_info_104c_8400_16ab_8501 +static const pciSubsystemInfo pci_ss_info_104c_9066_104c_9066 = + {0x104c, 0x9066, pci_subsys_104c_9066_104c_9066, 0}; +#undef pci_ss_info_104c_9066 +#define pci_ss_info_104c_9066 pci_ss_info_104c_9066_104c_9066 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b04 = + {0x1186, 0x3b04, pci_subsys_104c_9066_1186_3b04, 0}; +#undef pci_ss_info_1186_3b04 +#define pci_ss_info_1186_3b04 pci_ss_info_104c_9066_1186_3b04 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b05 = + {0x1186, 0x3b05, pci_subsys_104c_9066_1186_3b05, 0}; +#undef pci_ss_info_1186_3b05 +#define pci_ss_info_1186_3b05 pci_ss_info_104c_9066_1186_3b05 +static const pciSubsystemInfo pci_ss_info_104c_9066_13d1_aba0 = + {0x13d1, 0xaba0, pci_subsys_104c_9066_13d1_aba0, 0}; +#undef pci_ss_info_13d1_aba0 +#define pci_ss_info_13d1_aba0 pci_ss_info_104c_9066_13d1_aba0 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_5000 = + {0x175c, 0x5000, pci_subsys_104c_a106_175c_5000, 0}; +#undef pci_ss_info_175c_5000 +#define pci_ss_info_175c_5000 pci_ss_info_104c_a106_175c_5000 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_6400 = + {0x175c, 0x6400, pci_subsys_104c_a106_175c_6400, 0}; +#undef pci_ss_info_175c_6400 +#define pci_ss_info_175c_6400 pci_ss_info_104c_a106_175c_6400 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_8700 = + {0x175c, 0x8700, pci_subsys_104c_a106_175c_8700, 0}; +#undef pci_ss_info_175c_8700 +#define pci_ss_info_175c_8700 pci_ss_info_104c_a106_175c_8700 +static const pciSubsystemInfo pci_ss_info_104c_ac16_1014_0092 = + {0x1014, 0x0092, pci_subsys_104c_ac16_1014_0092, 0}; +#undef pci_ss_info_1014_0092 +#define pci_ss_info_1014_0092 pci_ss_info_104c_ac16_1014_0092 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_1014_0130 = + {0x1014, 0x0130, pci_subsys_104c_ac1b_1014_0130, 0}; +#undef pci_ss_info_1014_0130 +#define pci_ss_info_1014_0130 pci_ss_info_104c_ac1b_1014_0130 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_0e11_b121 = + {0x0e11, 0xb121, pci_subsys_104c_ac1c_0e11_b121, 0}; +#undef pci_ss_info_0e11_b121 +#define pci_ss_info_0e11_b121 pci_ss_info_104c_ac1c_0e11_b121 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_1028_0088 = + {0x1028, 0x0088, pci_subsys_104c_ac1c_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_104c_ac1c_1028_0088 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_ac44_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_ac44_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_ac44_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_ac44_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_ac44_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_ac44_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac47_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac47_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac47_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac47_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac4a_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac4a_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac4a_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac4a_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac51_0e11_004e = + {0x0e11, 0x004e, pci_subsys_104c_ac51_0e11_004e, 0}; +#undef pci_ss_info_0e11_004e +#define pci_ss_info_0e11_004e pci_ss_info_104c_ac51_0e11_004e +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_104c_ac51_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_104c_ac51_1028_00b1 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_012a = + {0x1028, 0x012a, pci_subsys_104c_ac51_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_104c_ac51_1028_012a +static const pciSubsystemInfo pci_ss_info_104c_ac51_1033_80cd = + {0x1033, 0x80cd, pci_subsys_104c_ac51_1033_80cd, 0}; +#undef pci_ss_info_1033_80cd +#define pci_ss_info_1033_80cd pci_ss_info_104c_ac51_1033_80cd +static const pciSubsystemInfo pci_ss_info_104c_ac51_1095_10cf = + {0x1095, 0x10cf, pci_subsys_104c_ac51_1095_10cf, 0}; +#undef pci_ss_info_1095_10cf +#define pci_ss_info_1095_10cf pci_ss_info_104c_ac51_1095_10cf +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0528 = + {0x1014, 0x0528, pci_subsys_104c_ac56_1014_0528, 0}; +#undef pci_ss_info_1014_0528 +#define pci_ss_info_1014_0528 pci_ss_info_104c_ac56_1014_0528 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_5100 = + {0x175c, 0x5100, pci_subsys_104c_ac60_175c_5100, 0}; +#undef pci_ss_info_175c_5100 +#define pci_ss_info_175c_5100 pci_ss_info_104c_ac60_175c_5100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6100 = + {0x175c, 0x6100, pci_subsys_104c_ac60_175c_6100, 0}; +#undef pci_ss_info_175c_6100 +#define pci_ss_info_175c_6100 pci_ss_info_104c_ac60_175c_6100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6200 = + {0x175c, 0x6200, pci_subsys_104c_ac60_175c_6200, 0}; +#undef pci_ss_info_175c_6200 +#define pci_ss_info_175c_6200 pci_ss_info_104c_ac60_175c_6200 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_8800 = + {0x175c, 0x8800, pci_subsys_104c_ac60_175c_8800, 0}; +#undef pci_ss_info_175c_8800 +#define pci_ss_info_175c_8800 pci_ss_info_104c_ac60_175c_8800 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1702 = + {0x1043, 0x1702, pci_subsys_1050_6692_1043_1702, 0}; +#undef pci_ss_info_1043_1702 +#define pci_ss_info_1043_1702 pci_ss_info_1050_6692_1043_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1703 = + {0x1043, 0x1703, pci_subsys_1050_6692_1043_1703, 0}; +#undef pci_ss_info_1043_1703 +#define pci_ss_info_1043_1703 pci_ss_info_1050_6692_1043_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1707 = + {0x1043, 0x1707, pci_subsys_1050_6692_1043_1707, 0}; +#undef pci_ss_info_1043_1707 +#define pci_ss_info_1043_1707 pci_ss_info_1050_6692_1043_1707 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1702 = + {0x144f, 0x1702, pci_subsys_1050_6692_144f_1702, 0}; +#undef pci_ss_info_144f_1702 +#define pci_ss_info_144f_1702 pci_ss_info_1050_6692_144f_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1703 = + {0x144f, 0x1703, pci_subsys_1050_6692_144f_1703, 0}; +#undef pci_ss_info_144f_1703 +#define pci_ss_info_144f_1703 pci_ss_info_1050_6692_144f_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1707 = + {0x144f, 0x1707, pci_subsys_1050_6692_144f_1707, 0}; +#undef pci_ss_info_144f_1707 +#define pci_ss_info_144f_1707 pci_ss_info_1050_6692_144f_1707 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0101 = + {0x14fb, 0x0101, pci_subsys_1057_1801_14fb_0101, 0}; +#undef pci_ss_info_14fb_0101 +#define pci_ss_info_14fb_0101 pci_ss_info_1057_1801_14fb_0101 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0102 = + {0x14fb, 0x0102, pci_subsys_1057_1801_14fb_0102, 0}; +#undef pci_ss_info_14fb_0102 +#define pci_ss_info_14fb_0102 pci_ss_info_1057_1801_14fb_0102 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0202 = + {0x14fb, 0x0202, pci_subsys_1057_1801_14fb_0202, 0}; +#undef pci_ss_info_14fb_0202 +#define pci_ss_info_14fb_0202 pci_ss_info_1057_1801_14fb_0202 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0611 = + {0x14fb, 0x0611, pci_subsys_1057_1801_14fb_0611, 0}; +#undef pci_ss_info_14fb_0611 +#define pci_ss_info_14fb_0611 pci_ss_info_1057_1801_14fb_0611 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0612 = + {0x14fb, 0x0612, pci_subsys_1057_1801_14fb_0612, 0}; +#undef pci_ss_info_14fb_0612 +#define pci_ss_info_14fb_0612 pci_ss_info_1057_1801_14fb_0612 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0613 = + {0x14fb, 0x0613, pci_subsys_1057_1801_14fb_0613, 0}; +#undef pci_ss_info_14fb_0613 +#define pci_ss_info_14fb_0613 pci_ss_info_1057_1801_14fb_0613 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0614 = + {0x14fb, 0x0614, pci_subsys_1057_1801_14fb_0614, 0}; +#undef pci_ss_info_14fb_0614 +#define pci_ss_info_14fb_0614 pci_ss_info_1057_1801_14fb_0614 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0621 = + {0x14fb, 0x0621, pci_subsys_1057_1801_14fb_0621, 0}; +#undef pci_ss_info_14fb_0621 +#define pci_ss_info_14fb_0621 pci_ss_info_1057_1801_14fb_0621 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0622 = + {0x14fb, 0x0622, pci_subsys_1057_1801_14fb_0622, 0}; +#undef pci_ss_info_14fb_0622 +#define pci_ss_info_14fb_0622 pci_ss_info_1057_1801_14fb_0622 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0810 = + {0x14fb, 0x0810, pci_subsys_1057_1801_14fb_0810, 0}; +#undef pci_ss_info_14fb_0810 +#define pci_ss_info_14fb_0810 pci_ss_info_1057_1801_14fb_0810 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4200 = + {0x175c, 0x4200, pci_subsys_1057_1801_175c_4200, 0}; +#undef pci_ss_info_175c_4200 +#define pci_ss_info_175c_4200 pci_ss_info_1057_1801_175c_4200 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4300 = + {0x175c, 0x4300, pci_subsys_1057_1801_175c_4300, 0}; +#undef pci_ss_info_175c_4300 +#define pci_ss_info_175c_4300 pci_ss_info_1057_1801_175c_4300 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4400 = + {0x175c, 0x4400, pci_subsys_1057_1801_175c_4400, 0}; +#undef pci_ss_info_175c_4400 +#define pci_ss_info_175c_4400 pci_ss_info_1057_1801_175c_4400 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0010 = + {0xecc0, 0x0010, pci_subsys_1057_1801_ecc0_0010, 0}; +#undef pci_ss_info_ecc0_0010 +#define pci_ss_info_ecc0_0010 pci_ss_info_1057_1801_ecc0_0010 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0020 = + {0xecc0, 0x0020, pci_subsys_1057_1801_ecc0_0020, 0}; +#undef pci_ss_info_ecc0_0020 +#define pci_ss_info_ecc0_0020 pci_ss_info_1057_1801_ecc0_0020 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0031 = + {0xecc0, 0x0031, pci_subsys_1057_1801_ecc0_0031, 0}; +#undef pci_ss_info_ecc0_0031 +#define pci_ss_info_ecc0_0031 pci_ss_info_1057_1801_ecc0_0031 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0040 = + {0xecc0, 0x0040, pci_subsys_1057_1801_ecc0_0040, 0}; +#undef pci_ss_info_ecc0_0040 +#define pci_ss_info_ecc0_0040 pci_ss_info_1057_1801_ecc0_0040 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0041 = + {0xecc0, 0x0041, pci_subsys_1057_1801_ecc0_0041, 0}; +#undef pci_ss_info_ecc0_0041 +#define pci_ss_info_ecc0_0041 pci_ss_info_1057_1801_ecc0_0041 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_1801_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_1801_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_1801_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_1801_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_1801_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_1801_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_1801_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_1801_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_1801_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_1801_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_3410_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_3410_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_3410_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_3410_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0060 = + {0xecc0, 0x0060, pci_subsys_1057_3410_ecc0_0060, 0}; +#undef pci_ss_info_ecc0_0060 +#define pci_ss_info_ecc0_0060 pci_ss_info_1057_3410_ecc0_0060 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_3410_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_3410_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_3410_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_3410_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_3410_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_3410_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0080 = + {0xecc0, 0x0080, pci_subsys_1057_3410_ecc0_0080, 0}; +#undef pci_ss_info_ecc0_0080 +#define pci_ss_info_ecc0_0080 pci_ss_info_1057_3410_ecc0_0080 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0081 = + {0xecc0, 0x0081, pci_subsys_1057_3410_ecc0_0081, 0}; +#undef pci_ss_info_ecc0_0081 +#define pci_ss_info_ecc0_0081 pci_ss_info_1057_3410_ecc0_0081 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0090 = + {0xecc0, 0x0090, pci_subsys_1057_3410_ecc0_0090, 0}; +#undef pci_ss_info_ecc0_0090 +#define pci_ss_info_ecc0_0090 pci_ss_info_1057_3410_ecc0_0090 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00a0 = + {0xecc0, 0x00a0, pci_subsys_1057_3410_ecc0_00a0, 0}; +#undef pci_ss_info_ecc0_00a0 +#define pci_ss_info_ecc0_00a0 pci_ss_info_1057_3410_ecc0_00a0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00b0 = + {0xecc0, 0x00b0, pci_subsys_1057_3410_ecc0_00b0, 0}; +#undef pci_ss_info_ecc0_00b0 +#define pci_ss_info_ecc0_00b0 pci_ss_info_1057_3410_ecc0_00b0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0100 = + {0xecc0, 0x0100, pci_subsys_1057_3410_ecc0_0100, 0}; +#undef pci_ss_info_ecc0_0100 +#define pci_ss_info_ecc0_0100 pci_ss_info_1057_3410_ecc0_0100 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +#endif +static const pciSubsystemInfo pci_ss_info_105a_3319_8086_3427 = + {0x8086, 0x3427, pci_subsys_105a_3319_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_105a_3319_8086_3427 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_3373_1043_80f5 = + {0x1043, 0x80f5, pci_subsys_105a_3373_1043_80f5, 0}; +#undef pci_ss_info_1043_80f5 +#define pci_ss_info_1043_80f5 pci_ss_info_105a_3373_1043_80f5 +static const pciSubsystemInfo pci_ss_info_105a_3373_1462_702e = + {0x1462, 0x702e, pci_subsys_105a_3373_1462_702e, 0}; +#undef pci_ss_info_1462_702e +#define pci_ss_info_1462_702e pci_ss_info_105a_3373_1462_702e +static const pciSubsystemInfo pci_ss_info_105a_3376_1043_809e = + {0x1043, 0x809e, pci_subsys_105a_3376_1043_809e, 0}; +#undef pci_ss_info_1043_809e +#define pci_ss_info_1043_809e pci_ss_info_105a_3376_1043_809e +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_4d69_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d69_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d69_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_1043_807e = + {0x1043, 0x807e, pci_subsys_105a_5275_1043_807e, 0}; +#undef pci_ss_info_1043_807e +#define pci_ss_info_1043_807e pci_ss_info_105a_5275_1043_807e +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_1275 = + {0x105a, 0x1275, pci_subsys_105a_5275_105a_1275, 0}; +#undef pci_ss_info_105a_1275 +#define pci_ss_info_105a_1275 pci_ss_info_105a_5275_105a_1275 +static const pciSubsystemInfo pci_ss_info_105a_5275_1458_b001 = + {0x1458, 0xb001, pci_subsys_105a_5275_1458_b001, 0}; +#undef pci_ss_info_1458_b001 +#define pci_ss_info_1458_b001 pci_ss_info_105a_5275_1458_b001 +static const pciSubsystemInfo pci_ss_info_105a_6268_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_6268_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_6268_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_5348_105d_0037 = + {0x105d, 0x0037, pci_subsys_105d_5348_105d_0037, 0}; +#undef pci_ss_info_105d_0037 +#define pci_ss_info_105d_0037 pci_ss_info_105d_5348_105d_0037 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0050 = + {0x1069, 0x0050, pci_subsys_1069_0050_1069_0050, 0}; +#undef pci_ss_info_1069_0050 +#define pci_ss_info_1069_0050 pci_ss_info_1069_0050_1069_0050 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0052 = + {0x1069, 0x0052, pci_subsys_1069_0050_1069_0052, 0}; +#undef pci_ss_info_1069_0052 +#define pci_ss_info_1069_0052 pci_ss_info_1069_0050_1069_0052 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0054 = + {0x1069, 0x0054, pci_subsys_1069_0050_1069_0054, 0}; +#undef pci_ss_info_1069_0054 +#define pci_ss_info_1069_0054 pci_ss_info_1069_0050_1069_0054 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0242 = + {0x1014, 0x0242, pci_subsys_1069_b166_1014_0242, 0}; +#undef pci_ss_info_1014_0242 +#define pci_ss_info_1014_0242 pci_ss_info_1069_b166_1014_0242 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0266 = + {0x1014, 0x0266, pci_subsys_1069_b166_1014_0266, 0}; +#undef pci_ss_info_1014_0266 +#define pci_ss_info_1014_0266 pci_ss_info_1069_b166_1014_0266 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0278 = + {0x1014, 0x0278, pci_subsys_1069_b166_1014_0278, 0}; +#undef pci_ss_info_1014_0278 +#define pci_ss_info_1014_0278 pci_ss_info_1069_b166_1014_0278 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d3 = + {0x1014, 0x02d3, pci_subsys_1069_b166_1014_02d3, 0}; +#undef pci_ss_info_1014_02d3 +#define pci_ss_info_1014_02d3 pci_ss_info_1069_b166_1014_02d3 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d4 = + {0x1014, 0x02d4, pci_subsys_1069_b166_1014_02d4, 0}; +#undef pci_ss_info_1014_02d4 +#define pci_ss_info_1014_02d4 pci_ss_info_1069_b166_1014_02d4 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0200 = + {0x1069, 0x0200, pci_subsys_1069_b166_1069_0200, 0}; +#undef pci_ss_info_1069_0200 +#define pci_ss_info_1069_0200 pci_ss_info_1069_b166_1069_0200 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0202 = + {0x1069, 0x0202, pci_subsys_1069_b166_1069_0202, 0}; +#undef pci_ss_info_1069_0202 +#define pci_ss_info_1069_0202 pci_ss_info_1069_b166_1069_0202 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0204 = + {0x1069, 0x0204, pci_subsys_1069_b166_1069_0204, 0}; +#undef pci_ss_info_1069_0204 +#define pci_ss_info_1069_0204 pci_ss_info_1069_b166_1069_0204 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0206 = + {0x1069, 0x0206, pci_subsys_1069_b166_1069_0206, 0}; +#undef pci_ss_info_1069_0206 +#define pci_ss_info_1069_0206 pci_ss_info_1069_b166_1069_0206 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0030 = + {0x1069, 0x0030, pci_subsys_1069_ba56_1069_0030, 0}; +#undef pci_ss_info_1069_0030 +#define pci_ss_info_1069_0030 pci_ss_info_1069_ba56_1069_0030 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0040 = + {0x1069, 0x0040, pci_subsys_1069_ba56_1069_0040, 0}; +#undef pci_ss_info_1069_0040 +#define pci_ss_info_1069_0040 pci_ss_info_1069_ba56_1069_0040 +static const pciSubsystemInfo pci_ss_info_1069_ba57_1069_0072 = + {0x1069, 0x0072, pci_subsys_1069_ba57_1069_0072, 0}; +#undef pci_ss_info_1069_0072 +#define pci_ss_info_1069_0072 pci_ss_info_1069_ba57_1069_0072 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_106b_0031_106b_5811 = + {0x106b, 0x5811, pci_subsys_106b_0031_106b_5811, 0}; +#undef pci_ss_info_106b_5811 +#define pci_ss_info_106b_5811 pci_ss_info_106b_0031_106b_5811 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +static const pciSubsystemInfo pci_ss_info_1077_2200_1077_0002 = + {0x1077, 0x0002, pci_subsys_1077_2200_1077_0002, 0}; +#undef pci_ss_info_1077_0002 +#define pci_ss_info_1077_0002 pci_ss_info_1077_2200_1077_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +static const pciSubsystemInfo pci_ss_info_1095_0680_1095_3680 = + {0x1095, 0x3680, pci_subsys_1095_0680_1095_3680, 0}; +#undef pci_ss_info_1095_3680 +#define pci_ss_info_1095_3680 pci_ss_info_1095_0680_1095_3680 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_3112 = + {0x1095, 0x3112, pci_subsys_1095_3112_1095_3112, 0}; +#undef pci_ss_info_1095_3112 +#define pci_ss_info_1095_3112 pci_ss_info_1095_3112_1095_3112 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_6112 = + {0x1095, 0x6112, pci_subsys_1095_3112_1095_6112, 0}; +#undef pci_ss_info_1095_6112 +#define pci_ss_info_1095_6112 pci_ss_info_1095_3112_1095_6112 +static const pciSubsystemInfo pci_ss_info_1095_3112_9005_0250 = + {0x9005, 0x0250, pci_subsys_1095_3112_9005_0250, 0}; +#undef pci_ss_info_9005_0250 +#define pci_ss_info_9005_0250 pci_ss_info_1095_3112_9005_0250 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_3114 = + {0x1095, 0x3114, pci_subsys_1095_3114_1095_3114, 0}; +#undef pci_ss_info_1095_3114 +#define pci_ss_info_1095_3114 pci_ss_info_1095_3114_1095_3114 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_6114 = + {0x1095, 0x6114, pci_subsys_1095_3114_1095_6114, 0}; +#undef pci_ss_info_1095_6114 +#define pci_ss_info_1095_6114 pci_ss_info_1095_3114_1095_6114 +static const pciSubsystemInfo pci_ss_info_1095_3124_1095_3124 = + {0x1095, 0x3124, pci_subsys_1095_3124_1095_3124, 0}; +#undef pci_ss_info_1095_3124 +#define pci_ss_info_1095_3124 pci_ss_info_1095_3124_1095_3124 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_3512 = + {0x1095, 0x3512, pci_subsys_1095_3512_1095_3512, 0}; +#undef pci_ss_info_1095_3512 +#define pci_ss_info_1095_3512 pci_ss_info_1095_3512_1095_3512 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_6512 = + {0x1095, 0x6512, pci_subsys_1095_3512_1095_6512, 0}; +#undef pci_ss_info_1095_6512 +#define pci_ss_info_1095_6512 pci_ss_info_1095_3512_1095_6512 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_036e_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_036e_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_036e_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_036e_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0003 = + {0x1461, 0x0003, pci_subsys_109e_036e_1461_0003, 0}; +#undef pci_ss_info_1461_0003 +#define pci_ss_info_1461_0003 pci_ss_info_109e_036e_1461_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_036e_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_036e_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_036e_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_036e_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_036e_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_036e_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_036e_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_036e_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_036e_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_0878_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_0878_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_0878_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_0878_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_0878_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_0878_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_0878_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_0878_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_0878_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_0878_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_0878_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_0878_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_0878_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10a9_0009_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_10a9_0009_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_10a9_0009_10a9_8002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_6540_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6540_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6540_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6541_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6541_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6541_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6542_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6542_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6542_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2862 = + {0x10b5, 0x2862, pci_subsys_10b5_9030_10b5_2862, 0}; +#undef pci_ss_info_10b5_2862 +#define pci_ss_info_10b5_2862 pci_ss_info_10b5_9030_10b5_2862 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2906 = + {0x10b5, 0x2906, pci_subsys_10b5_9030_10b5_2906, 0}; +#undef pci_ss_info_10b5_2906 +#define pci_ss_info_10b5_2906 pci_ss_info_10b5_9030_10b5_2906 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2940 = + {0x10b5, 0x2940, pci_subsys_10b5_9030_10b5_2940, 0}; +#undef pci_ss_info_10b5_2940 +#define pci_ss_info_10b5_2940 pci_ss_info_10b5_9030_10b5_2940 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2977 = + {0x10b5, 0x2977, pci_subsys_10b5_9030_10b5_2977, 0}; +#undef pci_ss_info_10b5_2977 +#define pci_ss_info_10b5_2977 pci_ss_info_10b5_9030_10b5_2977 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2978 = + {0x10b5, 0x2978, pci_subsys_10b5_9030_10b5_2978, 0}; +#undef pci_ss_info_10b5_2978 +#define pci_ss_info_10b5_2978 pci_ss_info_10b5_9030_10b5_2978 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3025 = + {0x10b5, 0x3025, pci_subsys_10b5_9030_10b5_3025, 0}; +#undef pci_ss_info_10b5_3025 +#define pci_ss_info_10b5_3025 pci_ss_info_10b5_9030_10b5_3025 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3068 = + {0x10b5, 0x3068, pci_subsys_10b5_9030_10b5_3068, 0}; +#undef pci_ss_info_10b5_3068 +#define pci_ss_info_10b5_3068 pci_ss_info_10b5_9030_10b5_3068 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3136 = + {0x1397, 0x3136, pci_subsys_10b5_9030_1397_3136, 0}; +#undef pci_ss_info_1397_3136 +#define pci_ss_info_1397_3136 pci_ss_info_10b5_9030_1397_3136 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3137 = + {0x1397, 0x3137, pci_subsys_10b5_9030_1397_3137, 0}; +#undef pci_ss_info_1397_3137 +#define pci_ss_info_1397_3137 pci_ss_info_10b5_9030_1397_3137 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1518_0200 = + {0x1518, 0x0200, pci_subsys_10b5_9030_1518_0200, 0}; +#undef pci_ss_info_1518_0200 +#define pci_ss_info_1518_0200 pci_ss_info_10b5_9030_1518_0200 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1067 = + {0x10b5, 0x1067, pci_subsys_10b5_9050_10b5_1067, 0}; +#undef pci_ss_info_10b5_1067 +#define pci_ss_info_10b5_1067 pci_ss_info_10b5_9050_10b5_1067 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1172 = + {0x10b5, 0x1172, pci_subsys_10b5_9050_10b5_1172, 0}; +#undef pci_ss_info_10b5_1172 +#define pci_ss_info_10b5_1172 pci_ss_info_10b5_9050_10b5_1172 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2221 = + {0x10b5, 0x2221, pci_subsys_10b5_9050_10b5_2221, 0}; +#undef pci_ss_info_10b5_2221 +#define pci_ss_info_10b5_2221 pci_ss_info_10b5_9050_10b5_2221 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2431 = + {0x10b5, 0x2431, pci_subsys_10b5_9050_10b5_2431, 0}; +#undef pci_ss_info_10b5_2431 +#define pci_ss_info_10b5_2431 pci_ss_info_10b5_9050_10b5_2431 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2905 = + {0x10b5, 0x2905, pci_subsys_10b5_9050_10b5_2905, 0}; +#undef pci_ss_info_10b5_2905 +#define pci_ss_info_10b5_2905 pci_ss_info_10b5_9050_10b5_2905 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1498_0362 = + {0x1498, 0x0362, pci_subsys_10b5_9050_1498_0362, 0}; +#undef pci_ss_info_1498_0362 +#define pci_ss_info_1498_0362 pci_ss_info_10b5_9050_1498_0362 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_2036 = + {0x5654, 0x2036, pci_subsys_10b5_9050_5654_2036, 0}; +#undef pci_ss_info_5654_2036 +#define pci_ss_info_5654_2036 pci_ss_info_10b5_9050_5654_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_3132 = + {0x5654, 0x3132, pci_subsys_10b5_9050_5654_3132, 0}; +#undef pci_ss_info_5654_3132 +#define pci_ss_info_5654_3132 pci_ss_info_10b5_9050_5654_3132 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2696 = + {0x10b5, 0x2696, pci_subsys_10b5_9054_10b5_2696, 0}; +#undef pci_ss_info_10b5_2696 +#define pci_ss_info_10b5_2696 pci_ss_info_10b5_9054_10b5_2696 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2717 = + {0x10b5, 0x2717, pci_subsys_10b5_9054_10b5_2717, 0}; +#undef pci_ss_info_10b5_2717 +#define pci_ss_info_10b5_2717 pci_ss_info_10b5_9054_10b5_2717 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2844 = + {0x10b5, 0x2844, pci_subsys_10b5_9054_10b5_2844, 0}; +#undef pci_ss_info_10b5_2844 +#define pci_ss_info_10b5_2844 pci_ss_info_10b5_9054_10b5_2844 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12c7_4001 = + {0x12c7, 0x4001, pci_subsys_10b5_9054_12c7_4001, 0}; +#undef pci_ss_info_12c7_4001 +#define pci_ss_info_12c7_4001 pci_ss_info_10b5_9054_12c7_4001 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9054_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9054_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0011 = + {0x16df, 0x0011, pci_subsys_10b5_9054_16df_0011, 0}; +#undef pci_ss_info_16df_0011 +#define pci_ss_info_16df_0011 pci_ss_info_10b5_9054_16df_0011 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0012 = + {0x16df, 0x0012, pci_subsys_10b5_9054_16df_0012, 0}; +#undef pci_ss_info_16df_0012 +#define pci_ss_info_16df_0012 pci_ss_info_10b5_9054_16df_0012 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0013 = + {0x16df, 0x0013, pci_subsys_10b5_9054_16df_0013, 0}; +#undef pci_ss_info_16df_0013 +#define pci_ss_info_16df_0013 pci_ss_info_10b5_9054_16df_0013 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0014 = + {0x16df, 0x0014, pci_subsys_10b5_9054_16df_0014, 0}; +#undef pci_ss_info_16df_0014 +#define pci_ss_info_16df_0014 pci_ss_info_10b5_9054_16df_0014 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0015 = + {0x16df, 0x0015, pci_subsys_10b5_9054_16df_0015, 0}; +#undef pci_ss_info_16df_0015 +#define pci_ss_info_16df_0015 pci_ss_info_10b5_9054_16df_0015 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0016 = + {0x16df, 0x0016, pci_subsys_10b5_9054_16df_0016, 0}; +#undef pci_ss_info_16df_0016 +#define pci_ss_info_16df_0016 pci_ss_info_10b5_9054_16df_0016 +static const pciSubsystemInfo pci_ss_info_10b5_9056_10b5_2979 = + {0x10b5, 0x2979, pci_subsys_10b5_9056_10b5_2979, 0}; +#undef pci_ss_info_10b5_2979 +#define pci_ss_info_10b5_2979 pci_ss_info_10b5_9056_10b5_2979 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10eb = + {0x103c, 0x10eb, pci_subsys_10b5_9080_103c_10eb, 0}; +#undef pci_ss_info_103c_10eb +#define pci_ss_info_103c_10eb pci_ss_info_10b5_9080_103c_10eb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10ec = + {0x103c, 0x10ec, pci_subsys_10b5_9080_103c_10ec, 0}; +#undef pci_ss_info_103c_10ec +#define pci_ss_info_103c_10ec pci_ss_info_10b5_9080_103c_10ec +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9080_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9080_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12df_4422 = + {0x12df, 0x4422, pci_subsys_10b5_9080_12df_4422, 0}; +#undef pci_ss_info_12df_4422 +#define pci_ss_info_12df_4422 pci_ss_info_10b5_9080_12df_4422 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_0013_10b7_2031 = + {0x10b7, 0x2031, pci_subsys_10b7_0013_10b7_2031, 0}; +#undef pci_ss_info_10b7_2031 +#define pci_ss_info_10b7_2031 pci_ss_info_10b7_0013_10b7_2031 +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_1700_1043_80eb = + {0x1043, 0x80eb, pci_subsys_10b7_1700_1043_80eb, 0}; +#undef pci_ss_info_1043_80eb +#define pci_ss_info_1043_80eb pci_ss_info_10b7_1700_1043_80eb +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0010 = + {0x10b7, 0x0010, pci_subsys_10b7_1700_10b7_0010, 0}; +#undef pci_ss_info_10b7_0010 +#define pci_ss_info_10b7_0010 pci_ss_info_10b7_1700_10b7_0010 +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0020 = + {0x10b7, 0x0020, pci_subsys_10b7_1700_10b7_0020, 0}; +#undef pci_ss_info_10b7_0020 +#define pci_ss_info_10b7_0020 pci_ss_info_10b7_1700_10b7_0020 +static const pciSubsystemInfo pci_ss_info_10b7_1700_147b_1407 = + {0x147b, 0x1407, pci_subsys_10b7_1700_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_10b7_1700_147b_1407 +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9200_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9200_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_00fe = + {0x1028, 0x00fe, pci_subsys_10b7_9200_1028_00fe, 0}; +#undef pci_ss_info_1028_00fe +#define pci_ss_info_1028_00fe pci_ss_info_10b7_9200_1028_00fe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_012a = + {0x1028, 0x012a, pci_subsys_10b7_9200_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_10b7_9200_1028_012a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10f1_2466 = + {0x10f1, 0x2466, pci_subsys_10b7_9200_10f1_2466, 0}; +#undef pci_ss_info_10f1_2466 +#define pci_ss_info_10f1_2466 pci_ss_info_10b7_9200_10f1_2466 +static const pciSubsystemInfo pci_ss_info_10b7_9201_1043_80ab = + {0x1043, 0x80ab, pci_subsys_10b7_9201_1043_80ab, 0}; +#undef pci_ss_info_1043_80ab +#define pci_ss_info_1043_80ab pci_ss_info_10b7_9201_1043_80ab +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_1014_053b = + {0x1014, 0x053b, pci_subsys_10b9_1533_1014_053b, 0}; +#undef pci_ss_info_1014_053b +#define pci_ss_info_1014_053b pci_ss_info_10b9_1533_1014_053b +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_050f = + {0x1014, 0x050f, pci_subsys_10b9_5229_1014_050f, 0}; +#undef pci_ss_info_1014_050f +#define pci_ss_info_1014_050f pci_ss_info_10b9_5229_1014_050f +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_053d = + {0x1014, 0x053d, pci_subsys_10b9_5229_1014_053d, 0}; +#undef pci_ss_info_1014_053d +#define pci_ss_info_1014_053d pci_ss_info_10b9_5229_1014_053d +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5229_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5229_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5229_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5237_1014_0540 = + {0x1014, 0x0540, pci_subsys_10b9_5237_1014_0540, 0}; +#undef pci_ss_info_1014_0540 +#define pci_ss_info_1014_0540 pci_ss_info_10b9_5237_1014_0540 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5237_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5237_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_104d_810f = + {0x104d, 0x810f, pci_subsys_10b9_5237_104d_810f, 0}; +#undef pci_ss_info_104d_810f +#define pci_ss_info_104d_810f pci_ss_info_10b9_5237_104d_810f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_053e = + {0x1014, 0x053e, pci_subsys_10b9_5451_1014_053e, 0}; +#undef pci_ss_info_1014_053e +#define pci_ss_info_1014_053e pci_ss_info_10b9_5451_1014_053e +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5451_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5451_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5451_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_10b9_5451 = + {0x10b9, 0x5451, pci_subsys_10b9_5451_10b9_5451, 0}; +#undef pci_ss_info_10b9_5451 +#define pci_ss_info_10b9_5451 pci_ss_info_10b9_5451_10b9_5451 +static const pciSubsystemInfo pci_ss_info_10b9_5457_1014_0535 = + {0x1014, 0x0535, pci_subsys_10b9_5457_1014_0535, 0}; +#undef pci_ss_info_1014_0535 +#define pci_ss_info_1014_0535 pci_ss_info_10b9_5457_1014_0535 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5457_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5457_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5457_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_0510 = + {0x1014, 0x0510, pci_subsys_10b9_7101_1014_0510, 0}; +#undef pci_ss_info_1014_0510 +#define pci_ss_info_1014_0510 pci_ss_info_10b9_7101_1014_0510 +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_053c = + {0x1014, 0x053c, pci_subsys_10b9_7101_1014_053c, 0}; +#undef pci_ss_info_1014_053c +#define pci_ss_info_1014_053c pci_ss_info_10b9_7101_1014_053c +#endif +static const pciSubsystemInfo pci_ss_info_10b9_7101_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_7101_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_7101_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_0005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_0005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_8005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_8005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c19 = + {0x1048, 0x0c19, pci_subsys_10de_0020_1048_0c19, 0}; +#undef pci_ss_info_1048_0c19 +#define pci_ss_info_1048_0c19 pci_ss_info_10de_0020_1048_0c19 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1c = + {0x1048, 0x0c1c, pci_subsys_10de_0020_1048_0c1c, 0}; +#undef pci_ss_info_1048_0c1c +#define pci_ss_info_1048_0c1c pci_ss_info_10de_0020_1048_0c1c +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_0028_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_0028_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c28 = + {0x1048, 0x0c28, pci_subsys_10de_0028_1048_0c28, 0}; +#undef pci_ss_info_1048_0c28 +#define pci_ss_info_1048_0c28 pci_ss_info_10de_0028_1048_0c28 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c29 = + {0x1048, 0x0c29, pci_subsys_10de_0028_1048_0c29, 0}; +#undef pci_ss_info_1048_0c29 +#define pci_ss_info_1048_0c29 pci_ss_info_10de_0028_1048_0c29 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2a = + {0x1048, 0x0c2a, pci_subsys_10de_0028_1048_0c2a, 0}; +#undef pci_ss_info_1048_0c2a +#define pci_ss_info_1048_0c2a pci_ss_info_10de_0028_1048_0c2a +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2b = + {0x1048, 0x0c2b, pci_subsys_10de_0028_1048_0c2b, 0}; +#undef pci_ss_info_1048_0c2b +#define pci_ss_info_1048_0c2b pci_ss_info_10de_0028_1048_0c2b +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c31 = + {0x1048, 0x0c31, pci_subsys_10de_0028_1048_0c31, 0}; +#undef pci_ss_info_1048_0c31 +#define pci_ss_info_1048_0c31 pci_ss_info_10de_0028_1048_0c31 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c32 = + {0x1048, 0x0c32, pci_subsys_10de_0028_1048_0c32, 0}; +#undef pci_ss_info_1048_0c32 +#define pci_ss_info_1048_0c32 pci_ss_info_10de_0028_1048_0c32 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c33 = + {0x1048, 0x0c33, pci_subsys_10de_0028_1048_0c33, 0}; +#undef pci_ss_info_1048_0c33 +#define pci_ss_info_1048_0c33 pci_ss_info_10de_0028_1048_0c33 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c34 = + {0x1048, 0x0c34, pci_subsys_10de_0028_1048_0c34, 0}; +#undef pci_ss_info_1048_0c34 +#define pci_ss_info_1048_0c34 pci_ss_info_10de_0028_1048_0c34 +static const pciSubsystemInfo pci_ss_info_10de_0028_107d_2134 = + {0x107d, 0x2134, pci_subsys_10de_0028_107d_2134, 0}; +#undef pci_ss_info_107d_2134 +#define pci_ss_info_107d_2134 pci_ss_info_10de_0028_107d_2134 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2e = + {0x1048, 0x0c2e, pci_subsys_10de_0029_1048_0c2e, 0}; +#undef pci_ss_info_1048_0c2e +#define pci_ss_info_1048_0c2e pci_ss_info_10de_0029_1048_0c2e +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2f = + {0x1048, 0x0c2f, pci_subsys_10de_0029_1048_0c2f, 0}; +#undef pci_ss_info_1048_0c2f +#define pci_ss_info_1048_0c2f pci_ss_info_10de_0029_1048_0c2f +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c30 = + {0x1048, 0x0c30, pci_subsys_10de_0029_1048_0c30, 0}; +#undef pci_ss_info_1048_0c30 +#define pci_ss_info_1048_0c30 pci_ss_info_10de_0029_1048_0c30 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c20 = + {0x1048, 0x0c20, pci_subsys_10de_002c_1048_0c20, 0}; +#undef pci_ss_info_1048_0c20 +#define pci_ss_info_1048_0c20 pci_ss_info_10de_002c_1048_0c20 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_002c_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_002c_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3b = + {0x1048, 0x0c3b, pci_subsys_10de_002d_1048_0c3b, 0}; +#undef pci_ss_info_1048_0c3b +#define pci_ss_info_1048_0c3b pci_ss_info_10de_002d_1048_0c3b +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_002d_1569_002d = + {0x1569, 0x002d, pci_subsys_10de_002d_1569_002d, 0}; +#undef pci_ss_info_1569_002d +#define pci_ss_info_1569_002d pci_ss_info_10de_002d_1569_002d +static const pciSubsystemInfo pci_ss_info_10de_0041_1043_817b = + {0x1043, 0x817b, pci_subsys_10de_0041_1043_817b, 0}; +#undef pci_ss_info_1043_817b +#define pci_ss_info_1043_817b pci_ss_info_10de_0041_1043_817b +static const pciSubsystemInfo pci_ss_info_10de_0050_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0050_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0050_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0050_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0050_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0050_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0050_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0050_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0050_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0052_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0052_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0052_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0052_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0052_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0052_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0052_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0052_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0052_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0053_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0053_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0053_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0053_1458_5002 = + {0x1458, 0x5002, pci_subsys_10de_0053_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_10de_0053_1458_5002 +static const pciSubsystemInfo pci_ss_info_10de_0053_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0053_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0053_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0054_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0054_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0054_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0055_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0055_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0055_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0057_1043_8141 = + {0x1043, 0x8141, pci_subsys_10de_0057_1043_8141, 0}; +#undef pci_ss_info_1043_8141 +#define pci_ss_info_1043_8141 pci_ss_info_10de_0057_1043_8141 +static const pciSubsystemInfo pci_ss_info_10de_0057_1458_e000 = + {0x1458, 0xe000, pci_subsys_10de_0057_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10de_0057_1458_e000 +static const pciSubsystemInfo pci_ss_info_10de_0057_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0057_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0057_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0059_1043_812a = + {0x1043, 0x812a, pci_subsys_10de_0059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_10de_0059_1043_812a +static const pciSubsystemInfo pci_ss_info_10de_005a_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005a_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005a_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005a_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005a_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005a_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005a_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005a_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005a_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005b_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005b_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005b_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005b_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005b_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005b_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005b_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005b_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005b_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005e_1458_5000 = + {0x1458, 0x5000, pci_subsys_10de_005e_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_10de_005e_1458_5000 +static const pciSubsystemInfo pci_ss_info_10de_005e_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005e_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005e_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0066_1043_80a7 = + {0x1043, 0x80a7, pci_subsys_10de_0066_1043_80a7, 0}; +#undef pci_ss_info_1043_80a7 +#define pci_ss_info_1043_80a7 pci_ss_info_10de_0066_1043_80a7 +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_006b_10de_006b = + {0x10de, 0x006b, pci_subsys_10de_006b_10de_006b, 0}; +#undef pci_ss_info_10de_006b +#define pci_ss_info_10de_006b pci_ss_info_10de_006b_10de_006b +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_00df_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00df_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00df_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e0_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e0_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e0_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e1_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e1_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e1_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e3_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e3_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e3_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e4_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e4_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e4_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e5_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e5_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e5_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e7_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e7_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e7_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e8_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e8_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e8_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00ea_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00ea_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00ea_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00f1_1043_81a6 = + {0x1043, 0x81a6, pci_subsys_10de_00f1_1043_81a6, 0}; +#undef pci_ss_info_1043_81a6 +#define pci_ss_info_1043_81a6 pci_ss_info_10de_00f1_1043_81a6 +static const pciSubsystemInfo pci_ss_info_10de_00f2_1682_211c = + {0x1682, 0x211c, pci_subsys_10de_00f2_1682_211c, 0}; +#undef pci_ss_info_1682_211c +#define pci_ss_info_1682_211c pci_ss_info_10de_00f2_1682_211c +static const pciSubsystemInfo pci_ss_info_10de_00f9_1682_2120 = + {0x1682, 0x2120, pci_subsys_10de_00f9_1682_2120, 0}; +#undef pci_ss_info_1682_2120 +#define pci_ss_info_1682_2120 pci_ss_info_10de_00f9_1682_2120 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c41 = + {0x1048, 0x0c41, pci_subsys_10de_0100_1048_0c41, 0}; +#undef pci_ss_info_1048_0c41 +#define pci_ss_info_1048_0c41 pci_ss_info_10de_0100_1048_0c41 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c43 = + {0x1048, 0x0c43, pci_subsys_10de_0100_1048_0c43, 0}; +#undef pci_ss_info_1048_0c43 +#define pci_ss_info_1048_0c43 pci_ss_info_10de_0100_1048_0c43 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c48 = + {0x1048, 0x0c48, pci_subsys_10de_0100_1048_0c48, 0}; +#undef pci_ss_info_1048_0c48 +#define pci_ss_info_1048_0c48 pci_ss_info_10de_0100_1048_0c48 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1048_0c42 = + {0x1048, 0x0c42, pci_subsys_10de_0101_1048_0c42, 0}; +#undef pci_ss_info_1048_0c42 +#define pci_ss_info_1048_0c42 pci_ss_info_10de_0101_1048_0c42 +static const pciSubsystemInfo pci_ss_info_10de_0101_107d_2822 = + {0x107d, 0x2822, pci_subsys_10de_0101_107d_2822, 0}; +#undef pci_ss_info_107d_2822 +#define pci_ss_info_107d_2822 pci_ss_info_10de_0101_107d_2822 +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c40 = + {0x1048, 0x0c40, pci_subsys_10de_0103_1048_0c40, 0}; +#undef pci_ss_info_1048_0c40 +#define pci_ss_info_1048_0c40 pci_ss_info_10de_0103_1048_0c40 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c44 = + {0x1048, 0x0c44, pci_subsys_10de_0103_1048_0c44, 0}; +#undef pci_ss_info_1048_0c44 +#define pci_ss_info_1048_0c44 pci_ss_info_10de_0103_1048_0c44 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c45 = + {0x1048, 0x0c45, pci_subsys_10de_0103_1048_0c45, 0}; +#undef pci_ss_info_1048_0c45 +#define pci_ss_info_1048_0c45 pci_ss_info_10de_0103_1048_0c45 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4a = + {0x1048, 0x0c4a, pci_subsys_10de_0103_1048_0c4a, 0}; +#undef pci_ss_info_1048_0c4a +#define pci_ss_info_1048_0c4a pci_ss_info_10de_0103_1048_0c4a +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4b = + {0x1048, 0x0c4b, pci_subsys_10de_0103_1048_0c4b, 0}; +#undef pci_ss_info_1048_0c4b +#define pci_ss_info_1048_0c4b pci_ss_info_10de_0103_1048_0c4b +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c60 = + {0x1048, 0x0c60, pci_subsys_10de_0110_1048_0c60, 0}; +#undef pci_ss_info_1048_0c60 +#define pci_ss_info_1048_0c60 pci_ss_info_10de_0110_1048_0c60 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c61 = + {0x1048, 0x0c61, pci_subsys_10de_0110_1048_0c61, 0}; +#undef pci_ss_info_1048_0c61 +#define pci_ss_info_1048_0c61 pci_ss_info_10de_0110_1048_0c61 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c63 = + {0x1048, 0x0c63, pci_subsys_10de_0110_1048_0c63, 0}; +#undef pci_ss_info_1048_0c63 +#define pci_ss_info_1048_0c63 pci_ss_info_10de_0110_1048_0c63 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c64 = + {0x1048, 0x0c64, pci_subsys_10de_0110_1048_0c64, 0}; +#undef pci_ss_info_1048_0c64 +#define pci_ss_info_1048_0c64 pci_ss_info_10de_0110_1048_0c64 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c65 = + {0x1048, 0x0c65, pci_subsys_10de_0110_1048_0c65, 0}; +#undef pci_ss_info_1048_0c65 +#define pci_ss_info_1048_0c65 pci_ss_info_10de_0110_1048_0c65 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c66 = + {0x1048, 0x0c66, pci_subsys_10de_0110_1048_0c66, 0}; +#undef pci_ss_info_1048_0c66 +#define pci_ss_info_1048_0c66 pci_ss_info_10de_0110_1048_0c66 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_0091 = + {0x10de, 0x0091, pci_subsys_10de_0110_10de_0091, 0}; +#undef pci_ss_info_10de_0091 +#define pci_ss_info_10de_0091 pci_ss_info_10de_0110_10de_0091 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_00a1 = + {0x10de, 0x00a1, pci_subsys_10de_0110_10de_00a1, 0}; +#undef pci_ss_info_10de_00a1 +#define pci_ss_info_10de_00a1 pci_ss_info_10de_0110_10de_00a1 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0141_1458_3124 = + {0x1458, 0x3124, pci_subsys_10de_0141_1458_3124, 0}; +#undef pci_ss_info_1458_3124 +#define pci_ss_info_1458_3124 pci_ss_info_10de_0141_1458_3124 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c50 = + {0x1048, 0x0c50, pci_subsys_10de_0150_1048_0c50, 0}; +#undef pci_ss_info_1048_0c50 +#define pci_ss_info_1048_0c50 pci_ss_info_10de_0150_1048_0c50 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c52 = + {0x1048, 0x0c52, pci_subsys_10de_0150_1048_0c52, 0}; +#undef pci_ss_info_1048_0c52 +#define pci_ss_info_1048_0c52 pci_ss_info_10de_0150_1048_0c52 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2842 = + {0x107d, 0x2842, pci_subsys_10de_0150_107d_2842, 0}; +#undef pci_ss_info_107d_2842 +#define pci_ss_info_107d_2842 pci_ss_info_10de_0150_107d_2842 +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0151_1462_5506 = + {0x1462, 0x5506, pci_subsys_10de_0151_1462_5506, 0}; +#undef pci_ss_info_1462_5506 +#define pci_ss_info_1462_5506 pci_ss_info_10de_0151_1462_5506 +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_10b0_0002 = + {0x10b0, 0x0002, pci_subsys_10de_0171_10b0_0002, 0}; +#undef pci_ss_info_10b0_0002 +#define pci_ss_info_10b0_0002 pci_ss_info_10de_0171_10b0_0002 +static const pciSubsystemInfo pci_ss_info_10de_0171_10de_0008 = + {0x10de, 0x0008, pci_subsys_10de_0171_10de_0008, 0}; +#undef pci_ss_info_10de_0008 +#define pci_ss_info_10de_0008 pci_ss_info_10de_0171_10de_0008 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8852 = + {0x1462, 0x8852, pci_subsys_10de_0171_1462_8852, 0}; +#undef pci_ss_info_1462_8852 +#define pci_ss_info_1462_8852 pci_ss_info_10de_0171_1462_8852 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0176_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_10de_0176_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_10de_0176_4c53_1090 +static const pciSubsystemInfo pci_ss_info_10de_0179_10de_0179 = + {0x10de, 0x0179, pci_subsys_10de_0179_10de_0179, 0}; +#undef pci_ss_info_10de_0179 +#define pci_ss_info_10de_0179 pci_ss_info_10de_0179_10de_0179 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_806f = + {0x1043, 0x806f, pci_subsys_10de_0181_1043_806f, 0}; +#undef pci_ss_info_1043_806f +#define pci_ss_info_1043_806f pci_ss_info_10de_0181_1043_806f +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8880 = + {0x1462, 0x8880, pci_subsys_10de_0181_1462_8880, 0}; +#undef pci_ss_info_1462_8880 +#define pci_ss_info_1462_8880 pci_ss_info_10de_0181_1462_8880 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8900 = + {0x1462, 0x8900, pci_subsys_10de_0181_1462_8900, 0}; +#undef pci_ss_info_1462_8900 +#define pci_ss_info_1462_8900 pci_ss_info_10de_0181_1462_8900 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_9350 = + {0x1462, 0x9350, pci_subsys_10de_0181_1462_9350, 0}; +#undef pci_ss_info_1462_9350 +#define pci_ss_info_1462_9350 pci_ss_info_10de_0181_1462_9350 +static const pciSubsystemInfo pci_ss_info_10de_0181_147b_8f0d = + {0x147b, 0x8f0d, pci_subsys_10de_0181_147b_8f0d, 0}; +#undef pci_ss_info_147b_8f0d +#define pci_ss_info_147b_8f0d pci_ss_info_10de_0181_147b_8f0d +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0200_1048_0c70 = + {0x1048, 0x0c70, pci_subsys_10de_0200_1048_0c70, 0}; +#undef pci_ss_info_1048_0c70 +#define pci_ss_info_1048_0c70 pci_ss_info_10de_0200_1048_0c70 +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0251_1043_8023 = + {0x1043, 0x8023, pci_subsys_10de_0251_1043_8023, 0}; +#undef pci_ss_info_1043_8023 +#define pci_ss_info_1043_8023 pci_ss_info_10de_0251_1043_8023 +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +static const pciSubsystemInfo pci_ss_info_10de_0314_1043_814a = + {0x1043, 0x814a, pci_subsys_10de_0314_1043_814a, 0}; +#undef pci_ss_info_1043_814a +#define pci_ss_info_1043_814a pci_ss_info_10de_0314_1043_814a +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9171 = + {0x1462, 0x9171, pci_subsys_10de_0322_1462_9171, 0}; +#undef pci_ss_info_1462_9171 +#define pci_ss_info_1462_9171 pci_ss_info_10de_0322_1462_9171 +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9360 = + {0x1462, 0x9360, pci_subsys_10de_0322_1462_9360, 0}; +#undef pci_ss_info_1462_9360 +#define pci_ss_info_1462_9360 pci_ss_info_10de_0322_1462_9360 +static const pciSubsystemInfo pci_ss_info_10de_0324_1028_0196 = + {0x1028, 0x0196, pci_subsys_10de_0324_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_10de_0324_1028_0196 +static const pciSubsystemInfo pci_ss_info_10de_0324_1071_8160 = + {0x1071, 0x8160, pci_subsys_10de_0324_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10de_0324_1071_8160 +static const pciSubsystemInfo pci_ss_info_10de_0331_1043_8145 = + {0x1043, 0x8145, pci_subsys_10de_0331_1043_8145, 0}; +#undef pci_ss_info_1043_8145 +#define pci_ss_info_1043_8145 pci_ss_info_10de_0331_1043_8145 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +static const pciSubsystemInfo pci_ss_info_10ec_8139_0357_000a = + {0x0357, 0x000a, pci_subsys_10ec_8139_0357_000a, 0}; +#undef pci_ss_info_0357_000a +#define pci_ss_info_0357_000a pci_ss_info_10ec_8139_0357_000a +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_005a = + {0x1025, 0x005a, pci_subsys_10ec_8139_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_10ec_8139_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_1043_8109 = + {0x1043, 0x8109, pci_subsys_10ec_8139_1043_8109, 0}; +#undef pci_ss_info_1043_8109 +#define pci_ss_info_1043_8109 pci_ss_info_10ec_8139_1043_8109 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1071_8160 = + {0x1071, 0x8160, pci_subsys_10ec_8139_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10ec_8139_1071_8160 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1113_ec01 = + {0x1113, 0xec01, pci_subsys_10ec_8139_1113_ec01, 0}; +#undef pci_ss_info_1113_ec01 +#define pci_ss_info_1113_ec01 pci_ss_info_10ec_8139_1113_ec01 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8139_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8139_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_14cb_0200 = + {0x14cb, 0x0200, pci_subsys_10ec_8139_14cb_0200, 0}; +#undef pci_ss_info_14cb_0200 +#define pci_ss_info_14cb_0200 pci_ss_info_10ec_8139_14cb_0200 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1799_5000 = + {0x1799, 0x5000, pci_subsys_10ec_8139_1799_5000, 0}; +#undef pci_ss_info_1799_5000 +#define pci_ss_info_1799_5000 pci_ss_info_10ec_8139_1799_5000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_9001_1695 = + {0x9001, 0x1695, pci_subsys_10ec_8139_9001_1695, 0}; +#undef pci_ss_info_9001_1695 +#define pci_ss_info_9001_1695 pci_ss_info_10ec_8139_9001_1695 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1259_c107 = + {0x1259, 0xc107, pci_subsys_10ec_8169_1259_c107, 0}; +#undef pci_ss_info_1259_c107 +#define pci_ss_info_1259_c107 pci_ss_info_10ec_8169_1259_c107 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +static const pciSubsystemInfo pci_ss_info_10ec_8169_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8169_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8169_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1462_702c = + {0x1462, 0x702c, pci_subsys_10ec_8169_1462_702c, 0}; +#undef pci_ss_info_1462_702c +#define pci_ss_info_1462_702c pci_ss_info_10ec_8169_1462_702c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8064 = + {0x1102, 0x8064, pci_subsys_1102_0002_1102_8064, 0}; +#undef pci_ss_info_1102_8064 +#define pci_ss_info_1102_8064 pci_ss_info_1102_0002_1102_8064 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8065 = + {0x1102, 0x8065, pci_subsys_1102_0002_1102_8065, 0}; +#undef pci_ss_info_1102_8065 +#define pci_ss_info_1102_8065 pci_ss_info_1102_0002_1102_8065 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8067 = + {0x1102, 0x8067, pci_subsys_1102_0002_1102_8067, 0}; +#undef pci_ss_info_1102_8067 +#define pci_ss_info_1102_8067 pci_ss_info_1102_0002_1102_8067 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0058 = + {0x1102, 0x0058, pci_subsys_1102_0004_1102_0058, 0}; +#undef pci_ss_info_1102_0058 +#define pci_ss_info_1102_0058 pci_ss_info_1102_0004_1102_0058 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_1007 = + {0x1102, 0x1007, pci_subsys_1102_0004_1102_1007, 0}; +#undef pci_ss_info_1102_1007 +#define pci_ss_info_1102_1007 pci_ss_info_1102_0004_1102_1007 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_2002 = + {0x1102, 0x2002, pci_subsys_1102_0004_1102_2002, 0}; +#undef pci_ss_info_1102_2002 +#define pci_ss_info_1102_2002 pci_ss_info_1102_0004_1102_2002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_0007 = + {0x1102, 0x0007, pci_subsys_1102_0007_1102_0007, 0}; +#undef pci_ss_info_1102_0007 +#define pci_ss_info_1102_0007 pci_ss_info_1102_0007_1102_0007 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_0007_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_0007_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_0007_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_0007_1102_1002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1006 = + {0x1102, 0x1006, pci_subsys_1102_0007_1102_1006, 0}; +#undef pci_ss_info_1102_1006 +#define pci_ss_info_1102_1006 pci_ss_info_1102_0007_1102_1006 +static const pciSubsystemInfo pci_ss_info_1102_0007_1462_1009 = + {0x1462, 0x1009, pci_subsys_1102_0007_1462_1009, 0}; +#undef pci_ss_info_1462_1009 +#define pci_ss_info_1462_1009 pci_ss_info_1102_0007_1462_1009 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_7005_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_7005_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_7005_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_7005_1102_1002 +#endif +static const pciSubsystemInfo pci_ss_info_1102_8938_1033_80e5 = + {0x1033, 0x80e5, pci_subsys_1102_8938_1033_80e5, 0}; +#undef pci_ss_info_1033_80e5 +#define pci_ss_info_1033_80e5 pci_ss_info_1102_8938_1033_80e5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_8938_1071_7150 = + {0x1071, 0x7150, pci_subsys_1102_8938_1071_7150, 0}; +#undef pci_ss_info_1071_7150 +#define pci_ss_info_1071_7150 pci_ss_info_1102_8938_1071_7150 +static const pciSubsystemInfo pci_ss_info_1102_8938_110a_5938 = + {0x110a, 0x5938, pci_subsys_1102_8938_110a_5938, 0}; +#undef pci_ss_info_110a_5938 +#define pci_ss_info_110a_5938 pci_ss_info_1102_8938_110a_5938 +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100c = + {0x13bd, 0x100c, pci_subsys_1102_8938_13bd_100c, 0}; +#undef pci_ss_info_13bd_100c +#define pci_ss_info_13bd_100c pci_ss_info_1102_8938_13bd_100c +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100d = + {0x13bd, 0x100d, pci_subsys_1102_8938_13bd_100d, 0}; +#undef pci_ss_info_13bd_100d +#define pci_ss_info_13bd_100d pci_ss_info_1102_8938_13bd_100d +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100e = + {0x13bd, 0x100e, pci_subsys_1102_8938_13bd_100e, 0}; +#undef pci_ss_info_13bd_100e +#define pci_ss_info_13bd_100e pci_ss_info_1102_8938_13bd_100e +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_f6f1 = + {0x13bd, 0xf6f1, pci_subsys_1102_8938_13bd_f6f1, 0}; +#undef pci_ss_info_13bd_f6f1 +#define pci_ss_info_13bd_f6f1 pci_ss_info_1102_8938_13bd_f6f1 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_0e70 = + {0x14ff, 0x0e70, pci_subsys_1102_8938_14ff_0e70, 0}; +#undef pci_ss_info_14ff_0e70 +#define pci_ss_info_14ff_0e70 pci_ss_info_1102_8938_14ff_0e70 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_c401 = + {0x14ff, 0xc401, pci_subsys_1102_8938_14ff_c401, 0}; +#undef pci_ss_info_14ff_c401 +#define pci_ss_info_14ff_c401 pci_ss_info_1102_8938_14ff_c401 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b400 = + {0x156d, 0xb400, pci_subsys_1102_8938_156d_b400, 0}; +#undef pci_ss_info_156d_b400 +#define pci_ss_info_156d_b400 pci_ss_info_1102_8938_156d_b400 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b550 = + {0x156d, 0xb550, pci_subsys_1102_8938_156d_b550, 0}; +#undef pci_ss_info_156d_b550 +#define pci_ss_info_156d_b550 pci_ss_info_1102_8938_156d_b550 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b560 = + {0x156d, 0xb560, pci_subsys_1102_8938_156d_b560, 0}; +#undef pci_ss_info_156d_b560 +#define pci_ss_info_156d_b560 pci_ss_info_1102_8938_156d_b560 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b700 = + {0x156d, 0xb700, pci_subsys_1102_8938_156d_b700, 0}; +#undef pci_ss_info_156d_b700 +#define pci_ss_info_156d_b700 pci_ss_info_1102_8938_156d_b700 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b795 = + {0x156d, 0xb795, pci_subsys_1102_8938_156d_b795, 0}; +#undef pci_ss_info_156d_b795 +#define pci_ss_info_156d_b795 pci_ss_info_1102_8938_156d_b795 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b797 = + {0x156d, 0xb797, pci_subsys_1102_8938_156d_b797, 0}; +#undef pci_ss_info_156d_b797 +#define pci_ss_info_156d_b797 pci_ss_info_1102_8938_156d_b797 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0003 = + {0x1103, 0x0003, pci_subsys_1103_0004_1103_0003, 0}; +#undef pci_ss_info_1103_0003 +#define pci_ss_info_1103_0003 pci_ss_info_1103_0004_1103_0003 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0004 = + {0x1103, 0x0004, pci_subsys_1103_0004_1103_0004, 0}; +#undef pci_ss_info_1103_0004 +#define pci_ss_info_1103_0004 pci_ss_info_1103_0004_1103_0004 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0006 = + {0x1103, 0x0006, pci_subsys_1103_0004_1103_0006, 0}; +#undef pci_ss_info_1103_0006 +#define pci_ss_info_1103_0006 pci_ss_info_1103_0004_1103_0006 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0007 = + {0x1103, 0x0007, pci_subsys_1103_0004_1103_0007, 0}; +#undef pci_ss_info_1103_0007 +#define pci_ss_info_1103_0007 pci_ss_info_1103_0004_1103_0007 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0008 = + {0x1103, 0x0008, pci_subsys_1103_0004_1103_0008, 0}; +#undef pci_ss_info_1103_0008 +#define pci_ss_info_1103_0008 pci_ss_info_1103_0004_1103_0008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1105_8475_1105_0001 = + {0x1105, 0x0001, pci_subsys_1105_8475_1105_0001, 0}; +#undef pci_ss_info_1105_0001 +#define pci_ss_info_1105_0001 pci_ss_info_1105_8475_1105_0001 +static const pciSubsystemInfo pci_ss_info_1105_8476_127d_0000 = + {0x127d, 0x0000, pci_subsys_1105_8476_127d_0000, 0}; +#undef pci_ss_info_127d_0000 +#define pci_ss_info_127d_0000 pci_ss_info_1105_8476_127d_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_0282_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_0282_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_0282_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_0305_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_0305_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_0305_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0571_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0571_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_0571_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_0571_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_0571_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_0571_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_0571_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_0571_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_0571_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_0571_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_0571_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_0571_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0571_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_0571_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_0571_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_0571_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_0571_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_0571_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_0571_1849_0571 = + {0x1849, 0x0571, pci_subsys_1106_0571_1849_0571, 0}; +#undef pci_ss_info_1849_0571 +#define pci_ss_info_1849_0571 pci_ss_info_1106_0571_1849_0571 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0605_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0605_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0605_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0686_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0686_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0686_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0686_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0691_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0691_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3038_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3038_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3038_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3038_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_8080 = + {0x1043, 0x8080, pci_subsys_1106_3038_1043_8080, 0}; +#undef pci_ss_info_1043_8080 +#define pci_ss_info_1043_8080 pci_ss_info_1106_3038_1043_8080 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3038_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3038_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3038_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3038_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3038_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3038_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3038_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3038_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3038_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3038_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3038_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3038_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3038_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3038_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3038_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3038_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3038_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3038_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3038_1849_3038 = + {0x1849, 0x3038, pci_subsys_1106_3038_1849_3038, 0}; +#undef pci_ss_info_1849_3038 +#define pci_ss_info_1849_3038 pci_ss_info_1106_3038_1849_3038 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3044_0574_086c = + {0x0574, 0x086c, pci_subsys_1106_3044_0574_086c, 0}; +#undef pci_ss_info_0574_086c +#define pci_ss_info_0574_086c pci_ss_info_1106_3044_0574_086c +#endif +static const pciSubsystemInfo pci_ss_info_1106_3044_1025_005a = + {0x1025, 0x005a, pci_subsys_1106_3044_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1106_3044_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3044_1043_808a = + {0x1043, 0x808a, pci_subsys_1106_3044_1043_808a, 0}; +#undef pci_ss_info_1043_808a +#define pci_ss_info_1043_808a pci_ss_info_1106_3044_1043_808a +static const pciSubsystemInfo pci_ss_info_1106_3044_1458_1000 = + {0x1458, 0x1000, pci_subsys_1106_3044_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_1106_3044_1458_1000 +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_702d = + {0x1462, 0x702d, pci_subsys_1106_3044_1462_702d, 0}; +#undef pci_ss_info_1462_702d +#define pci_ss_info_1462_702d pci_ss_info_1106_3044_1462_702d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_971d = + {0x1462, 0x971d, pci_subsys_1106_3044_1462_971d, 0}; +#undef pci_ss_info_1462_971d +#define pci_ss_info_1462_971d pci_ss_info_1106_3044_1462_971d +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3057_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3057_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3057_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3057_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_0097 = + {0x0e11, 0x0097, pci_subsys_1106_3058_0e11_0097, 0}; +#undef pci_ss_info_0e11_0097 +#define pci_ss_info_0e11_0097 pci_ss_info_1106_3058_0e11_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3058_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3058_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3058_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3058_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3058_1043_1106 = + {0x1043, 0x1106, pci_subsys_1106_3058_1043_1106, 0}; +#undef pci_ss_info_1043_1106 +#define pci_ss_info_1043_1106 pci_ss_info_1106_3058_1043_1106 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3300 = + {0x1462, 0x3300, pci_subsys_1106_3058_1462_3300, 0}; +#undef pci_ss_info_1462_3300 +#define pci_ss_info_1462_3300 pci_ss_info_1106_3058_1462_3300 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3059_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3059_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_8095 = + {0x1043, 0x8095, pci_subsys_1106_3059_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_1106_3059_1043_8095 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3059_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3059_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80b0 = + {0x1043, 0x80b0, pci_subsys_1106_3059_1043_80b0, 0}; +#undef pci_ss_info_1043_80b0 +#define pci_ss_info_1043_80b0 pci_ss_info_1106_3059_1043_80b0 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_812a = + {0x1043, 0x812a, pci_subsys_1106_3059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_1106_3059_1043_812a +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_3059 = + {0x1106, 0x3059, pci_subsys_1106_3059_1106_3059, 0}; +#undef pci_ss_info_1106_3059 +#define pci_ss_info_1106_3059 pci_ss_info_1106_3059_1106_3059 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4161 = + {0x1106, 0x4161, pci_subsys_1106_3059_1106_4161, 0}; +#undef pci_ss_info_1106_4161 +#define pci_ss_info_1106_4161 pci_ss_info_1106_3059_1106_4161 +static const pciSubsystemInfo pci_ss_info_1106_3059_1297_c160 = + {0x1297, 0xc160, pci_subsys_1106_3059_1297_c160, 0}; +#undef pci_ss_info_1297_c160 +#define pci_ss_info_1297_c160 pci_ss_info_1106_3059_1297_c160 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_0080 = + {0x1462, 0x0080, pci_subsys_1106_3059_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_1106_3059_1462_0080 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_3800 = + {0x1462, 0x3800, pci_subsys_1106_3059_1462_3800, 0}; +#undef pci_ss_info_1462_3800 +#define pci_ss_info_1462_3800 pci_ss_info_1106_3059_1462_3800 +static const pciSubsystemInfo pci_ss_info_1106_3059_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3059_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3059_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3059_1849_9761 = + {0x1849, 0x9761, pci_subsys_1106_3059_1849_9761, 0}; +#undef pci_ss_info_1849_9761 +#define pci_ss_info_1849_9761 pci_ss_info_1106_3059_1849_9761 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3059_4005_4710 = + {0x4005, 0x4710, pci_subsys_1106_3059_4005_4710, 0}; +#undef pci_ss_info_4005_4710 +#define pci_ss_info_4005_4710 pci_ss_info_1106_3059_4005_4710 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3059_a0a0_01b6 = + {0xa0a0, 0x01b6, pci_subsys_1106_3059_a0a0_01b6, 0}; +#undef pci_ss_info_a0a0_01b6 +#define pci_ss_info_a0a0_01b6 pci_ss_info_1106_3059_a0a0_01b6 +static const pciSubsystemInfo pci_ss_info_1106_3065_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3065_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3065_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3065_13b9_1421 = + {0x13b9, 0x1421, pci_subsys_1106_3065_13b9_1421, 0}; +#undef pci_ss_info_13b9_1421 +#define pci_ss_info_13b9_1421 pci_ss_info_1106_3065_13b9_1421 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_3005 = + {0x1695, 0x3005, pci_subsys_1106_3065_1695_3005, 0}; +#undef pci_ss_info_1695_3005 +#define pci_ss_info_1695_3005 pci_ss_info_1106_3065_1695_3005 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_300c = + {0x1695, 0x300c, pci_subsys_1106_3065_1695_300c, 0}; +#undef pci_ss_info_1695_300c +#define pci_ss_info_1695_300c pci_ss_info_1106_3065_1695_300c +static const pciSubsystemInfo pci_ss_info_1106_3065_1849_3065 = + {0x1849, 0x3065, pci_subsys_1106_3065_1849_3065, 0}; +#undef pci_ss_info_1849_3065 +#define pci_ss_info_1849_3065 pci_ss_info_1106_3065_1849_3065 +static const pciSubsystemInfo pci_ss_info_1106_3068_1462_309e = + {0x1462, 0x309e, pci_subsys_1106_3068_1462_309e, 0}; +#undef pci_ss_info_1462_309e +#define pci_ss_info_1462_309e pci_ss_info_1106_3068_1462_309e +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3099_1849_3099 = + {0x1849, 0x3099, pci_subsys_1106_3099_1849_3099, 0}; +#undef pci_ss_info_1849_3099 +#define pci_ss_info_1849_3099 pci_ss_info_1106_3099_1849_3099 +static const pciSubsystemInfo pci_ss_info_1106_3104_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3104_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3104_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3104_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3104_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3104_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3104_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3104_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3104_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3104_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3104_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3104_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3104_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3104_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3104_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3104_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3104_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3104_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3104_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3104_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3104_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3104_1849_3104 = + {0x1849, 0x3104, pci_subsys_1106_3104_1849_3104, 0}; +#undef pci_ss_info_1849_3104 +#define pci_ss_info_1849_3104 pci_ss_info_1106_3104_1849_3104 +static const pciSubsystemInfo pci_ss_info_1106_3106_1186_1403 = + {0x1186, 0x1403, pci_subsys_1106_3106_1186_1403, 0}; +#undef pci_ss_info_1186_1403 +#define pci_ss_info_1186_1403 pci_ss_info_1106_3106_1186_1403 +static const pciSubsystemInfo pci_ss_info_1106_3116_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3116_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3116_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3147_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3147_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3147_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3149_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3149_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3149_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3149_1458_b003 = + {0x1458, 0xb003, pci_subsys_1106_3149_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_1106_3149_1458_b003 +static const pciSubsystemInfo pci_ss_info_1106_3149_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3149_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3149_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3149_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3149_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1408 = + {0x147b, 0x1408, pci_subsys_1106_3149_147b_1408, 0}; +#undef pci_ss_info_147b_1408 +#define pci_ss_info_147b_1408 pci_ss_info_1106_3149_147b_1408 +static const pciSubsystemInfo pci_ss_info_1106_3149_1849_3149 = + {0x1849, 0x3149, pci_subsys_1106_3149_1849_3149, 0}; +#undef pci_ss_info_1849_3149 +#define pci_ss_info_1849_3149 pci_ss_info_1106_3149_1849_3149 +static const pciSubsystemInfo pci_ss_info_1106_3164_1462_7028 = + {0x1462, 0x7028, pci_subsys_1106_3164_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_1106_3164_1462_7028 +static const pciSubsystemInfo pci_ss_info_1106_3177_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3177_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3177_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3177_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3177_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3177_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3177_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3177_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3177_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3177_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3177_1849_3177 = + {0x1849, 0x3177, pci_subsys_1106_3177_1849_3177, 0}; +#undef pci_ss_info_1849_3177 +#define pci_ss_info_1849_3177 pci_ss_info_1106_3177_1849_3177 +static const pciSubsystemInfo pci_ss_info_1106_3188_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_3188_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_3188_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_3188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3188_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3189_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3189_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3189_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3189_1849_3189 = + {0x1849, 0x3189, pci_subsys_1106_3189_1849_3189, 0}; +#undef pci_ss_info_1849_3189 +#define pci_ss_info_1849_3189 pci_ss_info_1106_3189_1849_3189 +static const pciSubsystemInfo pci_ss_info_1106_3205_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3205_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3205_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3227_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3227_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3227_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3227_1106_3227 = + {0x1106, 0x3227, pci_subsys_1106_3227_1106_3227, 0}; +#undef pci_ss_info_1106_3227 +#define pci_ss_info_1106_3227 pci_ss_info_1106_3227_1106_3227 +static const pciSubsystemInfo pci_ss_info_1106_3227_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3227_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3227_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3227_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3227_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3227_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3227_1849_3227 = + {0x1849, 0x3227, pci_subsys_1106_3227_1849_3227, 0}; +#undef pci_ss_info_1849_3227 +#define pci_ss_info_1849_3227 pci_ss_info_1106_3227_1849_3227 +static const pciSubsystemInfo pci_ss_info_1106_7205_1458_d000 = + {0x1458, 0xd000, pci_subsys_1106_7205_1458_d000, 0}; +#undef pci_ss_info_1458_d000 +#define pci_ss_info_1458_d000 pci_ss_info_1106_7205_1458_d000 +static const pciSubsystemInfo pci_ss_info_1106_8598_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_8598_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_8598_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_b188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_b188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_b188_147b_1407 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_1113_2242 = + {0x1113, 0x2242, pci_subsys_1113_1216_1113_2242, 0}; +#undef pci_ss_info_1113_2242 +#define pci_ss_info_1113_2242 pci_ss_info_1113_1216_1113_2242 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_5402_1244_0f00 = + {0x1244, 0x0f00, pci_subsys_1131_5402_1244_0f00, 0}; +#undef pci_ss_info_1244_0f00 +#define pci_ss_info_1244_0f00 pci_ss_info_1131_5402_1244_0f00 +#endif +static const pciSubsystemInfo pci_ss_info_1131_7130_102b_48d0 = + {0x102b, 0x48d0, pci_subsys_1131_7130_102b_48d0, 0}; +#undef pci_ss_info_102b_48d0 +#define pci_ss_info_102b_48d0 pci_ss_info_1131_7130_102b_48d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7130_1048_226b = + {0x1048, 0x226b, pci_subsys_1131_7130_1048_226b, 0}; +#undef pci_ss_info_1048_226b +#define pci_ss_info_1048_226b pci_ss_info_1131_7130_1048_226b +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7130_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7130_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2005 = + {0x1131, 0x2005, pci_subsys_1131_7130_1131_2005, 0}; +#undef pci_ss_info_1131_2005 +#define pci_ss_info_1131_2005 pci_ss_info_1131_7130_1131_2005 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_050c = + {0x1461, 0x050c, pci_subsys_1131_7130_1461_050c, 0}; +#undef pci_ss_info_1461_050c +#define pci_ss_info_1461_050c pci_ss_info_1131_7130_1461_050c +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_10ff = + {0x1461, 0x10ff, pci_subsys_1131_7130_1461_10ff, 0}; +#undef pci_ss_info_1461_10ff +#define pci_ss_info_1461_10ff pci_ss_info_1131_7130_1461_10ff +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2108 = + {0x1461, 0x2108, pci_subsys_1131_7130_1461_2108, 0}; +#undef pci_ss_info_1461_2108 +#define pci_ss_info_1461_2108 pci_ss_info_1131_7130_1461_2108 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2115 = + {0x1461, 0x2115, pci_subsys_1131_7130_1461_2115, 0}; +#undef pci_ss_info_1461_2115 +#define pci_ss_info_1461_2115 pci_ss_info_1131_7130_1461_2115 +static const pciSubsystemInfo pci_ss_info_1131_7130_153b_1152 = + {0x153b, 0x1152, pci_subsys_1131_7130_153b_1152, 0}; +#undef pci_ss_info_153b_1152 +#define pci_ss_info_153b_1152 pci_ss_info_1131_7130_153b_1152 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7130_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7130_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7130_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7130_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7130_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_002b_11bd = + {0x002b, 0x11bd, pci_subsys_1131_7133_002b_11bd, 0}; +#undef pci_ss_info_002b_11bd +#define pci_ss_info_002b_11bd pci_ss_info_1131_7133_002b_11bd +static const pciSubsystemInfo pci_ss_info_1131_7133_1019_4cb5 = + {0x1019, 0x4cb5, pci_subsys_1131_7133_1019_4cb5, 0}; +#undef pci_ss_info_1019_4cb5 +#define pci_ss_info_1019_4cb5 pci_ss_info_1131_7133_1019_4cb5 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7133_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7133_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4843 = + {0x1043, 0x4843, pci_subsys_1131_7133_1043_4843, 0}; +#undef pci_ss_info_1043_4843 +#define pci_ss_info_1043_4843 pci_ss_info_1131_7133_1043_4843 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7133_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7133_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_f31f = + {0x1461, 0xf31f, pci_subsys_1131_7133_1461_f31f, 0}; +#undef pci_ss_info_1461_f31f +#define pci_ss_info_1461_f31f pci_ss_info_1131_7133_1461_f31f +static const pciSubsystemInfo pci_ss_info_1131_7133_1489_0214 = + {0x1489, 0x0214, pci_subsys_1131_7133_1489_0214, 0}; +#undef pci_ss_info_1489_0214 +#define pci_ss_info_1489_0214 pci_ss_info_1131_7133_1489_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1162 = + {0x153b, 0x1162, pci_subsys_1131_7133_153b_1162, 0}; +#undef pci_ss_info_153b_1162 +#define pci_ss_info_153b_1162 pci_ss_info_1131_7133_153b_1162 +static const pciSubsystemInfo pci_ss_info_1131_7133_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7133_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7133_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7133_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7133_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0212 = + {0x5168, 0x0212, pci_subsys_1131_7133_5168_0212, 0}; +#undef pci_ss_info_5168_0212 +#define pci_ss_info_5168_0212 pci_ss_info_1131_7133_5168_0212 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0214 = + {0x5168, 0x0214, pci_subsys_1131_7133_5168_0214, 0}; +#undef pci_ss_info_5168_0214 +#define pci_ss_info_5168_0214 pci_ss_info_1131_7133_5168_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0306 = + {0x5168, 0x0306, pci_subsys_1131_7133_5168_0306, 0}; +#undef pci_ss_info_5168_0306 +#define pci_ss_info_5168_0306 pci_ss_info_1131_7133_5168_0306 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0502 = + {0x5168, 0x0502, pci_subsys_1131_7133_5168_0502, 0}; +#undef pci_ss_info_5168_0502 +#define pci_ss_info_5168_0502 pci_ss_info_1131_7133_5168_0502 +static const pciSubsystemInfo pci_ss_info_1131_7134_1019_4cb4 = + {0x1019, 0x4cb4, pci_subsys_1131_7134_1019_4cb4, 0}; +#undef pci_ss_info_1019_4cb4 +#define pci_ss_info_1019_4cb4 pci_ss_info_1131_7134_1019_4cb4 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4840 = + {0x1043, 0x4840, pci_subsys_1131_7134_1043_4840, 0}; +#undef pci_ss_info_1043_4840 +#define pci_ss_info_1043_4840 pci_ss_info_1131_7134_1043_4840 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4842 = + {0x1043, 0x4842, pci_subsys_1131_7134_1043_4842, 0}; +#undef pci_ss_info_1043_4842 +#define pci_ss_info_1043_4842 pci_ss_info_1131_7134_1043_4842 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_4e85 = + {0x1131, 0x4e85, pci_subsys_1131_7134_1131_4e85, 0}; +#undef pci_ss_info_1131_4e85 +#define pci_ss_info_1131_4e85 pci_ss_info_1131_7134_1131_4e85 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_6752 = + {0x1131, 0x6752, pci_subsys_1131_7134_1131_6752, 0}; +#undef pci_ss_info_1131_6752 +#define pci_ss_info_1131_6752 pci_ss_info_1131_7134_1131_6752 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_7133 = + {0x1131, 0x7133, pci_subsys_1131_7134_1131_7133, 0}; +#undef pci_ss_info_1131_7133 +#define pci_ss_info_1131_7133 pci_ss_info_1131_7134_1131_7133 +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7134_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7134_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002d = + {0x11bd, 0x002d, pci_subsys_1131_7134_11bd_002d, 0}; +#undef pci_ss_info_11bd_002d +#define pci_ss_info_11bd_002d pci_ss_info_1131_7134_11bd_002d +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_2c00 = + {0x1461, 0x2c00, pci_subsys_1131_7134_1461_2c00, 0}; +#undef pci_ss_info_1461_2c00 +#define pci_ss_info_1461_2c00 pci_ss_info_1131_7134_1461_2c00 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_2c05 = + {0x1461, 0x2c05, pci_subsys_1131_7134_1461_2c05, 0}; +#undef pci_ss_info_1461_2c05 +#define pci_ss_info_1461_2c05 pci_ss_info_1131_7134_1461_2c05 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70a = + {0x1461, 0xa70a, pci_subsys_1131_7134_1461_a70a, 0}; +#undef pci_ss_info_1461_a70a +#define pci_ss_info_1461_a70a pci_ss_info_1131_7134_1461_a70a +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70b = + {0x1461, 0xa70b, pci_subsys_1131_7134_1461_a70b, 0}; +#undef pci_ss_info_1461_a70b +#define pci_ss_info_1461_a70b pci_ss_info_1131_7134_1461_a70b +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_d6ee = + {0x1461, 0xd6ee, pci_subsys_1131_7134_1461_d6ee, 0}; +#undef pci_ss_info_1461_d6ee +#define pci_ss_info_1461_d6ee pci_ss_info_1131_7134_1461_d6ee +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1142 = + {0x153b, 0x1142, pci_subsys_1131_7134_153b_1142, 0}; +#undef pci_ss_info_153b_1142 +#define pci_ss_info_153b_1142 pci_ss_info_1131_7134_153b_1142 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1143 = + {0x153b, 0x1143, pci_subsys_1131_7134_153b_1143, 0}; +#undef pci_ss_info_153b_1143 +#define pci_ss_info_153b_1143 pci_ss_info_1131_7134_153b_1143 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1158 = + {0x153b, 0x1158, pci_subsys_1131_7134_153b_1158, 0}; +#undef pci_ss_info_153b_1158 +#define pci_ss_info_153b_1158 pci_ss_info_1131_7134_153b_1158 +static const pciSubsystemInfo pci_ss_info_1131_7134_1540_9524 = + {0x1540, 0x9524, pci_subsys_1131_7134_1540_9524, 0}; +#undef pci_ss_info_1540_9524 +#define pci_ss_info_1540_9524 pci_ss_info_1131_7134_1540_9524 +static const pciSubsystemInfo pci_ss_info_1131_7134_16be_0003 = + {0x16be, 0x0003, pci_subsys_1131_7134_16be_0003, 0}; +#undef pci_ss_info_16be_0003 +#define pci_ss_info_16be_0003 pci_ss_info_1131_7134_16be_0003 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c200 = + {0x185b, 0xc200, pci_subsys_1131_7134_185b_c200, 0}; +#undef pci_ss_info_185b_c200 +#define pci_ss_info_185b_c200 pci_ss_info_1131_7134_185b_c200 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_a006 = + {0x1894, 0xa006, pci_subsys_1131_7134_1894_a006, 0}; +#undef pci_ss_info_1894_a006 +#define pci_ss_info_1894_a006 pci_ss_info_1131_7134_1894_a006 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_fe01 = + {0x1894, 0xfe01, pci_subsys_1131_7134_1894_fe01, 0}; +#undef pci_ss_info_1894_fe01 +#define pci_ss_info_1894_fe01 pci_ss_info_1131_7134_1894_fe01 +static const pciSubsystemInfo pci_ss_info_1131_7135_1421_0350 = + {0x1421, 0x0350, pci_subsys_1131_7135_1421_0350, 0}; +#undef pci_ss_info_1421_0350 +#define pci_ss_info_1421_0350 pci_ss_info_1131_7135_1421_0350 +static const pciSubsystemInfo pci_ss_info_1131_7135_1421_0370 = + {0x1421, 0x0370, pci_subsys_1131_7135_1421_0370, 0}; +#undef pci_ss_info_1421_0370 +#define pci_ss_info_1421_0370 pci_ss_info_1131_7135_1421_0370 +static const pciSubsystemInfo pci_ss_info_1131_7135_5168_0212 = + {0x5168, 0x0212, pci_subsys_1131_7135_5168_0212, 0}; +#undef pci_ss_info_5168_0212 +#define pci_ss_info_5168_0212 pci_ss_info_1131_7135_5168_0212 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_0000 = + {0x110a, 0x0000, pci_subsys_1131_7146_110a_0000, 0}; +#undef pci_ss_info_110a_0000 +#define pci_ss_info_110a_0000 pci_ss_info_1131_7146_110a_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_ffff = + {0x110a, 0xffff, pci_subsys_1131_7146_110a_ffff, 0}; +#undef pci_ss_info_110a_ffff +#define pci_ss_info_110a_ffff pci_ss_info_1131_7146_110a_ffff +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f56 = + {0x1131, 0x4f56, pci_subsys_1131_7146_1131_4f56, 0}; +#undef pci_ss_info_1131_4f56 +#define pci_ss_info_1131_4f56 pci_ss_info_1131_7146_1131_4f56 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f60 = + {0x1131, 0x4f60, pci_subsys_1131_7146_1131_4f60, 0}; +#undef pci_ss_info_1131_4f60 +#define pci_ss_info_1131_4f60 pci_ss_info_1131_7146_1131_4f60 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f61 = + {0x1131, 0x4f61, pci_subsys_1131_7146_1131_4f61, 0}; +#undef pci_ss_info_1131_4f61 +#define pci_ss_info_1131_4f61 pci_ss_info_1131_7146_1131_4f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_5f61 = + {0x1131, 0x5f61, pci_subsys_1131_7146_1131_5f61, 0}; +#undef pci_ss_info_1131_5f61 +#define pci_ss_info_1131_5f61 pci_ss_info_1131_7146_1131_5f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000f = + {0x11bd, 0x000f, pci_subsys_1131_7146_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_1131_7146_11bd_000f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_1131_7146_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_1131_7146_13c2_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0001 = + {0x13c2, 0x0001, pci_subsys_1131_7146_13c2_0001, 0}; +#undef pci_ss_info_13c2_0001 +#define pci_ss_info_13c2_0001 pci_ss_info_1131_7146_13c2_0001 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0002 = + {0x13c2, 0x0002, pci_subsys_1131_7146_13c2_0002, 0}; +#undef pci_ss_info_13c2_0002 +#define pci_ss_info_13c2_0002 pci_ss_info_1131_7146_13c2_0002 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0003 = + {0x13c2, 0x0003, pci_subsys_1131_7146_13c2_0003, 0}; +#undef pci_ss_info_13c2_0003 +#define pci_ss_info_13c2_0003 pci_ss_info_1131_7146_13c2_0003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0004 = + {0x13c2, 0x0004, pci_subsys_1131_7146_13c2_0004, 0}; +#undef pci_ss_info_13c2_0004 +#define pci_ss_info_13c2_0004 pci_ss_info_1131_7146_13c2_0004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0006 = + {0x13c2, 0x0006, pci_subsys_1131_7146_13c2_0006, 0}; +#undef pci_ss_info_13c2_0006 +#define pci_ss_info_13c2_0006 pci_ss_info_1131_7146_13c2_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0008 = + {0x13c2, 0x0008, pci_subsys_1131_7146_13c2_0008, 0}; +#undef pci_ss_info_13c2_0008 +#define pci_ss_info_13c2_0008 pci_ss_info_1131_7146_13c2_0008 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_000a = + {0x13c2, 0x000a, pci_subsys_1131_7146_13c2_000a, 0}; +#undef pci_ss_info_13c2_000a +#define pci_ss_info_13c2_000a pci_ss_info_1131_7146_13c2_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1003 = + {0x13c2, 0x1003, pci_subsys_1131_7146_13c2_1003, 0}; +#undef pci_ss_info_13c2_1003 +#define pci_ss_info_13c2_1003 pci_ss_info_1131_7146_13c2_1003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1004 = + {0x13c2, 0x1004, pci_subsys_1131_7146_13c2_1004, 0}; +#undef pci_ss_info_13c2_1004 +#define pci_ss_info_13c2_1004 pci_ss_info_1131_7146_13c2_1004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1005 = + {0x13c2, 0x1005, pci_subsys_1131_7146_13c2_1005, 0}; +#undef pci_ss_info_13c2_1005 +#define pci_ss_info_13c2_1005 pci_ss_info_1131_7146_13c2_1005 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100c = + {0x13c2, 0x100c, pci_subsys_1131_7146_13c2_100c, 0}; +#undef pci_ss_info_13c2_100c +#define pci_ss_info_13c2_100c pci_ss_info_1131_7146_13c2_100c +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100f = + {0x13c2, 0x100f, pci_subsys_1131_7146_13c2_100f, 0}; +#undef pci_ss_info_13c2_100f +#define pci_ss_info_13c2_100f pci_ss_info_1131_7146_13c2_100f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1011 = + {0x13c2, 0x1011, pci_subsys_1131_7146_13c2_1011, 0}; +#undef pci_ss_info_13c2_1011 +#define pci_ss_info_13c2_1011 pci_ss_info_1131_7146_13c2_1011 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1013 = + {0x13c2, 0x1013, pci_subsys_1131_7146_13c2_1013, 0}; +#undef pci_ss_info_13c2_1013 +#define pci_ss_info_13c2_1013 pci_ss_info_1131_7146_13c2_1013 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1102 = + {0x13c2, 0x1102, pci_subsys_1131_7146_13c2_1102, 0}; +#undef pci_ss_info_13c2_1102 +#define pci_ss_info_13c2_1102 pci_ss_info_1131_7146_13c2_1102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e010_110a_0021 = + {0x110a, 0x0021, pci_subsys_1133_e010_110a_0021, 0}; +#undef pci_ss_info_110a_0021 +#define pci_ss_info_110a_0021 pci_ss_info_1133_e010_110a_0021 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_1300 = + {0x1133, 0x1300, pci_subsys_1133_e013_1133_1300, 0}; +#undef pci_ss_info_1133_1300 +#define pci_ss_info_1133_1300 pci_ss_info_1133_e013_1133_1300 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_e013 = + {0x1133, 0xe013, pci_subsys_1133_e013_1133_e013, 0}; +#undef pci_ss_info_1133_e013 +#define pci_ss_info_1133_e013 pci_ss_info_1133_e013_1133_e013 +static const pciSubsystemInfo pci_ss_info_1133_e015_1133_e015 = + {0x1133, 0xe015, pci_subsys_1133_e015_1133_e015, 0}; +#undef pci_ss_info_1133_e015 +#define pci_ss_info_1133_e015 pci_ss_info_1133_e015_1133_e015 +static const pciSubsystemInfo pci_ss_info_1133_e017_1133_e017 = + {0x1133, 0xe017, pci_subsys_1133_e017_1133_e017, 0}; +#undef pci_ss_info_1133_e017 +#define pci_ss_info_1133_e017 pci_ss_info_1133_e017_1133_e017 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_1800 = + {0x1133, 0x1800, pci_subsys_1133_e018_1133_1800, 0}; +#undef pci_ss_info_1133_1800 +#define pci_ss_info_1133_1800 pci_ss_info_1133_e018_1133_1800 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_e018 = + {0x1133, 0xe018, pci_subsys_1133_e018_1133_e018, 0}; +#undef pci_ss_info_1133_e018 +#define pci_ss_info_1133_e018 pci_ss_info_1133_e018_1133_e018 +static const pciSubsystemInfo pci_ss_info_1133_e019_1133_e019 = + {0x1133, 0xe019, pci_subsys_1133_e019_1133_e019, 0}; +#undef pci_ss_info_1133_e019 +#define pci_ss_info_1133_e019 pci_ss_info_1133_e019_1133_e019 +static const pciSubsystemInfo pci_ss_info_1133_e01b_1133_e01b = + {0x1133, 0xe01b, pci_subsys_1133_e01b_1133_e01b, 0}; +#undef pci_ss_info_1133_e01b +#define pci_ss_info_1133_e01b pci_ss_info_1133_e01b_1133_e01b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c01 = + {0x1133, 0x1c01, pci_subsys_1133_e01c_1133_1c01, 0}; +#undef pci_ss_info_1133_1c01 +#define pci_ss_info_1133_1c01 pci_ss_info_1133_e01c_1133_1c01 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c02 = + {0x1133, 0x1c02, pci_subsys_1133_e01c_1133_1c02, 0}; +#undef pci_ss_info_1133_1c02 +#define pci_ss_info_1133_1c02 pci_ss_info_1133_e01c_1133_1c02 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c03 = + {0x1133, 0x1c03, pci_subsys_1133_e01c_1133_1c03, 0}; +#undef pci_ss_info_1133_1c03 +#define pci_ss_info_1133_1c03 pci_ss_info_1133_e01c_1133_1c03 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c04 = + {0x1133, 0x1c04, pci_subsys_1133_e01c_1133_1c04, 0}; +#undef pci_ss_info_1133_1c04 +#define pci_ss_info_1133_1c04 pci_ss_info_1133_e01c_1133_1c04 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c05 = + {0x1133, 0x1c05, pci_subsys_1133_e01c_1133_1c05, 0}; +#undef pci_ss_info_1133_1c05 +#define pci_ss_info_1133_1c05 pci_ss_info_1133_e01c_1133_1c05 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c06 = + {0x1133, 0x1c06, pci_subsys_1133_e01c_1133_1c06, 0}; +#undef pci_ss_info_1133_1c06 +#define pci_ss_info_1133_1c06 pci_ss_info_1133_e01c_1133_1c06 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c07 = + {0x1133, 0x1c07, pci_subsys_1133_e01c_1133_1c07, 0}; +#undef pci_ss_info_1133_1c07 +#define pci_ss_info_1133_1c07 pci_ss_info_1133_e01c_1133_1c07 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c08 = + {0x1133, 0x1c08, pci_subsys_1133_e01c_1133_1c08, 0}; +#undef pci_ss_info_1133_1c08 +#define pci_ss_info_1133_1c08 pci_ss_info_1133_e01c_1133_1c08 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c09 = + {0x1133, 0x1c09, pci_subsys_1133_e01c_1133_1c09, 0}; +#undef pci_ss_info_1133_1c09 +#define pci_ss_info_1133_1c09 pci_ss_info_1133_e01c_1133_1c09 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0a = + {0x1133, 0x1c0a, pci_subsys_1133_e01c_1133_1c0a, 0}; +#undef pci_ss_info_1133_1c0a +#define pci_ss_info_1133_1c0a pci_ss_info_1133_e01c_1133_1c0a +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0b = + {0x1133, 0x1c0b, pci_subsys_1133_e01c_1133_1c0b, 0}; +#undef pci_ss_info_1133_1c0b +#define pci_ss_info_1133_1c0b pci_ss_info_1133_e01c_1133_1c0b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0c = + {0x1133, 0x1c0c, pci_subsys_1133_e01c_1133_1c0c, 0}; +#undef pci_ss_info_1133_1c0c +#define pci_ss_info_1133_1c0c pci_ss_info_1133_e01c_1133_1c0c +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_2400 = + {0x1133, 0x2400, pci_subsys_1133_e024_1133_2400, 0}; +#undef pci_ss_info_1133_2400 +#define pci_ss_info_1133_2400 pci_ss_info_1133_e024_1133_2400 +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_e024 = + {0x1133, 0xe024, pci_subsys_1133_e024_1133_e024, 0}; +#undef pci_ss_info_1133_e024 +#define pci_ss_info_1133_e024 pci_ss_info_1133_e024_1133_e024 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_2800 = + {0x1133, 0x2800, pci_subsys_1133_e028_1133_2800, 0}; +#undef pci_ss_info_1133_2800 +#define pci_ss_info_1133_2800 pci_ss_info_1133_e028_1133_2800 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_e028 = + {0x1133, 0xe028, pci_subsys_1133_e028_1133_e028, 0}; +#undef pci_ss_info_1133_e028 +#define pci_ss_info_1133_e028 pci_ss_info_1133_e028_1133_e028 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2971 = + {0x1259, 0x2971, pci_subsys_1148_4300_1259_2971, 0}; +#undef pci_ss_info_1259_2971 +#define pci_ss_info_1259_2971 pci_ss_info_1148_4300_1259_2971 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2973 = + {0x1259, 0x2973, pci_subsys_1148_4300_1259_2973, 0}; +#undef pci_ss_info_1259_2973 +#define pci_ss_info_1259_2973 pci_ss_info_1148_4300_1259_2973 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2974 = + {0x1259, 0x2974, pci_subsys_1148_4300_1259_2974, 0}; +#undef pci_ss_info_1259_2974 +#define pci_ss_info_1259_2974 pci_ss_info_1148_4300_1259_2974 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2976 = + {0x1259, 0x2976, pci_subsys_1148_4300_1259_2976, 0}; +#undef pci_ss_info_1259_2976 +#define pci_ss_info_1259_2976 pci_ss_info_1148_4300_1259_2976 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0121 = + {0x1148, 0x0121, pci_subsys_1148_4320_1148_0121, 0}; +#undef pci_ss_info_1148_0121 +#define pci_ss_info_1148_0121 pci_ss_info_1148_4320_1148_0121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0221 = + {0x1148, 0x0221, pci_subsys_1148_4320_1148_0221, 0}; +#undef pci_ss_info_1148_0221 +#define pci_ss_info_1148_0221 pci_ss_info_1148_4320_1148_0221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0321 = + {0x1148, 0x0321, pci_subsys_1148_4320_1148_0321, 0}; +#undef pci_ss_info_1148_0321 +#define pci_ss_info_1148_0321 pci_ss_info_1148_4320_1148_0321 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0421 = + {0x1148, 0x0421, pci_subsys_1148_4320_1148_0421, 0}; +#undef pci_ss_info_1148_0421 +#define pci_ss_info_1148_0421 pci_ss_info_1148_4320_1148_0421 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0621 = + {0x1148, 0x0621, pci_subsys_1148_4320_1148_0621, 0}; +#undef pci_ss_info_1148_0621 +#define pci_ss_info_1148_0621 pci_ss_info_1148_4320_1148_0621 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0721 = + {0x1148, 0x0721, pci_subsys_1148_4320_1148_0721, 0}; +#undef pci_ss_info_1148_0721 +#define pci_ss_info_1148_0721 pci_ss_info_1148_4320_1148_0721 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0821 = + {0x1148, 0x0821, pci_subsys_1148_4320_1148_0821, 0}; +#undef pci_ss_info_1148_0821 +#define pci_ss_info_1148_0821 pci_ss_info_1148_4320_1148_0821 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0921 = + {0x1148, 0x0921, pci_subsys_1148_4320_1148_0921, 0}; +#undef pci_ss_info_1148_0921 +#define pci_ss_info_1148_0921 pci_ss_info_1148_4320_1148_0921 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1121 = + {0x1148, 0x1121, pci_subsys_1148_4320_1148_1121, 0}; +#undef pci_ss_info_1148_1121 +#define pci_ss_info_1148_1121 pci_ss_info_1148_4320_1148_1121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1221 = + {0x1148, 0x1221, pci_subsys_1148_4320_1148_1221, 0}; +#undef pci_ss_info_1148_1221 +#define pci_ss_info_1148_1221 pci_ss_info_1148_4320_1148_1221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_3221 = + {0x1148, 0x3221, pci_subsys_1148_4320_1148_3221, 0}; +#undef pci_ss_info_1148_3221 +#define pci_ss_info_1148_3221 pci_ss_info_1148_4320_1148_3221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2100 = + {0x1148, 0x2100, pci_subsys_1148_9e00_1148_2100, 0}; +#undef pci_ss_info_1148_2100 +#define pci_ss_info_1148_2100 pci_ss_info_1148_9e00_1148_2100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_21d0 = + {0x1148, 0x21d0, pci_subsys_1148_9e00_1148_21d0, 0}; +#undef pci_ss_info_1148_21d0 +#define pci_ss_info_1148_21d0 pci_ss_info_1148_9e00_1148_21d0 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2200 = + {0x1148, 0x2200, pci_subsys_1148_9e00_1148_2200, 0}; +#undef pci_ss_info_1148_2200 +#define pci_ss_info_1148_2200 pci_ss_info_1148_9e00_1148_2200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8100 = + {0x1148, 0x8100, pci_subsys_1148_9e00_1148_8100, 0}; +#undef pci_ss_info_1148_8100 +#define pci_ss_info_1148_8100 pci_ss_info_1148_9e00_1148_8100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8200 = + {0x1148, 0x8200, pci_subsys_1148_9e00_1148_8200, 0}; +#undef pci_ss_info_1148_8200 +#define pci_ss_info_1148_8200 pci_ss_info_1148_9e00_1148_8200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9100 = + {0x1148, 0x9100, pci_subsys_1148_9e00_1148_9100, 0}; +#undef pci_ss_info_1148_9100 +#define pci_ss_info_1148_9100 pci_ss_info_1148_9e00_1148_9100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9200 = + {0x1148, 0x9200, pci_subsys_1148_9e00_1148_9200, 0}; +#undef pci_ss_info_1148_9200 +#define pci_ss_info_1148_9200 pci_ss_info_1148_9e00_1148_9200 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0003_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0003_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0201_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0201_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0201_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0203_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0203_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0203_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0212_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0212_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0212_4c53_1080 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_c134 = + {0x1028, 0xc134, pci_subsys_1166_0213_1028_c134, 0}; +#undef pci_ss_info_1028_c134 +#define pci_ss_info_1028_c134 pci_ss_info_1166_0213_1028_c134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0213_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0213_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0213_1734_1012 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0217_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0217_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0217_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0220_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0220_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0220_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0221_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0221_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0221_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0227_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0227_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0227_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0230_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0230_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0230_4c53_1080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0601_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0601_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0601_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_060a_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_060a_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_060a_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8013 = + {0x117c, 0x8013, pci_subsys_117c_0030_117c_8013, 0}; +#undef pci_ss_info_117c_8013 +#define pci_ss_info_117c_8013 pci_ss_info_117c_0030_117c_8013 +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8014 = + {0x117c, 0x8014, pci_subsys_117c_0030_117c_8014, 0}; +#undef pci_ss_info_117c_8014 +#define pci_ss_info_117c_8014 pci_ss_info_117c_0030_117c_8014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0476_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0476_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0476_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0476_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1987 = + {0x1043, 0x1987, pci_subsys_1180_0476_1043_1987, 0}; +#undef pci_ss_info_1043_1987 +#define pci_ss_info_1043_1987 pci_ss_info_1180_0476_1043_1987 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_14ef_0220 = + {0x14ef, 0x0220, pci_subsys_1180_0476_14ef_0220, 0}; +#undef pci_ss_info_14ef_0220 +#define pci_ss_info_14ef_0220 pci_ss_info_1180_0476_14ef_0220 +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0522_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0522_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0522_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +static const pciSubsystemInfo pci_ss_info_1180_0592_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0592_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0592_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0556 = + {0x1014, 0x0556, pci_subsys_1180_0822_1014_0556, 0}; +#undef pci_ss_info_1014_0556 +#define pci_ss_info_1014_0556 pci_ss_info_1180_0822_1014_0556 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0822_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0822_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_01a2 = + {0x1028, 0x01a2, pci_subsys_1180_0822_1028_01a2, 0}; +#undef pci_ss_info_1028_01a2 +#define pci_ss_info_1028_01a2 pci_ss_info_1180_0822_1028_01a2 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0822_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0822_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0822_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0852_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0852_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0852_1043_1967 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1303 = + {0x1186, 0x1303, pci_subsys_1186_1300_1186_1303, 0}; +#undef pci_ss_info_1186_1303 +#define pci_ss_info_1186_1303 pci_ss_info_1186_1300_1186_1303 +static const pciSubsystemInfo pci_ss_info_1186_4c00_1186_4c00 = + {0x1186, 0x4c00, pci_subsys_1186_4c00_1186_4c00, 0}; +#undef pci_ss_info_1186_4c00 +#define pci_ss_info_1186_4c00 pci_ss_info_1186_4c00_1186_4c00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_1faa_1385_4e00 = + {0x1385, 0x4e00, pci_subsys_11ab_1faa_1385_4e00, 0}; +#undef pci_ss_info_1385_4e00 +#define pci_ss_info_1385_4e00 pci_ss_info_11ab_1faa_1385_4e00 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_0f38 = + {0x1019, 0x0f38, pci_subsys_11ab_4320_1019_0f38, 0}; +#undef pci_ss_info_1019_0f38 +#define pci_ss_info_1019_0f38 pci_ss_info_11ab_4320_1019_0f38 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_8001 = + {0x1019, 0x8001, pci_subsys_11ab_4320_1019_8001, 0}; +#undef pci_ss_info_1019_8001 +#define pci_ss_info_1019_8001 pci_ss_info_11ab_4320_1019_8001 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_173c = + {0x1043, 0x173c, pci_subsys_11ab_4320_1043_173c, 0}; +#undef pci_ss_info_1043_173c +#define pci_ss_info_1043_173c pci_ss_info_11ab_4320_1043_173c +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_811a = + {0x1043, 0x811a, pci_subsys_11ab_4320_1043_811a, 0}; +#undef pci_ss_info_1043_811a +#define pci_ss_info_1043_811a pci_ss_info_11ab_4320_1043_811a +static const pciSubsystemInfo pci_ss_info_11ab_4320_105b_0c19 = + {0x105b, 0x0c19, pci_subsys_11ab_4320_105b_0c19, 0}; +#undef pci_ss_info_105b_0c19 +#define pci_ss_info_105b_0c19 pci_ss_info_11ab_4320_105b_0c19 +static const pciSubsystemInfo pci_ss_info_11ab_4320_10b8_b452 = + {0x10b8, 0xb452, pci_subsys_11ab_4320_10b8_b452, 0}; +#undef pci_ss_info_10b8_b452 +#define pci_ss_info_10b8_b452 pci_ss_info_11ab_4320_10b8_b452 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0121 = + {0x11ab, 0x0121, pci_subsys_11ab_4320_11ab_0121, 0}; +#undef pci_ss_info_11ab_0121 +#define pci_ss_info_11ab_0121 pci_ss_info_11ab_4320_11ab_0121 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0321 = + {0x11ab, 0x0321, pci_subsys_11ab_4320_11ab_0321, 0}; +#undef pci_ss_info_11ab_0321 +#define pci_ss_info_11ab_0321 pci_ss_info_11ab_4320_11ab_0321 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_1021 = + {0x11ab, 0x1021, pci_subsys_11ab_4320_11ab_1021, 0}; +#undef pci_ss_info_11ab_1021 +#define pci_ss_info_11ab_1021 pci_ss_info_11ab_4320_11ab_1021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4320_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4320_11ab_5021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_9521 = + {0x11ab, 0x9521, pci_subsys_11ab_4320_11ab_9521, 0}; +#undef pci_ss_info_11ab_9521 +#define pci_ss_info_11ab_9521 pci_ss_info_11ab_4320_11ab_9521 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4320_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4320_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4320_147b_1406 = + {0x147b, 0x1406, pci_subsys_11ab_4320_147b_1406, 0}; +#undef pci_ss_info_147b_1406 +#define pci_ss_info_147b_1406 pci_ss_info_11ab_4320_147b_1406 +static const pciSubsystemInfo pci_ss_info_11ab_4320_15d4_0047 = + {0x15d4, 0x0047, pci_subsys_11ab_4320_15d4_0047, 0}; +#undef pci_ss_info_15d4_0047 +#define pci_ss_info_15d4_0047 pci_ss_info_11ab_4320_15d4_0047 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1695_9025 = + {0x1695, 0x9025, pci_subsys_11ab_4320_1695_9025, 0}; +#undef pci_ss_info_1695_9025 +#define pci_ss_info_1695_9025 pci_ss_info_11ab_4320_1695_9025 +static const pciSubsystemInfo pci_ss_info_11ab_4320_17f2_1c03 = + {0x17f2, 0x1c03, pci_subsys_11ab_4320_17f2_1c03, 0}; +#undef pci_ss_info_17f2_1c03 +#define pci_ss_info_17f2_1c03 pci_ss_info_11ab_4320_17f2_1c03 +static const pciSubsystemInfo pci_ss_info_11ab_4320_270f_2803 = + {0x270f, 0x2803, pci_subsys_11ab_4320_270f_2803, 0}; +#undef pci_ss_info_270f_2803 +#define pci_ss_info_270f_2803 pci_ss_info_11ab_4320_270f_2803 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4350_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4350_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4350_11ab_3521 = + {0x11ab, 0x3521, pci_subsys_11ab_4350_11ab_3521, 0}; +#undef pci_ss_info_11ab_3521 +#define pci_ss_info_11ab_3521 pci_ss_info_11ab_4350_11ab_3521 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4350_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4350_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4350_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4350_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4350_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4350_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4350_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4350_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4350_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4350_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4350_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4350_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4350_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4350_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4350_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4350_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4350_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4350_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4350_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4350_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4350_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4350_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4350_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4350_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4351_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4351_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4351_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4351_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4351_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4351_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4351_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4351_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4351_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4351_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4351_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4351_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4351_11ab_3621 = + {0x11ab, 0x3621, pci_subsys_11ab_4351_11ab_3621, 0}; +#undef pci_ss_info_11ab_3621 +#define pci_ss_info_11ab_3621 pci_ss_info_11ab_4351_11ab_3621 +static const pciSubsystemInfo pci_ss_info_11ab_4351_13d1_ac12 = + {0x13d1, 0xac12, pci_subsys_11ab_4351_13d1_ac12, 0}; +#undef pci_ss_info_13d1_ac12 +#define pci_ss_info_13d1_ac12 pci_ss_info_11ab_4351_13d1_ac12 +static const pciSubsystemInfo pci_ss_info_11ab_4351_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4351_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4351_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4351_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4351_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4351_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4351_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4351_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4351_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4351_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4351_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4351_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4351_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4351_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4351_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4351_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4351_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4351_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4351_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4351_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4351_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4351_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4351_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4351_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4351_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4351_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4351_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1043_8134 = + {0x1043, 0x8134, pci_subsys_11ab_4360_1043_8134, 0}; +#undef pci_ss_info_1043_8134 +#define pci_ss_info_1043_8134 pci_ss_info_11ab_4360_1043_8134 +static const pciSubsystemInfo pci_ss_info_11ab_4360_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4360_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4360_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4360_11ab_5221 = + {0x11ab, 0x5221, pci_subsys_11ab_4360_11ab_5221, 0}; +#undef pci_ss_info_11ab_5221 +#define pci_ss_info_11ab_5221 pci_ss_info_11ab_4360_11ab_5221 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4360_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4360_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1462_052c = + {0x1462, 0x052c, pci_subsys_11ab_4360_1462_052c, 0}; +#undef pci_ss_info_1462_052c +#define pci_ss_info_1462_052c pci_ss_info_11ab_4360_1462_052c +static const pciSubsystemInfo pci_ss_info_11ab_4360_1849_8052 = + {0x1849, 0x8052, pci_subsys_11ab_4360_1849_8052, 0}; +#undef pci_ss_info_1849_8052 +#define pci_ss_info_1849_8052 pci_ss_info_11ab_4360_1849_8052 +static const pciSubsystemInfo pci_ss_info_11ab_4360_a0a0_0509 = + {0xa0a0, 0x0509, pci_subsys_11ab_4360_a0a0_0509, 0}; +#undef pci_ss_info_a0a0_0509 +#define pci_ss_info_a0a0_0509 pci_ss_info_11ab_4360_a0a0_0509 +static const pciSubsystemInfo pci_ss_info_11ab_4361_107b_3015 = + {0x107b, 0x3015, pci_subsys_11ab_4361_107b_3015, 0}; +#undef pci_ss_info_107b_3015 +#define pci_ss_info_107b_3015 pci_ss_info_11ab_4361_107b_3015 +static const pciSubsystemInfo pci_ss_info_11ab_4361_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4361_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4361_11ab_5021 +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3063 = + {0x8086, 0x3063, pci_subsys_11ab_4361_8086_3063, 0}; +#undef pci_ss_info_8086_3063 +#define pci_ss_info_8086_3063 pci_ss_info_11ab_4361_8086_3063 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3439 = + {0x8086, 0x3439, pci_subsys_11ab_4361_8086_3439, 0}; +#undef pci_ss_info_8086_3439 +#define pci_ss_info_8086_3439 pci_ss_info_11ab_4361_8086_3439 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4362_103c_2a0d = + {0x103c, 0x2a0d, pci_subsys_11ab_4362_103c_2a0d, 0}; +#undef pci_ss_info_103c_2a0d +#define pci_ss_info_103c_2a0d pci_ss_info_11ab_4362_103c_2a0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_4362_1043_8142 = + {0x1043, 0x8142, pci_subsys_11ab_4362_1043_8142, 0}; +#undef pci_ss_info_1043_8142 +#define pci_ss_info_1043_8142 pci_ss_info_11ab_4362_1043_8142 +static const pciSubsystemInfo pci_ss_info_11ab_4362_109f_3197 = + {0x109f, 0x3197, pci_subsys_11ab_4362_109f_3197, 0}; +#undef pci_ss_info_109f_3197 +#define pci_ss_info_109f_3197 pci_ss_info_11ab_4362_109f_3197 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4362_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4362_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10fd_a430 = + {0x10fd, 0xa430, pci_subsys_11ab_4362_10fd_a430, 0}; +#undef pci_ss_info_10fd_a430 +#define pci_ss_info_10fd_a430 pci_ss_info_11ab_4362_10fd_a430 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4362_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4362_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4362_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4362_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4362_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4362_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4362_11ab_5321 = + {0x11ab, 0x5321, pci_subsys_11ab_4362_11ab_5321, 0}; +#undef pci_ss_info_11ab_5321 +#define pci_ss_info_11ab_5321 pci_ss_info_11ab_4362_11ab_5321 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c240 = + {0x1297, 0xc240, pci_subsys_11ab_4362_1297_c240, 0}; +#undef pci_ss_info_1297_c240 +#define pci_ss_info_1297_c240 pci_ss_info_11ab_4362_1297_c240 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c241 = + {0x1297, 0xc241, pci_subsys_11ab_4362_1297_c241, 0}; +#undef pci_ss_info_1297_c241 +#define pci_ss_info_1297_c241 pci_ss_info_11ab_4362_1297_c241 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c242 = + {0x1297, 0xc242, pci_subsys_11ab_4362_1297_c242, 0}; +#undef pci_ss_info_1297_c242 +#define pci_ss_info_1297_c242 pci_ss_info_11ab_4362_1297_c242 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c243 = + {0x1297, 0xc243, pci_subsys_11ab_4362_1297_c243, 0}; +#undef pci_ss_info_1297_c243 +#define pci_ss_info_1297_c243 pci_ss_info_11ab_4362_1297_c243 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c244 = + {0x1297, 0xc244, pci_subsys_11ab_4362_1297_c244, 0}; +#undef pci_ss_info_1297_c244 +#define pci_ss_info_1297_c244 pci_ss_info_11ab_4362_1297_c244 +static const pciSubsystemInfo pci_ss_info_11ab_4362_13d1_ac11 = + {0x13d1, 0xac11, pci_subsys_11ab_4362_13d1_ac11, 0}; +#undef pci_ss_info_13d1_ac11 +#define pci_ss_info_13d1_ac11 pci_ss_info_11ab_4362_13d1_ac11 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4362_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4362_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1462_058c = + {0x1462, 0x058c, pci_subsys_11ab_4362_1462_058c, 0}; +#undef pci_ss_info_1462_058c +#define pci_ss_info_1462_058c pci_ss_info_11ab_4362_1462_058c +static const pciSubsystemInfo pci_ss_info_11ab_4362_14c0_0012 = + {0x14c0, 0x0012, pci_subsys_11ab_4362_14c0_0012, 0}; +#undef pci_ss_info_14c0_0012 +#define pci_ss_info_14c0_0012 pci_ss_info_11ab_4362_14c0_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1558_04a0 = + {0x1558, 0x04a0, pci_subsys_11ab_4362_1558_04a0, 0}; +#undef pci_ss_info_1558_04a0 +#define pci_ss_info_1558_04a0 pci_ss_info_11ab_4362_1558_04a0 +static const pciSubsystemInfo pci_ss_info_11ab_4362_15bd_1003 = + {0x15bd, 0x1003, pci_subsys_11ab_4362_15bd_1003, 0}; +#undef pci_ss_info_15bd_1003 +#define pci_ss_info_15bd_1003 pci_ss_info_11ab_4362_15bd_1003 +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203c = + {0x161f, 0x203c, pci_subsys_11ab_4362_161f_203c, 0}; +#undef pci_ss_info_161f_203c +#define pci_ss_info_161f_203c pci_ss_info_11ab_4362_161f_203c +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4362_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4362_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1695_9029 = + {0x1695, 0x9029, pci_subsys_11ab_4362_1695_9029, 0}; +#undef pci_ss_info_1695_9029 +#define pci_ss_info_1695_9029 pci_ss_info_11ab_4362_1695_9029 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17f2_2c08 = + {0x17f2, 0x2c08, pci_subsys_11ab_4362_17f2_2c08, 0}; +#undef pci_ss_info_17f2_2c08 +#define pci_ss_info_17f2_2c08 pci_ss_info_11ab_4362_17f2_2c08 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17ff_0585 = + {0x17ff, 0x0585, pci_subsys_11ab_4362_17ff_0585, 0}; +#undef pci_ss_info_17ff_0585 +#define pci_ss_info_17ff_0585 pci_ss_info_11ab_4362_17ff_0585 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1849_8053 = + {0x1849, 0x8053, pci_subsys_11ab_4362_1849_8053, 0}; +#undef pci_ss_info_1849_8053 +#define pci_ss_info_1849_8053 pci_ss_info_11ab_4362_1849_8053 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000b = + {0x1854, 0x000b, pci_subsys_11ab_4362_1854_000b, 0}; +#undef pci_ss_info_1854_000b +#define pci_ss_info_1854_000b pci_ss_info_11ab_4362_1854_000b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000c = + {0x1854, 0x000c, pci_subsys_11ab_4362_1854_000c, 0}; +#undef pci_ss_info_1854_000c +#define pci_ss_info_1854_000c pci_ss_info_11ab_4362_1854_000c +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0010 = + {0x1854, 0x0010, pci_subsys_11ab_4362_1854_0010, 0}; +#undef pci_ss_info_1854_0010 +#define pci_ss_info_1854_0010 pci_ss_info_11ab_4362_1854_0010 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0013 = + {0x1854, 0x0013, pci_subsys_11ab_4362_1854_0013, 0}; +#undef pci_ss_info_1854_0013 +#define pci_ss_info_1854_0013 pci_ss_info_11ab_4362_1854_0013 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0014 = + {0x1854, 0x0014, pci_subsys_11ab_4362_1854_0014, 0}; +#undef pci_ss_info_1854_0014 +#define pci_ss_info_1854_0014 pci_ss_info_11ab_4362_1854_0014 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0015 = + {0x1854, 0x0015, pci_subsys_11ab_4362_1854_0015, 0}; +#undef pci_ss_info_1854_0015 +#define pci_ss_info_1854_0015 pci_ss_info_11ab_4362_1854_0015 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001a = + {0x1854, 0x001a, pci_subsys_11ab_4362_1854_001a, 0}; +#undef pci_ss_info_1854_001a +#define pci_ss_info_1854_001a pci_ss_info_11ab_4362_1854_001a +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001b = + {0x1854, 0x001b, pci_subsys_11ab_4362_1854_001b, 0}; +#undef pci_ss_info_1854_001b +#define pci_ss_info_1854_001b pci_ss_info_11ab_4362_1854_001b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001d = + {0x1854, 0x001d, pci_subsys_11ab_4362_1854_001d, 0}; +#undef pci_ss_info_1854_001d +#define pci_ss_info_1854_001d pci_ss_info_11ab_4362_1854_001d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001f = + {0x1854, 0x001f, pci_subsys_11ab_4362_1854_001f, 0}; +#undef pci_ss_info_1854_001f +#define pci_ss_info_1854_001f pci_ss_info_11ab_4362_1854_001f +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0021 = + {0x1854, 0x0021, pci_subsys_11ab_4362_1854_0021, 0}; +#undef pci_ss_info_1854_0021 +#define pci_ss_info_1854_0021 pci_ss_info_11ab_4362_1854_0021 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0022 = + {0x1854, 0x0022, pci_subsys_11ab_4362_1854_0022, 0}; +#undef pci_ss_info_1854_0022 +#define pci_ss_info_1854_0022 pci_ss_info_11ab_4362_1854_0022 +static const pciSubsystemInfo pci_ss_info_11ab_4362_270f_2801 = + {0x270f, 0x2801, pci_subsys_11ab_4362_270f_2801, 0}; +#undef pci_ss_info_270f_2801 +#define pci_ss_info_270f_2801 pci_ss_info_11ab_4362_270f_2801 +static const pciSubsystemInfo pci_ss_info_11ab_4362_a0a0_0506 = + {0xa0a0, 0x0506, pci_subsys_11ab_4362_a0a0_0506, 0}; +#undef pci_ss_info_a0a0_0506 +#define pci_ss_info_a0a0_0506 pci_ss_info_11ab_4362_a0a0_0506 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2203 = + {0x8086, 0x2203, pci_subsys_11c1_0445_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_11c1_0445_8086_2203 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2204 = + {0x8086, 0x2204, pci_subsys_11c1_0445_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_11c1_0445_8086_2204 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_1033_80a8 = + {0x1033, 0x80a8, pci_subsys_11c1_0450_1033_80a8, 0}; +#undef pci_ss_info_1033_80a8 +#define pci_ss_info_1033_80a8 pci_ss_info_11c1_0450_1033_80a8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_1468_0450 = + {0x1468, 0x0450, pci_subsys_11c1_0450_1468_0450, 0}; +#undef pci_ss_info_1468_0450 +#define pci_ss_info_1468_0450 pci_ss_info_11c1_0450_1468_0450 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_4005_144f = + {0x4005, 0x144f, pci_subsys_11c1_0450_4005_144f, 0}; +#undef pci_ss_info_4005_144f +#define pci_ss_info_4005_144f pci_ss_info_11c1_0450_4005_144f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_5811_8086_524c = + {0x8086, 0x524c, pci_subsys_11c1_5811_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_11c1_5811_8086_524c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab12 = + {0x11c1, 0xab12, pci_subsys_11c1_ab11_11c1_ab12, 0}; +#undef pci_ss_info_11c1_ab12 +#define pci_ss_info_11c1_ab12 pci_ss_info_11c1_ab11_11c1_ab12 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab13 = + {0x11c1, 0xab13, pci_subsys_11c1_ab11_11c1_ab13, 0}; +#undef pci_ss_info_11c1_ab13 +#define pci_ss_info_11c1_ab13 pci_ss_info_11c1_ab11_11c1_ab13 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab15 = + {0x11c1, 0xab15, pci_subsys_11c1_ab11_11c1_ab15, 0}; +#undef pci_ss_info_11c1_ab15 +#define pci_ss_info_11c1_ab15 pci_ss_info_11c1_ab11_11c1_ab15 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab16 = + {0x11c1, 0xab16, pci_subsys_11c1_ab11_11c1_ab16, 0}; +#undef pci_ss_info_11c1_ab16 +#define pci_ss_info_11c1_ab16 pci_ss_info_11c1_ab11_11c1_ab16 +static const pciSubsystemInfo pci_ss_info_11c1_ab30_14cd_2012 = + {0x14cd, 0x2012, pci_subsys_11c1_ab30_14cd_2012, 0}; +#undef pci_ss_info_14cd_2012 +#define pci_ss_info_14cd_2012 pci_ss_info_11c1_ab30_14cd_2012 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_12f8_8a02 = + {0x12f8, 0x8a02, pci_subsys_11de_6057_12f8_8a02, 0}; +#undef pci_ss_info_12f8_8a02 +#define pci_ss_info_12f8_8a02 pci_ss_info_11de_6057_12f8_8a02 +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +static const pciSubsystemInfo pci_ss_info_11de_6120_1de1_9fff = + {0x1de1, 0x9fff, pci_subsys_11de_6120_1de1_9fff, 0}; +#undef pci_ss_info_1de1_9fff +#define pci_ss_info_1de1_9fff pci_ss_info_11de_6120_1de1_9fff +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1014_020c = + {0x1014, 0x020c, pci_subsys_1217_6972_1014_020c, 0}; +#undef pci_ss_info_1014_020c +#define pci_ss_info_1014_020c pci_ss_info_1217_6972_1014_020c +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7110_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7110_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7110_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7110_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7223_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7223_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7223_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7223_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0057 = + {0x121a, 0x0057, pci_subsys_121a_0005_121a_0057, 0}; +#undef pci_ss_info_121a_0057 +#define pci_ss_info_121a_0057 pci_ss_info_121a_0005_121a_0057 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0009_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0009_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000f = + {0x11bd, 0x000f, pci_subsys_123f_8120_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_123f_8120_11bd_000f +static const pciSubsystemInfo pci_ss_info_123f_8120_1809_0016 = + {0x1809, 0x0016, pci_subsys_123f_8120_1809_0016, 0}; +#undef pci_ss_info_1809_0016 +#define pci_ss_info_1809_0016 pci_ss_info_123f_8120_1809_0016 +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125b_1400_1186_1100 = + {0x1186, 0x1100, pci_subsys_125b_1400_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_125b_1400_1186_1100 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +static const pciSubsystemInfo pci_ss_info_125d_1969_153b_111b = + {0x153b, 0x111b, pci_subsys_125d_1969_153b_111b, 0}; +#undef pci_ss_info_153b_111b +#define pci_ss_info_153b_111b pci_ss_info_125d_1969_153b_111b +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_125d_1988_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_125d_1988_0e11_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_125d_1998_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_125d_1998_1028_00b1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3872_1468_0202 = + {0x1468, 0x0202, pci_subsys_1260_3872_1468_0202, 0}; +#undef pci_ss_info_1468_0202 +#define pci_ss_info_1468_0202 pci_ss_info_1260_3872_1468_0202 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3700 = + {0x1186, 0x3700, pci_subsys_1260_3873_1186_3700, 0}; +#undef pci_ss_info_1186_3700 +#define pci_ss_info_1186_3700 pci_ss_info_1260_3873_1186_3700 +static const pciSubsystemInfo pci_ss_info_1260_3873_1385_4105 = + {0x1385, 0x4105, pci_subsys_1260_3873_1385_4105, 0}; +#undef pci_ss_info_1385_4105 +#define pci_ss_info_1385_4105 pci_ss_info_1260_3873_1385_4105 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_16a5_1601 = + {0x16a5, 0x1601, pci_subsys_1260_3873_16a5_1601, 0}; +#undef pci_ss_info_16a5_1601 +#define pci_ss_info_16a5_1601 pci_ss_info_1260_3873_16a5_1601 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3886_17cf_0037 = + {0x17cf, 0x0037, pci_subsys_1260_3886_17cf_0037, 0}; +#undef pci_ss_info_17cf_0037 +#define pci_ss_info_17cf_0037 pci_ss_info_1260_3886_17cf_0037 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2802 = + {0x10b8, 0x2802, pci_subsys_1260_3890_10b8_2802, 0}; +#undef pci_ss_info_10b8_2802 +#define pci_ss_info_10b8_2802 pci_ss_info_1260_3890_10b8_2802 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2835 = + {0x10b8, 0x2835, pci_subsys_1260_3890_10b8_2835, 0}; +#undef pci_ss_info_10b8_2835 +#define pci_ss_info_10b8_2835 pci_ss_info_1260_3890_10b8_2835 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_a835 = + {0x10b8, 0xa835, pci_subsys_1260_3890_10b8_a835, 0}; +#undef pci_ss_info_10b8_a835 +#define pci_ss_info_10b8_a835 pci_ss_info_1260_3890_10b8_a835 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_4203 = + {0x1113, 0x4203, pci_subsys_1260_3890_1113_4203, 0}; +#undef pci_ss_info_1113_4203 +#define pci_ss_info_1113_4203 pci_ss_info_1260_3890_1113_4203 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee03 = + {0x1113, 0xee03, pci_subsys_1260_3890_1113_ee03, 0}; +#undef pci_ss_info_1113_ee03 +#define pci_ss_info_1113_ee03 pci_ss_info_1260_3890_1113_ee03 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee08 = + {0x1113, 0xee08, pci_subsys_1260_3890_1113_ee08, 0}; +#undef pci_ss_info_1113_ee08 +#define pci_ss_info_1113_ee08 pci_ss_info_1260_3890_1113_ee08 +static const pciSubsystemInfo pci_ss_info_1260_3890_1186_3202 = + {0x1186, 0x3202, pci_subsys_1260_3890_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_1260_3890_1186_3202 +static const pciSubsystemInfo pci_ss_info_1260_3890_1259_c104 = + {0x1259, 0xc104, pci_subsys_1260_3890_1259_c104, 0}; +#undef pci_ss_info_1259_c104 +#define pci_ss_info_1259_c104 pci_ss_info_1260_3890_1259_c104 +static const pciSubsystemInfo pci_ss_info_1260_3890_1385_4800 = + {0x1385, 0x4800, pci_subsys_1260_3890_1385_4800, 0}; +#undef pci_ss_info_1385_4800 +#define pci_ss_info_1385_4800 pci_ss_info_1260_3890_1385_4800 +static const pciSubsystemInfo pci_ss_info_1260_3890_16a5_1605 = + {0x16a5, 0x1605, pci_subsys_1260_3890_16a5_1605, 0}; +#undef pci_ss_info_16a5_1605 +#define pci_ss_info_16a5_1605 pci_ss_info_1260_3890_16a5_1605 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0014 = + {0x17cf, 0x0014, pci_subsys_1260_3890_17cf_0014, 0}; +#undef pci_ss_info_17cf_0014 +#define pci_ss_info_17cf_0014 pci_ss_info_1260_3890_17cf_0014 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0020 = + {0x17cf, 0x0020, pci_subsys_1260_3890_17cf_0020, 0}; +#undef pci_ss_info_17cf_0020 +#define pci_ss_info_17cf_0020 pci_ss_info_1260_3890_17cf_0020 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_1371_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_1371_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4541 = + {0x8086, 0x4541, pci_subsys_1274_1371_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_1274_1371_8086_4541 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_5880_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_5880_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1005_127a = + {0x1005, 0x127a, pci_subsys_127a_1005_1005_127a, 0}; +#undef pci_ss_info_1005_127a +#define pci_ss_info_1005_127a pci_ss_info_127a_1005_1005_127a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1283_8212_1283_0001 = + {0x1283, 0x0001, pci_subsys_1283_8212_1283_0001, 0}; +#undef pci_ss_info_1283_0001 +#define pci_ss_info_1283_0001 pci_ss_info_1283_8212_1283_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_1014_0104 = + {0x1014, 0x0104, pci_subsys_12ae_0001_1014_0104, 0}; +#undef pci_ss_info_1014_0104 +#define pci_ss_info_1014_0104 pci_ss_info_12ae_0001_1014_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_12ae_0002_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_12ae_0002_10a9_8002 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1317_8201_10b8_2635 = + {0x10b8, 0x2635, pci_subsys_1317_8201_10b8_2635, 0}; +#undef pci_ss_info_10b8_2635 +#define pci_ss_info_10b8_2635 pci_ss_info_1317_8201_10b8_2635 +static const pciSubsystemInfo pci_ss_info_1317_8201_1317_8201 = + {0x1317, 0x8201, pci_subsys_1317_8201_1317_8201, 0}; +#undef pci_ss_info_1317_8201 +#define pci_ss_info_1317_8201 pci_ss_info_1317_8201_1317_8201 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1319_0801_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0801_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0801_1319_1319 +static const pciSubsystemInfo pci_ss_info_1319_0802_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0802_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0802_1319_1319 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7890_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7890_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7890_134d_0001 +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1371_434e_1371_434e = + {0x1371, 0x434e, pci_subsys_1371_434e_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_1371_434e_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1704 = + {0x0675, 0x1704, pci_subsys_1397_2bd0_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1397_2bd0_0675_1704 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1708 = + {0x0675, 0x1708, pci_subsys_1397_2bd0_0675_1708, 0}; +#undef pci_ss_info_0675_1708 +#define pci_ss_info_0675_1708 pci_ss_info_1397_2bd0_0675_1708 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13c1_1001_13c1_1001 = + {0x13c1, 0x1001, pci_subsys_13c1_1001_13c1_1001, 0}; +#undef pci_ss_info_13c1_1001 +#define pci_ss_info_13c1_1001 pci_ss_info_13c1_1001_13c1_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8035 = + {0x1043, 0x8035, pci_subsys_13f6_0111_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_13f6_0111_1043_8035 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1681_a000 = + {0x1681, 0xa000, pci_subsys_13f6_0111_1681_a000, 0}; +#undef pci_ss_info_1681_a000 +#define pci_ss_info_1681_a000 pci_ss_info_13f6_0111_1681_a000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_1712 = + {0x1412, 0x1712, pci_subsys_1412_1712_1412_1712, 0}; +#undef pci_ss_info_1412_1712 +#define pci_ss_info_1412_1712 pci_ss_info_1412_1712_1412_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d630 = + {0x1412, 0xd630, pci_subsys_1412_1712_1412_d630, 0}; +#undef pci_ss_info_1412_d630 +#define pci_ss_info_1412_d630 pci_ss_info_1412_1712_1412_d630 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d631 = + {0x1412, 0xd631, pci_subsys_1412_1712_1412_d631, 0}; +#undef pci_ss_info_1412_d631 +#define pci_ss_info_1412_d631 pci_ss_info_1412_1712_1412_d631 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d632 = + {0x1412, 0xd632, pci_subsys_1412_1712_1412_d632, 0}; +#undef pci_ss_info_1412_d632 +#define pci_ss_info_1412_d632 pci_ss_info_1412_1712_1412_d632 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d633 = + {0x1412, 0xd633, pci_subsys_1412_1712_1412_d633, 0}; +#undef pci_ss_info_1412_d633 +#define pci_ss_info_1412_d633 pci_ss_info_1412_1712_1412_d633 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d634 = + {0x1412, 0xd634, pci_subsys_1412_1712_1412_d634, 0}; +#undef pci_ss_info_1412_d634 +#define pci_ss_info_1412_d634 pci_ss_info_1412_1712_1412_d634 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d635 = + {0x1412, 0xd635, pci_subsys_1412_1712_1412_d635, 0}; +#undef pci_ss_info_1412_d635 +#define pci_ss_info_1412_d635 pci_ss_info_1412_1712_1412_d635 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d637 = + {0x1412, 0xd637, pci_subsys_1412_1712_1412_d637, 0}; +#undef pci_ss_info_1412_d637 +#define pci_ss_info_1412_d637 pci_ss_info_1412_1712_1412_d637 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d638 = + {0x1412, 0xd638, pci_subsys_1412_1712_1412_d638, 0}; +#undef pci_ss_info_1412_d638 +#define pci_ss_info_1412_d638 pci_ss_info_1412_1712_1412_d638 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63b = + {0x1412, 0xd63b, pci_subsys_1412_1712_1412_d63b, 0}; +#undef pci_ss_info_1412_d63b +#define pci_ss_info_1412_d63b pci_ss_info_1412_1712_1412_d63b +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63c = + {0x1412, 0xd63c, pci_subsys_1412_1712_1412_d63c, 0}; +#undef pci_ss_info_1412_d63c +#define pci_ss_info_1412_d63c pci_ss_info_1412_1712_1412_d63c +static const pciSubsystemInfo pci_ss_info_1412_1712_1416_1712 = + {0x1416, 0x1712, pci_subsys_1412_1712_1416_1712, 0}; +#undef pci_ss_info_1416_1712 +#define pci_ss_info_1416_1712 pci_ss_info_1412_1712_1416_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1115 = + {0x153b, 0x1115, pci_subsys_1412_1712_153b_1115, 0}; +#undef pci_ss_info_153b_1115 +#define pci_ss_info_153b_1115 pci_ss_info_1412_1712_153b_1115 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1125 = + {0x153b, 0x1125, pci_subsys_1412_1712_153b_1125, 0}; +#undef pci_ss_info_153b_1125 +#define pci_ss_info_153b_1125 pci_ss_info_1412_1712_153b_1125 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112b = + {0x153b, 0x112b, pci_subsys_1412_1712_153b_112b, 0}; +#undef pci_ss_info_153b_112b +#define pci_ss_info_153b_112b pci_ss_info_1412_1712_153b_112b +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112c = + {0x153b, 0x112c, pci_subsys_1412_1712_153b_112c, 0}; +#undef pci_ss_info_153b_112c +#define pci_ss_info_153b_112c pci_ss_info_1412_1712_153b_112c +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1130 = + {0x153b, 0x1130, pci_subsys_1412_1712_153b_1130, 0}; +#undef pci_ss_info_153b_1130 +#define pci_ss_info_153b_1130 pci_ss_info_1412_1712_153b_1130 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1138 = + {0x153b, 0x1138, pci_subsys_1412_1712_153b_1138, 0}; +#undef pci_ss_info_153b_1138 +#define pci_ss_info_153b_1138 pci_ss_info_1412_1712_153b_1138 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1151 = + {0x153b, 0x1151, pci_subsys_1412_1712_153b_1151, 0}; +#undef pci_ss_info_153b_1151 +#define pci_ss_info_153b_1151 pci_ss_info_1412_1712_153b_1151 +static const pciSubsystemInfo pci_ss_info_1412_1712_16ce_1040 = + {0x16ce, 0x1040, pci_subsys_1412_1712_16ce_1040, 0}; +#undef pci_ss_info_16ce_1040 +#define pci_ss_info_16ce_1040 pci_ss_info_1412_1712_16ce_1040 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_1724 = + {0x1412, 0x1724, pci_subsys_1412_1724_1412_1724, 0}; +#undef pci_ss_info_1412_1724 +#define pci_ss_info_1412_1724 pci_ss_info_1412_1724_1412_1724 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3630 = + {0x1412, 0x3630, pci_subsys_1412_1724_1412_3630, 0}; +#undef pci_ss_info_1412_3630 +#define pci_ss_info_1412_3630 pci_ss_info_1412_1724_1412_3630 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3631 = + {0x1412, 0x3631, pci_subsys_1412_1724_1412_3631, 0}; +#undef pci_ss_info_1412_3631 +#define pci_ss_info_1412_3631 pci_ss_info_1412_1724_1412_3631 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1145 = + {0x153b, 0x1145, pci_subsys_1412_1724_153b_1145, 0}; +#undef pci_ss_info_153b_1145 +#define pci_ss_info_153b_1145 pci_ss_info_1412_1724_153b_1145 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1147 = + {0x153b, 0x1147, pci_subsys_1412_1724_153b_1147, 0}; +#undef pci_ss_info_153b_1147 +#define pci_ss_info_153b_1147 pci_ss_info_1412_1724_153b_1147 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1153 = + {0x153b, 0x1153, pci_subsys_1412_1724_153b_1153, 0}; +#undef pci_ss_info_153b_1153 +#define pci_ss_info_153b_1153 pci_ss_info_1412_1724_153b_1153 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f641 = + {0x270f, 0xf641, pci_subsys_1412_1724_270f_f641, 0}; +#undef pci_ss_info_270f_f641 +#define pci_ss_info_270f_f641 pci_ss_info_1412_1724_270f_f641 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f645 = + {0x270f, 0xf645, pci_subsys_1412_1724_270f_f645, 0}; +#undef pci_ss_info_270f_f645 +#define pci_ss_info_270f_f645 pci_ss_info_1412_1724_270f_f645 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2050 = + {0x131f, 0x2050, pci_subsys_1415_9501_131f_2050, 0}; +#undef pci_ss_info_131f_2050 +#define pci_ss_info_131f_2050 pci_ss_info_1415_9501_131f_2050 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2051 = + {0x131f, 0x2051, pci_subsys_1415_9501_131f_2051, 0}; +#undef pci_ss_info_131f_2051 +#define pci_ss_info_131f_2051 pci_ss_info_1415_9501_131f_2051 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128a = + {0x103c, 0x128a, pci_subsys_14e4_1645_103c_128a, 0}; +#undef pci_ss_info_103c_128a +#define pci_ss_info_103c_128a pci_ss_info_14e4_1645_103c_128a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128b = + {0x103c, 0x128b, pci_subsys_14e4_1645_103c_128b, 0}; +#undef pci_ss_info_103c_128b +#define pci_ss_info_103c_128b pci_ss_info_14e4_1645_103c_128b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12a4 = + {0x103c, 0x12a4, pci_subsys_14e4_1645_103c_12a4, 0}; +#undef pci_ss_info_103c_12a4 +#define pci_ss_info_103c_12a4 pci_ss_info_14e4_1645_103c_12a4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12c1 = + {0x103c, 0x12c1, pci_subsys_14e4_1645_103c_12c1, 0}; +#undef pci_ss_info_103c_12c1 +#define pci_ss_info_103c_12c1 pci_ss_info_14e4_1645_103c_12c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_1300 = + {0x103c, 0x1300, pci_subsys_14e4_1645_103c_1300, 0}; +#undef pci_ss_info_103c_1300 +#define pci_ss_info_103c_1300 pci_ss_info_14e4_1645_103c_1300 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1645_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1645_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8011 = + {0x10a9, 0x8011, pci_subsys_14e4_1645_10a9_8011, 0}; +#undef pci_ss_info_10a9_8011 +#define pci_ss_info_10a9_8011 pci_ss_info_14e4_1645_10a9_8011 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8012 = + {0x10a9, 0x8012, pci_subsys_14e4_1645_10a9_8012, 0}; +#undef pci_ss_info_10a9_8012 +#define pci_ss_info_10a9_8012 pci_ss_info_14e4_1645_10a9_8012 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1647_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1647_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1734_100b = + {0x1734, 0x100b, pci_subsys_14e4_1648_1734_100b, 0}; +#undef pci_ss_info_1734_100b +#define pci_ss_info_1734_100b pci_ss_info_14e4_1648_1734_100b +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3101 = + {0x103c, 0x3101, pci_subsys_14e4_164a_103c_3101, 0}; +#undef pci_ss_info_103c_3101 +#define pci_ss_info_103c_3101 pci_ss_info_14e4_164a_103c_3101 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1653_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1653_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1653_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1654_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1654_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3100 = + {0x103c, 0x3100, pci_subsys_14e4_1654_103c_3100, 0}; +#undef pci_ss_info_103c_3100 +#define pci_ss_info_103c_3100 pci_ss_info_14e4_1654_103c_3100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3226 = + {0x103c, 0x3226, pci_subsys_14e4_1654_103c_3226, 0}; +#undef pci_ss_info_103c_3226 +#define pci_ss_info_103c_3226 pci_ss_info_14e4_1654_103c_3226 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7031 = + {0x103c, 0x7031, pci_subsys_14e4_1659_103c_7031, 0}; +#undef pci_ss_info_103c_7031 +#define pci_ss_info_103c_7031 pci_ss_info_14e4_1659_103c_7031 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7032 = + {0x103c, 0x7032, pci_subsys_14e4_1659_103c_7032, 0}; +#undef pci_ss_info_103c_7032 +#define pci_ss_info_103c_7032 pci_ss_info_14e4_1659_103c_7032 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1734_1061 = + {0x1734, 0x1061, pci_subsys_14e4_1659_1734_1061, 0}; +#undef pci_ss_info_1734_1061 +#define pci_ss_info_1734_1061 pci_ss_info_14e4_1659_1734_1061 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165d_1028_865d = + {0x1028, 0x865d, pci_subsys_14e4_165d_1028_865d, 0}; +#undef pci_ss_info_1028_865d +#define pci_ss_info_1028_865d pci_ss_info_14e4_165d_1028_865d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_088c = + {0x103c, 0x088c, pci_subsys_14e4_165e_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_14e4_165e_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_0890 = + {0x103c, 0x0890, pci_subsys_14e4_165e_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_14e4_165e_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_165e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_165e_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1668_103c_7039 = + {0x103c, 0x7039, pci_subsys_14e4_1668_103c_7039, 0}; +#undef pci_ss_info_103c_7039 +#define pci_ss_info_103c_7039 pci_ss_info_14e4_1668_103c_7039 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0179 = + {0x1028, 0x0179, pci_subsys_14e4_1677_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_14e4_1677_1028_0179 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0182 = + {0x1028, 0x0182, pci_subsys_14e4_1677_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_14e4_1677_1028_0182 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_01ad = + {0x1028, 0x01ad, pci_subsys_14e4_1677_1028_01ad, 0}; +#undef pci_ss_info_1028_01ad +#define pci_ss_info_1028_01ad pci_ss_info_14e4_1677_1028_01ad +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1677_1734_105d = + {0x1734, 0x105d, pci_subsys_14e4_1677_1734_105d, 0}; +#undef pci_ss_info_1734_105d +#define pci_ss_info_1734_105d pci_ss_info_14e4_1677_1734_105d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1696_103c_12bc = + {0x103c, 0x12bc, pci_subsys_14e4_1696_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_14e4_1696_103c_12bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_169c_103c_308b = + {0x103c, 0x308b, pci_subsys_14e4_169c_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_14e4_169c_103c_308b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16aa_103c_3102 = + {0x103c, 0x3102, pci_subsys_14e4_16aa_103c_3102, 0}; +#undef pci_ss_info_103c_3102 +#define pci_ss_info_103c_3102 pci_ss_info_14e4_16aa_103c_3102 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16c7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16c7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16c7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16c7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12c3 = + {0x103c, 0x12c3, pci_subsys_14e4_16c7_103c_12c3, 0}; +#undef pci_ss_info_103c_12c3 +#define pci_ss_info_103c_12c3 pci_ss_info_14e4_16c7_103c_12c3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12ca = + {0x103c, 0x12ca, pci_subsys_14e4_16c7_103c_12ca, 0}; +#undef pci_ss_info_103c_12ca +#define pci_ss_info_103c_12ca pci_ss_info_14e4_16c7_103c_12ca +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0188 = + {0x1028, 0x0188, pci_subsys_14e4_170c_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_14e4_170c_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0196 = + {0x1028, 0x0196, pci_subsys_14e4_170c_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_14e4_170c_1028_0196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_170c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_170c_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_170d_1014_0545 = + {0x1014, 0x0545, pci_subsys_14e4_170d_1014_0545, 0}; +#undef pci_ss_info_1014_0545 +#define pci_ss_info_1014_0545 pci_ss_info_14e4_170d_1014_0545 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4301_1028_0407 = + {0x1028, 0x0407, pci_subsys_14e4_4301_1028_0407, 0}; +#undef pci_ss_info_1028_0407 +#define pci_ss_info_1028_0407 pci_ss_info_14e4_4301_1028_0407 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4301_1043_0120 = + {0x1043, 0x0120, pci_subsys_14e4_4301_1043_0120, 0}; +#undef pci_ss_info_1043_0120 +#define pci_ss_info_1043_0120 pci_ss_info_14e4_4301_1043_0120 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4318_103c_1356 = + {0x103c, 0x1356, pci_subsys_14e4_4318_103c_1356, 0}; +#undef pci_ss_info_103c_1356 +#define pci_ss_info_103c_1356 pci_ss_info_14e4_4318_103c_1356 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0311 = + {0x1468, 0x0311, pci_subsys_14e4_4318_1468_0311, 0}; +#undef pci_ss_info_1468_0311 +#define pci_ss_info_1468_0311 pci_ss_info_14e4_4318_1468_0311 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_0449 = + {0x14e4, 0x0449, pci_subsys_14e4_4318_14e4_0449, 0}; +#undef pci_ss_info_14e4_0449 +#define pci_ss_info_14e4_0449 pci_ss_info_14e4_4318_14e4_0449 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_4318 = + {0x14e4, 0x4318, pci_subsys_14e4_4318_14e4_4318, 0}; +#undef pci_ss_info_14e4_4318 +#define pci_ss_info_14e4_4318 pci_ss_info_14e4_4318_14e4_4318 +static const pciSubsystemInfo pci_ss_info_14e4_4318_16ec_0119 = + {0x16ec, 0x0119, pci_subsys_14e4_4318_16ec_0119, 0}; +#undef pci_ss_info_16ec_0119 +#define pci_ss_info_16ec_0119 pci_ss_info_14e4_4318_16ec_0119 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4320_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4320_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4320_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4320_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12fa = + {0x103c, 0x12fa, pci_subsys_14e4_4320_103c_12fa, 0}; +#undef pci_ss_info_103c_12fa +#define pci_ss_info_103c_12fa pci_ss_info_14e4_4320_103c_12fa +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_1043_100f = + {0x1043, 0x100f, pci_subsys_14e4_4320_1043_100f, 0}; +#undef pci_ss_info_1043_100f +#define pci_ss_info_1043_100f pci_ss_info_14e4_4320_1043_100f +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1057_7025 = + {0x1057, 0x7025, pci_subsys_14e4_4320_1057_7025, 0}; +#undef pci_ss_info_1057_7025 +#define pci_ss_info_1057_7025 pci_ss_info_14e4_4320_1057_7025 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_106b_004e = + {0x106b, 0x004e, pci_subsys_14e4_4320_106b_004e, 0}; +#undef pci_ss_info_106b_004e +#define pci_ss_info_106b_004e pci_ss_info_14e4_4320_106b_004e +static const pciSubsystemInfo pci_ss_info_14e4_4320_14e4_4320 = + {0x14e4, 0x4320, pci_subsys_14e4_4320_14e4_4320, 0}; +#undef pci_ss_info_14e4_4320 +#define pci_ss_info_14e4_4320 pci_ss_info_14e4_4320_14e4_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1737_4320 = + {0x1737, 0x4320, pci_subsys_14e4_4320_1737_4320, 0}; +#undef pci_ss_info_1737_4320 +#define pci_ss_info_1737_4320 pci_ss_info_14e4_4320_1737_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7001 = + {0x1799, 0x7001, pci_subsys_14e4_4320_1799_7001, 0}; +#undef pci_ss_info_1799_7001 +#define pci_ss_info_1799_7001 pci_ss_info_14e4_4320_1799_7001 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7010 = + {0x1799, 0x7010, pci_subsys_14e4_4320_1799_7010, 0}; +#undef pci_ss_info_1799_7010 +#define pci_ss_info_1799_7010 pci_ss_info_14e4_4320_1799_7010 +static const pciSubsystemInfo pci_ss_info_14e4_4320_185f_1220 = + {0x185f, 0x1220, pci_subsys_14e4_4320_185f_1220, 0}; +#undef pci_ss_info_185f_1220 +#define pci_ss_info_185f_1220 pci_ss_info_14e4_4320_185f_1220 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4324_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4324_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4324_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4324_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0003 = + {0x1414, 0x0003, pci_subsys_14e4_4325_1414_0003, 0}; +#undef pci_ss_info_1414_0003 +#define pci_ss_info_1414_0003 pci_ss_info_14e4_4325_1414_0003 +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0004 = + {0x1414, 0x0004, pci_subsys_14e4_4325_1414_0004, 0}; +#undef pci_ss_info_1414_0004 +#define pci_ss_info_1414_0004 pci_ss_info_14e4_4325_1414_0004 +static const pciSubsystemInfo pci_ss_info_14e4_4401_1043_80a8 = + {0x1043, 0x80a8, pci_subsys_14e4_4401_1043_80a8, 0}; +#undef pci_ss_info_1043_80a8 +#define pci_ss_info_1043_80a8 pci_ss_info_14e4_4401_1043_80a8 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2045_14f1_2045 = + {0x14f1, 0x2045, pci_subsys_14f1_2045_14f1_2045, 0}; +#undef pci_ss_info_14f1_2045 +#define pci_ss_info_14f1_2045 pci_ss_info_14f1_2045_14f1_2045 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8800_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8800_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8800_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8800_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8800_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8800_0070_9002 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_00f8 = + {0x1002, 0x00f8, pci_subsys_14f1_8800_1002_00f8, 0}; +#undef pci_ss_info_1002_00f8 +#define pci_ss_info_1002_00f8 pci_ss_info_14f1_8800_1002_00f8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_8800_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8800_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8800_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6613 = + {0x107d, 0x6613, pci_subsys_14f1_8800_107d_6613, 0}; +#undef pci_ss_info_107d_6613 +#define pci_ss_info_107d_6613 pci_ss_info_14f1_8800_107d_6613 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6620 = + {0x107d, 0x6620, pci_subsys_14f1_8800_107d_6620, 0}; +#undef pci_ss_info_107d_6620 +#define pci_ss_info_107d_6620 pci_ss_info_14f1_8800_107d_6620 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8800_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8800_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d003 = + {0x10fc, 0xd003, pci_subsys_14f1_8800_10fc_d003, 0}; +#undef pci_ss_info_10fc_d003 +#define pci_ss_info_10fc_d003 pci_ss_info_14f1_8800_10fc_d003 +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d035 = + {0x10fc, 0xd035, pci_subsys_14f1_8800_10fc_d035, 0}; +#undef pci_ss_info_10fc_d035 +#define pci_ss_info_10fc_d035 pci_ss_info_14f1_8800_10fc_d035 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000b = + {0x1461, 0x000b, pci_subsys_14f1_8800_1461_000b, 0}; +#undef pci_ss_info_1461_000b +#define pci_ss_info_1461_000b pci_ss_info_14f1_8800_1461_000b +static const pciSubsystemInfo pci_ss_info_14f1_8800_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8800_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8800_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14c7_0107 = + {0x14c7, 0x0107, pci_subsys_14f1_8800_14c7_0107, 0}; +#undef pci_ss_info_14c7_0107 +#define pci_ss_info_14c7_0107 pci_ss_info_14f1_8800_14c7_0107 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8800_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8800_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0342 = + {0x14f1, 0x0342, pci_subsys_14f1_8800_14f1_0342, 0}; +#undef pci_ss_info_14f1_0342 +#define pci_ss_info_14f1_0342 pci_ss_info_14f1_8800_14f1_0342 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1540_2580 = + {0x1540, 0x2580, pci_subsys_14f1_8800_1540_2580, 0}; +#undef pci_ss_info_1540_2580 +#define pci_ss_info_1540_2580 pci_ss_info_14f1_8800_1540_2580 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4811 = + {0x1554, 0x4811, pci_subsys_14f1_8800_1554_4811, 0}; +#undef pci_ss_info_1554_4811 +#define pci_ss_info_1554_4811 pci_ss_info_14f1_8800_1554_4811 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8800_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8800_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8800_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8800_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_a8a6 = + {0x17de, 0xa8a6, pci_subsys_14f1_8800_17de_a8a6, 0}; +#undef pci_ss_info_17de_a8a6 +#define pci_ss_info_17de_a8a6 pci_ss_info_14f1_8800_17de_a8a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8800_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8800_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8800_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8800_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8800_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8800_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8800_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8800_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8800_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8800_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8800_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8800_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8800_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8801_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8801_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8801_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8802_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8802_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8802_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8802_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8802_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8802_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8802_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8802_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8802_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8802_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8802_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8802_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8802_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8802_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8802_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8802_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8802_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8802_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8802_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8802_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8802_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8802_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8802_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8802_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8802_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8802_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8802_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8802_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8802_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8802_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8804_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8804_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8804_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8811_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8811_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8811_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8811_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8811_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8811_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8811_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8811_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8811_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8811_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8811_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8811_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8811_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8811_18ac_db00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0c00 = + {0x1522, 0x0c00, pci_subsys_1522_0100_1522_0c00, 0}; +#undef pci_ss_info_1522_0c00 +#define pci_ss_info_1522_0c00 pci_ss_info_1522_0100_1522_0c00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0d00 = + {0x1522, 0x0d00, pci_subsys_1522_0100_1522_0d00, 0}; +#undef pci_ss_info_1522_0d00 +#define pci_ss_info_1522_0d00 pci_ss_info_1522_0100_1522_0d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_1d00 = + {0x1522, 0x1d00, pci_subsys_1522_0100_1522_1d00, 0}; +#undef pci_ss_info_1522_1d00 +#define pci_ss_info_1522_1d00 pci_ss_info_1522_0100_1522_1d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2000 = + {0x1522, 0x2000, pci_subsys_1522_0100_1522_2000, 0}; +#undef pci_ss_info_1522_2000 +#define pci_ss_info_1522_2000 pci_ss_info_1522_0100_1522_2000 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2100 = + {0x1522, 0x2100, pci_subsys_1522_0100_1522_2100, 0}; +#undef pci_ss_info_1522_2100 +#define pci_ss_info_1522_2100 pci_ss_info_1522_0100_1522_2100 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2200 = + {0x1522, 0x2200, pci_subsys_1522_0100_1522_2200, 0}; +#undef pci_ss_info_1522_2200 +#define pci_ss_info_1522_2200 pci_ss_info_1522_0100_1522_2200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2300 = + {0x1522, 0x2300, pci_subsys_1522_0100_1522_2300, 0}; +#undef pci_ss_info_1522_2300 +#define pci_ss_info_1522_2300 pci_ss_info_1522_0100_1522_2300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2400 = + {0x1522, 0x2400, pci_subsys_1522_0100_1522_2400, 0}; +#undef pci_ss_info_1522_2400 +#define pci_ss_info_1522_2400 pci_ss_info_1522_0100_1522_2400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2500 = + {0x1522, 0x2500, pci_subsys_1522_0100_1522_2500, 0}; +#undef pci_ss_info_1522_2500 +#define pci_ss_info_1522_2500 pci_ss_info_1522_0100_1522_2500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2600 = + {0x1522, 0x2600, pci_subsys_1522_0100_1522_2600, 0}; +#undef pci_ss_info_1522_2600 +#define pci_ss_info_1522_2600 pci_ss_info_1522_0100_1522_2600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2700 = + {0x1522, 0x2700, pci_subsys_1522_0100_1522_2700, 0}; +#undef pci_ss_info_1522_2700 +#define pci_ss_info_1522_2700 pci_ss_info_1522_0100_1522_2700 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_005a = + {0x1025, 0x005a, pci_subsys_1524_1410_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1524_1410_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_167b_2102_187e_3406 = + {0x187e, 0x3406, pci_subsys_167b_2102_187e_3406, 0}; +#undef pci_ss_info_187e_3406 +#define pci_ss_info_187e_3406 pci_ss_info_167b_2102_187e_3406 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_168c_0013_1113_d301 = + {0x1113, 0xd301, pci_subsys_168c_0013_1113_d301, 0}; +#undef pci_ss_info_1113_d301 +#define pci_ss_info_1113_d301 pci_ss_info_168c_0013_1113_d301 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3202 = + {0x1186, 0x3202, pci_subsys_168c_0013_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_168c_0013_1186_3202 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3203 = + {0x1186, 0x3203, pci_subsys_168c_0013_1186_3203, 0}; +#undef pci_ss_info_1186_3203 +#define pci_ss_info_1186_3203 pci_ss_info_168c_0013_1186_3203 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a12 = + {0x1186, 0x3a12, pci_subsys_168c_0013_1186_3a12, 0}; +#undef pci_ss_info_1186_3a12 +#define pci_ss_info_1186_3a12 pci_ss_info_168c_0013_1186_3a12 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a13 = + {0x1186, 0x3a13, pci_subsys_168c_0013_1186_3a13, 0}; +#undef pci_ss_info_1186_3a13 +#define pci_ss_info_1186_3a13 pci_ss_info_168c_0013_1186_3a13 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a14 = + {0x1186, 0x3a14, pci_subsys_168c_0013_1186_3a14, 0}; +#undef pci_ss_info_1186_3a14 +#define pci_ss_info_1186_3a14 pci_ss_info_168c_0013_1186_3a14 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a17 = + {0x1186, 0x3a17, pci_subsys_168c_0013_1186_3a17, 0}; +#undef pci_ss_info_1186_3a17 +#define pci_ss_info_1186_3a17 pci_ss_info_168c_0013_1186_3a17 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a18 = + {0x1186, 0x3a18, pci_subsys_168c_0013_1186_3a18, 0}; +#undef pci_ss_info_1186_3a18 +#define pci_ss_info_1186_3a18 pci_ss_info_168c_0013_1186_3a18 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a63 = + {0x1186, 0x3a63, pci_subsys_168c_0013_1186_3a63, 0}; +#undef pci_ss_info_1186_3a63 +#define pci_ss_info_1186_3a63 pci_ss_info_168c_0013_1186_3a63 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a94 = + {0x1186, 0x3a94, pci_subsys_168c_0013_1186_3a94, 0}; +#undef pci_ss_info_1186_3a94 +#define pci_ss_info_1186_3a94 pci_ss_info_168c_0013_1186_3a94 +static const pciSubsystemInfo pci_ss_info_168c_0013_1385_4d00 = + {0x1385, 0x4d00, pci_subsys_168c_0013_1385_4d00, 0}; +#undef pci_ss_info_1385_4d00 +#define pci_ss_info_1385_4d00 pci_ss_info_168c_0013_1385_4d00 +static const pciSubsystemInfo pci_ss_info_168c_0013_1458_e911 = + {0x1458, 0xe911, pci_subsys_168c_0013_1458_e911, 0}; +#undef pci_ss_info_1458_e911 +#define pci_ss_info_1458_e911 pci_ss_info_168c_0013_1458_e911 +static const pciSubsystemInfo pci_ss_info_168c_0013_14b7_0a60 = + {0x14b7, 0x0a60, pci_subsys_168c_0013_14b7_0a60, 0}; +#undef pci_ss_info_14b7_0a60 +#define pci_ss_info_14b7_0a60 pci_ss_info_168c_0013_14b7_0a60 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_0013 = + {0x168c, 0x0013, pci_subsys_168c_0013_168c_0013, 0}; +#undef pci_ss_info_168c_0013 +#define pci_ss_info_168c_0013 pci_ss_info_168c_0013_168c_0013 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1025 = + {0x168c, 0x1025, pci_subsys_168c_0013_168c_1025, 0}; +#undef pci_ss_info_168c_1025 +#define pci_ss_info_168c_1025 pci_ss_info_168c_0013_168c_1025 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1027 = + {0x168c, 0x1027, pci_subsys_168c_0013_168c_1027, 0}; +#undef pci_ss_info_168c_1027 +#define pci_ss_info_168c_1027 pci_ss_info_168c_0013_168c_1027 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2026 = + {0x168c, 0x2026, pci_subsys_168c_0013_168c_2026, 0}; +#undef pci_ss_info_168c_2026 +#define pci_ss_info_168c_2026 pci_ss_info_168c_0013_168c_2026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2041 = + {0x168c, 0x2041, pci_subsys_168c_0013_168c_2041, 0}; +#undef pci_ss_info_168c_2041 +#define pci_ss_info_168c_2041 pci_ss_info_168c_0013_168c_2041 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2042 = + {0x168c, 0x2042, pci_subsys_168c_0013_168c_2042, 0}; +#undef pci_ss_info_168c_2042 +#define pci_ss_info_168c_2042 pci_ss_info_168c_0013_168c_2042 +static const pciSubsystemInfo pci_ss_info_168c_0013_16ab_7302 = + {0x16ab, 0x7302, pci_subsys_168c_0013_16ab_7302, 0}; +#undef pci_ss_info_16ab_7302 +#define pci_ss_info_16ab_7302 pci_ss_info_168c_0013_16ab_7302 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a15 = + {0x1186, 0x3a15, pci_subsys_168c_001a_1186_3a15, 0}; +#undef pci_ss_info_1186_3a15 +#define pci_ss_info_1186_3a15 pci_ss_info_168c_001a_1186_3a15 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a16 = + {0x1186, 0x3a16, pci_subsys_168c_001a_1186_3a16, 0}; +#undef pci_ss_info_1186_3a16 +#define pci_ss_info_1186_3a16 pci_ss_info_168c_001a_1186_3a16 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a23 = + {0x1186, 0x3a23, pci_subsys_168c_001a_1186_3a23, 0}; +#undef pci_ss_info_1186_3a23 +#define pci_ss_info_1186_3a23 pci_ss_info_168c_001a_1186_3a23 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a24 = + {0x1186, 0x3a24, pci_subsys_168c_001a_1186_3a24, 0}; +#undef pci_ss_info_1186_3a24 +#define pci_ss_info_1186_3a24 pci_ss_info_168c_001a_1186_3a24 +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_1052 = + {0x168c, 0x1052, pci_subsys_168c_001a_168c_1052, 0}; +#undef pci_ss_info_168c_1052 +#define pci_ss_info_168c_1052 pci_ss_info_168c_001a_168c_1052 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a19 = + {0x1186, 0x3a19, pci_subsys_168c_001b_1186_3a19, 0}; +#undef pci_ss_info_1186_3a19 +#define pci_ss_info_1186_3a19 pci_ss_info_168c_001b_1186_3a19 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a22 = + {0x1186, 0x3a22, pci_subsys_168c_001b_1186_3a22, 0}; +#undef pci_ss_info_1186_3a22 +#define pci_ss_info_1186_3a22 pci_ss_info_168c_001b_1186_3a22 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0015 = + {0x1737, 0x0015, pci_subsys_1737_1032_1737_0015, 0}; +#undef pci_ss_info_1737_0015 +#define pci_ss_info_1737_0015 pci_ss_info_1737_1032_1737_0015 +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0024 = + {0x1737, 0x0024, pci_subsys_1737_1032_1737_0024, 0}; +#undef pci_ss_info_1737_0024 +#define pci_ss_info_1737_0024 pci_ss_info_1737_1032_1737_0024 +static const pciSubsystemInfo pci_ss_info_1737_1064_1737_0016 = + {0x1737, 0x0016, pci_subsys_1737_1064_1737_0016, 0}; +#undef pci_ss_info_1737_0016 +#define pci_ss_info_1737_0016 pci_ss_info_1737_1064_1737_0016 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_17d3_5831_103c_12d5 = + {0x103c, 0x12d5, pci_subsys_17d3_5831_103c_12d5, 0}; +#undef pci_ss_info_103c_12d5 +#define pci_ss_info_103c_12d5 pci_ss_info_17d3_5831_103c_12d5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17fe_2220_17fe_2220 = + {0x17fe, 0x2220, pci_subsys_17fe_2220_17fe_2220, 0}; +#undef pci_ss_info_17fe_2220 +#define pci_ss_info_17fe_2220 pci_ss_info_17fe_2220_17fe_2220 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1814_0101_1043_0127 = + {0x1043, 0x0127, pci_subsys_1814_0101_1043_0127, 0}; +#undef pci_ss_info_1043_0127 +#define pci_ss_info_1043_0127 pci_ss_info_1814_0101_1043_0127 +static const pciSubsystemInfo pci_ss_info_1814_0101_1462_6828 = + {0x1462, 0x6828, pci_subsys_1814_0101_1462_6828, 0}; +#undef pci_ss_info_1462_6828 +#define pci_ss_info_1462_6828 pci_ss_info_1814_0101_1462_6828 +static const pciSubsystemInfo pci_ss_info_1814_0201_1043_130f = + {0x1043, 0x130f, pci_subsys_1814_0201_1043_130f, 0}; +#undef pci_ss_info_1043_130f +#define pci_ss_info_1043_130f pci_ss_info_1814_0201_1043_130f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001e = + {0x1371, 0x001e, pci_subsys_1814_0201_1371_001e, 0}; +#undef pci_ss_info_1371_001e +#define pci_ss_info_1371_001e pci_ss_info_1814_0201_1371_001e +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001f = + {0x1371, 0x001f, pci_subsys_1814_0201_1371_001f, 0}; +#undef pci_ss_info_1371_001f +#define pci_ss_info_1371_001f pci_ss_info_1814_0201_1371_001f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_0020 = + {0x1371, 0x0020, pci_subsys_1814_0201_1371_0020, 0}; +#undef pci_ss_info_1371_0020 +#define pci_ss_info_1371_0020 pci_ss_info_1814_0201_1371_0020 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e381 = + {0x1458, 0xe381, pci_subsys_1814_0201_1458_e381, 0}; +#undef pci_ss_info_1458_e381 +#define pci_ss_info_1458_e381 pci_ss_info_1814_0201_1458_e381 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e931 = + {0x1458, 0xe931, pci_subsys_1814_0201_1458_e931, 0}; +#undef pci_ss_info_1458_e931 +#define pci_ss_info_1458_e931 pci_ss_info_1814_0201_1458_e931 +static const pciSubsystemInfo pci_ss_info_1814_0201_1462_6835 = + {0x1462, 0x6835, pci_subsys_1814_0201_1462_6835, 0}; +#undef pci_ss_info_1462_6835 +#define pci_ss_info_1462_6835 pci_ss_info_1814_0201_1462_6835 +static const pciSubsystemInfo pci_ss_info_1814_0201_1737_0032 = + {0x1737, 0x0032, pci_subsys_1814_0201_1737_0032, 0}; +#undef pci_ss_info_1737_0032 +#define pci_ss_info_1737_0032 pci_ss_info_1814_0201_1737_0032 +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_700a = + {0x1799, 0x700a, pci_subsys_1814_0201_1799_700a, 0}; +#undef pci_ss_info_1799_700a +#define pci_ss_info_1799_700a pci_ss_info_1814_0201_1799_700a +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_701a = + {0x1799, 0x701a, pci_subsys_1814_0201_1799_701a, 0}; +#undef pci_ss_info_1799_701a +#define pci_ss_info_1799_701a pci_ss_info_1814_0201_1799_701a +static const pciSubsystemInfo pci_ss_info_1814_0201_185f_22a0 = + {0x185f, 0x22a0, pci_subsys_1814_0201_185f_22a0, 0}; +#undef pci_ss_info_185f_22a0 +#define pci_ss_info_185f_22a0 pci_ss_info_1814_0201_185f_22a0 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c006_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c006_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c006_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c006_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c006_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c006_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c006_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c006_18ec_d004 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c058_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c058_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c058_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c058_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c058_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c058_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c058_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c058_18ec_d004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_3388_0021_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_3388_0021_4c53_1050 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_3388_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_3388_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_3388_0021_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_3388_0021_4c53_1090 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_3388_0021_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_3388_0021_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3010 = + {0x4c53, 0x3010, pci_subsys_3388_0021_4c53_3010, 0}; +#undef pci_ss_info_4c53_3010 +#define pci_ss_info_4c53_3010 pci_ss_info_3388_0021_4c53_3010 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3011 = + {0x4c53, 0x3011, pci_subsys_3388_0021_4c53_3011, 0}; +#undef pci_ss_info_4c53_3011 +#define pci_ss_info_4c53_3011 pci_ss_info_3388_0021_4c53_3011 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_4000 = + {0x4c53, 0x4000, pci_subsys_3388_0021_4c53_4000, 0}; +#undef pci_ss_info_4c53_4000 +#define pci_ss_info_4c53_4000 pci_ss_info_3388_0021_4c53_4000 +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0002_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0002_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0002_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0003_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0003_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0003_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0006_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0006_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0006_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0006_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0008_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0008_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0008_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0009_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0009_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_3d3d_0009_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_3d3d_0009_13e9_1000 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4009 = + {0x0070, 0x4009, pci_subsys_4444_0016_0070_4009, 0}; +#undef pci_ss_info_0070_4009 +#define pci_ss_info_0070_4009 pci_ss_info_4444_0016_0070_4009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8003 = + {0x0070, 0x8003, pci_subsys_4444_0016_0070_8003, 0}; +#undef pci_ss_info_0070_8003 +#define pci_ss_info_0070_8003 pci_ss_info_4444_0016_0070_8003 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4000 = + {0x0070, 0x4000, pci_subsys_4444_0803_0070_4000, 0}; +#undef pci_ss_info_0070_4000 +#define pci_ss_info_0070_4000 pci_ss_info_4444_0803_0070_4000 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0803_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0803_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3cf = + {0x1461, 0xa3cf, pci_subsys_4444_0803_1461_a3cf, 0}; +#undef pci_ss_info_1461_a3cf +#define pci_ss_info_1461_a3cf pci_ss_info_4444_0803_1461_a3cf +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3000 = + {0x4c53, 0x3000, pci_subsys_4c53_0000_4c53_3000, 0}; +#undef pci_ss_info_4c53_3000 +#define pci_ss_info_4c53_3000 pci_ss_info_4c53_0000_4c53_3000 +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3001 = + {0x4c53, 0x3001, pci_subsys_4c53_0000_4c53_3001, 0}; +#undef pci_ss_info_4c53_3001 +#define pci_ss_info_4c53_3001 pci_ss_info_4c53_0000_4c53_3001 +static const pciSubsystemInfo pci_ss_info_4c53_0001_4c53_3002 = + {0x4c53, 0x3002, pci_subsys_4c53_0001_4c53_3002, 0}; +#undef pci_ss_info_4c53_3002 +#define pci_ss_info_4c53_3002 pci_ss_info_4c53_0001_4c53_3002 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8110 = + {0x1033, 0x8110, pci_subsys_5333_8a22_1033_8110, 0}; +#undef pci_ss_info_1033_8110 +#define pci_ss_info_1033_8110 pci_ss_info_5333_8a22_1033_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c12_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c12_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c12_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01af = + {0x8086, 0x01af, pci_subsys_8086_0600_8086_01af, 0}; +#undef pci_ss_info_8086_01af +#define pci_ss_info_8086_01af pci_ss_info_8086_0600_8086_01af +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01c1 = + {0x8086, 0x01c1, pci_subsys_8086_0600_8086_01c1, 0}; +#undef pci_ss_info_8086_01c1 +#define pci_ss_info_8086_01c1 pci_ss_info_8086_0600_8086_01c1 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01f7 = + {0x8086, 0x01f7, pci_subsys_8086_0600_8086_01f7, 0}; +#undef pci_ss_info_8086_01f7 +#define pci_ss_info_8086_01f7 pci_ss_info_8086_0600_8086_01f7 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1001_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1001_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_1008_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_1008_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_1008_1028_011c = + {0x1028, 0x011c, pci_subsys_8086_1008_1028_011c, 0}; +#undef pci_ss_info_1028_011c +#define pci_ss_info_1028_011c pci_ss_info_8086_1008_1028_011c +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_3108 = + {0x8086, 0x3108, pci_subsys_8086_1008_8086_3108, 0}; +#undef pci_ss_info_8086_3108 +#define pci_ss_info_8086_3108 pci_ss_info_8086_1008_8086_3108 +static const pciSubsystemInfo pci_ss_info_8086_1009_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1009_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1009_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100d_1028_0123 = + {0x1028, 0x0123, pci_subsys_8086_100d_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_8086_100d_1028_0123 +static const pciSubsystemInfo pci_ss_info_8086_100d_1079_891f = + {0x1079, 0x891f, pci_subsys_8086_100d_1079_891f, 0}; +#undef pci_ss_info_1079_891f +#define pci_ss_info_1079_891f pci_ss_info_8086_100d_1079_891f +static const pciSubsystemInfo pci_ss_info_8086_100d_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_100d_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_100d_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_100d_8086_110d = + {0x8086, 0x110d, pci_subsys_8086_100d_8086_110d, 0}; +#undef pci_ss_info_8086_110d +#define pci_ss_info_8086_110d pci_ss_info_8086_100d_8086_110d +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_100e_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_100e_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_100e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_100e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_100e_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_100e_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_100e_1024_0134 = + {0x1024, 0x0134, pci_subsys_8086_100e_1024_0134, 0}; +#undef pci_ss_info_1024_0134 +#define pci_ss_info_1024_0134 pci_ss_info_8086_100e_1024_0134 +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_002e = + {0x1028, 0x002e, pci_subsys_8086_100e_1028_002e, 0}; +#undef pci_ss_info_1028_002e +#define pci_ss_info_1028_002e pci_ss_info_8086_100e_1028_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0151 = + {0x1028, 0x0151, pci_subsys_8086_100e_1028_0151, 0}; +#undef pci_ss_info_1028_0151 +#define pci_ss_info_1028_0151 pci_ss_info_8086_100e_1028_0151 +static const pciSubsystemInfo pci_ss_info_8086_100e_107b_8920 = + {0x107b, 0x8920, pci_subsys_8086_100e_107b_8920, 0}; +#undef pci_ss_info_107b_8920 +#define pci_ss_info_107b_8920 pci_ss_info_8086_100e_107b_8920 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_100e_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_100e_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_100e_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_100e_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_100f_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_100f_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_028e = + {0x1014, 0x028e, pci_subsys_8086_100f_1014_028e, 0}; +#undef pci_ss_info_1014_028e +#define pci_ss_info_1014_028e pci_ss_info_8086_100f_1014_028e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_100f_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_100f_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_0e11_00db = + {0x0e11, 0x00db, pci_subsys_8086_1010_0e11_00db, 0}; +#undef pci_ss_info_0e11_00db +#define pci_ss_info_0e11_00db pci_ss_info_8086_1010_0e11_00db +static const pciSubsystemInfo pci_ss_info_8086_1010_1014_027c = + {0x1014, 0x027c, pci_subsys_8086_1010_1014_027c, 0}; +#undef pci_ss_info_1014_027c +#define pci_ss_info_1014_027c pci_ss_info_8086_1010_1014_027c +static const pciSubsystemInfo pci_ss_info_8086_1010_18fb_7872 = + {0x18fb, 0x7872, pci_subsys_8086_1010_18fb_7872, 0}; +#undef pci_ss_info_18fb_7872 +#define pci_ss_info_18fb_7872 pci_ss_info_8086_1010_18fb_7872 +static const pciSubsystemInfo pci_ss_info_8086_1010_1fc1_0026 = + {0x1fc1, 0x0026, pci_subsys_8086_1010_1fc1_0026, 0}; +#undef pci_ss_info_1fc1_0026 +#define pci_ss_info_1fc1_0026 pci_ss_info_8086_1010_1fc1_0026 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1010_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1010_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_1010_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_1010_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1010_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1010_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_1010_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_1010_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_1010_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_1010_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_1011_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1011_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1011_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1011_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1011_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1012_0e11_00dc = + {0x0e11, 0x00dc, pci_subsys_8086_1012_0e11_00dc, 0}; +#undef pci_ss_info_0e11_00dc +#define pci_ss_info_0e11_00dc pci_ss_info_8086_1012_0e11_00dc +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1013_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1013_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1013_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1013_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1113 = + {0x8086, 0x1113, pci_subsys_8086_1013_8086_1113, 0}; +#undef pci_ss_info_8086_1113 +#define pci_ss_info_8086_1113 pci_ss_info_8086_1013_8086_1113 +static const pciSubsystemInfo pci_ss_info_8086_1016_1014_052c = + {0x1014, 0x052c, pci_subsys_8086_1016_1014_052c, 0}; +#undef pci_ss_info_1014_052c +#define pci_ss_info_1014_052c pci_ss_info_8086_1016_1014_052c +static const pciSubsystemInfo pci_ss_info_8086_1016_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1016_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1016_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1016_8086_1016 = + {0x8086, 0x1016, pci_subsys_8086_1016_8086_1016, 0}; +#undef pci_ss_info_8086_1016 +#define pci_ss_info_8086_1016 pci_ss_info_8086_1016_8086_1016 +static const pciSubsystemInfo pci_ss_info_8086_1017_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1017_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1017_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1018_8086_1018 = + {0x8086, 0x1018, pci_subsys_8086_1018_8086_1018, 0}; +#undef pci_ss_info_8086_1018 +#define pci_ss_info_8086_1018 pci_ss_info_8086_1018_8086_1018 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_1019 = + {0x1458, 0x1019, pci_subsys_8086_1019_1458_1019, 0}; +#undef pci_ss_info_1458_1019 +#define pci_ss_info_1458_1019 pci_ss_info_8086_1019_1458_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_e000 = + {0x1458, 0xe000, pci_subsys_8086_1019_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_8086_1019_1458_e000 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_1019 = + {0x8086, 0x1019, pci_subsys_8086_1019_8086_1019, 0}; +#undef pci_ss_info_8086_1019 +#define pci_ss_info_8086_1019 pci_ss_info_8086_1019_8086_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_301f = + {0x8086, 0x301f, pci_subsys_8086_1019_8086_301f, 0}; +#undef pci_ss_info_8086_301f +#define pci_ss_info_8086_301f pci_ss_info_8086_1019_8086_301f +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1019_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1019_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_101d_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_101d_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_101d_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_101e_1014_0549 = + {0x1014, 0x0549, pci_subsys_8086_101e_1014_0549, 0}; +#undef pci_ss_info_1014_0549 +#define pci_ss_info_1014_0549 pci_ss_info_8086_101e_1014_0549 +static const pciSubsystemInfo pci_ss_info_8086_101e_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_101e_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_101e_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_101e_8086_101e = + {0x8086, 0x101e, pci_subsys_8086_101e_8086_101e, 0}; +#undef pci_ss_info_8086_101e +#define pci_ss_info_8086_101e pci_ss_info_8086_101e_8086_101e +static const pciSubsystemInfo pci_ss_info_8086_1026_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_1026_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_1026_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1026_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1026_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1026_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1026_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1026_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1026_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1026 = + {0x8086, 0x1026, pci_subsys_8086_1026_8086_1026, 0}; +#undef pci_ss_info_8086_1026 +#define pci_ss_info_8086_1026 pci_ss_info_8086_1026_8086_1026 +static const pciSubsystemInfo pci_ss_info_8086_1027_103c_3103 = + {0x103c, 0x3103, pci_subsys_8086_1027_103c_3103, 0}; +#undef pci_ss_info_103c_3103 +#define pci_ss_info_103c_3103 pci_ss_info_8086_1027_103c_3103 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1027_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1027_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1027_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1027_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1027_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1027_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1027 = + {0x8086, 0x1027, pci_subsys_8086_1027_8086_1027, 0}; +#undef pci_ss_info_8086_1027 +#define pci_ss_info_8086_1027 pci_ss_info_8086_1027_8086_1027 +static const pciSubsystemInfo pci_ss_info_8086_1028_8086_1028 = + {0x8086, 0x1028, pci_subsys_8086_1028_8086_1028, 0}; +#undef pci_ss_info_8086_1028 +#define pci_ss_info_8086_1028 pci_ss_info_8086_1028_8086_1028 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1031_813c_104d = + {0x813c, 0x104d, pci_subsys_8086_1031_813c_104d, 0}; +#undef pci_ss_info_813c_104d +#define pci_ss_info_813c_104d pci_ss_info_8086_1031_813c_104d +static const pciSubsystemInfo pci_ss_info_8086_1038_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_8086_1038_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_8086_1038_0e11_0098 +static const pciSubsystemInfo pci_ss_info_8086_1039_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_1039_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_1039_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1043_8086_2527 = + {0x8086, 0x2527, pci_subsys_8086_1043_8086_2527, 0}; +#undef pci_ss_info_8086_2527 +#define pci_ss_info_8086_2527 pci_ss_info_8086_1043_8086_2527 +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a01f = + {0x8086, 0xa01f, pci_subsys_8086_1048_8086_a01f, 0}; +#undef pci_ss_info_8086_a01f +#define pci_ss_info_8086_a01f pci_ss_info_8086_1048_8086_a01f +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a11f = + {0x8086, 0xa11f, pci_subsys_8086_1048_8086_a11f, 0}; +#undef pci_ss_info_8086_a11f +#define pci_ss_info_8086_a11f pci_ss_info_8086_1048_8086_a11f +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_728c = + {0x1462, 0x728c, pci_subsys_8086_1050_1462_728c, 0}; +#undef pci_ss_info_1462_728c +#define pci_ss_info_1462_728c pci_ss_info_8086_1050_1462_728c +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_758c = + {0x1462, 0x758c, pci_subsys_8086_1050_1462_758c, 0}; +#undef pci_ss_info_1462_758c +#define pci_ss_info_1462_758c pci_ss_info_8086_1050_1462_758c +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3020 = + {0x8086, 0x3020, pci_subsys_8086_1050_8086_3020, 0}; +#undef pci_ss_info_8086_3020 +#define pci_ss_info_8086_3020 pci_ss_info_8086_1050_8086_3020 +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_302f = + {0x8086, 0x302f, pci_subsys_8086_1050_8086_302f, 0}; +#undef pci_ss_info_8086_302f +#define pci_ss_info_8086_302f pci_ss_info_8086_1050_8086_302f +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1050_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1050_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_1075_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1075_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1075_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_0075 = + {0x8086, 0x0075, pci_subsys_8086_1075_8086_0075, 0}; +#undef pci_ss_info_8086_0075 +#define pci_ss_info_8086_0075 pci_ss_info_8086_1075_8086_0075 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_1075 = + {0x8086, 0x1075, pci_subsys_8086_1075_8086_1075, 0}; +#undef pci_ss_info_8086_1075 +#define pci_ss_info_8086_1075 pci_ss_info_8086_1075_8086_1075 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1076_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1076_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_1076_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_1076_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_0076 = + {0x8086, 0x0076, pci_subsys_8086_1076_8086_0076, 0}; +#undef pci_ss_info_8086_0076 +#define pci_ss_info_8086_0076 pci_ss_info_8086_1076_8086_0076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1076 = + {0x8086, 0x1076, pci_subsys_8086_1076_8086_1076, 0}; +#undef pci_ss_info_8086_1076 +#define pci_ss_info_8086_1076 pci_ss_info_8086_1076_8086_1076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1176 = + {0x8086, 0x1176, pci_subsys_8086_1076_8086_1176, 0}; +#undef pci_ss_info_8086_1176 +#define pci_ss_info_8086_1176 pci_ss_info_8086_1076_8086_1176 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1276 = + {0x8086, 0x1276, pci_subsys_8086_1076_8086_1276, 0}; +#undef pci_ss_info_8086_1276 +#define pci_ss_info_8086_1276 pci_ss_info_8086_1076_8086_1276 +static const pciSubsystemInfo pci_ss_info_8086_1077_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1077_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1077_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_0077 = + {0x8086, 0x0077, pci_subsys_8086_1077_8086_0077, 0}; +#undef pci_ss_info_8086_0077 +#define pci_ss_info_8086_0077 pci_ss_info_8086_1077_8086_0077 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_1077 = + {0x8086, 0x1077, pci_subsys_8086_1077_8086_1077, 0}; +#undef pci_ss_info_8086_1077 +#define pci_ss_info_8086_1077 pci_ss_info_8086_1077_8086_1077 +static const pciSubsystemInfo pci_ss_info_8086_1078_8086_1078 = + {0x8086, 0x1078, pci_subsys_8086_1078_8086_1078, 0}; +#undef pci_ss_info_8086_1078 +#define pci_ss_info_8086_1078 pci_ss_info_8086_1078_8086_1078 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12a6 = + {0x103c, 0x12a6, pci_subsys_8086_1079_103c_12a6, 0}; +#undef pci_ss_info_103c_12a6 +#define pci_ss_info_103c_12a6 pci_ss_info_8086_1079_103c_12a6 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12cf = + {0x103c, 0x12cf, pci_subsys_8086_1079_103c_12cf, 0}; +#undef pci_ss_info_103c_12cf +#define pci_ss_info_103c_12cf pci_ss_info_8086_1079_103c_12cf +static const pciSubsystemInfo pci_ss_info_8086_1079_1fc1_0027 = + {0x1fc1, 0x0027, pci_subsys_8086_1079_1fc1_0027, 0}; +#undef pci_ss_info_1fc1_0027 +#define pci_ss_info_1fc1_0027 pci_ss_info_8086_1079_1fc1_0027 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1079_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1079_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_1079_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_1079_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_0079 = + {0x8086, 0x0079, pci_subsys_8086_1079_8086_0079, 0}; +#undef pci_ss_info_8086_0079 +#define pci_ss_info_8086_0079 pci_ss_info_8086_1079_8086_0079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1079 = + {0x8086, 0x1079, pci_subsys_8086_1079_8086_1079, 0}; +#undef pci_ss_info_8086_1079 +#define pci_ss_info_8086_1079 pci_ss_info_8086_1079_8086_1079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1179 = + {0x8086, 0x1179, pci_subsys_8086_1079_8086_1179, 0}; +#undef pci_ss_info_8086_1179 +#define pci_ss_info_8086_1179 pci_ss_info_8086_1079_8086_1179 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_117a = + {0x8086, 0x117a, pci_subsys_8086_1079_8086_117a, 0}; +#undef pci_ss_info_8086_117a +#define pci_ss_info_8086_117a pci_ss_info_8086_1079_8086_117a +static const pciSubsystemInfo pci_ss_info_8086_107a_103c_12a8 = + {0x103c, 0x12a8, pci_subsys_8086_107a_103c_12a8, 0}; +#undef pci_ss_info_103c_12a8 +#define pci_ss_info_103c_12a8 pci_ss_info_8086_107a_103c_12a8 +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_107a = + {0x8086, 0x107a, pci_subsys_8086_107a_8086_107a, 0}; +#undef pci_ss_info_8086_107a +#define pci_ss_info_8086_107a pci_ss_info_8086_107a_8086_107a +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_127a = + {0x8086, 0x127a, pci_subsys_8086_107a_8086_127a, 0}; +#undef pci_ss_info_8086_127a +#define pci_ss_info_8086_127a pci_ss_info_8086_107a_8086_127a +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_007b = + {0x8086, 0x007b, pci_subsys_8086_107b_8086_007b, 0}; +#undef pci_ss_info_8086_007b +#define pci_ss_info_8086_007b pci_ss_info_8086_107b_8086_007b +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_107b = + {0x8086, 0x107b, pci_subsys_8086_107b_8086_107b, 0}; +#undef pci_ss_info_8086_107b +#define pci_ss_info_8086_107b pci_ss_info_8086_107b_8086_107b +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1130_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1130_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1130_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1130_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1132_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1132_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_1132_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_1132_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1132_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1132_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_1209_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_1209_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_1209_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_1209_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1070 = + {0x4c53, 0x1070, pci_subsys_8086_1209_4c53_1070, 0}; +#undef pci_ss_info_4c53_1070 +#define pci_ss_info_4c53_1070 pci_ss_info_8086_1209_4c53_1070 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_00ce = + {0x1028, 0x00ce, pci_subsys_8086_1229_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_8086_1229_1028_00ce +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_108e_10cf = + {0x108e, 0x10cf, pci_subsys_8086_1229_108e_10cf, 0}; +#undef pci_ss_info_108e_10cf +#define pci_ss_info_108e_10cf pci_ss_info_8086_1229_108e_10cf +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_110a_008b = + {0x110a, 0x008b, pci_subsys_8086_1229_110a_008b, 0}; +#undef pci_ss_info_110a_008b +#define pci_ss_info_110a_008b pci_ss_info_8086_1229_110a_008b +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_8086_1229_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_8086_1229_13e9_1000 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1229_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1229_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_1229_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_1229_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3411 = + {0x8086, 0x3411, pci_subsys_8086_1229_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_8086_1229_8086_3411 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1461_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1461_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1461_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_8086_1960_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_8086_1960_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_8086_1960_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_8086_1960_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1040 = + {0xe4bf, 0x1040, pci_subsys_8086_1960_e4bf_1040, 0}; +#undef pci_ss_info_e4bf_1040 +#define pci_ss_info_e4bf_1040 pci_ss_info_8086_1960_e4bf_1040 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_3100 = + {0xe4bf, 0x3100, pci_subsys_8086_1960_e4bf_3100, 0}; +#undef pci_ss_info_e4bf_3100 +#define pci_ss_info_e4bf_3100 pci_ss_info_8086_1960_e4bf_3100 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1a30_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_1a30_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_1a30_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_110a_0051 = + {0x110a, 0x0051, pci_subsys_8086_2415_110a_0051, 0}; +#undef pci_ss_info_110a_0051 +#define pci_ss_info_110a_0051 pci_ss_info_8086_2415_110a_0051 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2415_1734_1025 = + {0x1734, 0x1025, pci_subsys_8086_2415_1734_1025, 0}; +#undef pci_ss_info_1734_1025 +#define pci_ss_info_1734_1025 pci_ss_info_8086_2415_1734_1025 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2442_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2442_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2442_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2442_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2442_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2442_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2442_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2442_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2442_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2443_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2443_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2443_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2443_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2443_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2443_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2444_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2444_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2444_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2444_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2444_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2444_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2444_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2445_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2445_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2448_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2448_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2448_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2448_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_2448_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_2448_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_2449_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_2449_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2449_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2449_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_2449_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_2449_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1179_ff01 = + {0x1179, 0xff01, pci_subsys_8086_2449_1179_ff01, 0}; +#undef pci_ss_info_1179_ff01 +#define pci_ss_info_1179_ff01 pci_ss_info_8086_2449_1179_ff01 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_244b_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_244b_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_244b_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_244b_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_244b_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_244b_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_244e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_244e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_244e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2482_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2482_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2482_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2482_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2482_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_2482_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_2482_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2484_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2484_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1013_5959 = + {0x1013, 0x5959, pci_subsys_8086_2485_1013_5959, 0}; +#undef pci_ss_info_1013_5959 +#define pci_ss_info_1013_5959 pci_ss_info_8086_2485_1013_5959 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_101f_1025 = + {0x101f, 0x1025, pci_subsys_8086_2486_101f_1025, 0}; +#undef pci_ss_info_101f_1025 +#define pci_ss_info_101f_1025 pci_ss_info_8086_2486_101f_1025 +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_2486_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_2486_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2487_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2487_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_248a_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_248a_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_248a_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_248a_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c0_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c0_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c2_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c2_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c2_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c2_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c2_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c2_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c2_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c2_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c2_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c2_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c2_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c2_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c2_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c2_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c2_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c2_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c2_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c2_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c2_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c2_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c2_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c2_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c2_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c2_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c2_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c2_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c3_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c3_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c3_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c3_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c3_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c3_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c3_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c3_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c3_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c3_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c3_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c3_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c3_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24c3_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24c3_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c3_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c3_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c3_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c3_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c3_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c4_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c4_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c4_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c4_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c4_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c4_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c4_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c4_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c4_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c4_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c4_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c4_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c4_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c4_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c4_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c4_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c4_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c4_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c4_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c4_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c4_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c4_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c4_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c5_0e11_00b8 = + {0x0e11, 0x00b8, pci_subsys_8086_24c5_0e11_00b8, 0}; +#undef pci_ss_info_0e11_00b8 +#define pci_ss_info_0e11_00b8 pci_ss_info_8086_24c5_0e11_00b8 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c5_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c5_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c5_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c5_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24c5_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24c5_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c5_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c5_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c5_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c5_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c5_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c5_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c5_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c5_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c5_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c5_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24c5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24c5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c5_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c5_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c6_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c6_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c6_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c6_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c6_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c6_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c6_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c6_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c6_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c6_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c6_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c7_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c7_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c7_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c7_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c7_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c7_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c7_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c7_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c7_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c7_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c7_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c7_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c7_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c7_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c7_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c7_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c7_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c7_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c7_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c7_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c7_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c7_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c7_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c7_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24ca_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24ca_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24ca_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24ca_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24ca_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24ca_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24ca_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24ca_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24ca_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24ca_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24ca_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24ca_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24ca_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24ca_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24ca_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24ca_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24ca_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cb_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cb_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cb_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cb_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24cb_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24cb_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cb_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cb_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24cc_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cc_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cc_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cd_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cd_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24cd_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24cd_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cd_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cd_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24cd_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24cd_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24cd_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24cd_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24cd_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24cd_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24cd_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24cd_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24cd_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24cd_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24cd_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24cd_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1509_1968 = + {0x1509, 0x1968, pci_subsys_8086_24cd_1509_1968, 0}; +#undef pci_ss_info_1509_1968 +#define pci_ss_info_1509_1968 pci_ss_info_8086_24cd_1509_1968 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cd_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cd_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cd_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cd_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d1_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d1_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d1_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d1_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d1_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d1_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d1_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d1_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d1_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d1_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1458_24d1 = + {0x1458, 0x24d1, pci_subsys_8086_24d1_1458_24d1, 0}; +#undef pci_ss_info_1458_24d1 +#define pci_ss_info_1458_24d1 pci_ss_info_8086_24d1_1458_24d1 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d1_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d1_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d1_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d1_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d1_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d1_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d1_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d1_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d1_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d1_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d1_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d2_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d2_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d2_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d2_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d2_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d2_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d2_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d2_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d2_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d2_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d2_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d2_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d2_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d2_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d2_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d2_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d2_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d2_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d2_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d2_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d2_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d2_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d2_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d2_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d2_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d2_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d3_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d3_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d3_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d3_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d3_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d3_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d3_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d3_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d3_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d3_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d3_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d3_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d3_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d3_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d3_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d3_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d3_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d4_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d4_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d4_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d4_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d4_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d4_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d4_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d4_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d4_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d4_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d4_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d4_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d4_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d4_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d4_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d4_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d4_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d4_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d4_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d4_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d4_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d4_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d4_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d4_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d4_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d4_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d5_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d5_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d5_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d5_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d5_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_80f3 = + {0x1043, 0x80f3, pci_subsys_8086_24d5_1043_80f3, 0}; +#undef pci_ss_info_1043_80f3 +#define pci_ss_info_1043_80f3 pci_ss_info_8086_24d5_1043_80f3 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_810f = + {0x1043, 0x810f, pci_subsys_8086_24d5_1043_810f, 0}; +#undef pci_ss_info_1043_810f +#define pci_ss_info_1043_810f pci_ss_info_8086_24d5_1043_810f +static const pciSubsystemInfo pci_ss_info_8086_24d5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24d5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24d5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d5_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d5_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_a000 = + {0x8086, 0xa000, pci_subsys_8086_24d5_8086_a000, 0}; +#undef pci_ss_info_8086_a000 +#define pci_ss_info_8086_a000 pci_ss_info_8086_24d5_8086_a000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e000 = + {0x8086, 0xe000, pci_subsys_8086_24d5_8086_e000, 0}; +#undef pci_ss_info_8086_e000 +#define pci_ss_info_8086_e000 pci_ss_info_8086_24d5_8086_e000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e001 = + {0x8086, 0xe001, pci_subsys_8086_24d5_8086_e001, 0}; +#undef pci_ss_info_8086_e001 +#define pci_ss_info_8086_e001 pci_ss_info_8086_24d5_8086_e001 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d7_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d7_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d7_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d7_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d7_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d7_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d7_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d7_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d7_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d7_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d7_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d7_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d7_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d7_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d7_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d7_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d7_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d7_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d7_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d7_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d7_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d7_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d7_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d7_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24db_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24db_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24db_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24db_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24db_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24db_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24db_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24db_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24db_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24db_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24db_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24db_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24db_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24db_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_24db_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_24db_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_24db_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24db_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24db_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24db_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24db_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24db_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_24db = + {0x8086, 0x24db, pci_subsys_8086_24db_8086_24db, 0}; +#undef pci_ss_info_8086_24db +#define pci_ss_info_8086_24db pci_ss_info_8086_24db_8086_24db +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24db_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24db_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24db_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24db_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24db_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24db_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24dd_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24dd_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24dd_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24dd_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24dd_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24dd_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24dd_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24dd_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24dd_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24dd_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24dd_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_24dd_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_24dd_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24dd_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24dd_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24dd_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24dd_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24dd_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24dd_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24dd_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24dd_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24de_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24de_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24de_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24de_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24de_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24de_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24de_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24de_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24de_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24de_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24de_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24de_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24de_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24de_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24de_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24de_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24de_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24de_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24de_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24de_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24de_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24de_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24de_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24de_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2541_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2541_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_2541_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2541_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2541_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2544_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2544_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2544_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_254c_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_254c_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_254c_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_254c_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2560_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_2560_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_2560_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_2560_1458_2560 = + {0x1458, 0x2560, pci_subsys_8086_2560_1458_2560, 0}; +#undef pci_ss_info_1458_2560 +#define pci_ss_info_1458_2560 pci_ss_info_8086_2560_1458_2560 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_2562_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2562_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2562_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2570_1043_80f2 = + {0x1043, 0x80f2, pci_subsys_8086_2570_1043_80f2, 0}; +#undef pci_ss_info_1043_80f2 +#define pci_ss_info_1043_80f2 pci_ss_info_8086_2570_1043_80f2 +static const pciSubsystemInfo pci_ss_info_8086_2570_1458_2570 = + {0x1458, 0x2570, pci_subsys_8086_2570_1458_2570, 0}; +#undef pci_ss_info_1458_2570 +#define pci_ss_info_1458_2570 pci_ss_info_8086_2570_1458_2570 +static const pciSubsystemInfo pci_ss_info_8086_2572_1028_019d = + {0x1028, 0x019d, pci_subsys_8086_2572_1028_019d, 0}; +#undef pci_ss_info_1028_019d +#define pci_ss_info_1028_019d pci_ss_info_8086_2572_1028_019d +static const pciSubsystemInfo pci_ss_info_8086_2572_1043_80a5 = + {0x1043, 0x80a5, pci_subsys_8086_2572_1043_80a5, 0}; +#undef pci_ss_info_1043_80a5 +#define pci_ss_info_1043_80a5 pci_ss_info_8086_2572_1043_80a5 +static const pciSubsystemInfo pci_ss_info_8086_2578_1458_2578 = + {0x1458, 0x2578, pci_subsys_8086_2578_1458_2578, 0}; +#undef pci_ss_info_1458_2578 +#define pci_ss_info_1458_2578 pci_ss_info_8086_2578_1458_2578 +static const pciSubsystemInfo pci_ss_info_8086_2578_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_2578_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_2578_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_2578_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_2578_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_2578_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1458_2580 = + {0x1458, 0x2580, pci_subsys_8086_2580_1458_2580, 0}; +#undef pci_ss_info_1458_2580 +#define pci_ss_info_1458_2580 pci_ss_info_8086_2580_1458_2580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2580_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2580_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2580_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2580_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2580_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2582_1028_1079 = + {0x1028, 0x1079, pci_subsys_8086_2582_1028_1079, 0}; +#undef pci_ss_info_1028_1079 +#define pci_ss_info_1028_1079 pci_ss_info_8086_2582_1028_1079 +static const pciSubsystemInfo pci_ss_info_8086_2582_1458_2582 = + {0x1458, 0x2582, pci_subsys_8086_2582_1458_2582, 0}; +#undef pci_ss_info_1458_2582 +#define pci_ss_info_1458_2582 pci_ss_info_8086_2582_1458_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2582_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2582_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2590_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2590_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2590_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2590_a304_81b7 = + {0xa304, 0x81b7, pci_subsys_8086_2590_a304_81b7, 0}; +#undef pci_ss_info_a304_81b7 +#define pci_ss_info_a304_81b7 pci_ss_info_8086_2590_a304_81b7 +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2592_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2592_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2592_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2592_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2592_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a2_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a2_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a2_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a2_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a3_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a3_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a3_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a3_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a3_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a3_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a4_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a4_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a4_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a4_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a4_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a4_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a6_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a6_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a6_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a9_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a9_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a9_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a9_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a9_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a9_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25aa_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25aa_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25aa_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25aa_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ab_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ab_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ab_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ab_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ab_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ab_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ac_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ac_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ac_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ac_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ac_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ac_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ad_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ad_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ad_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ad_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ad_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ad_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25b0_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25b0_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25b0_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25b0_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_2640_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2640_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2640_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2640_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2640_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2640_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2641_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2641_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2641_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2651_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2651_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2651_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2651_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2651_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2651_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2651_8086_4147 = + {0x8086, 0x4147, pci_subsys_8086_2651_8086_4147, 0}; +#undef pci_ss_info_8086_4147 +#define pci_ss_info_8086_4147 pci_ss_info_8086_2651_8086_4147 +static const pciSubsystemInfo pci_ss_info_8086_2652_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2652_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2652_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2658_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2658_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2658_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2658_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2658_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2658_1458_2558 = + {0x1458, 0x2558, pci_subsys_8086_2658_1458_2558, 0}; +#undef pci_ss_info_1458_2558 +#define pci_ss_info_1458_2558 pci_ss_info_8086_2658_1458_2558 +static const pciSubsystemInfo pci_ss_info_8086_2658_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2658_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2658_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2658_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2658_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2659_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2659_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2659_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2659_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2659_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2659_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2659_1458_2659 = + {0x1458, 0x2659, pci_subsys_8086_2659_1458_2659, 0}; +#undef pci_ss_info_1458_2659 +#define pci_ss_info_1458_2659 pci_ss_info_8086_2659_1458_2659 +static const pciSubsystemInfo pci_ss_info_8086_2659_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2659_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2659_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2659_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2659_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2659_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265a_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265a_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265a_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265a_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265a_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265a_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265b_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265b_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265b_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265b_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265b_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265b_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265b_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265b_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265b_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265b_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265b_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265b_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265b_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265b_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265b_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265c_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265c_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265c_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265c_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265c_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_265c_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_265c_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_265c_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265c_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265c_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265c_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265c_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265c_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2660_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2660_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2660_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266a_1458_266a = + {0x1458, 0x266a, pci_subsys_8086_266a_1458_266a, 0}; +#undef pci_ss_info_1458_266a +#define pci_ss_info_1458_266a pci_ss_info_8086_266a_1458_266a +static const pciSubsystemInfo pci_ss_info_8086_266a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_266d_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266d_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266d_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266e_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266e_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_266e_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_266e_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0188 = + {0x1028, 0x0188, pci_subsys_8086_266e_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_8086_266e_1028_0188 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266e_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_266e_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_266e_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_266e_1734_105a = + {0x1734, 0x105a, pci_subsys_8086_266e_1734_105a, 0}; +#undef pci_ss_info_1734_105a +#define pci_ss_info_1734_105a pci_ss_info_8086_266e_1734_105a +static const pciSubsystemInfo pci_ss_info_8086_266f_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266f_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266f_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266f_1458_266f = + {0x1458, 0x266f, pci_subsys_8086_266f_1458_266f, 0}; +#undef pci_ss_info_1458_266f +#define pci_ss_info_1458_266f pci_ss_info_8086_266f_1458_266f +static const pciSubsystemInfo pci_ss_info_8086_266f_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266f_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266f_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266f_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266f_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266f_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2770_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2770_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2770_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2772_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2772_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2772_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2782_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2782_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2782_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2792_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2792_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2792_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2792_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2792_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2792_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_27b8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27b8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27b8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c0_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c0_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c0_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c9_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c9_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c9_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27ca_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27ca_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27ca_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cb_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cb_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cb_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cc_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cc_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cc_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27da_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27da_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27da_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27dc_8086_308d = + {0x8086, 0x308d, pci_subsys_8086_27dc_8086_308d, 0}; +#undef pci_ss_info_8086_308d +#define pci_ss_info_8086_308d pci_ss_info_8086_27dc_8086_308d +static const pciSubsystemInfo pci_ss_info_8086_27df_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27df_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27df_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_3340_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_3340_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_3340_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_3340_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_3340_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_3340_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_3340_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_3575_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_3575_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_3575_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3580_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3580_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3580_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3580_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3580_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3580_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3580_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3580_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3580_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3580_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3580_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3580_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3580_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3581_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3581_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3581_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3582_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3582_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3582_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3582_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3582_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3582_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3582_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3582_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3584_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3584_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3584_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3584_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3584_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3584_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3584_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3584_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3584_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3584_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3584_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3584_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3584_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3585_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3585_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3585_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3585_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3585_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3585_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3585_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3585_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3585_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3585_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3585_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3585_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3585_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3590_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_3590_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_3590_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_3590_1734_103e = + {0x1734, 0x103e, pci_subsys_8086_3590_1734_103e, 0}; +#undef pci_ss_info_1734_103e +#define pci_ss_info_1734_103e pci_ss_info_8086_3590_1734_103e +static const pciSubsystemInfo pci_ss_info_8086_3590_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3590_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3590_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3591_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_3591_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_3591_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_3591_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3591_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3591_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3594_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3594_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3594_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_359e_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_359e_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_359e_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7110_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7110_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7110_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7111_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7111_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7111_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7112_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7112_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7112_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7113_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7113_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7113_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7120_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7120_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7120_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7120_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7121_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7121_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7121_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7121_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_8086_4341 = + {0x8086, 0x4341, pci_subsys_8086_7121_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_8086_7121_8086_4341 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7190_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7190_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_7190_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_7190_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_7190_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_7190_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7192_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_7192_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_7192_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7194_1033_0000 = + {0x1033, 0x0000, pci_subsys_8086_7194_1033_0000, 0}; +#undef pci_ss_info_1033_0000 +#define pci_ss_info_1033_0000 pci_ss_info_8086_7194_1033_0000 +static const pciSubsystemInfo pci_ss_info_8086_7194_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_7194_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_7194_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_7195_1033_80cc = + {0x1033, 0x80cc, pci_subsys_8086_7195_1033_80cc, 0}; +#undef pci_ss_info_1033_80cc +#define pci_ss_info_1033_80cc pci_ss_info_8086_7195_1033_80cc +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_71a0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_71a0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_71a0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_71a0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_71a2_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_71a2_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_71a2_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0ded = + {0x1993, 0x0ded, pci_subsys_8086_8500_1993_0ded, 0}; +#undef pci_ss_info_1993_0ded +#define pci_ss_info_1993_0ded pci_ss_info_8086_8500_1993_0ded +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0dee = + {0x1993, 0x0dee, pci_subsys_8086_8500_1993_0dee, 0}; +#undef pci_ss_info_1993_0dee +#define pci_ss_info_1993_0dee pci_ss_info_8086_8500_1993_0dee +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0def = + {0x1993, 0x0def, pci_subsys_8086_8500_1993_0def, 0}; +#undef pci_ss_info_1993_0def +#define pci_ss_info_1993_0def pci_ss_info_8086_8500_1993_0def +static const pciSubsystemInfo pci_ss_info_8086_b555_12d9_000a = + {0x12d9, 0x000a, pci_subsys_8086_b555_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_8086_b555_12d9_000a +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_b555_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_b555_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_b555_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_b555_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +static const pciSubsystemInfo pci_ss_info_9004_8178_9004_7881 = + {0x9004, 0x7881, pci_subsys_9004_8178_9004_7881, 0}; +#undef pci_ss_info_9004_7881 +#define pci_ss_info_9004_7881 pci_ss_info_9004_8178_9004_7881 +static const pciSubsystemInfo pci_ss_info_9004_8778_9004_7887 = + {0x9004, 0x7887, pci_subsys_9004_8778_9004_7887, 0}; +#undef pci_ss_info_9004_7887 +#define pci_ss_info_9004_7887 pci_ss_info_9004_8778_9004_7887 +static const pciSubsystemInfo pci_ss_info_9004_8878_9004_7888 = + {0x9004, 0x7888, pci_subsys_9004_8878_9004_7888, 0}; +#undef pci_ss_info_9004_7888 +#define pci_ss_info_9004_7888 pci_ss_info_9004_8878_9004_7888 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_2180 = + {0x9005, 0x2180, pci_subsys_9005_0010_9005_2180, 0}; +#undef pci_ss_info_9005_2180 +#define pci_ss_info_9005_2180 pci_ss_info_9005_0010_9005_2180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_8100 = + {0x9005, 0x8100, pci_subsys_9005_0010_9005_8100, 0}; +#undef pci_ss_info_9005_8100 +#define pci_ss_info_9005_8100 pci_ss_info_9005_0010_9005_8100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a100 = + {0x9005, 0xa100, pci_subsys_9005_0010_9005_a100, 0}; +#undef pci_ss_info_9005_a100 +#define pci_ss_info_9005_a100 pci_ss_info_9005_0010_9005_a100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_0010_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_0010_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_e100 = + {0x9005, 0xe100, pci_subsys_9005_0010_9005_e100, 0}; +#undef pci_ss_info_9005_e100 +#define pci_ss_info_9005_e100 pci_ss_info_9005_0010_9005_e100 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_0003 = + {0x9005, 0x0003, pci_subsys_9005_0013_9005_0003, 0}; +#undef pci_ss_info_9005_0003 +#define pci_ss_info_9005_0003 pci_ss_info_9005_0013_9005_0003 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_0013_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_0013_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_001f_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_f500 = + {0x9005, 0xf500, pci_subsys_9005_0050_9005_f500, 0}; +#undef pci_ss_info_9005_f500 +#define pci_ss_info_9005_f500 pci_ss_info_9005_0050_9005_f500 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0050_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0050_9005_ffff +static const pciSubsystemInfo pci_ss_info_9005_0051_9005_b500 = + {0x9005, 0xb500, pci_subsys_9005_0051_9005_b500, 0}; +#undef pci_ss_info_9005_b500 +#define pci_ss_info_9005_b500 pci_ss_info_9005_0051_9005_b500 +static const pciSubsystemInfo pci_ss_info_9005_0053_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0053_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0053_9005_ffff +#endif +static const pciSubsystemInfo pci_ss_info_9005_0080_0e11_e2a0 = + {0x0e11, 0xe2a0, pci_subsys_9005_0080_0e11_e2a0, 0}; +#undef pci_ss_info_0e11_e2a0 +#define pci_ss_info_0e11_e2a0 pci_ss_info_9005_0080_0e11_e2a0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_6220 = + {0x9005, 0x6220, pci_subsys_9005_0080_9005_6220, 0}; +#undef pci_ss_info_9005_6220 +#define pci_ss_info_9005_6220 pci_ss_info_9005_0080_9005_6220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_62a0 = + {0x9005, 0x62a0, pci_subsys_9005_0080_9005_62a0, 0}; +#undef pci_ss_info_9005_62a0 +#define pci_ss_info_9005_62a0 pci_ss_info_9005_0080_9005_62a0 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e220 = + {0x9005, 0xe220, pci_subsys_9005_0080_9005_e220, 0}; +#undef pci_ss_info_9005_e220 +#define pci_ss_info_9005_e220 pci_ss_info_9005_0080_9005_e220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e2a0 = + {0x9005, 0xe2a0, pci_subsys_9005_0080_9005_e2a0, 0}; +#undef pci_ss_info_9005_e2a0 +#define pci_ss_info_9005_e2a0 pci_ss_info_9005_0080_9005_e2a0 +static const pciSubsystemInfo pci_ss_info_9005_0081_9005_62a1 = + {0x9005, 0x62a1, pci_subsys_9005_0081_9005_62a1, 0}; +#undef pci_ss_info_9005_62a1 +#define pci_ss_info_9005_62a1 pci_ss_info_9005_0081_9005_62a1 +static const pciSubsystemInfo pci_ss_info_9005_008f_1179_0001 = + {0x1179, 0x0001, pci_subsys_9005_008f_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_9005_008f_1179_0001 +static const pciSubsystemInfo pci_ss_info_9005_008f_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_008f_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_008f_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c0_0e11_f620 = + {0x0e11, 0xf620, pci_subsys_9005_00c0_0e11_f620, 0}; +#undef pci_ss_info_0e11_f620 +#define pci_ss_info_0e11_f620 pci_ss_info_9005_00c0_0e11_f620 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00c0_9005_f620 = + {0x9005, 0xf620, pci_subsys_9005_00c0_9005_f620, 0}; +#undef pci_ss_info_9005_f620 +#define pci_ss_info_9005_f620 pci_ss_info_9005_00c0_9005_f620 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_9005_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_9005_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00ce = + {0x1028, 0x00ce, pci_subsys_9005_00cf_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_9005_00cf_1028_00ce +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_9005_00cf_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_9005_00cf_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_9005_00cf_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_9005_00cf_1028_00d9 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00cf_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_9005_00cf_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_9005_00cf_10f1_2462 +static const pciSubsystemInfo pci_ss_info_9005_00cf_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_00cf_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_00cf_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_8086_3411 = + {0x8086, 0x3411, pci_subsys_9005_00cf_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_9005_00cf_8086_3411 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_0279 = + {0x1014, 0x0279, pci_subsys_9005_0250_1014_0279, 0}; +#undef pci_ss_info_1014_0279 +#define pci_ss_info_1014_0279 pci_ss_info_9005_0250_1014_0279 +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_028c = + {0x1014, 0x028c, pci_subsys_9005_0250_1014_028c, 0}; +#undef pci_ss_info_1014_028c +#define pci_ss_info_1014_028c pci_ss_info_9005_0250_1014_028c +static const pciSubsystemInfo pci_ss_info_9005_0283_9005_0283 = + {0x9005, 0x0283, pci_subsys_9005_0283_9005_0283, 0}; +#undef pci_ss_info_9005_0283 +#define pci_ss_info_9005_0283 pci_ss_info_9005_0283_9005_0283 +static const pciSubsystemInfo pci_ss_info_9005_0284_9005_0284 = + {0x9005, 0x0284, pci_subsys_9005_0284_9005_0284, 0}; +#undef pci_ss_info_9005_0284 +#define pci_ss_info_9005_0284 pci_ss_info_9005_0284_9005_0284 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_0e11_0295 = + {0x0e11, 0x0295, pci_subsys_9005_0285_0e11_0295, 0}; +#undef pci_ss_info_0e11_0295 +#define pci_ss_info_0e11_0295 pci_ss_info_9005_0285_0e11_0295 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_1014_02f2 = + {0x1014, 0x02f2, pci_subsys_9005_0285_1014_02f2, 0}; +#undef pci_ss_info_1014_02f2 +#define pci_ss_info_1014_02f2 pci_ss_info_9005_0285_1014_02f2 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0287 = + {0x1028, 0x0287, pci_subsys_9005_0285_1028_0287, 0}; +#undef pci_ss_info_1028_0287 +#define pci_ss_info_1028_0287 pci_ss_info_9005_0285_1028_0287 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0291 = + {0x1028, 0x0291, pci_subsys_9005_0285_1028_0291, 0}; +#undef pci_ss_info_1028_0291 +#define pci_ss_info_1028_0291 pci_ss_info_9005_0285_1028_0291 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_103c_3227 = + {0x103c, 0x3227, pci_subsys_9005_0285_103c_3227, 0}; +#undef pci_ss_info_103c_3227 +#define pci_ss_info_103c_3227 pci_ss_info_9005_0285_103c_3227 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0286 = + {0x17aa, 0x0286, pci_subsys_9005_0285_17aa_0286, 0}; +#undef pci_ss_info_17aa_0286 +#define pci_ss_info_17aa_0286 pci_ss_info_9005_0285_17aa_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0287 = + {0x17aa, 0x0287, pci_subsys_9005_0285_17aa_0287, 0}; +#undef pci_ss_info_17aa_0287 +#define pci_ss_info_17aa_0287 pci_ss_info_9005_0285_17aa_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0285 = + {0x9005, 0x0285, pci_subsys_9005_0285_9005_0285, 0}; +#undef pci_ss_info_9005_0285 +#define pci_ss_info_9005_0285 pci_ss_info_9005_0285_9005_0285 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0286 = + {0x9005, 0x0286, pci_subsys_9005_0285_9005_0286, 0}; +#undef pci_ss_info_9005_0286 +#define pci_ss_info_9005_0286 pci_ss_info_9005_0285_9005_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0287 = + {0x9005, 0x0287, pci_subsys_9005_0285_9005_0287, 0}; +#undef pci_ss_info_9005_0287 +#define pci_ss_info_9005_0287 pci_ss_info_9005_0285_9005_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0288 = + {0x9005, 0x0288, pci_subsys_9005_0285_9005_0288, 0}; +#undef pci_ss_info_9005_0288 +#define pci_ss_info_9005_0288 pci_ss_info_9005_0285_9005_0288 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0289 = + {0x9005, 0x0289, pci_subsys_9005_0285_9005_0289, 0}; +#undef pci_ss_info_9005_0289 +#define pci_ss_info_9005_0289 pci_ss_info_9005_0285_9005_0289 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028a = + {0x9005, 0x028a, pci_subsys_9005_0285_9005_028a, 0}; +#undef pci_ss_info_9005_028a +#define pci_ss_info_9005_028a pci_ss_info_9005_0285_9005_028a +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028b = + {0x9005, 0x028b, pci_subsys_9005_0285_9005_028b, 0}; +#undef pci_ss_info_9005_028b +#define pci_ss_info_9005_028b pci_ss_info_9005_0285_9005_028b +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028e = + {0x9005, 0x028e, pci_subsys_9005_0285_9005_028e, 0}; +#undef pci_ss_info_9005_028e +#define pci_ss_info_9005_028e pci_ss_info_9005_0285_9005_028e +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028f = + {0x9005, 0x028f, pci_subsys_9005_0285_9005_028f, 0}; +#undef pci_ss_info_9005_028f +#define pci_ss_info_9005_028f pci_ss_info_9005_0285_9005_028f +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0290 = + {0x9005, 0x0290, pci_subsys_9005_0285_9005_0290, 0}; +#undef pci_ss_info_9005_0290 +#define pci_ss_info_9005_0290 pci_ss_info_9005_0285_9005_0290 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0292 = + {0x9005, 0x0292, pci_subsys_9005_0285_9005_0292, 0}; +#undef pci_ss_info_9005_0292 +#define pci_ss_info_9005_0292 pci_ss_info_9005_0285_9005_0292 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0293 = + {0x9005, 0x0293, pci_subsys_9005_0285_9005_0293, 0}; +#undef pci_ss_info_9005_0293 +#define pci_ss_info_9005_0293 pci_ss_info_9005_0285_9005_0293 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0294 = + {0x9005, 0x0294, pci_subsys_9005_0285_9005_0294, 0}; +#undef pci_ss_info_9005_0294 +#define pci_ss_info_9005_0294 pci_ss_info_9005_0285_9005_0294 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0296 = + {0x9005, 0x0296, pci_subsys_9005_0285_9005_0296, 0}; +#undef pci_ss_info_9005_0296 +#define pci_ss_info_9005_0296 pci_ss_info_9005_0285_9005_0296 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0297 = + {0x9005, 0x0297, pci_subsys_9005_0285_9005_0297, 0}; +#undef pci_ss_info_9005_0297 +#define pci_ss_info_9005_0297 pci_ss_info_9005_0285_9005_0297 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0298 = + {0x9005, 0x0298, pci_subsys_9005_0285_9005_0298, 0}; +#undef pci_ss_info_9005_0298 +#define pci_ss_info_9005_0298 pci_ss_info_9005_0285_9005_0298 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0299 = + {0x9005, 0x0299, pci_subsys_9005_0285_9005_0299, 0}; +#undef pci_ss_info_9005_0299 +#define pci_ss_info_9005_0299 pci_ss_info_9005_0285_9005_0299 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_029a = + {0x9005, 0x029a, pci_subsys_9005_0285_9005_029a, 0}; +#undef pci_ss_info_9005_029a +#define pci_ss_info_9005_029a pci_ss_info_9005_0285_9005_029a +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9540 = + {0x1014, 0x9540, pci_subsys_9005_0286_1014_9540, 0}; +#undef pci_ss_info_1014_9540 +#define pci_ss_info_1014_9540 pci_ss_info_9005_0286_1014_9540 +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9580 = + {0x1014, 0x9580, pci_subsys_9005_0286_1014_9580, 0}; +#undef pci_ss_info_1014_9580 +#define pci_ss_info_1014_9580 pci_ss_info_9005_0286_1014_9580 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028c = + {0x9005, 0x028c, pci_subsys_9005_0286_9005_028c, 0}; +#undef pci_ss_info_9005_028c +#define pci_ss_info_9005_028c pci_ss_info_9005_0286_9005_028c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028d = + {0x9005, 0x028d, pci_subsys_9005_0286_9005_028d, 0}; +#undef pci_ss_info_9005_028d +#define pci_ss_info_9005_028d pci_ss_info_9005_0286_9005_028d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029b = + {0x9005, 0x029b, pci_subsys_9005_0286_9005_029b, 0}; +#undef pci_ss_info_9005_029b +#define pci_ss_info_9005_029b pci_ss_info_9005_0286_9005_029b +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029c = + {0x9005, 0x029c, pci_subsys_9005_0286_9005_029c, 0}; +#undef pci_ss_info_9005_029c +#define pci_ss_info_9005_029c pci_ss_info_9005_0286_9005_029c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029d = + {0x9005, 0x029d, pci_subsys_9005_0286_9005_029d, 0}; +#undef pci_ss_info_9005_029d +#define pci_ss_info_9005_029d pci_ss_info_9005_0286_9005_029d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029e = + {0x9005, 0x029e, pci_subsys_9005_0286_9005_029e, 0}; +#undef pci_ss_info_9005_029e +#define pci_ss_info_9005_029e pci_ss_info_9005_0286_9005_029e +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029f = + {0x9005, 0x029f, pci_subsys_9005_0286_9005_029f, 0}; +#undef pci_ss_info_9005_029f +#define pci_ss_info_9005_029f pci_ss_info_9005_0286_9005_029f +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a0 = + {0x9005, 0x02a0, pci_subsys_9005_0286_9005_02a0, 0}; +#undef pci_ss_info_9005_02a0 +#define pci_ss_info_9005_02a0 pci_ss_info_9005_0286_9005_02a0 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a1 = + {0x9005, 0x02a1, pci_subsys_9005_0286_9005_02a1, 0}; +#undef pci_ss_info_9005_02a1 +#define pci_ss_info_9005_02a1 pci_ss_info_9005_0286_9005_02a1 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a2 = + {0x9005, 0x02a2, pci_subsys_9005_0286_9005_02a2, 0}; +#undef pci_ss_info_9005_02a2 +#define pci_ss_info_9005_02a2 pci_ss_info_9005_0286_9005_02a2 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a3 = + {0x9005, 0x02a3, pci_subsys_9005_0286_9005_02a3, 0}; +#undef pci_ss_info_9005_02a3 +#define pci_ss_info_9005_02a3 pci_ss_info_9005_0286_9005_02a3 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a4 = + {0x9005, 0x02a4, pci_subsys_9005_0286_9005_02a4, 0}; +#undef pci_ss_info_9005_02a4 +#define pci_ss_info_9005_02a4 pci_ss_info_9005_0286_9005_02a4 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a5 = + {0x9005, 0x02a5, pci_subsys_9005_0286_9005_02a5, 0}; +#undef pci_ss_info_9005_02a5 +#define pci_ss_info_9005_02a5 pci_ss_info_9005_0286_9005_02a5 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a6 = + {0x9005, 0x02a6, pci_subsys_9005_0286_9005_02a6, 0}; +#undef pci_ss_info_9005_02a6 +#define pci_ss_info_9005_02a6 pci_ss_info_9005_0286_9005_02a6 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_0800 = + {0x9005, 0x0800, pci_subsys_9005_0286_9005_0800, 0}; +#undef pci_ss_info_9005_0800 +#define pci_ss_info_9005_0800 pci_ss_info_9005_0286_9005_0800 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_9005_0500_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_9005_0500_1014_02c1 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_9005_0500_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_9005_0500_1014_02c2 +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02bf = + {0x1014, 0x02bf, pci_subsys_9005_0503_1014_02bf, 0}; +#undef pci_ss_info_1014_02bf +#define pci_ss_info_1014_02bf pci_ss_info_9005_0503_1014_02bf +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02d5 = + {0x1014, 0x02d5, pci_subsys_9005_0503_1014_02d5, 0}; +#undef pci_ss_info_1014_02d5 +#define pci_ss_info_1014_02d5 pci_ss_info_9005_0503_1014_02d5 +#endif +static const pciSubsystemInfo pci_ss_info_9005_8011_0e11_00ac = + {0x0e11, 0x00ac, pci_subsys_9005_8011_0e11_00ac, 0}; +#undef pci_ss_info_0e11_00ac +#define pci_ss_info_0e11_00ac pci_ss_info_9005_8011_0e11_00ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_8011_9005_0041 = + {0x9005, 0x0041, pci_subsys_9005_8011_9005_0041, 0}; +#undef pci_ss_info_9005_0041 +#define pci_ss_info_9005_0041 pci_ss_info_9005_8011_9005_0041 +static const pciSubsystemInfo pci_ss_info_9005_801f_1734_1011 = + {0x1734, 0x1011, pci_subsys_9005_801f_1734_1011, 0}; +#undef pci_ss_info_1734_1011 +#define pci_ss_info_1734_1011 pci_ss_info_9005_801f_1734_1011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9710_9815_1000_0020 = + {0x1000, 0x0020, pci_subsys_9710_9815_1000_0020, 0}; +#undef pci_ss_info_1000_0020 +#define pci_ss_info_1000_0020 pci_ss_info_9710_9815_1000_0020 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0002 = + {0x1000, 0x0002, pci_subsys_9710_9835_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_9710_9835_1000_0002 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0012 = + {0x1000, 0x0012, pci_subsys_9710_9835_1000_0012, 0}; +#undef pci_ss_info_1000_0012 +#define pci_ss_info_1000_0012 pci_ss_info_9710_9835_1000_0012 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0004 = + {0x1000, 0x0004, pci_subsys_9710_9845_1000_0004, 0}; +#undef pci_ss_info_1000_0004 +#define pci_ss_info_1000_0004 pci_ss_info_9710_9845_1000_0004 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0006 = + {0x1000, 0x0006, pci_subsys_9710_9845_1000_0006, 0}; +#undef pci_ss_info_1000_0006 +#define pci_ss_info_1000_0006 pci_ss_info_9710_9845_1000_0006 +static const pciSubsystemInfo pci_ss_info_9710_9855_1000_0014 = + {0x1000, 0x0014, pci_subsys_9710_9855_1000_0014, 0}; +#undef pci_ss_info_1000_0014 +#define pci_ss_info_1000_0014 pci_ss_info_9710_9855_1000_0014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0001 = + {0x0059, 0x0001, pci_subsys_e159_0001_0059_0001, 0}; +#undef pci_ss_info_0059_0001 +#define pci_ss_info_0059_0001 pci_ss_info_e159_0001_0059_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0003 = + {0x0059, 0x0003, pci_subsys_e159_0001_0059_0003, 0}; +#undef pci_ss_info_0059_0003 +#define pci_ss_info_0059_0003 pci_ss_info_e159_0001_0059_0003 +static const pciSubsystemInfo pci_ss_info_e159_0001_00a7_0001 = + {0x00a7, 0x0001, pci_subsys_e159_0001_00a7_0001, 0}; +#undef pci_ss_info_00a7_0001 +#define pci_ss_info_00a7_0001 pci_ss_info_e159_0001_00a7_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_6159_0001 = + {0x6159, 0x0001, pci_subsys_e159_0001_6159_0001, 0}; +#undef pci_ss_info_6159_0001 +#define pci_ss_info_6159_0001 pci_ss_info_e159_0001_6159_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_79fe_0001 = + {0x79fe, 0x0001, pci_subsys_e159_0001_79fe_0001, 0}; +#undef pci_ss_info_79fe_0001 +#define pci_ss_info_79fe_0001 pci_ss_info_e159_0001_79fe_0001 +#endif +static const pciSubsystemInfo pci_ss_info_e159_0001_8086_0003 = + {0x8086, 0x0003, pci_subsys_e159_0001_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_e159_0001_8086_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_b1b9_0001 = + {0xb1b9, 0x0001, pci_subsys_e159_0001_b1b9_0001, 0}; +#undef pci_ss_info_b1b9_0001 +#define pci_ss_info_b1b9_0001 pci_ss_info_e159_0001_b1b9_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_b1b9_0003 = + {0xb1b9, 0x0003, pci_subsys_e159_0001_b1b9_0003, 0}; +#undef pci_ss_info_b1b9_0003 +#define pci_ss_info_b1b9_0003 pci_ss_info_e159_0001_b1b9_0003 +#endif +#define pci_ss_list_0070_0003 NULL +#define pci_ss_list_0070_0009 NULL +#define pci_ss_list_0070_0801 NULL +#define pci_ss_list_0070_0807 NULL +#define pci_ss_list_0070_4000 NULL +#define pci_ss_list_0070_4001 NULL +#define pci_ss_list_0070_4009 NULL +#define pci_ss_list_0070_4800 NULL +#define pci_ss_list_0070_4801 NULL +#define pci_ss_list_0070_4803 NULL +#define pci_ss_list_0070_8003 NULL +#define pci_ss_list_0070_8801 NULL +#define pci_ss_list_0070_c801 NULL +#define pci_ss_list_0070_e807 NULL +#define pci_ss_list_0070_e817 NULL +#define pci_ss_list_0095_0680 NULL +#define pci_ss_list_018a_0106 NULL +#define pci_ss_list_021b_8139 NULL +#define pci_ss_list_0270_0801 NULL +#define pci_ss_list_0291_8212 NULL +#define pci_ss_list_02ac_1012 NULL +#define pci_ss_list_0357_000a NULL +#define pci_ss_list_0432_0001 NULL +#define pci_ss_list_045e_006e NULL +#define pci_ss_list_045e_00c2 NULL +#define pci_ss_list_04cf_8818 NULL +#define pci_ss_list_05e3_0701 NULL +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_0675_1703 NULL +#define pci_ss_list_0675_1704 NULL +#define pci_ss_list_067b_3507 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0b49_064f NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_0046[] = { + &pci_ss_info_0e11_0046_0e11_409a, + &pci_ss_info_0e11_0046_0e11_409b, + &pci_ss_info_0e11_0046_0e11_409c, + &pci_ss_info_0e11_0046_0e11_409d, + NULL +}; +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_005a NULL +#define pci_ss_list_0e11_007c NULL +#define pci_ss_list_0e11_007d NULL +#define pci_ss_list_0e11_0085 NULL +#define pci_ss_list_0e11_00b1 NULL +#define pci_ss_list_0e11_00bb NULL +#define pci_ss_list_0e11_00ca NULL +#define pci_ss_list_0e11_00cb NULL +#define pci_ss_list_0e11_00cf NULL +#define pci_ss_list_0e11_00d0 NULL +#define pci_ss_list_0e11_00d1 NULL +#define pci_ss_list_0e11_00e3 NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_4030 NULL +#define pci_ss_list_0e11_4031 NULL +#define pci_ss_list_0e11_4032 NULL +#define pci_ss_list_0e11_4033 NULL +#define pci_ss_list_0e11_4034 NULL +#define pci_ss_list_0e11_4040 NULL +#define pci_ss_list_0e11_4048 NULL +#define pci_ss_list_0e11_4050 NULL +#define pci_ss_list_0e11_4051 NULL +#define pci_ss_list_0e11_4058 NULL +#define pci_ss_list_0e11_4070 NULL +#define pci_ss_list_0e11_4080 NULL +#define pci_ss_list_0e11_4082 NULL +#define pci_ss_list_0e11_4083 NULL +#define pci_ss_list_0e11_4091 NULL +#define pci_ss_list_0e11_409a NULL +#define pci_ss_list_0e11_409b NULL +#define pci_ss_list_0e11_409c NULL +#define pci_ss_list_0e11_409d NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_b178[] = { + &pci_ss_info_0e11_b178_0e11_4080, + &pci_ss_info_0e11_b178_0e11_4082, + &pci_ss_info_0e11_b178_0e11_4083, + NULL +}; +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_b200 NULL +#define pci_ss_list_0e11_b203 NULL +#define pci_ss_list_0e11_b204 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0003[] = { + &pci_ss_info_1000_0003_1000_1000, + NULL +}; +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0006[] = { + &pci_ss_info_1000_0006_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000a[] = { + &pci_ss_info_1000_000a_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000b[] = { + &pci_ss_info_1000_000b_0e11_6004, + &pci_ss_info_1000_000b_1000_1000, + &pci_ss_info_1000_000b_1000_1010, + &pci_ss_info_1000_000b_1000_1020, + &pci_ss_info_1000_000b_13e9_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1000_1010, + &pci_ss_info_1000_000c_1000_1020, + &pci_ss_info_1000_000c_1de1_3906, + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1000_1000, + &pci_ss_info_1000_000f_1000_1010, + &pci_ss_info_1000_000f_1000_1020, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1de1_3904, + &pci_ss_info_1000_000f_4c53_1000, + &pci_ss_info_1000_000f_4c53_1050, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + &pci_ss_info_1000_0010_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0012[] = { + &pci_ss_info_1000_0012_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0013[] = { + &pci_ss_info_1000_0013_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1000_1000, + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0021[] = { + &pci_ss_info_1000_0021_1000_1000, + &pci_ss_info_1000_0021_1000_1010, + &pci_ss_info_1000_0021_124b_1070, + &pci_ss_info_1000_0021_4c53_1080, + &pci_ss_info_1000_0021_4c53_1300, + &pci_ss_info_1000_0021_4c53_1310, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_0e11_00da, + &pci_ss_info_1000_0030_1028_0123, + &pci_ss_info_1000_0030_1028_014a, + &pci_ss_info_1000_0030_1028_016c, + &pci_ss_info_1000_0030_1028_0183, + &pci_ss_info_1000_0030_1028_1010, + &pci_ss_info_1000_0030_124b_1170, + &pci_ss_info_1000_0030_1734_1052, + NULL +}; +#define pci_ss_list_1000_0031 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0032[] = { + &pci_ss_info_1000_0032_1000_1000, + NULL +}; +#define pci_ss_list_1000_0033 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0040[] = { + &pci_ss_info_1000_0040_1000_0033, + &pci_ss_info_1000_0040_1000_0066, + NULL +}; +#define pci_ss_list_1000_0041 NULL +#define pci_ss_list_1000_0050 NULL +#define pci_ss_list_1000_0054 NULL +#define pci_ss_list_1000_0056 NULL +#define pci_ss_list_1000_0058 NULL +#define pci_ss_list_1000_005a NULL +#define pci_ss_list_1000_005c NULL +#define pci_ss_list_1000_005e NULL +#define pci_ss_list_1000_0060 NULL +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0407[] = { + &pci_ss_info_1000_0407_1000_0530, + &pci_ss_info_1000_0407_1000_0531, + &pci_ss_info_1000_0407_1000_0532, + &pci_ss_info_1000_0407_1028_0531, + &pci_ss_info_1000_0407_1028_0533, + &pci_ss_info_1000_0407_8086_0530, + &pci_ss_info_1000_0407_8086_0532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0408[] = { + &pci_ss_info_1000_0408_1000_0001, + &pci_ss_info_1000_0408_1000_0002, + &pci_ss_info_1000_0408_1025_004d, + &pci_ss_info_1000_0408_1028_0001, + &pci_ss_info_1000_0408_1028_0002, + &pci_ss_info_1000_0408_1734_1065, + &pci_ss_info_1000_0408_8086_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0409[] = { + &pci_ss_info_1000_0409_1000_3004, + &pci_ss_info_1000_0409_1000_3008, + &pci_ss_info_1000_0409_8086_3008, + &pci_ss_info_1000_0409_8086_3431, + &pci_ss_info_1000_0409_8086_3499, + NULL +}; +#define pci_ss_list_1000_0621 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0622[] = { + &pci_ss_info_1000_0622_1000_1020, + NULL +}; +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0626[] = { + &pci_ss_info_1000_0626_1000_1010, + NULL +}; +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0640 NULL +#define pci_ss_list_1000_0642 NULL +#define pci_ss_list_1000_0646 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0804 NULL +#define pci_ss_list_1000_0805 NULL +#define pci_ss_list_1000_0806 NULL +#define pci_ss_list_1000_0807 NULL +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1000_0518, + &pci_ss_info_1000_1960_1000_0520, + &pci_ss_info_1000_1960_1000_0522, + &pci_ss_info_1000_1960_1000_0523, + &pci_ss_info_1000_1960_1000_4523, + &pci_ss_info_1000_1960_1000_a520, + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + &pci_ss_info_1000_1960_1028_0533, + &pci_ss_info_1000_1960_8086_0520, + &pci_ss_info_1000_1960_8086_0523, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_3150 NULL +#define pci_ss_list_1002_3152 NULL +#define pci_ss_list_1002_3154 NULL +#define pci_ss_list_1002_3e50 NULL +#define pci_ss_list_1002_3e54 NULL +#define pci_ss_list_1002_3e70 NULL +#define pci_ss_list_1002_4136 NULL +#define pci_ss_list_1002_4137 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4148 NULL +#define pci_ss_list_1002_4149 NULL +#define pci_ss_list_1002_414a NULL +#define pci_ss_list_1002_414b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4150[] = { + &pci_ss_info_1002_4150_1002_0002, + &pci_ss_info_1002_4150_1002_0003, + &pci_ss_info_1002_4150_1458_4024, + &pci_ss_info_1002_4150_148c_2064, + &pci_ss_info_1002_4150_148c_2066, + &pci_ss_info_1002_4150_174b_7c19, + &pci_ss_info_1002_4150_174b_7c29, + &pci_ss_info_1002_4150_17ee_2002, + &pci_ss_info_1002_4150_18bc_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4151[] = { + &pci_ss_info_1002_4151_1043_c004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4152[] = { + &pci_ss_info_1002_4152_1002_0002, + &pci_ss_info_1002_4152_1002_4772, + &pci_ss_info_1002_4152_1043_c002, + &pci_ss_info_1002_4152_1043_c01a, + &pci_ss_info_1002_4152_174b_7c29, + &pci_ss_info_1002_4152_1787_4002, + NULL +}; +#define pci_ss_list_1002_4153 NULL +#define pci_ss_list_1002_4154 NULL +#define pci_ss_list_1002_4155 NULL +#define pci_ss_list_1002_4156 NULL +#define pci_ss_list_1002_4157 NULL +#define pci_ss_list_1002_4158 NULL +#define pci_ss_list_1002_4164 NULL +#define pci_ss_list_1002_4165 NULL +#define pci_ss_list_1002_4166 NULL +#define pci_ss_list_1002_4168 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4170[] = { + &pci_ss_info_1002_4170_1002_0003, + &pci_ss_info_1002_4170_1458_4025, + &pci_ss_info_1002_4170_148c_2067, + &pci_ss_info_1002_4170_174b_7c28, + &pci_ss_info_1002_4170_17ee_2003, + &pci_ss_info_1002_4170_18bc_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4171[] = { + &pci_ss_info_1002_4171_1043_c005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4172[] = { + &pci_ss_info_1002_4172_1002_0003, + &pci_ss_info_1002_4172_1002_4773, + &pci_ss_info_1002_4172_1043_c003, + &pci_ss_info_1002_4172_1043_c01b, + &pci_ss_info_1002_4172_174b_7c28, + &pci_ss_info_1002_4172_1787_4003, + NULL +}; +#define pci_ss_list_1002_4173 NULL +#define pci_ss_list_1002_4237 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4243 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4336[] = { + &pci_ss_info_1002_4336_1002_4336, + &pci_ss_info_1002_4336_103c_0024, + &pci_ss_info_1002_4336_161f_2029, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4337[] = { + &pci_ss_info_1002_4337_1014_053a, + &pci_ss_info_1002_4337_103c_0850, + NULL +}; +#define pci_ss_list_1002_4341 NULL +#define pci_ss_list_1002_4345 NULL +#define pci_ss_list_1002_4347 NULL +#define pci_ss_list_1002_4348 NULL +#define pci_ss_list_1002_4349 NULL +#define pci_ss_list_1002_434d NULL +#define pci_ss_list_1002_4353 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4363 NULL +#define pci_ss_list_1002_436e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4370[] = { + &pci_ss_info_1002_4370_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4371[] = { + &pci_ss_info_1002_4371_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4372[] = { + &pci_ss_info_1002_4372_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4373[] = { + &pci_ss_info_1002_4373_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4374[] = { + &pci_ss_info_1002_4374_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4375[] = { + &pci_ss_info_1002_4375_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4376[] = { + &pci_ss_info_1002_4376_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4377[] = { + &pci_ss_info_1002_4377_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4378[] = { + &pci_ss_info_1002_4378_103c_308b, + NULL +}; +#define pci_ss_list_1002_4379 NULL +#define pci_ss_list_1002_437a NULL +#define pci_ss_list_1002_4437 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00ce, + &pci_ss_info_1002_4752_1028_00d1, + &pci_ss_info_1002_4752_1028_00d9, + &pci_ss_info_1002_4752_1028_0134, + &pci_ss_info_1002_4752_1734_007a, + &pci_ss_info_1002_4752_8086_3411, + &pci_ss_info_1002_4752_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0084, + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +#define pci_ss_list_1002_4a48 NULL +#define pci_ss_list_1002_4a49 NULL +#define pci_ss_list_1002_4a4a NULL +#define pci_ss_list_1002_4a4b NULL +#define pci_ss_list_1002_4a4c NULL +#define pci_ss_list_1002_4a4d NULL +#define pci_ss_list_1002_4a4e NULL +#define pci_ss_list_1002_4a50 NULL +#define pci_ss_list_1002_4a70 NULL +#define pci_ss_list_1002_4b49 NULL +#define pci_ss_list_1002_4b4b NULL +#define pci_ss_list_1002_4b4c NULL +#define pci_ss_list_1002_4b69 NULL +#define pci_ss_list_1002_4b6b NULL +#define pci_ss_list_1002_4b6c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e7, + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c46[] = { + &pci_ss_info_1002_4c46_1028_00b1, + NULL +}; +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_0e11_b160, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + &pci_ss_info_1002_4c4d_1028_00aa, + &pci_ss_info_1002_4c4d_1028_00bb, + &pci_ss_info_1002_4c4d_10e1_10cf, + &pci_ss_info_1002_4c4d_13bd_1019, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c52[] = { + &pci_ss_info_1002_4c52_1033_8112, + NULL +}; +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_1028_012a, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_0e11_b111, + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + &pci_ss_info_1002_4c59_1509_1930, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4c6e NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e44[] = { + &pci_ss_info_1002_4e44_1002_515e, + &pci_ss_info_1002_4e44_1002_5965, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4e45[] = { + &pci_ss_info_1002_4e45_1002_0002, + &pci_ss_info_1002_4e45_1681_0002, + NULL +}; +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e48 NULL +#define pci_ss_list_1002_4e49 NULL +#define pci_ss_list_1002_4e4a NULL +#define pci_ss_list_1002_4e4b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e50[] = { + &pci_ss_info_1002_4e50_1025_005a, + &pci_ss_info_1002_4e50_103c_088c, + &pci_ss_info_1002_4e50_103c_0890, + &pci_ss_info_1002_4e50_1734_1055, + NULL +}; +#define pci_ss_list_1002_4e51 NULL +#define pci_ss_list_1002_4e52 NULL +#define pci_ss_list_1002_4e53 NULL +#define pci_ss_list_1002_4e54 NULL +#define pci_ss_list_1002_4e56 NULL +#define pci_ss_list_1002_4e64 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e65[] = { + &pci_ss_info_1002_4e65_1002_0003, + &pci_ss_info_1002_4e65_1681_0003, + NULL +}; +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_4e68 NULL +#define pci_ss_list_1002_4e69 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e6a[] = { + &pci_ss_info_1002_4e6a_1002_4e71, + NULL +}; +#define pci_ss_list_1002_4e71 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_1681_0010, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +#define pci_ss_list_1002_5154 NULL +#define pci_ss_list_1002_5155 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1002_103a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7146, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1028_019a, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_174b_7c28, + &pci_ss_info_1002_5159_1787_0202, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_515e NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5346[] = { + &pci_ss_info_1002_5346_1002_0048, + NULL +}; +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +#define pci_ss_list_1002_5460 NULL +#define pci_ss_list_1002_5464 NULL +#define pci_ss_list_1002_5548 NULL +#define pci_ss_list_1002_5549 NULL +#define pci_ss_list_1002_554a NULL +#define pci_ss_list_1002_554b NULL +#define pci_ss_list_1002_554d NULL +#define pci_ss_list_1002_554f NULL +#define pci_ss_list_1002_5550 NULL +#define pci_ss_list_1002_5551 NULL +#define pci_ss_list_1002_5552 NULL +#define pci_ss_list_1002_5554 NULL +#define pci_ss_list_1002_556b NULL +#define pci_ss_list_1002_556d NULL +#define pci_ss_list_1002_556f NULL +#define pci_ss_list_1002_564a NULL +#define pci_ss_list_1002_564b NULL +#define pci_ss_list_1002_5652 NULL +#define pci_ss_list_1002_5653 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_5830 NULL +#define pci_ss_list_1002_5831 NULL +#define pci_ss_list_1002_5832 NULL +#define pci_ss_list_1002_5833 NULL +#define pci_ss_list_1002_5834 NULL +#define pci_ss_list_1002_5835 NULL +#define pci_ss_list_1002_5838 NULL +#define pci_ss_list_1002_5940 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5941[] = { + &pci_ss_info_1002_5941_1458_4019, + &pci_ss_info_1002_5941_174b_7c12, + &pci_ss_info_1002_5941_17af_200d, + &pci_ss_info_1002_5941_18bc_0050, + NULL +}; +#define pci_ss_list_1002_5944 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5950[] = { + &pci_ss_info_1002_5950_103c_308b, + NULL +}; +#define pci_ss_list_1002_5951 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5954[] = { + &pci_ss_info_1002_5954_1002_5954, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5955[] = { + &pci_ss_info_1002_5955_1002_5955, + &pci_ss_info_1002_5955_103c_308b, + NULL +}; +#define pci_ss_list_1002_5960 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5961[] = { + &pci_ss_info_1002_5961_1002_2f72, + &pci_ss_info_1002_5961_1019_4c30, + &pci_ss_info_1002_5961_12ab_5961, + &pci_ss_info_1002_5961_1458_4018, + &pci_ss_info_1002_5961_174b_7c13, + &pci_ss_info_1002_5961_17af_200c, + &pci_ss_info_1002_5961_18bc_0050, + &pci_ss_info_1002_5961_18bc_0051, + &pci_ss_info_1002_5961_18bc_0053, + NULL +}; +#define pci_ss_list_1002_5962 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5964[] = { + &pci_ss_info_1002_5964_1043_c006, + &pci_ss_info_1002_5964_1458_4018, + &pci_ss_info_1002_5964_147b_6191, + &pci_ss_info_1002_5964_148c_2073, + &pci_ss_info_1002_5964_174b_7c13, + &pci_ss_info_1002_5964_1787_5964, + &pci_ss_info_1002_5964_17af_2012, + &pci_ss_info_1002_5964_18bc_0170, + &pci_ss_info_1002_5964_18bc_0173, + NULL +}; +#define pci_ss_list_1002_5969 NULL +#define pci_ss_list_1002_5974 NULL +#define pci_ss_list_1002_5975 NULL +#define pci_ss_list_1002_5a34 NULL +#define pci_ss_list_1002_5a41 NULL +#define pci_ss_list_1002_5a42 NULL +#define pci_ss_list_1002_5a61 NULL +#define pci_ss_list_1002_5a62 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b60[] = { + &pci_ss_info_1002_5b60_1043_002a, + &pci_ss_info_1002_5b60_1043_032e, + NULL +}; +#define pci_ss_list_1002_5b62 NULL +#define pci_ss_list_1002_5b63 NULL +#define pci_ss_list_1002_5b64 NULL +#define pci_ss_list_1002_5b65 NULL +#define pci_ss_list_1002_5b70 NULL +#define pci_ss_list_1002_5b72 NULL +#define pci_ss_list_1002_5b73 NULL +#define pci_ss_list_1002_5b74 NULL +#define pci_ss_list_1002_5c61 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5c63[] = { + &pci_ss_info_1002_5c63_1002_5c63, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5d44[] = { + &pci_ss_info_1002_5d44_1458_4019, + &pci_ss_info_1002_5d44_174b_7c12, + &pci_ss_info_1002_5d44_1787_5965, + &pci_ss_info_1002_5d44_17af_2013, + &pci_ss_info_1002_5d44_18bc_0171, + &pci_ss_info_1002_5d44_18bc_0172, + NULL +}; +#define pci_ss_list_1002_5d48 NULL +#define pci_ss_list_1002_5d49 NULL +#define pci_ss_list_1002_5d4a NULL +#define pci_ss_list_1002_5d4d NULL +static const pciSubsystemInfo *pci_ss_list_1002_5d52[] = { + &pci_ss_info_1002_5d52_1002_0b12, + &pci_ss_info_1002_5d52_1002_0b13, + NULL +}; +#define pci_ss_list_1002_5d57 NULL +#define pci_ss_list_1002_5d6d NULL +#define pci_ss_list_1002_5d72 NULL +#define pci_ss_list_1002_5d77 NULL +#define pci_ss_list_1002_5e48 NULL +#define pci_ss_list_1002_5e49 NULL +#define pci_ss_list_1002_5e4a NULL +#define pci_ss_list_1002_5e4b NULL +#define pci_ss_list_1002_5e4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e4d[] = { + &pci_ss_info_1002_5e4d_148c_2116, + NULL +}; +#define pci_ss_list_1002_5e4f NULL +#define pci_ss_list_1002_5e6b NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e6d[] = { + &pci_ss_info_1002_5e6d_148c_2117, + NULL +}; +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1002_7010 NULL +#define pci_ss_list_1002_7105 NULL +#define pci_ss_list_1002_7109 NULL +#define pci_ss_list_1002_7833 NULL +#define pci_ss_list_1002_7834 NULL +#define pci_ss_list_1002_7835 NULL +#define pci_ss_list_1002_7838 NULL +#define pci_ss_list_1002_7c37 NULL +#define pci_ss_list_1002_cab0 NULL +#define pci_ss_list_1002_cab2 NULL +#define pci_ss_list_1002_cab3 NULL +#define pci_ss_list_1002_cbb2 NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +static const pciSubsystemInfo *pci_ss_list_100b_0020[] = { + &pci_ss_info_100b_0020_103c_0024, + &pci_ss_info_100b_0020_1385_f311, + NULL +}; +#define pci_ss_list_100b_0021 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0028 NULL +#define pci_ss_list_100b_002a NULL +#define pci_ss_list_100b_002b NULL +#define pci_ss_list_100b_002d NULL +#define pci_ss_list_100b_002e NULL +#define pci_ss_list_100b_002f NULL +#define pci_ss_list_100b_0030 NULL +#define pci_ss_list_100b_0035 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_0510 NULL +#define pci_ss_list_100b_0511 NULL +#define pci_ss_list_100b_0515 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +#define pci_ss_list_1011_000f NULL +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +#define pci_ss_list_1011_0017 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1186_1112, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_14cb_0100, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_4c53_1050, + &pci_ss_info_1011_0046_4c53_1051, + &pci_ss_info_1011_0046_9005_0364, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4000 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_153b_1136, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0031[] = { + &pci_ss_info_1014_0031_1014_0031, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_0037 NULL +#define pci_ss_list_1014_003a NULL +#define pci_ss_list_1014_003c NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0054 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_005e NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +#define pci_ss_list_1014_008b NULL +#define pci_ss_list_1014_008e NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0091 NULL +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_009f NULL +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1014_00b7[] = { + &pci_ss_info_1014_00b7_1092_00b8, + NULL +}; +#define pci_ss_list_1014_00b8 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0104 NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_015e NULL +#define pci_ss_list_1014_0160 NULL +#define pci_ss_list_1014_016e NULL +#define pci_ss_list_1014_0170 NULL +#define pci_ss_list_1014_017d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0180[] = { + &pci_ss_info_1014_0180_1014_0241, + &pci_ss_info_1014_0180_1014_0264, + NULL +}; +#define pci_ss_list_1014_0188 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_01c1 NULL +#define pci_ss_list_1014_01e6 NULL +#define pci_ss_list_1014_01ff NULL +static const pciSubsystemInfo *pci_ss_list_1014_0219[] = { + &pci_ss_info_1014_0219_1014_021a, + &pci_ss_info_1014_0219_1014_0251, + &pci_ss_info_1014_0219_1014_0252, + NULL +}; +#define pci_ss_list_1014_021b NULL +#define pci_ss_list_1014_021c NULL +#define pci_ss_list_1014_0233 NULL +#define pci_ss_list_1014_0266 NULL +#define pci_ss_list_1014_0268 NULL +#define pci_ss_list_1014_0269 NULL +static const pciSubsystemInfo *pci_ss_list_1014_028c[] = { + &pci_ss_info_1014_028c_1014_028d, + &pci_ss_info_1014_028c_1014_02be, + &pci_ss_info_1014_028c_1014_02c0, + &pci_ss_info_1014_028c_1014_030d, + NULL +}; +#define pci_ss_list_1014_02a1 NULL +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_0314 NULL +#define pci_ss_list_1014_3022 NULL +#define pci_ss_list_1014_4022 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#define pci_ss_list_101e_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0477, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_101e_0494, + &pci_ss_info_101e_1960_101e_0503, + &pci_ss_info_101e_1960_101e_0511, + &pci_ss_info_101e_1960_101e_0522, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + &pci_ss_info_101e_1960_103c_60e7, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_1022_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + &pci_ss_info_1022_2000_1259_2702, + &pci_ss_info_1022_2000_1259_2703, + &pci_ss_info_1022_2000_4c53_1000, + &pci_ss_info_1022_2000_4c53_1010, + &pci_ss_info_1022_2000_4c53_1020, + &pci_ss_info_1022_2000_4c53_1030, + &pci_ss_info_1022_2000_4c53_1040, + &pci_ss_info_1022_2000_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2003 NULL +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_208f NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700a NULL +#define pci_ss_list_1022_700b NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7458 NULL +#define pci_ss_list_1022_7459 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7460[] = { + &pci_ss_info_1022_7460_161f_3017, + NULL +}; +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7464[] = { + &pci_ss_info_1022_7464_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7468[] = { + &pci_ss_info_1022_7468_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7469[] = { + &pci_ss_info_1022_7469_1022_2b80, + &pci_ss_info_1022_7469_161f_3017, + NULL +}; +#define pci_ss_list_1022_746a NULL +static const pciSubsystemInfo *pci_ss_list_1022_746b[] = { + &pci_ss_info_1022_746b_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_746d[] = { + &pci_ss_info_1022_746d_161f_3017, + NULL +}; +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1022_756b NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +static const pciSubsystemInfo *pci_ss_list_1023_2001[] = { + &pci_ss_info_1023_2001_122d_1400, + NULL +}; +#define pci_ss_list_1023_2100 NULL +#define pci_ss_list_1023_2200 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + &pci_ss_info_1023_8620_1014_1025, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_1671 NULL +#define pci_ss_list_1025_1672 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +#define pci_ss_list_1028_0009 NULL +#define pci_ss_list_1028_000a NULL +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000d NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_1028_0010 NULL +#define pci_ss_list_1028_0011 NULL +#define pci_ss_list_1028_0012 NULL +static const pciSubsystemInfo *pci_ss_list_1028_0013[] = { + &pci_ss_info_1028_0013_1028_016c, + &pci_ss_info_1028_0013_1028_016d, + &pci_ss_info_1028_0013_1028_016e, + &pci_ss_info_1028_0013_1028_016f, + &pci_ss_info_1028_0013_1028_0170, + NULL +}; +#define pci_ss_list_1028_0014 NULL +#define pci_ss_list_1028_0015 NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102a_001f[] = { + &pci_ss_info_102a_001f_9005_000f, + &pci_ss_info_102a_001f_9005_0106, + &pci_ss_info_102a_001f_9005_a180, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00c5[] = { + &pci_ss_info_102a_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00cf[] = { + &pci_ss_info_102a_00cf_1028_0106, + &pci_ss_info_102a_00cf_1028_0121, + NULL +}; +#endif +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0100 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0d43, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + &pci_ss_info_102b_0527_102b_0850, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0528[] = { + &pci_ss_info_102b_0528_102b_1020, + &pci_ss_info_102b_0528_102b_1030, + &pci_ss_info_102b_0528_102b_14e1, + &pci_ss_info_102b_0528_102b_2021, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2537[] = { + &pci_ss_info_102b_2537_102b_1820, + &pci_ss_info_102b_2537_102b_1830, + &pci_ss_info_102b_2537_102b_1c10, + &pci_ss_info_102b_2537_102b_2811, + &pci_ss_info_102b_2537_102b_2c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2538[] = { + &pci_ss_info_102b_2538_102b_08c7, + &pci_ss_info_102b_2538_102b_0907, + &pci_ss_info_102b_2538_102b_1047, + &pci_ss_info_102b_2538_102b_1087, + &pci_ss_info_102b_2538_102b_2538, + &pci_ss_info_102b_2538_102b_3007, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + &pci_ss_info_102c_00c0_4c53_1000, + &pci_ss_info_102c_00c0_4c53_1010, + &pci_ss_info_102c_00c0_4c53_1020, + &pci_ss_info_102c_00c0_4c53_1030, + &pci_ss_info_102c_00c0_4c53_1050, + &pci_ss_info_102c_00c0_4c53_1051, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + &pci_ss_info_102c_00e5_1179_0001, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_102c_0c30[] = { + &pci_ss_info_102c_0c30_4c53_1000, + &pci_ss_info_102c_0c30_4c53_1050, + &pci_ss_info_102c_0c30_4c53_1051, + &pci_ss_info_102c_0c30_4c53_1080, + NULL +}; +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#define pci_ss_list_102f_000a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#define pci_ss_list_102f_0030 NULL +#define pci_ss_list_102f_0031 NULL +#define pci_ss_list_102f_0105 NULL +#define pci_ss_list_102f_0106 NULL +#define pci_ss_list_102f_0107 NULL +#define pci_ss_list_102f_0108 NULL +#define pci_ss_list_102f_0180 NULL +#define pci_ss_list_102f_0181 NULL +#define pci_ss_list_102f_0182 NULL +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0000 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1033_0035, + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_14c2_0105, + &pci_ss_info_1033_0035_1799_0001, + &pci_ss_info_1033_0035_1931_000a, + &pci_ss_info_1033_0035_1931_000b, + &pci_ss_info_1033_0035_807d_0035, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +#define pci_ss_list_1033_0072 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a5 NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +#define pci_ss_list_1033_00ce NULL +#define pci_ss_list_1033_00df NULL +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_14c2_0205, + &pci_ss_info_1033_00e0_1799_0002, + &pci_ss_info_1033_00e0_807d_1043, + NULL +}; +#define pci_ss_list_1033_00e7 NULL +#define pci_ss_list_1033_00f2 NULL +#define pci_ss_list_1033_00f3 NULL +#define pci_ss_list_1033_010c NULL +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0003 NULL +#define pci_ss_list_1039_0004 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_000a NULL +#define pci_ss_list_1039_0016 NULL +#define pci_ss_list_1039_0018 NULL +#define pci_ss_list_1039_0180 NULL +#define pci_ss_list_1039_0181 NULL +#define pci_ss_list_1039_0182 NULL +#define pci_ss_list_1039_0191 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0550 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0648 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0655 NULL +#define pci_ss_list_1039_0660 NULL +#define pci_ss_list_1039_0661 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0741 NULL +#define pci_ss_list_1039_0745 NULL +#define pci_ss_list_1039_0746 NULL +#define pci_ss_list_1039_0755 NULL +#define pci_ss_list_1039_0760 NULL +#define pci_ss_list_1039_0761 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1019_0a14, + &pci_ss_info_1039_0900_1039_0900, + &pci_ss_info_1039_0900_1043_8035, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_0963 NULL +#define pci_ss_list_1039_0964 NULL +#define pci_ss_list_1039_0965 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + &pci_ss_info_1039_5513_1043_8035, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + &pci_ss_info_1039_6300_1043_8035, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6330[] = { + &pci_ss_info_1039_6330_1039_6330, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1019_0a14, + &pci_ss_info_1039_7001_1039_7000, + &pci_ss_info_1039_7001_1462_5470, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +#define pci_ss_list_1039_7012 NULL +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_1039_7019 NULL +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1006 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_100a NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + &pci_ss_info_103c_1048_103c_1301, + NULL +}; +#define pci_ss_list_103c_1054 NULL +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_10f0 NULL +#define pci_ss_list_103c_10f1 NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_127c NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_1291 NULL +#define pci_ss_list_103c_12b4 NULL +#define pci_ss_list_103c_12fa NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_103c_3080 NULL +#define pci_ss_list_103c_3220 NULL +#define pci_ss_list_103c_3230 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043_0675[] = { + &pci_ss_info_1043_0675_0675_1704, + &pci_ss_info_1043_0675_0675_1707, + &pci_ss_info_1043_0675_10cf_105e, + NULL +}; +#define pci_ss_list_1043_4015 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1043_4057 NULL +#define pci_ss_list_1043_8043 NULL +#define pci_ss_list_1043_807b NULL +#define pci_ss_list_1043_80bb NULL +#define pci_ss_list_1043_80c5 NULL +#define pci_ss_list_1043_80df NULL +#define pci_ss_list_1043_8187 NULL +#define pci_ss_list_1043_8188 NULL +#endif +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1044_a511[] = { + &pci_ss_info_1044_a511_1044_c032, + &pci_ss_info_1044_a511_1044_c035, + NULL +}; +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0c60 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048_8901[] = { + &pci_ss_info_1048_8901_1048_0935, + NULL +}; +#endif +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0209 NULL +#define pci_ss_list_104a_020a NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_021a NULL +#define pci_ss_list_104a_021b NULL +#define pci_ss_list_104a_0500 NULL +#define pci_ss_list_104a_0564 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104a_55cc NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a34, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_1048_0a36, + &pci_ss_info_104c_3d07_1048_0a43, + &pci_ss_info_104c_3d07_1048_0a44, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8020[] = { + &pci_ss_info_104c_8020_11bd_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8023[] = { + &pci_ss_info_104c_8023_103c_088c, + &pci_ss_info_104c_8023_1043_808b, + NULL +}; +#define pci_ss_list_104c_8024 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8025[] = { + &pci_ss_info_104c_8025_1458_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8026[] = { + &pci_ss_info_104c_8026_1043_808d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8029[] = { + &pci_ss_info_104c_8029_1028_0163, + &pci_ss_info_104c_8029_1028_0196, + &pci_ss_info_104c_8029_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_802b[] = { + &pci_ss_info_104c_802b_1028_0139, + &pci_ss_info_104c_802b_1028_014e, + NULL +}; +#define pci_ss_list_104c_802e NULL +static const pciSubsystemInfo *pci_ss_list_104c_8031[] = { + &pci_ss_info_104c_8031_103c_099c, + &pci_ss_info_104c_8031_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8032[] = { + &pci_ss_info_104c_8032_103c_099c, + &pci_ss_info_104c_8032_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8033[] = { + &pci_ss_info_104c_8033_103c_099c, + &pci_ss_info_104c_8033_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8034[] = { + &pci_ss_info_104c_8034_103c_099c, + &pci_ss_info_104c_8034_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8035[] = { + &pci_ss_info_104c_8035_103c_099c, + NULL +}; +#define pci_ss_list_104c_8036 NULL +#define pci_ss_list_104c_8038 NULL +#define pci_ss_list_104c_8201 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8204[] = { + &pci_ss_info_104c_8204_1028_0139, + &pci_ss_info_104c_8204_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8400[] = { + &pci_ss_info_104c_8400_1186_3b00, + &pci_ss_info_104c_8400_1186_3b01, + &pci_ss_info_104c_8400_16ab_8501, + NULL +}; +#define pci_ss_list_104c_8401 NULL +#define pci_ss_list_104c_9000 NULL +static const pciSubsystemInfo *pci_ss_list_104c_9066[] = { + &pci_ss_info_104c_9066_104c_9066, + &pci_ss_info_104c_9066_1186_3b04, + &pci_ss_info_104c_9066_1186_3b05, + &pci_ss_info_104c_9066_13d1_aba0, + NULL +}; +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +static const pciSubsystemInfo *pci_ss_list_104c_a106[] = { + &pci_ss_info_104c_a106_175c_5000, + &pci_ss_info_104c_a106_175c_6400, + &pci_ss_info_104c_a106_175c_8700, + NULL +}; +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac16[] = { + &pci_ss_info_104c_ac16_1014_0092, + NULL +}; +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + &pci_ss_info_104c_ac1b_1014_0130, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac1c[] = { + &pci_ss_info_104c_ac1c_0e11_b121, + &pci_ss_info_104c_ac1c_1028_0088, + NULL +}; +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac44[] = { + &pci_ss_info_104c_ac44_1028_0163, + &pci_ss_info_104c_ac44_1028_0196, + &pci_ss_info_104c_ac44_1071_8160, + NULL +}; +#define pci_ss_list_104c_ac46 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac47[] = { + &pci_ss_info_104c_ac47_1028_0139, + &pci_ss_info_104c_ac47_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac4a[] = { + &pci_ss_info_104c_ac4a_1028_0139, + &pci_ss_info_104c_ac4a_1028_014e, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_0e11_004e, + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_1028_00b1, + &pci_ss_info_104c_ac51_1028_012a, + &pci_ss_info_104c_ac51_1033_80cd, + &pci_ss_info_104c_ac51_1095_10cf, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +#define pci_ss_list_104c_ac54 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac56[] = { + &pci_ss_info_104c_ac56_1014_0528, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac60[] = { + &pci_ss_info_104c_ac60_175c_5100, + &pci_ss_info_104c_ac60_175c_6100, + &pci_ss_info_104c_ac60_175c_6200, + &pci_ss_info_104c_ac60_175c_8800, + NULL +}; +#define pci_ss_list_104c_ac8d NULL +#define pci_ss_list_104c_ac8e NULL +#define pci_ss_list_104c_ac8f NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8004 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +static const pciSubsystemInfo *pci_ss_list_1050_6692[] = { + &pci_ss_info_1050_6692_1043_1702, + &pci_ss_info_1050_6692_1043_1703, + &pci_ss_info_1050_6692_1043_1707, + &pci_ss_info_1050_6692_144f_1702, + &pci_ss_info_1050_6692_144f_1703, + &pci_ss_info_1050_6692_144f_1707, + NULL +}; +#define pci_ss_list_1050_9921 NULL +#define pci_ss_list_1050_9922 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0008 NULL +#define pci_ss_list_1057_0009 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_14fb_0101, + &pci_ss_info_1057_1801_14fb_0102, + &pci_ss_info_1057_1801_14fb_0202, + &pci_ss_info_1057_1801_14fb_0611, + &pci_ss_info_1057_1801_14fb_0612, + &pci_ss_info_1057_1801_14fb_0613, + &pci_ss_info_1057_1801_14fb_0614, + &pci_ss_info_1057_1801_14fb_0621, + &pci_ss_info_1057_1801_14fb_0622, + &pci_ss_info_1057_1801_14fb_0810, + &pci_ss_info_1057_1801_175c_4200, + &pci_ss_info_1057_1801_175c_4300, + &pci_ss_info_1057_1801_175c_4400, + &pci_ss_info_1057_1801_ecc0_0010, + &pci_ss_info_1057_1801_ecc0_0020, + &pci_ss_info_1057_1801_ecc0_0030, + &pci_ss_info_1057_1801_ecc0_0031, + &pci_ss_info_1057_1801_ecc0_0040, + &pci_ss_info_1057_1801_ecc0_0041, + &pci_ss_info_1057_1801_ecc0_0050, + &pci_ss_info_1057_1801_ecc0_0051, + &pci_ss_info_1057_1801_ecc0_0070, + &pci_ss_info_1057_1801_ecc0_0071, + &pci_ss_info_1057_1801_ecc0_0072, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_18c1 NULL +static const pciSubsystemInfo *pci_ss_list_1057_3410[] = { + &pci_ss_info_1057_3410_ecc0_0050, + &pci_ss_info_1057_3410_ecc0_0051, + &pci_ss_info_1057_3410_ecc0_0060, + &pci_ss_info_1057_3410_ecc0_0070, + &pci_ss_info_1057_3410_ecc0_0071, + &pci_ss_info_1057_3410_ecc0_0072, + &pci_ss_info_1057_3410_ecc0_0080, + &pci_ss_info_1057_3410_ecc0_0081, + &pci_ss_info_1057_3410_ecc0_0090, + &pci_ss_info_1057_3410_ecc0_00a0, + &pci_ss_info_1057_3410_ecc0_00b0, + &pci_ss_info_1057_3410_ecc0_0100, + NULL +}; +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_5803 NULL +#define pci_ss_list_1057_5806 NULL +#define pci_ss_list_1057_5808 NULL +#define pci_ss_list_1057_6400 NULL +#define pci_ss_list_1057_6405 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3318 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3319[] = { + &pci_ss_info_105a_3319_8086_3427, + NULL +}; +#define pci_ss_list_105a_3371 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3373[] = { + &pci_ss_info_105a_3373_1043_80f5, + &pci_ss_info_105a_3373_1462_702e, + NULL +}; +#define pci_ss_list_105a_3375 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3376[] = { + &pci_ss_info_105a_3376_1043_809e, + NULL +}; +#define pci_ss_list_105a_3515 NULL +#define pci_ss_list_105a_3519 NULL +#define pci_ss_list_105a_3571 NULL +#define pci_ss_list_105a_3574 NULL +#define pci_ss_list_105a_3577 NULL +#define pci_ss_list_105a_3d17 NULL +#define pci_ss_list_105a_3d18 NULL +#define pci_ss_list_105a_3d73 NULL +#define pci_ss_list_105a_3d75 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d69[] = { + &pci_ss_info_105a_4d69_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_1043_807e, + &pci_ss_info_105a_5275_105a_0275, + &pci_ss_info_105a_5275_105a_1275, + &pci_ss_info_105a_5275_1458_b001, + NULL +}; +#define pci_ss_list_105a_5300 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6268[] = { + &pci_ss_info_105a_6268_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_6622 NULL +#define pci_ss_list_105a_6624 NULL +#define pci_ss_list_105a_6626 NULL +#define pci_ss_list_105a_6629 NULL +#define pci_ss_list_105a_7275 NULL +#define pci_ss_list_105a_8002 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_5348[] = { + &pci_ss_info_105d_5348_105d_0037, + NULL +}; +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_0301 NULL +#define pci_ss_list_1067_0304 NULL +#define pci_ss_list_1067_0308 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069_0050[] = { + &pci_ss_info_1069_0050_1069_0050, + &pci_ss_info_1069_0050_1069_0052, + &pci_ss_info_1069_0050_1069_0054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_b166[] = { + &pci_ss_info_1069_b166_1014_0242, + &pci_ss_info_1069_b166_1014_0266, + &pci_ss_info_1069_b166_1014_0278, + &pci_ss_info_1069_b166_1014_02d3, + &pci_ss_info_1069_b166_1014_02d4, + &pci_ss_info_1069_b166_1069_0200, + &pci_ss_info_1069_b166_1069_0202, + &pci_ss_info_1069_b166_1069_0204, + &pci_ss_info_1069_b166_1069_0206, + NULL +}; +#define pci_ss_list_1069_ba55 NULL +static const pciSubsystemInfo *pci_ss_list_1069_ba56[] = { + &pci_ss_info_1069_ba56_1069_0030, + &pci_ss_info_1069_ba56_1069_0040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_ba57[] = { + &pci_ss_info_1069_ba57_1069_0072, + NULL +}; +#endif +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000c NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b_0031[] = { + &pci_ss_info_106b_0031_106b_5811, + NULL +}; +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_0035 NULL +#define pci_ss_list_106b_0036 NULL +#define pci_ss_list_106b_003b NULL +#define pci_ss_list_106b_003e NULL +#define pci_ss_list_106b_003f NULL +#define pci_ss_list_106b_0040 NULL +#define pci_ss_list_106b_0041 NULL +#define pci_ss_list_106b_0042 NULL +#define pci_ss_list_106b_0043 NULL +#define pci_ss_list_106b_0045 NULL +#define pci_ss_list_106b_0046 NULL +#define pci_ss_list_106b_0047 NULL +#define pci_ss_list_106b_0048 NULL +#define pci_ss_list_106b_0049 NULL +#define pci_ss_list_106b_004b NULL +#define pci_ss_list_106b_004c NULL +#define pci_ss_list_106b_004f NULL +#define pci_ss_list_106b_0050 NULL +#define pci_ss_list_106b_0051 NULL +#define pci_ss_list_106b_0052 NULL +#define pci_ss_list_106b_0053 NULL +#define pci_ss_list_106b_0054 NULL +#define pci_ss_list_106b_0055 NULL +#define pci_ss_list_106b_0058 NULL +#define pci_ss_list_106b_0059 NULL +#define pci_ss_list_106b_0066 NULL +#define pci_ss_list_106b_0067 NULL +#define pci_ss_list_106b_0068 NULL +#define pci_ss_list_106b_0069 NULL +#define pci_ss_list_106b_006a NULL +#define pci_ss_list_106b_006b NULL +#define pci_ss_list_106b_1645 NULL +#endif +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1071_8160 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1077_2200[] = { + &pci_ss_info_1077_2200_1077_0002, + NULL +}; +#define pci_ss_list_1077_2300 NULL +#define pci_ss_list_1077_2312 NULL +#define pci_ss_list_1077_2322 NULL +#define pci_ss_list_1077_2422 NULL +#define pci_ss_list_1077_2432 NULL +#define pci_ss_list_1077_3010 NULL +#define pci_ss_list_1077_3022 NULL +#define pci_ss_list_1077_4010 NULL +#define pci_ss_list_1077_4022 NULL +#define pci_ss_list_1077_6312 NULL +#define pci_ss_list_1077_6322 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107d_2134 NULL +#define pci_ss_list_107d_2971 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_1648 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_8002 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_108e_a801 NULL +#define pci_ss_list_108e_abba NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1091_07a0 NULL +#define pci_ss_list_1091_1091 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1310 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_14e0 NULL +#define pci_ss_list_1093_14f0 NULL +#define pci_ss_list_1093_17d0 NULL +#define pci_ss_list_1093_1870 NULL +#define pci_ss_list_1093_1880 NULL +#define pci_ss_list_1093_18b0 NULL +#define pci_ss_list_1093_2410 NULL +#define pci_ss_list_1093_2890 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_2a70 NULL +#define pci_ss_list_1093_2a80 NULL +#define pci_ss_list_1093_2c80 NULL +#define pci_ss_list_1093_2ca0 NULL +#define pci_ss_list_1093_70b8 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0240 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#define pci_ss_list_1095_0648 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0680[] = { + &pci_ss_info_1095_0680_1095_3680, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3112[] = { + &pci_ss_info_1095_3112_1095_3112, + &pci_ss_info_1095_3112_1095_6112, + &pci_ss_info_1095_3112_9005_0250, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3114[] = { + &pci_ss_info_1095_3114_1095_3114, + &pci_ss_info_1095_3114_1095_6114, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3124[] = { + &pci_ss_info_1095_3124_1095_3124, + NULL +}; +#define pci_ss_list_1095_3132 NULL +static const pciSubsystemInfo *pci_ss_list_1095_3512[] = { + &pci_ss_info_1095_3512_1095_3512, + &pci_ss_info_1095_3512_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_032e NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_0071_0101, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0002, + &pci_ss_info_109e_036e_1461_0003, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_1461_0761, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1822_0001, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_18ac_d500, + &pci_ss_info_109e_036e_270f_fc00, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_0071_0101, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0002, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_1461_0761, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_1822_0001, + &pci_ss_info_109e_0878_18ac_d500, + &pci_ss_info_109e_0878_270f_fc00, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_3052 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9_0009[] = { + &pci_ss_info_10a9_0009_10a9_8002, + NULL +}; +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_100a NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_4001 NULL +#define pci_ss_list_10a9_4002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#define pci_ss_list_10a9_8010 NULL +#define pci_ss_list_10a9_8018 NULL +#endif +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1042 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2540 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_6540[] = { + &pci_ss_info_10b5_6540_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6541[] = { + &pci_ss_info_10b5_6541_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6542[] = { + &pci_ss_info_10b5_6542_4c53_10e0, + NULL +}; +#define pci_ss_list_10b5_8111 NULL +#define pci_ss_list_10b5_8114 NULL +#define pci_ss_list_10b5_8516 NULL +#define pci_ss_list_10b5_8532 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_10b5_2862, + &pci_ss_info_10b5_9030_10b5_2906, + &pci_ss_info_10b5_9030_10b5_2940, + &pci_ss_info_10b5_9030_10b5_2977, + &pci_ss_info_10b5_9030_10b5_2978, + &pci_ss_info_10b5_9030_10b5_3025, + &pci_ss_info_10b5_9030_10b5_3068, + &pci_ss_info_10b5_9030_1397_3136, + &pci_ss_info_10b5_9030_1397_3137, + &pci_ss_info_10b5_9030_1518_0200, + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_1067, + &pci_ss_info_10b5_9050_10b5_1172, + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2221, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_2431, + &pci_ss_info_10b5_9050_10b5_2905, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1498_0362, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_2036, + &pci_ss_info_10b5_9050_5654_3132, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + &pci_ss_info_10b5_9054_10b5_2696, + &pci_ss_info_10b5_9054_10b5_2717, + &pci_ss_info_10b5_9054_10b5_2844, + &pci_ss_info_10b5_9054_12c7_4001, + &pci_ss_info_10b5_9054_12d9_0002, + &pci_ss_info_10b5_9054_16df_0011, + &pci_ss_info_10b5_9054_16df_0012, + &pci_ss_info_10b5_9054_16df_0013, + &pci_ss_info_10b5_9054_16df_0014, + &pci_ss_info_10b5_9054_16df_0015, + &pci_ss_info_10b5_9054_16df_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9056[] = { + &pci_ss_info_10b5_9056_10b5_2979, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_103c_10eb, + &pci_ss_info_10b5_9080_103c_10ec, + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + &pci_ss_info_10b5_9080_12d9_0002, + &pci_ss_info_10b5_9080_12df_4422, + NULL +}; +#define pci_ss_list_10b5_bb04 NULL +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_0013[] = { + &pci_ss_info_10b7_0013_10b7_2031, + NULL +}; +#define pci_ss_list_10b7_0910 NULL +#define pci_ss_list_10b7_1006 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_1201 NULL +#define pci_ss_list_10b7_1202 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1700[] = { + &pci_ss_info_10b7_1700_1043_80eb, + &pci_ss_info_10b7_1700_10b7_0010, + &pci_ss_info_10b7_1700_10b7_0020, + &pci_ss_info_10b7_1700_147b_1407, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6000 NULL +#define pci_ss_list_10b7_6001 NULL +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7770 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_80eb NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_1028_0097, + &pci_ss_info_10b7_9200_1028_00fe, + &pci_ss_info_10b7_9200_1028_012a, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + &pci_ss_info_10b7_9200_10f1_2466, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9201[] = { + &pci_ss_info_10b7_9201_1043_80ab, + NULL +}; +#define pci_ss_list_10b7_9202 NULL +#define pci_ss_list_10b7_9210 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990a NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_2802 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +#define pci_ss_list_10b9_0101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_0780 NULL +#define pci_ss_list_10b9_0782 NULL +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_1014_053b, + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1573 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1672 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_1689 NULL +#define pci_ss_list_10b9_1695 NULL +#define pci_ss_list_10b9_1697 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_3323 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +#define pci_ss_list_10b9_5228 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1014_050f, + &pci_ss_info_10b9_5229_1014_053d, + &pci_ss_info_10b9_5229_103c_0024, + &pci_ss_info_10b9_5229_1043_8053, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5237[] = { + &pci_ss_info_10b9_5237_1014_0540, + &pci_ss_info_10b9_5237_103c_0024, + &pci_ss_info_10b9_5237_104d_810f, + NULL +}; +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5246 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_524b NULL +#define pci_ss_list_10b9_524c NULL +#define pci_ss_list_10b9_524d NULL +#define pci_ss_list_10b9_524e NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +#define pci_ss_list_10b9_5263 NULL +#define pci_ss_list_10b9_5281 NULL +#define pci_ss_list_10b9_5287 NULL +#define pci_ss_list_10b9_5288 NULL +#define pci_ss_list_10b9_5289 NULL +#define pci_ss_list_10b9_5450 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + &pci_ss_info_10b9_5451_1014_053e, + &pci_ss_info_10b9_5451_103c_0024, + &pci_ss_info_10b9_5451_10b9_5451, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5457[] = { + &pci_ss_info_10b9_5457_1014_0535, + &pci_ss_info_10b9_5457_103c_0024, + NULL +}; +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5461 NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_1014_0510, + &pci_ss_info_10b9_7101_1014_053c, + &pci_ss_info_10b9_7101_103c_0024, + NULL +}; +#endif +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10ba_0304 NULL +#define pci_ss_list_10ba_0308 NULL +#define pci_ss_list_10ba_1002 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + &pci_ss_info_10c8_0005_1028_0088, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_0088, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cc_0660 NULL +#define pci_ss_list_10cc_0661 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0431 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8626 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10dd_0100 NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c19, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1048_0c1c, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1048_0c21, + &pci_ss_info_10de_0028_1048_0c28, + &pci_ss_info_10de_0028_1048_0c29, + &pci_ss_info_10de_0028_1048_0c2a, + &pci_ss_info_10de_0028_1048_0c2b, + &pci_ss_info_10de_0028_1048_0c31, + &pci_ss_info_10de_0028_1048_0c32, + &pci_ss_info_10de_0028_1048_0c33, + &pci_ss_info_10de_0028_1048_0c34, + &pci_ss_info_10de_0028_107d_2134, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1048_0c2e, + &pci_ss_info_10de_0029_1048_0c2f, + &pci_ss_info_10de_0029_1048_0c30, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1048_0c20, + &pci_ss_info_10de_002c_1048_0c21, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_1048_0c3b, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + &pci_ss_info_10de_002d_1569_002d, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +#define pci_ss_list_10de_0034 NULL +#define pci_ss_list_10de_0035 NULL +#define pci_ss_list_10de_0036 NULL +#define pci_ss_list_10de_0037 NULL +#define pci_ss_list_10de_0038 NULL +#define pci_ss_list_10de_003a NULL +#define pci_ss_list_10de_003b NULL +#define pci_ss_list_10de_003c NULL +#define pci_ss_list_10de_003d NULL +#define pci_ss_list_10de_003e NULL +#define pci_ss_list_10de_0040 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0041[] = { + &pci_ss_info_10de_0041_1043_817b, + NULL +}; +#define pci_ss_list_10de_0042 NULL +#define pci_ss_list_10de_0043 NULL +#define pci_ss_list_10de_0045 NULL +#define pci_ss_list_10de_0046 NULL +#define pci_ss_list_10de_0048 NULL +#define pci_ss_list_10de_0049 NULL +#define pci_ss_list_10de_004e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0050[] = { + &pci_ss_info_10de_0050_1043_815a, + &pci_ss_info_10de_0050_1458_0c11, + &pci_ss_info_10de_0050_1462_7100, + NULL +}; +#define pci_ss_list_10de_0051 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0052[] = { + &pci_ss_info_10de_0052_1043_815a, + &pci_ss_info_10de_0052_1458_0c11, + &pci_ss_info_10de_0052_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0053[] = { + &pci_ss_info_10de_0053_1043_815a, + &pci_ss_info_10de_0053_1458_5002, + &pci_ss_info_10de_0053_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0054[] = { + &pci_ss_info_10de_0054_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0055[] = { + &pci_ss_info_10de_0055_1043_815a, + NULL +}; +#define pci_ss_list_10de_0056 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0057[] = { + &pci_ss_info_10de_0057_1043_8141, + &pci_ss_info_10de_0057_1458_e000, + &pci_ss_info_10de_0057_1462_7100, + NULL +}; +#define pci_ss_list_10de_0058 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0059[] = { + &pci_ss_info_10de_0059_1043_812a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005a[] = { + &pci_ss_info_10de_005a_1043_815a, + &pci_ss_info_10de_005a_1458_5004, + &pci_ss_info_10de_005a_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005b[] = { + &pci_ss_info_10de_005b_1043_815a, + &pci_ss_info_10de_005b_1458_5004, + &pci_ss_info_10de_005b_1462_7100, + NULL +}; +#define pci_ss_list_10de_005c NULL +#define pci_ss_list_10de_005d NULL +static const pciSubsystemInfo *pci_ss_list_10de_005e[] = { + &pci_ss_info_10de_005e_1458_5000, + &pci_ss_info_10de_005e_1462_7100, + NULL +}; +#define pci_ss_list_10de_005f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + NULL +}; +#define pci_ss_list_10de_0064 NULL +#define pci_ss_list_10de_0065 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0066[] = { + &pci_ss_info_10de_0066_1043_80a7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + NULL +}; +#define pci_ss_list_10de_006a NULL +static const pciSubsystemInfo *pci_ss_list_10de_006b[] = { + &pci_ss_info_10de_006b_10de_006b, + NULL +}; +#define pci_ss_list_10de_006c NULL +#define pci_ss_list_10de_006d NULL +#define pci_ss_list_10de_006e NULL +#define pci_ss_list_10de_0080 NULL +#define pci_ss_list_10de_0084 NULL +#define pci_ss_list_10de_0085 NULL +#define pci_ss_list_10de_0086 NULL +#define pci_ss_list_10de_0087 NULL +#define pci_ss_list_10de_0088 NULL +#define pci_ss_list_10de_008a NULL +#define pci_ss_list_10de_008b NULL +#define pci_ss_list_10de_008c NULL +#define pci_ss_list_10de_008e NULL +#define pci_ss_list_10de_0091 NULL +#define pci_ss_list_10de_0092 NULL +#define pci_ss_list_10de_0099 NULL +#define pci_ss_list_10de_009d NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +#define pci_ss_list_10de_00c0 NULL +#define pci_ss_list_10de_00c1 NULL +#define pci_ss_list_10de_00c2 NULL +#define pci_ss_list_10de_00c3 NULL +#define pci_ss_list_10de_00c8 NULL +#define pci_ss_list_10de_00c9 NULL +#define pci_ss_list_10de_00cc NULL +#define pci_ss_list_10de_00cd NULL +#define pci_ss_list_10de_00ce NULL +#define pci_ss_list_10de_00d0 NULL +#define pci_ss_list_10de_00d1 NULL +#define pci_ss_list_10de_00d2 NULL +#define pci_ss_list_10de_00d3 NULL +#define pci_ss_list_10de_00d4 NULL +#define pci_ss_list_10de_00d5 NULL +#define pci_ss_list_10de_00d6 NULL +#define pci_ss_list_10de_00d7 NULL +#define pci_ss_list_10de_00d8 NULL +#define pci_ss_list_10de_00d9 NULL +#define pci_ss_list_10de_00da NULL +#define pci_ss_list_10de_00dd NULL +static const pciSubsystemInfo *pci_ss_list_10de_00df[] = { + &pci_ss_info_10de_00df_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e0[] = { + &pci_ss_info_10de_00e0_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e1[] = { + &pci_ss_info_10de_00e1_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e2 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e3[] = { + &pci_ss_info_10de_00e3_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e4[] = { + &pci_ss_info_10de_00e4_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e5[] = { + &pci_ss_info_10de_00e5_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e6 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e7[] = { + &pci_ss_info_10de_00e7_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e8[] = { + &pci_ss_info_10de_00e8_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00ea[] = { + &pci_ss_info_10de_00ea_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00ed NULL +#define pci_ss_list_10de_00ee NULL +#define pci_ss_list_10de_00f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f1[] = { + &pci_ss_info_10de_00f1_1043_81a6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00f2[] = { + &pci_ss_info_10de_00f2_1682_211c, + NULL +}; +#define pci_ss_list_10de_00f3 NULL +#define pci_ss_list_10de_00f8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f9[] = { + &pci_ss_info_10de_00f9_1682_2120, + NULL +}; +#define pci_ss_list_10de_00fa NULL +#define pci_ss_list_10de_00fb NULL +#define pci_ss_list_10de_00fc NULL +#define pci_ss_list_10de_00fd NULL +#define pci_ss_list_10de_00fe NULL +#define pci_ss_list_10de_00ff NULL +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1048_0c41, + &pci_ss_info_10de_0100_1048_0c43, + &pci_ss_info_10de_0100_1048_0c48, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1048_0c42, + &pci_ss_info_10de_0101_107d_2822, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0103[] = { + &pci_ss_info_10de_0103_1048_0c40, + &pci_ss_info_10de_0103_1048_0c44, + &pci_ss_info_10de_0103_1048_0c45, + &pci_ss_info_10de_0103_1048_0c4a, + &pci_ss_info_10de_0103_1048_0c4b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1048_0c60, + &pci_ss_info_10de_0110_1048_0c61, + &pci_ss_info_10de_0110_1048_0c63, + &pci_ss_info_10de_0110_1048_0c64, + &pci_ss_info_10de_0110_1048_0c65, + &pci_ss_info_10de_0110_1048_0c66, + &pci_ss_info_10de_0110_10de_0091, + &pci_ss_info_10de_0110_10de_00a1, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +#define pci_ss_list_10de_0140 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0141[] = { + &pci_ss_info_10de_0141_1458_3124, + NULL +}; +#define pci_ss_list_10de_0142 NULL +#define pci_ss_list_10de_0144 NULL +#define pci_ss_list_10de_0145 NULL +#define pci_ss_list_10de_0146 NULL +#define pci_ss_list_10de_0147 NULL +#define pci_ss_list_10de_0148 NULL +#define pci_ss_list_10de_0149 NULL +#define pci_ss_list_10de_014e NULL +#define pci_ss_list_10de_014f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_1048_0c50, + &pci_ss_info_10de_0150_1048_0c52, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_107d_2842, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + &pci_ss_info_10de_0151_1462_5506, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0160 NULL +#define pci_ss_list_10de_0161 NULL +#define pci_ss_list_10de_0162 NULL +#define pci_ss_list_10de_0163 NULL +#define pci_ss_list_10de_0164 NULL +#define pci_ss_list_10de_0165 NULL +#define pci_ss_list_10de_0166 NULL +#define pci_ss_list_10de_0167 NULL +#define pci_ss_list_10de_0168 NULL +#define pci_ss_list_10de_0169 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_10b0_0002, + &pci_ss_info_10de_0171_10de_0008, + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_1462_8852, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0176[] = { + &pci_ss_info_10de_0176_4c53_1090, + NULL +}; +#define pci_ss_list_10de_0177 NULL +#define pci_ss_list_10de_0178 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0179[] = { + &pci_ss_info_10de_0179_10de_0179, + NULL +}; +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_017d NULL +static const pciSubsystemInfo *pci_ss_list_10de_0181[] = { + &pci_ss_info_10de_0181_1043_806f, + &pci_ss_info_10de_0181_1462_8880, + &pci_ss_info_10de_0181_1462_8900, + &pci_ss_info_10de_0181_1462_9350, + &pci_ss_info_10de_0181_147b_8f0d, + NULL +}; +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0185 NULL +#define pci_ss_list_10de_0186 NULL +#define pci_ss_list_10de_0187 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_018c NULL +#define pci_ss_list_10de_018d NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b0 NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +#define pci_ss_list_10de_01e0 NULL +#define pci_ss_list_10de_01e8 NULL +#define pci_ss_list_10de_01ea NULL +#define pci_ss_list_10de_01eb NULL +#define pci_ss_list_10de_01ec NULL +#define pci_ss_list_10de_01ed NULL +#define pci_ss_list_10de_01ee NULL +#define pci_ss_list_10de_01ef NULL +#define pci_ss_list_10de_01f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + &pci_ss_info_10de_0200_1048_0c70, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0211 NULL +#define pci_ss_list_10de_0212 NULL +#define pci_ss_list_10de_0215 NULL +#define pci_ss_list_10de_0221 NULL +#define pci_ss_list_10de_0240 NULL +#define pci_ss_list_10de_0241 NULL +#define pci_ss_list_10de_0242 NULL +#define pci_ss_list_10de_0243 NULL +#define pci_ss_list_10de_0244 NULL +#define pci_ss_list_10de_0245 NULL +#define pci_ss_list_10de_0246 NULL +#define pci_ss_list_10de_0247 NULL +#define pci_ss_list_10de_0248 NULL +#define pci_ss_list_10de_0249 NULL +#define pci_ss_list_10de_024a NULL +#define pci_ss_list_10de_024b NULL +#define pci_ss_list_10de_024c NULL +#define pci_ss_list_10de_024d NULL +#define pci_ss_list_10de_024e NULL +#define pci_ss_list_10de_024f NULL +#define pci_ss_list_10de_0250 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0251[] = { + &pci_ss_info_10de_0251_1043_8023, + NULL +}; +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +#define pci_ss_list_10de_0260 NULL +#define pci_ss_list_10de_0261 NULL +#define pci_ss_list_10de_0262 NULL +#define pci_ss_list_10de_0263 NULL +#define pci_ss_list_10de_0264 NULL +#define pci_ss_list_10de_0265 NULL +#define pci_ss_list_10de_0266 NULL +#define pci_ss_list_10de_0267 NULL +#define pci_ss_list_10de_0268 NULL +#define pci_ss_list_10de_0269 NULL +#define pci_ss_list_10de_026a NULL +#define pci_ss_list_10de_026b NULL +#define pci_ss_list_10de_026c NULL +#define pci_ss_list_10de_026d NULL +#define pci_ss_list_10de_026e NULL +#define pci_ss_list_10de_026f NULL +#define pci_ss_list_10de_0270 NULL +#define pci_ss_list_10de_0271 NULL +#define pci_ss_list_10de_0272 NULL +#define pci_ss_list_10de_027e NULL +#define pci_ss_list_10de_027f NULL +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0286 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_028c NULL +#define pci_ss_list_10de_02a0 NULL +#define pci_ss_list_10de_02f0 NULL +#define pci_ss_list_10de_02f1 NULL +#define pci_ss_list_10de_02f2 NULL +#define pci_ss_list_10de_02f3 NULL +#define pci_ss_list_10de_02f4 NULL +#define pci_ss_list_10de_02f5 NULL +#define pci_ss_list_10de_02f6 NULL +#define pci_ss_list_10de_02f7 NULL +#define pci_ss_list_10de_02f8 NULL +#define pci_ss_list_10de_02f9 NULL +#define pci_ss_list_10de_02fa NULL +#define pci_ss_list_10de_02fb NULL +#define pci_ss_list_10de_02fc NULL +#define pci_ss_list_10de_02fd NULL +#define pci_ss_list_10de_02fe NULL +#define pci_ss_list_10de_02ff NULL +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10de_0311 NULL +#define pci_ss_list_10de_0312 NULL +#define pci_ss_list_10de_0313 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0314[] = { + &pci_ss_info_10de_0314_1043_814a, + NULL +}; +#define pci_ss_list_10de_0316 NULL +#define pci_ss_list_10de_0317 NULL +#define pci_ss_list_10de_031a NULL +#define pci_ss_list_10de_031b NULL +#define pci_ss_list_10de_031c NULL +#define pci_ss_list_10de_031d NULL +#define pci_ss_list_10de_031e NULL +#define pci_ss_list_10de_031f NULL +#define pci_ss_list_10de_0320 NULL +#define pci_ss_list_10de_0321 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0322[] = { + &pci_ss_info_10de_0322_1462_9171, + &pci_ss_info_10de_0322_1462_9360, + NULL +}; +#define pci_ss_list_10de_0323 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0324[] = { + &pci_ss_info_10de_0324_1028_0196, + &pci_ss_info_10de_0324_1071_8160, + NULL +}; +#define pci_ss_list_10de_0325 NULL +#define pci_ss_list_10de_0326 NULL +#define pci_ss_list_10de_0327 NULL +#define pci_ss_list_10de_0328 NULL +#define pci_ss_list_10de_0329 NULL +#define pci_ss_list_10de_032a NULL +#define pci_ss_list_10de_032b NULL +#define pci_ss_list_10de_032c NULL +#define pci_ss_list_10de_032d NULL +#define pci_ss_list_10de_032f NULL +#define pci_ss_list_10de_0330 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0331[] = { + &pci_ss_info_10de_0331_1043_8145, + NULL +}; +#define pci_ss_list_10de_0332 NULL +#define pci_ss_list_10de_0333 NULL +#define pci_ss_list_10de_0334 NULL +#define pci_ss_list_10de_0338 NULL +#define pci_ss_list_10de_033f NULL +#define pci_ss_list_10de_0341 NULL +#define pci_ss_list_10de_0342 NULL +#define pci_ss_list_10de_0343 NULL +#define pci_ss_list_10de_0344 NULL +#define pci_ss_list_10de_0345 NULL +#define pci_ss_list_10de_0347 NULL +#define pci_ss_list_10de_0348 NULL +#define pci_ss_list_10de_0349 NULL +#define pci_ss_list_10de_034b NULL +#define pci_ss_list_10de_034c NULL +#define pci_ss_list_10de_034e NULL +#define pci_ss_list_10de_034f NULL +#define pci_ss_list_10de_0360 NULL +#define pci_ss_list_10de_0361 NULL +#define pci_ss_list_10de_0362 NULL +#define pci_ss_list_10de_0363 NULL +#define pci_ss_list_10de_0364 NULL +#define pci_ss_list_10de_0365 NULL +#define pci_ss_list_10de_0366 NULL +#define pci_ss_list_10de_0367 NULL +#define pci_ss_list_10de_0368 NULL +#define pci_ss_list_10de_0369 NULL +#define pci_ss_list_10de_036a NULL +#define pci_ss_list_10de_036c NULL +#define pci_ss_list_10de_036d NULL +#define pci_ss_list_10de_036e NULL +#define pci_ss_list_10de_0371 NULL +#define pci_ss_list_10de_0372 NULL +#define pci_ss_list_10de_0373 NULL +#define pci_ss_list_10de_037a NULL +#define pci_ss_list_10de_037e NULL +#define pci_ss_list_10de_037f NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f0a1 NULL +#define pci_ss_list_10df_f0a5 NULL +#define pci_ss_list_10df_f0b5 NULL +#define pci_ss_list_10df_f0d1 NULL +#define pci_ss_list_10df_f0d5 NULL +#define pci_ss_list_10df_f0e1 NULL +#define pci_ss_list_10df_f0e5 NULL +#define pci_ss_list_10df_f0f5 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f701 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f801 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f901 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10df_f981 NULL +#define pci_ss_list_10df_f982 NULL +#define pci_ss_list_10df_fa00 NULL +#define pci_ss_list_10df_fb00 NULL +#define pci_ss_list_10df_fc00 NULL +#define pci_ss_list_10df_fc10 NULL +#define pci_ss_list_10df_fc20 NULL +#define pci_ss_list_10df_fd00 NULL +#define pci_ss_list_10df_fe00 NULL +#define pci_ss_list_10df_ff00 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0148 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e3_8260 NULL +#define pci_ss_list_10e3_8261 NULL +#define pci_ss_list_10e4_8029 NULL +#define pci_ss_list_10e8_1072 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_814c NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_81e6 NULL +#define pci_ss_list_10e8_8291 NULL +#define pci_ss_list_10e8_82c4 NULL +#define pci_ss_list_10e8_82c5 NULL +#define pci_ss_list_10e8_82c6 NULL +#define pci_ss_list_10e8_82c7 NULL +#define pci_ss_list_10e8_82ca NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10e8_82e2 NULL +#define pci_ss_list_10e8_8851 NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10ea_5252 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#define pci_ss_list_10ec_0139 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_0357_000a, + &pci_ss_info_10ec_8139_1025_005a, + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_1043_8109, + &pci_ss_info_10ec_8139_1071_8160, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1113_ec01, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_1458_e000, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_14cb_0200, + &pci_ss_info_10ec_8139_1799_5000, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_9001_1695, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1259_c107, + &pci_ss_info_10ec_8169_1371_434e, + &pci_ss_info_10ec_8169_1458_e000, + &pci_ss_info_10ec_8169_1462_702c, + NULL +}; +#define pci_ss_list_10ec_8180 NULL +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_0314 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ee_3fc6 NULL +#define pci_ss_list_10ee_8381 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#define pci_ss_list_1101_9502 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + &pci_ss_info_1102_0002_1102_8064, + &pci_ss_info_1102_0002_1102_8065, + &pci_ss_info_1102_0002_1102_8067, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + &pci_ss_info_1102_0004_1102_0058, + &pci_ss_info_1102_0004_1102_1007, + &pci_ss_info_1102_0004_1102_2002, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_0007[] = { + &pci_ss_info_1102_0007_1102_0007, + &pci_ss_info_1102_0007_1102_1001, + &pci_ss_info_1102_0007_1102_1002, + &pci_ss_info_1102_0007_1102_1006, + &pci_ss_info_1102_0007_1462_1009, + NULL +}; +#define pci_ss_list_1102_0008 NULL +#define pci_ss_list_1102_100a NULL +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +static const pciSubsystemInfo *pci_ss_list_1102_7005[] = { + &pci_ss_info_1102_7005_1102_1001, + &pci_ss_info_1102_7005_1102_1002, + NULL +}; +#define pci_ss_list_1102_8064 NULL +static const pciSubsystemInfo *pci_ss_list_1102_8938[] = { + &pci_ss_info_1102_8938_1033_80e5, + &pci_ss_info_1102_8938_1071_7150, + &pci_ss_info_1102_8938_110a_5938, + &pci_ss_info_1102_8938_13bd_100c, + &pci_ss_info_1102_8938_13bd_100d, + &pci_ss_info_1102_8938_13bd_100e, + &pci_ss_info_1102_8938_13bd_f6f1, + &pci_ss_info_1102_8938_14ff_0e70, + &pci_ss_info_1102_8938_14ff_c401, + &pci_ss_info_1102_8938_156d_b400, + &pci_ss_info_1102_8938_156d_b550, + &pci_ss_info_1102_8938_156d_b560, + &pci_ss_info_1102_8938_156d_b700, + &pci_ss_info_1102_8938_156d_b795, + &pci_ss_info_1102_8938_156d_b797, + NULL +}; +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0003, + &pci_ss_info_1103_0004_1103_0004, + &pci_ss_info_1103_0004_1103_0005, + &pci_ss_info_1103_0004_1103_0006, + &pci_ss_info_1103_0004_1103_0007, + &pci_ss_info_1103_0004_1103_0008, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#define pci_ss_list_1103_0009 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1105_8401 NULL +#define pci_ss_list_1105_8470 NULL +#define pci_ss_list_1105_8471 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105_8475[] = { + &pci_ss_info_1105_8475_1105_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1105_8476[] = { + &pci_ss_info_1105_8476_127d_0000, + NULL +}; +#define pci_ss_list_1105_8485 NULL +#define pci_ss_list_1105_8486 NULL +#endif +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +#define pci_ss_list_1106_0204 NULL +#define pci_ss_list_1106_0238 NULL +#define pci_ss_list_1106_0259 NULL +#define pci_ss_list_1106_0269 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106_0282[] = { + &pci_ss_info_1106_0282_1043_80a3, + NULL +}; +#define pci_ss_list_1106_0290 NULL +#define pci_ss_list_1106_0296 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1019_0987, + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0308 NULL +#define pci_ss_list_1106_0314 NULL +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1019_0985, + &pci_ss_info_1106_0571_1019_0a81, + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1043_808c, + &pci_ss_info_1106_0571_1043_80a1, + &pci_ss_info_1106_0571_1043_80ed, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1297_f641, + &pci_ss_info_1106_0571_1458_5002, + &pci_ss_info_1106_0571_1462_7020, + &pci_ss_info_1106_0571_147b_1407, + &pci_ss_info_1106_0571_1849_0571, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0591 NULL +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0605[] = { + &pci_ss_info_1106_0605_1043_802c, + NULL +}; +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1019_0985, + &pci_ss_info_1106_0686_1043_802c, + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1019_0985, + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1204 NULL +#define pci_ss_list_1106_1208 NULL +#define pci_ss_list_1106_1238 NULL +#define pci_ss_list_1106_1258 NULL +#define pci_ss_list_1106_1259 NULL +#define pci_ss_list_1106_1269 NULL +#define pci_ss_list_1106_1282 NULL +#define pci_ss_list_1106_1290 NULL +#define pci_ss_list_1106_1296 NULL +#define pci_ss_list_1106_1308 NULL +#define pci_ss_list_1106_1314 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +#define pci_ss_list_1106_2204 NULL +#define pci_ss_list_1106_2208 NULL +#define pci_ss_list_1106_2238 NULL +#define pci_ss_list_1106_2258 NULL +#define pci_ss_list_1106_2259 NULL +#define pci_ss_list_1106_2269 NULL +#define pci_ss_list_1106_2282 NULL +#define pci_ss_list_1106_2290 NULL +#define pci_ss_list_1106_2296 NULL +#define pci_ss_list_1106_2308 NULL +#define pci_ss_list_1106_2314 NULL +#define pci_ss_list_1106_287a NULL +#define pci_ss_list_1106_287b NULL +#define pci_ss_list_1106_287c NULL +#define pci_ss_list_1106_287d NULL +#define pci_ss_list_1106_287e NULL +#define pci_ss_list_1106_3022 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1019_0985, + &pci_ss_info_1106_3038_1019_0a81, + &pci_ss_info_1106_3038_1043_8080, + &pci_ss_info_1106_3038_1043_808c, + &pci_ss_info_1106_3038_1043_80a1, + &pci_ss_info_1106_3038_1043_80ed, + &pci_ss_info_1106_3038_1179_0001, + &pci_ss_info_1106_3038_1458_5004, + &pci_ss_info_1106_3038_1462_7020, + &pci_ss_info_1106_3038_147b_1407, + &pci_ss_info_1106_3038_182d_201d, + &pci_ss_info_1106_3038_1849_3038, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3044[] = { + &pci_ss_info_1106_3044_0574_086c, + &pci_ss_info_1106_3044_1025_005a, + &pci_ss_info_1106_3044_1043_808a, + &pci_ss_info_1106_3044_1458_1000, + &pci_ss_info_1106_3044_1462_702d, + &pci_ss_info_1106_3044_1462_971d, + NULL +}; +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +#define pci_ss_list_1106_3053 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1019_0985, + &pci_ss_info_1106_3057_1019_0987, + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_0097, + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1019_0985, + &pci_ss_info_1106_3058_1019_0987, + &pci_ss_info_1106_3058_1043_1106, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_1462_3300, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1019_0a81, + &pci_ss_info_1106_3059_1043_8095, + &pci_ss_info_1106_3059_1043_80a1, + &pci_ss_info_1106_3059_1043_80b0, + &pci_ss_info_1106_3059_1043_812a, + &pci_ss_info_1106_3059_1106_3059, + &pci_ss_info_1106_3059_1106_4161, + &pci_ss_info_1106_3059_1297_c160, + &pci_ss_info_1106_3059_1458_a002, + &pci_ss_info_1106_3059_1462_0080, + &pci_ss_info_1106_3059_1462_3800, + &pci_ss_info_1106_3059_147b_1407, + &pci_ss_info_1106_3059_1849_9761, + &pci_ss_info_1106_3059_4005_4710, + &pci_ss_info_1106_3059_a0a0_01b6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1043_80a1, + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + &pci_ss_info_1106_3065_13b9_1421, + &pci_ss_info_1106_3065_1695_3005, + &pci_ss_info_1106_3065_1695_300c, + &pci_ss_info_1106_3065_1849_3065, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3068[] = { + &pci_ss_info_1106_3068_1462_309e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + &pci_ss_info_1106_3099_1849_3099, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1019_0a81, + &pci_ss_info_1106_3104_1043_808c, + &pci_ss_info_1106_3104_1043_80a1, + &pci_ss_info_1106_3104_1043_80ed, + &pci_ss_info_1106_3104_1297_f641, + &pci_ss_info_1106_3104_1458_5004, + &pci_ss_info_1106_3104_1462_7020, + &pci_ss_info_1106_3104_147b_1407, + &pci_ss_info_1106_3104_182d_201d, + &pci_ss_info_1106_3104_1849_3104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3106[] = { + &pci_ss_info_1106_3106_1186_1403, + NULL +}; +#define pci_ss_list_1106_3108 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3113 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3116[] = { + &pci_ss_info_1106_3116_1297_f641, + NULL +}; +#define pci_ss_list_1106_3118 NULL +#define pci_ss_list_1106_3119 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3147[] = { + &pci_ss_info_1106_3147_1043_808c, + NULL +}; +#define pci_ss_list_1106_3148 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3149[] = { + &pci_ss_info_1106_3149_1043_80ed, + &pci_ss_info_1106_3149_1458_b003, + &pci_ss_info_1106_3149_1462_7020, + &pci_ss_info_1106_3149_147b_1407, + &pci_ss_info_1106_3149_147b_1408, + &pci_ss_info_1106_3149_1849_3149, + NULL +}; +#define pci_ss_list_1106_3156 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3164[] = { + &pci_ss_info_1106_3164_1462_7028, + NULL +}; +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1019_0a81, + &pci_ss_info_1106_3177_1043_808c, + &pci_ss_info_1106_3177_1043_80a1, + &pci_ss_info_1106_3177_1297_f641, + &pci_ss_info_1106_3177_1458_5001, + &pci_ss_info_1106_3177_1849_3177, + NULL +}; +#define pci_ss_list_1106_3178 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3188[] = { + &pci_ss_info_1106_3188_1043_80a3, + &pci_ss_info_1106_3188_147b_1407, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1043_807f, + &pci_ss_info_1106_3189_1458_5000, + &pci_ss_info_1106_3189_1849_3189, + NULL +}; +#define pci_ss_list_1106_3204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3205[] = { + &pci_ss_info_1106_3205_1458_5000, + NULL +}; +#define pci_ss_list_1106_3208 NULL +#define pci_ss_list_1106_3213 NULL +#define pci_ss_list_1106_3218 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3227[] = { + &pci_ss_info_1106_3227_1043_80ed, + &pci_ss_info_1106_3227_1106_3227, + &pci_ss_info_1106_3227_1458_5001, + &pci_ss_info_1106_3227_147b_1407, + &pci_ss_info_1106_3227_1849_3227, + NULL +}; +#define pci_ss_list_1106_3238 NULL +#define pci_ss_list_1106_3249 NULL +#define pci_ss_list_1106_3258 NULL +#define pci_ss_list_1106_3259 NULL +#define pci_ss_list_1106_3269 NULL +#define pci_ss_list_1106_3282 NULL +#define pci_ss_list_1106_3288 NULL +#define pci_ss_list_1106_3290 NULL +#define pci_ss_list_1106_3296 NULL +#define pci_ss_list_1106_3337 NULL +#define pci_ss_list_1106_3349 NULL +#define pci_ss_list_1106_337a NULL +#define pci_ss_list_1106_337b NULL +#define pci_ss_list_1106_4149 NULL +#define pci_ss_list_1106_4204 NULL +#define pci_ss_list_1106_4208 NULL +#define pci_ss_list_1106_4238 NULL +#define pci_ss_list_1106_4258 NULL +#define pci_ss_list_1106_4259 NULL +#define pci_ss_list_1106_4269 NULL +#define pci_ss_list_1106_4282 NULL +#define pci_ss_list_1106_4290 NULL +#define pci_ss_list_1106_4296 NULL +#define pci_ss_list_1106_4308 NULL +#define pci_ss_list_1106_4314 NULL +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_5208 NULL +#define pci_ss_list_1106_5238 NULL +#define pci_ss_list_1106_5290 NULL +#define pci_ss_list_1106_5308 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_7204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_7205[] = { + &pci_ss_info_1106_7205_1458_d000, + NULL +}; +#define pci_ss_list_1106_7208 NULL +#define pci_ss_list_1106_7238 NULL +#define pci_ss_list_1106_7258 NULL +#define pci_ss_list_1106_7259 NULL +#define pci_ss_list_1106_7269 NULL +#define pci_ss_list_1106_7282 NULL +#define pci_ss_list_1106_7290 NULL +#define pci_ss_list_1106_7296 NULL +#define pci_ss_list_1106_7308 NULL +#define pci_ss_list_1106_7314 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +static const pciSubsystemInfo *pci_ss_list_1106_8598[] = { + &pci_ss_info_1106_8598_1019_0985, + NULL +}; +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_a208 NULL +#define pci_ss_list_1106_a238 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b113 NULL +#define pci_ss_list_1106_b115 NULL +#define pci_ss_list_1106_b168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_b188[] = { + &pci_ss_info_1106_b188_147b_1407, + NULL +}; +#define pci_ss_list_1106_b198 NULL +#define pci_ss_list_1106_b213 NULL +#define pci_ss_list_1106_c208 NULL +#define pci_ss_list_1106_c238 NULL +#define pci_ss_list_1106_d104 NULL +#define pci_ss_list_1106_d208 NULL +#define pci_ss_list_1106_d213 NULL +#define pci_ss_list_1106_d238 NULL +#define pci_ss_list_1106_e208 NULL +#define pci_ss_list_1106_e238 NULL +#define pci_ss_list_1106_f208 NULL +#define pci_ss_list_1106_f238 NULL +#endif +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_0006 NULL +#define pci_ss_list_110a_0015 NULL +#define pci_ss_list_110a_001d NULL +#define pci_ss_list_110a_007b NULL +#define pci_ss_list_110a_007c NULL +#define pci_ss_list_110a_007d NULL +#define pci_ss_list_110a_2101 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_2104 NULL +#define pci_ss_list_110a_3142 NULL +#define pci_ss_list_110a_4021 NULL +#define pci_ss_list_110a_4029 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_1113_2242, + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#define pci_ss_list_1113_d301 NULL +#define pci_ss_list_1113_ec02 NULL +#endif +#define pci_ss_list_1114_0506 NULL +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0010 NULL +#define pci_ss_list_1119_0011 NULL +#define pci_ss_list_1119_0012 NULL +#define pci_ss_list_1119_0013 NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_02ff NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#define pci_ss_list_111a_1203 NULL +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111d_0004 NULL +#define pci_ss_list_111d_0005 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_112f_0008 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_5400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_5402[] = { + &pci_ss_info_1131_5402_1244_0f00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7130[] = { + &pci_ss_info_1131_7130_102b_48d0, + &pci_ss_info_1131_7130_1048_226b, + &pci_ss_info_1131_7130_1131_2001, + &pci_ss_info_1131_7130_1131_2005, + &pci_ss_info_1131_7130_1461_050c, + &pci_ss_info_1131_7130_1461_10ff, + &pci_ss_info_1131_7130_1461_2108, + &pci_ss_info_1131_7130_1461_2115, + &pci_ss_info_1131_7130_153b_1152, + &pci_ss_info_1131_7130_185b_c100, + &pci_ss_info_1131_7130_5168_0138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7133[] = { + &pci_ss_info_1131_7133_002b_11bd, + &pci_ss_info_1131_7133_1019_4cb5, + &pci_ss_info_1131_7133_1043_0210, + &pci_ss_info_1131_7133_1043_4843, + &pci_ss_info_1131_7133_1131_2001, + &pci_ss_info_1131_7133_1461_f31f, + &pci_ss_info_1131_7133_1489_0214, + &pci_ss_info_1131_7133_153b_1162, + &pci_ss_info_1131_7133_185b_c100, + &pci_ss_info_1131_7133_5168_0138, + &pci_ss_info_1131_7133_5168_0212, + &pci_ss_info_1131_7133_5168_0214, + &pci_ss_info_1131_7133_5168_0306, + &pci_ss_info_1131_7133_5168_0502, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7134[] = { + &pci_ss_info_1131_7134_1019_4cb4, + &pci_ss_info_1131_7134_1043_4840, + &pci_ss_info_1131_7134_1043_4842, + &pci_ss_info_1131_7134_1131_4e85, + &pci_ss_info_1131_7134_1131_6752, + &pci_ss_info_1131_7134_1131_7133, + &pci_ss_info_1131_7134_11bd_002b, + &pci_ss_info_1131_7134_11bd_002d, + &pci_ss_info_1131_7134_1461_2c00, + &pci_ss_info_1131_7134_1461_2c05, + &pci_ss_info_1131_7134_1461_a70a, + &pci_ss_info_1131_7134_1461_a70b, + &pci_ss_info_1131_7134_1461_d6ee, + &pci_ss_info_1131_7134_153b_1142, + &pci_ss_info_1131_7134_153b_1143, + &pci_ss_info_1131_7134_153b_1158, + &pci_ss_info_1131_7134_1540_9524, + &pci_ss_info_1131_7134_16be_0003, + &pci_ss_info_1131_7134_185b_c200, + &pci_ss_info_1131_7134_1894_a006, + &pci_ss_info_1131_7134_1894_fe01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7135[] = { + &pci_ss_info_1131_7135_1421_0350, + &pci_ss_info_1131_7135_1421_0370, + &pci_ss_info_1131_7135_5168_0212, + NULL +}; +#define pci_ss_list_1131_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_110a_0000, + &pci_ss_info_1131_7146_110a_ffff, + &pci_ss_info_1131_7146_1131_4f56, + &pci_ss_info_1131_7146_1131_4f60, + &pci_ss_info_1131_7146_1131_4f61, + &pci_ss_info_1131_7146_1131_5f61, + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + &pci_ss_info_1131_7146_11bd_000f, + &pci_ss_info_1131_7146_13c2_0000, + &pci_ss_info_1131_7146_13c2_0001, + &pci_ss_info_1131_7146_13c2_0002, + &pci_ss_info_1131_7146_13c2_0003, + &pci_ss_info_1131_7146_13c2_0004, + &pci_ss_info_1131_7146_13c2_0006, + &pci_ss_info_1131_7146_13c2_0008, + &pci_ss_info_1131_7146_13c2_000a, + &pci_ss_info_1131_7146_13c2_1003, + &pci_ss_info_1131_7146_13c2_1004, + &pci_ss_info_1131_7146_13c2_1005, + &pci_ss_info_1131_7146_13c2_100c, + &pci_ss_info_1131_7146_13c2_100f, + &pci_ss_info_1131_7146_13c2_1011, + &pci_ss_info_1131_7146_13c2_1013, + &pci_ss_info_1131_7146_13c2_1102, + NULL +}; +#define pci_ss_list_1131_9730 NULL +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#define pci_ss_list_1133_e001 NULL +#define pci_ss_list_1133_e002 NULL +#define pci_ss_list_1133_e003 NULL +#define pci_ss_list_1133_e004 NULL +#define pci_ss_list_1133_e005 NULL +#define pci_ss_list_1133_e006 NULL +#define pci_ss_list_1133_e007 NULL +#define pci_ss_list_1133_e008 NULL +#define pci_ss_list_1133_e009 NULL +#define pci_ss_list_1133_e00a NULL +#define pci_ss_list_1133_e00b NULL +#define pci_ss_list_1133_e00c NULL +#define pci_ss_list_1133_e00d NULL +#define pci_ss_list_1133_e00e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_110a_0021, + NULL +}; +#define pci_ss_list_1133_e011 NULL +#define pci_ss_list_1133_e012 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e013[] = { + &pci_ss_info_1133_e013_1133_1300, + &pci_ss_info_1133_e013_1133_e013, + NULL +}; +#define pci_ss_list_1133_e014 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e015[] = { + &pci_ss_info_1133_e015_1133_e015, + NULL +}; +#define pci_ss_list_1133_e016 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e017[] = { + &pci_ss_info_1133_e017_1133_e017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e018[] = { + &pci_ss_info_1133_e018_1133_1800, + &pci_ss_info_1133_e018_1133_e018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e019[] = { + &pci_ss_info_1133_e019_1133_e019, + NULL +}; +#define pci_ss_list_1133_e01a NULL +static const pciSubsystemInfo *pci_ss_list_1133_e01b[] = { + &pci_ss_info_1133_e01b_1133_e01b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e01c[] = { + &pci_ss_info_1133_e01c_1133_1c01, + &pci_ss_info_1133_e01c_1133_1c02, + &pci_ss_info_1133_e01c_1133_1c03, + &pci_ss_info_1133_e01c_1133_1c04, + &pci_ss_info_1133_e01c_1133_1c05, + &pci_ss_info_1133_e01c_1133_1c06, + &pci_ss_info_1133_e01c_1133_1c07, + &pci_ss_info_1133_e01c_1133_1c08, + &pci_ss_info_1133_e01c_1133_1c09, + &pci_ss_info_1133_e01c_1133_1c0a, + &pci_ss_info_1133_e01c_1133_1c0b, + &pci_ss_info_1133_e01c_1133_1c0c, + NULL +}; +#define pci_ss_list_1133_e01e NULL +#define pci_ss_list_1133_e020 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e024[] = { + &pci_ss_info_1133_e024_1133_2400, + &pci_ss_info_1133_e024_1133_e024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e028[] = { + &pci_ss_info_1133_e028_1133_2800, + &pci_ss_info_1133_e028_1133_e028, + NULL +}; +#define pci_ss_list_1133_e02a NULL +#define pci_ss_list_1133_e02c NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1134_0002 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#define pci_ss_list_1145_f020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2971, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2973, + &pci_ss_info_1148_4300_1259_2974, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2976, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_0121, + &pci_ss_info_1148_4320_1148_0221, + &pci_ss_info_1148_4320_1148_0321, + &pci_ss_info_1148_4320_1148_0421, + &pci_ss_info_1148_4320_1148_0621, + &pci_ss_info_1148_4320_1148_0721, + &pci_ss_info_1148_4320_1148_0821, + &pci_ss_info_1148_4320_1148_0921, + &pci_ss_info_1148_4320_1148_1121, + &pci_ss_info_1148_4320_1148_1221, + &pci_ss_info_1148_4320_1148_3221, + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#define pci_ss_list_1148_4500 NULL +#define pci_ss_list_1148_9000 NULL +#define pci_ss_list_1148_9843 NULL +static const pciSubsystemInfo *pci_ss_list_1148_9e00[] = { + &pci_ss_info_1148_9e00_1148_2100, + &pci_ss_info_1148_9e00_1148_21d0, + &pci_ss_info_1148_9e00_1148_2200, + &pci_ss_info_1148_9e00_1148_8100, + &pci_ss_info_1148_9e00_1148_8200, + &pci_ss_info_1148_9e00_1148_9100, + &pci_ss_info_1148_9e00_1148_9200, + NULL +}; +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0013 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0028 NULL +#define pci_ss_list_114f_0029 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0043 NULL +#define pci_ss_list_114f_0044 NULL +#define pci_ss_list_114f_0045 NULL +#define pci_ss_list_114f_004e NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_00b0 NULL +#define pci_ss_list_114f_00b1 NULL +#define pci_ss_list_114f_00c8 NULL +#define pci_ss_list_114f_00c9 NULL +#define pci_ss_list_114f_00ca NULL +#define pci_ss_list_114f_00cb NULL +#define pci_ss_list_114f_00d0 NULL +#define pci_ss_list_114f_00d1 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_0182, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +#define pci_ss_list_115d_00d4 NULL +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0000 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0006 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0036 NULL +#define pci_ss_list_1166_0101 NULL +#define pci_ss_list_1166_0104 NULL +#define pci_ss_list_1166_0110 NULL +#define pci_ss_list_1166_0130 NULL +#define pci_ss_list_1166_0132 NULL +#define pci_ss_list_1166_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166_0201[] = { + &pci_ss_info_1166_0201_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0203[] = { + &pci_ss_info_1166_0203_1734_1012, + NULL +}; +#define pci_ss_list_1166_0205 NULL +#define pci_ss_list_1166_0211 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0212[] = { + &pci_ss_info_1166_0212_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0213[] = { + &pci_ss_info_1166_0213_1028_c134, + &pci_ss_info_1166_0213_1734_1012, + NULL +}; +#define pci_ss_list_1166_0214 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0217[] = { + &pci_ss_info_1166_0217_1028_4134, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0220[] = { + &pci_ss_info_1166_0220_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0221[] = { + &pci_ss_info_1166_0221_1734_1012, + NULL +}; +#define pci_ss_list_1166_0223 NULL +#define pci_ss_list_1166_0225 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0227[] = { + &pci_ss_info_1166_0227_1734_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0230[] = { + &pci_ss_info_1166_0230_4c53_1080, + NULL +}; +#define pci_ss_list_1166_0234 NULL +#define pci_ss_list_1166_0240 NULL +#define pci_ss_list_1166_0241 NULL +#define pci_ss_list_1166_0242 NULL +#define pci_ss_list_1166_024a NULL +#endif +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0102 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0601[] = { + &pci_ss_info_1179_0601_1179_0001, + NULL +}; +#define pci_ss_list_1179_0603 NULL +static const pciSubsystemInfo *pci_ss_list_1179_060a[] = { + &pci_ss_info_1179_060a_1179_0001, + NULL +}; +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c_0030[] = { + &pci_ss_info_117c_0030_117c_8013, + &pci_ss_info_117c_0030_117c_8014, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_1028_0188, + &pci_ss_info_1180_0476_1043_1967, + &pci_ss_info_1180_0476_1043_1987, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + &pci_ss_info_1180_0476_14ef_0220, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +#define pci_ss_list_1180_0511 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + &pci_ss_info_1180_0522_1043_1967, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + NULL +}; +#define pci_ss_list_1180_0554 NULL +#define pci_ss_list_1180_0575 NULL +#define pci_ss_list_1180_0576 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0592[] = { + &pci_ss_info_1180_0592_1043_1967, + NULL +}; +#define pci_ss_list_1180_0811 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0822[] = { + &pci_ss_info_1180_0822_1014_0556, + &pci_ss_info_1180_0822_1028_0188, + &pci_ss_info_1180_0822_1028_01a2, + &pci_ss_info_1180_0822_1043_1967, + NULL +}; +#define pci_ss_list_1180_0841 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0852[] = { + &pci_ss_info_1180_0852_1043_1967, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +#define pci_ss_list_1186_1025 NULL +#define pci_ss_list_1186_1026 NULL +#define pci_ss_list_1186_1043 NULL +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + &pci_ss_info_1186_1300_1186_1303, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1541 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_2027 NULL +#define pci_ss_list_1186_3203 NULL +#define pci_ss_list_1186_3300 NULL +#define pci_ss_list_1186_3a03 NULL +#define pci_ss_list_1186_3a04 NULL +#define pci_ss_list_1186_3a05 NULL +#define pci_ss_list_1186_3a07 NULL +#define pci_ss_list_1186_3a08 NULL +#define pci_ss_list_1186_3a10 NULL +#define pci_ss_list_1186_3a11 NULL +#define pci_ss_list_1186_3a12 NULL +#define pci_ss_list_1186_3a13 NULL +#define pci_ss_list_1186_3a14 NULL +#define pci_ss_list_1186_3a63 NULL +#define pci_ss_list_1186_4000 NULL +#define pci_ss_list_1186_4300 NULL +static const pciSubsystemInfo *pci_ss_list_1186_4c00[] = { + &pci_ss_info_1186_4c00_1186_4c00, + NULL +}; +#define pci_ss_list_1186_8400 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1191_8060 NULL +#define pci_ss_list_1191_8080 NULL +#define pci_ss_list_1191_8081 NULL +#define pci_ss_list_1191_808a NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_1197_010c NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_138f NULL +#define pci_ss_list_11ab_1fa6 NULL +#define pci_ss_list_11ab_1fa7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab_1faa[] = { + &pci_ss_info_11ab_1faa_1385_4e00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4320[] = { + &pci_ss_info_11ab_4320_1019_0f38, + &pci_ss_info_11ab_4320_1019_8001, + &pci_ss_info_11ab_4320_1043_173c, + &pci_ss_info_11ab_4320_1043_811a, + &pci_ss_info_11ab_4320_105b_0c19, + &pci_ss_info_11ab_4320_10b8_b452, + &pci_ss_info_11ab_4320_11ab_0121, + &pci_ss_info_11ab_4320_11ab_0321, + &pci_ss_info_11ab_4320_11ab_1021, + &pci_ss_info_11ab_4320_11ab_5021, + &pci_ss_info_11ab_4320_11ab_9521, + &pci_ss_info_11ab_4320_1458_e000, + &pci_ss_info_11ab_4320_147b_1406, + &pci_ss_info_11ab_4320_15d4_0047, + &pci_ss_info_11ab_4320_1695_9025, + &pci_ss_info_11ab_4320_17f2_1c03, + &pci_ss_info_11ab_4320_270f_2803, + NULL +}; +#define pci_ss_list_11ab_4340 NULL +#define pci_ss_list_11ab_4341 NULL +#define pci_ss_list_11ab_4342 NULL +#define pci_ss_list_11ab_4343 NULL +#define pci_ss_list_11ab_4344 NULL +#define pci_ss_list_11ab_4345 NULL +#define pci_ss_list_11ab_4346 NULL +#define pci_ss_list_11ab_4347 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4350[] = { + &pci_ss_info_11ab_4350_1179_0001, + &pci_ss_info_11ab_4350_11ab_3521, + &pci_ss_info_11ab_4350_1854_000d, + &pci_ss_info_11ab_4350_1854_000e, + &pci_ss_info_11ab_4350_1854_000f, + &pci_ss_info_11ab_4350_1854_0011, + &pci_ss_info_11ab_4350_1854_0012, + &pci_ss_info_11ab_4350_1854_0016, + &pci_ss_info_11ab_4350_1854_0017, + &pci_ss_info_11ab_4350_1854_0018, + &pci_ss_info_11ab_4350_1854_0019, + &pci_ss_info_11ab_4350_1854_001c, + &pci_ss_info_11ab_4350_1854_001e, + &pci_ss_info_11ab_4350_1854_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4351[] = { + &pci_ss_info_11ab_4351_107b_4009, + &pci_ss_info_11ab_4351_10f7_8338, + &pci_ss_info_11ab_4351_1179_0001, + &pci_ss_info_11ab_4351_1179_ff00, + &pci_ss_info_11ab_4351_1179_ff10, + &pci_ss_info_11ab_4351_11ab_3621, + &pci_ss_info_11ab_4351_13d1_ac12, + &pci_ss_info_11ab_4351_161f_203d, + &pci_ss_info_11ab_4351_1854_000d, + &pci_ss_info_11ab_4351_1854_000e, + &pci_ss_info_11ab_4351_1854_000f, + &pci_ss_info_11ab_4351_1854_0011, + &pci_ss_info_11ab_4351_1854_0012, + &pci_ss_info_11ab_4351_1854_0016, + &pci_ss_info_11ab_4351_1854_0017, + &pci_ss_info_11ab_4351_1854_0018, + &pci_ss_info_11ab_4351_1854_0019, + &pci_ss_info_11ab_4351_1854_001c, + &pci_ss_info_11ab_4351_1854_001e, + &pci_ss_info_11ab_4351_1854_0020, + NULL +}; +#define pci_ss_list_11ab_4352 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4360[] = { + &pci_ss_info_11ab_4360_1043_8134, + &pci_ss_info_11ab_4360_107b_4009, + &pci_ss_info_11ab_4360_11ab_5221, + &pci_ss_info_11ab_4360_1458_e000, + &pci_ss_info_11ab_4360_1462_052c, + &pci_ss_info_11ab_4360_1849_8052, + &pci_ss_info_11ab_4360_a0a0_0509, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4361[] = { + &pci_ss_info_11ab_4361_107b_3015, + &pci_ss_info_11ab_4361_11ab_5021, + &pci_ss_info_11ab_4361_8086_3063, + &pci_ss_info_11ab_4361_8086_3439, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4362[] = { + &pci_ss_info_11ab_4362_103c_2a0d, + &pci_ss_info_11ab_4362_1043_8142, + &pci_ss_info_11ab_4362_109f_3197, + &pci_ss_info_11ab_4362_10f7_8338, + &pci_ss_info_11ab_4362_10fd_a430, + &pci_ss_info_11ab_4362_1179_0001, + &pci_ss_info_11ab_4362_1179_ff00, + &pci_ss_info_11ab_4362_1179_ff10, + &pci_ss_info_11ab_4362_11ab_5321, + &pci_ss_info_11ab_4362_1297_c240, + &pci_ss_info_11ab_4362_1297_c241, + &pci_ss_info_11ab_4362_1297_c242, + &pci_ss_info_11ab_4362_1297_c243, + &pci_ss_info_11ab_4362_1297_c244, + &pci_ss_info_11ab_4362_13d1_ac11, + &pci_ss_info_11ab_4362_1458_e000, + &pci_ss_info_11ab_4362_1462_058c, + &pci_ss_info_11ab_4362_14c0_0012, + &pci_ss_info_11ab_4362_1558_04a0, + &pci_ss_info_11ab_4362_15bd_1003, + &pci_ss_info_11ab_4362_161f_203c, + &pci_ss_info_11ab_4362_161f_203d, + &pci_ss_info_11ab_4362_1695_9029, + &pci_ss_info_11ab_4362_17f2_2c08, + &pci_ss_info_11ab_4362_17ff_0585, + &pci_ss_info_11ab_4362_1849_8053, + &pci_ss_info_11ab_4362_1854_000b, + &pci_ss_info_11ab_4362_1854_000c, + &pci_ss_info_11ab_4362_1854_0010, + &pci_ss_info_11ab_4362_1854_0013, + &pci_ss_info_11ab_4362_1854_0014, + &pci_ss_info_11ab_4362_1854_0015, + &pci_ss_info_11ab_4362_1854_001a, + &pci_ss_info_11ab_4362_1854_001b, + &pci_ss_info_11ab_4362_1854_001d, + &pci_ss_info_11ab_4362_1854_001f, + &pci_ss_info_11ab_4362_1854_0021, + &pci_ss_info_11ab_4362_1854_0022, + &pci_ss_info_11ab_4362_270f_2801, + &pci_ss_info_11ab_4362_a0a0_0506, + NULL +}; +#define pci_ss_list_11ab_4363 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_5005 NULL +#define pci_ss_list_11ab_5040 NULL +#define pci_ss_list_11ab_5041 NULL +#define pci_ss_list_11ab_5080 NULL +#define pci_ss_list_11ab_5081 NULL +#define pci_ss_list_11ab_6041 NULL +#define pci_ss_list_11ab_6081 NULL +#define pci_ss_list_11ab_6460 NULL +#define pci_ss_list_11ab_6480 NULL +#define pci_ss_list_11ab_f003 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11af_0001 NULL +#define pci_ss_list_11af_ee40 NULL +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#define pci_ss_list_11bd_bede NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0445[] = { + &pci_ss_info_11c1_0445_8086_2203, + &pci_ss_info_11c1_0445_8086_2204, + NULL +}; +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_1033_80a8, + &pci_ss_info_11c1_0450_144f_4005, + &pci_ss_info_11c1_0450_1468_0450, + &pci_ss_info_11c1_0450_4005_144f, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_048c NULL +#define pci_ss_list_11c1_048f NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_8086_524c, + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +#define pci_ss_list_11c1_8110 NULL +#define pci_ss_list_11c1_ab10 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab11[] = { + &pci_ss_info_11c1_ab11_11c1_ab12, + &pci_ss_info_11c1_ab11_11c1_ab13, + &pci_ss_info_11c1_ab11_11c1_ab15, + &pci_ss_info_11c1_ab11_11c1_ab16, + NULL +}; +#define pci_ss_list_11c1_ab20 NULL +#define pci_ss_list_11c1_ab21 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab30[] = { + &pci_ss_info_11c1_ab30_14cd_2012, + NULL +}; +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1535 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d4_5340 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_12f8_8a02, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + &pci_ss_info_11de_6120_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_11e3_0001 NULL +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_000d NULL +#define pci_ss_list_11fe_000e NULL +#define pci_ss_list_11fe_000f NULL +#define pci_ss_list_11fe_0801 NULL +#define pci_ss_list_11fe_0802 NULL +#define pci_ss_list_11fe_0803 NULL +#define pci_ss_list_11fe_0805 NULL +#define pci_ss_list_11fe_080c NULL +#define pci_ss_list_11fe_080d NULL +#define pci_ss_list_11fe_0812 NULL +#define pci_ss_list_11fe_0903 NULL +#define pci_ss_list_11fe_8015 NULL +#define pci_ss_list_11ff_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1014_020c, + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_7110[] = { + &pci_ss_info_1217_7110_103c_088c, + &pci_ss_info_1217_7110_103c_0890, + NULL +}; +#define pci_ss_list_1217_7112 NULL +#define pci_ss_list_1217_7113 NULL +#define pci_ss_list_1217_7114 NULL +#define pci_ss_list_1217_7134 NULL +#define pci_ss_list_1217_71e2 NULL +#define pci_ss_list_1217_7212 NULL +#define pci_ss_list_1217_7213 NULL +static const pciSubsystemInfo *pci_ss_list_1217_7223[] = { + &pci_ss_info_1217_7223_103c_088c, + &pci_ss_info_1217_7223_103c_0890, + NULL +}; +#define pci_ss_list_1217_7233 NULL +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0057, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0003, + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_1227_0006 NULL +#define pci_ss_list_1227_0023 NULL +#define pci_ss_list_122d_1206 NULL +#define pci_ss_list_122d_1400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + &pci_ss_info_123f_8120_11bd_000f, + &pci_ss_info_123f_8120_1809_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#define pci_ss_list_1242_6562 NULL +#define pci_ss_list_1242_656a NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#define pci_ss_list_1244_2700 NULL +#define pci_ss_list_1244_2900 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_1259_a117 NULL +#define pci_ss_list_1259_a120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125b_1400[] = { + &pci_ss_info_125b_1400_1186_1100, + NULL +}; +#endif +#define pci_ss_list_125c_0101 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + &pci_ss_info_125d_1969_153b_111b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_0e11_0098, + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00b1, + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3872[] = { + &pci_ss_info_1260_3872_1468_0202, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1186_3700, + &pci_ss_info_1260_3873_1385_4105, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_16a5_1601, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3886[] = { + &pci_ss_info_1260_3886_17cf_0037, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3890[] = { + &pci_ss_info_1260_3890_10b8_2802, + &pci_ss_info_1260_3890_10b8_2835, + &pci_ss_info_1260_3890_10b8_a835, + &pci_ss_info_1260_3890_1113_4203, + &pci_ss_info_1260_3890_1113_ee03, + &pci_ss_info_1260_3890_1113_ee08, + &pci_ss_info_1260_3890_1186_3202, + &pci_ss_info_1260_3890_1259_c104, + &pci_ss_info_1260_3890_1385_4800, + &pci_ss_info_1260_3890_16a5_1605, + &pci_ss_info_1260_3890_17cf_0014, + &pci_ss_info_1260_3890_17cf_0020, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +#define pci_ss_list_1260_ffff NULL +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126c_1211 NULL +#define pci_ss_list_126c_126c NULL +#define pci_ss_list_126f_0501 NULL +#define pci_ss_list_126f_0510 NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0730 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#define pci_ss_list_1274_1171 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1274_8001, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4541, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1274_8001, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1278_0710 NULL +#define pci_ss_list_1279_0060 NULL +#define pci_ss_list_1279_0061 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1005_127a, + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#define pci_ss_list_1283_8211 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283_8212[] = { + &pci_ss_info_1283_8212_1283_0001, + NULL +}; +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8872 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#endif +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12a3_8105 NULL +#define pci_ss_list_12ab_0000 NULL +#define pci_ss_list_12ab_0002 NULL +#define pci_ss_list_12ab_3000 NULL +#define pci_ss_list_12ab_fff3 NULL +#define pci_ss_list_12ab_ffff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_1014_0104, + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_10a9_8002, + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#define pci_ss_list_12ae_00fa NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c4_0001 NULL +#define pci_ss_list_12c4_0002 NULL +#define pci_ss_list_12c4_0003 NULL +#define pci_ss_list_12c4_0004 NULL +#define pci_ss_list_12c4_0005 NULL +#define pci_ss_list_12c4_0006 NULL +#define pci_ss_list_12c4_0007 NULL +#define pci_ss_list_12c4_0008 NULL +#define pci_ss_list_12c4_0009 NULL +#define pci_ss_list_12c4_000a NULL +#define pci_ss_list_12c4_000b NULL +#define pci_ss_list_12c4_000c NULL +#define pci_ss_list_12c4_000d NULL +#define pci_ss_list_12c4_0100 NULL +#define pci_ss_list_12c4_0201 NULL +#define pci_ss_list_12c4_0202 NULL +#define pci_ss_list_12c4_0300 NULL +#define pci_ss_list_12c4_0301 NULL +#define pci_ss_list_12c4_0302 NULL +#define pci_ss_list_12c4_0310 NULL +#define pci_ss_list_12c4_0311 NULL +#define pci_ss_list_12c4_0312 NULL +#define pci_ss_list_12c4_0320 NULL +#define pci_ss_list_12c4_0321 NULL +#define pci_ss_list_12c4_0322 NULL +#define pci_ss_list_12c4_0330 NULL +#define pci_ss_list_12c4_0331 NULL +#define pci_ss_list_12c4_0332 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12d4_0200 NULL +#define pci_ss_list_12d5_0003 NULL +#define pci_ss_list_12d5_1000 NULL +#define pci_ss_list_12d8_8150 NULL +#define pci_ss_list_12d9_0002 NULL +#define pci_ss_list_12d9_0004 NULL +#define pci_ss_list_12d9_0005 NULL +#define pci_ss_list_12de_0200 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_12fb_0001 NULL +#define pci_ss_list_12fb_00f5 NULL +#define pci_ss_list_12fb_02ad NULL +#define pci_ss_list_12fb_2adc NULL +#define pci_ss_list_12fb_3100 NULL +#define pci_ss_list_12fb_3500 NULL +#define pci_ss_list_12fb_4d4f NULL +#define pci_ss_list_12fb_8120 NULL +#define pci_ss_list_12fb_da62 NULL +#define pci_ss_list_12fb_db62 NULL +#define pci_ss_list_12fb_dc62 NULL +#define pci_ss_list_12fb_dd62 NULL +#define pci_ss_list_12fb_eddc NULL +#define pci_ss_list_12fb_fa01 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#define pci_ss_list_1307_004d NULL +#define pci_ss_list_1307_0052 NULL +#define pci_ss_list_1307_0054 NULL +#define pci_ss_list_1307_005e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#define pci_ss_list_1317_0985 NULL +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1317_2850 NULL +#define pci_ss_list_1317_5120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317_8201[] = { + &pci_ss_info_1317_8201_10b8_2635, + &pci_ss_info_1317_8201_1317_8201, + NULL +}; +#define pci_ss_list_1317_8211 NULL +#define pci_ss_list_1317_9511 NULL +#endif +#define pci_ss_list_1318_0911 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319_0801[] = { + &pci_ss_info_1319_0801_1319_1319, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1319_0802[] = { + &pci_ss_info_1319_0802_1319_1319, + NULL +}; +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#endif +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#define pci_ss_list_131f_2081 NULL +#endif +#define pci_ss_list_1331_0030 NULL +#define pci_ss_list_1331_8200 NULL +#define pci_ss_list_1331_8201 NULL +#define pci_ss_list_1331_8202 NULL +#define pci_ss_list_1331_8210 NULL +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_1332_5425 NULL +#define pci_ss_list_1332_6140 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_2189 NULL +#define pci_ss_list_134d_2486 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7890[] = { + &pci_ss_info_134d_7890_134d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_5101 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1360_0101 NULL +#define pci_ss_list_1360_0102 NULL +#define pci_ss_list_1360_0103 NULL +#define pci_ss_list_1360_0201 NULL +#define pci_ss_list_1360_0202 NULL +#define pci_ss_list_1360_0203 NULL +#define pci_ss_list_1360_0301 NULL +#define pci_ss_list_1360_0302 NULL +#define pci_ss_list_136b_ff01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371_434e[] = { + &pci_ss_info_1371_434e_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1374_0024 NULL +#define pci_ss_list_1374_0025 NULL +#define pci_ss_list_1374_0026 NULL +#define pci_ss_list_1374_0027 NULL +#define pci_ss_list_1374_0029 NULL +#define pci_ss_list_1374_002a NULL +#define pci_ss_list_1374_002b NULL +#define pci_ss_list_1374_002c NULL +#define pci_ss_list_1374_002d NULL +#define pci_ss_list_1374_002e NULL +#define pci_ss_list_1374_002f NULL +#define pci_ss_list_1374_0030 NULL +#define pci_ss_list_1374_0031 NULL +#define pci_ss_list_1374_0032 NULL +#define pci_ss_list_1374_0034 NULL +#define pci_ss_list_1374_0035 NULL +#define pci_ss_list_1374_0036 NULL +#define pci_ss_list_1374_0037 NULL +#define pci_ss_list_1374_0038 NULL +#define pci_ss_list_1374_0039 NULL +#define pci_ss_list_1374_003a NULL +#define pci_ss_list_137a_0001 NULL +#define pci_ss_list_1382_0001 NULL +#define pci_ss_list_1382_2008 NULL +#define pci_ss_list_1382_2088 NULL +#define pci_ss_list_1382_20c8 NULL +#define pci_ss_list_1382_4008 NULL +#define pci_ss_list_1382_4010 NULL +#define pci_ss_list_1382_4048 NULL +#define pci_ss_list_1382_4088 NULL +#define pci_ss_list_1382_4248 NULL +#define pci_ss_list_1385_0013 NULL +#define pci_ss_list_1385_311a NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_4105 NULL +#define pci_ss_list_1385_4400 NULL +#define pci_ss_list_1385_4600 NULL +#define pci_ss_list_1385_4601 NULL +#define pci_ss_list_1385_4610 NULL +#define pci_ss_list_1385_4800 NULL +#define pci_ss_list_1385_4900 NULL +#define pci_ss_list_1385_4a00 NULL +#define pci_ss_list_1385_4b00 NULL +#define pci_ss_list_1385_4c00 NULL +#define pci_ss_list_1385_4e00 NULL +#define pci_ss_list_1385_4f00 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_6b00 NULL +#define pci_ss_list_1385_f004 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1141 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#define pci_ss_list_1397_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_0675_1704, + &pci_ss_info_1397_2bd0_0675_1708, + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a3_001d NULL +#define pci_ss_list_13a3_0020 NULL +#define pci_ss_list_13a3_0026 NULL +#define pci_ss_list_13a8_0152 NULL +#define pci_ss_list_13a8_0154 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c0_0020 NULL +#define pci_ss_list_13c0_0030 NULL +#define pci_ss_list_13c0_0210 NULL +#define pci_ss_list_13c1_1000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1_1001[] = { + &pci_ss_info_13c1_1001_13c1_1001, + NULL +}; +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13c1_1003 NULL +#endif +#define pci_ss_list_13c6_0520 NULL +#define pci_ss_list_13c6_0620 NULL +#define pci_ss_list_13c6_0820 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d0_2200 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab03 NULL +#define pci_ss_list_13d1_ab06 NULL +#define pci_ss_list_13d1_ab08 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13f0_0200 NULL +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f0_1023 NULL +#define pci_ss_list_13f4_1401 NULL +#define pci_ss_list_13f6_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8035, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + &pci_ss_info_13f6_0111_1681_a000, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1240 NULL +#define pci_ss_list_13fe_1600 NULL +#define pci_ss_list_13fe_1733 NULL +#define pci_ss_list_13fe_1752 NULL +#define pci_ss_list_13fe_1754 NULL +#define pci_ss_list_13fe_1756 NULL +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0110 NULL +#define pci_ss_list_1407_0111 NULL +#define pci_ss_list_1407_0120 NULL +#define pci_ss_list_1407_0121 NULL +#define pci_ss_list_1407_0180 NULL +#define pci_ss_list_1407_0181 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0220 NULL +#define pci_ss_list_1407_0221 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412_1712[] = { + &pci_ss_info_1412_1712_1412_1712, + &pci_ss_info_1412_1712_1412_d630, + &pci_ss_info_1412_1712_1412_d631, + &pci_ss_info_1412_1712_1412_d632, + &pci_ss_info_1412_1712_1412_d633, + &pci_ss_info_1412_1712_1412_d634, + &pci_ss_info_1412_1712_1412_d635, + &pci_ss_info_1412_1712_1412_d637, + &pci_ss_info_1412_1712_1412_d638, + &pci_ss_info_1412_1712_1412_d63b, + &pci_ss_info_1412_1712_1412_d63c, + &pci_ss_info_1412_1712_1416_1712, + &pci_ss_info_1412_1712_153b_1115, + &pci_ss_info_1412_1712_153b_1125, + &pci_ss_info_1412_1712_153b_112b, + &pci_ss_info_1412_1712_153b_112c, + &pci_ss_info_1412_1712_153b_1130, + &pci_ss_info_1412_1712_153b_1138, + &pci_ss_info_1412_1712_153b_1151, + &pci_ss_info_1412_1712_16ce_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1412_1724[] = { + &pci_ss_info_1412_1724_1412_1724, + &pci_ss_info_1412_1724_1412_3630, + &pci_ss_info_1412_1724_1412_3631, + &pci_ss_info_1412_1724_153b_1145, + &pci_ss_info_1412_1724_153b_1147, + &pci_ss_info_1412_1724_153b_1153, + &pci_ss_info_1412_1724_270f_f641, + &pci_ss_info_1412_1724_270f_f645, + NULL +}; +#endif +#define pci_ss_list_1415_8403 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_131f_2050, + &pci_ss_info_1415_9501_131f_2051, + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +#define pci_ss_list_1415_9510 NULL +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9521 NULL +#define pci_ss_list_1415_9523 NULL +#endif +#define pci_ss_list_1420_8002 NULL +#define pci_ss_list_1420_8003 NULL +#define pci_ss_list_1425_000b NULL +#define pci_ss_list_142e_4020 NULL +#define pci_ss_list_142e_4337 NULL +#define pci_ss_list_1432_9130 NULL +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8164 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_1458_0c11 NULL +#define pci_ss_list_1458_e911 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_1461_a3ce NULL +#define pci_ss_list_1461_a3cf NULL +#define pci_ss_list_1462_5501 NULL +#define pci_ss_list_1462_6819 NULL +#define pci_ss_list_1462_6825 NULL +#define pci_ss_list_1462_8725 NULL +#define pci_ss_list_1462_9000 NULL +#define pci_ss_list_1462_9110 NULL +#define pci_ss_list_1462_9119 NULL +#define pci_ss_list_1462_9591 NULL +#define pci_ss_list_146c_1430 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_1497_1497 NULL +#define pci_ss_list_1498_21cd NULL +#define pci_ss_list_1498_30c8 NULL +#define pci_ss_list_149d_0001 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14b9_a505 NULL +#define pci_ss_list_14b9_a506 NULL +#define pci_ss_list_14c1_8043 NULL +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14d9_0010 NULL +#define pci_ss_list_14d9_9000 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#define pci_ss_list_14e4_0800 NULL +#define pci_ss_list_14e4_0804 NULL +#define pci_ss_list_14e4_0805 NULL +#define pci_ss_list_14e4_0806 NULL +#define pci_ss_list_14e4_080b NULL +#define pci_ss_list_14e4_080f NULL +#define pci_ss_list_14e4_0811 NULL +#define pci_ss_list_14e4_0816 NULL +#define pci_ss_list_14e4_1600 NULL +#define pci_ss_list_14e4_1601 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_103c_128a, + &pci_ss_info_14e4_1645_103c_128b, + &pci_ss_info_14e4_1645_103c_12a4, + &pci_ss_info_14e4_1645_103c_12c1, + &pci_ss_info_14e4_1645_103c_1300, + &pci_ss_info_14e4_1645_10a9_8010, + &pci_ss_info_14e4_1645_10a9_8011, + &pci_ss_info_14e4_1645_10a9_8012, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_10a9_8010, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + &pci_ss_info_14e4_1648_1734_100b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164a[] = { + &pci_ss_info_14e4_164a_103c_3101, + NULL +}; +#define pci_ss_list_14e4_164c NULL +#define pci_ss_list_14e4_164d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1653[] = { + &pci_ss_info_14e4_1653_0e11_00e3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1654[] = { + &pci_ss_info_14e4_1654_0e11_00e3, + &pci_ss_info_14e4_1654_103c_3100, + &pci_ss_info_14e4_1654_103c_3226, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1659[] = { + &pci_ss_info_14e4_1659_103c_7031, + &pci_ss_info_14e4_1659_103c_7032, + &pci_ss_info_14e4_1659_1734_1061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165d[] = { + &pci_ss_info_14e4_165d_1028_865d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165e[] = { + &pci_ss_info_14e4_165e_103c_088c, + &pci_ss_info_14e4_165e_103c_0890, + &pci_ss_info_14e4_165e_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1668[] = { + &pci_ss_info_14e4_1668_103c_7039, + NULL +}; +#define pci_ss_list_14e4_166a NULL +#define pci_ss_list_14e4_166b NULL +#define pci_ss_list_14e4_166e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1677[] = { + &pci_ss_info_14e4_1677_1028_0179, + &pci_ss_info_14e4_1677_1028_0182, + &pci_ss_info_14e4_1677_1028_01ad, + &pci_ss_info_14e4_1677_1734_105d, + NULL +}; +#define pci_ss_list_14e4_1678 NULL +#define pci_ss_list_14e4_167d NULL +#define pci_ss_list_14e4_167e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_103c_12bc, + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_169c[] = { + &pci_ss_info_14e4_169c_103c_308b, + NULL +}; +#define pci_ss_list_14e4_169d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16aa[] = { + &pci_ss_info_14e4_16aa_103c_3102, + NULL +}; +#define pci_ss_list_14e4_16ac NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_0e11_00ca, + &pci_ss_info_14e4_16c7_0e11_00cb, + &pci_ss_info_14e4_16c7_103c_12c3, + &pci_ss_info_14e4_16c7_103c_12ca, + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_16dd NULL +#define pci_ss_list_14e4_16f7 NULL +#define pci_ss_list_14e4_16fd NULL +#define pci_ss_list_14e4_16fe NULL +static const pciSubsystemInfo *pci_ss_list_14e4_170c[] = { + &pci_ss_info_14e4_170c_1028_0188, + &pci_ss_info_14e4_170c_1028_0196, + &pci_ss_info_14e4_170c_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_170d[] = { + &pci_ss_info_14e4_170d_1014_0545, + NULL +}; +#define pci_ss_list_14e4_170e NULL +#define pci_ss_list_14e4_3352 NULL +#define pci_ss_list_14e4_3360 NULL +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4301[] = { + &pci_ss_info_14e4_4301_1028_0407, + &pci_ss_info_14e4_4301_1043_0120, + NULL +}; +#define pci_ss_list_14e4_4305 NULL +#define pci_ss_list_14e4_4306 NULL +#define pci_ss_list_14e4_4307 NULL +#define pci_ss_list_14e4_4310 NULL +#define pci_ss_list_14e4_4312 NULL +#define pci_ss_list_14e4_4313 NULL +#define pci_ss_list_14e4_4315 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4318[] = { + &pci_ss_info_14e4_4318_103c_1356, + &pci_ss_info_14e4_4318_1468_0311, + &pci_ss_info_14e4_4318_14e4_0449, + &pci_ss_info_14e4_4318_14e4_4318, + &pci_ss_info_14e4_4318_16ec_0119, + NULL +}; +#define pci_ss_list_14e4_4319 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4320[] = { + &pci_ss_info_14e4_4320_1028_0001, + &pci_ss_info_14e4_4320_1028_0003, + &pci_ss_info_14e4_4320_103c_12fa, + &pci_ss_info_14e4_4320_1043_100f, + &pci_ss_info_14e4_4320_1057_7025, + &pci_ss_info_14e4_4320_106b_004e, + &pci_ss_info_14e4_4320_14e4_4320, + &pci_ss_info_14e4_4320_1737_4320, + &pci_ss_info_14e4_4320_1799_7001, + &pci_ss_info_14e4_4320_1799_7010, + &pci_ss_info_14e4_4320_185f_1220, + NULL +}; +#define pci_ss_list_14e4_4321 NULL +#define pci_ss_list_14e4_4322 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4324[] = { + &pci_ss_info_14e4_4324_1028_0001, + &pci_ss_info_14e4_4324_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_4325[] = { + &pci_ss_info_14e4_4325_1414_0003, + &pci_ss_info_14e4_4325_1414_0004, + NULL +}; +#define pci_ss_list_14e4_4326 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4401[] = { + &pci_ss_info_14e4_4401_1043_80a8, + NULL +}; +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4403 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_4430 NULL +#define pci_ss_list_14e4_4432 NULL +#define pci_ss_list_14e4_4610 NULL +#define pci_ss_list_14e4_4611 NULL +#define pci_ss_list_14e4_4612 NULL +#define pci_ss_list_14e4_4613 NULL +#define pci_ss_list_14e4_4614 NULL +#define pci_ss_list_14e4_4615 NULL +#define pci_ss_list_14e4_4704 NULL +#define pci_ss_list_14e4_4705 NULL +#define pci_ss_list_14e4_4706 NULL +#define pci_ss_list_14e4_4707 NULL +#define pci_ss_list_14e4_4708 NULL +#define pci_ss_list_14e4_4710 NULL +#define pci_ss_list_14e4_4711 NULL +#define pci_ss_list_14e4_4712 NULL +#define pci_ss_list_14e4_4713 NULL +#define pci_ss_list_14e4_4714 NULL +#define pci_ss_list_14e4_4715 NULL +#define pci_ss_list_14e4_4716 NULL +#define pci_ss_list_14e4_4717 NULL +#define pci_ss_list_14e4_4718 NULL +#define pci_ss_list_14e4_4720 NULL +#define pci_ss_list_14e4_5365 NULL +#define pci_ss_list_14e4_5600 NULL +#define pci_ss_list_14e4_5605 NULL +#define pci_ss_list_14e4_5615 NULL +#define pci_ss_list_14e4_5625 NULL +#define pci_ss_list_14e4_5645 NULL +#define pci_ss_list_14e4_5670 NULL +#define pci_ss_list_14e4_5680 NULL +#define pci_ss_list_14e4_5690 NULL +#define pci_ss_list_14e4_5691 NULL +#define pci_ss_list_14e4_5692 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#define pci_ss_list_14e4_5822 NULL +#define pci_ss_list_14e4_5823 NULL +#define pci_ss_list_14e4_5824 NULL +#define pci_ss_list_14e4_5840 NULL +#define pci_ss_list_14e4_5841 NULL +#define pci_ss_list_14e4_5850 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14ea_ab07 NULL +#define pci_ss_list_14ea_ab08 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1085 NULL +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +#define pci_ss_list_14f1_1620 NULL +#define pci_ss_list_14f1_1621 NULL +#define pci_ss_list_14f1_1622 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +#define pci_ss_list_14f1_1811 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2045[] = { + &pci_ss_info_14f1_2045_14f1_2045, + NULL +}; +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_2f02 NULL +#define pci_ss_list_14f1_2f11 NULL +#define pci_ss_list_14f1_2f20 NULL +#define pci_ss_list_14f1_8234 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_8800[] = { + &pci_ss_info_14f1_8800_0070_2801, + &pci_ss_info_14f1_8800_0070_3401, + &pci_ss_info_14f1_8800_0070_9002, + &pci_ss_info_14f1_8800_1002_00f8, + &pci_ss_info_14f1_8800_1043_4823, + &pci_ss_info_14f1_8800_107d_6613, + &pci_ss_info_14f1_8800_107d_6620, + &pci_ss_info_14f1_8800_107d_663c, + &pci_ss_info_14f1_8800_10fc_d003, + &pci_ss_info_14f1_8800_10fc_d035, + &pci_ss_info_14f1_8800_1461_000b, + &pci_ss_info_14f1_8800_1462_8606, + &pci_ss_info_14f1_8800_14c7_0107, + &pci_ss_info_14f1_8800_14f1_0187, + &pci_ss_info_14f1_8800_14f1_0342, + &pci_ss_info_14f1_8800_1540_2580, + &pci_ss_info_14f1_8800_1554_4811, + &pci_ss_info_14f1_8800_17de_08a1, + &pci_ss_info_14f1_8800_17de_08a6, + &pci_ss_info_14f1_8800_17de_a8a6, + &pci_ss_info_14f1_8800_18ac_d500, + &pci_ss_info_14f1_8800_18ac_d810, + &pci_ss_info_14f1_8800_18ac_d820, + &pci_ss_info_14f1_8800_18ac_db00, + &pci_ss_info_14f1_8800_18ac_db10, + &pci_ss_info_14f1_8800_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8801[] = { + &pci_ss_info_14f1_8801_0070_2801, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8802[] = { + &pci_ss_info_14f1_8802_0070_2801, + &pci_ss_info_14f1_8802_0070_9002, + &pci_ss_info_14f1_8802_1043_4823, + &pci_ss_info_14f1_8802_107d_663c, + &pci_ss_info_14f1_8802_14f1_0187, + &pci_ss_info_14f1_8802_17de_08a1, + &pci_ss_info_14f1_8802_17de_08a6, + &pci_ss_info_14f1_8802_18ac_d500, + &pci_ss_info_14f1_8802_18ac_d810, + &pci_ss_info_14f1_8802_18ac_d820, + &pci_ss_info_14f1_8802_18ac_db00, + &pci_ss_info_14f1_8802_18ac_db10, + &pci_ss_info_14f1_8802_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8804[] = { + &pci_ss_info_14f1_8804_0070_9002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8811[] = { + &pci_ss_info_14f1_8811_0070_3401, + &pci_ss_info_14f1_8811_1462_8606, + &pci_ss_info_14f1_8811_18ac_d500, + &pci_ss_info_14f1_8811_18ac_d810, + &pci_ss_info_14f1_8811_18ac_d820, + &pci_ss_info_14f1_8811_18ac_db00, + NULL +}; +#endif +#define pci_ss_list_14f2_0120 NULL +#define pci_ss_list_14f2_0121 NULL +#define pci_ss_list_14f2_0122 NULL +#define pci_ss_list_14f2_0123 NULL +#define pci_ss_list_14f2_0124 NULL +#define pci_ss_list_14f3_2030 NULL +#define pci_ss_list_14f3_2050 NULL +#define pci_ss_list_14f3_2060 NULL +#define pci_ss_list_14f8_2077 NULL +#define pci_ss_list_14fc_0000 NULL +#define pci_ss_list_14fc_0001 NULL +#define pci_ss_list_1500_1360 NULL +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#define pci_ss_list_1516_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#define pci_ss_list_1516_0891 NULL +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151c_0003 NULL +#define pci_ss_list_151c_4000 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + &pci_ss_info_1522_0100_1522_0c00, + &pci_ss_info_1522_0100_1522_0d00, + &pci_ss_info_1522_0100_1522_1d00, + &pci_ss_info_1522_0100_1522_2000, + &pci_ss_info_1522_0100_1522_2100, + &pci_ss_info_1522_0100_1522_2200, + &pci_ss_info_1522_0100_1522_2300, + &pci_ss_info_1522_0100_1522_2400, + &pci_ss_info_1522_0100_1522_2500, + &pci_ss_info_1522_0100_1522_2600, + &pci_ss_info_1522_0100_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1524_0510 NULL +#define pci_ss_list_1524_0520 NULL +#define pci_ss_list_1524_0530 NULL +#define pci_ss_list_1524_0550 NULL +#define pci_ss_list_1524_0610 NULL +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1524_1410[] = { + &pci_ss_info_1524_1410_1025_005a, + NULL +}; +#define pci_ss_list_1524_1411 NULL +#define pci_ss_list_1524_1412 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1524_1421 NULL +#define pci_ss_list_1524_1422 NULL +#endif +#define pci_ss_list_1538_0303 NULL +#define pci_ss_list_153b_1144 NULL +#define pci_ss_list_153b_1147 NULL +#define pci_ss_list_153b_1158 NULL +#define pci_ss_list_153f_0001 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_1578_5615 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0405 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15ad_0720 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15b3_5a44 NULL +#define pci_ss_list_15b3_5a45 NULL +#define pci_ss_list_15b3_5a46 NULL +#define pci_ss_list_15b3_5e8d NULL +#define pci_ss_list_15b3_6274 NULL +#define pci_ss_list_15b3_6278 NULL +#define pci_ss_list_15b3_6279 NULL +#define pci_ss_list_15b3_6282 NULL +#define pci_ss_list_15bc_1100 NULL +#define pci_ss_list_15bc_2922 NULL +#define pci_ss_list_15bc_2928 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c5_8010 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_15e9_1841 NULL +#define pci_ss_list_15ec_3101 NULL +#define pci_ss_list_15ec_5102 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1619_0610 NULL +#define pci_ss_list_1619_0620 NULL +#define pci_ss_list_1619_0640 NULL +#define pci_ss_list_1619_1610 NULL +#define pci_ss_list_1619_2610 NULL +#define pci_ss_list_1626_8410 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1637_3874 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_3052 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_165f_1020 NULL +#define pci_ss_list_1668_0100 NULL +#define pci_ss_list_166d_0001 NULL +#define pci_ss_list_166d_0002 NULL +#define pci_ss_list_1677_104e NULL +#define pci_ss_list_1677_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_167b_2102[] = { + &pci_ss_info_167b_2102_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1681_0010 NULL +#define pci_ss_list_1688_1170 NULL +#define pci_ss_list_168c_0007 NULL +#define pci_ss_list_168c_0011 NULL +#define pci_ss_list_168c_0012 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c_0013[] = { + &pci_ss_info_168c_0013_1113_d301, + &pci_ss_info_168c_0013_1186_3202, + &pci_ss_info_168c_0013_1186_3203, + &pci_ss_info_168c_0013_1186_3a12, + &pci_ss_info_168c_0013_1186_3a13, + &pci_ss_info_168c_0013_1186_3a14, + &pci_ss_info_168c_0013_1186_3a17, + &pci_ss_info_168c_0013_1186_3a18, + &pci_ss_info_168c_0013_1186_3a63, + &pci_ss_info_168c_0013_1186_3a94, + &pci_ss_info_168c_0013_1385_4d00, + &pci_ss_info_168c_0013_1458_e911, + &pci_ss_info_168c_0013_14b7_0a60, + &pci_ss_info_168c_0013_168c_0013, + &pci_ss_info_168c_0013_168c_1025, + &pci_ss_info_168c_0013_168c_1027, + &pci_ss_info_168c_0013_168c_2026, + &pci_ss_info_168c_0013_168c_2041, + &pci_ss_info_168c_0013_168c_2042, + &pci_ss_info_168c_0013_16ab_7302, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001a[] = { + &pci_ss_info_168c_001a_1186_3a15, + &pci_ss_info_168c_001a_1186_3a16, + &pci_ss_info_168c_001a_1186_3a23, + &pci_ss_info_168c_001a_1186_3a24, + &pci_ss_info_168c_001a_168c_1052, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001b[] = { + &pci_ss_info_168c_001b_1186_3a19, + &pci_ss_info_168c_001b_1186_3a22, + NULL +}; +#define pci_ss_list_168c_0020 NULL +#define pci_ss_list_168c_1014 NULL +#endif +#define pci_ss_list_169c_0044 NULL +#define pci_ss_list_16ab_1100 NULL +#define pci_ss_list_16ab_1101 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ab_8501 NULL +#define pci_ss_list_16ae_1141 NULL +#define pci_ss_list_16ca_0001 NULL +#define pci_ss_list_16e3_1e0f NULL +#define pci_ss_list_16ec_00ff NULL +#define pci_ss_list_16ec_0116 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_16ed_1001 NULL +#define pci_ss_list_16f4_8000 NULL +#define pci_ss_list_170b_0100 NULL +#define pci_ss_list_1725_7174 NULL +#define pci_ss_list_172a_13c8 NULL +#define pci_ss_list_1737_0013 NULL +#define pci_ss_list_1737_0015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737_1032[] = { + &pci_ss_info_1737_1032_1737_0015, + &pci_ss_info_1737_1032_1737_0024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1737_1064[] = { + &pci_ss_info_1737_1064_1737_0016, + NULL +}; +#define pci_ss_list_1737_ab08 NULL +#define pci_ss_list_1737_ab09 NULL +#endif +#define pci_ss_list_173b_03e8 NULL +#define pci_ss_list_173b_03e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#define pci_ss_list_173b_03eb NULL +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_1799_6001 NULL +#define pci_ss_list_1799_6020 NULL +#define pci_ss_list_1799_6060 NULL +#define pci_ss_list_1799_7000 NULL +#define pci_ss_list_1799_7010 NULL +#define pci_ss_list_179c_0557 NULL +#define pci_ss_list_179c_0566 NULL +#define pci_ss_list_179c_5031 NULL +#define pci_ss_list_179c_5121 NULL +#define pci_ss_list_179c_5211 NULL +#define pci_ss_list_179c_5679 NULL +#define pci_ss_list_17a0_8033 NULL +#define pci_ss_list_17a0_8034 NULL +#define pci_ss_list_17b3_ab08 NULL +#define pci_ss_list_17b4_0011 NULL +#define pci_ss_list_17cc_2280 NULL +#define pci_ss_list_17d3_1110 NULL +#define pci_ss_list_17d3_1120 NULL +#define pci_ss_list_17d3_1130 NULL +#define pci_ss_list_17d3_1160 NULL +#define pci_ss_list_17d3_1210 NULL +#define pci_ss_list_17d3_1220 NULL +#define pci_ss_list_17d3_1230 NULL +#define pci_ss_list_17d3_1260 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17d3_5831[] = { + &pci_ss_info_17d3_5831_103c_12d5, + NULL +}; +#define pci_ss_list_17d3_5832 NULL +#endif +#define pci_ss_list_17fe_2120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe_2220[] = { + &pci_ss_info_17fe_2220_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1814_0101[] = { + &pci_ss_info_1814_0101_1043_0127, + &pci_ss_info_1814_0101_1462_6828, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0201[] = { + &pci_ss_info_1814_0201_1043_130f, + &pci_ss_info_1814_0201_1371_001e, + &pci_ss_info_1814_0201_1371_001f, + &pci_ss_info_1814_0201_1371_0020, + &pci_ss_info_1814_0201_1458_e381, + &pci_ss_info_1814_0201_1458_e931, + &pci_ss_info_1814_0201_1462_6835, + &pci_ss_info_1814_0201_1737_0032, + &pci_ss_info_1814_0201_1799_700a, + &pci_ss_info_1814_0201_1799_701a, + &pci_ss_info_1814_0201_185f_22a0, + NULL +}; +#define pci_ss_list_1814_0401 NULL +#endif +#define pci_ss_list_1822_4e35 NULL +#define pci_ss_list_182d_3069 NULL +#define pci_ss_list_182d_9790 NULL +#define pci_ss_list_183b_08a7 NULL +#define pci_ss_list_183b_08a8 NULL +#define pci_ss_list_183b_08a9 NULL +#define pci_ss_list_1864_2110 NULL +#define pci_ss_list_1867_5a44 NULL +#define pci_ss_list_1867_5a45 NULL +#define pci_ss_list_1867_5a46 NULL +#define pci_ss_list_1867_6278 NULL +#define pci_ss_list_1867_6282 NULL +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_18ac_d500 NULL +#define pci_ss_list_18ac_d810 NULL +#define pci_ss_list_18ac_d820 NULL +#define pci_ss_list_18b8_b001 NULL +#define pci_ss_list_18ca_0020 NULL +#define pci_ss_list_18ca_0040 NULL +#define pci_ss_list_18d2_3069 NULL +#define pci_ss_list_18dd_4c6f NULL +#define pci_ss_list_18e6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec_c006[] = { + &pci_ss_info_18ec_c006_18ec_d001, + &pci_ss_info_18ec_c006_18ec_d002, + &pci_ss_info_18ec_c006_18ec_d003, + &pci_ss_info_18ec_c006_18ec_d004, + NULL +}; +#define pci_ss_list_18ec_c045 NULL +#define pci_ss_list_18ec_c050 NULL +static const pciSubsystemInfo *pci_ss_list_18ec_c058[] = { + &pci_ss_info_18ec_c058_18ec_d001, + &pci_ss_info_18ec_c058_18ec_d002, + &pci_ss_info_18ec_c058_18ec_d003, + &pci_ss_info_18ec_c058_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7_0001 NULL +#define pci_ss_list_18f7_0002 NULL +#define pci_ss_list_18f7_0004 NULL +#define pci_ss_list_18f7_0005 NULL +#define pci_ss_list_18f7_000a NULL +#define pci_ss_list_1957_0080 NULL +#define pci_ss_list_1957_0081 NULL +#define pci_ss_list_1957_0082 NULL +#define pci_ss_list_1957_0083 NULL +#define pci_ss_list_1957_0084 NULL +#define pci_ss_list_1957_0085 NULL +#define pci_ss_list_1957_0086 NULL +#define pci_ss_list_1957_0087 NULL +#define pci_ss_list_1966_1975 NULL +#define pci_ss_list_196a_0101 NULL +#define pci_ss_list_196a_0102 NULL +#define pci_ss_list_197b_2360 NULL +#define pci_ss_list_197b_2363 NULL +#define pci_ss_list_1989_0001 NULL +#define pci_ss_list_1989_8001 NULL +#define pci_ss_list_19ae_0520 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_1fc0_0300 NULL +#define pci_ss_list_1fc1_000d NULL +#define pci_ss_list_1fce_0001 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_0021[] = { + &pci_ss_info_3388_0021_4c53_1050, + &pci_ss_info_3388_0021_4c53_1080, + &pci_ss_info_3388_0021_4c53_1090, + &pci_ss_info_3388_0021_4c53_10a0, + &pci_ss_info_3388_0021_4c53_3010, + &pci_ss_info_3388_0021_4c53_3011, + &pci_ss_info_3388_0021_4c53_4000, + NULL +}; +#define pci_ss_list_3388_0022 NULL +#define pci_ss_list_3388_0026 NULL +#define pci_ss_list_3388_101a NULL +#define pci_ss_list_3388_101b NULL +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3842_c370 NULL +#define pci_ss_list_3d3d_0001 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0002[] = { + &pci_ss_info_3d3d_0002_0000_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0003[] = { + &pci_ss_info_3d3d_0003_0000_0000, + NULL +}; +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0006[] = { + &pci_ss_info_3d3d_0006_0000_0000, + &pci_ss_info_3d3d_0006_1048_0a42, + NULL +}; +#define pci_ss_list_3d3d_0007 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0008[] = { + &pci_ss_info_3d3d_0008_1048_0a42, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_1048_0a42, + &pci_ss_info_3d3d_0009_13e9_1000, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_000d NULL +#define pci_ss_list_3d3d_0011 NULL +#define pci_ss_list_3d3d_0012 NULL +#define pci_ss_list_3d3d_0013 NULL +#define pci_ss_list_3d3d_0020 NULL +#define pci_ss_list_3d3d_0022 NULL +#define pci_ss_list_3d3d_0024 NULL +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_07a1 NULL +#define pci_ss_list_3d3d_07a2 NULL +#define pci_ss_list_3d3d_07a3 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_4144_0044 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4444_0016[] = { + &pci_ss_info_4444_0016_0070_4009, + &pci_ss_info_4444_0016_0070_8003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4444_0803[] = { + &pci_ss_info_4444_0803_0070_4000, + &pci_ss_info_4444_0803_0070_4001, + &pci_ss_info_4444_0803_1461_a3cf, + NULL +}; +#endif +#define pci_ss_list_4916_1960 NULL +#define pci_ss_list_494f_10e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53_0000[] = { + &pci_ss_info_4c53_0000_4c53_3000, + &pci_ss_info_4c53_0000_4c53_3001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4c53_0001[] = { + &pci_ss_info_4c53_0001_4c53_3002, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5168_0301 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_1033_8110, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + &pci_ss_info_5333_8c12_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_544c_0350 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_5654_3132 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_6666_0004 NULL +#define pci_ss_list_6666_0101 NULL +#define pci_ss_list_7063_2000 NULL +#define pci_ss_list_7063_3000 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0309 NULL +#define pci_ss_list_8086_030d NULL +#define pci_ss_list_8086_0326 NULL +#define pci_ss_list_8086_0327 NULL +#define pci_ss_list_8086_0329 NULL +#define pci_ss_list_8086_032a NULL +#define pci_ss_list_8086_032c NULL +#define pci_ss_list_8086_0330 NULL +#define pci_ss_list_8086_0331 NULL +#define pci_ss_list_8086_0332 NULL +#define pci_ss_list_8086_0333 NULL +#define pci_ss_list_8086_0334 NULL +#define pci_ss_list_8086_0335 NULL +#define pci_ss_list_8086_0336 NULL +#define pci_ss_list_8086_0340 NULL +#define pci_ss_list_8086_0341 NULL +#define pci_ss_list_8086_0370 NULL +#define pci_ss_list_8086_0371 NULL +#define pci_ss_list_8086_0372 NULL +#define pci_ss_list_8086_0373 NULL +#define pci_ss_list_8086_0374 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0500 NULL +#define pci_ss_list_8086_0501 NULL +#define pci_ss_list_8086_0502 NULL +#define pci_ss_list_8086_0503 NULL +#define pci_ss_list_8086_0510 NULL +#define pci_ss_list_8086_0511 NULL +#define pci_ss_list_8086_0512 NULL +#define pci_ss_list_8086_0513 NULL +#define pci_ss_list_8086_0514 NULL +#define pci_ss_list_8086_0515 NULL +#define pci_ss_list_8086_0516 NULL +#define pci_ss_list_8086_0530 NULL +#define pci_ss_list_8086_0531 NULL +#define pci_ss_list_8086_0532 NULL +#define pci_ss_list_8086_0533 NULL +#define pci_ss_list_8086_0534 NULL +#define pci_ss_list_8086_0535 NULL +#define pci_ss_list_8086_0536 NULL +#define pci_ss_list_8086_0537 NULL +static const pciSubsystemInfo *pci_ss_list_8086_0600[] = { + &pci_ss_info_8086_0600_8086_01af, + &pci_ss_info_8086_0600_8086_01c1, + &pci_ss_info_8086_0600_8086_01f7, + NULL +}; +#define pci_ss_list_8086_061f NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1002, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_1014_0269, + &pci_ss_info_8086_1008_1028_011c, + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + &pci_ss_info_8086_1008_8086_3108, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_1014_0268, + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +#define pci_ss_list_8086_100a NULL +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100d[] = { + &pci_ss_info_8086_100d_1028_0123, + &pci_ss_info_8086_100d_1079_891f, + &pci_ss_info_8086_100d_4c53_1080, + &pci_ss_info_8086_100d_8086_110d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_1014_0265, + &pci_ss_info_8086_100e_1014_0267, + &pci_ss_info_8086_100e_1014_026a, + &pci_ss_info_8086_100e_1024_0134, + &pci_ss_info_8086_100e_1028_002e, + &pci_ss_info_8086_100e_1028_0151, + &pci_ss_info_8086_100e_107b_8920, + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + &pci_ss_info_8086_100e_8086_1376, + &pci_ss_info_8086_100e_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_1014_0269, + &pci_ss_info_8086_100f_1014_028e, + &pci_ss_info_8086_100f_8086_1000, + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_0e11_00db, + &pci_ss_info_8086_1010_1014_027c, + &pci_ss_info_8086_1010_18fb_7872, + &pci_ss_info_8086_1010_1fc1_0026, + &pci_ss_info_8086_1010_4c53_1080, + &pci_ss_info_8086_1010_4c53_10a0, + &pci_ss_info_8086_1010_8086_1011, + &pci_ss_info_8086_1010_8086_1012, + &pci_ss_info_8086_1010_8086_101a, + &pci_ss_info_8086_1010_8086_3424, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_1014_0268, + &pci_ss_info_8086_1011_8086_1002, + &pci_ss_info_8086_1011_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_0e11_00dc, + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1013[] = { + &pci_ss_info_8086_1013_8086_0013, + &pci_ss_info_8086_1013_8086_1013, + &pci_ss_info_8086_1013_8086_1113, + NULL +}; +#define pci_ss_list_8086_1014 NULL +#define pci_ss_list_8086_1015 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1016[] = { + &pci_ss_info_8086_1016_1014_052c, + &pci_ss_info_8086_1016_1179_0001, + &pci_ss_info_8086_1016_8086_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1017[] = { + &pci_ss_info_8086_1017_8086_1017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1018[] = { + &pci_ss_info_8086_1018_8086_1018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1019[] = { + &pci_ss_info_8086_1019_1458_1019, + &pci_ss_info_8086_1019_1458_e000, + &pci_ss_info_8086_1019_8086_1019, + &pci_ss_info_8086_1019_8086_301f, + &pci_ss_info_8086_1019_8086_3427, + NULL +}; +#define pci_ss_list_8086_101a NULL +static const pciSubsystemInfo *pci_ss_list_8086_101d[] = { + &pci_ss_info_8086_101d_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101e[] = { + &pci_ss_info_8086_101e_1014_0549, + &pci_ss_info_8086_101e_1179_0001, + &pci_ss_info_8086_101e_8086_101e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1026[] = { + &pci_ss_info_8086_1026_1028_0169, + &pci_ss_info_8086_1026_8086_1000, + &pci_ss_info_8086_1026_8086_1001, + &pci_ss_info_8086_1026_8086_1002, + &pci_ss_info_8086_1026_8086_1026, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1027[] = { + &pci_ss_info_8086_1027_103c_3103, + &pci_ss_info_8086_1027_8086_1001, + &pci_ss_info_8086_1027_8086_1002, + &pci_ss_info_8086_1027_8086_1003, + &pci_ss_info_8086_1027_8086_1027, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1028[] = { + &pci_ss_info_8086_1028_8086_1028, + NULL +}; +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + &pci_ss_info_8086_1031_813c_104d, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1038[] = { + &pci_ss_info_8086_1038_0e11_0098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1039[] = { + &pci_ss_info_8086_1039_1014_0267, + NULL +}; +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +#define pci_ss_list_8086_103d NULL +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1043[] = { + &pci_ss_info_8086_1043_8086_2527, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1048[] = { + &pci_ss_info_8086_1048_8086_a01f, + &pci_ss_info_8086_1048_8086_a11f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1050[] = { + &pci_ss_info_8086_1050_1462_728c, + &pci_ss_info_8086_1050_1462_758c, + &pci_ss_info_8086_1050_8086_3020, + &pci_ss_info_8086_1050_8086_302f, + &pci_ss_info_8086_1050_8086_3427, + NULL +}; +#define pci_ss_list_8086_1051 NULL +#define pci_ss_list_8086_1052 NULL +#define pci_ss_list_8086_1053 NULL +#define pci_ss_list_8086_1059 NULL +#define pci_ss_list_8086_105e NULL +#define pci_ss_list_8086_105f NULL +#define pci_ss_list_8086_1060 NULL +#define pci_ss_list_8086_1064 NULL +#define pci_ss_list_8086_1065 NULL +#define pci_ss_list_8086_1066 NULL +#define pci_ss_list_8086_1067 NULL +#define pci_ss_list_8086_1068 NULL +#define pci_ss_list_8086_1069 NULL +#define pci_ss_list_8086_106a NULL +#define pci_ss_list_8086_106b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1075[] = { + &pci_ss_info_8086_1075_1028_0165, + &pci_ss_info_8086_1075_8086_0075, + &pci_ss_info_8086_1075_8086_1075, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1076[] = { + &pci_ss_info_8086_1076_1028_0165, + &pci_ss_info_8086_1076_1028_019a, + &pci_ss_info_8086_1076_8086_0076, + &pci_ss_info_8086_1076_8086_1076, + &pci_ss_info_8086_1076_8086_1176, + &pci_ss_info_8086_1076_8086_1276, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1077[] = { + &pci_ss_info_8086_1077_1179_0001, + &pci_ss_info_8086_1077_8086_0077, + &pci_ss_info_8086_1077_8086_1077, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1078[] = { + &pci_ss_info_8086_1078_8086_1078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1079[] = { + &pci_ss_info_8086_1079_103c_12a6, + &pci_ss_info_8086_1079_103c_12cf, + &pci_ss_info_8086_1079_1fc1_0027, + &pci_ss_info_8086_1079_4c53_1090, + &pci_ss_info_8086_1079_4c53_10b0, + &pci_ss_info_8086_1079_8086_0079, + &pci_ss_info_8086_1079_8086_1079, + &pci_ss_info_8086_1079_8086_1179, + &pci_ss_info_8086_1079_8086_117a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107a[] = { + &pci_ss_info_8086_107a_103c_12a8, + &pci_ss_info_8086_107a_8086_107a, + &pci_ss_info_8086_107a_8086_127a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107b[] = { + &pci_ss_info_8086_107b_8086_007b, + &pci_ss_info_8086_107b_8086_107b, + NULL +}; +#define pci_ss_list_8086_107c NULL +#define pci_ss_list_8086_107d NULL +#define pci_ss_list_8086_107e NULL +#define pci_ss_list_8086_107f NULL +#define pci_ss_list_8086_1080 NULL +#define pci_ss_list_8086_1081 NULL +#define pci_ss_list_8086_1082 NULL +#define pci_ss_list_8086_1083 NULL +#define pci_ss_list_8086_1084 NULL +#define pci_ss_list_8086_1085 NULL +#define pci_ss_list_8086_1086 NULL +#define pci_ss_list_8086_1087 NULL +#define pci_ss_list_8086_1089 NULL +#define pci_ss_list_8086_108a NULL +#define pci_ss_list_8086_108b NULL +#define pci_ss_list_8086_108c NULL +#define pci_ss_list_8086_1096 NULL +#define pci_ss_list_8086_1097 NULL +#define pci_ss_list_8086_1098 NULL +#define pci_ss_list_8086_1099 NULL +#define pci_ss_list_8086_109a NULL +#define pci_ss_list_8086_1107 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + &pci_ss_info_8086_1130_8086_4532, + &pci_ss_info_8086_1130_8086_4557, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + &pci_ss_info_8086_1132_8086_4532, + &pci_ss_info_8086_1132_8086_4541, + &pci_ss_info_8086_1132_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1209[] = { + &pci_ss_info_8086_1209_4c53_1050, + &pci_ss_info_8086_1209_4c53_1051, + &pci_ss_info_8086_1209_4c53_1070, + NULL +}; +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1028_00ce, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_108e_10cf, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_110a_008b, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_13e9_1000, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_4c53_1080, + &pci_ss_info_8086_1229_4c53_10e0, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + &pci_ss_info_8086_1229_8086_3411, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123e NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + &pci_ss_info_8086_1461_4c53_1090, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + &pci_ss_info_8086_1960_e4bf_1010, + &pci_ss_info_8086_1960_e4bf_1020, + &pci_ss_info_8086_1960_e4bf_1040, + &pci_ss_info_8086_1960_e4bf_3100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1a30[] = { + &pci_ss_info_8086_1a30_1028_010e, + NULL +}; +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_1a38 NULL +#define pci_ss_list_8086_1a48 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_110a_0051, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + &pci_ss_info_8086_2415_1734_1025, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_1028_010e, + &pci_ss_info_8086_2442_1043_8027, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + &pci_ss_info_8086_2442_8086_4532, + &pci_ss_info_8086_2442_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1028_010e, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + &pci_ss_info_8086_2443_8086_4532, + &pci_ss_info_8086_2443_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_1028_010e, + &pci_ss_info_8086_2444_1043_8027, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + &pci_ss_info_8086_2444_8086_4532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + &pci_ss_info_8086_2445_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2448[] = { + &pci_ss_info_8086_2448_103c_099c, + &pci_ss_info_8086_2448_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_1014_0265, + &pci_ss_info_8086_2449_1014_0267, + &pci_ss_info_8086_2449_1014_026a, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1179_ff01, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1028_010e, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + &pci_ss_info_8086_244b_8086_4532, + &pci_ss_info_8086_244b_8086_4557, + NULL +}; +#define pci_ss_list_8086_244c NULL +static const pciSubsystemInfo *pci_ss_list_8086_244e[] = { + &pci_ss_info_8086_244e_1014_0267, + NULL +}; +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_0e11_0030, + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + &pci_ss_info_8086_2482_8086_3424, + &pci_ss_info_8086_2482_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_0e11_0030, + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1013_5959, + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_101f_1025, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_1179_0001, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_0e11_0030, + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_0e11_0030, + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + &pci_ss_info_8086_248a_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1014_0267, + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1014_0267, + &pci_ss_info_8086_24c2_1025_005a, + &pci_ss_info_8086_24c2_1028_0126, + &pci_ss_info_8086_24c2_1028_0163, + &pci_ss_info_8086_24c2_1028_0196, + &pci_ss_info_8086_24c2_103c_088c, + &pci_ss_info_8086_24c2_103c_0890, + &pci_ss_info_8086_24c2_1071_8160, + &pci_ss_info_8086_24c2_1462_5800, + &pci_ss_info_8086_24c2_1509_2990, + &pci_ss_info_8086_24c2_1734_1055, + &pci_ss_info_8086_24c2_4c53_1090, + &pci_ss_info_8086_24c2_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1014_0267, + &pci_ss_info_8086_24c3_1025_005a, + &pci_ss_info_8086_24c3_1028_0126, + &pci_ss_info_8086_24c3_103c_088c, + &pci_ss_info_8086_24c3_103c_0890, + &pci_ss_info_8086_24c3_1071_8160, + &pci_ss_info_8086_24c3_1458_24c2, + &pci_ss_info_8086_24c3_1462_5800, + &pci_ss_info_8086_24c3_1734_1055, + &pci_ss_info_8086_24c3_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1014_0267, + &pci_ss_info_8086_24c4_1025_005a, + &pci_ss_info_8086_24c4_1028_0126, + &pci_ss_info_8086_24c4_1028_0163, + &pci_ss_info_8086_24c4_1028_0196, + &pci_ss_info_8086_24c4_103c_088c, + &pci_ss_info_8086_24c4_103c_0890, + &pci_ss_info_8086_24c4_1071_8160, + &pci_ss_info_8086_24c4_1462_5800, + &pci_ss_info_8086_24c4_1509_2990, + &pci_ss_info_8086_24c4_4c53_1090, + &pci_ss_info_8086_24c4_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_0e11_00b8, + &pci_ss_info_8086_24c5_1014_0267, + &pci_ss_info_8086_24c5_1025_005a, + &pci_ss_info_8086_24c5_1028_0139, + &pci_ss_info_8086_24c5_1028_0163, + &pci_ss_info_8086_24c5_1028_0196, + &pci_ss_info_8086_24c5_103c_088c, + &pci_ss_info_8086_24c5_103c_0890, + &pci_ss_info_8086_24c5_1071_8160, + &pci_ss_info_8086_24c5_1458_a002, + &pci_ss_info_8086_24c5_1462_5800, + &pci_ss_info_8086_24c5_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c6[] = { + &pci_ss_info_8086_24c6_1025_005a, + &pci_ss_info_8086_24c6_1028_0196, + &pci_ss_info_8086_24c6_103c_088c, + &pci_ss_info_8086_24c6_103c_0890, + &pci_ss_info_8086_24c6_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1014_0267, + &pci_ss_info_8086_24c7_1025_005a, + &pci_ss_info_8086_24c7_1028_0126, + &pci_ss_info_8086_24c7_1028_0163, + &pci_ss_info_8086_24c7_1028_0196, + &pci_ss_info_8086_24c7_103c_088c, + &pci_ss_info_8086_24c7_103c_0890, + &pci_ss_info_8086_24c7_1071_8160, + &pci_ss_info_8086_24c7_1462_5800, + &pci_ss_info_8086_24c7_1509_2990, + &pci_ss_info_8086_24c7_4c53_1090, + &pci_ss_info_8086_24c7_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24ca[] = { + &pci_ss_info_8086_24ca_1025_005a, + &pci_ss_info_8086_24ca_1028_0163, + &pci_ss_info_8086_24ca_1028_0196, + &pci_ss_info_8086_24ca_103c_088c, + &pci_ss_info_8086_24ca_103c_0890, + &pci_ss_info_8086_24ca_1071_8160, + &pci_ss_info_8086_24ca_1734_1055, + &pci_ss_info_8086_24ca_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1014_0267, + &pci_ss_info_8086_24cb_1028_0126, + &pci_ss_info_8086_24cb_1458_24c2, + &pci_ss_info_8086_24cb_1462_5800, + &pci_ss_info_8086_24cb_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cc[] = { + &pci_ss_info_8086_24cc_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1014_0267, + &pci_ss_info_8086_24cd_1025_005a, + &pci_ss_info_8086_24cd_1028_0126, + &pci_ss_info_8086_24cd_1028_0139, + &pci_ss_info_8086_24cd_1028_0163, + &pci_ss_info_8086_24cd_1028_0196, + &pci_ss_info_8086_24cd_103c_088c, + &pci_ss_info_8086_24cd_103c_0890, + &pci_ss_info_8086_24cd_1071_8160, + &pci_ss_info_8086_24cd_1462_3981, + &pci_ss_info_8086_24cd_1509_1968, + &pci_ss_info_8086_24cd_1734_1055, + &pci_ss_info_8086_24cd_4c53_1090, + NULL +}; +#define pci_ss_list_8086_24d0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d1[] = { + &pci_ss_info_8086_24d1_1028_0169, + &pci_ss_info_8086_24d1_1028_019a, + &pci_ss_info_8086_24d1_103c_12bc, + &pci_ss_info_8086_24d1_1043_80a6, + &pci_ss_info_8086_24d1_1458_24d1, + &pci_ss_info_8086_24d1_1462_7280, + &pci_ss_info_8086_24d1_15d9_4580, + &pci_ss_info_8086_24d1_8086_3427, + &pci_ss_info_8086_24d1_8086_4246, + &pci_ss_info_8086_24d1_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d2[] = { + &pci_ss_info_8086_24d2_1028_0169, + &pci_ss_info_8086_24d2_1028_0183, + &pci_ss_info_8086_24d2_1028_019a, + &pci_ss_info_8086_24d2_103c_12bc, + &pci_ss_info_8086_24d2_1043_80a6, + &pci_ss_info_8086_24d2_1458_24d2, + &pci_ss_info_8086_24d2_1462_7280, + &pci_ss_info_8086_24d2_15d9_4580, + &pci_ss_info_8086_24d2_1734_101c, + &pci_ss_info_8086_24d2_8086_3427, + &pci_ss_info_8086_24d2_8086_4246, + &pci_ss_info_8086_24d2_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d3[] = { + &pci_ss_info_8086_24d3_1028_0169, + &pci_ss_info_8086_24d3_1043_80a6, + &pci_ss_info_8086_24d3_1458_24d2, + &pci_ss_info_8086_24d3_1462_7280, + &pci_ss_info_8086_24d3_15d9_4580, + &pci_ss_info_8086_24d3_1734_101c, + &pci_ss_info_8086_24d3_8086_3427, + &pci_ss_info_8086_24d3_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d4[] = { + &pci_ss_info_8086_24d4_1028_0169, + &pci_ss_info_8086_24d4_1028_0183, + &pci_ss_info_8086_24d4_1028_019a, + &pci_ss_info_8086_24d4_103c_12bc, + &pci_ss_info_8086_24d4_1043_80a6, + &pci_ss_info_8086_24d4_1458_24d2, + &pci_ss_info_8086_24d4_1462_7280, + &pci_ss_info_8086_24d4_15d9_4580, + &pci_ss_info_8086_24d4_1734_101c, + &pci_ss_info_8086_24d4_8086_3427, + &pci_ss_info_8086_24d4_8086_4246, + &pci_ss_info_8086_24d4_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d5[] = { + &pci_ss_info_8086_24d5_1028_0169, + &pci_ss_info_8086_24d5_103c_12bc, + &pci_ss_info_8086_24d5_1043_80f3, + &pci_ss_info_8086_24d5_1043_810f, + &pci_ss_info_8086_24d5_1458_a002, + &pci_ss_info_8086_24d5_1462_7280, + &pci_ss_info_8086_24d5_8086_a000, + &pci_ss_info_8086_24d5_8086_e000, + &pci_ss_info_8086_24d5_8086_e001, + NULL +}; +#define pci_ss_list_8086_24d6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d7[] = { + &pci_ss_info_8086_24d7_1028_0169, + &pci_ss_info_8086_24d7_1028_0183, + &pci_ss_info_8086_24d7_103c_12bc, + &pci_ss_info_8086_24d7_1043_80a6, + &pci_ss_info_8086_24d7_1458_24d2, + &pci_ss_info_8086_24d7_1462_7280, + &pci_ss_info_8086_24d7_15d9_4580, + &pci_ss_info_8086_24d7_1734_101c, + &pci_ss_info_8086_24d7_8086_3427, + &pci_ss_info_8086_24d7_8086_4246, + &pci_ss_info_8086_24d7_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24db[] = { + &pci_ss_info_8086_24db_1028_0169, + &pci_ss_info_8086_24db_1028_019a, + &pci_ss_info_8086_24db_103c_12bc, + &pci_ss_info_8086_24db_1043_80a6, + &pci_ss_info_8086_24db_1458_24d2, + &pci_ss_info_8086_24db_1462_7280, + &pci_ss_info_8086_24db_1462_7580, + &pci_ss_info_8086_24db_15d9_4580, + &pci_ss_info_8086_24db_1734_101c, + &pci_ss_info_8086_24db_8086_24db, + &pci_ss_info_8086_24db_8086_3427, + &pci_ss_info_8086_24db_8086_4246, + &pci_ss_info_8086_24db_8086_524c, + NULL +}; +#define pci_ss_list_8086_24dc NULL +static const pciSubsystemInfo *pci_ss_list_8086_24dd[] = { + &pci_ss_info_8086_24dd_1028_0169, + &pci_ss_info_8086_24dd_1028_0183, + &pci_ss_info_8086_24dd_1028_019a, + &pci_ss_info_8086_24dd_103c_12bc, + &pci_ss_info_8086_24dd_1043_80a6, + &pci_ss_info_8086_24dd_1458_5006, + &pci_ss_info_8086_24dd_1462_7280, + &pci_ss_info_8086_24dd_8086_3427, + &pci_ss_info_8086_24dd_8086_4246, + &pci_ss_info_8086_24dd_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24de[] = { + &pci_ss_info_8086_24de_1028_0169, + &pci_ss_info_8086_24de_1043_80a6, + &pci_ss_info_8086_24de_1458_24d2, + &pci_ss_info_8086_24de_1462_7280, + &pci_ss_info_8086_24de_15d9_4580, + &pci_ss_info_8086_24de_1734_101c, + &pci_ss_info_8086_24de_8086_3427, + &pci_ss_info_8086_24de_8086_4246, + &pci_ss_info_8086_24de_8086_524c, + NULL +}; +#define pci_ss_list_8086_24df NULL +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + &pci_ss_info_8086_2541_4c53_1090, + &pci_ss_info_8086_2541_8086_3424, + NULL +}; +#define pci_ss_list_8086_2543 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2544[] = { + &pci_ss_info_8086_2544_4c53_1090, + NULL +}; +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_254c[] = { + &pci_ss_info_8086_254c_4c53_1090, + &pci_ss_info_8086_254c_8086_3424, + NULL +}; +#define pci_ss_list_8086_2550 NULL +#define pci_ss_list_8086_2551 NULL +#define pci_ss_list_8086_2552 NULL +#define pci_ss_list_8086_2553 NULL +#define pci_ss_list_8086_2554 NULL +#define pci_ss_list_8086_255d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1028_0126, + &pci_ss_info_8086_2560_1458_2560, + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2562[] = { + &pci_ss_info_8086_2562_1014_0267, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2570[] = { + &pci_ss_info_8086_2570_1043_80f2, + &pci_ss_info_8086_2570_1458_2570, + NULL +}; +#define pci_ss_list_8086_2571 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2572[] = { + &pci_ss_info_8086_2572_1028_019d, + &pci_ss_info_8086_2572_1043_80a5, + NULL +}; +#define pci_ss_list_8086_2573 NULL +#define pci_ss_list_8086_2576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2578[] = { + &pci_ss_info_8086_2578_1458_2578, + &pci_ss_info_8086_2578_1462_7580, + &pci_ss_info_8086_2578_15d9_4580, + NULL +}; +#define pci_ss_list_8086_2579 NULL +#define pci_ss_list_8086_257b NULL +#define pci_ss_list_8086_257e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2580[] = { + &pci_ss_info_8086_2580_1458_2580, + &pci_ss_info_8086_2580_1462_7028, + &pci_ss_info_8086_2580_1734_105b, + NULL +}; +#define pci_ss_list_8086_2581 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2582[] = { + &pci_ss_info_8086_2582_1028_1079, + &pci_ss_info_8086_2582_1458_2582, + &pci_ss_info_8086_2582_1734_105b, + NULL +}; +#define pci_ss_list_8086_2584 NULL +#define pci_ss_list_8086_2585 NULL +#define pci_ss_list_8086_2588 NULL +#define pci_ss_list_8086_2589 NULL +#define pci_ss_list_8086_258a NULL +static const pciSubsystemInfo *pci_ss_list_8086_2590[] = { + &pci_ss_info_8086_2590_103c_099c, + &pci_ss_info_8086_2590_a304_81b7, + NULL +}; +#define pci_ss_list_8086_2591 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2592[] = { + &pci_ss_info_8086_2592_103c_099c, + &pci_ss_info_8086_2592_1043_1881, + NULL +}; +#define pci_ss_list_8086_25a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a2[] = { + &pci_ss_info_8086_25a2_4c53_10b0, + &pci_ss_info_8086_25a2_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a3[] = { + &pci_ss_info_8086_25a3_4c53_10b0, + &pci_ss_info_8086_25a3_4c53_10d0, + &pci_ss_info_8086_25a3_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a4[] = { + &pci_ss_info_8086_25a4_4c53_10b0, + &pci_ss_info_8086_25a4_4c53_10d0, + &pci_ss_info_8086_25a4_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a6[] = { + &pci_ss_info_8086_25a6_4c53_10b0, + NULL +}; +#define pci_ss_list_8086_25a7 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a9[] = { + &pci_ss_info_8086_25a9_4c53_10b0, + &pci_ss_info_8086_25a9_4c53_10d0, + &pci_ss_info_8086_25a9_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25aa[] = { + &pci_ss_info_8086_25aa_4c53_10b0, + &pci_ss_info_8086_25aa_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ab[] = { + &pci_ss_info_8086_25ab_4c53_10b0, + &pci_ss_info_8086_25ab_4c53_10d0, + &pci_ss_info_8086_25ab_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ac[] = { + &pci_ss_info_8086_25ac_4c53_10b0, + &pci_ss_info_8086_25ac_4c53_10d0, + &pci_ss_info_8086_25ac_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ad[] = { + &pci_ss_info_8086_25ad_4c53_10b0, + &pci_ss_info_8086_25ad_4c53_10d0, + &pci_ss_info_8086_25ad_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25ae NULL +static const pciSubsystemInfo *pci_ss_list_8086_25b0[] = { + &pci_ss_info_8086_25b0_4c53_10d0, + &pci_ss_info_8086_25b0_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25c0 NULL +#define pci_ss_list_8086_25d0 NULL +#define pci_ss_list_8086_25d4 NULL +#define pci_ss_list_8086_25d8 NULL +#define pci_ss_list_8086_25e2 NULL +#define pci_ss_list_8086_25e3 NULL +#define pci_ss_list_8086_25e4 NULL +#define pci_ss_list_8086_25e5 NULL +#define pci_ss_list_8086_25e6 NULL +#define pci_ss_list_8086_25e7 NULL +#define pci_ss_list_8086_25e8 NULL +#define pci_ss_list_8086_25f0 NULL +#define pci_ss_list_8086_25f1 NULL +#define pci_ss_list_8086_25f3 NULL +#define pci_ss_list_8086_25f5 NULL +#define pci_ss_list_8086_25f6 NULL +#define pci_ss_list_8086_25f7 NULL +#define pci_ss_list_8086_25f8 NULL +#define pci_ss_list_8086_25f9 NULL +#define pci_ss_list_8086_25fa NULL +#define pci_ss_list_8086_2600 NULL +#define pci_ss_list_8086_2601 NULL +#define pci_ss_list_8086_2602 NULL +#define pci_ss_list_8086_2603 NULL +#define pci_ss_list_8086_2604 NULL +#define pci_ss_list_8086_2605 NULL +#define pci_ss_list_8086_2606 NULL +#define pci_ss_list_8086_2607 NULL +#define pci_ss_list_8086_2608 NULL +#define pci_ss_list_8086_2609 NULL +#define pci_ss_list_8086_260a NULL +#define pci_ss_list_8086_260c NULL +#define pci_ss_list_8086_2610 NULL +#define pci_ss_list_8086_2611 NULL +#define pci_ss_list_8086_2612 NULL +#define pci_ss_list_8086_2613 NULL +#define pci_ss_list_8086_2614 NULL +#define pci_ss_list_8086_2615 NULL +#define pci_ss_list_8086_2617 NULL +#define pci_ss_list_8086_2618 NULL +#define pci_ss_list_8086_2619 NULL +#define pci_ss_list_8086_261a NULL +#define pci_ss_list_8086_261b NULL +#define pci_ss_list_8086_261c NULL +#define pci_ss_list_8086_261d NULL +#define pci_ss_list_8086_261e NULL +#define pci_ss_list_8086_2620 NULL +#define pci_ss_list_8086_2621 NULL +#define pci_ss_list_8086_2622 NULL +#define pci_ss_list_8086_2623 NULL +#define pci_ss_list_8086_2624 NULL +#define pci_ss_list_8086_2625 NULL +#define pci_ss_list_8086_2626 NULL +#define pci_ss_list_8086_2627 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2640[] = { + &pci_ss_info_8086_2640_1462_7028, + &pci_ss_info_8086_2640_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2641[] = { + &pci_ss_info_8086_2641_103c_099c, + NULL +}; +#define pci_ss_list_8086_2642 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2651[] = { + &pci_ss_info_8086_2651_1028_0179, + &pci_ss_info_8086_2651_1734_105c, + &pci_ss_info_8086_2651_8086_4147, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2652[] = { + &pci_ss_info_8086_2652_1462_7028, + NULL +}; +#define pci_ss_list_8086_2653 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2658[] = { + &pci_ss_info_8086_2658_1028_0179, + &pci_ss_info_8086_2658_103c_099c, + &pci_ss_info_8086_2658_1458_2558, + &pci_ss_info_8086_2658_1462_7028, + &pci_ss_info_8086_2658_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2659[] = { + &pci_ss_info_8086_2659_1028_0179, + &pci_ss_info_8086_2659_103c_099c, + &pci_ss_info_8086_2659_1458_2659, + &pci_ss_info_8086_2659_1462_7028, + &pci_ss_info_8086_2659_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265a[] = { + &pci_ss_info_8086_265a_1028_0179, + &pci_ss_info_8086_265a_103c_099c, + &pci_ss_info_8086_265a_1458_265a, + &pci_ss_info_8086_265a_1462_7028, + &pci_ss_info_8086_265a_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265b[] = { + &pci_ss_info_8086_265b_1028_0179, + &pci_ss_info_8086_265b_103c_099c, + &pci_ss_info_8086_265b_1458_265a, + &pci_ss_info_8086_265b_1462_7028, + &pci_ss_info_8086_265b_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265c[] = { + &pci_ss_info_8086_265c_1028_0179, + &pci_ss_info_8086_265c_103c_099c, + &pci_ss_info_8086_265c_1458_5006, + &pci_ss_info_8086_265c_1462_7028, + &pci_ss_info_8086_265c_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2660[] = { + &pci_ss_info_8086_2660_103c_099c, + NULL +}; +#define pci_ss_list_8086_2662 NULL +#define pci_ss_list_8086_2664 NULL +#define pci_ss_list_8086_2666 NULL +#define pci_ss_list_8086_2668 NULL +static const pciSubsystemInfo *pci_ss_list_8086_266a[] = { + &pci_ss_info_8086_266a_1028_0179, + &pci_ss_info_8086_266a_1458_266a, + &pci_ss_info_8086_266a_1462_7028, + &pci_ss_info_8086_266a_1734_105c, + NULL +}; +#define pci_ss_list_8086_266c NULL +static const pciSubsystemInfo *pci_ss_list_8086_266d[] = { + &pci_ss_info_8086_266d_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266e[] = { + &pci_ss_info_8086_266e_1028_0179, + &pci_ss_info_8086_266e_1028_0182, + &pci_ss_info_8086_266e_1028_0188, + &pci_ss_info_8086_266e_103c_099c, + &pci_ss_info_8086_266e_1458_a002, + &pci_ss_info_8086_266e_1734_105a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266f[] = { + &pci_ss_info_8086_266f_103c_099c, + &pci_ss_info_8086_266f_1458_266f, + &pci_ss_info_8086_266f_1462_7028, + &pci_ss_info_8086_266f_1734_105c, + NULL +}; +#define pci_ss_list_8086_2670 NULL +#define pci_ss_list_8086_2680 NULL +#define pci_ss_list_8086_2681 NULL +#define pci_ss_list_8086_2682 NULL +#define pci_ss_list_8086_2683 NULL +#define pci_ss_list_8086_2688 NULL +#define pci_ss_list_8086_2689 NULL +#define pci_ss_list_8086_268a NULL +#define pci_ss_list_8086_268b NULL +#define pci_ss_list_8086_268c NULL +#define pci_ss_list_8086_2690 NULL +#define pci_ss_list_8086_2692 NULL +#define pci_ss_list_8086_2694 NULL +#define pci_ss_list_8086_2696 NULL +#define pci_ss_list_8086_2698 NULL +#define pci_ss_list_8086_2699 NULL +#define pci_ss_list_8086_269a NULL +#define pci_ss_list_8086_269b NULL +#define pci_ss_list_8086_269e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2770[] = { + &pci_ss_info_8086_2770_8086_544e, + NULL +}; +#define pci_ss_list_8086_2771 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2772[] = { + &pci_ss_info_8086_2772_8086_544e, + NULL +}; +#define pci_ss_list_8086_2774 NULL +#define pci_ss_list_8086_2775 NULL +#define pci_ss_list_8086_2776 NULL +#define pci_ss_list_8086_2778 NULL +#define pci_ss_list_8086_2779 NULL +#define pci_ss_list_8086_277a NULL +#define pci_ss_list_8086_277c NULL +#define pci_ss_list_8086_277d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2782[] = { + &pci_ss_info_8086_2782_1734_105b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2792[] = { + &pci_ss_info_8086_2792_103c_099c, + &pci_ss_info_8086_2792_1043_1881, + NULL +}; +#define pci_ss_list_8086_27a0 NULL +#define pci_ss_list_8086_27a1 NULL +#define pci_ss_list_8086_27a2 NULL +#define pci_ss_list_8086_27a6 NULL +#define pci_ss_list_8086_27b0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27b8[] = { + &pci_ss_info_8086_27b8_8086_544e, + NULL +}; +#define pci_ss_list_8086_27b9 NULL +#define pci_ss_list_8086_27bd NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c0[] = { + &pci_ss_info_8086_27c0_8086_544e, + NULL +}; +#define pci_ss_list_8086_27c1 NULL +#define pci_ss_list_8086_27c3 NULL +#define pci_ss_list_8086_27c4 NULL +#define pci_ss_list_8086_27c5 NULL +#define pci_ss_list_8086_27c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c8[] = { + &pci_ss_info_8086_27c8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27c9[] = { + &pci_ss_info_8086_27c9_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27ca[] = { + &pci_ss_info_8086_27ca_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cb[] = { + &pci_ss_info_8086_27cb_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cc[] = { + &pci_ss_info_8086_27cc_8086_544e, + NULL +}; +#define pci_ss_list_8086_27d0 NULL +#define pci_ss_list_8086_27d2 NULL +#define pci_ss_list_8086_27d4 NULL +#define pci_ss_list_8086_27d6 NULL +#define pci_ss_list_8086_27d8 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27da[] = { + &pci_ss_info_8086_27da_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27dc[] = { + &pci_ss_info_8086_27dc_8086_308d, + NULL +}; +#define pci_ss_list_8086_27dd NULL +#define pci_ss_list_8086_27de NULL +static const pciSubsystemInfo *pci_ss_list_8086_27df[] = { + &pci_ss_info_8086_27df_8086_544e, + NULL +}; +#define pci_ss_list_8086_27e0 NULL +#define pci_ss_list_8086_27e2 NULL +#define pci_ss_list_8086_3092 NULL +#define pci_ss_list_8086_3200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3340[] = { + &pci_ss_info_8086_3340_1025_005a, + &pci_ss_info_8086_3340_103c_088c, + &pci_ss_info_8086_3340_103c_0890, + NULL +}; +#define pci_ss_list_8086_3341 NULL +#define pci_ss_list_8086_3500 NULL +#define pci_ss_list_8086_3501 NULL +#define pci_ss_list_8086_3504 NULL +#define pci_ss_list_8086_3505 NULL +#define pci_ss_list_8086_350c NULL +#define pci_ss_list_8086_350d NULL +#define pci_ss_list_8086_3510 NULL +#define pci_ss_list_8086_3511 NULL +#define pci_ss_list_8086_3514 NULL +#define pci_ss_list_8086_3515 NULL +#define pci_ss_list_8086_3518 NULL +#define pci_ss_list_8086_3519 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_0e11_0030, + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3580[] = { + &pci_ss_info_8086_3580_1028_0139, + &pci_ss_info_8086_3580_1028_0163, + &pci_ss_info_8086_3580_1028_0196, + &pci_ss_info_8086_3580_1734_1055, + &pci_ss_info_8086_3580_4c53_10b0, + &pci_ss_info_8086_3580_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3581[] = { + &pci_ss_info_8086_3581_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3582[] = { + &pci_ss_info_8086_3582_1028_0139, + &pci_ss_info_8086_3582_1028_0163, + &pci_ss_info_8086_3582_4c53_10b0, + &pci_ss_info_8086_3582_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3584[] = { + &pci_ss_info_8086_3584_1028_0139, + &pci_ss_info_8086_3584_1028_0163, + &pci_ss_info_8086_3584_1028_0196, + &pci_ss_info_8086_3584_1734_1055, + &pci_ss_info_8086_3584_4c53_10b0, + &pci_ss_info_8086_3584_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3585[] = { + &pci_ss_info_8086_3585_1028_0139, + &pci_ss_info_8086_3585_1028_0163, + &pci_ss_info_8086_3585_1028_0196, + &pci_ss_info_8086_3585_1734_1055, + &pci_ss_info_8086_3585_4c53_10b0, + &pci_ss_info_8086_3585_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3590[] = { + &pci_ss_info_8086_3590_1028_019a, + &pci_ss_info_8086_3590_1734_103e, + &pci_ss_info_8086_3590_4c53_10d0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3591[] = { + &pci_ss_info_8086_3591_1028_0169, + &pci_ss_info_8086_3591_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3592 NULL +#define pci_ss_list_8086_3593 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3594[] = { + &pci_ss_info_8086_3594_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3595 NULL +#define pci_ss_list_8086_3596 NULL +#define pci_ss_list_8086_3597 NULL +#define pci_ss_list_8086_3598 NULL +#define pci_ss_list_8086_3599 NULL +#define pci_ss_list_8086_359a NULL +#define pci_ss_list_8086_359b NULL +static const pciSubsystemInfo *pci_ss_list_8086_359e[] = { + &pci_ss_info_8086_359e_1028_0169, + NULL +}; +#define pci_ss_list_8086_4220 NULL +#define pci_ss_list_8086_4223 NULL +#define pci_ss_list_8086_4224 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7050 NULL +#define pci_ss_list_8086_7051 NULL +#define pci_ss_list_8086_7100 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7110[] = { + &pci_ss_info_8086_7110_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7111[] = { + &pci_ss_info_8086_7111_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7112[] = { + &pci_ss_info_8086_7112_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7113[] = { + &pci_ss_info_8086_7113_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7120[] = { + &pci_ss_info_8086_7120_4c53_1040, + &pci_ss_info_8086_7120_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7121[] = { + &pci_ss_info_8086_7121_4c53_1040, + &pci_ss_info_8086_7121_4c53_1060, + &pci_ss_info_8086_7121_8086_4341, + NULL +}; +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1179_0001, + &pci_ss_info_8086_7190_15ad_1976, + &pci_ss_info_8086_7190_4c53_1050, + &pci_ss_info_8086_7190_4c53_1051, + NULL +}; +#define pci_ss_list_8086_7191 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + &pci_ss_info_8086_7192_4c53_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7194[] = { + &pci_ss_info_8086_7194_1033_0000, + &pci_ss_info_8086_7194_4c53_10a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_1033_80cc, + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a0[] = { + &pci_ss_info_8086_71a0_4c53_1050, + &pci_ss_info_8086_71a0_4c53_1051, + NULL +}; +#define pci_ss_list_8086_71a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a2[] = { + &pci_ss_info_8086_71a2_4c53_1000, + NULL +}; +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +static const pciSubsystemInfo *pci_ss_list_8086_8500[] = { + &pci_ss_info_8086_8500_1993_0ded, + &pci_ss_info_8086_8500_1993_0dee, + &pci_ss_info_8086_8500_1993_0def, + NULL +}; +#define pci_ss_list_8086_9000 NULL +#define pci_ss_list_8086_9001 NULL +#define pci_ss_list_8086_9004 NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_12d9_000a, + &pci_ss_info_8086_b555_4c53_1050, + &pci_ss_info_8086_b555_4c53_1051, + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8c4a_1980 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_0078 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7710 NULL +#define pci_ss_list_9004_7711 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8178[] = { + &pci_ss_info_9004_8178_9004_7881, + NULL +}; +#define pci_ss_list_9004_8278 NULL +#define pci_ss_list_9004_8378 NULL +#define pci_ss_list_9004_8478 NULL +#define pci_ss_list_9004_8578 NULL +#define pci_ss_list_9004_8678 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8778[] = { + &pci_ss_info_9004_8778_9004_7887, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8878[] = { + &pci_ss_info_9004_8878_9004_7888, + NULL +}; +#define pci_ss_list_9004_8b78 NULL +#define pci_ss_list_9004_ec78 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005_0010[] = { + &pci_ss_info_9005_0010_9005_2180, + &pci_ss_info_9005_0010_9005_8100, + &pci_ss_info_9005_0010_9005_a100, + &pci_ss_info_9005_0010_9005_a180, + &pci_ss_info_9005_0010_9005_e100, + NULL +}; +#define pci_ss_list_9005_0011 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0013[] = { + &pci_ss_info_9005_0013_9005_0003, + &pci_ss_info_9005_0013_9005_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_001f[] = { + &pci_ss_info_9005_001f_9005_000f, + &pci_ss_info_9005_001f_9005_a180, + NULL +}; +#define pci_ss_list_9005_0020 NULL +#define pci_ss_list_9005_002f NULL +#define pci_ss_list_9005_0030 NULL +#define pci_ss_list_9005_003f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0050[] = { + &pci_ss_info_9005_0050_9005_f500, + &pci_ss_info_9005_0050_9005_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0051[] = { + &pci_ss_info_9005_0051_9005_b500, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0053[] = { + &pci_ss_info_9005_0053_9005_ffff, + NULL +}; +#define pci_ss_list_9005_005f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0080[] = { + &pci_ss_info_9005_0080_0e11_e2a0, + &pci_ss_info_9005_0080_9005_6220, + &pci_ss_info_9005_0080_9005_62a0, + &pci_ss_info_9005_0080_9005_e220, + &pci_ss_info_9005_0080_9005_e2a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0081[] = { + &pci_ss_info_9005_0081_9005_62a1, + NULL +}; +#define pci_ss_list_9005_0083 NULL +static const pciSubsystemInfo *pci_ss_list_9005_008f[] = { + &pci_ss_info_9005_008f_1179_0001, + &pci_ss_info_9005_008f_15d9_9005, + NULL +}; +#define pci_ss_list_9005_0092 NULL +#define pci_ss_list_9005_0093 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c0[] = { + &pci_ss_info_9005_00c0_0e11_f620, + &pci_ss_info_9005_00c0_9005_f620, + NULL +}; +#define pci_ss_list_9005_00c1 NULL +#define pci_ss_list_9005_00c3 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c5[] = { + &pci_ss_info_9005_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00cf[] = { + &pci_ss_info_9005_00cf_1028_00ce, + &pci_ss_info_9005_00cf_1028_00d1, + &pci_ss_info_9005_00cf_1028_00d9, + &pci_ss_info_9005_00cf_10f1_2462, + &pci_ss_info_9005_00cf_15d9_9005, + &pci_ss_info_9005_00cf_8086_3411, + NULL +}; +#define pci_ss_list_9005_0241 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0250[] = { + &pci_ss_info_9005_0250_1014_0279, + &pci_ss_info_9005_0250_1014_028c, + NULL +}; +#define pci_ss_list_9005_0279 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0283[] = { + &pci_ss_info_9005_0283_9005_0283, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0284[] = { + &pci_ss_info_9005_0284_9005_0284, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0285[] = { + &pci_ss_info_9005_0285_0e11_0295, + &pci_ss_info_9005_0285_1014_02f2, + &pci_ss_info_9005_0285_1028_0287, + &pci_ss_info_9005_0285_1028_0291, + &pci_ss_info_9005_0285_103c_3227, + &pci_ss_info_9005_0285_17aa_0286, + &pci_ss_info_9005_0285_17aa_0287, + &pci_ss_info_9005_0285_9005_0285, + &pci_ss_info_9005_0285_9005_0286, + &pci_ss_info_9005_0285_9005_0287, + &pci_ss_info_9005_0285_9005_0288, + &pci_ss_info_9005_0285_9005_0289, + &pci_ss_info_9005_0285_9005_028a, + &pci_ss_info_9005_0285_9005_028b, + &pci_ss_info_9005_0285_9005_028e, + &pci_ss_info_9005_0285_9005_028f, + &pci_ss_info_9005_0285_9005_0290, + &pci_ss_info_9005_0285_9005_0292, + &pci_ss_info_9005_0285_9005_0293, + &pci_ss_info_9005_0285_9005_0294, + &pci_ss_info_9005_0285_9005_0296, + &pci_ss_info_9005_0285_9005_0297, + &pci_ss_info_9005_0285_9005_0298, + &pci_ss_info_9005_0285_9005_0299, + &pci_ss_info_9005_0285_9005_029a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0286[] = { + &pci_ss_info_9005_0286_1014_9540, + &pci_ss_info_9005_0286_1014_9580, + &pci_ss_info_9005_0286_9005_028c, + &pci_ss_info_9005_0286_9005_028d, + &pci_ss_info_9005_0286_9005_029b, + &pci_ss_info_9005_0286_9005_029c, + &pci_ss_info_9005_0286_9005_029d, + &pci_ss_info_9005_0286_9005_029e, + &pci_ss_info_9005_0286_9005_029f, + &pci_ss_info_9005_0286_9005_02a0, + &pci_ss_info_9005_0286_9005_02a1, + &pci_ss_info_9005_0286_9005_02a2, + &pci_ss_info_9005_0286_9005_02a3, + &pci_ss_info_9005_0286_9005_02a4, + &pci_ss_info_9005_0286_9005_02a5, + &pci_ss_info_9005_0286_9005_02a6, + &pci_ss_info_9005_0286_9005_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0500[] = { + &pci_ss_info_9005_0500_1014_02c1, + &pci_ss_info_9005_0500_1014_02c2, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0503[] = { + &pci_ss_info_9005_0503_1014_02bf, + &pci_ss_info_9005_0503_1014_02d5, + NULL +}; +#define pci_ss_list_9005_0910 NULL +#define pci_ss_list_9005_091e NULL +#define pci_ss_list_9005_8000 NULL +#define pci_ss_list_9005_800f NULL +#define pci_ss_list_9005_8010 NULL +static const pciSubsystemInfo *pci_ss_list_9005_8011[] = { + &pci_ss_info_9005_8011_0e11_00ac, + &pci_ss_info_9005_8011_9005_0041, + NULL +}; +#define pci_ss_list_9005_8012 NULL +#define pci_ss_list_9005_8013 NULL +#define pci_ss_list_9005_8014 NULL +#define pci_ss_list_9005_8015 NULL +#define pci_ss_list_9005_8016 NULL +#define pci_ss_list_9005_8017 NULL +#define pci_ss_list_9005_801c NULL +#define pci_ss_list_9005_801d NULL +#define pci_ss_list_9005_801e NULL +static const pciSubsystemInfo *pci_ss_list_9005_801f[] = { + &pci_ss_info_9005_801f_1734_1011, + NULL +}; +#define pci_ss_list_9005_8080 NULL +#define pci_ss_list_9005_808f NULL +#define pci_ss_list_9005_8090 NULL +#define pci_ss_list_9005_8091 NULL +#define pci_ss_list_9005_8092 NULL +#define pci_ss_list_9005_8093 NULL +#define pci_ss_list_9005_8094 NULL +#define pci_ss_list_9005_8095 NULL +#define pci_ss_list_9005_8096 NULL +#define pci_ss_list_9005_8097 NULL +#define pci_ss_list_9005_809c NULL +#define pci_ss_list_9005_809d NULL +#define pci_ss_list_9005_809e NULL +#define pci_ss_list_9005_809f NULL +#endif +#define pci_ss_list_907f_2015 NULL +#define pci_ss_list_9412_6565 NULL +#define pci_ss_list_9699_6565 NULL +#define pci_ss_list_9710_7780 NULL +#define pci_ss_list_9710_9805 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9710_9815[] = { + &pci_ss_info_9710_9815_1000_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9835[] = { + &pci_ss_info_9710_9835_1000_0002, + &pci_ss_info_9710_9835_1000_0012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9845[] = { + &pci_ss_info_9710_9845_1000_0004, + &pci_ss_info_9710_9845_1000_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9855[] = { + &pci_ss_info_9710_9855_1000_0014, + NULL +}; +#endif +#define pci_ss_list_9902_0001 NULL +#define pci_ss_list_9902_0002 NULL +#define pci_ss_list_9902_0003 NULL +#define pci_ss_list_a727_0013 NULL +#define pci_ss_list_aecb_6250 NULL +#define pci_ss_list_affe_dead NULL +#define pci_ss_list_cafe_0003 NULL +#define pci_ss_list_cddd_0101 NULL +#define pci_ss_list_cddd_0200 NULL +#define pci_ss_list_d161_0205 NULL +#define pci_ss_list_d161_0210 NULL +#define pci_ss_list_d161_0405 NULL +#define pci_ss_list_d161_0410 NULL +#define pci_ss_list_d161_2400 NULL +#define pci_ss_list_d4d4_0601 NULL +#define pci_ss_list_deaf_9050 NULL +#define pci_ss_list_deaf_9051 NULL +#define pci_ss_list_deaf_9052 NULL +#define pci_ss_list_e000_e000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e159_0001[] = { + &pci_ss_info_e159_0001_0059_0001, + &pci_ss_info_e159_0001_0059_0003, + &pci_ss_info_e159_0001_00a7_0001, + &pci_ss_info_e159_0001_6159_0001, + &pci_ss_info_e159_0001_79fe_0001, + &pci_ss_info_e159_0001_8086_0003, + &pci_ss_info_e159_0001_b1b9_0001, + &pci_ss_info_e159_0001_b1b9_0003, + NULL +}; +#define pci_ss_list_e159_0002 NULL +#endif +#define pci_ss_list_ea01_000a NULL +#define pci_ss_list_ea01_0032 NULL +#define pci_ss_list_ea01_003e NULL +#define pci_ss_list_ea01_0041 NULL +#define pci_ss_list_ea01_0043 NULL +#define pci_ss_list_ea01_0046 NULL +#define pci_ss_list_ea01_0052 NULL +#define pci_ss_list_ea01_0800 NULL +#define pci_ss_list_ea60_9896 NULL +#define pci_ss_list_ea60_9897 NULL +#define pci_ss_list_ea60_9898 NULL +#define pci_ss_list_eace_3100 NULL +#define pci_ss_list_eace_3200 NULL +#define pci_ss_list_eace_320e NULL +#define pci_ss_list_eace_340e NULL +#define pci_ss_list_eace_341e NULL +#define pci_ss_list_eace_3500 NULL +#define pci_ss_list_eace_351c NULL +#define pci_ss_list_eace_4100 NULL +#define pci_ss_list_eace_4110 NULL +#define pci_ss_list_eace_4220 NULL +#define pci_ss_list_eace_422e NULL +#define pci_ss_list_ec80_ec00 NULL +#define pci_ss_list_edd8_a091 NULL +#define pci_ss_list_edd8_a099 NULL +#define pci_ss_list_edd8_a0a1 NULL +#define pci_ss_list_edd8_a0a9 NULL +#define pci_ss_list_f1d0_c0fe NULL +#define pci_ss_list_f1d0_c0ff NULL +#define pci_ss_list_f1d0_cafe NULL +#define pci_ss_list_f1d0_cfee NULL +#define pci_ss_list_f1d0_dcaf NULL +#define pci_ss_list_f1d0_dfee NULL +#define pci_ss_list_f1d0_efac NULL +#define pci_ss_list_f1d0_facd NULL +#define pci_ss_list_fa57_0001 NULL +#define pci_ss_list_feda_a0fa NULL +#define pci_ss_list_feda_a10e NULL +#define pci_ss_list_fede_0003 NULL +#define pci_ss_list_fffd_0101 NULL +#define pci_ss_list_fffe_0405 NULL +#define pci_ss_list_fffe_0710 NULL +#ifdef INIT_VENDOR_SUBSYS_INFO +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0000[] = { + &pci_ss_info_0000_0000, + NULL +}; +#endif +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0059[] = { + &pci_ss_info_0059_0001, + &pci_ss_info_0059_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_2801, + &pci_ss_info_0070_3401, + &pci_ss_info_0070_4000, + &pci_ss_info_0070_4001, + &pci_ss_info_0070_4009, + &pci_ss_info_0070_8003, + &pci_ss_info_0070_9002, + &pci_ss_info_0070_ff01, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0071[] = { + &pci_ss_info_0071_0101, + NULL +}; +#endif +#define pci_ss_list_0095 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_00a7[] = { + &pci_ss_info_00a7_0001, + NULL +}; +#endif +#define pci_ss_list_0100 NULL +#define pci_ss_list_018a NULL +#define pci_ss_list_021b NULL +#define pci_ss_list_0270 NULL +#define pci_ss_list_0291 NULL +#define pci_ss_list_02ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0357[] = { + &pci_ss_info_0357_000a, + NULL +}; +#endif +#define pci_ss_list_0432 NULL +#define pci_ss_list_045e NULL +#define pci_ss_list_04cf NULL +#define pci_ss_list_05e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0675[] = { + &pci_ss_info_0675_1704, + &pci_ss_info_0675_1707, + &pci_ss_info_0675_1708, + NULL +}; +#endif +#define pci_ss_list_067b NULL +#define pci_ss_list_0721 NULL +#define pci_ss_list_07e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +#define pci_ss_list_0b49 NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0030, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_004e, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0097, + &pci_ss_info_0e11_0098, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00ac, + &pci_ss_info_0e11_00b8, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_00da, + &pci_ss_info_0e11_00db, + &pci_ss_info_0e11_00dc, + &pci_ss_info_0e11_00e3, + &pci_ss_info_0e11_0295, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_4080, + &pci_ss_info_0e11_4082, + &pci_ss_info_0e11_4083, + &pci_ss_info_0e11_409a, + &pci_ss_info_0e11_409b, + &pci_ss_info_0e11_409c, + &pci_ss_info_0e11_409d, + &pci_ss_info_0e11_6004, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e7, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b121, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b160, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + &pci_ss_info_0e11_e2a0, + &pci_ss_info_0e11_f620, + NULL +}; +#define pci_ss_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_0001, + &pci_ss_info_1000_0002, + &pci_ss_info_1000_0004, + &pci_ss_info_1000_0006, + &pci_ss_info_1000_0012, + &pci_ss_info_1000_0014, + &pci_ss_info_1000_0020, + &pci_ss_info_1000_0033, + &pci_ss_info_1000_0066, + &pci_ss_info_1000_0518, + &pci_ss_info_1000_0520, + &pci_ss_info_1000_0522, + &pci_ss_info_1000_0523, + &pci_ss_info_1000_0530, + &pci_ss_info_1000_0531, + &pci_ss_info_1000_0532, + &pci_ss_info_1000_1000, + &pci_ss_info_1000_1010, + &pci_ss_info_1000_1020, + &pci_ss_info_1000_3004, + &pci_ss_info_1000_3008, + &pci_ss_info_1000_4523, + &pci_ss_info_1000_a520, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_00f8, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_0b12, + &pci_ss_info_1002_0b13, + &pci_ss_info_1002_103a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_2f72, + &pci_ss_info_1002_4336, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4772, + &pci_ss_info_1002_4773, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_4e71, + &pci_ss_info_1002_515e, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_5954, + &pci_ss_info_1002_5955, + &pci_ss_info_1002_5965, + &pci_ss_info_1002_5c63, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1005[] = { + &pci_ss_info_1005_127a, + NULL +}; +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + &pci_ss_info_1013_5959, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_0031, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0092, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0104, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0130, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020c, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021a, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0241, + &pci_ss_info_1014_0242, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0251, + &pci_ss_info_1014_0252, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0264, + &pci_ss_info_1014_0265, + &pci_ss_info_1014_0266, + &pci_ss_info_1014_0267, + &pci_ss_info_1014_0268, + &pci_ss_info_1014_0269, + &pci_ss_info_1014_026a, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0278, + &pci_ss_info_1014_0279, + &pci_ss_info_1014_027c, + &pci_ss_info_1014_028c, + &pci_ss_info_1014_028d, + &pci_ss_info_1014_028e, + &pci_ss_info_1014_02be, + &pci_ss_info_1014_02bf, + &pci_ss_info_1014_02c0, + &pci_ss_info_1014_02c1, + &pci_ss_info_1014_02c2, + &pci_ss_info_1014_02d3, + &pci_ss_info_1014_02d4, + &pci_ss_info_1014_02d5, + &pci_ss_info_1014_02f2, + &pci_ss_info_1014_030d, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_050f, + &pci_ss_info_1014_0510, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_0528, + &pci_ss_info_1014_052c, + &pci_ss_info_1014_0535, + &pci_ss_info_1014_053a, + &pci_ss_info_1014_053b, + &pci_ss_info_1014_053c, + &pci_ss_info_1014_053d, + &pci_ss_info_1014_053e, + &pci_ss_info_1014_0540, + &pci_ss_info_1014_0545, + &pci_ss_info_1014_0549, + &pci_ss_info_1014_0556, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_1025, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9540, + &pci_ss_info_1014_9580, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_0985, + &pci_ss_info_1019_0987, + &pci_ss_info_1019_0a14, + &pci_ss_info_1019_0a81, + &pci_ss_info_1019_0f38, + &pci_ss_info_1019_4c30, + &pci_ss_info_1019_4cb4, + &pci_ss_info_1019_4cb5, + &pci_ss_info_1019_7018, + &pci_ss_info_1019_8001, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0477, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0494, + &pci_ss_info_101e_0503, + &pci_ss_info_101e_0511, + &pci_ss_info_101e_0522, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101f[] = { + &pci_ss_info_101f_1025, + NULL +}; +#endif +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +static const pciSubsystemInfo *pci_ss_list_1022[] = { + &pci_ss_info_1022_2000, + &pci_ss_info_1022_2b80, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1024[] = { + &pci_ss_info_1024_0134, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_004d, + &pci_ss_info_1025_005a, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_002e, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00aa, + &pci_ss_info_1028_00b1, + &pci_ss_info_1028_00bb, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00ce, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_00fe, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_010e, + &pci_ss_info_1028_011c, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0123, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_012a, + &pci_ss_info_1028_0134, + &pci_ss_info_1028_0139, + &pci_ss_info_1028_014a, + &pci_ss_info_1028_014e, + &pci_ss_info_1028_0151, + &pci_ss_info_1028_0163, + &pci_ss_info_1028_0165, + &pci_ss_info_1028_0169, + &pci_ss_info_1028_016c, + &pci_ss_info_1028_016d, + &pci_ss_info_1028_016e, + &pci_ss_info_1028_016f, + &pci_ss_info_1028_0170, + &pci_ss_info_1028_0179, + &pci_ss_info_1028_0182, + &pci_ss_info_1028_0183, + &pci_ss_info_1028_0188, + &pci_ss_info_1028_0196, + &pci_ss_info_1028_019a, + &pci_ss_info_1028_019d, + &pci_ss_info_1028_01a2, + &pci_ss_info_1028_01ad, + &pci_ss_info_1028_0287, + &pci_ss_info_1028_0291, + &pci_ss_info_1028_0407, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_0533, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1079, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_4134, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_865d, + &pci_ss_info_1028_c082, + &pci_ss_info_1028_c134, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0850, + &pci_ss_info_102b_08c7, + &pci_ss_info_102b_0907, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0d43, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1020, + &pci_ss_info_102b_1030, + &pci_ss_info_102b_1047, + &pci_ss_info_102b_1087, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_14e1, + &pci_ss_info_102b_1820, + &pci_ss_info_102b_1830, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1c10, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2021, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2538, + &pci_ss_info_102b_2811, + &pci_ss_info_102b_2c11, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3007, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48d0, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_0000, + &pci_ss_info_1033_0035, + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80a8, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + &pci_ss_info_1033_80cc, + &pci_ss_info_1033_80cd, + &pci_ss_info_1033_80e5, + &pci_ss_info_1033_8110, + &pci_ss_info_1033_8112, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_6330, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_0024, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_0850, + &pci_ss_info_103c_088c, + &pci_ss_info_103c_0890, + &pci_ss_info_103c_099c, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_10eb, + &pci_ss_info_103c_10ec, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + &pci_ss_info_103c_128a, + &pci_ss_info_103c_128b, + &pci_ss_info_103c_12a4, + &pci_ss_info_103c_12a6, + &pci_ss_info_103c_12a8, + &pci_ss_info_103c_12bc, + &pci_ss_info_103c_12c1, + &pci_ss_info_103c_12c3, + &pci_ss_info_103c_12ca, + &pci_ss_info_103c_12cf, + &pci_ss_info_103c_12d5, + &pci_ss_info_103c_12fa, + &pci_ss_info_103c_1300, + &pci_ss_info_103c_1301, + &pci_ss_info_103c_1356, + &pci_ss_info_103c_2a0d, + &pci_ss_info_103c_308b, + &pci_ss_info_103c_3100, + &pci_ss_info_103c_3101, + &pci_ss_info_103c_3102, + &pci_ss_info_103c_3103, + &pci_ss_info_103c_3226, + &pci_ss_info_103c_3227, + &pci_ss_info_103c_60e7, + &pci_ss_info_103c_7031, + &pci_ss_info_103c_7032, + &pci_ss_info_103c_7039, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_002a, + &pci_ss_info_1043_0120, + &pci_ss_info_1043_0127, + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0210, + &pci_ss_info_1043_032e, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_100f, + &pci_ss_info_1043_1106, + &pci_ss_info_1043_130f, + &pci_ss_info_1043_1702, + &pci_ss_info_1043_1703, + &pci_ss_info_1043_1707, + &pci_ss_info_1043_173c, + &pci_ss_info_1043_1881, + &pci_ss_info_1043_1967, + &pci_ss_info_1043_1987, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_4823, + &pci_ss_info_1043_4840, + &pci_ss_info_1043_4842, + &pci_ss_info_1043_4843, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8023, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_802c, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_8035, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_806f, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807e, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_8080, + &pci_ss_info_1043_808a, + &pci_ss_info_1043_808b, + &pci_ss_info_1043_808c, + &pci_ss_info_1043_808d, + &pci_ss_info_1043_8095, + &pci_ss_info_1043_809e, + &pci_ss_info_1043_80a1, + &pci_ss_info_1043_80a3, + &pci_ss_info_1043_80a5, + &pci_ss_info_1043_80a6, + &pci_ss_info_1043_80a7, + &pci_ss_info_1043_80a8, + &pci_ss_info_1043_80ab, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80b0, + &pci_ss_info_1043_80e2, + &pci_ss_info_1043_80eb, + &pci_ss_info_1043_80ed, + &pci_ss_info_1043_80f2, + &pci_ss_info_1043_80f3, + &pci_ss_info_1043_80f5, + &pci_ss_info_1043_8109, + &pci_ss_info_1043_810f, + &pci_ss_info_1043_811a, + &pci_ss_info_1043_812a, + &pci_ss_info_1043_8134, + &pci_ss_info_1043_8141, + &pci_ss_info_1043_8142, + &pci_ss_info_1043_8145, + &pci_ss_info_1043_814a, + &pci_ss_info_1043_815a, + &pci_ss_info_1043_817b, + &pci_ss_info_1043_81a6, + &pci_ss_info_1043_c002, + &pci_ss_info_1043_c003, + &pci_ss_info_1043_c004, + &pci_ss_info_1043_c005, + &pci_ss_info_1043_c006, + &pci_ss_info_1043_c01a, + &pci_ss_info_1043_c01b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c032, + &pci_ss_info_1044_c035, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0935, + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a34, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0a36, + &pci_ss_info_1048_0a42, + &pci_ss_info_1048_0a43, + &pci_ss_info_1048_0a44, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c19, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c1c, + &pci_ss_info_1048_0c20, + &pci_ss_info_1048_0c21, + &pci_ss_info_1048_0c28, + &pci_ss_info_1048_0c29, + &pci_ss_info_1048_0c2a, + &pci_ss_info_1048_0c2b, + &pci_ss_info_1048_0c2e, + &pci_ss_info_1048_0c2f, + &pci_ss_info_1048_0c30, + &pci_ss_info_1048_0c31, + &pci_ss_info_1048_0c32, + &pci_ss_info_1048_0c33, + &pci_ss_info_1048_0c34, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c3b, + &pci_ss_info_1048_0c40, + &pci_ss_info_1048_0c41, + &pci_ss_info_1048_0c42, + &pci_ss_info_1048_0c43, + &pci_ss_info_1048_0c44, + &pci_ss_info_1048_0c45, + &pci_ss_info_1048_0c48, + &pci_ss_info_1048_0c4a, + &pci_ss_info_1048_0c4b, + &pci_ss_info_1048_0c50, + &pci_ss_info_1048_0c52, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_0c60, + &pci_ss_info_1048_0c61, + &pci_ss_info_1048_0c63, + &pci_ss_info_1048_0c64, + &pci_ss_info_1048_0c65, + &pci_ss_info_1048_0c66, + &pci_ss_info_1048_0c70, + &pci_ss_info_1048_1500, + &pci_ss_info_1048_226b, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +#define pci_ss_list_104a NULL +#define pci_ss_list_104b NULL +static const pciSubsystemInfo *pci_ss_list_104c[] = { + &pci_ss_info_104c_9066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_810f, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + &pci_ss_info_1057_7025, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_1275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105b[] = { + &pci_ss_info_105b_0c19, + NULL +}; +#endif +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_0037, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + &pci_ss_info_1069_0030, + &pci_ss_info_1069_0040, + &pci_ss_info_1069_0050, + &pci_ss_info_1069_0052, + &pci_ss_info_1069_0054, + &pci_ss_info_1069_0072, + &pci_ss_info_1069_0200, + &pci_ss_info_1069_0202, + &pci_ss_info_1069_0204, + &pci_ss_info_1069_0206, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b[] = { + &pci_ss_info_106b_004e, + &pci_ss_info_106b_5811, + NULL +}; +#endif +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1071[] = { + &pci_ss_info_1071_7150, + &pci_ss_info_1071_8160, + NULL +}; +#endif +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + &pci_ss_info_1077_0002, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1079[] = { + &pci_ss_info_1079_891f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_3015, + &pci_ss_info_107b_4009, + &pci_ss_info_107b_5350, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + &pci_ss_info_107b_8920, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2134, + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2822, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2842, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + &pci_ss_info_107d_6613, + &pci_ss_info_107d_6620, + &pci_ss_info_107d_663c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_108e[] = { + &pci_ss_info_108e_10cf, + NULL +}; +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_00b8, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + &pci_ss_info_1095_10cf, + &pci_ss_info_1095_3112, + &pci_ss_info_1095_3114, + &pci_ss_info_1095_3124, + &pci_ss_info_1095_3512, + &pci_ss_info_1095_3680, + &pci_ss_info_1095_6112, + &pci_ss_info_1095_6114, + &pci_ss_info_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + &pci_ss_info_109f_3197, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9[] = { + &pci_ss_info_10a9_8002, + &pci_ss_info_10a9_8010, + &pci_ss_info_10a9_8011, + &pci_ss_info_10a9_8012, + NULL +}; +#endif +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + &pci_ss_info_10b0_0002, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_1067, + &pci_ss_info_10b5_1172, + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2221, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2431, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_2696, + &pci_ss_info_10b5_2717, + &pci_ss_info_10b5_2844, + &pci_ss_info_10b5_2862, + &pci_ss_info_10b5_2905, + &pci_ss_info_10b5_2906, + &pci_ss_info_10b5_2940, + &pci_ss_info_10b5_2977, + &pci_ss_info_10b5_2978, + &pci_ss_info_10b5_2979, + &pci_ss_info_10b5_3025, + &pci_ss_info_10b5_3068, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_0010, + &pci_ss_info_10b7_0020, + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2031, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_2635, + &pci_ss_info_10b8_2802, + &pci_ss_info_10b8_2835, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + &pci_ss_info_10b8_a835, + &pci_ss_info_10b8_b452, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_5451, + &pci_ss_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105e, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_0008, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + &pci_ss_info_10de_006b, + &pci_ss_info_10de_0091, + &pci_ss_info_10de_00a1, + &pci_ss_info_10de_0179, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + &pci_ss_info_10e1_10cf, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + &pci_ss_info_10f1_2466, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + &pci_ss_info_10f7_8338, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fc[] = { + &pci_ss_info_10fc_d003, + &pci_ss_info_10fc_d035, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fd[] = { + &pci_ss_info_10fd_a430, + NULL +}; +#endif +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0007, + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_0058, + &pci_ss_info_1102_1001, + &pci_ss_info_1102_1002, + &pci_ss_info_1102_1006, + &pci_ss_info_1102_1007, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_2002, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + &pci_ss_info_1102_8064, + &pci_ss_info_1102_8065, + &pci_ss_info_1102_8067, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0003, + &pci_ss_info_1103_0004, + &pci_ss_info_1103_0005, + &pci_ss_info_1103_0006, + &pci_ss_info_1103_0007, + &pci_ss_info_1103_0008, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105[] = { + &pci_ss_info_1105_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_3059, + &pci_ss_info_1106_3227, + &pci_ss_info_1106_4161, + &pci_ss_info_1106_4511, + NULL +}; +#endif +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0000, + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0021, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_0051, + &pci_ss_info_110a_008b, + &pci_ss_info_110a_5938, + &pci_ss_info_110a_8005, + &pci_ss_info_110a_ffff, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_2242, + &pci_ss_info_1113_4203, + &pci_ss_info_1113_9211, + &pci_ss_info_1113_d301, + &pci_ss_info_1113_ec01, + &pci_ss_info_1113_ee03, + &pci_ss_info_1113_ee08, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131[] = { + &pci_ss_info_1131_2001, + &pci_ss_info_1131_2005, + &pci_ss_info_1131_4e85, + &pci_ss_info_1131_4f56, + &pci_ss_info_1131_4f60, + &pci_ss_info_1131_4f61, + &pci_ss_info_1131_5f61, + &pci_ss_info_1131_6752, + &pci_ss_info_1131_7133, + NULL +}; +#endif +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_1300, + &pci_ss_info_1133_1800, + &pci_ss_info_1133_1c01, + &pci_ss_info_1133_1c02, + &pci_ss_info_1133_1c03, + &pci_ss_info_1133_1c04, + &pci_ss_info_1133_1c05, + &pci_ss_info_1133_1c06, + &pci_ss_info_1133_1c07, + &pci_ss_info_1133_1c08, + &pci_ss_info_1133_1c09, + &pci_ss_info_1133_1c0a, + &pci_ss_info_1133_1c0b, + &pci_ss_info_1133_1c0c, + &pci_ss_info_1133_2400, + &pci_ss_info_1133_2800, + &pci_ss_info_1133_e013, + &pci_ss_info_1133_e015, + &pci_ss_info_1133_e017, + &pci_ss_info_1133_e018, + &pci_ss_info_1133_e019, + &pci_ss_info_1133_e01b, + &pci_ss_info_1133_e024, + &pci_ss_info_1133_e028, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_0121, + &pci_ss_info_1148_0221, + &pci_ss_info_1148_0321, + &pci_ss_info_1148_0421, + &pci_ss_info_1148_0621, + &pci_ss_info_1148_0721, + &pci_ss_info_1148_0821, + &pci_ss_info_1148_0921, + &pci_ss_info_1148_1121, + &pci_ss_info_1148_1221, + &pci_ss_info_1148_2100, + &pci_ss_info_1148_21d0, + &pci_ss_info_1148_2200, + &pci_ss_info_1148_3221, + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_8100, + &pci_ss_info_1148_8200, + &pci_ss_info_1148_9100, + &pci_ss_info_1148_9200, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#define pci_ss_list_1154 NULL +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + &pci_ss_info_1179_ff01, + &pci_ss_info_1179_ff10, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c[] = { + &pci_ss_info_117c_8013, + &pci_ss_info_117c_8014, + NULL +}; +#endif +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1303, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_1403, + &pci_ss_info_1186_3202, + &pci_ss_info_1186_3203, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_3700, + &pci_ss_info_1186_3a12, + &pci_ss_info_1186_3a13, + &pci_ss_info_1186_3a14, + &pci_ss_info_1186_3a15, + &pci_ss_info_1186_3a16, + &pci_ss_info_1186_3a17, + &pci_ss_info_1186_3a18, + &pci_ss_info_1186_3a19, + &pci_ss_info_1186_3a22, + &pci_ss_info_1186_3a23, + &pci_ss_info_1186_3a24, + &pci_ss_info_1186_3a63, + &pci_ss_info_1186_3a94, + &pci_ss_info_1186_3b00, + &pci_ss_info_1186_3b01, + &pci_ss_info_1186_3b04, + &pci_ss_info_1186_3b05, + &pci_ss_info_1186_4c00, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#define pci_ss_list_1195 NULL +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab[] = { + &pci_ss_info_11ab_0121, + &pci_ss_info_11ab_0321, + &pci_ss_info_11ab_1021, + &pci_ss_info_11ab_3521, + &pci_ss_info_11ab_3621, + &pci_ss_info_11ab_5021, + &pci_ss_info_11ab_5221, + &pci_ss_info_11ab_5321, + &pci_ss_info_11ab_9521, + NULL +}; +#endif +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_000f, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + &pci_ss_info_11bd_002b, + &pci_ss_info_11bd_002d, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + &pci_ss_info_11c1_ab12, + &pci_ss_info_11c1_ab13, + &pci_ss_info_11c1_ab15, + &pci_ss_info_11c1_ab16, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0057, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_1400, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + &pci_ss_info_1244_0f00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_1070, + &pci_ss_info_124b_1170, + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2702, + &pci_ss_info_1259_2703, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2971, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2973, + &pci_ss_info_1259_2974, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2976, + &pci_ss_info_1259_2977, + &pci_ss_info_1259_c104, + &pci_ss_info_1259_c107, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#define pci_ss_list_1260 NULL +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + &pci_ss_info_1274_8001, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127d[] = { + &pci_ss_info_127d_0000, + NULL +}; +#endif +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283[] = { + &pci_ss_info_1283_0001, + NULL +}; +#endif +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1297[] = { + &pci_ss_info_1297_c160, + &pci_ss_info_1297_c240, + &pci_ss_info_1297_c241, + &pci_ss_info_1297_c242, + &pci_ss_info_1297_c243, + &pci_ss_info_1297_c244, + &pci_ss_info_1297_f641, + NULL +}; +#endif +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ab[] = { + &pci_ss_info_12ab_5961, + NULL +}; +#endif +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#define pci_ss_list_12c4 NULL +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c7[] = { + &pci_ss_info_12c7_4001, + NULL +}; +#endif +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_0002, + &pci_ss_info_12d9_000a, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12df[] = { + &pci_ss_info_12df_4422, + NULL +}; +#endif +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12f8[] = { + &pci_ss_info_12f8_8a02, + NULL +}; +#endif +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317[] = { + &pci_ss_info_1317_8201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319[] = { + &pci_ss_info_1319_1319, + NULL +}; +#endif +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + &pci_ss_info_131f_2050, + &pci_ss_info_131f_2051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#define pci_ss_list_1351 NULL +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_001e, + &pci_ss_info_1371_001f, + &pci_ss_info_1371_0020, + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_4105, + &pci_ss_info_1385_4800, + &pci_ss_info_1385_4d00, + &pci_ss_info_1385_4e00, + &pci_ss_info_1385_f004, + &pci_ss_info_1385_f311, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + &pci_ss_info_1397_3136, + &pci_ss_info_1397_3137, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13b9[] = { + &pci_ss_info_13b9_1421, + NULL +}; +#endif +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13bd[] = { + &pci_ss_info_13bd_100c, + &pci_ss_info_13bd_100d, + &pci_ss_info_13bd_100e, + &pci_ss_info_13bd_1019, + &pci_ss_info_13bd_f6f1, + NULL +}; +#endif +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1[] = { + &pci_ss_info_13c1_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c2[] = { + &pci_ss_info_13c2_0000, + &pci_ss_info_13c2_0001, + &pci_ss_info_13c2_0002, + &pci_ss_info_13c2_0003, + &pci_ss_info_13c2_0004, + &pci_ss_info_13c2_0006, + &pci_ss_info_13c2_0008, + &pci_ss_info_13c2_000a, + &pci_ss_info_13c2_1003, + &pci_ss_info_13c2_1004, + &pci_ss_info_13c2_1005, + &pci_ss_info_13c2_100c, + &pci_ss_info_13c2_100f, + &pci_ss_info_13c2_1011, + &pci_ss_info_13c2_1013, + &pci_ss_info_13c2_1102, + NULL +}; +#endif +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + &pci_ss_info_13d1_aba0, + &pci_ss_info_13d1_ac11, + &pci_ss_info_13d1_ac12, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + &pci_ss_info_13e9_1000, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412[] = { + &pci_ss_info_1412_1712, + &pci_ss_info_1412_1724, + &pci_ss_info_1412_3630, + &pci_ss_info_1412_3631, + &pci_ss_info_1412_d630, + &pci_ss_info_1412_d631, + &pci_ss_info_1412_d632, + &pci_ss_info_1412_d633, + &pci_ss_info_1412_d634, + &pci_ss_info_1412_d635, + &pci_ss_info_1412_d637, + &pci_ss_info_1412_d638, + &pci_ss_info_1412_d63b, + &pci_ss_info_1412_d63c, + NULL +}; +#endif +#define pci_ss_list_1413 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1414[] = { + &pci_ss_info_1414_0003, + &pci_ss_info_1414_0004, + NULL +}; +#endif +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_1712, + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1421[] = { + &pci_ss_info_1421_0350, + &pci_ss_info_1421_0370, + NULL +}; +#endif +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#define pci_ss_list_1435 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_1702, + &pci_ss_info_144f_1703, + &pci_ss_info_144f_1707, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_0c11, + &pci_ss_info_1458_1000, + &pci_ss_info_1458_1019, + &pci_ss_info_1458_24c2, + &pci_ss_info_1458_24d1, + &pci_ss_info_1458_24d2, + &pci_ss_info_1458_2558, + &pci_ss_info_1458_2560, + &pci_ss_info_1458_2570, + &pci_ss_info_1458_2578, + &pci_ss_info_1458_2580, + &pci_ss_info_1458_2582, + &pci_ss_info_1458_2659, + &pci_ss_info_1458_265a, + &pci_ss_info_1458_266a, + &pci_ss_info_1458_266f, + &pci_ss_info_1458_3124, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_4018, + &pci_ss_info_1458_4019, + &pci_ss_info_1458_4024, + &pci_ss_info_1458_4025, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_5006, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + &pci_ss_info_1458_b001, + &pci_ss_info_1458_b003, + &pci_ss_info_1458_d000, + &pci_ss_info_1458_e000, + &pci_ss_info_1458_e381, + &pci_ss_info_1458_e911, + &pci_ss_info_1458_e931, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0002, + &pci_ss_info_1461_0003, + &pci_ss_info_1461_0004, + &pci_ss_info_1461_000b, + &pci_ss_info_1461_050c, + &pci_ss_info_1461_0761, + &pci_ss_info_1461_10ff, + &pci_ss_info_1461_2108, + &pci_ss_info_1461_2115, + &pci_ss_info_1461_2c00, + &pci_ss_info_1461_2c05, + &pci_ss_info_1461_a3cf, + &pci_ss_info_1461_a70a, + &pci_ss_info_1461_a70b, + &pci_ss_info_1461_d6ee, + &pci_ss_info_1461_f31f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_0080, + &pci_ss_info_1462_052c, + &pci_ss_info_1462_058c, + &pci_ss_info_1462_1009, + &pci_ss_info_1462_3091, + &pci_ss_info_1462_309e, + &pci_ss_info_1462_3300, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3800, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5470, + &pci_ss_info_1462_5506, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6828, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6835, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_7020, + &pci_ss_info_1462_7028, + &pci_ss_info_1462_702c, + &pci_ss_info_1462_702d, + &pci_ss_info_1462_702e, + &pci_ss_info_1462_7100, + &pci_ss_info_1462_7280, + &pci_ss_info_1462_728c, + &pci_ss_info_1462_7580, + &pci_ss_info_1462_758c, + &pci_ss_info_1462_8606, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + &pci_ss_info_1462_8852, + &pci_ss_info_1462_8880, + &pci_ss_info_1462_8900, + &pci_ss_info_1462_9171, + &pci_ss_info_1462_9350, + &pci_ss_info_1462_9360, + &pci_ss_info_1462_971d, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0202, + &pci_ss_info_1468_0311, + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_0450, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#define pci_ss_list_1471 NULL +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_1406, + &pci_ss_info_147b_1407, + &pci_ss_info_147b_1408, + &pci_ss_info_147b_1c0b, + &pci_ss_info_147b_6191, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_8f0d, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_0214, + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + &pci_ss_info_148c_2064, + &pci_ss_info_148c_2066, + &pci_ss_info_148c_2067, + &pci_ss_info_148c_2073, + &pci_ss_info_148c_2116, + &pci_ss_info_148c_2117, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1498[] = { + &pci_ss_info_1498_0362, + NULL +}; +#endif +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14b7[] = { + &pci_ss_info_14b7_0a60, + NULL +}; +#endif +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + &pci_ss_info_14c0_0012, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c2[] = { + &pci_ss_info_14c2_0105, + &pci_ss_info_14c2_0205, + NULL +}; +#endif +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c7[] = { + &pci_ss_info_14c7_0107, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cb[] = { + &pci_ss_info_14cb_0100, + &pci_ss_info_14cb_0200, + NULL +}; +#endif +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2012, + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_0449, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_4318, + &pci_ss_info_14e4_4320, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ef[] = { + &pci_ss_info_14ef_0220, + NULL +}; +#endif +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0187, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0342, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_2045, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fb[] = { + &pci_ss_info_14fb_0101, + &pci_ss_info_14fb_0102, + &pci_ss_info_14fb_0202, + &pci_ss_info_14fb_0611, + &pci_ss_info_14fb_0612, + &pci_ss_info_14fb_0613, + &pci_ss_info_14fb_0614, + &pci_ss_info_14fb_0621, + &pci_ss_info_14fb_0622, + &pci_ss_info_14fb_0810, + NULL +}; +#endif +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_0e70, + &pci_ss_info_14ff_1100, + &pci_ss_info_14ff_c401, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_1930, + &pci_ss_info_1509_1968, + &pci_ss_info_1509_2990, + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#define pci_ss_list_1517 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1518[] = { + &pci_ss_info_1518_0200, + NULL +}; +#endif +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + &pci_ss_info_1522_0c00, + &pci_ss_info_1522_0d00, + &pci_ss_info_1522_1d00, + &pci_ss_info_1522_2000, + &pci_ss_info_1522_2100, + &pci_ss_info_1522_2200, + &pci_ss_info_1522_2300, + &pci_ss_info_1522_2400, + &pci_ss_info_1522_2500, + &pci_ss_info_1522_2600, + &pci_ss_info_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_153b[] = { + &pci_ss_info_153b_1115, + &pci_ss_info_153b_111b, + &pci_ss_info_153b_1125, + &pci_ss_info_153b_112b, + &pci_ss_info_153b_112c, + &pci_ss_info_153b_1130, + &pci_ss_info_153b_1136, + &pci_ss_info_153b_1138, + &pci_ss_info_153b_1142, + &pci_ss_info_153b_1143, + &pci_ss_info_153b_1145, + &pci_ss_info_153b_1147, + &pci_ss_info_153b_1151, + &pci_ss_info_153b_1152, + &pci_ss_info_153b_1153, + &pci_ss_info_153b_1158, + &pci_ss_info_153b_1162, + NULL +}; +#endif +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1540[] = { + &pci_ss_info_1540_2580, + &pci_ss_info_1540_9524, + NULL +}; +#endif +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + &pci_ss_info_1554_4811, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_04a0, + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_002d, + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_156d[] = { + &pci_ss_info_156d_b400, + &pci_ss_info_156d_b550, + &pci_ss_info_156d_b560, + &pci_ss_info_156d_b700, + &pci_ss_info_156d_b795, + &pci_ss_info_156d_b797, + NULL +}; +#endif +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +static const pciSubsystemInfo *pci_ss_list_15ad[] = { + &pci_ss_info_15ad_1976, + NULL +}; +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15bd[] = { + &pci_ss_info_15bd_1003, + NULL +}; +#endif +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d4[] = { + &pci_ss_info_15d4_0047, + NULL +}; +#endif +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_4580, + &pci_ss_info_15d9_9005, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#define pci_ss_list_1601 NULL +#define pci_ss_list_1602 NULL +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#define pci_ss_list_1612 NULL +#define pci_ss_list_1619 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_161f[] = { + &pci_ss_info_161f_2029, + &pci_ss_info_161f_203c, + &pci_ss_info_161f_203d, + &pci_ss_info_161f_3017, + NULL +}; +#endif +#define pci_ss_list_1626 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1637 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_165f NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#define pci_ss_list_166d NULL +#define pci_ss_list_1677 NULL +#define pci_ss_list_167b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0002, + &pci_ss_info_1681_0003, + &pci_ss_info_1681_0010, + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a000, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1682[] = { + &pci_ss_info_1682_211c, + &pci_ss_info_1682_2120, + NULL +}; +#endif +#define pci_ss_list_1688 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c[] = { + &pci_ss_info_168c_0013, + &pci_ss_info_168c_1025, + &pci_ss_info_168c_1027, + &pci_ss_info_168c_1052, + &pci_ss_info_168c_2026, + &pci_ss_info_168c_2041, + &pci_ss_info_168c_2042, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1695[] = { + &pci_ss_info_1695_3005, + &pci_ss_info_1695_300c, + &pci_ss_info_1695_9025, + &pci_ss_info_1695_9029, + NULL +}; +#endif +#define pci_ss_list_169c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16a5[] = { + &pci_ss_info_16a5_1601, + &pci_ss_info_16a5_1605, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ab[] = { + &pci_ss_info_16ab_7302, + &pci_ss_info_16ab_8501, + NULL +}; +#endif +#define pci_ss_list_16ae NULL +#define pci_ss_list_16af NULL +#define pci_ss_list_16b4 NULL +#define pci_ss_list_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_0003, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16c8 NULL +#define pci_ss_list_16ca NULL +#define pci_ss_list_16cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ce[] = { + &pci_ss_info_16ce_1040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16df[] = { + &pci_ss_info_16df_0011, + &pci_ss_info_16df_0012, + &pci_ss_info_16df_0013, + &pci_ss_info_16df_0014, + &pci_ss_info_16df_0015, + &pci_ss_info_16df_0016, + NULL +}; +#endif +#define pci_ss_list_16e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ec[] = { + &pci_ss_info_16ec_0119, + NULL +}; +#endif +#define pci_ss_list_16ed NULL +#define pci_ss_list_16f3 NULL +#define pci_ss_list_16f4 NULL +#define pci_ss_list_16f6 NULL +#define pci_ss_list_1702 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#define pci_ss_list_1725 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1734[] = { + &pci_ss_info_1734_007a, + &pci_ss_info_1734_100b, + &pci_ss_info_1734_1011, + &pci_ss_info_1734_1012, + &pci_ss_info_1734_101c, + &pci_ss_info_1734_1025, + &pci_ss_info_1734_103e, + &pci_ss_info_1734_1052, + &pci_ss_info_1734_1055, + &pci_ss_info_1734_105a, + &pci_ss_info_1734_105b, + &pci_ss_info_1734_105c, + &pci_ss_info_1734_105d, + &pci_ss_info_1734_1061, + &pci_ss_info_1734_1065, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_0015, + &pci_ss_info_1737_0016, + &pci_ss_info_1737_0024, + &pci_ss_info_1737_0032, + &pci_ss_info_1737_3874, + &pci_ss_info_1737_4320, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#define pci_ss_list_1749 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7146, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + &pci_ss_info_174b_7c12, + &pci_ss_info_174b_7c13, + &pci_ss_info_174b_7c19, + &pci_ss_info_174b_7c28, + &pci_ss_info_174b_7c29, + NULL +}; +#endif +#define pci_ss_list_174d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_175c[] = { + &pci_ss_info_175c_4200, + &pci_ss_info_175c_4300, + &pci_ss_info_175c_4400, + &pci_ss_info_175c_5000, + &pci_ss_info_175c_5100, + &pci_ss_info_175c_6100, + &pci_ss_info_175c_6200, + &pci_ss_info_175c_6400, + &pci_ss_info_175c_8700, + &pci_ss_info_175c_8800, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#define pci_ss_list_1775 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + &pci_ss_info_1787_4002, + &pci_ss_info_1787_4003, + &pci_ss_info_1787_5964, + &pci_ss_info_1787_5965, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#define pci_ss_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + &pci_ss_info_1799_5000, + &pci_ss_info_1799_7001, + &pci_ss_info_1799_700a, + &pci_ss_info_1799_7010, + &pci_ss_info_1799_701a, + NULL +}; +#endif +#define pci_ss_list_179c NULL +#define pci_ss_list_17a0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17aa[] = { + &pci_ss_info_17aa_0286, + &pci_ss_info_17aa_0287, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + &pci_ss_info_17af_200c, + &pci_ss_info_17af_200d, + &pci_ss_info_17af_2012, + &pci_ss_info_17af_2013, + NULL +}; +#endif +#define pci_ss_list_17b3 NULL +#define pci_ss_list_17b4 NULL +#define pci_ss_list_17c0 NULL +#define pci_ss_list_17c2 NULL +#define pci_ss_list_17cb NULL +#define pci_ss_list_17cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17cf[] = { + &pci_ss_info_17cf_0014, + &pci_ss_info_17cf_0020, + &pci_ss_info_17cf_0037, + NULL +}; +#endif +#define pci_ss_list_17d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17de[] = { + &pci_ss_info_17de_08a1, + &pci_ss_info_17de_08a6, + &pci_ss_info_17de_a8a6, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ee[] = { + &pci_ss_info_17ee_2002, + &pci_ss_info_17ee_2003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17f2[] = { + &pci_ss_info_17f2_1c03, + &pci_ss_info_17f2_2c08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe[] = { + &pci_ss_info_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ff[] = { + &pci_ss_info_17ff_0585, + NULL +}; +#endif +#define pci_ss_list_1813 NULL +#define pci_ss_list_1814 NULL +#define pci_ss_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1822[] = { + &pci_ss_info_1822_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_182d[] = { + &pci_ss_info_182d_201d, + NULL +}; +#endif +#define pci_ss_list_1830 NULL +#define pci_ss_list_183b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1849[] = { + &pci_ss_info_1849_0571, + &pci_ss_info_1849_3038, + &pci_ss_info_1849_3065, + &pci_ss_info_1849_3099, + &pci_ss_info_1849_3104, + &pci_ss_info_1849_3149, + &pci_ss_info_1849_3177, + &pci_ss_info_1849_3189, + &pci_ss_info_1849_3227, + &pci_ss_info_1849_8052, + &pci_ss_info_1849_8053, + &pci_ss_info_1849_9761, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1854[] = { + &pci_ss_info_1854_000b, + &pci_ss_info_1854_000c, + &pci_ss_info_1854_000d, + &pci_ss_info_1854_000e, + &pci_ss_info_1854_000f, + &pci_ss_info_1854_0010, + &pci_ss_info_1854_0011, + &pci_ss_info_1854_0012, + &pci_ss_info_1854_0013, + &pci_ss_info_1854_0014, + &pci_ss_info_1854_0015, + &pci_ss_info_1854_0016, + &pci_ss_info_1854_0017, + &pci_ss_info_1854_0018, + &pci_ss_info_1854_0019, + &pci_ss_info_1854_001a, + &pci_ss_info_1854_001b, + &pci_ss_info_1854_001c, + &pci_ss_info_1854_001d, + &pci_ss_info_1854_001e, + &pci_ss_info_1854_001f, + &pci_ss_info_1854_0020, + &pci_ss_info_1854_0021, + &pci_ss_info_1854_0022, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185b[] = { + &pci_ss_info_185b_c100, + &pci_ss_info_185b_c200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185f[] = { + &pci_ss_info_185f_1220, + &pci_ss_info_185f_22a0, + NULL +}; +#endif +#define pci_ss_list_1864 NULL +#define pci_ss_list_1867 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_187e[] = { + &pci_ss_info_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1894[] = { + &pci_ss_info_1894_a006, + &pci_ss_info_1894_fe01, + NULL +}; +#endif +#define pci_ss_list_1896 NULL +#define pci_ss_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ac[] = { + &pci_ss_info_18ac_d500, + &pci_ss_info_18ac_d810, + &pci_ss_info_18ac_d820, + &pci_ss_info_18ac_db00, + &pci_ss_info_18ac_db10, + NULL +}; +#endif +#define pci_ss_list_18b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18bc[] = { + &pci_ss_info_18bc_0050, + &pci_ss_info_18bc_0051, + &pci_ss_info_18bc_0053, + &pci_ss_info_18bc_0100, + &pci_ss_info_18bc_0101, + &pci_ss_info_18bc_0170, + &pci_ss_info_18bc_0171, + &pci_ss_info_18bc_0172, + &pci_ss_info_18bc_0173, + NULL +}; +#endif +#define pci_ss_list_18c8 NULL +#define pci_ss_list_18c9 NULL +#define pci_ss_list_18ca NULL +#define pci_ss_list_18d2 NULL +#define pci_ss_list_18dd NULL +#define pci_ss_list_18e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec[] = { + &pci_ss_info_18ec_d001, + &pci_ss_info_18ec_d002, + &pci_ss_info_18ec_d003, + &pci_ss_info_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18fb[] = { + &pci_ss_info_18fb_7872, + NULL +}; +#endif +#define pci_ss_list_1924 NULL +#define pci_ss_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1931[] = { + &pci_ss_info_1931_000a, + &pci_ss_info_1931_000b, + NULL +}; +#endif +#define pci_ss_list_1942 NULL +#define pci_ss_list_1957 NULL +#define pci_ss_list_1958 NULL +#define pci_ss_list_1966 NULL +#define pci_ss_list_196a NULL +#define pci_ss_list_197b NULL +#define pci_ss_list_1989 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1993[] = { + &pci_ss_info_1993_0ded, + &pci_ss_info_1993_0dee, + &pci_ss_info_1993_0def, + NULL +}; +#endif +#define pci_ss_list_19ae NULL +#define pci_ss_list_19d4 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3906, + &pci_ss_info_1de1_3907, + &pci_ss_info_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_1fc0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1fc1[] = { + &pci_ss_info_1fc1_0026, + &pci_ss_info_1fc1_0027, + NULL +}; +#endif +#define pci_ss_list_1fce NULL +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_2801, + &pci_ss_info_270f_2803, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + &pci_ss_info_270f_f641, + &pci_ss_info_270f_f645, + &pci_ss_info_270f_fc00, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_3842 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_144f, + &pci_ss_info_4005_4000, + &pci_ss_info_4005_4710, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_4144 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_494f NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53[] = { + &pci_ss_info_4c53_1000, + &pci_ss_info_4c53_1010, + &pci_ss_info_4c53_1020, + &pci_ss_info_4c53_1030, + &pci_ss_info_4c53_1040, + &pci_ss_info_4c53_1050, + &pci_ss_info_4c53_1051, + &pci_ss_info_4c53_1060, + &pci_ss_info_4c53_1070, + &pci_ss_info_4c53_1080, + &pci_ss_info_4c53_1090, + &pci_ss_info_4c53_10a0, + &pci_ss_info_4c53_10b0, + &pci_ss_info_4c53_10d0, + &pci_ss_info_4c53_10e0, + &pci_ss_info_4c53_1300, + &pci_ss_info_4c53_1310, + &pci_ss_info_4c53_3000, + &pci_ss_info_4c53_3001, + &pci_ss_info_4c53_3002, + &pci_ss_info_4c53_3010, + &pci_ss_info_4c53_3011, + &pci_ss_info_4c53_4000, + NULL +}; +#endif +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5168[] = { + &pci_ss_info_5168_0138, + &pci_ss_info_5168_0212, + &pci_ss_info_5168_0214, + &pci_ss_info_5168_0306, + &pci_ss_info_5168_0502, + NULL +}; +#endif +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_2036, + &pci_ss_info_5654_3132, + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_5851 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_7063[] = { + &pci_ss_info_7063_3000, + NULL +}; +#endif +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_807d[] = { + &pci_ss_info_807d_0035, + &pci_ss_info_807d_1043, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_0075, + &pci_ss_info_8086_0076, + &pci_ss_info_8086_0077, + &pci_ss_info_8086_0079, + &pci_ss_info_8086_007b, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_01af, + &pci_ss_info_8086_01c1, + &pci_ss_info_8086_01f7, + &pci_ss_info_8086_0520, + &pci_ss_info_8086_0523, + &pci_ss_info_8086_0530, + &pci_ss_info_8086_0532, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1016, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1018, + &pci_ss_info_8086_1019, + &pci_ss_info_8086_101a, + &pci_ss_info_8086_101e, + &pci_ss_info_8086_1026, + &pci_ss_info_8086_1027, + &pci_ss_info_8086_1028, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_1075, + &pci_ss_info_8086_1076, + &pci_ss_info_8086_1077, + &pci_ss_info_8086_1078, + &pci_ss_info_8086_1079, + &pci_ss_info_8086_107a, + &pci_ss_info_8086_107b, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_110d, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1113, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_1176, + &pci_ss_info_8086_1179, + &pci_ss_info_8086_117a, + &pci_ss_info_8086_1276, + &pci_ss_info_8086_127a, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1376, + &pci_ss_info_8086_1476, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_24db, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_2527, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_301f, + &pci_ss_info_8086_3020, + &pci_ss_info_8086_302f, + &pci_ss_info_8086_3063, + &pci_ss_info_8086_308d, + &pci_ss_info_8086_3108, + &pci_ss_info_8086_3411, + &pci_ss_info_8086_3424, + &pci_ss_info_8086_3427, + &pci_ss_info_8086_3431, + &pci_ss_info_8086_3439, + &pci_ss_info_8086_3499, + &pci_ss_info_8086_4147, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4246, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4532, + &pci_ss_info_8086_4541, + &pci_ss_info_8086_4557, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_524c, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_544e, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + &pci_ss_info_8086_a000, + &pci_ss_info_8086_a01f, + &pci_ss_info_8086_a11f, + &pci_ss_info_8086_e000, + &pci_ss_info_8086_e001, + NULL +}; +#define pci_ss_list_8401 NULL +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8912 NULL +#define pci_ss_list_8c4a NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7881, + &pci_ss_info_9004_7887, + &pci_ss_info_9004_7888, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005[] = { + &pci_ss_info_9005_0003, + &pci_ss_info_9005_000f, + &pci_ss_info_9005_0041, + &pci_ss_info_9005_0106, + &pci_ss_info_9005_0250, + &pci_ss_info_9005_0283, + &pci_ss_info_9005_0284, + &pci_ss_info_9005_0285, + &pci_ss_info_9005_0286, + &pci_ss_info_9005_0287, + &pci_ss_info_9005_0288, + &pci_ss_info_9005_0289, + &pci_ss_info_9005_028a, + &pci_ss_info_9005_028b, + &pci_ss_info_9005_028c, + &pci_ss_info_9005_028d, + &pci_ss_info_9005_028e, + &pci_ss_info_9005_028f, + &pci_ss_info_9005_0290, + &pci_ss_info_9005_0292, + &pci_ss_info_9005_0293, + &pci_ss_info_9005_0294, + &pci_ss_info_9005_0296, + &pci_ss_info_9005_0297, + &pci_ss_info_9005_0298, + &pci_ss_info_9005_0299, + &pci_ss_info_9005_029a, + &pci_ss_info_9005_029b, + &pci_ss_info_9005_029c, + &pci_ss_info_9005_029d, + &pci_ss_info_9005_029e, + &pci_ss_info_9005_029f, + &pci_ss_info_9005_02a0, + &pci_ss_info_9005_02a1, + &pci_ss_info_9005_02a2, + &pci_ss_info_9005_02a3, + &pci_ss_info_9005_02a4, + &pci_ss_info_9005_02a5, + &pci_ss_info_9005_02a6, + &pci_ss_info_9005_0364, + &pci_ss_info_9005_0365, + &pci_ss_info_9005_0800, + &pci_ss_info_9005_1364, + &pci_ss_info_9005_1365, + &pci_ss_info_9005_2180, + &pci_ss_info_9005_6220, + &pci_ss_info_9005_62a0, + &pci_ss_info_9005_62a1, + &pci_ss_info_9005_8100, + &pci_ss_info_9005_a100, + &pci_ss_info_9005_a180, + &pci_ss_info_9005_b500, + &pci_ss_info_9005_e100, + &pci_ss_info_9005_e220, + &pci_ss_info_9005_e2a0, + &pci_ss_info_9005_f500, + &pci_ss_info_9005_f620, + &pci_ss_info_9005_ffff, + NULL +}; +#endif +#define pci_ss_list_907f NULL +#define pci_ss_list_919a NULL +#define pci_ss_list_9412 NULL +#define pci_ss_list_9699 NULL +#define pci_ss_list_9710 NULL +#define pci_ss_list_9902 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a0a0[] = { + &pci_ss_info_a0a0_0007, + &pci_ss_info_a0a0_0022, + &pci_ss_info_a0a0_01b6, + &pci_ss_info_a0a0_0506, + &pci_ss_info_a0a0_0509, + NULL +}; +#endif +#define pci_ss_list_a0f1 NULL +#define pci_ss_list_a200 NULL +#define pci_ss_list_a259 NULL +#define pci_ss_list_a25b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a304[] = { + &pci_ss_info_a304_81b7, + NULL +}; +#endif +#define pci_ss_list_a727 NULL +#define pci_ss_list_aa42 NULL +#define pci_ss_list_ac1e NULL +#define pci_ss_list_ac3d NULL +#define pci_ss_list_aecb NULL +#define pci_ss_list_affe NULL +#define pci_ss_list_b1b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_bd11[] = { + &pci_ss_info_bd11_1200, + NULL +}; +#endif +#define pci_ss_list_c001 NULL +#define pci_ss_list_c0a9 NULL +#define pci_ss_list_c0de NULL +#define pci_ss_list_c0fe NULL +#define pci_ss_list_ca50 NULL +#define pci_ss_list_cafe NULL +#define pci_ss_list_cccc NULL +#define pci_ss_list_cddd NULL +#define pci_ss_list_d161 NULL +#define pci_ss_list_d4d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d531[] = { + &pci_ss_info_d531_c002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d84d[] = { + &pci_ss_info_d84d_4006, + &pci_ss_info_d84d_4008, + &pci_ss_info_d84d_4014, + &pci_ss_info_d84d_4018, + &pci_ss_info_d84d_4025, + &pci_ss_info_d84d_4027, + &pci_ss_info_d84d_4028, + &pci_ss_info_d84d_4036, + &pci_ss_info_d84d_4037, + &pci_ss_info_d84d_4038, + &pci_ss_info_d84d_4052, + &pci_ss_info_d84d_4053, + &pci_ss_info_d84d_4055, + &pci_ss_info_d84d_4058, + &pci_ss_info_d84d_4065, + &pci_ss_info_d84d_4068, + &pci_ss_info_d84d_4078, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_dead[] = { + &pci_ss_info_dead_0800, + NULL +}; +#endif +#define pci_ss_list_deaf NULL +#define pci_ss_list_e000 NULL +#define pci_ss_list_e159 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e4bf[] = { + &pci_ss_info_e4bf_1000, + &pci_ss_info_e4bf_1010, + &pci_ss_info_e4bf_1020, + &pci_ss_info_e4bf_1040, + &pci_ss_info_e4bf_3100, + NULL +}; +#endif +#define pci_ss_list_e55e NULL +#define pci_ss_list_ea01 NULL +#define pci_ss_list_ea60 NULL +#define pci_ss_list_eabb NULL +#define pci_ss_list_eace NULL +#define pci_ss_list_ec80 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_ecc0[] = { + &pci_ss_info_ecc0_0010, + &pci_ss_info_ecc0_0020, + &pci_ss_info_ecc0_0030, + &pci_ss_info_ecc0_0031, + &pci_ss_info_ecc0_0040, + &pci_ss_info_ecc0_0041, + &pci_ss_info_ecc0_0050, + &pci_ss_info_ecc0_0051, + &pci_ss_info_ecc0_0060, + &pci_ss_info_ecc0_0070, + &pci_ss_info_ecc0_0071, + &pci_ss_info_ecc0_0072, + &pci_ss_info_ecc0_0080, + &pci_ss_info_ecc0_0081, + &pci_ss_info_ecc0_0090, + &pci_ss_info_ecc0_00a0, + &pci_ss_info_ecc0_00b0, + &pci_ss_info_ecc0_0100, + NULL +}; +#endif +#define pci_ss_list_edd8 NULL +#define pci_ss_list_f1d0 NULL +#define pci_ss_list_fa57 NULL +#define pci_ss_list_febd NULL +#define pci_ss_list_feda NULL +#define pci_ss_list_fede NULL +#define pci_ss_list_fffd NULL +#define pci_ss_list_fffe NULL +#define pci_ss_list_ffff NULL +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0070_0003 = { + 0x0003, pci_device_0070_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0009 = { + 0x0009, pci_device_0070_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0801 = { + 0x0801, pci_device_0070_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_0807 = { + 0x0807, pci_device_0070_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4000 = { + 0x4000, pci_device_0070_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4001 = { + 0x4001, pci_device_0070_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4009 = { + 0x4009, pci_device_0070_4009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4800 = { + 0x4800, pci_device_0070_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4801 = { + 0x4801, pci_device_0070_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_4803 = { + 0x4803, pci_device_0070_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_8003 = { + 0x8003, pci_device_0070_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_8801 = { + 0x8801, pci_device_0070_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_c801 = { + 0xc801, pci_device_0070_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_e807 = { + 0xe807, pci_device_0070_e807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_e807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0070_e817 = { + 0xe817, pci_device_0070_e817, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0070_e817, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0095_0680 = { + 0x0680, pci_device_0095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0095_0680, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_018a_0106 = { + 0x0106, pci_device_018a_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_018a_0106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_021b_8139 = { + 0x8139, pci_device_021b_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_021b_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0270_0801 = { + 0x0801, pci_device_0270_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0270_0801, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0291_8212 = { + 0x8212, pci_device_0291_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0291_8212, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_02ac_1012 = { + 0x1012, pci_device_02ac_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_02ac_1012, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0357_000a = { + 0x000a, pci_device_0357_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0357_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0432_0001 = { + 0x0001, pci_device_0432_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0432_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_045e_006e = { + 0x006e, pci_device_045e_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_045e_00c2 = { + 0x00c2, pci_device_045e_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_00c2, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_04cf_8818 = { + 0x8818, pci_device_04cf_8818, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_04cf_8818, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05e3_0701 = { + 0x0701, pci_device_05e3_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05e3_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1703 = { + 0x1703, pci_device_0675_1703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1703, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1704 = { + 0x1704, pci_device_0675_1704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_067b_3507 = { + 0x3507, pci_device_067b_3507, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_3507, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b49_064f = { + 0x064f, pci_device_0b49_064f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b49_064f, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0046 = { + 0x0046, pci_device_0e11_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_005a = { + 0x005a, pci_device_0e11_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007c = { + 0x007c, pci_device_0e11_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007d = { + 0x007d, pci_device_0e11_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0085 = { + 0x0085, pci_device_0e11_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00b1 = { + 0x00b1, pci_device_0e11_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00bb = { + 0x00bb, pci_device_0e11_00bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00ca = { + 0x00ca, pci_device_0e11_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cb = { + 0x00cb, pci_device_0e11_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cf = { + 0x00cf, pci_device_0e11_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d0 = { + 0x00d0, pci_device_0e11_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d1 = { + 0x00d1, pci_device_0e11_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00e3 = { + 0x00e3, pci_device_0e11_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4030 = { + 0x4030, pci_device_0e11_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4031 = { + 0x4031, pci_device_0e11_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4032 = { + 0x4032, pci_device_0e11_4032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4033 = { + 0x4033, pci_device_0e11_4033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4034 = { + 0x4034, pci_device_0e11_4034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4040 = { + 0x4040, pci_device_0e11_4040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4048 = { + 0x4048, pci_device_0e11_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4050 = { + 0x4050, pci_device_0e11_4050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4051 = { + 0x4051, pci_device_0e11_4051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4058 = { + 0x4058, pci_device_0e11_4058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4070 = { + 0x4070, pci_device_0e11_4070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4080 = { + 0x4080, pci_device_0e11_4080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4082 = { + 0x4082, pci_device_0e11_4082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4083 = { + 0x4083, pci_device_0e11_4083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4091 = { + 0x4091, pci_device_0e11_4091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409a = { + 0x409a, pci_device_0e11_409a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409b = { + 0x409b, pci_device_0e11_409b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409c = { + 0x409c, pci_device_0e11_409c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409d = { + 0x409d, pci_device_0e11_409d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b200 = { + 0xb200, pci_device_0e11_b200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b203 = { + 0xb203, pci_device_0e11_b203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b204 = { + 0xb204, pci_device_0e11_b204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0031 = { + 0x0031, pci_device_1000_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0032 = { + 0x0032, pci_device_1000_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0033 = { + 0x0033, pci_device_1000_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0041 = { + 0x0041, pci_device_1000_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0050 = { + 0x0050, pci_device_1000_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0054 = { + 0x0054, pci_device_1000_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0056 = { + 0x0056, pci_device_1000_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0058 = { + 0x0058, pci_device_1000_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005a = { + 0x005a, pci_device_1000_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005c = { + 0x005c, pci_device_1000_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005e = { + 0x005e, pci_device_1000_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0060 = { + 0x0060, pci_device_1000_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0407 = { + 0x0407, pci_device_1000_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0408 = { + 0x0408, pci_device_1000_0408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0409 = { + 0x0409, pci_device_1000_0409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0640 = { + 0x0640, pci_device_1000_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0642 = { + 0x0642, pci_device_1000_0642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0646 = { + 0x0646, pci_device_1000_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0804 = { + 0x0804, pci_device_1000_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0805 = { + 0x0805, pci_device_1000_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0806 = { + 0x0806, pci_device_1000_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0807 = { + 0x0807, pci_device_1000_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_3150 = { + 0x3150, pci_device_1002_3150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3152 = { + 0x3152, pci_device_1002_3152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3154 = { + 0x3154, pci_device_1002_3154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e50 = { + 0x3e50, pci_device_1002_3e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e54 = { + 0x3e54, pci_device_1002_3e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e70 = { + 0x3e70, pci_device_1002_3e70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4136 = { + 0x4136, pci_device_1002_4136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4137 = { + 0x4137, pci_device_1002_4137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4148 = { + 0x4148, pci_device_1002_4148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4149 = { + 0x4149, pci_device_1002_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414a = { + 0x414a, pci_device_1002_414a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414b = { + 0x414b, pci_device_1002_414b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4150 = { + 0x4150, pci_device_1002_4150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4151 = { + 0x4151, pci_device_1002_4151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4152 = { + 0x4152, pci_device_1002_4152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4153 = { + 0x4153, pci_device_1002_4153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4154 = { + 0x4154, pci_device_1002_4154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4155 = { + 0x4155, pci_device_1002_4155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4156 = { + 0x4156, pci_device_1002_4156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4157 = { + 0x4157, pci_device_1002_4157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4164 = { + 0x4164, pci_device_1002_4164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4165 = { + 0x4165, pci_device_1002_4165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4166 = { + 0x4166, pci_device_1002_4166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4168 = { + 0x4168, pci_device_1002_4168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4170 = { + 0x4170, pci_device_1002_4170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4171 = { + 0x4171, pci_device_1002_4171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4172 = { + 0x4172, pci_device_1002_4172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4173 = { + 0x4173, pci_device_1002_4173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4237 = { + 0x4237, pci_device_1002_4237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4243 = { + 0x4243, pci_device_1002_4243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4341 = { + 0x4341, pci_device_1002_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4345 = { + 0x4345, pci_device_1002_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4347 = { + 0x4347, pci_device_1002_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4348 = { + 0x4348, pci_device_1002_4348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4349 = { + 0x4349, pci_device_1002_4349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_434d = { + 0x434d, pci_device_1002_434d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_434d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4353 = { + 0x4353, pci_device_1002_4353, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4353, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4363 = { + 0x4363, pci_device_1002_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_436e = { + 0x436e, pci_device_1002_436e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_436e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4370 = { + 0x4370, pci_device_1002_4370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4371 = { + 0x4371, pci_device_1002_4371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4372 = { + 0x4372, pci_device_1002_4372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4373 = { + 0x4373, pci_device_1002_4373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4374 = { + 0x4374, pci_device_1002_4374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4375 = { + 0x4375, pci_device_1002_4375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4376 = { + 0x4376, pci_device_1002_4376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4377 = { + 0x4377, pci_device_1002_4377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4378 = { + 0x4378, pci_device_1002_4378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4379 = { + 0x4379, pci_device_1002_4379, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4379, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437a = { + 0x437a, pci_device_1002_437a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4437 = { + 0x4437, pci_device_1002_4437, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4437, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a48 = { + 0x4a48, pci_device_1002_4a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a49 = { + 0x4a49, pci_device_1002_4a49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4a = { + 0x4a4a, pci_device_1002_4a4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4b = { + 0x4a4b, pci_device_1002_4a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4c = { + 0x4a4c, pci_device_1002_4a4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4d = { + 0x4a4d, pci_device_1002_4a4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4e = { + 0x4a4e, pci_device_1002_4a4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a50 = { + 0x4a50, pci_device_1002_4a50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a70 = { + 0x4a70, pci_device_1002_4a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b49 = { + 0x4b49, pci_device_1002_4b49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4b = { + 0x4b4b, pci_device_1002_4b4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4c = { + 0x4b4c, pci_device_1002_4b4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b69 = { + 0x4b69, pci_device_1002_4b69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6b = { + 0x4b6b, pci_device_1002_4b6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6c = { + 0x4b6c, pci_device_1002_4b6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c6e = { + 0x4c6e, pci_device_1002_4c6e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c6e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e48 = { + 0x4e48, pci_device_1002_4e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e49 = { + 0x4e49, pci_device_1002_4e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4a = { + 0x4e4a, pci_device_1002_4e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4b = { + 0x4e4b, pci_device_1002_4e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e50 = { + 0x4e50, pci_device_1002_4e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e51 = { + 0x4e51, pci_device_1002_4e51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e52 = { + 0x4e52, pci_device_1002_4e52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e53 = { + 0x4e53, pci_device_1002_4e53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e54 = { + 0x4e54, pci_device_1002_4e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e56 = { + 0x4e56, pci_device_1002_4e56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e68 = { + 0x4e68, pci_device_1002_4e68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e69 = { + 0x4e69, pci_device_1002_4e69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e6a = { + 0x4e6a, pci_device_1002_4e6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e71 = { + 0x4e71, pci_device_1002_4e71, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e71, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5154 = { + 0x5154, pci_device_1002_5154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5155 = { + 0x5155, pci_device_1002_5155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515e = { + 0x515e, pci_device_1002_515e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5460 = { + 0x5460, pci_device_1002_5460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5464 = { + 0x5464, pci_device_1002_5464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5548 = { + 0x5548, pci_device_1002_5548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5549 = { + 0x5549, pci_device_1002_5549, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5549, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554a = { + 0x554a, pci_device_1002_554a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554b = { + 0x554b, pci_device_1002_554b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554d = { + 0x554d, pci_device_1002_554d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554f = { + 0x554f, pci_device_1002_554f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5550 = { + 0x5550, pci_device_1002_5550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5551 = { + 0x5551, pci_device_1002_5551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5552 = { + 0x5552, pci_device_1002_5552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5554 = { + 0x5554, pci_device_1002_5554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556b = { + 0x556b, pci_device_1002_556b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556d = { + 0x556d, pci_device_1002_556d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556f = { + 0x556f, pci_device_1002_556f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564a = { + 0x564a, pci_device_1002_564a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564b = { + 0x564b, pci_device_1002_564b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5652 = { + 0x5652, pci_device_1002_5652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5653 = { + 0x5653, pci_device_1002_5653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5830 = { + 0x5830, pci_device_1002_5830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5831 = { + 0x5831, pci_device_1002_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5832 = { + 0x5832, pci_device_1002_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5833 = { + 0x5833, pci_device_1002_5833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5834 = { + 0x5834, pci_device_1002_5834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5835 = { + 0x5835, pci_device_1002_5835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5838 = { + 0x5838, pci_device_1002_5838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5940 = { + 0x5940, pci_device_1002_5940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5941 = { + 0x5941, pci_device_1002_5941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5944 = { + 0x5944, pci_device_1002_5944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5950 = { + 0x5950, pci_device_1002_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5951 = { + 0x5951, pci_device_1002_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5954 = { + 0x5954, pci_device_1002_5954, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5954, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5955 = { + 0x5955, pci_device_1002_5955, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5955, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5960 = { + 0x5960, pci_device_1002_5960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5961 = { + 0x5961, pci_device_1002_5961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5962 = { + 0x5962, pci_device_1002_5962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5964 = { + 0x5964, pci_device_1002_5964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5969 = { + 0x5969, pci_device_1002_5969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5974 = { + 0x5974, pci_device_1002_5974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5975 = { + 0x5975, pci_device_1002_5975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a34 = { + 0x5a34, pci_device_1002_5a34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a41 = { + 0x5a41, pci_device_1002_5a41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a42 = { + 0x5a42, pci_device_1002_5a42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a61 = { + 0x5a61, pci_device_1002_5a61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a62 = { + 0x5a62, pci_device_1002_5a62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b60 = { + 0x5b60, pci_device_1002_5b60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b62 = { + 0x5b62, pci_device_1002_5b62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b63 = { + 0x5b63, pci_device_1002_5b63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b64 = { + 0x5b64, pci_device_1002_5b64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b65 = { + 0x5b65, pci_device_1002_5b65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b70 = { + 0x5b70, pci_device_1002_5b70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b72 = { + 0x5b72, pci_device_1002_5b72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b73 = { + 0x5b73, pci_device_1002_5b73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b74 = { + 0x5b74, pci_device_1002_5b74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c61 = { + 0x5c61, pci_device_1002_5c61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c63 = { + 0x5c63, pci_device_1002_5c63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d44 = { + 0x5d44, pci_device_1002_5d44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d48 = { + 0x5d48, pci_device_1002_5d48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d49 = { + 0x5d49, pci_device_1002_5d49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4a = { + 0x5d4a, pci_device_1002_5d4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4d = { + 0x5d4d, pci_device_1002_5d4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d52 = { + 0x5d52, pci_device_1002_5d52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d57 = { + 0x5d57, pci_device_1002_5d57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6d = { + 0x5d6d, pci_device_1002_5d6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d72 = { + 0x5d72, pci_device_1002_5d72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d77 = { + 0x5d77, pci_device_1002_5d77, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d77, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e48 = { + 0x5e48, pci_device_1002_5e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e49 = { + 0x5e49, pci_device_1002_5e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4a = { + 0x5e4a, pci_device_1002_5e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4b = { + 0x5e4b, pci_device_1002_5e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4c = { + 0x5e4c, pci_device_1002_5e4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4d = { + 0x5e4d, pci_device_1002_5e4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4f = { + 0x5e4f, pci_device_1002_5e4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6b = { + 0x5e6b, pci_device_1002_5e6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6d = { + 0x5e6d, pci_device_1002_5e6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7010 = { + 0x7010, pci_device_1002_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7105 = { + 0x7105, pci_device_1002_7105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7109 = { + 0x7109, pci_device_1002_7109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7833 = { + 0x7833, pci_device_1002_7833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7834 = { + 0x7834, pci_device_1002_7834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7835 = { + 0x7835, pci_device_1002_7835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7838 = { + 0x7838, pci_device_1002_7838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7c37 = { + 0x7c37, pci_device_1002_7c37, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7c37, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab0 = { + 0xcab0, pci_device_1002_cab0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab2 = { + 0xcab2, pci_device_1002_cab2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab3 = { + 0xcab3, pci_device_1002_cab3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cbb2 = { + 0xcbb2, pci_device_1002_cbb2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cbb2, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0021 = { + 0x0021, pci_device_100b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0028 = { + 0x0028, pci_device_100b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002a = { + 0x002a, pci_device_100b_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002b = { + 0x002b, pci_device_100b_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002d = { + 0x002d, pci_device_100b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002e = { + 0x002e, pci_device_100b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002f = { + 0x002f, pci_device_100b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0030 = { + 0x0030, pci_device_100b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0035 = { + 0x0035, pci_device_100b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0510 = { + 0x0510, pci_device_100b_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0511 = { + 0x0511, pci_device_100b_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0515 = { + 0x0515, pci_device_100b_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0017 = { + 0x0017, pci_device_1011_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4000 = { + 0x4000, pci_device_1013_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0031 = { + 0x0031, pci_device_1014_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0037 = { + 0x0037, pci_device_1014_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003c = { + 0x003c, pci_device_1014_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0054 = { + 0x0054, pci_device_1014_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005e = { + 0x005e, pci_device_1014_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008b = { + 0x008b, pci_device_1014_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008e = { + 0x008e, pci_device_1014_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0091 = { + 0x0091, pci_device_1014_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_009f = { + 0x009f, pci_device_1014_009f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_009f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b8 = { + 0x00b8, pci_device_1014_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0104 = { + 0x0104, pci_device_1014_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_015e = { + 0x015e, pci_device_1014_015e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_015e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0160 = { + 0x0160, pci_device_1014_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_016e = { + 0x016e, pci_device_1014_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0170 = { + 0x0170, pci_device_1014_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_017d = { + 0x017d, pci_device_1014_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0180 = { + 0x0180, pci_device_1014_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0188 = { + 0x0188, pci_device_1014_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01c1 = { + 0x01c1, pci_device_1014_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01e6 = { + 0x01e6, pci_device_1014_01e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01ff = { + 0x01ff, pci_device_1014_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0219 = { + 0x0219, pci_device_1014_0219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021b = { + 0x021b, pci_device_1014_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021c = { + 0x021c, pci_device_1014_021c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0233 = { + 0x0233, pci_device_1014_0233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0266 = { + 0x0266, pci_device_1014_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0268 = { + 0x0268, pci_device_1014_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0269 = { + 0x0269, pci_device_1014_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_028c = { + 0x028c, pci_device_1014_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02a1 = { + 0x02a1, pci_device_1014_02a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0314 = { + 0x0314, pci_device_1014_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_3022 = { + 0x3022, pci_device_1014_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_4022 = { + 0x4022, pci_device_1014_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_0009 = { + 0x0009, pci_device_101e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2003 = { + 0x2003, pci_device_1022_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_208f = { + 0x208f, pci_device_1022_208f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_208f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700a = { + 0x700a, pci_device_1022_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700b = { + 0x700b, pci_device_1022_700b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7458 = { + 0x7458, pci_device_1022_7458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7459 = { + 0x7459, pci_device_1022_7459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_756b = { + 0x756b, pci_device_1022_756b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_756b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2100 = { + 0x2100, pci_device_1023_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2200 = { + 0x2200, pci_device_1023_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1671 = { + 0x1671, pci_device_1025_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1672 = { + 0x1672, pci_device_1025_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0009 = { + 0x0009, pci_device_1028_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000d = { + 0x000d, pci_device_1028_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0010 = { + 0x0010, pci_device_1028_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0011 = { + 0x0011, pci_device_1028_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0012 = { + 0x0012, pci_device_1028_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0013 = { + 0x0013, pci_device_1028_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0014 = { + 0x0014, pci_device_1028_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0015 = { + 0x0015, pci_device_1028_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0015, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_001f = { + 0x001f, pci_device_102a_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00c5 = { + 0x00c5, pci_device_102a_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00cf = { + 0x00cf, pci_device_102a_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00cf, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0100 = { + 0x0100, pci_device_102b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0528 = { + 0x0528, pci_device_102b_0528, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0528, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2537 = { + 0x2537, pci_device_102b_2537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2538 = { + 0x2538, pci_device_102b_2538, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2538, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_000a = { + 0x000a, pci_device_102f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0030 = { + 0x0030, pci_device_102f_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0031 = { + 0x0031, pci_device_102f_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0105 = { + 0x0105, pci_device_102f_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0106 = { + 0x0106, pci_device_102f_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0107 = { + 0x0107, pci_device_102f_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0108 = { + 0x0108, pci_device_102f_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0180 = { + 0x0180, pci_device_102f_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0181 = { + 0x0181, pci_device_102f_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0182 = { + 0x0182, pci_device_102f_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0182, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0000 = { + 0x0000, pci_device_1033_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0072 = { + 0x0072, pci_device_1033_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a5 = { + 0x00a5, pci_device_1033_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00ce = { + 0x00ce, pci_device_1033_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00df = { + 0x00df, pci_device_1033_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e7 = { + 0x00e7, pci_device_1033_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f2 = { + 0x00f2, pci_device_1033_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f3 = { + 0x00f3, pci_device_1033_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_010c = { + 0x010c, pci_device_1033_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_010c, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0003 = { + 0x0003, pci_device_1039_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0004 = { + 0x0004, pci_device_1039_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_000a = { + 0x000a, pci_device_1039_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0016 = { + 0x0016, pci_device_1039_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0180 = { + 0x0180, pci_device_1039_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0181 = { + 0x0181, pci_device_1039_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0182 = { + 0x0182, pci_device_1039_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0191 = { + 0x0191, pci_device_1039_0191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0550 = { + 0x0550, pci_device_1039_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0648 = { + 0x0648, pci_device_1039_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0655 = { + 0x0655, pci_device_1039_0655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0660 = { + 0x0660, pci_device_1039_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0661 = { + 0x0661, pci_device_1039_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0661, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0741 = { + 0x0741, pci_device_1039_0741, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0741, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0746 = { + 0x0746, pci_device_1039_0746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0755 = { + 0x0755, pci_device_1039_0755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0760 = { + 0x0760, pci_device_1039_0760, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0760, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0761 = { + 0x0761, pci_device_1039_0761, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0761, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0963 = { + 0x0963, pci_device_1039_0963, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0963, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0964 = { + 0x0964, pci_device_1039_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0965 = { + 0x0965, pci_device_1039_0965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6330 = { + 0x6330, pci_device_1039_6330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7019 = { + 0x7019, pci_device_1039_7019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1006 = { + 0x1006, pci_device_103c_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_100a = { + 0x100a, pci_device_103c_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1054 = { + 0x1054, pci_device_103c_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f0 = { + 0x10f0, pci_device_103c_10f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f1 = { + 0x10f1, pci_device_103c_10f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127c = { + 0x127c, pci_device_103c_127c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1291 = { + 0x1291, pci_device_103c_1291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12b4 = { + 0x12b4, pci_device_103c_12b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12fa = { + 0x12fa, pci_device_103c_12fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3080 = { + 0x3080, pci_device_103c_3080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3220 = { + 0x3220, pci_device_103c_3220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3230 = { + 0x3230, pci_device_103c_3230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3230, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4015 = { + 0x4015, pci_device_1043_4015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4057 = { + 0x4057, pci_device_1043_4057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8043 = { + 0x8043, pci_device_1043_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_807b = { + 0x807b, pci_device_1043_807b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_807b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80bb = { + 0x80bb, pci_device_1043_80bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80c5 = { + 0x80c5, pci_device_1043_80c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80df = { + 0x80df, pci_device_1043_80df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8187 = { + 0x8187, pci_device_1043_8187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8188 = { + 0x8188, pci_device_1043_8188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8188, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0c60 = { + 0x0c60, pci_device_1048_0c60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0c60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_8901 = { + 0x8901, pci_device_1048_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_8901, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0209 = { + 0x0209, pci_device_104a_0209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_020a = { + 0x020a, pci_device_104a_020a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_020a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021a = { + 0x021a, pci_device_104a_021a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021b = { + 0x021b, pci_device_104a_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0500 = { + 0x0500, pci_device_104a_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0564 = { + 0x0564, pci_device_104a_0564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_55cc = { + 0x55cc, pci_device_104a_55cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_55cc, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8025 = { + 0x8025, pci_device_104c_8025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8029 = { + 0x8029, pci_device_104c_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802b = { + 0x802b, pci_device_104c_802b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802e = { + 0x802e, pci_device_104c_802e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8031 = { + 0x8031, pci_device_104c_8031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8032 = { + 0x8032, pci_device_104c_8032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8033 = { + 0x8033, pci_device_104c_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8034 = { + 0x8034, pci_device_104c_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8035 = { + 0x8035, pci_device_104c_8035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8036 = { + 0x8036, pci_device_104c_8036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8038 = { + 0x8038, pci_device_104c_8038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8201 = { + 0x8201, pci_device_104c_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8204 = { + 0x8204, pci_device_104c_8204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8401 = { + 0x8401, pci_device_104c_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9000 = { + 0x9000, pci_device_104c_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9066 = { + 0x9066, pci_device_104c_9066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac44 = { + 0xac44, pci_device_104c_ac44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac46 = { + 0xac46, pci_device_104c_ac46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac47 = { + 0xac47, pci_device_104c_ac47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac4a = { + 0xac4a, pci_device_104c_ac4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac54 = { + 0xac54, pci_device_104c_ac54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8d = { + 0xac8d, pci_device_104c_ac8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8e = { + 0xac8e, pci_device_104c_ac8e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8f = { + 0xac8f, pci_device_104c_ac8f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8004 = { + 0x8004, pci_device_104d_8004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9921 = { + 0x9921, pci_device_1050_9921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9922 = { + 0x9922, pci_device_1050_9922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0008 = { + 0x0008, pci_device_1057_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0009 = { + 0x0009, pci_device_1057_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c1 = { + 0x18c1, pci_device_1057_18c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3410 = { + 0x3410, pci_device_1057_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5803 = { + 0x5803, pci_device_1057_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5806 = { + 0x5806, pci_device_1057_5806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5808 = { + 0x5808, pci_device_1057_5808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6405 = { + 0x6405, pci_device_1057_6405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6405, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3318 = { + 0x3318, pci_device_105a_3318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3319 = { + 0x3319, pci_device_105a_3319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3371 = { + 0x3371, pci_device_105a_3371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3373 = { + 0x3373, pci_device_105a_3373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3375 = { + 0x3375, pci_device_105a_3375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3515 = { + 0x3515, pci_device_105a_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3519 = { + 0x3519, pci_device_105a_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3571 = { + 0x3571, pci_device_105a_3571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3574 = { + 0x3574, pci_device_105a_3574, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3574, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3577 = { + 0x3577, pci_device_105a_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d17 = { + 0x3d17, pci_device_105a_3d17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d18 = { + 0x3d18, pci_device_105a_3d18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d73 = { + 0x3d73, pci_device_105a_3d73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d75 = { + 0x3d75, pci_device_105a_3d75, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d75, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6622 = { + 0x6622, pci_device_105a_6622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6624 = { + 0x6624, pci_device_105a_6624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6626 = { + 0x6626, pci_device_105a_6626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6629 = { + 0x6629, pci_device_105a_6629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8002 = { + 0x8002, pci_device_105a_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_0301 = { + 0x0301, pci_device_1067_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0304 = { + 0x0304, pci_device_1067_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0308 = { + 0x0308, pci_device_1067_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0020 = { + 0x0020, pci_device_1069_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_b166 = { + 0xb166, pci_device_1069_b166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_b166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba57 = { + 0xba57, pci_device_1069_ba57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba57, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000c = { + 0x000c, pci_device_106b_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0035 = { + 0x0035, pci_device_106b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0036 = { + 0x0036, pci_device_106b_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003b = { + 0x003b, pci_device_106b_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003e = { + 0x003e, pci_device_106b_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003f = { + 0x003f, pci_device_106b_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0040 = { + 0x0040, pci_device_106b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0041 = { + 0x0041, pci_device_106b_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0042 = { + 0x0042, pci_device_106b_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0043 = { + 0x0043, pci_device_106b_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0045 = { + 0x0045, pci_device_106b_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0046 = { + 0x0046, pci_device_106b_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0047 = { + 0x0047, pci_device_106b_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0048 = { + 0x0048, pci_device_106b_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0049 = { + 0x0049, pci_device_106b_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004b = { + 0x004b, pci_device_106b_004b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004c = { + 0x004c, pci_device_106b_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004f = { + 0x004f, pci_device_106b_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0050 = { + 0x0050, pci_device_106b_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0051 = { + 0x0051, pci_device_106b_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0052 = { + 0x0052, pci_device_106b_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0053 = { + 0x0053, pci_device_106b_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0054 = { + 0x0054, pci_device_106b_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0055 = { + 0x0055, pci_device_106b_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0058 = { + 0x0058, pci_device_106b_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0059 = { + 0x0059, pci_device_106b_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0066 = { + 0x0066, pci_device_106b_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0067 = { + 0x0067, pci_device_106b_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0068 = { + 0x0068, pci_device_106b_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0069 = { + 0x0069, pci_device_106b_0069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006a = { + 0x006a, pci_device_106b_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006b = { + 0x006b, pci_device_106b_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1071_8160 = { + 0x8160, pci_device_1071_8160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1071_8160, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2322 = { + 0x2322, pci_device_1077_2322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2422 = { + 0x2422, pci_device_1077_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2432 = { + 0x2432, pci_device_1077_2432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3010 = { + 0x3010, pci_device_1077_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3022 = { + 0x3022, pci_device_1077_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4010 = { + 0x4010, pci_device_1077_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4022 = { + 0x4022, pci_device_1077_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6312 = { + 0x6312, pci_device_1077_6312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6322 = { + 0x6322, pci_device_1077_6322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6322, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2134 = { + 0x2134, pci_device_107d_2134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2971 = { + 0x2971, pci_device_107d_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2971, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1648 = { + 0x1648, pci_device_108e_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8002 = { + 0x8002, pci_device_108e_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a801 = { + 0xa801, pci_device_108e_a801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_abba = { + 0xabba, pci_device_108e_abba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_abba, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_07a0 = { + 0x07a0, pci_device_1091_07a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_07a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_1091 = { + 0x1091, pci_device_1091_1091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_1091, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1310 = { + 0x1310, pci_device_1093_1310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14e0 = { + 0x14e0, pci_device_1093_14e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14f0 = { + 0x14f0, pci_device_1093_14f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_17d0 = { + 0x17d0, pci_device_1093_17d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_17d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1870 = { + 0x1870, pci_device_1093_1870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1880 = { + 0x1880, pci_device_1093_1880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_18b0 = { + 0x18b0, pci_device_1093_18b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_18b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2410 = { + 0x2410, pci_device_1093_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2890 = { + 0x2890, pci_device_1093_2890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a70 = { + 0x2a70, pci_device_1093_2a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a80 = { + 0x2a80, pci_device_1093_2a80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2c80 = { + 0x2c80, pci_device_1093_2c80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2c80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2ca0 = { + 0x2ca0, pci_device_1093_2ca0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2ca0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70b8 = { + 0x70b8, pci_device_1093_70b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0240 = { + 0x0240, pci_device_1095_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3114 = { + 0x3114, pci_device_1095_3114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3124 = { + 0x3124, pci_device_1095_3124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3132 = { + 0x3132, pci_device_1095_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3512 = { + 0x3512, pci_device_1095_3512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3512, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_032e = { + 0x032e, pci_device_109e_032e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_032e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_3052 = { + 0x3052, pci_device_10a5_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_100a = { + 0x100a, pci_device_10a9_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4001 = { + 0x4001, pci_device_10a9_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4002 = { + 0x4002, pci_device_10a9_4002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8010 = { + 0x8010, pci_device_10a9_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8018 = { + 0x8018, pci_device_10a9_8018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1042 = { + 0x1042, pci_device_10b5_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2540 = { + 0x2540, pci_device_10b5_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6540 = { + 0x6540, pci_device_10b5_6540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6541 = { + 0x6541, pci_device_10b5_6541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6542 = { + 0x6542, pci_device_10b5_6542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8111 = { + 0x8111, pci_device_10b5_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8114 = { + 0x8114, pci_device_10b5_8114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8516 = { + 0x8516, pci_device_10b5_8516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8532 = { + 0x8532, pci_device_10b5_8532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9056 = { + 0x9056, pci_device_10b5_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_bb04 = { + 0xbb04, pci_device_10b5_bb04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_bb04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0013 = { + 0x0013, pci_device_10b7_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0910 = { + 0x0910, pci_device_10b7_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1201 = { + 0x1201, pci_device_10b7_1201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1202 = { + 0x1202, pci_device_10b7_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1700 = { + 0x1700, pci_device_10b7_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6000 = { + 0x6000, pci_device_10b7_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6001 = { + 0x6001, pci_device_10b7_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7770 = { + 0x7770, pci_device_10b7_7770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_80eb = { + 0x80eb, pci_device_10b7_80eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_80eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9202 = { + 0x9202, pci_device_10b7_9202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9210 = { + 0x9210, pci_device_10b7_9210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990a = { + 0x990a, pci_device_10b7_990a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_2802 = { + 0x2802, pci_device_10b8_2802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_2802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b9_0101 = { + 0x0101, pci_device_10b9_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0780 = { + 0x0780, pci_device_10b9_0780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0782 = { + 0x0782, pci_device_10b9_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1573 = { + 0x1573, pci_device_10b9_1573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1672 = { + 0x1672, pci_device_10b9_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1689 = { + 0x1689, pci_device_10b9_1689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1695 = { + 0x1695, pci_device_10b9_1695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1695, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1697 = { + 0x1697, pci_device_10b9_1697, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1697, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3323 = { + 0x3323, pci_device_10b9_3323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5228 = { + 0x5228, pci_device_10b9_5228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5246 = { + 0x5246, pci_device_10b9_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524b = { + 0x524b, pci_device_10b9_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524c = { + 0x524c, pci_device_10b9_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524d = { + 0x524d, pci_device_10b9_524d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524e = { + 0x524e, pci_device_10b9_524e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5263 = { + 0x5263, pci_device_10b9_5263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5281 = { + 0x5281, pci_device_10b9_5281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5287 = { + 0x5287, pci_device_10b9_5287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5288 = { + 0x5288, pci_device_10b9_5288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5289 = { + 0x5289, pci_device_10b9_5289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5450 = { + 0x5450, pci_device_10b9_5450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5461 = { + 0x5461, pci_device_10b9_5461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0304 = { + 0x0304, pci_device_10ba_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0308 = { + 0x0308, pci_device_10ba_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_1002 = { + 0x1002, pci_device_10ba_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cc_0660 = { + 0x0660, pci_device_10cc_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cc_0661 = { + 0x0661, pci_device_10cc_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0661, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0431 = { + 0x0431, pci_device_10d9_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8626 = { + 0x8626, pci_device_10d9_8626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dd_0100 = { + 0x0100, pci_device_10dd_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dd_0100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0034 = { + 0x0034, pci_device_10de_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0035 = { + 0x0035, pci_device_10de_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0036 = { + 0x0036, pci_device_10de_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0037 = { + 0x0037, pci_device_10de_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0038 = { + 0x0038, pci_device_10de_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003a = { + 0x003a, pci_device_10de_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003b = { + 0x003b, pci_device_10de_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003c = { + 0x003c, pci_device_10de_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003d = { + 0x003d, pci_device_10de_003d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003e = { + 0x003e, pci_device_10de_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0040 = { + 0x0040, pci_device_10de_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0041 = { + 0x0041, pci_device_10de_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0042 = { + 0x0042, pci_device_10de_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0043 = { + 0x0043, pci_device_10de_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0045 = { + 0x0045, pci_device_10de_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0046 = { + 0x0046, pci_device_10de_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0048 = { + 0x0048, pci_device_10de_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0049 = { + 0x0049, pci_device_10de_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004e = { + 0x004e, pci_device_10de_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0050 = { + 0x0050, pci_device_10de_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0051 = { + 0x0051, pci_device_10de_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0052 = { + 0x0052, pci_device_10de_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0053 = { + 0x0053, pci_device_10de_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0054 = { + 0x0054, pci_device_10de_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0055 = { + 0x0055, pci_device_10de_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0056 = { + 0x0056, pci_device_10de_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0057 = { + 0x0057, pci_device_10de_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0058 = { + 0x0058, pci_device_10de_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0059 = { + 0x0059, pci_device_10de_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005a = { + 0x005a, pci_device_10de_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005b = { + 0x005b, pci_device_10de_005b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005c = { + 0x005c, pci_device_10de_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005d = { + 0x005d, pci_device_10de_005d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005e = { + 0x005e, pci_device_10de_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005f = { + 0x005f, pci_device_10de_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006c = { + 0x006c, pci_device_10de_006c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006d = { + 0x006d, pci_device_10de_006d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0080 = { + 0x0080, pci_device_10de_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0084 = { + 0x0084, pci_device_10de_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0085 = { + 0x0085, pci_device_10de_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0086 = { + 0x0086, pci_device_10de_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0087 = { + 0x0087, pci_device_10de_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0088 = { + 0x0088, pci_device_10de_0088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008a = { + 0x008a, pci_device_10de_008a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008b = { + 0x008b, pci_device_10de_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008c = { + 0x008c, pci_device_10de_008c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008e = { + 0x008e, pci_device_10de_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0091 = { + 0x0091, pci_device_10de_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0092 = { + 0x0092, pci_device_10de_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0099 = { + 0x0099, pci_device_10de_0099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_009d = { + 0x009d, pci_device_10de_009d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_009d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c0 = { + 0x00c0, pci_device_10de_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c1 = { + 0x00c1, pci_device_10de_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c2 = { + 0x00c2, pci_device_10de_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c3 = { + 0x00c3, pci_device_10de_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c8 = { + 0x00c8, pci_device_10de_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c9 = { + 0x00c9, pci_device_10de_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cc = { + 0x00cc, pci_device_10de_00cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cd = { + 0x00cd, pci_device_10de_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ce = { + 0x00ce, pci_device_10de_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d0 = { + 0x00d0, pci_device_10de_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d1 = { + 0x00d1, pci_device_10de_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d2 = { + 0x00d2, pci_device_10de_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d3 = { + 0x00d3, pci_device_10de_00d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d4 = { + 0x00d4, pci_device_10de_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d5 = { + 0x00d5, pci_device_10de_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d6 = { + 0x00d6, pci_device_10de_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d7 = { + 0x00d7, pci_device_10de_00d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d8 = { + 0x00d8, pci_device_10de_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d9 = { + 0x00d9, pci_device_10de_00d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00da = { + 0x00da, pci_device_10de_00da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00dd = { + 0x00dd, pci_device_10de_00dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00df = { + 0x00df, pci_device_10de_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e0 = { + 0x00e0, pci_device_10de_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e1 = { + 0x00e1, pci_device_10de_00e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e2 = { + 0x00e2, pci_device_10de_00e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e3 = { + 0x00e3, pci_device_10de_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e4 = { + 0x00e4, pci_device_10de_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e5 = { + 0x00e5, pci_device_10de_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e6 = { + 0x00e6, pci_device_10de_00e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e7 = { + 0x00e7, pci_device_10de_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e8 = { + 0x00e8, pci_device_10de_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ea = { + 0x00ea, pci_device_10de_00ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ed = { + 0x00ed, pci_device_10de_00ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ee = { + 0x00ee, pci_device_10de_00ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f0 = { + 0x00f0, pci_device_10de_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f1 = { + 0x00f1, pci_device_10de_00f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f2 = { + 0x00f2, pci_device_10de_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f3 = { + 0x00f3, pci_device_10de_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f8 = { + 0x00f8, pci_device_10de_00f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f9 = { + 0x00f9, pci_device_10de_00f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fa = { + 0x00fa, pci_device_10de_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fb = { + 0x00fb, pci_device_10de_00fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fc = { + 0x00fc, pci_device_10de_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fd = { + 0x00fd, pci_device_10de_00fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fe = { + 0x00fe, pci_device_10de_00fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ff = { + 0x00ff, pci_device_10de_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0140 = { + 0x0140, pci_device_10de_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0141 = { + 0x0141, pci_device_10de_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0142 = { + 0x0142, pci_device_10de_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0144 = { + 0x0144, pci_device_10de_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0145 = { + 0x0145, pci_device_10de_0145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0146 = { + 0x0146, pci_device_10de_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0147 = { + 0x0147, pci_device_10de_0147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0148 = { + 0x0148, pci_device_10de_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0149 = { + 0x0149, pci_device_10de_0149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014e = { + 0x014e, pci_device_10de_014e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014f = { + 0x014f, pci_device_10de_014f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0160 = { + 0x0160, pci_device_10de_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0161 = { + 0x0161, pci_device_10de_0161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0162 = { + 0x0162, pci_device_10de_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0163 = { + 0x0163, pci_device_10de_0163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0164 = { + 0x0164, pci_device_10de_0164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0165 = { + 0x0165, pci_device_10de_0165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0166 = { + 0x0166, pci_device_10de_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0167 = { + 0x0167, pci_device_10de_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0168 = { + 0x0168, pci_device_10de_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0169 = { + 0x0169, pci_device_10de_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0177 = { + 0x0177, pci_device_10de_0177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017d = { + 0x017d, pci_device_10de_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0185 = { + 0x0185, pci_device_10de_0185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0186 = { + 0x0186, pci_device_10de_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0187 = { + 0x0187, pci_device_10de_0187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018c = { + 0x018c, pci_device_10de_018c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018d = { + 0x018d, pci_device_10de_018d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b0 = { + 0x01b0, pci_device_10de_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e0 = { + 0x01e0, pci_device_10de_01e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ea = { + 0x01ea, pci_device_10de_01ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01eb = { + 0x01eb, pci_device_10de_01eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ec = { + 0x01ec, pci_device_10de_01ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ed = { + 0x01ed, pci_device_10de_01ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ee = { + 0x01ee, pci_device_10de_01ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ef = { + 0x01ef, pci_device_10de_01ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0211 = { + 0x0211, pci_device_10de_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0212 = { + 0x0212, pci_device_10de_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0215 = { + 0x0215, pci_device_10de_0215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0221 = { + 0x0221, pci_device_10de_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0240 = { + 0x0240, pci_device_10de_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0241 = { + 0x0241, pci_device_10de_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0242 = { + 0x0242, pci_device_10de_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0243 = { + 0x0243, pci_device_10de_0243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0244 = { + 0x0244, pci_device_10de_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0245 = { + 0x0245, pci_device_10de_0245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0246 = { + 0x0246, pci_device_10de_0246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0247 = { + 0x0247, pci_device_10de_0247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0248 = { + 0x0248, pci_device_10de_0248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0249 = { + 0x0249, pci_device_10de_0249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024a = { + 0x024a, pci_device_10de_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024b = { + 0x024b, pci_device_10de_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024c = { + 0x024c, pci_device_10de_024c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024d = { + 0x024d, pci_device_10de_024d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024e = { + 0x024e, pci_device_10de_024e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024f = { + 0x024f, pci_device_10de_024f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0260 = { + 0x0260, pci_device_10de_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0261 = { + 0x0261, pci_device_10de_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0262 = { + 0x0262, pci_device_10de_0262, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0262, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0263 = { + 0x0263, pci_device_10de_0263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0264 = { + 0x0264, pci_device_10de_0264, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0264, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0265 = { + 0x0265, pci_device_10de_0265, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0265, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0266 = { + 0x0266, pci_device_10de_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0267 = { + 0x0267, pci_device_10de_0267, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0267, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0268 = { + 0x0268, pci_device_10de_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0269 = { + 0x0269, pci_device_10de_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026a = { + 0x026a, pci_device_10de_026a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026b = { + 0x026b, pci_device_10de_026b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026c = { + 0x026c, pci_device_10de_026c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026d = { + 0x026d, pci_device_10de_026d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026e = { + 0x026e, pci_device_10de_026e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026f = { + 0x026f, pci_device_10de_026f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0270 = { + 0x0270, pci_device_10de_0270, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0270, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0271 = { + 0x0271, pci_device_10de_0271, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0271, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0272 = { + 0x0272, pci_device_10de_0272, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0272, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027e = { + 0x027e, pci_device_10de_027e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027f = { + 0x027f, pci_device_10de_027f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0286 = { + 0x0286, pci_device_10de_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_028c = { + 0x028c, pci_device_10de_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02a0 = { + 0x02a0, pci_device_10de_02a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f0 = { + 0x02f0, pci_device_10de_02f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f1 = { + 0x02f1, pci_device_10de_02f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f2 = { + 0x02f2, pci_device_10de_02f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f3 = { + 0x02f3, pci_device_10de_02f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f4 = { + 0x02f4, pci_device_10de_02f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f5 = { + 0x02f5, pci_device_10de_02f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f6 = { + 0x02f6, pci_device_10de_02f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f7 = { + 0x02f7, pci_device_10de_02f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f8 = { + 0x02f8, pci_device_10de_02f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f9 = { + 0x02f9, pci_device_10de_02f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fa = { + 0x02fa, pci_device_10de_02fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fb = { + 0x02fb, pci_device_10de_02fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fc = { + 0x02fc, pci_device_10de_02fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fd = { + 0x02fd, pci_device_10de_02fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fe = { + 0x02fe, pci_device_10de_02fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02ff = { + 0x02ff, pci_device_10de_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0311 = { + 0x0311, pci_device_10de_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0312 = { + 0x0312, pci_device_10de_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0313 = { + 0x0313, pci_device_10de_0313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0314 = { + 0x0314, pci_device_10de_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0316 = { + 0x0316, pci_device_10de_0316, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0316, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0317 = { + 0x0317, pci_device_10de_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0317, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031a = { + 0x031a, pci_device_10de_031a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031b = { + 0x031b, pci_device_10de_031b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031c = { + 0x031c, pci_device_10de_031c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031d = { + 0x031d, pci_device_10de_031d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031e = { + 0x031e, pci_device_10de_031e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031f = { + 0x031f, pci_device_10de_031f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0320 = { + 0x0320, pci_device_10de_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0321 = { + 0x0321, pci_device_10de_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0322 = { + 0x0322, pci_device_10de_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0323 = { + 0x0323, pci_device_10de_0323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0324 = { + 0x0324, pci_device_10de_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0325 = { + 0x0325, pci_device_10de_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0326 = { + 0x0326, pci_device_10de_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0327 = { + 0x0327, pci_device_10de_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0328 = { + 0x0328, pci_device_10de_0328, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0328, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0329 = { + 0x0329, pci_device_10de_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032a = { + 0x032a, pci_device_10de_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032b = { + 0x032b, pci_device_10de_032b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032c = { + 0x032c, pci_device_10de_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032d = { + 0x032d, pci_device_10de_032d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032f = { + 0x032f, pci_device_10de_032f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0330 = { + 0x0330, pci_device_10de_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0331 = { + 0x0331, pci_device_10de_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0332 = { + 0x0332, pci_device_10de_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0333 = { + 0x0333, pci_device_10de_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0334 = { + 0x0334, pci_device_10de_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0338 = { + 0x0338, pci_device_10de_0338, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0338, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_033f = { + 0x033f, pci_device_10de_033f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_033f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0341 = { + 0x0341, pci_device_10de_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0342 = { + 0x0342, pci_device_10de_0342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0343 = { + 0x0343, pci_device_10de_0343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0344 = { + 0x0344, pci_device_10de_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0345 = { + 0x0345, pci_device_10de_0345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0347 = { + 0x0347, pci_device_10de_0347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0348 = { + 0x0348, pci_device_10de_0348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0349 = { + 0x0349, pci_device_10de_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034b = { + 0x034b, pci_device_10de_034b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034c = { + 0x034c, pci_device_10de_034c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034e = { + 0x034e, pci_device_10de_034e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034f = { + 0x034f, pci_device_10de_034f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0360 = { + 0x0360, pci_device_10de_0360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0361 = { + 0x0361, pci_device_10de_0361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0362 = { + 0x0362, pci_device_10de_0362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0363 = { + 0x0363, pci_device_10de_0363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0364 = { + 0x0364, pci_device_10de_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0365 = { + 0x0365, pci_device_10de_0365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0366 = { + 0x0366, pci_device_10de_0366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0367 = { + 0x0367, pci_device_10de_0367, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0367, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0368 = { + 0x0368, pci_device_10de_0368, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0368, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0369 = { + 0x0369, pci_device_10de_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036a = { + 0x036a, pci_device_10de_036a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036c = { + 0x036c, pci_device_10de_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036d = { + 0x036d, pci_device_10de_036d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036e = { + 0x036e, pci_device_10de_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0371 = { + 0x0371, pci_device_10de_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0372 = { + 0x0372, pci_device_10de_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0373 = { + 0x0373, pci_device_10de_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037a = { + 0x037a, pci_device_10de_037a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037e = { + 0x037e, pci_device_10de_037e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037f = { + 0x037f, pci_device_10de_037f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a1 = { + 0xf0a1, pci_device_10df_f0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a5 = { + 0xf0a5, pci_device_10df_f0a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0b5 = { + 0xf0b5, pci_device_10df_f0b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d1 = { + 0xf0d1, pci_device_10df_f0d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d5 = { + 0xf0d5, pci_device_10df_f0d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e1 = { + 0xf0e1, pci_device_10df_f0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e5 = { + 0xf0e5, pci_device_10df_f0e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0f5 = { + 0xf0f5, pci_device_10df_f0f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f701 = { + 0xf701, pci_device_10df_f701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f801 = { + 0xf801, pci_device_10df_f801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f901 = { + 0xf901, pci_device_10df_f901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f981 = { + 0xf981, pci_device_10df_f981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f982 = { + 0xf982, pci_device_10df_f982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fa00 = { + 0xfa00, pci_device_10df_fa00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fa00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fb00 = { + 0xfb00, pci_device_10df_fb00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fb00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc00 = { + 0xfc00, pci_device_10df_fc00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc10 = { + 0xfc10, pci_device_10df_fc10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc20 = { + 0xfc20, pci_device_10df_fc20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fd00 = { + 0xfd00, pci_device_10df_fd00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fd00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fe00 = { + 0xfe00, pci_device_10df_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_ff00 = { + 0xff00, pci_device_10df_ff00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_ff00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0148 = { + 0x0148, pci_device_10e3_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8260 = { + 0x8260, pci_device_10e3_8260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8261 = { + 0x8261, pci_device_10e3_8261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8261, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e4_8029 = { + 0x8029, pci_device_10e4_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e4_8029, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_1072 = { + 0x1072, pci_device_10e8_1072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_1072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_814c = { + 0x814c, pci_device_10e8_814c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_814c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_81e6 = { + 0x81e6, pci_device_10e8_81e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_81e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8291 = { + 0x8291, pci_device_10e8_8291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c4 = { + 0x82c4, pci_device_10e8_82c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c5 = { + 0x82c5, pci_device_10e8_82c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c6 = { + 0x82c6, pci_device_10e8_82c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c7 = { + 0x82c7, pci_device_10e8_82c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82ca = { + 0x82ca, pci_device_10e8_82ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82e2 = { + 0x82e2, pci_device_10e8_82e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8851 = { + 0x8851, pci_device_10e8_8851, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8851, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5252 = { + 0x5252, pci_device_10ea_5252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5252, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_0139 = { + 0x0139, pci_device_10ec_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8180 = { + 0x8180, pci_device_10ec_8180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_0314 = { + 0x0314, pci_device_10ee_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc6 = { + 0x3fc6, pci_device_10ee_3fc6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_8381 = { + 0x8381, pci_device_10ee_8381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_8381, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9502 = { + 0x9502, pci_device_1101_9502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9502, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0x0401 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0007 = { + 0x0007, pci_device_1102_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0008 = { + 0x0008, pci_device_1102_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_100a = { + 0x100a, pci_device_1102_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7005 = { + 0x7005, pci_device_1102_7005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0009 = { + 0x0009, pci_device_1103_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0009, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8401 = { + 0x8401, pci_device_1105_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8470 = { + 0x8470, pci_device_1105_8470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8471 = { + 0x8471, pci_device_1105_8471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8475 = { + 0x8475, pci_device_1105_8475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8476 = { + 0x8476, pci_device_1105_8476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8485 = { + 0x8485, pci_device_1105_8485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8486 = { + 0x8486, pci_device_1105_8486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8486, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0204 = { + 0x0204, pci_device_1106_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0238 = { + 0x0238, pci_device_1106_0238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0259 = { + 0x0259, pci_device_1106_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0269 = { + 0x0269, pci_device_1106_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0282 = { + 0x0282, pci_device_1106_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0290 = { + 0x0290, pci_device_1106_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0296 = { + 0x0296, pci_device_1106_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0308 = { + 0x0308, pci_device_1106_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0314 = { + 0x0314, pci_device_1106_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0591 = { + 0x0591, pci_device_1106_0591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1204 = { + 0x1204, pci_device_1106_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1208 = { + 0x1208, pci_device_1106_1208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1238 = { + 0x1238, pci_device_1106_1238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1258 = { + 0x1258, pci_device_1106_1258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1259 = { + 0x1259, pci_device_1106_1259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1269 = { + 0x1269, pci_device_1106_1269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1282 = { + 0x1282, pci_device_1106_1282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1290 = { + 0x1290, pci_device_1106_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1296 = { + 0x1296, pci_device_1106_1296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1308 = { + 0x1308, pci_device_1106_1308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1314 = { + 0x1314, pci_device_1106_1314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2204 = { + 0x2204, pci_device_1106_2204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2208 = { + 0x2208, pci_device_1106_2208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2238 = { + 0x2238, pci_device_1106_2238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2258 = { + 0x2258, pci_device_1106_2258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2259 = { + 0x2259, pci_device_1106_2259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2269 = { + 0x2269, pci_device_1106_2269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2282 = { + 0x2282, pci_device_1106_2282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2290 = { + 0x2290, pci_device_1106_2290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2296 = { + 0x2296, pci_device_1106_2296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2308 = { + 0x2308, pci_device_1106_2308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2314 = { + 0x2314, pci_device_1106_2314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287a = { + 0x287a, pci_device_1106_287a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287b = { + 0x287b, pci_device_1106_287b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287c = { + 0x287c, pci_device_1106_287c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287d = { + 0x287d, pci_device_1106_287d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287e = { + 0x287e, pci_device_1106_287e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3022 = { + 0x3022, pci_device_1106_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3053 = { + 0x3053, pci_device_1106_3053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3108 = { + 0x3108, pci_device_1106_3108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3113 = { + 0x3113, pci_device_1106_3113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3118 = { + 0x3118, pci_device_1106_3118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3119 = { + 0x3119, pci_device_1106_3119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3149 = { + 0x3149, pci_device_1106_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3164 = { + 0x3164, pci_device_1106_3164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3178 = { + 0x3178, pci_device_1106_3178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3188 = { + 0x3188, pci_device_1106_3188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3204 = { + 0x3204, pci_device_1106_3204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3205 = { + 0x3205, pci_device_1106_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3208 = { + 0x3208, pci_device_1106_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3213 = { + 0x3213, pci_device_1106_3213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3218 = { + 0x3218, pci_device_1106_3218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3227 = { + 0x3227, pci_device_1106_3227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3238 = { + 0x3238, pci_device_1106_3238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3249 = { + 0x3249, pci_device_1106_3249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3258 = { + 0x3258, pci_device_1106_3258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3259 = { + 0x3259, pci_device_1106_3259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3269 = { + 0x3269, pci_device_1106_3269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3282 = { + 0x3282, pci_device_1106_3282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3288 = { + 0x3288, pci_device_1106_3288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3290 = { + 0x3290, pci_device_1106_3290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3296 = { + 0x3296, pci_device_1106_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3337 = { + 0x3337, pci_device_1106_3337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3349 = { + 0x3349, pci_device_1106_3349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337a = { + 0x337a, pci_device_1106_337a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337b = { + 0x337b, pci_device_1106_337b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4149 = { + 0x4149, pci_device_1106_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4204 = { + 0x4204, pci_device_1106_4204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4208 = { + 0x4208, pci_device_1106_4208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4238 = { + 0x4238, pci_device_1106_4238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4258 = { + 0x4258, pci_device_1106_4258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4259 = { + 0x4259, pci_device_1106_4259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4269 = { + 0x4269, pci_device_1106_4269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4282 = { + 0x4282, pci_device_1106_4282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4290 = { + 0x4290, pci_device_1106_4290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4296 = { + 0x4296, pci_device_1106_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4308 = { + 0x4308, pci_device_1106_4308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4314 = { + 0x4314, pci_device_1106_4314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5208 = { + 0x5208, pci_device_1106_5208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5238 = { + 0x5238, pci_device_1106_5238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5290 = { + 0x5290, pci_device_1106_5290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5308 = { + 0x5308, pci_device_1106_5308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7204 = { + 0x7204, pci_device_1106_7204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7205 = { + 0x7205, pci_device_1106_7205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7208 = { + 0x7208, pci_device_1106_7208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7238 = { + 0x7238, pci_device_1106_7238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7258 = { + 0x7258, pci_device_1106_7258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7259 = { + 0x7259, pci_device_1106_7259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7269 = { + 0x7269, pci_device_1106_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7282 = { + 0x7282, pci_device_1106_7282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7290 = { + 0x7290, pci_device_1106_7290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7296 = { + 0x7296, pci_device_1106_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7308 = { + 0x7308, pci_device_1106_7308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7314 = { + 0x7314, pci_device_1106_7314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a208 = { + 0xa208, pci_device_1106_a208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a238 = { + 0xa238, pci_device_1106_a238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b113 = { + 0xb113, pci_device_1106_b113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b115 = { + 0xb115, pci_device_1106_b115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b188 = { + 0xb188, pci_device_1106_b188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b198 = { + 0xb198, pci_device_1106_b198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b213 = { + 0xb213, pci_device_1106_b213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c208 = { + 0xc208, pci_device_1106_c208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c238 = { + 0xc238, pci_device_1106_c238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d104 = { + 0xd104, pci_device_1106_d104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d208 = { + 0xd208, pci_device_1106_d208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d213 = { + 0xd213, pci_device_1106_d213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d238 = { + 0xd238, pci_device_1106_d238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e208 = { + 0xe208, pci_device_1106_e208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e238 = { + 0xe238, pci_device_1106_e238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f208 = { + 0xf208, pci_device_1106_f208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f238 = { + 0xf238, pci_device_1106_f238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f238, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0006 = { + 0x0006, pci_device_110a_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0015 = { + 0x0015, pci_device_110a_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_001d = { + 0x001d, pci_device_110a_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007b = { + 0x007b, pci_device_110a_007b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007c = { + 0x007c, pci_device_110a_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007d = { + 0x007d, pci_device_110a_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2101 = { + 0x2101, pci_device_110a_2101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2104 = { + 0x2104, pci_device_110a_2104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_3142 = { + 0x3142, pci_device_110a_3142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_3142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4021 = { + 0x4021, pci_device_110a_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4029 = { + 0x4029, pci_device_110a_4029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_d301 = { + 0xd301, pci_device_1113_d301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_d301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_ec02 = { + 0xec02, pci_device_1113_ec02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_ec02, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1114_0506 = { + 0x0506, pci_device_1114_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1114_0506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0010 = { + 0x0010, pci_device_1119_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0011 = { + 0x0011, pci_device_1119_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0012 = { + 0x0012, pci_device_1119_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0013 = { + 0x0013, pci_device_1119_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_02ff = { + 0x02ff, pci_device_1119_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_1203 = { + 0x1203, pci_device_111a_1203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_1203, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0004 = { + 0x0004, pci_device_111d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0005 = { + 0x0005, pci_device_111d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0008 = { + 0x0008, pci_device_112f_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5400 = { + 0x5400, pci_device_1131_5400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5402 = { + 0x5402, pci_device_1131_5402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7135 = { + 0x7135, pci_device_1131_7135, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7135, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_9730 = { + 0x9730, pci_device_1131_9730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_9730, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e006 = { + 0xe006, pci_device_1133_e006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e007 = { + 0xe007, pci_device_1133_e007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e008 = { + 0xe008, pci_device_1133_e008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e009 = { + 0xe009, pci_device_1133_e009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00a = { + 0xe00a, pci_device_1133_e00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00c = { + 0xe00c, pci_device_1133_e00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00d = { + 0xe00d, pci_device_1133_e00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00e = { + 0xe00e, pci_device_1133_e00e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e011 = { + 0xe011, pci_device_1133_e011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e013 = { + 0xe013, pci_device_1133_e013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e015 = { + 0xe015, pci_device_1133_e015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e016 = { + 0xe016, pci_device_1133_e016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e017 = { + 0xe017, pci_device_1133_e017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e019 = { + 0xe019, pci_device_1133_e019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01a = { + 0xe01a, pci_device_1133_e01a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01b = { + 0xe01b, pci_device_1133_e01b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01c = { + 0xe01c, pci_device_1133_e01c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01e = { + 0xe01e, pci_device_1133_e01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e020 = { + 0xe020, pci_device_1133_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e024 = { + 0xe024, pci_device_1133_e024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e028 = { + 0xe028, pci_device_1133_e028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02a = { + 0xe02a, pci_device_1133_e02a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02c = { + 0xe02c, pci_device_1133_e02c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1134_0002 = { + 0x0002, pci_device_1134_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f020 = { + 0xf020, pci_device_1145_f020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4500 = { + 0x4500, pci_device_1148_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9000 = { + 0x9000, pci_device_1148_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9843 = { + 0x9843, pci_device_1148_9843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9e00 = { + 0x9e00, pci_device_1148_9e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9e00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0013 = { + 0x0013, pci_device_114f_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0028 = { + 0x0028, pci_device_114f_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0029 = { + 0x0029, pci_device_114f_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0043 = { + 0x0043, pci_device_114f_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0044 = { + 0x0044, pci_device_114f_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0045 = { + 0x0045, pci_device_114f_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_004e = { + 0x004e, pci_device_114f_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b0 = { + 0x00b0, pci_device_114f_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b1 = { + 0x00b1, pci_device_114f_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c8 = { + 0x00c8, pci_device_114f_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c9 = { + 0x00c9, pci_device_114f_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00ca = { + 0x00ca, pci_device_114f_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00cb = { + 0x00cb, pci_device_114f_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d0 = { + 0x00d0, pci_device_114f_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d1 = { + 0x00d1, pci_device_114f_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_00d4 = { + 0x00d4, pci_device_115d_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0000 = { + 0x0000, pci_device_1166_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0006 = { + 0x0006, pci_device_1166_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0036 = { + 0x0036, pci_device_1166_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0101 = { + 0x0101, pci_device_1166_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0104 = { + 0x0104, pci_device_1166_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0110 = { + 0x0110, pci_device_1166_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0130 = { + 0x0130, pci_device_1166_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0132 = { + 0x0132, pci_device_1166_0132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0205 = { + 0x0205, pci_device_1166_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0214 = { + 0x0214, pci_device_1166_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0217 = { + 0x0217, pci_device_1166_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0223 = { + 0x0223, pci_device_1166_0223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0230 = { + 0x0230, pci_device_1166_0230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0234 = { + 0x0234, pci_device_1166_0234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0240 = { + 0x0240, pci_device_1166_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0241 = { + 0x0241, pci_device_1166_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0242 = { + 0x0242, pci_device_1166_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024a = { + 0x024a, pci_device_1166_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0102 = { + 0x0102, pci_device_1179_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_117c_0030 = { + 0x0030, pci_device_117c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_117c_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0511 = { + 0x0511, pci_device_1180_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0554 = { + 0x0554, pci_device_1180_0554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0575 = { + 0x0575, pci_device_1180_0575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0576 = { + 0x0576, pci_device_1180_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0592 = { + 0x0592, pci_device_1180_0592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0811 = { + 0x0811, pci_device_1180_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0822 = { + 0x0822, pci_device_1180_0822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0841 = { + 0x0841, pci_device_1180_0841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0852 = { + 0x0852, pci_device_1180_0852, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0852, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1025 = { + 0x1025, pci_device_1186_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1026 = { + 0x1026, pci_device_1186_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1043 = { + 0x1043, pci_device_1186_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1541 = { + 0x1541, pci_device_1186_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_2027 = { + 0x2027, pci_device_1186_2027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_2027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3203 = { + 0x3203, pci_device_1186_3203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3300 = { + 0x3300, pci_device_1186_3300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a03 = { + 0x3a03, pci_device_1186_3a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a04 = { + 0x3a04, pci_device_1186_3a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a05 = { + 0x3a05, pci_device_1186_3a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a07 = { + 0x3a07, pci_device_1186_3a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a08 = { + 0x3a08, pci_device_1186_3a08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a10 = { + 0x3a10, pci_device_1186_3a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a11 = { + 0x3a11, pci_device_1186_3a11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a12 = { + 0x3a12, pci_device_1186_3a12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a13 = { + 0x3a13, pci_device_1186_3a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a14 = { + 0x3a14, pci_device_1186_3a14, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a14, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a63 = { + 0x3a63, pci_device_1186_3a63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4300 = { + 0x4300, pci_device_1186_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4c00 = { + 0x4c00, pci_device_1186_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_8400 = { + 0x8400, pci_device_1186_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_8400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8060 = { + 0x8060, pci_device_1191_8060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8080 = { + 0x8080, pci_device_1191_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8081 = { + 0x8081, pci_device_1191_8081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_808a = { + 0x808a, pci_device_1191_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_808a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1197_010c = { + 0x010c, pci_device_1197_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1197_010c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_138f = { + 0x138f, pci_device_11ab_138f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_138f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa6 = { + 0x1fa6, pci_device_11ab_1fa6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa7 = { + 0x1fa7, pci_device_11ab_1fa7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1faa = { + 0x1faa, pci_device_11ab_1faa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1faa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4320 = { + 0x4320, pci_device_11ab_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4340 = { + 0x4340, pci_device_11ab_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4341 = { + 0x4341, pci_device_11ab_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4342 = { + 0x4342, pci_device_11ab_4342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4343 = { + 0x4343, pci_device_11ab_4343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4344 = { + 0x4344, pci_device_11ab_4344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4345 = { + 0x4345, pci_device_11ab_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4346 = { + 0x4346, pci_device_11ab_4346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4347 = { + 0x4347, pci_device_11ab_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4350 = { + 0x4350, pci_device_11ab_4350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4351 = { + 0x4351, pci_device_11ab_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4352 = { + 0x4352, pci_device_11ab_4352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4360 = { + 0x4360, pci_device_11ab_4360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4361 = { + 0x4361, pci_device_11ab_4361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4362 = { + 0x4362, pci_device_11ab_4362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4363 = { + 0x4363, pci_device_11ab_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5005 = { + 0x5005, pci_device_11ab_5005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5040 = { + 0x5040, pci_device_11ab_5040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5041 = { + 0x5041, pci_device_11ab_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5080 = { + 0x5080, pci_device_11ab_5080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5081 = { + 0x5081, pci_device_11ab_5081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6041 = { + 0x6041, pci_device_11ab_6041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6081 = { + 0x6081, pci_device_11ab_6081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6460 = { + 0x6460, pci_device_11ab_6460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6480 = { + 0x6480, pci_device_11ab_6480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11af_0001 = { + 0x0001, pci_device_11af_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11af_ee40 = { + 0xee40, pci_device_11af_ee40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_ee40, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bd_bede = { + 0xbede, pci_device_11bd_bede, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_bede, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048c = { + 0x048c, pci_device_11c1_048c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048f = { + 0x048f, pci_device_11c1_048f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_8110 = { + 0x8110, pci_device_11c1_8110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_8110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab10 = { + 0xab10, pci_device_11c1_ab10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab11 = { + 0xab11, pci_device_11c1_ab11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab20 = { + 0xab20, pci_device_11c1_ab20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab21 = { + 0xab21, pci_device_11c1_ab21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab30 = { + 0xab30, pci_device_11c1_ab30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab30, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1535 = { + 0x1535, pci_device_11d4_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_5340 = { + 0x5340, pci_device_11d4_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_5340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_0001 = { + 0x0001, pci_device_11e3_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000d = { + 0x000d, pci_device_11fe_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000e = { + 0x000e, pci_device_11fe_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000f = { + 0x000f, pci_device_11fe_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0801 = { + 0x0801, pci_device_11fe_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0802 = { + 0x0802, pci_device_11fe_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0803 = { + 0x0803, pci_device_11fe_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0805 = { + 0x0805, pci_device_11fe_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080c = { + 0x080c, pci_device_11fe_080c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080d = { + 0x080d, pci_device_11fe_080d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0812 = { + 0x0812, pci_device_11fe_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0903 = { + 0x0903, pci_device_11fe_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ff_0003 = { + 0x0003, pci_device_11ff_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ff_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7110 = { + 0x7110, pci_device_1217_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7112 = { + 0x7112, pci_device_1217_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7113 = { + 0x7113, pci_device_1217_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7114 = { + 0x7114, pci_device_1217_7114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7134 = { + 0x7134, pci_device_1217_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_71e2 = { + 0x71e2, pci_device_1217_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7212 = { + 0x7212, pci_device_1217_7212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7213 = { + 0x7213, pci_device_1217_7213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7223 = { + 0x7223, pci_device_1217_7223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7233 = { + 0x7233, pci_device_1217_7233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7233, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1227_0006 = { + 0x0006, pci_device_1227_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1227_0023 = { + 0x0023, pci_device_1227_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_1400 = { + 0x1400, pci_device_122d_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_6562 = { + 0x6562, pci_device_1242_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_656a = { + 0x656a, pci_device_1242_656a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_656a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2700 = { + 0x2700, pci_device_1244_2700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2900 = { + 0x2900, pci_device_1244_2900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2900, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a117 = { + 0xa117, pci_device_1259_a117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a117, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a120 = { + 0xa120, pci_device_1259_a120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0101 = { + 0x0101, pci_device_125c_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3872 = { + 0x3872, pci_device_1260_3872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3886 = { + 0x3886, pci_device_1260_3886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3890 = { + 0x3890, pci_device_1260_3890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_ffff = { + 0xffff, pci_device_1260_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_126c_1211 = { + 0x1211, pci_device_126c_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126c_126c = { + 0x126c, pci_device_126c_126c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_126c, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0501 = { + 0x0501, pci_device_126f_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0510 = { + 0x0510, pci_device_126f_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0730 = { + 0x0730, pci_device_126f_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1171 = { + 0x1171, pci_device_1274_1171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1278_0710 = { + 0x0710, pci_device_1278_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0710, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0060 = { + 0x0060, pci_device_1279_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0061 = { + 0x0061, pci_device_1279_0061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8211 = { + 0x8211, pci_device_1283_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8212 = { + 0x8212, pci_device_1283_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8872 = { + 0x8872, pci_device_1283_8872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12a3_8105 = { + 0x8105, pci_device_12a3_8105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12a3_8105, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_0000 = { + 0x0000, pci_device_12ab_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_0002 = { + 0x0002, pci_device_12ab_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_fff3 = { + 0xfff3, pci_device_12ab_fff3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_fff3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_ffff = { + 0xffff, pci_device_12ab_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_00fa = { + 0x00fa, pci_device_12ae_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_00fa, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c4_0001 = { + 0x0001, pci_device_12c4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0002 = { + 0x0002, pci_device_12c4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0003 = { + 0x0003, pci_device_12c4_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0004 = { + 0x0004, pci_device_12c4_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0005 = { + 0x0005, pci_device_12c4_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0006 = { + 0x0006, pci_device_12c4_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0007 = { + 0x0007, pci_device_12c4_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0008 = { + 0x0008, pci_device_12c4_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0009 = { + 0x0009, pci_device_12c4_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000a = { + 0x000a, pci_device_12c4_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000b = { + 0x000b, pci_device_12c4_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000c = { + 0x000c, pci_device_12c4_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000d = { + 0x000d, pci_device_12c4_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0100 = { + 0x0100, pci_device_12c4_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0201 = { + 0x0201, pci_device_12c4_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0202 = { + 0x0202, pci_device_12c4_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0300 = { + 0x0300, pci_device_12c4_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0301 = { + 0x0301, pci_device_12c4_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0302 = { + 0x0302, pci_device_12c4_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0310 = { + 0x0310, pci_device_12c4_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0311 = { + 0x0311, pci_device_12c4_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0312 = { + 0x0312, pci_device_12c4_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0320 = { + 0x0320, pci_device_12c4_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0321 = { + 0x0321, pci_device_12c4_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0322 = { + 0x0322, pci_device_12c4_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0330 = { + 0x0330, pci_device_12c4_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0331 = { + 0x0331, pci_device_12c4_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0332 = { + 0x0332, pci_device_12c4_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0332, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d4_0200 = { + 0x0200, pci_device_12d4_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d4_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d5_0003 = { + 0x0003, pci_device_12d5_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d5_1000 = { + 0x1000, pci_device_12d5_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_1000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d8_8150 = { + 0x8150, pci_device_12d8_8150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d8_8150, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d9_0002 = { + 0x0002, pci_device_12d9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0004 = { + 0x0004, pci_device_12d9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0005 = { + 0x0005, pci_device_12d9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12de_0200 = { + 0x0200, pci_device_12de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12de_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12fb_0001 = { + 0x0001, pci_device_12fb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_00f5 = { + 0x00f5, pci_device_12fb_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_02ad = { + 0x02ad, pci_device_12fb_02ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_02ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_2adc = { + 0x2adc, pci_device_12fb_2adc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_2adc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3100 = { + 0x3100, pci_device_12fb_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3500 = { + 0x3500, pci_device_12fb_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_4d4f = { + 0x4d4f, pci_device_12fb_4d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_4d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_8120 = { + 0x8120, pci_device_12fb_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_da62 = { + 0xda62, pci_device_12fb_da62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_da62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_db62 = { + 0xdb62, pci_device_12fb_db62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_db62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dc62 = { + 0xdc62, pci_device_12fb_dc62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dc62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dd62 = { + 0xdd62, pci_device_12fb_dd62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dd62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_eddc = { + 0xeddc, pci_device_12fb_eddc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_eddc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_fa01 = { + 0xfa01, pci_device_12fb_fa01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_fa01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004d = { + 0x004d, pci_device_1307_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0052 = { + 0x0052, pci_device_1307_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0054 = { + 0x0054, pci_device_1307_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_005e = { + 0x005e, pci_device_1307_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_005e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_2850 = { + 0x2850, pci_device_1317_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_5120 = { + 0x5120, pci_device_1317_5120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_5120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8201 = { + 0x8201, pci_device_1317_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8211 = { + 0x8211, pci_device_1317_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_9511 = { + 0x9511, pci_device_1317_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2081 = { + 0x2081, pci_device_131f_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2081, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1331_0030 = { + 0x0030, pci_device_1331_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8200 = { + 0x8200, pci_device_1331_8200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8201 = { + 0x8201, pci_device_1331_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8202 = { + 0x8202, pci_device_1331_8202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8210 = { + 0x8210, pci_device_1331_8210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_5425 = { + 0x5425, pci_device_1332_5425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_6140 = { + 0x6140, pci_device_1332_6140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_6140, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_2189 = { + 0x2189, pci_device_134d_2189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_2486 = { + 0x2486, pci_device_134d_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_5101 = { + 0x5101, pci_device_135e_5101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_5101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1360_0101 = { + 0x0101, pci_device_1360_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0102 = { + 0x0102, pci_device_1360_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0103 = { + 0x0103, pci_device_1360_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0201 = { + 0x0201, pci_device_1360_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0202 = { + 0x0202, pci_device_1360_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0203 = { + 0x0203, pci_device_1360_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0301 = { + 0x0301, pci_device_1360_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0302 = { + 0x0302, pci_device_1360_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0302, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136b_ff01 = { + 0xff01, pci_device_136b_ff01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136b_ff01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1371_434e = { + 0x434e, pci_device_1371_434e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1371_434e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1374_0024 = { + 0x0024, pci_device_1374_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0025 = { + 0x0025, pci_device_1374_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0026 = { + 0x0026, pci_device_1374_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0027 = { + 0x0027, pci_device_1374_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0029 = { + 0x0029, pci_device_1374_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002a = { + 0x002a, pci_device_1374_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002b = { + 0x002b, pci_device_1374_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002c = { + 0x002c, pci_device_1374_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002d = { + 0x002d, pci_device_1374_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002e = { + 0x002e, pci_device_1374_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002f = { + 0x002f, pci_device_1374_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0030 = { + 0x0030, pci_device_1374_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0031 = { + 0x0031, pci_device_1374_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0032 = { + 0x0032, pci_device_1374_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0034 = { + 0x0034, pci_device_1374_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0035 = { + 0x0035, pci_device_1374_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0036 = { + 0x0036, pci_device_1374_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0037 = { + 0x0037, pci_device_1374_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0038 = { + 0x0038, pci_device_1374_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0039 = { + 0x0039, pci_device_1374_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_003a = { + 0x003a, pci_device_1374_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_003a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_137a_0001 = { + 0x0001, pci_device_137a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_137a_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1382_0001 = { + 0x0001, pci_device_1382_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2008 = { + 0x2008, pci_device_1382_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2088 = { + 0x2088, pci_device_1382_2088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_20c8 = { + 0x20c8, pci_device_1382_20c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_20c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4008 = { + 0x4008, pci_device_1382_4008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4010 = { + 0x4010, pci_device_1382_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4048 = { + 0x4048, pci_device_1382_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4088 = { + 0x4088, pci_device_1382_4088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4248 = { + 0x4248, pci_device_1382_4248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4248, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_0013 = { + 0x0013, pci_device_1385_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_311a = { + 0x311a, pci_device_1385_311a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_311a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4105 = { + 0x4105, pci_device_1385_4105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4400 = { + 0x4400, pci_device_1385_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4600 = { + 0x4600, pci_device_1385_4600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4601 = { + 0x4601, pci_device_1385_4601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4610 = { + 0x4610, pci_device_1385_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4800 = { + 0x4800, pci_device_1385_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4900 = { + 0x4900, pci_device_1385_4900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4a00 = { + 0x4a00, pci_device_1385_4a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4b00 = { + 0x4b00, pci_device_1385_4b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4c00 = { + 0x4c00, pci_device_1385_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4e00 = { + 0x4e00, pci_device_1385_4e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4f00 = { + 0x4f00, pci_device_1385_4f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6b00 = { + 0x6b00, pci_device_1385_6b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f004 = { + 0xf004, pci_device_1385_f004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1141 = { + 0x1141, pci_device_1393_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_16b8 = { + 0x16b8, pci_device_1397_16b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_16b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_001d = { + 0x001d, pci_device_13a3_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0020 = { + 0x0020, pci_device_13a3_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0026 = { + 0x0026, pci_device_13a3_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0026, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0152 = { + 0x0152, pci_device_13a8_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0154 = { + 0x0154, pci_device_13a8_0154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0020 = { + 0x0020, pci_device_13c0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0030 = { + 0x0030, pci_device_13c0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0210 = { + 0x0210, pci_device_13c0_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1003 = { + 0x1003, pci_device_13c1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c6_0520 = { + 0x0520, pci_device_13c6_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0620 = { + 0x0620, pci_device_13c6_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0820 = { + 0x0820, pci_device_13c6_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d0_2200 = { + 0x2200, pci_device_13d0_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab03 = { + 0xab03, pci_device_13d1_ab03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab08 = { + 0xab08, pci_device_13d1_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0200 = { + 0x0200, pci_device_13f0_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_1023 = { + 0x1023, pci_device_13f0_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_1023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0011 = { + 0x0011, pci_device_13f6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1240 = { + 0x1240, pci_device_13fe_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1600 = { + 0x1600, pci_device_13fe_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1733 = { + 0x1733, pci_device_13fe_1733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1752 = { + 0x1752, pci_device_13fe_1752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1754 = { + 0x1754, pci_device_13fe_1754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0110 = { + 0x0110, pci_device_1407_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0111 = { + 0x0111, pci_device_1407_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0120 = { + 0x0120, pci_device_1407_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0121 = { + 0x0121, pci_device_1407_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0180 = { + 0x0180, pci_device_1407_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0181 = { + 0x0181, pci_device_1407_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0220 = { + 0x0220, pci_device_1407_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0221 = { + 0x0221, pci_device_1407_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9510 = { + 0x9510, pci_device_1415_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9523 = { + 0x9523, pci_device_1415_9523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9523, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1420_8002 = { + 0x8002, pci_device_1420_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1420_8003 = { + 0x8003, pci_device_1420_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1425_000b = { + 0x000b, pci_device_1425_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1425_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_142e_4020 = { + 0x4020, pci_device_142e_4020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_142e_4337 = { + 0x4337, pci_device_142e_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4337, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1432_9130 = { + 0x9130, pci_device_1432_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1432_9130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8164 = { + 0x8164, pci_device_144a_8164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1458_0c11 = { + 0x0c11, pci_device_1458_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1458_e911 = { + 0xe911, pci_device_1458_e911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_e911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1461_a3ce = { + 0xa3ce, pci_device_1461_a3ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_a3ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1461_a3cf = { + 0xa3cf, pci_device_1461_a3cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_a3cf, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1462_5501 = { + 0x5501, pci_device_1462_5501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_5501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6819 = { + 0x6819, pci_device_1462_6819, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6819, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6825 = { + 0x6825, pci_device_1462_6825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_8725 = { + 0x8725, pci_device_1462_8725, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_8725, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9000 = { + 0x9000, pci_device_1462_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9110 = { + 0x9110, pci_device_1462_9110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9119 = { + 0x9119, pci_device_1462_9119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9591 = { + 0x9591, pci_device_1462_9591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9591, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_146c_1430 = { + 0x1430, pci_device_146c_1430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_146c_1430, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1497_1497 = { + 0x1497, pci_device_1497_1497, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1497_1497, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1498_21cd = { + 0x21cd, pci_device_1498_21cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_30c8 = { + 0x30c8, pci_device_1498_30c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_30c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_149d_0001 = { + 0x0001, pci_device_149d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_149d_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a505 = { + 0xa505, pci_device_14b9_a505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a506 = { + 0xa506, pci_device_14b9_a506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14c1_8043 = { + 0x8043, pci_device_14c1_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_8043, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d9_0010 = { + 0x0010, pci_device_14d9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d9_9000 = { + 0x9000, pci_device_14d9_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_9000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_0800 = { + 0x0800, pci_device_14e4_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0804 = { + 0x0804, pci_device_14e4_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0805 = { + 0x0805, pci_device_14e4_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0806 = { + 0x0806, pci_device_14e4_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080b = { + 0x080b, pci_device_14e4_080b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080f = { + 0x080f, pci_device_14e4_080f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0811 = { + 0x0811, pci_device_14e4_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0816 = { + 0x0816, pci_device_14e4_0816, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0816, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1600 = { + 0x1600, pci_device_14e4_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1601 = { + 0x1601, pci_device_14e4_1601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164a = { + 0x164a, pci_device_14e4_164a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164c = { + 0x164c, pci_device_14e4_164c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1654 = { + 0x1654, pci_device_14e4_1654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1659 = { + 0x1659, pci_device_14e4_1659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165e = { + 0x165e, pci_device_14e4_165e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1668 = { + 0x1668, pci_device_14e4_1668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166a = { + 0x166a, pci_device_14e4_166a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166b = { + 0x166b, pci_device_14e4_166b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166e = { + 0x166e, pci_device_14e4_166e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1677 = { + 0x1677, pci_device_14e4_1677, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1677, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1678 = { + 0x1678, pci_device_14e4_1678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167d = { + 0x167d, pci_device_14e4_167d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167e = { + 0x167e, pci_device_14e4_167e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169c = { + 0x169c, pci_device_14e4_169c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169d = { + 0x169d, pci_device_14e4_169d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16aa = { + 0x16aa, pci_device_14e4_16aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16ac = { + 0x16ac, pci_device_14e4_16ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16dd = { + 0x16dd, pci_device_14e4_16dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16f7 = { + 0x16f7, pci_device_14e4_16f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fd = { + 0x16fd, pci_device_14e4_16fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fe = { + 0x16fe, pci_device_14e4_16fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170c = { + 0x170c, pci_device_14e4_170c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170d = { + 0x170d, pci_device_14e4_170d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170e = { + 0x170e, pci_device_14e4_170e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3352 = { + 0x3352, pci_device_14e4_3352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3360 = { + 0x3360, pci_device_14e4_3360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4305 = { + 0x4305, pci_device_14e4_4305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4306 = { + 0x4306, pci_device_14e4_4306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4307 = { + 0x4307, pci_device_14e4_4307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4310 = { + 0x4310, pci_device_14e4_4310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4312 = { + 0x4312, pci_device_14e4_4312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4313 = { + 0x4313, pci_device_14e4_4313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4315 = { + 0x4315, pci_device_14e4_4315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4318 = { + 0x4318, pci_device_14e4_4318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4319 = { + 0x4319, pci_device_14e4_4319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4320 = { + 0x4320, pci_device_14e4_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4321 = { + 0x4321, pci_device_14e4_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4322 = { + 0x4322, pci_device_14e4_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4324 = { + 0x4324, pci_device_14e4_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4325 = { + 0x4325, pci_device_14e4_4325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4326 = { + 0x4326, pci_device_14e4_4326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4403 = { + 0x4403, pci_device_14e4_4403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4430 = { + 0x4430, pci_device_14e4_4430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4432 = { + 0x4432, pci_device_14e4_4432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4610 = { + 0x4610, pci_device_14e4_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4611 = { + 0x4611, pci_device_14e4_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4612 = { + 0x4612, pci_device_14e4_4612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4613 = { + 0x4613, pci_device_14e4_4613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4614 = { + 0x4614, pci_device_14e4_4614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4615 = { + 0x4615, pci_device_14e4_4615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4704 = { + 0x4704, pci_device_14e4_4704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4704, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4705 = { + 0x4705, pci_device_14e4_4705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4705, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4706 = { + 0x4706, pci_device_14e4_4706, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4706, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4707 = { + 0x4707, pci_device_14e4_4707, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4707, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4708 = { + 0x4708, pci_device_14e4_4708, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4708, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4710 = { + 0x4710, pci_device_14e4_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4711 = { + 0x4711, pci_device_14e4_4711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4712 = { + 0x4712, pci_device_14e4_4712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4713 = { + 0x4713, pci_device_14e4_4713, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4713, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4714 = { + 0x4714, pci_device_14e4_4714, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4714, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4715 = { + 0x4715, pci_device_14e4_4715, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4715, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4716 = { + 0x4716, pci_device_14e4_4716, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4716, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4717 = { + 0x4717, pci_device_14e4_4717, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4717, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4718 = { + 0x4718, pci_device_14e4_4718, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4718, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4720 = { + 0x4720, pci_device_14e4_4720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5365 = { + 0x5365, pci_device_14e4_5365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5600 = { + 0x5600, pci_device_14e4_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5605 = { + 0x5605, pci_device_14e4_5605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5615 = { + 0x5615, pci_device_14e4_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5625 = { + 0x5625, pci_device_14e4_5625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5645 = { + 0x5645, pci_device_14e4_5645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5670 = { + 0x5670, pci_device_14e4_5670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5680 = { + 0x5680, pci_device_14e4_5680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5690 = { + 0x5690, pci_device_14e4_5690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5691 = { + 0x5691, pci_device_14e4_5691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5692 = { + 0x5692, pci_device_14e4_5692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5822 = { + 0x5822, pci_device_14e4_5822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5823 = { + 0x5823, pci_device_14e4_5823, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5823, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5824 = { + 0x5824, pci_device_14e4_5824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5840 = { + 0x5840, pci_device_14e4_5840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5841 = { + 0x5841, pci_device_14e4_5841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5850 = { + 0x5850, pci_device_14e4_5850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5850, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab07 = { + 0xab07, pci_device_14ea_ab07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab08 = { + 0xab08, pci_device_14ea_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1085 = { + 0x1085, pci_device_14f1_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1620 = { + 0x1620, pci_device_14f1_1620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1621 = { + 0x1621, pci_device_14f1_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1622 = { + 0x1622, pci_device_14f1_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1811 = { + 0x1811, pci_device_14f1_1811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f02 = { + 0x2f02, pci_device_14f1_2f02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f11 = { + 0x2f11, pci_device_14f1_2f11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f20 = { + 0x2f20, pci_device_14f1_2f20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8800 = { + 0x8800, pci_device_14f1_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8801 = { + 0x8801, pci_device_14f1_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8802 = { + 0x8802, pci_device_14f1_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8804 = { + 0x8804, pci_device_14f1_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8811 = { + 0x8811, pci_device_14f1_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f2_0120 = { + 0x0120, pci_device_14f2_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0121 = { + 0x0121, pci_device_14f2_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0122 = { + 0x0122, pci_device_14f2_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0123 = { + 0x0123, pci_device_14f2_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0124 = { + 0x0124, pci_device_14f2_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0124, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f3_2030 = { + 0x2030, pci_device_14f3_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2050 = { + 0x2050, pci_device_14f3_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2060 = { + 0x2060, pci_device_14f3_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2060, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f8_2077 = { + 0x2077, pci_device_14f8_2077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f8_2077, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14fc_0000 = { + 0x0000, pci_device_14fc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0001 = { + 0x0001, pci_device_14fc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1500_1360 = { + 0x1360, pci_device_1500_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1500_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0800 = { + 0x0800, pci_device_1516_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0891 = { + 0x0891, pci_device_1516_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151c_0003 = { + 0x0003, pci_device_151c_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151c_4000 = { + 0x4000, pci_device_151c_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_0510 = { + 0x0510, pci_device_1524_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0520 = { + 0x0520, pci_device_1524_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0530 = { + 0x0530, pci_device_1524_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0550 = { + 0x0550, pci_device_1524_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0610 = { + 0x0610, pci_device_1524_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1411 = { + 0x1411, pci_device_1524_1411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1412 = { + 0x1412, pci_device_1524_1412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1421 = { + 0x1421, pci_device_1524_1421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1422 = { + 0x1422, pci_device_1524_1422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1422, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1538_0303 = { + 0x0303, pci_device_1538_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1538_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153b_1144 = { + 0x1144, pci_device_153b_1144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1147 = { + 0x1147, pci_device_153b_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1158 = { + 0x1158, pci_device_153b_1158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153f_0001 = { + 0x0001, pci_device_153f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1578_5615 = { + 0x5615, pci_device_1578_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1578_5615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0405 = { + 0x0405, pci_device_15ad_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0720 = { + 0x0720, pci_device_15ad_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0720, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a44 = { + 0x5a44, pci_device_15b3_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a45 = { + 0x5a45, pci_device_15b3_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a46 = { + 0x5a46, pci_device_15b3_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5e8d = { + 0x5e8d, pci_device_15b3_5e8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5e8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6274 = { + 0x6274, pci_device_15b3_6274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6278 = { + 0x6278, pci_device_15b3_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6279 = { + 0x6279, pci_device_15b3_6279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6282 = { + 0x6282, pci_device_15b3_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_1100 = { + 0x1100, pci_device_15bc_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2922 = { + 0x2922, pci_device_15bc_2922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2928 = { + 0x2928, pci_device_15bc_2928, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2928, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c5_8010 = { + 0x8010, pci_device_15c5_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c5_8010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e9_1841 = { + 0x1841, pci_device_15e9_1841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e9_1841, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15ec_3101 = { + 0x3101, pci_device_15ec_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ec_5102 = { + 0x5102, pci_device_15ec_5102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_5102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0610 = { + 0x0610, pci_device_1619_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0620 = { + 0x0620, pci_device_1619_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0640 = { + 0x0640, pci_device_1619_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_1610 = { + 0x1610, pci_device_1619_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_2610 = { + 0x2610, pci_device_1619_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_2610, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1626_8410 = { + 0x8410, pci_device_1626_8410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1626_8410, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1637_3874 = { + 0x3874, pci_device_1637_3874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1637_3874, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_3052 = { + 0x3052, pci_device_163c_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165f_1020 = { + 0x1020, pci_device_165f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165f_1020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1668_0100 = { + 0x0100, pci_device_1668_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1668_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_166d_0001 = { + 0x0001, pci_device_166d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_166d_0002 = { + 0x0002, pci_device_166d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1677_104e = { + 0x104e, pci_device_1677_104e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_104e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_12d7 = { + 0x12d7, pci_device_1677_12d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_12d7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167b_2102 = { + 0x2102, pci_device_167b_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167b_2102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1681_0010 = { + 0x0010, pci_device_1681_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1681_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1688_1170 = { + 0x1170, pci_device_1688_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1688_1170, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_168c_0007 = { + 0x0007, pci_device_168c_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0011 = { + 0x0011, pci_device_168c_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0012 = { + 0x0012, pci_device_168c_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0013 = { + 0x0013, pci_device_168c_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001a = { + 0x001a, pci_device_168c_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001b = { + 0x001b, pci_device_168c_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0020 = { + 0x0020, pci_device_168c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_1014 = { + 0x1014, pci_device_168c_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_1014, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_169c_0044 = { + 0x0044, pci_device_169c_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_169c_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1100 = { + 0x1100, pci_device_16ab_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1101 = { + 0x1101, pci_device_16ab_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_8501 = { + 0x8501, pci_device_16ab_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_8501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ae_1141 = { + 0x1141, pci_device_16ae_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ae_1141, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ca_0001 = { + 0x0001, pci_device_16ca_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ca_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e3_1e0f = { + 0x1e0f, pci_device_16e3_1e0f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e3_1e0f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_00ff = { + 0x00ff, pci_device_16ec_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_0116 = { + 0x0116, pci_device_16ec_0116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_0116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ed_1001 = { + 0x1001, pci_device_16ed_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ed_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16f4_8000 = { + 0x8000, pci_device_16f4_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16f4_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_170b_0100 = { + 0x0100, pci_device_170b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_170b_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1725_7174 = { + 0x7174, pci_device_1725_7174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1725_7174, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_172a_13c8 = { + 0x13c8, pci_device_172a_13c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_172a_13c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1737_0013 = { + 0x0013, pci_device_1737_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_0015 = { + 0x0015, pci_device_1737_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1032 = { + 0x1032, pci_device_1737_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1064 = { + 0x1064, pci_device_1737_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab08 = { + 0xab08, pci_device_1737_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab09 = { + 0xab09, pci_device_1737_ab09, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab09, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03e9 = { + 0x03e9, pci_device_173b_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03eb = { + 0x03eb, pci_device_173b_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03eb, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1799_6001 = { + 0x6001, pci_device_1799_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6020 = { + 0x6020, pci_device_1799_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6060 = { + 0x6060, pci_device_1799_6060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7000 = { + 0x7000, pci_device_1799_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7010 = { + 0x7010, pci_device_1799_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_179c_0557 = { + 0x0557, pci_device_179c_0557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_0566 = { + 0x0566, pci_device_179c_0566, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0566, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5031 = { + 0x5031, pci_device_179c_5031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5121 = { + 0x5121, pci_device_179c_5121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5211 = { + 0x5211, pci_device_179c_5211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5679 = { + 0x5679, pci_device_179c_5679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5679, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17a0_8033 = { + 0x8033, pci_device_17a0_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17a0_8034 = { + 0x8034, pci_device_17a0_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8034, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b3_ab08 = { + 0xab08, pci_device_17b3_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b3_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b4_0011 = { + 0x0011, pci_device_17b4_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b4_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d3_1110 = { + 0x1110, pci_device_17d3_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1120 = { + 0x1120, pci_device_17d3_1120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1130 = { + 0x1130, pci_device_17d3_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1160 = { + 0x1160, pci_device_17d3_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1210 = { + 0x1210, pci_device_17d3_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1220 = { + 0x1220, pci_device_17d3_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1230 = { + 0x1230, pci_device_17d3_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1260 = { + 0x1260, pci_device_17d3_1260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_5831 = { + 0x5831, pci_device_17d3_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_5832 = { + 0x5832, pci_device_17d3_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_5832, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17fe_2120 = { + 0x2120, pci_device_17fe_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17fe_2220 = { + 0x2220, pci_device_17fe_2220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1814_0101 = { + 0x0101, pci_device_1814_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0201 = { + 0x0201, pci_device_1814_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0401 = { + 0x0401, pci_device_1814_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1822_4e35 = { + 0x4e35, pci_device_1822_4e35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1822_4e35, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182d_3069 = { + 0x3069, pci_device_182d_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_3069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_182d_9790 = { + 0x9790, pci_device_182d_9790, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_9790, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_183b_08a7 = { + 0x08a7, pci_device_183b_08a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a8 = { + 0x08a8, pci_device_183b_08a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a9 = { + 0x08a9, pci_device_183b_08a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a9, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1864_2110 = { + 0x2110, pci_device_1864_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1864_2110, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1867_5a44 = { + 0x5a44, pci_device_1867_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a45 = { + 0x5a45, pci_device_1867_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a46 = { + 0x5a46, pci_device_1867_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6278 = { + 0x6278, pci_device_1867_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6282 = { + 0x6282, pci_device_1867_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ac_d500 = { + 0xd500, pci_device_18ac_d500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d810 = { + 0xd810, pci_device_18ac_d810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d820 = { + 0xd820, pci_device_18ac_d820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18b8_b001 = { + 0xb001, pci_device_18b8_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18b8_b001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ca_0020 = { + 0x0020, pci_device_18ca_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ca_0040 = { + 0x0040, pci_device_18ca_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18d2_3069 = { + 0x3069, pci_device_18d2_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18d2_3069, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18dd_4c6f = { + 0x4c6f, pci_device_18dd_4c6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18dd_4c6f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18e6_0001 = { + 0x0001, pci_device_18e6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18e6_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ec_c006 = { + 0xc006, pci_device_18ec_c006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c045 = { + 0xc045, pci_device_18ec_c045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c050 = { + 0xc050, pci_device_18ec_c050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c058 = { + 0xc058, pci_device_18ec_c058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c058, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f7_0001 = { + 0x0001, pci_device_18f7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0002 = { + 0x0002, pci_device_18f7_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0004 = { + 0x0004, pci_device_18f7_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0005 = { + 0x0005, pci_device_18f7_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_000a = { + 0x000a, pci_device_18f7_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1957_0080 = { + 0x0080, pci_device_1957_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0081 = { + 0x0081, pci_device_1957_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0082 = { + 0x0082, pci_device_1957_0082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0083 = { + 0x0083, pci_device_1957_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0084 = { + 0x0084, pci_device_1957_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0085 = { + 0x0085, pci_device_1957_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0086 = { + 0x0086, pci_device_1957_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0087 = { + 0x0087, pci_device_1957_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0087, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1966_1975 = { + 0x1975, pci_device_1966_1975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1966_1975, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_196a_0101 = { + 0x0101, pci_device_196a_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_196a_0102 = { + 0x0102, pci_device_196a_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_197b_2360 = { + 0x2360, pci_device_197b_2360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2363 = { + 0x2363, pci_device_197b_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2363, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1989_0001 = { + 0x0001, pci_device_1989_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1989_8001 = { + 0x8001, pci_device_1989_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ae_0520 = { + 0x0520, pci_device_19ae_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ae_0520, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc0_0300 = { + 0x0300, pci_device_1fc0_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc0_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc1_000d = { + 0x000d, pci_device_1fc1_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_000d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fce_0001 = { + 0x0001, pci_device_1fce_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fce_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0020 = { + 0x0020, pci_device_3388_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0022 = { + 0x0022, pci_device_3388_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0026 = { + 0x0026, pci_device_3388_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101a = { + 0x101a, pci_device_3388_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101b = { + 0x101b, pci_device_3388_101b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3842_c370 = { + 0xc370, pci_device_3842_c370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3842_c370, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000d = { + 0x000d, pci_device_3d3d_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0011 = { + 0x0011, pci_device_3d3d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0012 = { + 0x0012, pci_device_3d3d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0013 = { + 0x0013, pci_device_3d3d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0020 = { + 0x0020, pci_device_3d3d_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0022 = { + 0x0022, pci_device_3d3d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0024 = { + 0x0024, pci_device_3d3d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a1 = { + 0x07a1, pci_device_3d3d_07a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a2 = { + 0x07a2, pci_device_3d3d_07a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a3 = { + 0x07a3, pci_device_3d3d_07a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4144_0044 = { + 0x0044, pci_device_4144_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4144_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0016 = { + 0x0016, pci_device_4444_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_494f_10e8 = { + 0x10e8, pci_device_494f_10e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_494f_10e8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4c53_0000 = { + 0x0000, pci_device_4c53_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4c53_0001 = { + 0x0001, pci_device_4c53_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5168_0301 = { + 0x0301, pci_device_5168_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_544c_0350 = { + 0x0350, pci_device_544c_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_544c_0350, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5654_3132 = { + 0x3132, pci_device_5654_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5654_3132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0004 = { + 0x0004, pci_device_6666_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0101 = { + 0x0101, pci_device_6666_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_7063_2000 = { + 0x2000, pci_device_7063_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_3000 = { + 0x3000, pci_device_7063_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0309 = { + 0x0309, pci_device_8086_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_030d = { + 0x030d, pci_device_8086_030d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_030d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0326 = { + 0x0326, pci_device_8086_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0327 = { + 0x0327, pci_device_8086_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0329 = { + 0x0329, pci_device_8086_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032a = { + 0x032a, pci_device_8086_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032c = { + 0x032c, pci_device_8086_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0330 = { + 0x0330, pci_device_8086_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0331 = { + 0x0331, pci_device_8086_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0332 = { + 0x0332, pci_device_8086_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0333 = { + 0x0333, pci_device_8086_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0334 = { + 0x0334, pci_device_8086_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0335 = { + 0x0335, pci_device_8086_0335, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0335, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0336 = { + 0x0336, pci_device_8086_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0340 = { + 0x0340, pci_device_8086_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0341 = { + 0x0341, pci_device_8086_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0370 = { + 0x0370, pci_device_8086_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0371 = { + 0x0371, pci_device_8086_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0372 = { + 0x0372, pci_device_8086_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0373 = { + 0x0373, pci_device_8086_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0374 = { + 0x0374, pci_device_8086_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0500 = { + 0x0500, pci_device_8086_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0501 = { + 0x0501, pci_device_8086_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0502 = { + 0x0502, pci_device_8086_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0503 = { + 0x0503, pci_device_8086_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0510 = { + 0x0510, pci_device_8086_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0511 = { + 0x0511, pci_device_8086_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0512 = { + 0x0512, pci_device_8086_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0513 = { + 0x0513, pci_device_8086_0513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0514 = { + 0x0514, pci_device_8086_0514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0515 = { + 0x0515, pci_device_8086_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0516 = { + 0x0516, pci_device_8086_0516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0530 = { + 0x0530, pci_device_8086_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0531 = { + 0x0531, pci_device_8086_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0532 = { + 0x0532, pci_device_8086_0532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0533 = { + 0x0533, pci_device_8086_0533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0534 = { + 0x0534, pci_device_8086_0534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0535 = { + 0x0535, pci_device_8086_0535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0536 = { + 0x0536, pci_device_8086_0536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0537 = { + 0x0537, pci_device_8086_0537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_061f = { + 0x061f, pci_device_8086_061f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_061f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100a = { + 0x100a, pci_device_8086_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1013 = { + 0x1013, pci_device_8086_1013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1014 = { + 0x1014, pci_device_8086_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1016 = { + 0x1016, pci_device_8086_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1017 = { + 0x1017, pci_device_8086_1017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1018 = { + 0x1018, pci_device_8086_1018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1019 = { + 0x1019, pci_device_8086_1019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101a = { + 0x101a, pci_device_8086_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101d = { + 0x101d, pci_device_8086_101d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101e = { + 0x101e, pci_device_8086_101e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1026 = { + 0x1026, pci_device_8086_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1027 = { + 0x1027, pci_device_8086_1027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1028 = { + 0x1028, pci_device_8086_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1043 = { + 0x1043, pci_device_8086_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1048 = { + 0x1048, pci_device_8086_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1050 = { + 0x1050, pci_device_8086_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1051 = { + 0x1051, pci_device_8086_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1052 = { + 0x1052, pci_device_8086_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1053 = { + 0x1053, pci_device_8086_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105e = { + 0x105e, pci_device_8086_105e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105f = { + 0x105f, pci_device_8086_105f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1060 = { + 0x1060, pci_device_8086_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1064 = { + 0x1064, pci_device_8086_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1065 = { + 0x1065, pci_device_8086_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1066 = { + 0x1066, pci_device_8086_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1067 = { + 0x1067, pci_device_8086_1067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1068 = { + 0x1068, pci_device_8086_1068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1069 = { + 0x1069, pci_device_8086_1069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106a = { + 0x106a, pci_device_8086_106a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106b = { + 0x106b, pci_device_8086_106b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1075 = { + 0x1075, pci_device_8086_1075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1076 = { + 0x1076, pci_device_8086_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1077 = { + 0x1077, pci_device_8086_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1078 = { + 0x1078, pci_device_8086_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1079 = { + 0x1079, pci_device_8086_1079, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1079, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107a = { + 0x107a, pci_device_8086_107a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107b = { + 0x107b, pci_device_8086_107b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107c = { + 0x107c, pci_device_8086_107c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107d = { + 0x107d, pci_device_8086_107d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107e = { + 0x107e, pci_device_8086_107e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107f = { + 0x107f, pci_device_8086_107f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1080 = { + 0x1080, pci_device_8086_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1081 = { + 0x1081, pci_device_8086_1081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1082 = { + 0x1082, pci_device_8086_1082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1083 = { + 0x1083, pci_device_8086_1083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1084 = { + 0x1084, pci_device_8086_1084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1085 = { + 0x1085, pci_device_8086_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1086 = { + 0x1086, pci_device_8086_1086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1087 = { + 0x1087, pci_device_8086_1087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1089 = { + 0x1089, pci_device_8086_1089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108a = { + 0x108a, pci_device_8086_108a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108b = { + 0x108b, pci_device_8086_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108c = { + 0x108c, pci_device_8086_108c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1096 = { + 0x1096, pci_device_8086_1096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1097 = { + 0x1097, pci_device_8086_1097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1098 = { + 0x1098, pci_device_8086_1098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1099 = { + 0x1099, pci_device_8086_1099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109a = { + 0x109a, pci_device_8086_109a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1107 = { + 0x1107, pci_device_8086_1107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123e = { + 0x123e, pci_device_8086_123e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a38 = { + 0x1a38, pci_device_8086_1a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a48 = { + 0x1a48, pci_device_8086_1a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c1 = { + 0x24c1, pci_device_8086_24c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24ca = { + 0x24ca, pci_device_8086_24ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cc = { + 0x24cc, pci_device_8086_24cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d0 = { + 0x24d0, pci_device_8086_24d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d1 = { + 0x24d1, pci_device_8086_24d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d2 = { + 0x24d2, pci_device_8086_24d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d3 = { + 0x24d3, pci_device_8086_24d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d4 = { + 0x24d4, pci_device_8086_24d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d5 = { + 0x24d5, pci_device_8086_24d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d6 = { + 0x24d6, pci_device_8086_24d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d7 = { + 0x24d7, pci_device_8086_24d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24db = { + 0x24db, pci_device_8086_24db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dc = { + 0x24dc, pci_device_8086_24dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dd = { + 0x24dd, pci_device_8086_24dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24de = { + 0x24de, pci_device_8086_24de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24df = { + 0x24df, pci_device_8086_24df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_254c = { + 0x254c, pci_device_8086_254c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_254c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2550 = { + 0x2550, pci_device_8086_2550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2551 = { + 0x2551, pci_device_8086_2551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2552 = { + 0x2552, pci_device_8086_2552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2553 = { + 0x2553, pci_device_8086_2553, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2553, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2554 = { + 0x2554, pci_device_8086_2554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_255d = { + 0x255d, pci_device_8086_255d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_255d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2571 = { + 0x2571, pci_device_8086_2571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2573 = { + 0x2573, pci_device_8086_2573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2576 = { + 0x2576, pci_device_8086_2576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2578 = { + 0x2578, pci_device_8086_2578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2579 = { + 0x2579, pci_device_8086_2579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257b = { + 0x257b, pci_device_8086_257b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257e = { + 0x257e, pci_device_8086_257e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2580 = { + 0x2580, pci_device_8086_2580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2581 = { + 0x2581, pci_device_8086_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2582 = { + 0x2582, pci_device_8086_2582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2584 = { + 0x2584, pci_device_8086_2584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2585 = { + 0x2585, pci_device_8086_2585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2588 = { + 0x2588, pci_device_8086_2588, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2588, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2589 = { + 0x2589, pci_device_8086_2589, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2589, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_258a = { + 0x258a, pci_device_8086_258a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_258a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2590 = { + 0x2590, pci_device_8086_2590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2591 = { + 0x2591, pci_device_8086_2591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2592 = { + 0x2592, pci_device_8086_2592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a1 = { + 0x25a1, pci_device_8086_25a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a2 = { + 0x25a2, pci_device_8086_25a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a3 = { + 0x25a3, pci_device_8086_25a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a4 = { + 0x25a4, pci_device_8086_25a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a6 = { + 0x25a6, pci_device_8086_25a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a7 = { + 0x25a7, pci_device_8086_25a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a9 = { + 0x25a9, pci_device_8086_25a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25aa = { + 0x25aa, pci_device_8086_25aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ab = { + 0x25ab, pci_device_8086_25ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ac = { + 0x25ac, pci_device_8086_25ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ad = { + 0x25ad, pci_device_8086_25ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ae = { + 0x25ae, pci_device_8086_25ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25b0 = { + 0x25b0, pci_device_8086_25b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25c0 = { + 0x25c0, pci_device_8086_25c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d0 = { + 0x25d0, pci_device_8086_25d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d4 = { + 0x25d4, pci_device_8086_25d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d8 = { + 0x25d8, pci_device_8086_25d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e2 = { + 0x25e2, pci_device_8086_25e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e3 = { + 0x25e3, pci_device_8086_25e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e4 = { + 0x25e4, pci_device_8086_25e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e5 = { + 0x25e5, pci_device_8086_25e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e6 = { + 0x25e6, pci_device_8086_25e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e7 = { + 0x25e7, pci_device_8086_25e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e8 = { + 0x25e8, pci_device_8086_25e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f0 = { + 0x25f0, pci_device_8086_25f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f1 = { + 0x25f1, pci_device_8086_25f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f3 = { + 0x25f3, pci_device_8086_25f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f5 = { + 0x25f5, pci_device_8086_25f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f6 = { + 0x25f6, pci_device_8086_25f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f7 = { + 0x25f7, pci_device_8086_25f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f8 = { + 0x25f8, pci_device_8086_25f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f9 = { + 0x25f9, pci_device_8086_25f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25fa = { + 0x25fa, pci_device_8086_25fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2600 = { + 0x2600, pci_device_8086_2600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2601 = { + 0x2601, pci_device_8086_2601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2602 = { + 0x2602, pci_device_8086_2602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2603 = { + 0x2603, pci_device_8086_2603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2604 = { + 0x2604, pci_device_8086_2604, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2604, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2605 = { + 0x2605, pci_device_8086_2605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2606 = { + 0x2606, pci_device_8086_2606, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2606, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2607 = { + 0x2607, pci_device_8086_2607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2608 = { + 0x2608, pci_device_8086_2608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2609 = { + 0x2609, pci_device_8086_2609, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2609, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260a = { + 0x260a, pci_device_8086_260a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260c = { + 0x260c, pci_device_8086_260c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2610 = { + 0x2610, pci_device_8086_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2611 = { + 0x2611, pci_device_8086_2611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2612 = { + 0x2612, pci_device_8086_2612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2613 = { + 0x2613, pci_device_8086_2613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2614 = { + 0x2614, pci_device_8086_2614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2615 = { + 0x2615, pci_device_8086_2615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2617 = { + 0x2617, pci_device_8086_2617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2618 = { + 0x2618, pci_device_8086_2618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2619 = { + 0x2619, pci_device_8086_2619, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2619, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261a = { + 0x261a, pci_device_8086_261a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261b = { + 0x261b, pci_device_8086_261b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261c = { + 0x261c, pci_device_8086_261c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261d = { + 0x261d, pci_device_8086_261d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261e = { + 0x261e, pci_device_8086_261e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2620 = { + 0x2620, pci_device_8086_2620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2621 = { + 0x2621, pci_device_8086_2621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2622 = { + 0x2622, pci_device_8086_2622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2623 = { + 0x2623, pci_device_8086_2623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2624 = { + 0x2624, pci_device_8086_2624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2625 = { + 0x2625, pci_device_8086_2625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2626 = { + 0x2626, pci_device_8086_2626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2627 = { + 0x2627, pci_device_8086_2627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2640 = { + 0x2640, pci_device_8086_2640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2641 = { + 0x2641, pci_device_8086_2641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2642 = { + 0x2642, pci_device_8086_2642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2651 = { + 0x2651, pci_device_8086_2651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2652 = { + 0x2652, pci_device_8086_2652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2653 = { + 0x2653, pci_device_8086_2653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2658 = { + 0x2658, pci_device_8086_2658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2659 = { + 0x2659, pci_device_8086_2659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265a = { + 0x265a, pci_device_8086_265a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265b = { + 0x265b, pci_device_8086_265b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265c = { + 0x265c, pci_device_8086_265c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2660 = { + 0x2660, pci_device_8086_2660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2662 = { + 0x2662, pci_device_8086_2662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2664 = { + 0x2664, pci_device_8086_2664, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2664, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2666 = { + 0x2666, pci_device_8086_2666, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2666, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2668 = { + 0x2668, pci_device_8086_2668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266a = { + 0x266a, pci_device_8086_266a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266c = { + 0x266c, pci_device_8086_266c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266d = { + 0x266d, pci_device_8086_266d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266e = { + 0x266e, pci_device_8086_266e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266f = { + 0x266f, pci_device_8086_266f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2670 = { + 0x2670, pci_device_8086_2670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2680 = { + 0x2680, pci_device_8086_2680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2681 = { + 0x2681, pci_device_8086_2681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2682 = { + 0x2682, pci_device_8086_2682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2683 = { + 0x2683, pci_device_8086_2683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2688 = { + 0x2688, pci_device_8086_2688, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2688, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2689 = { + 0x2689, pci_device_8086_2689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268a = { + 0x268a, pci_device_8086_268a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268b = { + 0x268b, pci_device_8086_268b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268c = { + 0x268c, pci_device_8086_268c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2690 = { + 0x2690, pci_device_8086_2690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2692 = { + 0x2692, pci_device_8086_2692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2694 = { + 0x2694, pci_device_8086_2694, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2694, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2696 = { + 0x2696, pci_device_8086_2696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2698 = { + 0x2698, pci_device_8086_2698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2699 = { + 0x2699, pci_device_8086_2699, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2699, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269a = { + 0x269a, pci_device_8086_269a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269b = { + 0x269b, pci_device_8086_269b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269e = { + 0x269e, pci_device_8086_269e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2770 = { + 0x2770, pci_device_8086_2770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2771 = { + 0x2771, pci_device_8086_2771, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2771, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2772 = { + 0x2772, pci_device_8086_2772, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2772, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2774 = { + 0x2774, pci_device_8086_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2775 = { + 0x2775, pci_device_8086_2775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2776 = { + 0x2776, pci_device_8086_2776, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2776, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2778 = { + 0x2778, pci_device_8086_2778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2779 = { + 0x2779, pci_device_8086_2779, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2779, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277a = { + 0x277a, pci_device_8086_277a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277c = { + 0x277c, pci_device_8086_277c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277d = { + 0x277d, pci_device_8086_277d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2782 = { + 0x2782, pci_device_8086_2782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2792 = { + 0x2792, pci_device_8086_2792, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2792, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a0 = { + 0x27a0, pci_device_8086_27a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a1 = { + 0x27a1, pci_device_8086_27a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a2 = { + 0x27a2, pci_device_8086_27a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a6 = { + 0x27a6, pci_device_8086_27a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b0 = { + 0x27b0, pci_device_8086_27b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b8 = { + 0x27b8, pci_device_8086_27b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b9 = { + 0x27b9, pci_device_8086_27b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27bd = { + 0x27bd, pci_device_8086_27bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c0 = { + 0x27c0, pci_device_8086_27c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c1 = { + 0x27c1, pci_device_8086_27c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c3 = { + 0x27c3, pci_device_8086_27c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c4 = { + 0x27c4, pci_device_8086_27c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c5 = { + 0x27c5, pci_device_8086_27c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c6 = { + 0x27c6, pci_device_8086_27c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c8 = { + 0x27c8, pci_device_8086_27c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c9 = { + 0x27c9, pci_device_8086_27c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27ca = { + 0x27ca, pci_device_8086_27ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cb = { + 0x27cb, pci_device_8086_27cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cc = { + 0x27cc, pci_device_8086_27cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d0 = { + 0x27d0, pci_device_8086_27d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d2 = { + 0x27d2, pci_device_8086_27d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d4 = { + 0x27d4, pci_device_8086_27d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d6 = { + 0x27d6, pci_device_8086_27d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d8 = { + 0x27d8, pci_device_8086_27d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27da = { + 0x27da, pci_device_8086_27da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dc = { + 0x27dc, pci_device_8086_27dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dd = { + 0x27dd, pci_device_8086_27dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27de = { + 0x27de, pci_device_8086_27de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27df = { + 0x27df, pci_device_8086_27df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e0 = { + 0x27e0, pci_device_8086_27e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e2 = { + 0x27e2, pci_device_8086_27e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3200 = { + 0x3200, pci_device_8086_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3340 = { + 0x3340, pci_device_8086_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3341 = { + 0x3341, pci_device_8086_3341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3500 = { + 0x3500, pci_device_8086_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3501 = { + 0x3501, pci_device_8086_3501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3504 = { + 0x3504, pci_device_8086_3504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3505 = { + 0x3505, pci_device_8086_3505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350c = { + 0x350c, pci_device_8086_350c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350d = { + 0x350d, pci_device_8086_350d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3510 = { + 0x3510, pci_device_8086_3510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3511 = { + 0x3511, pci_device_8086_3511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3514 = { + 0x3514, pci_device_8086_3514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3515 = { + 0x3515, pci_device_8086_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3518 = { + 0x3518, pci_device_8086_3518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3519 = { + 0x3519, pci_device_8086_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3581 = { + 0x3581, pci_device_8086_3581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3584 = { + 0x3584, pci_device_8086_3584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3585 = { + 0x3585, pci_device_8086_3585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3590 = { + 0x3590, pci_device_8086_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3591 = { + 0x3591, pci_device_8086_3591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3592 = { + 0x3592, pci_device_8086_3592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3593 = { + 0x3593, pci_device_8086_3593, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3593, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3594 = { + 0x3594, pci_device_8086_3594, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3594, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3595 = { + 0x3595, pci_device_8086_3595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3596 = { + 0x3596, pci_device_8086_3596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3597 = { + 0x3597, pci_device_8086_3597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3598 = { + 0x3598, pci_device_8086_3598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3599 = { + 0x3599, pci_device_8086_3599, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3599, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359a = { + 0x359a, pci_device_8086_359a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359b = { + 0x359b, pci_device_8086_359b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359e = { + 0x359e, pci_device_8086_359e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4220 = { + 0x4220, pci_device_8086_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4223 = { + 0x4223, pci_device_8086_4223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4224 = { + 0x4224, pci_device_8086_4224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7050 = { + 0x7050, pci_device_8086_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7051 = { + 0x7051, pci_device_8086_7051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_8500 = { + 0x8500, pci_device_8086_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9000 = { + 0x9000, pci_device_8086_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9001 = { + 0x9001, pci_device_8086_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9004 = { + 0x9004, pci_device_8086_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8c4a_1980 = { + 0x1980, pci_device_8c4a_1980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8c4a_1980, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_0078 = { + 0x0078, pci_device_9004_0078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_0078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7710 = { + 0x7710, pci_device_9004_7710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7711 = { + 0x7711, pci_device_9004_7711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8278 = { + 0x8278, pci_device_9004_8278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8378 = { + 0x8378, pci_device_9004_8378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8478 = { + 0x8478, pci_device_9004_8478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8578 = { + 0x8578, pci_device_9004_8578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8678 = { + 0x8678, pci_device_9004_8678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8778 = { + 0x8778, pci_device_9004_8778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8878 = { + 0x8878, pci_device_9004_8878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8b78 = { + 0x8b78, pci_device_9004_8b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_ec78 = { + 0xec78, pci_device_9004_ec78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_ec78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9005_0010 = { + 0x0010, pci_device_9005_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0011 = { + 0x0011, pci_device_9005_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0013 = { + 0x0013, pci_device_9005_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_001f = { + 0x001f, pci_device_9005_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0020 = { + 0x0020, pci_device_9005_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_002f = { + 0x002f, pci_device_9005_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0030 = { + 0x0030, pci_device_9005_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_003f = { + 0x003f, pci_device_9005_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0050 = { + 0x0050, pci_device_9005_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0051 = { + 0x0051, pci_device_9005_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0053 = { + 0x0053, pci_device_9005_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_005f = { + 0x005f, pci_device_9005_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0080 = { + 0x0080, pci_device_9005_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0081 = { + 0x0081, pci_device_9005_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0083 = { + 0x0083, pci_device_9005_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_008f = { + 0x008f, pci_device_9005_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0092 = { + 0x0092, pci_device_9005_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0093 = { + 0x0093, pci_device_9005_0093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c0 = { + 0x00c0, pci_device_9005_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c1 = { + 0x00c1, pci_device_9005_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c3 = { + 0x00c3, pci_device_9005_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c5 = { + 0x00c5, pci_device_9005_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00cf = { + 0x00cf, pci_device_9005_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0241 = { + 0x0241, pci_device_9005_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0250 = { + 0x0250, pci_device_9005_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0279 = { + 0x0279, pci_device_9005_0279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0283 = { + 0x0283, pci_device_9005_0283, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0283, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0284 = { + 0x0284, pci_device_9005_0284, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0284, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0285 = { + 0x0285, pci_device_9005_0285, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0285, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0286 = { + 0x0286, pci_device_9005_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0500 = { + 0x0500, pci_device_9005_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0503 = { + 0x0503, pci_device_9005_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0910 = { + 0x0910, pci_device_9005_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_091e = { + 0x091e, pci_device_9005_091e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_091e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8000 = { + 0x8000, pci_device_9005_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_800f = { + 0x800f, pci_device_9005_800f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_800f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8010 = { + 0x8010, pci_device_9005_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8011 = { + 0x8011, pci_device_9005_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8012 = { + 0x8012, pci_device_9005_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8013 = { + 0x8013, pci_device_9005_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8014 = { + 0x8014, pci_device_9005_8014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8015 = { + 0x8015, pci_device_9005_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8016 = { + 0x8016, pci_device_9005_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8017 = { + 0x8017, pci_device_9005_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801c = { + 0x801c, pci_device_9005_801c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801d = { + 0x801d, pci_device_9005_801d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801e = { + 0x801e, pci_device_9005_801e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801f = { + 0x801f, pci_device_9005_801f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8080 = { + 0x8080, pci_device_9005_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_808f = { + 0x808f, pci_device_9005_808f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_808f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8090 = { + 0x8090, pci_device_9005_8090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8091 = { + 0x8091, pci_device_9005_8091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8092 = { + 0x8092, pci_device_9005_8092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8093 = { + 0x8093, pci_device_9005_8093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8094 = { + 0x8094, pci_device_9005_8094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8095 = { + 0x8095, pci_device_9005_8095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8096 = { + 0x8096, pci_device_9005_8096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8097 = { + 0x8097, pci_device_9005_8097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809c = { + 0x809c, pci_device_9005_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809d = { + 0x809d, pci_device_9005_809d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809e = { + 0x809e, pci_device_9005_809e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809f = { + 0x809f, pci_device_9005_809f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_907f_2015 = { + 0x2015, pci_device_907f_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_907f_2015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9412_6565 = { + 0x6565, pci_device_9412_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9412_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9699_6565 = { + 0x6565, pci_device_9699_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9699_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9710_7780 = { + 0x7780, pci_device_9710_7780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_7780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9805 = { + 0x9805, pci_device_9710_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9815 = { + 0x9815, pci_device_9710_9815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9835 = { + 0x9835, pci_device_9710_9835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9845 = { + 0x9845, pci_device_9710_9845, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9845, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9855 = { + 0x9855, pci_device_9710_9855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9855, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9902_0001 = { + 0x0001, pci_device_9902_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0002 = { + 0x0002, pci_device_9902_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0003 = { + 0x0003, pci_device_9902_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_a727_0013 = { + 0x0013, pci_device_a727_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_a727_0013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_aecb_6250 = { + 0x6250, pci_device_aecb_6250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_aecb_6250, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_affe_dead = { + 0xdead, pci_device_affe_dead, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_affe_dead, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cafe_0003 = { + 0x0003, pci_device_cafe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cafe_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cddd_0101 = { + 0x0101, pci_device_cddd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_cddd_0200 = { + 0x0200, pci_device_cddd_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d161_0205 = { + 0x0205, pci_device_d161_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0210 = { + 0x0210, pci_device_d161_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0405 = { + 0x0405, pci_device_d161_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0410 = { + 0x0410, pci_device_d161_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_2400 = { + 0x2400, pci_device_d161_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d4d4_0601 = { + 0x0601, pci_device_d4d4_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d4d4_0601, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_deaf_9050 = { + 0x9050, pci_device_deaf_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9051 = { + 0x9051, pci_device_deaf_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9052 = { + 0x9052, pci_device_deaf_9052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9052, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e000_e000 = { + 0xe000, pci_device_e000_e000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e000_e000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e159_0001 = { + 0x0001, pci_device_e159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_e159_0002 = { + 0x0002, pci_device_e159_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea01_000a = { + 0x000a, pci_device_ea01_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0032 = { + 0x0032, pci_device_ea01_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_003e = { + 0x003e, pci_device_ea01_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0041 = { + 0x0041, pci_device_ea01_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0043 = { + 0x0043, pci_device_ea01_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0046 = { + 0x0046, pci_device_ea01_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0052 = { + 0x0052, pci_device_ea01_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0800 = { + 0x0800, pci_device_ea01_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea60_9896 = { + 0x9896, pci_device_ea60_9896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9897 = { + 0x9897, pci_device_ea60_9897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9898 = { + 0x9898, pci_device_ea60_9898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_eace_3100 = { + 0x3100, pci_device_eace_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3200 = { + 0x3200, pci_device_eace_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_320e = { + 0x320e, pci_device_eace_320e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_320e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_340e = { + 0x340e, pci_device_eace_340e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_340e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_341e = { + 0x341e, pci_device_eace_341e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_341e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3500 = { + 0x3500, pci_device_eace_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_351c = { + 0x351c, pci_device_eace_351c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_351c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4100 = { + 0x4100, pci_device_eace_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4110 = { + 0x4110, pci_device_eace_4110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4220 = { + 0x4220, pci_device_eace_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_422e = { + 0x422e, pci_device_eace_422e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_422e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ec80_ec00 = { + 0xec00, pci_device_ec80_ec00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ec80_ec00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_edd8_a091 = { + 0xa091, pci_device_edd8_a091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a099 = { + 0xa099, pci_device_edd8_a099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a1 = { + 0xa0a1, pci_device_edd8_a0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a9 = { + 0xa0a9, pci_device_edd8_a0a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a9, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_f1d0_c0fe = { + 0xc0fe, pci_device_f1d0_c0fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_c0ff = { + 0xc0ff, pci_device_f1d0_c0ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cafe = { + 0xcafe, pci_device_f1d0_cafe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cafe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cfee = { + 0xcfee, pci_device_f1d0_cfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dcaf = { + 0xdcaf, pci_device_f1d0_dcaf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dcaf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dfee = { + 0xdfee, pci_device_f1d0_dfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_efac = { + 0xefac, pci_device_f1d0_efac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_efac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_facd = { + 0xfacd, pci_device_f1d0_facd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_facd, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fa57_0001 = { + 0x0001, pci_device_fa57_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fa57_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_feda_a0fa = { + 0xa0fa, pci_device_feda_a0fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a0fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_feda_a10e = { + 0xa10e, pci_device_feda_a10e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a10e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fede_0003 = { + 0x0003, pci_device_fede_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fede_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffd_0101 = { + 0x0101, pci_device_fffd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffd_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffe_0405 = { + 0x0405, pci_device_fffe_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_fffe_0710 = { + 0x0710, pci_device_fffe_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0710, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0070[] = { + &pci_dev_info_0070_0003, + &pci_dev_info_0070_0009, + &pci_dev_info_0070_0801, + &pci_dev_info_0070_0807, + &pci_dev_info_0070_4000, + &pci_dev_info_0070_4001, + &pci_dev_info_0070_4009, + &pci_dev_info_0070_4800, + &pci_dev_info_0070_4801, + &pci_dev_info_0070_4803, + &pci_dev_info_0070_8003, + &pci_dev_info_0070_8801, + &pci_dev_info_0070_c801, + &pci_dev_info_0070_e807, + &pci_dev_info_0070_e817, + NULL +}; +#endif +#define pci_dev_list_0071 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0095[] = { + &pci_dev_info_0095_0680, + NULL +}; +#endif +#define pci_dev_list_00a7 NULL +#define pci_dev_list_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_018a[] = { + &pci_dev_info_018a_0106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_021b[] = { + &pci_dev_info_021b_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0270[] = { + &pci_dev_info_0270_0801, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0291[] = { + &pci_dev_info_0291_8212, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_02ac[] = { + &pci_dev_info_02ac_1012, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0357[] = { + &pci_dev_info_0357_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0432[] = { + &pci_dev_info_0432_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_045e[] = { + &pci_dev_info_045e_006e, + &pci_dev_info_045e_00c2, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_04cf[] = { + &pci_dev_info_04cf_8818, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05e3[] = { + &pci_dev_info_05e3_0701, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + &pci_dev_info_0675_1703, + &pci_dev_info_0675_1704, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_067b[] = { + &pci_dev_info_067b_3507, + NULL +}; +#endif +#define pci_dev_list_0721 NULL +#define pci_dev_list_07e2 NULL +#define pci_dev_list_0925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b49[] = { + &pci_dev_info_0b49_064f, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0046, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_005a, + &pci_dev_info_0e11_007c, + &pci_dev_info_0e11_007d, + &pci_dev_info_0e11_0085, + &pci_dev_info_0e11_00b1, + &pci_dev_info_0e11_00bb, + &pci_dev_info_0e11_00ca, + &pci_dev_info_0e11_00cb, + &pci_dev_info_0e11_00cf, + &pci_dev_info_0e11_00d0, + &pci_dev_info_0e11_00d1, + &pci_dev_info_0e11_00e3, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_4030, + &pci_dev_info_0e11_4031, + &pci_dev_info_0e11_4032, + &pci_dev_info_0e11_4033, + &pci_dev_info_0e11_4034, + &pci_dev_info_0e11_4040, + &pci_dev_info_0e11_4048, + &pci_dev_info_0e11_4050, + &pci_dev_info_0e11_4051, + &pci_dev_info_0e11_4058, + &pci_dev_info_0e11_4070, + &pci_dev_info_0e11_4080, + &pci_dev_info_0e11_4082, + &pci_dev_info_0e11_4083, + &pci_dev_info_0e11_4091, + &pci_dev_info_0e11_409a, + &pci_dev_info_0e11_409b, + &pci_dev_info_0e11_409c, + &pci_dev_info_0e11_409d, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_b200, + &pci_dev_info_0e11_b203, + &pci_dev_info_0e11_b204, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0031, + &pci_dev_info_1000_0032, + &pci_dev_info_1000_0033, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_0041, + &pci_dev_info_1000_0050, + &pci_dev_info_1000_0054, + &pci_dev_info_1000_0056, + &pci_dev_info_1000_0058, + &pci_dev_info_1000_005a, + &pci_dev_info_1000_005c, + &pci_dev_info_1000_005e, + &pci_dev_info_1000_0060, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0407, + &pci_dev_info_1000_0408, + &pci_dev_info_1000_0409, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0640, + &pci_dev_info_1000_0642, + &pci_dev_info_1000_0646, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0804, + &pci_dev_info_1000_0805, + &pci_dev_info_1000_0806, + &pci_dev_info_1000_0807, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_3150, + &pci_dev_info_1002_3152, + &pci_dev_info_1002_3154, + &pci_dev_info_1002_3e50, + &pci_dev_info_1002_3e54, + &pci_dev_info_1002_3e70, + &pci_dev_info_1002_4136, + &pci_dev_info_1002_4137, + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4148, + &pci_dev_info_1002_4149, + &pci_dev_info_1002_414a, + &pci_dev_info_1002_414b, + &pci_dev_info_1002_4150, + &pci_dev_info_1002_4151, + &pci_dev_info_1002_4152, + &pci_dev_info_1002_4153, + &pci_dev_info_1002_4154, + &pci_dev_info_1002_4155, + &pci_dev_info_1002_4156, + &pci_dev_info_1002_4157, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4164, + &pci_dev_info_1002_4165, + &pci_dev_info_1002_4166, + &pci_dev_info_1002_4168, + &pci_dev_info_1002_4170, + &pci_dev_info_1002_4171, + &pci_dev_info_1002_4172, + &pci_dev_info_1002_4173, + &pci_dev_info_1002_4237, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4243, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4341, + &pci_dev_info_1002_4345, + &pci_dev_info_1002_4347, + &pci_dev_info_1002_4348, + &pci_dev_info_1002_4349, + &pci_dev_info_1002_434d, + &pci_dev_info_1002_4353, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4363, + &pci_dev_info_1002_436e, + &pci_dev_info_1002_4370, + &pci_dev_info_1002_4371, + &pci_dev_info_1002_4372, + &pci_dev_info_1002_4373, + &pci_dev_info_1002_4374, + &pci_dev_info_1002_4375, + &pci_dev_info_1002_4376, + &pci_dev_info_1002_4377, + &pci_dev_info_1002_4378, + &pci_dev_info_1002_4379, + &pci_dev_info_1002_437a, + &pci_dev_info_1002_4437, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4a48, + &pci_dev_info_1002_4a49, + &pci_dev_info_1002_4a4a, + &pci_dev_info_1002_4a4b, + &pci_dev_info_1002_4a4c, + &pci_dev_info_1002_4a4d, + &pci_dev_info_1002_4a4e, + &pci_dev_info_1002_4a50, + &pci_dev_info_1002_4a70, + &pci_dev_info_1002_4b49, + &pci_dev_info_1002_4b4b, + &pci_dev_info_1002_4b4c, + &pci_dev_info_1002_4b69, + &pci_dev_info_1002_4b6b, + &pci_dev_info_1002_4b6c, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4c6e, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e48, + &pci_dev_info_1002_4e49, + &pci_dev_info_1002_4e4a, + &pci_dev_info_1002_4e4b, + &pci_dev_info_1002_4e50, + &pci_dev_info_1002_4e51, + &pci_dev_info_1002_4e52, + &pci_dev_info_1002_4e53, + &pci_dev_info_1002_4e54, + &pci_dev_info_1002_4e56, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_4e68, + &pci_dev_info_1002_4e69, + &pci_dev_info_1002_4e6a, + &pci_dev_info_1002_4e71, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5154, + &pci_dev_info_1002_5155, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_515e, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5460, + &pci_dev_info_1002_5464, + &pci_dev_info_1002_5548, + &pci_dev_info_1002_5549, + &pci_dev_info_1002_554a, + &pci_dev_info_1002_554b, + &pci_dev_info_1002_554d, + &pci_dev_info_1002_554f, + &pci_dev_info_1002_5550, + &pci_dev_info_1002_5551, + &pci_dev_info_1002_5552, + &pci_dev_info_1002_5554, + &pci_dev_info_1002_556b, + &pci_dev_info_1002_556d, + &pci_dev_info_1002_556f, + &pci_dev_info_1002_564a, + &pci_dev_info_1002_564b, + &pci_dev_info_1002_5652, + &pci_dev_info_1002_5653, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_5830, + &pci_dev_info_1002_5831, + &pci_dev_info_1002_5832, + &pci_dev_info_1002_5833, + &pci_dev_info_1002_5834, + &pci_dev_info_1002_5835, + &pci_dev_info_1002_5838, + &pci_dev_info_1002_5940, + &pci_dev_info_1002_5941, + &pci_dev_info_1002_5944, + &pci_dev_info_1002_5950, + &pci_dev_info_1002_5951, + &pci_dev_info_1002_5954, + &pci_dev_info_1002_5955, + &pci_dev_info_1002_5960, + &pci_dev_info_1002_5961, + &pci_dev_info_1002_5962, + &pci_dev_info_1002_5964, + &pci_dev_info_1002_5969, + &pci_dev_info_1002_5974, + &pci_dev_info_1002_5975, + &pci_dev_info_1002_5a34, + &pci_dev_info_1002_5a41, + &pci_dev_info_1002_5a42, + &pci_dev_info_1002_5a61, + &pci_dev_info_1002_5a62, + &pci_dev_info_1002_5b60, + &pci_dev_info_1002_5b62, + &pci_dev_info_1002_5b63, + &pci_dev_info_1002_5b64, + &pci_dev_info_1002_5b65, + &pci_dev_info_1002_5b70, + &pci_dev_info_1002_5b72, + &pci_dev_info_1002_5b73, + &pci_dev_info_1002_5b74, + &pci_dev_info_1002_5c61, + &pci_dev_info_1002_5c63, + &pci_dev_info_1002_5d44, + &pci_dev_info_1002_5d48, + &pci_dev_info_1002_5d49, + &pci_dev_info_1002_5d4a, + &pci_dev_info_1002_5d4d, + &pci_dev_info_1002_5d52, + &pci_dev_info_1002_5d57, + &pci_dev_info_1002_5d6d, + &pci_dev_info_1002_5d72, + &pci_dev_info_1002_5d77, + &pci_dev_info_1002_5e48, + &pci_dev_info_1002_5e49, + &pci_dev_info_1002_5e4a, + &pci_dev_info_1002_5e4b, + &pci_dev_info_1002_5e4c, + &pci_dev_info_1002_5e4d, + &pci_dev_info_1002_5e4f, + &pci_dev_info_1002_5e6b, + &pci_dev_info_1002_5e6d, + &pci_dev_info_1002_700f, + &pci_dev_info_1002_7010, + &pci_dev_info_1002_7105, + &pci_dev_info_1002_7109, + &pci_dev_info_1002_7833, + &pci_dev_info_1002_7834, + &pci_dev_info_1002_7835, + &pci_dev_info_1002_7838, + &pci_dev_info_1002_7c37, + &pci_dev_info_1002_cab0, + &pci_dev_info_1002_cab2, + &pci_dev_info_1002_cab3, + &pci_dev_info_1002_cbb2, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0021, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0028, + &pci_dev_info_100b_002a, + &pci_dev_info_100b_002b, + &pci_dev_info_100b_002d, + &pci_dev_info_100b_002e, + &pci_dev_info_100b_002f, + &pci_dev_info_100b_0030, + &pci_dev_info_100b_0035, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_0510, + &pci_dev_info_100b_0511, + &pci_dev_info_100b_0515, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0017, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4000, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0031, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_0037, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003c, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0054, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_005e, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_008b, + &pci_dev_info_1014_008e, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0091, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_009f, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00b8, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0104, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_015e, + &pci_dev_info_1014_0160, + &pci_dev_info_1014_016e, + &pci_dev_info_1014_0170, + &pci_dev_info_1014_017d, + &pci_dev_info_1014_0180, + &pci_dev_info_1014_0188, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_01c1, + &pci_dev_info_1014_01e6, + &pci_dev_info_1014_01ff, + &pci_dev_info_1014_0219, + &pci_dev_info_1014_021b, + &pci_dev_info_1014_021c, + &pci_dev_info_1014_0233, + &pci_dev_info_1014_0266, + &pci_dev_info_1014_0268, + &pci_dev_info_1014_0269, + &pci_dev_info_1014_028c, + &pci_dev_info_1014_02a1, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_0314, + &pci_dev_info_1014_3022, + &pci_dev_info_1014_4022, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_0009, + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2003, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_208f, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700a, + &pci_dev_info_1022_700b, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7458, + &pci_dev_info_1022_7459, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + &pci_dev_info_1022_756b, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_2100, + &pci_dev_info_1023_2200, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_1671, + &pci_dev_info_1025_1672, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_0009, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000d, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + &pci_dev_info_1028_0010, + &pci_dev_info_1028_0011, + &pci_dev_info_1028_0012, + &pci_dev_info_1028_0013, + &pci_dev_info_1028_0014, + &pci_dev_info_1028_0015, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + &pci_dev_info_102a_001f, + &pci_dev_info_102a_00c5, + &pci_dev_info_102a_00cf, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0100, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0528, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_2537, + &pci_dev_info_102b_2538, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_000a, + &pci_dev_info_102f_0020, + &pci_dev_info_102f_0030, + &pci_dev_info_102f_0031, + &pci_dev_info_102f_0105, + &pci_dev_info_102f_0106, + &pci_dev_info_102f_0107, + &pci_dev_info_102f_0108, + &pci_dev_info_102f_0180, + &pci_dev_info_102f_0181, + &pci_dev_info_102f_0182, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0000, + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0072, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a5, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00ce, + &pci_dev_info_1033_00df, + &pci_dev_info_1033_00e0, + &pci_dev_info_1033_00e7, + &pci_dev_info_1033_00f2, + &pci_dev_info_1033_00f3, + &pci_dev_info_1033_010c, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0003, + &pci_dev_info_1039_0004, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_000a, + &pci_dev_info_1039_0016, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0180, + &pci_dev_info_1039_0181, + &pci_dev_info_1039_0182, + &pci_dev_info_1039_0191, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0550, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0648, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0655, + &pci_dev_info_1039_0660, + &pci_dev_info_1039_0661, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0741, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0746, + &pci_dev_info_1039_0755, + &pci_dev_info_1039_0760, + &pci_dev_info_1039_0761, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_0963, + &pci_dev_info_1039_0964, + &pci_dev_info_1039_0965, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_6330, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + &pci_dev_info_1039_7019, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1006, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_100a, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1054, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_10f0, + &pci_dev_info_103c_10f1, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_127c, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_1291, + &pci_dev_info_103c_12b4, + &pci_dev_info_103c_12fa, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + &pci_dev_info_103c_3080, + &pci_dev_info_103c_3220, + &pci_dev_info_103c_3230, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_4015, + &pci_dev_info_1043_4021, + &pci_dev_info_1043_4057, + &pci_dev_info_1043_8043, + &pci_dev_info_1043_807b, + &pci_dev_info_1043_80bb, + &pci_dev_info_1043_80c5, + &pci_dev_info_1043_80df, + &pci_dev_info_1043_8187, + &pci_dev_info_1043_8188, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0c60, + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + &pci_dev_info_1048_8901, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0209, + &pci_dev_info_104a_020a, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_021a, + &pci_dev_info_104a_021b, + &pci_dev_info_104a_0500, + &pci_dev_info_104a_0564, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + &pci_dev_info_104a_55cc, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8025, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8029, + &pci_dev_info_104c_802b, + &pci_dev_info_104c_802e, + &pci_dev_info_104c_8031, + &pci_dev_info_104c_8032, + &pci_dev_info_104c_8033, + &pci_dev_info_104c_8034, + &pci_dev_info_104c_8035, + &pci_dev_info_104c_8036, + &pci_dev_info_104c_8038, + &pci_dev_info_104c_8201, + &pci_dev_info_104c_8204, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_8401, + &pci_dev_info_104c_9000, + &pci_dev_info_104c_9066, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac44, + &pci_dev_info_104c_ac46, + &pci_dev_info_104c_ac47, + &pci_dev_info_104c_ac4a, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac54, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_ac8d, + &pci_dev_info_104c_ac8e, + &pci_dev_info_104c_ac8f, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8004, + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9921, + &pci_dev_info_1050_9922, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0008, + &pci_dev_info_1057_0009, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_18c1, + &pci_dev_info_1057_3410, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_5803, + &pci_dev_info_1057_5806, + &pci_dev_info_1057_5808, + &pci_dev_info_1057_6400, + &pci_dev_info_1057_6405, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3318, + &pci_dev_info_105a_3319, + &pci_dev_info_105a_3371, + &pci_dev_info_105a_3373, + &pci_dev_info_105a_3375, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_3515, + &pci_dev_info_105a_3519, + &pci_dev_info_105a_3571, + &pci_dev_info_105a_3574, + &pci_dev_info_105a_3577, + &pci_dev_info_105a_3d17, + &pci_dev_info_105a_3d18, + &pci_dev_info_105a_3d73, + &pci_dev_info_105a_3d75, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_6622, + &pci_dev_info_105a_6624, + &pci_dev_info_105a_6626, + &pci_dev_info_105a_6629, + &pci_dev_info_105a_7275, + &pci_dev_info_105a_8002, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_0301, + &pci_dev_info_1067_0304, + &pci_dev_info_1067_0308, + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0020, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_b166, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + &pci_dev_info_1069_ba57, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000c, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_0035, + &pci_dev_info_106b_0036, + &pci_dev_info_106b_003b, + &pci_dev_info_106b_003e, + &pci_dev_info_106b_003f, + &pci_dev_info_106b_0040, + &pci_dev_info_106b_0041, + &pci_dev_info_106b_0042, + &pci_dev_info_106b_0043, + &pci_dev_info_106b_0045, + &pci_dev_info_106b_0046, + &pci_dev_info_106b_0047, + &pci_dev_info_106b_0048, + &pci_dev_info_106b_0049, + &pci_dev_info_106b_004b, + &pci_dev_info_106b_004c, + &pci_dev_info_106b_004f, + &pci_dev_info_106b_0050, + &pci_dev_info_106b_0051, + &pci_dev_info_106b_0052, + &pci_dev_info_106b_0053, + &pci_dev_info_106b_0054, + &pci_dev_info_106b_0055, + &pci_dev_info_106b_0058, + &pci_dev_info_106b_0059, + &pci_dev_info_106b_0066, + &pci_dev_info_106b_0067, + &pci_dev_info_106b_0068, + &pci_dev_info_106b_0069, + &pci_dev_info_106b_006a, + &pci_dev_info_106b_006b, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1071[] = { + &pci_dev_info_1071_8160, + NULL +}; +#endif +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + &pci_dev_info_1077_2322, + &pci_dev_info_1077_2422, + &pci_dev_info_1077_2432, + &pci_dev_info_1077_3010, + &pci_dev_info_1077_3022, + &pci_dev_info_1077_4010, + &pci_dev_info_1077_4022, + &pci_dev_info_1077_6312, + &pci_dev_info_1077_6322, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + &pci_dev_info_107d_2134, + &pci_dev_info_107d_2971, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_1648, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_8002, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + &pci_dev_info_108e_a801, + &pci_dev_info_108e_abba, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + &pci_dev_info_1091_07a0, + &pci_dev_info_1091_1091, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1310, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_14e0, + &pci_dev_info_1093_14f0, + &pci_dev_info_1093_17d0, + &pci_dev_info_1093_1870, + &pci_dev_info_1093_1880, + &pci_dev_info_1093_18b0, + &pci_dev_info_1093_2410, + &pci_dev_info_1093_2890, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_2a70, + &pci_dev_info_1093_2a80, + &pci_dev_info_1093_2c80, + &pci_dev_info_1093_2ca0, + &pci_dev_info_1093_70b8, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0240, + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + &pci_dev_info_1095_3114, + &pci_dev_info_1095_3124, + &pci_dev_info_1095_3132, + &pci_dev_info_1095_3512, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_032e, + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_3052, + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_100a, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_4001, + &pci_dev_info_10a9_4002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + &pci_dev_info_10a9_8010, + &pci_dev_info_10a9_8018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1042, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2540, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_6540, + &pci_dev_info_10b5_6541, + &pci_dev_info_10b5_6542, + &pci_dev_info_10b5_8111, + &pci_dev_info_10b5_8114, + &pci_dev_info_10b5_8516, + &pci_dev_info_10b5_8532, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9056, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + &pci_dev_info_10b5_bb04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_0013, + &pci_dev_info_10b7_0910, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_1201, + &pci_dev_info_10b7_1202, + &pci_dev_info_10b7_1700, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6000, + &pci_dev_info_10b7_6001, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7770, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_80eb, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9202, + &pci_dev_info_10b7_9210, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990a, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_2802, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0101, + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_0780, + &pci_dev_info_10b9_0782, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1573, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1672, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_1689, + &pci_dev_info_10b9_1695, + &pci_dev_info_10b9_1697, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_3323, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5228, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5246, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_524b, + &pci_dev_info_10b9_524c, + &pci_dev_info_10b9_524d, + &pci_dev_info_10b9_524e, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5263, + &pci_dev_info_10b9_5281, + &pci_dev_info_10b9_5287, + &pci_dev_info_10b9_5288, + &pci_dev_info_10b9_5289, + &pci_dev_info_10b9_5450, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5461, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + &pci_dev_info_10ba_0304, + &pci_dev_info_10ba_0308, + &pci_dev_info_10ba_1002, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cc[] = { + &pci_dev_info_10cc_0660, + &pci_dev_info_10cc_0661, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0431, + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8626, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dd[] = { + &pci_dev_info_10dd_0100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0034, + &pci_dev_info_10de_0035, + &pci_dev_info_10de_0036, + &pci_dev_info_10de_0037, + &pci_dev_info_10de_0038, + &pci_dev_info_10de_003a, + &pci_dev_info_10de_003b, + &pci_dev_info_10de_003c, + &pci_dev_info_10de_003d, + &pci_dev_info_10de_003e, + &pci_dev_info_10de_0040, + &pci_dev_info_10de_0041, + &pci_dev_info_10de_0042, + &pci_dev_info_10de_0043, + &pci_dev_info_10de_0045, + &pci_dev_info_10de_0046, + &pci_dev_info_10de_0048, + &pci_dev_info_10de_0049, + &pci_dev_info_10de_004e, + &pci_dev_info_10de_0050, + &pci_dev_info_10de_0051, + &pci_dev_info_10de_0052, + &pci_dev_info_10de_0053, + &pci_dev_info_10de_0054, + &pci_dev_info_10de_0055, + &pci_dev_info_10de_0056, + &pci_dev_info_10de_0057, + &pci_dev_info_10de_0058, + &pci_dev_info_10de_0059, + &pci_dev_info_10de_005a, + &pci_dev_info_10de_005b, + &pci_dev_info_10de_005c, + &pci_dev_info_10de_005d, + &pci_dev_info_10de_005e, + &pci_dev_info_10de_005f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006c, + &pci_dev_info_10de_006d, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_0080, + &pci_dev_info_10de_0084, + &pci_dev_info_10de_0085, + &pci_dev_info_10de_0086, + &pci_dev_info_10de_0087, + &pci_dev_info_10de_0088, + &pci_dev_info_10de_008a, + &pci_dev_info_10de_008b, + &pci_dev_info_10de_008c, + &pci_dev_info_10de_008e, + &pci_dev_info_10de_0091, + &pci_dev_info_10de_0092, + &pci_dev_info_10de_0099, + &pci_dev_info_10de_009d, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_00c0, + &pci_dev_info_10de_00c1, + &pci_dev_info_10de_00c2, + &pci_dev_info_10de_00c3, + &pci_dev_info_10de_00c8, + &pci_dev_info_10de_00c9, + &pci_dev_info_10de_00cc, + &pci_dev_info_10de_00cd, + &pci_dev_info_10de_00ce, + &pci_dev_info_10de_00d0, + &pci_dev_info_10de_00d1, + &pci_dev_info_10de_00d2, + &pci_dev_info_10de_00d3, + &pci_dev_info_10de_00d4, + &pci_dev_info_10de_00d5, + &pci_dev_info_10de_00d6, + &pci_dev_info_10de_00d7, + &pci_dev_info_10de_00d8, + &pci_dev_info_10de_00d9, + &pci_dev_info_10de_00da, + &pci_dev_info_10de_00dd, + &pci_dev_info_10de_00df, + &pci_dev_info_10de_00e0, + &pci_dev_info_10de_00e1, + &pci_dev_info_10de_00e2, + &pci_dev_info_10de_00e3, + &pci_dev_info_10de_00e4, + &pci_dev_info_10de_00e5, + &pci_dev_info_10de_00e6, + &pci_dev_info_10de_00e7, + &pci_dev_info_10de_00e8, + &pci_dev_info_10de_00ea, + &pci_dev_info_10de_00ed, + &pci_dev_info_10de_00ee, + &pci_dev_info_10de_00f0, + &pci_dev_info_10de_00f1, + &pci_dev_info_10de_00f2, + &pci_dev_info_10de_00f3, + &pci_dev_info_10de_00f8, + &pci_dev_info_10de_00f9, + &pci_dev_info_10de_00fa, + &pci_dev_info_10de_00fb, + &pci_dev_info_10de_00fc, + &pci_dev_info_10de_00fd, + &pci_dev_info_10de_00fe, + &pci_dev_info_10de_00ff, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0140, + &pci_dev_info_10de_0141, + &pci_dev_info_10de_0142, + &pci_dev_info_10de_0144, + &pci_dev_info_10de_0145, + &pci_dev_info_10de_0146, + &pci_dev_info_10de_0147, + &pci_dev_info_10de_0148, + &pci_dev_info_10de_0149, + &pci_dev_info_10de_014e, + &pci_dev_info_10de_014f, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0160, + &pci_dev_info_10de_0161, + &pci_dev_info_10de_0162, + &pci_dev_info_10de_0163, + &pci_dev_info_10de_0164, + &pci_dev_info_10de_0165, + &pci_dev_info_10de_0166, + &pci_dev_info_10de_0167, + &pci_dev_info_10de_0168, + &pci_dev_info_10de_0169, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0177, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_017d, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0185, + &pci_dev_info_10de_0186, + &pci_dev_info_10de_0187, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_018c, + &pci_dev_info_10de_018d, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b0, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01e0, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01ea, + &pci_dev_info_10de_01eb, + &pci_dev_info_10de_01ec, + &pci_dev_info_10de_01ed, + &pci_dev_info_10de_01ee, + &pci_dev_info_10de_01ef, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0211, + &pci_dev_info_10de_0212, + &pci_dev_info_10de_0215, + &pci_dev_info_10de_0221, + &pci_dev_info_10de_0240, + &pci_dev_info_10de_0241, + &pci_dev_info_10de_0242, + &pci_dev_info_10de_0243, + &pci_dev_info_10de_0244, + &pci_dev_info_10de_0245, + &pci_dev_info_10de_0246, + &pci_dev_info_10de_0247, + &pci_dev_info_10de_0248, + &pci_dev_info_10de_0249, + &pci_dev_info_10de_024a, + &pci_dev_info_10de_024b, + &pci_dev_info_10de_024c, + &pci_dev_info_10de_024d, + &pci_dev_info_10de_024e, + &pci_dev_info_10de_024f, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0260, + &pci_dev_info_10de_0261, + &pci_dev_info_10de_0262, + &pci_dev_info_10de_0263, + &pci_dev_info_10de_0264, + &pci_dev_info_10de_0265, + &pci_dev_info_10de_0266, + &pci_dev_info_10de_0267, + &pci_dev_info_10de_0268, + &pci_dev_info_10de_0269, + &pci_dev_info_10de_026a, + &pci_dev_info_10de_026b, + &pci_dev_info_10de_026c, + &pci_dev_info_10de_026d, + &pci_dev_info_10de_026e, + &pci_dev_info_10de_026f, + &pci_dev_info_10de_0270, + &pci_dev_info_10de_0271, + &pci_dev_info_10de_0272, + &pci_dev_info_10de_027e, + &pci_dev_info_10de_027f, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0286, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_028c, + &pci_dev_info_10de_02a0, + &pci_dev_info_10de_02f0, + &pci_dev_info_10de_02f1, + &pci_dev_info_10de_02f2, + &pci_dev_info_10de_02f3, + &pci_dev_info_10de_02f4, + &pci_dev_info_10de_02f5, + &pci_dev_info_10de_02f6, + &pci_dev_info_10de_02f7, + &pci_dev_info_10de_02f8, + &pci_dev_info_10de_02f9, + &pci_dev_info_10de_02fa, + &pci_dev_info_10de_02fb, + &pci_dev_info_10de_02fc, + &pci_dev_info_10de_02fd, + &pci_dev_info_10de_02fe, + &pci_dev_info_10de_02ff, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + &pci_dev_info_10de_0311, + &pci_dev_info_10de_0312, + &pci_dev_info_10de_0313, + &pci_dev_info_10de_0314, + &pci_dev_info_10de_0316, + &pci_dev_info_10de_0317, + &pci_dev_info_10de_031a, + &pci_dev_info_10de_031b, + &pci_dev_info_10de_031c, + &pci_dev_info_10de_031d, + &pci_dev_info_10de_031e, + &pci_dev_info_10de_031f, + &pci_dev_info_10de_0320, + &pci_dev_info_10de_0321, + &pci_dev_info_10de_0322, + &pci_dev_info_10de_0323, + &pci_dev_info_10de_0324, + &pci_dev_info_10de_0325, + &pci_dev_info_10de_0326, + &pci_dev_info_10de_0327, + &pci_dev_info_10de_0328, + &pci_dev_info_10de_0329, + &pci_dev_info_10de_032a, + &pci_dev_info_10de_032b, + &pci_dev_info_10de_032c, + &pci_dev_info_10de_032d, + &pci_dev_info_10de_032f, + &pci_dev_info_10de_0330, + &pci_dev_info_10de_0331, + &pci_dev_info_10de_0332, + &pci_dev_info_10de_0333, + &pci_dev_info_10de_0334, + &pci_dev_info_10de_0338, + &pci_dev_info_10de_033f, + &pci_dev_info_10de_0341, + &pci_dev_info_10de_0342, + &pci_dev_info_10de_0343, + &pci_dev_info_10de_0344, + &pci_dev_info_10de_0345, + &pci_dev_info_10de_0347, + &pci_dev_info_10de_0348, + &pci_dev_info_10de_0349, + &pci_dev_info_10de_034b, + &pci_dev_info_10de_034c, + &pci_dev_info_10de_034e, + &pci_dev_info_10de_034f, + &pci_dev_info_10de_0360, + &pci_dev_info_10de_0361, + &pci_dev_info_10de_0362, + &pci_dev_info_10de_0363, + &pci_dev_info_10de_0364, + &pci_dev_info_10de_0365, + &pci_dev_info_10de_0366, + &pci_dev_info_10de_0367, + &pci_dev_info_10de_0368, + &pci_dev_info_10de_0369, + &pci_dev_info_10de_036a, + &pci_dev_info_10de_036c, + &pci_dev_info_10de_036d, + &pci_dev_info_10de_036e, + &pci_dev_info_10de_0371, + &pci_dev_info_10de_0372, + &pci_dev_info_10de_0373, + &pci_dev_info_10de_037a, + &pci_dev_info_10de_037e, + &pci_dev_info_10de_037f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f0a1, + &pci_dev_info_10df_f0a5, + &pci_dev_info_10df_f0b5, + &pci_dev_info_10df_f0d1, + &pci_dev_info_10df_f0d5, + &pci_dev_info_10df_f0e1, + &pci_dev_info_10df_f0e5, + &pci_dev_info_10df_f0f5, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f701, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f801, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f901, + &pci_dev_info_10df_f980, + &pci_dev_info_10df_f981, + &pci_dev_info_10df_f982, + &pci_dev_info_10df_fa00, + &pci_dev_info_10df_fb00, + &pci_dev_info_10df_fc00, + &pci_dev_info_10df_fc10, + &pci_dev_info_10df_fc20, + &pci_dev_info_10df_fd00, + &pci_dev_info_10df_fe00, + &pci_dev_info_10df_ff00, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0148, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + &pci_dev_info_10e3_8260, + &pci_dev_info_10e3_8261, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e4[] = { + &pci_dev_info_10e4_8029, + NULL +}; +#endif +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_1072, + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_814c, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_81e6, + &pci_dev_info_10e8_8291, + &pci_dev_info_10e8_82c4, + &pci_dev_info_10e8_82c5, + &pci_dev_info_10e8_82c6, + &pci_dev_info_10e8_82c7, + &pci_dev_info_10e8_82ca, + &pci_dev_info_10e8_82db, + &pci_dev_info_10e8_82e2, + &pci_dev_info_10e8_8851, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + &pci_dev_info_10ea_5252, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_0139, + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8180, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_0314, + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + &pci_dev_info_10ee_3fc6, + &pci_dev_info_10ee_8381, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#define pci_dev_list_10f1 NULL +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + &pci_dev_info_1101_9502, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_0007, + &pci_dev_info_1102_0008, + &pci_dev_info_1102_100a, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_7005, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + &pci_dev_info_1103_0009, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + &pci_dev_info_1105_8401, + &pci_dev_info_1105_8470, + &pci_dev_info_1105_8471, + &pci_dev_info_1105_8475, + &pci_dev_info_1105_8476, + &pci_dev_info_1105_8485, + &pci_dev_info_1105_8486, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0204, + &pci_dev_info_1106_0238, + &pci_dev_info_1106_0259, + &pci_dev_info_1106_0269, + &pci_dev_info_1106_0282, + &pci_dev_info_1106_0290, + &pci_dev_info_1106_0296, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0308, + &pci_dev_info_1106_0314, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0591, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1204, + &pci_dev_info_1106_1208, + &pci_dev_info_1106_1238, + &pci_dev_info_1106_1258, + &pci_dev_info_1106_1259, + &pci_dev_info_1106_1269, + &pci_dev_info_1106_1282, + &pci_dev_info_1106_1290, + &pci_dev_info_1106_1296, + &pci_dev_info_1106_1308, + &pci_dev_info_1106_1314, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_2204, + &pci_dev_info_1106_2208, + &pci_dev_info_1106_2238, + &pci_dev_info_1106_2258, + &pci_dev_info_1106_2259, + &pci_dev_info_1106_2269, + &pci_dev_info_1106_2282, + &pci_dev_info_1106_2290, + &pci_dev_info_1106_2296, + &pci_dev_info_1106_2308, + &pci_dev_info_1106_2314, + &pci_dev_info_1106_287a, + &pci_dev_info_1106_287b, + &pci_dev_info_1106_287c, + &pci_dev_info_1106_287d, + &pci_dev_info_1106_287e, + &pci_dev_info_1106_3022, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3053, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3108, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3113, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3118, + &pci_dev_info_1106_3119, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3149, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3164, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3178, + &pci_dev_info_1106_3188, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_3204, + &pci_dev_info_1106_3205, + &pci_dev_info_1106_3208, + &pci_dev_info_1106_3213, + &pci_dev_info_1106_3218, + &pci_dev_info_1106_3227, + &pci_dev_info_1106_3238, + &pci_dev_info_1106_3249, + &pci_dev_info_1106_3258, + &pci_dev_info_1106_3259, + &pci_dev_info_1106_3269, + &pci_dev_info_1106_3282, + &pci_dev_info_1106_3288, + &pci_dev_info_1106_3290, + &pci_dev_info_1106_3296, + &pci_dev_info_1106_3337, + &pci_dev_info_1106_3349, + &pci_dev_info_1106_337a, + &pci_dev_info_1106_337b, + &pci_dev_info_1106_4149, + &pci_dev_info_1106_4204, + &pci_dev_info_1106_4208, + &pci_dev_info_1106_4238, + &pci_dev_info_1106_4258, + &pci_dev_info_1106_4259, + &pci_dev_info_1106_4269, + &pci_dev_info_1106_4282, + &pci_dev_info_1106_4290, + &pci_dev_info_1106_4296, + &pci_dev_info_1106_4308, + &pci_dev_info_1106_4314, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_5208, + &pci_dev_info_1106_5238, + &pci_dev_info_1106_5290, + &pci_dev_info_1106_5308, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_7204, + &pci_dev_info_1106_7205, + &pci_dev_info_1106_7208, + &pci_dev_info_1106_7238, + &pci_dev_info_1106_7258, + &pci_dev_info_1106_7259, + &pci_dev_info_1106_7269, + &pci_dev_info_1106_7282, + &pci_dev_info_1106_7290, + &pci_dev_info_1106_7296, + &pci_dev_info_1106_7308, + &pci_dev_info_1106_7314, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_a208, + &pci_dev_info_1106_a238, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b113, + &pci_dev_info_1106_b115, + &pci_dev_info_1106_b168, + &pci_dev_info_1106_b188, + &pci_dev_info_1106_b198, + &pci_dev_info_1106_b213, + &pci_dev_info_1106_c208, + &pci_dev_info_1106_c238, + &pci_dev_info_1106_d104, + &pci_dev_info_1106_d208, + &pci_dev_info_1106_d213, + &pci_dev_info_1106_d238, + &pci_dev_info_1106_e208, + &pci_dev_info_1106_e238, + &pci_dev_info_1106_f208, + &pci_dev_info_1106_f238, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_0006, + &pci_dev_info_110a_0015, + &pci_dev_info_110a_001d, + &pci_dev_info_110a_007b, + &pci_dev_info_110a_007c, + &pci_dev_info_110a_007d, + &pci_dev_info_110a_2101, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_2104, + &pci_dev_info_110a_3142, + &pci_dev_info_110a_4021, + &pci_dev_info_110a_4029, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + &pci_dev_info_1113_d301, + &pci_dev_info_1113_ec02, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1114[] = { + &pci_dev_info_1114_0506, + NULL +}; +#endif +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0010, + &pci_dev_info_1119_0011, + &pci_dev_info_1119_0012, + &pci_dev_info_1119_0013, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_02ff, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + &pci_dev_info_111a_1203, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + &pci_dev_info_111d_0004, + &pci_dev_info_111d_0005, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#define pci_dev_list_1124 NULL +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + &pci_dev_info_112f_0008, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_5400, + &pci_dev_info_1131_5402, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7135, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + &pci_dev_info_1131_9730, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e006, + &pci_dev_info_1133_e007, + &pci_dev_info_1133_e008, + &pci_dev_info_1133_e009, + &pci_dev_info_1133_e00a, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e00c, + &pci_dev_info_1133_e00d, + &pci_dev_info_1133_e00e, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e011, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e013, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e015, + &pci_dev_info_1133_e016, + &pci_dev_info_1133_e017, + &pci_dev_info_1133_e018, + &pci_dev_info_1133_e019, + &pci_dev_info_1133_e01a, + &pci_dev_info_1133_e01b, + &pci_dev_info_1133_e01c, + &pci_dev_info_1133_e01e, + &pci_dev_info_1133_e020, + &pci_dev_info_1133_e024, + &pci_dev_info_1133_e028, + &pci_dev_info_1133_e02a, + &pci_dev_info_1133_e02c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + &pci_dev_info_1134_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + &pci_dev_info_1145_f020, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + &pci_dev_info_1148_4500, + &pci_dev_info_1148_9000, + &pci_dev_info_1148_9843, + &pci_dev_info_1148_9e00, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0013, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0028, + &pci_dev_info_114f_0029, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0043, + &pci_dev_info_114f_0044, + &pci_dev_info_114f_0045, + &pci_dev_info_114f_004e, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_00b0, + &pci_dev_info_114f_00b1, + &pci_dev_info_114f_00c8, + &pci_dev_info_114f_00c9, + &pci_dev_info_114f_00ca, + &pci_dev_info_114f_00cb, + &pci_dev_info_114f_00d0, + &pci_dev_info_114f_00d1, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_00d4, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0000, + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0006, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0036, + &pci_dev_info_1166_0101, + &pci_dev_info_1166_0104, + &pci_dev_info_1166_0110, + &pci_dev_info_1166_0130, + &pci_dev_info_1166_0132, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0205, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0214, + &pci_dev_info_1166_0217, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0223, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + &pci_dev_info_1166_0230, + &pci_dev_info_1166_0234, + &pci_dev_info_1166_0240, + &pci_dev_info_1166_0241, + &pci_dev_info_1166_0242, + &pci_dev_info_1166_024a, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0102, + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_117c[] = { + &pci_dev_info_117c_0030, + NULL +}; +#endif +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0511, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + &pci_dev_info_1180_0554, + &pci_dev_info_1180_0575, + &pci_dev_info_1180_0576, + &pci_dev_info_1180_0592, + &pci_dev_info_1180_0811, + &pci_dev_info_1180_0822, + &pci_dev_info_1180_0841, + &pci_dev_info_1180_0852, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1025, + &pci_dev_info_1186_1026, + &pci_dev_info_1186_1043, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1541, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_2027, + &pci_dev_info_1186_3203, + &pci_dev_info_1186_3300, + &pci_dev_info_1186_3a03, + &pci_dev_info_1186_3a04, + &pci_dev_info_1186_3a05, + &pci_dev_info_1186_3a07, + &pci_dev_info_1186_3a08, + &pci_dev_info_1186_3a10, + &pci_dev_info_1186_3a11, + &pci_dev_info_1186_3a12, + &pci_dev_info_1186_3a13, + &pci_dev_info_1186_3a14, + &pci_dev_info_1186_3a63, + &pci_dev_info_1186_4000, + &pci_dev_info_1186_4300, + &pci_dev_info_1186_4c00, + &pci_dev_info_1186_8400, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + &pci_dev_info_1191_8060, + &pci_dev_info_1191_8080, + &pci_dev_info_1191_8081, + &pci_dev_info_1191_808a, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1197[] = { + &pci_dev_info_1197_010c, + NULL +}; +#endif +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_138f, + &pci_dev_info_11ab_1fa6, + &pci_dev_info_11ab_1fa7, + &pci_dev_info_11ab_1faa, + &pci_dev_info_11ab_4320, + &pci_dev_info_11ab_4340, + &pci_dev_info_11ab_4341, + &pci_dev_info_11ab_4342, + &pci_dev_info_11ab_4343, + &pci_dev_info_11ab_4344, + &pci_dev_info_11ab_4345, + &pci_dev_info_11ab_4346, + &pci_dev_info_11ab_4347, + &pci_dev_info_11ab_4350, + &pci_dev_info_11ab_4351, + &pci_dev_info_11ab_4352, + &pci_dev_info_11ab_4360, + &pci_dev_info_11ab_4361, + &pci_dev_info_11ab_4362, + &pci_dev_info_11ab_4363, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_5005, + &pci_dev_info_11ab_5040, + &pci_dev_info_11ab_5041, + &pci_dev_info_11ab_5080, + &pci_dev_info_11ab_5081, + &pci_dev_info_11ab_6041, + &pci_dev_info_11ab_6081, + &pci_dev_info_11ab_6460, + &pci_dev_info_11ab_6480, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11af[] = { + &pci_dev_info_11af_0001, + &pci_dev_info_11af_ee40, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bd[] = { + &pci_dev_info_11bd_bede, + NULL +}; +#endif +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_048c, + &pci_dev_info_11c1_048f, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + &pci_dev_info_11c1_8110, + &pci_dev_info_11c1_ab10, + &pci_dev_info_11c1_ab11, + &pci_dev_info_11c1_ab20, + &pci_dev_info_11c1_ab21, + &pci_dev_info_11c1_ab30, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1535, + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + &pci_dev_info_11d4_5340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_0001, + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_000d, + &pci_dev_info_11fe_000e, + &pci_dev_info_11fe_000f, + &pci_dev_info_11fe_0801, + &pci_dev_info_11fe_0802, + &pci_dev_info_11fe_0803, + &pci_dev_info_11fe_0805, + &pci_dev_info_11fe_080c, + &pci_dev_info_11fe_080d, + &pci_dev_info_11fe_0812, + &pci_dev_info_11fe_0903, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ff[] = { + &pci_dev_info_11ff_0003, + NULL +}; +#endif +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + &pci_dev_info_1217_7110, + &pci_dev_info_1217_7112, + &pci_dev_info_1217_7113, + &pci_dev_info_1217_7114, + &pci_dev_info_1217_7134, + &pci_dev_info_1217_71e2, + &pci_dev_info_1217_7212, + &pci_dev_info_1217_7213, + &pci_dev_info_1217_7223, + &pci_dev_info_1217_7233, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#define pci_dev_list_121e NULL +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1227[] = { + &pci_dev_info_1227_0006, + &pci_dev_info_1227_0023, + NULL +}; +#endif +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_1400, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + &pci_dev_info_1242_6562, + &pci_dev_info_1242_656a, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + &pci_dev_info_1244_2700, + &pci_dev_info_1244_2900, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + &pci_dev_info_1259_a117, + &pci_dev_info_1259_a120, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0101, + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3872, + &pci_dev_info_1260_3873, + &pci_dev_info_1260_3886, + &pci_dev_info_1260_3890, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + &pci_dev_info_1260_ffff, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_126c[] = { + &pci_dev_info_126c_1211, + &pci_dev_info_126c_126c, + NULL +}; +#endif +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0501, + &pci_dev_info_126f_0510, + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0730, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1171, + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + &pci_dev_info_1278_0710, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0060, + &pci_dev_info_1279_0061, + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8211, + &pci_dev_info_1283_8212, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8872, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12a3[] = { + &pci_dev_info_12a3_8105, + NULL +}; +#endif +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_0000, + &pci_dev_info_12ab_0002, + &pci_dev_info_12ab_3000, + &pci_dev_info_12ab_fff3, + &pci_dev_info_12ab_ffff, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + &pci_dev_info_12ae_00fa, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c4[] = { + &pci_dev_info_12c4_0001, + &pci_dev_info_12c4_0002, + &pci_dev_info_12c4_0003, + &pci_dev_info_12c4_0004, + &pci_dev_info_12c4_0005, + &pci_dev_info_12c4_0006, + &pci_dev_info_12c4_0007, + &pci_dev_info_12c4_0008, + &pci_dev_info_12c4_0009, + &pci_dev_info_12c4_000a, + &pci_dev_info_12c4_000b, + &pci_dev_info_12c4_000c, + &pci_dev_info_12c4_000d, + &pci_dev_info_12c4_0100, + &pci_dev_info_12c4_0201, + &pci_dev_info_12c4_0202, + &pci_dev_info_12c4_0300, + &pci_dev_info_12c4_0301, + &pci_dev_info_12c4_0302, + &pci_dev_info_12c4_0310, + &pci_dev_info_12c4_0311, + &pci_dev_info_12c4_0312, + &pci_dev_info_12c4_0320, + &pci_dev_info_12c4_0321, + &pci_dev_info_12c4_0322, + &pci_dev_info_12c4_0330, + &pci_dev_info_12c4_0331, + &pci_dev_info_12c4_0332, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d4[] = { + &pci_dev_info_12d4_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d5[] = { + &pci_dev_info_12d5_0003, + &pci_dev_info_12d5_1000, + NULL +}; +#endif +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d8[] = { + &pci_dev_info_12d8_8150, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d9[] = { + &pci_dev_info_12d9_0002, + &pci_dev_info_12d9_0004, + &pci_dev_info_12d9_0005, + NULL +}; +#endif +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12de[] = { + &pci_dev_info_12de_0200, + NULL +}; +#endif +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12fb[] = { + &pci_dev_info_12fb_0001, + &pci_dev_info_12fb_00f5, + &pci_dev_info_12fb_02ad, + &pci_dev_info_12fb_2adc, + &pci_dev_info_12fb_3100, + &pci_dev_info_12fb_3500, + &pci_dev_info_12fb_4d4f, + &pci_dev_info_12fb_8120, + &pci_dev_info_12fb_da62, + &pci_dev_info_12fb_db62, + &pci_dev_info_12fb_dc62, + &pci_dev_info_12fb_dd62, + &pci_dev_info_12fb_eddc, + &pci_dev_info_12fb_fa01, + NULL +}; +#endif +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + &pci_dev_info_1307_004d, + &pci_dev_info_1307_0052, + &pci_dev_info_1307_0054, + &pci_dev_info_1307_005e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + &pci_dev_info_1317_2850, + &pci_dev_info_1317_5120, + &pci_dev_info_1317_8201, + &pci_dev_info_1317_8211, + &pci_dev_info_1317_9511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + &pci_dev_info_131f_2081, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1331[] = { + &pci_dev_info_1331_0030, + &pci_dev_info_1331_8200, + &pci_dev_info_1331_8201, + &pci_dev_info_1331_8202, + &pci_dev_info_1331_8210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + &pci_dev_info_1332_5425, + &pci_dev_info_1332_6140, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_2189, + &pci_dev_info_134d_2486, + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_5101, + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1360[] = { + &pci_dev_info_1360_0101, + &pci_dev_info_1360_0102, + &pci_dev_info_1360_0103, + &pci_dev_info_1360_0201, + &pci_dev_info_1360_0202, + &pci_dev_info_1360_0203, + &pci_dev_info_1360_0301, + &pci_dev_info_1360_0302, + NULL +}; +#endif +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#define pci_dev_list_136a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136b[] = { + &pci_dev_info_136b_ff01, + NULL +}; +#endif +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1371[] = { + &pci_dev_info_1371_434e, + NULL +}; +#endif +#define pci_dev_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1374[] = { + &pci_dev_info_1374_0024, + &pci_dev_info_1374_0025, + &pci_dev_info_1374_0026, + &pci_dev_info_1374_0027, + &pci_dev_info_1374_0029, + &pci_dev_info_1374_002a, + &pci_dev_info_1374_002b, + &pci_dev_info_1374_002c, + &pci_dev_info_1374_002d, + &pci_dev_info_1374_002e, + &pci_dev_info_1374_002f, + &pci_dev_info_1374_0030, + &pci_dev_info_1374_0031, + &pci_dev_info_1374_0032, + &pci_dev_info_1374_0034, + &pci_dev_info_1374_0035, + &pci_dev_info_1374_0036, + &pci_dev_info_1374_0037, + &pci_dev_info_1374_0038, + &pci_dev_info_1374_0039, + &pci_dev_info_1374_003a, + NULL +}; +#endif +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_137a[] = { + &pci_dev_info_137a_0001, + NULL +}; +#endif +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1382[] = { + &pci_dev_info_1382_0001, + &pci_dev_info_1382_2008, + &pci_dev_info_1382_2088, + &pci_dev_info_1382_20c8, + &pci_dev_info_1382_4008, + &pci_dev_info_1382_4010, + &pci_dev_info_1382_4048, + &pci_dev_info_1382_4088, + &pci_dev_info_1382_4248, + NULL +}; +#endif +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_0013, + &pci_dev_info_1385_311a, + &pci_dev_info_1385_4100, + &pci_dev_info_1385_4105, + &pci_dev_info_1385_4400, + &pci_dev_info_1385_4600, + &pci_dev_info_1385_4601, + &pci_dev_info_1385_4610, + &pci_dev_info_1385_4800, + &pci_dev_info_1385_4900, + &pci_dev_info_1385_4a00, + &pci_dev_info_1385_4b00, + &pci_dev_info_1385_4c00, + &pci_dev_info_1385_4e00, + &pci_dev_info_1385_4f00, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_6b00, + &pci_dev_info_1385_f004, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1141, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_16b8, + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + &pci_dev_info_13a3_001d, + &pci_dev_info_13a3_0020, + &pci_dev_info_13a3_0026, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0152, + &pci_dev_info_13a8_0154, + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + &pci_dev_info_13c0_0020, + &pci_dev_info_13c0_0030, + &pci_dev_info_13c0_0210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + &pci_dev_info_13c1_1003, + NULL +}; +#endif +#define pci_dev_list_13c2 NULL +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c6[] = { + &pci_dev_info_13c6_0520, + &pci_dev_info_13c6_0620, + &pci_dev_info_13c6_0820, + NULL +}; +#endif +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + &pci_dev_info_13d0_2200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab03, + &pci_dev_info_13d1_ab06, + &pci_dev_info_13d1_ab08, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#define pci_dev_list_13ec NULL +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0200, + &pci_dev_info_13f0_0201, + &pci_dev_info_13f0_1023, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0011, + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1240, + &pci_dev_info_13fe_1600, + &pci_dev_info_13fe_1733, + &pci_dev_info_13fe_1752, + &pci_dev_info_13fe_1754, + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0110, + &pci_dev_info_1407_0111, + &pci_dev_info_1407_0120, + &pci_dev_info_1407_0121, + &pci_dev_info_1407_0180, + &pci_dev_info_1407_0181, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0220, + &pci_dev_info_1407_0221, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9510, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9521, + &pci_dev_info_1415_9523, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1420[] = { + &pci_dev_info_1420_8002, + &pci_dev_info_1420_8003, + NULL +}; +#endif +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1425[] = { + &pci_dev_info_1425_000b, + NULL +}; +#endif +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_142e[] = { + &pci_dev_info_142e_4020, + &pci_dev_info_142e_4337, + NULL +}; +#endif +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1432[] = { + &pci_dev_info_1432_9130, + NULL +}; +#endif +#define pci_dev_list_1433 NULL +#define pci_dev_list_1435 NULL +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8164, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#define pci_dev_list_144d NULL +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1458[] = { + &pci_dev_info_1458_0c11, + &pci_dev_info_1458_e911, + NULL +}; +#endif +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1461[] = { + &pci_dev_info_1461_a3ce, + &pci_dev_info_1461_a3cf, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1462[] = { + &pci_dev_info_1462_5501, + &pci_dev_info_1462_6819, + &pci_dev_info_1462_6825, + &pci_dev_info_1462_8725, + &pci_dev_info_1462_9000, + &pci_dev_info_1462_9110, + &pci_dev_info_1462_9119, + &pci_dev_info_1462_9591, + NULL +}; +#endif +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_146c[] = { + &pci_dev_info_146c_1430, + NULL +}; +#endif +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1497[] = { + &pci_dev_info_1497_1497, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1498[] = { + &pci_dev_info_1498_21cd, + &pci_dev_info_1498_30c8, + NULL +}; +#endif +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_149d[] = { + &pci_dev_info_149d_0001, + NULL +}; +#endif +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + &pci_dev_info_14b9_a505, + &pci_dev_info_14b9_a506, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#define pci_dev_list_14bc NULL +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14c1[] = { + &pci_dev_info_14c1_8043, + NULL +}; +#endif +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d9[] = { + &pci_dev_info_14d9_0010, + &pci_dev_info_14d9_9000, + NULL +}; +#endif +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_0800, + &pci_dev_info_14e4_0804, + &pci_dev_info_14e4_0805, + &pci_dev_info_14e4_0806, + &pci_dev_info_14e4_080b, + &pci_dev_info_14e4_080f, + &pci_dev_info_14e4_0811, + &pci_dev_info_14e4_0816, + &pci_dev_info_14e4_1600, + &pci_dev_info_14e4_1601, + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164a, + &pci_dev_info_14e4_164c, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_1654, + &pci_dev_info_14e4_1659, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_165e, + &pci_dev_info_14e4_1668, + &pci_dev_info_14e4_166a, + &pci_dev_info_14e4_166b, + &pci_dev_info_14e4_166e, + &pci_dev_info_14e4_1677, + &pci_dev_info_14e4_1678, + &pci_dev_info_14e4_167d, + &pci_dev_info_14e4_167e, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_169c, + &pci_dev_info_14e4_169d, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16aa, + &pci_dev_info_14e4_16ac, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_16dd, + &pci_dev_info_14e4_16f7, + &pci_dev_info_14e4_16fd, + &pci_dev_info_14e4_16fe, + &pci_dev_info_14e4_170c, + &pci_dev_info_14e4_170d, + &pci_dev_info_14e4_170e, + &pci_dev_info_14e4_3352, + &pci_dev_info_14e4_3360, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4305, + &pci_dev_info_14e4_4306, + &pci_dev_info_14e4_4307, + &pci_dev_info_14e4_4310, + &pci_dev_info_14e4_4312, + &pci_dev_info_14e4_4313, + &pci_dev_info_14e4_4315, + &pci_dev_info_14e4_4318, + &pci_dev_info_14e4_4319, + &pci_dev_info_14e4_4320, + &pci_dev_info_14e4_4321, + &pci_dev_info_14e4_4322, + &pci_dev_info_14e4_4324, + &pci_dev_info_14e4_4325, + &pci_dev_info_14e4_4326, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4403, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_4430, + &pci_dev_info_14e4_4432, + &pci_dev_info_14e4_4610, + &pci_dev_info_14e4_4611, + &pci_dev_info_14e4_4612, + &pci_dev_info_14e4_4613, + &pci_dev_info_14e4_4614, + &pci_dev_info_14e4_4615, + &pci_dev_info_14e4_4704, + &pci_dev_info_14e4_4705, + &pci_dev_info_14e4_4706, + &pci_dev_info_14e4_4707, + &pci_dev_info_14e4_4708, + &pci_dev_info_14e4_4710, + &pci_dev_info_14e4_4711, + &pci_dev_info_14e4_4712, + &pci_dev_info_14e4_4713, + &pci_dev_info_14e4_4714, + &pci_dev_info_14e4_4715, + &pci_dev_info_14e4_4716, + &pci_dev_info_14e4_4717, + &pci_dev_info_14e4_4718, + &pci_dev_info_14e4_4720, + &pci_dev_info_14e4_5365, + &pci_dev_info_14e4_5600, + &pci_dev_info_14e4_5605, + &pci_dev_info_14e4_5615, + &pci_dev_info_14e4_5625, + &pci_dev_info_14e4_5645, + &pci_dev_info_14e4_5670, + &pci_dev_info_14e4_5680, + &pci_dev_info_14e4_5690, + &pci_dev_info_14e4_5691, + &pci_dev_info_14e4_5692, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + &pci_dev_info_14e4_5822, + &pci_dev_info_14e4_5823, + &pci_dev_info_14e4_5824, + &pci_dev_info_14e4_5840, + &pci_dev_info_14e4_5841, + &pci_dev_info_14e4_5850, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + &pci_dev_info_14ea_ab07, + &pci_dev_info_14ea_ab08, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1085, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1620, + &pci_dev_info_14f1_1621, + &pci_dev_info_14f1_1622, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1811, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_2f02, + &pci_dev_info_14f1_2f11, + &pci_dev_info_14f1_2f20, + &pci_dev_info_14f1_8234, + &pci_dev_info_14f1_8800, + &pci_dev_info_14f1_8801, + &pci_dev_info_14f1_8802, + &pci_dev_info_14f1_8804, + &pci_dev_info_14f1_8811, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f2[] = { + &pci_dev_info_14f2_0120, + &pci_dev_info_14f2_0121, + &pci_dev_info_14f2_0122, + &pci_dev_info_14f2_0123, + &pci_dev_info_14f2_0124, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f3[] = { + &pci_dev_info_14f3_2030, + &pci_dev_info_14f3_2050, + &pci_dev_info_14f3_2060, + NULL +}; +#endif +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f8[] = { + &pci_dev_info_14f8_2077, + NULL +}; +#endif +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14fc[] = { + &pci_dev_info_14fc_0000, + &pci_dev_info_14fc_0001, + NULL +}; +#endif +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1500[] = { + &pci_dev_info_1500_1360, + NULL +}; +#endif +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0800, + &pci_dev_info_1516_0803, + &pci_dev_info_1516_0891, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151c[] = { + &pci_dev_info_151c_0003, + &pci_dev_info_151c_4000, + NULL +}; +#endif +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_0510, + &pci_dev_info_1524_0520, + &pci_dev_info_1524_0530, + &pci_dev_info_1524_0550, + &pci_dev_info_1524_0610, + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1411, + &pci_dev_info_1524_1412, + &pci_dev_info_1524_1420, + &pci_dev_info_1524_1421, + &pci_dev_info_1524_1422, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#define pci_dev_list_1532 NULL +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1538[] = { + &pci_dev_info_1538_0303, + NULL +}; +#endif +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153b[] = { + &pci_dev_info_153b_1144, + &pci_dev_info_153b_1147, + &pci_dev_info_153b_1158, + NULL +}; +#endif +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153f[] = { + &pci_dev_info_153f_0001, + NULL +}; +#endif +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#define pci_dev_list_1542 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1578[] = { + &pci_dev_info_1578_5615, + NULL +}; +#endif +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0405, + &pci_dev_info_15ad_0710, + &pci_dev_info_15ad_0720, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + &pci_dev_info_15b3_5a44, + &pci_dev_info_15b3_5a45, + &pci_dev_info_15b3_5a46, + &pci_dev_info_15b3_5e8d, + &pci_dev_info_15b3_6274, + &pci_dev_info_15b3_6278, + &pci_dev_info_15b3_6279, + &pci_dev_info_15b3_6282, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_1100, + &pci_dev_info_15bc_2922, + &pci_dev_info_15bc_2928, + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c5[] = { + &pci_dev_info_15c5_8010, + NULL +}; +#endif +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e9[] = { + &pci_dev_info_15e9_1841, + NULL +}; +#endif +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15ec[] = { + &pci_dev_info_15ec_3101, + &pci_dev_info_15ec_5102, + NULL +}; +#endif +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + &pci_dev_info_1619_0610, + &pci_dev_info_1619_0620, + &pci_dev_info_1619_0640, + &pci_dev_info_1619_1610, + &pci_dev_info_1619_2610, + NULL +}; +#endif +#define pci_dev_list_161f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1626[] = { + &pci_dev_info_1626_8410, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1637[] = { + &pci_dev_info_1637_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_3052, + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165f[] = { + &pci_dev_info_165f_1020, + NULL +}; +#endif +#define pci_dev_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1668[] = { + &pci_dev_info_1668_0100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_166d[] = { + &pci_dev_info_166d_0001, + &pci_dev_info_166d_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1677[] = { + &pci_dev_info_1677_104e, + &pci_dev_info_1677_12d7, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167b[] = { + &pci_dev_info_167b_2102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1681[] = { + &pci_dev_info_1681_0010, + NULL +}; +#endif +#define pci_dev_list_1682 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1688[] = { + &pci_dev_info_1688_1170, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_168c[] = { + &pci_dev_info_168c_0007, + &pci_dev_info_168c_0011, + &pci_dev_info_168c_0012, + &pci_dev_info_168c_0013, + &pci_dev_info_168c_001a, + &pci_dev_info_168c_001b, + &pci_dev_info_168c_0020, + &pci_dev_info_168c_1014, + NULL +}; +#endif +#define pci_dev_list_1695 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_169c[] = { + &pci_dev_info_169c_0044, + NULL +}; +#endif +#define pci_dev_list_16a5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1100, + &pci_dev_info_16ab_1101, + &pci_dev_info_16ab_1102, + &pci_dev_info_16ab_8501, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ae[] = { + &pci_dev_info_16ae_1141, + NULL +}; +#endif +#define pci_dev_list_16af NULL +#define pci_dev_list_16b4 NULL +#define pci_dev_list_16b8 NULL +#define pci_dev_list_16be NULL +#define pci_dev_list_16c8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ca[] = { + &pci_dev_info_16ca_0001, + NULL +}; +#endif +#define pci_dev_list_16cd NULL +#define pci_dev_list_16ce NULL +#define pci_dev_list_16df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e3[] = { + &pci_dev_info_16e3_1e0f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_00ff, + &pci_dev_info_16ec_0116, + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ed[] = { + &pci_dev_info_16ed_1001, + NULL +}; +#endif +#define pci_dev_list_16f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16f4[] = { + &pci_dev_info_16f4_8000, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1702 NULL +#define pci_dev_list_1705 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_170b[] = { + &pci_dev_info_170b_0100, + NULL +}; +#endif +#define pci_dev_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1725[] = { + &pci_dev_info_1725_7174, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_172a[] = { + &pci_dev_info_172a_13c8, + NULL +}; +#endif +#define pci_dev_list_1734 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1737[] = { + &pci_dev_info_1737_0013, + &pci_dev_info_1737_0015, + &pci_dev_info_1737_1032, + &pci_dev_info_1737_1064, + &pci_dev_info_1737_ab08, + &pci_dev_info_1737_ab09, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03e9, + &pci_dev_info_173b_03ea, + &pci_dev_info_173b_03eb, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_1749 NULL +#define pci_dev_list_174b NULL +#define pci_dev_list_174d NULL +#define pci_dev_list_175c NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1775 NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1799[] = { + &pci_dev_info_1799_6001, + &pci_dev_info_1799_6020, + &pci_dev_info_1799_6060, + &pci_dev_info_1799_7000, + &pci_dev_info_1799_7010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_179c[] = { + &pci_dev_info_179c_0557, + &pci_dev_info_179c_0566, + &pci_dev_info_179c_5031, + &pci_dev_info_179c_5121, + &pci_dev_info_179c_5211, + &pci_dev_info_179c_5679, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17a0[] = { + &pci_dev_info_17a0_8033, + &pci_dev_info_17a0_8034, + NULL +}; +#endif +#define pci_dev_list_17aa NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b3[] = { + &pci_dev_info_17b3_ab08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b4[] = { + &pci_dev_info_17b4_0011, + NULL +}; +#endif +#define pci_dev_list_17c0 NULL +#define pci_dev_list_17c2 NULL +#define pci_dev_list_17cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#define pci_dev_list_17cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d3[] = { + &pci_dev_info_17d3_1110, + &pci_dev_info_17d3_1120, + &pci_dev_info_17d3_1130, + &pci_dev_info_17d3_1160, + &pci_dev_info_17d3_1210, + &pci_dev_info_17d3_1220, + &pci_dev_info_17d3_1230, + &pci_dev_info_17d3_1260, + &pci_dev_info_17d3_5831, + &pci_dev_info_17d3_5832, + NULL +}; +#endif +#define pci_dev_list_17de NULL +#define pci_dev_list_17ee NULL +#define pci_dev_list_17f2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17fe[] = { + &pci_dev_info_17fe_2120, + &pci_dev_info_17fe_2220, + NULL +}; +#endif +#define pci_dev_list_17ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1814[] = { + &pci_dev_info_1814_0101, + &pci_dev_info_1814_0201, + &pci_dev_info_1814_0401, + NULL +}; +#endif +#define pci_dev_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1822[] = { + &pci_dev_info_1822_4e35, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182d[] = { + &pci_dev_info_182d_3069, + &pci_dev_info_182d_9790, + NULL +}; +#endif +#define pci_dev_list_1830 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_183b[] = { + &pci_dev_info_183b_08a7, + &pci_dev_info_183b_08a8, + &pci_dev_info_183b_08a9, + NULL +}; +#endif +#define pci_dev_list_1849 NULL +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#define pci_dev_list_1854 NULL +#define pci_dev_list_185b NULL +#define pci_dev_list_185f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1864[] = { + &pci_dev_info_1864_2110, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1867[] = { + &pci_dev_info_1867_5a44, + &pci_dev_info_1867_5a45, + &pci_dev_info_1867_5a46, + &pci_dev_info_1867_6278, + &pci_dev_info_1867_6282, + NULL +}; +#endif +#define pci_dev_list_187e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#define pci_dev_list_1894 NULL +#define pci_dev_list_1896 NULL +#define pci_dev_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ac[] = { + &pci_dev_info_18ac_d500, + &pci_dev_info_18ac_d810, + &pci_dev_info_18ac_d820, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18b8[] = { + &pci_dev_info_18b8_b001, + NULL +}; +#endif +#define pci_dev_list_18bc NULL +#define pci_dev_list_18c8 NULL +#define pci_dev_list_18c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ca[] = { + &pci_dev_info_18ca_0020, + &pci_dev_info_18ca_0040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18d2[] = { + &pci_dev_info_18d2_3069, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18dd[] = { + &pci_dev_info_18dd_4c6f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18e6[] = { + &pci_dev_info_18e6_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ec[] = { + &pci_dev_info_18ec_c006, + &pci_dev_info_18ec_c045, + &pci_dev_info_18ec_c050, + &pci_dev_info_18ec_c058, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f7[] = { + &pci_dev_info_18f7_0001, + &pci_dev_info_18f7_0002, + &pci_dev_info_18f7_0004, + &pci_dev_info_18f7_0005, + &pci_dev_info_18f7_000a, + NULL +}; +#endif +#define pci_dev_list_18fb NULL +#define pci_dev_list_1924 NULL +#define pci_dev_list_192e NULL +#define pci_dev_list_1931 NULL +#define pci_dev_list_1942 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1957[] = { + &pci_dev_info_1957_0080, + &pci_dev_info_1957_0081, + &pci_dev_info_1957_0082, + &pci_dev_info_1957_0083, + &pci_dev_info_1957_0084, + &pci_dev_info_1957_0085, + &pci_dev_info_1957_0086, + &pci_dev_info_1957_0087, + NULL +}; +#endif +#define pci_dev_list_1958 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1966[] = { + &pci_dev_info_1966_1975, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_196a[] = { + &pci_dev_info_196a_0101, + &pci_dev_info_196a_0102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_197b[] = { + &pci_dev_info_197b_2360, + &pci_dev_info_197b_2363, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1989[] = { + &pci_dev_info_1989_0001, + &pci_dev_info_1989_8001, + NULL +}; +#endif +#define pci_dev_list_1993 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ae[] = { + &pci_dev_info_19ae_0520, + NULL +}; +#endif +#define pci_dev_list_19d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc0[] = { + &pci_dev_info_1fc0_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc1[] = { + &pci_dev_info_1fc1_000d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fce[] = { + &pci_dev_info_1fce_0001, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0020, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_0022, + &pci_dev_info_3388_0026, + &pci_dev_info_3388_101a, + &pci_dev_info_3388_101b, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3842[] = { + &pci_dev_info_3842_c370, + NULL +}; +#endif +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_000d, + &pci_dev_info_3d3d_0011, + &pci_dev_info_3d3d_0012, + &pci_dev_info_3d3d_0013, + &pci_dev_info_3d3d_0020, + &pci_dev_info_3d3d_0022, + &pci_dev_info_3d3d_0024, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_07a1, + &pci_dev_info_3d3d_07a2, + &pci_dev_info_3d3d_07a3, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4144[] = { + &pci_dev_info_4144_0044, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0016, + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_494f[] = { + &pci_dev_info_494f_10e8, + NULL +}; +#endif +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4c53[] = { + &pci_dev_info_4c53_0000, + &pci_dev_info_4c53_0001, + NULL +}; +#endif +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5168[] = { + &pci_dev_info_5168_0301, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_544c[] = { + &pci_dev_info_544c_0350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5654[] = { + &pci_dev_info_5654_3132, + NULL +}; +#endif +#define pci_dev_list_5700 NULL +#define pci_dev_list_5851 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + &pci_dev_info_6666_0004, + &pci_dev_info_6666_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_7063[] = { + &pci_dev_info_7063_2000, + &pci_dev_info_7063_3000, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +#define pci_dev_list_807d NULL +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0309, + &pci_dev_info_8086_030d, + &pci_dev_info_8086_0326, + &pci_dev_info_8086_0327, + &pci_dev_info_8086_0329, + &pci_dev_info_8086_032a, + &pci_dev_info_8086_032c, + &pci_dev_info_8086_0330, + &pci_dev_info_8086_0331, + &pci_dev_info_8086_0332, + &pci_dev_info_8086_0333, + &pci_dev_info_8086_0334, + &pci_dev_info_8086_0335, + &pci_dev_info_8086_0336, + &pci_dev_info_8086_0340, + &pci_dev_info_8086_0341, + &pci_dev_info_8086_0370, + &pci_dev_info_8086_0371, + &pci_dev_info_8086_0372, + &pci_dev_info_8086_0373, + &pci_dev_info_8086_0374, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0500, + &pci_dev_info_8086_0501, + &pci_dev_info_8086_0502, + &pci_dev_info_8086_0503, + &pci_dev_info_8086_0510, + &pci_dev_info_8086_0511, + &pci_dev_info_8086_0512, + &pci_dev_info_8086_0513, + &pci_dev_info_8086_0514, + &pci_dev_info_8086_0515, + &pci_dev_info_8086_0516, + &pci_dev_info_8086_0530, + &pci_dev_info_8086_0531, + &pci_dev_info_8086_0532, + &pci_dev_info_8086_0533, + &pci_dev_info_8086_0534, + &pci_dev_info_8086_0535, + &pci_dev_info_8086_0536, + &pci_dev_info_8086_0537, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_061f, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100a, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1013, + &pci_dev_info_8086_1014, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1016, + &pci_dev_info_8086_1017, + &pci_dev_info_8086_1018, + &pci_dev_info_8086_1019, + &pci_dev_info_8086_101a, + &pci_dev_info_8086_101d, + &pci_dev_info_8086_101e, + &pci_dev_info_8086_1026, + &pci_dev_info_8086_1027, + &pci_dev_info_8086_1028, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1043, + &pci_dev_info_8086_1048, + &pci_dev_info_8086_1050, + &pci_dev_info_8086_1051, + &pci_dev_info_8086_1052, + &pci_dev_info_8086_1053, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_105e, + &pci_dev_info_8086_105f, + &pci_dev_info_8086_1060, + &pci_dev_info_8086_1064, + &pci_dev_info_8086_1065, + &pci_dev_info_8086_1066, + &pci_dev_info_8086_1067, + &pci_dev_info_8086_1068, + &pci_dev_info_8086_1069, + &pci_dev_info_8086_106a, + &pci_dev_info_8086_106b, + &pci_dev_info_8086_1075, + &pci_dev_info_8086_1076, + &pci_dev_info_8086_1077, + &pci_dev_info_8086_1078, + &pci_dev_info_8086_1079, + &pci_dev_info_8086_107a, + &pci_dev_info_8086_107b, + &pci_dev_info_8086_107c, + &pci_dev_info_8086_107d, + &pci_dev_info_8086_107e, + &pci_dev_info_8086_107f, + &pci_dev_info_8086_1080, + &pci_dev_info_8086_1081, + &pci_dev_info_8086_1082, + &pci_dev_info_8086_1083, + &pci_dev_info_8086_1084, + &pci_dev_info_8086_1085, + &pci_dev_info_8086_1086, + &pci_dev_info_8086_1087, + &pci_dev_info_8086_1089, + &pci_dev_info_8086_108a, + &pci_dev_info_8086_108b, + &pci_dev_info_8086_108c, + &pci_dev_info_8086_1096, + &pci_dev_info_8086_1097, + &pci_dev_info_8086_1098, + &pci_dev_info_8086_1099, + &pci_dev_info_8086_109a, + &pci_dev_info_8086_1107, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123e, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_1a38, + &pci_dev_info_8086_1a48, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c1, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24ca, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cc, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_24d0, + &pci_dev_info_8086_24d1, + &pci_dev_info_8086_24d2, + &pci_dev_info_8086_24d3, + &pci_dev_info_8086_24d4, + &pci_dev_info_8086_24d5, + &pci_dev_info_8086_24d6, + &pci_dev_info_8086_24d7, + &pci_dev_info_8086_24db, + &pci_dev_info_8086_24dc, + &pci_dev_info_8086_24dd, + &pci_dev_info_8086_24de, + &pci_dev_info_8086_24df, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_254c, + &pci_dev_info_8086_2550, + &pci_dev_info_8086_2551, + &pci_dev_info_8086_2552, + &pci_dev_info_8086_2553, + &pci_dev_info_8086_2554, + &pci_dev_info_8086_255d, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2571, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_2573, + &pci_dev_info_8086_2576, + &pci_dev_info_8086_2578, + &pci_dev_info_8086_2579, + &pci_dev_info_8086_257b, + &pci_dev_info_8086_257e, + &pci_dev_info_8086_2580, + &pci_dev_info_8086_2581, + &pci_dev_info_8086_2582, + &pci_dev_info_8086_2584, + &pci_dev_info_8086_2585, + &pci_dev_info_8086_2588, + &pci_dev_info_8086_2589, + &pci_dev_info_8086_258a, + &pci_dev_info_8086_2590, + &pci_dev_info_8086_2591, + &pci_dev_info_8086_2592, + &pci_dev_info_8086_25a1, + &pci_dev_info_8086_25a2, + &pci_dev_info_8086_25a3, + &pci_dev_info_8086_25a4, + &pci_dev_info_8086_25a6, + &pci_dev_info_8086_25a7, + &pci_dev_info_8086_25a9, + &pci_dev_info_8086_25aa, + &pci_dev_info_8086_25ab, + &pci_dev_info_8086_25ac, + &pci_dev_info_8086_25ad, + &pci_dev_info_8086_25ae, + &pci_dev_info_8086_25b0, + &pci_dev_info_8086_25c0, + &pci_dev_info_8086_25d0, + &pci_dev_info_8086_25d4, + &pci_dev_info_8086_25d8, + &pci_dev_info_8086_25e2, + &pci_dev_info_8086_25e3, + &pci_dev_info_8086_25e4, + &pci_dev_info_8086_25e5, + &pci_dev_info_8086_25e6, + &pci_dev_info_8086_25e7, + &pci_dev_info_8086_25e8, + &pci_dev_info_8086_25f0, + &pci_dev_info_8086_25f1, + &pci_dev_info_8086_25f3, + &pci_dev_info_8086_25f5, + &pci_dev_info_8086_25f6, + &pci_dev_info_8086_25f7, + &pci_dev_info_8086_25f8, + &pci_dev_info_8086_25f9, + &pci_dev_info_8086_25fa, + &pci_dev_info_8086_2600, + &pci_dev_info_8086_2601, + &pci_dev_info_8086_2602, + &pci_dev_info_8086_2603, + &pci_dev_info_8086_2604, + &pci_dev_info_8086_2605, + &pci_dev_info_8086_2606, + &pci_dev_info_8086_2607, + &pci_dev_info_8086_2608, + &pci_dev_info_8086_2609, + &pci_dev_info_8086_260a, + &pci_dev_info_8086_260c, + &pci_dev_info_8086_2610, + &pci_dev_info_8086_2611, + &pci_dev_info_8086_2612, + &pci_dev_info_8086_2613, + &pci_dev_info_8086_2614, + &pci_dev_info_8086_2615, + &pci_dev_info_8086_2617, + &pci_dev_info_8086_2618, + &pci_dev_info_8086_2619, + &pci_dev_info_8086_261a, + &pci_dev_info_8086_261b, + &pci_dev_info_8086_261c, + &pci_dev_info_8086_261d, + &pci_dev_info_8086_261e, + &pci_dev_info_8086_2620, + &pci_dev_info_8086_2621, + &pci_dev_info_8086_2622, + &pci_dev_info_8086_2623, + &pci_dev_info_8086_2624, + &pci_dev_info_8086_2625, + &pci_dev_info_8086_2626, + &pci_dev_info_8086_2627, + &pci_dev_info_8086_2640, + &pci_dev_info_8086_2641, + &pci_dev_info_8086_2642, + &pci_dev_info_8086_2651, + &pci_dev_info_8086_2652, + &pci_dev_info_8086_2653, + &pci_dev_info_8086_2658, + &pci_dev_info_8086_2659, + &pci_dev_info_8086_265a, + &pci_dev_info_8086_265b, + &pci_dev_info_8086_265c, + &pci_dev_info_8086_2660, + &pci_dev_info_8086_2662, + &pci_dev_info_8086_2664, + &pci_dev_info_8086_2666, + &pci_dev_info_8086_2668, + &pci_dev_info_8086_266a, + &pci_dev_info_8086_266c, + &pci_dev_info_8086_266d, + &pci_dev_info_8086_266e, + &pci_dev_info_8086_266f, + &pci_dev_info_8086_2670, + &pci_dev_info_8086_2680, + &pci_dev_info_8086_2681, + &pci_dev_info_8086_2682, + &pci_dev_info_8086_2683, + &pci_dev_info_8086_2688, + &pci_dev_info_8086_2689, + &pci_dev_info_8086_268a, + &pci_dev_info_8086_268b, + &pci_dev_info_8086_268c, + &pci_dev_info_8086_2690, + &pci_dev_info_8086_2692, + &pci_dev_info_8086_2694, + &pci_dev_info_8086_2696, + &pci_dev_info_8086_2698, + &pci_dev_info_8086_2699, + &pci_dev_info_8086_269a, + &pci_dev_info_8086_269b, + &pci_dev_info_8086_269e, + &pci_dev_info_8086_2770, + &pci_dev_info_8086_2771, + &pci_dev_info_8086_2772, + &pci_dev_info_8086_2774, + &pci_dev_info_8086_2775, + &pci_dev_info_8086_2776, + &pci_dev_info_8086_2778, + &pci_dev_info_8086_2779, + &pci_dev_info_8086_277a, + &pci_dev_info_8086_277c, + &pci_dev_info_8086_277d, + &pci_dev_info_8086_2782, + &pci_dev_info_8086_2792, + &pci_dev_info_8086_27a0, + &pci_dev_info_8086_27a1, + &pci_dev_info_8086_27a2, + &pci_dev_info_8086_27a6, + &pci_dev_info_8086_27b0, + &pci_dev_info_8086_27b8, + &pci_dev_info_8086_27b9, + &pci_dev_info_8086_27bd, + &pci_dev_info_8086_27c0, + &pci_dev_info_8086_27c1, + &pci_dev_info_8086_27c3, + &pci_dev_info_8086_27c4, + &pci_dev_info_8086_27c5, + &pci_dev_info_8086_27c6, + &pci_dev_info_8086_27c8, + &pci_dev_info_8086_27c9, + &pci_dev_info_8086_27ca, + &pci_dev_info_8086_27cb, + &pci_dev_info_8086_27cc, + &pci_dev_info_8086_27d0, + &pci_dev_info_8086_27d2, + &pci_dev_info_8086_27d4, + &pci_dev_info_8086_27d6, + &pci_dev_info_8086_27d8, + &pci_dev_info_8086_27da, + &pci_dev_info_8086_27dc, + &pci_dev_info_8086_27dd, + &pci_dev_info_8086_27de, + &pci_dev_info_8086_27df, + &pci_dev_info_8086_27e0, + &pci_dev_info_8086_27e2, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3200, + &pci_dev_info_8086_3340, + &pci_dev_info_8086_3341, + &pci_dev_info_8086_3500, + &pci_dev_info_8086_3501, + &pci_dev_info_8086_3504, + &pci_dev_info_8086_3505, + &pci_dev_info_8086_350c, + &pci_dev_info_8086_350d, + &pci_dev_info_8086_3510, + &pci_dev_info_8086_3511, + &pci_dev_info_8086_3514, + &pci_dev_info_8086_3515, + &pci_dev_info_8086_3518, + &pci_dev_info_8086_3519, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3581, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_3584, + &pci_dev_info_8086_3585, + &pci_dev_info_8086_3590, + &pci_dev_info_8086_3591, + &pci_dev_info_8086_3592, + &pci_dev_info_8086_3593, + &pci_dev_info_8086_3594, + &pci_dev_info_8086_3595, + &pci_dev_info_8086_3596, + &pci_dev_info_8086_3597, + &pci_dev_info_8086_3598, + &pci_dev_info_8086_3599, + &pci_dev_info_8086_359a, + &pci_dev_info_8086_359b, + &pci_dev_info_8086_359e, + &pci_dev_info_8086_4220, + &pci_dev_info_8086_4223, + &pci_dev_info_8086_4224, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7050, + &pci_dev_info_8086_7051, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_8500, + &pci_dev_info_8086_9000, + &pci_dev_info_8086_9001, + &pci_dev_info_8086_9004, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + NULL +}; +#define pci_dev_list_8401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8912 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8c4a[] = { + &pci_dev_info_8c4a_1980, + NULL +}; +#endif +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_0078, + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7710, + &pci_dev_info_9004_7711, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + &pci_dev_info_9004_8278, + &pci_dev_info_9004_8378, + &pci_dev_info_9004_8478, + &pci_dev_info_9004_8578, + &pci_dev_info_9004_8678, + &pci_dev_info_9004_8778, + &pci_dev_info_9004_8878, + &pci_dev_info_9004_8b78, + &pci_dev_info_9004_ec78, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9005[] = { + &pci_dev_info_9005_0010, + &pci_dev_info_9005_0011, + &pci_dev_info_9005_0013, + &pci_dev_info_9005_001f, + &pci_dev_info_9005_0020, + &pci_dev_info_9005_002f, + &pci_dev_info_9005_0030, + &pci_dev_info_9005_003f, + &pci_dev_info_9005_0050, + &pci_dev_info_9005_0051, + &pci_dev_info_9005_0053, + &pci_dev_info_9005_005f, + &pci_dev_info_9005_0080, + &pci_dev_info_9005_0081, + &pci_dev_info_9005_0083, + &pci_dev_info_9005_008f, + &pci_dev_info_9005_0092, + &pci_dev_info_9005_0093, + &pci_dev_info_9005_00c0, + &pci_dev_info_9005_00c1, + &pci_dev_info_9005_00c3, + &pci_dev_info_9005_00c5, + &pci_dev_info_9005_00cf, + &pci_dev_info_9005_0241, + &pci_dev_info_9005_0250, + &pci_dev_info_9005_0279, + &pci_dev_info_9005_0283, + &pci_dev_info_9005_0284, + &pci_dev_info_9005_0285, + &pci_dev_info_9005_0286, + &pci_dev_info_9005_0500, + &pci_dev_info_9005_0503, + &pci_dev_info_9005_0910, + &pci_dev_info_9005_091e, + &pci_dev_info_9005_8000, + &pci_dev_info_9005_800f, + &pci_dev_info_9005_8010, + &pci_dev_info_9005_8011, + &pci_dev_info_9005_8012, + &pci_dev_info_9005_8013, + &pci_dev_info_9005_8014, + &pci_dev_info_9005_8015, + &pci_dev_info_9005_8016, + &pci_dev_info_9005_8017, + &pci_dev_info_9005_801c, + &pci_dev_info_9005_801d, + &pci_dev_info_9005_801e, + &pci_dev_info_9005_801f, + &pci_dev_info_9005_8080, + &pci_dev_info_9005_808f, + &pci_dev_info_9005_8090, + &pci_dev_info_9005_8091, + &pci_dev_info_9005_8092, + &pci_dev_info_9005_8093, + &pci_dev_info_9005_8094, + &pci_dev_info_9005_8095, + &pci_dev_info_9005_8096, + &pci_dev_info_9005_8097, + &pci_dev_info_9005_809c, + &pci_dev_info_9005_809d, + &pci_dev_info_9005_809e, + &pci_dev_info_9005_809f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_907f[] = { + &pci_dev_info_907f_2015, + NULL +}; +#endif +#define pci_dev_list_919a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9412[] = { + &pci_dev_info_9412_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9699[] = { + &pci_dev_info_9699_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9710[] = { + &pci_dev_info_9710_7780, + &pci_dev_info_9710_9805, + &pci_dev_info_9710_9815, + &pci_dev_info_9710_9835, + &pci_dev_info_9710_9845, + &pci_dev_info_9710_9855, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9902[] = { + &pci_dev_info_9902_0001, + &pci_dev_info_9902_0002, + &pci_dev_info_9902_0003, + NULL +}; +#endif +#define pci_dev_list_a0a0 NULL +#define pci_dev_list_a0f1 NULL +#define pci_dev_list_a200 NULL +#define pci_dev_list_a259 NULL +#define pci_dev_list_a25b NULL +#define pci_dev_list_a304 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_a727[] = { + &pci_dev_info_a727_0013, + NULL +}; +#endif +#define pci_dev_list_aa42 NULL +#define pci_dev_list_ac1e NULL +#define pci_dev_list_ac3d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_aecb[] = { + &pci_dev_info_aecb_6250, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_affe[] = { + &pci_dev_info_affe_dead, + NULL +}; +#endif +#define pci_dev_list_b1b3 NULL +#define pci_dev_list_bd11 NULL +#define pci_dev_list_c001 NULL +#define pci_dev_list_c0a9 NULL +#define pci_dev_list_c0de NULL +#define pci_dev_list_c0fe NULL +#define pci_dev_list_ca50 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cafe[] = { + &pci_dev_info_cafe_0003, + NULL +}; +#endif +#define pci_dev_list_cccc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cddd[] = { + &pci_dev_info_cddd_0101, + &pci_dev_info_cddd_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d161[] = { + &pci_dev_info_d161_0205, + &pci_dev_info_d161_0210, + &pci_dev_info_d161_0405, + &pci_dev_info_d161_0410, + &pci_dev_info_d161_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d4d4[] = { + &pci_dev_info_d4d4_0601, + NULL +}; +#endif +#define pci_dev_list_d531 NULL +#define pci_dev_list_d84d NULL +#define pci_dev_list_dead NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_deaf[] = { + &pci_dev_info_deaf_9050, + &pci_dev_info_deaf_9051, + &pci_dev_info_deaf_9052, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e000[] = { + &pci_dev_info_e000_e000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e159[] = { + &pci_dev_info_e159_0001, + &pci_dev_info_e159_0002, + NULL +}; +#endif +#define pci_dev_list_e4bf NULL +#define pci_dev_list_e55e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea01[] = { + &pci_dev_info_ea01_000a, + &pci_dev_info_ea01_0032, + &pci_dev_info_ea01_003e, + &pci_dev_info_ea01_0041, + &pci_dev_info_ea01_0043, + &pci_dev_info_ea01_0046, + &pci_dev_info_ea01_0052, + &pci_dev_info_ea01_0800, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea60[] = { + &pci_dev_info_ea60_9896, + &pci_dev_info_ea60_9897, + &pci_dev_info_ea60_9898, + NULL +}; +#endif +#define pci_dev_list_eabb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_eace[] = { + &pci_dev_info_eace_3100, + &pci_dev_info_eace_3200, + &pci_dev_info_eace_320e, + &pci_dev_info_eace_340e, + &pci_dev_info_eace_341e, + &pci_dev_info_eace_3500, + &pci_dev_info_eace_351c, + &pci_dev_info_eace_4100, + &pci_dev_info_eace_4110, + &pci_dev_info_eace_4220, + &pci_dev_info_eace_422e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ec80[] = { + &pci_dev_info_ec80_ec00, + NULL +}; +#endif +#define pci_dev_list_ecc0 NULL +static const pciDeviceInfo *pci_dev_list_edd8[] = { + &pci_dev_info_edd8_a091, + &pci_dev_info_edd8_a099, + &pci_dev_info_edd8_a0a1, + &pci_dev_info_edd8_a0a9, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_f1d0[] = { + &pci_dev_info_f1d0_c0fe, + &pci_dev_info_f1d0_c0ff, + &pci_dev_info_f1d0_cafe, + &pci_dev_info_f1d0_cfee, + &pci_dev_info_f1d0_dcaf, + &pci_dev_info_f1d0_dfee, + &pci_dev_info_f1d0_efac, + &pci_dev_info_f1d0_facd, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fa57[] = { + &pci_dev_info_fa57_0001, + NULL +}; +#endif +#define pci_dev_list_febd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_feda[] = { + &pci_dev_info_feda_a0fa, + &pci_dev_info_feda_a10e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fede[] = { + &pci_dev_info_fede_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffd[] = { + &pci_dev_info_fffd_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffe[] = { + &pci_dev_info_fffe_0405, + &pci_dev_info_fffe_0710, + NULL +}; +#endif +#define pci_dev_list_ffff NULL + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_dev_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_dev_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_dev_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_dev_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_dev_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_dev_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_dev_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_dev_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_dev_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_dev_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_dev_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_dev_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_dev_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_dev_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_dev_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_dev_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_dev_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_dev_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_dev_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_dev_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_dev_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_dev_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_dev_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_dev_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_dev_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_dev_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_dev_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_dev_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_dev_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_dev_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_dev_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_dev_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_dev_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_dev_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_dev_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_dev_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_dev_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_dev_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_dev_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_dev_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_dev_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_dev_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_dev_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_dev_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_dev_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_dev_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_dev_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_dev_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_dev_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_dev_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_dev_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_dev_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_dev_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_dev_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_dev_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_dev_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_dev_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_dev_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_dev_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_dev_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_dev_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_dev_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_dev_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_dev_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_dev_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_dev_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_dev_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_dev_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_dev_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_dev_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_dev_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_dev_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_dev_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_dev_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_dev_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_dev_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_dev_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_dev_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_dev_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_dev_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_dev_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_dev_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_dev_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_dev_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_dev_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_dev_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_dev_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_dev_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_dev_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_dev_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_dev_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_dev_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_dev_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_dev_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_dev_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_dev_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_dev_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_dev_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_dev_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_dev_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_dev_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_dev_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_dev_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_dev_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_dev_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_dev_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_dev_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_dev_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_dev_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_dev_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_dev_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_dev_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_dev_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_dev_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_dev_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_dev_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_dev_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_dev_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_dev_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_dev_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_dev_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_dev_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_dev_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_dev_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_dev_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_dev_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_dev_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_dev_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_dev_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_dev_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_dev_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_dev_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_dev_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_dev_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_dev_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_dev_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_dev_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_dev_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_dev_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_dev_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_dev_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_dev_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_dev_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_dev_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_dev_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_dev_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_dev_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_dev_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_dev_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_dev_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_dev_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_dev_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_dev_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_dev_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_dev_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_dev_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_dev_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_dev_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_dev_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_dev_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_dev_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_dev_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_dev_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_dev_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_dev_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_dev_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_dev_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_dev_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_dev_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_dev_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_dev_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_dev_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_dev_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_ss_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_ss_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_ss_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_ss_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_ss_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_ss_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_ss_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_ss_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_ss_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_ss_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_ss_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_ss_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_ss_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_ss_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_ss_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_ss_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_ss_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_ss_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_ss_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_ss_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_ss_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_ss_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_ss_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_ss_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_ss_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_ss_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_ss_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_ss_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_ss_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_ss_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_ss_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_ss_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_ss_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_ss_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_ss_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_ss_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_ss_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_ss_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_ss_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_ss_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_ss_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_ss_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_ss_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_ss_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_ss_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_ss_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_ss_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_ss_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_ss_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_ss_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_ss_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_ss_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_ss_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_ss_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_ss_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_ss_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_ss_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_ss_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_ss_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_ss_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_ss_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_ss_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_ss_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_ss_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_ss_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_ss_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_ss_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_ss_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_ss_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_ss_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_ss_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_ss_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_ss_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_ss_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_ss_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_ss_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_ss_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_ss_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_ss_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_ss_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_ss_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_ss_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_ss_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_ss_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_ss_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_ss_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_ss_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_ss_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_ss_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_ss_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_ss_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_ss_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_ss_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_ss_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_ss_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_ss_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_ss_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_ss_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_ss_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_ss_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_ss_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_ss_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_ss_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_ss_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_ss_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_ss_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_ss_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_ss_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_ss_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_ss_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_ss_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_ss_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_ss_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_ss_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_ss_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_ss_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_ss_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_ss_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_ss_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_ss_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_ss_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_ss_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_ss_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_ss_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_ss_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_ss_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_ss_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_ss_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_ss_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_ss_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_ss_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_ss_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_ss_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_ss_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_ss_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_ss_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_ss_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_ss_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_ss_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_ss_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_ss_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_ss_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_ss_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_ss_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_ss_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_ss_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_ss_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_ss_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_ss_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_ss_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_ss_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_ss_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_ss_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_ss_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_ss_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_ss_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_ss_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_ss_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_ss_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_ss_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_ss_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_ss_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_ss_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_ss_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_ss_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_ss_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_ss_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_ss_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_ss_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_ss_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_ss_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_ss_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_ss_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86PciStr.h (revision 51223) @@ -0,0 +1,67 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86PciStr.h,v 1.2 2003/08/24 17:37:10 dawes Exp $ */ +/* + * Copyright (c) 2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * Structs used to hold the pre-parsed pci.ids data. These are private + * to the scanpci and pcidata modules. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_PCISTR_H +#define _XF86_PCISTR_H + +typedef struct { + unsigned short VendorID; + unsigned short SubsystemID; + const char *SubsystemName; + unsigned short class; +} pciSubsystemInfo; + +typedef struct { + unsigned short DeviceID; + const char *DeviceName; + const pciSubsystemInfo **Subsystem; + unsigned short class; +} pciDeviceInfo; + +typedef struct { + unsigned short VendorID; + const char *VendorName; + const pciDeviceInfo **Device; +} pciVendorInfo; + +typedef struct { + unsigned short VendorID; + const char *VendorName; + const pciSubsystemInfo **Subsystem; +} pciVendorSubsysInfo; + +#endif /* _XF86_PCISTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Priv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Priv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Priv.h (revision 51223) @@ -0,0 +1,228 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Priv.h,v 3.83 2004/01/27 01:31:45 dawes Exp $ */ + +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains declarations for private XFree86 functions and variables, + * and definitions of private macros. + * + * "private" means not available to video drivers. + */ + +#ifndef _XF86PRIV_H +#define _XF86PRIV_H + +#include "xf86Privstr.h" +#include "propertyst.h" + +/* + * Parameters set ONLY from the command line options + * The global state of these things is held in xf86InfoRec (when appropriate). + */ +extern const char *xf86ConfigFile; +extern Bool xf86AllowMouseOpenFail; +#ifdef XF86VIDMODE +extern Bool xf86VidModeDisabled; +extern Bool xf86VidModeAllowNonLocal; +#endif +#ifdef XF86MISC +extern Bool xf86MiscModInDevDisabled; +extern Bool xf86MiscModInDevAllowNonLocal; +#endif +extern Bool xf86fpFlag; +extern Bool xf86coFlag; +extern Bool xf86sFlag; +extern Bool xf86bsEnableFlag; +extern Bool xf86bsDisableFlag; +extern Bool xf86silkenMouseDisableFlag; +extern Bool xf86acpiDisableFlag; +extern char *xf86LayoutName; +extern char *xf86ScreenName; +extern char *xf86PointerName; +extern char *xf86KeyboardName; +#ifdef KEEPBPP +extern int xf86Bpp; +#endif +extern int xf86FbBpp; +extern int xf86Depth; +extern Pix24Flags xf86Pix24; +extern rgb xf86Weight; +extern Bool xf86FlipPixels; +extern Bool xf86BestRefresh; +extern Gamma xf86Gamma; +extern char *xf86ServerName; +extern Bool xf86ShowUnresolved; +extern PciBusId xf86IsolateDevice; + +/* Other parameters */ + +extern xf86InfoRec xf86Info; +extern const char *xf86InputDeviceList; +extern const char *xf86ModulePath; +extern MessageType xf86ModPathFrom; +extern const char *xf86LogFile; +extern MessageType xf86LogFileFrom; +extern Bool xf86LogFileWasOpened; +extern serverLayoutRec xf86ConfigLayout; +extern Pix24Flags xf86ConfigPix24; + +extern unsigned short xf86MouseCflags[]; +extern Bool xf86SupportedMouseTypes[]; +extern int xf86NumMouseTypes; + +#ifdef XFree86LOADER +extern DriverPtr *xf86DriverList; +extern ModuleInfoPtr *xf86ModuleInfoList; +extern int xf86NumModuleInfos; +#else +extern DriverPtr xf86DriverList[]; +#endif +extern int xf86NumDrivers; +extern Bool xf86Resetting; +extern Bool xf86Initialising; +extern Bool xf86ProbeFailed; +extern int xf86NumScreens; +extern pciVideoPtr *xf86PciVideoInfo; +extern xf86CurrentAccessRec xf86CurrentAccess; +extern const char *xf86VisualNames[]; +extern int xf86Verbose; /* verbosity level */ +extern int xf86LogVerbose; /* log file verbosity level */ +extern Bool xf86ProbeOnly; +extern Bool xf86DoProbe; +extern Bool xorgHWAccess; + +extern RootWinPropPtr *xf86RegisteredPropertiesTable; + +#ifndef DEFAULT_VERBOSE +#define DEFAULT_VERBOSE 0 +#endif +#ifndef DEFAULT_LOG_VERBOSE +#define DEFAULT_LOG_VERBOSE 3 +#endif +#ifndef DEFAULT_DPI +#define DEFAULT_DPI 75 +#endif + +#define DEFAULT_UNRESOLVED TRUE +#define DEFAULT_BEST_REFRESH FALSE + +/* Function Prototypes */ +#ifndef _NO_XF86_PROTOTYPES + +/* xf86Bus.c */ + +void xf86BusProbe(void); +void xf86ChangeBusIndex(int oldIndex, int newIndex); +void xf86AccessInit(void); +void xf86AccessEnter(void); +void xf86AccessLeave(void); +void xf86EntityInit(void); +void xf86EntityEnter(void); +void xf86EntityLeave(void); +void xf86AccessLeaveState(void); + +void xf86FindPrimaryDevice(void); +/* new RAC */ +void xf86ResourceBrokerInit(void); +void xf86PostProbe(void); +void xf86ClearEntityListForScreen(int scrnIndex); +void xf86AddDevToEntity(int entityIndex, GDevPtr dev); +extern void xf86PostPreInit(void); +extern void xf86PostScreenInit(void); +extern memType getValidBIOSBase(PCITAG tag, int num); +extern int pciTestMultiDeviceCard(int bus, int dev, int func, PCITAG** pTag); + +/* xf86Config.c */ + +Bool xf86PathIsAbsolute(const char *path); +Bool xf86PathIsSafe(const char *path); + +/* xf86DefaultModes */ + +extern DisplayModeRec xf86DefaultModes []; + +/* xf86DoScanPci.c */ + +void DoScanPci(int argc, char **argv, int i); + +/* xf86DoProbe.c */ +void DoProbeArgs(int argc, char **argv, int i); +void DoProbe(void); +void DoConfigure(void); + +/* xf86Events.c */ + +void xf86PostKbdEvent(unsigned key); +void xf86PostMseEvent(DeviceIntPtr device, int buttons, int dx, int dy); +void xf86Wakeup(pointer blockData, int err, pointer pReadmask); +void xf86SigHandler(int signo); +#ifdef MEMDEBUG +void xf86SigMemDebug(int signo); +#endif +void xf86HandlePMEvents(int fd, pointer data); +extern int (*xf86PMGetEventFromOs)(int fd,pmEvent *events,int num); +extern pmWait (*xf86PMConfirmEventToOs)(int fd,pmEvent event); +void xf86GrabServerCallback(CallbackListPtr *, pointer, pointer); + +/* xf86Helper.c */ +void xf86LogInit(void); +void xf86CloseLog(void); + +/* xf86Init.c */ +Bool xf86LoadModules(char **list, pointer *optlist); +int xf86SetVerbosity(int verb); +int xf86SetLogVerbosity(int verb); + +/* xf86Io.c */ + +void xf86KbdBell(int percent, DeviceIntPtr pKeyboard, pointer ctrl, + int unused); +void xf86KbdLeds(void); +void xf86UpdateKbdLeds(void); +void xf86KbdCtrl(DevicePtr pKeyboard, KeybdCtrl *ctrl); +void xf86InitKBD(Bool init); +int xf86KbdProc(DeviceIntPtr pKeyboard, int what); + +/* xf86Kbd.c */ + +void xf86KbdGetMapping(KeySymsPtr pKeySyms, CARD8 *pModMap); + +/* xf86Lock.c */ + +#ifdef USE_XF86_SERVERLOCK +void xf86UnlockServer(void); +#endif + +/* xf86XKB.c */ + +void xf86InitXkb(void); + +#endif /* _NO_XF86_PROTOTYPES */ + + +#endif /* _XF86PRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Privstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Privstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Privstr.h (revision 51223) @@ -0,0 +1,234 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Privstr.h,v 1.41 2004/01/27 01:31:45 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the private XFree86 data structures/types. + * None of the data structures here should be used by video drivers. + */ + +#ifndef _XF86PRIVSTR_H +#define _XF86PRIVSTR_H + +#include "xf86Pci.h" +#include "xf86str.h" + +/* PCI probe flags */ + +typedef enum { + PCIProbe1 = 0, + PCIProbe2, + PCIForceConfig1, + PCIForceConfig2, + PCIForceNone, + PCIOsConfig +} PciProbeType; + +typedef enum { + LogNone, + LogFlush, + LogSync +} Log; + +typedef enum { + SKNever, + SKWhenNeeded, + SKAlways +} SpecialKeysInDDX; + +/* + * xf86InfoRec contains global parameters which the video drivers never + * need to access. Global parameters which the video drivers do need + * should be individual globals. + */ + +typedef struct { + + /* keyboard part */ + DeviceIntPtr pKeyboard; + DeviceProc kbdProc; /* procedure for initializing */ + void (* kbdEvents)(void); /* proc for processing events */ + int consoleFd; + int kbdFd; + int vtno; + int kbdType; /* AT84 / AT101 */ + int kbdRate; + int kbdDelay; + int bell_pitch; + int bell_duration; + Bool autoRepeat; + unsigned long leds; + unsigned long xleds; + char * vtinit; + int scanPrefix; /* scancode-state */ + Bool capsLock; + Bool numLock; + Bool scrollLock; + Bool modeSwitchLock; + Bool composeLock; + Bool vtSysreq; + SpecialKeysInDDX ddxSpecialKeys; + Bool ActionKeyBindingsSet; +#if defined(SVR4) && defined(i386) + Bool panix106; +#endif /* SVR4 && i386 */ +#if defined(__OpenBSD__) || defined(__NetBSD__) + int wsKbdType; +#endif + + /* mouse part */ + DeviceIntPtr pMouse; +#ifdef XINPUT + pointer mouseLocal; +#endif + + /* event handler part */ + int lastEventTime; + Bool vtRequestsPending; + Bool inputPending; + Bool dontVTSwitch; + Bool dontZap; + Bool dontZoom; + Bool notrapSignals; /* don't exit cleanly - die at fault */ + Bool caughtSignal; + + /* graphics part */ + Bool sharedMonitor; + ScreenPtr currentScreen; +#if defined(CSRG_BASED) || defined(__FreeBSD_kernel__) + int screenFd; /* fd for memory mapped access to + * vga card */ + int consType; /* Which console driver? */ +#endif + +#ifdef XKB + /* + * would like to use an XkbComponentNamesRec here but can't without + * pulling in a bunch of header files. :-( + */ + char * xkbkeymap; + char * xkbkeycodes; + char * xkbtypes; + char * xkbcompat; + char * xkbsymbols; + char * xkbgeometry; + Bool xkbcomponents_specified; + char * xkbrules; + char * xkbmodel; + char * xkblayout; + char * xkbvariant; + char * xkboptions; +#endif + + /* Other things */ + Bool allowMouseOpenFail; + Bool vidModeEnabled; /* VidMode extension enabled */ + Bool vidModeAllowNonLocal; /* allow non-local VidMode + * connections */ + Bool miscModInDevEnabled; /* Allow input devices to be + * changed */ + Bool miscModInDevAllowNonLocal; + PciProbeType pciFlags; + Pix24Flags pixmap24; + MessageType pix24From; +#if defined(i386) || defined(__i386__) + Bool pc98; +#endif + Bool pmFlag; + Log log; + int estimateSizesAggressively; + Bool kbdCustomKeycodes; + Bool disableRandR; + MessageType randRFrom; + struct { + Bool disabled; /* enable/disable deactivating + * grabs or closing the + * connection to the grabbing + * client */ + ClientPtr override; /* client that disabled + * grab deactivation. + */ + Bool allowDeactivate; + Bool allowClosedown; + ServerGrabInfoRec server; + } grabInfo; +} xf86InfoRec, *xf86InfoPtr; + +#ifdef DPMSExtension +/* Private info for DPMS */ +typedef struct { + CloseScreenProcPtr CloseScreen; + Bool Enabled; + int Flags; +} DPMSRec, *DPMSPtr; +#endif + +#ifdef XF86VIDMODE +/* Private info for Video Mode Extentsion */ +typedef struct { + DisplayModePtr First; + DisplayModePtr Next; + int Flags; + CloseScreenProcPtr CloseScreen; +} VidModeRec, *VidModePtr; +#endif + +/* Information for root window properties. */ +typedef struct _RootWinProp { + struct _RootWinProp * next; + char * name; + Atom type; + short format; + long size; + pointer data; +} RootWinProp, *RootWinPropPtr; + +/* private resource types */ +#define ResNoAvoid ResBios + +/* ISC's cc can't handle ~ of UL constants, so explicitly type cast them. */ +#define XLED1 ((unsigned long) 0x00000001) +#define XLED2 ((unsigned long) 0x00000002) +#define XLED3 ((unsigned long) 0x00000004) +#define XLED4 ((unsigned long) 0x00000008) +#define XCAPS ((unsigned long) 0x20000000) +#define XNUM ((unsigned long) 0x40000000) +#define XSCR ((unsigned long) 0x80000000) +#define XCOMP ((unsigned long) 0x00008000) + +/* BSD console driver types (consType) */ +#if defined(CSRG_BASED) || defined(__FreeBSD_kernel__) +#define PCCONS 0 +#define CODRV011 1 +#define CODRV01X 2 +#define SYSCONS 8 +#define PCVT 16 +#define WSCONS 32 +#endif + +#endif /* _XF86PRIVSTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RAC.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RAC.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RAC.h (revision 51223) @@ -0,0 +1,18 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/rac/xf86RAC.h,v 1.2 1999/05/15 12:10:33 dawes Exp $ */ + +#ifndef __XF86RAC_H +#define __XF86RAC_H 1 + +#include "screenint.h" +#include "misc.h" +#include "xf86.h" + +Bool xf86RACInit(ScreenPtr pScreen, unsigned int flag); + +/* flags */ +#define RAC_FB 0x01 +#define RAC_CURSOR 0x02 +#define RAC_COLORMAP 0x04 +#define RAC_VIEWPORT 0x08 + +#endif /* __XF86RAC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDac.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDac.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDac.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86RamDac.h,v 1.9 1999/03/28 15:33:02 dawes Exp $ */ + +#ifndef _XF86RAMDAC_H +#define _XF86RAMDAC_H 1 + +#include "colormapst.h" +#include "xf86Cursor.h" + +/* Define unique vendor codes for RAMDAC's */ +#define VENDOR_IBM 0x0000 +#define VENDOR_BT 0x0001 +#define VENDOR_TI 0x0002 + +typedef struct _RamDacRegRec { +/* This is probably the nastiest assumption, we allocate 1024 slots for + * ramdac registers, should be enough. I've checked IBM and TVP series + * and they seem o.k + * Then we allocate 768 entries for the DAC too. IBM640 needs 1024 -FIXME + */ + unsigned short DacRegs[0x400]; /* register set */ + unsigned char DAC[0x300]; /* colour map */ + Bool Overlay; +} RamDacRegRec, *RamDacRegRecPtr; + +typedef struct _RamDacHWRegRec { + RamDacRegRec SavedReg; + RamDacRegRec ModeReg; +} RamDacHWRec, *RamDacHWRecPtr; + +typedef struct _RamDacRec { + CARD32 RamDacType; + + void (*LoadPalette)( + ScrnInfoPtr pScrn, + int numColors, + int *indices, + LOCO *colors, + VisualPtr pVisual + ); + + unsigned char (*ReadDAC)( + ScrnInfoPtr pScrn, + CARD32 + ); + + void (*WriteDAC)( + ScrnInfoPtr pScrn, + CARD32, + unsigned char, + unsigned char + ); + + void (*WriteAddress)( + ScrnInfoPtr pScrn, + CARD32 + ); + + void (*WriteData)( + ScrnInfoPtr pScrn, + unsigned char + ); + + void (*ReadAddress)( + ScrnInfoPtr pScrn, + CARD32 + ); + + unsigned char (*ReadData)( + ScrnInfoPtr pScrn + ); +} RamDacRec, *RamDacRecPtr; + +typedef struct _RamDacHelperRec { + CARD32 RamDacType; + + void (*Restore)( + ScrnInfoPtr pScrn, + RamDacRecPtr ramdacPtr, + RamDacRegRecPtr ramdacReg + ); + + void (*Save)( + ScrnInfoPtr pScrn, + RamDacRecPtr ramdacPtr, + RamDacRegRecPtr ramdacReg + ); + + void (*SetBpp)( + ScrnInfoPtr pScrn, + RamDacRegRecPtr ramdacReg + ); + + void (*HWCursorInit)( + xf86CursorInfoPtr infoPtr + ); +} RamDacHelperRec, *RamDacHelperRecPtr; + +#define RAMDACHWPTR(p) ((RamDacHWRecPtr)((p)->privates[RamDacGetHWIndex()].ptr)) + +typedef struct _RamdacScreenRec { + RamDacRecPtr RamDacRec; +} RamDacScreenRec, *RamDacScreenRecPtr; +#define RAMDACSCRPTR(p) ((RamDacScreenRecPtr)((p)->privates[RamDacGetScreenIndex()].ptr))->RamDacRec + +extern int RamDacHWPrivateIndex; +extern int RamDacScreenPrivateIndex; + +typedef struct { + int token; +} RamDacSupportedInfoRec, *RamDacSupportedInfoRecPtr; + +RamDacRecPtr RamDacCreateInfoRec(void); +RamDacHelperRecPtr RamDacHelperCreateInfoRec(void); +void RamDacDestroyInfoRec(RamDacRecPtr RamDacRec); +void RamDacHelperDestroyInfoRec(RamDacHelperRecPtr RamDacRec); +Bool RamDacInit(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec); +void RamDacSetGamma(ScrnInfoPtr pScrn, Bool Real8BitDac); +void RamDacRestoreDACValues(ScrnInfoPtr pScrn); +Bool RamDacHandleColormaps(ScreenPtr pScreen, int maxColors, int sigRGBbits, + unsigned int flags); +void RamDacFreeRec(ScrnInfoPtr pScrn); +int RamDacGetHWIndex(void); + +#endif /* _XF86RAMDAC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDacPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDacPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86RamDacPriv.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86RamDacPriv.h,v 1.3 1998/12/06 06:08:37 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "xf86RamDac.h" +#include "xf86cmap.h" + +void RamDacGetRecPrivate(void); +Bool RamDacGetRec(ScrnInfoPtr pScrn); +int RamDacGetScreenIndex(void); +void RamDacLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Resources.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Resources.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Resources.h (revision 51223) @@ -0,0 +1,140 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Resources.h,v 1.15 2003/08/24 17:36:55 dawes Exp $ */ + +/* + * Copyright (c) 1999-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86_RESOURCES_H + +#define _XF86_RESOURCES_H + +#include "xf86str.h" + +#define _END {ResEnd,0,0} + +#define _VGA_EXCLUSIVE \ + {ResExcMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResExcIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +#define _VGA_SHARED \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +#define _VGA_SHARED_MEM \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF} + +#define _VGA_SHARED_IO \ + {ResShrIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Exclusive unused VGA: resources unneeded but cannot be disabled. + * Like old Millennium. + */ +#define _VGA_EXCLUSIVE_UNUSED \ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcUusdIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResExcUusdIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Shared unused VGA: resources unneeded but cannot be disabled + * independently. This is used to determine if a device needs RAC. + */ +#define _VGA_SHARED_UNUSED \ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrUusdIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrUusdIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Sparse versions of the above for those adapters that respond to all ISA + * aliases of VGA ports. + */ +#define _VGA_EXCLUSIVE_SPARSE \ + {ResExcMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcIoSparse | ResBios | ResBus, 0x03B0, 0x03F8},\ + {ResExcIoSparse | ResBios | ResBus, 0x03B8, 0x03FC},\ + {ResExcIoSparse | ResBios | ResBus, 0x03C0, 0x03E0} + +#define _VGA_SHARED_SPARSE \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrIoSparse | ResBios | ResBus, 0x03B0, 0x03F8},\ + {ResShrIoSparse | ResBios | ResBus, 0x03B8, 0x03FC},\ + {ResShrIoSparse | ResBios | ResBus, 0x03C0, 0x03E0} + +#define _8514_EXCLUSIVE \ + {ResExcIoSparse | ResBios | ResBus, 0x02E8, 0x03F8} + +#define _8514_SHARED \ + {ResShrIoSparse | ResBios | ResBus, 0x02E8, 0x03F8} + +/* Predefined resources */ +extern resRange resVgaExclusive[]; +extern resRange resVgaShared[]; +extern resRange resVgaIoShared[]; +extern resRange resVgaMemShared[]; +extern resRange resVgaUnusedExclusive[]; +extern resRange resVgaUnusedShared[]; +extern resRange resVgaSparseExclusive[]; +extern resRange resVgaSparseShared[]; +extern resRange res8514Exclusive[]; +extern resRange res8514Shared[]; + +/* Less misleading aliases for xf86SetOperatingState() */ +#define resVgaMem resVgaMemShared +#define resVgaIo resVgaIoShared +#define resVga resVgaShared + +/* Old style names */ +#define RES_EXCLUSIVE_VGA resVgaExclusive +#define RES_SHARED_VGA resVgaShared +#define RES_EXCLUSIVE_8514 res8514Exclusive +#define RES_SHARED_8514 res8514Shared + +#define _PCI_AVOID_PC_STYLE \ + {ResExcIoSparse | ResBus, 0x0100, 0x0300},\ + {ResExcIoSparse | ResBus, 0x0200, 0x0200},\ + {ResExcMemBlock | ResBus, 0xA0000,0xFFFFF} + +extern resRange PciAvoid[]; + +#define RES_UNDEFINED NULL +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86ScanPci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86ScanPci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86ScanPci.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86ScanPci.h,v 1.3 2003/08/24 17:37:10 dawes Exp $ */ +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef SCANPCI_H_ +#define SCANPCI_H_ + +#include "xf86PciData.h" + +typedef void (*ScanPciDisplayCardInfoProcPtr)(int verbosity); + +/* + * Whoever loads this module needs to define these and initialise them + * after loading. + */ + +extern ScanPciDisplayCardInfoProcPtr xf86DisplayPCICardInfo; + +void ScanPciDisplayPCICardInfo(int verbosity); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Version.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Version.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Version.h (revision 51223) @@ -0,0 +1,62 @@ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 1.2 2004/04/23 19:20:02 eich Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.566 2003/12/19 04:52:11 dawes Exp $ */ + +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef XF86_VERSION_CURRENT + +#define XF86_VERSION_MAJOR 4 +#define XF86_VERSION_MINOR 3 +#define XF86_VERSION_PATCH 99 +#define XF86_VERSION_SNAP 902 + +/* This has five arguments for compatibilty reasons */ +#define XF86_VERSION_NUMERIC(major,minor,patch,snap,dummy) \ + (((major) * 10000000) + ((minor) * 100000) + ((patch) * 1000) + snap) + +#define XF86_GET_MAJOR_VERSION(vers) ((vers) / 10000000) +#define XF86_GET_MINOR_VERSION(vers) (((vers) % 10000000) / 100000) +#define XF86_GET_PATCH_VERSION(vers) (((vers) % 100000) / 1000) +#define XF86_GET_SNAP_VERSION(vers) ((vers) % 1000) + +/* Define these for compatibility. They'll be removed at some point. */ +#define XF86_VERSION_SUBMINOR XF86_VERSION_PATCH +#define XF86_VERSION_BETA 0 +#define XF86_VERSION_ALPHA XF86_VERSION_SNAP + +#define XF86_VERSION_CURRENT \ + XF86_VERSION_NUMERIC(XF86_VERSION_MAJOR, \ + XF86_VERSION_MINOR, \ + XF86_VERSION_PATCH, \ + XF86_VERSION_SNAP, \ + 0) + +#endif + +/* $XConsortium: xf86Version.h /main/78 1996/10/28 05:42:10 kaleb $ */ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 1.2 2004/04/23 19:20:02 eich Exp $ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Xinput.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Xinput.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86Xinput.h (revision 51223) @@ -0,0 +1,220 @@ +/* $XConsortium: xf86Xinput.h /main/11 1996/10/27 11:05:29 kaleb $ */ +/* + * Copyright 1995-1999 by Frederic Lepied, France. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Frederic Lepied not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Frederic Lepied makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * FREDERIC LEPIED DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL FREDERIC LEPIED BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Xinput.h,v 3.36 2003/08/24 17:36:55 dawes Exp $ */ + +#ifndef _xf86Xinput_h +#define _xf86Xinput_h + +#ifndef NEED_EVENTS +#define NEED_EVENTS +#endif +#include "xf86str.h" +#include "inputstr.h" +#ifdef XINPUT +#include +#include +#include "XIstubs.h" +#endif + +/* Input device flags */ +#define XI86_OPEN_ON_INIT 0x01 /* open the device at startup time */ +#define XI86_CONFIGURED 0x02 /* the device has been configured */ +#define XI86_ALWAYS_CORE 0x04 /* device always controls the pointer */ +/* the device sends Xinput and core pointer events */ +#define XI86_SEND_CORE_EVENTS XI86_ALWAYS_CORE +/* if the device is the core pointer or is sending core events, and + * SEND_DRAG_EVENTS is false, and a buttons is done, then no motion events + * (mouse drag action) are sent. This is mainly to allow a touch screen to be + * used with netscape and other browsers which do strange things if the mouse + * moves between button down and button up. With a touch screen, this motion + * is common due to the user's finger moving slightly. + */ +#define XI86_SEND_DRAG_EVENTS 0x08 +#define XI86_CORE_POINTER 0x10 /* device is the core pointer */ +#define XI86_CORE_KEYBOARD 0x20 /* device is the core keyboard */ +#define XI86_POINTER_CAPABLE 0x40 /* capable of being a core pointer */ +#define XI86_KEYBOARD_CAPABLE 0x80 /* capable of being a core keyboard */ + +#define XI_PRIVATE(dev) \ + (((LocalDevicePtr)((dev)->public.devicePrivate))->private) + +#ifdef DBG +#undef DBG +#endif +#define DBG(lvl, f) {if ((lvl) <= xf86GetVerbosity()) f;} + +#ifdef HAS_MOTION_HISTORY +#undef HAS_MOTION_HISTORY +#endif +#define HAS_MOTION_HISTORY(local) ((local)->dev->valuator && (local)->dev->valuator->numMotionEvents) + +#ifdef XINPUT +/* This holds the input driver entry and module information. */ +typedef struct _InputDriverRec { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + struct _LocalDeviceRec *(*PreInit)(struct _InputDriverRec *drv, + IDevPtr dev, int flags); + void (*UnInit)(struct _InputDriverRec *drv, + struct _LocalDeviceRec *pInfo, + int flags); + pointer module; + int refCount; +} InputDriverRec, *InputDriverPtr; +#endif + +/* This is to input devices what the ScrnInfoRec is to screens. */ + +typedef struct _LocalDeviceRec { + struct _LocalDeviceRec *next; + char * name; + int flags; + + Bool (*device_control)(DeviceIntPtr device, int what); + void (*read_input)(struct _LocalDeviceRec *local); + int (*control_proc)(struct _LocalDeviceRec *local, + xDeviceCtl *control); + void (*close_proc)(struct _LocalDeviceRec *local); + int (*switch_mode)(ClientPtr client, DeviceIntPtr dev, + int mode); + Bool (*conversion_proc)(struct _LocalDeviceRec *local, + int first, int num, int v0, + int v1, int v2, int v3, int v4, + int v5, int *x, int *y); + Bool (*reverse_conversion_proc)( + struct _LocalDeviceRec *local, + int x, int y, int *valuators); + + int fd; + Atom atom; + DeviceIntPtr dev; + pointer private; + int private_flags; + pointer motion_history; + ValuatorMotionProcPtr motion_history_proc; + unsigned int history_size; /* only for configuration purpose */ + unsigned int first; + unsigned int last; + int old_x; + int old_y; + float dxremaind; + float dyremaind; + char * type_name; + IntegerFeedbackPtr always_core_feedback; + IDevPtr conf_idev; + InputDriverPtr drv; + pointer module; + pointer options; +} LocalDeviceRec, *LocalDevicePtr, InputInfoRec, *InputInfoPtr; + +typedef struct _DeviceAssocRec +{ + char * config_section_name; + LocalDevicePtr (*device_allocate)(void); +} DeviceAssocRec, *DeviceAssocPtr; + +/* xf86Globals.c */ +extern InputInfoPtr xf86InputDevs; + +/* xf86Xinput.c */ +int xf86IsCorePointer(DeviceIntPtr dev); +int xf86IsCoreKeyboard(DeviceIntPtr dev); +void xf86XInputSetSendCoreEvents(LocalDevicePtr local, Bool always); +#define xf86AlwaysCore(a,b) xf86XInputSetSendCoreEvents(a,b) + +void InitExtInput(void); +Bool xf86eqInit(DevicePtr pKbd, DevicePtr pPtr); +void xf86eqEnqueue(struct _xEvent *event); +void xf86eqProcessInputEvents (void); +void xf86eqSwitchScreen(ScreenPtr pScreen, Bool fromDIX); +void xf86PostMotionEvent(DeviceIntPtr device, int is_absolute, + int first_valuator, int num_valuators, ...); +void xf86PostProximityEvent(DeviceIntPtr device, int is_in, + int first_valuator, int num_valuators, ...); +void xf86PostButtonEvent(DeviceIntPtr device, int is_absolute, int button, + int is_down, int first_valuator, int num_valuators, + ...); +void xf86PostKeyEvent(DeviceIntPtr device, unsigned int key_code, int is_down, + int is_absolute, int first_valuator, int num_valuators, + ...); +void xf86PostKeyboardEvent(DeviceIntPtr device, unsigned int key_code, + int is_down); +void xf86MotionHistoryAllocate(LocalDevicePtr local); +int xf86GetMotionEvents(DeviceIntPtr dev, xTimecoord *buff, + unsigned long start, unsigned long stop, + ScreenPtr pScreen); +void xf86XinputFinalizeInit(DeviceIntPtr dev); +Bool xf86CheckButton(int button, int down); +void xf86SwitchCoreDevice(LocalDevicePtr device, DeviceIntPtr core); +LocalDevicePtr xf86FirstLocalDevice(void); +int xf86ScaleAxis(int Cx, int Sxhigh, int Sxlow, int Rxhigh, int Rxlow); +void xf86XInputSetScreen(LocalDevicePtr local, int screen_number, int x, int y); +void xf86ProcessCommonOptions(InputInfoPtr pInfo, pointer options); +void xf86InitValuatorAxisStruct(DeviceIntPtr dev, int axnum, int minval, + int maxval, int resolution, int min_res, + int max_res); +void xf86InitValuatorDefaults(DeviceIntPtr dev, int axnum); +void xf86AddEnabledDevice(InputInfoPtr pInfo); +void xf86RemoveEnabledDevice(InputInfoPtr pInfo); + +/* xf86Helper.c */ +void xf86AddInputDriver(InputDriverPtr driver, pointer module, int flags); +void xf86DeleteInputDriver(int drvIndex); +InputInfoPtr xf86AllocateInput(InputDriverPtr drv, int flags); +void xf86DeleteInput(InputInfoPtr pInp, int flags); + +/* xf86Option.c */ +void xf86CollectInputOptions(InputInfoPtr pInfo, const char **defaultOpts, + pointer extraOpts); + +#endif /* _xf86Xinput_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSlib.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSlib.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSlib.h (revision 51223) @@ -0,0 +1,759 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h,v 3.94 2003/11/03 05:11:51 tsi Exp $ */ +/* + * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany + * Copyright 1992 by David Dawes + * Copyright 1992 by Jim Tsillas + * Copyright 1992 by Rich Murphey + * Copyright 1992 by Robert Baron + * Copyright 1992 by Orest Zborowski + * Copyright 1993 by Vrije Universiteit, The Netherlands + * Copyright 1993 by David Wexelblat + * Copyright 1994, 1996 by Holger Veit + * Copyright 1997 by Takis Psarogiannakopoulos + * Copyright 1994-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * The ARM32 code here carries the following copyright: + * + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the + * source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" + * name nor any trademark or logo of Digital Equipment Corporation may be + * used to endorse or promote products derived from this software without + * the prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. + * In no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for lost profits, loss + * of revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even + * if advised of the possibility of such damage. + * + */ + +/* $XConsortium: xf86_OSlib.h /main/22 1996/10/27 11:06:31 kaleb $ */ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h,v 1.7 2005/05/21 07:46:37 alanc Exp $ */ + +/* + * This is private, and should not be included by any drivers. Drivers + * may include xf86_OSproc.h to get prototypes for public interfaces. + */ + +#ifndef _XF86_OSLIB_H +#define _XF86_OSLIB_H + +#include +#include + +/* + * Define some things from the "ANSI" C wrappers that are needed in the + * the core server. + */ +#ifndef HAVE_WRAPPER_DECLS +#define HAVE_WRAPPER_DECLS +#undef usleep +#define usleep(a) xf86usleep(a) +extern void xf86usleep(unsigned long); +extern int xf86getpagesize(void); +extern int xf86GetErrno(void); +typedef unsigned long xf86size_t; +typedef signed long xf86ssize_t; +#endif + +#include +#include +#include + +/**************************************************************************/ +/* SYSV386 (SVR3, SVR4), including Solaris */ +/**************************************************************************/ +#if (defined(SYSV) || defined(SVR4)) && \ + !defined(DGUX) && !defined(sgi) && \ + (defined(sun) || defined(i386)) +# ifdef SCO325 +# ifndef _SVID3 +# define _SVID3 +# endif +# ifndef _NO_STATIC +# define _NO_STATIC +# endif +# endif +# include +# include +# include +# include +# include +# if defined(__SCO__) || defined(ISC) +# include +# endif + +# ifdef ISC +# define TIOCMSET (TIOC|26) /* set all modem bits */ +# define TIOCMBIS (TIOC|27) /* bis modem bits */ +# define TIOCMBIC (TIOC|28) /* bic modem bits */ +# define TIOCMGET (TIOC|29) /* get all modem bits */ +# endif + +# include + +# if defined(PowerMAX_OS) +# define HAS_USL_VTS +# include +# include +# elif defined(_NEED_SYSI86) +# include +# if !(defined (sun) && defined (SVR4)) +# include +# endif +# include +# include +# include +# if defined(SVR4) && !defined(sun) +# include +# endif /* SVR4 && !sun */ +/* V86SC_IOPL was moved to on Solaris 7 and later */ +# if defined(sun) && defined (SVR4) /* Solaris? */ +# if defined(i386) || defined(__x86) /* on x86 or x64? */ +# if !defined(V86SC_IOPL) /* Solaris 7 or later? */ +# include /* Nope */ +# endif +# endif /* V86SC_IOPL */ +# else +# include /* Not solaris */ +# endif /* sun && i386 && SVR4 */ +# if defined(sun) && (defined (i386) || defined(__x86)) && defined (SVR4) +# include +# endif +# endif /* _NEED_SYSI86 */ + +# if defined(HAS_SVR3_MMAPDRV) +# include +# if !defined(_NEED_SYSI86) +# include +# include +# endif +# include /* MMAP driver header */ +# endif + +# if !defined(sun) || (!defined(sparc) && !defined(__SOL8__)) +# define HAS_USL_VTS +# endif +# if !defined(sun) +# include +# endif +# if defined(SCO325) +# include +# include +# include +# include +# define LED_CAP CLKED +# define LED_NUM NLKED +# define LED_SCR SLKED +# elif defined(HAS_USL_VTS) +# include +# include +# include +# elif defined(sun) +# include +# include +# include + +/* undefine symbols from we don't need that conflict with enum + definitions in parser/xf86tokens.h */ +# undef STRING +# undef LEFTALT +# undef RIGHTALT + +# define LED_CAP LED_CAPS_LOCK +# define LED_NUM LED_NUM_LOCK +# define LED_SCR LED_SCROLL_LOCK +# define LED_COMP LED_COMPOSE +# endif /* sun */ + +# if !defined(VT_ACKACQ) +# define VT_ACKACQ 2 +# endif /* !VT_ACKACQ */ + +# if defined(__SCO__) +# include +# define POSIX_TTY +# endif /* __SCO__ */ + +# if defined(SVR4) || defined(SCO325) +# include +# if !(defined(sun) && defined (SVR4)) +# define DEV_MEM "/dev/pmem" +# elif defined(PowerMAX_OS) +# define DEV_MEM "/dev/iomem" +# endif +# ifdef SCO325 +# undef DEV_MEM +# define DEV_MEM "/dev/mem" +# endif +# define CLEARDTR_SUPPORT +# define POSIX_TTY +# endif /* SVR4 */ + +# ifdef ISC +# include +# define POSIX_TTY +# endif + +# if defined(sun) && defined (i386) && defined (SVR4) && !defined(__SOL8__) +# define USE_VT_SYSREQ +# define VT_SYSREQ_DEFAULT TRUE +# endif + +# if defined(ATT) && !defined(i386) +# define i386 /* not defined in ANSI C mode */ +# endif /* ATT && !i386 */ + +# if (defined(ATT) || defined(SVR4)) && !defined(sun) +# ifndef __UNIXWARE__ +# ifndef XQUEUE +# define XQUEUE +# endif +# endif +# include +# endif /* ATT || SVR4 */ + +# ifdef SYSV +# if !defined(ISC) || defined(ISC202) || defined(ISC22) +# define NEED_STRERROR +# endif +# endif + +#endif /* (SYSV || SVR4) && !DGUX */ + + + +/**************************************************************************/ +/* DG/ux R4.20MU03 Intel AViion Machines */ +/**************************************************************************/ +#if defined(DGUX) && defined(SVR4) +#include +#include +#include +#include /* Use termios for BSD Flavor ttys */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* Memory handling */ +#include /* definitios for KDENABIO KDDISABIO needed for IOPL s */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#define POSIX_TTY + +#undef HAS_USL_VTS +#undef USE_VT_SYSREQ +#undef VT_ACKACQ + +#define LED_CAP KBD_LED_CAPS_LOCK +#define LED_NUM KBD_LED_NUM_LOCK +#define LED_SCR KBD_LED_SCROLL_LOCK + +#define KDGKBTYPE KBD_GET_LANGUAGE + + +/* General keyboard types */ +# define KB_84 2 +# define KB_101 1 /* Because ioctl(dgkeybdFd,KBD_GET_LANGUAGE,&type) gives 1=US keyboard */ +# define KB_OTHER 3 + +#define KDSETLED KBD_SET_LED +#define KDGETLED KBD_GET_STATE +#undef KDMKTONE +#define KDMKTONE KBD_TONE_HIGH + + +#undef DEV_MEM +#define DEV_MEM "/dev/mem" +#define CLEARDTR_SUPPORT + +#undef VT_SYSREQ_DEFAULT +#define VT_SYSREQ_DEFAULT FALSE /* Make sure that we dont define any VTs since DG/ux has none */ + +#endif /* DGUX && SVR4 */ + +/**************************************************************************/ +/* Linux or Glibc-based system */ +/**************************************************************************/ +#if defined(__linux__) || defined(__GLIBC__) +# include +# include +# include +# include +# include + +#ifdef __GNU__ /* GNU/Hurd */ +# define USE_OSMOUSE +#endif + +# ifdef __linux__ +# include +# else /* __GLIBC__ */ +# include +# endif +# ifdef __sparc__ +# include +# endif + +# include + +# include + +# include +# ifdef __linux__ +# define HAS_USL_VTS +# include +# include +# define LDGMAP GIO_SCRNMAP +# define LDSMAP PIO_SCRNMAP +# define LDNMAP LDSMAP +# define CLEARDTR_SUPPORT +# define USE_VT_SYSREQ +# endif + +# define POSIX_TTY + +#endif /* __linux__ || __GLIBC__ */ + +/**************************************************************************/ +/* LynxOS AT */ +/**************************************************************************/ +#if defined(Lynx) + +# include +# include +# include +# include +# include +# include +# include + +# include +extern int errno; + +/* smem_create et.al. to access physical memory */ +# include + +/* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + +/* atc drivers ignores argument to VT_RELDISP ioctl */ +# define VT_ACKACQ 2 + +# include +# define POSIX_TTY +# define CLEARDTR_SUPPORT + +/* LynxOS 2.5.1 has these */ +# ifdef LED_NUMLOCK +# define LED_CAP LED_CAPSLOCK +# define LED_NUM LED_NUMLOCK +# define LED_SCR LED_SCROLLOCK +# endif + +#endif /* Lynx */ + +/**************************************************************************/ +/* 386BSD and derivatives, BSD/386 */ +/**************************************************************************/ + +#if defined(__386BSD__) && (defined(__FreeBSD__) || defined(__NetBSD__)) +# undef __386BSD__ +#endif + +#ifdef CSRG_BASED +# include +# include + +# include +# define termio termios +# define POSIX_TTY + +# include + +# include +# include +# include + +# if defined(__bsdi__) +# include +# if (_BSDI_VERSION < 199510) +# include +# endif +# endif /* __bsdi__ */ + +#endif /* CSRG_BASED */ + +/**************************************************************************/ +/* Kernel of *BSD */ +/**************************************************************************/ +#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || \ + defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__) + +# include +# if defined(__FreeBSD_version) && !defined(__FreeBSD_kernel_version) +# define __FreeBSD_kernel_version __FreeBSD_version +# endif + +# if !defined(LINKKIT) + /* Don't need this stuff for the Link Kit */ +# if defined(__bsdi__) +# include +# define CONSOLE_X_MODE_ON PCCONIOCRAW +# define CONSOLE_X_MODE_OFF PCCONIOCCOOK +# define CONSOLE_X_BELL PCCONIOCBEEP +# else /* __bsdi__ */ +# if defined(__OpenBSD__) +# ifdef PCCONS_SUPPORT +# include +# undef CONSOLE_X_MODE_ON +# undef CONSOLE_X_MODE_OFF +# undef CONSOLE_X_BELL +# endif +# endif +# ifdef SYSCONS_SUPPORT +# define COMPAT_SYSCONS +# if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) +# include +# else +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +# if (__FreeBSD_kernel_version >= 410000) +# include +# include +# else +# include +# endif /* FreeBSD 4.1 RELEASE or lator */ +# else +# include +# endif +# endif +# endif /* SYSCONS_SUPPORT */ +# if defined(PCVT_SUPPORT) +# if !defined(SYSCONS_SUPPORT) + /* no syscons, so include pcvt specific header file */ +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +# include +# else +# if defined(__NetBSD__) || defined(__OpenBSD__) +# if !defined(WSCONS_SUPPORT) +# include +# endif /* WSCONS_SUPPORT */ +# else +# include +# endif /* __NetBSD__ */ +# endif /* __FreeBSD_kernel__ || __OpenBSD__ */ +# else /* pcvt and syscons: hard-code the ID magic */ +# define VGAPCVTID _IOWR('V',113, struct pcvtid) + struct pcvtid { + char name[16]; + int rmajor, rminor; + }; +# endif /* PCVT_SUPPORT && SYSCONS_SUPPORT */ +# endif /* PCVT_SUPPORT */ +# ifdef WSCONS_SUPPORT +# include +# include +# endif /* WSCONS_SUPPORT */ +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +# if (__FreeBSD_kernel_version >= 500013) +# include +# else +# undef MOUSE_GETINFO +# include +# endif +# endif + /* Include these definitions in case ioctl_pc.h didn't get included */ +# ifndef CONSOLE_X_MODE_ON +# define CONSOLE_X_MODE_ON _IO('t',121) +# endif +# ifndef CONSOLE_X_MODE_OFF +# define CONSOLE_X_MODE_OFF _IO('t',122) +# endif +# ifndef CONSOLE_X_BELL +# define CONSOLE_X_BELL _IOW('t',123,int[2]) +# endif +# ifndef CONSOLE_X_TV_ON +# define CONSOLE_X_TV_ON _IOW('t',155,int) +# define XMODE_RGB 0 +# define XMODE_NTSC 1 +# define XMODE_PAL 2 +# define XMODE_SECAM 3 +# endif +# ifndef CONSOLE_X_TV_OFF +# define CONSOLE_X_TV_OFF _IO('t',156) +# endif +#ifndef CONSOLE_GET_LINEAR_INFO +# define CONSOLE_GET_LINEAR_INFO _IOR('t',157,struct map_info) +#endif +#ifndef CONSOLE_GET_IO_INFO +# define CONSOLE_GET_IO_INFO _IOR('t',158,struct map_info) +#endif +#ifndef CONSOLE_GET_MEM_INFO +# define CONSOLE_GET_MEM_INFO _IOR('t',159,struct map_info) +#endif +# endif /* __bsdi__ */ +# endif /* !LINKKIT */ + +#if defined(USE_I386_IOPL) || defined(USE_AMD64_IOPL) +#include +#endif + +# define CLEARDTR_SUPPORT + +# if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT) || defined(WSCONS_SUPPORT) +# define USE_VT_SYSREQ +# endif + +#endif +/* __FreeBSD_kernel__ || __NetBSD__ || __OpenBSD__ || __bsdi__ */ + +/**************************************************************************/ +/* OS/2 */ +/**************************************************************************/ +/* currently OS/2 with a modified EMX/GCC compiler only */ +#if defined(__UNIXOS2__) +# include +# include +# include + +/* I would have liked to have this included here always, but + * it causes clashes for BYTE and BOOL with Xmd.h, which is too dangerous. + * So I'll include it in place where I know it does no harm. + */ +#if defined(I_NEED_OS2_H) +# undef BOOL +# undef BYTE +# include +#endif + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +/* could detect more keyboards */ +# define KB_OTHER 3 + + /* LEDs */ +# define LED_CAP 0x40 +# define LED_NUM 0x20 +# define LED_SCR 0x10 + + /* mouse driver */ +# define OSMOUSE_ONLY +# define MOUSE_PROTOCOL_IN_KERNEL + +extern char* __XOS2RedirRoot(char*); + +#endif + +/**************************************************************************/ +/* QNX4 */ +/**************************************************************************/ +/* This is the QNX code for Watcom 10.6 and QNX 4.x */ +#if defined(QNX4) +#include +#include +#include +#include +#include +#include + +/* Warning: by default, the fd_set size is 32 in QNX! */ +#define FD_SETSIZE 256 +#include + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + + /* LEDs */ +# define LED_CAP 0x04 +# define LED_NUM 0x02 +# define LED_SCR 0x01 + +# define POSIX_TTY +# define OSMOUSE_ONLY +# define MOUSE_PROTOCOL_IN_KERNEL + +#define TIOCM_DTR 0x0001 /* data terminal ready */ +#define TIOCM_RTS 0x0002 /* request to send */ +#define TIOCM_CTS 0x1000 /* clear to send */ +#define TIOCM_DSR 0x2000 /* data set ready */ +#define TIOCM_RI 0x4000 /* ring */ +#define TIOCM_RNG TIOCM_RI +#define TIOCM_CD 0x8000 /* carrier detect */ +#define TIOCM_CAR TIOCM_CD +#define TIOCM_LE 0x0100 /* line enable */ +#define TIOCM_ST 0x0200 /* secondary transmit */ +#define TIOCM_SR 0x0400 /* secondary receive */ + +#endif + +/**************************************************************************/ +/* QNX/Neutrino */ +/**************************************************************************/ +/* This is the Neutrino code for for NTO2.0 and GCC */ +#if defined(__QNXNTO__) +#include +#include +#include +#include +#include +#include + +/* Warning: by default, the fd_set size is 32 in NTO! */ +#define FD_SETSIZE 256 +#include + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + +# define POSIX_TTY + +#endif + +/**************************************************************************/ +/* IRIX */ +/**************************************************************************/ +#if defined(sgi) + +#include +#include +#include + +#endif + +/**************************************************************************/ +/* Generic */ +/**************************************************************************/ + +#include /* May need to adjust this for other OSs */ + +/* + * Hack originally for ISC 2.2 POSIX headers, but may apply elsewhere, + * and it's safe, so just do it. + */ +#if !defined(O_NDELAY) && defined(O_NONBLOCK) +# define O_NDELAY O_NONBLOCK +#endif /* !O_NDELAY && O_NONBLOCK */ + +#if !defined(MAXHOSTNAMELEN) +# define MAXHOSTNAMELEN 32 +#endif /* !MAXHOSTNAMELEN */ + +#if !defined(X_NOT_POSIX) +# if defined(_POSIX_SOURCE) +# include +# else +# define _POSIX_SOURCE +# include +# undef _POSIX_SOURCE +# endif /* _POSIX_SOURCE */ +#endif /* !X_NOT_POSIX */ +#if !defined(PATH_MAX) +# if defined(MAXPATHLEN) +# define PATH_MAX MAXPATHLEN +# else +# define PATH_MAX 1024 +# endif /* MAXPATHLEN */ +#endif /* !PATH_MAX */ + +#ifdef NEED_STRERROR +# ifndef strerror +extern char *sys_errlist[]; +extern int sys_nerr; +# define strerror(n) \ + ((n) >= 0 && (n) < sys_nerr) ? sys_errlist[n] : "unknown error" +# endif /* !strerror */ +#endif /* NEED_STRERROR */ + +#if defined(ISC) || defined(Lynx) +#define rint(x) RInt(x) +double RInt( + double x +); +#endif + +#ifndef DEV_MEM +#define DEV_MEM "/dev/mem" +#endif + +#ifndef VT_SYSREQ_DEFAULT +#define VT_SYSREQ_DEFAULT FALSE +#endif + +#ifdef OSMOUSE_ONLY +# ifndef MOUSE_PROTOCOL_IN_KERNEL +# define MOUSE_PROTOCOL_IN_KERNEL +# endif +#endif + +#define SYSCALL(call) while(((call) == -1) && (errno == EINTR)) + +#define XF86_OS_PRIVS +#include "xf86_OSproc.h" + +#ifndef NO_COMPILER_H +#include "compiler.h" +#endif + +#endif /* _XF86_OSLIB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_OSproc.h (revision 51223) @@ -0,0 +1,277 @@ +/* + * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany + * Copyright 1992 by David Dawes + * Copyright 1992 by Jim Tsillas + * Copyright 1992 by Rich Murphey + * Copyright 1992 by Robert Baron + * Copyright 1992 by Orest Zborowski + * Copyright 1993 by Vrije Universiteit, The Netherlands + * Copyright 1993 by David Wexelblat + * Copyright 1994, 1996 by Holger Veit + * Copyright 1994-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * The ARM32 code here carries the following copyright: + * + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the + * source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" + * name nor any trademark or logo of Digital Equipment Corporation may be + * used to endorse or promote products derived from this software without + * the prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. + * In no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for lost profits, loss + * of revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even + * if advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v 3.56 2003/08/24 17:37:03 dawes Exp $ */ + +#ifndef _XF86_OSPROC_H +#define _XF86_OSPROC_H + +#ifdef XF86_OS_PRIVS +#include "xf86Pci.h" +#endif + +/* + * The actual prototypes have been pulled into this seperate file so + * that they can can be used without pulling in all of the OS specific + * stuff like sys/stat.h, etc. This casues problem for loadable modules. + */ + +/* + * Flags for xf86MapVidMem(). Multiple flags can be or'd together. The + * flags may be used as hints. For example it would be permissible to + * enable write combining for memory marked only for framebuffer use. + */ + +#define VIDMEM_FRAMEBUFFER 0x01 /* memory for framebuffer use */ +#define VIDMEM_MMIO 0x02 /* memory for I/O use */ +#define VIDMEM_MMIO_32BIT 0x04 /* memory accesses >= 32bit */ +#define VIDMEM_READSIDEEFFECT 0x08 /* reads can have side-effects */ +#define VIDMEM_SPARSE 0x10 /* sparse mapping required + * assumed when VIDMEM_MMIO is + * set. May be used with + * VIDMEM_FRAMEBUFFER) */ +#define VIDMEM_READONLY 0x20 /* read-only mapping + * used when reading BIOS images + * through xf86MapVidMem() */ + +/* + * OS-independent modem state flags for xf86SetSerialModemState() and + * xf86GetSerialModemState(). + */ +#define XF86_M_LE 0x001 /* line enable */ +#define XF86_M_DTR 0x002 /* data terminal ready */ +#define XF86_M_RTS 0x004 /* request to send */ +#define XF86_M_ST 0x008 /* secondary transmit */ +#define XF86_M_SR 0x010 /* secondary receive */ +#define XF86_M_CTS 0x020 /* clear to send */ +#define XF86_M_CAR 0x040 /* carrier detect */ +#define XF86_M_RNG 0x080 /* ring */ +#define XF86_M_DSR 0x100 /* data set ready */ + +#ifdef XF86_OS_PRIVS +extern void xf86WrapperInit(void); +#endif + +#ifndef NO_OSLIB_PROTOTYPES +/* + * This is to prevent re-entrancy to FatalError() when aborting. + * Anything that can be called as a result of AbortDDX() should use this + * instead of FatalError(). + */ + +#define xf86FatalError(a, b) \ + if (dispatchException & DE_TERMINATE) { \ + ErrorF(a, b); \ + ErrorF("\n"); \ + return; \ + } else FatalError(a, b) + +/***************************************************************************/ +/* Prototypes */ +/***************************************************************************/ + +#include +#include "opaque.h" + +#if defined(XQUEUE) +#include "input.h" /* for DeviceIntPtr */ +#endif + +_XFUNCPROTOBEGIN + +/* public functions */ +extern Bool xf86LinearVidMem(void); +extern Bool xf86CheckMTRR(int); +extern pointer xf86MapVidMem(int, int, unsigned long, unsigned long); +extern void xf86UnMapVidMem(int, pointer, unsigned long); +extern void xf86MapReadSideEffects(int, int, pointer, unsigned long); +extern int xf86ReadBIOS(unsigned long, unsigned long, unsigned char *, int); +extern Bool xf86EnableIO(void); +extern void xf86DisableIO(void); +extern Bool xf86DisableInterrupts(void); +extern void xf86EnableInterrupts(void); +extern void xf86SetTVOut(int); +extern void xf86SetRGBOut(void); +extern void xf86SoundKbdBell(int, int, int); +#if defined(QNX4) +#pragma aux xf86BusToMem modify [eax ebx ecx edx esi edi]; +#pragma aux xf86MemToBus modify [eax ebx ecx edx esi edi]; +#endif +extern void xf86BusToMem(unsigned char *, unsigned char *, int); +extern void xf86MemToBus(unsigned char *, unsigned char *, int); +extern void xf86IODelay(void); +extern void xf86UDelay(long usec); +extern void xf86SlowBcopy(unsigned char *, unsigned char *, int); +extern int xf86OpenSerial(pointer options); +extern int xf86SetSerial(int fd, pointer options); +extern int xf86SetSerialSpeed(int fd, int speed); +extern int xf86ReadSerial(int fd, void *buf, int count); +extern int xf86WriteSerial(int fd, const void *buf, int count); +extern int xf86CloseSerial(int fd); +extern int xf86FlushInput(int fd); +extern int xf86WaitForInput(int fd, int timeout); +extern int xf86SerialSendBreak(int fd, int duration); +extern int xf86SetSerialModemState(int fd, int state); +extern int xf86GetSerialModemState(int fd); +extern int xf86SerialModemSetBits(int fd, int bits); +extern int xf86SerialModemClearBits(int fd, int bits); +extern int xf86LoadKernelModule(const char *pathname); + +/* AGP GART interface */ + +typedef struct _AgpInfo { + CARD32 bridgeId; + CARD32 agpMode; + unsigned long base; + unsigned long size; + unsigned long totalPages; + unsigned long systemPages; + unsigned long usedPages; +} AgpInfo, *AgpInfoPtr; + +extern Bool xf86AgpGARTSupported(void); +extern AgpInfoPtr xf86GetAGPInfo(int screenNum); +extern Bool xf86AcquireGART(int screenNum); +extern Bool xf86ReleaseGART(int screenNum); +extern int xf86AllocateGARTMemory(int screenNum, unsigned long size, int type, + unsigned long *physical); +extern Bool xf86DeallocateGARTMemory(int screenNum, int key); +extern Bool xf86BindGARTMemory(int screenNum, int key, unsigned long offset); +extern Bool xf86UnbindGARTMemory(int screenNum, int key); +extern Bool xf86EnableAGP(int screenNum, CARD32 mode); +extern Bool xf86GARTCloseScreen(int screenNum); + +/* These routines are in shared/sigio.c and are not loaded as part of the + module. These routines are small, and the code if very POSIX-signal (or + OS-signal) specific, so it seemed better to provide more complex + wrappers than to wrap each individual function called. */ +extern int xf86InstallSIGIOHandler(int fd, void (*f)(int, void *), void *); +extern int xf86RemoveSIGIOHandler(int fd); +extern int xf86BlockSIGIO (void); +extern void xf86UnblockSIGIO (int); +#ifdef XFree86Server +extern void xf86AssertBlockedSIGIO (char *); +#endif +extern Bool xf86SIGIOSupported (void); + +#ifdef XF86_OS_PRIVS +typedef void (*PMClose)(void); +extern void xf86OpenConsole(void); +extern void xf86CloseConsole(void); +extern Bool xf86VTSwitchPending(void); +extern Bool xf86VTSwitchAway(void); +extern Bool xf86VTSwitchTo(void); +extern void xf86VTRequest(int sig); +extern int xf86ProcessArgument(int, char **, int); +extern void xf86UseMsg(void); +extern void xf86SetKbdLeds(int); +extern int xf86GetKbdLeds(void); +extern void xf86SetKbdRepeat(char); +extern void xf86KbdInit(void); +extern int xf86KbdOn(void); +extern int xf86KbdOff(void); +extern void xf86KbdEvents(void); +#ifdef XQUEUE +extern int xf86XqueKbdProc(DeviceIntPtr, int); +extern void xf86XqueEvents(void); +#endif +extern void xf86ReloadInputDevs(int sig); +#ifdef WSCONS_SUPPORT +extern void xf86WSKbdEvents(void); +#endif +extern PMClose xf86OSPMOpen(void); + +#ifdef NEED_OS_RAC_PROTOS +/* RAC-related privs */ +/* internal to os-support layer */ +resPtr xf86StdBusAccWindowsFromOS(void); +resPtr xf86StdPciAccWindowsFromOS(void); +resPtr xf86StdIsaAccWindowsFromOS(void); +resPtr xf86StdAccResFromOS(resPtr ret); + +/* available to the common layer */ +resPtr xf86BusAccWindowsFromOS(void); +resPtr xf86PciBusAccWindowsFromOS(void); +#ifdef INCLUDE_UNUSED +resPtr xf86IsaBusAccWindowsFromOS(void); +#endif +resPtr xf86AccResFromOS(resPtr ret); +#endif /* NEED_OS_RAC_PROTOS */ + +extern Bool xf86GetPciSizeFromOS(PCITAG tag, int indx, int* bits); +extern Bool xf86GetPciOffsetFromOS(PCITAG tag, int indx, unsigned long* bases); +extern unsigned long xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base); + +extern void xf86MakeNewMapping(int, int, unsigned long, unsigned long, pointer); +extern void xf86InitVidMem(void); + +#endif /* XF86_OS_PRIVS */ + + +_XFUNCPROTOEND +#endif /* NO_OSLIB_PROTOTYPES */ + +#endif /* _XF86_OSPROC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_ansic.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_ansic.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_ansic.h (revision 51223) @@ -0,0 +1,354 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_ansic.h,v 3.53 2003/10/28 18:36:37 tsi Exp $ */ +/* + * Copyright 1997-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef _XF86_ANSIC_H +#define _XF86_ANSIC_H + +/* Handle */ + +#ifndef IN_MODULE +# include +#else /* !IN_MODULE */ +# ifndef __OS2ELF__ +# include +# else /* __OS2ELF__ */ + /* EMX/gcc_elf under OS/2 does not have native header files */ +# if !defined (_VA_LIST) +# define _VA_LIST + typedef char *va_list; +# endif +# define _VA_ROUND(t) ((sizeof (t) + 3) & -4) +# if !defined (va_start) +# define va_start(ap,v) ap = (va_list)&v + ((sizeof (v) + 3) & -4) +# define va_end(ap) (ap = 0, (void)0) +# define va_arg(ap,t) (ap += _VA_ROUND (t), *(t *)(ap - _VA_ROUND (t))) +# endif +# endif /* __OS2ELF__ */ +#endif /* IN_MODULE */ + +/* + * The first set of definitions are required both for modules and + * libc_wrapper.c. + */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_TYPES) + +#if !defined(SYSV) && !defined(SVR4) && !defined(Lynx) || \ + defined(__SCO__) || defined(__UNIXWARE__) +#define HAVE_VSSCANF +#define HAVE_VFSCANF +#endif + +#ifndef NULL +#if (defined(SVR4) || defined(SYSV)) && !defined(__GNUC__) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif +#endif +#ifndef EOF +#define EOF (-1) +#endif + +#ifndef PATH_MAX +#define PATH_MAX 1024 +#endif + +/* stuff */ +#define x_BITSPERBYTE 8 +#define x_BITS(type) (x_BITSPERBYTE * (int)sizeof(type)) +#define x_SHORTBITS x_BITS(short) +#define x_INTBITS x_BITS(int) +#define x_LONGBITS x_BITS(long) +#ifndef SHRT_MIN +#define SHRT_MIN ((short)(1 << (x_SHORTBITS - 1))) +#endif + +#ifndef FONTMODULE +#include "misc.h" +#endif +#include "xf86_libc.h" +#ifndef SHRT_MAX +#define SHRT_MAX ((short)~SHRT_MIN) +#endif +#ifndef USHRT_MAX +#define USHRT_MAX ((unsigned short)~0) +#endif +#ifndef MINSHORT +#define MINSHORT SHRT_MIN +#endif +#ifndef MAXSHORT +#define MAXSHORT SHRT_MAX +#endif +#ifndef INT_MIN +#define INT_MIN (1 << (x_INTBITS - 1)) +#endif +#ifndef INT_MAX +#define INT_MAX (~INT_MIN) +#endif +#ifndef UINT_MAX +#define UINT_MAX (~0) +#endif +#ifndef MININT +#define MININT INT_MIN +#endif +#ifndef MAXINT +#define MAXINT INT_MAX +#endif +#ifndef LONG_MIN +#define LONG_MIN ((long)(1 << (x_LONGBITS - 1))) +#endif +#ifndef LONG_MAX +#define LONG_MAX ((long)~LONG_MIN) +#endif +#ifndef ULONG_MAX +#define ULONG_MAX ((unsigned long)~0UL) +#endif +#ifndef MINLONG +#define MINLONG LONG_MIN +#endif +#ifndef MAXLONG +#define MAXLONG LONG_MAX +#endif + +#endif /* XFree86LOADER || NEED_XF86_TYPES */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_PROTOTYPES) +/* + * ANSI C compilers only. + */ + +/* ANSI C emulation library */ + +extern void xf86abort(void); +extern int xf86abs(int); +extern double xf86acos(double); +extern double xf86asin(double); +extern double xf86atan(double); +extern double xf86atan2(double,double); +extern double xf86atof(const char*); +extern int xf86atoi(const char*); +extern long xf86atol(const char*); +extern void *xf86bsearch(const void *, const void *, xf86size_t, xf86size_t, + int (*)(const void *, const void *)); +extern double xf86ceil(double); +extern void* xf86calloc(xf86size_t,xf86size_t); +extern void xf86clearerr(XF86FILE*); +extern double xf86cos(double); +extern void xf86exit(int); +extern double xf86exp(double); +extern double xf86fabs(double); +extern int xf86fclose(XF86FILE*); +extern int xf86feof(XF86FILE*); +extern int xf86ferror(XF86FILE*); +extern int xf86fflush(XF86FILE*); +extern int xf86fgetc(XF86FILE*); +extern int xf86getc(XF86FILE*); +extern int xf86fgetpos(XF86FILE*,XF86fpos_t*); +extern char* xf86fgets(char*,INT32,XF86FILE*); +extern int xf86finite(double); +extern double xf86floor(double); +extern double xf86fmod(double,double); +extern XF86FILE* xf86fopen(const char*,const char*); +extern double xf86frexp(double, int*); +extern int xf86printf(const char*,...); +extern int xf86fprintf(XF86FILE*,const char*,...); +extern int xf86fputc(int,XF86FILE*); +extern int xf86fputs(const char*,XF86FILE*); +extern xf86size_t xf86fread(void*,xf86size_t,xf86size_t,XF86FILE*); +extern void xf86free(void*); +extern XF86FILE* xf86freopen(const char*,const char*,XF86FILE*); +#if defined(HAVE_VFSCANF) || !defined(NEED_XF86_PROTOTYPES) +extern int xf86fscanf(XF86FILE*,const char*,...); +#else +extern int xf86fscanf(/*XF86FILE*,const char*,char *,char *,char *,char *, + char *,char *,char *,char *,char *,char * */); +#endif +extern int xf86fseek(XF86FILE*,long,int); +extern int xf86fsetpos(XF86FILE*,const XF86fpos_t*); +extern long xf86ftell(XF86FILE*); +extern xf86size_t xf86fwrite(const void*,xf86size_t,xf86size_t,XF86FILE*); +extern char* xf86getenv(const char*); +extern int xf86isalnum(int); +extern int xf86isalpha(int); +extern int xf86iscntrl(int); +extern int xf86isdigit(int); +extern int xf86isgraph(int); +extern int xf86islower(int); +extern int xf86isprint(int); +extern int xf86ispunct(int); +extern int xf86isspace(int); +extern int xf86isupper(int); +extern int xf86isxdigit(int); +extern long xf86labs(long); +extern double xf86ldexp(double,int); +extern double xf86log(double); +extern double xf86log10(double); +extern void* xf86malloc(xf86size_t); +extern void* xf86memchr(const void*,int,xf86size_t); +extern int xf86memcmp(const void*,const void*,xf86size_t); +extern void* xf86memcpy(void*,const void*,xf86size_t); +extern void* xf86memmove(void*,const void*,xf86size_t); +extern void* xf86memset(void*,int,xf86size_t); +extern double xf86modf(double,double*); +extern void xf86perror(const char*); +extern double xf86pow(double,double); +extern void xf86qsort(void*, xf86size_t, xf86size_t, + int(*)(const void*, const void*)); +extern void* xf86realloc(void*,xf86size_t); +extern int xf86remove(const char*); +extern int xf86rename(const char*,const char*); +extern void xf86rewind(XF86FILE*); +extern int xf86setbuf(XF86FILE*,char*); +extern int xf86setvbuf(XF86FILE*,char*,int,xf86size_t); +extern double xf86sin(double); +extern int xf86sprintf(char*,const char*,...); +extern int xf86snprintf(char*,xf86size_t,const char*,...); +extern double xf86sqrt(double); +#if defined(HAVE_VSSCANF) || !defined(NEED_XF86_PROTOTYPES) +extern int xf86sscanf(char*,const char*,...); +#else +extern int xf86sscanf(/*char*,const char*,char *,char *,char *,char *, + char *,char *,char *,char *,char *,char * */); +#endif +extern char* xf86strcat(char*,const char*); +extern char* xf86strchr(const char*, int c); +extern int xf86strcmp(const char*,const char*); +extern int xf86strcasecmp(const char*,const char*); +extern char* xf86strcpy(char*,const char*); +extern xf86size_t xf86strcspn(const char*,const char*); +extern char* xf86strerror(int); +extern xf86size_t xf86strlcat(char*,const char*,xf86size_t); +extern xf86size_t xf86strlcpy(char*,const char*,xf86size_t); +extern xf86size_t xf86strlen(const char*); +extern char* xf86strncat(char *, const char *, xf86size_t); +extern int xf86strncmp(const char*,const char*,xf86size_t); +extern int xf86strncasecmp(const char*,const char*,xf86size_t); +extern char* xf86strncpy(char*,const char*,xf86size_t); +extern char* xf86strpbrk(const char*,const char*); +extern char* xf86strrchr(const char*,int); +extern xf86size_t xf86strspn(const char*,const char*); +extern char* xf86strstr(const char*,const char*); +extern double xf86strtod(const char*,char**); +extern char* xf86strtok(char*,const char*); +extern long xf86strtol(const char*,char**,int); +extern unsigned long xf86strtoul(const char*,char**,int); +extern double xf86tan(double); +extern XF86FILE* xf86tmpfile(void); +extern char* xf86tmpnam(char*); +extern int xf86tolower(int); +extern int xf86toupper(int); +extern int xf86ungetc(int,XF86FILE*); +extern int xf86vfprintf(XF86FILE*,const char*,va_list); +extern int xf86vsprintf(char*,const char*,va_list); +extern int xf86vsnprintf(char*,xf86size_t,const char*,va_list); + +extern int xf86open(const char*, int,...); +extern int xf86close(int); +extern long xf86lseek(int, long, int); +extern int xf86ioctl(int, unsigned long, pointer); +extern xf86ssize_t xf86read(int, void *, xf86size_t); +extern xf86ssize_t xf86write(int, const void *, xf86size_t); +extern void* xf86mmap(void*, xf86size_t, int, int, int, xf86size_t /* off_t */); +extern int xf86munmap(void*, xf86size_t); +extern int xf86stat(const char *, struct xf86stat *); +extern int xf86fstat(int, struct xf86stat *); +extern int xf86access(const char *, int); +extern int xf86errno; +extern int xf86GetErrno(void); + +extern double xf86HUGE_VAL; + +extern double xf86hypot(double,double); + +/* non-ANSI C functions */ +extern XF86DIR* xf86opendir(const char*); +extern int xf86closedir(XF86DIR*); +extern XF86DIRENT* xf86readdir(XF86DIR*); +extern void xf86rewinddir(XF86DIR*); +extern void xf86bcopy(const void*,void*,xf86size_t); +extern int xf86ffs(int); +extern char* xf86strdup(const char*); +extern void xf86bzero(void*,unsigned int); +extern int xf86execl(const char *, const char *, ...); +extern long xf86fpossize(void); +extern int xf86chmod(const char *, xf86mode_t); +extern int xf86chown(const char *, xf86uid_t, xf86gid_t); +extern xf86uid_t xf86geteuid(void); +extern xf86gid_t xf86getegid(void); +extern int xf86getpid(void); +extern int xf86mknod(const char *, xf86mode_t, xf86dev_t); +extern int xf86mkdir(const char *, xf86mode_t); +unsigned int xf86sleep(unsigned int seconds); +/* sysv IPC */ +extern int xf86shmget(xf86key_t key, int size, int xf86shmflg); +extern char * xf86shmat(int id, char *addr, int xf86shmflg); +extern int xf86shmdt(char *addr); +extern int xf86shmctl(int id, int xf86cmd, pointer buf); + +extern int xf86setjmp(xf86jmp_buf env); +extern int xf86setjmp0(xf86jmp_buf env); +extern int xf86setjmp1(xf86jmp_buf env, int); +extern int xf86setjmp1_arg2(void); +extern int xf86setjmperror(xf86jmp_buf env); +extern int xf86getjmptype(void); +extern void xf86longjmp(xf86jmp_buf env, int val); +#define xf86setjmp_macro(env) \ + (xf86getjmptype() == 0 ? xf86setjmp0((env)) : \ + (xf86getjmptype() == 1 ? xf86setjmp1((env), xf86setjmp1_arg2()) : \ + xf86setjmperror((env)))) + +#else /* XFree86LOADER || NEED_XF86_PROTOTYPES */ +#include +#include +#include +#include +#include +#include +#ifdef HAVE_SYSV_IPC +#include +#include +#endif +#include +#define stat_t struct stat +#endif /* XFree86LOADER || NEED_XF86_PROTOTYPES */ + +/* + * These things are always required by drivers (but not by libc_wrapper.c), + * even for a static server because some OSs don't provide them. + */ + +extern int xf86getpagesize(void); +extern void xf86usleep(unsigned long); +extern void xf86getsecs(long *, long *); +#ifndef DONT_DEFINE_WRAPPERS +#undef getpagesize +#define getpagesize() xf86getpagesize() +#undef usleep +#define usleep(ul) xf86usleep(ul) +#undef getsecs +#define getsecs(a, b) xf86getsecs(a, b) +#endif +#endif /* _XF86_ANSIC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_libc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_libc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86_libc.h (revision 51223) @@ -0,0 +1,726 @@ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/os-support/xf86_libc.h,v 1.6 2005/04/22 22:04:37 alanc Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_libc.h,v 3.63 2003/12/08 21:46:55 alanh Exp $ */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file is an attempt to make developing code for the new loadable module + * architecure simpler. It tries to use macros to hide all libc wrappers so + * that all that is needed to "port" a module to this architecture is to + * include this one header file + * + * Revision history: + * + * + * 0.4 Apr 12 1997 add the ANSI defines + * 0.3 Feb 24 1997 handle getenv + * 0.2 Feb 24 1997 hide few FILE functions + * 0.1 Feb 24 1997 hide the trivial functions mem* str* + */ + +#ifndef XF86_LIBC_H +#define XF86_LIBC_H 1 + +#include +#include + +/* + * The first set of definitions are required both for modules and + * libc_wrapper.c. + */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_TYPES) + +/* + * First, the new data types + * + * note: if some pointer is declared "opaque" here, pass it between + * xf86* functions only, and don't rely on it having a whatever internal + * structure, even if some source file might reveal the existence of + * such a structure. + */ +typedef void XF86FILE; /* opaque FILE replacement */ +extern XF86FILE* xf86stdin; +extern XF86FILE* xf86stdout; +extern XF86FILE* xf86stderr; + +typedef void XF86fpos_t; /* opaque fpos_t replacement */ + +#define _XF86NAMELEN 263 /* enough for a larger filename */ + /* (divisble by 8) */ +typedef void XF86DIR; /* opaque DIR replacement */ + +/* Note: the following is POSIX! POSIX only requires the d_name member. + * Normal Unix has often a number of other members, but don't rely on that + */ +struct _xf86dirent { /* types in struct dirent/direct: */ + char d_name[_XF86NAMELEN+1]; /* char [MAXNAMLEN]; might be smaller or unaligned */ +}; +typedef struct _xf86dirent XF86DIRENT; + +typedef unsigned long xf86size_t; +typedef signed long xf86ssize_t; +typedef unsigned long xf86dev_t; +typedef unsigned int xf86mode_t; +typedef unsigned int xf86uid_t; +typedef unsigned int xf86gid_t; + +struct xf86stat { + xf86dev_t st_rdev; /* This is incomplete, and makes assumptions */ +}; + +/* sysv IPC */ +typedef int xf86key_t; + +/* setjmp/longjmp */ +#if defined(__ia64__) +typedef int xf86jmp_buf[1024] __attribute__ ((aligned (16))); /* guarantees 128-bit alignment! */ +#else +typedef int xf86jmp_buf[1024]; +#endif + +/* for setvbuf */ +#define XF86_IONBF 1 +#define XF86_IOFBF 2 +#define XF86_IOLBF 3 + +/* for open (XXX not complete) */ +#define XF86_O_RDONLY 0x0000 +#define XF86_O_WRONLY 0x0001 +#define XF86_O_RDWR 0x0002 +#define XF86_O_CREAT 0x0200 + +/* for mmap */ +#define XF86_PROT_EXEC 0x0001 +#define XF86_PROT_READ 0x0002 +#define XF86_PROT_WRITE 0x0004 +#define XF86_PROT_NONE 0x0008 +#define XF86_MAP_FIXED 0x0001 +#define XF86_MAP_SHARED 0x0002 +#define XF86_MAP_PRIVATE 0x0004 +#define XF86_MAP_32BIT 0x0040 +#define XF86_MAP_FAILED ((void *)-1) + +/* for fseek */ +#define XF86_SEEK_SET 0 +#define XF86_SEEK_CUR 1 +#define XF86_SEEK_END 2 + +/* for access */ +#define XF86_R_OK 0 +#define XF86_W_OK 1 +#define XF86_X_OK 2 +#define XF86_F_OK 3 + +/* for chmod */ +#define XF86_S_ISUID 04000 /* set user ID on execution */ +#define XF86_S_ISGID 02000 /* set group ID on execution */ +#define XF86_S_ISVTX 01000 /* sticky bit */ +#define XF86_S_IRUSR 00400 /* read by owner */ +#define XF86_S_IWUSR 00200 /* write by owner */ +#define XF86_S_IXUSR 00100 /* execute/search by owner */ +#define XF86_S_IRGRP 00040 /* read by group */ +#define XF86_S_IWGRP 00020 /* write by group */ +#define XF86_S_IXGRP 00010 /* execute/search by group */ +#define XF86_S_IROTH 00004 /* read by others */ +#define XF86_S_IWOTH 00002 /* write by others */ +#define XF86_S_IXOTH 00001 /* execute/search by others */ + +/* for mknod */ +#define XF86_S_IFREG 0010000 +#define XF86_S_IFCHR 0020000 +#define XF86_S_IFBLK 0040000 +#define XF86_S_IFIFO 0100000 + +/* + * errno values + * They start at 1000 just so they don't match real errnos at all + */ +#define xf86_UNKNOWN 1000 +#define xf86_EACCES 1001 +#define xf86_EAGAIN 1002 +#define xf86_EBADF 1003 +#define xf86_EEXIST 1004 +#define xf86_EFAULT 1005 +#define xf86_EINTR 1006 +#define xf86_EINVAL 1007 +#define xf86_EISDIR 1008 +#define xf86_ELOOP 1009 +#define xf86_EMFILE 1010 +#define xf86_ENAMETOOLONG 1011 +#define xf86_ENFILE 1012 +#define xf86_ENOENT 1013 +#define xf86_ENOMEM 1014 +#define xf86_ENOSPC 1015 +#define xf86_ENOTDIR 1016 +#define xf86_EPIPE 1017 +#define xf86_EROFS 1018 +#define xf86_ETXTBSY 1019 +#define xf86_ENOTTY 1020 +#define xf86_ENOSYS 1021 +#define xf86_EBUSY 1022 +#define xf86_ENODEV 1023 +#define xf86_EIO 1024 + +#define xf86_ESRCH 1025 +#define xf86_ENXIO 1026 +#define xf86_E2BIG 1027 +#define xf86_ENOEXEC 1028 +#define xf86_ECHILD 1029 +#define xf86_ENOTBLK 1030 +#define xf86_EXDEV 1031 +#define xf86_EFBIG 1032 +#define xf86_ESPIPE 1033 +#define xf86_EMLINK 1034 +#define xf86_EDOM 1035 +#define xf86_ERANGE 1036 + + +/* sysv IPV */ +/* xf86shmget() */ +#define XF86IPC_CREAT 01000 +#define XF86IPC_EXCL 02000 +#define XF86IPC_NOWAIT 04000 +#define XF86SHM_R 0400 +#define XF86SHM_W 0200 +#define XF86IPC_PRIVATE ((xf86key_t)0) +/* xf86shmat() */ +#define XF86SHM_RDONLY 010000 /* attach read-only else read-write */ +#define XF86SHM_RND 020000 /* round attach address to SHMLBA */ +#define XF86SHM_REMAP 040000 /* take-over region on attach */ +/* xf86shmclt() */ +#define XF86IPC_RMID 0 + +#endif /* defined(XFree86LOADER) || defined(NEED_XF86_TYPES) */ + +/* + * the rest of this file should only be included for code that is supposed + * to go into modules + */ + +#if defined(XFree86LOADER) && !defined(DONT_DEFINE_WRAPPERS) + +#undef abort +#define abort() xf86abort() +#undef abs +#define abs(i) xf86abs(i) +#undef acos +#define acos(d) xf86acos(d) +#undef asin +#define asin(d) xf86asin(d) +#undef atan +#define atan(d) xf86atan(d) +#undef atan2 +#define atan2(d1,d2) xf86atan2(d1,d2) +#undef atof +#define atof(ccp) xf86atof(ccp) +#undef atoi +#define atoi(ccp) xf86atoi(ccp) +#undef atol +#define atol(ccp) xf86atol(ccp) +#undef bsearch +#define bsearch(a,b,c,d,e) xf86bsearch(a,b,c,d,e) +#undef ceil +#define ceil(d) xf86ceil(d) +#undef calloc +#define calloc(I1,I2) xf86calloc(I1,I2) +#undef clearerr +#define clearerr(FP) xf86clearerr(FP) +#undef cos +#define cos(d) xf86cos(d) +#undef exit +#define exit(i) xf86exit(i) +#undef exp +#define exp(d) xf86exp(d) +#undef fabs +#define fabs(d) xf86fabs(d) +#undef fclose +#define fclose(FP) xf86fclose(FP) +#undef feof +#define feof(FP) xf86feof(FP) +#undef ferror +#define ferror(FP) xf86ferror(FP) +#undef fflush +#define fflush(FP) xf86fflush(FP) +#undef fgetc +#define fgetc(FP) xf86fgetc(FP) +#undef getc +#define getc(FP) xf86getc(FP) +#undef fgetpos +#define fgetpos(FP,fpp) xf86fgetpos(FP,fpp) +#undef fgets +#define fgets(cp,i,FP) xf86fgets(cp,i,FP) +#undef finite +#define finite(d) xf86finite(d) +#undef floor +#define floor(d) xf86floor(d) +#undef fmod +#define fmod(d1,d2) xf86fmod(d1,d2) +#undef fopen +#define fopen(ccp1,ccp2) xf86fopen(ccp1,ccp2) +#undef printf +#define printf xf86printf +#undef fprintf +#define fprintf xf86fprintf +#undef fputc +#define fputc(i,FP) xf86fputc(i,FP) +#undef fputs +#define fputs(ccp,FP) xf86fputs(ccp,FP) +#undef fread +#define fread(vp,I1,I2,FP) xf86fread(vp,I1,I2,FP) +#undef free +#define free(vp) xf86free(vp) +#undef freopen +#define freopen(ccp1,ccp2,FP) xf86freopen(ccp1,ccp2,FP) +#undef frexp +#define frexp(x,exp) xf86frexp(x,exp) +#undef fscanf +#define fscanf xf86fscanf +#undef fseek +#define fseek(FP,l,i) xf86fseek(FP,l,i) +#undef fsetpos +#define fsetpos(FP,cfpp) xf86fsetpos(FP,cfpp) +#undef ftell +#define ftell(FP) xf86ftell(FP) +#undef fwrite +#define fwrite(cvp,I1,I2,FP) xf86fwrite(cvp,I1,I2,FP) +#undef getenv +#define getenv(ccp) xf86getenv(ccp) +#undef isalnum +#define isalnum(i) xf86isalnum(i) +#undef isalpha +#define isalpha(i) xf86isalpha(i) +#undef iscntrl +#define iscntrl(i) xf86iscntrl(i) +#undef isdigit +#define isdigit(i) xf86isdigit(i) +#undef isgraph +#define isgraph(i) xf86isgraph(i) +#undef islower +#define islower(i) xf86islower(i) +#undef isprint +#define isprint(i) xf86isprint(i) +#undef ispunct +#define ispunct(i) xf86ispunct(i) +#undef isspace +#define isspace(i) xf86isspace(i) +#undef isupper +#define isupper(i) xf86isupper(i) +#undef isxdigit +#define isxdigit(i) xf86isxdigit(i) +#undef labs +#define labs(l) xf86labs(l) +#undef ldexp +#define ldexp(x, exp) xf86ldexp(x, exp) +#undef log +#define log(d) xf86log(d) +#undef log10 +#define log10(d) xf86log10(d) +#undef malloc +#define malloc(I) xf86malloc(I) +#undef memchr +#define memchr(cvp,i,I) xf86memchr(cvp,i,I) +#undef memcmp +#define memcmp(cvp1,cvp2,I) xf86memcmp(cvp1,cvp2,I) +#undef memcpy +#define memcpy(vp,cvp,I) xf86memcpy(vp,cvp,I) +#undef memmove +#define memmove(vp,cvp,I) xf86memmove(vp,cvp,I) +#undef memset +#define memset(vp,int,I) xf86memset(vp,int,I) +#undef modf +#define modf(d,dp) xf86modf(d,dp) +#undef perror +#define perror(ccp) xf86perror(ccp) +#undef pow +#define pow(d1,d2) xf86pow(d1,d2) +#undef realloc +#define realloc(vp,I) xf86realloc(vp,I) +#undef remove +#define remove(ccp) xf86remove(ccp) +#undef rename +#define rename(ccp1,ccp2) xf86rename(ccp1,ccp2) +#undef rewind +#define rewind(FP) xf86rewind(FP) +#undef setbuf +#define setbuf(FP,cp) xf86setbuf(FP,cp) +#undef setvbuf +#define setvbuf(FP,cp,i,I) xf86setvbuf(FP,cp,i,I) +#undef sin +#define sin(d) xf86sin(d) +#undef snprintf +#define snprintf xf86snprintf +#undef sprintf +#define sprintf xf86sprintf +#undef sqrt +#define sqrt(d) xf86sqrt(d) +#undef sscanf +#define sscanf xf86sscanf +#undef strcat +#define strcat(cp,ccp) xf86strcat(cp,ccp) +#undef strcmp +#define strcmp(ccp1,ccp2) xf86strcmp(ccp1,ccp2) +#undef strcasecmp +#define strcasecmp(ccp1,ccp2) xf86strcasecmp(ccp1,ccp2) +#undef strcpy +#define strcpy(cp,ccp) xf86strcpy(cp,ccp) +#undef strcspn +#define strcspn(ccp1,ccp2) xf86strcspn(ccp1,ccp2) +#undef strerror +#define strerror(i) xf86strerror(i) +#undef strlcat +#define strlcat(cp,ccp,I) xf86strlcat(cp,ccp,I) +#undef strlcpy +#define strlcpy(cp,ccp,I) xf86strlcpy(cp,ccp,I) +#undef strlen +#define strlen(ccp) xf86strlen(ccp) +#undef strncmp +#define strncmp(ccp1,ccp2,I) xf86strncmp(ccp1,ccp2,I) +#undef strncasecmp +#define strncasecmp(ccp1,ccp2,I) xf86strncasecmp(ccp1,ccp2,I) +#undef strncpy +#define strncpy(cp,ccp,I) xf86strncpy(cp,ccp,I) +#undef strpbrk +#define strpbrk(ccp1,ccp2) xf86strpbrk(ccp1,ccp2) +#undef strchr +#define strchr(ccp,i) xf86strchr(ccp,i) +#undef strrchr +#define strrchr(ccp,i) xf86strrchr(ccp,i) +#undef strspn +#define strspn(ccp1,ccp2) xf86strspn(ccp1,ccp2) +#undef strstr +#define strstr(ccp1,ccp2) xf86strstr(ccp1,ccp2) +#undef srttod +#define strtod(ccp,cpp) xf86strtod(ccp,cpp) +#undef strtok +#define strtok(cp,ccp) xf86strtok(cp,ccp) +#undef strtol +#define strtol(ccp,cpp,i) xf86strtol(ccp,cpp,i) +#undef strtoul +#define strtoul(ccp,cpp,i) xf86strtoul(ccp,cpp,i) +#undef tan +#define tan(d) xf86tan(d) +#undef tmpfile +#define tmpfile() xf86tmpfile() +#undef tolower +#define tolower(i) xf86tolower(i) +#undef toupper +#define toupper(i) xf86toupper(i) +#undef ungetc +#define ungetc(i,FP) xf86ungetc(i,FP) +#undef vfprinf +#define vfprintf(p,f,a) xf86vfprintf(p,f,a) +#undef vsnprintf +#define vsnprintf(s,n,f,a) xf86vsnprintf(s,n,f,a) +#undef vsprintf +#define vsprintf(s,f,a) xf86vsprintf(s,f,a) +/* XXX Disable assert as if NDEBUG was defined */ +/* Some X headers defined this away too */ +#undef assert +#define assert(a) ((void)0) +#undef HUGE_VAL +#define HUGE_VAL xf86HUGE_VAL + +#undef hypot +#define hypot(x,y) xf86hypot(x,y) + +#undef qsort +#define qsort(b, n, s, f) xf86qsort(b, n, s, f) + +/* non-ANSI C functions */ +#undef opendir +#define opendir(cp) xf86opendir(cp) +#undef closedir +#define closedir(DP) xf86closedir(DP) +#undef readdir +#define readdir(DP) xf86readdir(DP) +#undef rewinddir +#define rewinddir(DP) xf86rewinddir(DP) +#undef bcopy +#define bcopy(vp,cvp,I) xf86memmove(cvp,vp,I) +#undef ffs +#define ffs(i) xf86ffs(i) +#undef strdup +#define strdup(ccp) xf86strdup(ccp) +#undef bzero +#define bzero(vp,ui) xf86bzero(vp,ui) +#undef execl +#define execl xf86execl +#undef chmod +#define chmod(a,b) xf86chmod(a,b) +#undef chown +#define chown(a,b,c) xf86chown(a,b,c) +#undef geteuid +#define geteuid xf86geteuid +#undef getegid +#define getegid xf86getegid +#undef getpid +#define getpid xf86getpid +#undef mknod +#define mknod(a,b,c) xf86mknod(a,b,c) +#undef sleep +#define sleep(a) xf86sleep(a) +#undef mkdir +#define mkdir(a,b) xf86mkdir(a,b) +#undef getpagesize +#define getpagesize xf86getpagesize +#undef shmget +#define shmget(a,b,c) xf86shmget(a,b,c) +#undef shmat +#define shmat(a,b,c) xf86shmat(a,b,c) +#undef shmdt +#define shmdt(a) xf86shmdt(a) +#undef shmctl +#define shmctl(a,b,c) xf86shmctl(a,b,c) + +#undef S_ISUID +#define S_ISUID XF86_S_ISUID +#undef S_ISGID +#define S_ISGID XF86_S_ISGID +#undef S_ISVTX +#define S_ISVTX XF86_S_ISVTX +#undef S_IRUSR +#define S_IRUSR XF86_S_IRUSR +#undef S_IWUSR +#define S_IWUSR XF86_S_IWUSR +#undef S_IXUSR +#define S_IXUSR XF86_S_IXUSR +#undef S_IRGRP +#define S_IRGRP XF86_S_IRGRP +#undef S_IWGRP +#define S_IWGRP XF86_S_IWGRP +#undef S_IXGRP +#define S_IXGRP XF86_S_IXGRP +#undef S_IROTH +#define S_IROTH XF86_S_IROTH +#undef S_IWOTH +#define S_IWOTH XF86_S_IWOTH +#undef S_IXOTH +#define S_IXOTH XF86_S_IXOTH +#undef S_IFREG +#define S_IFREG XF86_S_IFREG +#undef S_IFCHR +#define S_IFCHR XF86_S_IFCHR +#undef S_IFBLK +#define S_IFBLK XF86_S_IFBLK +#undef S_IFIFO +#define S_IFIFO XF86_S_IFIFO + +/* some types */ +#undef FILE +#define FILE XF86FILE +#undef fpos_t +#define fpos_t XF86fpos_t +#undef DIR +#define DIR XF86DIR +#undef DIRENT +#define DIRENT XF86DIRENT +#undef size_t +#define size_t xf86size_t +#undef ssize_t +#define ssize_t xf86ssize_t +#undef dev_t +#define dev_t xf86dev_t +#undef mode_t +#define mode_t xf86mode_t +#undef uid_t +#define uid_t xf86uid_t +#undef gid_t +#define gid_t xf86gid_t +#undef stat_t +#define stat_t struct xf86stat + +#undef ulong +#define ulong unsigned long + +/* + * There should be no need to #undef any of these. If they are already + * defined it is because some illegal header has been included. + */ + +/* some vars */ +#undef stdin +#define stdin xf86stdin +#undef stdout +#define stdout xf86stdout +#undef stderr +#define stderr xf86stderr + +#undef SEEK_SET +#define SEEK_SET XF86_SEEK_SET +#undef SEEK_CUR +#define SEEK_CUR XF86_SEEK_CUR +#undef SEEK_END +#define SEEK_END XF86_SEEK_END + +/* + * XXX Basic I/O functions BAD,BAD,BAD! + */ +#define open xf86open +#define close(a) xf86close(a) +#define lseek(a,b,c) xf86lseek(a,b,c) +#if !defined(__DragonFly__) +#define ioctl(a,b,c) xf86ioctl(a,b,c) +#endif +#define read(a,b,c) xf86read(a,b,c) +#define write(a,b,c) xf86write(a,b,c) +#define mmap(a,b,c,d,e,f) xf86mmap(a,b,c,d,e,f) +#define munmap(a,b) xf86munmap(a,b) +#define stat(a,b) xf86stat(a,b) +#define fstat(a,b) xf86fstat(a,b) +#define access(a,b) xf86access(a,b) +#undef O_RDONLY +#define O_RDONLY XF86_O_RDONLY +#undef O_WRONLY +#define O_WRONLY XF86_O_WRONLY +#undef O_RDWR +#define O_RDWR XF86_O_RDWR +#undef O_CREAT +#define O_CREAT XF86_O_CREAT +#undef PROT_EXEC +#define PROT_EXEC XF86_PROT_EXEC +#undef PROT_READ +#define PROT_READ XF86_PROT_READ +#undef PROT_WRITE +#define PROT_WRITE XF86_PROT_WRITE +#undef PROT_NONE +#define PROT_NONE XF86_PROT_NONE +#undef MAP_FIXED +#define MAP_FIXED XF86_MAP_FIXED +#undef MAP_SHARED +#define MAP_SHARED XF86_MAP_SHARED +#undef MAP_PRIVATE +#define MAP_PRIVATE XF86_MAP_PRIVATE +#undef MAP_FAILED +#define MAP_FAILED XF86_MAP_FAILED +#undef R_OK +#define R_OK XF86_R_OK +#undef W_OK +#define W_OK XF86_W_OK +#undef X_OK +#define X_OK XF86_X_OK +#undef F_OK +#define F_OK XF86_F_OK +#undef errno +#define errno xf86errno +#undef putchar +#define putchar(i) xf86fputc(i, xf86stdout) +#undef puts +#define puts(s) xf86fputs(s, xf86stdout) + +#undef EACCES +#define EACCES xf86_EACCES +#undef EAGAIN +#define EAGAIN xf86_EAGAIN +#undef EBADF +#define EBADF xf86_EBADF +#undef EEXIST +#define EEXIST xf86_EEXIST +#undef EFAULT +#define EFAULT xf86_EFAULT +#undef EINTR +#define EINTR xf86_EINTR +#undef EINVAL +#define EINVAL xf86_EINVAL +#undef EISDIR +#define EISDIR xf86_EISDIR +#undef ELOOP +#define ELOOP xf86_ELOOP +#undef EMFILE +#define EMFILE xf86_EMFILE +#undef ENAMETOOLONG +#define ENAMETOOLONG xf86_ENAMETOOLONG +#undef ENFILE +#define ENFILE xf86_ENFILE +#undef ENOENT +#define ENOENT xf86_ENOENT +#undef ENOMEM +#define ENOMEM xf86_ENOMEM +#undef ENOSPC +#define ENOSPC xf86_ENOSPC +#undef ENOTDIR +#define ENOTDIR xf86_ENOTDIR +#undef EPIPE +#define EPIPE xf86_EPIPE +#undef EROFS +#define EROFS xf86_EROFS +#undef ETXTBSY +#define ETXTBSY xf86_ETXTBSY +#undef ENOTTY +#define ENOTTY xf86_ENOTTY +#undef ENOSYS +#define ENOSYS xf86_ENOSYS +#undef EBUSY +#define EBUSY xf86_EBUSY +#undef ENODEV +#define ENODEV xf86_ENODEV +#undef EIO +#define EIO xf86_EIO + +/* IPC stuff */ +#undef SHM_RDONLY +#define SHM_RDONLY XF86SHM_RDONLY +#undef SHM_RND +#define SHM_RND XF86SHM_RND +#undef SHM_REMAP +#define SHM_REMAP XF86SHM_REMAP +#undef IPC_RMID +#define IPC_RMID XF86IPC_RMID +#undef IPC_CREAT +#define IPC_CREAT XF86IPC_CREAT +#undef IPC_EXCL +#define IPC_EXCL XF86IPC_EXCL +#undef PC_NOWAIT +#define IPC_NOWAIT XF86IPC_NOWAIT +#undef SHM_R +#define SHM_R XF86SHM_R +#undef SHM_W +#define SHM_W XF86SHM_W +#undef IPC_PRIVATE +#define IPC_PRIVATE XF86IPC_PRIVATE + +/* Some ANSI macros */ +#undef FILENAME_MAX +#define FILENAME_MAX 1024 + +#if (defined(sun) && defined(__SVR4)) +# define _FILEDEFED /* Already have FILE defined, don't redefine it */ +#endif + +#endif /* XFree86LOADER && !DONT_DEFINE_WRAPPERS */ + +#if defined(XFree86LOADER) && \ + (!defined(DONT_DEFINE_WRAPPERS) || defined(DEFINE_SETJMP_WRAPPERS)) +#undef setjmp +#define setjmp(a) xf86setjmp_macro(a) +#undef longjmp +#define longjmp(a,b) xf86longjmp(a,b) +#undef jmp_buf +#define jmp_buf xf86jmp_buf +#endif + +#endif /* XF86_LIBC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86cmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86cmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86cmap.h (revision 51223) @@ -0,0 +1,76 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86cmap.h,v 1.9 2003/10/17 20:02:12 alanh Exp $ */ + +/* + * Copyright (c) 1998-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86CMAP_H +#define _XF86CMAP_H + +#include "xf86str.h" +#include "colormapst.h" + +#define CMAP_PALETTED_TRUECOLOR 0x0000001 +#define CMAP_RELOAD_ON_MODE_SWITCH 0x0000002 +#define CMAP_LOAD_EVEN_IF_OFFSCREEN 0x0000004 + +Bool xf86HandleColormaps( + ScreenPtr pScreen, + int maxCol, + int sigRGBbits, + xf86LoadPaletteProc *loadPalette, + xf86SetOverscanProc *setOverscan, + unsigned int flags +); + +int +xf86ChangeGamma( + ScreenPtr pScreen, + Gamma newGamma +); + +int +xf86ChangeGammaRamp( + ScreenPtr pScreen, + int size, + unsigned short *red, + unsigned short *green, + unsigned short *blue +); + +int xf86GetGammaRampSize(ScreenPtr pScreen); + +int +xf86GetGammaRamp( + ScreenPtr pScreen, + int size, + unsigned short *red, + unsigned short *green, + unsigned short *blue +); + +#endif /* _XF86CMAP_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86dgaext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86dgaext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86dgaext.h (revision 51223) @@ -0,0 +1,12 @@ +/* $XFree86$ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86DGAEXT_H_ +#define _XF86DGAEXT_H_ + +extern DISPATCH_PROC(ProcXF86DGADispatch); + +#endif /* _XF86DGAEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drm.h (revision 51223) @@ -0,0 +1,638 @@ +/** + * \file xf86drm.h + * OS-independent header for DRM user-level library interface. + * + * \author Rickard E. (Rik) Faith + */ + +/* + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h,v 1.26 2003/08/16 19:26:37 dawes Exp $ */ + +#ifndef _XF86DRM_H_ +#define _XF86DRM_H_ + +#include + + /* Defaults, if nothing set in xf86config */ +#define DRM_DEV_UID 0 +#define DRM_DEV_GID 0 +/* Default /dev/dri directory permissions 0755 */ +#define DRM_DEV_DIRMODE \ + (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) +#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) + +#define DRM_DIR_NAME "/dev/dri" +#define DRM_DEV_NAME "%s/card%d" +#define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */ + +#define DRM_ERR_NO_DEVICE (-1001) +#define DRM_ERR_NO_ACCESS (-1002) +#define DRM_ERR_NOT_ROOT (-1003) +#define DRM_ERR_INVALID (-1004) +#define DRM_ERR_NO_FD (-1005) + +#define DRM_AGP_NO_HANDLE 0 + +typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */ +typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */ + +/** + * Driver version information. + * + * \sa drmGetVersion() and drmSetVersion(). + */ +typedef struct _drmVersion { + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ + int name_len; /**< Length of name buffer */ + char *name; /**< Name of driver */ + int date_len; /**< Length of date buffer */ + char *date; /**< User-space buffer to hold date */ + int desc_len; /**< Length of desc buffer */ + char *desc; /**< User-space buffer to hold desc */ +} drmVersion, *drmVersionPtr; + +typedef struct _drmStats { + unsigned long count; /**< Number of data */ + struct { + unsigned long value; /**< Value from kernel */ + const char *long_format; /**< Suggested format for long_name */ + const char *long_name; /**< Long name for value */ + const char *rate_format; /**< Suggested format for rate_name */ + const char *rate_name; /**< Short name for value per second */ + int isvalue; /**< True if value (vs. counter) */ + const char *mult_names; /**< Multiplier names (e.g., "KGM") */ + int mult; /**< Multiplier value (e.g., 1024) */ + int verbose; /**< Suggest only in verbose output */ + } data[15]; +} drmStatsT; + + + /* All of these enums *MUST* match with the + kernel implementation -- so do *NOT* + change them! (The drmlib implementation + will just copy the flags instead of + translating them.) */ +typedef enum { + DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */ + DRM_REGISTERS = 1, /**< no caching, no core dump */ + DRM_SHM = 2, /**< shared, cached */ + DRM_AGP = 3, /**< AGP/GART */ + DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */ + DRM_CONSISTENT = 5 /**< PCI consistent */ +} drmMapType; + +typedef enum { + DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */ + DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */ + DRM_LOCKED = 0x0004, /**< Physical pages locked */ + DRM_KERNEL = 0x0008, /**< Kernel requires access */ + DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */ + DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */ + DRM_REMOVABLE = 0x0040 /**< Removable mapping */ +} drmMapFlags; + +/** + * \warning These values *MUST* match drm.h + */ +typedef enum { + /** \name Flags for DMA buffer dispatch */ + /*@{*/ + DRM_DMA_BLOCK = 0x01, /**< + * Block until buffer dispatched. + * + * \note the buffer may not yet have been + * processed by the hardware -- getting a + * hardware lock with the hardware quiescent + * will ensure that the buffer has been + * processed. + */ + DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ + DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + /*@}*/ + + /** \name Flags for DMA buffer request */ + /*@{*/ + DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ + /*@}*/ +} drmDMAFlags; + +typedef enum { + DRM_PAGE_ALIGN = 0x01, + DRM_AGP_BUFFER = 0x02, + DRM_SG_BUFFER = 0x04, + DRM_FB_BUFFER = 0x08 +} drmBufDescFlags; + +typedef enum { + DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ + DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ +} drmLockFlags; + +typedef enum { + DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and + never swapped. */ + DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */ +} drm_context_tFlags, *drm_context_tFlagsPtr; + +typedef struct _drmBufDesc { + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ +} drmBufDesc, *drmBufDescPtr; + +typedef struct _drmBufInfo { + int count; /**< Number of buffers described in list */ + drmBufDescPtr list; /**< List of buffer descriptions */ +} drmBufInfo, *drmBufInfoPtr; + +typedef struct _drmBuf { + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + drmAddress address; /**< Address */ +} drmBuf, *drmBufPtr; + +/** + * Buffer mapping information. + * + * Used by drmMapBufs() and drmUnmapBufs() to store information about the + * mapped buffers. + */ +typedef struct _drmBufMap { + int count; /**< Number of buffers mapped */ + drmBufPtr list; /**< Buffers */ +} drmBufMap, *drmBufMapPtr; + +typedef struct _drmLock { + volatile unsigned int lock; + char padding[60]; + /* This is big enough for most current (and future?) architectures: + DEC Alpha: 32 bytes + Intel Merced: ? + Intel P5/PPro/PII/PIII: 32 bytes + Intel StrongARM: 32 bytes + Intel i386/i486: 16 bytes + MIPS: 32 bytes (?) + Motorola 68k: 16 bytes + Motorola PowerPC: 32 bytes + Sun SPARC: 32 bytes + */ +} drmLock, *drmLockPtr; + +/** + * Indices here refer to the offset into + * list in drmBufInfo + */ +typedef struct _drmDMAReq { + drm_context_t context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int *send_list; /**< List of handles to buffers */ + int *send_sizes; /**< Lengths of data to send, in bytes */ + drmDMAFlags flags; /**< Flags */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size of buffers requested */ + int *request_list; /**< Buffer information */ + int *request_sizes; /**< Minimum acceptable sizes */ + int granted_count; /**< Number of buffers granted at this size */ +} drmDMAReq, *drmDMAReqPtr; + +typedef struct _drmRegion { + drm_handle_t handle; + unsigned int offset; + drmSize size; + drmAddress map; +} drmRegion, *drmRegionPtr; + +typedef struct _drmTextureRegion { + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; /**< Explicitly pad this out */ + unsigned int age; +} drmTextureRegion, *drmTextureRegionPtr; + + +typedef enum { + DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ +} drmVBlankSeqType; + +typedef struct _drmVBlankReq { + drmVBlankSeqType type; + unsigned int sequence; + unsigned long signal; +} drmVBlankReq, *drmVBlankReqPtr; + +typedef struct _drmVBlankReply { + drmVBlankSeqType type; + unsigned int sequence; + long tval_sec; + long tval_usec; +} drmVBlankReply, *drmVBlankReplyPtr; + +typedef union _drmVBlank { + drmVBlankReq request; + drmVBlankReply reply; +} drmVBlank, *drmVBlankPtr; + +typedef struct _drmSetVersion { + int drm_di_major; + int drm_di_minor; + int drm_dd_major; + int drm_dd_minor; +} drmSetVersion, *drmSetVersionPtr; + + +#define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) + +#define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ +#define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ + +#if defined(__GNUC__) && (__GNUC__ >= 2) +# if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) + /* Reflect changes here to drmP.h */ +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + int __dummy; /* Can't mark eax as clobbered */ \ + __asm__ __volatile__( \ + "lock ; cmpxchg %4,%1\n\t" \ + "setnz %0" \ + : "=d" (__ret), \ + "=m" (__drm_dummy_lock(lock)), \ + "=a" (__dummy) \ + : "2" (old), \ + "r" (new)); \ + } while (0) + +#elif defined(__alpha__) + +#define DRM_CAS(lock, old, new, ret) \ + do { \ + int old32; \ + int cur32; \ + __asm__ __volatile__( \ + " mb\n" \ + " zap %4, 0xF0, %0\n" \ + " ldl_l %1, %2\n" \ + " zap %1, 0xF0, %1\n" \ + " cmpeq %0, %1, %1\n" \ + " beq %1, 1f\n" \ + " bis %5, %5, %1\n" \ + " stl_c %1, %2\n" \ + "1: xor %1, 1, %1\n" \ + " stl %1, %3" \ + : "=r" (old32), \ + "=&r" (cur32), \ + "=m" (__drm_dummy_lock(lock)),\ + "=m" (ret) \ + : "r" (old), \ + "r" (new)); \ + } while(0) + +#elif defined(__sparc__) + +#define DRM_CAS(lock,old,new,__ret) \ +do { register unsigned int __old __asm("o0"); \ + register unsigned int __new __asm("o1"); \ + register volatile unsigned int *__lock __asm("o2"); \ + __old = old; \ + __new = new; \ + __lock = (volatile unsigned int *)lock; \ + __asm__ __volatile__( \ + /*"cas [%2], %3, %0"*/ \ + ".word 0xd3e29008\n\t" \ + /*"membar #StoreStore | #StoreLoad"*/ \ + ".word 0x8143e00a" \ + : "=&r" (__new) \ + : "0" (__new), \ + "r" (__lock), \ + "r" (__old) \ + : "memory"); \ + __ret = (__new != __old); \ +} while(0) + +#elif defined(__ia64__) + +#ifdef __INTEL_COMPILER +/* this currently generates bad code (missing stop bits)... */ +#include + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned long __result, __old = (old) & 0xffffffff; \ + __mf(); \ + __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ + __ret = (__result) != (__old); \ +/* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ + (old), (new)) \ + != (old)); */\ + } while (0) + +#else +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned int __result, __old = (old); \ + __asm__ __volatile__( \ + "mf\n" \ + "mov ar.ccv=%2\n" \ + ";;\n" \ + "cmpxchg4.acq %0=%1,%3,ar.ccv" \ + : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ + : "r" ((unsigned long)__old), "r" (new) \ + : "memory"); \ + __ret = (__result) != (__old); \ + } while (0) + +#endif + +#elif defined(__powerpc__) + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + __asm__ __volatile__( \ + "sync;" \ + "0: lwarx %0,0,%1;" \ + " xor. %0,%3,%0;" \ + " bne 1f;" \ + " stwcx. %2,0,%1;" \ + " bne- 0b;" \ + "1: " \ + "sync;" \ + : "=&r"(__ret) \ + : "r"(lock), "r"(new), "r"(old) \ + : "cr0", "memory"); \ + } while (0) + +#endif /* architecture */ +#endif /* __GNUC__ >= 2 */ + +#ifndef DRM_CAS +#define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ +#endif + +#if defined(__alpha__) || defined(__powerpc__) +#define DRM_CAS_RESULT(_result) int _result +#else +#define DRM_CAS_RESULT(_result) char _result +#endif + +#define DRM_LIGHT_LOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + } while(0) + + /* This one counts fast locks -- for + benchmarking only. */ +#define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + else ++count; \ + } while(0) + +#define DRM_LOCK(fd,lock,context,flags) \ + do { \ + if (flags) drmGetLock(fd,context,flags); \ + else DRM_LIGHT_LOCK(fd,lock,context); \ + } while(0) + +#define DRM_UNLOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ + if (__ret) drmUnlock(fd,context); \ + } while(0) + + /* Simple spin locks */ +#define DRM_SPINLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + do { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) while ((spin)->lock); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_TAKE(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + int cur; \ + do { \ + cur = (*spin).lock; \ + DRM_CAS(spin,cur,val,__ret); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ + do { \ + int __i; \ + __ret = 1; \ + for (__i = 0; __ret && __i < count; __i++) { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) for (;__i < count && (spin)->lock; __i++); \ + } \ + } while(0) + +#define DRM_SPINUNLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + if ((*spin).lock == val) { /* else server stole lock */ \ + do { \ + DRM_CAS(spin,val,0,__ret); \ + } while (__ret); \ + } \ + } while(0) + +/* General user-level programmer's API: unprivileged */ +extern int drmAvailable(void); +extern int drmOpen(const char *name, const char *busid); +extern int drmClose(int fd); +extern drmVersionPtr drmGetVersion(int fd); +extern drmVersionPtr drmGetLibVersion(int fd); +extern void drmFreeVersion(drmVersionPtr); +extern int drmGetMagic(int fd, drm_magic_t * magic); +extern char *drmGetBusid(int fd); +extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, + int funcnum); +extern int drmGetMap(int fd, int idx, drm_handle_t *offset, + drmSize *size, drmMapType *type, + drmMapFlags *flags, drm_handle_t *handle, + int *mtrr); +extern int drmGetClient(int fd, int idx, int *auth, int *pid, + int *uid, unsigned long *magic, + unsigned long *iocs); +extern int drmGetStats(int fd, drmStatsT *stats); +extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); +extern int drmCommandNone(int fd, unsigned long drmCommandIndex); +extern int drmCommandRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); + +/* General user-level programmer's API: X server (root) only */ +extern void drmFreeBusid(const char *busid); +extern int drmSetBusid(int fd, const char *busid); +extern int drmAuthMagic(int fd, drm_magic_t magic); +extern int drmAddMap(int fd, + drm_handle_t offset, + drmSize size, + drmMapType type, + drmMapFlags flags, + drm_handle_t * handle); +extern int drmRmMap(int fd, drm_handle_t handle); +extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t handle); + +extern int drmAddBufs(int fd, int count, int size, + drmBufDescFlags flags, + int agp_offset); +extern int drmMarkBufs(int fd, double low, double high); +extern int drmCreateContext(int fd, drm_context_t * handle); +extern int drmSetContextFlags(int fd, drm_context_t context, + drm_context_tFlags flags); +extern int drmGetContextFlags(int fd, drm_context_t context, + drm_context_tFlagsPtr flags); +extern int drmAddContextTag(int fd, drm_context_t context, void *tag); +extern int drmDelContextTag(int fd, drm_context_t context); +extern void *drmGetContextTag(int fd, drm_context_t context); +extern drm_context_t * drmGetReservedContextList(int fd, int *count); +extern void drmFreeReservedContextList(drm_context_t *); +extern int drmSwitchToContext(int fd, drm_context_t context); +extern int drmDestroyContext(int fd, drm_context_t handle); +extern int drmCreateDrawable(int fd, drm_drawable_t * handle); +extern int drmDestroyDrawable(int fd, drm_drawable_t handle); +extern int drmCtlInstHandler(int fd, int irq); +extern int drmCtlUninstHandler(int fd); +extern int drmInstallSIGIOHandler(int fd, + void (*f)(int fd, + void *oldctx, + void *newctx)); +extern int drmRemoveSIGIOHandler(int fd); + +/* General user-level programmer's API: authenticated client and/or X */ +extern int drmMap(int fd, + drm_handle_t handle, + drmSize size, + drmAddressPtr address); +extern int drmUnmap(drmAddress address, drmSize size); +extern drmBufInfoPtr drmGetBufInfo(int fd); +extern drmBufMapPtr drmMapBufs(int fd); +extern int drmUnmapBufs(drmBufMapPtr bufs); +extern int drmDMA(int fd, drmDMAReqPtr request); +extern int drmFreeBufs(int fd, int count, int *list); +extern int drmGetLock(int fd, + drm_context_t context, + drmLockFlags flags); +extern int drmUnlock(int fd, drm_context_t context); +extern int drmFinish(int fd, int context, drmLockFlags flags); +extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t * handle); + +/* AGP/GART support: X server (root) only */ +extern int drmAgpAcquire(int fd); +extern int drmAgpRelease(int fd); +extern int drmAgpEnable(int fd, unsigned long mode); +extern int drmAgpAlloc(int fd, unsigned long size, + unsigned long type, unsigned long *address, + drm_handle_t *handle); +extern int drmAgpFree(int fd, drm_handle_t handle); +extern int drmAgpBind(int fd, drm_handle_t handle, + unsigned long offset); +extern int drmAgpUnbind(int fd, drm_handle_t handle); + +/* AGP/GART info: authenticated client and/or X */ +extern int drmAgpVersionMajor(int fd); +extern int drmAgpVersionMinor(int fd); +extern unsigned long drmAgpGetMode(int fd); +extern unsigned long drmAgpBase(int fd); /* Physical location */ +extern unsigned long drmAgpSize(int fd); /* Bytes */ +extern unsigned long drmAgpMemoryUsed(int fd); +extern unsigned long drmAgpMemoryAvail(int fd); +extern unsigned int drmAgpVendorId(int fd); +extern unsigned int drmAgpDeviceId(int fd); + +/* PCI scatter/gather support: X server (root) only */ +extern int drmScatterGatherAlloc(int fd, unsigned long size, + drm_handle_t *handle); +extern int drmScatterGatherFree(int fd, drm_handle_t handle); + +extern int drmWaitVBlank(int fd, drmVBlankPtr vbl); + +/* Support routines */ +extern int drmError(int err, const char *label); +extern void *drmMalloc(int size); +extern void drmFree(void *pt); + +/* Hash table routines */ +extern void *drmHashCreate(void); +extern int drmHashDestroy(void *t); +extern int drmHashLookup(void *t, unsigned long key, void **value); +extern int drmHashInsert(void *t, unsigned long key, void *value); +extern int drmHashDelete(void *t, unsigned long key); +extern int drmHashFirst(void *t, unsigned long *key, void **value); +extern int drmHashNext(void *t, unsigned long *key, void **value); + +/* PRNG routines */ +extern void *drmRandomCreate(unsigned long seed); +extern int drmRandomDestroy(void *state); +extern unsigned long drmRandom(void *state); +extern double drmRandomDouble(void *state); + +/* Skip list routines */ + +extern void *drmSLCreate(void); +extern int drmSLDestroy(void *l); +extern int drmSLLookup(void *l, unsigned long key, void **value); +extern int drmSLInsert(void *l, unsigned long key, void *value); +extern int drmSLDelete(void *l, unsigned long key); +extern int drmSLNext(void *l, unsigned long *key, void **value); +extern int drmSLFirst(void *l, unsigned long *key, void **value); +extern void drmSLDump(void *l); +extern int drmSLLookupNeighbors(void *l, unsigned long key, + unsigned long *prev_key, void **prev_value, + unsigned long *next_key, void **next_value); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drmCompat.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drmCompat.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86drmCompat.h (revision 51223) @@ -0,0 +1,259 @@ +/* xf86drmCompat.h -- OS-independent header for old device specific DRM user-level + * library interface + * + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * Kevin E. Martin + * Keith Whitwell + * + * Backwards compatability modules broken out by: + * Jens Owen + * + * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drmCompat.h,v 1.1 2002/10/30 12:52:23 alanh Exp $ + * + */ + +#ifndef _XF86DRI_COMPAT_H_ +#define _XF86DRI_COMPAT_H_ + +/* WARNING: Do not change, or add, anything to this file. It is only provided + * for binary backwards compatability with the old driver specific DRM + * extensions used before XFree86 4.3. + */ + +#ifndef __user +#define __user +#endif + +/* I810 */ + +typedef struct { + unsigned int start; + unsigned int end; + unsigned int size; + unsigned int mmio_offset; + unsigned int buffers_offset; + int sarea_off; + + unsigned int front_offset; + unsigned int back_offset; + unsigned int depth_offset; + unsigned int overlay_offset; + unsigned int overlay_physical; + unsigned int w; + unsigned int h; + unsigned int pitch; + unsigned int pitch_bits; +} drmCompatI810Init; + +extern Bool drmI810CleanupDma(int driSubFD); +extern Bool drmI810InitDma(int driSubFD, drmCompatI810Init *info ); + +/* Mga */ + +typedef struct { + unsigned long sarea_priv_offset; + int chipset; + int sgram; + unsigned int maccess; + unsigned int fb_cpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; + unsigned int texture_offset[2]; + unsigned int texture_size[2]; + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long status_offset; + unsigned long warp_offset; + unsigned long primary_offset; + unsigned long buffers_offset; +} drmCompatMGAInit; + +extern int drmMGAInitDMA( int fd, drmCompatMGAInit *info ); +extern int drmMGACleanupDMA( int fd ); +extern int drmMGAFlushDMA( int fd, drmLockFlags flags ); +extern int drmMGAEngineReset( int fd ); +extern int drmMGAFullScreen( int fd, int enable ); +extern int drmMGASwapBuffers( int fd ); +extern int drmMGAClear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int depth_mask ); +extern int drmMGAFlushVertexBuffer( int fd, int indx, int used, int discard ); +extern int drmMGAFlushIndices( int fd, int indx, + int start, int end, int discard ); +extern int drmMGATextureLoad( int fd, int indx, + unsigned int dstorg, unsigned int length ); +extern int drmMGAAgpBlit( int fd, unsigned int planemask, + unsigned int src, int src_pitch, + unsigned int dst, int dst_pitch, + int delta_sx, int delta_sy, + int delta_dx, int delta_dy, + int height, int ydir ); + +/* R128 */ + +typedef struct { + unsigned long sarea_priv_offset; + int is_pci; + int cce_mode; + int cce_secure; + int ring_size; + int usec_timeout; + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + unsigned int span_offset; + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; +} drmCompatR128Init; + +extern int drmR128InitCCE( int fd, drmCompatR128Init *info ); +extern int drmR128CleanupCCE( int fd ); +extern int drmR128StartCCE( int fd ); +extern int drmR128StopCCE( int fd ); +extern int drmR128ResetCCE( int fd ); +extern int drmR128WaitForIdleCCE( int fd ); +extern int drmR128EngineReset( int fd ); +extern int drmR128FullScreen( int fd, int enable ); +extern int drmR128SwapBuffers( int fd ); +extern int drmR128Clear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int depth_mask ); +extern int drmR128FlushVertexBuffer( int fd, int prim, int indx, + int count, int discard ); +extern int drmR128FlushIndices( int fd, int prim, int indx, + int start, int end, int discard ); +extern int drmR128TextureBlit( int fd, int indx, + int offset, int pitch, int format, + int x, int y, int width, int height ); +extern int drmR128WriteDepthSpan( int fd, int n, int x, int y, + const unsigned int depth[], + const unsigned char mask[] ); +extern int drmR128WriteDepthPixels( int fd, int n, + const int x[], const int y[], + const unsigned int depth[], + const unsigned char mask[] ); +extern int drmR128ReadDepthSpan( int fd, int n, int x, int y ); +extern int drmR128ReadDepthPixels( int fd, int n, + const int x[], const int y[] ); +extern int drmR128PolygonStipple( int fd, unsigned int *mask ); +extern int drmR128FlushIndirectBuffer( int fd, int indx, + int start, int end, int discard ); + +/* Radeon */ + +typedef struct { + unsigned long sarea_priv_offset; + int is_pci; + int cp_mode; + int agp_size; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; +} drmCompatRadeonInit; + +typedef struct { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + void *data; +} drmCompatRadeonTexImage; + +extern int drmRadeonInitCP( int fd, drmCompatRadeonInit *info ); +extern int drmRadeonCleanupCP( int fd ); +extern int drmRadeonStartCP( int fd ); +extern int drmRadeonStopCP( int fd ); +extern int drmRadeonResetCP( int fd ); +extern int drmRadeonWaitForIdleCP( int fd ); +extern int drmRadeonEngineReset( int fd ); +extern int drmRadeonFullScreen( int fd, int enable ); +extern int drmRadeonSwapBuffers( int fd ); +extern int drmRadeonClear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int stencil, + void *boxes, int nbox ); +extern int drmRadeonFlushVertexBuffer( int fd, int prim, int indx, + int count, int discard ); +extern int drmRadeonFlushIndices( int fd, int prim, int indx, + int start, int end, int discard ); +extern int drmRadeonLoadTexture( int fd, int offset, int pitch, int format, + int width, int height, + drmCompatRadeonTexImage *image ); +extern int drmRadeonPolygonStipple( int fd, unsigned int *mask ); +extern int drmRadeonFlushIndirectBuffer( int fd, int indx, + int start, int end, int discard ); + +/* SiS */ +extern Bool drmSiSAgpInit(int driSubFD, int offset, int size); + +/* I830 */ +typedef struct { + unsigned int start; + unsigned int end; + unsigned int size; + unsigned int mmio_offset; + unsigned int buffers_offset; + int sarea_off; + unsigned int front_offset; + unsigned int back_offset; + unsigned int depth_offset; + unsigned int w; + unsigned int h; + unsigned int pitch; + unsigned int pitch_bits; + unsigned int cpp; +} drmCompatI830Init; + +extern Bool drmI830CleanupDma(int driSubFD); +extern Bool drmI830InitDma(int driSubFD, drmCompatI830Init *info ); + +#endif + +/* WARNING: Do not change, or add, anything to this file. It is only provided + * for binary backwards compatability with the old driver specific DRM + * extensions used before XFree86 4.3. + */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86fbman.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86fbman.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86fbman.h (revision 51223) @@ -0,0 +1,227 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86fbman.h,v 1.14 2003/10/09 12:40:54 alanh Exp $ */ + +/* + * Copyright (c) 1998-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86FBMAN_H +#define _XF86FBMAN_H + + +#include "scrnintstr.h" +#include "regionstr.h" + + +#define FAVOR_AREA_THEN_WIDTH 0 +#define FAVOR_AREA_THEN_HEIGHT 1 +#define FAVOR_WIDTH_THEN_AREA 2 +#define FAVOR_HEIGHT_THEN_AREA 3 + +#define PRIORITY_LOW 0 +#define PRIORITY_NORMAL 1 +#define PRIORITY_EXTREME 2 + + +typedef struct _FBArea { + ScreenPtr pScreen; + BoxRec box; + int granularity; + void (*MoveAreaCallback)(struct _FBArea*, struct _FBArea*); + void (*RemoveAreaCallback)(struct _FBArea*); + DevUnion devPrivate; +} FBArea, *FBAreaPtr; + +typedef struct _FBLinear { + ScreenPtr pScreen; + int size; + int offset; + int granularity; + void (*MoveLinearCallback)(struct _FBLinear*, struct _FBLinear*); + void (*RemoveLinearCallback)(struct _FBLinear*); + DevUnion devPrivate; +} FBLinear, *FBLinearPtr; + +typedef void (*FreeBoxCallbackProcPtr)(ScreenPtr, RegionPtr, pointer); +typedef void (*MoveAreaCallbackProcPtr)(FBAreaPtr, FBAreaPtr); +typedef void (*RemoveAreaCallbackProcPtr)(FBAreaPtr); + +typedef void (*MoveLinearCallbackProcPtr)(FBLinearPtr, FBLinearPtr); +typedef void (*RemoveLinearCallbackProcPtr)(FBLinearPtr); + + +typedef struct { + FBAreaPtr (*AllocateOffscreenArea)( + ScreenPtr pScreen, + int w, int h, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData); + void (*FreeOffscreenArea)(FBAreaPtr area); + Bool (*ResizeOffscreenArea)(FBAreaPtr area, int w, int h); + Bool (*QueryLargestOffscreenArea)( + ScreenPtr pScreen, + int *width, int *height, + int granularity, + int preferences, + int priority); + Bool (*RegisterFreeBoxCallback)( + ScreenPtr pScreen, + FreeBoxCallbackProcPtr FreeBoxCallback, + pointer devPriv); +/* linear functions */ + FBLinearPtr (*AllocateOffscreenLinear)( + ScreenPtr pScreen, + int size, + int granularity, + MoveLinearCallbackProcPtr moveCB, + RemoveLinearCallbackProcPtr removeCB, + pointer privData); + void (*FreeOffscreenLinear)(FBLinearPtr area); + Bool (*ResizeOffscreenLinear)(FBLinearPtr area, int size); + Bool (*QueryLargestOffscreenLinear)( + ScreenPtr pScreen, + int *size, + int granularity, + int priority); + Bool (*PurgeOffscreenAreas) (ScreenPtr); +} FBManagerFuncs, *FBManagerFuncsPtr; + + +Bool xf86RegisterOffscreenManager( + ScreenPtr pScreen, + FBManagerFuncsPtr funcs +); + +Bool +xf86InitFBManagerRegion( + ScreenPtr pScreen, + RegionPtr ScreenRegion +); + +Bool +xf86InitFBManagerArea( + ScreenPtr pScreen, + int PixalArea, + int Verbosity +); + +Bool +xf86InitFBManager( + ScreenPtr pScreen, + BoxPtr FullBox +); + +Bool +xf86InitFBManagerLinear( + ScreenPtr pScreen, + int offset, + int size +); + +Bool +xf86FBManagerRunning( + ScreenPtr pScreen +); + +FBAreaPtr +xf86AllocateOffscreenArea ( + ScreenPtr pScreen, + int w, int h, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData +); + +FBAreaPtr +xf86AllocateLinearOffscreenArea ( + ScreenPtr pScreen, + int length, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData +); + +FBLinearPtr +xf86AllocateOffscreenLinear ( + ScreenPtr pScreen, + int length, + int granularity, + MoveLinearCallbackProcPtr moveCB, + RemoveLinearCallbackProcPtr removeCB, + pointer privData +); + +void xf86FreeOffscreenArea(FBAreaPtr area); +void xf86FreeOffscreenLinear(FBLinearPtr area); + +Bool +xf86ResizeOffscreenArea( + FBAreaPtr resize, + int w, int h +); + +Bool +xf86ResizeOffscreenLinear( + FBLinearPtr resize, + int size +); + + +Bool +xf86RegisterFreeBoxCallback( + ScreenPtr pScreen, + FreeBoxCallbackProcPtr FreeBoxCallback, + pointer devPriv +); + +Bool +xf86PurgeUnlockedOffscreenAreas( + ScreenPtr pScreen +); + + +Bool +xf86QueryLargestOffscreenArea( + ScreenPtr pScreen, + int *width, int *height, + int granularity, + int preferences, + int priority +); + +Bool +xf86QueryLargestOffscreenLinear( + ScreenPtr pScreen, + int *size, + int granularity, + int priority +); + + +#endif /* _XF86FBMAN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx.h (revision 51223) @@ -0,0 +1,43 @@ +/* $XFree86: xc/programs/Xserver/GL/include/GL/xf86glx.h,v 1.3 1999/06/14 07:31:41 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "miscstruct.h" + +#ifdef XFree86LOADER +#include "xf86_ansic.h" +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx_util.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx_util.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glx_util.h (revision 51223) @@ -0,0 +1,106 @@ +/* $XFree86: xc/programs/Xserver/GL/mesa/src/X/xf86glx_util.h,v 1.5 2000/08/10 17:40:29 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Brian Paul + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86GLX_UTIL_H_ +#define _XF86GLX_UTIL_H_ + +#ifdef __CYGWIN__ +#undef WIN32 +#undef _WIN32 +#endif + +#include +#include +#include +#include "GL/xmesa.h" + +#define XMESA_USE_PUTPIXEL_MACRO + +struct _XMesaImageRec { + int width, height; + char *data; + int bytes_per_line; /* Padded to 32 bits */ + int bits_per_pixel; +}; + +extern XMesaImage *XMesaCreateImage(int bitsPerPixel, int width, int height, + char *data); +extern void XMesaDestroyImage(XMesaImage *image); +extern unsigned long XMesaGetPixel(XMesaImage *image, int x, int y); +#ifdef XMESA_USE_PUTPIXEL_MACRO +#define XMesaPutPixel(__i,__x,__y,__p) \ +{ \ + CARD8 *__row = (CARD8 *)(__i->data + __y*__i->bytes_per_line); \ + CARD8 *__i8; \ + CARD16 *__i16; \ + CARD32 *__i32; \ + switch (__i->bits_per_pixel) { \ + case 8: \ + __i8 = (CARD8 *)__row; \ + __i8[__x] = (CARD8)__p; \ + break; \ + case 15: \ + case 16: \ + __i16 = (CARD16 *)__row; \ + __i16[__x] = (CARD16)__p; \ + break; \ + case 24: /* WARNING: architecture specific code */ \ + __i8 = (CARD8 *)__row; \ + __i8[__x*3] = (CARD8)(__p); \ + __i8[__x*3+1] = (CARD8)(__p>>8); \ + __i8[__x*3+2] = (CARD8)(__p>>16); \ + break; \ + case 32: \ + __i32 = (CARD32 *)__row; \ + __i32[__x] = (CARD32)__p; \ + break; \ + } \ +} +#else +extern void XMesaPutPixel(XMesaImage *image, int x, int y, + unsigned long pixel); +#endif + +extern void XMesaPutImageHelper(ScreenPtr display, + DrawablePtr d, GCPtr gc, + XMesaImage *image, + int src_x, int src_y, + int dest_x, int dest_y, + unsigned int width, unsigned int height); + +#endif /* _XF86GLX_UTIL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glxint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glxint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86glxint.h (revision 51223) @@ -0,0 +1,102 @@ +/* $XFree86: xc/programs/Xserver/GL/mesa/src/X/xf86glxint.h,v 1.4 2002/02/22 21:45:08 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86GLXINT_H_ +#define _XF86GLXINT_H_ + +#include +#include +#include + +typedef struct __MESA_screenRec __MESA_screen; +struct __MESA_screenRec { + int num_vis; + __GLcontextModes *modes; + XMesaVisual *xm_vis; + void **private; +}; + +typedef struct __MESA_bufferRec *__MESA_buffer; +struct __MESA_bufferRec { + XMesaBuffer xm_buf; + GLboolean (*fbresize)(__GLdrawableBuffer *buf, + GLint x, GLint y, GLuint width, GLuint height, + __GLdrawablePrivate *glPriv, GLuint bufferMask); + GLboolean (*fbswap)(__GLXdrawablePrivate *glxPriv); +}; + +extern void __MESA_setVisualConfigs(int nconfigs, __GLXvisualConfig *configs, + void **privates); +extern Bool __MESA_initVisuals(VisualPtr *visualp, DepthPtr *depthp, + int *nvisualp, int *ndepthp, int *rootDepthp, + VisualID *defaultVisp, unsigned long sizes, + int bitsPerRGB); +extern Bool __MESA_screenProbe(int screen); + +extern void __MESA_resetExtension(void); + +extern void __MESA_createBuffer(__GLXdrawablePrivate *glxPriv); +extern GLboolean __MESA_resizeBuffers(__GLdrawableBuffer *buf, + GLint x, GLint y, + GLuint width, GLuint height, + __GLdrawablePrivate *glPriv, + GLuint bufferMask); +extern GLboolean __MESA_swapBuffers(__GLXdrawablePrivate *glxPriv); +extern void __MESA_destroyBuffer(__GLdrawablePrivate *glPriv); + +extern __GLinterface *__MESA_createContext(__GLimports *imports, + __GLcontextModes *modes, + __GLinterface *shareGC); +extern GLboolean __MESA_destroyContext(__GLcontext *gc); +extern GLboolean __MESA_loseCurrent(__GLcontext *gc); +extern GLboolean __MESA_makeCurrent(__GLcontext *gc); +extern GLboolean __MESA_shareContext(__GLcontext *gc, __GLcontext *gcShare); +extern GLboolean __MESA_copyContext(__GLcontext *dst, const __GLcontext *src, + GLuint mask); +extern GLboolean __MESA_forceCurrent(__GLcontext *gc); + +extern GLboolean __MESA_notifyResize(__GLcontext *gc); +extern void __MESA_notifyDestroy(__GLcontext *gc); +extern void __MESA_notifySwapBuffers(__GLcontext *gc); +extern struct __GLdispatchStateRec *__MESA_dispatchExec(__GLcontext *gc); +extern void __MESA_beginDispatchOverride(__GLcontext *gc); +extern void __MESA_endDispatchOverride(__GLcontext *gc); + +extern GLuint __glFloorLog2(GLuint val); + +#endif /* _XF86GLXINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86i2c.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86i2c.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86i2c.h (revision 51223) @@ -0,0 +1,97 @@ +/* + * Copyright (C) 1998 Itai Nahshon, Michael Schimek + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/i2c/xf86i2c.h,v 1.10 2003/07/16 01:38:47 dawes Exp $ */ + +#ifndef _XF86I2C_H +#define _XF86I2C_H + +#include "regionstr.h" + +typedef unsigned char I2CByte; +typedef unsigned short I2CSlaveAddr; + +typedef struct _I2CBusRec *I2CBusPtr; +typedef struct _I2CDevRec *I2CDevPtr; + +/* I2C masters have to register themselves */ + +typedef struct _I2CBusRec { + char * BusName; + int scrnIndex; + + void (*I2CUDelay) (I2CBusPtr b, int usec); + + void (*I2CPutBits)(I2CBusPtr b, int scl, int sda); + void (*I2CGetBits)(I2CBusPtr b, int *scl, int *sda); + + /* Look at the generic routines to see how these functions should behave. */ + + Bool (*I2CStart) (I2CBusPtr b, int timeout); + Bool (*I2CAddress)(I2CDevPtr d, I2CSlaveAddr); + void (*I2CStop) (I2CDevPtr d); + Bool (*I2CPutByte)(I2CDevPtr d, I2CByte data); + Bool (*I2CGetByte)(I2CDevPtr d, I2CByte *data, Bool); + + DevUnion DriverPrivate; + + int HoldTime; /* 1 / bus clock frequency, 5 or 2 usec */ + + int BitTimeout; /* usec */ + int ByteTimeout; /* usec */ + int AcknTimeout; /* usec */ + int StartTimeout; /* usec */ + int RiseFallTime; /* usec */ + + I2CDevPtr FirstDev; + I2CBusPtr NextBus; + Bool (*I2CWriteRead)(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead); +} I2CBusRec; + +I2CBusPtr xf86CreateI2CBusRec(void); +void xf86DestroyI2CBusRec(I2CBusPtr pI2CBus, Bool unalloc, Bool devs_too); +Bool xf86I2CBusInit(I2CBusPtr pI2CBus); +I2CBusPtr xf86I2CFindBus(int scrnIndex, char *name); +int xf86I2CGetScreenBuses(int scrnIndex, I2CBusPtr **pppI2CBus); + + +/* I2C slave devices */ + +typedef struct _I2CDevRec { + char * DevName; + + int BitTimeout; /* usec */ + int ByteTimeout; /* usec */ + int AcknTimeout; /* usec */ + int StartTimeout; /* usec */ + + I2CSlaveAddr SlaveAddr; + I2CBusPtr pI2CBus; + I2CDevPtr NextDev; + DevUnion DriverPrivate; +} I2CDevRec; + +I2CDevPtr xf86CreateI2CDevRec(void); +void xf86DestroyI2CDevRec(I2CDevPtr pI2CDev, Bool unalloc); +Bool xf86I2CDevInit(I2CDevPtr pI2CDev); +I2CDevPtr xf86I2CFindDev(I2CBusPtr, I2CSlaveAddr); + +/* See descriptions of these functions in xf86i2c.c */ + +Bool xf86I2CProbeAddress(I2CBusPtr pI2CBus, I2CSlaveAddr); +Bool xf86I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead); +#define xf86I2CRead(d, rb, nr) xf86I2CWriteRead(d, NULL, 0, rb, nr) +Bool xf86I2CReadStatus(I2CDevPtr d, I2CByte *pbyte); +Bool xf86I2CReadByte(I2CDevPtr d, I2CByte subaddr, I2CByte *pbyte); +Bool xf86I2CReadBytes(I2CDevPtr d, I2CByte subaddr, I2CByte *pbyte, int n); +Bool xf86I2CReadWord(I2CDevPtr d, I2CByte subaddr, unsigned short *pword); +#define xf86I2CWrite(d, wb, nw) xf86I2CWriteRead(d, wb, nw, NULL, 0) +Bool xf86I2CWriteByte(I2CDevPtr d, I2CByte subaddr, I2CByte byte); +Bool xf86I2CWriteBytes(I2CDevPtr d, I2CByte subaddr, I2CByte *WriteBuffer, int nWrite); +Bool xf86I2CWriteWord(I2CDevPtr d, I2CByte subaddr, unsigned short word); +Bool xf86I2CWriteVec(I2CDevPtr d, I2CByte *vec, int nValues); + +#endif /*_XF86I2C_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86int10.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86int10.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86int10.h (revision 51223) @@ -0,0 +1,198 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86int10.h,v 1.23 2002/04/04 14:05:51 eich Exp $ */ + +/* + * XFree86 int10 module + * execute BIOS int 10h calls in x86 real mode environment + * Copyright 1999 Egbert Eich + */ + +#ifndef _XF86INT10_H +#define _XF86INT10_H + +#include +#include +#include "xf86Pci.h" + +#define SEG_ADDR(x) (((x) >> 4) & 0x00F000) +#define SEG_OFF(x) ((x) & 0x0FFFF) + +#define SET_BIOS_SCRATCH 0x1 +#define RESTORE_BIOS_SCRATCH 0x2 + +/* int10 info structure */ +typedef struct { + int entityIndex; + int scrnIndex; + pointer cpuRegs; + CARD16 BIOSseg; + CARD16 inb40time; + char * BIOSScratch; + int Flags; + pointer private; + struct _int10Mem* mem; + int num; + int ax; + int bx; + int cx; + int dx; + int si; + int di; + int es; + int bp; + int flags; + int stackseg; + PCITAG Tag; + IOADDRESS ioBase; +} xf86Int10InfoRec, *xf86Int10InfoPtr; + +typedef struct _int10Mem { + CARD8(*rb)(xf86Int10InfoPtr, int); + CARD16(*rw)(xf86Int10InfoPtr, int); + CARD32(*rl)(xf86Int10InfoPtr, int); + void(*wb)(xf86Int10InfoPtr, int, CARD8); + void(*ww)(xf86Int10InfoPtr, int, CARD16); + void(*wl)(xf86Int10InfoPtr, int, CARD32); +} int10MemRec, *int10MemPtr; + +typedef struct { + CARD8 save_msr; + CARD8 save_pos102; + CARD8 save_vse; + CARD8 save_46e8; +} legacyVGARec, *legacyVGAPtr; + +typedef struct { + BusType bus; + union { + struct { + int bus; + int dev; + int func; + } pci; + int legacy; + } location; +} xf86int10BiosLocation, *xf86int10BiosLocationPtr; + +/* OS dependent functions */ +xf86Int10InfoPtr xf86InitInt10(int entityIndex); +xf86Int10InfoPtr xf86ExtendedInitInt10(int entityIndex, int Flags); +void xf86FreeInt10(xf86Int10InfoPtr pInt); +void *xf86Int10AllocPages(xf86Int10InfoPtr pInt, int num, int *off); +void xf86Int10FreePages(xf86Int10InfoPtr pInt, void *pbase, int num); +pointer xf86int10Addr(xf86Int10InfoPtr pInt, CARD32 addr); + +/* x86 executor related functions */ +void xf86ExecX86int10(xf86Int10InfoPtr pInt); + +#ifdef _INT10_PRIVATE + +#define I_S_DEFAULT_INT_VECT 0xFF065 +#define SYS_SIZE 0x100000 +#define SYS_BIOS 0xF0000 +#if 1 +#define BIOS_SIZE 0x10000 +#else /* a bug in DGUX requires this - let's try it */ +#define BIOS_SIZE (0x10000 - 1) +#endif +#define LOW_PAGE_SIZE 0x600 +#define V_RAM 0xA0000 +#define VRAM_SIZE 0x20000 +#define V_BIOS_SIZE 0x10000 +#define V_BIOS 0xC0000 +#define BIOS_SCRATCH_OFF 0x449 +#define BIOS_SCRATCH_END 0x466 +#define BIOS_SCRATCH_LEN (BIOS_SCRATCH_END - BIOS_SCRATCH_OFF + 1) +#define HIGH_MEM V_BIOS +#define HIGH_MEM_SIZE (SYS_BIOS - HIGH_MEM) +#define SEG_ADR(type, seg, reg) type((seg << 4) + (X86_##reg)) +#define SEG_EADR(type, seg, reg) type((seg << 4) + (X86_E##reg)) + +#define X86_TF_MASK 0x00000100 +#define X86_IF_MASK 0x00000200 +#define X86_IOPL_MASK 0x00003000 +#define X86_NT_MASK 0x00004000 +#define X86_VM_MASK 0x00020000 +#define X86_AC_MASK 0x00040000 +#define X86_VIF_MASK 0x00080000 /* virtual interrupt flag */ +#define X86_VIP_MASK 0x00100000 /* virtual interrupt pending */ +#define X86_ID_MASK 0x00200000 + +#define MEM_RB(name, addr) (*name->mem->rb)(name, addr) +#define MEM_RW(name, addr) (*name->mem->rw)(name, addr) +#define MEM_RL(name, addr) (*name->mem->rl)(name, addr) +#define MEM_WB(name, addr, val) (*name->mem->wb)(name, addr, val) +#define MEM_WW(name, addr, val) (*name->mem->ww)(name, addr, val) +#define MEM_WL(name, addr, val) (*name->mem->wl)(name, addr, val) + +/* OS dependent functions */ +Bool MapCurrentInt10(xf86Int10InfoPtr pInt); +/* x86 executor related functions */ +Bool xf86Int10ExecSetup(xf86Int10InfoPtr pInt); + +/* int.c */ +extern xf86Int10InfoPtr Int10Current; +int int_handler(xf86Int10InfoPtr pInt); + +/* helper_exec.c */ +int setup_int(xf86Int10InfoPtr pInt); +void finish_int(xf86Int10InfoPtr, int sig); +CARD32 getIntVect(xf86Int10InfoPtr pInt, int num); +void pushw(xf86Int10InfoPtr pInt, CARD16 val); +int run_bios_int(int num, xf86Int10InfoPtr pInt); +void dump_code(xf86Int10InfoPtr pInt); +void dump_registers(xf86Int10InfoPtr pInt); +void stack_trace(xf86Int10InfoPtr pInt); +xf86Int10InfoPtr getInt10Rec(int entityIndex); +CARD8 bios_checksum(CARD8 *start, int size); +void LockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); +void UnlockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); +#if defined (_PC) +void xf86Int10SaveRestoreBIOSVars(xf86Int10InfoPtr pInt, Bool save); +#endif +int port_rep_inb(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_inw(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_inl(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outb(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outw(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outl(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); + +CARD8 x_inb(CARD16 port); +CARD16 x_inw(CARD16 port); +void x_outb(CARD16 port, CARD8 val); +void x_outw(CARD16 port, CARD16 val); +CARD32 x_inl(CARD16 port); +void x_outl(CARD16 port, CARD32 val); + +CARD8 Mem_rb(CARD32 addr); +CARD16 Mem_rw(CARD32 addr); +CARD32 Mem_rl(CARD32 addr); +void Mem_wb(CARD32 addr, CARD8 val); +void Mem_ww(CARD32 addr, CARD16 val); +void Mem_wl(CARD32 addr, CARD32 val); + +/* helper_mem.c */ +void setup_int_vect(xf86Int10InfoPtr pInt); +int setup_system_bios(void *base_addr); +void reset_int_vect(xf86Int10InfoPtr pInt); +void set_return_trap(xf86Int10InfoPtr pInt); +void * xf86HandleInt10Options(ScrnInfoPtr pScrn, int entityIndex); +Bool int10skip(void* options); +Bool int10_check_bios(int scrnIndex, int codeSeg, unsigned char* vbiosMem); +Bool initPrimary(void* options); +void xf86int10ParseBiosLocation(void* options, + xf86int10BiosLocationPtr bios); +#ifdef DEBUG +void dprint(unsigned long start, unsigned long size); +#endif + +/* pci.c */ +int mapPciRom(int pciEntity, unsigned char *address); + +#endif /* _INT10_PRIVATE */ +#endif /* _XF86INT10_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86miscproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86miscproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86miscproc.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86: xc/programs/Xserver/Xext/xf86miscproc.h,v 1.5 2002/11/20 04:04:58 dawes Exp $ */ + +/* Prototypes for Pointer/Keyboard functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86MISCPROC_H_ +#define _XF86MISCPROC_H_ + +typedef enum { + MISC_MSE_PROTO, + MISC_MSE_BAUDRATE, + MISC_MSE_SAMPLERATE, + MISC_MSE_RESOLUTION, + MISC_MSE_BUTTONS, + MISC_MSE_EM3BUTTONS, + MISC_MSE_EM3TIMEOUT, + MISC_MSE_CHORDMIDDLE, + MISC_MSE_FLAGS +} MiscExtMseValType; + +typedef enum { + MISC_KBD_TYPE, + MISC_KBD_RATE, + MISC_KBD_DELAY, + MISC_KBD_SERVNUMLOCK +} MiscExtKbdValType; + +typedef enum { + MISC_RET_SUCCESS, + MISC_RET_BADVAL, + MISC_RET_BADMSEPROTO, + MISC_RET_BADBAUDRATE, + MISC_RET_BADFLAGS, + MISC_RET_BADCOMBO, + MISC_RET_BADKBDTYPE, + MISC_RET_NOMODULE +} MiscExtReturn; + +typedef enum { + MISC_POINTER, + MISC_KEYBOARD +} MiscExtStructType; + +#define MISC_MSEFLAG_CLEARDTR 1 +#define MISC_MSEFLAG_CLEARRTS 2 +#define MISC_MSEFLAG_REOPEN 128 + +void XFree86MiscExtensionInit(void); + +Bool MiscExtGetMouseSettings(pointer *mouse, char **devname); +int MiscExtGetMouseValue(pointer mouse, MiscExtMseValType valtype); +Bool MiscExtSetMouseValue(pointer mouse, MiscExtMseValType valtype, int value); +Bool MiscExtGetKbdSettings(pointer *kbd); +int MiscExtGetKbdValue(pointer kbd, MiscExtKbdValType valtype); +Bool MiscExtSetKbdValue(pointer kbd, MiscExtKbdValType valtype, int value); +int MiscExtSetGrabKeysState(ClientPtr client, int enable); +pointer MiscExtCreateStruct(MiscExtStructType mse_or_kbd); +void MiscExtDestroyStruct(pointer structure, MiscExtStructType mse_or_kbd); +MiscExtReturn MiscExtApply(pointer structure, MiscExtStructType mse_or_kbd); +Bool MiscExtSetMouseDevice(pointer mouse, char* device); +Bool MiscExtGetFilePaths(const char **configfile, const char **modulepath, + const char **logfile); +int MiscExtPassMessage(int scrn, const char *msgtype, const char *msgval, + char **retstr); + +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86pciBus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86pciBus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86pciBus.h (revision 51223) @@ -0,0 +1,99 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86pciBus.h,v 3.10 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_PCI_BUS_H +#define _XF86_PCI_BUS_H + +#define PCITAG_SPECIAL pciTag(0xFF,0xFF,0xFF) + +typedef struct { + CARD32 command; + CARD32 base[6]; + CARD32 biosBase; +} pciSave, *pciSavePtr; + +typedef struct { + PCITAG tag; + CARD32 ctrl; +} pciArg; + +typedef struct { + int busnum; + int devnum; + int funcnum; + pciArg arg; + xf86AccessRec ioAccess; + xf86AccessRec io_memAccess; + xf86AccessRec memAccess; + pciSave save; + pciSave restore; + Bool ctrl; +} pciAccRec, *pciAccPtr; + +typedef union { + CARD16 control; +} pciBridgesSave, *pciBridgesSavePtr; + +typedef struct pciBusRec { + int brbus, brdev, brfunc; /* ID of the bridge to this bus */ + int primary, secondary, subordinate; + int subclass; /* bridge type */ + int interface; + resPtr preferred_io; /* I/O range */ + resPtr preferred_mem; /* non-prefetchable memory range */ + resPtr preferred_pmem; /* prefetchable memory range */ + resPtr io; /* for subtractive PCI-PCI bridges */ + resPtr mem; + resPtr pmem; + int brcontrol; /* bridge_control byte */ + struct pciBusRec *next; +} PciBusRec, *PciBusPtr; + +void xf86PciProbe(void); +void ValidatePci(void); +resList GetImplicitPciResources(int entityIndex); +void initPciState(void); +void initPciBusState(void); +void DisablePciAccess(void); +void DisablePciBusAccess(void); +void PciStateEnter(void); +void PciBusStateEnter(void); +void PciStateLeave(void); +void PciBusStateLeave(void); +resPtr ResourceBrokerInitPci(resPtr *osRes); +void pciConvertRange2Host(int entityIndex, resRange *pRange); +void isaConvertRange2Host(resRange *pRange); + +extern pciAccPtr * xf86PciAccInfo; + +#endif /* _XF86_PCI_BUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86sbusBus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86sbusBus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86sbusBus.h (revision 51223) @@ -0,0 +1,98 @@ +/* + * SBUS bus-specific declarations + * + * Copyright (C) 2000 Jakub Jelinek (jakub@redhat.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.h,v 3.4 2001/10/28 03:33:19 tsi Exp $ */ + +#ifndef _XF86_SBUSBUS_H +#define _XF86_SBUSBUS_H + +#include "xf86str.h" + +#define SBUS_DEVICE_BW2 0x0001 +#define SBUS_DEVICE_CG2 0x0002 +#define SBUS_DEVICE_CG3 0x0003 +#define SBUS_DEVICE_CG4 0x0004 +#define SBUS_DEVICE_CG6 0x0005 +#define SBUS_DEVICE_CG8 0x0006 +#define SBUS_DEVICE_CG12 0x0007 +#define SBUS_DEVICE_CG14 0x0008 +#define SBUS_DEVICE_LEO 0x0009 +#define SBUS_DEVICE_TCX 0x000a +#define SBUS_DEVICE_FFB 0x000b +#define SBUS_DEVICE_GT 0x000c +#define SBUS_DEVICE_MGX 0x000d + +typedef struct sbus_prom_node { + int node; + /* Because of misdesigned openpromio */ + int cookie[2]; +} sbusPromNode, *sbusPromNodePtr; + +typedef struct sbus_device { + int devId; + int fbNum; + int fd; + int width, height; + sbusPromNode node; + char *descr; + char *device; +} sbusDevice, *sbusDevicePtr; + +extern struct sbus_devtable { + int devId; + int fbType; + char *promName; + char *descr; +} sbusDeviceTable[]; + +void xf86SbusProbe(void); +extern sbusDevicePtr *xf86SbusInfo; + +int xf86MatchSbusInstances(const char *driverName, int sbusDevId, + GDevPtr *devList, int numDevs, DriverPtr drvp, + int **foundEntities); +sbusDevicePtr xf86GetSbusInfoForEntity(int entityIndex); +int xf86GetEntityForSbusInfo(sbusDevicePtr psdp); +void xf86SbusUseBuiltinMode(ScrnInfoPtr pScrn, sbusDevicePtr psdp); +pointer xf86MapSbusMem(sbusDevicePtr psdp, unsigned long offset, + unsigned long size); +void xf86UnmapSbusMem(sbusDevicePtr psdp, pointer addr, unsigned long size); +void xf86SbusHideOsHwCursor(sbusDevicePtr psdp); +void xf86SbusSetOsHwCursorCmap(sbusDevicePtr psdp, int bg, int fg); +Bool xf86SbusHandleColormaps(ScreenPtr pScreen, sbusDevicePtr psdp); + +extern int promRootNode; + +int promGetSibling(int node); +int promGetChild(int node); +char * promGetProperty(const char *prop, int *lenp); +int promGetBool(const char *prop); + +int sparcPromInit(void); +void sparcPromClose(void); +char * sparcPromGetProperty(sbusPromNodePtr pnode, const char *prop, int *lenp); +int sparcPromGetBool(sbusPromNodePtr pnode, const char *prop); +void sparcPromAssignNodes(void); +char * sparcPromNode2Pathname(sbusPromNodePtr pnode); +int sparcPromPathname2Node(const char *pathName); + +#endif /* _XF86_SBUSBUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86str.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86str.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86str.h (revision 51223) @@ -0,0 +1,1140 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86str.h,v 1.97 2003/10/30 17:36:56 tsi Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the public XFree86 data structures/types. + * Any data structures that video drivers need to access should go here. + */ + +#ifndef _XF86STR_H +#define _XF86STR_H + +#include "misc.h" +#include "input.h" +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "colormapst.h" +#include "xf86Module.h" +#include "xf86Opt.h" +#include "xf86Pci.h" + +/* + * memType is of the size of the addressable memory (machine size) + * usually unsigned long. + */ +typedef unsigned long memType; + +/* Video mode flags */ + +typedef enum { + V_PHSYNC = 0x0001, + V_NHSYNC = 0x0002, + V_PVSYNC = 0x0004, + V_NVSYNC = 0x0008, + V_INTERLACE = 0x0010, + V_DBLSCAN = 0x0020, + V_CSYNC = 0x0040, + V_PCSYNC = 0x0080, + V_NCSYNC = 0x0100, + V_HSKEW = 0x0200, /* hskew provided */ + V_BCAST = 0x0400, + V_PIXMUX = 0x1000, + V_DBLCLK = 0x2000, + V_CLKDIV2 = 0x4000 +} ModeFlags; + +typedef enum { + INTERLACE_HALVE_V = 0x0001 /* Halve V values for interlacing */ +} CrtcAdjustFlags; + +/* Flags passed to ChipValidMode() */ +typedef enum { + MODECHECK_INITIAL = 0, + MODECHECK_FINAL = 1 +} ModeCheckFlags; + +/* These are possible return values for xf86CheckMode() and ValidMode() */ +typedef enum { + MODE_OK = 0, /* Mode OK */ + MODE_HSYNC, /* hsync out of range */ + MODE_VSYNC, /* vsync out of range */ + MODE_H_ILLEGAL, /* mode has illegal horizontal timings */ + MODE_V_ILLEGAL, /* mode has illegal horizontal timings */ + MODE_BAD_WIDTH, /* requires an unsupported linepitch */ + MODE_NOMODE, /* no mode with a maching name */ + MODE_NO_INTERLACE, /* interlaced mode not supported */ + MODE_NO_DBLESCAN, /* doublescan mode not supported */ + MODE_NO_VSCAN, /* multiscan mode not supported */ + MODE_MEM, /* insufficient video memory */ + MODE_VIRTUAL_X, /* mode width too large for specified virtual size */ + MODE_VIRTUAL_Y, /* mode height too large for specified virtual size */ + MODE_MEM_VIRT, /* insufficient video memory given virtual size */ + MODE_NOCLOCK, /* no fixed clock available */ + MODE_CLOCK_HIGH, /* clock required is too high */ + MODE_CLOCK_LOW, /* clock required is too low */ + MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */ + MODE_BAD_HVALUE, /* horizontal timing was out of range */ + MODE_BAD_VVALUE, /* vertical timing was out of range */ + MODE_BAD_VSCAN, /* VScan value out of range */ + MODE_HSYNC_NARROW, /* horizontal sync too narrow */ + MODE_HSYNC_WIDE, /* horizontal sync too wide */ + MODE_HBLANK_NARROW, /* horizontal blanking too narrow */ + MODE_HBLANK_WIDE, /* horizontal blanking too wide */ + MODE_VSYNC_NARROW, /* vertical sync too narrow */ + MODE_VSYNC_WIDE, /* vertical sync too wide */ + MODE_VBLANK_NARROW, /* vertical blanking too narrow */ + MODE_VBLANK_WIDE, /* vertical blanking too wide */ + MODE_PANEL, /* exceeds panel dimensions */ + MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */ + MODE_ONE_WIDTH, /* only one width is supported */ + MODE_ONE_HEIGHT, /* only one height is supported */ + MODE_ONE_SIZE, /* only one resolution is supported */ + MODE_BAD = -2, /* unspecified reason */ + MODE_ERROR = -1 /* error condition */ +} ModeStatus; + +# define M_T_BUILTIN 0x01 /* built-in mode */ +# define M_T_CLOCK_C (0x02 | M_T_BUILTIN) /* built-in mode - configure clock */ +# define M_T_CRTC_C (0x04 | M_T_BUILTIN) /* built-in mode - configure CRTC */ +# define M_T_CLOCK_CRTC_C (M_T_CLOCK_C | M_T_CRTC_C) + /* built-in mode - configure CRTC and clock */ +# define M_T_DEFAULT 0x10 /* (VESA) default modes */ +# define M_T_USERDEF 0x20 /* One of the modes from the config file */ + +/* Video mode */ +typedef struct _DisplayModeRec { + struct _DisplayModeRec * prev; + struct _DisplayModeRec * next; + char * name; /* identifier for the mode */ + ModeStatus status; + int type; + + /* These are the values that the user sees/provides */ + int Clock; /* pixel clock freq (kHz) */ + int HDisplay; /* horizontal timing */ + int HSyncStart; + int HSyncEnd; + int HTotal; + int HSkew; + int VDisplay; /* vertical timing */ + int VSyncStart; + int VSyncEnd; + int VTotal; + int VScan; + int Flags; + + /* These are the values the hardware uses */ + int ClockIndex; + int SynthClock; /* Actual clock freq to + * be programmed (kHz) */ + int CrtcHDisplay; + int CrtcHBlankStart; + int CrtcHSyncStart; + int CrtcHSyncEnd; + int CrtcHBlankEnd; + int CrtcHTotal; + int CrtcHSkew; + int CrtcVDisplay; + int CrtcVBlankStart; + int CrtcVSyncStart; + int CrtcVSyncEnd; + int CrtcVBlankEnd; + int CrtcVTotal; + Bool CrtcHAdjusted; + Bool CrtcVAdjusted; + int PrivSize; + INT32 * Private; + int PrivFlags; + + float HSync, VRefresh; +} DisplayModeRec, *DisplayModePtr; + +/* The monitor description */ + +#define MAX_HSYNC 8 +#define MAX_VREFRESH 8 + +typedef struct { float hi, lo; } range; + +typedef struct { CARD32 red, green, blue; } rgb; + +typedef struct { float red, green, blue; } Gamma; + +/* The permitted gamma range is 1 / GAMMA_MAX <= g <= GAMMA_MAX */ +#define GAMMA_MAX 10.0 +#define GAMMA_MIN (1.0 / GAMMA_MAX) +#define GAMMA_ZERO (GAMMA_MIN / 100.0) + +typedef struct { + char * id; + char * vendor; + char * model; + int nHsync; + range hsync[MAX_HSYNC]; + int nVrefresh; + range vrefresh[MAX_VREFRESH]; + DisplayModePtr Modes; /* Start of the monitor's mode list */ + DisplayModePtr Last; /* End of the monitor's mode list */ + Gamma gamma; /* Gamma of the monitor */ + int widthmm; + int heightmm; + pointer options; + pointer DDC; +} MonRec, *MonPtr; + +/* the list of clock ranges */ +typedef struct x_ClockRange { + struct x_ClockRange *next; + int minClock; /* (kHz) */ + int maxClock; /* (kHz) */ + int clockIndex; /* -1 for programmable clocks */ + Bool interlaceAllowed; + Bool doubleScanAllowed; + int ClockMulFactor; + int ClockDivFactor; + int PrivFlags; +} ClockRange, *ClockRangePtr; + +/* Need to store the strategy with clockRange for VidMode extension */ +typedef struct x_ClockRanges { + struct x_ClockRanges *next; + int minClock; + int maxClock; + int clockIndex; /* -1 for programmable clocks */ + Bool interlaceAllowed; + Bool doubleScanAllowed; + int ClockMulFactor; + int ClockDivFactor; + int PrivFlags; + int strategy; +} ClockRanges, *ClockRangesPtr; + +/* + * The driverFunc. xorgDriverFuncOp specifies the action driver should + * perform. If requested option is not supported function should return + * FALSE. pointer can be used to pass arguments to the function or + * to return data to the caller. + */ +typedef struct _ScrnInfoRec *ScrnInfoPtr; + +/* do not change order */ +typedef enum { + RR_GET_INFO, + RR_SET_CONFIG, + RR_GET_MODE_MM, + GET_REQUIRED_HW_INTERFACES = 10 +} xorgDriverFuncOp; + +typedef Bool xorgDriverFuncProc (ScrnInfoPtr, xorgDriverFuncOp, + pointer); + +/* RR_GET_INFO, RR_SET_CONFIG */ +typedef struct { + int rotation; + int rate; + int width; + int height; +} xorgRRConfig; + +typedef union { + short RRRotations; + xorgRRConfig RRConfig; +} xorgRRRotation, *xorgRRRotationPtr; + +/* RR_GET_MODE_MM */ +typedef struct { + DisplayModePtr mode; + int virtX; + int virtY; + int mmWidth; + int mmHeight; +} xorgRRModeMM, *xorgRRModeMMPtr; + +/* GET_REQUIRED_HW_INTERFACES */ +#define HW_IO 1 +#define HW_MMIO 2 +#define NEED_IO_ENABLED(x) (x & HW_IO) + +typedef CARD32 xorgHWFlags; + +/* + * The driver list struct. This contains the information required for each + * driver before a ScrnInfoRec has been allocated. + */ +struct _DriverRec; + +typedef struct { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + Bool (*Probe)(struct _DriverRec *drv, int flags); + const OptionInfoRec * (*AvailableOptions)(int chipid, int bustype); + pointer module; + int refCount; +} DriverRec1; + +typedef struct _DriverRec { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + Bool (*Probe)(struct _DriverRec *drv, int flags); + const OptionInfoRec * (*AvailableOptions)(int chipid, int bustype); + pointer module; + int refCount; + xorgDriverFuncProc *driverFunc; +} DriverRec, *DriverPtr; + +/* + * AddDriver flags + */ +#define HaveDriverFuncs 1 + + +#ifdef XFree86LOADER +/* + * The optional module list struct. This allows modules exporting helping + * functions to configuration tools, the Xserver, or any other + * application/module interested in such information. + */ +typedef struct _ModuleInfoRec { + int moduleVersion; + char * moduleName; + pointer module; + int refCount; + const OptionInfoRec * (*AvailableOptions)(void *unused); + pointer unused[8]; /* leave some space for more fields */ +} ModuleInfoRec, *ModuleInfoPtr; +#endif + +/* + * These are the private bus types. New types can be added here. Types + * required for the public interface should be added to xf86str.h, with + * function prototypes added to xf86.h. + */ + +/* Tolerate prior #include */ +#if defined(linux) && defined(_INPUT_H) +#undef BUS_NONE +#undef BUS_ISA +#undef BUS_PCI +#undef BUS_SBUS +#undef BUS_last +#endif + +typedef enum { + BUS_NONE, + BUS_ISA, + BUS_PCI, + BUS_SBUS, + BUS_last /* Keep last */ +} BusType; + +typedef struct { + int bus; + int device; + int func; +} PciBusId; + +typedef struct { + unsigned int dummy; +} IsaBusId; + +typedef struct { + int fbNum; +} SbusBusId; + +typedef struct _bus { + BusType type; + union { + IsaBusId isa; + PciBusId pci; + SbusBusId sbus; + } id; +} BusRec, *BusPtr; + +#define MAXCLOCKS 128 +typedef enum { + DAC_BPP8 = 0, + DAC_BPP16, + DAC_BPP24, + DAC_BPP32, + MAXDACSPEEDS +} DacSpeedIndex; + +typedef struct { + char * identifier; + char * vendor; + char * board; + char * chipset; + char * ramdac; + char * driver; + struct _confscreenrec * myScreenSection; + Bool claimed; + int dacSpeeds[MAXDACSPEEDS]; + int numclocks; + int clock[MAXCLOCKS]; + char * clockchip; + char * busID; + Bool active; + Bool inUse; + int videoRam; + int textClockFreq; + unsigned long BiosBase; /* Base address of video BIOS */ + unsigned long MemBase; /* Frame buffer base address */ + unsigned long IOBase; + int chipID; + int chipRev; + pointer options; + int irq; + int screen; /* For multi-CRTC cards */ +} GDevRec, *GDevPtr; + +typedef int (*FindIsaDevProc)(GDevPtr dev); + +typedef struct { + char * identifier; + char * driver; + pointer commonOptions; + pointer extraOptions; +} IDevRec, *IDevPtr; + +typedef struct { + int vendor; + int chipType; + int chipRev; + int subsysVendor; + int subsysCard; + int bus; + int device; + int func; + int class; + int subclass; + int interface; + memType memBase[6]; + memType ioBase[6]; + int size[6]; + unsigned char type[6]; + memType biosBase; + int biosSize; + pointer thisCard; + Bool validSize; + Bool validate; + CARD32 listed_class; +} pciVideoRec, *pciVideoPtr; + +typedef struct { + int frameX0; + int frameY0; + int virtualX; + int virtualY; + int depth; + int fbbpp; + rgb weight; + rgb blackColour; + rgb whiteColour; + int defaultVisual; + char ** modes; + pointer options; +} DispRec, *DispPtr; + +typedef struct _confxvportrec { + char * identifier; + pointer options; +} confXvPortRec, *confXvPortPtr; + +typedef struct _confxvadaptrec { + char * identifier; + int numports; + confXvPortPtr ports; + pointer options; +} confXvAdaptorRec, *confXvAdaptorPtr; + +typedef struct _confscreenrec { + char * id; + int screennum; + int defaultdepth; + int defaultbpp; + int defaultfbbpp; + MonPtr monitor; + GDevPtr device; + int numdisplays; + DispPtr displays; + int numxvadaptors; + confXvAdaptorPtr xvadaptors; + pointer options; +} confScreenRec, *confScreenPtr; + +typedef enum { + PosObsolete = -1, + PosAbsolute = 0, + PosRightOf, + PosLeftOf, + PosAbove, + PosBelow, + PosRelative +} PositionType; + +typedef struct _screenlayoutrec { + confScreenPtr screen; + char * topname; + confScreenPtr top; + char * bottomname; + confScreenPtr bottom; + char * leftname; + confScreenPtr left; + char * rightname; + confScreenPtr right; + PositionType where; + int x; + int y; + char * refname; + confScreenPtr refscreen; +} screenLayoutRec, *screenLayoutPtr; + +typedef struct _serverlayoutrec { + char * id; + screenLayoutPtr screens; + GDevPtr inactives; + IDevPtr inputs; + pointer options; +} serverLayoutRec, *serverLayoutPtr; + +typedef struct _confdribufferrec { + int count; + int size; + enum { + XF86DRI_WC_HINT = 0x0001 /* Placeholder: not implemented */ + } flags; +} confDRIBufferRec, *confDRIBufferPtr; + +typedef struct _confdrirec { + int group; + int mode; + int bufs_count; + confDRIBufferRec *bufs; +} confDRIRec, *confDRIPtr; + +/* These values should be adjusted when new fields are added to ScrnInfoRec */ +#define NUM_RESERVED_INTS 16 +#define NUM_RESERVED_POINTERS 15 +#define NUM_RESERVED_FUNCS 11 + +typedef pointer (*funcPointer)(void); + +/* flags for depth 24 pixmap options */ +typedef enum { + Pix24DontCare = 0, + Pix24Use24, + Pix24Use32 +} Pix24Flags; + +/* Power management events: so far we only support APM */ + +typedef enum { + XF86_APM_UNKNOWN = -1, + XF86_APM_SYS_STANDBY, + XF86_APM_SYS_SUSPEND, + XF86_APM_CRITICAL_SUSPEND, + XF86_APM_USER_STANDBY, + XF86_APM_USER_SUSPEND, + XF86_APM_STANDBY_RESUME, + XF86_APM_NORMAL_RESUME, + XF86_APM_CRITICAL_RESUME, + XF86_APM_LOW_BATTERY, + XF86_APM_POWER_STATUS_CHANGE, + XF86_APM_UPDATE_TIME, + XF86_APM_CAPABILITY_CHANGED, + XF86_APM_STANDBY_FAILED, + XF86_APM_SUSPEND_FAILED +} pmEvent; + +typedef enum { + PM_WAIT, + PM_CONTINUE, + PM_FAILED, + PM_NONE +} pmWait; + +/* + * The IO access enabler struct. This contains the address for + * the IOEnable/IODisable funcs for their specific bus along + * with a pointer to data needed by them + */ +typedef struct _AccessRec { + void (*AccessDisable)(void *arg); + void (*AccessEnable)(void *arg); + void *arg; +} xf86AccessRec, *xf86AccessPtr; + +typedef struct { + xf86AccessPtr mem; + xf86AccessPtr io; + xf86AccessPtr io_mem; +} xf86SetAccessFuncRec, *xf86SetAccessFuncPtr; + +/* bus-access-related types */ +typedef enum { + NONE, + IO, + MEM_IO, + MEM +} resType; + +typedef struct _EntityAccessRec { + xf86AccessPtr fallback; + xf86AccessPtr pAccess; + resType rt; + pointer busAcc; + struct _EntityAccessRec *next; +} EntityAccessRec, *EntityAccessPtr; + +typedef struct _CurrAccRec { + EntityAccessPtr pMemAccess; + EntityAccessPtr pIoAccess; +} xf86CurrentAccessRec, *xf86CurrentAccessPtr; + +/* new RAC */ + +/* Resource Type values */ +#define ResNone ((unsigned long)(-1)) + +#define ResMem 0x0001 +#define ResIo 0x0002 +#define ResIrq 0x0003 +#define ResDma 0x0004 +#define ResPciCfg 0x000e /* PCI Configuration space */ +#define ResPhysMask 0x000F + +#define ResExclusive 0x0010 +#define ResShared 0x0020 +#define ResAny 0x0040 +#define ResAccMask 0x0070 +#define ResUnused 0x0080 + +#define ResUnusedOpr 0x0100 +#define ResDisableOpr 0x0200 +#define ResOprMask 0x0300 + +#define ResBlock 0x0400 +#define ResSparse 0x0800 +#define ResExtMask 0x0C00 + +#define ResEstimated 0x001000 +#define ResInit 0x002000 +#define ResBios 0x004000 +#define ResMiscMask 0x00F000 + +#define ResBus 0x010000 +#define ResOverlap 0x020000 + +#if defined(__alpha__) && defined(linux) +# define ResDomain 0x1ff000000ul +#else +# define ResDomain 0xff000000ul +#endif +#define ResTypeMask (ResPhysMask | ResDomain) /* For conflict check */ + +#define ResEnd ResNone + +#define ResExcMemBlock (ResMem | ResExclusive | ResBlock) +#define ResExcIoBlock (ResIo | ResExclusive | ResBlock) +#define ResShrMemBlock (ResMem | ResShared | ResBlock) +#define ResShrIoBlock (ResIo | ResShared | ResBlock) +#define ResExcUusdMemBlock (ResMem | ResExclusive | ResUnused | ResBlock) +#define ResExcUusdIoBlock (ResIo | ResExclusive | ResUnused | ResBlock) +#define ResShrUusdMemBlock (ResMem | ResShared | ResUnused | ResBlock) +#define ResShrUusdIoBlock (ResIo | ResShared | ResUnused | ResBlock) +#define ResExcUusdMemSparse (ResMem | ResExclusive | ResUnused | ResSparse) +#define ResExcUusdIoSparse (ResIo | ResExclusive | ResUnused | ResSparse) +#define ResShrUusdMemSparse (ResMem | ResShared | ResUnused | ResSparse) +#define ResShrUusdIoSparse (ResIo | ResShared | ResUnused | ResSparse) + +#define ResExcMemSparse (ResMem | ResExclusive | ResSparse) +#define ResExcIoSparse (ResIo | ResExclusive | ResSparse) +#define ResShrMemSparse (ResMem | ResShared | ResSparse) +#define ResShrIoSparse (ResIo | ResShared | ResSparse) +#define ResUusdMemSparse (ResMem | ResUnused | ResSparse) +#define ResUusdIoSparse (ResIo | ResUnused | ResSparse) + +#define ResIsMem(r) (((r)->type & ResPhysMask) == ResMem) +#define ResIsIo(r) (((r)->type & ResPhysMask) == ResIo) +#define ResIsExclusive(r) (((r)->type & ResAccMask) == ResExclusive) +#define ResIsShared(r) (((r)->type & ResAccMask) == ResShared) +#define ResIsUnused(r) (((r)->type & ResAccMask) == ResUnused) +#define ResIsBlock(r) (((r)->type & ResExtMask) == ResBlock) +#define ResIsSparse(r) (((r)->type & ResExtMask) == ResSparse) +#define ResIsEstimated(r) (((r)->type & ResMiscMask) == ResEstimated) +#define ResCanOverlap(r) (ResIsEstimated(r) || ((r)->type & ResOverlap)) + +typedef struct { + unsigned long type; /* shared, exclusive, unused etc. */ + memType a; + memType b; +} resRange, *resList; + +#define RANGE_TYPE(type, domain) \ + (((unsigned long)(domain) << 24) | ((type) & ~ResBus)) +#define RANGE(r,u,v,t) {\ + (r).a = (u);\ + (r).b = (v);\ + (r).type = (t);\ + } + +#define rBase a +#define rMask b +#define rBegin a +#define rEnd b + +/* resource record */ +typedef struct _resRec *resPtr; +typedef struct _resRec { + resRange val; + int entityIndex; /* who owns the resource */ + resPtr next; +} resRec; + +#define sparse_base val.rBase +#define sparse_mask val.rMask +#define block_begin val.rBegin +#define block_end val.rEnd +#define res_type val.type + +typedef struct { + int numChipset; + resRange *resList; +} IsaChipsets; + +typedef struct { + int numChipset; + int PCIid; + resRange *resList; +} PciChipsets; + +/* Entity properties */ +typedef void (*EntityProc)(int entityIndex,pointer private); + +typedef struct _entityInfo { + int index; + BusRec location; + int chipset; + Bool active; + resPtr resources; + GDevPtr device; + DriverPtr driver; +} EntityInfoRec, *EntityInfoPtr; + +/* server states */ + +typedef enum { + SETUP, + OPERATING +} xf86State; + +typedef enum { + NOTIFY_SETUP_TRANSITION, + NOTIFY_SETUP, + NOTIFY_OPERATING, + NOTIFY_OPERATING_TRANSITION, + NOTIFY_ENABLE, + NOTIFY_ENTER, + NOTIFY_LEAVE +} xf86NotifyState; + +typedef void (*xf86StateChangeNotificationCallbackFunc)(xf86NotifyState state,pointer); + +/* DGA */ + +typedef struct { + int num; /* A unique identifier for the mode (num > 0) */ + DisplayModePtr mode; + int flags; /* DGA_CONCURRENT_ACCESS, etc... */ + int imageWidth; /* linear accessible portion (pixels) */ + int imageHeight; + int pixmapWidth; /* Xlib accessible portion (pixels) */ + int pixmapHeight; /* both fields ignored if no concurrent access */ + int bytesPerScanline; + int byteOrder; /* MSBFirst, LSBFirst */ + int depth; + int bitsPerPixel; + unsigned long red_mask; + unsigned long green_mask; + unsigned long blue_mask; + short visualClass; + int viewportWidth; + int viewportHeight; + int xViewportStep; /* viewport position granularity */ + int yViewportStep; + int maxViewportX; /* max viewport origin */ + int maxViewportY; + int viewportFlags; /* types of page flipping possible */ + int offset; /* offset into physical memory */ + unsigned char *address; /* server's mapped framebuffer */ + int reserved1; + int reserved2; +} DGAModeRec, *DGAModePtr; + +typedef struct { + DGAModePtr mode; + PixmapPtr pPix; +} DGADeviceRec, *DGADevicePtr; + +/* + * Flags for driver Probe() functions. + */ +#define PROBE_DEFAULT 0x00 +#define PROBE_DETECT 0x01 +#define PROBE_TRYHARD 0x02 + +/* + * Driver entry point types + */ + +typedef Bool xf86ProbeProc (DriverPtr, int); +typedef Bool xf86PreInitProc (ScrnInfoPtr, int); +typedef Bool xf86ScreenInitProc (int, ScreenPtr, int, char**); +typedef Bool xf86SwitchModeProc (int, DisplayModePtr, int); +typedef void xf86AdjustFrameProc (int, int, int, int); +typedef Bool xf86EnterVTProc (int, int); +typedef void xf86LeaveVTProc (int, int); +typedef void xf86FreeScreenProc (int, int); +typedef ModeStatus xf86ValidModeProc (int, DisplayModePtr, Bool, int); +typedef void xf86EnableDisableFBAccessProc(int, Bool); +typedef int xf86SetDGAModeProc (int, int, DGADevicePtr); +typedef int xf86ChangeGammaProc (int, Gamma); +typedef void xf86PointerMovedProc (int, int, int); +typedef Bool xf86PMEventProc (int, pmEvent, Bool); +typedef int xf86HandleMessageProc (int, const char*, const char*, char**); +typedef void xf86DPMSSetProc (ScrnInfoPtr, int, int); +typedef void xf86LoadPaletteProc (ScrnInfoPtr, int, int *, LOCO *, VisualPtr); +typedef void xf86SetOverscanProc (ScrnInfoPtr, int); + + +/* + * ScrnInfoRec + * + * There is one of these for each screen, and it holds all the screen-specific + * information. + * + * Note: the size and layout must be kept the same across versions. New + * fields are to be added in place of the "reserved*" fields. No fields + * are to be dependent on compile-time defines. + */ + + +typedef struct _ScrnInfoRec { + int driverVersion; + char * driverName; /* canonical name used in */ + /* the config file */ + ScreenPtr pScreen; /* Pointer to the ScreenRec */ + int scrnIndex; /* Number of this screen */ + Bool configured; /* Is this screen valid */ + int origIndex; /* initial number assigned to + * this screen before + * finalising the number of + * available screens */ + + /* Display-wide screenInfo values needed by this screen */ + int imageByteOrder; + int bitmapScanlineUnit; + int bitmapScanlinePad; + int bitmapBitOrder; + int numFormats; + PixmapFormatRec formats[MAXFORMATS]; + PixmapFormatRec fbFormat; + + int bitsPerPixel; /* fb bpp */ + Pix24Flags pixmap24; /* pixmap pref for depth 24 */ + int depth; /* depth of default visual */ + MessageType depthFrom; /* set from config? */ + MessageType bitsPerPixelFrom; /* set from config? */ + rgb weight; /* r/g/b weights */ + rgb mask; /* rgb masks */ + rgb offset; /* rgb offsets */ + int rgbBits; /* Number of bits in r/g/b */ + Gamma gamma; /* Gamma of the monitor */ + int defaultVisual; /* default visual class */ + int maxHValue; /* max horizontal timing */ + int maxVValue; /* max vertical timing value */ + int virtualX; /* Virtual width */ + int virtualY; /* Virtual height */ + int xInc; /* Horizontal timing increment */ + MessageType virtualFrom; /* set from config? */ + int displayWidth; /* memory pitch */ + int frameX0; /* viewport position */ + int frameY0; + int frameX1; + int frameY1; + int zoomLocked; /* Disallow mode changes */ + DisplayModePtr modePool; /* list of compatible modes */ + DisplayModePtr modes; /* list of actual modes */ + DisplayModePtr currentMode; /* current mode + * This was previously + * overloaded with the modes + * field, which is a pointer + * into a circular list */ + confScreenPtr confScreen; /* Screen config info */ + MonPtr monitor; /* Monitor information */ + DispPtr display; /* Display information */ + int * entityList; /* List of device entities */ + int numEntities; + int widthmm; /* physical display dimensions + * in mm */ + int heightmm; + int xDpi; /* width DPI */ + int yDpi; /* height DPI */ + char * name; /* Name to prefix messages */ + pointer driverPrivate; /* Driver private area */ + DevUnion * privates; /* Other privates can hook in + * here */ + DriverPtr drv; /* xf86DriverList[] entry */ + pointer module; /* Pointer to module head */ + int colorKey; + int overlayFlags; + + /* Some of these may be moved out of here into the driver private area */ + + char * chipset; /* chipset name */ + char * ramdac; /* ramdac name */ + char * clockchip; /* clock name */ + Bool progClock; /* clock is programmable */ + int numClocks; /* number of clocks */ + int clock[MAXCLOCKS]; /* list of clock frequencies */ + int videoRam; /* amount of video ram (kb) */ + unsigned long biosBase; /* Base address of video BIOS */ + unsigned long memPhysBase; /* Physical address of FB */ + unsigned long fbOffset; /* Offset of FB in the above */ + IOADDRESS domainIOBase; /* Domain I/O base address */ + int memClk; /* memory clock */ + int textClockFreq; /* clock of text mode */ + Bool flipPixels; /* swap default black/white */ + pointer options; + + int chipID; + int chipRev; + int racMemFlags; + int racIoFlags; + pointer access; + xf86CurrentAccessPtr CurrentAccess; + resType resourceType; + pointer busAccess; + + /* Allow screens to be enabled/disabled individually */ + Bool vtSema; + DevUnion pixmapPrivate; /* saved devPrivate from pixmap */ + + /* hw cursor moves at SIGIO time */ + Bool silkenMouse; + + /* Storage for clockRanges and adjustFlags for use with the VidMode ext */ + ClockRangesPtr clockRanges; + int adjustFlags; + + /* + * These can be used when the minor ABI version is incremented. + * The NUM_* parameters must be reduced appropriately to keep the + * structure size and alignment unchanged. + */ + int reservedInt[NUM_RESERVED_INTS]; + + int * entityInstanceList; + pointer reservedPtr[NUM_RESERVED_POINTERS]; + + /* + * Driver entry points. + * + */ + + xf86ProbeProc *Probe; + xf86PreInitProc *PreInit; + xf86ScreenInitProc *ScreenInit; + xf86SwitchModeProc *SwitchMode; + xf86AdjustFrameProc *AdjustFrame; + xf86EnterVTProc *EnterVT; + xf86LeaveVTProc *LeaveVT; + xf86FreeScreenProc *FreeScreen; + xf86ValidModeProc *ValidMode; + xf86EnableDisableFBAccessProc *EnableDisableFBAccess; + xf86SetDGAModeProc *SetDGAMode; + xf86ChangeGammaProc *ChangeGamma; + xf86PointerMovedProc *PointerMoved; + xf86PMEventProc *PMEvent; + xf86HandleMessageProc *HandleMessage; + xf86DPMSSetProc *DPMSSet; + xf86LoadPaletteProc *LoadPalette; + xf86SetOverscanProc *SetOverscan; + xorgDriverFuncProc *DriverFunc; + + /* + * This can be used when the minor ABI version is incremented. + * The NUM_* parameter must be reduced appropriately to keep the + * structure size and alignment unchanged. + */ + funcPointer reservedFuncs[NUM_RESERVED_FUNCS]; + +} ScrnInfoRec; + + +typedef struct { + Bool (*OpenFramebuffer)( + ScrnInfoPtr pScrn, + char **name, + unsigned char **mem, + int *size, + int *offset, + int *extra + ); + void (*CloseFramebuffer)(ScrnInfoPtr pScrn); + Bool (*SetMode)(ScrnInfoPtr pScrn, DGAModePtr pMode); + void (*SetViewport)(ScrnInfoPtr pScrn, int x, int y, int flags); + int (*GetViewport)(ScrnInfoPtr pScrn); + void (*Sync)(ScrnInfoPtr); + void (*FillRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned long color + ); + void (*BlitRect)( + ScrnInfoPtr pScrn, + int srcx, int srcy, + int w, int h, + int dstx, int dsty + ); + void (*BlitTransRect)( + ScrnInfoPtr pScrn, + int srcx, int srcy, + int w, int h, + int dstx, int dsty, + unsigned long color + ); +} DGAFunctionRec, *DGAFunctionPtr; + +typedef struct { + int token; /* id of the token */ + const char * name; /* token name */ +} SymTabRec, *SymTabPtr; + +/* flags for xf86LookupMode */ +typedef enum { + LOOKUP_DEFAULT = 0, /* Use default mode lookup method */ + LOOKUP_BEST_REFRESH, /* Pick modes with best refresh */ + LOOKUP_CLOSEST_CLOCK, /* Pick modes with the closest clock */ + LOOKUP_LIST_ORDER, /* Pick first useful mode in list */ + LOOKUP_CLKDIV2 = 0x0100, /* Allow half clocks */ + LOOKUP_OPTIONAL_TOLERANCES = 0x0200 /* Allow missing hsync/vrefresh */ +} LookupModeFlags; + +#define NoDepth24Support 0x00 +#define Support24bppFb 0x01 /* 24bpp framebuffer supported */ +#define Support32bppFb 0x02 /* 32bpp framebuffer supported */ +#define SupportConvert24to32 0x04 /* Can convert 24bpp pixmap to 32bpp */ +#define SupportConvert32to24 0x08 /* Can convert 32bpp pixmap to 24bpp */ +#define PreferConvert24to32 0x10 /* prefer 24bpp pixmap to 32bpp conv */ +#define PreferConvert32to24 0x20 /* prefer 32bpp pixmap to 24bpp conv */ + + +/* For DPMS */ +typedef void (*DPMSSetProcPtr)(ScrnInfoPtr, int, int); + +/* Input handler proc */ +typedef void (*InputHandlerProc)(int fd, pointer data); + +/* These are used by xf86GetClocks */ +#define CLK_REG_SAVE -1 +#define CLK_REG_RESTORE -2 + +/* xf86Debug.c */ +#ifdef BUILDDEBUG +typedef struct { + long sec; + long usec; +} xf86TsRec, *xf86TsPtr; +#endif + +/* + * misc constants + */ +#define INTERLACE_REFRESH_WEIGHT 1.5 +#define SYNC_TOLERANCE 0.01 /* 1 percent */ +#define CLOCK_TOLERANCE 2000 /* Clock matching tolerance (2MHz) */ + + +#define OVERLAY_8_32_DUALFB 0x00000001 +#define OVERLAY_8_24_DUALFB 0x00000002 +#define OVERLAY_8_16_DUALFB 0x00000004 +#define OVERLAY_8_32_PLANAR 0x00000008 + +#if 0 +#define LD_RESOLV_IFDONE 0 /* only check if no more + delays pending */ +#define LD_RESOLV_NOW 1 /* finish one delay step */ +#define LD_RESOLV_FORCE 2 /* force checking... */ +#endif + +/* Values of xf86Info.mouseFlags */ +#define MF_CLEAR_DTR 1 +#define MF_CLEAR_RTS 2 + +/* Action Events */ +typedef enum { + ACTION_TERMINATE = 0, /* Terminate Server */ + ACTION_NEXT_MODE = 10, /* Switch to next video mode */ + ACTION_PREV_MODE, + ACTION_DISABLEGRAB = 20, /* Cancel server/pointer/kbd grabs */ + ACTION_CLOSECLIENT, /* Kill client holding grab */ + ACTION_SWITCHSCREEN = 100, /* VT switch */ + ACTION_SWITCHSCREEN_NEXT, + ACTION_SWITCHSCREEN_PREV, + ACTION_MESSAGE = 9999 /* Generic message passing */ +} ActionEvent; + +/* xf86Versions.c */ +/* + * Never change existing values, and always assign values explicitly. + * NUM_BUILTIN_IFS must always be the last entry. + */ +typedef enum { + BUILTIN_IF_OSMOUSE = 0, + BUILTIN_IF_OSKBD = 1, + NUM_BUILTIN_IFS +} BuiltinInterface; + +/* + * These are intentionally the same as the module version macros. + * It is possible to register a module as providing a specific interface, + * in which case the module's version is used. This feature isn't + * really ready for use yet though. + */ + +#define BUILTIN_INTERFACE_VERSION_NUMERIC(maj, min, patch) \ + ((((maj) & 0xFF) << 24) | (((min) & 0xFF) << 16) | (patch & 0xFFFF)) +#define GET_BUILTIN_INTERFACE_MAJOR_VERSION(vers) (((vers) >> 24) & 0xFF) +#define GET_BUILTIN_INTERFACE_MINOR_VERSION(vers) (((vers) >> 16) & 0xFF) +#define GET_BUILTIN_INTERFACE_PATCH_VERSION(vers) ((vers) & 0xFFFF) + +#endif /* _XF86STR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86tokens.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86tokens.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86tokens.h (revision 51223) @@ -0,0 +1,280 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86tokens.h,v 1.20 2003/08/24 17:37:09 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86_tokens_h +#define _xf86_tokens_h + +/* Undefine symbols that some OSs might define */ +#undef IOBASE + +/* + * Each token should have a unique value regardless of the section + * it is used in. + */ + +typedef enum { + /* errno-style tokens */ + EOF_TOKEN = -4, + LOCK_TOKEN = -3, + ERROR_TOKEN = -2, + + /* value type tokens */ + NUMBER = 1, + STRING, + + /* Tokens that can appear in many sections */ + SECTION, + SUBSECTION, + ENDSECTION, + ENDSUBSECTION, + IDENTIFIER, + VENDOR, + DASH, + COMMA, + OPTION, + COMMENT, + + /* Frequency units */ + HRZ, + KHZ, + MHZ, + + /* File tokens */ + FONTPATH, + RGBPATH, + MODULEPATH, + INPUTDEVICES, + LOGFILEPATH, + + /* Server Flag tokens. These are deprecated in favour of generic Options */ + NOTRAPSIGNALS, + DONTZAP, + DONTZOOM, + DISABLEVIDMODE, + ALLOWNONLOCAL, + DISABLEMODINDEV, + MODINDEVALLOWNONLOCAL, + ALLOWMOUSEOPENFAIL, + BLANKTIME, + STANDBYTIME, + SUSPENDTIME, + OFFTIME, + DEFAULTLAYOUT, + + /* Monitor tokens */ + MODEL, + MODELINE, + DISPLAYSIZE, + HORIZSYNC, + VERTREFRESH, + MODE, + GAMMA, + USEMODES, + + /* Modes tokens */ + /* no new ones */ + + /* Mode tokens */ + DOTCLOCK, + HTIMINGS, + VTIMINGS, + FLAGS, + HSKEW, + BCAST, + VSCAN, + ENDMODE, + + /* Screen tokens */ + OBSDRIVER, + MDEVICE, + MONITOR, + SCREENNO, + DEFAULTDEPTH, + DEFAULTBPP, + DEFAULTFBBPP, + + /* VideoAdaptor tokens */ + VIDEOADAPTOR, + + /* Mode timing tokens */ + TT_INTERLACE, + TT_PHSYNC, + TT_NHSYNC, + TT_PVSYNC, + TT_NVSYNC, + TT_CSYNC, + TT_PCSYNC, + TT_NCSYNC, + TT_DBLSCAN, + TT_HSKEW, + TT_BCAST, + TT_VSCAN, + TT_CUSTOM, + + /* Module tokens */ + LOAD, + LOAD_DRIVER, + + /* Device tokens */ + DRIVER, + CHIPSET, + CLOCKS, + VIDEORAM, + BOARD, + IOBASE, + RAMDAC, + DACSPEED, + BIOSBASE, + MEMBASE, + CLOCKCHIP, + CHIPID, + CHIPREV, + CARD, + BUSID, + TEXTCLOCKFRQ, + IRQ, + + /* Keyboard tokens */ + AUTOREPEAT, + XLEDS, + KPROTOCOL, + XKBKEYMAP, + XKBCOMPAT, + XKBTYPES, + XKBKEYCODES, + XKBGEOMETRY, + XKBSYMBOLS, + XKBDISABLE, + PANIX106, + XKBRULES, + XKBMODEL, + XKBLAYOUT, + XKBVARIANT, + XKBOPTIONS, + /* The next two have become ServerFlags options */ + VTINIT, + VTSYSREQ, + /* Obsolete keyboard tokens */ + SERVERNUM, + LEFTALT, + RIGHTALT, + SCROLLLOCK_TOK, + RIGHTCTL, + /* arguments for the above obsolete tokens */ + CONF_KM_META, + CONF_KM_COMPOSE, + CONF_KM_MODESHIFT, + CONF_KM_MODELOCK, + CONF_KM_SCROLLLOCK, + CONF_KM_CONTROL, + + /* Pointer tokens */ + EMULATE3, + BAUDRATE, + SAMPLERATE, + PRESOLUTION, + CLEARDTR, + CLEARRTS, + CHORDMIDDLE, + PROTOCOL, + PDEVICE, + EM3TIMEOUT, + DEVICE_NAME, + ALWAYSCORE, + PBUTTONS, + ZAXISMAPPING, + + /* Pointer Z axis mapping tokens */ + XAXIS, + YAXIS, + + /* Display tokens */ + MODES, + VIEWPORT, + VIRTUAL, + VISUAL, + BLACK_TOK, + WHITE_TOK, + DEPTH, + BPP, + WEIGHT, + + /* Layout Tokens */ + SCREEN, + INACTIVE, + INPUTDEVICE, + + /* Adjaceny Tokens */ + RIGHTOF, + LEFTOF, + ABOVE, + BELOW, + RELATIVE, + ABSOLUTE, + + /* Vendor Tokens */ + VENDORNAME, + + /* DRI Tokens */ + GROUP, + BUFFERS +} ParserTokens; + +#endif /* _xf86_tokens_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86x86emu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86x86emu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86x86emu.h (revision 51223) @@ -0,0 +1,55 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86x86emu.h,v 1.1 2000/01/23 04:44:35 dawes Exp $ */ +/* + * XFree86 int10 module + * execute BIOS int 10h calls in x86 real mode environment + * Copyright 1999 Egbert Eich + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef XF86X86EMU_H_ +#define XF86X86EMU_H_ +#include + +#define M _X86EMU_env + +#define X86_EAX M.x86.R_EAX +#define X86_EBX M.x86.R_EBX +#define X86_ECX M.x86.R_ECX +#define X86_EDX M.x86.R_EDX +#define X86_ESI M.x86.R_ESI +#define X86_EDI M.x86.R_EDI +#define X86_EBP M.x86.R_EBP +#define X86_EIP M.x86.R_EIP +#define X86_ESP M.x86.R_ESP +#define X86_EFLAGS M.x86.R_EFLG + +#define X86_FLAGS M.x86.R_FLG +#define X86_AX M.x86.R_AX +#define X86_BX M.x86.R_BX +#define X86_CX M.x86.R_CX +#define X86_DX M.x86.R_DX +#define X86_SI M.x86.R_SI +#define X86_DI M.x86.R_DI +#define X86_BP M.x86.R_BP +#define X86_IP M.x86.R_IP +#define X86_SP M.x86.R_SP +#define X86_CS M.x86.R_CS +#define X86_DS M.x86.R_DS +#define X86_ES M.x86.R_ES +#define X86_SS M.x86.R_SS +#define X86_FS M.x86.R_FS +#define X86_GS M.x86.R_GS + +#define X86_AL M.x86.R_AL +#define X86_BL M.x86.R_BL +#define X86_CL M.x86.R_CL +#define X86_DL M.x86.R_DL + +#define X86_AH M.x86.R_AH +#define X86_BH M.x86.R_BH +#define X86_CH M.x86.R_CH +#define X86_DH M.x86.R_DH + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xv.h (revision 51223) @@ -0,0 +1,271 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xv.h,v 1.25 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 1998-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XV_H_ +#define _XF86XV_H_ + +#include "xvdix.h" +#include "xf86str.h" + +#define VIDEO_NO_CLIPPING 0x00000001 +#define VIDEO_INVERT_CLIPLIST 0x00000002 +#define VIDEO_OVERLAID_IMAGES 0x00000004 +#define VIDEO_OVERLAID_STILLS 0x00000008 +#define VIDEO_CLIP_TO_VIEWPORT 0x00000010 + +typedef struct { + int id; + int type; + int byte_order; + unsigned char guid[16]; + int bits_per_pixel; + int format; + int num_planes; + + /* for RGB formats only */ + int depth; + unsigned int red_mask; + unsigned int green_mask; + unsigned int blue_mask; + + /* for YUV formats only */ + unsigned int y_sample_bits; + unsigned int u_sample_bits; + unsigned int v_sample_bits; + unsigned int horz_y_period; + unsigned int horz_u_period; + unsigned int horz_v_period; + unsigned int vert_y_period; + unsigned int vert_u_period; + unsigned int vert_v_period; + char component_order[32]; + int scanline_order; +} XF86ImageRec, *XF86ImagePtr; + + +typedef struct { + ScrnInfoPtr pScrn; + int id; + unsigned short width, height; + int *pitches; /* bytes */ + int *offsets; /* in bytes from start of framebuffer */ + DevUnion devPrivate; +} XF86SurfaceRec, *XF86SurfacePtr; + + +typedef int (* PutVideoFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data ); +typedef int (* PutStillFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data ); +typedef int (* GetVideoFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data ); +typedef int (* GetStillFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data ); +typedef void (* StopVideoFuncPtr)(ScrnInfoPtr pScrn, pointer data, Bool Exit); +typedef int (* SetPortAttributeFuncPtr)(ScrnInfoPtr pScrn, Atom attribute, + INT32 value, pointer data); +typedef int (* GetPortAttributeFuncPtr)(ScrnInfoPtr pScrn, Atom attribute, + INT32 *value, pointer data); +typedef void (* QueryBestSizeFuncPtr)(ScrnInfoPtr pScrn, Bool motion, + short vid_w, short vid_h, short drw_w, short drw_h, + unsigned int *p_w, unsigned int *p_h, pointer data); +typedef int (* PutImageFuncPtr)( ScrnInfoPtr pScrn, + short src_x, short src_y, short drw_x, short drw_y, + short src_w, short src_h, short drw_w, short drw_h, + int image, unsigned char* buf, short width, short height, Bool Sync, + RegionPtr clipBoxes, pointer data ); +typedef int (* ReputImageFuncPtr)( ScrnInfoPtr pScrn, short drw_x, short drw_y, + RegionPtr clipBoxes, pointer data ); +typedef int (*QueryImageAttributesFuncPtr)(ScrnInfoPtr pScrn, + int image, unsigned short *width, unsigned short *height, + int *pitches, int *offsets); + +typedef enum { + XV_OFF, + XV_PENDING, + XV_ON +} XvStatus; + +/*** this is what the driver needs to fill out ***/ + +typedef struct { + int id; + char *name; + unsigned short width, height; + XvRationalRec rate; +} XF86VideoEncodingRec, *XF86VideoEncodingPtr; + +typedef struct { + char depth; + short class; +} XF86VideoFormatRec, *XF86VideoFormatPtr; + +typedef struct { + int flags; + int min_value; + int max_value; + char *name; +} XF86AttributeRec, *XF86AttributePtr; + +typedef struct { + unsigned int type; + int flags; + char *name; + int nEncodings; + XF86VideoEncodingPtr pEncodings; + int nFormats; + XF86VideoFormatPtr pFormats; + int nPorts; + DevUnion *pPortPrivates; + int nAttributes; + XF86AttributePtr pAttributes; + int nImages; + XF86ImagePtr pImages; + PutVideoFuncPtr PutVideo; + PutStillFuncPtr PutStill; + GetVideoFuncPtr GetVideo; + GetStillFuncPtr GetStill; + StopVideoFuncPtr StopVideo; + SetPortAttributeFuncPtr SetPortAttribute; + GetPortAttributeFuncPtr GetPortAttribute; + QueryBestSizeFuncPtr QueryBestSize; + PutImageFuncPtr PutImage; + ReputImageFuncPtr ReputImage; + QueryImageAttributesFuncPtr QueryImageAttributes; +} XF86VideoAdaptorRec, *XF86VideoAdaptorPtr; + +typedef struct { + XF86ImagePtr image; + int flags; + int (*alloc_surface)(ScrnInfoPtr pScrn, + int id, + unsigned short width, + unsigned short height, + XF86SurfacePtr surface); + int (*free_surface)(XF86SurfacePtr surface); + int (*display) (XF86SurfacePtr surface, + short vid_x, short vid_y, + short drw_x, short drw_y, + short vid_w, short vid_h, + short drw_w, short drw_h, + RegionPtr clipBoxes); + int (*stop) (XF86SurfacePtr surface); + int (*getAttribute) (ScrnInfoPtr pScrn, Atom attr, INT32 *value); + int (*setAttribute) (ScrnInfoPtr pScrn, Atom attr, INT32 value); + int max_width; + int max_height; + int num_attributes; + XF86AttributePtr attributes; +} XF86OffscreenImageRec, *XF86OffscreenImagePtr; + +Bool +xf86XVScreenInit( + ScreenPtr pScreen, + XF86VideoAdaptorPtr *Adaptors, + int num +); + +typedef int (* xf86XVInitGenericAdaptorPtr)(ScrnInfoPtr pScrn, + XF86VideoAdaptorPtr **Adaptors); + +int +xf86XVRegisterGenericAdaptorDriver( + xf86XVInitGenericAdaptorPtr InitFunc +); + +int +xf86XVListGenericAdaptors( + ScrnInfoPtr pScrn, + XF86VideoAdaptorPtr **Adaptors +); + +Bool +xf86XVRegisterOffscreenImages( + ScreenPtr pScreen, + XF86OffscreenImagePtr images, + int num +); + +XF86OffscreenImagePtr +xf86XVQueryOffscreenImages( + ScreenPtr pScreen, + int *num +); + +XF86VideoAdaptorPtr xf86XVAllocateVideoAdaptorRec(ScrnInfoPtr pScrn); + +void xf86XVFreeVideoAdaptorRec(XF86VideoAdaptorPtr ptr); + +void +xf86XVFillKeyHelper (ScreenPtr pScreen, CARD32 key, RegionPtr clipboxes); + +Bool +xf86XVClipVideoHelper( + BoxPtr dst, + INT32 *xa, + INT32 *xb, + INT32 *ya, + INT32 *yb, + RegionPtr reg, + INT32 width, + INT32 height +); + +void +xf86XVCopyYUV12ToPacked( + const void *srcy, + const void *srcv, + const void *srcu, + void *dst, + int srcPitchy, + int srcPitchuv, + int dstPitch, + int h, + int w +); + +void +xf86XVCopyPacked( + const void *src, + void *dst, + int srcPitch, + int dstPitch, + int h, + int w +); + +#endif /* _XF86XV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvmc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvmc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvmc.h (revision 51223) @@ -0,0 +1,164 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xvmc.h,v 1.7 2003/10/08 22:31:59 mvojkovi Exp $ */ + +/* + * Copyright (c) 2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XVMC_H +#define _XF86XVMC_H + +#include "xvmcext.h" +#include "xf86xv.h" + +typedef struct { + int num_xvimages; + int *xvimage_ids; /* reference the subpictures in the XF86MCAdaptorRec */ +} XF86MCImageIDList; + +typedef struct { + int surface_type_id; /* Driver generated. Must be unique on the port */ + int chroma_format; + int color_description; /* no longer used */ + unsigned short max_width; + unsigned short max_height; + unsigned short subpicture_max_width; + unsigned short subpicture_max_height; + int mc_type; + int flags; + XF86MCImageIDList *compatible_subpictures; /* can be null, if none */ +} XF86MCSurfaceInfoRec, *XF86MCSurfaceInfoPtr; + + +/* + xf86XvMCCreateContextProc + + DIX will fill everything out in the context except the driver_priv. + The port_priv holds the private data specified for the port when + Xv was initialized by the driver. + The driver may store whatever it wants in driver_priv and edit + the width, height and flags. If the driver wants to return something + to the client it can allocate space in priv and specify the number + of 32 bit words in num_priv. This must be dynamically allocated + space because DIX will free it after it passes it to the client. +*/ + + +typedef int (*xf86XvMCCreateContextProcPtr) ( + ScrnInfoPtr pScrn, + XvMCContextPtr context, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroyContextProcPtr) ( + ScrnInfoPtr pScrn, + XvMCContextPtr context +); + +/* + xf86XvMCCreateSurfaceProc + + DIX will fill everything out in the surface except the driver_priv. + The driver may store whatever it wants in driver_priv. The driver + may pass data back to the client in the same manner as the + xf86XvMCCreateContextProc. +*/ + + +typedef int (*xf86XvMCCreateSurfaceProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSurfacePtr surface, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroySurfaceProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSurfacePtr surface +); + +/* + xf86XvMCCreateSubpictureProc + + DIX will fill everything out in the subpicture except the driver_priv, + num_palette_entries, entry_bytes and component_order. The driver may + store whatever it wants in driver_priv and edit the width and height. + If it is a paletted subpicture the driver needs to fill out the + num_palette_entries, entry_bytes and component_order. These are + not communicated to the client until the time the surface is + created. + + The driver may pass data back to the client in the same manner as the + xf86XvMCCreateContextProc. +*/ + + +typedef int (*xf86XvMCCreateSubpictureProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSubpicturePtr subpicture, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroySubpictureProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSubpicturePtr subpicture +); + + +typedef struct { + char *name; + int num_surfaces; + XF86MCSurfaceInfoPtr *surfaces; + int num_subpictures; + XF86ImagePtr *subpictures; + xf86XvMCCreateContextProcPtr CreateContext; + xf86XvMCDestroyContextProcPtr DestroyContext; + xf86XvMCCreateSurfaceProcPtr CreateSurface; + xf86XvMCDestroySurfaceProcPtr DestroySurface; + xf86XvMCCreateSubpictureProcPtr CreateSubpicture; + xf86XvMCDestroySubpictureProcPtr DestroySubpicture; +} XF86MCAdaptorRec, *XF86MCAdaptorPtr; + +/* + xf86XvMCScreenInit + + Unlike Xv, the adaptor data is not copied from this structure. + This structure's data is used so it must stick around for the + life of the server. Note that it's an array of pointers not + an array of structures. +*/ + +Bool xf86XvMCScreenInit( + ScreenPtr pScreen, + int num_adaptors, + XF86MCAdaptorPtr *adaptors +); + +XF86MCAdaptorPtr xf86XvMCCreateAdaptorRec (void); +void xf86XvMCDestroyAdaptorRec(XF86MCAdaptorPtr adaptor); + +#endif /* _XF86XVMC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xf86xvpriv.h (revision 51223) @@ -0,0 +1,86 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xvpriv.h,v 1.2 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XVPRIV_H_ +#define _XF86XVPRIV_H_ + +#include "xf86xv.h" + +/*** These are DDX layer privates ***/ + +extern int XF86XvScreenIndex; + +typedef struct { + DestroyWindowProcPtr DestroyWindow; + ClipNotifyProcPtr ClipNotify; + WindowExposuresProcPtr WindowExposures; + void (*AdjustFrame)(int, int, int, int); + Bool (*EnterVT)(int, int); + void (*LeaveVT)(int, int); + GCPtr videoGC; +} XF86XVScreenRec, *XF86XVScreenPtr; + +typedef struct { + int flags; + PutVideoFuncPtr PutVideo; + PutStillFuncPtr PutStill; + GetVideoFuncPtr GetVideo; + GetStillFuncPtr GetStill; + StopVideoFuncPtr StopVideo; + SetPortAttributeFuncPtr SetPortAttribute; + GetPortAttributeFuncPtr GetPortAttribute; + QueryBestSizeFuncPtr QueryBestSize; + PutImageFuncPtr PutImage; + ReputImageFuncPtr ReputImage; + QueryImageAttributesFuncPtr QueryImageAttributes; +} XvAdaptorRecPrivate, *XvAdaptorRecPrivatePtr; + +typedef struct { + ScrnInfoPtr pScrn; + DrawablePtr pDraw; + unsigned char type; + unsigned int subWindowMode; + DDXPointRec clipOrg; + RegionPtr clientClip; + RegionPtr pCompositeClip; + Bool FreeCompositeClip; + XvAdaptorRecPrivatePtr AdaptorRec; + XvStatus isOn; + Bool moved; + int vid_x, vid_y, vid_w, vid_h; + int drw_x, drw_y, drw_w, drw_h; + DevUnion DevPriv; +} XvPortRecPrivate, *XvPortRecPrivatePtr; + +typedef struct _XF86XVWindowRec{ + XvPortRecPrivatePtr PortRec; + struct _XF86XVWindowRec *next; +} XF86XVWindowRec, *XF86XVWindowPtr; + +#endif /* _XF86XVPRIV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfIOKit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfIOKit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfIOKit.h (revision 51223) @@ -0,0 +1,57 @@ +/* + xfIOKit.h + + IOKit specific functions and definitions +*/ +/* + * Copyright (c) 2001-2002 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/xfIOKit.h,v 1.10 2003/03/15 18:02:08 torrey Exp $ */ + +#ifndef _XFIOKIT_H +#define _XFIOKIT_H + +#include +#include +#include +#include "screenint.h" +#include "darwin.h" + +typedef struct { + io_connect_t fbService; + StdFBShmem_t *cursorShmem; + unsigned char *framebuffer; + unsigned char *shadowPtr; +} XFIOKitScreenRec, *XFIOKitScreenPtr; + +#define XFIOKIT_SCREEN_PRIV(pScreen) \ + ((XFIOKitScreenPtr)pScreen->devPrivates[xfIOKitScreenIndex].ptr) + +extern int xfIOKitScreenIndex; // index into pScreen.devPrivates +extern io_connect_t xfIOKitInputConnect; + +Bool XFIOKitInitCursor(ScreenPtr pScreen); + +#endif /* _XFIOKIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixes.h (revision 51223) @@ -0,0 +1,54 @@ +/* + * $Id: xfixes.h,v 1.6 2005/07/03 07:02:08 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XFIXES_H_ +#define _XFIXES_H_ + +#include "resource.h" + +extern RESTYPE RegionResType; +extern int XFixesErrorBase; + +#define VERIFY_REGION(pRegion, rid, client, mode) { \ + pRegion = SecurityLookupIDByType (client, rid, RegionResType, mode); \ + if (!pRegion) { \ + client->errorValue = rid; \ + return XFixesErrorBase + BadRegion; \ + } \ +} + +#define VERIFY_REGION_OR_NONE(pRegion, rid, client, mode) { \ + pRegion = 0; \ + if (rid) VERIFY_REGION(pRegion, rid, client, mode); \ +} + +RegionPtr +XFixesRegionCopy (RegionPtr pRegion); + + +#endif /* _XFIXES_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixesint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixesint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xfixesint.h (revision 51223) @@ -0,0 +1,243 @@ +/* + * $Id: xfixesint.h,v 1.7 2005/07/03 08:53:54 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XFIXESINT_H_ +#define _XFIXESINT_H_ + +#define NEED_EVENTS +#include +#include +#include "misc.h" +#include "os.h" +#include "dixstruct.h" +#include "extnsionst.h" +#include +#include "windowstr.h" +#include "selection.h" +#include "xfixes.h" + +extern unsigned char XFixesReqCode; +extern int XFixesEventBase; +extern int XFixesClientPrivateIndex; + +typedef struct _XFixesClient { + CARD32 major_version; + CARD32 minor_version; +} XFixesClientRec, *XFixesClientPtr; + +#define GetXFixesClient(pClient) ((XFixesClientPtr) (pClient)->devPrivates[XFixesClientPrivateIndex].ptr) + +extern int (*ProcXFixesVector[XFixesNumberRequests])(ClientPtr); +extern int (*SProcXFixesVector[XFixesNumberRequests])(ClientPtr); + +/* Initialize extension at server startup time */ + +void +XFixesExtensionInit(void); + +/* Save set */ +int +ProcXFixesChangeSaveSet(ClientPtr client); + +int +SProcXFixesChangeSaveSet(ClientPtr client); + +/* Selection events */ +int +ProcXFixesSelectSelectionInput (ClientPtr client); + +int +SProcXFixesSelectSelectionInput (ClientPtr client); + +void +SXFixesSelectionNotifyEvent (xXFixesSelectionNotifyEvent *from, + xXFixesSelectionNotifyEvent *to); +Bool +XFixesSelectionInit (void); + +/* Cursor notification */ +Bool +XFixesCursorInit (void); + +int +ProcXFixesSelectCursorInput (ClientPtr client); + +int +SProcXFixesSelectCursorInput (ClientPtr client); + +void +SXFixesCursorNotifyEvent (xXFixesCursorNotifyEvent *from, + xXFixesCursorNotifyEvent *to); + +int +ProcXFixesGetCursorImage (ClientPtr client); + +int +SProcXFixesGetCursorImage (ClientPtr client); + +/* Cursor names (Version 2) */ + +int +ProcXFixesSetCursorName (ClientPtr client); + +int +SProcXFixesSetCursorName (ClientPtr client); + +int +ProcXFixesGetCursorName (ClientPtr client); + +int +SProcXFixesGetCursorName (ClientPtr client); + +int +ProcXFixesGetCursorImageAndName (ClientPtr client); + +int +SProcXFixesGetCursorImageAndName (ClientPtr client); + +/* Cursor replacement (Version 2) */ + +int +ProcXFixesChangeCursor (ClientPtr client); + +int +SProcXFixesChangeCursor (ClientPtr client); + +int +ProcXFixesChangeCursorByName (ClientPtr client); + +int +SProcXFixesChangeCursorByName (ClientPtr client); + +/* Region objects (Version 2* */ +Bool +XFixesRegionInit (void); + +int +ProcXFixesCreateRegion (ClientPtr client); + +int +SProcXFixesCreateRegion (ClientPtr client); + +int +ProcXFixesCreateRegionFromBitmap (ClientPtr client); + +int +SProcXFixesCreateRegionFromBitmap (ClientPtr client); + +int +ProcXFixesCreateRegionFromWindow (ClientPtr client); + +int +SProcXFixesCreateRegionFromWindow (ClientPtr client); + +int +ProcXFixesCreateRegionFromGC (ClientPtr client); + +int +SProcXFixesCreateRegionFromGC (ClientPtr client); + +int +ProcXFixesCreateRegionFromPicture (ClientPtr client); + +int +SProcXFixesCreateRegionFromPicture (ClientPtr client); + +int +ProcXFixesDestroyRegion (ClientPtr client); + +int +SProcXFixesDestroyRegion (ClientPtr client); + +int +ProcXFixesSetRegion (ClientPtr client); + +int +SProcXFixesSetRegion (ClientPtr client); + +int +ProcXFixesCopyRegion (ClientPtr client); + +int +SProcXFixesCopyRegion (ClientPtr client); + +int +ProcXFixesCombineRegion (ClientPtr client); + +int +SProcXFixesCombineRegion (ClientPtr client); + +int +ProcXFixesInvertRegion (ClientPtr client); + +int +SProcXFixesInvertRegion (ClientPtr client); + +int +ProcXFixesTranslateRegion (ClientPtr client); + +int +SProcXFixesTranslateRegion (ClientPtr client); + +int +ProcXFixesRegionExtents (ClientPtr client); + +int +SProcXFixesRegionExtents (ClientPtr client); + +int +ProcXFixesFetchRegion (ClientPtr client); + +int +SProcXFixesFetchRegion (ClientPtr client); + +int +ProcXFixesSetGCClipRegion (ClientPtr client); + +int +SProcXFixesSetGCClipRegion (ClientPtr client); + +int +ProcXFixesSetWindowShapeRegion (ClientPtr client); + +int +SProcXFixesSetWindowShapeRegion (ClientPtr client); + +int +ProcXFixesSetPictureClipRegion (ClientPtr client); + +int +SProcXFixesSetPictureClipRegion (ClientPtr client); + +int +ProcXFixesExpandRegion (ClientPtr client); + +int +SProcXFixesExpandRegion (ClientPtr client); + +#endif /* _XFIXESINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xisb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xisb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xisb.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* $XFree86$ */ + +#ifndef _xisb_H_ +#define _xisb_H_ + +/****************************************************************************** + * Definitions + * structs, typedefs, #defines, enums + *****************************************************************************/ + +typedef struct _XISBuffer +{ + int fd; + int trace; + int block_duration; + xf86ssize_t current; /* bytes read */ + xf86ssize_t end; + xf86ssize_t buffer_size; + unsigned char *buf; +} XISBuffer; + +/****************************************************************************** + * Declarations + * variables: use xisb_LOC in front + * of globals. + * put locals in the .c file. + *****************************************************************************/ +XISBuffer * XisbNew (int fd, xf86ssize_t size); +void XisbFree (XISBuffer *b); +int XisbRead (XISBuffer *b); +xf86ssize_t XisbWrite (XISBuffer *b, unsigned char *msg, xf86ssize_t len); +void XisbTrace (XISBuffer *b, int trace); +void XisbBlockDuration (XISBuffer *b, int block_duration); + +/* + * DO NOT PUT ANYTHING AFTER THIS ENDIF + */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkb.h (revision 51223) @@ -0,0 +1,72 @@ +/* $XFree86$ */ + +/* #include "XKBfile.h" */ + +extern int ProcXkbUseExtension(ClientPtr client); +extern int ProcXkbSelectEvents(ClientPtr client); +extern int ProcXkbBell(ClientPtr client); +extern int ProcXkbGetState(ClientPtr client); +extern int ProcXkbLatchLockState(ClientPtr client); +extern int ProcXkbGetControls(ClientPtr client); +extern int ProcXkbSetControls(ClientPtr client); +extern int ProcXkbGetMap(ClientPtr client); +extern int ProcXkbSetMap(ClientPtr client); +extern int ProcXkbGetCompatMap(ClientPtr client); +extern int ProcXkbSetCompatMap(ClientPtr client); +extern int ProcXkbGetIndicatorState(ClientPtr client); +extern int ProcXkbGetIndicatorMap(ClientPtr client); +extern int ProcXkbSetIndicatorMap(ClientPtr client); +extern int ProcXkbGetNamedIndicator(ClientPtr client); +extern int ProcXkbSetNamedIndicator(ClientPtr client); +extern int ProcXkbGetNames(ClientPtr client); +extern int ProcXkbSetNames(ClientPtr client); +extern int ProcXkbGetGeometry(ClientPtr client); +extern int ProcXkbSetGeometry(ClientPtr client); +extern int ProcXkbPerClientFlags(ClientPtr client); +extern int ProcXkbListComponents(ClientPtr client); +extern int ProcXkbGetKbdByName(ClientPtr client); +extern int ProcXkbGetDeviceInfo(ClientPtr client); +extern int ProcXkbSetDeviceInfo(ClientPtr client); +extern int ProcXkbSetDebuggingFlags(ClientPtr client); + +extern int XkbSetRepeatRate(DeviceIntPtr dev, int timeout, int interval, int major, int minor); +extern int XkbGetRepeatRate(DeviceIntPtr dev, int *timeout, int *interval); + +extern Status XkbComputeGetIndicatorMapReplySize( + XkbIndicatorPtr indicators, + xkbGetIndicatorMapReply *rep); +extern int XkbSendIndicatorMap( + ClientPtr client, + XkbIndicatorPtr indicators, + xkbGetIndicatorMapReply *rep); + +extern void XkbComputeCompatState(XkbSrvInfoPtr xkbi); +extern void XkbSetPhysicalLockingKey(DeviceIntPtr dev, unsigned key); + +extern Bool XkbFilterEvents(ClientPtr pClient, int nEvents, xEvent *xE); + +extern Bool XkbApplyLEDChangeToKeyboard( + XkbSrvInfoPtr xkbi, + XkbIndicatorMapPtr map, + Bool on, + XkbChangesPtr change); + +extern Bool XkbWriteRulesProp(ClientPtr client, pointer closure); + +extern XkbAction XkbGetButtonAction(DeviceIntPtr kbd, DeviceIntPtr dev, int button); + +/* extern Status XkbMergeFile(XkbDescPtr xkb, XkbFileInfo finfo); */ + +extern Bool XkbDDXCompileNamedKeymap( + XkbDescPtr xkb, + XkbComponentNamesPtr names, + char * nameRtrn, + int nameRtrnLen); + +extern Bool XkbDDXCompileKeymapByNames( + XkbDescPtr xkb, + XkbComponentNamesPtr names, + unsigned want, + unsigned need, + char * nameRtrn, + int nameRtrnLen); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkbDflts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkbDflts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xkbDflts.h (revision 51223) @@ -0,0 +1,513 @@ +/* $Xorg: xkbDflts.h,v 1.3 2000/08/17 19:53:47 cpqbld Exp $ */ +/* $XFree86: xc/programs/Xserver/xkb/xkbDflts.h,v 1.2 2001/10/28 03:34:20 tsi Exp $ */ +/* This file generated automatically by xkbcomp */ +/* DO NOT EDIT */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DEFAULT_H +#define DEFAULT_H 1 + +#ifndef XKB_IN_SERVER +#define GET_ATOM(d,s) XInternAtom(d,s,0) +#define DPYTYPE Display * +#else +#define GET_ATOM(d,s) MakeAtom(s,strlen(s),1) +#define DPYTYPE char * +#endif +#define NUM_KEYS 1 + +#define vmod_NumLock 0 +#define vmod_Alt 1 +#define vmod_LevelThree 2 +#define vmod_AltGr 3 +#define vmod_ScrollLock 4 + +#define vmod_NumLockMask (1<<0) +#define vmod_AltMask (1<<1) +#define vmod_LevelThreeMask (1<<2) +#define vmod_AltGrMask (1<<3) +#define vmod_ScrollLockMask (1<<4) + +/* types name is "default" */ +static Atom lnames_ONE_LEVEL[1]; + +static XkbKTMapEntryRec map_TWO_LEVEL[1]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } } +}; +static Atom lnames_TWO_LEVEL[2]; + +static XkbKTMapEntryRec map_ALPHABETIC[2]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 1, 0, { LockMask, LockMask, 0 } } +}; +static XkbModsRec preserve_ALPHABETIC[2]= { + { 0, 0, 0 }, + { LockMask, LockMask, 0 } +}; +static Atom lnames_ALPHABETIC[2]; + +static XkbKTMapEntryRec map_KEYPAD[2]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 0, 1, { 0, 0, vmod_NumLockMask } } +}; +static Atom lnames_KEYPAD[2]; + +static XkbKTMapEntryRec map_PC_BREAK[1]= { + { 1, 1, { ControlMask, ControlMask, 0 } } +}; +static Atom lnames_PC_BREAK[2]; + +static XkbKTMapEntryRec map_PC_SYSRQ[1]= { + { 0, 1, { 0, 0, vmod_AltMask } } +}; +static Atom lnames_PC_SYSRQ[2]; + +static XkbKTMapEntryRec map_CTRL_ALT[1]= { + { 0, 1, { ControlMask, ControlMask, vmod_AltMask } } +}; +static Atom lnames_CTRL_ALT[2]; + +static XkbKTMapEntryRec map_THREE_LEVEL[3]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 0, 2, { 0, 0, vmod_LevelThreeMask } }, + { 0, 2, { ShiftMask, ShiftMask, vmod_LevelThreeMask } } +}; +static Atom lnames_THREE_LEVEL[3]; + +static XkbKTMapEntryRec map_SHIFT_ALT[1]= { + { 0, 1, { ShiftMask, ShiftMask, vmod_AltMask } } +}; +static Atom lnames_SHIFT_ALT[2]; + +static XkbKeyTypeRec dflt_types[]= { + { + { 0, 0, 0 }, + 1, + 0, NULL, NULL, + None, lnames_ONE_LEVEL + }, + { + { ShiftMask, ShiftMask, 0 }, + 2, + 1, map_TWO_LEVEL, NULL, + None, lnames_TWO_LEVEL + }, + { + { ShiftMask|LockMask, ShiftMask|LockMask, 0 }, + 2, + 2, map_ALPHABETIC, preserve_ALPHABETIC, + None, lnames_ALPHABETIC + }, + { + { ShiftMask, ShiftMask, vmod_NumLockMask }, + 2, + 2, map_KEYPAD, NULL, + None, lnames_KEYPAD + }, + { + { ControlMask, ControlMask, 0 }, + 2, + 1, map_PC_BREAK, NULL, + None, lnames_PC_BREAK + }, + { + { 0, 0, vmod_AltMask }, + 2, + 1, map_PC_SYSRQ, NULL, + None, lnames_PC_SYSRQ + }, + { + { ControlMask, ControlMask, vmod_AltMask }, + 2, + 1, map_CTRL_ALT, NULL, + None, lnames_CTRL_ALT + }, + { + { ShiftMask, ShiftMask, vmod_LevelThreeMask }, + 3, + 3, map_THREE_LEVEL, NULL, + None, lnames_THREE_LEVEL + }, + { + { ShiftMask, ShiftMask, vmod_AltMask }, + 2, + 1, map_SHIFT_ALT, NULL, + None, lnames_SHIFT_ALT + } +}; +#define num_dflt_types (sizeof(dflt_types)/sizeof(XkbKeyTypeRec)) + + +static void +initTypeNames(DPYTYPE dpy) +{ + dflt_types[0].name= GET_ATOM(dpy,"ONE_LEVEL"); + lnames_ONE_LEVEL[0]= GET_ATOM(dpy,"Any"); + dflt_types[1].name= GET_ATOM(dpy,"TWO_LEVEL"); + lnames_TWO_LEVEL[0]= GET_ATOM(dpy,"Base"); + lnames_TWO_LEVEL[1]= GET_ATOM(dpy,"Shift"); + dflt_types[2].name= GET_ATOM(dpy,"ALPHABETIC"); + lnames_ALPHABETIC[0]= GET_ATOM(dpy,"Base"); + lnames_ALPHABETIC[1]= GET_ATOM(dpy,"Caps"); + dflt_types[3].name= GET_ATOM(dpy,"KEYPAD"); + lnames_KEYPAD[0]= GET_ATOM(dpy,"Base"); + lnames_KEYPAD[1]= GET_ATOM(dpy,"Number"); + dflt_types[4].name= GET_ATOM(dpy,"PC_BREAK"); + lnames_PC_BREAK[0]= GET_ATOM(dpy,"Base"); + lnames_PC_BREAK[1]= GET_ATOM(dpy,"Control"); + dflt_types[5].name= GET_ATOM(dpy,"PC_SYSRQ"); + lnames_PC_SYSRQ[0]= GET_ATOM(dpy,"Base"); + lnames_PC_SYSRQ[1]= GET_ATOM(dpy,"Alt"); + dflt_types[6].name= GET_ATOM(dpy,"CTRL+ALT"); + lnames_CTRL_ALT[0]= GET_ATOM(dpy,"Base"); + lnames_CTRL_ALT[1]= GET_ATOM(dpy,"Ctrl+Alt"); + dflt_types[7].name= GET_ATOM(dpy,"THREE_LEVEL"); + lnames_THREE_LEVEL[0]= GET_ATOM(dpy,"Base"); + lnames_THREE_LEVEL[1]= GET_ATOM(dpy,"Shift"); + lnames_THREE_LEVEL[2]= GET_ATOM(dpy,"Level3"); + dflt_types[8].name= GET_ATOM(dpy,"SHIFT+ALT"); + lnames_SHIFT_ALT[0]= GET_ATOM(dpy,"Base"); + lnames_SHIFT_ALT[1]= GET_ATOM(dpy,"Shift+Alt"); +} +/* compat name is "default" */ +static XkbSymInterpretRec dfltSI[69]= { + { XK_ISO_Level2_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_Exactly, ShiftMask, + 255, + { XkbSA_LatchMods, { 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Eisu_Shift, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Eisu_toggle, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Kana_Shift, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Kana_Lock, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Shift_Lock, 0x0000, + XkbSI_AnyOf, ShiftMask|LockMask, + 255, + { XkbSA_LockMods, { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Num_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 0, + { XkbSA_LockMods, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_Alt_L, 0x0000, + XkbSI_AnyOf, 0xff, + 1, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Alt_R, 0x0000, + XkbSI_AnyOf, 0xff, + 1, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Scroll_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 4, + { XkbSA_LockMods, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 255, + { XkbSA_ISOLock, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Level3_Shift, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOf, 0xff, + 2, + { XkbSA_SetMods, { 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00 } } }, + { XK_ISO_Level3_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOf, 0xff, + 2, + { XkbSA_LatchMods, { 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00 } } }, + { XK_Mode_switch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_SetGroup, { 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_1, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_End, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_2, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_Down, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_3, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_Next, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_4, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Left, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_6, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Right, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_7, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Home, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_8, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Up, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_9, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Prior, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_5, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Begin, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F1, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Divide, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F2, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Multiply, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F3, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Subtract, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Separator, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Add, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_0, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Insert, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Decimal, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Delete, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_EnableKeys, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00 } } }, + { XK_Pointer_Accelerate, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00 } } }, + { XK_Pointer_DfltBtnNext, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DfltBtnPrev, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_AccessX_Enable, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00 } } }, + { XK_Terminate_Server, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_Terminate, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Group_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LatchGroup, { 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Next_Group, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LockGroup, { 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Prev_Group, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LockGroup, { 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_First_Group, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockGroup, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Last_Group, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockGroup, { 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { NoSymbol, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_LockMods, { 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { NoSymbol, 0x0000, + XkbSI_AnyOf, 0xff, + 255, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } } +}; +#define num_dfltSI (sizeof(dfltSI)/sizeof(XkbSymInterpretRec)) + +static XkbCompatMapRec compatMap= { + dfltSI, + { /* group compatibility */ + { 0, 0, 0 }, + { 0, 0, vmod_AltGrMask }, + { 0, 0, vmod_AltGrMask }, + { 0, 0, vmod_AltGrMask } + }, + num_dfltSI, num_dfltSI +}; + +static XkbIndicatorRec indicators= { + 0x0, + { + { 0x80, 0, 0x00, XkbIM_UseEffective, { LockMask, LockMask, 0 }, 0 }, + { 0x80, 0, 0x00, XkbIM_UseEffective, { 0, 0, vmod_NumLockMask }, 0 }, + { 0x80, 0, 0x00, XkbIM_UseLocked, { ShiftMask, ShiftMask, 0 }, 0 }, + { 0x80, 0, 0x00, 0, { 0, 0, 0 }, XkbMouseKeysMask }, + { 0x80, 0, 0x00, XkbIM_UseLocked, { 0, 0, vmod_ScrollLockMask }, 0 }, + { 0x80, XkbIM_UseEffective, 0xfe, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 } + } +}; +static void +initIndicatorNames(DPYTYPE dpy,XkbDescPtr xkb) +{ + xkb->names->indicators[ 0]= GET_ATOM(dpy,"Caps Lock"); + xkb->names->indicators[ 1]= GET_ATOM(dpy,"Num Lock"); + xkb->names->indicators[ 2]= GET_ATOM(dpy,"Shift Lock"); + xkb->names->indicators[ 3]= GET_ATOM(dpy,"Mouse Keys"); + xkb->names->indicators[ 4]= GET_ATOM(dpy,"Scroll Lock"); + xkb->names->indicators[ 5]= GET_ATOM(dpy,"Group 2"); +} +#endif /* DEFAULT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-config.h (revision 51223) @@ -0,0 +1,110 @@ +/* include/xorg-config.h. Generated by configure. */ +/* xorg-config.h.in: not at all generated. -*- c -*- + * + * This file differs from xorg-server.h.in in that -server is installed + * with the rest of the SDK for external drivers/modules to use, whereas + * -config is for internal use only (i.e. building the DDX). + * + */ + +#ifndef _XORG_CONFIG_H_ +#define _XORG_CONFIG_H_ + +#include +#include + +/* Building Xorg server. */ +#define XORGSERVER 1 + +/* Current X.Org version. */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((0) * 100000) + ((0) * 1000) + 0) + +/* Need XFree86 libc-replacement typedefs. */ +#define NEED_XF86_TYPES 1 + +/* Need XFree86 libc-replacement functions. */ +#define NEED_XF86_PROTOTYPES 1 + +/* Name of X server. */ +#define __XSERVERNAME__ "Xorg" + +/* URL to go to for support. */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Use libdl-based loader. */ +#define DLOPEN_SUPPORT 1 + +/* Built-in output drivers. */ +#define DRIVERS {} + +/* Built-in input drivers. */ +#define IDRIVERS {} + +/* Path to configuration file. */ +#define XF86CONFIGFILE "xorg.conf" + +/* Path to configuration file. */ +#define __XCONFIGFILE__ "xorg.conf" + +/* Path to loadable modules. */ +#define DEFAULT_MODULE_PATH "/opt/debrix/lib/xorg/modules" + +/* Path to server log file. */ +#define DEFAULT_LOGPREFIX "/opt/debrix/var/log/Xorg." + +/* Building DRI-capable DDX. */ +#define XF86DRI 1 + +/* Solaris 8 or later? */ +/* #undef __SOL8__ */ + +/* Whether to use pixmap privates */ +#define PIXPRIV 1 + +/* Define to 1 if you have the `walkcontext' function (used on Solaris for + xorg_backtrace in hw/xfree86/common/xf86Events.c */ +/* #undef HAVE_WALKCONTEXT */ + +/* Define to 1 if unsigned long is 64 bits. */ +#define _XSERVER64 1 + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* Define to 1 if NetBSD built-in MTRR support is available */ +/* #undef HAS_MTRR_BUILTIN */ + +/* Define to 1 if BSD MTRR support is available */ +/* #undef HAS_MTRR_SUPPORT */ + +/* NetBSD PIO alpha IO */ +/* #undef USE_ALPHA_PIO */ + +/* BSD AMD64 iopl */ +/* #undef USE_AMD64_IOPL */ + +/* BSD /dev/io */ +/* #undef USE_DEV_IO */ + +/* BSD i386 iopl */ +/* #undef USE_I386_IOPL */ + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PCVT console */ +/* #undef PCVT_SUPPORT */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +#endif /* _XORG_CONFIG_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-server.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-server.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorg-server.h (revision 51223) @@ -0,0 +1,245 @@ +/* include/xorg-server.h. Generated by configure. */ +/* xorg-server.h.in -*- c -*- + * + * This file is the template file for the xorg-server.h file which gets + * installed as part of the SDK. The #defines in this file overlap + * with those from config.h, but only for those options that we want + * to export to external modules. Boilerplate autotool #defines such + * as HAVE_STUFF and PACKAGE_NAME is kept in config.h + * + * It is still possible to update config.h.in using autoheader, since + * autoheader only creates a .h.in file for the first + * AM_CONFIG_HEADER() line, and thus does not overwrite this file. + * + * However, it should be kept in sync with this file. + */ + +#ifndef _XORG_SERVER_H_ +#define _XORG_SERVER_H_ + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/opt/debrix/lib/X11/fonts/misc/,/opt/debrix/lib/X11/fonts/TTF/,/opt/debrix/lib/X11/fonts/OTF,/opt/debrix/lib/X11/fonts/Type1/,/opt/debrix/lib/X11/fonts/CID/,/opt/debrix/lib/X11/fonts/100dpi/,/opt/debrix/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Building with libdl */ +#define DLOPEN_SUPPORT 1 + +/* Build DPMS extension */ +#define DPMSExtension 1 + +/* Built-in output drivers */ +#define DRIVERS {} + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Include handhelds.org h3600 touchscreen driver */ +/* #undef H3600_TS */ + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* Support SHM */ +#define HAS_SHM 1 + +/* Built-in input drivers */ +#define IDRIVERS {} + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM Extension */ +#define MITSHM 1 + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Need XFree86 helper functions */ +#define NEED_XF86_PROTOTYPES 1 + +/* Need XFree86 typedefs */ +#define NEED_XF86_TYPES 1 + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Support RANDR extension */ +#define RANDR 1 + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Enable touchscreen support */ +/* #undef TOUCHSCREEN */ + +/* Support tslib touchscreen abstraction library */ +/* #undef TSLIB */ + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* Use builtin rgb color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* unaligned word accesses behave as expected */ +/* #undef WORKING_UNALIGNED_INT */ + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Support Xdmcp */ +#define XDMCP 1 + +/* Build XFree86 BigFont extension */ +#define XF86BIGFONT 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Enable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Support loadable input and output drivers */ +/* #undef XLOADABLE */ + +/* Build DRI extension */ +#define XF86DRI 1 + +/* Build Xorg server */ +#define XORGSERVER 1 + +/* Vendor release */ +#define XORG_RELEASE "Release 7.0" + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((0) * 100000) + ((0) * 1000) + 0) + +/* Build Xv Extension */ +#define XvExtension 1 + +/* Build XvMC Extension */ +#define XvMCExtension 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv Extension */ +#define XV 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 + +/* Vendor web address for support */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Location of configuration file */ +#define __XCONFIGFILE__ "xorg.conf" + +/* XKB default rules */ +#define __XKBDEFRULES__ "xorg" + +/* Name of X server */ +#define __XSERVERNAME__ "Xorg" + +/* Define to 1 if unsigned long is 64 bits. */ +#define _XSERVER64 1 + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PCVT console */ +/* #undef PCVT_SUPPORT */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +#endif /* _XORG_SERVER_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorgVersion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorgVersion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xorgVersion.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/xorgVersion.h,v 1.3 2004/08/16 02:07:53 kem Exp $ */ + +/* + * Copyright (c) 2004, X.Org Foundation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef XORG_VERSION_H +# define XORG_VERSION_H + +# ifndef XORG_VERSION_CURRENT +# error +# endif + +# define XORG_VERSION_NUMERIC(major,minor,patch,snap,dummy) \ + (((major) * 10000000) + ((minor) * 100000) + ((patch) * 1000) + snap) + +# define XORG_GET_MAJOR_VERSION(vers) ((vers) / 10000000) +# define XORG_GET_MINOR_VERSION(vers) (((vers) % 10000000) / 100000) +# define XORG_GET_PATCH_VERSION(vers) (((vers) % 100000) / 1000) +# define XORG_GET_SNAP_VERSION(vers) ((vers) % 1000) + +# define XORG_VERSION_MAJOR XORG_GET_MAJOR_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_MINOR XORG_GET_MINOR_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_PATCH XORG_GET_PATCH_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_SNAP XORG_GET_SNAP_VERSION(XORG_VERSION_CURRENT) + +#endif +/* $XdotOrg: xc/programs/Xserver/hw/xfree86/xorgVersion.h,v 1.3 2004/08/16 02:07:53 kem Exp $ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xpr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xpr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xpr.h (revision 51223) @@ -0,0 +1,49 @@ +/* + * Xplugin rootless implementation + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XdotOrg: xc/programs/Xserver/hw/darwin/quartz/xpr/xpr.h,v 1.2 2004/04/23 19:16:52 eich Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/xpr.h,v 1.4 2003/11/12 20:21:52 torrey Exp $ */ + +#ifndef XPR_H +#define XPR_H + +#include "screenint.h" + +extern Bool QuartzModeBundleInit(void); + +void AppleDRIExtensionInit(void); +void xprAppleWMInit(void); +Bool xprInit(ScreenPtr pScreen); +Bool xprIsX11Window(void *nsWindow, int windowNumber); +void xprHideWindows(Bool hide); + +Bool QuartzInitCursor(ScreenPtr pScreen); +void QuartzSuspendXCursor(ScreenPtr pScreen); +void QuartzResumeXCursor(ScreenPtr pScreen, int x, int y); + +#endif /* XPR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xqueue.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xqueue.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xqueue.h (revision 51223) @@ -0,0 +1,12 @@ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_XQUEUE_H_ +#define _XF86_XQUEUE_H_ + +Bool XqueueMousePreInit(InputInfoPtr pInfo, const char *protocol, int flags); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xtest1dd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xtest1dd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xtest1dd.h (revision 51223) @@ -0,0 +1,127 @@ +/* $XFree86: xc/programs/Xserver/Xext/xtest1dd.h,v 3.2 2001/08/01 00:44:44 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef XTEST1DD_H +#define XTEST1DD_H 1 + +extern short xtest_mousex; +extern short xtest_mousey; +extern int playback_on; +extern ClientPtr current_xtest_client; +extern ClientPtr playback_client; +extern KeyCode xtest_command_key; + +extern void stop_stealing_input( + void +); + +extern void +steal_input( + ClientPtr /* client */, + CARD32 /* mode */ +); + +extern void +flush_input_actions( + void +); + +extern void +XTestStealJumpData( + int /* jx */, + int /* jy */, + int /* dev_type */ +); + +extern void +XTestStealMotionData( + int /* dx */, + int /* dy */, + int /* dev_type */, + int /* mx */, + int /* my */ +); + +extern Bool +XTestStealKeyData( + unsigned /* keycode */, + int /* keystate */, + int /* dev_type */, + int /* locx */, + int /* locy */ +); + +extern void +parse_fake_input( + ClientPtr /* client */, + char * /* req */ +); + +extern void +XTestComputeWaitTime( + struct timeval * /* waittime */ +); + +extern int +XTestProcessInputAction( + int /* readable */, + struct timeval * /* waittime */ +); + +extern void +abort_play_back( + void +); + +extern void +return_input_array_size( + ClientPtr /* client */ +); + +extern void XTestGenerateEvent( + int /* dev_type */, + int /* keycode */, + int /* keystate */, + int /* mousex */, + int /* mousey */ +); + +extern void XTestGetPointerPos( + short * /* fmousex */, + short * /* fmousey */ +); + +extern void XTestJumpPointer( + int /* jx */, + int /* jy */, + int /* dev_type */ +); + +#endif /* XTEST1DD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdisp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdisp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdisp.h (revision 51223) @@ -0,0 +1,3 @@ +/* $XFree86$ */ + +extern void XineramifyXv(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdix.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdix.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvdix.h (revision 51223) @@ -0,0 +1,291 @@ +/*********************************************************** +Copyright 1991 by Digital Equipment Corporation, Maynard, Massachusetts, +and the Massachusetts Institute of Technology, Cambridge, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the names of Digital or MIT not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/Xext/xvdix.h,v 1.7 2001/05/07 21:37:51 tsi Exp $ */ + +#ifndef XVDIX_H +#define XVDIX_H +/* +** File: +** +** xvdix.h --- Xv device independent header file +** +** Author: +** +** David Carver (Digital Workstation Engineering/Project Athena) +** +** Revisions: +** +** 29.08.91 Carver +** - removed UnrealizeWindow wrapper unrealizing windows no longer +** preempts video +** +** 11.06.91 Carver +** - changed SetPortControl to SetPortAttribute +** - changed GetPortControl to GetPortAttribute +** - changed QueryBestSize +** +** 15.05.91 Carver +** - version 2.0 upgrade +** +** 24.01.91 Carver +** - version 1.4 upgrade +** +*/ + +#include "scrnintstr.h" +#include + +extern int XvScreenIndex; +extern unsigned long XvExtensionGeneration; +extern unsigned long XvScreenGeneration; +extern unsigned long XvResourceGeneration; + +extern int XvReqCode; +extern int XvEventBase; +extern int XvErrorBase; + +extern unsigned long XvRTPort; +extern unsigned long XvRTEncoding; +extern unsigned long XvRTGrab; +extern unsigned long XvRTVideoNotify; +extern unsigned long XvRTVideoNotifyList; +extern unsigned long XvRTPortNotify; + +typedef struct { + int numerator; + int denominator; +} XvRationalRec, *XvRationalPtr; + +typedef struct { + char depth; + unsigned long visual; +} XvFormatRec, *XvFormatPtr; + +typedef struct { + unsigned long id; + ClientPtr client; +} XvGrabRec, *XvGrabPtr; + +typedef struct _XvVideoNotifyRec { + struct _XvVideoNotifyRec *next; + ClientPtr client; + unsigned long id; + unsigned long mask; +} XvVideoNotifyRec, *XvVideoNotifyPtr; + +typedef struct _XvPortNotifyRec { + struct _XvPortNotifyRec *next; + ClientPtr client; + unsigned long id; +} XvPortNotifyRec, *XvPortNotifyPtr; + +typedef struct { + int id; + ScreenPtr pScreen; + char *name; + unsigned short width, height; + XvRationalRec rate; +} XvEncodingRec, *XvEncodingPtr; + +typedef struct _XvAttributeRec { + int flags; + int min_value; + int max_value; + char *name; +} XvAttributeRec, *XvAttributePtr; + +typedef struct { + int id; + int type; + int byte_order; + char guid[16]; + int bits_per_pixel; + int format; + int num_planes; + + /* for RGB formats only */ + int depth; + unsigned int red_mask; + unsigned int green_mask; + unsigned int blue_mask; + + /* for YUV formats only */ + unsigned int y_sample_bits; + unsigned int u_sample_bits; + unsigned int v_sample_bits; + unsigned int horz_y_period; + unsigned int horz_u_period; + unsigned int horz_v_period; + unsigned int vert_y_period; + unsigned int vert_u_period; + unsigned int vert_v_period; + char component_order[32]; + int scanline_order; +} XvImageRec, *XvImagePtr; + +typedef struct { + unsigned long base_id; + unsigned char type; + char *name; + int nEncodings; + XvEncodingPtr pEncodings; + int nFormats; + XvFormatPtr pFormats; + int nAttributes; + XvAttributePtr pAttributes; + int nImages; + XvImagePtr pImages; + int nPorts; + struct _XvPortRec *pPorts; + ScreenPtr pScreen; + int (* ddAllocatePort)(unsigned long, struct _XvPortRec*, + struct _XvPortRec**); + int (* ddFreePort)(struct _XvPortRec*); + int (* ddPutVideo)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddPutStill)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddGetVideo)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddGetStill)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddStopVideo)(ClientPtr, struct _XvPortRec*, DrawablePtr); + int (* ddSetPortAttribute)(ClientPtr, struct _XvPortRec*, Atom, INT32); + int (* ddGetPortAttribute)(ClientPtr, struct _XvPortRec*, Atom, INT32*); + int (* ddQueryBestSize)(ClientPtr, struct _XvPortRec*, CARD8, + CARD16, CARD16,CARD16, CARD16, + unsigned int*, unsigned int*); + int (* ddPutImage)(ClientPtr, DrawablePtr, struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16, + XvImagePtr, unsigned char*, Bool, + CARD16, CARD16); + int (* ddQueryImageAttributes)(ClientPtr, struct _XvPortRec*, XvImagePtr, + CARD16*, CARD16*, int*, int*); + DevUnion devPriv; +} XvAdaptorRec, *XvAdaptorPtr; + +typedef struct _XvPortRec { + unsigned long id; + XvAdaptorPtr pAdaptor; + XvPortNotifyPtr pNotify; + DrawablePtr pDraw; + ClientPtr client; + XvGrabRec grab; + TimeStamp time; + DevUnion devPriv; +} XvPortRec, *XvPortPtr; + +#define LOOKUP_PORT(_id, client)\ + ((XvPortPtr)LookupIDByType(_id, XvRTPort)) + +#define LOOKUP_ENCODING(_id, client)\ + ((XvEncodingPtr)LookupIDByType(_id, XvRTEncoding)) + +#define LOOKUP_VIDEONOTIFY_LIST(_id, client)\ + ((XvVideoNotifyPtr)LookupIDByType(_id, XvRTVideoNotifyList)) + +#define LOOKUP_PORTNOTIFY_LIST(_id, client)\ + ((XvPortNotifyPtr)LookupIDByType(_id, XvRTPortNotifyList)) + +typedef struct { + int version, revision; + int nAdaptors; + XvAdaptorPtr pAdaptors; + DestroyWindowProcPtr DestroyWindow; + DestroyPixmapProcPtr DestroyPixmap; + CloseScreenProcPtr CloseScreen; + Bool (* ddCloseScreen)(int, ScreenPtr); + int (* ddQueryAdaptors)(ScreenPtr, XvAdaptorPtr*, int*); + DevUnion devPriv; +} XvScreenRec, *XvScreenPtr; + +#define SCREEN_PROLOGUE(pScreen, field)\ + ((pScreen)->field = \ + ((XvScreenPtr) \ + (pScreen)->devPrivates[XvScreenIndex].ptr)->field) + +#define SCREEN_EPILOGUE(pScreen, field, wrapper)\ + ((pScreen)->field = wrapper) + +/* Errors */ + +#define _XvBadPort (XvBadPort+XvErrorBase) +#define _XvBadEncoding (XvBadEncoding+XvErrorBase) + +extern int ProcXvDispatch(ClientPtr); +extern int SProcXvDispatch(ClientPtr); + +extern void XvExtensionInit(void); +extern int XvScreenInit(ScreenPtr); +extern int XvGetScreenIndex(void); +extern unsigned long XvGetRTPort(void); +extern int XvdiSendPortNotify(XvPortPtr, Atom, INT32); +extern int XvdiVideoStopped(XvPortPtr, int); + +extern int XvdiPutVideo(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiPutStill(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiGetVideo(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiGetStill(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiPutImage(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16, + XvImagePtr, unsigned char*, Bool, + CARD16, CARD16); +extern int XvdiSelectVideoNotify(ClientPtr, DrawablePtr, BOOL); +extern int XvdiSelectPortNotify(ClientPtr, XvPortPtr, BOOL); +extern int XvdiSetPortAttribute(ClientPtr, XvPortPtr, Atom, INT32); +extern int XvdiGetPortAttribute(ClientPtr, XvPortPtr, Atom, INT32*); +extern int XvdiStopVideo(ClientPtr, XvPortPtr, DrawablePtr); +extern int XvdiPreemptVideo(ClientPtr, XvPortPtr, DrawablePtr); +extern int XvdiMatchPort(XvPortPtr, DrawablePtr); +extern int XvdiGrabPort(ClientPtr, XvPortPtr, Time, int *); +extern int XvdiUngrabPort( ClientPtr, XvPortPtr, Time); + + +#if !defined(UNIXCPP) + +#define XVCALL(name) Xv##name + +#else + +#define XVCALL(name) Xv/**/name + +#endif + + +#endif /* XVDIX_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmcext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmcext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmcext.h (revision 51223) @@ -0,0 +1,116 @@ +/* $XFree86: xc/programs/Xserver/Xext/xvmcext.h,v 1.1 2001/04/07 11:04:21 alanh Exp $ */ + +#ifndef _XVMC_H +#define _XVMC_H +#include +#include "xvdix.h" + +typedef struct { + int num_xvimages; + int *xvimage_ids; +} XvMCImageIDList; + +typedef struct { + int surface_type_id; + int chroma_format; + int color_description; + unsigned short max_width; + unsigned short max_height; + unsigned short subpicture_max_width; + unsigned short subpicture_max_height; + int mc_type; + int flags; + XvMCImageIDList *compatible_subpictures; +} XvMCSurfaceInfoRec, *XvMCSurfaceInfoPtr; + +typedef struct { + XID context_id; + ScreenPtr pScreen; + int adapt_num; + int surface_type_id; + unsigned short width; + unsigned short height; + CARD32 flags; + int refcnt; + pointer port_priv; + pointer driver_priv; +} XvMCContextRec, *XvMCContextPtr; + +typedef struct { + XID surface_id; + int surface_type_id; + XvMCContextPtr context; + pointer driver_priv; +} XvMCSurfaceRec, *XvMCSurfacePtr; + + +typedef struct { + XID subpicture_id; + int xvimage_id; + unsigned short width; + unsigned short height; + int num_palette_entries; + int entry_bytes; + char component_order[4]; + XvMCContextPtr context; + pointer driver_priv; +} XvMCSubpictureRec, *XvMCSubpicturePtr; + +typedef int (*XvMCCreateContextProcPtr) ( + XvPortPtr port, + XvMCContextPtr context, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroyContextProcPtr) ( + XvMCContextPtr context +); + +typedef int (*XvMCCreateSurfaceProcPtr) ( + XvMCSurfacePtr surface, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroySurfaceProcPtr) ( + XvMCSurfacePtr surface +); + +typedef int (*XvMCCreateSubpictureProcPtr) ( + XvMCSubpicturePtr subpicture, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroySubpictureProcPtr) ( + XvMCSubpicturePtr subpicture +); + + +typedef struct { + XvAdaptorPtr xv_adaptor; + int num_surfaces; + XvMCSurfaceInfoPtr *surfaces; + int num_subpictures; + XvImagePtr *subpictures; + XvMCCreateContextProcPtr CreateContext; + XvMCDestroyContextProcPtr DestroyContext; + XvMCCreateSurfaceProcPtr CreateSurface; + XvMCDestroySurfaceProcPtr DestroySurface; + XvMCCreateSubpictureProcPtr CreateSubpicture; + XvMCDestroySubpictureProcPtr DestroySubpicture; +} XvMCAdaptorRec, *XvMCAdaptorPtr; + +void XvMCExtensionInit(void); + +int XvMCScreenInit(ScreenPtr pScreen, int num, XvMCAdaptorPtr adapt); + +XvImagePtr XvMCFindXvImage(XvPortPtr pPort, CARD32 id); + +int xf86XvMCRegisterDRInfo(ScreenPtr pScreen, char *name, + char *busID, int major, int minor, + int patchLevel); + + +#endif /* _XVMC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmodproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmodproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/xvmodproc.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XFree86: xc/programs/Xserver/Xext/xvmodproc.h,v 1.2 2001/03/05 04:51:55 mvojkovi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "xvmcext.h" + +extern int (*XvGetScreenIndexProc)(void); +extern unsigned long (*XvGetRTPortProc)(void); +extern int (*XvScreenInitProc)(ScreenPtr); +extern int (*XvMCScreenInitProc)(ScreenPtr, int, XvMCAdaptorPtr); + +extern void XvRegister(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/zx1PCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/zx1PCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.0.1/zx1PCI.h (revision 51223) @@ -0,0 +1,40 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.h,v 1.1 2003/02/23 20:26:49 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_ZX1_H +#define PCI_ZX1_H 1 + +#include + +void xf86PreScanZX1(void); +void xf86PostScanZX1(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/460gxPCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/460gxPCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/460gxPCI.h (revision 51223) @@ -0,0 +1,42 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/460gxPCI.h,v 1.1 2003/01/02 18:12:48 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_460GX_H +#define PCI_460GX_H 1 + +#include +#include + +Bool xorgProbe460GX(scanpciWrapperOpt flags); +void xf86PreScan460GX(void); +void xf86PostScan460GX(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/AttrValid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/AttrValid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/AttrValid.h (revision 51223) @@ -0,0 +1,216 @@ +/* $Xorg: AttrValid.h,v 1.4 2001/03/14 18:43:40 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_AttrValid_h +#define _Xp_AttrValid_h + +#include +#include "Oid.h" + +#define XpNumber(a) (sizeof(a) / sizeof(*(a))) + +/* + * Attribute pool validation valid values and defaults + */ +typedef struct +{ + XpOidList* valid_content_orientations_supported; + XpOidList* default_content_orientations_supported; + + XpOidDocFmtList* valid_document_formats_supported; + XpOidDocFmtList* default_document_formats_supported; + + XpOidList* valid_input_trays; + XpOidList* valid_medium_sizes; + + XpOidList* valid_plexes_supported; + XpOidList* default_plexes_supported; + + XpOidCardList* valid_printer_resolutions_supported; + XpOidCardList* default_printer_resolutions_supported; + + XpOidDocFmtList* valid_xp_embedded_formats_supported; + XpOidDocFmtList* default_xp_embedded_formats_supported; + + XpOidList* valid_xp_listfonts_modes_supported; + XpOidList* default_xp_listfonts_modes_supported; + + XpOidDocFmtList* valid_xp_raw_formats_supported; + XpOidDocFmtList* default_xp_raw_formats_supported; + + XpOidList* valid_xp_setup_proviso; + + XpOidDocFmt* default_document_format; + XpOidList* valid_available_compressions_supported; + XpOidList* default_available_compressions_supported; + +} XpValidatePoolsRec; + +/* + * XpOid resource access + */ +#define XpGetStringAttr(pContext, pool, oid) \ + (const char*)XpGetOneAttribute(pContext, pool, (char*)XpOidString(oid)) +#define XpPutStringAttr(pContext, pool, oid, value) \ + XpPutOneAttribute(pContext, pool, XpOidString(oid), value) + +#ifdef _XP_PRINT_SERVER_ /* needed for XpContextPtr in Printstr.h */ + +/* + * XpOid-valued attribute access + */ +XpOid XpGetOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oid_list); +void XpPutOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + XpOid value_oid); +void XpValidateOidAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oids, + XpOid default_oid); +/* + * cardinal-valued attribute access + */ +unsigned long XpGetCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_card_list); +void XpPutCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + unsigned long value_card); +void XpValidateCardAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_cards, + unsigned long default_card); +/* + * XpOidList-valued attribute access + */ +XpOidList* XpGetListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oid_list); +void XpPutListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* list); +void XpValidateListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_oids, + const XpOidList* default_oids); +/* + * XpOidCardList-valued attribute access + */ +XpOidCardList* XpGetCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_card_list); +void XpPutCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* list); +void XpValidateCardListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidCardList* valid_cards, + const XpOidCardList* default_cards); +/* + * XpOidDocFmtList-valued attribute access + */ +XpOidDocFmtList* XpGetDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* valid_fmt_list); +void XpPutDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* list); +void XpValidateDocFmtListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidDocFmtList* valid_fmts, + const XpOidDocFmtList* default_fmts); +/* + * XpOidMediumSS-valued attribute access + */ +XpOidMediumSS* XpGetMediumSSAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_trays, + const XpOidList* valid_sizes); +void XpPutMediumSSAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidMediumSS* msss); +const XpOidMediumSS* XpGetDefaultMediumSS(void); + +/* + * XpOidTrayMediumList-valued attribute access + */ +XpOidTrayMediumList* XpGetTrayMediumListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidList* valid_trays, + const XpOidMediumSS* msss); +void XpPutTrayMediumListAttr(XpContextPtr pContext, + XPAttributes pool, + XpOid oid, + const XpOidTrayMediumList* tm); +/* + * Attribute pool validation + */ +void XpValidateAttributePool(XpContextPtr pContext, + XPAttributes pool, + const XpValidatePoolsRec* vpr); +void XpValidatePrinterPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidateJobPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidateDocumentPool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); +void XpValidatePagePool(XpContextPtr pContext, + const XpValidatePoolsRec* vpr); + +#endif /* _XP_PRINT_SERVER_ */ + +#endif /* _Xp_AttrValid_h - don't add anything after this line */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BT.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BT.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BT.h (revision 51223) @@ -0,0 +1,33 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/BT.h,v 1.2 1998/07/25 16:57:17 dawes Exp $ */ + +#include "xf86RamDac.h" + +RamDacHelperRecPtr BTramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void BTramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void BTramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void BTramdacSetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); + +#define ATT20C504_RAMDAC (VENDOR_BT << 16) | 0x00 +#define ATT20C505_RAMDAC (VENDOR_BT << 16) | 0x01 +#define BT485_RAMDAC (VENDOR_BT << 16) | 0x02 + +/* + * BT registers + */ + +#define BT_WRITE_ADDR 0x00 +#define BT_RAMDAC_DATA 0x01 +#define BT_PIXEL_MASK 0x02 +#define BT_READ_ADDR 0x03 +#define BT_CURS_WR_ADDR 0x04 +#define BT_CURS_DATA 0x05 +#define BT_COMMAND_REG_0 0x06 +#define BT_CURS_RD_ADDR 0x07 +#define BT_COMMAND_REG_1 0x08 +#define BT_COMMAND_REG_2 0x09 +#define BT_STATUS_REG 0x0A +#define BT_CURS_RAM_DATA 0x0B +#define BT_CURS_X_LOW 0x0C +#define BT_CURS_X_HIGH 0x0D +#define BT_CURS_Y_LOW 0x0E +#define BT_CURS_Y_HIGH 0x0F Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BTPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BTPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/BTPriv.h (revision 51223) @@ -0,0 +1,21 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/BTPriv.h,v 1.1.2.1 1998/07/18 17:54:00 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "BT.h" + +typedef struct { + char *DeviceName; +} xf86BTramdacInfo; + +extern xf86BTramdacInfo BTramdacDeviceInfo[]; + +#ifdef INIT_BT_RAMDAC_INFO +xf86BTramdacInfo BTramdacDeviceInfo[] = { + {"AT&T 20C504"}, + {"AT&T 20C505"}, + {"BT485/484"} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Canvas.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Canvas.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Canvas.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + +Copyright 1987, 1998 The Open Group +Copyright 2002 Red Hat Inc., Durham, North Carolina. + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + * This file was originally taken from xc/lib/Xaw/Template.h + */ + +#ifndef _Canvas_h +#define _Canvas_h + +#include + +#define XtNcanvasExposeCallback "canvasExposeCallback" +#define XtCcanvasExposeCallback "CanvasExposeCallback" +#define XtNcanvasResizeCallback "canvasResizeCallback" +#define XtCcanvasResizeCallback "CanvasResizeCallback" + +typedef struct _CanvasClassRec *CanvasWidgetClass; +typedef struct _CanvasRec *CanvasWidget; +extern WidgetClass canvasWidgetClass; + +typedef struct _CanvasExposeDataRec { + Widget w; + XEvent *event; + Region region; +} CanvasExposeDataRec, *CanvasExposeDataPtr; + +#endif /* _Canvas_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/CanvasP.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/CanvasP.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/CanvasP.h (revision 51223) @@ -0,0 +1,66 @@ +/* $XFree86$ */ +/* + +Copyright 1987, 1998 The Open Group +Copyright 2002 Red Hat Inc., Durham, North Carolina. + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + * This file was originally taken from xc/lib/Xaw/TemplateP.h + */ + +#ifndef _CanvasP_h +#define _CanvasP_h + +#include "Canvas.h" + +/* include superclass private header file */ +#include + +typedef struct { + XtPointer extension; +} CanvasClassPart; + +typedef struct _CanvasClassRec { + CoreClassPart core_class; + CanvasClassPart canvas_class; +} CanvasClassRec; + +extern CanvasClassRec canvasClassRec; + +typedef struct { + XtCallbackList input_callback; + XtCallbackList expose_callback; + XtCallbackList resize_callback; +} CanvasPart; + +typedef struct _CanvasRec { + CorePart core; + CanvasPart canvas; +} CanvasRec; + +#endif /* _CanvasP_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ChkNotMaskEv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ChkNotMaskEv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ChkNotMaskEv.h (revision 51223) @@ -0,0 +1,41 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for #XCheckNotMaskEvent function. \see ChkNotMaskEv.c */ + +#ifndef _CHKNOTMASKEV_H_ +#define _CHKNOTMASKEV_H_ +extern Bool XCheckNotMaskEvent (Display *dpy, long mask, XEvent *event); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Configint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Configint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Configint.h (revision 51223) @@ -0,0 +1,226 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/Configint.h,v 1.21 2003/08/24 17:37:07 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * These definitions are used through out the configuration file parser, but + * they should not be visible outside of the parser. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _Configint_h_ +#define _Configint_h_ + +#include +#include +#include +#include +#include "xf86Parser.h" + +typedef struct +{ + int num; /* returned number */ + char *str; /* private copy of the return-string */ + double realnum; /* returned number as a real */ +} +LexRec, *LexPtr; + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#include "configProcs.h" +#include +#define xf86confmalloc malloc +#define xf86confrealloc realloc +#define xf86confcalloc calloc +#define xf86conffree free + +#define TestFree(a) if (a) { xf86conffree (a); a = NULL; } + +#define parsePrologue(typeptr,typerec) typeptr ptr; \ +if( (ptr=(typeptr)xf86confcalloc(1,sizeof(typerec))) == NULL ) { return NULL; } \ +memset(ptr,0,sizeof(typerec)); + +#define parsePrologueVoid(typeptr,typerec) int token; typeptr ptr; \ +if( (ptr=(typeptr)xf86confcalloc(1,sizeof(typerec))) == NULL ) { return; } \ +memset(ptr,0,sizeof(typerec)); + +#define HANDLE_RETURN(f,func)\ +if ((ptr->f=func) == NULL)\ +{\ + CLEANUP (ptr);\ + return (NULL);\ +} + +#define HANDLE_LIST(field,func,type)\ +{\ +type p = func ();\ +if (p == NULL)\ +{\ + CLEANUP (ptr);\ + return (NULL);\ +}\ +else\ +{\ + ptr->field = (type) xf86addListItem ((glp) ptr->field, (glp) p);\ +}\ +} + +#define Error(a,b) do { \ + xf86parseError (a, b); CLEANUP (ptr); return NULL; \ + } while (0) + +/* + * These are defines for error messages to promote consistency. + * error messages are preceded by the line number, section and file name, + * so these messages should be about the specific keyword and syntax in error. + * To help limit namespace polution, end each with _MSG. + * limit messages to 70 characters if possible. + */ + +#define BAD_OPTION_MSG \ +"The Option keyword requires 1 or 2 quoted strings to follow it." +#define INVALID_KEYWORD_MSG \ +"\"%s\" is not a valid keyword in this section." +#define INVALID_SECTION_MSG \ +"\"%s\" is not a valid section name." +#define UNEXPECTED_EOF_MSG \ +"Unexpected EOF. Missing EndSection keyword?" +#define QUOTE_MSG \ +"The %s keyword requires a quoted string to follow it." +#define NUMBER_MSG \ +"The %s keyword requires a number to follow it." +#define POSITIVE_INT_MSG \ +"The %s keyword requires a positive integer to follow it." +#define ZAXISMAPPING_MSG \ +"The ZAxisMapping keyword requires 2 positive numbers or X or Y to follow it." +#define AUTOREPEAT_MSG \ +"The AutoRepeat keyword requires 2 numbers (delay and rate) to follow it." +#define XLEDS_MSG \ +"The XLeds keyword requries one or more numbers to follow it." +#define DACSPEED_MSG \ +"The DacSpeed keyword must be followed by a list of up to %d numbers." +#define DISPLAYSIZE_MSG \ +"The DisplaySize keyword must be followed by the width and height in mm." +#define HORIZSYNC_MSG \ +"The HorizSync keyword must be followed by a list of numbers or ranges." +#define VERTREFRESH_MSG \ +"The VertRefresh keyword must be followed by a list of numbers or ranges." +#define VIEWPORT_MSG \ +"The Viewport keyword must be followed by an X and Y value." +#define VIRTUAL_MSG \ +"The Virtual keyword must be followed by a width and height value." +#define WEIGHT_MSG \ +"The Weight keyword must be followed by red, green and blue values." +#define BLACK_MSG \ +"The Black keyword must be followed by red, green and blue values." +#define WHITE_MSG \ +"The White keyword must be followed by red, green and blue values." +#define SCREEN_MSG \ +"The Screen keyword must be followed by an optional number, a screen name\n" \ +"\tin quotes, and optional position/layout information." +#define INVALID_SCR_MSG \ +"Invalid Screen line." +#define INPUTDEV_MSG \ +"The InputDevice keyword must be followed by an input device name in quotes." +#define INACTIVE_MSG \ +"The Inactive keyword must be followed by a Device name in quotes." +#define UNDEFINED_SCREEN_MSG \ +"Undefined Screen \"%s\" referenced by ServerLayout \"%s\"." +#define UNDEFINED_MONITOR_MSG \ +"Undefined Monitor \"%s\" referenced by Screen \"%s\"." +#define UNDEFINED_MODES_MSG \ +"Undefined Modes Section \"%s\" referenced by Monitor \"%s\"." +#define UNDEFINED_DEVICE_MSG \ +"Undefined Device \"%s\" referenced by Screen \"%s\"." +#define UNDEFINED_ADAPTOR_MSG \ +"Undefined VideoAdaptor \"%s\" referenced by Screen \"%s\"." +#define ADAPTOR_REF_TWICE_MSG \ +"VideoAdaptor \"%s\" already referenced by Screen \"%s\"." +#define UNDEFINED_DEVICE_LAY_MSG \ +"Undefined Device \"%s\" referenced by ServerLayout \"%s\"." +#define UNDEFINED_INPUT_MSG \ +"Undefined InputDevice \"%s\" referenced by ServerLayout \"%s\"." +#define NO_IDENT_MSG \ +"This section must have an Identifier line." +#define ONLY_ONE_MSG \ +"This section must have only one of either %s line." +#define UNDEFINED_DRIVER_MSG \ +"Device section \"%s\" must have a Driver line." +#define UNDEFINED_INPUTDRIVER_MSG \ +"InputDevice section \"%s\" must have a Driver line." +#define INVALID_GAMMA_MSG \ +"gamma correction value(s) expected\n either one value or three r/g/b values." +#define GROUP_MSG \ +"The Group keyword must be followed by either a group name in quotes or\n" \ +"\ta numerical group id." +#define MULTIPLE_MSG \ +"Multiple \"%s\" lines." + +/* Warning messages */ +#define OBSOLETE_MSG \ +"Ignoring obsolete keyword \"%s\"." +#define MOVED_TO_FLAGS_MSG \ +"Keyword \"%s\" is now an Option flag in the ServerFlags section." + +#endif /* _Configint_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/DiPrint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/DiPrint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/DiPrint.h (revision 51223) @@ -0,0 +1,81 @@ +/* $Xorg: DiPrint.h,v 1.3 2000/08/17 19:48:04 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* + * The XpDiListEntry struct is the type of each element of the array + * handed back to the extension code to handle a GetPrinterList request. + * We don't use the printerDb directly because of the desire to handle + * multiple locales. Creating this new array for each GetPrinterList + * request will allow us to build it with the description in the locale of + * the requesting client. + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XpDiPrint_H_ +#define _XpDiPrint_H_ 1 + +#include "scrnintstr.h" + +typedef struct _diListEntry { + char *name; + char *description; + char *localeName; + unsigned long rootWinId; +} XpDiListEntry; + +extern void XpDiFreePrinterList(XpDiListEntry **list); + +extern XpDiListEntry **XpDiGetPrinterList( + int nameLen, + char *name, + int localeLen, + char *locale); + +extern char * XpDiGetDriverName(int index, char *printerName); + +extern WindowPtr XpDiValidatePrinter(char *printerName, int printerNameLen); + +extern int PrinterOptions(int argc, char **argv, int i); + +extern void PrinterUseMsg(void); + +extern void PrinterInitGlobals(void); + +extern void PrinterInitOutput(ScreenInfo *pScreenInfo, int argc, char **argv); + +extern void _XpVoidNoop(void); + +extern Bool _XpBoolNoop(void); + +#endif /* _XpDiPrint_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/EVIstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/EVIstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/EVIstruct.h (revision 51223) @@ -0,0 +1,60 @@ +/* $Xorg: EVIstruct.h,v 1.3 2000/08/17 19:47:55 cpqbld Exp $ */ +/************************************************************ +Copyright (c) 1997 by Silicon Graphics Computer Systems, Inc. +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright +notice appear in all copies and that both that copyright +notice and this permission notice appear in supporting +documentation, and that the name of Silicon Graphics not be +used in advertising or publicity pertaining to distribution +of the software without specific prior written permission. +Silicon Graphics makes no representation about the suitability +of this software for any purpose. It is provided "as is" +without any express or implied warranty. +SILICON GRAPHICS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS +SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SILICON +GRAPHICS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL +DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE +OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. +********************************************************/ +/* $XFree86: xc/programs/Xserver/Xext/EVIstruct.h,v 3.5 2003/07/16 01:38:28 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef EVI_STRUCT_H +#define EVI_STRUCT_H + +/* + ****************************************************************************** + ** Per-ddx data + ****************************************************************************** + */ + +typedef int (*GetVisualInfoProc)( + VisualID32*, + int, + xExtendedVisualInfo**, + int*, + VisualID32**, + int* +); + +typedef void (*FreeVisualInfoProc)( + xExtendedVisualInfo*, + VisualID32* +); +typedef struct _EviPrivRec { + GetVisualInfoProc getVisualInfo; + FreeVisualInfoProc freeVisualInfo; +} EviPrivRec, *EviPrivPtr; + +extern EviPrivPtr eviDDXInit(void); +extern void eviDDXReset(void); + +#endif /* EVI_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBM.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBM.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBM.h (revision 51223) @@ -0,0 +1,386 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/IBM.h,v 1.7 1999/02/12 22:52:11 hohndel Exp $ */ + +#include + +RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +void IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +unsigned long IBMramdac526CalculateMNPCForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP, unsigned long *rC); +unsigned long IBMramdac640CalculateMNPCForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP, unsigned long *rC); +void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr); +void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr); + +typedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr); +IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void); + +#define IBM524_RAMDAC ((VENDOR_IBM << 16) | 0x00) +#define IBM524A_RAMDAC ((VENDOR_IBM << 16) | 0x01) +#define IBM525_RAMDAC ((VENDOR_IBM << 16) | 0x02) +#define IBM526_RAMDAC ((VENDOR_IBM << 16) | 0x03) +#define IBM526DB_RAMDAC ((VENDOR_IBM << 16) | 0x04) +#define IBM528_RAMDAC ((VENDOR_IBM << 16) | 0x05) +#define IBM528A_RAMDAC ((VENDOR_IBM << 16) | 0x06) +#define IBM624_RAMDAC ((VENDOR_IBM << 16) | 0x07) +#define IBM624DB_RAMDAC ((VENDOR_IBM << 16) | 0x08) +#define IBM640_RAMDAC ((VENDOR_IBM << 16) | 0x09) + +/* + * IBM Ramdac registers + */ + +#define IBMRGB_REF_FREQ_1 14.31818 +#define IBMRGB_REF_FREQ_2 50.00000 + +#define IBMRGB_rev 0x00 +#define IBMRGB_id 0x01 +#define IBMRGB_misc_clock 0x02 +#define IBMRGB_sync 0x03 +#define IBMRGB_hsync_pos 0x04 +#define IBMRGB_pwr_mgmt 0x05 +#define IBMRGB_dac_op 0x06 +#define IBMRGB_pal_ctrl 0x07 +#define IBMRGB_sysclk 0x08 /* not RGB525 */ +#define IBMRGB_pix_fmt 0x0a +#define IBMRGB_8bpp 0x0b +#define IBMRGB_16bpp 0x0c +#define IBMRGB_24bpp 0x0d +#define IBMRGB_32bpp 0x0e +#define IBMRGB_pll_ctrl1 0x10 +#define IBMRGB_pll_ctrl2 0x11 +#define IBMRGB_pll_ref_div_fix 0x14 +#define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */ +#define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */ +/* #define IBMRGB_f0 0x20 */ + +#define IBMRGB_sysclk_n 0x15 +#define IBMRGB_sysclk_m 0x16 +#define IBMRGB_sysclk_p 0x17 +#define IBMRGB_sysclk_c 0x18 + +#define IBMRGB_m0 0x20 +#define IBMRGB_n0 0x21 +#define IBMRGB_p0 0x22 +#define IBMRGB_c0 0x23 +#define IBMRGB_m1 0x24 +#define IBMRGB_n1 0x25 +#define IBMRGB_p1 0x26 +#define IBMRGB_c1 0x27 +#define IBMRGB_m2 0x28 +#define IBMRGB_n2 0x29 +#define IBMRGB_p2 0x2a +#define IBMRGB_c2 0x2b +#define IBMRGB_m3 0x2c +#define IBMRGB_n3 0x2d +#define IBMRGB_p3 0x2e +#define IBMRGB_c3 0x2f + +#define IBMRGB_curs 0x30 +#define IBMRGB_curs_xl 0x31 +#define IBMRGB_curs_xh 0x32 +#define IBMRGB_curs_yl 0x33 +#define IBMRGB_curs_yh 0x34 +#define IBMRGB_curs_hot_x 0x35 +#define IBMRGB_curs_hot_y 0x36 +#define IBMRGB_curs_col1_r 0x40 +#define IBMRGB_curs_col1_g 0x41 +#define IBMRGB_curs_col1_b 0x42 +#define IBMRGB_curs_col2_r 0x43 +#define IBMRGB_curs_col2_g 0x44 +#define IBMRGB_curs_col2_b 0x45 +#define IBMRGB_curs_col3_r 0x46 +#define IBMRGB_curs_col3_g 0x47 +#define IBMRGB_curs_col3_b 0x48 +#define IBMRGB_border_col_r 0x60 +#define IBMRGB_border_col_g 0x61 +#define IBMRGB_botder_col_b 0x62 +#define IBMRGB_key 0x68 +#define IBMRGB_key_mask 0x6C +#define IBMRGB_misc1 0x70 +#define IBMRGB_misc2 0x71 +#define IBMRGB_misc3 0x72 +#define IBMRGB_misc4 0x73 /* not RGB525 */ +#define IBMRGB_key_control 0x78 +#define IBMRGB_dac_sense 0x82 +#define IBMRGB_misr_r 0x84 +#define IBMRGB_misr_g 0x86 +#define IBMRGB_misr_b 0x88 +#define IBMRGB_pll_vco_div_in 0x8e +#define IBMRGB_pll_ref_div_in 0x8f +#define IBMRGB_vram_mask_0 0x90 +#define IBMRGB_vram_mask_1 0x91 +#define IBMRGB_vram_mask_2 0x92 +#define IBMRGB_vram_mask_3 0x93 +#define IBMRGB_curs_array 0x100 + + + +/* Constants rgb525.h */ + +/* RGB525_REVISION_LEVEL */ +#define RGB525_PRODUCT_REV_LEVEL 0xf0 + +/* RGB525_ID */ +#define RGB525_PRODUCT_ID 0x01 + +/* RGB525_MISC_CTRL_1 */ +#define MISR_CNTL_ENABLE 0x80 +#define VMSK_CNTL_ENABLE 0x40 +#define PADR_RDMT_RDADDR 0x0 +#define PADR_RDMT_PAL_STATE 0x20 +#define SENS_DSAB_DISABLE 0x10 +#define SENS_SEL_BIT3 0x0 +#define SENS_SEL_BIT7 0x08 +#define VRAM_SIZE_32 0x0 +#define VRAM_SIZE_64 0x01 + +/* RGB525_MISC_CTRL_2 */ +#define PCLK_SEL_LCLK 0x0 +#define PCLK_SEL_PLL 0x40 +#define PCLK_SEL_EXT 0x80 +#define INTL_MODE_ENABLE 0x20 +#define BLANK_CNTL_ENABLE 0x10 +#define COL_RES_6BIT 0x0 +#define COL_RES_8BIT 0x04 +#define PORT_SEL_VGA 0x0 +#define PORT_SEL_VRAM 0x01 + +/* RGB525_MISC_CTRL_3 */ +#define SWAP_RB 0x80 +#define SWAP_WORD_LOHI 0x0 +#define SWAP_WORD_HILO 0x10 +#define SWAP_NIB_HILO 0x0 +#define SWAP_NIB_LOHI 0x02 + +/* RGB525_MISC_CLK_CTRL */ +#define DDOT_CLK_ENABLE 0x0 +#define DDOT_CLK_DISABLE 0x80 +#define SCLK_ENABLE 0x0 +#define SCLK_DISABLE 0x40 +#define B24P_DDOT_PLL 0x0 +#define B24P_DDOT_SCLK 0x20 +#define DDOT_DIV_PLL_1 0x0 +#define DDOT_DIV_PLL_2 0x02 +#define DDOT_DIV_PLL_4 0x04 +#define DDOT_DIV_PLL_8 0x06 +#define DDOT_DIV_PLL_16 0x08 +#define PLL_DISABLE 0x0 +#define PLL_ENABLE 0x01 + +/* RGB525_SYNC_CTRL */ +#define DLY_CNTL_ADD 0x0 +#define DLY_SYNC_NOADD 0x80 +#define CSYN_INVT_DISABLE 0x0 +#define CSYN_INVT_ENABLE 0x40 +#define VSYN_INVT_DISABLE 0x0 +#define VSYN_INVT_ENABLE 0x20 +#define HSYN_INVT_DISABLE 0x0 +#define HSYN_INVT_ENABLE 0x10 +#define VSYN_CNTL_NORMAL 0x0 +#define VSYN_CNTL_HIGH 0x04 +#define VSYN_CNTL_LOW 0x08 +#define VSYN_CNTL_DISABLE 0x0C +#define HSYN_CNTL_NORMAL 0x0 +#define HSYN_CNTL_HIGH 0x01 +#define HSYN_CNTL_LOW 0x02 +#define HSYN_CNTL_DISABLE 0x03 + +/* RGB525_HSYNC_CTRL */ +#define HSYN_POS(n) (n) + +/* RGB525_POWER_MANAGEMENT */ +#define SCLK_PWR_NORMAL 0x0 +#define SCLK_PWR_DISABLE 0x10 +#define DDOT_PWR_NORMAL 0x0 +#define DDOT_PWR_DISABLE 0x08 +#define SYNC_PWR_NORMAL 0x0 +#define SYNC_PWR_DISABLE 0x04 +#define ICLK_PWR_NORMAL 0x0 +#define ICLK_PWR_DISABLE 0x02 +#define DAC_PWR_NORMAL 0x0 +#define DAC_PWR_DISABLE 0x01 + +/* RGB525_DAC_OPERATION */ +#define SOG_DISABLE 0x0 +#define SOG_ENABLE 0x08 +#define BRB_NORMAL 0x0 +#define BRB_ALWAYS 0x04 +#define DSR_DAC_SLOW 0x02 +#define DSR_DAC_FAST 0x0 +#define DPE_DISABLE 0x0 +#define DPE_ENABLE 0x01 + +/* RGB525_PALETTE_CTRL */ +#define SIXBIT_LINEAR_ENABLE 0x0 +#define SIXBIT_LINEAR_DISABLE 0x80 +#define PALETTE_PARITION(n) (n) + +/* RGB525_PIXEL_FORMAT */ +#define PIXEL_FORMAT_4BPP 0x02 +#define PIXEL_FORMAT_8BPP 0x03 +#define PIXEL_FORMAT_16BPP 0x04 +#define PIXEL_FORMAT_24BPP 0x05 +#define PIXEL_FORMAT_32BPP 0x06 + +/* RGB525_8BPP_CTRL */ +#define B8_DCOL_INDIRECT 0x0 +#define B8_DCOL_DIRECT 0x01 + +/* RGB525_16BPP_CTRL */ +#define B16_DCOL_INDIRECT 0x0 +#define B16_DCOL_DYNAMIC 0x40 +#define B16_DCOL_DIRECT 0xC0 +#define B16_POL_FORCE_BYPASS 0x0 +#define B16_POL_FORCE_LOOKUP 0x20 +#define B16_ZIB 0x0 +#define B16_LINEAR 0x04 +#define B16_555 0x0 +#define B16_565 0x02 +#define B16_SPARSE 0x0 +#define B16_CONTIGUOUS 0x01 + +/* RGB525_24BPP_CTRL */ +#define B24_DCOL_INDIRECT 0x0 +#define B24_DCOL_DIRECT 0x01 + +/* RGB525_32BPP_CTRL */ +#define B32_POL_FORCE_BYPASS 0x0 +#define B32_POL_FORCE_LOOKUP 0x04 +#define B32_DCOL_INDIRECT 0x0 +#define B32_DCOL_DYNAMIC 0x01 +#define B32_DCOL_DIRECT 0x03 + +/* RGB525_PLL_CTRL_1 */ +#define REF_SRC_REFCLK 0x0 +#define REF_SRC_EXTCLK 0x10 +#define PLL_EXT_FS_3_0 0x0 +#define PLL_EXT_FS_2_0 0x01 +#define PLL_CNTL2_3_0 0x02 +#define PLL_CNTL2_2_0 0x03 + +/* RGB525_PLL_CTRL_2 */ +#define PLL_INT_FS_3_0(n) (n) +#define PLL_INT_FS_2_0(n) (n) + +/* RGB525_PLL_REF_DIV_COUNT */ +#define REF_DIV_COUNT(n) (n) + +/* RGB525_F0 - RGB525_F15 */ +#define VCO_DIV_COUNT(n) (n) + +/* RGB525_PLL_REFCLK values */ +#define RGB525_PLL_REFCLK_MHz(n) ((n)/2) + +/* RGB525_CURSOR_CONTROL */ +#define SMLC_PART_0 0x0 +#define SMLC_PART_1 0x40 +#define SMLC_PART_2 0x80 +#define SMLC_PART_3 0xC0 +#define PIX_ORDER_RL 0x0 +#define PIX_ORDER_LR 0x20 +#define LOC_READ_LAST 0x0 +#define LOC_READ_ACTUAL 0x10 +#define UPDT_CNTL_DELAYED 0x0 +#define UPDT_CNTL_IMMEDIATE 0x08 +#define CURSOR_SIZE_32 0x0 +#define CURSOR_SIZE_64 0x40 +#define CURSOR_MODE_OFF 0x0 +#define CURSOR_MODE_3_COLOR 0x01 +#define CURSOR_MODE_2_COLOR_HL 0x02 +#define CURSOR_MODE_2_COLOR 0x03 + +/* RGB525_REVISION_LEVEL */ +#define REVISION_LEVEL 0xF0 /* predefined */ + +/* RGB525_ID */ +#define ID_CODE 0x01 /* predefined */ + +/* MISR status */ +#define RGB525_MISR_DONE 0x01 + +/* the IBMRGB640 is rather different from the rest of the RAMDACs, + so we define a completely new set of register names for it */ +#define RGB640_SER_07_00 0x02 +#define RGB640_SER_15_08 0x03 +#define RGB640_SER_23_16 0x04 +#define RGB640_SER_31_24 0x05 +#define RGB640_SER_WID_03_00 0x06 +#define RGB640_SER_WID_07_04 0x07 +#define RGB640_SER_MODE 0x08 +#define IBM640_SER_2_1 0x00 +#define IBM640_SER_4_1 0x01 +#define IBM640_SER_8_1 0x02 +#define IBM640_SER_16_1 0x03 +#define IBM640_SER_16_3 0x05 +#define IBM640_SER_5_1 0x06 +#define RGB640_PIXEL_INTERLEAVE 0x09 +#define RGB640_MISC_CONF 0x0a +#define IBM640_PCLK 0x00 +#define IBM640_PCLK_2 0x40 +#define IBM640_PCLK_4 0x80 +#define IBM640_PCLK_8 0xc0 +#define IBM640_PSIZE10 0x10 +#define IBM640_LCI 0x08 +#define IBM640_WIDCTL_MASK 0x07 +#define RGB640_VGA_CONTROL 0x0b +#define IBM640_RDBK 0x04 +#define IBM640_PSIZE8 0x02 +#define IBM640_VRAM 0x01 +#define RGB640_DAC_CONTROL 0x0d +#define IBM640_MONO 0x08 +#define IBM640_DACENBL 0x04 +#define IBM640_SHUNT 0x02 +#define IBM640_SLOWSLEW 0x01 +#define RGB640_OUTPUT_CONTROL 0x0e +#define IBM640_RDAI 0x04 +#define IBM640_WDAI 0x02 +#define IBM640_WATCTL 0x01 +#define RGB640_SYNC_CONTROL 0x0f +#define IBM640_PWR 0x20 +#define IBM640_VSP 0x10 +#define IBM640_HSP 0x08 +#define IBM640_CSE 0x04 +#define IBM640_CSG 0x02 +#define IBM640_BPE 0x01 +#define RGB640_PLL_N 0x10 +#define RGB640_PLL_M 0x11 +#define RGB640_PLL_P 0x12 +#define RGB640_PLL_CTL 0x13 +#define IBM640_PLL_EN 0x04 +#define IBM640_PLL_HIGH 0x10 +#define IBM640_PLL_LOW 0x01 +#define RGB640_AUX_PLL_CTL 0x17 +#define IBM640_AUXPLL 0x04 +#define IBM640_AUX_HI 0x02 +#define IBM640_AUX_LO 0x01 +#define RGB640_CHROMA_KEY0 0x20 +#define RGB640_CHROMA_MASK0 0x21 +#define RGB640_CURS_X_LOW 0x40 +#define RGB640_CURS_X_HIGH 0x41 +#define RGB640_CURS_Y_LOW 0x42 +#define RGB640_CURS_Y_HIGH 0x43 +#define RGB640_CURS_OFFSETX 0x44 +#define RGB640_CURS_OFFSETY 0x45 +#define RGB640_CURSOR_CONTROL 0x4B +#define IBM640_CURS_OFF 0x00 +#define IBM640_CURS_MODE0 0x01 +#define IBM640_CURS_MODE1 0x02 +#define IBM640_CURS_MODE2 0x03 +#define IBM640_CURS_ADV 0x04 +#define RGB640_CROSSHAIR_CONTROL 0x57 +#define RGB640_VRAM_MASK0 0xf0 +#define RGB640_VRAM_MASK1 0xf1 +#define RGB640_VRAM_MASK2 0xf2 +#define RGB640_DIAGS 0xfa +#define RGB640_CURS_WRITE 0x1000 +#define RGB640_CURS_COL0 0x4800 +#define RGB640_CURS_COL1 0x4801 +#define RGB640_CURS_COL2 0x4802 +#define RGB640_CURS_COL3 0x4803 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBMPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBMPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/IBMPriv.h (revision 51223) @@ -0,0 +1,28 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/IBMPriv.h,v 1.1.2.2 1998/07/18 17:54:01 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "IBM.h" + +typedef struct { + char *DeviceName; +} xf86IBMramdacInfo; + +extern xf86IBMramdacInfo IBMramdacDeviceInfo[]; + +#ifdef INIT_IBM_RAMDAC_INFO +xf86IBMramdacInfo IBMramdacDeviceInfo[] = { + {"IBM 524"}, + {"IBM 524A"}, + {"IBM 525"}, + {"IBM 526"}, + {"IBM 526DB(DoubleBuffer)"}, + {"IBM 528"}, + {"IBM 528A"}, + {"IBM 624"}, + {"IBM 624DB(DoubleBuffer)"}, + {"IBM 640"} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OScompiler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OScompiler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OScompiler.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/OScompiler.h,v 1.3 1999/01/31 12:22:15 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/* $XConsortium: OScompiler.h /main/4 1996/02/21 17:56:09 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef __COMPILER_DEPENDANCIES__ +#define __COMPILER_DEPENDANCIES__ + +#define MOVE( src, dst, length ) memcpy( dst, src, length) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define ABS(x) (((x)>0)?(x):-(x)) + +#include "misc.h" +#include "compiler.h" + +#ifdef lint +/* So that lint doesn't complain about constructs it doesn't understand */ +#ifdef volatile +#undef volatile +#endif +#define volatile +#ifdef const +#undef const +#endif +#define const +#ifdef signed +#undef signed +#endif +#define signed +#ifdef _ANSI_DECLS_ +#undef _ANSI_DECLS_ +#endif +#endif + +#endif /* !__COMPILER_DEPENDANCIES__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Oid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Oid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Oid.h (revision 51223) @@ -0,0 +1,294 @@ +/* $Xorg: Oid.h,v 1.3 2000/08/17 19:48:06 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_Oid_h +#define _Xp_Oid_h + +#include + +/* + * include the auto-generated XpOid enum definition + */ +#include "OidDefs.h" + +/* + * messages + */ +#define XPMSG_WARN_MSS "Syntax error parsing medium-source-sizes" +#define XPMSG_WARN_ITM "Syntax error parsing input-trays-medium" +#define XPMSG_WARN_DOC_FMT "Syntax error parsing document format" +#define XPMSG_WARN_DOCFMT_LIST "Syntax error parsing document format list" +#define XPMSG_WARN_CARD_LIST "Syntax error parsing cardinal list" + +/* + * macros for memory allocation + */ +#define XpOidMalloc(size) ((char*)Xalloc((unsigned long)(size))) +#define XpOidCalloc(count, size) \ + ((char*)Xcalloc((unsigned long)((count)*(size)))) +#define XpOidFree(mem) (Xfree((unsigned long*)(mem))) + +/* + * list of object identifiers + */ +typedef struct _XpOidList +{ + XpOid* list; + int count; +} XpOidList; + +/* + * linked list of object identifiers + */ +typedef struct XpOidNodeStruct +{ + XpOid oid; + struct XpOidNodeStruct* next; +} *XpOidNode; + +typedef struct _XpOidLinkedList +{ + XpOidNode head; + XpOidNode tail; + XpOidNode current; + int count; +} XpOidLinkedList; + +/* + * XpOidMediumSourceSize and related definitions + */ +typedef struct +{ + float minimum_x; + float maximum_x; + float minimum_y; + float maximum_y; +} XpOidArea; + +typedef struct +{ + float lower_bound; + float upper_bound; +} XpOidRealRange; + +typedef struct +{ + XpOidRealRange range_across_feed; + float increment_across_feed; + XpOidRealRange range_in_feed; + float increment_in_feed; + BOOL long_edge_feeds; + XpOidArea assured_reproduction_area; +} XpOidMediumContinuousSize; + +typedef struct +{ + XpOid page_size; + BOOL long_edge_feeds; + XpOidArea assured_reproduction_area; +} XpOidMediumDiscreteSize; + +typedef struct +{ + XpOidMediumDiscreteSize* list; + int count; +} XpOidMediumDiscreteSizeList; + +typedef struct +{ + XpOid input_tray; /* may be set to xpoid_none or xpoid_unspecified */ + enum { XpOidMediumSS_DISCRETE, XpOidMediumSS_CONTINUOUS } mstag; + union + { + XpOidMediumDiscreteSizeList* discrete; + XpOidMediumContinuousSize* continuous_size; + } ms; /* "ms" is short for medium-size */ + +} XpOidMediumSourceSize; + +typedef struct +{ + XpOidMediumSourceSize* mss; + int count; +} XpOidMediumSS; + + +typedef struct +{ + XpOid input_tray; /* may be set to xpoid_none */ + XpOid medium; +} XpOidTrayMedium; + +typedef struct +{ + XpOidTrayMedium* list; + int count; +} XpOidTrayMediumList; + +typedef enum { + XPOID_NOTIFY_UNSUPPORTED, + XPOID_NOTIFY_NONE, + XPOID_NOTIFY_EMAIL +} XpOidNotify; + +typedef struct +{ + unsigned long *list; + int count; +} XpOidCardList; + +typedef struct +{ + char* format; + char* variant; + char* version; +} XpOidDocFmt; + +typedef struct +{ + XpOidDocFmt* list; + int count; +} XpOidDocFmtList; + + +/* + * XpOid public methods + */ +const char* XpOidString(XpOid); +int XpOidStringLength(XpOid); +XpOid XpOidFromString(const char* value); +BOOL XpOidTrayMediumListHasTray(const XpOidTrayMediumList* list, XpOid tray); + +/* + * XpOidList public methods + */ +XpOidList* XpOidListNew(const char* value_string, + const XpOidList* valid_oids); +#define XpOidListInit(l, a, c) { (l)->list = (a); (l)->count = (c); } +void XpOidListDelete(XpOidList*); +#define XpOidListCount(l) ((l) ? (l)->count : 0) +#define XpOidListGetOid(l, i) ((l) ? (l)->list[(i)] : xpoid_none) +int XpOidListGetIndex(const XpOidList* list, XpOid oid); +BOOL XpOidListHasOid(const XpOidList* list, XpOid oid); +char* XpOidListString(const XpOidList*); + + +/* + * XpOidLinkedList public methods + */ +XpOidLinkedList* XpOidLinkedListNew(void); +void XpOidLinkedListDelete(XpOidLinkedList*); +#define XpOidLinkedListCount(l) ((l) ? (l)->count : 0) +XpOid XpOidLinkedListGetOid(XpOidLinkedList* list, int i); +void XpOidLinkedListAddOid(XpOidLinkedList* list, XpOid oid); +int XpOidLinkedListGetIndex(XpOidLinkedList* list, XpOid oid); +BOOL XpOidLinkedListHasOid(XpOidLinkedList* list, + XpOid oid); +XpOid XpOidLinkedListFirstOid(XpOidLinkedList* list); +XpOid XpOidLinkedListNextOid(XpOidLinkedList* list); + +/* + * XpOidMediumSourceSize public methods + */ +XpOidMediumSS* XpOidMediumSSNew(const char* value_string, + const XpOidList* valid_trays, + const XpOidList* valid_medium_sizes); +void XpOidMediumSSDelete(XpOidMediumSS*); +#define XpOidMediumSSCount(me) ((me) ? (me)->count : 0) +BOOL XpOidMediumSSHasSize(XpOidMediumSS*, XpOid medium_size); +char* XpOidMediumSSString(const XpOidMediumSS*); + +/* + * XpOidTrayMediumList public methods + */ +XpOidTrayMediumList* XpOidTrayMediumListNew(const char* value_string, + const XpOidList* valid_trays, + const XpOidMediumSS* msss); +void XpOidTrayMediumListDelete(XpOidTrayMediumList* me); +#define XpOidTrayMediumListCount(me) ((me) ? (me)->count : 0) +#define XpOidTrayMediumListTray(me, i) \ + ((me) ? (me)->list[(i)].input_tray : xpoid_none) +#define XpOidTrayMediumListMedium(me, i) \ + ((me) ? (me)->list[(i)].medium : xpoid_none) +char* XpOidTrayMediumListString(const XpOidTrayMediumList*); + +/* + * XpOidNotify public methods + */ +XpOidNotify XpOidNotifyParse(const char* value_string); +const char* XpOidNotifyString(XpOidNotify notify); + +/* + * XpOidDocFmt public methods + */ +XpOidDocFmt* XpOidDocFmtNew(const char* value_string); +void XpOidDocFmtDelete(XpOidDocFmt*); +char* XpOidDocFmtString(XpOidDocFmt*); + +/* + * XpOidDocFmtList public methods + */ +XpOidDocFmtList* XpOidDocFmtListNew(const char* value_string, + const XpOidDocFmtList* valid_fmts); +void XpOidDocFmtListDelete(XpOidDocFmtList*); +char* XpOidDocFmtListString(const XpOidDocFmtList*); +#define XpOidDocFmtListCount(me) ((me) ? (me)->count : 0) +#define XpOidDocFmtListGetDocFmt(me, i) \ + ((me) ? &(me)->list[(i)] : (XpDocFmt*)NULL) +BOOL XpOidDocFmtListHasFmt(const XpOidDocFmtList* list, + const XpOidDocFmt* fmt); +/* + * XpOidCardList public methods + */ +XpOidCardList* XpOidCardListNew(const char* value_string, + const XpOidCardList* valid_cards); +#define XpOidCardListInit(l, a, c) { (l)->list = (a); (l)->count = (c); } +void XpOidCardListDelete(XpOidCardList*); +char* XpOidCardListString(const XpOidCardList*); +#define XpOidCardListCount(me) ((me) ? (me)->count : 0) +#define XpOidCardListGetCard(me, i) ((me) ? (me)->list[(i)] : 0) +BOOL XpOidCardListHasCard(const XpOidCardList*, unsigned long); + +/* + * misc parsing functions + */ +BOOL XpOidParseUnsignedValue(const char* value_string, + const char** ptr_return, + unsigned long* unsigned_return); + + +#endif /* _Xp_Oid_h - don't add anything after this line */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidDefs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidDefs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidDefs.h (revision 51223) @@ -0,0 +1,171 @@ +/* $Xorg: OidDefs.h,v 1.4 2001/03/14 18:45:13 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* This is an automatically-generated file. Do not edit. */ + +typedef enum { + xpoid_none, + xpoid_unspecified, + xpoid_att_descriptor, + xpoid_att_content_orientation, + xpoid_att_copy_count, + xpoid_att_default_printer_resolution, + xpoid_att_default_input_tray, + xpoid_att_default_medium, + xpoid_att_document_format, + xpoid_att_plex, + xpoid_att_xp_listfonts_modes, + xpoid_att_job_name, + xpoid_att_job_owner, + xpoid_att_notification_profile, + xpoid_att_xp_setup_state, + xpoid_att_xp_spooler_command_options, + xpoid_att_content_orientations_supported, + xpoid_att_document_formats_supported, + xpoid_att_dt_pdm_command, + xpoid_att_input_trays_medium, + xpoid_att_medium_source_sizes_supported, + xpoid_att_plexes_supported, + xpoid_att_printer_model, + xpoid_att_printer_name, + xpoid_att_printer_resolutions_supported, + xpoid_att_xp_embedded_formats_supported, + xpoid_att_xp_listfonts_modes_supported, + xpoid_att_xp_page_attributes_supported, + xpoid_att_xp_raw_formats_supported, + xpoid_att_xp_setup_proviso, + xpoid_att_document_attributes_supported, + xpoid_att_job_attributes_supported, + xpoid_att_locale, + xpoid_att_multiple_documents_supported, + xpoid_att_available_compression, + xpoid_att_available_compressions_supported, + xpoid_val_content_orientation_portrait, + xpoid_val_content_orientation_landscape, + xpoid_val_content_orientation_reverse_portrait, + xpoid_val_content_orientation_reverse_landscape, + xpoid_val_medium_size_iso_a0, + xpoid_val_medium_size_iso_a1, + xpoid_val_medium_size_iso_a2, + xpoid_val_medium_size_iso_a3, + xpoid_val_medium_size_iso_a4, + xpoid_val_medium_size_iso_a5, + xpoid_val_medium_size_iso_a6, + xpoid_val_medium_size_iso_a7, + xpoid_val_medium_size_iso_a8, + xpoid_val_medium_size_iso_a9, + xpoid_val_medium_size_iso_a10, + xpoid_val_medium_size_iso_b0, + xpoid_val_medium_size_iso_b1, + xpoid_val_medium_size_iso_b2, + xpoid_val_medium_size_iso_b3, + xpoid_val_medium_size_iso_b4, + xpoid_val_medium_size_iso_b5, + xpoid_val_medium_size_iso_b6, + xpoid_val_medium_size_iso_b7, + xpoid_val_medium_size_iso_b8, + xpoid_val_medium_size_iso_b9, + xpoid_val_medium_size_iso_b10, + xpoid_val_medium_size_na_letter, + xpoid_val_medium_size_na_legal, + xpoid_val_medium_size_executive, + xpoid_val_medium_size_folio, + xpoid_val_medium_size_invoice, + xpoid_val_medium_size_ledger, + xpoid_val_medium_size_quarto, + xpoid_val_medium_size_iso_c3, + xpoid_val_medium_size_iso_c4, + xpoid_val_medium_size_iso_c5, + xpoid_val_medium_size_iso_c6, + xpoid_val_medium_size_iso_designated_long, + xpoid_val_medium_size_na_10x13_envelope, + xpoid_val_medium_size_na_9x12_envelope, + xpoid_val_medium_size_na_number_10_envelope, + xpoid_val_medium_size_na_7x9_envelope, + xpoid_val_medium_size_na_9x11_envelope, + xpoid_val_medium_size_na_10x14_envelope, + xpoid_val_medium_size_na_number_9_envelope, + xpoid_val_medium_size_na_6x9_envelope, + xpoid_val_medium_size_na_10x15_envelope, + xpoid_val_medium_size_monarch_envelope, + xpoid_val_medium_size_a, + xpoid_val_medium_size_b, + xpoid_val_medium_size_c, + xpoid_val_medium_size_d, + xpoid_val_medium_size_e, + xpoid_val_medium_size_jis_b0, + xpoid_val_medium_size_jis_b1, + xpoid_val_medium_size_jis_b2, + xpoid_val_medium_size_jis_b3, + xpoid_val_medium_size_jis_b4, + xpoid_val_medium_size_jis_b5, + xpoid_val_medium_size_jis_b6, + xpoid_val_medium_size_jis_b7, + xpoid_val_medium_size_jis_b8, + xpoid_val_medium_size_jis_b9, + xpoid_val_medium_size_jis_b10, + xpoid_val_medium_size_hp_2x_postcard, + xpoid_val_medium_size_hp_european_edp, + xpoid_val_medium_size_hp_mini, + xpoid_val_medium_size_hp_postcard, + xpoid_val_medium_size_hp_tabloid, + xpoid_val_medium_size_hp_us_edp, + xpoid_val_medium_size_hp_us_government_legal, + xpoid_val_medium_size_hp_us_government_letter, + xpoid_val_plex_simplex, + xpoid_val_plex_duplex, + xpoid_val_plex_tumble, + xpoid_val_input_tray_top, + xpoid_val_input_tray_middle, + xpoid_val_input_tray_bottom, + xpoid_val_input_tray_envelope, + xpoid_val_input_tray_manual, + xpoid_val_input_tray_large_capacity, + xpoid_val_input_tray_main, + xpoid_val_input_tray_side, + xpoid_val_event_report_job_completed, + xpoid_val_delivery_method_electronic_mail, + xpoid_val_xp_setup_mandatory, + xpoid_val_xp_setup_optional, + xpoid_val_xp_setup_ok, + xpoid_val_xp_setup_incomplete, + xpoid_val_xp_list_glyph_fonts, + xpoid_val_xp_list_internal_printer_fonts, + xpoid_val_available_compressions_0, + xpoid_val_available_compressions_01, + xpoid_val_available_compressions_02, + xpoid_val_available_compressions_03, + xpoid_val_available_compressions_012, + xpoid_val_available_compressions_013, + xpoid_val_available_compressions_023, + xpoid_val_available_compressions_0123 +} XpOid; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidStrs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidStrs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/OidStrs.h (revision 51223) @@ -0,0 +1,173 @@ +/* $Xorg: OidStrs.h,v 1.4 2001/03/14 18:45:40 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* This is an automatically-generated file. Do not edit. */ + +static int XpOidStringMapCount = 127; + +static const XpOidStringMapEntry XpOidStringMap[] = { + { "", 0 }, + { "", 0 }, + { "descriptor", 10 }, + { "content-orientation", 19 }, + { "copy-count", 10 }, + { "default-printer-resolution", 26 }, + { "default-input-tray", 18 }, + { "default-medium", 14 }, + { "document-format", 15 }, + { "plex", 4 }, + { "xp-listfonts-modes", 18 }, + { "job-name", 8 }, + { "job-owner", 9 }, + { "notification-profile", 20 }, + { "xp-setup-state", 14 }, + { "xp-spooler-command-options", 26 }, + { "content-orientations-supported", 30 }, + { "document-formats-supported", 26 }, + { "dt-pdm-command", 14 }, + { "input-trays-medium", 18 }, + { "medium-source-sizes-supported", 29 }, + { "plexes-supported", 16 }, + { "printer-model", 13 }, + { "printer-name", 12 }, + { "printer-resolutions-supported", 29 }, + { "xp-embedded-formats-supported", 29 }, + { "xp-listfonts-modes-supported", 28 }, + { "xp-page-attributes-supported", 28 }, + { "xp-raw-formats-supported", 24 }, + { "xp-setup-proviso", 16 }, + { "document-attributes-supported", 29 }, + { "job-attributes-supported", 24 }, + { "locale", 6 }, + { "multiple-documents-supported", 28 }, + { "available-compression", 21 }, + { "available-compressions-supported", 32 }, + { "portrait", 8 }, + { "landscape", 9 }, + { "reverse-portrait", 16 }, + { "reverse-landscape", 17 }, + { "iso-a0", 6 }, + { "iso-a1", 6 }, + { "iso-a2", 6 }, + { "iso-a3", 6 }, + { "iso-a4", 6 }, + { "iso-a5", 6 }, + { "iso-a6", 6 }, + { "iso-a7", 6 }, + { "iso-a8", 6 }, + { "iso-a9", 6 }, + { "iso-a10", 7 }, + { "iso-b0", 6 }, + { "iso-b1", 6 }, + { "iso-b2", 6 }, + { "iso-b3", 6 }, + { "iso-b4", 6 }, + { "iso-b5", 6 }, + { "iso-b6", 6 }, + { "iso-b7", 6 }, + { "iso-b8", 6 }, + { "iso-b9", 6 }, + { "iso-b10", 7 }, + { "na-letter", 9 }, + { "na-legal", 8 }, + { "executive", 9 }, + { "folio", 5 }, + { "invoice", 7 }, + { "ledger", 6 }, + { "quarto", 6 }, + { "iso-c3", 6 }, + { "iso-c4", 6 }, + { "iso-c5", 6 }, + { "iso-c6", 6 }, + { "iso-designated-long", 19 }, + { "na-10x13-envelope", 17 }, + { "na-9x12-envelope", 16 }, + { "na-number-10-envelope", 21 }, + { "na-7x9-envelope", 15 }, + { "na-9x11-envelope", 16 }, + { "na-10x14-envelope", 17 }, + { "na-number-9-envelope", 20 }, + { "na-6x9-envelope", 15 }, + { "na-10x15-envelope", 17 }, + { "monarch-envelope", 16 }, + { "a", 1 }, + { "b", 1 }, + { "c", 1 }, + { "d", 1 }, + { "e", 1 }, + { "jis-b0", 6 }, + { "jis-b1", 6 }, + { "jis-b2", 6 }, + { "jis-b3", 6 }, + { "jis-b4", 6 }, + { "jis-b5", 6 }, + { "jis-b6", 6 }, + { "jis-b7", 6 }, + { "jis-b8", 6 }, + { "jis-b9", 6 }, + { "jis-b10", 7 }, + { "hp-2x-postcard", 14 }, + { "hp-european-edp", 15 }, + { "hp-mini", 7 }, + { "hp-postcard", 11 }, + { "hp-tabloid", 10 }, + { "hp-us-edp", 9 }, + { "hp-us-government-legal", 22 }, + { "hp-us-government-letter", 23 }, + { "simplex", 7 }, + { "duplex", 6 }, + { "tumble", 6 }, + { "top", 3 }, + { "middle", 6 }, + { "bottom", 6 }, + { "envelope", 8 }, + { "manual", 6 }, + { "large-capacity", 14 }, + { "main", 4 }, + { "side", 4 }, + { "event-report-job-completed", 26 }, + { "electronic-mail", 15 }, + { "xp-setup-mandatory", 18 }, + { "xp-setup-optional", 17 }, + { "xp-setup-ok", 11 }, + { "xp-setup-incomplete", 19 }, + { "xp-list-glyph-fonts", 19 }, + { "xp-list-internal-printer-fonts", 30 }, + { "0", 1 }, + { "01", 2 }, + { "02", 2 }, + { "03", 2 }, + { "012", 3 }, + { "013", 3 }, + { "023", 3 }, + { "0123", 4 } +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pci.h (revision 51223) @@ -0,0 +1,444 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v 1.45 2004/02/02 03:55:31 dawes Exp $ */ +/* + * Copyright 1998 by Concurrent Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Concurrent Computer + * Corporation not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Concurrent Computer Corporation makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Copyright 1998 by Metro Link Incorporated + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Metro Link + * Incorporated not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Metro Link Incorporated makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * This file is derived in part from the original xf86_PCI.h that included + * following copyright message: + * + * Copyright 1995 by Robin Cutshaw + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file has the private Pci definitions. The public ones are imported + * from xf86Pci.h. Drivers should not use this file. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _PCI_H +#define _PCI_H 1 + +#include +#include +#include "xf86Pci.h" +#include "xf86PciInfo.h" + +/* + * Global Definitions + */ +#define MAX_PCI_DEVICES 128 /* Max number of devices accomodated */ + /* by xf86scanpci */ +#if defined(sun) && defined(SVR4) && defined(sparc) +# define MAX_PCI_BUSES 4096 /* Max number of PCI buses */ +#elif defined(__alpha__) && defined (linux) +# define MAX_PCI_DOMAINS 512 +# define PCI_DOM_MASK 0x01fful +# define MAX_PCI_BUSES (MAX_PCI_DOMAINS*256) /* 256 per domain */ +#else +# define MAX_PCI_BUSES 256 /* Max number of PCI buses */ +#endif + +#define DEVID(vendor, device) \ + ((CARD32)((PCI_##device << 16) | PCI_##vendor)) + +#ifndef PCI_DOM_MASK +# define PCI_DOM_MASK 0x0ffu +#endif +#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) + +/* + * "b" contains an optional domain number. + */ +#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ + (((d) & 0x00001fu) << 11) | \ + (((f) & 0x000007u) << 8)) + +#define PCI_MAKE_BUS(d,b) ((((d) & (PCI_DOM_MASK)) << 8) | ((b) & 0xffu)) + +#define PCI_DOM_FROM_TAG(tag) (((tag) >> 24) & (PCI_DOM_MASK)) +#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) +#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) +#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) + +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) +#define PCI_BDEV_FROM_TAG(tag) ((tag) & 0x00fff800u) + +#define PCI_DOM_FROM_BUS(bus) (((bus) >> 8) & (PCI_DOM_MASK)) +#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu) +#define PCI_TAG_NO_DOMAIN(tag) ((tag) & 0x00ffff00u) + +/* + * Macros for bus numbers found in P2P headers. + */ +#define PCI_PRIMARY_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_PRIMARY_BUS_MASK ) >> 0) | (PCI_DOM_FROM_TAG(tag) << 8)) +#define PCI_SECONDARY_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_SECONDARY_BUS_MASK ) >> 8) | (PCI_DOM_FROM_TAG(tag) << 8)) +#define PCI_SUBORDINATE_BUS_EXTRACT(x, tag) \ + ((((x) & PCI_SUBORDINATE_BUS_MASK) >> 16) | (PCI_DOM_FROM_TAG(tag) << 8)) + +#define PCI_PRIMARY_BUS_INSERT(x, y) \ + (((x) & ~PCI_PRIMARY_BUS_MASK ) | (((y) & 0xffu) << 0)) +#define PCI_SECONDARY_BUS_INSERT(x, y) \ + (((x) & ~PCI_SECONDARY_BUS_MASK ) | (((y) & 0xffu) << 8)) +#define PCI_SUBORDINATE_BUS_INSERT(x, y) \ + (((x) & ~PCI_SUBORDINATE_BUS_MASK) | (((y) & 0xffu) << 16)) + +/* Ditto for CardBus bridges */ +#define PCI_CB_PRIMARY_BUS_EXTRACT(x, tag) \ + PCI_PRIMARY_BUS_EXTRACT(x, tag) +#define PCI_CB_CARDBUS_BUS_EXTRACT(x, tag) \ + PCI_SECONDARY_BUS_EXTRACT(x, tag) +#define PCI_CB_SUBORDINATE_BUS_EXTRACT(x, tag) \ + PCI_SUBORDINATE_BUS_EXTRACT(x, tag) + +#define PCI_CB_PRIMARY_BUS_INSERT(x, tag) \ + PCI_PRIMARY_BUS_INSERT(x, tag) +#define PCI_CB_CARDBUS_BUS_INSERT(x, tag) \ + PCI_SECONDARY_BUS_INSERT(x, tag) +#define PCI_CB_SUBORDINATE_BUS_INSERT(x, tag) \ + PCI_SUBORDINATE_BUS_INSERT(x, tag) + +#if X_BYTE_ORDER == X_BIG_ENDIAN +#define PCI_CPU(val) (((val >> 24) & 0x000000ff) | \ + ((val >> 8) & 0x0000ff00) | \ + ((val << 8) & 0x00ff0000) | \ + ((val << 24) & 0xff000000)) +#define PCI_CPU16(val) (((val >> 8) & 0x000000ff) | \ + ((val << 8) & 0x0000ff00)) +#else +#define PCI_CPU(val) (val) +#define PCI_CPU16(val) (val) +#endif + +/* + * Debug Macros/Definitions + */ +/* #define DEBUGPCI 2 */ /* Disable/enable trace in PCI code */ + +#if defined(DEBUGPCI) + +# define PCITRACE(lvl,printfargs) \ + if (lvl > xf86Verbose) { \ + ErrorF printfargs; \ + } + +#else /* !defined(DEBUGPCI) */ + +# define PCITRACE(lvl,printfargs) + +#endif /* !defined(DEBUGPCI) */ + +/* + * PCI Config mechanism definitions + */ +#define PCI_EN 0x80000000 + +#define PCI_CFGMECH1_ADDRESS_REG 0xCF8 +#define PCI_CFGMECH1_DATA_REG 0xCFC + +#define PCI_CFGMECH1_MAXDEV 32 + +/* + * Select architecture specific PCI init function + */ +#if defined(__alpha__) +# if defined(linux) +# define ARCH_PCI_INIT axpPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(__FreeBSD__) || defined(__OpenBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# elif defined(__NetBSD__) +# define ARCH_PCI_INIT netbsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__arm__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__hppa__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__ia64__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(FreeBSD) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +# define XF86SCANPCI_WRAPPER ia64ScanPCIWrapper +#elif defined(__i386__) || defined(i386) +# define ARCH_PCI_INIT ix86PciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# if defined(linux) +# define ARCH_PCI_OS_INIT linuxPciInit +# endif +#elif defined(__mc68000__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__mips__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__powerpc__) || defined(__powerpc64__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN /* Needs kernel work to remove */ +# elif defined(__FreeBSD__) || defined(__OpenBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# elif defined(__NetBSD__) +# define ARCH_PCI_INIT netbsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# else +# define ARCH_PCI_INIT ppcPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__s390__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__sh__) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +#elif defined(__sparc__) || defined(sparc) +# if defined(linux) +# define ARCH_PCI_INIT linuxPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif defined(sun) +# define ARCH_PCI_INIT sparcPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# elif (defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc64__) +# define ARCH_PCI_INIT freebsdPciInit +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# endif +# if !defined(__FreeBSD__) +# define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge +# endif +#elif defined(__amd64__) || defined(__amd64) +# if defined(__FreeBSD__) +# define ARCH_PCI_INIT freebsdPciInit +# else +# define ARCH_PCI_INIT ix86PciInit +# endif +# define INCLUDE_XF86_MAP_PCI_MEM +# define INCLUDE_XF86_NO_DOMAIN +# if defined(linux) +# define ARCH_PCI_OS_INIT linuxPciInit +# endif +#endif + +#ifndef ARCH_PCI_INIT +#error No PCI support available for this architecture/OS combination +#endif + +extern void ARCH_PCI_INIT(void); +#if defined(ARCH_PCI_OS_INIT) +extern void ARCH_PCI_OS_INIT(void); +#endif + +#if defined(ARCH_PCI_PCI_BRIDGE) +extern void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI); +#endif + +#if defined(XF86SCANPCI_WRAPPER) +typedef enum { + SCANPCI_INIT, + SCANPCI_TERM +} scanpciWrapperOpt; +extern void XF86SCANPCI_WRAPPER(scanpciWrapperOpt flags); +#endif + +/* + * Table of functions used to access a specific PCI bus domain + * (e.g. a primary PCI bus and all of its secondaries) + */ +typedef struct pci_bus_funcs { + CARD32 (*pciReadLong)(PCITAG, int); + void (*pciWriteLong)(PCITAG, int, CARD32); + void (*pciSetBitsLong)(PCITAG, int, CARD32, CARD32); + ADDRESS (*pciAddrHostToBus)(PCITAG, PciAddrType, ADDRESS); + ADDRESS (*pciAddrBusToHost)(PCITAG, PciAddrType, ADDRESS); + /* + * The next three are optional. If NULL, the corresponding function is + * to be performed generically. + */ + CARD16 (*pciControlBridge)(int, CARD16, CARD16); + void (*pciGetBridgeBuses)(int, int *, int *, int *); + /* Use pointer's to avoid #include recursion */ + void (*pciGetBridgeResources)(int, pointer *, pointer *, pointer *); + + /* These are optional and will be implemented using read long + * if not present. */ + CARD8 (*pciReadByte)(PCITAG, int); + void (*pciWriteByte)(PCITAG, int, CARD8); + CARD16 (*pciReadWord)(PCITAG, int); + void (*pciWriteWord)(PCITAG, int, CARD16); + +} pciBusFuncs_t, *pciBusFuncs_p; + +/* + * pciBusInfo_t - One structure per defined PCI bus + */ +typedef struct pci_bus_info { + unsigned char configMech; /* PCI config type to use */ + unsigned char numDevices; /* Range of valid devnums */ + unsigned char secondary; /* Boolean: bus is a secondary */ + int primary_bus; /* Parent bus */ + pciBusFuncs_p funcs; /* PCI access functions */ + void *pciBusPriv; /* Implementation private data */ + pciConfigPtr bridge; /* bridge that opens this bus */ +} pciBusInfo_t; + +#define HOST_NO_BUS ((pciBusInfo_t *)(-1)) + +/* configMech values */ +#define PCI_CFG_MECH_UNKNOWN 0 /* Not yet known */ +#define PCI_CFG_MECH_1 1 /* Most machines */ +#define PCI_CFG_MECH_2 2 /* Older PC's */ +#define PCI_CFG_MECH_OTHER 3 /* Something else */ + +/* Generic PCI service functions and helpers */ +PCITAG pciGenFindFirst(void); +PCITAG pciGenFindNext(void); +CARD32 pciCfgMech1Read(PCITAG tag, int offset); +void pciCfgMech1Write(PCITAG tag, int offset, CARD32 val); +void pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, + CARD32 val); +CARD32 pciByteSwap(CARD32); +Bool pciMfDev(int, int); +ADDRESS pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS); + +extern void pciSetOSBIOSPtr(int (*bios_fn)(PCITAG Tag, int basereg, unsigned char * buf, int len)); +extern PCITAG (*pciFindFirstFP)(void); +extern PCITAG (*pciFindNextFP)(void); + +extern CARD32 pciDevid; +extern CARD32 pciDevidMask; + +extern int pciMaxBusNum; + +extern int pciBusNum; +extern int pciDevNum; +extern int pciFuncNum; +extern PCITAG pciDeviceTag; + +extern pciBusInfo_t *pciBusInfo[]; + +#endif /* _PCI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pcl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pcl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pcl.h (revision 51223) @@ -0,0 +1,625 @@ +/* $Xorg: Pcl.h,v 1.3 2000/08/17 19:48:07 cpqbld Exp $ */ +/******************************************************************* +** +** ********************************************************* +** * +** * File: Pcl.h +** * +** * Contents: defines and includes for the Pcl driver +** * for a printing X server. +** * +** * Created: 1/30/95 +** * +** ********************************************************* +** +********************************************************************/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/Pcl.h,v 1.12 2001/12/21 21:02:05 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCL_H_ +#define _PCL_H_ + +#include +#include "scrnintstr.h" + +#include "PclDef.h" +#include "Pclmap.h" +#include "PclSFonts.h" + +#include +#include + +#include "regionstr.h" +#include +#include "dixfontstr.h" +#include "gcstruct.h" + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +typedef char *XPointer; +#endif +#define Status int +#define True 1 +#define False 0 +#include "misc.h" +#include +#include +#include "attributes.h" + +/****** + * externally visible variables from PclInit.c + ******/ +extern int PclScreenPrivateIndex, PclWindowPrivateIndex; +extern int PclContextPrivateIndex; +extern int PclPixmapPrivateIndex; +extern int PclGCPrivateIndex; + +/****** + * externally visible variables from PclAttVal.c + ******/ +extern XpValidatePoolsRec PclValidatePoolsRec; + +/* + * This structure defines a mapping from an X colormap ID to a list of + * print contexts which use the colormap. + */ +typedef struct _pclcontextlist { + XpContextPtr context; + struct _pclcontextlist *next; +} PclContextList, *PclContextListPtr; + +typedef struct _pclcmaptocontexts { + long colormapId; + PclContextListPtr contexts; + struct _pclcmaptocontexts *next; +} PclCmapToContexts; + +typedef struct { + PclCmapToContexts *colormaps; + CloseScreenProcPtr CloseScreen; +} PclScreenPrivRec, *PclScreenPrivPtr; + +/* + * This structure defines a mapping from an X colormap ID to a PCL + * palette ID. + */ +typedef struct _palettemap { + long colormapId; + int paletteId; + int downloaded; + struct _palettemap *next; +} PclPaletteMap, *PclPaletteMapPtr; + +typedef struct { + char *jobFileName; + FILE *pJobFile; + char *pageFileName; + FILE *pPageFile; + GC lastGC; + unsigned char *dash; + int validGC; + ClientPtr getDocClient; + int getDocBufSize; + PclSoftFontInfoPtr pSoftFontInfo; + PclPaletteMapPtr palettes; + int currentPalette; + int nextPaletteId; + PclPaletteMap staticGrayPalette; + PclPaletteMap trueColorPalette; + PclPaletteMap specialTrueColorPalette; + unsigned char *ctbl; + int ctbldim; + int isRaw; +#ifdef XP_PCL_LJ3 + unsigned int fcount; + unsigned int fcount_max; + char *figures; +#endif /* XP_PCL_LJ3 */ +} PclContextPrivRec, *PclContextPrivPtr; + +typedef struct { + int validContext; + XpContextPtr context; +} PclWindowPrivRec, *PclWindowPrivPtr; + +typedef struct { + unsigned long stippleFg, stippleBg; +} PclGCPrivRec, *PclGCPrivPtr; + +typedef struct { + XpContextPtr context; + char *tempFileName; + FILE *tempFile; + GC lastGC; + int validGC; +} PclPixmapPrivRec, *PclPixmapPrivPtr; + +/****** + * Defined functions + ******/ +#define SEND_PCL(f,c) fwrite( c, sizeof( char ), strlen( c ), f ) +#define SEND_PCL_COUNT(f,c,n) fwrite( c, sizeof( char ), n, f ) + +#ifndef XP_PCL_LJ3 +#define SAVE_PCL(f,p,c) SEND_PCL(f,c) +#define SAVE_PCL_COUNT(f,p,c,n) SEND_PCL_COUNT(f,c,n) +#define MACRO_START(f,p) SEND_PCL(f, "\033&f1Y\033&f0X") +#define MACRO_END(f) SEND_PCL(f, "\033&f1X") +#else +#define SAVE_PCL(f,p,c) PclSpoolFigs(p, c, strlen(c)) +#define SAVE_PCL_COUNT(f,p,c,n) PclSpoolFigs(p, c, n) +#define MACRO_START(f,p) p->fcount = 0 +#define MACRO_END(f) /* do nothing */ +#endif /* XP_PCL_LJ3 */ + +#define MIN(a,b) (((a)<(b))?(a):(b)) +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/****** + * Functions in PclArc.c + ******/ +extern void PclPolyArc( + DrawablePtr pDrawable, + GCPtr pGC, + int nArcs, + xArc *pArcs); +extern void PclPolyFillArc( + DrawablePtr pDrawable, + GCPtr pGC, + int nArcs, + xArc *pArcs); + +/****** + * Functions in PclArea.c + ******/ +extern void PclPutImage( + DrawablePtr pDrawable, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage); +extern RegionPtr PclCopyArea( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty); +RegionPtr PclCopyPlane( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + unsigned long plane); + + +/****** + * Functions in PclAttr.c + ******/ +extern char *PclGetAttributes( + XpContextPtr pCon, + XPAttributes pool ); +extern char *PclGetOneAttribute( + XpContextPtr pCon, + XPAttributes pool, + char *attr ); +extern int PclAugmentAttributes( + XpContextPtr pCon, + XPAttributes pool, + char *attrs ); +extern int PclSetAttributes( + XpContextPtr pCon, + XPAttributes pool, + char *attrs ); + +/****** + * Functions in PclColor.c + ******/ +extern Bool PclCreateDefColormap(ScreenPtr pScreen); +extern Bool PclCreateColormap(ColormapPtr pColor); +extern void PclDestroyColormap(ColormapPtr pColor); +extern void PclInstallColormap(ColormapPtr pColor); +extern void PclUninstallColormap(ColormapPtr pColor); +extern int PclListInstalledColormaps(ScreenPtr pScreen, + XID *pCmapList); +extern void PclStoreColors(ColormapPtr pColor, + int ndef, + xColorItem *pdefs); +extern void PclResolveColor(unsigned short *pRed, + unsigned short *pGreen, + unsigned short *pBlue, + VisualPtr pVisual); +extern int PclUpdateColormap(DrawablePtr pDrawable, + XpContextPtr pCon, + GCPtr gc, + FILE *outFile); +extern void PclLookUp(ColormapPtr cmap, + PclContextPrivPtr cPriv, + unsigned short *r, + unsigned short *g, + unsigned short *b); +extern PclPaletteMapPtr PclFindPaletteMap(PclContextPrivPtr cPriv, + ColormapPtr cmap, + GCPtr gc); +extern unsigned char *PclReadMap(char *, int *); + + +/****** + * Functions in PclCursor.c + ******/ +extern void PclConstrainCursor( + ScreenPtr pScreen, + BoxPtr pBox); +extern void PclCursorLimits( + ScreenPtr pScreen, + CursorPtr pCursor, + BoxPtr pHotBox, + BoxPtr pTopLeftbox); +extern Bool PclDisplayCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern Bool PclRealizeCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern Bool PclUnrealizeCursor( + ScreenPtr pScreen, + CursorPtr pCursor); +extern void PclRecolorCursor( + ScreenPtr pScreen, + CursorPtr pCursor, + Bool displayed); +extern Bool PclSetCursorPosition( + ScreenPtr pScreen, + int x, + int y, + Bool generateEvent); + +/****** + * Functions in PclSFonts.c + ******/ +extern void +PclDownloadSoftFont8( + FILE *fp, + PclSoftFontInfoPtr pSoftFontInfo, + PclFontHead8Ptr pfh, + PclCharDataPtr pcd, + unsigned char *code); +extern void PclDownloadSoftFont16( + FILE *fp, + PclSoftFontInfoPtr pSoftFontInfo, + PclFontHead16Ptr pfh, + PclCharDataPtr pcd, + unsigned char row, + unsigned char col); +extern PclSoftFontInfoPtr PclCreateSoftFontInfo(void); +extern void PclDestroySoftFontInfo( + PclSoftFontInfoPtr pSoftFontInfo ); + +/****** + * Functions in PclGC.c + ******/ +extern Bool PclCreateGC(GCPtr pGC); +extern void PclDestroyGC(GCPtr pGC); +extern int PclUpdateDrawableGC( + GCPtr pGC, + DrawablePtr pDrawable, + FILE **outFile); +extern void PclValidateGC( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable); +extern void PclSetDrawablePrivateStuff( + DrawablePtr pDrawable, + GC gc ); +extern int PclGetDrawablePrivateStuff( + DrawablePtr pDrawable, + GC *gc, + unsigned long *valid, + FILE **file ); +extern void PclSetDrawablePrivateGC( + DrawablePtr pDrawable, + GC gc); +extern void PclComputeCompositeClip( + GCPtr pGC, + DrawablePtr pDrawable); + +/****** + * Functions in PclInit.c + ******/ +extern Bool PclCloseScreen( + int index, + ScreenPtr pScreen); +extern Bool InitializeColorPclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern Bool InitializeMonoPclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern Bool InitializeLj3PclDriver( + int ndx, + ScreenPtr pScreen, + int argc, + char **argv); +extern XpContextPtr PclGetContextFromWindow( WindowPtr win ); + +/****** + * Functions in PclLine.c + ******/ +extern void PclPolyLine( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int nPoints, + xPoint *pPoints); +extern void PclPolySegment( + DrawablePtr pDrawable, + GCPtr pGC, + int nSegments, + xSegment *pSegments); + +/****** + * Functions in PclMisc.c + ******/ +extern void PclQueryBestSize( + int class, + short *pwidth, + short *pheight, + ScreenPtr pScreen); +extern char *GetPropString(WindowPtr pWin, char *propName); +extern int SystemCmd(char *cmdStr); +extern int PclGetMediumDimensions( + XpContextPtr pCon, + CARD16 *pWidth, + CARD16 *pHeight); +extern int PclGetReproducibleArea( + XpContextPtr pCon, + xRectangle *pRect); +extern void PclSendData( + FILE *outFile, + PclContextPrivPtr pConPriv, + BoxPtr pbox, + int nbox, + double ratio); + +/****** + * Functions in PclPixel.c + ******/ +extern void PclPolyPoint( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int nPoints, + xPoint *pPoints); +extern void PclPushPixels( + GCPtr pGC, + PixmapPtr pBitmap, + DrawablePtr pDrawable, + int width, + int height, + int x, + int y); + +/****** + * Functions in PclPixmap.c + ******/ +extern PixmapPtr PclCreatePixmap( + ScreenPtr pScreen, + int width, + int height, + int depth); +extern Bool PclDestroyPixmap(PixmapPtr pPixmap); + +/****** + * Functions in PclPolygon.c + ******/ +extern void PclPolyRectangle( + DrawablePtr pDrawable, + GCPtr pGC, + int nRects, + xRectangle *pRects); +extern void PclFillPolygon( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int nPoints, + DDXPointPtr pPoints); +extern void PclPolyFillRect( + DrawablePtr pDrawable, + GCPtr pGC, + int nRects, + xRectangle *pRects); + +/****** + * Functions in PclSpans.c + ******/ +extern void PclFillSpans( + DrawablePtr pDrawable, + GCPtr pGC, + int nSpans, + DDXPointPtr pPoints, + int *pWidths, + int fSorted); +extern void PclSetSpans( + DrawablePtr pDrawable, + GCPtr pGC, + char *pSrc, + DDXPointPtr pPoints, + int *pWidths, + int nSpans, + int fSorted); + +/****** + * Functions in PclText.c + ******/ +extern int PclPolyText8( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + char *string); +extern int PclPolyText16( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *string); +extern void PclImageText8( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + char *string); +extern void PclImageText16( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int count, + unsigned short *string); +extern void PclImageGlyphBlt( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nGlyphs, + CharInfoPtr *pCharInfo, + pointer pGlyphBase); +extern void PclPolyGlyphBlt( + DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nGlyphs, + CharInfoPtr *pCharInfo, + pointer pGlyphBase); + +/****** + * Functions in PclWindow.c + ******/ +extern Bool PclCreateWindow(register WindowPtr pWin); +extern Bool PclDestroyWindow(WindowPtr pWin); +extern Bool PclMapWindow(WindowPtr pWindow); +extern Bool PclPositionWindow( + register WindowPtr pWin, + int x, + int y); +extern Bool PclUnmapWindow(WindowPtr pWindow); +extern void PclCopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); +extern Bool PclChangeWindowAttributes( + register WindowPtr pWin, + register unsigned long mask); +extern void PclPaintWindow( + WindowPtr pWin, + RegionPtr pRegion, + int what); + +/****** + * Functions in PclFonts.c + ******/ +extern Bool PclRealizeFont( + ScreenPtr pscr, + FontPtr pFont); +extern Bool PclUnrealizeFont( + ScreenPtr pscr, + FontPtr pFont); + +/****** + * Functions in PclPrint.c + ******/ +extern int PclStartJob( + XpContextPtr pCon, + Bool sendClientData, + ClientPtr client); +extern int PclEndJob( + XpContextPtr pCon, + Bool cancel); +extern int PclStartPage( + XpContextPtr pCon, + WindowPtr pWin); +extern int PclEndPage( + XpContextPtr pCon, + WindowPtr pWin); +extern int PclStartDoc(XpContextPtr pCon, + XPDocumentType type); +extern int PclEndDoc( + XpContextPtr pCon, + Bool cancel); +extern int PclDocumentData( + XpContextPtr pCon, + DrawablePtr pDraw, + char *pData, + int len_data, + char *pFmt, + int len_fmt, + char *pOpt, + int len_opt, + ClientPtr client); +extern int PclGetDocumentData( + XpContextPtr pCon, + ClientPtr client, + int maxBufferSize); + + +#endif /* _PCL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclDef.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclDef.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclDef.h (revision 51223) @@ -0,0 +1,68 @@ +/* $Xorg: PclDef.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +/******************************************************************* +** +** ********************************************************* +** * +** * File: PclDef.h +** * +** * Contents: extran defines and includes for the Pcl driver +** * for a printing X server. +** * +** * Created: 7/31/95 +** * +** ********************************************************* +** +********************************************************************/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLDEF_H_ +#define _PCLDEF_H_ + +#define DT_PRINT_JOB_HEADER "DT_PRINT_JOB_HEADER" +#define DT_PRINT_JOB_TRAILER "DT_PRINT_JOB_TRAILER" +#define DT_PRINT_JOB_COMMAND "DT_PRINT_JOB_COMMAND" +#define DT_PRINT_JOB_EXEC_COMMAND "DT_PRINT_JOB_EXEC_COMMAND" +#define DT_PRINT_JOB_EXEC_OPTIONS "DT_PRINT_JOB_EXEC_OPTION" +#define DT_PRINT_PAGE_HEADER "DT_PRINT_PAGE_HEADER" +#define DT_PRINT_PAGE_TRAILER "DT_PRINT_PAGE_TRAILER" +#define DT_PRINT_PAGE_COMMAND "DT_PRINT_PAGE_COMMAND" + +#define DT_IN_FILE_STRING "%(InFile)%" +#define DT_OUT_FILE_STRING "%(OutFile)%" +#define DT_ALLOWED_COMMANDS_FILE "printCommands" + +#endif /* _PCLDEF_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclSFonts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclSFonts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PclSFonts.h (revision 51223) @@ -0,0 +1,116 @@ +/* $Xorg: PclSFonts.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLFONTS_H +#define _PCLFONTS_H + +/* -*-H-*- +****************************************************************************** +****************************************************************************** +* +* File: PclFonts.h +* Description: Send Soft Font Download data to the specified file pointer. +* +* +****************************************************************************** +****************************************************************************** +*/ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + + +typedef struct { + unsigned char fid; /* sfont font ID */ + unsigned char cindex; /* character indext */ +} PclFontMapRec, PclFontMapPtr; + +typedef struct { + int h_offset; + int v_offset; + unsigned int width; + unsigned int height; + int font_pitch; + unsigned char *raster_top; +} PclCharDataRec, *PclCharDataPtr; + +typedef struct { + unsigned char spacing; + unsigned int pitch; + unsigned int cellheight; + unsigned int cellwidth; + int ascent; + int descent; +} PclFontDescRec, *PclFontDescPtr; + +typedef struct _PclFontHead8Rec { + char *fontname; + PclFontDescRec fd; + unsigned short fid; + unsigned char *index; + struct _PclFontHead8Rec *next; +} PclFontHead8Rec, *PclFontHead8Ptr; + +typedef struct _PclFontHead16Rec { + char *fontname; + PclFontDescRec fd; + unsigned short cur_fid; + unsigned char cur_cindex; + PclFontMapRec **index; + unsigned short firstCol; + unsigned short lastCol; + unsigned short firstRow; + unsigned short lastRow; + struct _PclFontHead16Rec *next; +} PclFontHead16Rec, *PclFontHead16Ptr; + +typedef struct _PclInternalFontRec { + char *fontname; + float pitch; + float height; + char *pcl_font_name; + char *spacing; + struct _PclInternalFontRec *next; +} PclInternalFontRec, *PclInternalFontPtr; + +typedef struct { + PclFontHead8Ptr phead8; + PclFontHead16Ptr phead16; + PclInternalFontPtr pinfont; + unsigned char cur_max_fid; +} PclSoftFontInfoRec, *PclSoftFontInfoPtr; + +#define MONOSPACE 0 +#define PROPSPACE 1 + +#endif /* _PCLFONTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pclmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pclmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Pclmap.h (revision 51223) @@ -0,0 +1,213 @@ +/* $Xorg: Pclmap.h,v 1.3 2000/08/17 19:48:08 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/Pclmap.h,v 1.5 2001/07/25 15:05:00 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PCLMAP_H_ +#define _PCLMAP_H_ + +#ifdef XP_PCL_COLOR +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclCr##subname +#define CATNAME(prefix,subname) prefix##Color##subname +#else +#define PCLNAME(subname) PclCr/**/subname +#define CATNAME(prefix,subname) prefix/**/Color/**/subname +#endif +#endif /* XP_PCL_COLOR */ + +#ifdef XP_PCL_MONO +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclMn##subname +#define CATNAME(prefix,subname) prefix##Mono##subname +#else +#define PCLNAME(subname) PclMn/**/subname +#define CATNAME(prefix,subname) prefix/**/Mono/**/subname +#endif +#endif /* XP_PCL_MONO */ + +#ifdef XP_PCL_LJ3 +#ifdef CATNAME +#undef CATNAME +#endif +#if !defined(UNIXCPP) || defined(ANSICPP) +#define PCLNAME(subname) PclLj3##subname +#define CATNAME(prefix,subname) prefix##Lj3##subname +#else +#define PCLNAME(subname) PclLj3/**/subname +#define CATNAME(prefix,subname) prefix/**/Lj3/**/subname +#endif +#endif /* XP_PCL_LJ3 */ + +#ifdef PCLNAME + +/* PclInit.c */ +#define InitializePclDriver CATNAME(Initialize, PclDriver) +#define PclCloseScreen PCLNAME(CloseScreen) +#define PclGetContextFromWindow PCLNAME(GetContextFromWindow) +#define PclScreenPrivateIndex PCLNAME(ScreenPrivateIndex) +#define PclWindowPrivateIndex PCLNAME(WindowPrivateIndex) +#define PclContextPrivateIndex PCLNAME(ContextPrivateIndex) +#define PclPixmapPrivateIndex PCLNAME(PixmapPrivateIndex) +#define PclGCPrivateIndex PCLNAME(GCPrivateIndex) + +/* PclPrint.c */ +#define PclStartJob PCLNAME(StartJob) +#define PclEndJob PCLNAME(EndJob) +#define PclStartPage PCLNAME(StartPage) +#define PclEndPage PCLNAME(EndPage) +#define PclStartDoc PCLNAME(StartDoc) +#define PclEndDoc PCLNAME(EndDoc) +#define PclDocumentData PCLNAME(DocumentData) +#define PclGetDocumentData PCLNAME(GetDocumentData) + +/* PclWindow.c */ +#define PclCreateWindow PCLNAME(CreateWindow) +#define PclMapWindow PCLNAME(MapWindow) +#define PclPositionWindow PCLNAME(PositionWindow) +#define PclUnmapWindow PCLNAME(UnmapWindow) +#define PclCopyWindow PCLNAME(CopyWindow) +#define PclChangeWindowAttributes PCLNAME(ChangeWindowAttributes) +#define PclPaintWindow PCLNAME(PaintWindow) +#define PclDestroyWindow PCLNAME(DestroyWindow) + +/* PclGC.c */ +#define PclCreateGC PCLNAME(CreateGC) +#define PclDestroyGC PCLNAME(DestroyGC) +#define PclGetDrawablePrivateStuff PCLNAME(GetDrawablePrivateStuff) +#define PclSetDrawablePrivateGC PCLNAME(SetDrawablePrivateGC) +#define PclSendPattern PCLNAME(SendPattern) +#define PclUpdateDrawableGC PCLNAME(UpdateDrawableGC) +#define PclComputeCompositeClip PCLNAME(ComputeCompositeClip) +#define PclValidateGC PCLNAME(ValidateGC) + +/* PclAttr.c */ +#define PclGetAttributes PCLNAME(GetAttributes) +#define PclGetOneAttribute PCLNAME(GetOneAttribute) +#define PclAugmentAttributes PCLNAME(AugmentAttributes) +#define PclSetAttributes PCLNAME(SetAttributes) + +/* PclColor.c */ +#define PclLookUp PCLNAME(LookUp) +#define PclCreateDefColormap PCLNAME(CreateDefColormap) +#define PclCreateColormap PCLNAME(CreateColormap) +#define PclDestroyColormap PCLNAME(DestroyColormap) +#define PclInstallColormap PCLNAME(InstallColormap) +#define PclUninstallColormap PCLNAME(UninstallColormap) +#define PclListInstalledColormaps PCLNAME(ListInstalledColormaps) +#define PclStoreColors PCLNAME(StoreColors) +#define PclResolveColor PCLNAME(ResolveColor) +#define PclFindPaletteMap PCLNAME(FindPaletteMap) +#define PclUpdateColormap PCLNAME(UpdateColormap) +#define PclReadMap PCLNAME(ReadMap) + +/* PclPixmap.c */ +#define PclCreatePixmap PCLNAME(CreatePixmap) +#define PclDestroyPixmap PCLNAME(DestroyPixmap) + +/* PclArc.c */ +#define PclDoArc PCLNAME(DoArc) +#define PclPolyArc PCLNAME(PolyArc) +#define PclPolyFillArc PCLNAME(PolyFillArc) + +/* PclArea.c */ +#define PclPutImage PCLNAME(PutImage) +#define PclCopyArea PCLNAME(CopyArea) +#define PclCopyPlane PCLNAME(CopyPlane) + +/* PclLine */ +#define PclPolyLine PCLNAME(PolyLine) +#define PclPolySegment PCLNAME(PolySegment) + +/* PclPixel.c */ +#define PclPolyPoint PCLNAME(PolyPoint) +#define PclPushPixels PCLNAME(PushPixels) + +/* PclPolygon.c */ +#define PclPolyRectangle PCLNAME(PolyRectangle) +#define PclFillPolygon PCLNAME(FillPolygon) +#define PclPolyFillRect PCLNAME(PolyFillRect) + +/* PclSpans.c */ +#define PclFillSpans PCLNAME(FillSpans) +#define PclSetSpans PCLNAME(SetSpans) + +/* PclText.c */ +#define PclPolyText8 PCLNAME(PolyText8) +#define PclPolyText16 PCLNAME(PolyText16) +#define PclImageText8 PCLNAME(ImageText8) +#define PclImageText16 PCLNAME(ImageText16) +#define PclImageGlyphBlt PCLNAME(ImageGlyphBlt) +#define PclPolyGlyphBlt PCLNAME(PolyGlyphBlt) +#define PclPolyGlyphBlt PCLNAME(PolyGlyphBlt) + +/* PclFonts.c */ +#define PclRealizeFont PCLNAME(RealizeFont) +#define PclUnrealizeFont PCLNAME(UnrealizeFont) + +/* PclSFonts.c */ +#define PclDownloadSoftFont8 PCLNAME(DownloadSoftFont8) +#define PclDownloadSoftFont16 PCLNAME(DownloadSoftFont16) +#define PclCreateSoftFontInfo PCLNAME(CreateSoftFontInfo) +#define PclDestroySoftFontInfo PCLNAME(DestroySoftFontInfo) + +/* PclMisc.c */ +#define PclQueryBestSize PCLNAME(QueryBestSize) +#define GetPropString PCLNAME(GetPropString) +#define SystemCmd PCLNAME(SystemCmd) +#define PclGetMediumDimensions PCLNAME(GetMediumDimensions) +#define PclGetReproducibleArea PCLNAME(GetReproducibleArea) +#define PclSpoolFigs PCLNAME(SpoolFigs) +#define PclSendData PCLNAME(SendData) + +/* PclCursor.c */ +#define PclConstrainCursor PCLNAME(ConstrainCursor) +#define PclCursorLimits PCLNAME(CursorLimits) +#define PclDisplayCursor PCLNAME(DisplayCursor) +#define PclRealizeCursor PCLNAME(RealizeCursor) +#define PclUnrealizeCursor PCLNAME(UnrealizeCursor) +#define PclRecolorCursor PCLNAME(RecolorCursor) +#define PclSetCursorPosition PCLNAME(SetCursorPosition) + +#endif + +#endif /* _PCLMAP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Preferences.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Preferences.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Preferences.h (revision 51223) @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/Preferences.h,v 1.2 2003/01/15 02:34:05 torrey Exp $ */ + +#import + +@interface Preferences : NSObject +{ + IBOutlet NSPanel *window; + IBOutlet id displayField; + IBOutlet id dockSwitchButton; + IBOutlet id fakeButton; + IBOutlet id button2ModifiersMatrix; + IBOutlet id button3ModifiersMatrix; + IBOutlet id switchKeyButton; + IBOutlet id keymapFileField; + IBOutlet id modeMatrix; + IBOutlet id modeWindowButton; + IBOutlet id startupHelpButton; + IBOutlet id systemBeepButton; + IBOutlet id mouseAccelChangeButton; + IBOutlet id useXineramaButton; + IBOutlet id addToPathButton; + IBOutlet id addToPathField; + IBOutlet id useDefaultShellMatrix; + IBOutlet id useOtherShellField; + IBOutlet id depthButton; + + BOOL isGettingKeyCode; + int keyCode; + int modifiers; + NSMutableString *switchString; +} + +- (IBAction)close:(id)sender; +- (IBAction)pickFile:(id)sender; +- (IBAction)saveChanges:(id)sender; +- (IBAction)setKey:(id)sender; + +- (BOOL)sendEvent:(NSEvent *)anEvent; + +- (void)awakeFromNib; +- (void)windowWillClose:(NSNotification *)aNotification; + ++ (void)setUseKeymapFile:(BOOL)newUseKeymapFile; ++ (void)setKeymapFile:(NSString *)newFile; ++ (void)setSwitchString:(NSString *)newString; ++ (void)setKeyCode:(int)newKeyCode; ++ (void)setModifiers:(int)newModifiers; ++ (void)setDisplay:(int)newDisplay; ++ (void)setDockSwitch:(BOOL)newDockSwitch; ++ (void)setFakeButtons:(BOOL)newFakeButtons; ++ (void)setButton2Mask:(int)newFakeMask; ++ (void)setButton3Mask:(int)newFakeMask; ++ (void)setMouseAccelChange:(BOOL)newMouseAccelChange; ++ (void)setUseQDCursor:(int)newUseQDCursor; ++ (void)setRootless:(BOOL)newRootless; ++ (void)setUseAGL:(BOOL)newUseAGL; ++ (void)setModeWindow:(BOOL)newModeWindow; ++ (void)setStartupHelp:(BOOL)newStartupHelp; ++ (void)setSystemBeep:(BOOL)newSystemBeep; ++ (void)setEnableKeyEquivalents:(BOOL)newKeyEquivs; ++ (void)setXinerama:(BOOL)newXinerama; ++ (void)setAddToPath:(BOOL)newAddToPath; ++ (void)setAddToPathString:(NSString *)newAddToPathString; ++ (void)setUseDefaultShell:(BOOL)newUseDefaultShell; ++ (void)setShellString:(NSString *)newShellString; ++ (void)setDepth:(int)newDepth; ++ (void)setDisplayModeBundles:(NSArray *)newBundles; ++ (void)saveToDisk; + ++ (BOOL)useKeymapFile; ++ (NSString *)keymapFile; ++ (NSString *)switchString; ++ (unsigned int)keyCode; ++ (unsigned int)modifiers; ++ (int)display; ++ (BOOL)dockSwitch; ++ (BOOL)fakeButtons; ++ (int)button2Mask; ++ (int)button3Mask; ++ (BOOL)mouseAccelChange; ++ (int)useQDCursor; ++ (BOOL)rootless; ++ (BOOL)useAGL; ++ (BOOL)modeWindow; ++ (BOOL)startupHelp; ++ (BOOL)systemBeep; ++ (BOOL)enableKeyEquivalents; ++ (BOOL)xinerama; ++ (BOOL)addToPath; ++ (NSString *)addToPathString; ++ (BOOL)useDefaultShell; ++ (NSString *)shellString; ++ (int)depth; ++ (NSArray *)displayModeBundles; + +@end + +// Possible settings for useQDCursor +enum { + qdCursor_Never, // never use QuickDraw cursor + qdCursor_Not8Bit, // don't try to use QuickDraw with 8-bit depth + qdCursor_Always // always try to use QuickDraw cursor +}; + +// Possible settings for depth +enum { + depth_Current, + depth_8Bit, + depth_15Bit, + depth_24Bit +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Ps.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Ps.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Ps.h (revision 51223) @@ -0,0 +1,590 @@ +/* $Xorg: Ps.h,v 1.5 2001/02/09 02:04:35 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: Ps.h +** * +** * Contents: defines and includes for the Ps driver +** * for a printing X server. +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PS_H_ +#define _PS_H_ + +#include + +#ifdef abs +#undef abs /* this is because of a non-Spec1170ness in misc.h */ +#endif +#include +#include "scrnintstr.h" +#include "dix.h" + +#include "PsDef.h" +#include "psout.h" + +#include +#include + +#include "regionstr.h" +#include +#include "dixfontstr.h" +#include "gcstruct.h" + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +typedef char *XPointer; +#define Status int +#define True 1 +#define False 0 +#endif + +#include "misc.h" +#include +#include +#include "attributes.h" + + +/* + * Public index variables from PsInit.c + */ + +extern int PsScreenPrivateIndex; +extern int PsWindowPrivateIndex; +extern int PsContextPrivateIndex; +extern int PsPixmapPrivateIndex; +extern XpValidatePoolsRec PsValidatePoolsRec; + +/* + * Display list structures + */ + +#define DPY_BLOCKSIZE 4096 + +typedef struct +{ + int mode; + int nPoints; + xPoint *pPoints; +} PsPolyPointsRec; + +typedef struct +{ + int nSegments; + xSegment *pSegments; +} PsSegmentsRec; + +typedef struct +{ + int nRects; + xRectangle *pRects; +} PsRectanglesRec; + +typedef struct +{ + int nArcs; + xArc *pArcs; +} PsArcsRec; + +typedef struct +{ + int x; + int y; + int count; + char *string; +} PsText8Rec; + +typedef struct +{ + int x; + int y; + int count; + unsigned short *string; +} PsText16Rec; + +typedef struct +{ + int depth; + int x; + int y; + int w; + int h; + int leftPad; + int format; + int res; /* image resolution */ + char *pData; +} PsImageRec; + +typedef struct +{ + int x; + int y; + int w; + int h; +} PsFrameRec; + +typedef enum +{ + PolyPointCmd, + PolyLineCmd, + PolySegmentCmd, + PolyRectangleCmd, + FillPolygonCmd, + PolyFillRectCmd, + PolyArcCmd, + PolyFillArcCmd, + Text8Cmd, + Text16Cmd, + TextI8Cmd, + TextI16Cmd, + PutImageCmd, + BeginFrameCmd, + EndFrameCmd +} DisplayElmType; + +typedef struct _DisplayElmRec +{ + DisplayElmType type; + GCPtr gc; + union + { + PsPolyPointsRec polyPts; + PsSegmentsRec segments; + PsRectanglesRec rects; + PsArcsRec arcs; + PsText8Rec text8; + PsText16Rec text16; + PsImageRec image; + PsFrameRec frame; + } c; +} DisplayElmRec; + +typedef DisplayElmRec *DisplayElmPtr; + +typedef struct _DisplayListRec +{ + struct _DisplayListRec *next; + int nelms; + DisplayElmRec elms[DPY_BLOCKSIZE]; +} DisplayListRec; + +typedef DisplayListRec *DisplayListPtr; + +/* + * Private structures + */ + +typedef struct +{ + XrmDatabase resDB; + Bool (*DestroyWindow)(WindowPtr); +} PsScreenPrivRec, *PsScreenPrivPtr; + +typedef struct PsFontTypeInfoRec PsFontTypeInfoRec; + +/* Structure to hold information about one font on disk + * Notes: + * - multiple XLFD names can refer to the same |PsFontTypeInfoRec| (if + * they all use the same font on the disk) + * - the FreeType font download code uses multiple |PsFontTypeInfoRec| + * records for one font on disk if they differ in the encoding being + * used (this is an exception from the + * 'one-|PsFontTypeInfoRec|-per-font-on-disk'-design; maybe it it is better + * to rework that in a later step and add a new per-encoding structure). + */ +struct PsFontTypeInfoRec +{ + PsFontTypeInfoRec *next; /* Next record in list... */ + char *adobe_ps_name; /* PostScript font name (from the + * "_ADOBE_POSTSCRIPT_FONTNAME" atom) */ + char *download_ps_name; /* PostScript font name used for font download */ + char *filename; /* File name of font */ +#ifdef XP_USE_FREETYPE + char *ft_download_encoding; /* encoding used for download */ + PsFTDownloadFontType ft_download_font_type; /* PS font type used for download (e.g. Type1/Type3/CID/etc.) */ +#endif /* XP_USE_FREETYPE */ + int is_iso_encoding; /* Is this font encoded in ISO Latin 1 ? */ + int font_type; /* See PSFTI_FONT_TYPE_* below... */ + Bool downloadableFont; /* Font can be downloaded */ + Bool alreadyDownloaded[256]; /* Font has been downloaded (for 256 8bit "sub"-font) */ +}; + +#define PSFTI_FONT_TYPE_OTHER (0) +#define PSFTI_FONT_TYPE_PMF (1) +#define PSFTI_FONT_TYPE_PS_TYPE1_PFA (2) +#define PSFTI_FONT_TYPE_PS_TYPE1_PFB (3) +#define PSFTI_FONT_TYPE_TRUETYPE (4) +/* PSFTI_FONT_TYPE_FREETYPE is means the font is handled by the freetype engine */ +#define PSFTI_FONT_TYPE_FREETYPE (5) + +typedef struct PsFontInfoRec PsFontInfoRec; + +/* Structure which represents our context info for a single XLFD font + * Note that multiple |PsFontInfoRec| records can share the same + * |PsFontTypeInfoRec| record - the |PsFontInfoRec| records represent + * different appearances of the same font on disk(=|PsFontTypeInfoRec|)). + */ +struct PsFontInfoRec +{ + PsFontInfoRec *next; /* Next record in list... */ + /* |font| and |font_fontPrivate| are used by |PsFindFontInfoRec()| to + * identify a font */ + FontPtr font; /* The font this record is for */ + pointer font_fontPrivate; + PsFontTypeInfoRec *ftir; /* Record about the font file on disk */ + const char *dfl_name; /* XLFD for this font */ + int size; /* Font size. Use |mtx| if |size==0| */ + float mtx[4]; /* Transformation matrix (see |size|) */ +}; + +typedef struct +{ + char *jobFileName; + FILE *pJobFile; + GC lastGC; + unsigned char *dash; + int validGC; + ClientPtr getDocClient; + int getDocBufSize; + PsOutPtr pPsOut; + PsFontTypeInfoRec *fontTypeInfoRecords; + PsFontInfoRec *fontInfoRecords; +} PsContextPrivRec, *PsContextPrivPtr; + +typedef struct +{ + int validContext; + XpContextPtr context; +} PsWindowPrivRec, *PsWindowPrivPtr; + +typedef struct +{ + XpContextPtr context; + GC lastGC; + int validGC; + DisplayListPtr dispList; +} PsPixmapPrivRec, *PsPixmapPrivPtr; + +/* + * Macro functions + */ + +#define SEND_PS(f,c) fwrite( c, sizeof( char ), strlen( c ), f ) +#define MIN(a,b) (((a)<(b))?(a):(b)) +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* + * Functions in PsInit.c + */ + +extern Bool InitializePsDriver(int ndx, ScreenPtr pScreen, int argc, + char **argv); +extern XpContextPtr PsGetContextFromWindow(WindowPtr win); + +/* + * Functions in PsPrint.c + */ + +extern int PsStartJob(XpContextPtr pCon, Bool sendClientData, ClientPtr client); +extern int PsEndJob(XpContextPtr pCon, Bool cancel); +extern int PsStartPage(XpContextPtr pCon, WindowPtr pWin); +extern int PsEndPage(XpContextPtr pCon, WindowPtr pWin); +extern int PsStartDoc(XpContextPtr pCon, XPDocumentType type); +extern int PsEndDoc(XpContextPtr pCon, Bool cancel); +extern int PsDocumentData(XpContextPtr pCon, DrawablePtr pDraw, char *pData, + int len_data, char *pFmt, int len_fmt, char *pOpt, int len_opt, + ClientPtr client); +extern int PsGetDocumentData(XpContextPtr pCon, ClientPtr client, + int maxBufferSize); + +/* + * Functions in PsGC.c + */ + +extern Bool PsCreateGC(GCPtr pGC); +extern PsContextPrivPtr PsGetPsContextPriv( DrawablePtr pDrawable ); +extern int PsUpdateDrawableGC(GCPtr pGC, DrawablePtr pDrawable, + PsOutPtr *psOut, ColormapPtr *cMap); +extern void PsValidateGC(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable); +extern void PsChangeGC(GCPtr pGC, unsigned long changes); +extern void PsCopyGC(GCPtr pGCSrc, unsigned long mask, GCPtr pGCDst); +extern void PsDestroyGC(GCPtr pGC); +extern void PsChangeClip(GCPtr pGC, int type, pointer pValue, int nrects); +extern void PsDestroyClip(GCPtr pGC); +extern void PsCopyClip(GCPtr pgcDst, GCPtr pgcSrc); + +extern GCPtr PsCreateAndCopyGC(DrawablePtr pDrawable, GCPtr pSrc); + +/* + * Functions in PsMisc.c + */ + +extern void PsQueryBestSize(int type, short *pwidth, short *pheight, + ScreenPtr pScreen); +extern Bool PsCloseScreen(int index, ScreenPtr pScreen); +extern void PsLineAttrs(PsOutPtr psOut, GCPtr pGC, ColormapPtr cMap); +extern int PsGetMediumDimensions( + XpContextPtr pCon, + CARD16 *pWidth, + CARD16 *pHeight); +extern int PsGetReproducibleArea( + XpContextPtr pCon, + xRectangle *pRect); +extern int PsSetImageResolution( + XpContextPtr pCon, + int imageRes, + Bool *status); + +/* + * Functions in PsSpans.c + */ + +extern void PsFillSpans(DrawablePtr pDrawable, GCPtr pGC, int nSpans, + DDXPointPtr pPoints, int *pWidths, int fSorted); +extern void PsSetSpans(DrawablePtr pDrawable, GCPtr pGC, char *pSrc, + DDXPointPtr pPoints, int *pWidths, int nSpans, + int fSorted); + +/* + * Functions in PsArea.c + */ + +extern void PsPutScaledImage(DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + int imageRes, char *pImage); +extern void PsPutImage(DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + char *pImage); +extern void PsPutImageMask(DrawablePtr pDrawable, GCPtr pGC, int depth, int x, int y, + int w, int h, int leftPad, int format, char *pImage); +extern RegionPtr PsCopyArea(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty); +extern RegionPtr PsCopyPlane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty, unsigned long plane); + +/* + * Functions in PsPixel.c + */ + +extern void PsPolyPoint(DrawablePtr pDrawable, GCPtr pGC, int mode, + int nPoints, xPoint *pPoints); +extern void PsPushPixels(GCPtr pGC, PixmapPtr pBitmap, DrawablePtr pDrawable, + int width, int height, int x, int y); + +/* + * Functions in PsLine.c + */ + +extern void PsPolyLine(DrawablePtr pDrawable, GCPtr pGC, int mode, + int nPoints, xPoint *pPoints); +extern void PsPolySegment(DrawablePtr pDrawable, GCPtr pGC, int nSegments, + xSegment *pSegments); + +/* + * Functions in PsPolygon.c + */ + +extern void PsPolyRectangle(DrawablePtr pDrawable, GCPtr pGC, int nRects, + xRectangle *pRects); +extern void PsFillPolygon(DrawablePtr pDrawable, GCPtr pGC, int shape, + int mode, int nPoints, DDXPointPtr pPoints); +extern void PsPolyFillRect(DrawablePtr pDrawable, GCPtr pGC, int nRects, + xRectangle *pRects); + +/* + * Functions in PsPolygon.c + */ + +extern void PsPolyArc(DrawablePtr pDrawable, GCPtr pGC, int nArcs, + xArc *pArcs); +extern void PsPolyFillArc(DrawablePtr pDrawable, GCPtr pGC, int nArcs, + xArc *pArcs); + +/* + * Functions in PsText.c + */ + +extern int PsPolyText8(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, char *string); +extern int PsPolyText16(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, unsigned short *string); +extern void PsImageText8(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, char *string); +extern void PsImageText16(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + int count, unsigned short *string); +extern void PsImageGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + unsigned int nGlyphs, CharInfoPtr *pCharInfo, + pointer pGlyphBase); +extern void PsPolyGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, int x, int y, + unsigned int nGlyphs, CharInfoPtr *pCharInfo, + pointer pGlyphBase); + +/* + * Functions in PsWindow.c + */ + +extern Bool PsCreateWindow(WindowPtr pWin); +extern Bool PsMapWindow(WindowPtr pWin); +extern Bool PsPositionWindow(WindowPtr pWin, int x, int y); +extern Bool PsUnmapWindow(WindowPtr pWin); +extern void PsCopyWindow(WindowPtr pWin, DDXPointRec ptOldOrg, + RegionPtr prgnSrc); +extern Bool PsChangeWindowAttributes(WindowPtr pWin, unsigned long mask); +extern void PsPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); +extern Bool PsDestroyWindow(WindowPtr pWin); + +/* + * Functions in PsFonts.c + */ + +extern Bool PsRealizeFont(ScreenPtr pscr, FontPtr pFont); +extern Bool PsUnrealizeFont(ScreenPtr pscr, FontPtr pFont); +extern char *PsGetFontName(FontPtr pFont); +extern int PsGetFontSize(FontPtr pFont, float *mtx); +extern char *PsGetPSFontName(FontPtr pFont); +extern char *PsGetPSFaceOrFontName(FontPtr pFont); +extern int PsIsISOLatin1Encoding(FontPtr pFont); +extern char *PsGetEncodingName(FontPtr pFont); +extern PsFontInfoRec *PsGetFontInfoRec(DrawablePtr pDrawable, FontPtr pFont); +extern void PsFreeFontInfoRecords(PsContextPrivPtr priv); +extern PsFTDownloadFontType PsGetFTDownloadFontType(void); + +/* + * Functions in PsFTFonts.c + */ + +extern char *PsGetFTFontFileName(FontPtr pFont); +extern Bool PsIsFreeTypeFont(FontPtr pFont); + +/* + * Functions in PsAttr.c + */ + +extern char *PsGetAttributes(XpContextPtr pCon, XPAttributes pool); +extern char *PsGetOneAttribute(XpContextPtr pCon, XPAttributes pool, + char *attr); +extern int PsAugmentAttributes(XpContextPtr pCon, XPAttributes pool, + char *attrs); +extern int PsSetAttributes(XpContextPtr pCon, XPAttributes pool, char *attrs); + +/* + * Functions in PsColor.c + */ + +extern Bool PsCreateColormap(ColormapPtr pColor); +extern void PsDestroyColormap(ColormapPtr pColor); +extern void PsInstallColormap(ColormapPtr pColor); +extern void PsUninstallColormap(ColormapPtr pColor); +extern int PsListInstalledColormaps(ScreenPtr pScreen, XID *pCmapList); +extern void PsStoreColors(ColormapPtr pColor, int ndef, xColorItem *pdefs); +extern void PsResolveColor(unsigned short *pRed, unsigned short *pGreen, + unsigned short *pBlue, VisualPtr pVisual); +extern PsOutColor PsGetPixelColor(ColormapPtr cMap, int pixval); +extern void PsSetFillColor(DrawablePtr pDrawable, GCPtr pGC, PsOutPtr psOut, + ColormapPtr cMap); + +/* + * Functions in PsPixmap.c + */ + +extern PixmapPtr PsCreatePixmap(ScreenPtr pScreen, int width, int height, + int depth); +extern void PsScrubPixmap(PixmapPtr pPixmap); +extern Bool PsDestroyPixmap(PixmapPtr pPixmap); +extern DisplayListPtr PsGetFreeDisplayBlock(PsPixmapPrivPtr priv); +extern void PsReplayPixmap(PixmapPtr pix, DrawablePtr pDrawable); +extern int PsCloneDisplayElm(PixmapPtr dst, + DisplayElmPtr elm, DisplayElmPtr newElm, + int xoff, int yoff); +extern void PsCopyDisplayList(PixmapPtr src, PixmapPtr dst, int xoff, + int yoff, int x, int y, int w, int h); +extern PsElmPtr PsCreateFillElementList(PixmapPtr pix, int *nElms); +extern PsElmPtr PsCloneFillElementList(int nElms, PsElmPtr elms); +extern void PsDestroyFillElementList(int nElms, PsElmPtr elms); + +/* + * Functions in PsImageUtil.c + */ + +extern unsigned long +PsGetImagePixel(char *pImage, int depth, int w, int h, int leftPad, int format, + int px, int py); + +#endif /* _PS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PsDef.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PsDef.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/PsDef.h (revision 51223) @@ -0,0 +1,97 @@ +/* $Xorg: PsDef.h,v 1.4 2001/02/09 02:04:36 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: PsDef.h +** * +** * Contents: extran defines and includes for the Ps driver +** * for a printing X server. +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PSDEF_H_ +#define _PSDEF_H_ + +#define DT_PRINT_JOB_HEADER "DT_PRINT_JOB_HEADER" +#define DT_PRINT_JOB_TRAILER "DT_PRINT_JOB_TRAILER" +#define DT_PRINT_JOB_COMMAND "DT_PRINT_JOB_COMMAND" +#define DT_PRINT_JOB_EXEC_COMMAND "DT_PRINT_JOB_EXEC_COMMAND" +#define DT_PRINT_JOB_EXEC_OPTIONS "DT_PRINT_JOB_EXEC_OPTION" +#define DT_PRINT_PAGE_HEADER "DT_PRINT_PAGE_HEADER" +#define DT_PRINT_PAGE_TRAILER "DT_PRINT_PAGE_TRAILER" +#define DT_PRINT_PAGE_COMMAND "DT_PRINT_PAGE_COMMAND" + +#define DT_IN_FILE_STRING "%(InFile)%" +#define DT_OUT_FILE_STRING "%(OutFile)%" +#define DT_ALLOWED_COMMANDS_FILE "printCommands" + +#endif /* _PSDEF_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/README =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/README (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/README (revision 51223) @@ -0,0 +1,13 @@ +The contents of this directory were extracted from the contents of the +archive xorg-server-X11R7.1-1.1.0.tar.bz2, as downloaded from ftp.x.org, using +the following shell script: + +for i in `find xorg-server-X11R7.1-1.1.0 -name '*.h' | grep -v hw/xwin \ + | grep -v hw/xquartz | grep -v hw/kdrive | grep -v hw/xnest \ + | grep -v hw/xprint | grep -v hw/xgl` + do + cp $i $PATH_VBOX/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ + done + +In addition, the file xf86config.h was removed, as it conflicts with +xf86Config.h on non-case-sensitive file-systems. Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Raster.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Raster.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Raster.h (revision 51223) @@ -0,0 +1,118 @@ +/* $Xorg: Raster.h,v 1.3 2000/08/17 19:48:12 cpqbld Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ +/******************************************************************* +** +** ********************************************************* +** * +** * File: printer/Raster.h +** * +** * Contents: defines and includes for the raster layer +** * for a printing X server. +** * +** * Copyright: Copyright 1993 Hewlett-Packard Company +** * +** ********************************************************* +** +********************************************************************/ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _RASTER_H_ +#define _RASTER_H_ + +/* + * Some sleazes to force the XrmDB stuff into the server + */ +#ifndef HAVE_XPointer +#define HAVE_XPointer 1 +typedef char *XPointer; +#endif +#define Status int +#define True 1 +#define False 0 +#include "misc.h" +#include +#include +#include "attributes.h" + +#include + +#define MAX_TOKEN_LEN 512 + +#define RASTER_PRINT_PAGE_COMMAND "_XP_RASTER_PAGE_PROC_COMMAND" + +#define RASTER_IN_FILE_STRING "%(InFile)%" +#define RASTER_OUT_FILE_STRING "%(OutFile)%" + +#define RASTER_ALLOWED_COMMANDS_FILE "printCommands" + +/* + * Defines for the "options" in DtPrintDocumentData. + */ +#define PRE_RASTER "PRE-RASTER" +#define POST_RASTER "POST-RASTER" +#define NO_RASTER "NO-RASTER" + + +typedef struct { + char *pBits; + CreateWindowProcPtr CreateWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + DestroyWindowProcPtr DestroyWindow; + CloseScreenProcPtr CloseScreen; +} RasterScreenPrivRec, *RasterScreenPrivPtr; + +typedef struct { + XrmDatabase config; + char *jobFileName; + FILE *pJobFile; + char *pageFileName; + FILE *pPageFile; + char *preRasterFileName; /* Pre-raster document data */ + FILE *pPreRasterFile; + char *noRasterFileName; /* Raster replacement document data */ + FILE *pNoRasterFile; + char *postRasterFileName; /* Post-raster document data */ + FILE *pPostRasterFile; + ClientPtr getDocClient; + int getDocBufSize; +} RasterContextPrivRec, *RasterContextPrivPtr; + + +extern XpValidatePoolsRec RasterValidatePoolsRec; + +extern Bool InitializeRasterDriver(int ndx, ScreenPtr pScreen, int argc, + char **argv); + +#endif /* _RASTER_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TI.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TI.h,v 1.4 2000/05/02 21:04:46 alanh Exp $ */ + +#include + +unsigned long TIramdacCalculateMNPForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP); +RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); +void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); +void TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +void TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); +unsigned long TIramdac3030CalculateMNPForClock(unsigned long RefClock, + unsigned long ReqClock, char IsPixClock, unsigned long MinClock, + unsigned long MaxClock, unsigned long *rM, unsigned long *rN, + unsigned long *rP); +void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr); +void TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); + +typedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *, + VisualPtr); +TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void); + +#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00 +#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01 + +/* + * TI Ramdac registers + */ + +#define TIDAC_rev 0x01 +#define TIDAC_ind_curs_ctrl 0x06 +#define TIDAC_byte_router_ctrl 0x07 +#define TIDAC_latch_ctrl 0x0f +#define TIDAC_true_color_ctrl 0x18 +#define TIDAC_multiplex_ctrl 0x19 +#define TIDAC_clock_select 0x1a +#define TIDAC_palette_page 0x1c +#define TIDAC_general_ctrl 0x1d +#define TIDAC_misc_ctrl 0x1e +#define TIDAC_pll_addr 0x2c +#define TIDAC_pll_pixel_data 0x2d +#define TIDAC_pll_memory_data 0x2e +#define TIDAC_pll_loop_data 0x2f +#define TIDAC_key_over_low 0x30 +#define TIDAC_key_over_high 0x31 +#define TIDAC_key_red_low 0x32 +#define TIDAC_key_red_high 0x33 +#define TIDAC_key_green_low 0x34 +#define TIDAC_key_green_high 0x35 +#define TIDAC_key_blue_low 0x36 +#define TIDAC_key_blue_high 0x37 +#define TIDAC_key_ctrl 0x38 +#define TIDAC_clock_ctrl 0x39 +#define TIDAC_sense_test 0x3a +#define TIDAC_test_mode_data 0x3b +#define TIDAC_crc_remain_lsb 0x3c +#define TIDAC_crc_remain_msb 0x3d +#define TIDAC_crc_bit_select 0x3e +#define TIDAC_id 0x3f + +/* These are pll values that are accessed via TIDAC_pll_pixel_data */ +#define TIDAC_PIXEL_N 0x80 +#define TIDAC_PIXEL_M 0x81 +#define TIDAC_PIXEL_P 0x82 +#define TIDAC_PIXEL_VALID 0x83 + +/* These are pll values that are accessed via TIDAC_pll_loop_data */ +#define TIDAC_LOOP_N 0x90 +#define TIDAC_LOOP_M 0x91 +#define TIDAC_LOOP_P 0x92 +#define TIDAC_LOOP_VALID 0x93 + +/* Direct mapping addresses */ +#define TIDAC_INDEX 0xa0 +#define TIDAC_PALETTE_DATA 0xa1 +#define TIDAC_READ_MASK 0xa2 +#define TIDAC_READ_ADDR 0xa3 +#define TIDAC_CURS_WRITE_ADDR 0xa4 +#define TIDAC_CURS_COLOR 0xa5 +#define TIDAC_CURS_READ_ADDR 0xa7 +#define TIDAC_CURS_CTL 0xa9 +#define TIDAC_INDEXED_DATA 0xaa +#define TIDAC_CURS_RAM_DATA 0xab +#define TIDAC_CURS_XLOW 0xac +#define TIDAC_CURS_XHIGH 0xad +#define TIDAC_CURS_YLOW 0xae +#define TIDAC_CURS_YHIGH 0xaf + +#define TIDAC_sw_reset 0xff + +/* Constants */ +#define TIDAC_TVP_3026_ID 0x26 +#define TIDAC_TVP_3030_ID 0x30 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TIPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TIPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/TIPriv.h (revision 51223) @@ -0,0 +1,30 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TIPriv.h,v 1.2 1998/07/25 16:57:19 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "TI.h" + +typedef struct { + char *DeviceName; +} xf86TIramdacInfo; + +extern xf86TIramdacInfo TIramdacDeviceInfo[]; + +#ifdef INIT_TI_RAMDAC_INFO +xf86TIramdacInfo TIramdacDeviceInfo[] = { + {"TI TVP3030"}, + {"TI TVP3026"} +}; +#endif + +#define TISAVE(_reg) do { \ + ramdacReg->DacRegs[_reg] = (*ramdacPtr->ReadDAC)(pScrn, _reg); \ +} while (0) + +#define TIRESTORE(_reg) do { \ + (*ramdacPtr->WriteDAC)(pScrn, _reg, \ + (ramdacReg->DacRegs[_reg] & 0xFF00) >> 8, \ + ramdacReg->DacRegs[_reg]); \ +} while (0) Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XApplication.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XApplication.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XApplication.h (revision 51223) @@ -0,0 +1,47 @@ +// +// XApplication.h +// +// Created by Andreas Monitzer on January 6, 2001. +// +/* + * Copyright (c) 2001 Andreas Monitzer. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XFree86: $ */ + +#import + +#import "XServer.h" +#import "Preferences.h" + +@interface XApplication : NSApplication { + IBOutlet XServer *xserver; + IBOutlet Preferences *preferences; +} + +- (void)sendEvent:(NSEvent *)anEvent; + +@end Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XIstubs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XIstubs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XIstubs.h (revision 51223) @@ -0,0 +1,76 @@ +/* $XFree86: xc/programs/Xserver/include/XIstubs.h,v 3.1 1996/04/15 11:34:22 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef XI_STUBS_H +#define XI_STUBS_H 1 + +int +ChangeKeyboardDevice ( + DeviceIntPtr /* old_dev */, + DeviceIntPtr /* new_dev */); + +int +ChangePointerDevice ( + DeviceIntPtr /* old_dev */, + DeviceIntPtr /* new_dev */, + unsigned char /* x */, + unsigned char /* y */); + +void +CloseInputDevice ( + DeviceIntPtr /* d */, + ClientPtr /* client */); + +void +AddOtherInputDevices (void); + +void +OpenInputDevice ( + DeviceIntPtr /* dev */, + ClientPtr /* client */, + int * /* status */); + +int +SetDeviceMode ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* mode */); + +int +SetDeviceValuators ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int * /* valuators */, + int /* first_valuator */, + int /* num_valuators */); + +int +ChangeDeviceControl ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + xDeviceCtl * /* control */); + +#endif /* XI_STUBS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XServer.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XServer.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XServer.h (revision 51223) @@ -0,0 +1,138 @@ +// +// XServer.h +// +/* + * Copyright (c) 2001 Andreas Monitzer. All Rights Reserved. + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization. + */ +/* $XdotOrg: xserver/xorg/hw/darwin/quartz/XServer.h,v 1.5 2005/07/01 22:43:07 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/XServer.h,v 1.16 2003/11/23 06:04:01 torrey Exp $ */ + +#define BOOL xBOOL +#include +#undef BOOL + +#import + +@interface XServer : NSObject { + // Server state + int serverState; + NSRecursiveLock *serverLock; + NSMutableArray *pendingClients; + BOOL serverVisible; + BOOL rootlessMenuBarVisible; + BOOL queueShowServer; + BOOL quitWithoutQuery; + BOOL pendingAppQuitReply; + UInt32 mouseState; + unsigned short swallowedKey; + BOOL sendServerEvents; + BOOL x11Active; + + // Aqua interface + IBOutlet NSWindow *modeWindow; + IBOutlet NSButton *startupModeButton; + IBOutlet NSButton *startFullScreenButton; + IBOutlet NSButton *startRootlessButton; + IBOutlet NSWindow *helpWindow; + IBOutlet NSButton *startupHelpButton; + IBOutlet NSPanel *switchWindow; + + // Menu elements setable by Apple-WM extension + IBOutlet NSMenu *windowMenu; + IBOutlet NSMenuItem *windowSeparator; + IBOutlet NSMenu *dockMenu; + int checkedWindowItem; +} + +- (id)init; + +- (BOOL)translateEvent:(NSEvent *)anEvent; +- (BOOL)getMousePosition:(xEvent *)xe fromEvent:(NSEvent *)anEvent; + +- (NSString *)makeSafePath:(NSString *)path; + +- (BOOL)loadDisplayBundle; +- (void)startX; +- (void)finishStartX; +- (BOOL)startXClients; +- (void)runClient:(NSString *)filename; +- (void)run; +- (void)toggle; +- (void)showServer:(BOOL)show; +- (void)forceShowServer:(BOOL)show; +- (void)setRootClip:(BOOL)enable; +- (void)readPasteboard; +- (void)writePasteboard; +- (void)quitServer; +- (void)sendXEvent:(xEvent *)xe; +- (void)sendShowHide:(BOOL)show; +- (void)clientProcessDone:(int)clientStatus; +- (void)activateX11:(BOOL)state; +- (void)windowBecameKey:(NSNotification *)notification; +- (void)setX11WindowList:(NSArray *)list; +- (void)setX11WindowCheck:(NSNumber *)nn; + +// Aqua interface actions +- (IBAction)startFullScreen:(id)sender; +- (IBAction)startRootless:(id)sender; +- (IBAction)closeHelpAndShow:(id)sender; +- (IBAction)showSwitchPanel:(id)sender; +- (IBAction)showAction:(id)sender; +- (IBAction)itemSelected:(id)sender; +- (IBAction)nextWindow:(id)sender; +- (IBAction)previousWindow:(id)sender; +- (IBAction)performClose:(id)sender; +- (IBAction)performMiniaturize:(id)sender; +- (IBAction)performZoom:(id)sender; +- (IBAction)bringAllToFront:(id)sender; +- (IBAction)copy:(id)sender; + +// NSApplication delegate +- (NSApplicationTerminateReply)applicationShouldTerminate:(NSApplication *)sender; +- (void)applicationWillTerminate:(NSNotification *)aNotification; +- (void)applicationDidFinishLaunching:(NSNotification *)aNotification; +- (void)applicationDidHide:(NSNotification *)aNotification; +- (void)applicationDidUnhide:(NSNotification *)aNotification; +- (BOOL)applicationShouldHandleReopen:(NSApplication *)theApplication hasVisibleWindows:(BOOL)flag; +- (void)applicationWillResignActive:(NSNotification *)aNotification; +- (void)applicationWillBecomeActive:(NSNotification *)aNotification; +- (BOOL)application:(NSApplication *)theApplication openFile:(NSString *)filename; + +// NSPort delegate +- (void)handlePortMessage:(NSPortMessage *)portMessage; + +@end + +// X server states +enum { + server_NotStarted, + server_Starting, + server_Running, + server_Quitting, + server_Done +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XView.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XView.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/XView.h (revision 51223) @@ -0,0 +1,42 @@ +/* + * NSView subclass for Mac OS X rootless X server + * + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/XView.h,v 1.2 2002/07/15 19:58:31 torrey Exp $ */ + +#import + +@interface XView : NSQuickDrawView + +- (BOOL)isFlipped; +- (BOOL)isOpaque; +- (BOOL)acceptsFirstResponder; +- (BOOL)acceptsFirstMouse:(NSEvent *)theEvent; +- (BOOL)shouldDelayWindowOrderingForEvent:(NSEvent *)theEvent; + +- (void)mouseDown:(NSEvent *)anEvent; + +@end Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Xplugin.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Xplugin.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/Xplugin.h (revision 51223) @@ -0,0 +1,591 @@ +/* Xplugin.h -- windowing API for rootless X11 server + $Id$ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. + + Note that these interfaces are provided solely for the use of the + X11 server. Any other uses are unsupported and strongly discouraged. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/Xplugin.h,v 1.2 2003/05/02 00:08:49 torrey Exp $ */ + +#ifndef XPLUGIN_H +#define XPLUGIN_H 1 + +#include + +/* By default we use the X server definition of BoxRec to define xp_box, + so that the compiler can silently convert between the two. But if + XP_NO_X_HEADERS is defined, we'll define it ourselves. */ + +#ifndef XP_NO_X_HEADERS +# include "miscstruct.h" + typedef BoxRec xp_box; +#else + struct xp_box_struct { + short x1, y1, x2, y2; + }; + typedef struct xp_box_struct xp_box; +#endif + +typedef unsigned int xp_resource_id; +typedef xp_resource_id xp_window_id; +typedef xp_resource_id xp_surface_id; +typedef unsigned int xp_client_id; +typedef unsigned int xp_request_type; +typedef int xp_error; +typedef int xp_bool; + + +/* Error codes that the functions declared here may return. They all + numerically match their X equivalents, i.e. the XP_ can be dropped + if has been included. */ + +enum xp_error_enum { + XP_Success = 0, + XP_BadRequest = 1, + XP_BadValue = 2, + XP_BadWindow = 3, + XP_BadMatch = 8, + XP_BadAccess = 10, + XP_BadImplementation = 17, +}; + + +/* Event types generated by the plugin. */ + +enum xp_event_type_enum { + /* The global display configuration changed somehow. */ + XP_EVENT_DISPLAY_CHANGED = 1 << 0, + + /* A window changed state. Argument is xp_window_state_event */ + XP_EVENT_WINDOW_STATE_CHANGED = 1 << 1, + + /* An async request encountered an error. Argument is of type + xp_async_error_event */ + XP_EVENT_ASYNC_ERROR = 1 << 2, + + /* Sent when a surface is destroyed as a side effect of destroying + a window. Arg is of type xp_surface_id. */ + XP_EVENT_SURFACE_DESTROYED = 1 << 3, + + /* Sent when any GL contexts pointing at the given surface need to + call xp_update_gl_context () to refresh their state (because the + window moved or was resized. Arg is of type xp_surface_id. */ + XP_EVENT_SURFACE_CHANGED = 1 << 4, + + /* Sent when a window has been moved. Arg is of type xp_window_id. */ + XP_EVENT_WINDOW_MOVED = 1 << 5, +}; + +/* Function type used to receive events. */ + +typedef void (xp_event_fun) (unsigned int type, const void *arg, + unsigned int arg_size, void *user_data); + + +/* Operation types. Used when reporting errors asynchronously. */ + +enum xp_request_type_enum { + XP_REQUEST_NIL = 0, + XP_REQUEST_DESTROY_WINDOW = 1, + XP_REQUEST_CONFIGURE_WINDOW = 2, + XP_REQUEST_FLUSH_WINDOW = 3, + XP_REQUEST_COPY_WINDOW = 4, + XP_REQUEST_UNLOCK_WINDOW = 5, + XP_REQUEST_DISABLE_UPDATE = 6, + XP_REQUEST_REENABLE_UPDATE = 7, + XP_REQUEST_HIDE_CURSOR = 8, + XP_REQUEST_SHOW_CURSOR = 9, + XP_REQUEST_FRAME_DRAW = 10, +}; + +/* Structure used to report an error asynchronously. Passed as the "arg" + of an XP_EVENT_ASYNC_ERROR event. */ + +struct xp_async_error_event_struct { + xp_request_type request_type; + xp_resource_id id; + xp_error error; +}; + +typedef struct xp_async_error_event_struct xp_async_error_event; + + +/* Possible window states. */ + +enum xp_window_state_enum { + /* The window is not in the global list of possibly-visible windows. */ + XP_WINDOW_STATE_OFFSCREEN = 1 << 0, + + /* Parts of the window may be obscured by other windows. */ + XP_WINDOW_STATE_OBSCURED = 1 << 1, +}; + +/* Structure passed as argument of an XP_EVENT_WINDOW_STATE_CHANGED event. */ + +struct xp_window_state_event_struct { + xp_window_id id; + unsigned int state; +}; + +typedef struct xp_window_state_event_struct xp_window_state_event; + + +/* Function type used to supply a colormap for indexed drawables. */ + +typedef xp_error (xp_colormap_fun) (void *data, int first_color, + int n_colors, uint32_t *colors); + + +/* Window attributes structure. Used when creating and configuring windows. + Also used when configuring surfaces attached to windows. Functions that + take one of these structures also take a bit mask defining which + fields are set to meaningful values. */ + +enum xp_window_changes_enum { + XP_ORIGIN = 1 << 0, + XP_SIZE = 1 << 1, + XP_BOUNDS = XP_ORIGIN | XP_SIZE, + XP_SHAPE = 1 << 2, + XP_STACKING = 1 << 3, + XP_DEPTH = 1 << 4, + XP_COLORMAP = 1 << 5, + XP_WINDOW_LEVEL = 1 << 6, +}; + +struct xp_window_changes_struct { + /* XP_ORIGIN */ + int x, y; + + /* XP_SIZE */ + unsigned int width, height; + int bit_gravity; /* how to resize the backing store */ + + /* XP_SHAPE */ + int shape_nrects; /* -1 = remove shape */ + xp_box *shape_rects; + int shape_tx, shape_ty; /* translation for shape */ + + /* XP_STACKING */ + int stack_mode; + xp_window_id sibling; /* may be zero; in ABOVE/BELOW modes + it may specify a relative window */ + /* XP_DEPTH, window-only */ + unsigned int depth; + + /* XP_COLORMAP, window-only */ + xp_colormap_fun *colormap; + void *colormap_data; + + /* XP_WINDOW_LEVEL, window-only */ + int window_level; +}; + +typedef struct xp_window_changes_struct xp_window_changes; + +/* Values for bit_gravity field */ + +enum xp_bit_gravity_enum { + XP_GRAVITY_NONE = 0, /* no gravity, fill everything */ + XP_GRAVITY_NORTH_WEST = 1, /* anchor to top-left corner */ + XP_GRAVITY_NORTH_EAST = 2, /* anchor to top-right corner */ + XP_GRAVITY_SOUTH_EAST = 3, /* anchor to bottom-right corner */ + XP_GRAVITY_SOUTH_WEST = 4, /* anchor to bottom-left corner */ +}; + +/* Values for stack_mode field */ + +enum xp_window_stack_mode_enum { + XP_UNMAPPED = 0, /* remove the window */ + XP_MAPPED_ABOVE = 1, /* display the window on top */ + XP_MAPPED_BELOW = 2, /* display the window at bottom */ +}; + +/* Data formats for depth field and composite functions */ + +enum xp_depth_enum { + XP_DEPTH_NIL = 0, /* null source when compositing */ + XP_DEPTH_ARGB8888, + XP_DEPTH_RGB555, + XP_DEPTH_A8, /* for masks when compositing */ + XP_DEPTH_INDEX8, +}; + +/* Options that may be passed to the xp_init () function. */ + +enum xp_init_options_enum { + /* Don't mark that this process can be in the foreground. */ + XP_IN_BACKGROUND = 1 << 0, + + /* Deliver background pointer events to this process. */ + XP_BACKGROUND_EVENTS = 1 << 1, +}; + + + +/* Miscellaneous functions */ + +/* Initialize the plugin library. Only the copy/fill/composite functions + may be called without having previously called xp_init () */ + +extern xp_error xp_init (unsigned int options); + +/* Sets the current set of requested notifications to MASK. When any of + these arrive, CALLBACK will be invoked with CALLBACK-DATA. Note that + calling this function cancels any previously requested notifications + that aren't set in MASK. */ + +extern xp_error xp_select_events (unsigned int mask, + xp_event_fun *callback, + void *callback_data); + +/* Waits for all initiated operations to complete. */ + +extern xp_error xp_synchronize (void); + +/* Causes any display update initiated through the plugin libary to be + queued until update is reenabled. Note that calls to these functions + nest. */ + +extern xp_error xp_disable_update (void); +extern xp_error xp_reenable_update (void); + + + +/* Cursor functions. */ + +/* Installs the specified cursor. ARGB-DATA should point to 32-bit + premultiplied big-endian ARGB data. The HOT-X,HOT-Y parameters + specify the offset to the cursor's hot spot from its top-left + corner. */ + +extern xp_error xp_set_cursor (unsigned int width, unsigned int height, + unsigned int hot_x, unsigned int hot_y, + const uint32_t *argb_data, + unsigned int rowbytes); + +/* Hide and show the cursor if it's owned by the current process. Calls + to these functions nest. */ + +extern xp_error xp_hide_cursor (void); +extern xp_error xp_show_cursor (void); + + + +/* Window functions. */ + +/* Create a new window as defined by MASK and VALUES. MASK must contain + XP_BOUNDS or an error is raised. The id of the newly created window + is stored in *RET-ID if this function returns XP_Success. */ + +extern xp_error xp_create_window (unsigned int mask, + const xp_window_changes *values, + xp_window_id *ret_id); + +/* Destroys the window identified by ID. */ + +extern xp_error xp_destroy_window (xp_window_id id); + +/* Reconfigures the given window according to MASK and VALUES. */ + +extern xp_error xp_configure_window (xp_window_id id, unsigned int mask, + const xp_window_changes *values); + + +/* Returns true if NATIVE-ID is a window created by the plugin library. + If so and RET-ID is non-null, stores the id of the window in *RET-ID. */ + +extern xp_bool xp_lookup_native_window (unsigned int native_id, + xp_window_id *ret_id); + +/* If ID names a window created by the plugin library, stores it's native + window id in *RET-NATIVE-ID. */ + +extern xp_error xp_get_native_window (xp_window_id id, + unsigned int *ret_native_id); + + +/* Locks the rectangle IN-RECT (or, if null, the entire window) of the + given window's backing store. Any other non-null parameters are filled + in as follows: + + DEPTH = format of returned data. Currently either XP_DEPTH_ARGB8888 + or XP_DEPTH_RGB565 (possibly with 8 bit planar alpha). Data is + always stored in native byte order. + + BITS[0] = pointer to top-left pixel of locked color data + BITS[1] = pointer to top-left of locked alpha data, or null if window + has no alpha. If the alpha data is meshed, then BITS[1] = BITS[0]. + + ROWBYTES[0,1] = size in bytes of each row of color,alpha data + + OUT-RECT = rectangle specifying the current position and size of the + locked region relative to the window origin. + + Note that an error is raised when trying to lock an already locked + window. While the window is locked, the only operations that may + be performed on it are to modify, access or flush its marked region. */ + +extern xp_error xp_lock_window (xp_window_id id, + const xp_box *in_rect, + unsigned int *depth, + void *bits[2], + unsigned int rowbytes[2], + xp_box *out_rect); + +/* Mark that the region specified by SHAPE-NRECTS, SHAPE-RECTS, + SHAPE-TX, and SHAPE-TY in the specified window has been updated, and + will need to subsequently be redisplayed. */ + +extern xp_error xp_mark_window (xp_window_id id, int shape_nrects, + const xp_box *shape_rects, + int shape_tx, int shape_ty); + +/* Unlocks the specified window. If FLUSH is true, then any marked + regions are immediately redisplayed. Note that it's an error to + unlock an already unlocked window. */ + +extern xp_error xp_unlock_window (xp_window_id id, xp_bool flush); + +/* If anything is marked in the given window for redisplay, do it now. */ + +extern xp_error xp_flush_window (xp_window_id id); + +/* Moves the contents of the region DX,DY pixels away from that specified + by DST_RECTS and DST_NRECTS in the window with SRC-ID to the + destination region in the window DST-ID. Note that currently source + and destination windows must be the same. */ + +extern xp_error xp_copy_window (xp_window_id src_id, xp_window_id dst_id, + int dst_nrects, const xp_box *dst_rects, + int dx, int dy); + +/* Returns true if the given window has any regions marked for + redisplay. */ + +extern xp_bool xp_is_window_marked (xp_window_id id); + +/* If successful returns a superset of the region marked for update in + the given window. Use xp_free_region () to release the returned data. */ + +extern xp_error xp_get_marked_shape (xp_window_id id, + int *ret_nrects, xp_box **ret_rects); + +extern void xp_free_shape (int nrects, xp_box *rects); + +/* Searches for the first window below ABOVE-ID containing the point X,Y, + and returns it's window id in *RET-ID. If no window is found, *RET-ID + is set to zero. If ABOVE-ID is zero, finds the topmost window + containing the given point. */ + +extern xp_error xp_find_window (int x, int y, xp_window_id above_id, + xp_window_id *ret_id); + +/* Returns the current origin and size of the window ID in *BOUNDS-RET if + successful. */ +extern xp_error xp_get_window_bounds (xp_window_id id, xp_box *bounds_ret); + + + +/* Window surface functions. */ + +/* Create a new VRAM surface on the specified window. If successful, + returns the identifier of the new surface in *RET-SID. */ + +extern xp_error xp_create_surface (xp_window_id id, xp_surface_id *ret_sid); + +/* Destroys the specified surface. */ + +extern xp_error xp_destroy_surface (xp_surface_id sid); + +/* Reconfigures the specified surface as defined by MASK and VALUES. + Note that specifying XP_DEPTH is an error. */ + +extern xp_error xp_configure_surface (xp_surface_id sid, unsigned int mask, + const xp_window_changes *values); + +/* If successful, places the client identifier of the current process + in *RET-CLIENT. */ + +extern xp_error xp_get_client_id (xp_client_id *ret_client); + +/* Given a valid window,surface combination created by the current + process, attempts to allow the specified external client access + to that surface. If successful, returns two integers in RET-KEY + which the client can use to import the surface into their process. */ + +extern xp_error xp_export_surface (xp_window_id wid, xp_surface_id sid, + xp_client_id client, + unsigned int ret_key[2]); + +/* Given a two integer key returned from xp_export_surface (), tries + to import the surface into the current process. If successful the + local surface identifier is stored in *SID-RET. */ + +extern xp_error xp_import_surface (const unsigned int key[2], + xp_surface_id *sid_ret); + +/* If successful, stores the number of surfaces attached to the + specified window in *RET. */ + +extern xp_error xp_get_window_surface_count (xp_window_id id, + unsigned int *ret); + +/* Attaches the CGLContextObj CGL-CTX to the specified surface. */ + +extern xp_error xp_attach_gl_context (void *cgl_ctx, xp_surface_id sid); + +/* Updates the CGLContextObj CGL-CTX to reflect any recent changes to + the surface it's attached to. */ + +extern xp_error xp_update_gl_context (void *cgl_ctx); + + + +/* Window frame functions. */ + +/* Possible arguments to xp_frame_get_rect (). */ + +enum xp_frame_rect_enum { + XP_FRAME_RECT_TITLEBAR = 1, + XP_FRAME_RECT_TRACKING = 2, + XP_FRAME_RECT_GROWBOX = 3, +}; + +/* Classes of window frame. */ + +enum xp_frame_class_enum { + XP_FRAME_CLASS_DOCUMENT = 1 << 0, + XP_FRAME_CLASS_DIALOG = 1 << 1, + XP_FRAME_CLASS_MODAL_DIALOG = 1 << 2, + XP_FRAME_CLASS_SYSTEM_MODAL_DIALOG = 1 << 3, + XP_FRAME_CLASS_UTILITY = 1 << 4, + XP_FRAME_CLASS_TOOLBAR = 1 << 5, + XP_FRAME_CLASS_MENU = 1 << 6, + XP_FRAME_CLASS_SPLASH = 1 << 7, + XP_FRAME_CLASS_BORDERLESS = 1 << 8, +}; + +/* Attributes of window frames. */ + +enum xp_frame_attr_enum { + XP_FRAME_ACTIVE = 0x0001, + XP_FRAME_URGENT = 0x0002, + XP_FRAME_TITLE = 0x0004, + XP_FRAME_PRELIGHT = 0x0008, + XP_FRAME_SHADED = 0x0010, + XP_FRAME_CLOSE_BOX = 0x0100, + XP_FRAME_COLLAPSE = 0x0200, + XP_FRAME_ZOOM = 0x0400, + XP_FRAME_ANY_BUTTON = 0x0700, + XP_FRAME_CLOSE_BOX_CLICKED = 0x0800, + XP_FRAME_COLLAPSE_BOX_CLICKED = 0x1000, + XP_FRAME_ZOOM_BOX_CLICKED = 0x2000, + XP_FRAME_ANY_CLICKED = 0x3800, + XP_FRAME_GROW_BOX = 0x4000, +}; + +#define XP_FRAME_ATTR_IS_SET(a,b) (((a) & (b)) == (b)) +#define XP_FRAME_ATTR_IS_CLICKED(a,m) ((a) & ((m) << 3)) +#define XP_FRAME_ATTR_SET_CLICKED(a,m) ((a) |= ((m) << 3)) +#define XP_FRAME_ATTR_UNSET_CLICKED(a,m) ((a) &= ~((m) << 3)) + +#define XP_FRAME_POINTER_ATTRS (XP_FRAME_PRELIGHT \ + | XP_FRAME_ANY_BUTTON \ + | XP_FRAME_ANY_CLICKED) + +extern xp_error xp_frame_get_rect (int type, int class, const xp_box *outer, + const xp_box *inner, xp_box *ret); +extern xp_error xp_frame_hit_test (int class, int x, int y, + const xp_box *outer, + const xp_box *inner, int *ret); +extern xp_error xp_frame_draw (xp_window_id wid, int class, unsigned int attr, + const xp_box *outer, const xp_box *inner, + unsigned int title_len, + const unsigned char *title_bytes); + + + +/* Memory manipulation functions. */ + +enum xp_composite_op_enum { + XP_COMPOSITE_SRC = 0, + XP_COMPOSITE_OVER, +}; + +#define XP_COMPOSITE_FUNCTION(op, src_depth, mask_depth, dest_depth) \ + (((op) << 24) | ((src_depth) << 16) \ + | ((mask_depth) << 8) | ((dest_depth) << 0)) + +#define XP_COMPOSITE_FUNCTION_OP(f) (((f) >> 24) & 255) +#define XP_COMPOSITE_FUNCTION_SRC_DEPTH(f) (((f) >> 16) & 255) +#define XP_COMPOSITE_FUNCTION_MASK_DEPTH(f) (((f) >> 8) & 255) +#define XP_COMPOSITE_FUNCTION_DEST_DEPTH(f) (((f) >> 0) & 255) + +/* Composite WIDTH by HEIGHT pixels from source and mask to destination + using a specified function (if source and destination overlap, + undefined behavior results). + + For SRC and DEST, the first element of the array is the color data. If + the second element is non-null it implies that there is alpha data + (which may be meshed or planar). Data without alpha is assumed to be + opaque. + + Passing a null SRC-ROWBYTES pointer implies that the data SRC points + to is a single element. + + Operations that are not supported will return XP_BadImplementation. */ + +extern xp_error xp_composite_pixels (unsigned int width, unsigned int height, + unsigned int function, + void *src[2], unsigned int src_rowbytes[2], + void *mask, unsigned int mask_rowbytes, + void *dest[2], unsigned int dest_rowbytes[2]); + +/* Fill HEIGHT rows of data starting at DST. Each row will have WIDTH + bytes filled with the 32-bit pattern VALUE. Each row is DST-ROWBYTES + wide in total. */ + +extern void xp_fill_bytes (unsigned int width, + unsigned int height, uint32_t value, + void *dst, unsigned int dst_rowbytes); + +/* Copy HEIGHT rows of bytes from SRC to DST. Each row will have WIDTH + bytes copied. SRC and DST may overlap, and the right thing will happen. */ + +extern void xp_copy_bytes (unsigned int width, unsigned int height, + const void *src, unsigned int src_rowbytes, + void *dst, unsigned int dst_rowbytes); + +/* Suggestions for the minimum number of bytes or pixels for which it + makes sense to use some of the xp_ functions */ + +extern unsigned int xp_fill_bytes_threshold, xp_copy_bytes_threshold, + xp_composite_area_threshold, xp_scroll_area_threshold; + + +#endif /* XPLUGIN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/afb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/afb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/afb.h (revision 51223) @@ -0,0 +1,1127 @@ +/* $XFree86: xc/programs/Xserver/afb/afb.h,v 3.10 2003/10/29 22:15:19 tsi Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.0, 1/17/89 */ +/*********************************************************** + +Copyright (c) 1987 X Consortium + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of the X Consortium shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the X Consortium. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XConsortium: afb.h,v 5.31 94/04/17 20:28:15 dpw Exp $ */ +/* Monochrome Frame Buffer definitions + written by drewry, september 1986 +*/ + +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "regionstr.h" +#include "mibstore.h" +#include "mfb.h" + +extern int afbInverseAlu[]; +extern int afbScreenPrivateIndex; +/* warning: PixelType definition duplicated in maskbits.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ + +#define AFB_MAX_DEPTH 8 + +/* afbbitblt.c */ + +extern void afbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr afbBitBlt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (*doBitBlt)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ + ), + unsigned long /*planemask*/ +); + +extern RegionPtr afbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern RegionPtr afbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); + +extern void afbCopy1ToN( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltC.c */ + +extern void afbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltCI.c */ + +extern void afbDoBitbltCopyInverted( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltG.c */ + +extern void afbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltO.c */ + +extern void afbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbltX.c */ + +extern void afbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* afbbres.c */ + +extern void afbBresS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* afbbresd.c */ + +extern void afbBresD( + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/, + unsigned char * /*rrops*/, + unsigned char * /*bgrrops*/ +); +/* afbbstore.c */ + +extern void afbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void afbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* afbclip.c */ + +extern RegionPtr afbPixmapToRegion( + PixmapPtr /*pPix*/ +); + +/* afbcmap.c */ + +extern int afbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void afbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void afbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void afbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool afbInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern int afbExpandDirectColors( + ColormapPtr /*pmap*/, + int /*ndefs*/, + xColorItem * /*indefs*/, + xColorItem * /*outdefs*/ +); + +extern Bool afbCreateDefColormap( + ScreenPtr /*pScreen*/ +); + +extern Bool afbSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +extern Bool afbInitVisuals( + VisualPtr * /*visualp*/, + DepthPtr * /*depthp*/, + int * /*nvisualp*/, + int * /*ndepthp*/, + int * /*rootDepthp*/, + VisualID * /*defaultVisp*/, + unsigned long /*sizes*/, + int /*bitsPerRGB*/ +); + +/* afbfillarc.c */ + +extern void afbPolyFillArcSolid( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* afbfillrct.c */ + +extern void afbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); + +/* afbply1rct.c */ +extern void afbFillPolygonSolid( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*shape*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* afbfillsp.c */ + +extern void afbSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void afbUnnaturalOpaqueStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +/* afbfont.c */ + +extern Bool afbRealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +extern Bool afbUnrealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); +/* afbgc.c */ + +extern Bool afbCreateGC( + GCPtr /*pGC*/ +); + +extern void afbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +extern void afbDestroyGC( + GCPtr /*pGC*/ +); + +extern void afbReduceRop( + int /*alu*/, + Pixel /*src*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void afbReduceOpaqueStipple ( + Pixel /*fg*/, + Pixel /*bg*/, + unsigned long /*planemask*/, + int /*depth*/, + unsigned char * /*rrops*/ +); + +extern void afbComputeCompositeClip( + GCPtr /*pGC*/, + DrawablePtr /*pDrawable*/ +); + +/* afbgetsp.c */ + +extern void afbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* afbhrzvert.c */ + +extern void afbHorzS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); + +extern void afbVertS( + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*x1*/, + int /*y1*/, + int /*len*/, + unsigned char * /*rrops*/ +); +/* afbigbblak.c */ + +extern void afbImageGlyphBlt ( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* afbigbwht.c */ + +/* afbimage.c */ + +extern void afbPutImage( + DrawablePtr /*dst*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void afbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* afbline.c */ + +extern void afbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void afbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +/* afbmisc.c */ + +extern void afbQueryBestSize( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/ +); +/* afbpntarea.c */ + +extern void afbSolidFillArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + unsigned char * /*rrops*/ +); + +extern void afbStippleAreaPPW( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + unsigned char * /*rrops*/ +); +extern void afbStippleArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + PixmapPtr /*pstipple*/, + int /*xOff*/, + int /*yOff*/, + unsigned char * /*rrops*/ +); +/* afbplygblt.c */ + +extern void afbPolyGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +/* afbpixmap.c */ + +extern PixmapPtr afbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool afbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr afbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void afbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void afbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void afbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void afbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +extern void afbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); +/* afbpolypnt.c */ + +extern void afbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* afbpushpxl.c */ + +extern void afbPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* afbscrclse.c */ + +extern Bool afbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); +/* afbscrinit.c */ + +extern Bool afbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*pWinIndex*/, + int * /*pGCIndex*/ +); + +extern Bool afbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr afbGetWindowPixmap( + WindowPtr /*pWin*/ +); + +extern void afbSetWindowPixmap( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/ +); + +/* afbseg.c */ + +extern void afbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void afbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* afbsetsp.c */ + +extern void afbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + PixelType * /*psrc*/, + int /*alu*/, + PixelType * /*pdstBase*/, + int /*widthDst*/, + int /*sizeDst*/, + int /*depthDst*/, + int /*sizeSrc*/ +); + +extern void afbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* afbtegblt.c */ + +extern void afbTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* afbtileC.c */ + +extern void afbTileAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbTileAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned long /*planemask*/ +); + +extern void afbTileAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbTileAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned long /*planemask*/ +); + +extern void afbOpaqueStippleAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbOpaqueStippleAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +extern void afbOpaqueStippleAreaCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); +/* afbtileG.c */ + +extern void afbOpaqueStippleAreaGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/, + int /*xOff*/, + int /*yOff*/, + unsigned char */*rropsOS*/, + unsigned long /*planemask*/ +); + +/* afbwindow.c */ + +extern Bool afbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool afbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool afbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool afbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool afbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void afbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool afbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* afbzerarc.c */ + +extern void afbZeroPolyArcSS( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* + private field of pixmap + pixmap.devPrivate = (PixelType *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes + + private field of screen + a pixmap, for which we allocate storage. devPrivate is a pointer to +the bits in the hardware framebuffer. note that devKind can be poked to +make the code work for framebuffers that are wider than their +displayable screen (e.g. the early vsII, which displayed 960 pixels +across, but was 1024 in the hardware.) + + private field of GC +*/ + +typedef struct { + unsigned char rrops[AFB_MAX_DEPTH]; /* reduction of rasterop to 1 of 3 */ + unsigned char rropOS[AFB_MAX_DEPTH]; /* rop for opaque stipple */ +} afbPrivGC; +typedef afbPrivGC *afbPrivGCPtr; + +extern int afbGCPrivateIndex; /* index into GC private array */ +extern int afbWindowPrivateIndex; /* index into Window private array */ +#ifdef PIXMAP_PER_WINDOW +extern int frameWindowPrivateIndex; /* index into Window private array */ +#endif + +#define afbGetGCPrivate(pGC) \ + ((afbPrivGC *)((pGC)->devPrivates[afbGCPrivateIndex].ptr)) + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border tile is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; +} afbPrivWin; + +/* Common macros for extracting drawing information */ + +#define afbGetTypedWidth(pDrawable,wtype)( \ + (((pDrawable)->type == DRAWABLE_WINDOW) ? \ + (int)(((PixmapPtr)((pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr))->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define afbGetByteWidth(pDrawable) afbGetTypedWidth(pDrawable, unsigned char) + +#define afbGetPixelWidth(pDrawable) afbGetTypedWidth(pDrawable, PixelType) + +#define afbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr)(pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + else \ + _pPix = (PixmapPtr)(pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define afbGetPixelWidthSizeDepthAndPointer(pDrawable, width, size, dep, pointer) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr)(pDrawable)->pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + else \ + _pPix = (PixmapPtr)(pDrawable); \ + (pointer) = (PixelType *)_pPix->devPrivate.ptr; \ + (width) = ((int)_pPix->devKind) / sizeof (PixelType); \ + (size) = (width) * _pPix->drawable.height; \ + (dep) = _pPix->drawable.depth; (void)(dep); \ +} + +#define afbGetByteWidthAndPointer(pDrawable, width, pointer) \ + afbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define afbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + afbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define afbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = (PixmapPtr)(pWin)->drawable.pScreen->devPrivates[afbScreenPrivateIndex].ptr; \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define afbGetWindowPixelWidthAndPointer(pWin, width, pointer) \ + afbGetWindowTypedWidthAndPointer(pWin, width, pointer, PixelType, PixelType) + +#define afbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + afbGetWindowTypedWidthAndPointer(pWin, width, pointer, char, char) + +/* afb uses the following macros to calculate addresses in drawables. + * To support banked framebuffers, the macros come in four flavors. + * All four collapse into the same definition on unbanked devices. + * + * afbScanlineFoo - calculate address and do bank switching + * afbScanlineFooNoBankSwitch - calculate address, don't bank switch + * afbScanlineFooSrc - calculate address, switch source bank + * afbScanlineFooDst - calculate address, switch destination bank + */ + +/* The NoBankSwitch versions are the same for banked and unbanked cases */ + +#define afbScanlineIncNoBankSwitch(_ptr, _off) _ptr += (_off) +#define afbScanlineOffsetNoBankSwitch(_ptr, _off) ((_ptr) + (_off)) +#define afbScanlineDeltaNoBankSwitch(_ptr, _y, _w) \ + afbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w)) +#define afbScanlineNoBankSwitch(_ptr, _x, _y, _w) \ + afbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +#ifdef MFB_LINE_BANK + +#include "afblinebank.h" /* get macro definitions from this file */ + +#else /* !MFB_LINE_BANK - unbanked case */ + +#define afbScanlineInc(_ptr, _off) afbScanlineIncNoBankSwitch(_ptr, _off) +#define afbScanlineIncSrc(_ptr, _off) afbScanlineInc(_ptr, _off) +#define afbScanlineIncDst(_ptr, _off) afbScanlineInc(_ptr, _off) + +#define afbScanlineOffset(_ptr, _off) afbScanlineOffsetNoBankSwitch(_ptr, _off) +#define afbScanlineOffsetSrc(_ptr, _off) afbScanlineOffset(_ptr, _off) +#define afbScanlineOffsetDst(_ptr, _off) afbScanlineOffset(_ptr, _off) + +#define afbScanlineSrc(_ptr, _x, _y, _w) afbScanline(_ptr, _x, _y, _w) +#define afbScanlineDst(_ptr, _x, _y, _w) afbScanline(_ptr, _x, _y, _w) + +#define afbScanlineDeltaSrc(_ptr, _y, _w) afbScanlineDelta(_ptr, _y, _w) +#define afbScanlineDeltaDst(_ptr, _y, _w) afbScanlineDelta(_ptr, _y, _w) + +#endif /* MFB_LINE_BANK */ + +#define afbScanlineDelta(_ptr, _y, _w) \ + afbScanlineOffset(_ptr, (_y) * (_w)) + +#define afbScanline(_ptr, _x, _y, _w) \ + afbScanlineOffset(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +/* precomputed information about each glyph for GlyphBlt code. + this saves recalculating the per glyph information for each box. +*/ + +typedef struct _afbpos{ + int xpos; /* xposition of glyph's origin */ + int xchar; /* x position mod 32 */ + int leftEdge; + int rightEdge; + int topEdge; + int bottomEdge; + PixelType *pdstBase; /* longword with character origin */ + int widthGlyph; /* width in bytes of this glyph */ +} afbTEXTPOS; + +/* reduced raster ops for afb */ +#define RROP_BLACK GXclear +#define RROP_WHITE GXset +#define RROP_NOP GXnoop +#define RROP_INVERT GXinvert +#define RROP_COPY GXcopy + +/* macros for afbbitblt.c, afbfillsp.c + these let the code do one switch on the rop per call, rather + than a switch on the rop per item (span or rectangle.) +*/ + +#define fnCLEAR(src, dst) (0) +#define fnAND(src, dst) (src & dst) +#define fnANDREVERSE(src, dst) (src & ~dst) +#define fnCOPY(src, dst) (src) +#define fnANDINVERTED(src, dst) (~src & dst) +#define fnNOOP(src, dst) (dst) +#define fnXOR(src, dst) (src ^ dst) +#define fnOR(src, dst) (src | dst) +#define fnNOR(src, dst) (~(src | dst)) +#define fnEQUIV(src, dst) (~src ^ dst) +#define fnINVERT(src, dst) (~dst) +#define fnORREVERSE(src, dst) (src | ~dst) +#define fnCOPYINVERTED(src, dst) (~src) +#define fnORINVERTED(src, dst) (~src | dst) +#define fnNAND(src, dst) (~(src & dst)) +#undef fnSET +#define fnSET(src, dst) (~0) + +/* Using a "switch" statement is much faster in most cases + * since the compiler can do a look-up table or multi-way branch + * instruction, depending on the architecture. The result on + * A Sun 3/50 is at least 2.5 times faster, assuming a uniform + * distribution of RasterOp operation types. + * + * However, doing some profiling on a running system reveals + * GXcopy is the operation over 99.5% of the time and + * GXxor is the next most frequent (about .4%), so we make special + * checks for those first. + * + * Note that this requires a change to the "calling sequence" + * since we can't engineer a "switch" statement to have an lvalue. + */ +#undef DoRop +#define DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) \ + result = fnCOPY (src, dst); \ + else if (alu == GXxor) \ + result = fnXOR (src, dst); \ + else \ + switch (alu) { \ + case GXclear: \ + result = fnCLEAR (src, dst); \ + break; \ + case GXand: \ + result = fnAND (src, dst); \ + break; \ + case GXandReverse: \ + result = fnANDREVERSE (src, dst); \ + break; \ + case GXandInverted: \ + result = fnANDINVERTED (src, dst); \ + break; \ + default: \ + case GXnoop: \ + result = fnNOOP (src, dst); \ + break; \ + case GXor: \ + result = fnOR (src, dst); \ + break; \ + case GXnor: \ + result = fnNOR (src, dst); \ + break; \ + case GXequiv: \ + result = fnEQUIV (src, dst); \ + break; \ + case GXinvert: \ + result = fnINVERT (src, dst); \ + break; \ + case GXorReverse: \ + result = fnORREVERSE (src, dst); \ + break; \ + case GXcopyInverted: \ + result = fnCOPYINVERTED (src, dst); \ + break; \ + case GXorInverted: \ + result = fnORINVERTED (src, dst); \ + break; \ + case GXnand: \ + result = fnNAND (src, dst); \ + break; \ + case GXset: \ + result = fnSET (src, dst); \ + break; \ + } \ +} + + +/* C expression fragments for various operations. These get passed in + * as -D's on the compile command line. See afb/Imakefile. This + * fixes XBUG 6319. + * + * This seems like a good place to point out that afb's use of the + * words black and white is an unfortunate misnomer. In afb code, black + * means zero, and white means one. + */ +#define MFB_OPEQ_WHITE |= +#define MFB_OPEQ_BLACK &=~ +#define MFB_OPEQ_INVERT ^= +#define MFB_EQWHOLEWORD_WHITE =~0 +#define MFB_EQWHOLEWORD_BLACK =0 +#define MFB_EQWHOLEWORD_INVERT ^=~0 +#define MFB_OP_WHITE /* nothing */ +#define MFB_OP_BLACK ~ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/agpgart.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/agpgart.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/agpgart.h (revision 51223) @@ -0,0 +1,109 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/os-support/solaris/agpgart.h,v 1.2 2005/07/01 22:43:25 daniels Exp $ */ +/* + * AGPGART module version 0.99 + * Copyright (C) 1999 Jeff Hartmann + * Copyright (C) 1999 Precision Insight, Inc. + * Copyright (C) 1999 Xi Graphics, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, and/or sell copies of the Software, and to permit persons + * to whom the Software is furnished to do so, provided that the above + * copyright notice(s) and this permission notice appear in all copies of + * the Software and that both the above copyright notice(s) and this + * permission notice appear in supporting documentation. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT + * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL + * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING + * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Except as contained in this notice, the name of a copyright holder + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * of the copyright holder. + */ + +#ifndef _AGPGART_H +#define _AGPGART_H + +#pragma ident "@(#)agpgart.h 1.1 05/04/04 SMI" + +typedef struct _agp_version { + uint16_t agpv_major; + uint16_t agpv_minor; +} agp_version_t; + +typedef struct _agp_info { + agp_version_t agpi_version; + uint32_t agpi_devid; /* bridge vendor + device */ + uint32_t agpi_mode; /* mode of bridge */ + ulong_t agpi_aperbase; /* base of aperture */ + size_t agpi_apersize; /* aperture range size */ + uint32_t agpi_pgtotal; /* max number of pages in aperture */ + uint32_t agpi_pgsystem; /* same as pg_total */ + uint32_t agpi_pgused; /* NUMBER of currently used pages */ +} agp_info_t; + +typedef struct _agp_setup { + uint32_t agps_mode; +} agp_setup_t; + +typedef struct _agp_allocate { + int32_t agpa_key; + uint32_t agpa_pgcount; + uint32_t agpa_type; + uint32_t agpa_physical; /* for i810/830 driver */ +} agp_allocate_t; + +typedef struct _agp_bind { + int32_t agpb_key; + uint32_t agpb_pgstart; +} agp_bind_t; + +typedef struct _agp_unbind { + int32_t agpu_key; + uint32_t agpu_pri; /* no use in solaris */ +} agp_unbind_t; + +#define AGPIOC_BASE 'G' +#define AGPIOC_INFO _IOR(AGPIOC_BASE, 0, 100) +#define AGPIOC_ACQUIRE _IO(AGPIOC_BASE, 1) +#define AGPIOC_RELEASE _IO(AGPIOC_BASE, 2) +#define AGPIOC_SETUP _IOW(AGPIOC_BASE, 3, agp_setup_t) +#define AGPIOC_ALLOCATE _IOWR(AGPIOC_BASE, 4, agp_allocate_t) +#define AGPIOC_DEALLOCATE _IOW(AGPIOC_BASE, 5, int) +#define AGPIOC_BIND _IOW(AGPIOC_BASE, 6, agp_bind_t) +#define AGPIOC_UNBIND _IOW(AGPIOC_BASE, 7, agp_unbind_t) + +#define AGP_DEVICE "/dev/agpgart" + +#endif /* _AGPGART_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/allowev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/allowev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/allowev.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef ALLOWEV_H +#define ALLOWEV_H 1 + +int SProcXAllowDeviceEvents(ClientPtr /* client */ + ); + +int ProcXAllowDeviceEvents(ClientPtr /* client */ + ); + +#endif /* ALLOWEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/altixPCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/altixPCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/altixPCI.h (revision 51223) @@ -0,0 +1,20 @@ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_ALTIX_H +#define PCI_ALTIX_H 1 + +#include +#include + +Bool xorgProbeAltix(scanpciWrapperOpt flags); +void xf86PreScanAltix(void); +void xf86PostScanAltix(void); + +/* Some defines for PCI */ +#define VENDOR_SGI 0x10A9 +#define CHIP_TIO_CA 0x1010 +#define CHIP_PIC_PCI 0x1011 + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aout.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aout.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aout.h (revision 51223) @@ -0,0 +1,235 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/aout.h,v 1.7 2002/05/31 18:46:00 dawes Exp $ */ + +/* + * Borrowed from NetBSD's exec_aout.h + * + * Copyright (c) 1993, 1994 Christopher G. Demetriou + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AOUT_H +#define _AOUT_H + +#include + +/* Get prototype for ntohl, per SuSv3. */ +#include + +/* OS/2 EMX has ntohl in this file */ +#ifdef __UNIXOS2__ +#include +#endif + +#define __LDPGSZ 4096U +#ifndef AOUT_PAGSIZ +#define AOUT_PAGSIZ(ex) (__LDPGSZ) +#endif + +/* + * a.out header + */ +typedef struct AOUT_exec { + unsigned long a_midmag; /* htonl(flags<<26 | mid<<16 | magic) */ + unsigned long a_text; /* text segment size */ + unsigned long a_data; /* initialized data size */ + unsigned long a_bss; /* uninitialized data size */ + unsigned long a_syms; /* symbol table size */ + unsigned long a_entry; /* entry point */ + unsigned long a_trsize; /* text relocation size */ + unsigned long a_drsize; /* data relocation size */ +} AOUTHDR; + +/* a_magic */ +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ +#define QMAGIC 0314 /* "compact" demand load format; deprecated */ + +/* + * a_mid - keep sorted in numerical order for sanity's sake + * ensure that: 0 < mid < 0x3ff + */ +#define MID_ZERO 0 /* unknown - implementation dependent */ +#define MID_SUN010 1 /* sun 68010/68020 binary */ +#define MID_SUN020 2 /* sun 68020-only binary */ +#define MID_PC386 100 /* 386 PC binary. (so quoth BFD) */ +#define MID_HP200 200 /* hp200 (68010) BSD binary */ +#define MID_I386 134 /* i386 BSD binary */ +#define MID_M68K 135 /* m68k BSD binary with 8K page sizes */ +#define MID_M68K4K 136 /* m68k BSD binary with 4K page sizes */ +#define MID_NS32532 137 /* ns32532 */ +#define MID_SPARC 138 /* sparc */ +#define MID_PMAX 139 /* pmax */ +#define MID_VAX 140 /* vax */ +#define MID_ALPHA 141 /* Alpha BSD binary */ +#define MID_MIPS 142 /* big-endian MIPS */ +#define MID_ARM6 143 /* ARM6 */ +#define MID_HP300 300 /* hp300 (68020+68881) BSD binary */ +#define MID_HPUX 0x20C /* hp200/300 HP-UX binary */ +#define MID_HPUX800 0x20B /* hp800 HP-UX binary */ + +/* + * a_flags + */ +#define EX_DYNAMIC 0x20 +#define EX_PIC 0x10 +#define EX_DPMASK 0x30 +/* + * Interpretation of the (a_flags & EX_DPMASK) bits: + * + * 00 traditional executable or object file + * 01 object file contains PIC code (set by `as -k') + * 10 dynamic executable + * 11 position independent executable image + * (eg. a shared library) + * + */ + +/* + * The a.out structure's a_midmag field is a network-byteorder encoding + * of this int + * FFFFFFmmmmmmmmmmMMMMMMMMMMMMMMMM + * Where `F' is 6 bits of flag like EX_DYNAMIC, + * `m' is 10 bits of machine-id like MID_I386, and + * `M' is 16 bits worth of magic number, ie. ZMAGIC. + * The macros below will set/get the needed fields. + */ +#define AOUT_GETMAGIC(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? (ntohl(((ex)->a_midmag))&0xffffU) : ((ex)->a_midmag)) +#define AOUT_GETMAGIC2(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? (ntohl(((ex)->a_midmag))&0xffffU) : \ + (((ex)->a_midmag) | 0x10000) ) +#define AOUT_GETMID(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? ((ntohl(((ex)->a_midmag))>>16)&0x03ffU) : MID_ZERO ) +#define AOUT_GETFLAG(ex) \ + ( (((ex)->a_midmag)&0xffff0000U) ? ((ntohl(((ex)->a_midmag))>>26)&0x3fU) : 0 ) +#define AOUT_SETMAGIC(ex,mag,mid,flag) \ + ( (ex)->a_midmag = htonl( (((flag)&0x3fU)<<26) | (((mid)&0x03ffU)<<16) | \ + (((mag)&0xffffU)) ) ) + +#define AOUT_ALIGN(ex,x) \ + (AOUT_GETMAGIC(ex) == ZMAGIC || AOUT_GETMAGIC(ex) == QMAGIC ? \ + ((x) + __LDPGSZ - 1) & ~(__LDPGSZ - 1) : (x)) + +/* Valid magic number check. */ +#define AOUT_BADMAG(ex) \ + (AOUT_GETMAGIC(ex) != NMAGIC && AOUT_GETMAGIC(ex) != OMAGIC && \ + AOUT_GETMAGIC(ex) != ZMAGIC && AOUT_GETMAGIC(ex) != QMAGIC) + +/* Address of the bottom of the text segment. */ +#define AOUT_TXTADDR(ex) (AOUT_GETMAGIC2(ex) == (ZMAGIC|0x10000) ? 0 : __LDPGSZ) + +/* Address of the bottom of the data segment. */ +#define AOUT_DATADDR(ex) \ + (AOUT_GETMAGIC(ex) == OMAGIC ? AOUT_TXTADDR(ex) + (ex)->a_text : \ + (AOUT_TXTADDR(ex) + (ex)->a_text + __LDPGSZ - 1) & ~(__LDPGSZ - 1)) + +/* Address of the bottom of the bss segment. */ +#define AOUT_BSSADDR(ex) \ + (AOUT_DATADDR(ex) + (ex)->a_data) + +/* Text segment offset. */ +#define AOUT_TXTOFF(ex) \ + ( AOUT_GETMAGIC2(ex)==ZMAGIC || AOUT_GETMAGIC2(ex)==(QMAGIC|0x10000) ? \ + 0 : (AOUT_GETMAGIC2(ex)==(ZMAGIC|0x10000) ? __LDPGSZ : \ + sizeof(struct AOUT_exec)) ) + +/* Data segment offset. */ +#define AOUT_DATOFF(ex) \ + AOUT_ALIGN(ex, AOUT_TXTOFF(ex) + (ex)->a_text) + +/* Text relocation table offset. */ +#define AOUT_TRELOFF(ex) \ + (AOUT_DATOFF(ex) + (ex)->a_data) + +/* Data relocation table offset. */ +#define AOUT_DRELOFF(ex) \ + (AOUT_TRELOFF(ex) + (ex)->a_trsize) + +/* Symbol table offset. */ +#define AOUT_SYMOFF(ex) \ + (AOUT_DRELOFF(ex) + (ex)->a_drsize) + +/* String table offset. */ +#define AOUT_STROFF(ex) \ + (AOUT_SYMOFF(ex) + (ex)->a_syms) + +/* Relocation format. */ +struct relocation_info_i386 { + int r_address; /* offset in text or data segment */ + unsigned int r_symbolnum:24, /* ordinal number of add symbol */ + r_pcrel:1, /* 1 if value should be pc-relative */ + r_length:2, /* log base 2 of value's width */ + r_extern:1, /* 1 if need to add symbol to value */ + r_baserel:1, /* linkage table relative */ + r_jmptable:1, /* relocate to jump table */ + r_relative:1, /* load address relative */ + r_copy:1; /* run time copy */ +}; + +#define relocation_info relocation_info_i386 + +/* + * Symbol table entry format. The #ifdef's are so that programs including + * nlist.h can initialize nlist structures statically. + */ +typedef struct AOUT_nlist { + union { + char *n_name; /* symbol name (in memory) */ + long n_strx; /* file string table offset (on disk) */ + } n_un; + +#define AOUT_UNDF 0x00 /* undefined */ +#define AOUT_ABS 0x02 /* absolute address */ +#define AOUT_TEXT 0x04 /* text segment */ +#define AOUT_DATA 0x06 /* data segment */ +#define AOUT_BSS 0x08 /* bss segment */ +#define AOUT_INDR 0x0a /* alias definition */ +#define AOUT_SIZE 0x0c /* pseudo type, defines a symbol's size */ +#define AOUT_COMM 0x12 /* common reference */ +#define AOUT_FN 0x1e /* file name (AOUT_EXT on) */ +#define AOUT_WARN 0x1e /* warning message (AOUT_EXT off) */ + +#define AOUT_EXT 0x01 /* external (global) bit, OR'ed in */ +#define AOUT_TYPE 0x1e /* mask for all the type bits */ + unsigned char n_type; /* type defines */ + + char n_other; /* spare */ +#define n_hash n_desc /* used internally by ld(1); XXX */ + short n_desc; /* used by stab entries */ + unsigned long n_value; /* address/value of the symbol */ +} AOUT_nlist; + +#define AOUT_FORMAT "%08x" /* namelist value format; XXX */ +#define AOUT_STAB 0x0e0 /* mask for debugger symbols -- stab(5) */ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aoutloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aoutloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/aoutloader.h (revision 51223) @@ -0,0 +1,35 @@ +/* + * Copyright 1997,1998 Metro Link, Inc. + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/aoutloader.h,v 1.3 1998/09/20 14:41:03 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AOUTLOADER_H +#define _AOUTLOADER_H +extern void *AOUTLoadModule(loaderPtr, int, LOOKUP **, int flags); +extern void AOUTResolveSymbols(void *); +extern int AOUTCheckForUnresolved(void *); +extern char *AOUTAddressToSection(void *, unsigned long); +extern void AOUTUnloadModule(void *); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/appgroup.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/appgroup.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/appgroup.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86$ */ + +void XagClientStateChange( + CallbackListPtr* pcbl, + pointer nulldata, + pointer calldata); +int ProcXagCreate ( + register ClientPtr client); +int ProcXagDestroy( + register ClientPtr client); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/applewmExt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/applewmExt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/applewmExt.h (revision 51223) @@ -0,0 +1,85 @@ +/* + * External interface for the server's AppleWM support + */ +/************************************************************************** + +Copyright (c) 2002 Apple Computer, Inc. All Rights Reserved. +Copyright (c) 2003-2004 Torrey T. Lyons. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/applewmExt.h,v 1.2 2003/11/11 23:48:41 torrey Exp $ */ + +#ifndef _APPLEWMEXT_H_ +#define _APPLEWMEXT_H_ + +#include "window.h" + +typedef int (*DisableUpdateProc)(void); +typedef int (*EnableUpdateProc)(void); +typedef int (*SetWindowLevelProc)(WindowPtr pWin, int level); +typedef int (*FrameGetRectProc)(int type, int class, const BoxRec *outer, + const BoxRec *inner, BoxRec *ret); +typedef int (*FrameHitTestProc)(int class, int x, int y, + const BoxRec *outer, + const BoxRec *inner, int *ret); +typedef int (*FrameDrawProc)(WindowPtr pWin, int class, unsigned int attr, + const BoxRec *outer, const BoxRec *inner, + unsigned int title_len, + const unsigned char *title_bytes); + +/* + * AppleWM implementation function list + */ +typedef struct _AppleWMProcs { + DisableUpdateProc DisableUpdate; + EnableUpdateProc EnableUpdate; + SetWindowLevelProc SetWindowLevel; + FrameGetRectProc FrameGetRect; + FrameHitTestProc FrameHitTest; + FrameDrawProc FrameDraw; +} AppleWMProcsRec, *AppleWMProcsPtr; + +void AppleWMExtensionInit( + AppleWMProcsPtr procsPtr +); + +void AppleWMSetScreenOrigin( + WindowPtr pWin +); + +Bool AppleWMDoReorderWindow( + WindowPtr pWin +); + +void AppleWMSendEvent( + int /* type */, + unsigned int /* mask */, + int /* which */, + int /* arg */ +); + +unsigned int AppleWMSelectedEvents( + void +); + +#endif /* _APPLEWMEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ar.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ar.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ar.h (revision 51223) @@ -0,0 +1,75 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/ar.h,v 1.3 1998/07/25 16:56:12 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _AR_H +#define _AR_H + +#define ARMAG "!\n" +#define SARMAG 8 +#define ARFMAG "`\n" + +#if !(defined(__powerpc__) && defined(Lynx)) +struct ar_hdr { + char ar_name[16]; + char ar_date[12]; + char ar_uid[6]; + char ar_gid[6]; + char ar_mode[8]; + char ar_size[10]; + char ar_fmag[2]; +}; + +#else + +#define AIAMAG "\n" +#define SAIAMAG 8 +#define AIAFMAG "`\n" + +struct fl_hdr { /* archive fixed length header - printable ascii */ + char fl_magic[SAIAMAG]; /* Archive file magic string */ + char fl_memoff[12]; /* Offset to member table */ + char fl_gstoff[12]; /* Offset to global symbol table */ + char fl_fstmoff[12]; /* Offset to first archive member */ + char fl_lstmoff[12]; /* Offset to last archive member */ + char fl_freeoff[12]; /* Offset to first mem on free list */ +}; + +#define FL_HDR struct fl_hdr +#define FL_HSZ sizeof(FL_HDR) + +struct ar_hdr { /* archive file member header - printable ascii */ + char ar_size[12]; /* file member size - decimal */ + char ar_nxtmem[12]; /* pointer to next member - decimal */ + char ar_prvmem[12]; /* pointer to previous member - decimal */ + char ar_date[12]; /* file member date - decimal */ + char ar_uid[12]; /* file member user id - decimal */ + char ar_gid[12]; /* file member group id - decimal */ + char ar_mode[12]; /* file member mode - octal */ + char ar_namlen[4]; /* file member name length - decimal */ + union { + char an_name[2]; /* variable length member name */ + char an_fmag[2]; /* AIAFMAG - string to end header */ + } _ar_name; /* and variable length name */ +}; + +#define ar_name _ar_name.an_name + +/* + * Note: 'ar_namlen' contains the length of the member name which + * may be up to 255 chars. The character string containing + * the name begins at '_ar_name.ar_name'. The terminating + * string AIAFMAG, is only cosmetic. File member contents begin + * at the first even byte boundary past 'header position + + * sizeof(struct ar_hdr) + ar_namlen', and continue for + * 'ar_size' bytes. +*/ + +#define AR_HDR struct ar_hdr +#define AR_HSZ sizeof(AR_HDR) + +#endif /* !__powerpc__ && Lynx */ + +#endif /* _AR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/assyntax.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/assyntax.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/assyntax.h (revision 51223) @@ -0,0 +1,753 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/assyntax.h,v 3.13 2003/08/24 17:37:03 dawes Exp $ */ + +#ifndef __ASSYNTAX_H__ +#define __ASSYNTAX_H__ + +/* + * Copyright 1992 Vrije Universiteit, The Netherlands + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the Vrije Universiteit not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The Vrije Universiteit makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * The Vrije Universiteit DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL The Vrije Universiteit BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 1993-1999 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: assyntax.h /main/5 1996/02/21 17:50:49 kaleb $ */ + + /* + * assyntax.h + * + * Select the syntax appropriate to the 386 assembler being used + * To add support for more assemblers add more columns to the CHOICE + * macro. Note that register names must also have uppercase names + * to avoid macro recursion. e.g., #define ah %ah recurses! + * + * NB 1. Some of the macros for certain assemblers imply that the code is to + * run in protected mode!! Caveat emptor. + * + * NB 2. 486 specific instructions are not included. This is to discourage + * their accidental use in code that is intended to run on 386 and 486 + * systems. + * + * Supported assemblers: + * + * (a) AT&T SysVr4 as(1): default + * (b) GNU Assembler gas: define USE_GAS or GNU_ASSEMBLER + * (c) Amsterdam Compiler kit: define ACK_ASSEMBLER + * + * The following naming conventions have been used to identify the various + * data types: + * _SR = segment register version + * Integer: + * _Q = quadword = 64 bits + * _L = long = 32 bits + * _W = short = 16 bits + * _B = byte = 8 bits + * Floating-point: + * _X = m80real = 80 bits + * _D = double = 64 bits + * _S = single = 32 bits + * + * Author: Gregory J. Sharp, Sept 1992 + * Vrije Universiteit, Amsterdam, The Netherlands + */ + +#if defined(USE_GAS) && !defined(GNU_ASSEMBLER) +#define GNU_ASSEMBLER +#endif + +#if (defined(__STDC__) && !defined(UNIXCPP)) || (defined (sun) && defined (i386) && defined (SVR4) && defined (__STDC__) && !defined (__GNUC__)) +#define CONCAT(x, y) x ## y +#else +#define CONCAT(x, y) x/**/y +#endif + +#ifdef ACK_ASSEMBLER + +/* Assume we write code for 32-bit protected mode! */ + +/* Redefine register names for GAS & AT&T assemblers */ +#define AL al +#define AH ah +#define AX ax +#define EAX ax +#define BL bl +#define BH bh +#define BX bx +#define EBX bx +#define CL cl +#define CH ch +#define CX cx +#define ECX cx +#define DL dl +#define DH dh +#define DX dx +#define EDX dx +#define BP bp +#define EBP bp +#define SI si +#define ESI si +#define DI di +#define EDI di +#define SP sp +#define ESP sp +#define CS cs +#define SS ss +#define DS ds +#define ES es +#define FS fs +#define GS gs +/* Control Registers */ +#define CR0 cr0 +#define CR1 cr1 +#define CR2 cr2 +#define CR3 cr3 +/* Debug Registers */ +#define DR0 dr0 +#define DR1 dr1 +#define DR2 dr2 +#define DR3 dr3 +#define DR4 dr4 +#define DR5 dr5 +#define DR6 dr6 +#define DR7 dr7 +/* Floating-point Stack */ +#define ST st + +#define AS_BEGIN .sect .text; .sect .rom; .sect .data; .sect .bss; .sect .text + + +#define _WTOG o16 /* word toggle for _W instructions */ +#define _LTOG /* long toggle for _L instructions */ +#define ADDR_TOGGLE a16 +#define OPSZ_TOGGLE o16 +#define USE16 .use16 +#define USE32 .use32 + +#define CHOICE(a,b,c) c + +#else /* AT&T or GAS */ + +/* Redefine register names for GAS & AT&T assemblers */ +#define AL %al +#define AH %ah +#define AX %ax +#define EAX %eax +#define BL %bl +#define BH %bh +#define BX %bx +#define EBX %ebx +#define CL %cl +#define CH %ch +#define CX %cx +#define ECX %ecx +#define DL %dl +#define DH %dh +#define DX %dx +#define EDX %edx +#define BP %bp +#define EBP %ebp +#define SI %si +#define ESI %esi +#define DI %di +#define EDI %edi +#define SP %sp +#define ESP %esp +#define CS %cs +#define SS %ss +#define DS %ds +#define ES %es +#define FS %fs +#define GS %gs +/* Control Registers */ +#define CR0 %cr0 +#define CR1 %cr1 +#define CR2 %cr2 +#define CR3 %cr3 +/* Debug Registers */ +#define DR0 %db0 +#define DR1 %db1 +#define DR2 %db2 +#define DR3 %db3 +#define DR4 %db4 +#define DR5 %db5 +#define DR6 %db6 +#define DR7 %db7 +/* Floating-point Stack */ +#define ST %st + +#define AS_BEGIN +#define USE16 +#define USE32 + +#ifdef GNU_ASSEMBLER + +#define ADDR_TOGGLE aword +#define OPSZ_TOGGLE word + +#define CHOICE(a,b,c) b + +#else +/* + * AT&T ASSEMBLER SYNTAX + * ********************* + */ +#define CHOICE(a,b,c) a + +#define ADDR_TOGGLE addr16 +#define OPSZ_TOGGLE data16 + +#endif /* GNU_ASSEMBLER */ +#endif /* ACK_ASSEMBLER */ + + +#if defined(__QNX__) || defined(Lynx) || (defined(SYSV) || defined(SVR4)) && !defined(ACK_ASSEMBLER) || defined(__ELF__) || defined(__GNU__) +#define GLNAME(a) a +#else +#define GLNAME(a) CONCAT(_,a) +#endif + + + /****************************************/ + /* */ + /* Select the various choices */ + /* */ + /****************************************/ + + +/* Redefine assembler directives */ +/*********************************/ +#define GLOBL CHOICE(.globl, .globl, .extern) +#define ALIGNTEXT4 CHOICE(.align 4, .align ARG2(2,0x90), .align 4) +#define ALIGNTEXT2 CHOICE(.align 2, .align ARG2(1,0x90), .align 2) +/* ALIGNTEXT4ifNOP is the same as ALIGNTEXT4, but only if the space is + * guaranteed to be filled with NOPs. Otherwise it does nothing. + */ +#define ALIGNTEXT4ifNOP CHOICE(.align 4, .align ARG2(2,0x90), /*can't do it*/) +#define ALIGNDATA4 CHOICE(.align 4, .align ARG2(2,0x0), .align 4) +#define ALIGNDATA2 CHOICE(.align 2, .align ARG2(1,0x0), .align 2) +#define FILE(s) CHOICE(.file s, .file s, .file s) +#define STRING(s) CHOICE(.string s, .asciz s, .asciz s) +#define D_LONG CHOICE(.long, .long, .data4) +#define D_WORD CHOICE(.value, .short, .data2) +#define D_BYTE CHOICE(.byte, .byte, .data1) +#define SPACE CHOICE(.comm, .space, .space) +#define COMM CHOICE(.comm, .comm, .comm) +#define SEG_DATA CHOICE(.data, .data, .sect .data) +#define SEG_TEXT CHOICE(.text, .text, .sect .text) +#define SEG_BSS CHOICE(.bss, .bss, .sect .bss) + +#ifdef GNU_ASSEMBLER +#define D_SPACE(n) . = . + n +#else +#define D_SPACE(n) .space n +#endif + +/* Addressing Modes */ +/* Immediate Mode */ +#define ADDR(a) CHOICE(CONCAT($,a), CONCAT($,a), a) +#define CONST(a) CHOICE(CONCAT($,a), CONCAT($,a), a) + +/* Indirect Mode */ +#define CONTENT(a) CHOICE(a, a, (a)) /* take contents of variable */ +#define REGIND(a) CHOICE((a), (a), (a)) /* Register a indirect */ +/* Register b indirect plus displacement a */ +#define REGOFF(a, b) CHOICE(a(b), a(b), a(b)) +/* Reg indirect Base + Index + Displacement - this is mainly for 16-bit mode + * which has no scaling + */ +#define REGBID(b,i,d) CHOICE(d(b,i), d(b,i), d(b)(i)) +/* Reg indirect Base + (Index * Scale) + Displacement */ +#define REGBISD(b,i,s,d) CHOICE(d(b,i,s), d(b,i,s), d(b)(i*s)) +/* Displaced Scaled Index: */ +#define REGDIS(d,i,s) CHOICE(d(,i,s), d(,i,s), d(i * s)) +/* Indexed Base: */ +#define REGBI(b,i) CHOICE((b,i), (b,i), (b)(i)) +/* Displaced Base: */ +#define REGDB(d,b) CHOICE(d(b), d(b), d(b)) +/* Variable indirect: */ +#define VARINDIRECT(var) CHOICE(*var, *var, (var)) +/* Use register contents as jump/call target: */ +#define CODEPTR(reg) CHOICE(*reg, *reg, reg) + +/* For expressions requiring bracketing + * eg. (CRT0_PM | CRT_EM) + */ + +#define EXPR(a) CHOICE([a], (a), [a]) +#define ENOT(a) CHOICE(0!a, ~a, ~a) +#define EMUL(a,b) CHOICE(a\*b, a*b, a*b) +#define EDIV(a,b) CHOICE(a\/b, a/b, a/b) + +/* + * We have to beat the problem of commas within arguments to choice. + * eg. choice (add a,b, add b,a) will get argument mismatch. Luckily ANSI + * and other known cpp definitions evaluate arguments before substitution + * so the following works. + */ +#define ARG2(a, b) a,b +#define ARG3(a,b,c) a,b,c + +/* Redefine assembler commands */ +#define AAA CHOICE(aaa, aaa, aaa) +#define AAD CHOICE(aad, aad, aad) +#define AAM CHOICE(aam, aam, aam) +#define AAS CHOICE(aas, aas, aas) +#define ADC_L(a, b) CHOICE(adcl ARG2(a,b), adcl ARG2(a,b), _LTOG adc ARG2(b,a)) +#define ADC_W(a, b) CHOICE(adcw ARG2(a,b), adcw ARG2(a,b), _WTOG adc ARG2(b,a)) +#define ADC_B(a, b) CHOICE(adcb ARG2(a,b), adcb ARG2(a,b), adcb ARG2(b,a)) +#define ADD_L(a, b) CHOICE(addl ARG2(a,b), addl ARG2(a,b), _LTOG add ARG2(b,a)) +#define ADD_W(a, b) CHOICE(addw ARG2(a,b), addw ARG2(a,b), _WTOG add ARG2(b,a)) +#define ADD_B(a, b) CHOICE(addb ARG2(a,b), addb ARG2(a,b), addb ARG2(b,a)) +#define AND_L(a, b) CHOICE(andl ARG2(a,b), andl ARG2(a,b), _LTOG and ARG2(b,a)) +#define AND_W(a, b) CHOICE(andw ARG2(a,b), andw ARG2(a,b), _WTOG and ARG2(b,a)) +#define AND_B(a, b) CHOICE(andb ARG2(a,b), andb ARG2(a,b), andb ARG2(b,a)) +#define ARPL(a,b) CHOICE(arpl ARG2(a,b), arpl ARG2(a,b), arpl ARG2(b,a)) +#define BOUND_L(a, b) CHOICE(boundl ARG2(a,b), boundl ARG2(b,a), _LTOG bound ARG2(b,a)) +#define BOUND_W(a, b) CHOICE(boundw ARG2(a,b), boundw ARG2(b,a), _WTOG bound ARG2(b,a)) +#define BSF_L(a, b) CHOICE(bsfl ARG2(a,b), bsfl ARG2(a,b), _LTOG bsf ARG2(b,a)) +#define BSF_W(a, b) CHOICE(bsfw ARG2(a,b), bsfw ARG2(a,b), _WTOG bsf ARG2(b,a)) +#define BSR_L(a, b) CHOICE(bsrl ARG2(a,b), bsrl ARG2(a,b), _LTOG bsr ARG2(b,a)) +#define BSR_W(a, b) CHOICE(bsrw ARG2(a,b), bsrw ARG2(a,b), _WTOG bsr ARG2(b,a)) +#define BT_L(a, b) CHOICE(btl ARG2(a,b), btl ARG2(a,b), _LTOG bt ARG2(b,a)) +#define BT_W(a, b) CHOICE(btw ARG2(a,b), btw ARG2(a,b), _WTOG bt ARG2(b,a)) +#define BTC_L(a, b) CHOICE(btcl ARG2(a,b), btcl ARG2(a,b), _LTOG btc ARG2(b,a)) +#define BTC_W(a, b) CHOICE(btcw ARG2(a,b), btcw ARG2(a,b), _WTOG btc ARG2(b,a)) +#define BTR_L(a, b) CHOICE(btrl ARG2(a,b), btrl ARG2(a,b), _LTOG btr ARG2(b,a)) +#define BTR_W(a, b) CHOICE(btrw ARG2(a,b), btrw ARG2(a,b), _WTOG btr ARG2(b,a)) +#define BTS_L(a, b) CHOICE(btsl ARG2(a,b), btsl ARG2(a,b), _LTOG bts ARG2(b,a)) +#define BTS_W(a, b) CHOICE(btsw ARG2(a,b), btsw ARG2(a,b), _WTOG bts ARG2(b,a)) +#define CALL(a) CHOICE(call a, call a, call a) +#define CALLF(s,a) CHOICE(lcall ARG2(s,a), lcall ARG2(s,a), callf s:a) +#define CBW CHOICE(cbtw, cbw, cbw) +#define CWDE CHOICE(cwtd, cwde, cwde) +#define CLC CHOICE(clc, clc, clc) +#define CLD CHOICE(cld, cld, cld) +#define CLI CHOICE(cli, cli, cli) +#define CLTS CHOICE(clts, clts, clts) +#define CMC CHOICE(cmc, cmc, cmc) +#define CMP_L(a, b) CHOICE(cmpl ARG2(a,b), cmpl ARG2(a,b), _LTOG cmp ARG2(b,a)) +#define CMP_W(a, b) CHOICE(cmpw ARG2(a,b), cmpw ARG2(a,b), _WTOG cmp ARG2(b,a)) +#define CMP_B(a, b) CHOICE(cmpb ARG2(a,b), cmpb ARG2(a,b), cmpb ARG2(b,a)) +#define CMPS_L CHOICE(cmpsl, cmpsl, _LTOG cmps) +#define CMPS_W CHOICE(cmpsw, cmpsw, _WTOG cmps) +#define CMPS_B CHOICE(cmpsb, cmpsb, cmpsb) +#define CWD CHOICE(cwtl, cwd, cwd) +#define CDQ CHOICE(cltd, cdq, cdq) +#define DAA CHOICE(daa, daa, daa) +#define DAS CHOICE(das, das, das) +#define DEC_L(a) CHOICE(decl a, decl a, _LTOG dec a) +#define DEC_W(a) CHOICE(decw a, decw a, _WTOG dec a) +#define DEC_B(a) CHOICE(decb a, decb a, decb a) +#define DIV_L(a) CHOICE(divl a, divl a, div a) +#define DIV_W(a) CHOICE(divw a, divw a, div a) +#define DIV_B(a) CHOICE(divb a, divb a, divb a) +#define ENTER(a,b) CHOICE(enter ARG2(a,b), enter ARG2(a,b), enter ARG2(b,a)) +#define HLT CHOICE(hlt, hlt, hlt) +#define IDIV_L(a) CHOICE(idivl a, idivl a, _LTOG idiv a) +#define IDIV_W(a) CHOICE(idivw a, idivw a, _WTOG idiv a) +#define IDIV_B(a) CHOICE(idivb a, idivb a, idivb a) +/* More forms than this for imul!! */ +#define IMUL_L(a, b) CHOICE(imull ARG2(a,b), imull ARG2(a,b), _LTOG imul ARG2(b,a)) +#define IMUL_W(a, b) CHOICE(imulw ARG2(a,b), imulw ARG2(a,b), _WTOG imul ARG2(b,a)) +#define IMUL_B(a) CHOICE(imulb a, imulb a, imulb a) +#define IN_L CHOICE(inl (DX), inl ARG2(DX,EAX), _LTOG in DX) +#define IN_W CHOICE(inw (DX), inw ARG2(DX,AX), _WTOG in DX) +#define IN_B CHOICE(inb (DX), inb ARG2(DX,AL), inb DX) +/* Please AS code writer: use the following ONLY, if you refer to ports<256 + * directly, but not in IN1_W(DX), for instance, even if IN1_ looks nicer + */ +#if defined (sun) +#define IN1_L(a) CHOICE(inl (a), inl ARG2(a,EAX), _LTOG in a) +#define IN1_W(a) CHOICE(inw (a), inw ARG2(a,AX), _WTOG in a) +#define IN1_B(a) CHOICE(inb (a), inb ARG2(a,AL), inb a) +#else +#define IN1_L(a) CHOICE(inl a, inl ARG2(a,EAX), _LTOG in a) +#define IN1_W(a) CHOICE(inw a, inw ARG2(a,AX), _WTOG in a) +#define IN1_B(a) CHOICE(inb a, inb ARG2(a,AL), inb a) +#endif +#define INC_L(a) CHOICE(incl a, incl a, _LTOG inc a) +#define INC_W(a) CHOICE(incw a, incw a, _WTOG inc a) +#define INC_B(a) CHOICE(incb a, incb a, incb a) +#define INS_L CHOICE(insl, insl, _LTOG ins) +#define INS_W CHOICE(insw, insw, _WTOG ins) +#define INS_B CHOICE(insb, insb, insb) +#define INT(a) CHOICE(int a, int a, int a) +#define INT3 CHOICE(int CONST(3), int3, int CONST(3)) +#define INTO CHOICE(into, into, into) +#define IRET CHOICE(iret, iret, iret) +#define IRETD CHOICE(iret, iret, iretd) +#define JA(a) CHOICE(ja a, ja a, ja a) +#define JAE(a) CHOICE(jae a, jae a, jae a) +#define JB(a) CHOICE(jb a, jb a, jb a) +#define JBE(a) CHOICE(jbe a, jbe a, jbe a) +#define JC(a) CHOICE(jc a, jc a, jc a) +#define JE(a) CHOICE(je a, je a, je a) +#define JG(a) CHOICE(jg a, jg a, jg a) +#define JGE(a) CHOICE(jge a, jge a, jge a) +#define JL(a) CHOICE(jl a, jl a, jl a) +#define JLE(a) CHOICE(jle a, jle a, jle a) +#define JNA(a) CHOICE(jna a, jna a, jna a) +#define JNAE(a) CHOICE(jnae a, jnae a, jnae a) +#define JNB(a) CHOICE(jnb a, jnb a, jnb a) +#define JNBE(a) CHOICE(jnbe a, jnbe a, jnbe a) +#define JNC(a) CHOICE(jnc a, jnc a, jnc a) +#define JNE(a) CHOICE(jne a, jne a, jne a) +#define JNG(a) CHOICE(jng a, jng a, jng a) +#define JNGE(a) CHOICE(jnge a, jnge a, jnge a) +#define JNL(a) CHOICE(jnl a, jnl a, jnl a) +#define JNLE(a) CHOICE(jnle a, jnle a, jnle a) +#define JNO(a) CHOICE(jno a, jno a, jno a) +#define JNP(a) CHOICE(jnp a, jnp a, jnp a) +#define JNS(a) CHOICE(jns a, jns a, jns a) +#define JNZ(a) CHOICE(jnz a, jnz a, jnz a) +#define JO(a) CHOICE(jo a, jo a, jo a) +#define JP(a) CHOICE(jp a, jp a, jp a) +#define JPE(a) CHOICE(jpe a, jpe a, jpe a) +#define JPO(a) CHOICE(jpo a, jpo a, jpo a) +#define JS(a) CHOICE(js a, js a, js a) +#define JZ(a) CHOICE(jz a, jz a, jz a) +#define JMP(a) CHOICE(jmp a, jmp a, jmp a) +#define JMPF(s,a) CHOICE(ljmp ARG2(s,a), ljmp ARG2(s,a), jmpf s:a) +#define LAHF CHOICE(lahf, lahf, lahf) +#if !defined(_REAL_MODE) && !defined(_V86_MODE) +#define LAR(a, b) CHOICE(lar ARG2(a, b), lar ARG2(a, b), lar ARG2(b, a)) +#endif +#define LEA_L(a, b) CHOICE(leal ARG2(a,b), leal ARG2(a,b), _LTOG lea ARG2(b,a)) +#define LEA_W(a, b) CHOICE(leaw ARG2(a,b), leaw ARG2(a,b), _WTOG lea ARG2(b,a)) +#define LEAVE CHOICE(leave, leave, leave) +#define LGDT(a) CHOICE(lgdt a, lgdt a, lgdt a) +#define LIDT(a) CHOICE(lidt a, lidt a, lidt a) +#define LDS(a, b) CHOICE(ldsl ARG2(a,b), lds ARG2(a,b), lds ARG2(b,a)) +#define LES(a, b) CHOICE(lesl ARG2(a,b), les ARG2(a,b), les ARG2(b,a)) +#define LFS(a, b) CHOICE(lfsl ARG2(a,b), lfs ARG2(a,b), lfs ARG2(b,a)) +#define LGS(a, b) CHOICE(lgsl ARG2(a,b), lgs ARG2(a,b), lgs ARG2(b,a)) +#define LSS(a, b) CHOICE(lssl ARG2(a,b), lss ARG2(a,b), lss ARG2(b,a)) +#define LLDT(a) CHOICE(lldt a, lldt a, lldt a) +#define LMSW(a) CHOICE(lmsw a, lmsw a, lmsw a) +#define LOCK CHOICE(lock, lock, lock) +#define LODS_L CHOICE(lodsl, lodsl, _LTOG lods) +#define LODS_W CHOICE(lodsw, lodsw, _WTOG lods) +#define LODS_B CHOICE(lodsb, lodsb, lodsb) +#define LOOP(a) CHOICE(loop a, loop a, loop a) +#define LOOPE(a) CHOICE(loope a, loope a, loope a) +#define LOOPZ(a) CHOICE(loopz a, loopz a, loopz a) +#define LOOPNE(a) CHOICE(loopne a, loopne a, loopne a) +#define LOOPNZ(a) CHOICE(loopnz a, loopnz a, loopnz a) +#if !defined(_REAL_MODE) && !defined(_V86_MODE) +#define LSL(a, b) CHOICE(lsl ARG2(a,b), lsl ARG2(a,b), lsl ARG2(b,a)) +#endif +#define LTR(a) CHOICE(ltr a, ltr a, ltr a) +#define MOV_SR(a, b) CHOICE(movw ARG2(a,b), mov ARG2(a,b), mov ARG2(b,a)) +#define MOV_L(a, b) CHOICE(movl ARG2(a,b), movl ARG2(a,b), _LTOG mov ARG2(b,a)) +#define MOV_W(a, b) CHOICE(movw ARG2(a,b), movw ARG2(a,b), _WTOG mov ARG2(b,a)) +#define MOV_B(a, b) CHOICE(movb ARG2(a,b), movb ARG2(a,b), movb ARG2(b,a)) +#define MOVS_L CHOICE(movsl, movsl, _LTOG movs) +#define MOVS_W CHOICE(movsw, movsw, _WTOG movs) +#define MOVS_B CHOICE(movsb, movsb, movsb) +#define MOVSX_BL(a, b) CHOICE(movsbl ARG2(a,b), movsbl ARG2(a,b), movsx ARG2(b,a)) +#define MOVSX_BW(a, b) CHOICE(movsbw ARG2(a,b), movsbw ARG2(a,b), movsx ARG2(b,a)) +#define MOVSX_WL(a, b) CHOICE(movswl ARG2(a,b), movswl ARG2(a,b), movsx ARG2(b,a)) +#define MOVZX_BL(a, b) CHOICE(movzbl ARG2(a,b), movzbl ARG2(a,b), movzx ARG2(b,a)) +#define MOVZX_BW(a, b) CHOICE(movzbw ARG2(a,b), movzbw ARG2(a,b), movzx ARG2(b,a)) +#define MOVZX_WL(a, b) CHOICE(movzwl ARG2(a,b), movzwl ARG2(a,b), movzx ARG2(b,a)) +#define MUL_L(a) CHOICE(mull a, mull a, _LTOG mul a) +#define MUL_W(a) CHOICE(mulw a, mulw a, _WTOG mul a) +#define MUL_B(a) CHOICE(mulb a, mulb a, mulb a) +#define NEG_L(a) CHOICE(negl a, negl a, _LTOG neg a) +#define NEG_W(a) CHOICE(negw a, negw a, _WTOG neg a) +#define NEG_B(a) CHOICE(negb a, negb a, negb a) +#define NOP CHOICE(nop, nop, nop) +#define NOT_L(a) CHOICE(notl a, notl a, _LTOG not a) +#define NOT_W(a) CHOICE(notw a, notw a, _WTOG not a) +#define NOT_B(a) CHOICE(notb a, notb a, notb a) +#define OR_L(a,b) CHOICE(orl ARG2(a,b), orl ARG2(a,b), _LTOG or ARG2(b,a)) +#define OR_W(a,b) CHOICE(orw ARG2(a,b), orw ARG2(a,b), _WTOG or ARG2(b,a)) +#define OR_B(a,b) CHOICE(orb ARG2(a,b), orb ARG2(a,b), orb ARG2(b,a)) +#define OUT_L CHOICE(outl (DX), outl ARG2(EAX,DX), _LTOG out DX) +#define OUT_W CHOICE(outw (DX), outw ARG2(AX,DX), _WTOG out DX) +#define OUT_B CHOICE(outb (DX), outb ARG2(AL,DX), outb DX) +/* Please AS code writer: use the following ONLY, if you refer to ports<256 + * directly, but not in OUT1_W(DX), for instance, even if OUT1_ looks nicer + */ +#define OUT1_L(a) CHOICE(outl (a), outl ARG2(EAX,a), _LTOG out a) +#define OUT1_W(a) CHOICE(outw (a), outw ARG2(AX,a), _WTOG out a) +#define OUT1_B(a) CHOICE(outb (a), outb ARG2(AL,a), outb a) +#define OUTS_L CHOICE(outsl, outsl, _LTOG outs) +#define OUTS_W CHOICE(outsw, outsw, _WTOG outs) +#define OUTS_B CHOICE(outsb, outsb, outsb) +#define POP_SR(a) CHOICE(pop a, pop a, pop a) +#define POP_L(a) CHOICE(popl a, popl a, _LTOG pop a) +#define POP_W(a) CHOICE(popw a, popw a, _WTOG pop a) +#define POPA_L CHOICE(popal, popal, _LTOG popa) +#define POPA_W CHOICE(popaw, popaw, _WTOG popa) +#define POPF_L CHOICE(popfl, popfl, _LTOG popf) +#define POPF_W CHOICE(popfw, popfw, _WTOG popf) +#define PUSH_SR(a) CHOICE(push a, push a, push a) +#define PUSH_L(a) CHOICE(pushl a, pushl a, _LTOG push a) +#define PUSH_W(a) CHOICE(pushw a, pushw a, _WTOG push a) +#define PUSH_B(a) CHOICE(push a, pushb a, push a) +#define PUSHA_L CHOICE(pushal, pushal, _LTOG pusha) +#define PUSHA_W CHOICE(pushaw, pushaw, _WTOG pusha) +#define PUSHF_L CHOICE(pushfl, pushfl, _LTOG pushf) +#define PUSHF_W CHOICE(pushfw, pushfw, _WTOG pushf) +#define RCL_L(a, b) CHOICE(rcll ARG2(a,b), rcll ARG2(a,b), _LTOG rcl ARG2(b,a)) +#define RCL_W(a, b) CHOICE(rclw ARG2(a,b), rclw ARG2(a,b), _WTOG rcl ARG2(b,a)) +#define RCL_B(a, b) CHOICE(rclb ARG2(a,b), rclb ARG2(a,b), rclb ARG2(b,a)) +#define RCR_L(a, b) CHOICE(rcrl ARG2(a,b), rcrl ARG2(a,b), _LTOG rcr ARG2(b,a)) +#define RCR_W(a, b) CHOICE(rcrw ARG2(a,b), rcrw ARG2(a,b), _WTOG rcr ARG2(b,a)) +#define RCR_B(a, b) CHOICE(rcrb ARG2(a,b), rcrb ARG2(a,b), rcrb ARG2(b,a)) +#define ROL_L(a, b) CHOICE(roll ARG2(a,b), roll ARG2(a,b), _LTOG rol ARG2(b,a)) +#define ROL_W(a, b) CHOICE(rolw ARG2(a,b), rolw ARG2(a,b), _WTOG rol ARG2(b,a)) +#define ROL_B(a, b) CHOICE(rolb ARG2(a,b), rolb ARG2(a,b), rolb ARG2(b,a)) +#define ROR_L(a, b) CHOICE(rorl ARG2(a,b), rorl ARG2(a,b), _LTOG ror ARG2(b,a)) +#define ROR_W(a, b) CHOICE(rorw ARG2(a,b), rorw ARG2(a,b), _WTOG ror ARG2(b,a)) +#define ROR_B(a, b) CHOICE(rorb ARG2(a,b), rorb ARG2(a,b), rorb ARG2(b,a)) +#define REP CHOICE(rep ;, rep ;, repe) +#define REPE CHOICE(repz ;, repe ;, repe) +#define REPNE CHOICE(repnz ;, repne ;, repne) +#define REPNZ REPNE +#define REPZ REPE +#define RET CHOICE(ret, ret, ret) +#define SAHF CHOICE(sahf, sahf, sahf) +#define SAL_L(a, b) CHOICE(sall ARG2(a,b), sall ARG2(a,b), _LTOG sal ARG2(b,a)) +#define SAL_W(a, b) CHOICE(salw ARG2(a,b), salw ARG2(a,b), _WTOG sal ARG2(b,a)) +#define SAL_B(a, b) CHOICE(salb ARG2(a,b), salb ARG2(a,b), salb ARG2(b,a)) +#define SAR_L(a, b) CHOICE(sarl ARG2(a,b), sarl ARG2(a,b), _LTOG sar ARG2(b,a)) +#define SAR_W(a, b) CHOICE(sarw ARG2(a,b), sarw ARG2(a,b), _WTOG sar ARG2(b,a)) +#define SAR_B(a, b) CHOICE(sarb ARG2(a,b), sarb ARG2(a,b), sarb ARG2(b,a)) +#define SBB_L(a, b) CHOICE(sbbl ARG2(a,b), sbbl ARG2(a,b), _LTOG sbb ARG2(b,a)) +#define SBB_W(a, b) CHOICE(sbbw ARG2(a,b), sbbw ARG2(a,b), _WTOG sbb ARG2(b,a)) +#define SBB_B(a, b) CHOICE(sbbb ARG2(a,b), sbbb ARG2(a,b), sbbb ARG2(b,a)) +#define SCAS_L CHOICE(scasl, scasl, _LTOG scas) +#define SCAS_W CHOICE(scasw, scasw, _WTOG scas) +#define SCAS_B CHOICE(scasb, scasb, scasb) +#define SETA(a) CHOICE(seta a, seta a, seta a) +#define SETAE(a) CHOICE(setae a, setae a, setae a) +#define SETB(a) CHOICE(setb a, setb a, setb a) +#define SETBE(a) CHOICE(setbe a, setbe a, setbe a) +#define SETC(a) CHOICE(setc a, setb a, setb a) +#define SETE(a) CHOICE(sete a, sete a, sete a) +#define SETG(a) CHOICE(setg a, setg a, setg a) +#define SETGE(a) CHOICE(setge a, setge a, setge a) +#define SETL(a) CHOICE(setl a, setl a, setl a) +#define SETLE(a) CHOICE(setle a, setle a, setle a) +#define SETNA(a) CHOICE(setna a, setna a, setna a) +#define SETNAE(a) CHOICE(setnae a, setnae a, setnae a) +#define SETNB(a) CHOICE(setnb a, setnb a, setnb a) +#define SETNBE(a) CHOICE(setnbe a, setnbe a, setnbe a) +#define SETNC(a) CHOICE(setnc a, setnb a, setnb a) +#define SETNE(a) CHOICE(setne a, setne a, setne a) +#define SETNG(a) CHOICE(setng a, setng a, setng a) +#define SETNGE(a) CHOICE(setnge a, setnge a, setnge a) +#define SETNL(a) CHOICE(setnl a, setnl a, setnl a) +#define SETNLE(a) CHOICE(setnle a, setnle a, setnle a) +#define SETNO(a) CHOICE(setno a, setno a, setno a) +#define SETNP(a) CHOICE(setnp a, setnp a, setnp a) +#define SETNS(a) CHOICE(setns a, setns a, setna a) +#define SETNZ(a) CHOICE(setnz a, setnz a, setnz a) +#define SETO(a) CHOICE(seto a, seto a, seto a) +#define SETP(a) CHOICE(setp a, setp a, setp a) +#define SETPE(a) CHOICE(setpe a, setpe a, setpe a) +#define SETPO(a) CHOICE(setpo a, setpo a, setpo a) +#define SETS(a) CHOICE(sets a, sets a, seta a) +#define SETZ(a) CHOICE(setz a, setz a, setz a) +#define SGDT(a) CHOICE(sgdt a, sgdt a, sgdt a) +#define SIDT(a) CHOICE(sidt a, sidt a, sidt a) +#define SHL_L(a, b) CHOICE(shll ARG2(a,b), shll ARG2(a,b), _LTOG shl ARG2(b,a)) +#define SHL_W(a, b) CHOICE(shlw ARG2(a,b), shlw ARG2(a,b), _WTOG shl ARG2(b,a)) +#define SHL_B(a, b) CHOICE(shlb ARG2(a,b), shlb ARG2(a,b), shlb ARG2(b,a)) +#define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a)) +#define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL)) +#define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a)) +#define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL)) +#define SHR_L(a, b) CHOICE(shrl ARG2(a,b), shrl ARG2(a,b), _LTOG shr ARG2(b,a)) +#define SHR_W(a, b) CHOICE(shrw ARG2(a,b), shrw ARG2(a,b), _WTOG shr ARG2(b,a)) +#define SHR_B(a, b) CHOICE(shrb ARG2(a,b), shrb ARG2(a,b), shrb ARG2(b,a)) +#define SHRD_L(a,b,c) CHOICE(shrdl ARG3(a,b,c), shrdl ARG3(a,b,c), _LTOG shrd ARG3(c,b,a)) +#define SHRD2_L(a,b) CHOICE(shrdl ARG2(a,b), shrdl ARG3(CL,a,b), _LTOG shrd ARG3(b,a,CL)) +#define SHRD_W(a,b,c) CHOICE(shrdw ARG3(a,b,c), shrdw ARG3(a,b,c), _WTOG shrd ARG3(c,b,a)) +#define SHRD2_W(a,b) CHOICE(shrdw ARG2(a,b), shrdw ARG3(CL,a,b), _WTOG shrd ARG3(b,a,CL)) +#define SLDT(a) CHOICE(sldt a, sldt a, sldt a) +#define SMSW(a) CHOICE(smsw a, smsw a, smsw a) +#define STC CHOICE(stc, stc, stc) +#define STD CHOICE(std, std, std) +#define STI CHOICE(sti, sti, sti) +#define STOS_L CHOICE(stosl, stosl, _LTOG stos) +#define STOS_W CHOICE(stosw, stosw, _WTOG stos) +#define STOS_B CHOICE(stosb, stosb, stosb) +#define STR(a) CHOICE(str a, str a, str a) +#define SUB_L(a, b) CHOICE(subl ARG2(a,b), subl ARG2(a,b), _LTOG sub ARG2(b,a)) +#define SUB_W(a, b) CHOICE(subw ARG2(a,b), subw ARG2(a,b), _WTOG sub ARG2(b,a)) +#define SUB_B(a, b) CHOICE(subb ARG2(a,b), subb ARG2(a,b), subb ARG2(b,a)) +#define TEST_L(a, b) CHOICE(testl ARG2(a,b), testl ARG2(a,b), _LTOG test ARG2(b,a)) +#define TEST_W(a, b) CHOICE(testw ARG2(a,b), testw ARG2(a,b), _WTOG test ARG2(b,a)) +#define TEST_B(a, b) CHOICE(testb ARG2(a,b), testb ARG2(a,b), testb ARG2(b,a)) +#define VERR(a) CHOICE(verr a, verr a, verr a) +#define VERW(a) CHOICE(verw a, verw a, verw a) +#define WAIT CHOICE(wait, wait, wait) +#define XCHG_L(a, b) CHOICE(xchgl ARG2(a,b), xchgl ARG2(a,b), _LTOG xchg ARG2(b,a)) +#define XCHG_W(a, b) CHOICE(xchgw ARG2(a,b), xchgw ARG2(a,b), _WTOG xchg ARG2(b,a)) +#define XCHG_B(a, b) CHOICE(xchgb ARG2(a,b), xchgb ARG2(a,b), xchgb ARG2(b,a)) +#define XLAT CHOICE(xlat, xlat, xlat) +#define XOR_L(a, b) CHOICE(xorl ARG2(a,b), xorl ARG2(a,b), _LTOG xor ARG2(b,a)) +#define XOR_W(a, b) CHOICE(xorw ARG2(a,b), xorw ARG2(a,b), _WTOG xor ARG2(b,a)) +#define XOR_B(a, b) CHOICE(xorb ARG2(a,b), xorb ARG2(a,b), xorb ARG2(b,a)) + + +/* Floating Point Instructions */ +#define F2XM1 CHOICE(f2xm1, f2xm1, f2xm1) +#define FABS CHOICE(fabs, fabs, fabs) +#define FADD_D(a) CHOICE(faddl a, faddl a, faddd a) +#define FADD_S(a) CHOICE(fadds a, fadds a, fadds a) +#define FADD2(a, b) CHOICE(fadd ARG2(a,b), fadd ARG2(a,b), fadd ARG2(b,a)) +#define FADDP(a, b) CHOICE(faddp ARG2(a,b), faddp ARG2(a,b), faddp ARG2(b,a)) +#define FIADD_L(a) CHOICE(fiaddl a, fiaddl a, fiaddl a) +#define FIADD_W(a) CHOICE(fiadd a, fiadds a, fiadds a) +#define FBLD(a) CHOICE(fbld a, fbld a, fbld a) +#define FBSTP(a) CHOICE(fbstp a, fbstp a, fbstp a) +#define FCHS CHOICE(fchs, fchs, fchs) +#define FCLEX CHOICE(fclex, wait; fnclex, wait; fclex) +#define FNCLEX CHOICE(fnclex, fnclex, fclex) +#define FCOM(a) CHOICE(fcom a, fcom a, fcom a) +#define FCOM_D(a) CHOICE(fcoml a, fcoml a, fcomd a) +#define FCOM_S(a) CHOICE(fcoms a, fcoms a, fcoms a) +#define FCOMP(a) CHOICE(fcomp a, fcomp a, fcomp a) +#define FCOMP_D(a) CHOICE(fcompl a, fcompl a, fcompd a) +#define FCOMP_S(a) CHOICE(fcomps a, fcomps a, fcomps a) +#define FCOMPP CHOICE(fcompp, fcompp, fcompp) +#define FCOS CHOICE(fcos, fcos, fcos) +#define FDECSTP CHOICE(fdecstp, fdecstp, fdecstp) +#define FDIV_D(a) CHOICE(fdivl a, fdivl a, fdivd a) +#define FDIV_S(a) CHOICE(fdivs a, fdivs a, fdivs a) +#define FDIV2(a, b) CHOICE(fdiv ARG2(a,b), fdiv ARG2(a,b), fdiv ARG2(b,a)) +#define FDIVP(a, b) CHOICE(fdivp ARG2(a,b), fdivp ARG2(a,b), fdivp ARG2(b,a)) +#define FIDIV_L(a) CHOICE(fidivl a, fidivl a, fidivl a) +#define FIDIV_W(a) CHOICE(fidiv a, fidivs a, fidivs a) +#define FDIVR_D(a) CHOICE(fdivrl a, fdivrl a, fdivrd a) +#define FDIVR_S(a) CHOICE(fdivrs a, fdivrs a, fdivrs a) +#define FDIVR2(a, b) CHOICE(fdivr ARG2(a,b), fdivr ARG2(a,b), fdivr ARG2(b,a)) +#define FDIVRP(a, b) CHOICE(fdivrp ARG2(a,b), fdivrp ARG2(a,b), fdivrp ARG2(b,a)) +#define FIDIVR_L(a) CHOICE(fidivrl a, fidivrl a, fidivrl a) +#define FIDIVR_W(a) CHOICE(fidivr a, fidivrs a, fidivrs a) +#define FFREE(a) CHOICE(ffree a, ffree a, ffree a) +#define FICOM_L(a) CHOICE(ficoml a, ficoml a, ficoml a) +#define FICOM_W(a) CHOICE(ficom a, ficoms a, ficoms a) +#define FICOMP_L(a) CHOICE(ficompl a, ficompl a, ficompl a) +#define FICOMP_W(a) CHOICE(ficomp a, ficomps a, ficomps a) +#define FILD_Q(a) CHOICE(fildll a, fildq a, fildq a) +#define FILD_L(a) CHOICE(fildl a, fildl a, fildl a) +#define FILD_W(a) CHOICE(fild a, filds a, filds a) +#define FINCSTP CHOICE(fincstp, fincstp, fincstp) +#define FINIT CHOICE(finit, wait; fninit, wait; finit) +#define FNINIT CHOICE(fninit, fninit, finit) +#define FIST_L(a) CHOICE(fistl a, fistl a, fistl a) +#define FIST_W(a) CHOICE(fist a, fists a, fists a) +#define FISTP_Q(a) CHOICE(fistpll a, fistpq a, fistpq a) +#define FISTP_L(a) CHOICE(fistpl a, fistpl a, fistpl a) +#define FISTP_W(a) CHOICE(fistp a, fistps a, fistps a) +#define FLD_X(a) CHOICE(fldt a, fldt a, fldx a) /* 80 bit data type! */ +#define FLD_D(a) CHOICE(fldl a, fldl a, fldd a) +#define FLD_S(a) CHOICE(flds a, flds a, flds a) +#define FLD1 CHOICE(fld1, fld1, fld1) +#define FLDL2T CHOICE(fldl2t, fldl2t, fldl2t) +#define FLDL2E CHOICE(fldl2e, fldl2e, fldl2e) +#define FLDPI CHOICE(fldpi, fldpi, fldpi) +#define FLDLG2 CHOICE(fldlg2, fldlg2, fldlg2) +#define FLDLN2 CHOICE(fldln2, fldln2, fldln2) +#define FLDZ CHOICE(fldz, fldz, fldz) +#define FLDCW(a) CHOICE(fldcw a, fldcw a, fldcw a) +#define FLDENV(a) CHOICE(fldenv a, fldenv a, fldenv a) +#define FMUL_S(a) CHOICE(fmuls a, fmuls a, fmuls a) +#define FMUL_D(a) CHOICE(fmull a, fmull a, fmuld a) +#define FMUL2(a, b) CHOICE(fmul ARG2(a,b), fmul ARG2(a,b), fmul ARG2(b,a)) +#define FMULP(a, b) CHOICE(fmulp ARG2(a,b), fmulp ARG2(a,b), fmulp ARG2(b,a)) +#define FIMUL_L(a) CHOICE(fimull a, fimull a, fimull a) +#define FIMUL_W(a) CHOICE(fimul a, fimuls a, fimuls a) +#define FNOP CHOICE(fnop, fnop, fnop) +#define FPATAN CHOICE(fpatan, fpatan, fpatan) +#define FPREM CHOICE(fprem, fprem, fprem) +#define FPREM1 CHOICE(fprem1, fprem1, fprem1) +#define FPTAN CHOICE(fptan, fptan, fptan) +#define FRNDINT CHOICE(frndint, frndint, frndint) +#define FRSTOR(a) CHOICE(frstor a, frstor a, frstor a) +#define FSAVE(a) CHOICE(fsave a, wait; fnsave a, wait; fsave a) +#define FNSAVE(a) CHOICE(fnsave a, fnsave a, fsave a) +#define FSCALE CHOICE(fscale, fscale, fscale) +#define FSIN CHOICE(fsin, fsin, fsin) +#define FSINCOS CHOICE(fsincos, fsincos, fsincos) +#define FSQRT CHOICE(fsqrt, fsqrt, fsqrt) +#define FST_D(a) CHOICE(fstl a, fstl a, fstd a) +#define FST_S(a) CHOICE(fsts a, fsts a, fsts a) +#define FSTP_X(a) CHOICE(fstpt a, fstpt a, fstpx a) +#define FSTP_D(a) CHOICE(fstpl a, fstpl a, fstpd a) +#define FSTP_S(a) CHOICE(fstps a, fstps a, fstps a) +#define FSTCW(a) CHOICE(fstcw a, wait; fnstcw a, wait; fstcw a) +#define FNSTCW(a) CHOICE(fnstcw a, fnstcw a, fstcw a) +#define FSTENV(a) CHOICE(fstenv a, wait; fnstenv a, fstenv a) +#define FNSTENV(a) CHOICE(fnstenv a, fnstenv a, fstenv a) +#define FSTSW(a) CHOICE(fstsw a, wait; fnstsw a, wait; fstsw a) +#define FNSTSW(a) CHOICE(fnstsw a, fnstsw a, fstsw a) +#define FSUB_S(a) CHOICE(fsubs a, fsubs a, fsubs a) +#define FSUB_D(a) CHOICE(fsubl a, fsubl a, fsubd a) +#define FSUB2(a, b) CHOICE(fsub ARG2(a,b), fsub ARG2(a,b), fsub ARG2(b,a)) +#define FSUBP(a, b) CHOICE(fsubp ARG2(a,b), fsubp ARG2(a,b), fsubp ARG2(b,a)) +#define FISUB_L(a) CHOICE(fisubl a, fisubl a, fisubl a) +#define FISUB_W(a) CHOICE(fisub a, fisubs a, fisubs a) +#define FSUBR_S(a) CHOICE(fsubrs a, fsubrs a, fsubrs a) +#define FSUBR_D(a) CHOICE(fsubrl a, fsubrl a, fsubrd a) +#define FSUBR2(a, b) CHOICE(fsubr ARG2(a,b), fsubr ARG2(a,b), fsubr ARG2(b,a)) +#define FSUBRP(a, b) CHOICE(fsubrp ARG2(a,b), fsubrp ARG2(a,b), fsubrp ARG2(b,a)) +#define FISUBR_L(a) CHOICE(fisubrl a, fisubrl a, fisubrl a) +#define FISUBR_W(a) CHOICE(fisubr a, fisubrs a, fisubrs a) +#define FTST CHOICE(ftst, ftst, ftst) +#define FUCOM(a) CHOICE(fucom a, fucom a, fucom a) +#define FUCOMP(a) CHOICE(fucomp a, fucomp a, fucomp a) +#define FUCOMPP CHOICE(fucompp, fucompp, fucompp) +#define FWAIT CHOICE(wait, wait, wait) +#define FXAM CHOICE(fxam, fxam, fxam) +#define FXCH(a) CHOICE(fxch a, fxch a, fxch a) +#define FXTRACT CHOICE(fxtract, fxtract, fxtract) +#define FYL2X CHOICE(fyl2x, fyl2x, fyl2x) +#define FYL2XP1 CHOICE(fyl2xp1, fyl2xp1, fyl2xp1) + +#endif /* __ASSYNTAX_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/atKeynames.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/atKeynames.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/atKeynames.h (revision 51223) @@ -0,0 +1,298 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/atKeynames.h,v 3.21 2003/10/09 11:43:59 pascal Exp $ */ +/* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Thomas Roell makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: atKeynames.h /main/11 1996/03/09 11:17:41 kaleb $ */ + +#ifndef _ATKEYNAMES_H +#define _ATKEYNAMES_H + +#define XK_TECHNICAL +#define XK_KATAKANA +#include +#include + +#define GLYPHS_PER_KEY 4 +#define NUM_KEYCODES 248 +#define MIN_KEYCODE 8 +#define MAX_KEYCODE (NUM_KEYCODES + MIN_KEYCODE - 1) + +#define AltMask Mod1Mask +#define NumLockMask Mod2Mask +#define AltLangMask Mod3Mask +#define KanaMask Mod4Mask +#define ScrollLockMask Mod5Mask + +#define KeyPressed(k) (keyc->down[k >> 3] & (1 << (k & 7))) +#define ModifierDown(k) ((keyc->state & (k)) == (k)) + +/* + * NOTE: The AT/MF keyboards can generate (via the 8042) two (MF: three) + * sets of scancodes. Set3 can only be generated by a MF keyboard. + * Set2 sends a makecode for keypress, and the same code prefixed by a + * F0 for keyrelease. This is a little bit ugly to handle. Thus we use + * here for X386 the PC/XT compatible Set1. This set uses 8bit scancodes. + * Bit 7 ist set if the key is released. The code E0 switches to a + * different meaning to add the new MF cursorkeys, while not breaking old + * applications. E1 is another special prefix. Since I assume that there + * will be further versions of PC/XT scancode compatible keyboards, we + * may be in trouble one day. + * + * IDEA: 1) Use Set2 on AT84 keyboards and translate it to MF Set3. + * 2) Use the keyboards native set and translate it to common keysyms. + */ + +/* + * definition of the AT84/MF101/MF102 Keyboard: + * ============================================================ + * Defined Key Cap Glyphs Pressed value + * Key Name Main Also (hex) (dec) + * ---------------- ---------- ------- ------ ------ + */ + +#define KEY_Escape /* Escape 0x01 */ 1 +#define KEY_1 /* 1 ! 0x02 */ 2 +#define KEY_2 /* 2 @ 0x03 */ 3 +#define KEY_3 /* 3 # 0x04 */ 4 +#define KEY_4 /* 4 $ 0x05 */ 5 +#define KEY_5 /* 5 % 0x06 */ 6 +#define KEY_6 /* 6 ^ 0x07 */ 7 +#define KEY_7 /* 7 & 0x08 */ 8 +#define KEY_8 /* 8 * 0x09 */ 9 +#define KEY_9 /* 9 ( 0x0a */ 10 +#define KEY_0 /* 0 ) 0x0b */ 11 +#define KEY_Minus /* - (Minus) _ (Under) 0x0c */ 12 +#define KEY_Equal /* = (Equal) + 0x0d */ 13 +#define KEY_BackSpace /* Back Space 0x0e */ 14 +#define KEY_Tab /* Tab 0x0f */ 15 +#define KEY_Q /* Q 0x10 */ 16 +#define KEY_W /* W 0x11 */ 17 +#define KEY_E /* E 0x12 */ 18 +#define KEY_R /* R 0x13 */ 19 +#define KEY_T /* T 0x14 */ 20 +#define KEY_Y /* Y 0x15 */ 21 +#define KEY_U /* U 0x16 */ 22 +#define KEY_I /* I 0x17 */ 23 +#define KEY_O /* O 0x18 */ 24 +#define KEY_P /* P 0x19 */ 25 +#define KEY_LBrace /* [ { 0x1a */ 26 +#define KEY_RBrace /* ] } 0x1b */ 27 +#define KEY_Enter /* Enter 0x1c */ 28 +#define KEY_LCtrl /* Ctrl(left) 0x1d */ 29 +#define KEY_A /* A 0x1e */ 30 +#define KEY_S /* S 0x1f */ 31 +#define KEY_D /* D 0x20 */ 32 +#define KEY_F /* F 0x21 */ 33 +#define KEY_G /* G 0x22 */ 34 +#define KEY_H /* H 0x23 */ 35 +#define KEY_J /* J 0x24 */ 36 +#define KEY_K /* K 0x25 */ 37 +#define KEY_L /* L 0x26 */ 38 +#define KEY_SemiColon /* ;(SemiColon) :(Colon) 0x27 */ 39 +#define KEY_Quote /* ' (Apostr) " (Quote) 0x28 */ 40 +#define KEY_Tilde /* ` (Accent) ~ (Tilde) 0x29 */ 41 +#define KEY_ShiftL /* Shift(left) 0x2a */ 42 +#define KEY_BSlash /* \(BckSlash) |(VertBar)0x2b */ 43 +#define KEY_Z /* Z 0x2c */ 44 +#define KEY_X /* X 0x2d */ 45 +#define KEY_C /* C 0x2e */ 46 +#define KEY_V /* V 0x2f */ 47 +#define KEY_B /* B 0x30 */ 48 +#define KEY_N /* N 0x31 */ 49 +#define KEY_M /* M 0x32 */ 50 +#define KEY_Comma /* , (Comma) < (Less) 0x33 */ 51 +#define KEY_Period /* . (Period) >(Greater)0x34 */ 52 +#define KEY_Slash /* / (Slash) ? 0x35 */ 53 +#define KEY_ShiftR /* Shift(right) 0x36 */ 54 +#define KEY_KP_Multiply /* * 0x37 */ 55 +#define KEY_Alt /* Alt(left) 0x38 */ 56 +#define KEY_Space /* (SpaceBar) 0x39 */ 57 +#define KEY_CapsLock /* CapsLock 0x3a */ 58 +#define KEY_F1 /* F1 0x3b */ 59 +#define KEY_F2 /* F2 0x3c */ 60 +#define KEY_F3 /* F3 0x3d */ 61 +#define KEY_F4 /* F4 0x3e */ 62 +#define KEY_F5 /* F5 0x3f */ 63 +#define KEY_F6 /* F6 0x40 */ 64 +#define KEY_F7 /* F7 0x41 */ 65 +#define KEY_F8 /* F8 0x42 */ 66 +#define KEY_F9 /* F9 0x43 */ 67 +#define KEY_F10 /* F10 0x44 */ 68 +#define KEY_NumLock /* NumLock 0x45 */ 69 +#define KEY_ScrollLock /* ScrollLock 0x46 */ 70 +#define KEY_KP_7 /* 7 Home 0x47 */ 71 +#define KEY_KP_8 /* 8 Up 0x48 */ 72 +#define KEY_KP_9 /* 9 PgUp 0x49 */ 73 +#define KEY_KP_Minus /* - (Minus) 0x4a */ 74 +#define KEY_KP_4 /* 4 Left 0x4b */ 75 +#define KEY_KP_5 /* 5 0x4c */ 76 +#define KEY_KP_6 /* 6 Right 0x4d */ 77 +#define KEY_KP_Plus /* + (Plus) 0x4e */ 78 +#define KEY_KP_1 /* 1 End 0x4f */ 79 +#define KEY_KP_2 /* 2 Down 0x50 */ 80 +#define KEY_KP_3 /* 3 PgDown 0x51 */ 81 +#define KEY_KP_0 /* 0 Insert 0x52 */ 82 +#define KEY_KP_Decimal /* . (Decimal) Delete 0x53 */ 83 +#define KEY_SysReqest /* SysReqest 0x54 */ 84 + /* NOTUSED 0x55 */ +#define KEY_Less /* < (Less) >(Greater) 0x56 */ 86 +#define KEY_F11 /* F11 0x57 */ 87 +#define KEY_F12 /* F12 0x58 */ 88 + +#define KEY_Prefix0 /* special 0x60 */ 96 +#define KEY_Prefix1 /* specail 0x61 */ 97 + +/* + * The 'scancodes' below are generated by the server, because the MF101/102 + * keyboard sends them as sequence of other scancodes + */ +#define KEY_Home /* Home 0x59 */ 89 +#define KEY_Up /* Up 0x5a */ 90 +#define KEY_PgUp /* PgUp 0x5b */ 91 +#define KEY_Left /* Left 0x5c */ 92 +#define KEY_Begin /* Begin 0x5d */ 93 +#define KEY_Right /* Right 0x5e */ 94 +#define KEY_End /* End 0x5f */ 95 +#define KEY_Down /* Down 0x60 */ 96 +#define KEY_PgDown /* PgDown 0x61 */ 97 +#define KEY_Insert /* Insert 0x62 */ 98 +#define KEY_Delete /* Delete 0x63 */ 99 +#define KEY_KP_Enter /* Enter 0x64 */ 100 +#define KEY_RCtrl /* Ctrl(right) 0x65 */ 101 +#define KEY_Pause /* Pause 0x66 */ 102 +#define KEY_Print /* Print 0x67 */ 103 +#define KEY_KP_Divide /* Divide 0x68 */ 104 +#define KEY_AltLang /* AtlLang(right) 0x69 */ 105 +#define KEY_Break /* Break 0x6a */ 106 +#define KEY_LMeta /* Left Meta 0x6b */ 107 +#define KEY_RMeta /* Right Meta 0x6c */ 108 +#define KEY_Menu /* Menu 0x6d */ 109 +#define KEY_F13 /* F13 0x6e */ 110 +#define KEY_F14 /* F14 0x6f */ 111 +#define KEY_F15 /* F15 0x70 */ 112 +#define KEY_HKTG /* Hirugana/Katakana tog 0x70 */ 112 +#define KEY_F16 /* F16 0x71 */ 113 +#define KEY_F17 /* F17 0x72 */ 114 +#define KEY_KP_DEC /* KP_DEC 0x73 */ 115 +#define KEY_BSlash2 /* \ _ 0x73 */ 115 +#define KEY_KP_Equal /* Equal (Keypad) 0x76 */ 118 +#define KEY_XFER /* Kanji Transfer 0x79 */ 121 +#define KEY_NFER /* No Kanji Transfer 0x7b */ 123 +#define KEY_Yen /* Yen 0x7d */ 125 + +#define KEY_Power /* Power Key 0x84 */ 132 +#define KEY_Mute /* Audio Mute 0x85 */ 133 +#define KEY_AudioLower /* Audio Lower 0x86 */ 134 +#define KEY_AudioRaise /* Audio Raise 0x87 */ 135 +#define KEY_Help /* Help 0x88 */ 136 +#define KEY_L1 /* Stop 0x89 */ 137 +#define KEY_L2 /* Again 0x8a */ 138 +#define KEY_L3 /* Props 0x8b */ 139 +#define KEY_L4 /* Undo 0x8c */ 140 +#define KEY_L5 /* Front 0x8d */ 141 +#define KEY_L6 /* Copy 0x8e */ 142 +#define KEY_L7 /* Open 0x8f */ 143 +#define KEY_L8 /* Paste 0x90 */ 144 +#define KEY_L9 /* Find 0x91 */ 145 +#define KEY_L10 /* Cut 0x92 */ 146 + +/* + * Fake 'scancodes' in the following ranges are generated for 2-byte + * codes not handled elsewhere. These correspond to most extended keys + * on so-called "Internet" keyboards: + * + * 0x79-0x93 + * 0x96-0xa1 + * 0xa3-0xac + * 0xb1-0xb4 + * 0xba-0xbd + * 0xc2 + * 0xcc-0xd2 + * 0xd6-0xf7 + */ + +/* + * Remapped 'scancodes' are generated for single-byte codes in the range + * 0x59-0x5f,0x62-0x76. These are used for some extra keys on some keyboards. + */ + +#define KEY_0x59 0x95 +#define KEY_0x5A 0xA2 +#define KEY_0x5B 0xAD +#define KEY_0x5C KEY_KP_EQUAL +#define KEY_0x5D 0xAE +#define KEY_0x5E 0xAF +#define KEY_0x5F 0xB0 +#define KEY_0x62 0xB5 +#define KEY_0x63 0xB6 +#define KEY_0x64 0xB7 +#define KEY_0x65 0xB8 +#define KEY_0x66 0xB9 +#define KEY_0x67 0xBE +#define KEY_0x68 0xBF +#define KEY_0x69 0xC0 +#define KEY_0x6A 0xC1 +#define KEY_0x6B 0xC3 +#define KEY_0x6C 0xC4 +#define KEY_0x6D 0xC5 +#define KEY_0x6E 0xC6 +#define KEY_0x6F 0xC7 +#define KEY_0x70 0xC8 +#define KEY_0x71 0xC9 +#define KEY_0x72 0xCA +#define KEY_0x73 0xCB +#define KEY_0x74 0xD3 +#define KEY_0x75 0xD4 +#define KEY_0x76 0xD5 + +/* These are for "notused" and "unknown" entries in translation maps. */ +#define KEY_NOTUSED 0 +#define KEY_UNKNOWN 255 + +#endif /* _ATKEYNAMES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/attributes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/attributes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/attributes.h (revision 51223) @@ -0,0 +1,131 @@ +/* $Xorg: attributes.h,v 1.4 2001/03/14 18:42:44 pookie Exp $ */ +/* +(c) Copyright 1996 Hewlett-Packard Company +(c) Copyright 1996 International Business Machines Corp. +(c) Copyright 1996 Sun Microsystems, Inc. +(c) Copyright 1996 Novell, Inc. +(c) Copyright 1996 Digital Equipment Corp. +(c) Copyright 1996 Fujitsu Limited +(c) Copyright 1996 Hitachi, Ltd. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _Xp_attributes_h +#define _Xp_attributes_h 1 + +#include "scrnintstr.h" +#include "AttrValid.h" + +#define BFuncArgs int ndx, ScreenPtr pScreen, int argc, char **argv +typedef Bool (*pBFunc)(BFuncArgs); + +#define VFuncArgs char *name, XpValidatePoolsRec *pValRec, float *width, float *height, int *res +typedef void (*pVFunc)(VFuncArgs); + +/* + * attributes.c + */ +void XpInitAttributes(XpContextPtr pContext); +void XpBuildAttributeStore(char *printerName, + char *qualifierName); +void XpAddPrinterAttribute(char *printerName, + char *printerQualifier, + char *attributeName, + char *attributeValue); +void XpDestroyAttributes(XpContextPtr pContext); +char *XpGetConfigDir(Bool useLocale); +char *XpGetOneAttribute(XpContextPtr pContext, + XPAttributes class, + char *attributeName); +void XpPutOneAttribute(XpContextPtr pContext, + XPAttributes class, + const char* attributeName, + const char* value); +int XpRehashAttributes(void); +char *XpGetAttributes(XpContextPtr pContext, + XPAttributes class); +int XpAugmentAttributes(XpContextPtr pContext, + XPAttributes class, + char *attributes); +int XpSetAttributes(XpContextPtr pContext, + XPAttributes class, + char *attributes); +const char *XpGetPrinterAttribute(const char *printerName, + const char *attribute); +void XpGetTrayMediumFromContext(XpContextPtr pCon, + char **medium, + char **tray); +int XpSubmitJob(char *fileName, XpContextPtr pContext); + +/* + * mediaSizes.c + */ +int XpGetResolution(XpContextPtr pContext); +XpOid XpGetContentOrientation(XpContextPtr pContext); +XpOid XpGetAvailableCompression(XpContextPtr pContext); +XpOid XpGetPlex(XpContextPtr pContext); +XpOid XpGetPageSize(XpContextPtr pContext, + XpOid* pTray, + const XpOidMediumSS* msss); +void XpGetMediumMillimeters(XpOid page_size, + float *width, + float *height); +void XpGetMediumDimensions(XpContextPtr pContext, + unsigned short *width, + unsigned short *height); +void XpGetReproductionArea(XpContextPtr pContext, + xRectangle *pRect); +void XpGetMaxWidthHeightRes(const char *printer_name, + const XpValidatePoolsRec* vpr, + float *width, + float *height, + int* resolution); + +/* Util.c */ +char *ReplaceAnyString(char *string, + char *target, + char *replacement); +char *ReplaceFileString(char *string, + char *inFileName, + char *outFileName); +int TransferBytes(FILE *pSrcFile, + FILE *pDstFile, + int numBytes); +Bool CopyContentsAndDelete(FILE **ppSrcFile, + char **pSrcFileName, + FILE *pDstFile); +int XpSendDocumentData(ClientPtr client, + FILE *fp, + int fileLen, + int maxBufSize); +int XpFinishDocData(ClientPtr client); +Bool XpOpenTmpFile(char *mode, + char **fname, + FILE **stream); + +#endif /* _Xp_attributes_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bsd_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bsd_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bsd_kbd.h (revision 51223) @@ -0,0 +1,5 @@ +/* $XFree86$ */ + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstore.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstore.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstore.h (revision 51223) @@ -0,0 +1,23 @@ +/* $XFree86: xc/programs/Xserver/include/bstore.h,v 1.1 1998/04/05 16:44:25 robin Exp $*/ +/* + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies. The University of + * California makes no representations about the suitability of this software + * for any purpose. It is provided "as is" without express or implied + * warranty. + */ + +/* + * Moved here from mi to allow wrapping of lower level backing store functions. + * -- 1997.10.27 Marc Aurele La France (tsi@xfree86.org) + */ + +#ifndef _BSTORE_H_ +#define _BSTORE_H_ + +#include "bstorestr.h" + +#endif /* _BSTORE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstorestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstorestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bstorestr.h (revision 51223) @@ -0,0 +1,58 @@ +/* $XFree86: xc/programs/Xserver/include/bstorestr.h,v 1.2 2001/01/06 20:58:12 tsi Exp $*/ +/* + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, provided + * that the above copyright notice appear in all copies. The University of + * California makes no representations about the suitability of this software + * for any purpose. It is provided "as is" without express or implied + * warranty. + */ + +/* + * Moved here from mi to allow wrapping of lower level backing store functions. + * -- 1997.10.27 Marc Aurele La France (tsi@xfree86.org) + */ + +#ifndef _BSTORESTR_H_ +#define _BSTORESTR_H_ + +#include "gc.h" +#include "pixmap.h" +#include "region.h" +#include "window.h" + +typedef void (* BackingStoreSaveAreasProcPtr)( + PixmapPtr /*pBackingPixmap*/, + RegionPtr /*pObscured*/, + int /*x*/, + int /*y*/, + WindowPtr /*pWin*/); + +typedef void (* BackingStoreRestoreAreasProcPtr)( + PixmapPtr /*pBackingPixmap*/, + RegionPtr /*pExposed*/, + int /*x*/, + int /*y*/, + WindowPtr /*pWin*/); + +typedef void (* BackingStoreSetClipmaskRgnProcPtr)( + GCPtr /*pBackingGC*/, + RegionPtr /*pbackingCompositeClip*/); + +typedef PixmapPtr (* BackingStoreGetImagePixmapProcPtr)(void); + +typedef PixmapPtr (* BackingStoreGetSpansPixmapProcPtr)(void); + +typedef struct _BSFuncs { + + BackingStoreSaveAreasProcPtr SaveAreas; + BackingStoreRestoreAreasProcPtr RestoreAreas; + BackingStoreSetClipmaskRgnProcPtr SetClipmaskRgn; + BackingStoreGetImagePixmapProcPtr GetImagePixmap; + BackingStoreGetSpansPixmapProcPtr GetSpansPixmap; + +} BSFuncRec, *BSFuncPtr; + +#endif /* _BSTORESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bt829.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bt829.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/bt829.h (revision 51223) @@ -0,0 +1,115 @@ +#ifndef __BT829_H__ +#define __BT829_H__ + +#include "xf86i2c.h" + +typedef struct { + int tunertype; /* Must be set before init */ + /* Private variables */ + I2CDevRec d; + + CARD8 brightness; + CARD8 ccmode; + CARD8 code; + CARD16 contrast; + CARD8 format; + int height; + CARD8 hue; + CARD8 len; + CARD8 mux; + CARD8 out_en; + CARD8 p_io; + CARD16 sat_u; + CARD16 sat_v; + CARD8 vbien; + CARD8 vbifmt; + int width; + + CARD16 hdelay; + CARD16 hscale; + CARD16 vactive; + CARD16 vdelay; + CARD16 vscale; + + CARD16 htotal; + CARD8 id; + CARD8 svideo_mux; +} BT829Rec, *BT829Ptr; + +BT829Ptr bt829_Detect(I2CBusPtr b, I2CSlaveAddr addr); + +/* ATI card specific initialization */ +#define BT829_ATI_ADDR_1 0x8A +#define BT829_ATI_ADDR_2 0x88 +int bt829_ATIInit(BT829Ptr bt); + +#define BT829_NTSC 1 /* NTSC-M */ +#define BT829_NTSC_JAPAN 2 /* NTSC-Japan */ +#define BT829_PAL 3 /* PAL-B,D,G,H,I */ +#define BT829_PAL_M 4 /* PAL-M */ +#define BT829_PAL_N 5 /* PAL-N */ +#define BT829_SECAM 6 /* SECAM */ +#define BT829_PAL_N_COMB 7 /* PAL-N combination */ +int bt829_SetFormat(BT829Ptr bt, CARD8 format); + +#define BT829_MUX2 1 /* ATI -> composite video */ +#define BT829_MUX0 2 /* ATI -> tv tuner */ +#define BT829_MUX1 3 /* ATI -> s-video */ +int bt829_SetMux(BT829Ptr bt, CARD8 mux); + +int bt829_SetCaptSize(BT829Ptr bt, int width, int height); + +void bt829_SetBrightness(BT829Ptr bt, int brightness); +void bt829_SetContrast(BT829Ptr bt, int contrast); +void bt829_SetSaturation(BT829Ptr bt, int saturation); +void bt829_SetTint(BT829Ptr bt, int hue); /* Hue */ + +void bt829_SetOUT_EN(BT829Ptr bt, BOOL out_en); /* VPOLE register */ +void bt829_SetP_IO(BT829Ptr bt, CARD8 p_io); /* P_IO register */ + +int bt829_SetCC(BT829Ptr bt); + +#define BT829SymbolsList \ + "bt829_Detect", \ + "bt829_ATIInit", \ + "bt829_SetFormat", \ + "bt829_SetMux", \ + "bt829_SetBrightness", \ + "bt829_SetContrast", \ + "bt829_SetSaturation", \ + "bt829_SetTint", \ + "bt829_SetCaptSize", \ + "bt829_SetOUT_EN", \ + "bt829_SetP_IO" + +#ifdef XFree86LOADER + +#define xf86_bt829_Detect ((BT829Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("bt829_Detect")) +#define xf86_bt829_ATIInit ((int (*)(BT829Ptr))LoaderSymbol("bt829_ATIInit")) +#define xf86_bt829_SetFormat ((int (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetFormat")) +#define xf86_bt829_SetMux ((int (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetMux")) +#define xf86_bt829_SetCaptSize ((int (*)(BT829Ptr, int, int))LoaderSymbol("bt829_SetCaptSize")) +#define xf86_bt829_SetBrightness ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetBrightness")) +#define xf86_bt829_SetContrast ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetContrast")) +#define xf86_bt829_SetSaturation ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetSaturation")) +#define xf86_bt829_SetTint ((void (*)(BT829Ptr, int))LoaderSymbol("bt829_SetTint")) +#define xf86_bt829_SetOUT_EN ((void (*)(BT829Ptr, Bool))LoaderSymbol("bt829_SetOUT_EN")) +#define xf86_bt829_SetP_IO ((void (*)(BT829Ptr, CARD8))LoaderSymbol("bt829_SetP_IO")) + +#else + +#define xf86_bt829_Detect bt829_Detect +#define xf86_bt829_ATIInit bt829_ATIInit +#define xf86_bt829_SetFormat bt829_SetFormat +#define xf86_bt829_SetMux bt829_SetMux +#define xf86_bt829_SetCaptSize bt829_SetCaptSize +#define xf86_bt829_SetBrightness bt829_SetBrightness +#define xf86_bt829_SetContrast bt829_SetContrast +#define xf86_bt829_SetSaturation bt829_SetSaturation +#define xf86_bt829_SetTint bt829_SetTint +#define xf86_bt829_SetOUT_EN bt829_SetOUT_EN +#define xf86_bt829_SetP_IO bt829_SetP_IO + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/card-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/card-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/card-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +#include "config.h" + +#ifndef _xf86cfg_card_h +#define _xf86cfg_card_h + +/* + * Prototypes + */ +XtPointer CardConfig(XtPointer); +void CardModel(XF86SetupInfo*); +void CardFilterAction(Widget, XEvent*, String*, Cardinal*); + +#endif /* _xf86cfg_card_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cards.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cards.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cards.h (revision 51223) @@ -0,0 +1,38 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.h,v 3.4 1999/03/28 15:33:07 dawes Exp $ */ + + + + + +/* $XConsortium: cards.h /main/3 1996/02/21 18:12:53 kaleb $ */ + +#ifndef CARD_DATABASE_FILE +#define CARD_DATABASE_FILE "Cards" +#endif + +#define MAX_CARDS 1000 + +typedef struct { + char *name; /* Name of the card. */ + char *chipset; /* Chipset (decriptive). */ + char *server; /* Server identifier. */ + char *driver; /* Driver identifier. */ + char *ramdac; /* Ramdac identifier. */ + char *clockchip; /* Clockchip identifier. */ + char *dacspeed; /* DAC speed rating. */ + int flags; + char *lines; /* Additional Device section lines. */ +} Card; + +/* Flags: */ +#define NOCLOCKPROBE 0x1 /* Never probe clocks of the card. */ +#define UNSUPPORTED 0x2 /* Card is not supported (only VGA). */ + +extern int lastcard; + +extern Card card[MAX_CARDS]; + +extern int lookupcard ( char *name ); +extern int parse_database ( void ); +extern void sort_database ( void ); +extern void keypress ( void ); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb.h (revision 51223) @@ -0,0 +1,1321 @@ +/* $Xorg: cfb.h,v 1.3 2000/08/17 19:48:12 cpqbld Exp $ */ +/************************************************************ +Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright no- +tice appear in all copies and that both that copyright no- +tice and this permission notice appear in supporting docu- +mentation, and that the names of Sun or The Open Group +not be used in advertising or publicity pertaining to +distribution of the software without specific prior +written permission. Sun and The Open Group make no +representations about the suitability of this software for +any purpose. It is provided "as is" without any express or +implied warranty. + +SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- +NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI- +ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/cfb/cfb.h,v 3.29tsi Exp $ */ + +#if !defined(__CFB_H__) || defined(CFB_PROTOTYPES_ONLY) + +#include +#include "globals.h" +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "servermd.h" +#include "windowstr.h" +#include "mfb.h" +#undef PixelType + +#include "cfbmap.h" + +#ifndef CfbBits +#define CfbBits CARD32 +#endif + +#ifndef CFB_PROTOTYPES_ONLY +#define __CFB_H__ +/* + private filed of pixmap + pixmap.devPrivate = (unsigned int *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes +*/ + +extern int cfbGCPrivateIndex; +extern int cfbWindowPrivateIndex; + +/* private field of GC */ +typedef struct { + unsigned char rop; /* special case rop values */ + /* next two values unused in cfb, included for compatibility with mfb */ + unsigned char ropOpStip; /* rop for opaque stipple */ + /* this value is ropFillArea in mfb, usurped for cfb */ + unsigned char oneRect; /* drawable has one clip rect */ + CfbBits xor, and; /* reduced rop values */ + } cfbPrivGC; + +typedef cfbPrivGC *cfbPrivGCPtr; + +#define cfbGetGCPrivate(pGC) ((cfbPrivGCPtr)\ + (pGC)->devPrivates[cfbGCPrivateIndex].ptr) + +#define cfbGetCompositeClip(pGC) ((pGC)->pCompositeClip) + +/* way to carry RROP info around */ +typedef struct { + unsigned char rop; + CfbBits xor, and; +} cfbRRopRec, *cfbRRopPtr; + +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; + } cfbPrivWin; + +#define cfbGetWindowPrivate(_pWin) ((cfbPrivWin *)\ + (_pWin)->devPrivates[cfbWindowPrivateIndex].ptr) + + +/* cfb8bit.c */ + +extern int cfbSetStipple( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*planemask*/ +); + +extern int cfbSetOpaqueStipple( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*bg*/, + CfbBits /*planemask*/ +); + +extern int cfbComputeClipMasks32( + BoxPtr /*pBox*/, + int /*numRects*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + CARD32 * /*clips*/ +); +#endif /* !CFB_PROTOTYPES_ONLY */ +/* cfb8cppl.c */ + +extern void cfbCopyImagePlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbCopyPlane8to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane16to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane24to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); + +extern void cfbCopyPlane32to1( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ +); +#endif + +/* cfb8lineCO.c */ + +extern int cfb8LineSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8LineSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void cfb8ClippedLineCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8lineCP.c */ + +extern int cfb8LineSS1RectPreviousCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); +/* cfb8lineG.c */ + +extern int cfb8LineSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8ClippedLineGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8lineX.c */ + +extern int cfb8LineSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/, + DDXPointPtr /*pptInitOrig*/, + int * /*x1p*/, + int * /*y1p*/, + int * /*x2p*/, + int * /*y2p*/ +); + +extern void cfb8ClippedLineXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x1*/, + int /*y1*/, + int /*x2*/, + int /*y2*/, + BoxPtr /*boxp*/, + Bool /*shorten*/ +); +/* cfb8segC.c */ + +extern int cfb8SegmentSS1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfb8segCS.c */ + +extern int cfb8SegmentSS1RectShiftCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); + +extern void cfb8SegmentSS1Rect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfb8segG.c */ + +extern int cfb8SegmentSS1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfbsegX.c */ + +extern int cfb8SegmentSS1RectXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegInit*/ +); +/* cfballpriv.c */ + +extern Bool cfbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*window_index*/, + int * /*gc_index*/ +); +/* cfbbitblt.c */ + +extern RegionPtr cfbBitBlt( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (* /*doBitBlt*/)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ + ), + unsigned long /*bitPlane*/ +); + +#define cfbCopyPlaneExpand cfbBitBlt + +extern RegionPtr cfbCopyPlaneReduce( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + void (* /*doCopyPlane*/)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/, + unsigned long /*bitPlane*/ /* We must know which plane to reduce! */ + ), + unsigned long /*bitPlane*/ +); + +extern void cfbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); + +extern RegionPtr cfbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbCopyPlane1to8( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + int /*rop*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +#endif + +extern RegionPtr cfbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/ +); +/* cfbbltC.c */ + +extern void cfbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltG.c */ + +extern void cfbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltO.c */ + +extern void cfbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbltX.c */ + +extern void cfbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/, + unsigned long /*planemask*/ +); +/* cfbbres.c */ + +extern void cfbBresS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* cfbbresd.c */ + +extern void cfbBresD( + cfbRRopPtr /*rrops*/, + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* cfbbstore.c */ + +extern void cfbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void cfbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* cfbcmap.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern int cfbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void cfbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void cfbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void cfbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool cfbInitializeColormap( + ColormapPtr /*pmap*/ +); + +extern int cfbExpandDirectColors( + ColormapPtr /*pmap*/, + int /*ndef*/, + xColorItem * /*indefs*/, + xColorItem * /*outdefs*/ +); + +extern Bool cfbCreateDefColormap( + ScreenPtr /*pScreen*/ +); + +extern Bool cfbSetVisualTypes( + int /*depth*/, + int /*visuals*/, + int /*bitsPerRGB*/ +); + +extern void cfbClearVisualTypes(void); + +extern Bool cfbInitVisuals( + VisualPtr * /*visualp*/, + DepthPtr * /*depthp*/, + int * /*nvisualp*/, + int * /*ndepthp*/, + int * /*rootDepthp*/, + VisualID * /*defaultVisp*/, + unsigned long /*sizes*/, + int /*bitsPerRGB*/ +); +#endif +/* cfbfillarcC.c */ + +extern void cfbPolyFillArcSolidCopy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbfillarcG.c */ + +extern void cfbPolyFillArcSolidGeneral( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbfillrct.c */ + +extern void cfbFillBoxTileOdd( + DrawablePtr /*pDrawable*/, + int /*n*/, + BoxPtr /*rects*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/ +); + +extern void cfbFillRectTileOdd( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); +/* cfbfillsp.c */ + +extern void cfbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void cfbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfb8Stipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void cfb8OpaqueStipple32FS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +#endif +/* cfbgc.c */ + +extern GCOpsPtr cfbMatchCommon( + GCPtr /*pGC*/, + cfbPrivGCPtr /*devPriv*/ +); + +extern Bool cfbCreateGC( + GCPtr /*pGC*/ +); + +extern void cfbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +/* cfbgetsp.c */ + +extern void cfbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* cfbglblt8.c */ + +extern void cfbPolyGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbglrop8.c */ + +extern void cfbPolyGlyphRop8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbhrzvert.c */ + +extern void cfbHorzS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); + +extern void cfbVertS( + int /*rop*/, + CfbBits /*and*/, + CfbBits /*xor*/, + CfbBits * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); +/* cfbigblt8.c */ + +extern void cfbImageGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbimage.c */ + +extern void cfbPutImage( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void cfbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* cfbline.c */ + +extern void cfbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void cfbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); +/* cfbmskbits.c */ +/* cfbpixmap.c */ + +extern PixmapPtr cfbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool cfbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr cfbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void cfbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void cfbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void cfbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void cfbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +/* cfbply1rctC.c */ + +extern void cfbFillPoly1RectCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* cfbply1rctG.c */ + +extern void cfbFillPoly1RectGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* cfbpntwin.c */ + +extern void cfbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); + +extern void cfbFillBoxSolid( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + unsigned long /*pixel*/ +); + +extern void cfbFillBoxTile32( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/ +); +/* cfbpolypnt.c */ + +extern void cfbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* cfbpush8.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbPushPixels8( + GCPtr /*pGC*/, + PixmapPtr /*pBitmap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); +/* cfbrctstp8.c */ + +extern void cfb8FillRectOpaqueStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfb8FillRectTransparentStippled32( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfb8FillRectStippledUnnatural( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); +#endif +/* cfbrrop.c */ + +extern int cfbReduceRasterOp( + int /*rop*/, + CfbBits /*fg*/, + CfbBits /*pm*/, + CfbBits * /*andp*/, + CfbBits * /*xorp*/ +); +/* cfbscrinit.c */ + +extern Bool cfbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); + +extern Bool cfbSetupScreen( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern Bool cfbFinishScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern Bool cfbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr cfbGetScreenPixmap( + ScreenPtr /*pScreen*/ +); + +extern void cfbSetScreenPixmap( + PixmapPtr /*pPix*/ +); + +/* cfbseg.c */ + +extern void cfbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void cfbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* cfbsetsp.c */ + +extern void cfbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + unsigned int * /*psrc*/, + int /*alu*/, + int * /*pdstBase*/, + int /*widthDst*/, + unsigned long /*planemask*/ +); + +extern void cfbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* cfbsolidC.c */ + +extern void cfbFillRectSolidCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbsolidG.c */ + +extern void cfbFillRectSolidGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbsolidX.c */ + +extern void cfbFillRectSolidXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbSolidSpansXor( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbteblt8.c */ + +#ifndef CFB_PROTOTYPES_ONLY +extern void cfbTEGlyphBlt8( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*xInit*/, + int /*yInit*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +#endif +/* cfbtegblt.c */ + +extern void cfbTEGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* cfbtile32C.c */ + +extern void cfbFillRectTile32Copy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbTile32FSCopy( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbtile32G.c */ + +extern void cfbFillRectTile32General( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nBox*/, + BoxPtr /*pBox*/ +); + +extern void cfbTile32FSGeneral( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* cfbtileoddC.c */ + +extern void cfbFillBoxTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTileOddCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillBoxTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTile32sCopy( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* cfbtileoddG.c */ + +extern void cfbFillBoxTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTileOddGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillBoxTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*nBox*/, + BoxPtr /*pBox*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); + +extern void cfbFillSpanTile32sGeneral( + DrawablePtr /*pDrawable*/, + int /*n*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + PixmapPtr /*tile*/, + int /*xrot*/, + int /*yrot*/, + int /*alu*/, + unsigned long /*planemask*/ +); +/* cfbwindow.c */ + +extern Bool cfbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool cfbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool cfbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool cfbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool cfbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void cfbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool cfbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* cfbzerarcC.c */ + +extern void cfbZeroPolyArcSS8Copy( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbzerarcG.c */ + +extern void cfbZeroPolyArcSS8General( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* cfbzerarcX.c */ + +extern void cfbZeroPolyArcSS8Xor( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#if (!defined(SINGLEDEPTH) && PSZ != 8) || defined(FORCE_SEPARATE_PRIVATE) + +#define CFB_NEED_SCREEN_PRIVATE + +extern int cfbScreenPrivateIndex; +#endif + +#ifndef CFB_PROTOTYPES_ONLY + +/* Common macros for extracting drawing information */ + +#define cfbGetWindowPixmap(d) \ + ((* ((DrawablePtr)(d))->pScreen->GetWindowPixmap)((WindowPtr)(d))) + +#define cfbGetTypedWidth(pDrawable,wtype) (\ + (((pDrawable)->type != DRAWABLE_PIXMAP) ? \ + (int) (cfbGetWindowPixmap(pDrawable)->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define cfbGetByteWidth(pDrawable) cfbGetTypedWidth(pDrawable, unsigned char) + +#define cfbGetPixelWidth(pDrawable) cfbGetTypedWidth(pDrawable, PixelType) + +#define cfbGetLongWidth(pDrawable) cfbGetTypedWidth(pDrawable, CfbBits) + +#define cfbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) \ + _pPix = cfbGetWindowPixmap(pDrawable); \ + else \ + _pPix = (PixmapPtr) (pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define cfbGetByteWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define cfbGetLongWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, CfbBits, CfbBits) + +#define cfbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + cfbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = cfbGetWindowPixmap((DrawablePtr) (pWin)); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define cfbGetWindowLongWidthAndPointer(pWin, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, CfbBits, CfbBits) + +#define cfbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pWin, width, pointer, unsigned char, unsigned char) + +#define cfbGetWindowPixelWidthAndPointer(pDrawable, width, pointer) \ + cfbGetWindowTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +/* + * XFree86 empties the root BorderClip when the VT is inactive, + * here's a macro which uses that to disable GetImage and GetSpans + */ +#define cfbWindowEnabled(pWin) \ + REGION_NOTEMPTY((pWin)->drawable.pScreen, \ + &WindowTable[(pWin)->drawable.pScreen->myNum]->borderClip) + +#define cfbDrawableEnabled(pDrawable) \ + ((pDrawable)->type == DRAWABLE_PIXMAP ? \ + TRUE : cfbWindowEnabled((WindowPtr) pDrawable)) + +#include "micoord.h" + +#endif /* !CFB_PROTOTYPES_ONLY */ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb16.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb16.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb16.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb16.h,v 1.4 1998/11/28 10:42:50 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef _CFB16_H_ +#define _CFB16_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 16 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB16_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb24.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb24.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb24.h (revision 51223) @@ -0,0 +1,98 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb24.h,v 1.4 1998/11/28 10:42:51 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _CFB24_H_ +#define _CFB24_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 24 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB24_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb32.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfb32.h,v 1.4 1998/11/28 10:42:51 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef _CFB32_H_ +#define _CFB32_H_ + +/* + * C's preprocessing language substitutes >text<, not values... + */ + +#ifdef OLDPSZ +# undef OLDPSZ +#endif + +#ifdef PSZ + +# if (PSZ == 8) +# define OLDPSZ 8 +# endif + +# if (PSZ == 16) +# define OLDPSZ 16 +# endif + +# if (PSZ == 24) +# define OLDPSZ 24 +# endif + +# if (PSZ == 32) +# define OLDPSZ 32 +# endif + +# ifndef OLDPSZ + /* Maybe an #error here ? */ +# endif + +# undef PSZ + +#endif + +#define PSZ 32 +#define CFB_PROTOTYPES_ONLY +#include "cfb.h" +#undef CFB_PROTOTYPES_ONLY +#include "cfbunmap.h" + +#undef PSZ +#ifdef OLDPSZ + +# if (OLDPSZ == 8) +# define PSZ 8 +# endif + +# if (OLDPSZ == 16) +# define PSZ 16 +# endif + +# if (OLDPSZ == 24) +# define PSZ 24 +# endif + +# if (OLDPSZ == 32) +# define PSZ 32 +# endif + +# undef OLDPSZ + +#endif + +#endif /* _CFB32_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_16.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_16.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_16.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf8_16bpp/cfb8_16.h,v 1.1 1999/01/31 12:22:16 dawes Exp $ */ + +#ifndef _CFB8_16_H +#define _CFB8_16_H + +#include "regionstr.h" +#include "windowstr.h" + +typedef struct { + pointer pix8; + int width8; + pointer pix16; + int width16; + unsigned char key; +} cfb8_16ScreenRec, *cfb8_16ScreenPtr; + +extern int cfb8_16ScreenPrivateIndex; /* XXX */ +extern int cfb8_16GetScreenPrivateIndex(void); + +Bool +cfb8_16ScreenInit ( + ScreenPtr pScreen, + pointer pbits16, + pointer pbits8, + int xsize, int ysize, + int dpix, int dpiy, + int width16, + int width8 +); + +void +cfb8_16PaintWindow ( + WindowPtr pWin, + RegionPtr pRegion, + int what +); + +Bool cfb8_16CreateWindow(WindowPtr pWin); +Bool cfb8_16DestroyWindow(WindowPtr pWin); + +Bool +cfb8_16PositionWindow( + WindowPtr pWin, + int x, int y +); + +void +cfb8_16CopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + +Bool +cfb8_16ChangeWindowAttributes( + WindowPtr pWin, + unsigned long mask +); + +void +cfb8_16WindowExposures( + WindowPtr pWin, + RegionPtr pReg, + RegionPtr pOtherReg +); + +#define CFB8_16_GET_SCREEN_PRIVATE(pScreen)\ + (cfb8_16ScreenPtr)((pScreen)->devPrivates[cfb8_16GetScreenPrivateIndex()].ptr) + +#endif /* _CFB8_16_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8_32.h (revision 51223) @@ -0,0 +1,228 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf8_32bpp/cfb8_32.h,v 1.5 2000/03/02 02:32:52 mvojkovi Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _CFB8_32_H +#define _CFB8_32_H + +#include "gcstruct.h" + +typedef struct { + GCOps *Ops8bpp; + GCOps *Ops32bpp; + unsigned long changes; + Bool OpsAre8bpp; +} cfb8_32GCRec, *cfb8_32GCPtr; + +typedef struct { + unsigned char key; + void (*EnableDisableFBAccess)(int scrnIndex, Bool enable); + pointer visualData; +} cfb8_32ScreenRec, *cfb8_32ScreenPtr; + + +extern int cfb8_32GCPrivateIndex; /* XXX */ +extern int cfb8_32GetGCPrivateIndex(void); +extern int cfb8_32ScreenPrivateIndex; /* XXX */ +extern int cfb8_32GetScreenPrivateIndex(void); + +void +cfb8_32SaveAreas( + PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin +); + +void +cfb8_32RestoreAreas( + PixmapPtr pPixmap, + RegionPtr prgnRestore, + int xorg, + int yorg, + WindowPtr pWin +); + +RegionPtr +cfb8_32CopyArea( + DrawablePtr pSrcDraw, + DrawablePtr pDstDraw, + GC *pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty +); + +void +cfbDoBitblt8To32( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long planemask +); + +void +cfbDoBitblt32To8( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long planemask +); + + +void +cfb8_32ValidateGC8( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +void +cfb8_32ValidateGC32( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +void +cfb32ValidateGC_Underlay( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDrawable +); + +Bool cfb8_32CreateGC(GCPtr pGC); + +void +cfb8_32GetSpans( + DrawablePtr pDraw, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart +); + +void +cfb8_32PutImage ( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, int y, int w, int h, + int leftPad, + int format, + char *pImage +); + +void +cfb8_32GetImage ( + DrawablePtr pDraw, + int sx, int sy, int w, int h, + unsigned int format, + unsigned long planeMask, + char *pdstLine +); + +void +cfb8_32PaintWindow ( + WindowPtr pWin, + RegionPtr pRegion, + int what +); + +Bool +cfb8_32ScreenInit ( + ScreenPtr pScreen, + pointer pbits, + int xsize, int ysize, + int dpix, int dpiy, + int width +); + +void +cfb8_32FillBoxSolid8 ( + DrawablePtr pDraw, + int nbox, + BoxPtr pBox, + unsigned long color +); + + +void +cfb8_32FillBoxSolid32 ( + DrawablePtr pDraw, + int nbox, + BoxPtr pBox, + unsigned long color +); + +RegionPtr +cfb8_32CopyPlane( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty, + unsigned long bitPlane +); + +void +cfbDoBitblt8To8GXcopy( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long pm +); + +void +cfbDoBitblt24To24GXcopy( + DrawablePtr pSrc, + DrawablePtr pDst, + int rop, + RegionPtr prgnDst, + DDXPointPtr pptSrc, + unsigned long pm +); + +Bool cfb8_32CreateWindow(WindowPtr pWin); +Bool cfb8_32DestroyWindow(WindowPtr pWin); + +Bool +cfb8_32PositionWindow( + WindowPtr pWin, + int x, int y +); + +void +cfb8_32CopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + +Bool +cfb8_32ChangeWindowAttributes( + WindowPtr pWin, + unsigned long mask +); + + +#define CFB8_32_GET_GC_PRIVATE(pGC)\ + (cfb8_32GCPtr)((pGC)->devPrivates[cfb8_32GetGCPrivateIndex()].ptr) + +#define CFB8_32_GET_SCREEN_PRIVATE(pScreen)\ + (cfb8_32ScreenPtr)((pScreen)->devPrivates[cfb8_32GetScreenPrivateIndex()].ptr) + +Bool xf86Overlay8Plus32Init (ScreenPtr pScreen); + +#endif /* _CFB8_32_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8bit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8bit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfb8bit.h (revision 51223) @@ -0,0 +1,1572 @@ +/* + * cfb8bit.h + * + * Defines which are only useful to 8 bit color frame buffers + * + * That doesn't seem to be true any more. Some of the macros in here + * are used for depths other than 8. Perhaps the file should be + * renamed. dpw + */ +/* $XFree86: xc/programs/Xserver/cfb/cfb8bit.h,v 3.7 2001/12/14 19:59:20 dawes Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ + +/* $Xorg: cfb8bit.h,v 1.4 2001/02/09 02:04:37 xorgcvs Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "servermd.h" + +#if (BITMAP_BIT_ORDER == MSBFirst) +#define GetBitGroup(x) (((PixelGroup) (x)) >> (PGSZ - PGSZB)) +#define NextBitGroup(x) ((x) <<= PGSZB) +#define NextSomeBits(x,n) ((x) <<= (n)) +#else +#define GetBitGroup(x) ((x) & PGSZBMSK) +#define NextBitGroup(x) ((x) >>= PGSZB) +#define NextSomeBits(x,n) ((x) >>= (n)) +#endif + +#define RotBitsLeft(x,k) ((x) = BitLeft (x,k) | \ + BitRight (x, PGSZ-(k))) + +#if defined(__GNUC__) && defined(mc68020) +#undef RotBitsLeft +#define RotBitsLeft(x,k) asm("rol%.l %2,%0" \ + : "=d" (x) \ + : "0" (x), "dI" (k)) +#endif + +#if PSZ == 8 + +#define GetPixelGroup(x) (cfb8StippleXor[GetBitGroup(x)]) +#define RRopPixels(dst,x) (DoRRop(dst,cfb8StippleAnd[x], cfb8StippleXor[x])) +#define RRopPixelGroup(dst,x) (RRopPixels(dst,GetBitGroup(x))) +#define MaskRRopPixels(dst,x,mask) (DoMaskRRop(dst,cfb8StippleAnd[x], cfb8StippleXor[x], mask)) + +#define NUM_MASKS (1<= MFB_PPW) \ + { \ + inputBits = *srcTemp++; \ + bitsLeft -= MFB_PPW; \ + partBitsLeft = MFB_PPW; \ + } \ + else \ + { \ + inputBits = 0; \ + if (bitsLeft) \ + inputBits = *srcTemp & ~cfb8BitLenMasks[bitsLeft]; \ + srcTemp = srcStart; \ + partBitsLeft = bitsLeft; \ + bitsLeft = bitsWhole; \ + } + +#define NextUnnaturalStippleBits \ + if (partBitsLeft >= PPW) { \ + bits = GetBitGroup (inputBits); \ + NextBitGroup (inputBits); \ + partBitsLeft -= PPW; \ + } else { \ + bits = GetBitGroup (inputBits); \ + nextPartBits = PPW - partBitsLeft; \ + NextUnnaturalStippleWord \ + if (partBitsLeft < nextPartBits) { \ + if (partBitsLeft) {\ + bits |= BitRight (GetBitGroup (inputBits), \ + PPW - nextPartBits) & PPWMSK;\ + nextPartBits -= partBitsLeft; \ + } \ + NextUnnaturalStippleWord \ + } \ + bits |= BitRight (GetBitGroup (inputBits), \ + PPW - nextPartBits) & PPWMSK; \ + NextSomeBits (inputBits, nextPartBits); \ + partBitsLeft -= nextPartBits; \ + } + +#define NextUnnaturalStippleBitsFast \ + if (partBitsLeft >= PPW) { \ + bits = GetBitGroup(inputBits); \ + NextBitGroup(inputBits); \ + partBitsLeft -= PPW; \ + } else { \ + bits = GetBitGroup (inputBits); \ + nextPartBits = PPW - partBitsLeft; \ + inputBits = *srcTemp++; \ + bits |= BitRight (GetBitGroup (inputBits), \ + partBitsLeft) & PPWMSK; \ + NextSomeBits (inputBits, nextPartBits); \ + partBitsLeft = MFB_PPW - nextPartBits; \ + } + +/* + * WriteBitGroup takes the destination address, a pixel + * value (which must be 8 bits duplicated 4 time with PFILL) + * and the PPW bits to write, which must be in the low order + * bits of the register (probably from GetBitGroup) and writes + * the appropriate locations in memory with the pixel value. This + * is a copy-mode only operation. + */ + +#define RRopBitGroup(dst,bits) \ + { \ + *(dst) = RRopPixels(*(dst),bits); \ + } + +#define MaskRRopBitGroup(dst,bits,mask) \ + { \ + *(dst) = MaskRRopPixels(*(dst),bits,mask); \ + } +#endif /* PSZ == 8 */ + +#if !defined(AVOID_MEMORY_READ) && PSZ == 8 + +#define WriteBitGroup(dst,pixel,bits) \ + { \ + register PixelGroup _maskTmp = cfb8PixelMasks[(bits)]; \ + *(dst) = (*(dst) & ~_maskTmp) | ((pixel) & _maskTmp); \ + } + +#define SwitchBitGroup(dst,pixel,bits) \ + { \ + register PixelGroup _maskTmp = cfb8PixelMasks[(bits)]; \ + register PixelGroup _pixTmp = ((pixel) & _maskTmp); \ + _maskTmp = ~_maskTmp; \ + SwitchBitsLoop (*(dst) = (*(dst) & _maskTmp) | _pixTmp;) \ + } + +#else /* AVOID_MEMORY_READ */ + +#if PGSZ == 32 +#if (BITMAP_BIT_ORDER == MSBFirst) +#define SinglePixel0 3 +#define SinglePixel1 2 +#define SinglePixel2 1 +#define SinglePixel3 0 +#define SinglePixel4 7 +#define SinglePixel5 6 +#define SinglePixel6 5 +#define SinglePixel7 4 +#define SinglePixel8 0xB +#define SinglePixel9 0xA +#define DoublePixel0 1 +#define DoublePixel1 0 +#define DoublePixel2 3 +#define DoublePixel3 2 +#define DoublePixel4 5 +#define DoublePixel5 4 +#else +#define SinglePixel0 0 +#define SinglePixel1 1 +#define SinglePixel2 2 +#define SinglePixel3 3 +#define SinglePixel4 4 +#define SinglePixel5 5 +#define SinglePixel6 6 +#define SinglePixel7 7 +#define SinglePixel8 8 +#define SinglePixel9 9 +#define DoublePixel0 0 +#define DoublePixel1 1 +#define DoublePixel2 2 +#define DoublePixel3 3 +#define DoublePixel4 4 +#define DoublePixel5 5 +#endif +#define QuadPixel0 0 +#define QuadPixel1 1 +#define QuadPixel2 2 +#else /* PGSZ == 64 */ +#if (BITMAP_BIT_ORDER == MSBFirst) +#define SinglePixel0 7 +#define SinglePixel1 6 +#define SinglePixel2 5 +#define SinglePixel3 4 +#define SinglePixel4 3 +#define SinglePixel5 2 +#define SinglePixel6 1 +#define SinglePixel7 0 +#define DoublePixel0 3 +#define DoublePixel1 2 +#define DoublePixel2 1 +#define DoublePixel3 0 +#define QuadPixel0 1 +#define QuadPixel1 0 +#else +#define SinglePixel0 0 +#define SinglePixel1 1 +#define SinglePixel2 2 +#define SinglePixel3 3 +#define SinglePixel4 4 +#define SinglePixel5 5 +#define SinglePixel6 6 +#define SinglePixel7 7 +#define DoublePixel0 0 +#define DoublePixel1 1 +#define DoublePixel2 2 +#define DoublePixel3 3 +#define QuadPixel0 0 +#define QuadPixel1 1 +#endif +#define OctaPixel0 0 +#endif /* PGSZ == 64 */ + +#if PSZ == 8 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[0] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) \ + ((PixelGroup *) (dst))[OctaPixel0] = (pixel); \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + break; \ + case 4: \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ == 64 */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[0] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + if ( bits == 0xff ) \ + SwitchBitsLoop (((PixelGroup *) (dst))[OctaPixel0] = (pixel);) \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel);)\ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel1] = (pixel);)\ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel);) \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel);)\ + break; \ + case 4: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel6] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel7] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 13: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);)\ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel1] = (pixel);) \ + break; \ + } \ + } \ +} +#endif /* PGSZ == 64 */ +#endif /* PSZ == 8 */ + +#if PSZ == 16 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[QuadPixel0] = (pixel); \ + ((PixelGroup *) (dst))[QuadPixel1] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD16 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD16 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel3] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD16 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD32 *) (dst))[DoublePixel1] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 16 */ + +#if PSZ == 24 +/* 32 000011112222*/ +/* 24 000111222333*/ +/* 16 001122334455*/ +/* 8 0123456789AB*/ +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + { \ + register CARD32 reg_pixel = (pixel); \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel2] = ((reg_pixel>>16)&0xFF); \ + break; \ + case 2: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel&0xFF; \ + ((CARD16 *) (dst))[DoublePixel2] = (reg_pixel>>8)&0xFFFF; \ + break; \ + case 3: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel & 0xFF; \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel2] = (reg_pixel>>8)&0xFFFF; \ + ((CARD8 *) (dst))[SinglePixel2] = (reg_pixel>>16&0xFF); \ + break; \ + case 4: \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel8] = (reg_pixel>>16)&0xFF; \ + break; \ + case 5: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 16; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 6: \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 7: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel3] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel&0xFF; \ + break; \ + case 8: \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + ((CARD16 *) (dst))[DoublePixel5] = (reg_pixel>>8); \ + break; \ + case 9: \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel&0xFF; \ + break; \ + case 10: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel&0xFF; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + break; \ + case 11: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel0] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel; \ + break; \ + case 12: \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 13: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel2] = \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 14: \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = reg_pixel; \ + break; \ + case 15: \ + ((CARD16 *) (dst))[DoublePixel0] = \ + ((CARD16 *) (dst))[DoublePixel3] = reg_pixel; \ + ((CARD8 *) (dst))[SinglePixel3] = \ + ((CARD8 *) (dst))[SinglePixel9] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD16 *) (dst))[DoublePixel2] = \ + ((CARD16 *) (dst))[DoublePixel5] = reg_pixel; \ + reg_pixel >>= 8; \ + ((CARD8 *) (dst))[SinglePixel8] = \ + ((CARD8 *) (dst))[SinglePixel2] = reg_pixel; \ + break; \ + } \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[DoublePixel0] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel1] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel2] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel3] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel8] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel2] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel);) \ + ((CARD8 *) (dst))[SinglePixel9] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel5] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD16 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD8 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD16 *) (dst))[DoublePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD8 *) (dst))[SinglePixel3] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[QuadPixel0] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel1] = (pixel); \ + ((CARD32 *) (dst))[QuadPixel2] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 24 */ + +#if PSZ == 32 + +#if PGSZ == 32 +#define WriteBitGroup(dst,pixel,bits) \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } +#else /* PGSZ == 64 */ +#define WriteBitGroup(dst,pixel,bits) \ + if ( bits == 0xff ) { \ + ((PixelGroup *) (dst))[DoublePixel0] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel1] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel2] = (pixel); \ + ((PixelGroup *) (dst))[DoublePixel3] = (pixel); \ + } \ + else { \ + switch (bits & 0x0f) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel); \ + break; \ + } \ + switch ((bits & 0xf0) >> 4) { \ + case 0: \ + break; \ + case 1: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + break; \ + case 2: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 3: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + break; \ + case 4: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 5: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 6: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 7: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + break; \ + case 8: \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 9: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 10: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 11: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 12: \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 13: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 14: \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + case 15: \ + ((CARD32 *) (dst))[SinglePixel4] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel5] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel6] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel7] = (pixel); \ + break; \ + } \ + } +#endif /* PGSZ */ + +#if PGSZ == 32 +#define SwitchBitGroup(dst,pixel,bits) { \ + switch (bits) { \ + case 0: \ + break; \ + case 1: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel);) \ + break; \ + case 2: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 3: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel);) \ + break; \ + case 4: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 5: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 6: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 7: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel);) \ + break; \ + case 8: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 9: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 10: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 11: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 12: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 13: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 14: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + case 15: \ + SwitchBitsLoop (((CARD32 *) (dst))[SinglePixel0] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel1] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel2] = (pixel); \ + ((CARD32 *) (dst))[SinglePixel3] = (pixel);) \ + break; \ + } \ +} +#else /* PGSZ == 64 */ +#define SwitchBitGroup(dst,pixel,bits) { \ + cfb cannot hack 64-bit SwitchBitGroup psz=PSZ +#endif /* PGSZ */ + +#endif /* PSZ == 32 */ +#endif /* AVOID_MEMORY_READ */ + +extern PixelGroup cfb8BitLenMasks[PGSZ]; + +extern int cfb8SetStipple ( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*planemask*/ +); + +extern int cfb8SetOpaqueStipple ( + int /*alu*/, + CfbBits /*fg*/, + CfbBits /*bg*/, + CfbBits /*planemask*/ +); + +extern int cfb8ComputeClipMasks32 ( + BoxPtr /*pBox*/, + int /*numRects*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + CARD32 * /*clips*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmap.h (revision 51223) @@ -0,0 +1,344 @@ +/* + * $Xorg: cfbmap.h,v 1.4 2001/02/09 02:04:38 xorgcvs Exp $ + * +Copyright 1991, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ + +/* $XFree86: xc/programs/Xserver/cfb/cfbmap.h,v 3.11tsi Exp $ */ + +/* + * Map names around so that multiple depths can be supported simultaneously + */ + +#if 0 +#undef QuartetBitsTable +#undef QuartetPixelMaskTable +#undef cfb8ClippedLineCopy +#undef cfb8ClippedLineGeneral +#undef cfb8ClippedLineXor +#undef cfb8LineSS1Rect +#undef cfb8LineSS1RectCopy +#undef cfb8LineSS1RectGeneral +#undef cfb8LineSS1RectPreviousCopy +#undef cfb8LineSS1RectXor +#undef cfb8SegmentSS1Rect +#undef cfb8SegmentSS1RectCopy +#undef cfb8SegmentSS1RectGeneral +#undef cfb8SegmentSS1RectShiftCopy +#undef cfb8SegmentSS1RectXor +#undef cfbAllocatePrivates +#undef cfbBSFuncRec +#undef cfbBitBlt +#undef cfbBresD +#undef cfbBresS +#undef cfbChangeWindowAttributes +#undef cfbCloseScreen +#undef cfbCopyArea +#undef cfbCopyImagePlane +#undef cfbCopyPixmap +#undef cfbCopyPlane +#undef cfbCopyPlaneReduce +#undef cfbCopyRotatePixmap +#undef cfbCopyWindow +#undef cfbCreateGC +#undef cfbCreatePixmap +#undef cfbCreateScreenResources +#undef cfbCreateWindow +#undef cfbDestroyPixmap +#undef cfbDestroyWindow +#undef cfbDoBitblt +#undef cfbDoBitbltCopy +#undef cfbDoBitbltGeneral +#undef cfbDoBitbltOr +#undef cfbDoBitbltXor +#undef cfbFillBoxSolid +#undef cfbFillBoxTile32 +#undef cfbFillBoxTile32sCopy +#undef cfbFillBoxTile32sGeneral +#undef cfbFillBoxTileOdd +#undef cfbFillBoxTileOddCopy +#undef cfbFillBoxTileOddGeneral +#undef cfbFillPoly1RectCopy +#undef cfbFillPoly1RectGeneral +#undef cfbFillRectSolidCopy +#undef cfbFillRectSolidGeneral +#undef cfbFillRectSolidXor +#undef cfbFillRectTile32Copy +#undef cfbFillRectTile32General +#undef cfbFillRectTileOdd +#undef cfbFillSpanTile32sCopy +#undef cfbFillSpanTile32sGeneral +#undef cfbFillSpanTileOddCopy +#undef cfbFillSpanTileOddGeneral +#undef cfbFinishScreenInit +#undef cfbGCFuncs +#undef cfbGCPrivateIndex +#undef cfbGetImage +#undef cfbGetScreenPixmap +#undef cfbGetSpans +#undef cfbHorzS +#undef cfbImageGlyphBlt8 +#undef cfbInitializeColormap +#undef cfbInstallColormap +#undef cfbLineSD +#undef cfbLineSS +#undef cfbListInstalledColormaps +#undef cfbMapWindow +#undef cfbMatchCommon +#undef cfbNonTEOps +#undef cfbNonTEOps1Rect +#undef cfbPadPixmap +#undef cfbPaintWindow +#undef cfbPolyFillArcSolidCopy +#undef cfbPolyFillArcSolidGeneral +#undef cfbPolyFillRect +#undef cfbPolyGlyphBlt8 +#undef cfbPolyGlyphRop8 +#undef cfbPolyPoint +#undef cfbPositionWindow +#undef cfbPutImage +#undef cfbReduceRasterOp +#undef cfbResolveColor +#undef cfbRestoreAreas +#undef cfbSaveAreas +#undef cfbScreenInit +#undef cfbScreenPrivateIndex +#undef cfbSegmentSD +#undef cfbSegmentSS +#undef cfbSetScanline +#undef cfbSetScreenPixmap +#undef cfbSetSpans +#undef cfbSetupScreen +#undef cfbSolidSpansCopy +#undef cfbSolidSpansGeneral +#undef cfbSolidSpansXor +#undef cfbStippleStack +#undef cfbStippleStackTE +#undef cfbTEGlyphBlt +#undef cfbTEOps +#undef cfbTEOps1Rect +#undef cfbTile32FSCopy +#undef cfbTile32FSGeneral +#undef cfbUninstallColormap +#undef cfbUnmapWindow +#undef cfbUnnaturalStippleFS +#undef cfbUnnaturalTileFS +#undef cfbValidateGC +#undef cfbVertS +#undef cfbWindowPrivateIndex +#undef cfbXRotatePixmap +#undef cfbYRotatePixmap +#undef cfbZeroPolyArcSS8Copy +#undef cfbZeroPolyArcSS8General +#undef cfbZeroPolyArcSS8Xor +#undef cfbendpartial +#undef cfbendtab +#undef cfbmask +#undef cfbrmask +#undef cfbstartpartial +#undef cfbstarttab +#endif + +/* a losing vendor cpp dumps core if we define CFBNAME in terms of CATNAME */ + +#if PSZ != 8 + +#if PSZ == 32 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb32##subname +#else +#define CFBNAME(subname) cfb32/**/subname +#endif +#endif + +#if PSZ == 24 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb24##subname +#else +#define CFBNAME(subname) cfb24/**/subname +#endif +#endif + +#if PSZ == 16 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb16##subname +#else +#define CFBNAME(subname) cfb16/**/subname +#endif +#endif + +#if PSZ == 4 +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CFBNAME(subname) cfb4##subname +#else +#define CFBNAME(subname) cfb4/**/subname +#endif +#endif + +#ifndef CFBNAME +cfb can not hack PSZ yet +#endif + +#undef CATNAME + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define CATNAME(prefix,subname) prefix##subname +#else +#define CATNAME(prefix,subname) prefix/**/subname +#endif + +#define QuartetBitsTable CFBNAME(QuartetBitsTable) +#define QuartetPixelMaskTable CFBNAME(QuartetPixelMaskTable) +#define cfb8ClippedLineCopy CFBNAME(ClippedLineCopy) +#define cfb8ClippedLineGeneral CFBNAME(ClippedLineGeneral ) +#define cfb8ClippedLineXor CFBNAME(ClippedLineXor) +#define cfb8LineSS1Rect CFBNAME(LineSS1Rect) +#define cfb8LineSS1RectCopy CFBNAME(LineSS1RectCopy) +#define cfb8LineSS1RectGeneral CFBNAME(LineSS1RectGeneral ) +#define cfb8LineSS1RectPreviousCopy CFBNAME(LineSS1RectPreviousCopy) +#define cfb8LineSS1RectXor CFBNAME(LineSS1RectXor) +#define cfb8SegmentSS1Rect CFBNAME(SegmentSS1Rect) +#define cfb8SegmentSS1RectCopy CFBNAME(SegmentSS1RectCopy) +#define cfb8SegmentSS1RectGeneral CFBNAME(SegmentSS1RectGeneral ) +#define cfb8SegmentSS1RectShiftCopy CFBNAME(SegmentSS1RectShiftCopy) +#define cfb8SegmentSS1RectXor CFBNAME(SegmentSS1RectXor) +#define cfbAllocatePrivates CFBNAME(AllocatePrivates) +#define cfbBSFuncRec CFBNAME(BSFuncRec) +#define cfbBitBlt CFBNAME(BitBlt) +#define cfbBresD CFBNAME(BresD) +#define cfbBresS CFBNAME(BresS) +#define cfbChangeWindowAttributes CFBNAME(ChangeWindowAttributes) +#define cfbClearVisualTypes CFBNAME(cfbClearVisualTypes) +#define cfbCloseScreen CFBNAME(CloseScreen) +#define cfbCreateDefColormap CFBNAME (cfbCreateDefColormap) +#define cfbCopyArea CFBNAME(CopyArea) +#define cfbCopyImagePlane CFBNAME(CopyImagePlane) +#define cfbCopyPixmap CFBNAME(CopyPixmap) +#define cfbCopyPlane CFBNAME(CopyPlane) +#define cfbCopyPlaneReduce CFBNAME(CopyPlaneReduce) +#define cfbCopyRotatePixmap CFBNAME(CopyRotatePixmap) +#define cfbCopyWindow CFBNAME(CopyWindow) +#define cfbCreateGC CFBNAME(CreateGC) +#define cfbCreatePixmap CFBNAME(CreatePixmap) +#define cfbCreateScreenResources CFBNAME(CreateScreenResources) +#define cfbCreateWindow CFBNAME(CreateWindow) +#define cfbDestroyPixmap CFBNAME(DestroyPixmap) +#define cfbDestroyWindow CFBNAME(DestroyWindow) +#define cfbDoBitblt CFBNAME(DoBitblt) +#define cfbDoBitbltCopy CFBNAME(DoBitbltCopy) +#define cfbDoBitbltGeneral CFBNAME(DoBitbltGeneral) +#define cfbDoBitbltOr CFBNAME(DoBitbltOr) +#define cfbDoBitbltXor CFBNAME(DoBitbltXor) +#define cfbExpandDirectColors CFBNAME(cfbExpandDirectColors) +#define cfbFillBoxSolid CFBNAME(FillBoxSolid) +#define cfbFillBoxTile32 CFBNAME(FillBoxTile32) +#define cfbFillBoxTile32sCopy CFBNAME(FillBoxTile32sCopy) +#define cfbFillBoxTile32sGeneral CFBNAME(FillBoxTile32sGeneral) +#define cfbFillBoxTileOdd CFBNAME(FillBoxTileOdd) +#define cfbFillBoxTileOddCopy CFBNAME(FillBoxTileOddCopy) +#define cfbFillBoxTileOddGeneral CFBNAME(FillBoxTileOddGeneral) +#define cfbFillPoly1RectCopy CFBNAME(FillPoly1RectCopy) +#define cfbFillPoly1RectGeneral CFBNAME(FillPoly1RectGeneral) +#define cfbFillRectSolidCopy CFBNAME(FillRectSolidCopy) +#define cfbFillRectSolidGeneral CFBNAME(FillRectSolidGeneral) +#define cfbFillRectSolidXor CFBNAME(FillRectSolidXor) +#define cfbFillRectTile32Copy CFBNAME(FillRectTile32Copy) +#define cfbFillRectTile32General CFBNAME(FillRectTile32General) +#define cfbFillRectTileOdd CFBNAME(FillRectTileOdd) +#define cfbFillSpanTile32sCopy CFBNAME(FillSpanTile32sCopy) +#define cfbFillSpanTile32sGeneral CFBNAME(FillSpanTile32sGeneral) +#define cfbFillSpanTileOddCopy CFBNAME(FillSpanTileOddCopy) +#define cfbFillSpanTileOddGeneral CFBNAME(FillSpanTileOddGeneral) +#define cfbFinishScreenInit CFBNAME(FinishScreenInit) +#define cfbGCFuncs CFBNAME(GCFuncs) +#define cfbGCPrivateIndex CFBNAME(GCPrivateIndex) +#define cfbGetImage CFBNAME(GetImage) +#define cfbGetScreenPixmap CFBNAME(GetScreenPixmap) +#define cfbGetSpans CFBNAME(GetSpans) +#define cfbHorzS CFBNAME(HorzS) +#define cfbImageGlyphBlt8 CFBNAME(ImageGlyphBlt8) +#define cfbInitializeColormap CFBNAME(InitializeColormap) +#define cfbInitVisuals CFBNAME(cfbInitVisuals) +#define cfbInstallColormap CFBNAME(InstallColormap) +#define cfbLineSD CFBNAME(LineSD) +#define cfbLineSS CFBNAME(LineSS) +#define cfbListInstalledColormaps CFBNAME(ListInstalledColormaps) +#define cfbMapWindow CFBNAME(MapWindow) +#define cfbMatchCommon CFBNAME(MatchCommon) +#define cfbNonTEOps CFBNAME(NonTEOps) +#define cfbNonTEOps1Rect CFBNAME(NonTEOps1Rect) +#define cfbPadPixmap CFBNAME(PadPixmap) +#define cfbPaintWindow CFBNAME(PaintWindow) +#define cfbPolyFillArcSolidCopy CFBNAME(PolyFillArcSolidCopy) +#define cfbPolyFillArcSolidGeneral CFBNAME(PolyFillArcSolidGeneral) +#define cfbPolyFillRect CFBNAME(PolyFillRect) +#define cfbPolyGlyphBlt8 CFBNAME(PolyGlyphBlt8) +#define cfbPolyGlyphRop8 CFBNAME(PolyGlyphRop8) +#define cfbPolyPoint CFBNAME(PolyPoint) +#define cfbPositionWindow CFBNAME(PositionWindow) +#define cfbPutImage CFBNAME(PutImage) +#define cfbReduceRasterOp CFBNAME(ReduceRasterOp) +#define cfbResolveColor CFBNAME(ResolveColor) +#define cfbRestoreAreas CFBNAME(RestoreAreas) +#define cfbSaveAreas CFBNAME(SaveAreas) +#define cfbScreenInit CFBNAME(ScreenInit) +#define cfbScreenPrivateIndex CFBNAME(ScreenPrivateIndex) +#define cfbSegmentSD CFBNAME(SegmentSD) +#define cfbSegmentSS CFBNAME(SegmentSS) +#define cfbSetScanline CFBNAME(SetScanline) +#define cfbSetScreenPixmap CFBNAME(SetScreenPixmap) +#define cfbSetSpans CFBNAME(SetSpans) +#define cfbSetVisualTypes CFBNAME(cfbSetVisualTypes) +#define cfbSetupScreen CFBNAME(SetupScreen) +#define cfbSolidSpansCopy CFBNAME(SolidSpansCopy) +#define cfbSolidSpansGeneral CFBNAME(SolidSpansGeneral) +#define cfbSolidSpansXor CFBNAME(SolidSpansXor) +#define cfbStippleStack CFBNAME(StippleStack) +#define cfbStippleStackTE CFBNAME(StippleStackTE) +#define cfbTEGlyphBlt CFBNAME(TEGlyphBlt) +#define cfbTEOps CFBNAME(TEOps) +#define cfbTEOps1Rect CFBNAME(TEOps1Rect) +#define cfbTile32FSCopy CFBNAME(Tile32FSCopy) +#define cfbTile32FSGeneral CFBNAME(Tile32FSGeneral) +#define cfbUninstallColormap CFBNAME(UninstallColormap) +#define cfbUnmapWindow CFBNAME(UnmapWindow) +#define cfbUnnaturalStippleFS CFBNAME(UnnaturalStippleFS) +#define cfbUnnaturalTileFS CFBNAME(UnnaturalTileFS) +#define cfbValidateGC CFBNAME(ValidateGC) +#define cfbVertS CFBNAME(VertS) +#define cfbWindowPrivateIndex CFBNAME(WindowPrivateIndex) +#define cfbXRotatePixmap CFBNAME(XRotatePixmap) +#define cfbYRotatePixmap CFBNAME(YRotatePixmap) +#define cfbZeroPolyArcSS8Copy CFBNAME(ZeroPolyArcSSCopy) +#define cfbZeroPolyArcSS8General CFBNAME(ZeroPolyArcSSGeneral) +#define cfbZeroPolyArcSS8Xor CFBNAME(ZeroPolyArcSSXor) +#define cfbendpartial CFBNAME(endpartial) +#define cfbendtab CFBNAME(endtab) +#define cfbmask CFBNAME(mask) +#define cfbrmask CFBNAME(rmask) +#define cfbstartpartial CFBNAME(startpartial) +#define cfbstarttab CFBNAME(starttab) + +#endif /* PSZ != 8 */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmskbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmskbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbmskbits.h (revision 51223) @@ -0,0 +1,896 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfbmskbits.h,v 3.13tsi Exp $ */ +/************************************************************ +Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this +software and its documentation for any purpose and without +fee is hereby granted, provided that the above copyright no- +tice appear in all copies and that both that copyright no- +tice and this permission notice appear in supporting docu- +mentation, and that the names of Sun or The Open Group +not be used in advertising or publicity pertaining to +distribution of the software without specific prior +written permission. Sun and The Open Group make no +representations about the suitability of this software for +any purpose. It is provided "as is" without any express or +implied warranty. + +SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- +NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI- +ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH +THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/* $Xorg: cfbmskbits.h,v 1.3 2000/08/17 19:48:14 cpqbld Exp $ */ +/* Optimizations for PSZ == 32 added by Kyle Marvin (marvin@vitec.com) */ + +#include +#include +#include "servermd.h" +#if defined(XFREE86) || ( defined(__OpenBSD__) && defined(__alpha__) ) \ + || (defined(__bsdi__)) +#include "compiler.h" +#endif + +/* + * ========================================================================== + * Converted from mfb to support memory-mapped color framebuffer by smarks@sun, + * April-May 1987. + * + * The way I did the conversion was to consider each longword as an + * array of four bytes instead of an array of 32 one-bit pixels. So + * getbits() and putbits() retain much the same calling sequence, but + * they move bytes around instead of bits. Of course, this entails the + * removal of all of the one-bit-pixel dependencies from the other + * files, but the major bit-hacking stuff should be covered here. + * + * I've created some new macros that make it easier to understand what's + * going on in the pixel calculations, and that make it easier to change the + * pixel size. + * + * name explanation + * ---- ----------- + * PSZ pixel size (in bits) + * PGSZ pixel group size (in bits) + * PGSZB pixel group size (in bytes) + * PGSZBMSK mask with lowest PGSZB bits set to 1 + * PPW pixels per word (pixels per pixel group) + * PPWMSK mask with lowest PPW bits set to 1 + * PLST index of last pixel in a word (should be PPW-1) + * PIM pixel index mask (index within a pixel group) + * PWSH pixel-to-word shift (should be log2(PPW)) + * PMSK mask with lowest PSZ bits set to 1 + * + * + * Here are some sample values. In the notation cfbA,B: A is PSZ, and + * B is PGSZB. All the other values are derived from these + * two. This table does not show all combinations! + * + * name cfb8,4 cfb24,4 cfb32,4 cfb8,8 cfb24,8 cfb32,8 + * ---- ------ ------- ------ ------ ------ ------- + * PSZ 8 24 32 8 24 32 + * PGSZ 32 32 32 64 64 64 + * PGSZB 4 4 4 8 8 8 + * PGSZBMSK 0xF 0xF? 0xF 0xFF 0xFF 0xFF + * PPW 4 1 1 8 2 2 + * PPWMSK 0xF 0x1 0x1 0xFF 0x3? 0x3 + * PLST 3 0 0 7 1 1 + * PIM 0x3 0x0 0x0 0x7 0x1? 0x1 + * PWSH 2 0 0 3 1 1 + * PMSK 0xFF 0xFFFFFF 0xFFFFFFFF 0xFF 0xFFFFFF 0xFFFFFFFF + * + * + * I have also added a new macro, PFILL, that takes one pixel and + * replicates it throughout a word. This macro definition is dependent + * upon pixel and word size; it doesn't use macros like PPW and so + * forth. Examples: for monochrome, PFILL(1) => 0xffffffff, PFILL(0) => + * 0x00000000. For 8-bit color, PFILL(0x5d) => 0x5d5d5d5d. This macro + * is used primarily for replicating a plane mask into a word. + * + * Color framebuffers operations also support the notion of a plane + * mask. This mask determines which planes of the framebuffer can be + * altered; the others are left unchanged. I have added another + * parameter to the putbits and putbitsrop macros that is the plane + * mask. + * ========================================================================== + * + * Keith Packard (keithp@suse.com) + * 64bit code is no longer supported; it requires DIX support + * for repadding images which significantly impacts performance + */ + +/* + * PSZ needs to be defined before we get here. Usually it comes from a + * -DPSZ=foo on the compilation command line. + */ + +#ifndef PSZ +#define PSZ 8 +#endif + +/* + * PixelGroup is the data type used to operate on groups of pixels. + * We typedef it here to CARD32 with the assumption that you + * want to manipulate 32 bits worth of pixels at a time as you can. If CARD32 + * is not appropriate for your server, define it to something else + * before including this file. In this case you will also have to define + * PGSZB to the size in bytes of PixelGroup. + */ +#ifndef PixelGroup +#define PixelGroup CARD32 +#define PGSZB 4 +#endif /* PixelGroup */ + +#ifndef CfbBits +#define CfbBits CARD32 +#endif + +#define PGSZ (PGSZB << 3) +#define PPW (PGSZ/PSZ) +#define PLST (PPW-1) +#define PIM PLST +#define PMSK (((PixelGroup)1 << PSZ) - 1) +#define PPWMSK (((PixelGroup)1 << PPW) - 1) /* instead of BITMSK */ +#define PGSZBMSK (((PixelGroup)1 << PGSZB) - 1) + +/* set PWSH = log2(PPW) using brute force */ + +#if PPW == 1 +#define PWSH 0 +#else +#if PPW == 2 +#define PWSH 1 +#else +#if PPW == 4 +#define PWSH 2 +#else +#if PPW == 8 +#define PWSH 3 +#else +#if PPW == 16 +#define PWSH 4 +#endif /* PPW == 16 */ +#endif /* PPW == 8 */ +#endif /* PPW == 4 */ +#endif /* PPW == 2 */ +#endif /* PPW == 1 */ + +/* Defining PIXEL_ADDR means that individual pixels are addressable by this + * machine (as type PixelType). A possible CFB architecture which supported + * 8-bits-per-pixel on a non byte-addressable machine would not have this + * defined. + * + * Defining FOUR_BIT_CODE means that cfb knows how to stipple on this machine; + * eventually, stippling code for 16 and 32 bit devices should be written + * which would allow them to also use FOUR_BIT_CODE. There isn't that + * much to do in those cases, but it would make them quite a bit faster. + */ + +#if PSZ == 8 +#define PIXEL_ADDR +typedef CARD8 PixelType; +#define FOUR_BIT_CODE +#endif + +#if PSZ == 16 +#define PIXEL_ADDR +typedef CARD16 PixelType; +#endif + +#if PSZ == 24 +#undef PMSK +#define PMSK 0xFFFFFF +/*#undef PIM +#define PIM 3*/ +#define PIXEL_ADDR +typedef CARD32 PixelType; +#endif + +#if PSZ == 32 +#undef PMSK +#define PMSK 0xFFFFFFFF +#define PIXEL_ADDR +typedef CARD32 PixelType; +#endif + + +/* the following notes use the following conventions: +SCREEN LEFT SCREEN RIGHT +in this file and maskbits.c, left and right refer to screen coordinates, +NOT bit numbering in registers. + +cfbstarttab[n] + pixels[0,n-1] = 0's pixels[n,PPW-1] = 1's +cfbendtab[n] = + pixels[0,n-1] = 1's pixels[n,PPW-1] = 0's + +cfbstartpartial[], cfbendpartial[] + these are used as accelerators for doing putbits and masking out +bits that are all contained between longword boudaries. the extra +256 bytes of data seems a small price to pay -- code is smaller, +and narrow things (e.g. window borders) go faster. + +the names may seem misleading; they are derived not from which end +of the word the bits are turned on, but at which end of a scanline +the table tends to be used. + +look at the tables and macros to understand boundary conditions. +(careful readers will note that starttab[n] = ~endtab[n] for n != 0) + +----------------------------------------------------------------------- +these two macros depend on the screen's bit ordering. +in both of them x is a screen position. they are used to +combine bits collected from multiple longwords into a +single destination longword, and to unpack a single +source longword into multiple destinations. + +SCRLEFT(dst, x) + takes dst[x, PPW] and moves them to dst[0, PPW-x] + the contents of the rest of dst are 0 ONLY IF + dst is UNSIGNED. + is cast as an unsigned. + this is a right shift on the VAX, left shift on + Sun and pc-rt. + +SCRRIGHT(dst, x) + takes dst[0,x] and moves them to dst[PPW-x, PPW] + the contents of the rest of dst are 0 ONLY IF + dst is UNSIGNED. + this is a left shift on the VAX, right shift on + Sun and pc-rt. + + +the remaining macros are cpu-independent; all bit order dependencies +are built into the tables and the two macros above. + +maskbits(x, w, startmask, endmask, nlw) + for a span of width w starting at position x, returns +a mask for ragged pixels at start, mask for ragged pixels at end, +and the number of whole longwords between the ends. + +maskpartialbits(x, w, mask) + works like maskbits(), except all the pixels are in the + same longword (i.e. (x&0xPIM + w) <= PPW) + +mask32bits(x, w, startmask, endmask, nlw) + as maskbits, but does not calculate nlw. it is used by + cfbGlyphBlt to put down glyphs <= PPW bits wide. + +getbits(psrc, x, w, dst) + starting at position x in psrc (x < PPW), collect w + pixels and put them in the screen left portion of dst. + psrc is a longword pointer. this may span longword boundaries. + it special-cases fetching all w bits from one longword. + + +--------+--------+ +--------+ + | | m |n| | ==> | m |n| | + +--------+--------+ +--------+ + x x+w 0 w + psrc psrc+1 dst + m = PPW - x + n = w - m + + implementation: + get m pixels, move to screen-left of dst, zeroing rest of dst; + get n pixels from next word, move screen-right by m, zeroing + lower m pixels of word. + OR the two things together. + +putbits(src, x, w, pdst, planemask) + starting at position x in pdst, put down the screen-leftmost + w bits of src. pdst is a longword pointer. this may + span longword boundaries. + it special-cases putting all w bits into the same longword. + + +--------+ +--------+--------+ + | m |n| | ==> | | m |n| | + +--------+ +--------+--------+ + 0 w x x+w + dst pdst pdst+1 + m = PPW - x + n = w - m + + implementation: + get m pixels, shift screen-right by x, zero screen-leftmost x + pixels; zero rightmost m bits of *pdst and OR in stuff + from before the semicolon. + shift src screen-left by m, zero bits n-32; + zero leftmost n pixels of *(pdst+1) and OR in the + stuff from before the semicolon. + +putbitsrop(src, x, w, pdst, planemask, ROP) + like putbits but calls DoRop with the rasterop ROP (see cfb.h for + DoRop) + +getleftbits(psrc, w, dst) + get the leftmost w (w<=PPW) bits from *psrc and put them + in dst. this is used by the cfbGlyphBlt code for glyphs + <=PPW bits wide. +*/ + +#if (BITMAP_BIT_ORDER == MSBFirst) +#define BitRight(lw,n) ((lw) >> (n)) +#define BitLeft(lw,n) ((lw) << (n)) +#else /* (BITMAP_BIT_ORDER == LSBFirst) */ +#define BitRight(lw,n) ((lw) << (n)) +#define BitLeft(lw,n) ((lw) >> (n)) +#endif /* (BITMAP_BIT_ORDER == MSBFirst) */ + +#define SCRLEFT(lw, n) BitLeft (lw, (n) * PSZ) +#define SCRRIGHT(lw, n) BitRight(lw, (n) * PSZ) + +/* + * Note that the shift direction is independent of the byte ordering of the + * machine. The following is portable code. + */ +#if PPW == 16 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ | \ + ((p)&PMSK) << 4*PSZ | \ + ((p)&PMSK) << 5*PSZ | \ + ((p)&PMSK) << 6*PSZ | \ + ((p)&PMSK) << 7*PSZ | \ + ((p)&PMSK) << 8*PSZ | \ + ((p)&PMSK) << 9*PSZ | \ + ((p)&PMSK) << 10*PSZ | \ + ((p)&PMSK) << 11*PSZ | \ + ((p)&PMSK) << 12*PSZ | \ + ((p)&PMSK) << 13*PSZ | \ + ((p)&PMSK) << 14*PSZ | \ + ((p)&PMSK) << 15*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ + pf |= (pf << 4*PSZ); \ + pf |= (pf << 8*PSZ); \ +} +#endif /* PPW == 16 */ +#if PPW == 8 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ | \ + ((p)&PMSK) << 4*PSZ | \ + ((p)&PMSK) << 5*PSZ | \ + ((p)&PMSK) << 6*PSZ | \ + ((p)&PMSK) << 7*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ + pf |= (pf << 4*PSZ); \ +} +#endif +#if PPW == 4 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ | \ + ((p)&PMSK) << 2*PSZ | \ + ((p)&PMSK) << 3*PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ + pf |= (pf << 2*PSZ); \ +} +#endif +#if PPW == 2 +#define PFILL(p) ( ((p)&PMSK) | \ + ((p)&PMSK) << PSZ ) +#define PFILL2(p, pf) { \ + pf = (p) & PMSK; \ + pf |= (pf << PSZ); \ +} +#endif +#if PPW == 1 +#define PFILL(p) (p) +#define PFILL2(p,pf) (pf = (p)) +#endif + +/* + * Reduced raster op - using precomputed values, perform the above + * in three instructions + */ + +#define DoRRop(dst, and, xor) (((dst) & (and)) ^ (xor)) + +#define DoMaskRRop(dst, and, xor, mask) \ + (((dst) & ((and) | ~(mask))) ^ (xor & mask)) + +#if PSZ != 32 || PPW != 1 + +# if (PSZ == 24 && PPW == 1) +#define maskbits(x, w, startmask, endmask, nlw) {\ + startmask = cfbstarttab[(x)&3]; \ + endmask = cfbendtab[((x)+(w)) & 3]; \ + nlw = ((((x)+(w))*3)>>2) - (((x)*3 +3)>>2); \ +} + +#define mask32bits(x, w, startmask, endmask) \ + startmask = cfbstarttab[(x)&3]; \ + endmask = cfbendtab[((x)+(w)) & 3]; + +#define maskpartialbits(x, w, mask) \ + mask = cfbstartpartial[(x) & 3] & cfbendpartial[((x)+(w)) & 3]; + +#define maskbits24(x, w, startmask, endmask, nlw) \ + startmask = cfbstarttab24[(x) & 3]; \ + endmask = cfbendtab24[((x)+(w)) & 3]; \ + if (startmask){ \ + nlw = (((w) - (4 - ((x) & 3))) >> 2); \ + } else { \ + nlw = (w) >> 2; \ + } + +#define getbits24(psrc, dst, index) {\ + register int idx; \ + switch(idx = ((index)&3)<<1){ \ + case 0: \ + dst = (*(psrc) &cfbmask[idx]); \ + break; \ + case 6: \ + dst = BitLeft((*(psrc) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dst = BitLeft((*(psrc) &cfbmask[idx]), cfb24Shift[idx]) | \ + BitRight(((*((psrc)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ +} + +#define putbits24(src, w, pdst, planemask, index) {\ + register PixelGroup dstpixel; \ + register unsigned int idx; \ + switch(idx = ((index)&3)<<1){ \ + case 0: \ + dstpixel = (*(pdst) &cfbmask[idx]); \ + break; \ + case 6: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx])| \ + BitRight(((*((pdst)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ + dstpixel &= ~(planemask); \ + dstpixel |= (src & planemask); \ + *(pdst) &= cfbrmask[idx]; \ + switch(idx){ \ + case 0: \ + *(pdst) |= (dstpixel & cfbmask[idx]); \ + break; \ + case 2: \ + case 4: \ + pdst++;idx++; \ + *(pdst) = ((*(pdst)) & cfbrmask[idx]) | \ + (BitLeft(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + pdst--;idx--; \ + case 6: \ + *(pdst) |= (BitRight(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + break; \ + }; \ +} + +#define putbitsrop24(src, x, pdst, planemask, rop) \ +{ \ + register PixelGroup t1, dstpixel; \ + register unsigned int idx; \ + switch(idx = (x)<<1){ \ + case 0: \ + dstpixel = (*(pdst) &cfbmask[idx]); \ + break; \ + case 6: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx]); \ + break; \ + default: \ + dstpixel = BitLeft((*(pdst) &cfbmask[idx]), cfb24Shift[idx])| \ + BitRight(((*((pdst)+1)) &cfbmask[idx+1]), cfb24Shift[idx+1]); \ + }; \ + DoRop(t1, rop, (src), dstpixel); \ + dstpixel &= ~planemask; \ + dstpixel |= (t1 & planemask); \ + *(pdst) &= cfbrmask[idx]; \ + switch(idx){ \ + case 0: \ + *(pdst) |= (dstpixel & cfbmask[idx]); \ + break; \ + case 2: \ + case 4: \ + *((pdst)+1) = ((*((pdst)+1)) & cfbrmask[idx+1]) | \ + (BitLeft(dstpixel, cfb24Shift[idx+1]) & (cfbmask[idx+1])); \ + case 6: \ + *(pdst) |= (BitRight(dstpixel, cfb24Shift[idx]) & cfbmask[idx]); \ + }; \ +} +# else /* PSZ == 24 && PPW == 1 */ +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = cfbstarttab[(x)&PIM]; \ + endmask = cfbendtab[((x)+(w)) & PIM]; \ + if (startmask) \ + nlw = (((w) - (PPW - ((x)&PIM))) >> PWSH); \ + else \ + nlw = (w) >> PWSH; + +#define maskpartialbits(x, w, mask) \ + mask = cfbstartpartial[(x) & PIM] & cfbendpartial[((x) + (w)) & PIM]; + +#define mask32bits(x, w, startmask, endmask) \ + startmask = cfbstarttab[(x)&PIM]; \ + endmask = cfbendtab[((x)+(w)) & PIM]; + +/* FIXME */ +#define maskbits24(x, w, startmask, endmask, nlw) \ + abort() +#define getbits24(psrc, dst, index) \ + abort() +#define putbits24(src, w, pdst, planemask, index) \ + abort() +#define putbitsrop24(src, x, pdst, planemask, rop) \ + abort() + +#endif /* PSZ == 24 && PPW == 1 */ + +#define getbits(psrc, x, w, dst) \ +if ( ((x) + (w)) <= PPW) \ +{ \ + dst = SCRLEFT(*(psrc), (x)); \ +} \ +else \ +{ \ + int m; \ + m = PPW-(x); \ + dst = (SCRLEFT(*(psrc), (x)) & cfbendtab[m]) | \ + (SCRRIGHT(*((psrc)+1), m) & cfbstarttab[m]); \ +} + + +#define putbits(src, x, w, pdst, planemask) \ +if ( ((x)+(w)) <= PPW) \ +{ \ + PixelGroup tmpmask; \ + maskpartialbits((x), (w), tmpmask); \ + tmpmask &= PFILL(planemask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (SCRRIGHT(src, x) & tmpmask); \ +} \ +else \ +{ \ + unsigned int m; \ + unsigned int n; \ + PixelGroup pm = PFILL(planemask); \ + m = PPW-(x); \ + n = (w) - m; \ + *(pdst) = (*(pdst) & (cfbendtab[x] | ~pm)) | \ + (SCRRIGHT(src, x) & (cfbstarttab[x] & pm)); \ + *((pdst)+1) = (*((pdst)+1) & (cfbstarttab[n] | ~pm)) | \ + (SCRLEFT(src, m) & (cfbendtab[n] & pm)); \ +} +#if defined(__GNUC__) && defined(mc68020) +#undef getbits +#define FASTGETBITS(psrc, x, w, dst) \ + asm ("bfextu %3{%1:%2},%0" \ + : "=d" (dst) : "di" (x), "di" (w), "o" (*(char *)(psrc))) + +#define getbits(psrc,x,w,dst) \ +{ \ + FASTGETBITS(psrc, (x) * PSZ, (w) * PSZ, dst); \ + dst = SCRLEFT(dst,PPW-(w)); \ +} + +#define FASTPUTBITS(src, x, w, pdst) \ + asm ("bfins %3,%0{%1:%2}" \ + : "=o" (*(char *)(pdst)) \ + : "di" (x), "di" (w), "d" (src), "0" (*(char *) (pdst))) + +#undef putbits +#define putbits(src, x, w, pdst, planemask) \ +{ \ + if (planemask != PMSK) { \ + PixelGroup _m, _pm; \ + FASTGETBITS(pdst, (x) * PSZ , (w) * PSZ, _m); \ + PFILL2(planemask, _pm); \ + _m &= (~_pm); \ + _m |= (SCRRIGHT(src, PPW-(w)) & _pm); \ + FASTPUTBITS(_m, (x) * PSZ, (w) * PSZ, pdst); \ + } else { \ + FASTPUTBITS(SCRRIGHT(src, PPW-(w)), (x) * PSZ, (w) * PSZ, pdst); \ + } \ +} + + +#endif /* mc68020 */ + +#define putbitsrop(src, x, w, pdst, planemask, rop) \ +if ( ((x)+(w)) <= PPW) \ +{ \ + PixelGroup tmpmask; \ + PixelGroup t1, t2; \ + maskpartialbits((x), (w), tmpmask); \ + PFILL2(planemask, t1); \ + tmpmask &= t1; \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ +} \ +else \ +{ \ + CfbBits m; \ + CfbBits n; \ + PixelGroup t1, t2; \ + PixelGroup pm; \ + PFILL2(planemask, pm); \ + m = PPW-(x); \ + n = (w) - m; \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + *(pdst) = (*(pdst) & (cfbendtab[x] | ~pm)) | (t2 & (cfbstarttab[x] & pm));\ + t1 = SCRLEFT((src), m); \ + DoRop(t2, rop, t1, *((pdst) + 1)); \ + *((pdst)+1) = (*((pdst)+1) & (cfbstarttab[n] | ~pm)) | \ + (t2 & (cfbendtab[n] & pm)); \ +} + +#else /* PSZ == 32 && PPW == 1*/ + +/* + * These macros can be optimized for 32-bit pixels since there is no + * need to worry about left/right edge masking. These macros were + * derived from the above using the following reductions: + * + * - x & PIW = 0 [since PIW = 0] + * - all masking tables are only indexed by 0 [ due to above ] + * - cfbstartab[0] and cfbendtab[0] = 0 [ no left/right edge masks] + * - cfbstartpartial[0] and cfbendpartial[0] = ~0 [no partial pixel mask] + * + * Macro reduction based upon constants cannot be performed automatically + * by the compiler since it does not know the contents of the masking + * arrays in cfbmskbits.c. + */ +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = endmask = 0; \ + nlw = (w); + +#define maskpartialbits(x, w, mask) \ + mask = 0xFFFFFFFF; + +#define mask32bits(x, w, startmask, endmask) \ + startmask = endmask = 0; + +/* + * For 32-bit operations, getbits(), putbits(), and putbitsrop() + * will only be invoked with x = 0 and w = PPW (1). The getbits() + * macro is only called within left/right edge logic, which doesn't + * happen for 32-bit pixels. + */ +#define getbits(psrc, x, w, dst) (dst) = *(psrc) + +#define putbits(src, x, w, pdst, planemask) \ + *(pdst) = (*(pdst) & ~planemask) | (src & planemask); + +#define putbitsrop(src, x, w, pdst, planemask, rop) \ +{ \ + PixelGroup t1; \ + DoRop(t1, rop, (src), *(pdst)); \ + *(pdst) = (*(pdst) & ~planemask) | (t1 & planemask); \ +} + +#endif /* PSZ != 32 */ + +/* + * Use these macros only when you're using the MergeRop stuff + * in ../mfb/mergerop.h + */ + +/* useful only when not spanning destination longwords */ +#if PSZ == 24 +#define putbitsmropshort24(src,x,w,pdst,index) {\ + PixelGroup _tmpmask; \ + PixelGroup _t1; \ + maskpartialbits ((x), (w), _tmpmask); \ + _t1 = SCRRIGHT((src), (x)); \ + DoMaskMergeRop24(_t1, pdst, _tmpmask, index); \ +} +#endif +#define putbitsmropshort(src,x,w,pdst) {\ + PixelGroup _tmpmask; \ + PixelGroup _t1; \ + maskpartialbits ((x), (w), _tmpmask); \ + _t1 = SCRRIGHT((src), (x)); \ + *pdst = DoMaskMergeRop(_t1, *pdst, _tmpmask); \ +} + +/* useful only when spanning destination longwords */ +#define putbitsmroplong(src,x,w,pdst) { \ + PixelGroup _startmask, _endmask; \ + int _m; \ + PixelGroup _t1; \ + _m = PPW - (x); \ + _startmask = cfbstarttab[x]; \ + _endmask = cfbendtab[(w) - _m]; \ + _t1 = SCRRIGHT((src), (x)); \ + pdst[0] = DoMaskMergeRop(_t1,pdst[0],_startmask); \ + _t1 = SCRLEFT ((src),_m); \ + pdst[1] = DoMaskMergeRop(_t1,pdst[1],_endmask); \ +} + +#define putbitsmrop(src,x,w,pdst) \ +if ((x) + (w) <= PPW) {\ + putbitsmropshort(src,x,w,pdst); \ +} else { \ + putbitsmroplong(src,x,w,pdst); \ +} + +#if GETLEFTBITS_ALIGNMENT == 1 +#define getleftbits(psrc, w, dst) dst = *((unsigned int *) psrc) +#define getleftbits24(psrc, w, dst, idx){ \ + regiseter int index; \ + switch(index = ((idx)&3)<<1){ \ + case 0: \ + dst = (*((unsigned int *) psrc))&cfbmask[index]; \ + break; \ + case 2: \ + case 4: \ + dst = BitLeft(((*((unsigned int *) psrc))&cfbmask[index]), cfb24Shift[index]); \ + dst |= BitRight(((*((unsigned int *) psrc)+1)&cfbmask[index]), cfb4Shift[index]); \ + break; \ + case 6: \ + dst = BitLeft((*((unsigned int *) psrc)),cfb24Shift[index]); \ + break; \ + }; \ +} +#endif /* GETLEFTBITS_ALIGNMENT == 1 */ + +#define getglyphbits(psrc, x, w, dst) \ +{ \ + dst = BitLeft((unsigned) *(psrc), (x)); \ + if ( ((x) + (w)) > 32) \ + dst |= (BitRight((unsigned) *((psrc)+1), 32-(x))); \ +} +#if GETLEFTBITS_ALIGNMENT == 2 +#define getleftbits(psrc, w, dst) \ + { \ + if ( ((int)(psrc)) & 0x01 ) \ + getglyphbits( ((unsigned int *)(((char *)(psrc))-1)), 8, (w), (dst) ); \ + else \ + dst = *((unsigned int *) psrc); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 2 */ + +#if GETLEFTBITS_ALIGNMENT == 4 +#define getleftbits(psrc, w, dst) \ + { \ + int off, off_b; \ + off_b = (off = ( ((int)(psrc)) & 0x03)) << 3; \ + getglyphbits( \ + (unsigned int *)( ((char *)(psrc)) - off), \ + (off_b), (w), (dst) \ + ); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 4 */ + +/* + * getstipplepixels( psrcstip, x, w, ones, psrcpix, destpix ) + * + * Converts bits to pixels in a reasonable way. Takes w (1 <= w <= PPW) + * bits from *psrcstip, starting at bit x; call this a quartet of bits. + * Then, takes the pixels from *psrcpix corresponding to the one-bits (if + * ones is TRUE) or the zero-bits (if ones is FALSE) of the quartet + * and puts these pixels into destpix. + * + * Example: + * + * getstipplepixels( &(0x08192A3B), 17, 4, 1, &(0x4C5D6E7F), dest ) + * + * 0x08192A3B = 0000 1000 0001 1001 0010 1010 0011 1011 + * + * This will take 4 bits starting at bit 17, so the quartet is 0x5 = 0101. + * It will take pixels from 0x4C5D6E7F corresponding to the one-bits in this + * quartet, so dest = 0x005D007F. + * + * XXX Works with both byte order. + * XXX This works for all values of x and w within a doubleword. + */ +#if (BITMAP_BIT_ORDER == MSBFirst) +#define getstipplepixels( psrcstip, x, w, ones, psrcpix, destpix ) \ +{ \ + PixelGroup q; \ + int m; \ + if ((m = ((x) - ((PPW*PSZ)-PPW))) > 0) { \ + q = (*(psrcstip)) << m; \ + if ( (x)+(w) > (PPW*PSZ) ) \ + q |= *((psrcstip)+1) >> ((PPW*PSZ)-m); \ + } \ + else \ + q = (*(psrcstip)) >> -m; \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +/* I just copied this to get the linker satisfied on PowerPC, + * so this may not be correct at all. + */ +#define getstipplepixels24(psrcstip,xt,ones,psrcpix,destpix,stipindex) \ +{ \ + PixelGroup q; \ + q = *(psrcstip) >> (xt); \ + q = ((ones) ? q : ~q) & 1; \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +#else /* BITMAP_BIT_ORDER == LSB */ + +/* this must load 32 bits worth; for most machines, thats an int */ +#define CfbFetchUnaligned(x) ldl_u(x) + +#define getstipplepixels( psrcstip, xt, w, ones, psrcpix, destpix ) \ +{ \ + PixelGroup q; \ + q = CfbFetchUnaligned(psrcstip) >> (xt); \ + if ( ((xt)+(w)) > (PPW*PSZ) ) \ + q |= (CfbFetchUnaligned((psrcstip)+1)) << ((PPW*PSZ)-(xt)); \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +#if PSZ == 24 +# if 0 +#define getstipplepixels24(psrcstip,xt,w,ones,psrcpix,destpix,stipindex,srcindex,dstindex) \ +{ \ + PixelGroup q; \ + CfbBits src; \ + register unsigned int sidx; \ + register unsigned int didx; \ + sidx = ((srcindex) & 3)<<1; \ + didx = ((dstindex) & 3)<<1; \ + q = *(psrcstip) >> (xt); \ +/* if((srcindex)!=0)*/ \ +/* src = (((*(psrcpix)) << cfb24Shift[sidx]) & (cfbmask[sidx])) |*/ \ +/* (((*((psrcpix)+1)) << cfb24Shift[sidx+1]) & (cfbmask[sidx+1])); */\ +/* else */\ + src = (*(psrcpix))&0xFFFFFF; \ + if ( ((xt)+(w)) > PGSZ ) \ + q |= (*((psrcstip)+1)) << (PGSZ -(xt)); \ + q = QuartetBitsTable[(w)] & ((ones) ? q : ~q); \ + src &= QuartetPixelMaskTable[q]; \ + *(destpix) &= cfbrmask[didx]; \ + switch(didx) {\ + case 0: \ + *(destpix) |= (src &cfbmask[didx]); \ + break; \ + case 2: \ + case 4: \ + destpix++;didx++; \ + *(destpix) = ((*(destpix)) & (cfbrmask[didx]))| \ + (BitLeft(src, cfb24Shift[didx]) & (cfbmask[didx])); \ + destpix--; didx--;\ + case 6: \ + *(destpix) |= (BitRight(src, cfb24Shift[didx]) & cfbmask[didx]); \ + break; \ + }; \ +} +# else +#define getstipplepixels24(psrcstip,xt,ones,psrcpix,destpix,stipindex) \ +{ \ + PixelGroup q; \ + q = *(psrcstip) >> (xt); \ + q = ((ones) ? q : ~q) & 1; \ + *(destpix) = (*(psrcpix)) & QuartetPixelMaskTable[q]; \ +} +# endif +#endif /* PSZ == 24 */ +#endif + +extern PixelGroup cfbstarttab[]; +extern PixelGroup cfbendtab[]; +extern PixelGroup cfbstartpartial[]; +extern PixelGroup cfbendpartial[]; +extern PixelGroup cfbrmask[]; +extern PixelGroup cfbmask[]; +extern PixelGroup QuartetBitsTable[]; +extern PixelGroup QuartetPixelMaskTable[]; +#if PSZ == 24 +extern int cfb24Shift[]; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbrrop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbrrop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbrrop.h (revision 51223) @@ -0,0 +1,344 @@ +/* + * $Xorg: cfbrrop.h,v 1.4 2001/02/09 02:04:38 xorgcvs Exp $ + * +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ + +/* $XFree86: xc/programs/Xserver/cfb/cfbrrop.h,v 3.10tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GXcopy +#include +#endif + +#define RROP_FETCH_GC(gc) \ + RROP_FETCH_GCPRIV(((cfbPrivGCPtr)(gc)->devPrivates[cfbGCPrivateIndex].ptr)) + +#ifndef RROP +#define RROP GXset +#endif + +#if RROP == GXcopy +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_xor; \ + CfbBits piQxelXor[3], spiQxelXor[8]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[2] = rrop_xor << 24; \ + spiQxelXor[3] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[4] = rrop_xor << 16; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelXor[6] = rrop_xor << 8; \ + spiQxelXor[1] = spiQxelXor[7] = 0; \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) = (*(dst) & cfbrmask[idx])|spiQxelXor[idx]; \ + if (idx == 2 || idx == 4){ \ + idx++; \ + *((dst)+1) = (*((dst)+1) & cfbrmask[idx])|spiQxelXor[idx]; \ + } \ + } +#define RROP_SOLID(dst, idx) \ + (*(dst) = piQxelXor[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) = (*(dst) & ~(mask))|(piQxelXor[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelXor; (void)spiQxelXor; +#else +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; +#define RROP_DECLARE register CfbBits rrop_xor; +#define RROP_SOLID(dst) (*(dst) = (rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) = (*(dst) & ~(mask)) | ((rrop_xor) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Copy) +#endif /* GXcopy */ + +#if RROP == GXxor +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_xor; \ + CfbBits piQxelXor[3], spiQxelXor[8]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[2] = rrop_xor << 24; \ + spiQxelXor[3] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[4] = rrop_xor << 16; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelXor[6] = rrop_xor << 8; \ + spiQxelXor[1] = spiQxelXor[7] = 0; \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) ^= spiQxelXor[idx]; \ + if (idx == 2 || idx == 4) \ + *((dst)+1) ^= spiQxelXor[idx+1]; \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) ^= piQxelXor[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) ^= (piQxelXor[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelXor; (void)spiQxelXor; +#else +#define RROP_DECLARE register CfbBits rrop_xor; +#define RROP_FETCH_GCPRIV(devPriv) rrop_xor = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) ^= (rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) ^= ((rrop_xor) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Xor) +#endif /* GXxor */ + +#if RROP == GXand +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_and; \ + CfbBits piQxelAnd[3], spiQxelAnd[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + spiQxelAnd[0] = (rrop_and & 0xFFFFFF) | 0xFF000000; \ + spiQxelAnd[2] = (rrop_and << 24) | 0xFFFFFF; \ + spiQxelAnd[3] = ((rrop_and & 0xFFFF00)>> 8) | 0xFFFF0000; \ + spiQxelAnd[4] = (rrop_and << 16) | 0xFFFF; \ + spiQxelAnd[5] = ((rrop_and & 0xFF0000)>> 16) | 0xFFFFFF00; \ + spiQxelAnd[1] = (rrop_and << 8) | 0xFF; \ + piQxelAnd[0] = (rrop_and & 0xFFFFFF)|(rrop_and << 24); \ + piQxelAnd[1] = (rrop_and << 16)|((rrop_and & 0xFFFF00)>> 8); \ + piQxelAnd[2] = (rrop_and << 8)|((rrop_and & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) &= spiQxelAnd[0]; \ + break; \ + case 3: \ + *(dst) &= spiQxelAnd[1]; \ + break; \ + case 1: \ + *(dst) &= spiQxelAnd[2]; \ + *((dst)+1) &= spiQxelAnd[3]; \ + break; \ + case 2: \ + *(dst) &= spiQxelAnd[4]; \ + *((dst)+1) &= spiQxelAnd[5]; \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) &= piQxelAnd[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) &= (piQxelAnd[(idx)] | ~(mask))) +#define RROP_UNDECLARE (void)piQxelAnd; (void)spiQxelAnd; +#else +#define RROP_DECLARE register CfbBits rrop_and; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; +#define RROP_SOLID(dst) (*(dst) &= (rrop_and)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) &= ((rrop_and) | ~(mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,And) +#endif /* GXand */ + +#if RROP == GXor +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_or; \ + CfbBits piQxelOr[3], spiQxelOr[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_or = (devPriv)->xor; \ + spiQxelOr[0] = rrop_or & 0xFFFFFF; \ + spiQxelOr[1] = rrop_or << 24; \ + spiQxelOr[2] = rrop_or << 16; \ + spiQxelOr[3] = rrop_or << 8; \ + spiQxelOr[4] = (rrop_or & 0xFFFF00)>> 8; \ + spiQxelOr[5] = (rrop_or & 0xFF0000)>> 16; \ + piQxelOr[0] = (rrop_or & 0xFFFFFF)|(rrop_or << 24); \ + piQxelOr[1] = (rrop_or << 16)|((rrop_or & 0xFFFF00)>> 8); \ + piQxelOr[2] = (rrop_or << 8)|((rrop_or & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) |= spiQxelOr[0]; \ + break; \ + case 3: \ + *(dst) |= spiQxelOr[3]; \ + break; \ + case 1: \ + *(dst) |= spiQxelOr[1]; \ + *((dst)+1) |= spiQxelOr[4]; \ + break; \ + case 2: \ + *(dst) |= spiQxelOr[2]; \ + *((dst)+1) |= spiQxelOr[5]; \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) |= piQxelOr[(idx)]) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) |= (piQxelOr[(idx)] & (mask))) +#define RROP_UNDECLARE (void)piQxelOr; (void)spiQxelOr; +#else +#define RROP_DECLARE register CfbBits rrop_or; +#define RROP_FETCH_GCPRIV(devPriv) rrop_or = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) |= (rrop_or)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) |= ((rrop_or) & (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Or) +#endif /* GXor */ + +#if RROP == GXnoop +#define RROP_DECLARE +#define RROP_FETCH_GCPRIV(devPriv) +#define RROP_SOLID(dst) +#define RROP_SOLID_MASK(dst,mask) +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,Noop) +#define RROP_UNDECLARE +#endif /* GXnoop */ + +#if RROP == GXset +#if PSZ == 24 +#define RROP_DECLARE register CfbBits rrop_and, rrop_xor; \ + CfbBits piQxelAnd[3], piQxelXor[3], spiQxelAnd[6], spiQxelXor[6]; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + rrop_xor = (devPriv)->xor; \ + spiQxelXor[0] = rrop_xor & 0xFFFFFF; \ + spiQxelXor[1] = rrop_xor << 24; \ + spiQxelXor[2] = rrop_xor << 16; \ + spiQxelXor[3] = rrop_xor << 8; \ + spiQxelXor[4] = (rrop_xor & 0xFFFF00)>> 8; \ + spiQxelXor[5] = (rrop_xor & 0xFF0000)>> 16; \ + spiQxelAnd[0] = (rrop_and & 0xFFFFFF) | 0xFF000000; \ + spiQxelAnd[1] = (rrop_and << 24) | 0xFFFFFF; \ + spiQxelAnd[2] = (rrop_and << 16) | 0xFFFF; \ + spiQxelAnd[3] = (rrop_and << 8) | 0xFF; \ + spiQxelAnd[4] = ((rrop_and & 0xFFFF00)>> 8) | 0xFFFF0000; \ + spiQxelAnd[5] = ((rrop_and & 0xFF0000)>> 16) | 0xFFFFFF00; \ + piQxelAnd[0] = (rrop_and & 0xFFFFFF)|(rrop_and << 24); \ + piQxelAnd[1] = (rrop_and << 16)|((rrop_and & 0xFFFF00)>> 8); \ + piQxelAnd[2] = (rrop_and << 8)|((rrop_and & 0xFF0000)>> 16); \ + piQxelXor[0] = (rrop_xor & 0xFFFFFF)|(rrop_xor << 24); \ + piQxelXor[1] = (rrop_xor << 16)|((rrop_xor & 0xFFFF00)>> 8); \ + piQxelXor[2] = (rrop_xor << 8)|((rrop_xor & 0xFF0000)>> 16); +#define RROP_SOLID24(dst,index) {\ + switch((index) & 3){ \ + case 0: \ + *(dst) = ((*(dst) & (piQxelAnd[0] |0xFF000000))^(piQxelXor[0] & 0xFFFFFF)); \ + break; \ + case 3: \ + *(dst) = ((*(dst) & (piQxelAnd[2]|0xFF))^(piQxelXor[2] & 0xFFFFFF00)); \ + break; \ + case 1: \ + *(dst) = ((*(dst) & (piQxelAnd[0]|0xFFFFFF))^(piQxelXor[0] & 0xFF000000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[1]|0xFFFF0000))^(piQxelXor[1] & 0xFFFF)); \ + break; \ + case 2: \ + *(dst) = ((*(dst) & (piQxelAnd[1]|0xFFFF))^(piQxelXor[1] & 0xFFFF0000)); \ + *((dst)+1) = ((*((dst)+1) & (piQxelAnd[2]|0xFFFFFF00))^(piQxelXor[2] & 0xFF)); \ + break; \ + } \ + } +#define RROP_SOLID(dst,idx) \ + (*(dst) = DoRRop (*(dst), piQxelAnd[(idx)], piQxelXor[(idx)])) +#define RROP_SOLID_MASK(dst,mask,idx) \ + (*(dst) = DoMaskRRop (*(dst), piQxelAnd[(idx)], piQxelXor[(idx)], (mask))) +#define RROP_UNDECLARE (void)piQxelAnd; (void)piQxelXor; \ + (void)spiQxelAnd; (void)spiQxelXor; +#else +#define RROP_DECLARE register CfbBits rrop_and, rrop_xor; +#define RROP_FETCH_GCPRIV(devPriv) rrop_and = (devPriv)->and; \ + rrop_xor = (devPriv)->xor; +#define RROP_SOLID(dst) (*(dst) = DoRRop (*(dst), rrop_and, rrop_xor)) +#define RROP_SOLID_MASK(dst,mask) (*(dst) = DoMaskRRop (*(dst), rrop_and, rrop_xor, (mask))) +#define RROP_UNDECLARE +#endif +#define RROP_NAME(prefix) RROP_NAME_CAT(prefix,General) +#endif /* GXset */ + +#define RROP_UNROLL_CASE1(p,i) case (i): RROP_SOLID((p) - (i)); +#define RROP_UNROLL_CASE2(p,i) RROP_UNROLL_CASE1(p,(i)+1) RROP_UNROLL_CASE1(p,i) +#define RROP_UNROLL_CASE4(p,i) RROP_UNROLL_CASE2(p,(i)+2) RROP_UNROLL_CASE2(p,i) +#define RROP_UNROLL_CASE8(p,i) RROP_UNROLL_CASE4(p,(i)+4) RROP_UNROLL_CASE4(p,i) +#define RROP_UNROLL_CASE16(p,i) RROP_UNROLL_CASE8(p,(i)+8) RROP_UNROLL_CASE8(p,i) +#define RROP_UNROLL_CASE32(p,i) RROP_UNROLL_CASE16(p,(i)+16) RROP_UNROLL_CASE16(p,i) +#define RROP_UNROLL_CASE3(p) RROP_UNROLL_CASE2(p,2) RROP_UNROLL_CASE1(p,1) +#define RROP_UNROLL_CASE7(p) RROP_UNROLL_CASE4(p,4) RROP_UNROLL_CASE3(p) +#define RROP_UNROLL_CASE15(p) RROP_UNROLL_CASE8(p,8) RROP_UNROLL_CASE7(p) +#define RROP_UNROLL_CASE31(p) RROP_UNROLL_CASE16(p,16) RROP_UNROLL_CASE15(p) +#ifdef LONG64 +#define RROP_UNROLL_CASE63(p) RROP_UNROLL_CASE32(p,32) RROP_UNROLL_CASE31(p) +#endif /* LONG64 */ + +#define RROP_UNROLL_LOOP1(p,i) RROP_SOLID((p) + (i)); +#define RROP_UNROLL_LOOP2(p,i) RROP_UNROLL_LOOP1(p,(i)) RROP_UNROLL_LOOP1(p,(i)+1) +#define RROP_UNROLL_LOOP4(p,i) RROP_UNROLL_LOOP2(p,(i)) RROP_UNROLL_LOOP2(p,(i)+2) +#define RROP_UNROLL_LOOP8(p,i) RROP_UNROLL_LOOP4(p,(i)) RROP_UNROLL_LOOP4(p,(i)+4) +#define RROP_UNROLL_LOOP16(p,i) RROP_UNROLL_LOOP8(p,(i)) RROP_UNROLL_LOOP8(p,(i)+8) +#define RROP_UNROLL_LOOP32(p,i) RROP_UNROLL_LOOP16(p,(i)) RROP_UNROLL_LOOP16(p,(i)+16) +#ifdef LONG64 +#define RROP_UNROLL_LOOP64(p,i) RROP_UNROLL_LOOP32(p,(i)) RROP_UNROLL_LOOP32(p,(i)+32) +#endif /* LONG64 */ + +#if defined (FAST_CONSTANT_OFFSET_MODE) && defined (SHARED_IDCACHE) && (RROP == GXcopy) + +#ifdef LONG64 +#define RROP_UNROLL_SHIFT 6 +#define RROP_UNROLL_CASE(p) RROP_UNROLL_CASE63(p) +#define RROP_UNROLL_LOOP(p) RROP_UNROLL_LOOP64(p,-64) +#else /* not LONG64 */ +#define RROP_UNROLL_SHIFT 5 +#define RROP_UNROLL_CASE(p) RROP_UNROLL_CASE31(p) +#define RROP_UNROLL_LOOP(p) RROP_UNROLL_LOOP32(p,-32) +#endif /* LONG64 */ +#define RROP_UNROLL (1<>= RROP_UNROLL_SHIFT; \ + (pdst) += part * (sizeof (CfbBits) / sizeof (*pdst)); \ + switch (part) {\ + RROP_UNROLL_CASE((CfbBits *) (pdst)) \ + } \ + while (--(nmiddle) >= 0) { \ + (pdst) += RROP_UNROLL * (sizeof (CfbBits) / sizeof (*pdst)); \ + RROP_UNROLL_LOOP((CfbBits *) (pdst)) \ + } \ +} +#else +#define RROP_SPAN(pdst,nmiddle) \ + while (--(nmiddle) >= 0) { \ + RROP_SOLID((CfbBits *) (pdst)); \ + (pdst) += sizeof (CfbBits) / sizeof (*pdst); \ + } +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define RROP_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define RROP_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbtab.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbtab.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbtab.h (revision 51223) @@ -0,0 +1,16 @@ +/* $XFree86$ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _CFBTAB_H_ +#define _CFBTAB_H_ + +/* prototypes */ +#if 0 +extern int starttab[32], endtab[32]; +extern unsigned int partmasks[32][32]; +#endif + +#endif /* _CFBTAB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbunmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbunmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cfbunmap.h (revision 51223) @@ -0,0 +1,165 @@ +/* $XFree86: xc/programs/Xserver/cfb/cfbunmap.h,v 1.6 2003/07/19 13:22:28 tsi Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +/* + * Unmap names + */ + +#undef CFBNAME +#undef CATNAME + +#undef QuartetBitsTable +#undef QuartetPixelMaskTable +#undef cfb8ClippedLineCopy +#undef cfb8ClippedLineGeneral +#undef cfb8ClippedLineXor +#undef cfb8LineSS1Rect +#undef cfb8LineSS1RectCopy +#undef cfb8LineSS1RectGeneral +#undef cfb8LineSS1RectPreviousCopy +#undef cfb8LineSS1RectXor +#undef cfb8SegmentSS1Rect +#undef cfb8SegmentSS1RectCopy +#undef cfb8SegmentSS1RectGeneral +#undef cfb8SegmentSS1RectShiftCopy +#undef cfb8SegmentSS1RectXor +#undef cfbAllocatePrivates +#undef cfbBSFuncRec +#undef cfbBitBlt +#undef cfbBresD +#undef cfbBresS +#undef cfbChangeWindowAttributes +#undef cfbClearVisualTypes +#undef cfbCloseScreen +#undef cfbCreateDefColormap +#undef cfbCopyArea +#undef cfbCopyImagePlane +#undef cfbCopyPixmap +#undef cfbCopyPlane +#undef cfbCopyPlaneReduce +#undef cfbCopyRotatePixmap +#undef cfbCopyWindow +#undef cfbCreateGC +#undef cfbCreatePixmap +#undef cfbCreateScreenResources +#undef cfbCreateWindow +#undef cfbDestroyPixmap +#undef cfbDestroyWindow +#undef cfbDoBitblt +#undef cfbDoBitbltCopy +#undef cfbDoBitbltGeneral +#undef cfbDoBitbltOr +#undef cfbDoBitbltXor +#undef cfbExpandDirectColors +#undef cfbFillBoxSolid +#undef cfbFillBoxTile32 +#undef cfbFillBoxTile32sCopy +#undef cfbFillBoxTile32sGeneral +#undef cfbFillBoxTileOdd +#undef cfbFillBoxTileOddCopy +#undef cfbFillBoxTileOddGeneral +#undef cfbFillPoly1RectCopy +#undef cfbFillPoly1RectGeneral +#undef cfbFillRectSolidCopy +#undef cfbFillRectSolidGeneral +#undef cfbFillRectSolidXor +#undef cfbFillRectTile32Copy +#undef cfbFillRectTile32General +#undef cfbFillRectTileOdd +#undef cfbFillSpanTile32sCopy +#undef cfbFillSpanTile32sGeneral +#undef cfbFillSpanTileOddCopy +#undef cfbFillSpanTileOddGeneral +#undef cfbFinishScreenInit +#undef cfbGCFuncs +#undef cfbGCPrivateIndex +#undef cfbGetImage +#undef cfbGetScreenPixmap +#undef cfbGetSpans +#undef cfbHorzS +#undef cfbImageGlyphBlt8 +#undef cfbInitializeColormap +#undef cfbInitVisuals +#undef cfbInstallColormap +#undef cfbLineSD +#undef cfbLineSS +#undef cfbListInstalledColormaps +#undef cfbMapWindow +#undef cfbMatchCommon +#undef cfbNonTEOps +#undef cfbNonTEOps1Rect +#undef cfbPadPixmap +#undef cfbPaintWindow +#undef cfbPolyFillArcSolidCopy +#undef cfbPolyFillArcSolidGeneral +#undef cfbPolyFillRect +#undef cfbPolyGlyphBlt8 +#undef cfbPolyGlyphRop8 +#undef cfbPolyPoint +#undef cfbPositionWindow +#undef cfbPutImage +#undef cfbReduceRasterOp +#undef cfbResolveColor +#undef cfbRestoreAreas +#undef cfbSaveAreas +#undef cfbScreenInit +#undef cfbScreenPrivateIndex +#undef cfbSegmentSD +#undef cfbSegmentSS +#undef cfbSetScanline +#undef cfbSetScreenPixmap +#undef cfbSetSpans +#undef cfbSetVisualTypes +#undef cfbSetupScreen +#undef cfbSolidSpansCopy +#undef cfbSolidSpansGeneral +#undef cfbSolidSpansXor +#undef cfbStippleStack +#undef cfbStippleStackTE +#undef cfbTEGlyphBlt +#undef cfbTEOps +#undef cfbTEOps1Rect +#undef cfbTile32FSCopy +#undef cfbTile32FSGeneral +#undef cfbUninstallColormap +#undef cfbUnmapWindow +#undef cfbUnnaturalStippleFS +#undef cfbUnnaturalTileFS +#undef cfbValidateGC +#undef cfbVertS +#undef cfbWindowPrivateIndex +#undef cfbXRotatePixmap +#undef cfbYRotatePixmap +#undef cfbZeroPolyArcSS8Copy +#undef cfbZeroPolyArcSS8General +#undef cfbZeroPolyArcSS8Xor +#undef cfbendpartial +#undef cfbendtab +#undef cfbmask +#undef cfbrmask +#undef cfbstartpartial +#undef cfbstarttab Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgdctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgdctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgdctl.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGDCTL_H +#define CHGDCTL_H 1 + +int SProcXChangeDeviceControl(ClientPtr /* client */ + ); + +int ProcXChangeDeviceControl(ClientPtr /* client */ + ); + +void SRepXChangeDeviceControl(ClientPtr /* client */ , + int /* size */ , + xChangeDeviceControlReply * /* rep */ + ); + +#endif /* CHGDCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgfctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgfctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgfctl.h (revision 51223) @@ -0,0 +1,81 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGFCTL_H +#define CHGFCTL_H 1 + +int SProcXChangeFeedbackControl(ClientPtr /* client */ + ); + +int ProcXChangeFeedbackControl(ClientPtr /* client */ + ); + +int ChangeKbdFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + KbdFeedbackPtr /* k */ , + xKbdFeedbackCtl * /* f */ + ); + +int ChangePtrFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + PtrFeedbackPtr /* p */ , + xPtrFeedbackCtl * /* f */ + ); + +int ChangeIntegerFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + IntegerFeedbackPtr /* i */ , + xIntegerFeedbackCtl * /* f */ + ); + +int ChangeStringFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + StringFeedbackPtr /* s */ , + xStringFeedbackCtl * /* f */ + ); + +int ChangeBellFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + BellFeedbackPtr /* b */ , + xBellFeedbackCtl * /* f */ + ); + +int ChangeLedFeedback(ClientPtr /* client */ , + DeviceIntPtr /* dev */ , + unsigned long /* mask */ , + LedFeedbackPtr /* l */ , + xLedFeedbackCtl * /* f */ + ); + +#endif /* CHGFCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkbd.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGKBD_H +#define CHGKBD_H 1 + +int SProcXChangeKeyboardDevice(ClientPtr /* client */ + ); + +int ProcXChangeKeyboardDevice(ClientPtr /* client */ + ); + +void SRepXChangeKeyboardDevice(ClientPtr /* client */ , + int /* size */ , + xChangeKeyboardDeviceReply * /* rep */ + ); + +#endif /* CHGKBD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgkmap.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGKMAP_H +#define CHGKMAP_H 1 + +int SProcXChangeDeviceKeyMapping(ClientPtr /* client */ + ); + +int ProcXChangeDeviceKeyMapping(ClientPtr /* client */ + ); + +#endif /* CHGKMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgprop.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGPROP_H +#define CHGPROP_H 1 + +int SProcXChangeDeviceDontPropagateList(ClientPtr /* client */ + ); + +int ProcXChangeDeviceDontPropagateList(ClientPtr /* client */ + ); + +#endif /* CHGPROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgptr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgptr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/chgptr.h (revision 51223) @@ -0,0 +1,61 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CHGPTR_H +#define CHGPTR_H 1 + +int SProcXChangePointerDevice(ClientPtr /* client */ + ); + +int ProcXChangePointerDevice(ClientPtr /* client */ + ); + +void DeleteFocusClassDeviceStruct(DeviceIntPtr /* dev */ + ); + +void SendEventToAllWindows(DeviceIntPtr /* dev */ , + Mask /* mask */ , + xEvent * /* ev */ , + int /* count */ + ); + +void FindInterestedChildren( /* FIXME: could be static? */ + DeviceIntPtr /* dev */ , + WindowPtr /* p1 */ , + Mask /* mask */ , + xEvent * /* ev */ , + int /* count */ + ); + +void SRepXChangePointerDevice(ClientPtr /* client */ , + int /* size */ , + xChangePointerDeviceReply * /* rep */ + ); + +#endif /* CHGPTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closedev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closedev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closedev.h (revision 51223) @@ -0,0 +1,49 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef CLOSEDEV_H +#define CLOSEDEV_H 1 + +int SProcXCloseDevice(ClientPtr /* client */ + ); + +int ProcXCloseDevice(ClientPtr /* client */ + ); + +void DeleteEventsFromChildren(DeviceIntPtr /* dev */ , + WindowPtr /* p1 */ , + ClientPtr /* client */ + ); + +void DeleteDeviceEvents(DeviceIntPtr /* dev */ , + WindowPtr /* pWin */ , + ClientPtr /* client */ + ); + +#endif /* CLOSEDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closestr.h (revision 51223) @@ -0,0 +1,159 @@ +/* $Xorg: closestr.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ +/* + +Copyright 1991, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/include/closestr.h,v 3.4 2001/12/14 19:59:53 dawes Exp $ */ + + +#ifndef CLOSESTR_H +#define CLOSESTR_H + +#define NEED_REPLIES +#include +#include "closure.h" +#include "dix.h" +#include "misc.h" +#include "gcstruct.h" + +/* closure structures */ + +/* OpenFont */ + +typedef struct _OFclosure { + ClientPtr client; + short current_fpe; + short num_fpes; + FontPathElementPtr *fpe_list; + Mask flags; + Bool slept; + +/* XXX -- get these from request buffer instead? */ + char *origFontName; + int origFontNameLen; + XID fontid; + char *fontname; + int fnamelen; + FontPtr non_cachable_font; +} OFclosureRec; + +/* ListFontsWithInfo */ + +#define XLFDMAXFONTNAMELEN 256 +typedef struct _LFWIstate { + char pattern[XLFDMAXFONTNAMELEN]; + int patlen; + int current_fpe; + int max_names; + Bool list_started; + pointer private; +} LFWIstateRec, *LFWIstatePtr; + +typedef struct _LFWIclosure { + ClientPtr client; + int num_fpes; + FontPathElementPtr *fpe_list; + xListFontsWithInfoReply *reply; + int length; + LFWIstateRec current; + LFWIstateRec saved; + int savedNumFonts; + Bool haveSaved; + Bool slept; + char *savedName; +} LFWIclosureRec; + +/* ListFonts */ + +typedef struct _LFclosure { + ClientPtr client; + int num_fpes; + FontPathElementPtr *fpe_list; + FontNamesPtr names; + LFWIstateRec current; + LFWIstateRec saved; + Bool haveSaved; + Bool slept; + char *savedName; + int savedNameLen; +} LFclosureRec; + +/* PolyText */ + +typedef + int (* PolyTextPtr)( + DrawablePtr /* pDraw */, + GCPtr /* pGC */, + int /* x */, + int /* y */, + int /* count */, + void * /* chars or shorts */ + ); + +typedef struct _PTclosure { + ClientPtr client; + DrawablePtr pDraw; + GC *pGC; + unsigned char *pElt; + unsigned char *endReq; + unsigned char *data; + int xorg; + int yorg; + CARD8 reqType; + PolyTextPtr polyText; + int itemSize; + XID did; + int err; + Bool slept; +} PTclosureRec; + +/* ImageText */ + +typedef + void (* ImageTextPtr)( + DrawablePtr /* pDraw */, + GCPtr /* pGC */, + int /* x */, + int /* y */, + int /* count */, + void * /* chars or shorts */ + ); + +typedef struct _ITclosure { + ClientPtr client; + DrawablePtr pDraw; + GC *pGC; + BYTE nChars; + unsigned char *data; + int xorg; + int yorg; + CARD8 reqType; + ImageTextPtr imageText; + int itemSize; + XID did; + Bool slept; +} ITclosureRec; +#endif /* CLOSESTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closure.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closure.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/closure.h (revision 51223) @@ -0,0 +1,58 @@ +/* $Xorg: closure.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef CLOSURE_H +#define CLOSURE_H 1 + +typedef struct _LFclosure *LFclosurePtr; +typedef struct _LFWIclosure *LFWIclosurePtr; +typedef struct _OFclosure *OFclosurePtr; +typedef struct _PTclosure *PTclosurePtr; +typedef struct _ITclosure *ITclosurePtr; + +#endif /* CLOSURE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coff.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coff.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coff.h (revision 51223) @@ -0,0 +1,237 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/coff.h,v 1.5 1998/07/25 16:56:12 dawes Exp $ */ + +/* This file was implemented from the information in the book + Understanding and Using COFF + Gintaras R. Gircys + O'Reilly, 1988 + and by looking at the Linux kernel code. + + It is therefore most likely free to use... + + If the file format changes in the COFF object, this file should be + subsequently updated to reflect the changes. + + The actual loader module only uses a few of the COFF structures. + Only those are included here. If you wish more information about + COFF, thein check out the book mentioned above. +*/ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _COFF_H +#define _COFF_H + +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ +/* + * Intel 386/486 + */ + +/* + * FILE HEADER + */ + +typedef struct COFF_filehdr { + unsigned short f_magic; /* magic number */ + unsigned short f_nscns; /* number of sections */ + long f_timdat; /* time & date stamp */ + long f_symptr; /* file pointer to symtab */ + long f_nsyms; /* number of symtab entries */ + unsigned short f_opthdr; /* sizeof(optional hdr) */ + unsigned short f_flags; /* flags */ +} FILHDR; + +#define FILHSZ sizeof(FILHDR) + +/* + * SECTION HEADER + */ + +typedef struct COFF_scnhdr { + char s_name[8]; /* section name */ + long s_paddr; /* physical address */ + long s_vaddr; /* virtual address */ + long s_size; /* section size */ + long s_scnptr; /* raw data for section */ + long s_relptr; /* relocation */ + long s_lnnoptr; /* line numbers */ + unsigned short s_nreloc; /* number of relocation entries */ + unsigned short s_nlnno; /* number of line number entries */ + long s_flags; /* flags */ +} SCNHDR; + +#define COFF_SCNHDR struct COFF_scnhdr +#define COFF_SCNHSZ sizeof(COFF_SCNHDR) +#define SCNHSZ COFF_SCNHSZ + +/* + * the optional COFF header as used by Linux COFF + */ + +typedef struct { + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes */ + char dsize[4]; /* initialized data */ + char bsize[4]; /* uninitialized data */ + char entry[4]; /* entry point */ + char text_start[4]; /* base of text */ + char data_start[4]; /* base of data */ +} AOUTHDR; + +/* + * SYMBOLS + */ + +typedef struct COFF_syment { + union { + char _n_name[E_SYMNMLEN]; /* Symbol name (first 8 chars) */ + struct { + long _n_zeroes; /* Leading zeros */ + long _n_offset; /* Offset for a header section */ + } _n_n; + char *_n_nptr[2]; /* allows for overlaying */ + } _n; + + long n_value; /* address of the segment */ + short n_scnum; /* Section number */ + unsigned short n_type; /* Type of section */ + char n_sclass; /* Loader class */ + char n_numaux; /* Number of aux entries following */ +} SYMENT; + +#define n_name _n._n_name +#define n_nptr _n._n_nptr[1] +#define n_zeroes _n._n_n._n_zeroes +#define n_offset _n._n_n._n_offset + +#define COFF_E_SYMNMLEN 8 /* characters in a short symbol name */ +#define COFF_E_FILNMLEN 14 /* characters in a file name */ +#define COFF_E_DIMNUM 4 /* array dimensions in aux entry */ +#define SYMNMLEN COFF_E_SYMNMLEN +#define SYMESZ 18 /* not really sizeof(SYMENT) due to padding */ + +/* Special section number found in the symbol section */ +#define N_UNDEF 0 +#define N_ABS -1 +#define N_DEBUG -2 + +/* Symbol storage class values */ +#define C_NULL 0 +#define C_EXT 2 +#define C_FILE 103 +#define C_HIDEXT 107 + +/* + * AUX Entries + */ +typedef struct COFF_auxent { + long x_scnlen; + long x_parmhash; + unsigned short x_snhash; + unsigned char x_smtyp; + unsigned char x_smclas; + long x_stab; + unsigned short x_snstab; +} AUXENT; + +/* Auxillary Symbol type values */ +#define XTY_ER 0 /* Enternal Reference */ +#define XTY_SD 1 /* csect section definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* common csect definition */ + +/* Auxillary Symbol storage mapping class values */ +#define XMC_PR 0 /* Program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Debug dictionary */ +#define XMC_TC 3 /* TOC entry */ +#define XMC_UA 4 /* Unclassified */ +#define XMC_RW 5 /* Read/write data */ +#define XMC_GL 6 /* Global linkage */ +#define XMC_XO 7 /* Extended operation */ +#define XMC_SV 8 /* Supervisor call descriptor */ +#define XMC_BS 9 /* BSS class */ +#define XMC_DS 10 /* Function descriptor csect */ +#define XMC_UC 11 /* Unnamed FORTRAN comon */ +#define XMC_TI 12 /* Reserved */ +#define XMC_TB 13 /* Reserved */ +#define XMC_TC0 15 /* TOC anchor */ +#define XMC_TD 16 /* Scalar data entry in TOC */ + +/* + * RELOCATION DIRECTIVES + */ + +typedef struct COFF_reloc { + long r_vaddr; /* Virtual address of item */ + long r_symndx; /* Symbol index in the symtab */ +#if defined(__powerpc__) + union { + unsigned short _r_type; /* old style coff relocation type */ + struct { + char _r_rsize; /* sign and reloc bit len */ + char _r_rtype; /* toc relocation type */ + } _r_r; + } _r; +#define r_otype _r._r_type /* old style reloc - original name */ +#define r_rsize _r._r_r._r_rsize /* extract sign and bit len */ +#define r_type _r._r_r._r_rtype /* extract toc relocation type */ +#else + unsigned short r_type; /* Relocation type */ +#endif +} RELOC; + +#define COFF_RELOC struct COFF_reloc +#define COFF_RELSZ 10 +#define RELSZ COFF_RELSZ + +/* + * x86 Relocation types + */ +#define R_ABS 000 +#define R_DIR32 006 +#define R_PCRLONG 024 + +#if defined(__powerpc__) +/* + * Power PC + */ +#define R_LEN 0x1F /* extract bit-length field */ +#define R_SIGN 0x80 /* extract sign of relocation */ +#define R_FIXUP 0x40 /* extract code-fixup bit */ + +#define RELOC_RLEN(x) ((x)._r._r_r._r_rsize & R_LEN) +#define RELOC_RSIGN(x) ((x)._r._r_r._r_rsize & R_SIGN) +#define RELOC_RFIXUP(x) ((x)._r._r_r._r_rsize & R_FIXUP) +#define RELOC_RTYPE(x) ((x)._r._r_r._r_rtype) + +/* + * POWER and PowerPC - relocation types + */ +#define R_POS 0x00 /* A(sym) Positive Relocation */ +#define R_NEG 0x01 /* -A(sym) Negative Relocation */ +#define R_REL 0x02 /* A(sym-*) Relative to self */ +#define R_TOC 0x03 /* A(sym-TOC) Relative to TOC */ +#define R_TRL 0x12 /* A(sym-TOC) TOC Relative indirect load. */ + /* modifiable instruction */ +#define R_TRLA 0x13 /* A(sym-TOC) TOC Rel load address. modifiable inst */ +#define R_GL 0x05 /* A(external TOC of sym) Global Linkage */ +#define R_TCL 0x06 /* A(local TOC of sym) Local object TOC address */ +#define R_RL 0x0C /* A(sym) Pos indirect load. modifiable instruction */ +#define R_RLA 0x0D /* A(sym) Pos Load Address. modifiable instruction */ +#define R_REF 0x0F /* AL0(sym) Non relocating ref. No garbage collect */ +#define R_BA 0x08 /* A(sym) Branch absolute. Cannot modify instruction */ +#define R_RBA 0x18 /* A(sym) Branch absolute. modifiable instruction */ +#define R_RBAC 0x19 /* A(sym) Branch absolute constant. modifiable instr */ +#define R_BR 0x0A /* A(sym-*) Branch rel to self. non modifiable */ +#define R_RBR 0x1A /* A(sym-*) Branch rel to self. modifiable instr */ +#define R_RBRC 0x1B /* A(sym-*) Branch absolute const. */ + /* modifiable to R_RBR */ +#define R_RTB 0x04 /* A((sym-*)/2) RT IAR Rel Branch. non modifiable */ +#define R_RRTBI 0x14 /* A((sym-*)/2) RT IAR Rel Br. modifiable to R_RRTBA */ +#define R_RRTBA 0x15 /* A((sym-*)/2) RT absolute br. modifiable to R_RRTBI */ +#endif /* __powerpc */ + +#endif /* _COFF_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coffloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coffloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/coffloader.h (revision 51223) @@ -0,0 +1,38 @@ +/* + * + * Copyright 1997,1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/coffloader.h,v 1.3 1998/09/20 14:41:04 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _COFFLOADER_H +#define _COFFLOADER_H +/* coffloader.c */ +extern void *COFFLoadModule(loaderPtr, int, LOOKUP **, int flags); +extern void COFFResolveSymbols(void *); +extern int COFFCheckForUnresolved(void *); +extern char *COFFAddressToSection(void *, unsigned long); +extern void COFFUnloadModule(void *); +#endif /* _COFFLOADER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormap.h (revision 51223) @@ -0,0 +1,184 @@ +/* $XFree86: xc/programs/Xserver/include/colormap.h,v 1.5 2001/12/14 19:59:53 dawes Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +*/ +/* $Xorg: colormap.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ + +#ifndef CMAP_H +#define CMAP_H 1 + +#include +#include "screenint.h" +#include "window.h" + +/* these follow X.h's AllocNone and AllocAll */ +#define CM_PSCREEN 2 +#define CM_PWIN 3 +/* Passed internally in colormap.c */ +#define REDMAP 0 +#define GREENMAP 1 +#define BLUEMAP 2 +#define PSEUDOMAP 3 +#define AllocPrivate (-1) +#define AllocTemporary (-2) +#define DynamicClass 1 + +/* Values for the flags field of a colormap. These should have 1 bit set + * and not overlap */ +#define IsDefault 1 +#define AllAllocated 2 +#define BeingCreated 4 + + +typedef CARD32 Pixel; +typedef struct _CMEntry *EntryPtr; +/* moved to screenint.h: typedef struct _ColormapRec *ColormapPtr */ +typedef struct _colorResource *colorResourcePtr; + +extern int CreateColormap( + Colormap /*mid*/, + ScreenPtr /*pScreen*/, + VisualPtr /*pVisual*/, + ColormapPtr* /*ppcmap*/, + int /*alloc*/, + int /*client*/); + +extern int FreeColormap( + pointer /*pmap*/, + XID /*mid*/); + +extern int TellLostMap( + WindowPtr /*pwin*/, + pointer /* Colormap *pmid */); + +extern int TellGainedMap( + WindowPtr /*pwin*/, + pointer /* Colormap *pmid */); + +extern int CopyColormapAndFree( + Colormap /*mid*/, + ColormapPtr /*pSrc*/, + int /*client*/); + +extern int AllocColor( + ColormapPtr /*pmap*/, + unsigned short* /*pred*/, + unsigned short* /*pgreen*/, + unsigned short* /*pblue*/, + Pixel* /*pPix*/, + int /*client*/); + +extern void FakeAllocColor( + ColormapPtr /*pmap*/, + xColorItem * /*item*/); + +extern void FakeFreeColor( + ColormapPtr /*pmap*/, + Pixel /*pixel*/); + +typedef int (*ColorCompareProcPtr)( + EntryPtr /*pent*/, + xrgb * /*prgb*/); + +extern int FindColor( + ColormapPtr /*pmap*/, + EntryPtr /*pentFirst*/, + int /*size*/, + xrgb* /*prgb*/, + Pixel* /*pPixel*/, + int /*channel*/, + int /*client*/, + ColorCompareProcPtr /*comp*/); + +extern int QueryColors( + ColormapPtr /*pmap*/, + int /*count*/, + Pixel* /*ppixIn*/, + xrgb* /*prgbList*/); + +extern int FreeClientPixels( + pointer /*pcr*/, + XID /*fakeid*/); + +extern int AllocColorCells( + int /*client*/, + ColormapPtr /*pmap*/, + int /*colors*/, + int /*planes*/, + Bool /*contig*/, + Pixel* /*ppix*/, + Pixel* /*masks*/); + +extern int AllocColorPlanes( + int /*client*/, + ColormapPtr /*pmap*/, + int /*colors*/, + int /*r*/, + int /*g*/, + int /*b*/, + Bool /*contig*/, + Pixel* /*pixels*/, + Pixel* /*prmask*/, + Pixel* /*pgmask*/, + Pixel* /*pbmask*/); + +extern int FreeColors( + ColormapPtr /*pmap*/, + int /*client*/, + int /*count*/, + Pixel* /*pixels*/, + Pixel /*mask*/); + +extern int StoreColors( + ColormapPtr /*pmap*/, + int /*count*/, + xColorItem* /*defs*/); + +extern int IsMapInstalled( + Colormap /*map*/, + WindowPtr /*pWin*/); + +#endif /* CMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormapst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormapst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/colormapst.h (revision 51223) @@ -0,0 +1,134 @@ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +*/ +/* $Xorg: colormapst.h,v 1.4 2001/02/09 02:05:14 xorgcvs Exp $ */ + +#ifndef CMAPSTRUCT_H +#define CMAPSTRUCT_H 1 + +#include + +#include "colormap.h" +#include "screenint.h" + +/* Shared color -- the color is used by AllocColorPlanes */ +typedef struct +{ + unsigned short color; + short refcnt; +} SHAREDCOLOR; + +/* LOCO -- a local color for a PseudoColor cell. DirectColor maps always + * use the first value (called red) in the structure. What channel they + * are really talking about depends on which map they are in. */ +typedef struct +{ + unsigned short red, green, blue; +} LOCO; + +/* SHCO -- a shared color for a PseudoColor cell. Used with AllocColorPlanes. + * DirectColor maps always use the first value (called red) in the structure. + * What channel they are really talking about depends on which map they + * are in. */ +typedef struct +{ + SHAREDCOLOR *red, *green, *blue; +} SHCO; + + +/* color map entry */ +typedef struct _CMEntry +{ + union + { + LOCO local; + SHCO shco; + } co; + short refcnt; + Bool fShared; +} Entry; + +/* + * COLORMAPs can be used for either Direct or Pseudo color. PseudoColor + * only needs one cell table, we arbitrarily pick red. We keep track + * of that table with freeRed, numPixelsRed, and clientPixelsRed + * + * The padN variables are unfortunate ABI BC. See fdo bug #6924. + */ + +typedef struct _ColormapRec +{ + VisualPtr pVisual; + short class; /* PseudoColor or DirectColor */ +#if defined(_XSERVER64) + short pad0; + XID pad1; +#endif + XID mid; /* client's name for colormap */ +#if defined(_XSERVER64) && (X_BYTE_ORDER == X_LITTLE_ENDIAN) + XID pad2; +#endif + ScreenPtr pScreen; /* screen map is associated with */ + short flags; /* 1 = IsDefault + * 2 = AllAllocated */ + int freeRed; + int freeGreen; + int freeBlue; + int *numPixelsRed; + int *numPixelsGreen; + int *numPixelsBlue; + Pixel **clientPixelsRed; + Pixel **clientPixelsGreen; + Pixel **clientPixelsBlue; + Entry *red; + Entry *green; + Entry *blue; + pointer devPriv; + DevUnion *devPrivates; /* dynamic devPrivates added after devPriv + already existed - must keep devPriv */ +} ColormapRec; + +#endif /* COLORMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compiler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compiler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compiler.h (revision 51223) @@ -0,0 +1,1859 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/compiler.h,v 3.106 2004/02/02 03:55:28 dawes Exp $ */ +/* + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Thomas Roell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Thomas Roell makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XConsortium: compiler.h /main/16 1996/10/25 15:38:34 kaleb $ */ + +#ifndef _COMPILER_H + +# define _COMPILER_H + +#if defined(__SUNPRO_C) +# define DO_PROTOTYPES +#endif + +/* Allow drivers to use the GCC-supported __inline__ and/or __inline. */ +# ifndef __inline__ +# if defined(__GNUC__) + /* gcc has __inline__ */ +# elif defined(__HIGHC__) +# define __inline__ _Inline +# else +# define __inline__ /**/ +# endif +# endif /* __inline__ */ +# ifndef __inline +# if defined(__GNUC__) + /* gcc has __inline */ +# elif defined(__HIGHC__) +# define __inline _Inline +# else +# define __inline /**/ +# endif +# endif /* __inline */ + +# if defined(IODEBUG) && defined(__GNUC__) +# define outb RealOutb +# define outw RealOutw +# define outl RealOutl +# define inb RealInb +# define inw RealInw +# define inl RealInl +# endif + +# if defined(QNX4) /* Do this for now to keep Watcom happy */ +# define outb outp +# define outw outpw +# define outl outpd +# define inb inp +# define inw inpw +# define inl inpd + +/* Define the ffs function for inlining */ +extern int ffs(unsigned long); +# pragma aux ffs_ = \ + "bsf edx, eax" \ + "jnz bits_set" \ + "xor eax, eax" \ + "jmp exit1" \ + "bits_set:" \ + "mov eax, edx" \ + "inc eax" \ + "exit1:" \ + __parm [eax] \ + __modify [eax edx] \ + __value [eax] \ + ; +# endif + +# if defined(__SUNPRO_C) +# define DO_PROTOTYPES +# endif + +# if defined(NO_INLINE) || defined(DO_PROTOTYPES) + +# if !defined(__arm__) +# if !defined(__sparc__) && !defined(__arm32__) \ + && !(defined(__alpha__) && defined(linux)) \ + && !(defined(__ia64__) && defined(linux)) \ + +extern void outb(unsigned short, unsigned char); +extern void outw(unsigned short, unsigned short); +extern void outl(unsigned short, unsigned int); +extern unsigned int inb(unsigned short); +extern unsigned int inw(unsigned short); +extern unsigned int inl(unsigned short); + +# else /* __sparc__, __arm32__, __alpha__*/ + +extern void outb(unsigned long, unsigned char); +extern void outw(unsigned long, unsigned short); +extern void outl(unsigned long, unsigned int); +extern unsigned int inb(unsigned long); +extern unsigned int inw(unsigned long); +extern unsigned int inl(unsigned long); + +# endif /* __sparc__, __arm32__, __alpha__ */ +# endif /* __arm__ */ + +extern unsigned long ldq_u(unsigned long *); +extern unsigned long ldl_u(unsigned int *); +extern unsigned long ldw_u(unsigned short *); +extern void stq_u(unsigned long, unsigned long *); +extern void stl_u(unsigned long, unsigned int *); +extern void stw_u(unsigned long, unsigned short *); +extern void mem_barrier(void); +extern void write_mem_barrier(void); +extern void stl_brx(unsigned long, volatile unsigned char *, int); +extern void stw_brx(unsigned short, volatile unsigned char *, int); +extern unsigned long ldl_brx(volatile unsigned char *, int); +extern unsigned short ldw_brx(volatile unsigned char *, int); + +# endif + +# ifndef NO_INLINE +# ifdef __GNUC__ +# if (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) && (defined(__alpha__)) + +# ifdef linux +/* for Linux on Alpha, we use the LIBC _inx/_outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +extern void (*_alpha_outb)(char val, unsigned long port); +static __inline__ void +outb(unsigned long port, unsigned char val) +{ + _alpha_outb(val, port); +} + +extern void (*_alpha_outw)(short val, unsigned long port); +static __inline__ void +outw(unsigned long port, unsigned short val) +{ + _alpha_outw(val, port); +} + +extern void (*_alpha_outl)(int val, unsigned long port); +static __inline__ void +outl(unsigned long port, unsigned int val) +{ + _alpha_outl(val, port); +} + +extern unsigned int (*_alpha_inb)(unsigned long port); +static __inline__ unsigned int +inb(unsigned long port) +{ + return _alpha_inb(port); +} + +extern unsigned int (*_alpha_inw)(unsigned long port); +static __inline__ unsigned int +inw(unsigned long port) +{ + return _alpha_inw(port); +} + +extern unsigned int (*_alpha_inl)(unsigned long port); +static __inline__ unsigned int +inl(unsigned long port) +{ + return _alpha_inl(port); +} + +# endif /* linux */ + +# if (defined(__FreeBSD__) || defined(__OpenBSD__)) \ + && !defined(DO_PROTOTYPES) + +/* for FreeBSD and OpenBSD on Alpha, we use the libio (resp. libalpha) */ +/* inx/outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +extern void outb(unsigned int port, unsigned char val); +extern void outw(unsigned int port, unsigned short val); +extern void outl(unsigned int port, unsigned int val); +extern unsigned char inb(unsigned int port); +extern unsigned short inw(unsigned int port); +extern unsigned int inl(unsigned int port); + +# endif /* (__FreeBSD__ || __OpenBSD__ ) && !DO_PROTOTYPES */ + + +#if defined(__NetBSD__) +#include +#endif /* __NetBSD__ */ + +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +/* + * Elemental unaligned loads + */ +/* let's try making these things static */ + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +# endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +# endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +# else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +# endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +# else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +# endif +} + +/* to flush the I-cache before jumping to code which just got loaded */ +# define PAL_imb 134 +# define istream_mem_barrier() \ + __asm__ __volatile__("call_pal %0 #imb" : : "i" (PAL_imb) : "memory") +# define mem_barrier() __asm__ __volatile__("mb" : : : "memory") +# ifdef __ELF__ +# define write_mem_barrier() __asm__ __volatile__("wmb" : : : "memory") +# else /* ECOFF gas 2.6 doesn't know "wmb" :-( */ +# define write_mem_barrier() mem_barrier() +# endif + + +# elif defined(linux) && defined(__ia64__) + +# include + +# include + +struct __una_u64 { uint64_t x __attribute__((packed)); }; +struct __una_u32 { uint32_t x __attribute__((packed)); }; +struct __una_u16 { uint16_t x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +__uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +__uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +__ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +__ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +__ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +# define ldq_u(p) __uldq(p) +# define ldl_u(p) __uldl(p) +# define ldw_u(p) __uldw(p) +# define stq_u(v,p) __ustq(v,p) +# define stl_u(v,p) __ustl(v,p) +# define stw_u(v,p) __ustw(v,p) + +# ifndef __INTEL_COMPILER +# define mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") +# define write_mem_barrier() __asm__ __volatile__ ("mf" ::: "memory") +# else +# include "ia64intrin.h" +# define mem_barrier() __mf() +# define write_mem_barrier() __mf() +# endif + +/* + * This is overkill, but for different reasons depending on where it is used. + * This is thus general enough to be used everywhere cache flushes are needed. + * It doesn't handle memory access serialisation by other processors, though. + */ +# ifndef __INTEL_COMPILER +# define ia64_flush_cache(Addr) \ + __asm__ __volatile__ ( \ + "fc.i %0;;;" \ + "sync.i;;;" \ + "mf;;;" \ + "srlz.i;;;" \ + :: "r"(Addr) : "memory") +# else +# define ia64_flush_cache(Addr) { \ + __fc(Addr);\ + __synci();\ + __mf();\ + __isrlz();\ + } +# endif +# undef outb +# undef outw +# undef outl +# undef inb +# undef inw +# undef inl +extern void outb(unsigned long port, unsigned char val); +extern void outw(unsigned long port, unsigned short val); +extern void outl(unsigned long port, unsigned int val); +extern unsigned int inb(unsigned long port); +extern unsigned int inw(unsigned long port); +extern unsigned int inl(unsigned long port); + +# elif defined(linux) && defined(__amd64__) + +# include + +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) + +# define mem_barrier() \ + __asm__ __volatile__ ("lock; addl $0,0(%%rsp)": : :"memory") +# define write_mem_barrier() \ + __asm__ __volatile__ ("": : :"memory") + + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# elif (defined(linux) || defined(Lynx) || defined(sun) || defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc__) + +# if !defined(Lynx) +# ifndef ASI_PL +# define ASI_PL 0x88 +# endif + +# define barrier() __asm__ __volatile__(".word 0x8143e00a": : :"memory") + +static __inline__ void +outb(unsigned long port, unsigned char val) +{ + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +outw(unsigned long port, unsigned short val) +{ + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +outl(unsigned long port, unsigned int val) +{ + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (port), "i" (ASI_PL)); + barrier(); +} + +static __inline__ unsigned int +inb(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned long port) +{ + unsigned int ret; + __asm__ __volatile__("lda [%1] %2, %0" + : "=r" (ret) + : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned char +xf86ReadMmio8(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned char ret; + + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned short +xf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned short ret; + + __asm__ __volatile__("lduh [%1], %0" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ unsigned short +xf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned short ret; + + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("ld [%1], %0" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ unsigned int +xf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("lda [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PL)); + return ret; +} + +static __inline__ void +xf86WriteMmio8(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sth %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); + barrier(); +} + +static __inline__ void +xf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("st %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); + barrier(); +} + +static __inline__ void +xf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); + barrier(); +} + +static __inline__ void +xf86WriteMmio8NB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stba %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +static __inline__ void +xf86WriteMmio16BeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sth %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); +} + +static __inline__ void +xf86WriteMmio16LeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("stha %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +static __inline__ void +xf86WriteMmio32BeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("st %0, [%1]" + : /* No outputs */ + : "r" (val), "r" (addr)); +} + +static __inline__ void +xf86WriteMmio32LeNB(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sta %0, [%1] %2" + : /* No outputs */ + : "r" (val), "r" (addr), "i" (ASI_PL)); +} + +# endif /* !Lynx */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +# if defined(__arch64__) || defined(__sparcv9) +struct __una_u64 { unsigned long x __attribute__((packed)); }; +# endif +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long ldq_u(unsigned long *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +# if defined(__arch64__) || defined(__sparcv9) + const struct __una_u64 *ptr = (const struct __una_u64 *) p; +# else + const struct __una_u32 *ptr = (const struct __una_u32 *) p; +# endif + return ptr->x; +# else + unsigned long ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ unsigned long ldl_u(unsigned int *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) p; + return ptr->x; +# else + unsigned int ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ unsigned long ldw_u(unsigned short *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) p; + return ptr->x; +# else + unsigned short ret; + memmove(&ret, p, sizeof(*p)); + return ret; +# endif +} + +static __inline__ void stq_u(unsigned long val, unsigned long *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +# if defined(__arch64__) || defined(__sparcv9) + struct __una_u64 *ptr = (struct __una_u64 *) p; +# else + struct __una_u32 *ptr = (struct __una_u32 *) p; +# endif + ptr->x = val; +# else + unsigned long tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +static __inline__ void stl_u(unsigned long val, unsigned int *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) p; + ptr->x = val; +# else + unsigned int tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +static __inline__ void stw_u(unsigned long val, unsigned short *p) +{ +# if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) p; + ptr->x = val; +# else + unsigned short tmp = val; + memmove(p, &tmp, sizeof(*p)); +# endif +} + +# define mem_barrier() /* XXX: nop for now */ +# define write_mem_barrier() /* XXX: nop for now */ + +# elif defined(__mips__) || (defined(__arm32__) && !defined(__linux__)) +# ifdef __arm32__ +# define PORT_SIZE long +# else +# define PORT_SIZE short +# endif + +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void +outb(unsigned PORT_SIZE port, unsigned char val) +{ + *(volatile unsigned char*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ void +outw(unsigned PORT_SIZE port, unsigned short val) +{ + *(volatile unsigned short*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ void +outl(unsigned PORT_SIZE port, unsigned int val) +{ + *(volatile unsigned int*)(((unsigned PORT_SIZE)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int +inb(unsigned PORT_SIZE port) +{ + return *(volatile unsigned char*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + +static __inline__ unsigned int +inw(unsigned PORT_SIZE port) +{ + return *(volatile unsigned short*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + +static __inline__ unsigned int +inl(unsigned PORT_SIZE port) +{ + return *(volatile unsigned int*)(((unsigned PORT_SIZE)(port))+IOPortBase); +} + + +# if defined(__mips__) +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(3+(char *) r11))); + return r1; +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(3+(char *) r11))); + return r1; +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ + unsigned long r1; + __asm__("lwr %0,%2\n\t" + "lwl %0,%3\n\t" + :"=&r" (r1) + :"r" (r11), + "m" (*r11), + "m" (*(unsigned long *)(1+(char *) r11))); + return r1; +} + +# ifdef linux /* don't mess with other OSs */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads (and we don't support older + * versions anyway. Define some packed structures to talk about such things + * with. + */ + +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ void stw_u(unsigned long val, unsigned short *p) +{ + struct __una_u16 *ptr = (struct __una_u16 *) p; + ptr->x = val; +} + +static __inline__ void stl_u(unsigned long val, unsigned int *p) +{ + struct __una_u32 *ptr = (struct __una_u32 *) p; + ptr->x = val; +} + +# if X_BYTE_ORDER == X_BIG_ENDIAN +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + unsigned long addr = ((unsigned long)base) + offset; + unsigned int ret; + + __asm__ __volatile__("lw %0, 0(%1)" + : "=r" (ret) + : "r" (addr)); + return ret; +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + unsigned long addr = ((unsigned long)base) + offset; + + __asm__ __volatile__("sw %0, 0(%1)" + : /* No outputs */ + : "r" (val), "r" (addr)); +} +# endif + +# define mem_barrier() \ + __asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ + ".set\tnoreorder\n\t" \ + "# 8 nops to fool the R4400 pipeline\n\t" \ + "nop;nop;nop;nop;nop;nop;nop;nop\n\t" \ + ".set\treorder" \ + : /* no output */ \ + : /* no input */ \ + : "memory") +# define write_mem_barrier() mem_barrier() + +# else /* !linux */ + +# define stq_u(v,p) stl_u(v,p) +# define stl_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*(unsigned char *)(p)+1) = ((v) >> 8); \ + (*(unsigned char *)(p)+2) = ((v) >> 16); \ + (*(unsigned char *)(p)+3) = ((v) >> 24) + +# define stw_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*(unsigned char *)(p)+1) = ((v) >> 8) + +# define mem_barrier() /* NOP */ +# endif /* !linux */ +# endif /* __mips__ */ + +# if defined(__arm32__) +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ +# endif /* __arm32__ */ + +# elif (defined(Lynx) || defined(linux) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__FreeBSD__)) && defined(__powerpc__) + +# ifndef MAP_FAILED +# define MAP_FAILED ((void *)-1) +# endif + +extern volatile unsigned char *ioBase; + +#if defined(linux) && defined(__powerpc64__) +# include +#endif /* defined(linux) && defined(__powerpc64__) */ +#ifndef eieio /* We deal with arch-specific eieio() routines above... */ +# define eieio() __asm__ __volatile__ ("eieio" ::: "memory") +#endif /* eieio */ + +static __inline__ unsigned char +xf86ReadMmio8(__volatile__ void *base, const unsigned long offset) +{ + register unsigned char val; + __asm__ __volatile__( + "lbzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned short +xf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset) +{ + register unsigned short val; + __asm__ __volatile__( + "lhzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned short +xf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset) +{ + register unsigned short val; + __asm__ __volatile__( + "lhbrx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned int +xf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset) +{ + register unsigned int val; + __asm__ __volatile__( + "lwzx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ unsigned int +xf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset) +{ + register unsigned int val; + __asm__ __volatile__( + "lwbrx %0,%1,%2\n\t" + "eieio" + : "=r" (val) + : "b" (base), "r" (offset), + "m" (*((volatile unsigned char *)base+offset))); + return val; +} + +static __inline__ void +xf86WriteMmioNB8(__volatile__ void *base, const unsigned long offset, + const unsigned char val) +{ + __asm__ __volatile__( + "stbx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB16Le(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + __asm__ __volatile__( + "sthbrx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB16Be(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + __asm__ __volatile__( + "sthx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + __asm__ __volatile__( + "stwbrx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmioNB32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + __asm__ __volatile__( + "stwx %1,%2,%3\n\t" + : "=m" (*((volatile unsigned char *)base+offset)) + : "r" (val), "b" (base), "r" (offset)); +} + +static __inline__ void +xf86WriteMmio8(__volatile__ void *base, const unsigned long offset, + const unsigned char val) +{ + xf86WriteMmioNB8(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + xf86WriteMmioNB16Le(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset, + const unsigned short val) +{ + xf86WriteMmioNB16Be(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + xf86WriteMmioNB32Le(base, offset, val); + eieio(); +} + +static __inline__ void +xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, + const unsigned int val) +{ + xf86WriteMmioNB32Be(base, offset, val); + eieio(); +} + + +static __inline__ void +outb(unsigned short port, unsigned char value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio8((void *)ioBase, port, value); +} + +static __inline__ void +outw(unsigned short port, unsigned short value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio16Le((void *)ioBase, port, value); +} + +static __inline__ void +outl(unsigned short port, unsigned int value) +{ + if(ioBase == MAP_FAILED) return; + xf86WriteMmio32Le((void *)ioBase, port, value); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio8((void *)ioBase, port); +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio16Le((void *)ioBase, port); +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + if(ioBase == MAP_FAILED) return 0; + return xf86ReadMmio32Le((void *)ioBase, port); +} + +# define ldq_u(p) ldl_u(p) +# define ldl_u(p) ((*(unsigned char *)(p)) | \ + (*((unsigned char *)(p)+1)<<8) | \ + (*((unsigned char *)(p)+2)<<16) | \ + (*((unsigned char *)(p)+3)<<24)) +# define ldw_u(p) ((*(unsigned char *)(p)) | \ + (*((unsigned char *)(p)+1)<<8)) + +# define stq_u(v,p) stl_u(v,p) +# define stl_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*((unsigned char *)(p)+1)) = ((v) >> 8); \ + (*((unsigned char *)(p)+2)) = ((v) >> 16); \ + (*((unsigned char *)(p)+3)) = ((v) >> 24) +# define stw_u(v,p) (*(unsigned char *)(p)) = (v); \ + (*((unsigned char *)(p)+1)) = ((v) >> 8) + +# define mem_barrier() eieio() +# define write_mem_barrier() eieio() + +#elif defined(__arm__) && defined(__linux__) + +#define ldq_u(p) (*((unsigned long *)(p))) +#define ldl_u(p) (*((unsigned int *)(p))) +#define ldw_u(p) (*((unsigned short *)(p))) +#define stq_u(v,p) (*(unsigned long *)(p)) = (v) +#define stl_u(v,p) (*(unsigned int *)(p)) = (v) +#define stw_u(v,p) (*(unsigned short *)(p)) = (v) +#define mem_barrier() /* NOP */ +#define write_mem_barrier() /* NOP */ + +/* for Linux on ARM, we use the LIBC inx/outx routines */ +/* note that the appropriate setup via "ioperm" needs to be done */ +/* *before* any inx/outx is done. */ + +#include + +static __inline__ void +xf_outb(unsigned short port, unsigned char val) +{ + outb(val, port); +} + +static __inline__ void +xf_outw(unsigned short port, unsigned short val) +{ + outw(val, port); +} + +static __inline__ void +xf_outl(unsigned short port, unsigned int val) +{ + outl(val, port); +} + +#define outb xf_outb +#define outw xf_outw +#define outl xf_outl + +#define arm_flush_cache(addr) \ +do { \ + register unsigned long _beg __asm ("a1") = (unsigned long) (addr); \ + register unsigned long _end __asm ("a2") = (unsigned long) (addr) + 4;\ + register unsigned long _flg __asm ("a3") = 0; \ + __asm __volatile ("swi 0x9f0002 @ sys_cacheflush" \ + : "=r" (_beg) \ + : "0" (_beg), "r" (_end), "r" (_flg)); \ +} while (0) + +# else /* ix86 */ + +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ + +# if !defined(__SUNPRO_C) +# if !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__) +# ifdef GCCUSESGAS + +/* + * If gcc uses gas rather than the native assembler, the syntax of these + * inlines has to be different. DHD + */ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# else /* GCCUSESGAS */ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ + __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ + __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ + __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + unsigned char ret; + __asm__ __volatile__("in%B0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + unsigned short ret; + __asm__ __volatile__("in%W0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + unsigned int ret; + __asm__ __volatile__("in%L0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +# endif /* GCCUSESGAS */ + +# else /* !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__)*/ + +static __inline__ void +outb(unsigned short port, unsigned char val) +{ +} + +static __inline__ void +outw(unsigned short port, unsigned short val) +{ +} + +static __inline__ void +outl(unsigned short port, unsigned int val) +{ +} + +static __inline__ unsigned int +inb(unsigned short port) +{ + return 0; +} + +static __inline__ unsigned int +inw(unsigned short port) +{ + return 0; +} + +static __inline__ unsigned int +inl(unsigned short port) +{ + return 0; +} + +# endif /* FAKEIT */ +# endif /* __SUNPRO_C */ + +# endif /* ix86 */ + +# elif defined(__powerpc__) /* && !__GNUC__ */ +/* + * NON-GCC PowerPC - Presumed to be PowerMAX OS for now + */ +# ifndef PowerMAX_OS +# error - Non-gcc PowerPC and !PowerMAXOS ??? +# endif + +# define PPCIO_DEBUG 0 +# define PPCIO_INLINE 1 +# define USE_ABS_MACRO 1 +/* + * Use compiler intrinsics to access certain PPC machine instructions + */ +# define eieio() __inst_eieio() +# define stw_brx(val,base,ndx) __inst_sthbrx(val,base,ndx) +# define stl_brx(val,base,ndx) __inst_stwbrx(val,base,ndx) +# define ldw_brx(base,ndx) __inst_lhbrx(base,ndx) +# define ldl_brx(base,ndx) __inst_lwbrx(base,ndx) + +# define ldq_u(p) (*((unsigned long long *)(p))) +# define ldl_u(p) (*((unsigned long *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned long *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() eieio() +# define write_mem_barrier() eieio() + +extern volatile unsigned char *ioBase; + +# if !defined(abs) && defined(USE_ABS_MACRO) +# define abs(x) ((x) >= 0 ? (x) : -(x)) +# endif + +# undef inb +# undef inw +# undef inl +# undef outb +# undef outw +# undef outl + +# if PPCIO_DEBUG + +extern void debug_outb(unsigned int a, unsigned char b, int line, char *file); +extern void debug_outw(unsigned int a, unsigned short w, int line, char *file); +extern void debug_outl(unsigned int a, unsigned int l, int line, char *file); +extern unsigned char debug_inb(unsigned int a, int line, char *file); +extern unsigned short debug_inw(unsigned int a, int line, char *file); +extern unsigned int debug_inl(unsigned int a, int line, char *file); + +# define outb(a,b) debug_outb(a,b, __LINE__, __FILE__) +# define outw(a,w) debug_outw(a,w, __LINE__, __FILE__) +# define outl(a,l) debug_outl(a,l, __LINE__, __FILE__) +# define inb(a) debug_inb(a, __LINE__, __FILE__) +# define inw(a) debug_inw(a, __LINE__, __FILE__) +# define inl(a) debug_inl(a, __LINE__, __FILE__) + +# else /* !PPCIO_DEBUG */ + +extern unsigned char inb(unsigned int a); +extern unsigned short inw(unsigned int a); +extern unsigned int inl(unsigned int a); + +# if PPCIO_INLINE + +# define outb(a,b) \ + (*((volatile unsigned char *)(ioBase + (a))) = (b), eieio()) +# define outw(a,w) (stw_brx((w),ioBase,(a)), eieio()) +# define outl(a,l) (stl_brx((l),ioBase,(a)), eieio()) + +# else /* !PPCIO_INLINE */ + +extern void outb(unsigned int a, unsigned char b); +extern void outw(unsigned int a, unsigned short w); +extern void outl(unsigned int a, unsigned int l); + +# endif /* PPCIO_INLINE */ + +# endif /* !PPCIO_DEBUG */ + +# else /* !GNUC && !PPC */ +# if !defined(QNX4) +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef asm +# define asm __asm +# endif +# endif +# ifndef SCO325 +# if defined(__UNIXWARE__) +# if defined(IN_MODULE) +# /* avoid including for on UnixWare */ +# define ushort unsigned short +# define ushort_t unsigned short +# define ulong unsigned long +# define ulong_t unsigned long +# define uint_t unsigned int +# define uchar_t unsigned char +# else +# include +# endif /* IN_MODULE */ +# endif /* __UNIXWARE__ */ +# if !defined(sgi) && !defined(__SUNPRO_C) +# include +# endif +# else +# include "scoasm.h" +# endif +# if (!defined(__HIGHC__) && !defined(sgi) && !defined(__SUNPRO_C)) || \ + defined(__USLC__) +# pragma asm partial_optimization outl +# pragma asm partial_optimization outw +# pragma asm partial_optimization outb +# pragma asm partial_optimization inl +# pragma asm partial_optimization inw +# pragma asm partial_optimization inb +# endif +# endif +# define ldq_u(p) (*((unsigned long *)(p))) +# define ldl_u(p) (*((unsigned int *)(p))) +# define ldw_u(p) (*((unsigned short *)(p))) +# define stq_u(v,p) (*(unsigned long *)(p)) = (v) +# define stl_u(v,p) (*(unsigned int *)(p)) = (v) +# define stw_u(v,p) (*(unsigned short *)(p)) = (v) +# define mem_barrier() /* NOP */ +# define write_mem_barrier() /* NOP */ +# endif /* __GNUC__ */ + +# if defined(QNX4) +# include +extern unsigned inb(unsigned port); +extern unsigned inw(unsigned port); +extern unsigned inl(unsigned port); +extern void outb(unsigned port, unsigned val); +extern void outw(unsigned port, unsigned val); +extern void outl(unsigned port, unsigned val); +# endif /* QNX4 */ + +# if defined(IODEBUG) && defined(__GNUC__) +# undef inb +# undef inw +# undef inl +# undef outb +# undef outw +# undef outl +# define inb(a) __extension__ ({unsigned char __c=RealInb(a); ErrorF("inb(0x%03x) = 0x%02x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) +# define inw(a) __extension__ ({unsigned short __c=RealInw(a); ErrorF("inw(0x%03x) = 0x%04x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) +# define inl(a) __extension__ ({unsigned int __c=RealInl(a); ErrorF("inl(0x%03x) = 0x%08x\t@ line %4d, file %s\n", a, __c, __LINE__, __FILE__);__c;}) + +# define outb(a,b) (ErrorF("outb(0x%03x, 0x%02x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutb(a,b)) +# define outw(a,b) (ErrorF("outw(0x%03x, 0x%04x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutw(a,b)) +# define outl(a,b) (ErrorF("outl(0x%03x, 0x%08x)\t@ line %4d, file %s\n", a, b, __LINE__, __FILE__),RealOutl(a,b)) +# endif + +# endif /* NO_INLINE */ + +# ifdef __alpha__ +/* entry points for Mmio memory access routines */ +extern int (*xf86ReadMmio8)(void *, unsigned long); +extern int (*xf86ReadMmio16)(void *, unsigned long); +# ifndef STANDALONE_MMIO +extern int (*xf86ReadMmio32)(void *, unsigned long); +# else +/* Some DRI 3D drivers need MMIO_IN32. */ +static __inline__ int +xf86ReadMmio32(void *Base, unsigned long Offset) +{ + __asm__ __volatile__("mb" : : : "memory"); + return *(volatile unsigned int*)((unsigned long)Base+(Offset)); +} +# endif +extern void (*xf86WriteMmio8)(int, void *, unsigned long); +extern void (*xf86WriteMmio16)(int, void *, unsigned long); +extern void (*xf86WriteMmio32)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB8)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB16)(int, void *, unsigned long); +extern void (*xf86WriteMmioNB32)(int, void *, unsigned long); +extern void xf86JensenMemToBus(char *, long, long, int); +extern void xf86JensenBusToMem(char *, char *, unsigned long, int); +extern void xf86SlowBCopyFromBus(unsigned char *, unsigned char *, int); +extern void xf86SlowBCopyToBus(unsigned char *, unsigned char *, int); + +/* Some macros to hide the system dependencies for MMIO accesses */ +/* Changed to kill noise generated by gcc's -Wcast-align */ +# define MMIO_IN8(base, offset) (*xf86ReadMmio8)(base, offset) +# define MMIO_IN16(base, offset) (*xf86ReadMmio16)(base, offset) +# ifndef STANDALONE_MMIO +# define MMIO_IN32(base, offset) (*xf86ReadMmio32)(base, offset) +# else +# define MMIO_IN32(base, offset) xf86ReadMmio32(base, offset) +# endif + +# if defined (JENSEN_SUPPORT) +# define MMIO_OUT32(base, offset, val) \ + (*xf86WriteMmio32)((CARD32)(val), base, offset) +# define MMIO_ONB32(base, offset, val) \ + (*xf86WriteMmioNB32)((CARD32)(val), base, offset) +# else +# define MMIO_OUT32(base, offset, val) \ + do { \ + write_mem_barrier(); \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val); \ + } while (0) +# define MMIO_ONB32(base, offset, val) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# endif + +# define MMIO_OUT8(base, offset, val) \ + (*xf86WriteMmio8)((CARD8)(val), base, offset) +# define MMIO_OUT16(base, offset, val) \ + (*xf86WriteMmio16)((CARD16)(val), base, offset) +# define MMIO_ONB8(base, offset, val) \ + (*xf86WriteMmioNB8)((CARD8)(val), base, offset) +# define MMIO_ONB16(base, offset, val) \ + (*xf86WriteMmioNB16)((CARD16)(val), base, offset) +# define MMIO_MOVE32(base, offset, val) \ + MMIO_OUT32(base, offset, val) + +# elif defined(__powerpc__) + /* + * we provide byteswapping and no byteswapping functions here + * with byteswapping as default, + * drivers that don't need byteswapping should define PPC_MMIO_IS_BE + */ +# define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset) +# define MMIO_OUT8(base, offset, val) \ + xf86WriteMmio8(base, offset, (CARD8)(val)) +# define MMIO_ONB8(base, offset, val) \ + xf86WriteMmioNB8(base, offset, (CARD8)(val)) + +# if defined(PPC_MMIO_IS_BE) /* No byteswapping */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Be(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmioNB16Be(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmioNB32Be(base, offset, (CARD32)(val)) +# else /* byteswapping is the default */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Le(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Le(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmioNB16Le(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmioNB32Le(base, offset, (CARD32)(val)) +# endif + +# define MMIO_MOVE32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) + +static __inline__ void ppc_flush_icache(char *addr) +{ + __asm__ volatile ( + "dcbf 0,%0;" + "sync;" + "icbi 0,%0;" + "sync;" + "isync;" + : : "r"(addr) : "memory"); +} + +# elif defined(__sparc__) || defined(sparc) + /* + * Like powerpc, we provide byteswapping and no byteswapping functions + * here with byteswapping as default, drivers that don't need byteswapping + * should define SPARC_MMIO_IS_BE (perhaps create a generic macro so that we + * do not need to use PPC_MMIO_IS_BE and the sparc one in all the same places + * of drivers?). + */ +# define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset) +# define MMIO_OUT8(base, offset, val) \ + xf86WriteMmio8(base, offset, (CARD8)(val)) +# define MMIO_ONB8(base, offset, val) \ + xf86WriteMmio8NB(base, offset, (CARD8)(val)) + +# if defined(SPARC_MMIO_IS_BE) /* No byteswapping */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Be(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmio16BeNB(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmio32BeNB(base, offset, (CARD32)(val)) +# else /* byteswapping is the default */ +# define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset) +# define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset) +# define MMIO_OUT16(base, offset, val) \ + xf86WriteMmio16Le(base, offset, (CARD16)(val)) +# define MMIO_OUT32(base, offset, val) \ + xf86WriteMmio32Le(base, offset, (CARD32)(val)) +# define MMIO_ONB16(base, offset, val) \ + xf86WriteMmio16LeNB(base, offset, (CARD16)(val)) +# define MMIO_ONB32(base, offset, val) \ + xf86WriteMmio32LeNB(base, offset, (CARD32)(val)) +# endif + +# define MMIO_MOVE32(base, offset, val) \ + xf86WriteMmio32Be(base, offset, (CARD32)(val)) + +# else /* !__alpha__ && !__powerpc__ && !__sparc__ */ + +# define MMIO_IN8(base, offset) \ + *(volatile CARD8 *)(((CARD8*)(base)) + (offset)) +# define MMIO_IN16(base, offset) \ + *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset)) +# define MMIO_IN32(base, offset) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) +# define MMIO_OUT8(base, offset, val) \ + *(volatile CARD8 *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_OUT16(base, offset, val) \ + *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_OUT32(base, offset, val) \ + *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val) +# define MMIO_ONB8(base, offset, val) MMIO_OUT8(base, offset, val) +# define MMIO_ONB16(base, offset, val) MMIO_OUT16(base, offset, val) +# define MMIO_ONB32(base, offset, val) MMIO_OUT32(base, offset, val) + +# define MMIO_MOVE32(base, offset, val) MMIO_OUT32(base, offset, val) + +# endif /* __alpha__ */ + +/* + * With Intel, the version in os-support/misc/SlowBcopy.s is used. + * This avoids port I/O during the copy (which causes problems with + * some hardware). + */ +# ifdef __alpha__ +# define slowbcopy_tobus(src,dst,count) xf86SlowBCopyToBus(src,dst,count) +# define slowbcopy_frombus(src,dst,count) xf86SlowBCopyFromBus(src,dst,count) +# else /* __alpha__ */ +# define slowbcopy_tobus(src,dst,count) xf86SlowBcopy(src,dst,count) +# define slowbcopy_frombus(src,dst,count) xf86SlowBcopy(src,dst,count) +# endif /* __alpha__ */ + +#endif /* _COMPILER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/compint.h (revision 51223) @@ -0,0 +1,314 @@ +/* + * $Id: compint.h,v 1.7 2005/07/03 07:01:17 daniels Exp $ + * + * Copyright © 2006 Sun Microsystems + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Sun Microsystems not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Sun Microsystems makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * SUN MICROSYSTEMS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL SUN MICROSYSTEMS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _COMPINT_H_ +#define _COMPINT_H_ + +#include "misc.h" +#include "scrnintstr.h" +#include "os.h" +#include "regionstr.h" +#include "validate.h" +#include "windowstr.h" +#include "input.h" +#include "resource.h" +#include "colormapst.h" +#include "cursorstr.h" +#include "dixstruct.h" +#include "gcstruct.h" +#include "servermd.h" +#include "dixevents.h" +#include "globals.h" +#include "picturestr.h" +#include "extnsionst.h" +#include "mi.h" +#include "damage.h" +#include "damageextint.h" +#include "xfixes.h" +#include +#include + +/* + * enable this for debugging + + #define COMPOSITE_DEBUG + */ + +typedef struct _CompClientWindow { + struct _CompClientWindow *next; + XID id; + int update; +} CompClientWindowRec, *CompClientWindowPtr; + +typedef struct _CompWindow { + RegionRec borderClip; + DamagePtr damage; /* for automatic update mode */ + Bool damageRegistered; + Bool damaged; + int update; + CompClientWindowPtr clients; + int oldx; + int oldy; + PixmapPtr pOldPixmap; + int borderClipX, borderClipY; +} CompWindowRec, *CompWindowPtr; + +#define COMP_ORIGIN_INVALID 0x80000000 + +typedef struct _CompSubwindows { + int update; + CompClientWindowPtr clients; +} CompSubwindowsRec, *CompSubwindowsPtr; + +#ifndef COMP_INCLUDE_RGB24_VISUAL +#define COMP_INCLUDE_RGB24_VISUAL 0 +#endif + +#if COMP_INCLUDE_RGB24_VISUAL +#define NUM_COMP_ALTERNATE_VISUALS 2 +#else +#define NUM_COMP_ALTERNATE_VISUALS 1 +#endif + +typedef struct _CompOverlayClientRec *CompOverlayClientPtr; + +typedef struct _CompOverlayClientRec { + CompOverlayClientPtr pNext; + ClientPtr pClient; + ScreenPtr pScreen; + XID resource; +} CompOverlayClientRec; + +typedef struct _CompScreen { + PositionWindowProcPtr PositionWindow; + CopyWindowProcPtr CopyWindow; + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + PaintWindowProcPtr PaintWindowBackground; + ClipNotifyProcPtr ClipNotify; + /* + * Called from ConfigureWindow, these + * three track changes to the offscreen storage + * geometry + */ + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + ChangeBorderWidthProcPtr ChangeBorderWidth; + /* + * Reparenting has an effect on Subwindows redirect + */ + ReparentWindowProcPtr ReparentWindow; + + /* + * Colormaps for new visuals better not get installed + */ + InstallColormapProcPtr InstallColormap; + + ScreenBlockHandlerProcPtr BlockHandler; + CloseScreenProcPtr CloseScreen; + Bool damaged; + XID alternateVisuals[NUM_COMP_ALTERNATE_VISUALS]; + + WindowPtr pOverlayWin; + CompOverlayClientPtr pOverlayClients; + +} CompScreenRec, *CompScreenPtr; + +extern int CompScreenPrivateIndex; +extern int CompWindowPrivateIndex; +extern int CompSubwindowsPrivateIndex; + +#define GetCompScreen(s) ((CompScreenPtr) ((s)->devPrivates[CompScreenPrivateIndex].ptr)) +#define GetCompWindow(w) ((CompWindowPtr) ((w)->devPrivates[CompWindowPrivateIndex].ptr)) +#define GetCompSubwindows(w) ((CompSubwindowsPtr) ((w)->devPrivates[CompSubwindowsPrivateIndex].ptr)) + +extern RESTYPE CompositeClientWindowType; +extern RESTYPE CompositeClientSubwindowsType; + +/* + * compalloc.c + */ + +void +compReportDamage (DamagePtr pDamage, RegionPtr pRegion, void *closure); + +Bool +compRedirectWindow (ClientPtr pClient, WindowPtr pWin, int update); + +void +compFreeClientWindow (WindowPtr pWin, XID id); + +int +compUnredirectWindow (ClientPtr pClient, WindowPtr pWin, int update); + +int +compRedirectSubwindows (ClientPtr pClient, WindowPtr pWin, int update); + +void +compFreeClientSubwindows (WindowPtr pWin, XID id); + +int +compUnredirectSubwindows (ClientPtr pClient, WindowPtr pWin, int update); + +int +compRedirectOneSubwindow (WindowPtr pParent, WindowPtr pWin); + +int +compUnredirectOneSubwindow (WindowPtr pParent, WindowPtr pWin); + +Bool +compAllocPixmap (WindowPtr pWin); + +void +compFreePixmap (WindowPtr pWin); + +Bool +compReallocPixmap (WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, int bw); + +/* + * compext.c + */ + +void +CompositeExtensionInit (void); + +/* + * compinit.c + */ + +Bool +compScreenInit (ScreenPtr pScreen); + +/* + * compwindow.c + */ + +#ifdef COMPOSITE_DEBUG +void +compCheckTree (ScreenPtr pScreen); +#else +#define compCheckTree(s) +#endif + +void +compSetPixmap (WindowPtr pWin, PixmapPtr pPixmap); + +Bool +compCheckRedirect (WindowPtr pWin); + +Bool +compPositionWindow (WindowPtr pWin, int x, int y); + +Bool +compRealizeWindow (WindowPtr pWin); + +Bool +compUnrealizeWindow (WindowPtr pWin); + +void +compPaintWindowBackground (WindowPtr pWin, RegionPtr pRegion, int what); + +void +compClipNotify (WindowPtr pWin, int dx, int dy); + +void +compMoveWindow (WindowPtr pWin, int x, int y, WindowPtr pSib, VTKind kind); + +void +compResizeWindow (WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); + +void +compChangeBorderWidth (WindowPtr pWin, unsigned int border_width); + +void +compReparentWindow (WindowPtr pWin, WindowPtr pPriorParent); + +Bool +compCreateWindow (WindowPtr pWin); + +Bool +compDestroyWindow (WindowPtr pWin); + +void +compSetRedirectBorderClip (WindowPtr pWin, RegionPtr pRegion); + +RegionPtr +compGetRedirectBorderClip (WindowPtr pWin); + +void +compCopyWindow (WindowPtr pWin, DDXPointRec ptOldOrg, RegionPtr prgnSrc); + +void +compWindowUpdate (WindowPtr pWin); + +void +deleteCompOverlayClientsForScreen (ScreenPtr pScreen); + +int +ProcCompositeGetOverlayWindow (ClientPtr client); + +int +ProcCompositeReleaseOverlayWindow (ClientPtr client); + +int +SProcCompositeGetOverlayWindow (ClientPtr client); + +int +SProcCompositeReleaseOverlayWindow (ClientPtr client); + +WindowPtr +CompositeRealChildHead (WindowPtr pWin); + +int +DeleteWindowNoInputDevices(pointer value, XID wid); + +#endif /* _COMPINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/config.h (revision 51223) @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/config.h,v 1.21 2004/02/13 23:58:52 dawes Exp $ + */ + +#ifdef HAVE_CONFIG_H +# include "xorg-config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef sun +#undef index +#undef rindex +#include +#endif +#include + +#include + +#ifdef __UNIXOS2__ +#define strcasecmp stricmp +#define setenv putenv +#define PATH_MAX 260 +#endif + +/* Get PATH_MAX */ +#ifndef PATH_MAX +# if defined(_POSIX_SOURCE) +# include +# else +# define _POSIX_SOURCE +# include +# undef _POSIX_SOURCE +# endif +# ifndef PATH_MAX +# ifdef MAXPATHLEN +# define PATH_MAX MAXPATHLEN +# else +# define PATH_MAX 1024 +# endif +# endif +#endif + +#include +#include +#include +#include +#include +#include +#include + +#ifndef _xf86cfg_config_h +#define _xf86cfg_config_h + +/* Must match the offset in the xf86info structure at config.c, + * and is used also by interface.c + */ +#define MOUSE 0 +#define KEYBOARD 1 +#define CARD 2 +#define MONITOR 3 +#define SCREEN 4 +#define SERVER 5 + +#define UNUSED 0 +#define USED 1 + +#define CONFIG_LAYOUT 0 +#define CONFIG_SCREEN 1 +#define CONFIG_MODELINE 2 +#define CONFIG_ACCESSX 3 +extern int config_mode; + +#ifndef __UNIXOS2__ +#define CONFPATH "%A," "%R," \ + "/etc/X11/%R," "%P/etc/X11/%R," \ + "%E," "%F," \ + "/etc/X11/%F," "%P/etc/X11/%F," \ + "%D/%X," \ + "/etc/X11/%X-%M," "/etc/X11/%X," "/etc/%X," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#define USER_CONFPATH "/etc/X11/%S," "%P/etc/X11/%S," \ + "/etc/X11/%G," "%P/etc/X11/%G," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#else +#define CONFPATH "%&"XF86CONFIGDIR"/%R," "%&"XF86CONFIGDIR"/%X," \ + "%A," "%R," \ + "/etc/X11/%R," "%P/etc/X11/%R," \ + "%E," "%F," \ + "/etc/X11/%F," "%P/etc/X11/%F," \ + "%D/%X," \ + "/etc/X11/%X-%M," "/etc/X11/%X," "/etc/%X," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#define USER_CONFPATH "%&"XF86CONFIGDIR"/%X," "%&"XF86CONFIGDIR"/%X," \ + "/etc/X11/%S," "%P/etc/X11/%S," \ + "/etc/X11/%G," "%P/etc/X11/%G," \ + "%P/etc/X11/%X.%H," "%P/etc/X11/%X-%M," \ + "%P/etc/X11/%X," \ + "%P/lib/X11/%X.%H," "%P/lib/X11/%X-%M," \ + "%P/lib/X11/%X" +#endif + +/* + * Types + */ +typedef struct _XF86SetupInfo XF86SetupInfo; +typedef void (*XF86SetupFunction)(XF86SetupInfo*); + +typedef struct _XF86SetupFunctionList { + XF86SetupFunction *functions; + int num_functions; + int cur_function; +} XF86SetupFunctionList; + +struct _XF86SetupInfo { + int num_lists; + int cur_list; + XF86SetupFunctionList *lists; +}; + +typedef Bool (*ConfigCheckFunction)(void); + +typedef struct _xf86cfgDevice xf86cfgDevice; + +struct _xf86cfgDevice { + XtPointer config; + Widget widget; + int type, state, refcount; +}; + +typedef struct { + XF86ConfScreenPtr screen; + Widget widget; + int type, state, refcount; + xf86cfgDevice *card; + xf86cfgDevice *monitor; + short row, column; + XRectangle rect; + short rotate; +} xf86cfgScreen; + +/* this structure is used just to restore + properly the monitors layout in the + screen window configuration. + */ +typedef struct { + XF86ConfLayoutPtr layout; + xf86cfgScreen **screen; + XPoint *position; + int num_layouts; +} xf86cfgLayout; + +/* The vidmode extension usage is controlled by this structure. + * The information is read at startup, and added monitors cannot + * be configured, since they are not attached to a particular screen. + */ +typedef struct _xf86cfgVidMode xf86cfgVidmode; + +typedef struct { + XF86ConfLayoutPtr layout; /* current layout */ + Widget cpu; + xf86cfgLayout **layouts; + Cardinal num_layouts; + xf86cfgScreen **screens; + Cardinal num_screens; + xf86cfgDevice **devices; + Cardinal num_devices; + xf86cfgVidmode **vidmodes; + Cardinal num_vidmodes; +} xf86cfgComputer; + +/* + * Prototypes + */ +void StartConfig(void); +Bool ConfigLoop(ConfigCheckFunction); +void ConfigError(void); +void ChangeScreen(XF86ConfMonitorPtr, XF86ConfMonitorPtr, + XF86ConfDevicePtr, XF86ConfDevicePtr); +void SetTip(xf86cfgDevice*); +Bool startx(void); +void endx(void); +void startaccessx(void); +void ConfigCancelAction(Widget, XEvent*, String*, Cardinal*); +void ExpertConfigureStart(void); +void ExpertConfigureEnd(void); +void ExpertCloseAction(Widget, XEvent*, String*, Cardinal*); +void ExpertCallback(Widget, XtPointer, XtPointer); + +/* + * Initialization + */ +extern Widget toplevel, configp, current, back, next; +extern XtAppContext appcon; +extern XF86SetupInfo xf86info; +extern Widget ident_widget; +extern char *ident_string; +extern XF86ConfigPtr XF86Config; +extern char *XF86Config_path; +extern char *XF86Module_path; +extern char *XFree86_path; +extern char *XF86Font_path; +extern char *XF86RGB_path; +extern char *XFree86Dir; +extern xf86cfgComputer computer; +extern Atom wm_delete_window; +extern Display *DPY; +extern Pixmap menuPixmap; +#ifdef USE_MODULES +extern int nomodules; +#endif + +#endif /* _xf86cfg_config_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/configProcs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/configProcs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/configProcs.h (revision 51223) @@ -0,0 +1,132 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/configProcs.h,v 1.17 2003/08/24 17:37:08 dawes Exp $ */ +/* + * Copyright (c) 1997-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Private procs. Public procs are in xf86Parser.h and xf86Optrec.h */ + +/* Device.c */ +XF86ConfDevicePtr xf86parseDeviceSection(void); +void xf86printDeviceSection(FILE *cf, XF86ConfDevicePtr ptr); +void xf86freeDeviceList(XF86ConfDevicePtr ptr); +int xf86validateDevice(XF86ConfigPtr p); +/* Files.c */ +XF86ConfFilesPtr xf86parseFilesSection(void); +void xf86printFileSection(FILE *cf, XF86ConfFilesPtr ptr); +void xf86freeFiles(XF86ConfFilesPtr p); +/* Flags.c */ +XF86ConfFlagsPtr xf86parseFlagsSection(void); +void xf86printServerFlagsSection(FILE *f, XF86ConfFlagsPtr flags); +void xf86freeFlags(XF86ConfFlagsPtr flags); +/* Input.c */ +XF86ConfInputPtr xf86parseInputSection(void); +void xf86printInputSection(FILE *f, XF86ConfInputPtr ptr); +void xf86freeInputList(XF86ConfInputPtr ptr); +int xf86validateInput (XF86ConfigPtr p); +/* Keyboard.c */ +XF86ConfInputPtr xf86parseKeyboardSection(void); +/* Layout.c */ +XF86ConfLayoutPtr xf86parseLayoutSection(void); +void xf86printLayoutSection(FILE *cf, XF86ConfLayoutPtr ptr); +void xf86freeLayoutList(XF86ConfLayoutPtr ptr); +void xf86freeAdjacencyList(XF86ConfAdjacencyPtr ptr); +void xf86freeInputrefList(XF86ConfInputrefPtr ptr); +int xf86validateLayout(XF86ConfigPtr p); +/* Module.c */ +XF86LoadPtr xf86parseModuleSubSection(XF86LoadPtr head, char *name); +XF86ConfModulePtr xf86parseModuleSection(void); +void xf86printModuleSection(FILE *cf, XF86ConfModulePtr ptr); +XF86LoadPtr xf86addNewLoadDirective(XF86LoadPtr head, char *name, int type, XF86OptionPtr opts); +void xf86freeModules(XF86ConfModulePtr ptr); +/* Monitor.c */ +XF86ConfModeLinePtr xf86parseModeLine(void); +XF86ConfModeLinePtr xf86parseVerboseMode(void); +XF86ConfMonitorPtr xf86parseMonitorSection(void); +XF86ConfModesPtr xf86parseModesSection(void); +void xf86printMonitorSection(FILE *cf, XF86ConfMonitorPtr ptr); +void xf86printModesSection(FILE *cf, XF86ConfModesPtr ptr); +void xf86freeMonitorList(XF86ConfMonitorPtr ptr); +void xf86freeModesList(XF86ConfModesPtr ptr); +void xf86freeModeLineList(XF86ConfModeLinePtr ptr); +int xf86validateMonitor(XF86ConfigPtr p, XF86ConfScreenPtr screen); +/* Pointer.c */ +XF86ConfInputPtr xf86parsePointerSection(void); +/* Screen.c */ +XF86ConfDisplayPtr xf86parseDisplaySubSection(void); +XF86ConfScreenPtr xf86parseScreenSection(void); +void xf86printScreenSection(FILE *cf, XF86ConfScreenPtr ptr); +void xf86freeScreenList(XF86ConfScreenPtr ptr); +void xf86freeAdaptorLinkList(XF86ConfAdaptorLinkPtr ptr); +void xf86freeDisplayList(XF86ConfDisplayPtr ptr); +void xf86freeModeList(XF86ModePtr ptr); +int xf86validateScreen(XF86ConfigPtr p); +/* Vendor.c */ +XF86ConfVendorPtr xf86parseVendorSection(void); +XF86ConfVendSubPtr xf86parseVendorSubSection (void); +void xf86freeVendorList(XF86ConfVendorPtr p); +void xf86printVendorSection(FILE * cf, XF86ConfVendorPtr ptr); +void xf86freeVendorSubList (XF86ConfVendSubPtr ptr); +/* Video.c */ +XF86ConfVideoPortPtr xf86parseVideoPortSubSection(void); +XF86ConfVideoAdaptorPtr xf86parseVideoAdaptorSection(void); +void xf86printVideoAdaptorSection(FILE *cf, XF86ConfVideoAdaptorPtr ptr); +void xf86freeVideoAdaptorList(XF86ConfVideoAdaptorPtr ptr); +void xf86freeVideoPortList(XF86ConfVideoPortPtr ptr); +/* read.c */ +int xf86validateConfig(XF86ConfigPtr p); +/* scan.c */ +unsigned int xf86strToUL(char *str); +int xf86getToken(xf86ConfigSymTabRec *tab); +int xf86getSubToken(char **comment); +int xf86getSubTokenWithTab(char **comment, xf86ConfigSymTabRec *tab); +void xf86unGetToken(int token); +char *xf86tokenString(void); +void xf86parseError(char *format, ...); +void xf86parseWarning(char *format, ...); +void xf86validationError(char *format, ...); +void xf86setSection(char *section); +int xf86getStringToken(xf86ConfigSymTabRec *tab); +/* write.c */ +/* DRI.c */ +XF86ConfBuffersPtr xf86parseBuffers (void); +void xf86freeBuffersList (XF86ConfBuffersPtr ptr); +XF86ConfDRIPtr xf86parseDRISection (void); +void xf86printDRISection (FILE * cf, XF86ConfDRIPtr ptr); +void xf86freeDRI (XF86ConfDRIPtr ptr); +/* Extensions.c */ +XF86ConfExtensionsPtr xf86parseExtensionsSection (void); +void xf86printExtensionsSection (FILE * cf, XF86ConfExtensionsPtr ptr); +void xf86freeExtensions (XF86ConfExtensionsPtr ptr); + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef IN_XSERVER +/* Externally provided functions */ +void ErrorF(const char *f, ...); +void VErrorF(const char *f, va_list args); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cr.h (revision 51223) @@ -0,0 +1,62 @@ +/* + * Internal definitions of the Cocoa rootless implementation + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86$ */ + +#ifndef _CR_H +#define _CR_H + +#ifdef __OBJC__ +#import +#import "XView.h" +#else +typedef struct OpaqueNSWindow NSWindow; +typedef struct OpaqueXView XView; +#endif + +#undef BOOL +#define BOOL xBOOL +#include "screenint.h" +#include "window.h" +#undef BOOL + +// Predefined style for the window which is about to be framed +extern WindowPtr nextWindowToFrame; +extern unsigned int nextWindowStyle; + +typedef struct { + NSWindow *window; + XView *view; + GrafPtr port; + CGContextRef context; +} CRWindowRec, *CRWindowPtr; + +Bool CRInit(ScreenPtr pScreen); +void CRAppleWMInit(void); + +#endif /* _CR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursor.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XdotOrg: xserver/xorg/include/cursor.h,v 1.6 2005/08/24 11:18:30 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/include/cursor.h,v 1.6 2002/09/17 01:15:14 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: cursor.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef CURSOR_H +#define CURSOR_H + +#include "misc.h" +#include "screenint.h" +#include "window.h" + +#define NullCursor ((CursorPtr)NULL) + +/* Provide support for alpha composited cursors */ +#ifdef RENDER +#define ARGB_CURSOR +#endif + +typedef struct _Cursor *CursorPtr; +typedef struct _CursorMetric *CursorMetricPtr; + +extern CursorPtr rootCursor; + +extern int FreeCursor( + pointer /*pCurs*/, + XID /*cid*/); + +/* Quartz support on Mac OS X pulls in the QuickDraw + framework whose AllocCursor function conflicts here. */ +#ifdef __DARWIN__ +#define AllocCursor Darwin_X_AllocCursor +#endif +extern CursorPtr AllocCursor( + unsigned char* /*psrcbits*/, + unsigned char* /*pmaskbits*/, + CursorMetricPtr /*cm*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/); + +extern CursorPtr AllocCursorARGB( + unsigned char* /*psrcbits*/, + unsigned char* /*pmaskbits*/, + CARD32* /*argb*/, + CursorMetricPtr /*cm*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/); + +extern int AllocGlyphCursor( + Font /*source*/, + unsigned int /*sourceChar*/, + Font /*mask*/, + unsigned int /*maskChar*/, + unsigned /*foreRed*/, + unsigned /*foreGreen*/, + unsigned /*foreBlue*/, + unsigned /*backRed*/, + unsigned /*backGreen*/, + unsigned /*backBlue*/, + CursorPtr* /*ppCurs*/, + ClientPtr /*client*/); + +extern CursorPtr CreateRootCursor( + char* /*pfilename*/, + unsigned int /*glyph*/); + +extern int ServerBitsFromGlyph( + FontPtr /*pfont*/, + unsigned int /*ch*/, + register CursorMetricPtr /*cm*/, + unsigned char ** /*ppbits*/); + +extern Bool CursorMetricsFromGlyph( + FontPtr /*pfont*/, + unsigned /*ch*/, + CursorMetricPtr /*cm*/); + +extern void CheckCursorConfinement( + WindowPtr /*pWin*/); + +extern void NewCurrentScreen( + ScreenPtr /*newScreen*/, + int /*x*/, + int /*y*/); + +extern Bool PointerConfinedToScreen(void); + +extern void GetSpritePosition( + int * /*px*/, + int * /*py*/); + +#ifdef PANORAMIX +extern int XineramaGetCursorScreen(void); +#endif /* PANORAMIX */ + +#endif /* CURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursorstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursorstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cursorstr.h (revision 51223) @@ -0,0 +1,98 @@ +/* $Xorg: cursorstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/cursorstr.h,v 1.8 2002/11/30 06:21:51 keithp Exp $ */ + +#ifndef CURSORSTRUCT_H +#define CURSORSTRUCT_H + +#include "cursor.h" +/* + * device-independent cursor storage + */ + +/* + * source and mask point directly to the bits, which are in the server-defined + * bitmap format. + */ +typedef struct _CursorBits { + unsigned char *source; /* points to bits */ + unsigned char *mask; /* points to bits */ + Bool emptyMask; /* all zeros mask */ + unsigned short width, height, xhot, yhot; /* metrics */ + int refcnt; /* can be shared */ + pointer devPriv[MAXSCREENS]; /* set by pScr->RealizeCursor*/ +#ifdef ARGB_CURSOR + CARD32 *argb; /* full-color alpha blended */ +#endif +} CursorBits, *CursorBitsPtr; + +typedef struct _Cursor { + CursorBitsPtr bits; + unsigned short foreRed, foreGreen, foreBlue; /* device-independent color */ + unsigned short backRed, backGreen, backBlue; /* device-independent color */ + int refcnt; + pointer devPriv[MAXSCREENS]; /* set by pScr->RealizeCursor*/ +#ifdef XFIXES + CARD32 serialNumber; + Atom name; +#endif +} CursorRec; + +typedef struct _CursorMetric { + unsigned short width, height, xhot, yhot; +} CursorMetricRec; + +typedef struct { + int x, y; + ScreenPtr pScreen; +} HotSpot; + +#ifdef XEVIE +extern HotSpot xeviehot; +#endif +#endif /* CURSORSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cw.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cw.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/cw.h (revision 51223) @@ -0,0 +1,175 @@ +/* + * Copyright © 2004 Eric Anholt + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Eric Anholt not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Eric Anholt makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* $Header: /cvs/xorg/xc/programs/Xserver/miext/cw/cw.h,v 1.13 2005/10/02 08:28:26 anholt Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "gcstruct.h" +#include "picturestr.h" + +/* + * One of these structures is allocated per GC that gets used with a window with + * backing pixmap. + */ + +typedef struct { + GCPtr pBackingGC; /* Copy of the GC but with graphicsExposures + * set FALSE and the clientClip set to + * clip output to the valid regions of the + * backing pixmap. */ + unsigned long serialNumber; /* clientClip computed time */ + unsigned long stateChanges; /* changes in parent gc since last copy */ + GCOps *wrapOps; /* wrapped ops */ + GCFuncs *wrapFuncs; /* wrapped funcs */ +} cwGCRec, *cwGCPtr; + +extern int cwGCIndex; + +#define getCwGC(pGC) ((cwGCPtr)(pGC)->devPrivates[cwGCIndex].ptr) +#define setCwGC(pGC,p) ((pGC)->devPrivates[cwGCIndex].ptr = (pointer) (p)) + +/* + * One of these structures is allocated per Picture that gets used with a + * window with a backing pixmap + */ + +typedef struct { + PicturePtr pBackingPicture; + unsigned long serialNumber; + unsigned long stateChanges; +} cwPictureRec, *cwPicturePtr; + +#define getCwPicture(pPicture) \ + (pPicture->pDrawable ? (cwPicturePtr)(pPicture)->devPrivates[cwPictureIndex].ptr : 0) +#define setCwPicture(pPicture,p) ((pPicture)->devPrivates[cwPictureIndex].ptr = (pointer) (p)) + +extern int cwPictureIndex; + +extern int cwWindowIndex; + +#define cwWindowPrivate(pWindow) ((pWindow)->devPrivates[cwWindowIndex].ptr) +#define getCwPixmap(pWindow) ((PixmapPtr) cwWindowPrivate(pWindow)) +#define setCwPixmap(pWindow,pPixmap) (cwWindowPrivate(pWindow) = (pointer) (pPixmap)) + +#define cwDrawableIsRedirWindow(pDraw) \ + ((pDraw)->type == DRAWABLE_WINDOW && \ + getCwPixmap((WindowPtr) (pDraw)) != NULL) + +typedef struct { + /* + * screen func wrappers + */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + CreateGCProcPtr CreateGC; + + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + + GetWindowPixmapProcPtr GetWindowPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + +#ifdef RENDER + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; + + RasterizeTrapezoidProcPtr RasterizeTrapezoid; +#endif +} cwScreenRec, *cwScreenPtr; + +extern int cwScreenIndex; + +#define getCwScreen(pScreen) ((cwScreenPtr)(pScreen)->devPrivates[cwScreenIndex].ptr) +#define setCwScreen(pScreen,p) ((cwScreenPtr)(pScreen)->devPrivates[cwScreenIndex].ptr = (p)) + +#define CW_OFFSET_XYPOINTS(ppt, npt) do { \ + DDXPointPtr _ppt = (DDXPointPtr)(ppt); \ + int _i; \ + for (_i = 0; _i < npt; _i++) { \ + _ppt[_i].x += dst_off_x; \ + _ppt[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_RECTS(prect, nrect) do { \ + int _i; \ + for (_i = 0; _i < nrect; _i++) { \ + (prect)[_i].x += dst_off_x; \ + (prect)[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_ARCS(parc, narc) do { \ + int _i; \ + for (_i = 0; _i < narc; _i++) { \ + (parc)[_i].x += dst_off_x; \ + (parc)[_i].y += dst_off_y; \ + } \ +} while (0) + +#define CW_OFFSET_XY_DST(x, y) do { \ + (x) = (x) + dst_off_x; \ + (y) = (y) + dst_off_y; \ +} while (0) + +#define CW_OFFSET_XY_SRC(x, y) do { \ + (x) = (x) + src_off_x; \ + (y) = (y) + src_off_y; \ +} while (0) + +/* cw.c */ +DrawablePtr +cwGetBackingDrawable(DrawablePtr pDrawable, int *x_off, int *y_off); + +/* cw_render.c */ + +void +cwInitializeRender (ScreenPtr pScreen); + +void +cwFiniRender (ScreenPtr pScreen); + +/* cw.c */ + +void +miInitializeCompositeWrapper(ScreenPtr pScreen); + +/* Must be called before miInitializeCompositeWrapper */ +void +miDisableCompositeWrapper(ScreenPtr pScreen); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damage.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damage.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damage.h (revision 51223) @@ -0,0 +1,84 @@ +/* + * $Id: damage.h,v 1.3 2005/07/01 22:43:41 daniels Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGE_H_ +#define _DAMAGE_H_ + +typedef struct _damage *DamagePtr; + +typedef enum _damageReportLevel { + DamageReportRawRegion, + DamageReportDeltaRegion, + DamageReportBoundingBox, + DamageReportNonEmpty, + DamageReportNone +} DamageReportLevel; + +typedef void (*DamageReportFunc) (DamagePtr pDamage, RegionPtr pRegion, void *closure); +typedef void (*DamageDestroyFunc) (DamagePtr pDamage, void *closure); + +Bool +DamageSetup (ScreenPtr pScreen); + +DamagePtr +DamageCreate (DamageReportFunc damageReport, + DamageDestroyFunc damageDestroy, + DamageReportLevel damageLevel, + Bool isInternal, + ScreenPtr pScreen, + void * closure); + +void +DamageDrawInternal (ScreenPtr pScreen, Bool enable); + +void +DamageRegister (DrawablePtr pDrawable, + DamagePtr pDamage); + +void +DamageUnregister (DrawablePtr pDrawable, + DamagePtr pDamage); + +void +DamageDestroy (DamagePtr pDamage); + +Bool +DamageSubtract (DamagePtr pDamage, + const RegionPtr pRegion); + +void +DamageEmpty (DamagePtr pDamage); + +RegionPtr +DamageRegion (DamagePtr pDamage); + +void +DamageDamageRegion (DrawablePtr pDrawable, + const RegionPtr pRegion); + +#endif /* _DAMAGE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageext.h (revision 51223) @@ -0,0 +1,35 @@ +/* + * $Id: damageext.h,v 1.4 2005/07/01 22:43:06 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGEEXT_H_ +#define _DAMAGEEXT_H_ + +void +DamageExtensionInit(void); + +#endif /* _DAMAGEEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageextint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageextint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damageextint.h (revision 51223) @@ -0,0 +1,88 @@ +/* + * $Id: damageextint.h,v 1.5 2005/07/03 07:01:17 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGEEXTINT_H_ +#define _DAMAGEEXTINT_H_ + +#define NEED_EVENTS +#include +#include +#include "misc.h" +#include "os.h" +#include "dixstruct.h" +#include "extnsionst.h" +#include +#include "windowstr.h" +#include "selection.h" +#include "scrnintstr.h" +#include "damageext.h" +#include "damage.h" +#include "xfixes.h" + +extern unsigned char DamageReqCode; +extern int DamageEventBase; +extern int DamageErrorBase; +extern int DamageClientPrivateIndex; +extern RESTYPE DamageExtType; +extern RESTYPE DamageExtWinType; + +typedef struct _DamageClient { + CARD32 major_version; + CARD32 minor_version; + int critical; +} DamageClientRec, *DamageClientPtr; + +#define GetDamageClient(pClient) ((DamageClientPtr) (pClient)->devPrivates[DamageClientPrivateIndex].ptr) + +typedef struct _DamageExt { + DamagePtr pDamage; + DrawablePtr pDrawable; + DamageReportLevel level; + ClientPtr pClient; + XID id; +} DamageExtRec, *DamageExtPtr; + +extern int (*ProcDamageVector[/*XDamageNumberRequests*/])(ClientPtr); +extern int (*SProcDamageVector[/*XDamageNumberRequests*/])(ClientPtr); + +#define VERIFY_DAMAGEEXT(pDamageExt, rid, client, mode) { \ + pDamageExt = SecurityLookupIDByType (client, rid, DamageExtType, mode); \ + if (!pDamageExt) { \ + client->errorValue = rid; \ + return DamageErrorBase + BadDamage; \ + } \ +} + +void +SDamageNotifyEvent (xDamageNotifyEvent *from, + xDamageNotifyEvent *to); + +void +DamageExtSetCritical (ClientPtr pClient, Bool critical); + +#endif /* _DAMAGEEXTINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damagestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damagestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/damagestr.h (revision 51223) @@ -0,0 +1,114 @@ +/* + * $Id: damagestr.h,v 1.6 2005/07/03 07:02:01 daniels Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DAMAGESTR_H_ +#define _DAMAGESTR_H_ + +#include "damage.h" +#include "gcstruct.h" +#ifdef RENDER +# include "picturestr.h" +#endif + +typedef struct _damage { + DamagePtr pNext; + DamagePtr pNextWin; + RegionRec damage; + + DamageReportLevel damageLevel; + Bool isInternal; + void *closure; + Bool isWindow; + DrawablePtr pDrawable; + + DamageReportFunc damageReport; + DamageDestroyFunc damageDestroy; +} DamageRec; + +typedef struct _damageScrPriv { + int internalLevel; + + /* + * For DDXen which don't provide GetScreenPixmap, this provides + * a place to hook damage for windows on the screen + */ + DamagePtr pScreenDamage; + + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + CloseScreenProcPtr CloseScreen; + CreateGCProcPtr CreateGC; + DestroyPixmapProcPtr DestroyPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + DestroyWindowProcPtr DestroyWindow; +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif + BSFuncRec BackingStoreFuncs; +} DamageScrPrivRec, *DamageScrPrivPtr; + +typedef struct _damageGCPriv { + GCOps *ops; + GCFuncs *funcs; +} DamageGCPrivRec, *DamageGCPrivPtr; + +extern int damageScrPrivateIndex; +extern int damagePixPrivateIndex; +extern int damageGCPrivateIndex; +extern int damageWinPrivateIndex; + +#define damageGetScrPriv(pScr) \ + ((DamageScrPrivPtr) (pScr)->devPrivates[damageScrPrivateIndex].ptr) + +#define damageScrPriv(pScr) \ + DamageScrPrivPtr pScrPriv = damageGetScrPriv(pScr) + +#define damageGetPixPriv(pPix) \ + ((DamagePtr) (pPix)->devPrivates[damagePixPrivateIndex].ptr) + +#define damgeSetPixPriv(pPix,v) \ + ((pPix)->devPrivates[damagePixPrivateIndex].ptr = (pointer ) (v)) + +#define damagePixPriv(pPix) \ + DamagePtr pDamage = damageGetPixPriv(pPix) + +#define damageGetGCPriv(pGC) \ + ((DamageGCPrivPtr) (pGC)->devPrivates[damageGCPrivateIndex].ptr) + +#define damageGCPriv(pGC) \ + DamageGCPrivPtr pGCPriv = damageGetGCPriv(pGC) + +#define damageGetWinPriv(pWin) \ + ((DamagePtr) (pWin)->devPrivates[damageWinPrivateIndex].ptr) + +#define damageSetWinPriv(pWin,d) \ + ((pWin)->devPrivates[damageWinPrivateIndex].ptr = (d)) + +#endif /* _DAMAGESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwin.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwin.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwin.h (revision 51223) @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2001-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwin.h,v 1.20 2003/11/15 00:07:09 torrey Exp $ */ + +#ifndef _DARWIN_H +#define _DARWIN_H + +#include +#include "inputstr.h" +#include "scrnintstr.h" +#include + +typedef struct { + void *framebuffer; + int x; + int y; + int width; + int height; + int pitch; + int colorType; + int bitsPerPixel; + int colorBitsPerPixel; + int bitsPerComponent; +} DarwinFramebufferRec, *DarwinFramebufferPtr; + + +// From darwin.c +void DarwinPrintBanner(); +int DarwinParseModifierList(const char *constmodifiers); +void DarwinAdjustScreenOrigins(ScreenInfo *pScreenInfo); +void xf86SetRootClip (ScreenPtr pScreen, BOOL enable); + +// From darwinEvents.c +Bool DarwinEQInit(DevicePtr pKbd, DevicePtr pPtr); +void DarwinEQEnqueue(const xEvent *e); +void DarwinEQPointerPost(xEvent *e); +void DarwinEQSwitchScreen(ScreenPtr pScreen, Bool fromDIX); + +// From darwinKeyboard.c +int DarwinModifierNXKeyToNXKeycode(int key, int side); +void DarwinKeyboardInit(DeviceIntPtr pDev); +int DarwinModifierNXKeycodeToNXKey(unsigned char keycode, int *outSide); +int DarwinModifierNXKeyToNXMask(int key); +int DarwinModifierNXMaskToNXKey(int mask); +int DarwinModifierStringToNXKey(const char *string); + +// Mode specific functions +Bool DarwinModeAddScreen(int index, ScreenPtr pScreen); +Bool DarwinModeSetupScreen(int index, ScreenPtr pScreen); +void DarwinModeInitOutput(int argc,char **argv); +void DarwinModeInitInput(int argc, char **argv); +int DarwinModeProcessArgument(int argc, char *argv[], int i); +void DarwinModeProcessEvent(xEvent *xe); +void DarwinModeGiveUp(void); +void DarwinModeBell(int volume, DeviceIntPtr pDevice, pointer ctrl, int class); + + +#undef assert +#define assert(x) { if ((x) == 0) \ + FatalError("assert failed on line %d of %s!\n", __LINE__, __FILE__); } +#define kern_assert(x) { if ((x) != KERN_SUCCESS) \ + FatalError("assert failed on line %d of %s with kernel return 0x%x!\n", \ + __LINE__, __FILE__, x); } +#define SCREEN_PRIV(pScreen) \ + ((DarwinFramebufferPtr)pScreen->devPrivates[darwinScreenIndex].ptr) + + +#define MIN_KEYCODE XkbMinLegalKeyCode // unfortunately, this isn't 0... + + +/* + * Global variables from darwin.c + */ +extern int darwinScreenIndex; // index into pScreen.devPrivates +extern int darwinScreensFound; +extern io_connect_t darwinParamConnect; +extern int darwinEventReadFD; +extern int darwinEventWriteFD; +extern DeviceIntPtr darwinPointer; +extern DeviceIntPtr darwinKeyboard; + +// User preferences +extern int darwinMouseAccelChange; +extern int darwinFakeButtons; +extern int darwinFakeMouse2Mask; +extern int darwinFakeMouse3Mask; +extern int darwinSwapAltMeta; +extern char *darwinKeymapFile; +extern int darwinSyncKeymap; +extern unsigned int darwinDesiredWidth, darwinDesiredHeight; +extern int darwinDesiredDepth; +extern int darwinDesiredRefresh; + +// location of X11's (0,0) point in global screen coordinates +extern int darwinMainScreenX; +extern int darwinMainScreenY; + + +/* + * Special ddx events understood by the X server + */ +enum { + kXDarwinUpdateModifiers // update all modifier keys + = LASTEvent+1, // (from X.h list of event names) + kXDarwinUpdateButtons, // update state of mouse buttons 2 and up + kXDarwinScrollWheel, // scroll wheel event + + /* + * Quartz-specific events -- not used in IOKit mode + */ + kXDarwinActivate, // restore X drawing and cursor + kXDarwinDeactivate, // clip X drawing and switch to Aqua cursor + kXDarwinSetRootClip, // enable or disable drawing to the X screen + kXDarwinQuit, // kill the X server and release the display + kXDarwinReadPasteboard, // copy Mac OS X pasteboard into X cut buffer + kXDarwinWritePasteboard, // copy X cut buffer onto Mac OS X pasteboard + /* + * AppleWM events + */ + kXDarwinControllerNotify, // send an AppleWMControllerNotify event + kXDarwinPasteboardNotify, // notify the WM to copy or paste + /* + * Xplugin notification events + */ + kXDarwinDisplayChanged, // display configuration has changed + kXDarwinWindowState, // window visibility state has changed + kXDarwinWindowMoved // window has moved on screen +}; + +#endif /* _DARWIN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinClut8.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinClut8.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinClut8.h (revision 51223) @@ -0,0 +1,532 @@ +/* + * Darwin default 8-bit Colormap for StaticColor + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwinClut8.h,v 1.1.8.1 2003/03/04 01:31:43 torrey Exp $ */ + +#ifndef _DARWIN_CLUT8_ +#define _DARWIN_CLUT8_ + +#ifdef USE_NEW_CLUT + +static xColorItem darwinClut8[] = { + { 0, 0xffff, 0xffff, 0xffff, 0, 0 }, + { 1, 0xfefe, 0xfefe, 0xfefe, 0, 0 }, + { 2, 0xfdfd, 0xfdfd, 0xfdfd, 0, 0 }, + { 3, 0xb8b8, 0x2727, 0x2b2b, 0, 0 }, + { 4, 0xfcfc, 0xfcfc, 0xfcfc, 0, 0 }, + { 5, 0xffff, 0xffff, 0x0, 0, 0 }, + { 6, 0xfafa, 0xfafa, 0xfafa, 0, 0 }, + { 7, 0xf9f9, 0xf9f9, 0xf9f9, 0, 0 }, + { 8, 0xf8f8, 0xf8f8, 0xf8f8, 0, 0 }, + { 9, 0xf7f7, 0xf7f7, 0xf7f7, 0, 0 }, + { 10, 0xf6f6, 0xf6f6, 0xf6f6, 0, 0 }, + { 11, 0xf5f5, 0xf5f5, 0xf5f5, 0, 0 }, + { 12, 0xf4f4, 0xf4f4, 0xf4f4, 0, 0 }, + { 13, 0xf2f2, 0xf2f2, 0xf2f2, 0, 0 }, + { 14, 0xf1f1, 0xf1f1, 0xf1f1, 0, 0 }, + { 15, 0x0, 0x0, 0x0, 0, 0 }, + { 16, 0xefef, 0xefef, 0xefef, 0, 0 }, + { 17, 0xeeee, 0xeeee, 0xeeee, 0, 0 }, + { 18, 0xeded, 0xeded, 0xeded, 0, 0 }, + { 19, 0xebeb, 0xebeb, 0xebeb, 0, 0 }, + { 20, 0xe8e8, 0xe8e8, 0xe8e8, 0, 0 }, + { 21, 0xe7e7, 0xe7e7, 0xe7e7, 0, 0 }, + { 22, 0xc9c9, 0x3838, 0x3e3e, 0, 0 }, + { 23, 0xe5e5, 0xe5e5, 0xe5e5, 0, 0 }, + { 24, 0xffff, 0x0, 0xffff, 0, 0 }, + { 25, 0xfbfb, 0xfbfb, 0xfbfb, 0, 0 }, + { 26, 0xdede, 0x6c6c, 0x7272, 0, 0 }, + { 27, 0xe0e0, 0xe0e0, 0xe0e0, 0, 0 }, + { 28, 0xe8e8, 0x8686, 0x9090, 0, 0 }, + { 29, 0xdede, 0xdede, 0xdede, 0, 0 }, + { 30, 0xdddd, 0xdddd, 0xdddd, 0, 0 }, + { 31, 0xd3d3, 0x7e7e, 0x8d8d, 0, 0 }, + { 32, 0xd9d9, 0xd9d9, 0xd9d9, 0, 0 }, + { 33, 0xf3f3, 0x9696, 0xa6a6, 0, 0 }, + { 34, 0xb1b1, 0x1c1c, 0x3939, 0, 0 }, + { 35, 0xffff, 0x0, 0x0, 0, 0 }, + { 36, 0xbebe, 0x5e5e, 0x7272, 0, 0 }, + { 37, 0xd3d3, 0xd3d3, 0xd3d3, 0, 0 }, + { 38, 0xc6c6, 0x2e2e, 0x6767, 0, 0 }, + { 39, 0xd1d1, 0xd1d1, 0xd1d1, 0, 0 }, + { 40, 0xa3a3, 0x606, 0x4545, 0, 0 }, + { 41, 0xcece, 0xcece, 0xcece, 0, 0 }, + { 42, 0xcccc, 0xcccc, 0xffff, 0, 0 }, + { 43, 0xcccc, 0xcccc, 0xcccc, 0, 0 }, + { 44, 0xc6c6, 0x8f8f, 0xa7a7, 0, 0 }, + { 45, 0xe1e1, 0xd3d3, 0xd9d9, 0, 0 }, + { 46, 0xcece, 0x9e9e, 0xb4b4, 0, 0 }, + { 47, 0xcaca, 0xcaca, 0xcaca, 0, 0 }, + { 48, 0xbfbf, 0x3f3f, 0x7d7d, 0, 0 }, + { 49, 0xc9c9, 0xc9c9, 0xc9c9, 0, 0 }, + { 50, 0xf4f4, 0x8989, 0xbebe, 0, 0 }, + { 51, 0xc6c6, 0xc6c6, 0xc6c6, 0, 0 }, + { 52, 0xd6d6, 0x5151, 0x9797, 0, 0 }, + { 53, 0xc9c9, 0x2c2c, 0x8484, 0, 0 }, + { 54, 0x9696, 0x1a1a, 0x6a6a, 0, 0 }, + { 55, 0xc2c2, 0xc2c2, 0xc2c2, 0, 0 }, + { 56, 0xf3f3, 0x6f6f, 0xc6c6, 0, 0 }, + { 57, 0xe5e5, 0x4c4c, 0xbbbb, 0, 0 }, + { 58, 0xb7b7, 0x5a5a, 0x9c9c, 0, 0 }, + { 59, 0xbfbf, 0xbfbf, 0xbfbf, 0, 0 }, + { 60, 0xbebe, 0xbebe, 0xbebe, 0, 0 }, + { 61, 0xbdbd, 0xbdbd, 0xbdbd, 0, 0 }, + { 62, 0xb8b8, 0x2121, 0xa2a2, 0, 0 }, + { 63, 0xd3d3, 0x4444, 0xc0c0, 0, 0 }, + { 64, 0xc2c2, 0x6666, 0xb7b7, 0, 0 }, + { 65, 0xf4f4, 0x6666, 0xe6e6, 0, 0 }, + { 66, 0xfcfc, 0x7373, 0xfdfd, 0, 0 }, + { 67, 0xb9b9, 0xb9b9, 0xb9b9, 0, 0 }, + { 68, 0xeaea, 0xdfdf, 0xeaea, 0, 0 }, + { 69, 0xd4d4, 0x7171, 0xd5d5, 0, 0 }, + { 70, 0xf9f9, 0x8b8b, 0xffff, 0, 0 }, + { 71, 0xf5f5, 0xadad, 0xffff, 0, 0 }, + { 72, 0xbcbc, 0x9292, 0xc2c2, 0, 0 }, + { 73, 0xc7c7, 0x4f4f, 0xd9d9, 0, 0 }, + { 74, 0xa0a0, 0x4444, 0xafaf, 0, 0 }, + { 75, 0xc8c8, 0x8c8c, 0xd5d5, 0, 0 }, + { 76, 0xd7d7, 0x7474, 0xf7f7, 0, 0 }, + { 77, 0xb4b4, 0xb4b4, 0xb4b4, 0, 0 }, + { 78, 0xdada, 0x9595, 0xf9f9, 0, 0 }, + { 79, 0xeded, 0xcbcb, 0xffff, 0, 0 }, + { 80, 0xb2b2, 0xb2b2, 0xb2b2, 0, 0 }, + { 81, 0xa1a1, 0x6161, 0xd7d7, 0, 0 }, + { 82, 0xb2b2, 0x8585, 0xe2e2, 0, 0 }, + { 83, 0x5959, 0x2626, 0x9c9c, 0, 0 }, + { 84, 0x7c7c, 0x5151, 0xcccc, 0, 0 }, + { 85, 0xb0b0, 0xb0b0, 0xb0b0, 0, 0 }, + { 86, 0xb4b4, 0x8e8e, 0xfcfc, 0, 0 }, + { 87, 0xd5d5, 0xc0c0, 0xffff, 0, 0 }, + { 88, 0x5d5d, 0x3232, 0xcccc, 0, 0 }, + { 89, 0x7b7b, 0x5c5c, 0xe5e5, 0, 0 }, + { 90, 0xc0c0, 0xb0b0, 0xfdfd, 0, 0 }, + { 91, 0x6060, 0x5353, 0xadad, 0, 0 }, + { 92, 0x1212, 0xc0c, 0x7e7e, 0, 0 }, + { 93, 0x2e2e, 0x2929, 0x9999, 0, 0 }, + { 94, 0x7979, 0x7878, 0xe9e9, 0, 0 }, + { 95, 0x5b5b, 0x5c5c, 0xd0d0, 0, 0 }, + { 96, 0x6969, 0x6a6a, 0xcccc, 0, 0 }, + { 97, 0x9393, 0x9494, 0xf8f8, 0, 0 }, + { 98, 0x9292, 0x9292, 0xc3c3, 0, 0 }, + { 99, 0x4141, 0x4444, 0xbaba, 0, 0 }, + { 100, 0xa8a8, 0xabab, 0xffff, 0, 0 }, + { 101, 0xa3a3, 0xa3a3, 0xa3a3, 0, 0 }, + { 102, 0xdbdb, 0xdddd, 0xeaea, 0, 0 }, + { 103, 0x3131, 0x4949, 0xaaaa, 0, 0 }, + { 104, 0x7070, 0x8f8f, 0xf9f9, 0, 0 }, + { 105, 0x4848, 0x6666, 0xc1c1, 0, 0 }, + { 106, 0x5c5c, 0x7e7e, 0xe9e9, 0, 0 }, + { 107, 0xe2e2, 0xe5e5, 0xebeb, 0, 0 }, + { 108, 0xb0b0, 0xcdcd, 0xffff, 0, 0 }, + { 109, 0x6c6c, 0x8989, 0xb7b7, 0, 0 }, + { 110, 0x3434, 0x6565, 0xafaf, 0, 0 }, + { 111, 0x8c8c, 0xb9b9, 0xffff, 0, 0 }, + { 112, 0x3737, 0x7979, 0xd4d4, 0, 0 }, + { 113, 0x5a5a, 0x9999, 0xeaea, 0, 0 }, + { 114, 0xe0e, 0x4c4c, 0x9595, 0, 0 }, + { 115, 0x7979, 0xb9b9, 0xffff, 0, 0 }, + { 116, 0x8a8a, 0xa3a3, 0xbcbc, 0, 0 }, + { 117, 0x2020, 0x6161, 0x9d9d, 0, 0 }, + { 118, 0x8f8f, 0xaeae, 0xcaca, 0, 0 }, + { 119, 0xa0a, 0x6060, 0xa8a8, 0, 0 }, + { 120, 0x3f3f, 0x9494, 0xd9d9, 0, 0 }, + { 121, 0x6363, 0xb5b5, 0xf9f9, 0, 0 }, + { 122, 0xe2e2, 0xe8e8, 0xeded, 0, 0 }, + { 123, 0x2828, 0x6a6a, 0x9999, 0, 0 }, + { 124, 0x5555, 0xb2b2, 0xe7e7, 0, 0 }, + { 125, 0x3232, 0x8989, 0xa9a9, 0, 0 }, + { 126, 0xcfcf, 0xdada, 0xdede, 0, 0 }, + { 127, 0x2929, 0xa1a1, 0xc7c7, 0, 0 }, + { 128, 0x8686, 0xa9a9, 0xb4b4, 0, 0 }, + { 129, 0x0, 0x5f5f, 0x7979, 0, 0 }, + { 130, 0xc0c, 0x7777, 0x8e8e, 0, 0 }, + { 131, 0x1212, 0x8f8f, 0xabab, 0, 0 }, + { 132, 0x4141, 0xbaba, 0xd5d5, 0, 0 }, + { 133, 0x2424, 0x8282, 0x8383, 0, 0 }, + { 134, 0x2c2c, 0xc4c4, 0xc3c3, 0, 0 }, + { 135, 0x1a1a, 0xabab, 0xa6a6, 0, 0 }, + { 136, 0x4b4b, 0xa8a8, 0xa2a2, 0, 0 }, + { 137, 0xa0a, 0x9393, 0x8585, 0, 0 }, + { 138, 0xd0d, 0xa5a5, 0x9696, 0, 0 }, + { 139, 0x2626, 0xbcbc, 0xacac, 0, 0 }, + { 140, 0x404, 0x8181, 0x7272, 0, 0 }, + { 141, 0x1919, 0xb3b3, 0x8686, 0, 0 }, + { 142, 0x2929, 0xc1c1, 0x9494, 0, 0 }, + { 143, 0x2121, 0x9c9c, 0x7171, 0, 0 }, + { 144, 0x202, 0x8c8c, 0x5050, 0, 0 }, + { 145, 0x3535, 0xd0d0, 0x8989, 0, 0 }, + { 146, 0x4646, 0xa5a5, 0x7676, 0, 0 }, + { 147, 0x202, 0x7d7d, 0x3939, 0, 0 }, + { 148, 0x2929, 0xc9c9, 0x7171, 0, 0 }, + { 149, 0x5757, 0xd6d6, 0x8f8f, 0, 0 }, + { 150, 0xa2a2, 0xb5b5, 0xaaaa, 0, 0 }, + { 151, 0x101, 0x8888, 0x2a2a, 0, 0 }, + { 152, 0x7474, 0xbebe, 0x8a8a, 0, 0 }, + { 153, 0x1919, 0xb6b6, 0x4747, 0, 0 }, + { 154, 0x2d2d, 0xc6c6, 0x5151, 0, 0 }, + { 155, 0x3838, 0xdede, 0x5d5d, 0, 0 }, + { 156, 0x4c4c, 0xf4f4, 0x6f6f, 0, 0 }, + { 157, 0x9191, 0x9c9c, 0x9393, 0, 0 }, + { 158, 0x0, 0x8e8e, 0x1919, 0, 0 }, + { 159, 0x1010, 0xafaf, 0x2828, 0, 0 }, + { 160, 0xe3e3, 0xe3e3, 0xe3e3, 0, 0 }, + { 161, 0x808, 0xa1a1, 0x1a1a, 0, 0 }, + { 162, 0x5959, 0xc2c2, 0x6161, 0, 0 }, + { 163, 0xf0f0, 0xf0f0, 0xf0f0, 0, 0 }, + { 164, 0x8f8f, 0x9c9c, 0x9090, 0, 0 }, + { 165, 0x2323, 0xcece, 0x2a2a, 0, 0 }, + { 166, 0x1212, 0xbaba, 0x1717, 0, 0 }, + { 167, 0x101, 0x8a8a, 0x202, 0, 0 }, + { 168, 0x303, 0x9a9a, 0x202, 0, 0 }, + { 169, 0x4040, 0xe4e4, 0x4040, 0, 0 }, + { 170, 0x808, 0xb2b2, 0x505, 0, 0 }, + { 171, 0x1313, 0xcccc, 0xf0f, 0, 0 }, + { 172, 0x3636, 0xd7d7, 0x3232, 0, 0 }, + { 173, 0x2828, 0xe9e9, 0x1f1f, 0, 0 }, + { 174, 0x5353, 0xfbfb, 0x4c4c, 0, 0 }, + { 175, 0x6f6f, 0xafaf, 0x6a6a, 0, 0 }, + { 176, 0x7171, 0xe0e0, 0x6767, 0, 0 }, + { 177, 0x3232, 0xc0c0, 0x1212, 0, 0 }, + { 178, 0x2929, 0xa5a5, 0x808, 0, 0 }, + { 179, 0x5c5c, 0xdddd, 0x3535, 0, 0 }, + { 180, 0x0, 0xffff, 0xffff, 0, 0 }, + { 181, 0x6363, 0xc8c8, 0x4545, 0, 0 }, + { 182, 0x8686, 0xfdfd, 0x5b5b, 0, 0 }, + { 183, 0x7171, 0xf6f6, 0x3939, 0, 0 }, + { 184, 0x5555, 0xcccc, 0x1515, 0, 0 }, + { 185, 0x0, 0xffff, 0x0, 0, 0 }, + { 186, 0x9090, 0xcaca, 0x6e6e, 0, 0 }, + { 187, 0x4343, 0xa7a7, 0x101, 0, 0 }, + { 188, 0x8d8d, 0xe4e4, 0x3737, 0, 0 }, + { 189, 0xb3b3, 0xf0f0, 0x6464, 0, 0 }, + { 190, 0x8585, 0x8e8e, 0x7a7a, 0, 0 }, + { 191, 0xb0b0, 0xfafa, 0x4d4d, 0, 0 }, + { 192, 0xd6d6, 0xd6d6, 0xd6d6, 0, 0 }, + { 193, 0x8888, 0xd0d0, 0x1a1a, 0, 0 }, + { 194, 0x6a6a, 0xa7a7, 0x303, 0, 0 }, + { 195, 0x9898, 0xbfbf, 0x4141, 0, 0 }, + { 196, 0xcdcd, 0xf8f8, 0x5151, 0, 0 }, + { 197, 0x9494, 0xa4a4, 0x5555, 0, 0 }, + { 198, 0x9191, 0xb0b0, 0xa0a, 0, 0 }, + { 199, 0xdada, 0xf1f1, 0x3c3c, 0, 0 }, + { 200, 0xbaba, 0xcaca, 0x5353, 0, 0 }, + { 201, 0xb9b9, 0xc3c3, 0x2828, 0, 0 }, + { 202, 0xb1b1, 0xbaba, 0x1212, 0, 0 }, + { 203, 0xd2d2, 0xd9d9, 0x2626, 0, 0 }, + { 204, 0xe8e8, 0xecec, 0x2d2d, 0, 0 }, + { 205, 0x9898, 0x9696, 0x202, 0, 0 }, + { 206, 0xadad, 0xadad, 0x5c5c, 0, 0 }, + { 207, 0xe2e2, 0xd8d8, 0x3838, 0, 0 }, + { 208, 0xd9d9, 0xc4c4, 0x3838, 0, 0 }, + { 209, 0xa8a8, 0x9a9a, 0x5050, 0, 0 }, + { 210, 0x0, 0x0, 0xffff, 0, 0 }, + { 211, 0xbebe, 0xaeae, 0x5e5e, 0, 0 }, + { 212, 0x9a9a, 0x9898, 0x8e8e, 0, 0 }, + { 213, 0xacac, 0x8d8d, 0xd0d, 0, 0 }, + { 214, 0xc5c5, 0xa0a0, 0x2b2b, 0, 0 }, + { 215, 0xdbdb, 0xb5b5, 0x4848, 0, 0 }, + { 216, 0xdddd, 0x0, 0x0, 0, 0 }, + { 217, 0x9c9c, 0x6d6d, 0x303, 0, 0 }, + { 218, 0xd4d4, 0xa8a8, 0x4747, 0, 0 }, + { 219, 0xb7b7, 0x7171, 0x1717, 0, 0 }, + { 220, 0xdcdc, 0xa1a1, 0x5a5a, 0, 0 }, + { 221, 0xb9b9, 0x9c9c, 0x7c7c, 0, 0 }, + { 222, 0xb4b4, 0xabab, 0xa2a2, 0, 0 }, + { 223, 0x9e9e, 0x4b4b, 0x101, 0, 0 }, + { 224, 0xc8c8, 0x7878, 0x3535, 0, 0 }, + { 225, 0xd2d2, 0x8d8d, 0x5151, 0, 0 }, + { 226, 0xadad, 0x5252, 0xf0f, 0, 0 }, + { 227, 0x0, 0xbbbb, 0x0, 0, 0 }, + { 228, 0xb2b2, 0x6666, 0x3838, 0, 0 }, + { 229, 0xb1b1, 0xa6a6, 0x9f9f, 0, 0 }, + { 230, 0xb1b1, 0x8787, 0x6f6f, 0, 0 }, + { 231, 0xa4a4, 0x3434, 0x303, 0, 0 }, + { 232, 0xeeee, 0x9e9e, 0x8585, 0, 0 }, + { 233, 0xc9c9, 0x7373, 0x5a5a, 0, 0 }, + { 234, 0xe6e6, 0x9494, 0x7c7c, 0, 0 }, + { 235, 0xa9a9, 0x2222, 0x606, 0, 0 }, + { 236, 0xdbdb, 0x8787, 0x7474, 0, 0 }, + { 237, 0xb0b0, 0x2e2e, 0x1515, 0, 0 }, + { 238, 0xb7b7, 0x5a5a, 0x5050, 0, 0 }, + { 239, 0xb2b2, 0x4242, 0x3b3b, 0, 0 }, + { 240, 0xcdcd, 0x7373, 0x6e6e, 0, 0 }, + { 241, 0xd9d9, 0x5858, 0x5858, 0, 0 }, + { 242, 0xacac, 0xacac, 0xacac, 0, 0 }, + { 243, 0xa0a0, 0xa0a0, 0xa0a0, 0, 0 }, + { 244, 0x9a9a, 0x9a9a, 0x9a9a, 0, 0 }, + { 245, 0x9292, 0x9292, 0x9292, 0, 0 }, + { 246, 0x8e8e, 0x8e8e, 0x8e8e, 0, 0 }, + { 247, 0xbbbb, 0xbbbb, 0xbbbb, 0, 0 }, + { 248, 0x8181, 0x8181, 0x8181, 0, 0 }, + { 249, 0x8888, 0x8888, 0x8888, 0, 0 }, + { 250, 0x7777, 0x7777, 0x7777, 0, 0 }, + { 251, 0x5555, 0x5555, 0x5555, 0, 0 }, + { 252, 0x4444, 0x4444, 0x4444, 0, 0 }, + { 253, 0x2222, 0x2222, 0x2222, 0, 0 }, + { 254, 0x7b7b, 0x7b7b, 0x7b7b, 0, 0 }, + { 255, 0x0, 0x0, 0x0, 0, 0 }, +}; + +#else /* !USE_NEW_CLUT */ + +static xColorItem darwinClut8[] = { + { 0, 0x0000, 0x0000, 0x0000, 0, 0 }, + { 1, 0xffff, 0xffff, 0xcccc, 0, 0 }, + { 2, 0xffff, 0xffff, 0x9999, 0, 0 }, + { 3, 0xffff, 0xffff, 0x6666, 0, 0 }, + { 4, 0xffff, 0xffff, 0x3333, 0, 0 }, + { 5, 0xffff, 0xffff, 0x0000, 0, 0 }, + { 6, 0xffff, 0xcccc, 0xffff, 0, 0 }, + { 7, 0xffff, 0xcccc, 0xcccc, 0, 0 }, + { 8, 0xffff, 0xcccc, 0x9999, 0, 0 }, + { 9, 0xffff, 0xcccc, 0x6666, 0, 0 }, + { 10, 0xffff, 0xcccc, 0x3333, 0, 0 }, + { 11, 0xffff, 0xcccc, 0x0000, 0, 0 }, + { 12, 0xffff, 0x9999, 0xffff, 0, 0 }, + { 13, 0xffff, 0x9999, 0xcccc, 0, 0 }, + { 14, 0xffff, 0x9999, 0x9999, 0, 0 }, + { 15, 0xffff, 0x9999, 0x6666, 0, 0 }, + { 16, 0xffff, 0x9999, 0x3333, 0, 0 }, + { 17, 0xffff, 0x9999, 0x0000, 0, 0 }, + { 18, 0xffff, 0x6666, 0xffff, 0, 0 }, + { 19, 0xffff, 0x6666, 0xcccc, 0, 0 }, + { 20, 0xffff, 0x6666, 0x9999, 0, 0 }, + { 21, 0xffff, 0x6666, 0x6666, 0, 0 }, + { 22, 0xffff, 0x6666, 0x3333, 0, 0 }, + { 23, 0xffff, 0x6666, 0x0000, 0, 0 }, + { 24, 0xffff, 0x3333, 0xffff, 0, 0 }, + { 25, 0xffff, 0x3333, 0xcccc, 0, 0 }, + { 26, 0xffff, 0x3333, 0x9999, 0, 0 }, + { 27, 0xffff, 0x3333, 0x6666, 0, 0 }, + { 28, 0xffff, 0x3333, 0x3333, 0, 0 }, + { 29, 0xffff, 0x3333, 0x0000, 0, 0 }, + { 30, 0xffff, 0x0000, 0xffff, 0, 0 }, + { 31, 0xffff, 0x0000, 0xcccc, 0, 0 }, + { 32, 0xffff, 0x0000, 0x9999, 0, 0 }, + { 33, 0xffff, 0x0000, 0x6666, 0, 0 }, + { 34, 0xffff, 0x0000, 0x3333, 0, 0 }, + { 35, 0xffff, 0x0000, 0x0000, 0, 0 }, + { 36, 0xcccc, 0xffff, 0xffff, 0, 0 }, + { 37, 0xcccc, 0xffff, 0xcccc, 0, 0 }, + { 38, 0xcccc, 0xffff, 0x9999, 0, 0 }, + { 39, 0xcccc, 0xffff, 0x6666, 0, 0 }, + { 40, 0xcccc, 0xffff, 0x3333, 0, 0 }, + { 41, 0xcccc, 0xffff, 0x0000, 0, 0 }, + { 42, 0xcccc, 0xcccc, 0xffff, 0, 0 }, + { 43, 0xcccc, 0xcccc, 0xcccc, 0, 0 }, + { 44, 0xcccc, 0xcccc, 0x9999, 0, 0 }, + { 45, 0xcccc, 0xcccc, 0x6666, 0, 0 }, + { 46, 0xcccc, 0xcccc, 0x3333, 0, 0 }, + { 47, 0xcccc, 0xcccc, 0x0000, 0, 0 }, + { 48, 0xcccc, 0x9999, 0xffff, 0, 0 }, + { 49, 0xcccc, 0x9999, 0xcccc, 0, 0 }, + { 50, 0xcccc, 0x9999, 0x9999, 0, 0 }, + { 51, 0xcccc, 0x9999, 0x6666, 0, 0 }, + { 52, 0xcccc, 0x9999, 0x3333, 0, 0 }, + { 53, 0xcccc, 0x9999, 0x0000, 0, 0 }, + { 54, 0xcccc, 0x6666, 0xffff, 0, 0 }, + { 55, 0xcccc, 0x6666, 0xcccc, 0, 0 }, + { 56, 0xcccc, 0x6666, 0x9999, 0, 0 }, + { 57, 0xcccc, 0x6666, 0x6666, 0, 0 }, + { 58, 0xcccc, 0x6666, 0x3333, 0, 0 }, + { 59, 0xcccc, 0x6666, 0x0000, 0, 0 }, + { 60, 0xcccc, 0x3333, 0xffff, 0, 0 }, + { 61, 0xcccc, 0x3333, 0xcccc, 0, 0 }, + { 62, 0xcccc, 0x3333, 0x9999, 0, 0 }, + { 63, 0xcccc, 0x3333, 0x6666, 0, 0 }, + { 64, 0xcccc, 0x3333, 0x3333, 0, 0 }, + { 65, 0xcccc, 0x3333, 0x0000, 0, 0 }, + { 66, 0xcccc, 0x0000, 0xffff, 0, 0 }, + { 67, 0xcccc, 0x0000, 0xcccc, 0, 0 }, + { 68, 0xcccc, 0x0000, 0x9999, 0, 0 }, + { 69, 0xcccc, 0x0000, 0x6666, 0, 0 }, + { 70, 0xcccc, 0x0000, 0x3333, 0, 0 }, + { 71, 0xcccc, 0x0000, 0x0000, 0, 0 }, + { 72, 0x9999, 0xffff, 0xffff, 0, 0 }, + { 73, 0x9999, 0xffff, 0xcccc, 0, 0 }, + { 74, 0x9999, 0xffff, 0x9999, 0, 0 }, + { 75, 0x9999, 0xffff, 0x6666, 0, 0 }, + { 76, 0x9999, 0xffff, 0x3333, 0, 0 }, + { 77, 0x9999, 0xffff, 0x0000, 0, 0 }, + { 78, 0x9999, 0xcccc, 0xffff, 0, 0 }, + { 79, 0x9999, 0xcccc, 0xcccc, 0, 0 }, + { 80, 0x9999, 0xcccc, 0x9999, 0, 0 }, + { 81, 0x9999, 0xcccc, 0x6666, 0, 0 }, + { 82, 0x9999, 0xcccc, 0x3333, 0, 0 }, + { 83, 0x9999, 0xcccc, 0x0000, 0, 0 }, + { 84, 0x9999, 0x9999, 0xffff, 0, 0 }, + { 85, 0x9999, 0x9999, 0xcccc, 0, 0 }, + { 86, 0x9999, 0x9999, 0x9999, 0, 0 }, + { 87, 0x9999, 0x9999, 0x6666, 0, 0 }, + { 88, 0x9999, 0x9999, 0x3333, 0, 0 }, + { 89, 0x9999, 0x9999, 0x0000, 0, 0 }, + { 90, 0x9999, 0x6666, 0xffff, 0, 0 }, + { 91, 0x9999, 0x6666, 0xcccc, 0, 0 }, + { 92, 0x9999, 0x6666, 0x9999, 0, 0 }, + { 93, 0x9999, 0x6666, 0x6666, 0, 0 }, + { 94, 0x9999, 0x6666, 0x3333, 0, 0 }, + { 95, 0x9999, 0x6666, 0x0000, 0, 0 }, + { 96, 0x9999, 0x3333, 0xffff, 0, 0 }, + { 97, 0x9999, 0x3333, 0xcccc, 0, 0 }, + { 98, 0x9999, 0x3333, 0x9999, 0, 0 }, + { 99, 0x9999, 0x3333, 0x6666, 0, 0 }, + { 100, 0x9999, 0x3333, 0x3333, 0, 0 }, + { 101, 0x9999, 0x3333, 0x0000, 0, 0 }, + { 102, 0x9999, 0x0000, 0xffff, 0, 0 }, + { 103, 0x9999, 0x0000, 0xcccc, 0, 0 }, + { 104, 0x9999, 0x0000, 0x9999, 0, 0 }, + { 105, 0x9999, 0x0000, 0x6666, 0, 0 }, + { 106, 0x9999, 0x0000, 0x3333, 0, 0 }, + { 107, 0x9999, 0x0000, 0x0000, 0, 0 }, + { 108, 0x6666, 0xffff, 0xffff, 0, 0 }, + { 109, 0x6666, 0xffff, 0xcccc, 0, 0 }, + { 110, 0x6666, 0xffff, 0x9999, 0, 0 }, + { 111, 0x6666, 0xffff, 0x6666, 0, 0 }, + { 112, 0x6666, 0xffff, 0x3333, 0, 0 }, + { 113, 0x6666, 0xffff, 0x0000, 0, 0 }, + { 114, 0x6666, 0xcccc, 0xffff, 0, 0 }, + { 115, 0x6666, 0xcccc, 0xcccc, 0, 0 }, + { 116, 0x6666, 0xcccc, 0x9999, 0, 0 }, + { 117, 0x6666, 0xcccc, 0x6666, 0, 0 }, + { 118, 0x6666, 0xcccc, 0x3333, 0, 0 }, + { 119, 0x6666, 0xcccc, 0x0000, 0, 0 }, + { 120, 0x6666, 0x9999, 0xffff, 0, 0 }, + { 121, 0x6666, 0x9999, 0xcccc, 0, 0 }, + { 122, 0x6666, 0x9999, 0x9999, 0, 0 }, + { 123, 0x6666, 0x9999, 0x6666, 0, 0 }, + { 124, 0x6666, 0x9999, 0x3333, 0, 0 }, + { 125, 0x6666, 0x9999, 0x0000, 0, 0 }, + { 126, 0x6666, 0x6666, 0xffff, 0, 0 }, + { 127, 0x6666, 0x6666, 0xcccc, 0, 0 }, + { 128, 0x6666, 0x6666, 0x9999, 0, 0 }, + { 129, 0x6666, 0x6666, 0x6666, 0, 0 }, + { 130, 0x6666, 0x6666, 0x3333, 0, 0 }, + { 131, 0x6666, 0x6666, 0x0000, 0, 0 }, + { 132, 0x6666, 0x3333, 0xffff, 0, 0 }, + { 133, 0x6666, 0x3333, 0xcccc, 0, 0 }, + { 134, 0x6666, 0x3333, 0x9999, 0, 0 }, + { 135, 0x6666, 0x3333, 0x6666, 0, 0 }, + { 136, 0x6666, 0x3333, 0x3333, 0, 0 }, + { 137, 0x6666, 0x3333, 0x0000, 0, 0 }, + { 138, 0x6666, 0x0000, 0xffff, 0, 0 }, + { 139, 0x6666, 0x0000, 0xcccc, 0, 0 }, + { 140, 0x6666, 0x0000, 0x9999, 0, 0 }, + { 141, 0x6666, 0x0000, 0x6666, 0, 0 }, + { 142, 0x6666, 0x0000, 0x3333, 0, 0 }, + { 143, 0x6666, 0x0000, 0x0000, 0, 0 }, + { 144, 0x3333, 0xffff, 0xffff, 0, 0 }, + { 145, 0x3333, 0xffff, 0xcccc, 0, 0 }, + { 146, 0x3333, 0xffff, 0x9999, 0, 0 }, + { 147, 0x3333, 0xffff, 0x6666, 0, 0 }, + { 148, 0x3333, 0xffff, 0x3333, 0, 0 }, + { 149, 0x3333, 0xffff, 0x0000, 0, 0 }, + { 150, 0x3333, 0xcccc, 0xffff, 0, 0 }, + { 151, 0x3333, 0xcccc, 0xcccc, 0, 0 }, + { 152, 0x3333, 0xcccc, 0x9999, 0, 0 }, + { 153, 0x3333, 0xcccc, 0x6666, 0, 0 }, + { 154, 0x3333, 0xcccc, 0x3333, 0, 0 }, + { 155, 0x3333, 0xcccc, 0x0000, 0, 0 }, + { 156, 0x3333, 0x9999, 0xffff, 0, 0 }, + { 157, 0x3333, 0x9999, 0xcccc, 0, 0 }, + { 158, 0x3333, 0x9999, 0x9999, 0, 0 }, + { 159, 0x3333, 0x9999, 0x6666, 0, 0 }, + { 160, 0x3333, 0x9999, 0x3333, 0, 0 }, + { 161, 0x3333, 0x9999, 0x0000, 0, 0 }, + { 162, 0x3333, 0x6666, 0xffff, 0, 0 }, + { 163, 0x3333, 0x6666, 0xcccc, 0, 0 }, + { 164, 0x3333, 0x6666, 0x9999, 0, 0 }, + { 165, 0x3333, 0x6666, 0x6666, 0, 0 }, + { 166, 0x3333, 0x6666, 0x3333, 0, 0 }, + { 167, 0x3333, 0x6666, 0x0000, 0, 0 }, + { 168, 0x3333, 0x3333, 0xffff, 0, 0 }, + { 169, 0x3333, 0x3333, 0xcccc, 0, 0 }, + { 170, 0x3333, 0x3333, 0x9999, 0, 0 }, + { 171, 0x3333, 0x3333, 0x6666, 0, 0 }, + { 172, 0x3333, 0x3333, 0x3333, 0, 0 }, + { 173, 0x3333, 0x3333, 0x0000, 0, 0 }, + { 174, 0x3333, 0x0000, 0xffff, 0, 0 }, + { 175, 0x3333, 0x0000, 0xcccc, 0, 0 }, + { 176, 0x3333, 0x0000, 0x9999, 0, 0 }, + { 177, 0x3333, 0x0000, 0x6666, 0, 0 }, + { 178, 0x3333, 0x0000, 0x3333, 0, 0 }, + { 179, 0x3333, 0x0000, 0x0000, 0, 0 }, + { 180, 0x0000, 0xffff, 0xffff, 0, 0 }, + { 181, 0x0000, 0xffff, 0xcccc, 0, 0 }, + { 182, 0x0000, 0xffff, 0x9999, 0, 0 }, + { 183, 0x0000, 0xffff, 0x6666, 0, 0 }, + { 184, 0x0000, 0xffff, 0x3333, 0, 0 }, + { 185, 0x0000, 0xffff, 0x0000, 0, 0 }, + { 186, 0x0000, 0xcccc, 0xffff, 0, 0 }, + { 187, 0x0000, 0xcccc, 0xcccc, 0, 0 }, + { 188, 0x0000, 0xcccc, 0x9999, 0, 0 }, + { 189, 0x0000, 0xcccc, 0x6666, 0, 0 }, + { 190, 0x0000, 0xcccc, 0x3333, 0, 0 }, + { 191, 0x0000, 0xcccc, 0x0000, 0, 0 }, + { 192, 0x0000, 0x9999, 0xffff, 0, 0 }, + { 193, 0x0000, 0x9999, 0xcccc, 0, 0 }, + { 194, 0x0000, 0x9999, 0x9999, 0, 0 }, + { 195, 0x0000, 0x9999, 0x6666, 0, 0 }, + { 196, 0x0000, 0x9999, 0x3333, 0, 0 }, + { 197, 0x0000, 0x9999, 0x0000, 0, 0 }, + { 198, 0x0000, 0x6666, 0xffff, 0, 0 }, + { 199, 0x0000, 0x6666, 0xcccc, 0, 0 }, + { 200, 0x0000, 0x6666, 0x9999, 0, 0 }, + { 201, 0x0000, 0x6666, 0x6666, 0, 0 }, + { 202, 0x0000, 0x6666, 0x3333, 0, 0 }, + { 203, 0x0000, 0x6666, 0x0000, 0, 0 }, + { 204, 0x0000, 0x3333, 0xffff, 0, 0 }, + { 205, 0x0000, 0x3333, 0xcccc, 0, 0 }, + { 206, 0x0000, 0x3333, 0x9999, 0, 0 }, + { 207, 0x0000, 0x3333, 0x6666, 0, 0 }, + { 208, 0x0000, 0x3333, 0x3333, 0, 0 }, + { 209, 0x0000, 0x3333, 0x0000, 0, 0 }, + { 210, 0x0000, 0x0000, 0xffff, 0, 0 }, + { 211, 0x0000, 0x0000, 0xcccc, 0, 0 }, + { 212, 0x0000, 0x0000, 0x9999, 0, 0 }, + { 213, 0x0000, 0x0000, 0x6666, 0, 0 }, + { 214, 0x0000, 0x0000, 0x3333, 0, 0 }, + { 215, 0xeeee, 0x0000, 0x0000, 0, 0 }, + { 216, 0xdddd, 0x0000, 0x0000, 0, 0 }, + { 217, 0xbbbb, 0x0000, 0x0000, 0, 0 }, + { 218, 0xaaaa, 0x0000, 0x0000, 0, 0 }, + { 219, 0x8888, 0x0000, 0x0000, 0, 0 }, + { 220, 0x7777, 0x0000, 0x0000, 0, 0 }, + { 221, 0x5555, 0x0000, 0x0000, 0, 0 }, + { 222, 0x4444, 0x0000, 0x0000, 0, 0 }, + { 223, 0x2222, 0x0000, 0x0000, 0, 0 }, + { 224, 0x1111, 0x0000, 0x0000, 0, 0 }, + { 225, 0x0000, 0xeeee, 0x0000, 0, 0 }, + { 226, 0x0000, 0xdddd, 0x0000, 0, 0 }, + { 227, 0x0000, 0xbbbb, 0x0000, 0, 0 }, + { 228, 0x0000, 0xaaaa, 0x0000, 0, 0 }, + { 229, 0x0000, 0x8888, 0x0000, 0, 0 }, + { 230, 0x0000, 0x7777, 0x0000, 0, 0 }, + { 231, 0x0000, 0x5555, 0x0000, 0, 0 }, + { 232, 0x0000, 0x4444, 0x0000, 0, 0 }, + { 233, 0x0000, 0x2222, 0x0000, 0, 0 }, + { 234, 0x0000, 0x1111, 0x0000, 0, 0 }, + { 235, 0x0000, 0x0000, 0xeeee, 0, 0 }, + { 236, 0x0000, 0x0000, 0xdddd, 0, 0 }, + { 237, 0x0000, 0x0000, 0xbbbb, 0, 0 }, + { 238, 0x0000, 0x0000, 0xaaaa, 0, 0 }, + { 239, 0x0000, 0x0000, 0x8888, 0, 0 }, + { 240, 0x0000, 0x0000, 0x7777, 0, 0 }, + { 241, 0x0000, 0x0000, 0x5555, 0, 0 }, + { 242, 0x0000, 0x0000, 0x4444, 0, 0 }, + { 243, 0x0000, 0x0000, 0x2222, 0, 0 }, + { 244, 0x0000, 0x0000, 0x1111, 0, 0 }, + { 245, 0xeeee, 0xeeee, 0xeeee, 0, 0 }, + { 246, 0xdddd, 0xdddd, 0xdddd, 0, 0 }, + { 247, 0xbbbb, 0xbbbb, 0xbbbb, 0, 0 }, + { 248, 0xaaaa, 0xaaaa, 0xaaaa, 0, 0 }, + { 249, 0x8888, 0x8888, 0x8888, 0, 0 }, + { 250, 0x7777, 0x7777, 0x7777, 0, 0 }, + { 251, 0x5555, 0x5555, 0x5555, 0, 0 }, + { 252, 0x4444, 0x4444, 0x4444, 0, 0 }, + { 253, 0x2222, 0x2222, 0x2222, 0, 0 }, + { 254, 0x1111, 0x1111, 0x1111, 0, 0 }, + { 255, 0xffff, 0xffff, 0xffff, 0, 0 } +}; +#endif /* USE_NEW_CLUT */ + +#endif /* _DARWIN_CLUT8_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinKeyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinKeyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/darwinKeyboard.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/darwinKeyboard.c,v 1.18 2003/05/14 05:27:55 torrey Exp $ */ + +#ifndef DARWIN_KEYBOARD_H +#define DARWIN_KEYBOARD_H 1 + +#define XK_TECHNICAL // needed to get XK_Escape +#define XK_PUBLISHING +#include "keysym.h" +#include "inputstr.h" + +// Each key can generate 4 glyphs. They are, in order: +// unshifted, shifted, modeswitch unshifted, modeswitch shifted +#define GLYPHS_PER_KEY 4 +#define NUM_KEYCODES 248 // NX_NUMKEYCODES might be better +#define MAX_KEYCODE NUM_KEYCODES + MIN_KEYCODE - 1 + +typedef struct darwinKeyboardInfo_struct { + CARD8 modMap[MAP_LENGTH]; + KeySym keyMap[MAP_LENGTH * GLYPHS_PER_KEY]; + unsigned char modifierKeycodes[32][2]; +} darwinKeyboardInfo; + +void DarwinKeyboardReload(DeviceIntPtr pDev); +unsigned int DarwinModeSystemKeymapSeed(void); +Bool DarwinModeReadSystemKeymap(darwinKeyboardInfo *info); + +#endif /* DARWIN_KEYBOARD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dbestruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dbestruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dbestruct.h (revision 51223) @@ -0,0 +1,237 @@ +/* $Xorg: dbestruct.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for DIX-related DBE + * + *****************************************************************************/ +/* $XFree86$ */ + +#ifndef DBE_STRUCT_H +#define DBE_STRUCT_H + + +/* INCLUDES */ + +#define NEED_DBE_PROTOCOL +#include +#include "windowstr.h" + + +/* DEFINES */ + +#define DBE_SCREEN_PRIV(pScreen) \ + ((dbeScreenPrivIndex < 0) ? \ + NULL : \ + ((DbeScreenPrivPtr)((pScreen)->devPrivates[dbeScreenPrivIndex].ptr))) + +#define DBE_SCREEN_PRIV_FROM_DRAWABLE(pDrawable) \ + DBE_SCREEN_PRIV((pDrawable)->pScreen) + +#define DBE_SCREEN_PRIV_FROM_WINDOW_PRIV(pDbeWindowPriv) \ + DBE_SCREEN_PRIV((pDbeWindowPriv)->pWindow->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_WINDOW(pWindow) \ + DBE_SCREEN_PRIV((pWindow)->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_PIXMAP(pPixmap) \ + DBE_SCREEN_PRIV((pPixmap)->drawable.pScreen) + +#define DBE_SCREEN_PRIV_FROM_GC(pGC)\ + DBE_SCREEN_PRIV((pGC)->pScreen) + +#define DBE_WINDOW_PRIV(pWindow)\ + ((dbeWindowPrivIndex < 0) ? \ + NULL : \ + ((DbeWindowPrivPtr)(pWindow->devPrivates[dbeWindowPrivIndex].ptr))) + +/* Initial size of the buffer ID array in the window priv. */ +#define DBE_INIT_MAX_IDS 2 + +/* Reallocation increment for the buffer ID array. */ +#define DBE_INCR_MAX_IDS 4 + +/* Marker for free elements in the buffer ID array. */ +#define DBE_FREE_ID_ELEMENT 0 + + +/* TYPEDEFS */ + +/* Record used to pass swap information between DIX and DDX swapping + * procedures. + */ +typedef struct _DbeSwapInfoRec +{ + WindowPtr pWindow; + unsigned char swapAction; + +} DbeSwapInfoRec, *DbeSwapInfoPtr; + +/* + ****************************************************************************** + ** Per-window data + ****************************************************************************** + */ + +typedef struct _DbeWindowPrivRec +{ + /* A pointer to the window with which the DBE window private (buffer) is + * associated. + */ + WindowPtr pWindow; + + /* Last known swap action for this buffer. Legal values for this field + * are XdbeUndefined, XdbeBackground, XdbeUntouched, and XdbeCopied. + */ + unsigned char swapAction; + + /* Last known buffer size. + */ + unsigned short width, height; + + /* Coordinates used for static gravity when the window is positioned. + */ + short x, y; + + /* Number of XIDs associated with this buffer. + */ + int nBufferIDs; + + /* Capacity of the current buffer ID array, IDs. */ + int maxAvailableIDs; + + /* Pointer to the array of buffer IDs. This initially points to initIDs. + * When the static limit of the initIDs array is reached, the array is + * reallocated and this pointer is set to the new array instead of initIDs. + */ + XID *IDs; + + /* Initial array of buffer IDs. We are defining the XID array within the + * window priv to optimize for data locality. In most cases, only one + * buffer will be associated with a window. Having the array declared + * here can prevent us from accessing the data in another memory page, + * possibly resulting in a page swap and loss of performance. Initially we + * will use this array to store buffer IDs. For situations where we have + * more IDs than can fit in this static array, we will allocate a larger + * array to use, possibly suffering a performance loss. + */ + XID initIDs[DBE_INIT_MAX_IDS]; + + /* Device-specific private information. + */ + DevUnion *devPrivates; + +} DbeWindowPrivRec, *DbeWindowPrivPtr; + + +/* + ****************************************************************************** + ** Per-screen data + ****************************************************************************** + */ + +typedef struct _DbeScreenPrivRec +{ + /* Info for creating window privs */ + int winPrivPrivLen; /* Length of privs in DbeWindowPrivRec */ + unsigned int *winPrivPrivSizes; /* Array of private record sizes */ + unsigned int totalWinPrivSize; /* PrivRec + size of all priv priv ptrs */ + + /* Resources created by DIX to be used by DDX */ + RESTYPE dbeDrawableResType; + RESTYPE dbeWindowPrivResType; + + /* Private indices created by DIX to be used by DDX */ + int dbeScreenPrivIndex; + int dbeWindowPrivIndex; + + /* Wrapped functions + * It is the responsibilty of the DDX layer to wrap PositionWindow(). + * DbeExtensionInit wraps DestroyWindow(). + */ + PositionWindowProcPtr PositionWindow; + DestroyWindowProcPtr DestroyWindow; + + /* Per-screen DIX routines */ + Bool (*SetupBackgroundPainter)( + WindowPtr /*pWin*/, + GCPtr /*pGC*/ +); + DbeWindowPrivPtr (*AllocWinPriv)( + ScreenPtr /*pScreen*/ +); + int (*AllocWinPrivPrivIndex)( + void +); + Bool (*AllocWinPrivPriv)( + ScreenPtr /*pScreen*/, + int /*index*/, + unsigned /*amount*/ +); + + /* Per-screen DDX routines */ + Bool (*GetVisualInfo)( + ScreenPtr /*pScreen*/, + XdbeScreenVisualInfo * /*pVisInfo*/ +); + int (*AllocBackBufferName)( + WindowPtr /*pWin*/, + XID /*bufId*/, + int /*swapAction*/ +); + int (*SwapBuffers)( + ClientPtr /*client*/, + int * /*pNumWindows*/, + DbeSwapInfoPtr /*swapInfo*/ +); + void (*BeginIdiom)( + ClientPtr /*client*/ +); + void (*EndIdiom)( + ClientPtr /*client*/ +); + void (*WinPrivDelete)( + DbeWindowPrivPtr /*pDbeWindowPriv*/, + XID /*bufId*/ +); + void (*ResetProc)( + ScreenPtr /*pScreen*/ +); + void (*ValidateBuffer)( + WindowPtr /*pWin*/, + XID /*bufId*/, + Bool /*dstbuffer*/ +); + + /* Device-specific private information. + */ + DevUnion *devPrivates; + +} DbeScreenPrivRec, *DbeScreenPrivPtr; + +#endif /* DBE_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ddcPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ddcPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ddcPriv.h (revision 51223) @@ -0,0 +1,9 @@ +extern unsigned char *GetEDID_DDC1( + unsigned int * +); + +extern int DDC_checksum( + unsigned char *, + int +); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/debug.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/debug.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/debug.h (revision 51223) @@ -0,0 +1,210 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() +# define CHECK_SP_ACCESS() +# define CHECK_MEM_ACCESS() +# define CHECK_DATA_ACCESS() +#endif + +#ifdef DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef DEBUG +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (char *x); +extern void x86emu_decode_printf2 (char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/decode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/decode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/decode.h (revision 51223) @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +u32 decode_rm00_address(int rm); +u32 decode_rm01_address(int rm); +u32 decode_rm10_address(int rm); +u32 decode_sib_address(int sib, int mod); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/devbell.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/devbell.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/devbell.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DEVBELL_H +#define DEVBELL_H 1 + +int SProcXDeviceBell(ClientPtr /* client */ + ); + +int ProcXDeviceBell(ClientPtr /* client */ + ); + +#endif /* DEVBELL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dgaproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dgaproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dgaproc.h (revision 51223) @@ -0,0 +1,144 @@ +/* $XFree86: xc/programs/Xserver/Xext/dgaproc.h,v 1.21 2000/06/30 19:06:54 keithp Exp $ */ + +#ifndef __DGAPROC_H +#define __DGAPROC_H + +#include +#include "pixmap.h" + +#define DGA_CONCURRENT_ACCESS 0x00000001 +#define DGA_FILL_RECT 0x00000002 +#define DGA_BLIT_RECT 0x00000004 +#define DGA_BLIT_RECT_TRANS 0x00000008 +#define DGA_PIXMAP_AVAILABLE 0x00000010 + +#define DGA_INTERLACED 0x00010000 +#define DGA_DOUBLESCAN 0x00020000 + +#define DGA_FLIP_IMMEDIATE 0x00000001 +#define DGA_FLIP_RETRACE 0x00000002 + +#define DGA_COMPLETED 0x00000000 +#define DGA_PENDING 0x00000001 + +#define DGA_NEED_ROOT 0x00000001 + +typedef struct { + int num; /* A unique identifier for the mode (num > 0) */ + char *name; /* name of mode given in the XF86Config */ + int VSync_num; + int VSync_den; + int flags; /* DGA_CONCURRENT_ACCESS, etc... */ + int imageWidth; /* linear accessible portion (pixels) */ + int imageHeight; + int pixmapWidth; /* Xlib accessible portion (pixels) */ + int pixmapHeight; /* both fields ignored if no concurrent access */ + int bytesPerScanline; + int byteOrder; /* MSBFirst, LSBFirst */ + int depth; + int bitsPerPixel; + unsigned long red_mask; + unsigned long green_mask; + unsigned long blue_mask; + short visualClass; + int viewportWidth; + int viewportHeight; + int xViewportStep; /* viewport position granularity */ + int yViewportStep; + int maxViewportX; /* max viewport origin */ + int maxViewportY; + int viewportFlags; /* types of page flipping possible */ + int offset; + int reserved1; + int reserved2; +} XDGAModeRec, *XDGAModePtr; + +/* DDX interface */ + +int +DGASetMode( + int Index, + int num, + XDGAModePtr mode, + PixmapPtr *pPix +); + +void +DGASetInputMode( + int Index, + Bool keyboard, + Bool mouse +); + +void +DGASelectInput( + int Index, + ClientPtr client, + long mask +); + +Bool DGAAvailable(int Index); +Bool DGAActive(int Index); +void DGAShutdown(void); +void DGAInstallCmap(ColormapPtr cmap); +int DGAGetViewportStatus(int Index); +int DGASync(int Index); + +int +DGAFillRect( + int Index, + int x, int y, int w, int h, + unsigned long color +); + +int +DGABlitRect( + int Index, + int srcx, int srcy, + int w, int h, + int dstx, int dsty +); + +int +DGABlitTransRect( + int Index, + int srcx, int srcy, + int w, int h, + int dstx, int dsty, + unsigned long color +); + +int +DGASetViewport( + int Index, + int x, int y, + int mode +); + +int DGAGetModes(int Index); +int DGAGetOldDGAMode(int Index); + +int DGAGetModeInfo(int Index, XDGAModePtr mode, int num); + +Bool DGAVTSwitch(void); +Bool DGAStealMouseEvent(int Index, xEvent *e, int dx, int dy); +Bool DGAStealKeyEvent(int Index, xEvent *e); +Bool DGAIsDgaEvent (xEvent *e); + +Bool DGADeliverEvent (ScreenPtr pScreen, xEvent *e); + +Bool DGAOpenFramebuffer(int Index, char **name, unsigned char **mem, + int *size, int *offset, int *flags); +void DGACloseFramebuffer(int Index); +Bool DGAChangePixmapMode(int Index, int *x, int *y, int mode); +int DGACreateColormap(int Index, ClientPtr client, int id, int mode, + int alloc); + +extern unsigned char DGAReqCode; +extern int DGAErrorBase; +extern int DGAEventBase; +extern int *XDGAEventBase; + + + +#endif /* __DGAPROC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dispatch.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dispatch.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dispatch.h (revision 51223) @@ -0,0 +1,147 @@ +/* $XFree86: xc/programs/Xserver/dix/dispatch.h,v 3.2 2001/08/01 00:44:48 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/* + * This prototypes the dispatch.c module (except for functions declared in + * global headers), plus related dispatch procedures from devices.c, events.c, + * extension.c, property.c. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DISPATCH_H +#define DISPATCH_H 1 + +DISPATCH_PROC(InitClientPrivates); +DISPATCH_PROC(ProcAllocColor); +DISPATCH_PROC(ProcAllocColorCells); +DISPATCH_PROC(ProcAllocColorPlanes); +DISPATCH_PROC(ProcAllocNamedColor); +DISPATCH_PROC(ProcBell); +DISPATCH_PROC(ProcChangeAccessControl); +DISPATCH_PROC(ProcChangeCloseDownMode); +DISPATCH_PROC(ProcChangeGC); +DISPATCH_PROC(ProcChangeHosts); +DISPATCH_PROC(ProcChangeKeyboardControl); +DISPATCH_PROC(ProcChangeKeyboardMapping); +DISPATCH_PROC(ProcChangePointerControl); +DISPATCH_PROC(ProcChangeProperty); +DISPATCH_PROC(ProcChangeSaveSet); +DISPATCH_PROC(ProcChangeWindowAttributes); +DISPATCH_PROC(ProcCirculateWindow); +DISPATCH_PROC(ProcClearToBackground); +DISPATCH_PROC(ProcCloseFont); +DISPATCH_PROC(ProcConfigureWindow); +DISPATCH_PROC(ProcConvertSelection); +DISPATCH_PROC(ProcCopyArea); +DISPATCH_PROC(ProcCopyColormapAndFree); +DISPATCH_PROC(ProcCopyGC); +DISPATCH_PROC(ProcCopyPlane); +DISPATCH_PROC(ProcCreateColormap); +DISPATCH_PROC(ProcCreateCursor); +DISPATCH_PROC(ProcCreateGC); +DISPATCH_PROC(ProcCreateGlyphCursor); +DISPATCH_PROC(ProcCreatePixmap); +DISPATCH_PROC(ProcCreateWindow); +DISPATCH_PROC(ProcDeleteProperty); +DISPATCH_PROC(ProcDestroySubwindows); +DISPATCH_PROC(ProcDestroyWindow); +DISPATCH_PROC(ProcEstablishConnection); +DISPATCH_PROC(ProcFillPoly); +DISPATCH_PROC(ProcForceScreenSaver); +DISPATCH_PROC(ProcFreeColormap); +DISPATCH_PROC(ProcFreeColors); +DISPATCH_PROC(ProcFreeCursor); +DISPATCH_PROC(ProcFreeGC); +DISPATCH_PROC(ProcFreePixmap); +DISPATCH_PROC(ProcGetAtomName); +DISPATCH_PROC(ProcGetFontPath); +DISPATCH_PROC(ProcGetGeometry); +DISPATCH_PROC(ProcGetImage); +DISPATCH_PROC(ProcGetKeyboardControl); +DISPATCH_PROC(ProcGetKeyboardMapping); +DISPATCH_PROC(ProcGetModifierMapping); +DISPATCH_PROC(ProcGetMotionEvents); +DISPATCH_PROC(ProcGetPointerControl); +DISPATCH_PROC(ProcGetPointerMapping); +DISPATCH_PROC(ProcGetProperty); +DISPATCH_PROC(ProcGetScreenSaver); +DISPATCH_PROC(ProcGetSelectionOwner); +DISPATCH_PROC(ProcGetWindowAttributes); +DISPATCH_PROC(ProcGrabServer); +DISPATCH_PROC(ProcImageText16); +DISPATCH_PROC(ProcImageText8); +DISPATCH_PROC(ProcInitialConnection); +DISPATCH_PROC(ProcInstallColormap); +DISPATCH_PROC(ProcInternAtom); +DISPATCH_PROC(ProcKillClient); +DISPATCH_PROC(ProcListExtensions); +DISPATCH_PROC(ProcListFonts); +DISPATCH_PROC(ProcListFontsWithInfo); +DISPATCH_PROC(ProcListHosts); +DISPATCH_PROC(ProcListInstalledColormaps); +DISPATCH_PROC(ProcListProperties); +DISPATCH_PROC(ProcLookupColor); +DISPATCH_PROC(ProcMapSubwindows); +DISPATCH_PROC(ProcMapWindow); +DISPATCH_PROC(ProcNoOperation); +DISPATCH_PROC(ProcOpenFont); +DISPATCH_PROC(ProcPolyArc); +DISPATCH_PROC(ProcPolyFillArc); +DISPATCH_PROC(ProcPolyFillRectangle); +DISPATCH_PROC(ProcPolyLine); +DISPATCH_PROC(ProcPolyPoint); +DISPATCH_PROC(ProcPolyRectangle); +DISPATCH_PROC(ProcPolySegment); +DISPATCH_PROC(ProcPolyText); +DISPATCH_PROC(ProcPutImage); +DISPATCH_PROC(ProcQueryBestSize); +DISPATCH_PROC(ProcQueryColors); +DISPATCH_PROC(ProcQueryExtension); +DISPATCH_PROC(ProcQueryFont); +DISPATCH_PROC(ProcQueryKeymap); +DISPATCH_PROC(ProcQueryTextExtents); +DISPATCH_PROC(ProcQueryTree); +DISPATCH_PROC(ProcReparentWindow); +DISPATCH_PROC(ProcRotateProperties); +DISPATCH_PROC(ProcSetClipRectangles); +DISPATCH_PROC(ProcSetDashes); +DISPATCH_PROC(ProcSetFontPath); +DISPATCH_PROC(ProcSetModifierMapping); +DISPATCH_PROC(ProcSetPointerMapping); +DISPATCH_PROC(ProcSetScreenSaver); +DISPATCH_PROC(ProcSetSelectionOwner); +DISPATCH_PROC(ProcStoreColors); +DISPATCH_PROC(ProcStoreNamedColor); +DISPATCH_PROC(ProcTranslateCoords); +DISPATCH_PROC(ProcUngrabServer); +DISPATCH_PROC(ProcUninstallColormap); +DISPATCH_PROC(ProcUnmapSubwindows); +DISPATCH_PROC(ProcUnmapWindow); + +#endif /* DISPATCH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix-config.h (revision 51223) @@ -0,0 +1,440 @@ +/* include/dix-config.h. Generated by configure. */ +/* dix-config.h.in: not at all generated. -*- c -*- */ + +#ifndef _DIX_CONFIG_H_ +#define _DIX_CONFIG_H_ + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Builder address */ +#define BUILDERADDR "xorg@lists.freedesktop.org" + +/* Operating System Name */ +#define OSNAME "Linux 2.6.16-1.2122_FC6smp i686" + +/* Operating System Vendor */ +#define OSVENDOR "" + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/usr/local/lib/X11/fonts/misc/,/usr/local/lib/X11/fonts/TTF/,/usr/local/lib/X11/fonts/OTF,/usr/local/lib/X11/fonts/Type1/,/usr/local/lib/X11/fonts/CID/,/usr/local/lib/X11/fonts/100dpi/,/usr/local/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP + systems. This function is required for `alloca.c' support on those systems. + */ +/* #undef CRAY_STACKSEG_END */ + +/* Define to 1 if using `alloca.c'. */ +/* #undef C_ALLOCA */ + +/* Support Damage extension */ +#define DAMAGE 1 + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Use GetTimeInMillis */ +/* #undef DDXTIME */ + +/* Use OsVendorFatalError */ +/* #undef DDXOSFATALERROR */ + +/* Use OsVendorVErrorF */ +/* #undef DDXOSVERRORF */ + +/* Use ddxBeforeReset */ +/* #undef DDXBEFORERESET */ + +/* Build DPMS extension */ +#define DPMSExtension 1 + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Build GLX DRI loader */ +/* #undef GLX_DRI */ + +/* Path to DRI drivers */ +#define DRI_DRIVER_PATH "/usr/local/lib/dri" + +/* Include handhelds.org h3600 touchscreen driver */ +/* #undef H3600_TS */ + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* Define to 1 if you have the `getdtablesize' function. */ +#define HAS_GETDTABLESIZE 1 + +/* Define to 1 if you have the `getifaddrs' function. */ +#define HAS_GETIFADDRS 1 + +/* Define to 1 if you have the `getpeereid' function. */ +/* #undef HAS_GETPEEREID */ + +/* Define to 1 if you have the `getpeerucred' function. */ +/* #undef HAS_GETPEERUCRED */ + +/* Define to 1 if you have the `mmap' function. */ +#define HAS_MMAP 1 + +/* Support SHM */ +#define HAS_SHM 1 + +/* Define to 1 if you have `alloca', as a function or macro. */ +#define HAVE_ALLOCA 1 + +/* Define to 1 if you have and it should be used (not on Ultrix). + */ +#define HAVE_ALLOCA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_MTRR_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +#define HAVE_DIRENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you don't have `vprintf' but do have `_doprnt.' */ +/* #undef HAVE_DOPRNT */ + +/* Define to 1 if you have the header file. */ +#define HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `geteuid' function. */ +#define HAVE_GETEUID 1 + +/* Define to 1 if you have the `getopt' function. */ +#define HAVE_GETOPT 1 + +/* Define to 1 if you have the `getopt_long' function. */ +#define HAVE_GETOPT_LONG 1 + +/* Define to 1 if you have the `getuid' function. */ +#define HAVE_GETUID 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `m' library (-lm). */ +#define HAVE_LIBM 1 + +/* Define to 1 if you have the `link' function. */ +#define HAVE_LINK 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_AGPGART_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APM_BIOS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_FB_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_H3600_TS_H */ + +/* Define to 1 if you have the `memmove' function. */ +#define HAVE_MEMMOVE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have the `memset' function. */ +#define HAVE_MEMSET 1 + +/* Define to 1 if you have the `mkstemp' function. */ +#define HAVE_MKSTEMP 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_NDBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. */ +/* #undef HAVE_NDIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_RPCSVC_DBM_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the `strchr' function. */ +#define HAVE_STRCHR 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the `strrchr' function. */ +#define HAVE_STRRCHR 1 + +/* Define to 1 if you have the `strtol' function. */ +#define HAVE_STRTOL 1 + +/* Define to 1 if SYSV IPC is available */ +#define HAVE_SYSV_IPC 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_AGPIO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_DIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_IO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_NDIR_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_VM86_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_TSLIB_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to 1 if you have the `vprintf' function. */ +#define HAVE_VPRINTF 1 + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM Extension */ +#define MITSHM 1 + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Name of package */ +#define PACKAGE "xorg-server" + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Overall prefix */ +#define PROJECTROOT "/usr/local" + +/* Support RANDR extension */ +#define RANDR 1 + +/* Support Record extension */ +#define XRECORD 1 + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ +/* #undef STACK_DIRECTION */ + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Enable touchscreen support */ +/* #undef TOUCHSCREEN */ + +/* Support tslib touchscreen abstraction library */ +/* #undef TSLIB */ + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* Use builtin rgb color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* unaligned word accesses behave as expected */ +/* #undef WORKING_UNALIGNED_INT */ + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Build Security extension */ +#define XCSECURITY 1 + +/* Support Xdmcp */ +#define XDMCP 1 + +/* Build XEvIE extension */ +#define XEVIE 1 + +/* Build XFree86 BigFont extension */ +#define XF86BIGFONT 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Support XFixes extension */ +#define XFIXES 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Enable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Vendor release */ +#define XORG_RELEASE "Release 7.1" + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((1) * 100000) + ((0) * 1000) + 0) + +/* Xorg release date */ +#define XORG_DATE "22 May 2006" + +/* Build Xv Extension */ +#define XvExtension 1 + +/* Build XvMC Extension */ +#define XvMCExtension 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv extension */ +#define XV 1 + +/* Build LBX extension */ +/* #undef LBX */ + +/* Build APPGROUP extension */ +#define XAPPGROUP 1 + +/* Build TOG-CUP extension */ +#define TOGCUP 1 + +/* Build Extended-Visual-Information extension */ +#define EVI 1 + +/* Build Multibuffer extension */ +/* #undef MULTIBUFFER */ + +/* Support DRI extension */ +#define XF86DRI 1 + +/* Build DBE support */ +#define DBE 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +#ifndef _XOPEN_SOURCE +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 +#endif + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ + +/* Define to `int' if does not define. */ +/* #undef pid_t */ + +/* Build Rootless code */ +/* #undef ROOTLESS */ + +/* Define to 1 if unsigned long is 64 bits. */ +/* #undef _XSERVER64 */ + +/* Define to location of RGB database */ +#define RGB_DB "/usr/local/share/X11/rgb" + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* Define to 1 if `struct sockaddr_in' has a `sin_len' member */ +/* #undef BSD44SOCKETS */ + +/* Define to 1 if modules should avoid the libcwrapper */ +#define NO_LIBCWRAPPER 1 + +#endif /* _DIX_CONFIG_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dix.h (revision 51223) @@ -0,0 +1,817 @@ +/* $XFree86: xc/programs/Xserver/include/dix.h,v 3.26 2003/01/12 02:44:27 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: dix.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef DIX_H +#define DIX_H + +#include "gc.h" +#include "window.h" +#include "input.h" + +#define EARLIER -1 +#define SAMETIME 0 +#define LATER 1 + +#define NullClient ((ClientPtr) 0) +#define REQUEST(type) \ + register type *stuff = (type *)client->requestBuffer + + +#define REQUEST_SIZE_MATCH(req)\ + if ((sizeof(req) >> 2) != client->req_len)\ + return(BadLength) + +#define REQUEST_AT_LEAST_SIZE(req) \ + if ((sizeof(req) >> 2) > client->req_len )\ + return(BadLength) + +#define REQUEST_FIXED_SIZE(req, n)\ + if (((sizeof(req) >> 2) > client->req_len) || \ + (((sizeof(req) + (n) + 3) >> 2) != client->req_len)) \ + return(BadLength) + +#define LEGAL_NEW_RESOURCE(id,client)\ + if (!LegalNewID(id,client)) \ + {\ + client->errorValue = id;\ + return(BadIDChoice);\ + } + +/* XXX if you are using this macro, you are probably not generating Match + * errors where appropriate */ +#define LOOKUP_DRAWABLE(did, client)\ + ((client->lastDrawableID == did) ? \ + client->lastDrawable : (DrawablePtr)LookupDrawable(did, client)) + +#ifdef XCSECURITY + +#define SECURITY_VERIFY_DRAWABLE(pDraw, did, client, mode)\ + if (client->lastDrawableID == did && !client->trustLevel)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ + RC_DRAWABLE, mode);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + if (pDraw->type == UNDRAWABLE_WINDOW)\ + return BadMatch;\ + } + +#define SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, mode)\ + if (client->lastDrawableID == did && !client->trustLevel)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ + RC_DRAWABLE, mode);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + } + +#define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ + if (client->lastGCID == rid && !client->trustLevel)\ + pGC = client->lastGC;\ + else\ + pGC = (GC *) SecurityLookupIDByType(client, rid, RT_GC, mode);\ + if (!pGC)\ + {\ + client->errorValue = rid;\ + return (BadGC);\ + } + +#define VERIFY_DRAWABLE(pDraw, did, client)\ + SECURITY_VERIFY_DRAWABLE(pDraw, did, client, SecurityUnknownAccess) + +#define VERIFY_GEOMETRABLE(pDraw, did, client)\ + SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, SecurityUnknownAccess) + +#define VERIFY_GC(pGC, rid, client)\ + SECURITY_VERIFY_GC(pGC, rid, client, SecurityUnknownAccess) + +#else /* not XCSECURITY */ + +#define VERIFY_DRAWABLE(pDraw, did, client)\ + if (client->lastDrawableID == did)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) LookupIDByClass(did, RC_DRAWABLE);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + if (pDraw->type == UNDRAWABLE_WINDOW)\ + return BadMatch;\ + } + +#define VERIFY_GEOMETRABLE(pDraw, did, client)\ + if (client->lastDrawableID == did)\ + pDraw = client->lastDrawable;\ + else \ + {\ + pDraw = (DrawablePtr) LookupIDByClass(did, RC_DRAWABLE);\ + if (!pDraw) \ + {\ + client->errorValue = did; \ + return BadDrawable;\ + }\ + } + +#define VERIFY_GC(pGC, rid, client)\ + if (client->lastGCID == rid)\ + pGC = client->lastGC;\ + else\ + pGC = (GC *)LookupIDByType(rid, RT_GC);\ + if (!pGC)\ + {\ + client->errorValue = rid;\ + return (BadGC);\ + } + +#define SECURITY_VERIFY_DRAWABLE(pDraw, did, client, mode)\ + VERIFY_DRAWABLE(pDraw, did, client) + +#define SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, mode)\ + VERIFY_GEOMETRABLE(pDraw, did, client) + +#define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ + VERIFY_GC(pGC, rid, client) + +#endif /* XCSECURITY */ + +/* + * We think that most hardware implementations of DBE will want + * LookupID*(dbe_back_buffer_id) to return the window structure that the + * id is a back buffer for. Since both front and back buffers will + * return the same structure, you need to be able to distinguish + * somewhere what kind of buffer (front/back) was being asked for, so + * that ddx can render to the right place. That's the problem that the + * following code solves. Note: we couldn't embed this in the LookupID* + * functions because the VALIDATE_DRAWABLE_AND_GC macro often circumvents + * those functions by checking a one-element cache. That's why we're + * mucking with VALIDATE_DRAWABLE_AND_GC. + * + * If you put -DNEED_DBE_BUF_BITS into PervasiveDBEDefines, the window + * structure will have two additional bits defined, srcBuffer and + * dstBuffer, and their values will be maintained via the macros + * SET_DBE_DSTBUF and SET_DBE_SRCBUF (below). If you also + * put -DNEED_DBE_BUF_VALIDATE into PervasiveDBEDefines, the function + * DbeValidateBuffer will be called any time the bits change to give you + * a chance to do some setup. See the DBE code for more details on this + * function. We put in these levels of conditionality so that you can do + * just what you need to do, and no more. If neither of these defines + * are used, the bits won't be there, and VALIDATE_DRAWABLE_AND_GC will + * be unchanged. dpw + */ + +#if defined(NEED_DBE_BUF_BITS) +#define SET_DBE_DSTBUF(_pDraw, _drawID) \ + SET_DBE_BUF(_pDraw, _drawID, dstBuffer, TRUE) +#define SET_DBE_SRCBUF(_pDraw, _drawID) \ + SET_DBE_BUF(_pDraw, _drawID, srcBuffer, FALSE) +#if defined (NEED_DBE_BUF_VALIDATE) +#define SET_DBE_BUF(_pDraw, _drawID, _whichBuffer, _dstbuf) \ + if (_pDraw->type == DRAWABLE_WINDOW)\ + {\ + int thisbuf = (_pDraw->id == _drawID);\ + if (thisbuf != ((WindowPtr)_pDraw)->_whichBuffer)\ + {\ + ((WindowPtr)_pDraw)->_whichBuffer = thisbuf;\ + DbeValidateBuffer((WindowPtr)_pDraw, _drawID, _dstbuf);\ + }\ + } +#else /* want buffer bits, but don't need to call DbeValidateBuffer */ +#define SET_DBE_BUF(_pDraw, _drawID, _whichBuffer, _dstbuf) \ + if (_pDraw->type == DRAWABLE_WINDOW)\ + {\ + ((WindowPtr)_pDraw)->_whichBuffer = (_pDraw->id == _drawID);\ + } +#endif /* NEED_DBE_BUF_VALIDATE */ +#else /* don't want buffer bits in window */ +#define SET_DBE_DSTBUF(_pDraw, _drawID) /**/ +#define SET_DBE_SRCBUF(_pDraw, _drawID) /**/ +#endif /* NEED_DBE_BUF_BITS */ + +#define VALIDATE_DRAWABLE_AND_GC(drawID, pDraw, pGC, client)\ + if ((stuff->gc == INVALID) || (client->lastGCID != stuff->gc) ||\ + (client->lastDrawableID != drawID))\ + {\ + SECURITY_VERIFY_GEOMETRABLE(pDraw, drawID, client, SecurityWriteAccess);\ + SECURITY_VERIFY_GC(pGC, stuff->gc, client, SecurityReadAccess);\ + if ((pGC->depth != pDraw->depth) ||\ + (pGC->pScreen != pDraw->pScreen))\ + return (BadMatch);\ + client->lastDrawable = pDraw;\ + client->lastDrawableID = drawID;\ + client->lastGC = pGC;\ + client->lastGCID = stuff->gc;\ + }\ + else\ + {\ + pGC = client->lastGC;\ + pDraw = client->lastDrawable;\ + }\ + SET_DBE_DSTBUF(pDraw, drawID);\ + if (pGC->serialNumber != pDraw->serialNumber)\ + ValidateGC(pDraw, pGC); + + +#define WriteReplyToClient(pClient, size, pReply) { \ + if ((pClient)->swapped) \ + (*ReplySwapVector[((xReq *)(pClient)->requestBuffer)->reqType]) \ + (pClient, (int)(size), pReply); \ + else (void) WriteToClient(pClient, (int)(size), (char *)(pReply)); } + +#define WriteSwappedDataToClient(pClient, size, pbuf) \ + if ((pClient)->swapped) \ + (*(pClient)->pSwapReplyFunc)(pClient, (int)(size), pbuf); \ + else (void) WriteToClient (pClient, (int)(size), (char *)(pbuf)); + +typedef struct _TimeStamp *TimeStampPtr; + +#ifndef _XTYPEDEF_CLIENTPTR +typedef struct _Client *ClientPtr; /* also in misc.h */ +#define _XTYPEDEF_CLIENTPTR +#endif + +typedef struct _WorkQueue *WorkQueuePtr; + +extern ClientPtr requestingClient; +extern ClientPtr *clients; +extern ClientPtr serverClient; +extern int currentMaxClients; + +typedef int HWEventQueueType; +typedef HWEventQueueType* HWEventQueuePtr; + +extern HWEventQueuePtr checkForInput[2]; + +typedef struct _TimeStamp { + CARD32 months; /* really ~49.7 days */ + CARD32 milliseconds; +} TimeStamp; + +/* dispatch.c */ + +extern void SetInputCheck( + HWEventQueuePtr /*c0*/, + HWEventQueuePtr /*c1*/); + +extern void CloseDownClient( + ClientPtr /*client*/); + +extern void UpdateCurrentTime(void); + +extern void UpdateCurrentTimeIf(void); + +extern void InitSelections(void); + +extern void FlushClientCaches(XID /*id*/); + +extern int dixDestroyPixmap( + pointer /*value*/, + XID /*pid*/); + +extern void CloseDownRetainedResources(void); + +extern void InitClient( + ClientPtr /*client*/, + int /*i*/, + pointer /*ospriv*/); + +extern ClientPtr NextAvailableClient( + pointer /*ospriv*/); + +extern void SendErrorToClient( + ClientPtr /*client*/, + unsigned int /*majorCode*/, + unsigned int /*minorCode*/, + XID /*resId*/, + int /*errorCode*/); + +extern void DeleteWindowFromAnySelections( + WindowPtr /*pWin*/); + +extern void MarkClientException( + ClientPtr /*client*/); + +extern int GetGeometry( + ClientPtr /*client*/, + xGetGeometryReply* /* wa */); + +extern int SendConnSetup( + ClientPtr /*client*/, + char* /*reason*/); + +extern int DoGetImage( + ClientPtr /*client*/, + int /*format*/, + Drawable /*drawable*/, + int /*x*/, + int /*y*/, + int /*width*/, + int /*height*/, + Mask /*planemask*/, + xGetImageReply ** /*im_return*/); + +#ifdef LBX +extern void IncrementClientCount(void); +#endif /* LBX */ + +#if defined(DDXBEFORERESET) +extern void ddxBeforeReset (void); +#endif + +/* dixutils.c */ + +extern void CopyISOLatin1Lowered( + unsigned char * /*dest*/, + unsigned char * /*source*/, + int /*length*/); + +extern int CompareISOLatin1Lowered( + unsigned char * /*a*/, + int alen, + unsigned char * /*b*/, + int blen); + +#ifdef XCSECURITY + +extern WindowPtr SecurityLookupWindow( + XID /*rid*/, + ClientPtr /*client*/, + Mask /*access_mode*/); + +extern pointer SecurityLookupDrawable( + XID /*rid*/, + ClientPtr /*client*/, + Mask /*access_mode*/); + +extern WindowPtr LookupWindow( + XID /*rid*/, + ClientPtr /*client*/); + +extern pointer LookupDrawable( + XID /*rid*/, + ClientPtr /*client*/); + +#else + +extern WindowPtr LookupWindow( + XID /*rid*/, + ClientPtr /*client*/); + +extern pointer LookupDrawable( + XID /*rid*/, + ClientPtr /*client*/); + +#define SecurityLookupWindow(rid, client, access_mode) \ + LookupWindow(rid, client) + +#define SecurityLookupDrawable(rid, client, access_mode) \ + LookupDrawable(rid, client) + +#endif /* XCSECURITY */ + +extern ClientPtr LookupClient( + XID /*rid*/, + ClientPtr /*client*/); + +extern void NoopDDA(void); + +extern int AlterSaveSetForClient( + ClientPtr /*client*/, + WindowPtr /*pWin*/, + unsigned /*mode*/, + Bool /*toRoot*/, + Bool /*remap*/); + +extern void DeleteWindowFromAnySaveSet( + WindowPtr /*pWin*/); + +extern void BlockHandler( + pointer /*pTimeout*/, + pointer /*pReadmask*/); + +extern void WakeupHandler( + int /*result*/, + pointer /*pReadmask*/); + +typedef void (* WakeupHandlerProcPtr)( + pointer /* blockData */, + int /* result */, + pointer /* pReadmask */); + +extern Bool RegisterBlockAndWakeupHandlers( + BlockHandlerProcPtr /*blockHandler*/, + WakeupHandlerProcPtr /*wakeupHandler*/, + pointer /*blockData*/); + +extern void RemoveBlockAndWakeupHandlers( + BlockHandlerProcPtr /*blockHandler*/, + WakeupHandlerProcPtr /*wakeupHandler*/, + pointer /*blockData*/); + +extern void InitBlockAndWakeupHandlers(void); + +extern void ProcessWorkQueue(void); + +extern void ProcessWorkQueueZombies(void); + +extern Bool QueueWorkProc( + Bool (* /*function*/)( + ClientPtr /*clientUnused*/, + pointer /*closure*/), + ClientPtr /*client*/, + pointer /*closure*/ +); + +typedef Bool (* ClientSleepProcPtr)( + ClientPtr /*client*/, + pointer /*closure*/); + +extern Bool ClientSleep( + ClientPtr /*client*/, + ClientSleepProcPtr /* function */, + pointer /*closure*/); + +#ifndef ___CLIENTSIGNAL_DEFINED___ +#define ___CLIENTSIGNAL_DEFINED___ +extern Bool ClientSignal( + ClientPtr /*client*/); +#endif /* ___CLIENTSIGNAL_DEFINED___ */ + +extern void ClientWakeup( + ClientPtr /*client*/); + +extern Bool ClientIsAsleep( + ClientPtr /*client*/); + +/* atom.c */ + +extern Atom MakeAtom( + char * /*string*/, + unsigned /*len*/, + Bool /*makeit*/); + +extern Bool ValidAtom( + Atom /*atom*/); + +extern char *NameForAtom( + Atom /*atom*/); + +extern void AtomError(void); + +extern void FreeAllAtoms(void); + +extern void InitAtoms(void); + +/* events.c */ + +extern void SetMaskForEvent( + Mask /* mask */, + int /* event */); + + +extern Bool IsParent( + WindowPtr /* maybeparent */, + WindowPtr /* child */); + +extern WindowPtr GetCurrentRootWindow(void); + +extern WindowPtr GetSpriteWindow(void); + + +extern void NoticeEventTime(xEventPtr /* xE */); + +extern void EnqueueEvent( + xEventPtr /* xE */, + DeviceIntPtr /* device */, + int /* count */); + +extern void ComputeFreezes(void); + +extern void CheckGrabForSyncs( + DeviceIntPtr /* dev */, + Bool /* thisMode */, + Bool /* otherMode */); + +extern void ActivatePointerGrab( + DeviceIntPtr /* mouse */, + GrabPtr /* grab */, + TimeStamp /* time */, + Bool /* autoGrab */); + +extern void DeactivatePointerGrab( + DeviceIntPtr /* mouse */); + +extern void ActivateKeyboardGrab( + DeviceIntPtr /* keybd */, + GrabPtr /* grab */, + TimeStamp /* time */, + Bool /* passive */); + +extern void DeactivateKeyboardGrab( + DeviceIntPtr /* keybd */); + +extern void AllowSome( + ClientPtr /* client */, + TimeStamp /* time */, + DeviceIntPtr /* thisDev */, + int /* newState */); + +extern void ReleaseActiveGrabs( + ClientPtr client); + +extern int DeliverEventsToWindow( + WindowPtr /* pWin */, + xEventPtr /* pEvents */, + int /* count */, + Mask /* filter */, + GrabPtr /* grab */, + int /* mskidx */); + +extern int DeliverDeviceEvents( + WindowPtr /* pWin */, + xEventPtr /* xE */, + GrabPtr /* grab */, + WindowPtr /* stopAt */, + DeviceIntPtr /* dev */, + int /* count */); + +extern void DefineInitialRootWindow( + WindowPtr /* win */); + +extern void WindowHasNewCursor( + WindowPtr /* pWin */); + +extern Bool CheckDeviceGrabs( + DeviceIntPtr /* device */, + xEventPtr /* xE */, + int /* checkFirst */, + int /* count */); + +extern void DeliverFocusedEvent( + DeviceIntPtr /* keybd */, + xEventPtr /* xE */, + WindowPtr /* window */, + int /* count */); + +extern void DeliverGrabbedEvent( + xEventPtr /* xE */, + DeviceIntPtr /* thisDev */, + Bool /* deactivateGrab */, + int /* count */); + +#ifdef XKB +extern void FixKeyState( + xEvent * /* xE */, + DeviceIntPtr /* keybd */); +#endif /* XKB */ + +extern void RecalculateDeliverableEvents( + WindowPtr /* pWin */); + +extern int OtherClientGone( + pointer /* value */, + XID /* id */); + +extern void DoFocusEvents( + DeviceIntPtr /* dev */, + WindowPtr /* fromWin */, + WindowPtr /* toWin */, + int /* mode */); + +extern int SetInputFocus( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + Window /* focusID */, + CARD8 /* revertTo */, + Time /* ctime */, + Bool /* followOK */); + +extern int GrabDevice( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned /* this_mode */, + unsigned /* other_mode */, + Window /* grabWindow */, + unsigned /* ownerEvents */, + Time /* ctime */, + Mask /* mask */, + CARD8 * /* status */); + +extern void InitEvents(void); + +extern void CloseDownEvents(void); + +extern void DeleteWindowFromAnyEvents( + WindowPtr /* pWin */, + Bool /* freeResources */); + + +extern Mask EventMaskForClient( + WindowPtr /* pWin */, + ClientPtr /* client */); + + + +extern int DeliverEvents( + WindowPtr /*pWin*/, + xEventPtr /*xE*/, + int /*count*/, + WindowPtr /*otherParent*/); + + +extern void WriteEventsToClient( + ClientPtr /*pClient*/, + int /*count*/, + xEventPtr /*events*/); + +extern int TryClientEvents( + ClientPtr /*client*/, + xEventPtr /*pEvents*/, + int /*count*/, + Mask /*mask*/, + Mask /*filter*/, + GrabPtr /*grab*/); + +extern void WindowsRestructured(void); + + +#ifdef RANDR +void +ScreenRestructured (ScreenPtr pScreen); +#endif + +extern void ResetClientPrivates(void); + +extern int AllocateClientPrivateIndex(void); + +extern Bool AllocateClientPrivate( + int /*index*/, + unsigned /*amount*/); + +/* + * callback manager stuff + */ + +#ifndef _XTYPEDEF_CALLBACKLISTPTR +typedef struct _CallbackList *CallbackListPtr; /* also in misc.h */ +#define _XTYPEDEF_CALLBACKLISTPTR +#endif + +typedef void (*CallbackProcPtr) ( + CallbackListPtr *, pointer, pointer); + +typedef Bool (*AddCallbackProcPtr) ( + CallbackListPtr *, CallbackProcPtr, pointer); + +typedef Bool (*DeleteCallbackProcPtr) ( + CallbackListPtr *, CallbackProcPtr, pointer); + +typedef void (*CallCallbacksProcPtr) ( + CallbackListPtr *, pointer); + +typedef void (*DeleteCallbackListProcPtr) ( + CallbackListPtr *); + +typedef struct _CallbackProcs { + AddCallbackProcPtr AddCallback; + DeleteCallbackProcPtr DeleteCallback; + CallCallbacksProcPtr CallCallbacks; + DeleteCallbackListProcPtr DeleteCallbackList; +} CallbackFuncsRec, *CallbackFuncsPtr; + +extern Bool CreateCallbackList( + CallbackListPtr * /*pcbl*/, + CallbackFuncsPtr /*cbfuncs*/); + +extern Bool AddCallback( + CallbackListPtr * /*pcbl*/, + CallbackProcPtr /*callback*/, + pointer /*data*/); + +extern Bool DeleteCallback( + CallbackListPtr * /*pcbl*/, + CallbackProcPtr /*callback*/, + pointer /*data*/); + +extern void CallCallbacks( + CallbackListPtr * /*pcbl*/, + pointer /*call_data*/); + +extern void DeleteCallbackList( + CallbackListPtr * /*pcbl*/); + +extern void InitCallbackManager(void); + +/* + * ServerGrabCallback stuff + */ + +extern CallbackListPtr ServerGrabCallback; + +typedef enum {SERVER_GRABBED, SERVER_UNGRABBED, + CLIENT_PERVIOUS, CLIENT_IMPERVIOUS } ServerGrabState; + +typedef struct { + ClientPtr client; + ServerGrabState grabstate; +} ServerGrabInfoRec; + +/* + * EventCallback stuff + */ + +extern CallbackListPtr EventCallback; + +typedef struct { + ClientPtr client; + xEventPtr events; + int count; +} EventInfoRec; + +/* + * DeviceEventCallback stuff + */ + +extern CallbackListPtr DeviceEventCallback; + +typedef struct { + xEventPtr events; + int count; +} DeviceEventInfoRec; + +/* + * SelectionCallback stuff + */ + +extern CallbackListPtr SelectionCallback; + +typedef enum { + SelectionSetOwner, + SelectionWindowDestroy, + SelectionClientClose +} SelectionCallbackKind; + +typedef struct { + struct _Selection *selection; + SelectionCallbackKind kind; +} SelectionInfoRec; + +#endif /* DIX_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixevents.h (revision 51223) @@ -0,0 +1,106 @@ +/* $XFree86: xc/programs/Xserver/include/dixevents.h,v 3.4 2001/09/04 14:03:27 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef DIXEVENTS_H +#define DIXEVENTS_H + +extern void SetCriticalEvent(int /* event */); + +extern CursorPtr GetSpriteCursor(void); + +extern int ProcAllowEvents(ClientPtr /* client */); + +extern int MaybeDeliverEventsToClient( + WindowPtr /* pWin */, + xEvent * /* pEvents */, + int /* count */, + Mask /* filter */, + ClientPtr /* dontClient */); + +extern int ProcWarpPointer(ClientPtr /* client */); + +#if 0 +extern void +#ifdef XKB +CoreProcessKeyboardEvent ( +#else +ProcessKeyboardEvent ( +#endif + xEvent * /* xE */, + DeviceIntPtr /* keybd */, + int /* count */); + +extern void +#ifdef XKB +CoreProcessPointerEvent ( +#else +ProcessPointerEvent ( +#endif + xEvent * /* xE */, + DeviceIntPtr /* mouse */, + int /* count */); +#endif + +extern int EventSelectForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */); + +extern int EventSuppressForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + Bool * /* checkOptional */); + +extern int ProcSetInputFocus(ClientPtr /* client */); + +extern int ProcGetInputFocus(ClientPtr /* client */); + +extern int ProcGrabPointer(ClientPtr /* client */); + +extern int ProcChangeActivePointerGrab(ClientPtr /* client */); + +extern int ProcUngrabPointer(ClientPtr /* client */); + +extern int ProcGrabKeyboard(ClientPtr /* client */); + +extern int ProcUngrabKeyboard(ClientPtr /* client */); + +extern int ProcQueryPointer(ClientPtr /* client */); + +extern int ProcSendEvent(ClientPtr /* client */); + +extern int ProcUngrabKey(ClientPtr /* client */); + +extern int ProcGrabKey(ClientPtr /* client */); + +extern int ProcGrabButton(ClientPtr /* client */); + +extern int ProcUngrabButton(ClientPtr /* client */); + +extern int ProcRecolorCursor(ClientPtr /* client */); + +#endif /* DIXEVENTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfont.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfont.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfont.h (revision 51223) @@ -0,0 +1,155 @@ +/* $Xorg: dixfont.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/dixfont.h,v 3.7 2001/02/02 21:39:02 herrb Exp $ */ + +#ifndef DIXFONT_H +#define DIXFONT_H 1 + +#include "dix.h" +#include +#include "closure.h" +#include + +#define NullDIXFontProp ((DIXFontPropPtr)0) + +typedef struct _DIXFontProp *DIXFontPropPtr; + +extern FPEFunctions *fpe_functions; + +extern int FontToXError(int /*err*/); + +extern Bool SetDefaultFont(char * /*defaultfontname*/); + +extern void QueueFontWakeup(FontPathElementPtr /*fpe*/); + +extern void RemoveFontWakeup(FontPathElementPtr /*fpe*/); + +extern void FontWakeup(pointer /*data*/, + int /*count*/, + pointer /*LastSelectMask*/); + +extern int OpenFont(ClientPtr /*client*/, + XID /*fid*/, + Mask /*flags*/, + unsigned /*lenfname*/, + char * /*pfontname*/); + +extern int CloseFont(pointer /*pfont*/, + XID /*fid*/); + +typedef struct _xQueryFontReply *xQueryFontReplyPtr; + +extern void QueryFont(FontPtr /*pFont*/, + xQueryFontReplyPtr /*pReply*/, + int /*nProtoCCIStructs*/); + +extern int ListFonts(ClientPtr /*client*/, + unsigned char * /*pattern*/, + unsigned int /*length*/, + unsigned int /*max_names*/); + +int +doListFontsWithInfo(ClientPtr /*client*/, + LFWIclosurePtr /*c*/); + +extern int doPolyText(ClientPtr /*client*/, + PTclosurePtr /*c*/ +); + +extern int PolyText(ClientPtr /*client*/, + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + unsigned char * /*pElt*/, + unsigned char * /*endReq*/, + int /*xorg*/, + int /*yorg*/, + int /*reqType*/, + XID /*did*/); + +extern int doImageText(ClientPtr /*client*/, + ITclosurePtr /*c*/); + +extern int ImageText(ClientPtr /*client*/, + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nChars*/, + unsigned char * /*data*/, + int /*xorg*/, + int /*yorg*/, + int /*reqType*/, + XID /*did*/); + +extern int SetFontPath(ClientPtr /*client*/, + int /*npaths*/, + unsigned char * /*paths*/, + int * /*error*/); + +extern int SetDefaultFontPath(char * /*path*/); + +extern unsigned char *GetFontPath(int * /*count*/, + int * /*length*/); + +extern int LoadGlyphs(ClientPtr /*client*/, + FontPtr /*pfont*/, + unsigned /*nchars*/, + int /*item_size*/, + unsigned char * /*data*/); + +extern void DeleteClientFontStuff(ClientPtr /*client*/); + +/* Quartz support on Mac OS X pulls in the QuickDraw + framework whose InitFonts function conflicts here. */ +#ifdef __DARWIN__ +#define InitFonts Darwin_X_InitFonts +#endif +extern void InitFonts(void); + +extern void FreeFonts(void); + +extern FontPtr find_old_font(XID /*id*/); + +extern void GetGlyphs(FontPtr /*font*/, + unsigned long /*count*/, + unsigned char * /*chars*/, + FontEncoding /*fontEncoding*/, + unsigned long * /*glyphcount*/, + CharInfoPtr * /*glyphs*/); + +extern void QueryGlyphExtents(FontPtr /*pFont*/, + CharInfoPtr * /*charinfo*/, + unsigned long /*count*/, + ExtentInfoPtr /*info*/); + +extern Bool QueryTextExtents(FontPtr /*pFont*/, + unsigned long /*count*/, + unsigned char * /*chars*/, + ExtentInfoPtr /*info*/); + +extern Bool ParseGlyphCachingMode(char * /*str*/); + +extern void InitGlyphCaching(void); + +extern void SetGlyphCachingMode(int /*newmode*/); + +#endif /* DIXFONT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfontstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfontstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixfontstr.h (revision 51223) @@ -0,0 +1,95 @@ +/* $Xorg: dixfontstr.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef DIXFONTSTRUCT_H +#define DIXFONTSTRUCT_H + +#include "servermd.h" +#include "dixfont.h" +#include +#include "closure.h" +#define NEED_REPLIES +#include /* for xQueryFontReply */ + +#define FONTCHARSET(font) (font) +#define FONTMAXBOUNDS(font,field) (font)->info.maxbounds.field +#define FONTMINBOUNDS(font,field) (font)->info.minbounds.field +#define TERMINALFONT(font) (font)->info.terminalFont +#define FONTASCENT(font) (font)->info.fontAscent +#define FONTDESCENT(font) (font)->info.fontDescent +#define FONTGLYPHS(font) 0 +#define FONTCONSTMETRICS(font) (font)->info.constantMetrics +#define FONTCONSTWIDTH(font) (font)->info.constantWidth +#define FONTALLEXIST(font) (font)->info.allExist +#define FONTFIRSTCOL(font) (font)->info.firstCol +#define FONTLASTCOL(font) (font)->info.lastCol +#define FONTFIRSTROW(font) (font)->info.firstRow +#define FONTLASTROW(font) (font)->info.lastRow +#define FONTDEFAULTCH(font) (font)->info.defaultCh +#define FONTINKMIN(font) (&((font)->info.ink_minbounds)) +#define FONTINKMAX(font) (&((font)->info.ink_maxbounds)) +#define FONTPROPS(font) (font)->info.props +#define FONTGLYPHBITS(base,pci) ((unsigned char *) (pci)->bits) +#define FONTINFONPROPS(font) (font)->info.nprops + +/* some things haven't changed names, but we'll be careful anyway */ + +#define FONTREFCNT(font) (font)->refcnt + +/* + * for linear char sets + */ +#define N1dChars(pfont) (FONTLASTCOL(pfont) - FONTFIRSTCOL(pfont) + 1) + +/* + * for 2D char sets + */ +#define N2dChars(pfont) (N1dChars(pfont) * \ + (FONTLASTROW(pfont) - FONTFIRSTROW(pfont) + 1)) + +#ifndef GLYPHPADBYTES +#define GLYPHPADBYTES -1 +#endif + +#if GLYPHPADBYTES == 0 || GLYPHPADBYTES == 1 +#define GLYPHWIDTHBYTESPADDED(pci) (GLYPHWIDTHBYTES(pci)) +#define PADGLYPHWIDTHBYTES(w) (((w)+7)>>3) +#endif + +#if GLYPHPADBYTES == 2 +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+1) & ~0x1) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+1) & ~0x1) +#endif + +#if GLYPHPADBYTES == 4 +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+3) & ~0x3) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+3) & ~0x3) +#endif + +#if GLYPHPADBYTES == 8 /* for a cray? */ +#define GLYPHWIDTHBYTESPADDED(pci) ((GLYPHWIDTHBYTES(pci)+7) & ~0x7) +#define PADGLYPHWIDTHBYTES(w) (((((w)+7)>>3)+7) & ~0x7) +#endif + +#endif /* DIXFONTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixgrabs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixgrabs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixgrabs.h (revision 51223) @@ -0,0 +1,59 @@ +/* $XFree86: xc/programs/Xserver/include/dixgrabs.h,v 3.0 1996/04/15 11:34:27 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef DIXGRABS_H +#define DIXGRABS_H 1 + +extern GrabPtr CreateGrab( + int /* client */, + DeviceIntPtr /* device */, + WindowPtr /* window */, + Mask /* eventMask */, + Bool /* ownerEvents */, + Bool /* keyboardMode */, + Bool /* pointerMode */, + DeviceIntPtr /* modDevice */, + unsigned short /* modifiers */, + int /* type */, + KeyCode /* keybut */, + WindowPtr /* confineTo */, + CursorPtr /* cursor */); + +extern int DeletePassiveGrab( + pointer /* value */, + XID /* id */); + +extern Bool GrabMatchesSecond( + GrabPtr /* pFirstGrab */, + GrabPtr /* pSecondGrab */); + +extern int AddPassiveGrabToList( + GrabPtr /* pGrab */); + +extern Bool DeletePassiveGrabFromList( + GrabPtr /* pMinuendGrab */); + +#endif /* DIXGRABS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dixstruct.h (revision 51223) @@ -0,0 +1,233 @@ +/* $XFree86: xc/programs/Xserver/include/dixstruct.h,v 3.19tsi Exp $ */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: dixstruct.h,v 1.3 2000/08/17 19:53:29 cpqbld Exp $ */ + +#ifndef DIXSTRUCT_H +#define DIXSTRUCT_H + +#include "dix.h" +#include "resource.h" +#include "cursor.h" +#include "gc.h" +#include "pixmap.h" +#include + +/* + * direct-mapped hash table, used by resource manager to store + * translation from client ids to server addresses. + */ + +#ifdef DEBUG +#define MAX_REQUEST_LOG 100 +#endif + +extern CallbackListPtr ClientStateCallback; + +typedef struct { + ClientPtr client; + xConnSetupPrefix *prefix; + xConnSetup *setup; +} NewClientInfoRec; + +typedef void (*ReplySwapPtr) ( + ClientPtr /* pClient */, + int /* size */, + void * /* pbuf */); + +extern void ReplyNotSwappd ( + ClientPtr /* pClient */, + int /* size */, + void * /* pbuf */); + +typedef enum {ClientStateInitial, + ClientStateAuthenticating, + ClientStateRunning, + ClientStateRetained, + ClientStateGone, + ClientStateCheckingSecurity, + ClientStateCheckedSecurity} ClientState; + +#ifdef XFIXES +typedef struct _saveSet { + struct _Window *windowPtr; + Bool toRoot; + Bool remap; +} SaveSetElt; +#define SaveSetWindow(ss) ((ss).windowPtr) +#define SaveSetToRoot(ss) ((ss).toRoot) +#define SaveSetRemap(ss) ((ss).remap) +#define SaveSetAssignWindow(ss,w) ((ss).windowPtr = (w)) +#define SaveSetAssignToRoot(ss,tr) ((ss).toRoot = (tr)) +#define SaveSetAssignRemap(ss,rm) ((ss).remap = (rm)) +#else +typedef struct _Window *SaveSetElt; +#define SaveSetWindow(ss) (ss) +#define SaveSetToRoot(ss) FALSE +#define SaveSetRemap(ss) TRUE +#define SaveSetAssignWindow(ss,w) ((ss) = (w)) +#define SaveSetAssignToRoot(ss,tr) +#define SaveSetAssignRemap(ss,rm) +#endif + +typedef struct _Client { + int index; + Mask clientAsMask; + pointer requestBuffer; + pointer osPrivate; /* for OS layer, including scheduler */ + Bool swapped; + ReplySwapPtr pSwapReplyFunc; + XID errorValue; + int sequence; + int closeDownMode; + int clientGone; + int noClientException; /* this client died or needs to be + * killed */ + DrawablePtr lastDrawable; + Drawable lastDrawableID; + GCPtr lastGC; + GContext lastGCID; + SaveSetElt *saveSet; + int numSaved; + pointer screenPrivate[MAXSCREENS]; + int (**requestVector) ( + ClientPtr /* pClient */); + CARD32 req_len; /* length of current request */ + Bool big_requests; /* supports large requests */ + int priority; + ClientState clientState; + DevUnion *devPrivates; +#ifdef XKB + unsigned short xkbClientFlags; + unsigned short mapNotifyMask; + unsigned short newKeyboardNotifyMask; + unsigned short vMajor,vMinor; + KeyCode minKC,maxKC; +#endif + +#ifdef DEBUG + unsigned char requestLog[MAX_REQUEST_LOG]; + int requestLogIndex; +#endif +#ifdef LBX + int (*readRequest)(ClientPtr /*client*/); +#endif + unsigned long replyBytesRemaining; +#ifdef XCSECURITY + XID authId; + unsigned int trustLevel; + pointer (* CheckAccess)( + ClientPtr /*pClient*/, + XID /*id*/, + RESTYPE /*classes*/, + Mask /*access_mode*/, + pointer /*resourceval*/); +#endif +#ifdef XAPPGROUP + struct _AppGroupRec* appgroup; +#endif + struct _FontResolution * (*fontResFunc) ( /* no need for font.h */ + ClientPtr /* pClient */, + int * /* num */); +#ifdef SMART_SCHEDULE + int smart_priority; + long smart_start_tick; + long smart_stop_tick; + long smart_check_tick; +#endif +} ClientRec; + +#ifdef SMART_SCHEDULE +/* + * Scheduling interface + */ +extern long SmartScheduleTime; +extern long SmartScheduleInterval; +extern long SmartScheduleSlice; +extern long SmartScheduleMaxSlice; +extern unsigned long SmartScheduleIdleCount; +extern Bool SmartScheduleDisable; +extern Bool SmartScheduleIdle; +extern Bool SmartScheduleTimerStopped; +extern Bool SmartScheduleStartTimer(void); +#define SMART_MAX_PRIORITY (20) +#define SMART_MIN_PRIORITY (-20) + +extern Bool SmartScheduleInit(void); + +#endif + +/* This prototype is used pervasively in Xext, dix */ +#define DISPATCH_PROC(func) int func(ClientPtr /* client */) + +typedef struct _WorkQueue { + struct _WorkQueue *next; + Bool (*function) ( + ClientPtr /* pClient */, + pointer /* closure */ +); + ClientPtr client; + pointer closure; +} WorkQueueRec; + +extern TimeStamp currentTime; +extern TimeStamp lastDeviceEventTime; + +extern int CompareTimeStamps( + TimeStamp /*a*/, + TimeStamp /*b*/); + +extern TimeStamp ClientTimeToServerTime(CARD32 /*c*/); + +typedef struct _CallbackRec { + CallbackProcPtr proc; + pointer data; + Bool deleted; + struct _CallbackRec *next; +} CallbackRec, *CallbackPtr; + +typedef struct _CallbackList { + CallbackFuncsRec funcs; + int inCallback; + Bool deleted; + int numDeleted; + CallbackPtr list; +} CallbackListRec; + +/* proc vectors */ + +extern int (* InitialVector[3]) (ClientPtr /*client*/); + +extern int (* ProcVector[256]) (ClientPtr /*client*/); + +extern int (* SwappedProcVector[256]) (ClientPtr /*client*/); + +#ifdef K5AUTH +extern int (*k5_Vector[256])(ClientPtr /*client*/); +#endif + +extern ReplySwapPtr ReplySwapVector[256]; + +extern int ProcBadRequest(ClientPtr /*client*/); + +#endif /* DIXSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dlloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dlloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dlloader.h (revision 51223) @@ -0,0 +1,37 @@ +/* + * Copyright 1997 Metro Link, Inc. + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/dlloader.h,v 1.2 1998/07/25 16:56:14 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _DLLOADER_H +#define _DLLOADER_H +extern void *DLLoadModule(loaderPtr, int, LOOKUP **, int flags); +extern void DLResolveSymbols(void *); +extern int DLCheckForUnresolved(void *); +extern void DLUnloadModule(void *); +extern void *DLFindSymbol(const char *name); +extern void *DLFindSymbolLocal(pointer module, const char *name); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx-config.h (revision 51223) @@ -0,0 +1,98 @@ +/* + * Copyright 2005 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Provide configuration #define's and #undef's to build Xdmx in X.Org's + * modular source tree. + */ + +#ifndef DMX_CONFIG_H +#define DMX_CONFIG_H + +#include + +/* + * Note 1: This is a signed int that is printed as a decimal number. + * Since we want to make it human-interpretable, the fields are + * defined as: + * 2147483648 + * AAbbyymmdd + * AA: major version 01-20 + * bb: minor version 00-99 + * yy: year 00-99 [See Note 2] + * mm: month 01-12 + * dd: day 01-31 + * + * Note 2: The default epoch for the year is 2000. + * To change the default epoch, change the DMX_VENDOR_RELEASE + * macro below, bumb the minor version number, and change + * xdpyinfo to key off the major/minor version to determine the + * new epoch. Remember to do this on January 1, 2100 and every + * 100 years thereafter. + */ +#define DMX_VENDOR_RELEASE(major,minor,year,month,day) \ + ((major) * 100000000) + \ + ((minor) * 1000000) + \ + ((year-2000) * 10000) + \ + ((month) * 100) + \ + ((day) * 1) +#define VENDOR_RELEASE DMX_VENDOR_RELEASE(1,2,2004,6,30) +#define VENDOR_STRING "DMX Project" + +/* Enable the DMX extension */ +#define DMXEXT + +/* Disable the extensions that are not currently supported */ +#undef BEZIER +#undef PEXEXT +#undef MULTIBUFFER +#undef XV +#undef XIE +#undef DBE +#undef XF86VIDMODE +#undef XF86MISC +#undef XFreeXDGA +#undef XF86DRI +#undef MITSHM +#undef TOGCUP +#undef DPSEXT +#undef MITMISC +#undef SCREENSAVER +#undef RANDR +#undef XFIXES +#undef DAMAGE +#undef COMPOSITE +#undef FONTCACHE +#undef XFree86LOADER + +#endif /* DMX_CONFIG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx.h (revision 51223) @@ -0,0 +1,374 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Main header file included by all other DMX-related files. + */ + +/** \mainpage + * - DMX Home Page + * - DMX Project Page (on + * Source Forge) + * - Distributed Multihead + * X design, the design document for DMX + * - Client-to-Server + * DMX Extension to the X Protocol + */ + +#ifndef DMX_H +#define DMX_H + +#include "gcstruct.h" + +/* Handle client-side include files in one place. */ +#include "dmxclient.h" + +#include "globals.h" +#include "scrnintstr.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +#ifdef GLXEXT +#include +#include +#endif + +typedef enum { + PosNone = -1, + PosAbsolute = 0, + PosRightOf, + PosLeftOf, + PosAbove, + PosBelow, + PosRelative +} PositionType; + +/** Provide the typedef globally, but keep the contents opaque outside + * of the input routines. \see dmxinput.h */ +typedef struct _DMXInputInfo DMXInputInfo; + +/** Provide the typedef globally, but keep the contents opaque outside + * of the XSync statistic routines. \see dmxstat.c */ +typedef struct _DMXStatInfo DMXStatInfo; + +/** Global structure containing information about each backend screen. */ +typedef struct _DMXScreenInfo { + const char *name; /**< Name from command line or config file */ + int index; /**< Index into dmxScreens global */ + + /*---------- Back-end X server information ----------*/ + + Display *beDisplay; /**< Back-end X server's display */ + int beWidth; /**< Width of BE display */ + int beHeight; /**< Height of BE display */ + int beDepth; /**< Depth of BE display */ + int beBPP; /**< Bits per pixel of BE display */ + int beXDPI; /**< Horizontal dots per inch of BE */ + int beYDPI; /**< Vertical dots per inch of BE */ + + int beNumDepths; /**< Number of depths on BE server */ + int *beDepths; /**< Depths from BE server */ + + int beNumPixmapFormats; /**< Number of pixmap formats on BE */ + XPixmapFormatValues *bePixmapFormats; /**< Pixmap formats on BE */ + + int beNumVisuals; /**< Number of visuals on BE */ + XVisualInfo *beVisuals; /**< Visuals from BE server */ + int beDefVisualIndex; /**< Default visual index of BE */ + + int beNumDefColormaps; /**< Number of default colormaps */ + Colormap *beDefColormaps; /**< Default colormaps for DMX server */ + + Pixel beBlackPixel; /**< Default black pixel for BE */ + Pixel beWhitePixel; /**< Default white pixel for BE */ + + /*---------- Screen window information ----------*/ + + Window scrnWin; /**< "Screen" window on backend display */ + int scrnX; /**< X offset of "screen" WRT BE display */ + int scrnY; /**< Y offset of "screen" WRT BE display */ + int scrnWidth; /**< Width of "screen" */ + int scrnHeight; /**< Height of "screen" */ + int scrnXSign; /**< X offset sign of "screen" */ + int scrnYSign; /**< Y offset sign of "screen" */ + + /** Default drawables for "screen" */ + Drawable scrnDefDrawables[MAXFORMATS]; + + struct _DMXScreenInfo *next; /**< List of "screens" on same display */ + struct _DMXScreenInfo *over; /**< List of "screens" that overlap */ + + /*---------- Root window information ----------*/ + + Window rootWin; /**< "Root" window on backend display */ + int rootX; /**< X offset of "root" window WRT "screen"*/ + int rootY; /**< Y offset of "root" window WRT "screen"*/ + int rootWidth; /**< Width of "root" window */ + int rootHeight; /**< Height of "root" window */ + + int rootXOrigin; /**< Global X origin of "root" window */ + int rootYOrigin; /**< Global Y origin of "root" window */ + + /*---------- Shadow framebuffer information ----------*/ + + void *shadow; /**< Shadow framebuffer data (if enabled) */ + XlibGC shadowGC; /**< Default GC used by shadow FB code */ + XImage *shadowFBImage; /**< Screen image used by shadow FB code */ + + /*---------- Other related information ----------*/ + + int shared; /**< Non-zero if another Xdmx is running */ + + Bool WMRunningOnBE; + + Cursor noCursor; + Cursor curCursor; + /* Support for cursors on overlapped + * backend displays. */ + CursorPtr cursor; + int cursorVisible; + int cursorNotShared; /* for overlapping screens on a backend */ + + PositionType where; /**< Relative layout information */ + int whereX; /**< Relative layout information */ + int whereY; /**< Relative layout information */ + int whereRefScreen; /**< Relative layout information */ + + int savedTimeout; /**< Original screen saver timeout */ + int dpmsCapable; /**< Non-zero if backend is DPMS capable */ + int dpmsEnabled; /**< Non-zero if DPMS enabled */ + int dpmsStandby; /**< Original DPMS standby value */ + int dpmsSuspend; /**< Original DPMS suspend value */ + int dpmsOff; /**< Original DPMS off value */ + + DMXStatInfo *stat; /**< Statistics about XSync */ + Bool needsSync; /**< True if an XSync is pending */ + +#ifdef GLXEXT + /** Visual information for glxProxy */ + int numGlxVisuals; + __GLXvisualConfig *glxVisuals; + int glxMajorOpcode; + int glxErrorBase; + + /** FB config information for glxProxy */ + __GLXFBConfig *fbconfigs; + int numFBConfigs; +#endif + + /** Function pointers to wrapped screen + * functions */ + CloseScreenProcPtr CloseScreen; + SaveScreenProcPtr SaveScreen; + + CreateGCProcPtr CreateGC; + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + RestackWindowProcPtr RestackWindow; + WindowExposuresProcPtr WindowExposures; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + + ResizeWindowProcPtr ResizeWindow; + ReparentWindowProcPtr ReparentWindow; + + ChangeBorderWidthProcPtr ChangeBorderWidth; + + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + BitmapToRegionProcPtr BitmapToRegion; + + RealizeFontProcPtr RealizeFont; + UnrealizeFontProcPtr UnrealizeFont; + + CreateColormapProcPtr CreateColormap; + DestroyColormapProcPtr DestroyColormap; + InstallColormapProcPtr InstallColormap; + StoreColorsProcPtr StoreColors; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif + +#ifdef RENDER + CreatePictureProcPtr CreatePicture; + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + InitIndexedProcPtr InitIndexed; + CloseIndexedProcPtr CloseIndexed; + UpdateIndexedProcPtr UpdateIndexed; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; +#endif +} DMXScreenInfo; + +/* Global variables available to all Xserver/hw/dmx routines. */ +extern int dmxNumScreens; /**< Number of dmxScreens */ +extern DMXScreenInfo *dmxScreens; /**< List of outputs */ +extern int dmxShadowFB; /**< Non-zero if using + * shadow frame-buffer + * (deprecated) */ +extern XErrorEvent dmxLastErrorEvent; /**< Last error that + * occurred */ +extern Bool dmxErrorOccurred; /**< True if an error + * occurred */ +extern Bool dmxOffScreenOpt; /**< True if using off + * screen + * optimizations */ +extern Bool dmxSubdividePrimitives; /**< True if using the + * primitive subdivision + * optimization */ +extern Bool dmxLazyWindowCreation; /**< True if using the + * lazy window creation + * optimization */ +extern Bool dmxUseXKB; /**< True if the XKB + * extension should be + * used with the backend + * servers */ +extern int dmxDepth; /**< Requested depth if + * non-zero */ +#ifdef GLXEXT +extern Bool dmxGLXProxy; /**< True if glxProxy + * support is enabled */ +extern Bool dmxGLXSwapGroupSupport; /**< True if glxProxy + * support for swap + * groups and barriers + * is enabled */ +extern Bool dmxGLXSyncSwap; /**< True if glxProxy + * should force an XSync + * request after each + * swap buffers call */ +extern Bool dmxGLXFinishSwap; /**< True if glxProxy + * should force a + * glFinish request + * after each swap + * buffers call */ +#endif +extern char *dmxFontPath; /**< NULL if no font + * path is set on the + * command line; + * otherwise, a string + * of comma separated + * paths built from the + * command line + * specified font + * paths */ +extern Bool dmxIgnoreBadFontPaths; /**< True if bad font + * paths should be + * ignored during server + * init */ +extern Bool dmxAddRemoveScreens; /**< True if add and + * remove screens support + * is enabled */ + +/** Wrap screen or GC function pointer */ +#define DMX_WRAP(_entry, _newfunc, _saved, _actual) \ +do { \ + (_saved)->_entry = (_actual)->_entry; \ + (_actual)->_entry = (_newfunc); \ +} while (0) + +/** Unwrap screen or GC function pointer */ +#define DMX_UNWRAP(_entry, _saved, _actual) \ +do { \ + (_actual)->_entry = (_saved)->_entry; \ +} while (0) + +/* Define the MAXSCREENSALLOC/FREE macros, when MAXSCREENS patch has not + * been applied to sources. */ +#ifdef MAXSCREENS +#define MAXSCREEN_MAKECONSTSTR1(x) #x +#define MAXSCREEN_MAKECONSTSTR2(x) MAXSCREEN_MAKECONSTSTR1(x) + +#define MAXSCREEN_FAILED_TXT "Failed at [" \ + MAXSCREEN_MAKECONSTSTR2(__LINE__) ":" __FILE__ "] to allocate object: " + +#define _MAXSCREENSALLOCF(o,size,fatal) \ + do { \ + if (!o) { \ + o = xalloc((size) * sizeof(*(o))); \ + if (o) memset(o, 0, (size) * sizeof(*(o))); \ + if (!o && fatal) FatalError(MAXSCREEN_FAILED_TXT #o); \ + } \ + } while (0) +#define _MAXSCREENSALLOCR(o,size,retval) \ + do { \ + if (!o) { \ + o = xalloc((size) * sizeof(*(o))); \ + if (o) memset(o, 0, (size) * sizeof(*(o))); \ + if (!o) return retval; \ + } \ + } while (0) + +#define MAXSCREENSFREE(o) \ + do { \ + if (o) xfree(o); \ + o = NULL; \ + } while (0) + +#define MAXSCREENSALLOC(o) _MAXSCREENSALLOCF(o,MAXSCREENS, 0) +#define MAXSCREENSALLOC_FATAL(o) _MAXSCREENSALLOCF(o,MAXSCREENS, 1) +#define MAXSCREENSALLOC_RETURN(o,r) _MAXSCREENSALLOCR(o,MAXSCREENS, (r)) +#define MAXSCREENSALLOCPLUSONE(o) _MAXSCREENSALLOCF(o,MAXSCREENS+1,0) +#define MAXSCREENSALLOCPLUSONE_FATAL(o) _MAXSCREENSALLOCF(o,MAXSCREENS+1,1) +#define MAXSCREENSCALLOC(o,m) _MAXSCREENSALLOCF(o,MAXSCREENS*(m),0) +#define MAXSCREENSCALLOC_FATAL(o,m) _MAXSCREENSALLOCF(o,MAXSCREENS*(m),1) +#endif + +#endif /* DMX_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx_glxvisuals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx_glxvisuals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmx_glxvisuals.h (revision 51223) @@ -0,0 +1,64 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLXVISUALS_H +#define _GLXVISUALS_H + +#include + +/** GLX Visual private area. */ +typedef struct { + int x_visual_depth; + int x_visual_class; +} dmxGlxVisualPrivate; + +__GLXvisualConfig *GetGLXVisualConfigs(Display *dpy, + int screen, + int *nconfigs); + +__GLXFBConfig *GetGLXFBConfigs(Display *dpy, + int glxMajorOpcode, + int *nconfigs); + +__GLXvisualConfig *GetGLXVisualConfigsFromFBConfigs(__GLXFBConfig *fbconfigs, + int nfbconfigs, + XVisualInfo *visuals, + int nvisuals, + __GLXvisualConfig + *glxConfigs, + int nGlxConfigs, + int *nconfigs); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxarg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxarg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxarg.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to argument handling functions. \see dmxarg.c */ + +#ifndef _DMXARG_H_ +#define _DMXARG_H_ + +typedef struct _dmxArg *dmxArg; + +extern dmxArg dmxArgCreate(void); +extern void dmxArgFree(dmxArg a); +extern void dmxArgAdd(dmxArg a, const char *string); +extern const char *dmxArgV(dmxArg a, int item); +extern int dmxArgC(dmxArg a); +extern dmxArg dmxArgParse(const char *string); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxbackend.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxbackend.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxbackend.h (revision 51223) @@ -0,0 +1,57 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to backend input device support. \see dmxbackend.c \see + * dmxcommon.c */ + +#ifndef _DMXBACKEND_H_ +#define _DMXBACKEND_H_ + +extern pointer dmxBackendCreatePrivate(DeviceIntPtr pDevice); +extern void dmxBackendDestroyPrivate(pointer private); +extern void dmxBackendInit(DevicePtr pDev); +extern void dmxBackendLateReInit(DevicePtr pDev); +extern void dmxBackendMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxBackendKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxBackendCollectEvents(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void dmxBackendProcessInput(pointer private); +extern int dmxBackendFunctions(pointer private, DMXFunctionType function); +extern void dmxBackendUpdatePosition(pointer private, int x, int y); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcb.h (revision 51223) @@ -0,0 +1,54 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Header file for connection block functions. \see dmxcb.c. + */ + +#ifndef _DMXCB_H_ +#define _DMXCB_H_ +/** The cursor position, in global coordinates. */ +extern int dmxGlobalWidth, dmxGlobalHeight; + +/** #dmxComputeWidthHeight can either recompute the global bounding box + * or not. */ +typedef enum { + DMX_RECOMPUTE_BOUNDING_BOX, + DMX_NO_RECOMPUTE_BOUNDING_BOX +} DMXRecomputeFlag; + +extern void dmxSetWidthHeight(int width, int height); +extern void dmxComputeWidthHeight(DMXRecomputeFlag flag); +extern void dmxConnectionBlockCallback(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxclient.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxclient.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxclient.h (revision 51223) @@ -0,0 +1,152 @@ +/* $XFree86$ */ +/* + * Copyright (c) 1995 X Consortium + * Copyright 2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT, THE X CONSORTIUM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the X Consortium + * shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written + * authorization from the X Consortium. + */ + +/* + * Derived from hw/xnest/Xnest.h by Rickard E. (Rik) Faith + */ + +/** \file + * This file includes all client-side include files with proper wrapping. + */ + +#ifndef _DMXCLIENT_H_ +#define _DMXCLIENT_H_ + +#define GC XlibGC + +#ifdef _XSERVER64 +#define DMX64 +#undef _XSERVER64 +typedef unsigned long XID64; +typedef unsigned long Mask64; +typedef unsigned long Atom64; +typedef unsigned long VisualID64; +typedef unsigned long Time64; +#define XID XID64 +#define Mask Mask64 +#define Atom Atom64 +#define VisualID VisualID64 +#define Time Time64 +typedef XID Window64; +typedef XID Drawable64; +typedef XID Font64; +typedef XID Pixmap64; +typedef XID Cursor64; +typedef XID Colormap64; +typedef XID GContext64; +typedef XID KeySym64; +#define Window Window64 +#define Drawable Drawable64 +#define Font Font64 +#define Pixmap Pixmap64 +#define Cursor Cursor64 +#define Colormap Colormap64 +#define GContext GContext64 +#define KeySym KeySym64 +#endif + +#include +#include /* For _XExtension */ +#include /* from glxserver.h */ +#include /* from glxserver.h */ +#include +#include +#include +#include +#include /* For XmuSnprintf */ + +#ifdef SHAPE +#include +#endif + +#ifdef RENDER +#include +#undef PictFormatType +#endif + +#ifdef XKB +#include +#include +#endif + +#ifdef XINPUT +#include +#endif + +/* Always include these, since we query them even if we don't export XINPUT. */ +#include /* For XDevice */ +#include + +#undef GC + +#ifdef DMX64 +#define _XSERVER64 +#undef XID +#undef Mask +#undef Atom +#undef VisualID +#undef Time +#undef Window +#undef Drawable +#undef Font +#undef Pixmap +#undef Cursor +#undef Colormap +#undef GContext +#undef KeySym +#endif + +/* These are in exglobals.h, but that conflicts with X11/extensions/XKBsrv.h */ +extern int ProximityIn; +extern int ProximityOut; +extern int DeviceValuator; +extern int DeviceMotionNotify; +extern int DeviceFocusIn; +extern int DeviceFocusOut; +extern int DeviceStateNotify; +extern int DeviceMappingNotify; +extern int ChangeDeviceNotify; + +/* Some protocol gets included last, after undefines. */ +#include +#ifdef XKB +#include +#ifndef XKB_IN_SERVER +#define XKB_IN_SERVER +#endif +#include +#undef XPointer +#endif +#include + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcmap.h (revision 51223) @@ -0,0 +1,71 @@ +/* $XFree86$ */ +/* + * Copyright 2002-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Header file for colormap support. \see dmxcmap.c. */ + +#ifndef DMXCMAP_H +#define DMXCMAP_H + +#include "colormapst.h" + +/** Colormap private area. */ +typedef struct _dmxColormapPriv { + Colormap cmap; +} dmxColormapPrivRec, *dmxColormapPrivPtr; + + +extern Bool dmxCreateColormap(ColormapPtr pColormap); +extern void dmxDestroyColormap(ColormapPtr pColormap); +extern void dmxInstallColormap(ColormapPtr pColormap); +extern void dmxStoreColors(ColormapPtr pColormap, int ndef, xColorItem *pdef); + +extern Bool dmxCreateDefColormap(ScreenPtr pScreen); + +extern Bool dmxBECreateColormap(ColormapPtr pColormap); +extern Bool dmxBEFreeColormap(ColormapPtr pColormap); + +/** Private index. \see dmxcmap.c \see dmxscrinit.c \see dmxwindow.c */ +extern int dmxColormapPrivateIndex; + +/** Set colormap private structure. */ +#define DMX_SET_COLORMAP_PRIV(_pCMap, _pCMapPriv) \ + (_pCMap)->devPrivates[dmxColormapPrivateIndex].ptr \ + = (pointer)(_pCMapPriv); + +/** Get colormap private structure. */ +#define DMX_GET_COLORMAP_PRIV(_pCMap) \ + (dmxColormapPrivPtr)(_pCMap)->devPrivates[dmxColormapPrivateIndex].ptr + +#endif /* DMXCMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcommon.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86$ */ +/* + * Copyright 2002,2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to functions used by backend and console input devices. + * \see dmxcommon.c \see dmxbackend.c \see dmxconsole.c */ + +#ifndef _DMXCOMMON_H_ +#define _DMXCOMMON_H_ + +#define DMX_COMMON_OTHER \ + Display *display; \ + Window window; \ + DMXScreenInfo *be; \ + DMXLocalInputInfoPtr dmxLocal; \ + int initPointerX; \ + int initPointerY; \ + long eventMask; \ + KeybdCtrl kctrl; \ + PtrCtrl mctrl; \ + int kctrlset; \ + int mctrlset; \ + KeybdCtrl savedKctrl; \ + XModifierKeymap *savedModMap; \ + int stateSaved + +#ifdef XKB +#define DMX_COMMON_XKB \ + DMX_COMMON_OTHER; \ + XkbDescPtr xkb; \ + XkbIndicatorRec savedIndicators +#else +#define DMX_COMMON_XKB DMX_COMMON_OTHER +#endif + +#ifdef XINPUT +#define DMX_COMMON_PRIVATE \ + DMX_COMMON_XKB; \ + XDevice *xi +#else +#define DMX_COMMON_PRIVATE DMX_COMMON_OTHER +#endif + +#define GETONLYPRIVFROMPRIVATE \ + myPrivate *priv = private + +#define GETPRIVFROMPRIVATE \ + GETONLYPRIVFROMPRIVATE; \ + DMXInputInfo *dmxInput = &dmxInputs[priv->dmxLocal->inputIdx] + +#define GETDMXLOCALFROMPDEVICE \ + DevicePtr pDev = &pDevice->public; \ + DMXLocalInputInfoPtr dmxLocal = pDev->devicePrivate + +#define GETDMXINPUTFROMPRIV \ + DMXInputInfo *dmxInput = &dmxInputs[priv->dmxLocal->inputIdx] + +#define GETDMXINPUTFROMPDEVICE \ + GETDMXLOCALFROMPDEVICE; \ + DMXInputInfo *dmxInput = &dmxInputs[dmxLocal->inputIdx] + +#define GETDMXLOCALFROMPDEV \ + DMXLocalInputInfoPtr dmxLocal = pDev->devicePrivate + +#define GETDMXINPUTFROMPDEV \ + GETDMXLOCALFROMPDEV; \ + DMXInputInfo *dmxInput = &dmxInputs[dmxLocal->inputIdx] + +#define GETPRIVFROMPDEV \ + GETDMXLOCALFROMPDEV; \ + myPrivate *priv = dmxLocal->private + +#define DMX_KEYBOARD_EVENT_MASK \ + (KeyPressMask | KeyReleaseMask | KeymapStateMask) + +#define DMX_POINTER_EVENT_MASK \ + (ButtonPressMask | ButtonReleaseMask | PointerMotionMask) + +extern void dmxCommonKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxCommonKbdGetMap(DevicePtr pDev, + KeySymsPtr pKeySyms, CARD8 *pModMap); +extern void dmxCommonKbdCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +extern void dmxCommonKbdBell(DevicePtr pDev, int percent, + int volume, int pitch, int duration); +extern int dmxCommonKbdOn(DevicePtr pDev); +extern void dmxCommonKbdOff(DevicePtr pDev); +extern void dmxCommonMouGetMap(DevicePtr pDev, + unsigned char *map, int *nButtons); +extern void dmxCommonMouCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern int dmxCommonMouOn(DevicePtr pDev); +extern void dmxCommonMouOff(DevicePtr pDev); +extern int dmxFindPointerScreen(int x, int y); + +extern int dmxCommonOthOn(DevicePtr pDev); +extern void dmxCommonOthOff(DevicePtr pDev); +extern void dmxCommonOthGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); + + /* helper functions */ +extern pointer dmxCommonCopyPrivate(DeviceIntPtr pDevice); +extern void dmxCommonSaveState(pointer private); +extern void dmxCommonRestoreState(pointer private); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcompat.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcompat.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcompat.h (revision 51223) @@ -0,0 +1,45 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to VDL compatibility support. \see dmxcompat.c + * + * This file is not used by the DMX server. + */ + +#ifndef _DMXCOMPAT_H_ +#define _DMXCOMPAT_H_ + +extern DMXConfigEntryPtr dmxVDLRead(const char *filename); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconfig.h (revision 51223) @@ -0,0 +1,65 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for DMX configuration file support. \see dmxconfig.c */ + +#ifndef _DMXCONFIG_H_ +#define _DMXCONFIG_H_ +#define DMX_DEFAULT_XKB_RULES "xfree86" +#define DMX_DEFAULT_XKB_MODEL "pc101" +#define DMX_DEFAULT_XKB_LAYOUT "us" +#define DMX_DEFAULT_XKB_VARIANT NULL +#define DMX_DEFAULT_XKB_OPTIONS NULL + +extern void dmxConfigStoreDisplay(const char *display); +extern void dmxConfigStoreInput(const char *input); /* Core devices */ +extern void dmxConfigStoreXInput(const char *input); /* Non-core devices */ +extern void dmxConfigStoreFile(const char *file); +extern void dmxConfigStoreConfig(const char *config); +extern void dmxConfigConfigure(void); +extern void dmxConfigSetMaxScreens(void); + +extern void dmxConfigSetXkbRules(const char *rules); +extern void dmxConfigSetXkbModel(const char *model); +extern void dmxConfigSetXkbLayout(const char *layout); +extern void dmxConfigSetXkbVariant(const char *variant); +extern void dmxConfigSetXkbOptions(const char *options); + +extern char *dmxConfigGetXkbRules(void); +extern char *dmxConfigGetXkbModel(void); +extern char *dmxConfigGetXkbLayout(void); +extern char *dmxConfigGetXkbVariant(void); +extern char *dmxConfigGetXkbOptions(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconsole.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconsole.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxconsole.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for console device support. \see dmxconsole.c \see dmxcommon.c */ + +#ifndef _DMXCONSOLE_H_ +#define _DMXCONSOLE_H_ + +extern pointer dmxConsoleCreatePrivate(DeviceIntPtr pDevice); +extern void dmxConsoleDestroyPrivate(pointer private); +extern void dmxConsoleInit(DevicePtr pDev); +extern void dmxConsoleReInit(DevicePtr pDev); +extern void dmxConsoleMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxConsoleKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxConsoleCollectEvents(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern int dmxConsoleFunctions(pointer private, DMXFunctionType function); +extern void dmxConsoleUpdatePosition(pointer private, int x, int y); +extern void dmxConsoleKbdSetCtrl(pointer private, KeybdCtrl *ctrl); +extern void dmxConsoleCapture(DMXInputInfo *dmxInput); +extern void dmxConsoleUncapture(DMXInputInfo *dmxInput); +extern void dmxConsoleUpdateInfo(pointer private, + DMXUpdateType, WindowPtr pWindow); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxcursor.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * David H. Dawes + * Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for cursor support. \see dmxcursor.c. */ + +#ifndef DMXCURSOR_H +#define DMXCURSOR_H + +#include "mipointer.h" + +/** Cursor private area. */ +typedef struct _dmxCursorPriv { + Cursor cursor; +} dmxCursorPrivRec, *dmxCursorPrivPtr; + +/** Cursor functions for mi layer. \see dmxcursor.c \see dmxscrinit.c */ +extern miPointerScreenFuncRec dmxPointerCursorFuncs; +/** Sprite functions for mi layer. \see dmxcursor.c \see dmxscrinit.c */ +extern miPointerSpriteFuncRec dmxPointerSpriteFuncs; + +extern void dmxReInitOrigins(void); +extern void dmxInitOrigins(void); +extern void dmxInitOverlap(void); +extern void dmxCursorNoMulti(void); +extern void dmxMoveCursor(ScreenPtr pScreen, int x, int y); +extern void dmxCheckCursor(void); +extern int dmxOnScreen(int x, int y, DMXScreenInfo *dmxScreen); +extern void dmxHideCursor(DMXScreenInfo *dmxScreen); + +extern void dmxBECreateCursor(ScreenPtr pScreen, CursorPtr pCursor); +extern Bool dmxBEFreeCursor(ScreenPtr pScreen, CursorPtr pCursor); + +#define DMX_GET_CURSOR_PRIV(_pCursor, _pScreen) \ + (dmxCursorPrivPtr)(_pCursor)->devPriv[(_pScreen)->myNum] + +#endif /* DMXCURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdpms.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdpms.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdpms.h (revision 51223) @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Author: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for DPMS extension support. \see dmxdpms.c */ + +#ifndef _DMXDPMS_H_ +#define _DMXDPMS_H_ +extern void dmxDPMSInit(DMXScreenInfo *dmxScreen); +extern void dmxDPMSTerm(DMXScreenInfo *dmxScreen); +extern void dmxDPMSWakeup(void); /* Call when input is processed */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdummy.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdummy.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxdummy.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to dummy input device support. \see dmxdummy.c */ + +#ifndef _DMXDUMMY_H_ +#define _DMXDUMMY_H_ + +extern void dmxDummyMouGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern void dmxDummyKbdGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxeq.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxeq.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxeq.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to the event queue support. Some of these functions are + * included in dmxinput.h, since they are used by top-level .c + * files. \see dmxeq.c \see dmxinput.h */ + +#ifndef _DMXEQ_H_ +#define _DMXEQ_H_ +extern Bool dmxeqInit(DevicePtr pKbd, DevicePtr pPtr); +extern void dmxeqProcessInputEvents(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxevents.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to event processing functions. \see dmxevents.h */ + +#ifndef _DMXEVENTS_H_ +#define _DMXEVENTS_H_ + +extern void dmxMotion(DevicePtr pDev, int *v, int firstAxis, int axesCount, + DMXMotionType type, DMXBlockType block); +extern void dmxEnqueue(DevicePtr pDev, int type, int detail, KeySym keySym, + XEvent *e, DMXBlockType block); +extern int dmxCheckSpecialKeys(DevicePtr pDev, KeySym keySym); +extern void dmxInvalidateGlobalPosition(void); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxextension.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxextension.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxextension.h (revision 51223) @@ -0,0 +1,119 @@ +/* $XFree86$ */ +/* + * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Author: + * Rickard E. (Rik) Faith + * Kevin E. Martin + * + */ + +/** \file + * Interface for DMX extension support. These routines are called by + * function in Xserver/Xext/dmx.c. \see dmxextension.c */ + +#ifndef _DMXEXTENSION_H_ +#define _DMXEXTENSION_H_ + +/** Screen attributes. Used by #ProcDMXGetScreenAttributes and + * #ProcDMXChangeScreenAttributes. */ +typedef struct { + const char *displayName; + int logicalScreen; + + unsigned int screenWindowWidth; /* displayName's coordinate system */ + unsigned int screenWindowHeight; /* displayName's coordinate system */ + int screenWindowXoffset; /* displayName's coordinate system */ + int screenWindowYoffset; /* displayName's coordinate system */ + + unsigned int rootWindowWidth; /* screenWindow's coordinate system */ + unsigned int rootWindowHeight; /* screenWindow's coordinate system */ + int rootWindowXoffset; /* screenWindow's coordinate system */ + int rootWindowYoffset; /* screenWindow's coordinate system */ + + int rootWindowXorigin; /* global coordinate system */ + int rootWindowYorigin; /* global coordinate system */ +} DMXScreenAttributesRec, *DMXScreenAttributesPtr; + +/** Window attributes. Used by #ProcDMXGetWidowAttributes. */ +typedef struct { + int screen; + Window window; + xRectangle pos; + xRectangle vis; +} DMXWindowAttributesRec, *DMXWindowAttributesPtr; + +/** Desktop attributes. Used by #ProcDMXGetDesktopAttributes and + * #ProcDMXChangeDesktopAttributes. */ +typedef struct { + int width; + int height; + int shiftX; + int shiftY; +} DMXDesktopAttributesRec, *DMXDesktopAttributesPtr; + +/** Input attributes. Used by #ProcDMXGetInputAttributes. */ +typedef struct { + const char *name; + int inputType; + int physicalScreen; + int physicalId; + int isCore; + int sendsCore; + int detached; +} DMXInputAttributesRec, *DMXInputAttributesPtr; + + +extern unsigned long dmxGetNumScreens(void); +extern void dmxForceWindowCreation(WindowPtr pWindow); +extern void dmxFlushPendingSyncs(void); +extern Bool dmxGetScreenAttributes(int physical, + DMXScreenAttributesPtr attr); +extern Bool dmxGetWindowAttributes(WindowPtr pWindow, + DMXWindowAttributesPtr attr); +extern void dmxGetDesktopAttributes(DMXDesktopAttributesPtr attr); +extern int dmxGetInputCount(void); +extern int dmxGetInputAttributes(int deviceId, + DMXInputAttributesPtr attr); +extern int dmxAddInput(DMXInputAttributesPtr attr, int *deviceId); +extern int dmxRemoveInput(int deviceId); + +extern int dmxConfigureScreenWindows(int nscreens, + CARD32 *screens, + DMXScreenAttributesPtr attribs, + int *errorScreen); + +extern int dmxConfigureDesktop(DMXDesktopAttributesPtr attribs); + +/* dmxUpdateScreenResources exposed for dmxCreateWindow in dmxwindow.c */ +extern void dmxUpdateScreenResources(ScreenPtr pScreen, + int x, int y, int w, int h); + +extern int dmxAttachScreen(int idx, DMXScreenAttributesPtr attr); +extern int dmxDetachScreen(int idx); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxfont.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxfont.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxfont.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for font-related functions. \see dmxfont.c */ + +#ifndef DMXFONT_H +#define DMXFONT_H + +#include + +/** Font private area. */ +typedef struct _dmxFontPriv { + int refcnt; + XFontStruct **font; +} dmxFontPrivRec, *dmxFontPrivPtr; + +extern void dmxInitFonts(void); +extern void dmxResetFonts(void); + +extern Bool dmxRealizeFont(ScreenPtr pScreen, FontPtr pFont); +extern Bool dmxUnrealizeFont(ScreenPtr pScreen, FontPtr pFont); + +extern Bool dmxBELoadFont(ScreenPtr pScreen, FontPtr pFont); +extern Bool dmxBEFreeFont(ScreenPtr pScreen, FontPtr pFont); + +extern int dmxFontPrivateIndex; + +#endif /* DMXFONT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgc.h (revision 51223) @@ -0,0 +1,90 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for GC support. \see dmxgc.c */ + +#ifndef DMXGC_H +#define DMXGC_H + +#include "gcstruct.h" + +/** GC private area. */ +typedef struct _dmxGCPriv { + GCOps *ops; + GCFuncs *funcs; + XlibGC gc; + Bool msc; +} dmxGCPrivRec, *dmxGCPrivPtr; + + +extern Bool dmxInitGC(ScreenPtr pScreen); + +extern Bool dmxCreateGC(GCPtr pGC); +extern void dmxValidateGC(GCPtr pGC, unsigned long changes, + DrawablePtr pDrawable); +extern void dmxChangeGC(GCPtr pGC, unsigned long mask); +extern void dmxCopyGC(GCPtr pGCSrc, unsigned long changes, GCPtr pGCDst); +extern void dmxDestroyGC(GCPtr pGC); +extern void dmxChangeClip(GCPtr pGC, int type, pointer pvalue, int nrects); +extern void dmxDestroyClip(GCPtr pGC); +extern void dmxCopyClip(GCPtr pGCDst, GCPtr pGCSrc); + +extern void dmxBECreateGC(ScreenPtr pScreen, GCPtr pGC); +extern Bool dmxBEFreeGC(GCPtr pGC); + +/** Private index. \see dmxgc.c \see dmxscrinit.c */ +extern int dmxGCPrivateIndex; + +/** Get private. */ +#define DMX_GET_GC_PRIV(_pGC) \ + (dmxGCPrivPtr)(_pGC)->devPrivates[dmxGCPrivateIndex].ptr + +#define DMX_GC_FUNC_PROLOGUE(_pGC) \ +do { \ + dmxGCPrivPtr _pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_UNWRAP(funcs, _pGCPriv, (_pGC)); \ + if (_pGCPriv->ops) \ + DMX_UNWRAP(ops, _pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_GC_FUNC_EPILOGUE(_pGC) \ +do { \ + dmxGCPrivPtr _pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_WRAP(funcs, &dmxGCFuncs, _pGCPriv, (_pGC)); \ + if (_pGCPriv->ops) \ + DMX_WRAP(ops, &dmxGCOps, _pGCPriv, (_pGC)); \ +} while (0) + +#endif /* DMXGC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgcops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgcops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxgcops.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for gcops support. \see dmxgcops.c */ + +#ifndef DMXGCOPS_H +#define DMXGCOPS_H + +extern void dmxFillSpans(DrawablePtr pDrawable, GCPtr pGC, + int nInit, DDXPointPtr pptInit, int *pwidthInit, + int fSorted); +extern void dmxSetSpans(DrawablePtr pDrawable, GCPtr pGC, + char *psrc, DDXPointPtr ppt, int *pwidth, int nspans, + int fSorted); +extern void dmxPutImage(DrawablePtr pDrawable, GCPtr pGC, + int depth, int x, int y, int w, int h, + int leftPad, int format, char *pBits); +extern RegionPtr dmxCopyArea(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, + int dstx, int dsty); +extern RegionPtr dmxCopyPlane(DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int width, int height, + int dstx, int dsty, unsigned long bitPlane); +extern void dmxPolyPoint(DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr pptInit); +extern void dmxPolylines(DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr pptInit); +extern void dmxPolySegment(DrawablePtr pDrawable, GCPtr pGC, + int nseg, xSegment *pSegs); +extern void dmxPolyRectangle(DrawablePtr pDrawable, GCPtr pGC, + int nrects, xRectangle *pRects); +extern void dmxPolyArc(DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *parcs); +extern void dmxFillPolygon(DrawablePtr pDrawable, GCPtr pGC, + int shape, int mode, int count, DDXPointPtr pPts); +extern void dmxPolyFillRect(DrawablePtr pDrawable, GCPtr pGC, + int nrectFill, xRectangle *prectInit); +extern void dmxPolyFillArc(DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *parcs); +extern int dmxPolyText8(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, char *chars); +extern int dmxPolyText16(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, unsigned short *chars); +extern void dmxImageText8(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, char *chars); +extern void dmxImageText16(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, int count, unsigned short *chars); +extern void dmxImageGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); +extern void dmxPolyGlyphBlt(DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); +extern void dmxPushPixels(GCPtr pGC, PixmapPtr pBitMap, DrawablePtr pDst, + int w, int h, int x, int y); + +extern void dmxGetImage(DrawablePtr pDrawable, int sx, int sy, int w, int h, + unsigned int format, unsigned long planeMask, + char *pdstLine); +extern void dmxGetSpans(DrawablePtr pDrawable, int wMax, + DDXPointPtr ppt, int *pwidth, int nspans, + char *pdstStart); + +#endif /* DMXGCOPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinit.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86$ */ +/* + * Copyright 2004 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for initialization. \see dmxinit.c */ + +#ifndef DMXINIT_H +#define DMXINIT_H + +#include "scrnintstr.h" + +extern Bool dmxOpenDisplay(DMXScreenInfo *dmxScreen); +extern void dmxSetErrorHandler(DMXScreenInfo *dmxScreen); +extern void dmxCheckForWM(DMXScreenInfo *dmxScreen); +extern void dmxGetScreenAttribs(DMXScreenInfo *dmxScreen); +extern Bool dmxGetVisualInfo(DMXScreenInfo *dmxScreen); +extern void dmxGetColormaps(DMXScreenInfo *dmxScreen); +extern void dmxGetPixmapFormats(DMXScreenInfo *dmxScreen); + +#endif /* DMXINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinput.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinput.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinput.h (revision 51223) @@ -0,0 +1,163 @@ +/* $XFree86$ */ +/* + * Copyright 2001,2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * David H. Dawes + * Kevin E. Martin + * Rickard E. (Rik) Faith + * + */ + +/** \file + * This file provides access to: + * - global variables available to all hw/dmx routines, and + * - enumerations and typedefs needed by input routines in hw/dmx (and + * hw/dmx/input). + * + * The goal is that no files in hw/dmx should include header files from + * hw/dmx/input -- the interface defined here should be the only + * interface exported to the hw/dmx layer. \see input/dmxinputinit.c. + */ + +#ifndef DMXINPUT_H +#define DMXINPUT_H + +/** Maximum number of file descriptors for SIGIO handling */ +#define DMX_MAX_SIGIO_FDS 4 + +struct _DMXInputInfo; + +/** Reason why window layout was updated. */ +typedef enum { + DMX_UPDATE_REALIZE, /**< Window realized */ + DMX_UPDATE_UNREALIZE, /**< Window unrealized */ + DMX_UPDATE_RESTACK, /**< Stacking order changed */ + DMX_UPDATE_COPY, /**< Window copied */ + DMX_UPDATE_RESIZE, /**< Window resized */ + DMX_UPDATE_REPARENT /**< Window reparented */ +} DMXUpdateType; + +typedef void (*ProcessInputEventsProc)(struct _DMXInputInfo *); +typedef void (*UpdateWindowInfoProc)(struct _DMXInputInfo *, + DMXUpdateType, WindowPtr); + +/** An opaque structure that is only exposed in the dmx/input layer. */ +typedef struct _DMXLocalInputInfo *DMXLocalInputInfoPtr; + +/** State of the SIGIO engine */ +typedef enum { + DMX_NOSIGIO = 0, /**< Device does not use SIGIO at all. */ + DMX_USESIGIO, /**< Device can use SIGIO, but is not + * (e.g., because the VT is switch + * away). */ + DMX_ACTIVESIGIO /**< Device is currently using SIGIO. */ +} dmxSigioState; + +/** DMXInputInfo is typedef'd in #dmx.h so that all routines can have + * access to the global pointers. However, the elements are only + * available to input-related routines. */ +struct _DMXInputInfo { + const char *name; /**< Name of input display or device + * (from command line or config + * file) */ + Bool freename; /**< If true, free name on destroy */ + Bool detached; /**< If true, input screen is detached */ + int inputIdx; /**< Index into #dmxInputs global */ + int scrnIdx; /**< Index into #dmxScreens global */ + Bool core; /**< If True, initialize these + * devices as devices that send core + * events */ + Bool console; /**< True if console and backend + * input share the same backend + * display */ + + Bool windows; /**< True if window outlines are + * draw in console */ + + ProcessInputEventsProc processInputEvents; + UpdateWindowInfoProc updateWindowInfo; + + /* Local input information */ + dmxSigioState sigioState; /**< Current stat */ + int sigioFdCount; /**< Number of fds in use */ + int sigioFd[DMX_MAX_SIGIO_FDS]; /**< List of fds */ + Bool sigioAdded[DMX_MAX_SIGIO_FDS]; /**< Active fds */ + + + /** True if a VT switch is pending, but has not yet happened. */ + int vt_switch_pending; + + /** True if a VT switch has happened. */ + int vt_switched; + + /** Number of devices handled in this _DMXInputInfo structure. */ + int numDevs; + + /** List of actual input devices. Each _DMXInputInfo structure can + * refer to more than one device. For example, the keyboard and the + * pointer of a backend display; or all of the XInput extension + * devices on a backend display. */ + DMXLocalInputInfoPtr *devs; + + char *keycodes; /**< XKB keycodes from command line */ + char *symbols; /**< XKB symbols from command line */ + char *geometry; /**< XKB geometry from command line */ +}; + +extern int dmxNumInputs; /**< Number of #dmxInputs */ +extern DMXInputInfo *dmxInputs; /**< List of inputs */ + +extern void dmxInputInit(DMXInputInfo *dmxInput); +extern void dmxInputReInit(DMXInputInfo *dmxInput); +extern void dmxInputLateReInit(DMXInputInfo *dmxInput); +extern void dmxInputFree(DMXInputInfo *dmxInput); +extern void dmxInputLogDevices(void); +extern void dmxUpdateWindowInfo(DMXUpdateType type, WindowPtr pWindow); + +/* These functions are defined in input/dmxeq.c */ +extern Bool dmxeqInitialized(void); +extern void dmxeqEnqueue(xEvent *e); +extern void dmxeqSwitchScreen(ScreenPtr pScreen, Bool fromDIX); + +/* This type is used in input/dmxevents.c. Also, these functions are + * defined in input/dmxevents.c */ +typedef enum { + DMX_NO_BLOCK = 0, + DMX_BLOCK = 1 +} DMXBlockType; + +extern void dmxGetGlobalPosition(int *x, int *y); +extern DMXScreenInfo *dmxFindFirstScreen(int x, int y); +extern void dmxCoreMotion(int x, int y, int delta, + DMXBlockType block); + +/* Support for dynamic addition of inputs. This functions is defined in + * config/dmxconfig.c */ +extern DMXInputInfo *dmxConfigAddInput(const char *name, int core); +#endif /* DMXINPUT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinputinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinputinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxinputinit.h (revision 51223) @@ -0,0 +1,294 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for low-level input support. \see dmxinputinit.c */ + +#ifndef _DMXINPUTINIT_H_ +#define _DMXINPUTINIT_H_ + +#include "dmx.h" +#include "dmxinput.h" +#include "dmxlog.h" + + +#define DMX_LOCAL_DEFAULT_KEYBOARD "kbd" +#define DMX_LOCAL_DEFAULT_POINTER "ps2" +#define DMX_MAX_BUTTONS 256 +#define DMX_MOTION_SIZE 256 +#define DMX_MAX_VALUATORS 32 +#define DMX_MAX_AXES 32 +#define DMX_MAX_XINPUT_EVENT_TYPES 100 +#define DMX_MAP_ENTRIES 16 /* Must be a power of 2 */ +#define DMX_MAP_MASK (DMX_MAP_ENTRIES - 1) + +typedef enum { + DMX_FUNCTION_GRAB, + DMX_FUNCTION_TERMINATE, + DMX_FUNCTION_FINE +} DMXFunctionType; + +typedef enum { + DMX_LOCAL_HIGHLEVEL, + DMX_LOCAL_KEYBOARD, + DMX_LOCAL_MOUSE, + DMX_LOCAL_OTHER +} DMXLocalInputType; + +typedef enum { + DMX_LOCAL_TYPE_LOCAL, + DMX_LOCAL_TYPE_CONSOLE, + DMX_LOCAL_TYPE_BACKEND, + DMX_LOCAL_TYPE_COMMON +} DMXLocalInputExtType; + +typedef enum { + DMX_RELATIVE, + DMX_ABSOLUTE, + DMX_ABSOLUTE_CONFINED +} DMXMotionType; + +/** Stores information from low-level device that is used to initialize + * the device at the dix level. */ +typedef struct _DMXLocalInitInfo { + int keyboard; /**< Non-zero if the device is a keyboard */ + + int keyClass; /**< Non-zero if keys are present */ + KeySymsRec keySyms; /**< Key symbols */ + int freemap; /**< If non-zero, free keySyms.map */ + CARD8 modMap[MAP_LENGTH]; /**< Modifier map */ +#ifdef XKB + XkbDescPtr xkb; /**< XKB description */ + XkbComponentNamesRec names; /**< XKB component names */ + int freenames; /**< Non-zero if names should be free'd */ + int force; /**< Do not allow command line override */ +#endif + + int buttonClass; /**< Non-zero if buttons are present */ + int numButtons; /**< Number of buttons */ + unsigned char map[DMX_MAX_BUTTONS]; /**< Button map */ + + int valuatorClass; /**< Non-zero if valuators are + * present */ + int numRelAxes; /**< Number of relative axes */ + int numAbsAxes; /**< Number of absolute axes */ + int minval[DMX_MAX_AXES]; /**< Minimum values */ + int maxval[DMX_MAX_AXES]; /**< Maximum values */ + int res[DMX_MAX_AXES]; /**< Resolution */ + int minres[DMX_MAX_AXES]; /**< Minimum resolutions */ + int maxres[DMX_MAX_AXES]; /**< Maximum resolutions */ + + int focusClass; /**< Non-zero if device can + * cause focus */ + int proximityClass; /**< Non-zero if device + * causes proximity events */ + int kbdFeedbackClass; /**< Non-zero if device has + * keyboard feedback */ + int ptrFeedbackClass; /**< Non-zero if device has + * pointer feedback */ + int ledFeedbackClass; /**< Non-zero if device has + * LED indicators */ + int belFeedbackClass; /**< Non-zero if device has a + * bell */ + int intFeedbackClass; /**< Non-zero if device has + * integer feedback */ + int strFeedbackClass; /**< Non-zero if device has + * string feedback */ + + int maxSymbols; /**< Maximum symbols */ + int maxSymbolsSupported; /**< Maximum symbols supported */ + KeySym *symbols; /**< Key symbols */ +} DMXLocalInitInfo, *DMXLocalInitInfoPtr; + +typedef pointer (*dmxCreatePrivateProcPtr)(DeviceIntPtr); +typedef void (*dmxDestroyPrivateProcPtr)(pointer); + +typedef void (*dmxInitProcPtr)(DevicePtr); +typedef void (*dmxReInitProcPtr)(DevicePtr); +typedef void (*dmxLateReInitProcPtr)(DevicePtr); +typedef void (*dmxGetInfoProcPtr)(DevicePtr, DMXLocalInitInfoPtr); +typedef int (*dmxOnProcPtr)(DevicePtr); +typedef void (*dmxOffProcPtr)(DevicePtr); +typedef void (*dmxUpdatePositionProcPtr)(pointer, int x, int y); + +typedef void (*dmxVTPreSwitchProcPtr)(pointer); /* Turn I/O Off */ +typedef void (*dmxVTPostSwitchProcPtr)(pointer); /* Turn I/O On */ +typedef void (*dmxVTSwitchReturnProcPtr)(pointer); +typedef int (*dmxVTSwitchProcPtr)(pointer, int vt, + dmxVTSwitchReturnProcPtr, pointer); + +typedef void (*dmxMotionProcPtr)(DevicePtr, + int *valuators, + int firstAxis, + int axesCount, + DMXMotionType type, + DMXBlockType block); +typedef void (*dmxEnqueueProcPtr)(DevicePtr, int type, int detail, + KeySym keySym, XEvent *e, + DMXBlockType block); +typedef int (*dmxCheckSpecialProcPtr)(DevicePtr, KeySym keySym); +typedef void (*dmxCollectEventsProcPtr)(DevicePtr, + dmxMotionProcPtr, + dmxEnqueueProcPtr, + dmxCheckSpecialProcPtr, + DMXBlockType); +typedef void (*dmxProcessInputProcPtr)(pointer); +typedef void (*dmxUpdateInfoProcPtr)(pointer, DMXUpdateType, WindowPtr); +typedef int (*dmxFunctionsProcPtr)(pointer, DMXFunctionType); + +typedef void (*dmxKBCtrlProcPtr)(DevicePtr, KeybdCtrl *ctrl); +typedef void (*dmxMCtrlProcPtr)(DevicePtr, PtrCtrl *ctrl); +typedef void (*dmxKBBellProcPtr)(DevicePtr, int percent, + int volume, int pitch, int duration); + +/** Stores a mapping between the device id on the remote X server and + * the id on the DMX server */ +typedef struct _DMXEventMap { + int remote; /**< Event number on remote X server */ + int server; /**< Event number (unbiased) on DMX server */ +} DMXEventMap; + +/** This is the device-independent structure used by the low-level input + * routines. The contents are not exposed to top-level .c files (except + * dmxextensions.c). \see dmxinput.h \see dmxextensions.c */ +typedef struct _DMXLocalInputInfo { + const char *name; /**< Device name */ + DMXLocalInputType type; /**< Device type */ + DMXLocalInputExtType extType; /**< Extended device type */ + int binding; /**< Count of how many consecutive + * structs are bound to the same + * device */ + + /* Low-level (e.g., keyboard/mouse drivers) */ + + dmxCreatePrivateProcPtr create_private; /**< Create + * device-dependent + * private */ + dmxDestroyPrivateProcPtr destroy_private; /**< Destroy + * device-dependent + * private */ + dmxInitProcPtr init; /**< Initialize device */ + dmxReInitProcPtr reinit; /**< Reinitialize device + * (during a + * reconfiguration) */ + dmxLateReInitProcPtr latereinit; /**< Reinitialize a device + * (called very late + * during a + * reconfiguration) */ + dmxGetInfoProcPtr get_info; /**< Get device information */ + dmxOnProcPtr on; /**< Turn device on */ + dmxOffProcPtr off; /**< Turn device off */ + dmxUpdatePositionProcPtr update_position; /**< Called when another + * device updates the + * cursor position */ + dmxVTPreSwitchProcPtr vt_pre_switch; /**< Called before a VT switch */ + dmxVTPostSwitchProcPtr vt_post_switch; /**< Called after a VT switch */ + dmxVTSwitchProcPtr vt_switch; /**< Causes a VT switch */ + + dmxCollectEventsProcPtr collect_events; /**< Collect and enqueue + * events from the + * device*/ + dmxProcessInputProcPtr process_input; /**< Process event (from + * queue) */ + dmxFunctionsProcPtr functions; + dmxUpdateInfoProcPtr update_info; /**< Update window layout + * information */ + + dmxMCtrlProcPtr mCtrl; /**< Pointer control */ + dmxKBCtrlProcPtr kCtrl; /**< Keyboard control */ + dmxKBBellProcPtr kBell; /**< Bell control */ + + pointer private; /**< Device-dependent private */ + int isCore; /**< Is a DMX core device */ + int sendsCore; /**< Sends DMX core events */ + KeybdCtrl kctrl; /**< Keyboard control */ + PtrCtrl mctrl; /**< Pointer control */ + + DeviceIntPtr pDevice; /**< X-level device */ + int inputIdx; /**< High-level index */ + int lastX, lastY; /**< Last known position; + * for XInput in + * dmxevents.c */ + + int head; /**< XInput motion history + * head */ + int tail; /**< XInput motion history + * tail */ + unsigned long *history; /**< XInput motion history */ + int *valuators; /**< Cache of previous values */ + + /* for XInput ChangePointerDevice */ + int (*savedMotionProc)(DeviceIntPtr, + xTimecoord *, + unsigned long, + unsigned long, + ScreenPtr); + int savedMotionEvents; /**< Saved motion events */ + int savedSendsCore; /**< Saved sends-core flag */ + + DMXEventMap map[DMX_MAP_ENTRIES]; /**< XInput device id map */ + int mapOptimize; /**< XInput device id + * map + * optimization */ + + long deviceId; /**< device id on remote side, + * if any */ + const char *deviceName; /**< devive name on remote + * side, if any */ +} DMXLocalInputInfoRec; + +extern DMXLocalInputInfoPtr dmxLocalCorePointer, dmxLocalCoreKeyboard; + +extern void dmxLocalInitInput(DMXInputInfo *dmxInput); +extern DMXLocalInputInfoPtr dmxInputCopyLocal(DMXInputInfo *dmxInput, + DMXLocalInputInfoPtr s); + +extern void dmxChangePointerControl(DeviceIntPtr pDevice, PtrCtrl *ctrl); +extern void dmxKeyboardKbdCtrlProc(DeviceIntPtr pDevice, KeybdCtrl *ctrl); +extern void dmxKeyboardBellProc(int percent, DeviceIntPtr pDevice, + pointer ctrl, int unknown); + +extern int dmxInputExtensionErrorHandler(Display *dsp, char *name, + char *reason); + +extern int dmxInputDetach(DMXInputInfo *dmxInput); +extern void dmxInputDetachAll(DMXScreenInfo *dmxScreen); +extern int dmxInputDetachId(int id); +extern DMXInputInfo *dmxInputLocateId(int id); +extern int dmxInputAttachConsole(const char *name, int isCore, + int *id); +extern int dmxInputAttachBackend(int physicalScreen, int isCore, + int *id); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxlog.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxlog.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxlog.h (revision 51223) @@ -0,0 +1,79 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * This header is included by all files that need to use the DMX logging + * facilities. */ + +#ifndef _DMXLOG_H_ +#define _DMXLOG_H_ + +/** Logging levels -- output is tunable with #dmxSetLogLevel. */ +typedef enum { + dmxDebug, /**< Usually verbose debugging info */ + dmxInfo, /**< Non-warning information */ + dmxWarning, /**< A warning that may indicate DMX + * will not function as the user + * intends. */ + dmxError, /**< A non-fatal error that probably + * indicates DMX will not function as + * desired.*/ + dmxFatal /**< A fatal error that will cause DMX + * to shut down. */ +} dmxLogLevel; + +/* Logging functions used by Xserver/hw/dmx routines. */ +extern dmxLogLevel dmxSetLogLevel(dmxLogLevel newLevel); +extern dmxLogLevel dmxGetLogLevel(void); +extern void dmxLog(dmxLogLevel logLevel, const char *format, ...); +extern void dmxLogCont(dmxLogLevel logLevel, const char *format, ...); +extern const char *dmxEventName(int type); + +#ifndef DMX_LOG_STANDALONE +extern void dmxLogOutput(DMXScreenInfo *dmxScreen, const char *format, ...); +extern void dmxLogOutputCont(DMXScreenInfo *dmxScreen, const char *format, + ...); +extern void dmxLogOutputWarning(DMXScreenInfo *dmxScreen, const char *format, + ...); +extern void dmxLogInput(DMXInputInfo *dmxInput, const char *format, ...); +extern void dmxLogInputCont(DMXInputInfo *dmxInput, const char *format, ...); +extern void dmxLogArgs(dmxLogLevel logLevel, int argc, char **argv); +extern void dmxLogVisual(DMXScreenInfo *dmxScreen, XVisualInfo *vi, + int defaultVisual); +#ifdef XINPUT +extern const char *dmxXInputEventName(int type); +#endif +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmap.h (revision 51223) @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + */ + +/** \file + * Interface to XInput event mapping support. \see dmxmap.c */ + +#ifndef _DMXMAP_H_ +#define _DMXMAP_H_ +extern void dmxMapInsert(DMXLocalInputInfoPtr dmxLocal, + int remoteEvent, int serverEvent); +extern void dmxMapClear(DMXLocalInputInfoPtr dmxLocal); +extern int dmxMapLookup(DMXLocalInputInfoPtr dmxLocal, int remoteEvent); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmotion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmotion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxmotion.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to functions supporting motion events. \see dmxmotion.c */ + +#ifndef _DMXMOTION_H_ +#define _DMXMOTION_H_ + +extern int dmxPointerGetMotionBufferSize(void); +extern int dmxPointerGetMotionEvents(DeviceIntPtr pDevice, + xTimecoord *coords, + unsigned long start, + unsigned long stop, + ScreenPtr pScreen); +extern void dmxPointerPutMotionEvent(DeviceIntPtr pDevice, + int firstAxis, int axesCount, int *v, + unsigned long time); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxparse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxparse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxparse.h (revision 51223) @@ -0,0 +1,298 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to DMX configuration file parser. \see dmxparse.c */ + +#ifndef _DMXPARSE_H_ +#define _DMXPARSE_H_ + +#include /* For FILE */ + +/** Stores tokens not stored in other structures (e.g., keywords and ;) */ +typedef struct _DMXConfigToken { + int token; + int line; + const char *comment; +} DMXConfigToken, *DMXConfigTokenPtr; + +/** Stores parsed strings. */ +typedef struct _DMXConfigString { + int token; + int line; + const char *comment; + const char *string; + struct _DMXConfigString *next; +} DMXConfigString, *DMXConfigStringPtr; + +/** Stores parsed numbers. */ +typedef struct _DMXConfigNumber { + int token; + int line; + const char *comment; + int number; +} DMXConfigNumber, *DMXConfigNumberPtr; + +/** Stores parsed pairs (e.g., x y) */ +typedef struct _DMXConfigPair { + int token; + int line; + const char *comment; + int x; + int y; + int xsign; + int ysign; +} DMXConfigPair, *DMXConfigPairPtr; + +/** Stores parsed comments not stored with a token. */ +typedef struct _DMXConfigComment { + int token; + int line; + const char *comment; +} DMXConfigComment, *DMXConfigCommentPtr; + +typedef enum { + dmxConfigComment, + dmxConfigVirtual, + dmxConfigDisplay, + dmxConfigWall, + dmxConfigOption, + dmxConfigParam +} DMXConfigType; + +/** Stores a geometry specification. */ +typedef struct _DMXConfigPartDim { + DMXConfigPairPtr dim; + DMXConfigPairPtr offset; +} DMXConfigPartDim, *DMXConfigPartDimPtr; + +/** Stores a pair of geometry specifications. */ +typedef struct _DMXConfigFullDim { + DMXConfigPartDimPtr scrn; + DMXConfigPartDimPtr root; +} DMXConfigFullDim, *DMXConfigFullDimPtr; + +/** Stores parsed display information. */ +typedef struct _DMXConfigDisplay { + /* Summary information */ + const char *name; + /* Screen Window Geometry */ + int scrnWidth, scrnHeight; + int scrnX, scrnY; + int scrnXSign, scrnYSign; + /* Root Window Geometry */ + int rootWidth, rootHeight; + int rootX, rootY; + int rootXSign, rootYSign; + /* Origin in global space */ + int rootXOrigin, rootYOrigin; + + /* Raw configuration information */ + DMXConfigTokenPtr start; + DMXConfigStringPtr dname; + DMXConfigFullDimPtr dim; + DMXConfigPairPtr origin; + DMXConfigTokenPtr end; +} DMXConfigDisplay, *DMXConfigDisplayPtr; + +/** Stores parsed wall information. */ +typedef struct _DMXConfigWall { + /* Summary information */ + int width, height; /* dimensions of displays */ + int xwall, ywall; /* dimensions of wall, in tiles */ + + + /* Raw configuration informaiton */ + DMXConfigTokenPtr start; + DMXConfigPairPtr wallDim; + DMXConfigPairPtr displayDim; + DMXConfigStringPtr nameList; + DMXConfigTokenPtr end; +} DMXConfigWall, *DMXConfigWallPtr; + +/** Stores parsed option information. */ +typedef struct _DMXConfigOption { + /* Summary information */ + char *string; + + /* Raw configuration informaiton */ + DMXConfigTokenPtr start; + DMXConfigStringPtr option; + DMXConfigTokenPtr end; +} DMXConfigOption, *DMXConfigOptionPtr; + +/** Stores parsed param information. */ +typedef struct _DMXConfigParam { + int argc; + const char **argv; + + DMXConfigTokenPtr start; + DMXConfigTokenPtr open; + DMXConfigStringPtr param; + DMXConfigTokenPtr close; + DMXConfigTokenPtr end; /* Either open/close OR end */ + struct _DMXConfigParam *next; +} DMXConfigParam, *DMXConfigParamPtr; + +/** Stores options under an entry (subentry). */ +typedef struct _DMXConfigSub { + DMXConfigType type; + DMXConfigCommentPtr comment; + DMXConfigDisplayPtr display; + DMXConfigWallPtr wall; + DMXConfigOptionPtr option; + DMXConfigParamPtr param; + struct _DMXConfigSub *next; +} DMXConfigSub, *DMXConfigSubPtr; + +/** Stores parsed virtual information. */ +typedef struct _DMXConfigVirtual { + /* Summary information */ + const char *name; + int width, height; + + /* Raw configuration information */ + DMXConfigTokenPtr start; + DMXConfigStringPtr vname; + DMXConfigPairPtr dim; + DMXConfigTokenPtr open; + DMXConfigSubPtr subentry; + DMXConfigTokenPtr close; +} DMXConfigVirtual, *DMXConfigVirtualPtr; + +/** Heads entry storage. */ +typedef struct _DMXConfigEntry { + DMXConfigType type; + DMXConfigCommentPtr comment; + DMXConfigVirtualPtr virtual; + struct _DMXConfigEntry *next; +} DMXConfigEntry, *DMXConfigEntryPtr; + +extern DMXConfigEntryPtr dmxConfigEntry; + +extern int yylex(void); +extern int yydebug; +extern void yyerror(const char *message); + +extern void dmxConfigLog(const char *format, ...); +extern void *dmxConfigAlloc(unsigned long bytes); +extern void *dmxConfigRealloc(void *orig, + unsigned long orig_bytes, + unsigned long bytes); +extern const char *dmxConfigCopyString(const char *string, + int length); +extern void dmxConfigFree(void *area); +extern DMXConfigTokenPtr dmxConfigCreateToken(int token, int line, + const char *comment); +extern void dmxConfigFreeToken(DMXConfigTokenPtr p); +extern DMXConfigStringPtr dmxConfigCreateString(int token, int line, + const char *comment, + const char *string); +extern void dmxConfigFreeString(DMXConfigStringPtr p); +extern DMXConfigNumberPtr dmxConfigCreateNumber(int token, int line, + const char *comment, + int number); +extern void dmxConfigFreeNumber(DMXConfigNumberPtr p); +extern DMXConfigPairPtr dmxConfigCreatePair(int token, int line, + const char *comment, + int x, int y, + int xsign, int ysign); +extern void dmxConfigFreePair(DMXConfigPairPtr p); +extern DMXConfigCommentPtr dmxConfigCreateComment(int token, int line, + const char *comment); +extern void dmxConfigFreeComment(DMXConfigCommentPtr p); +extern DMXConfigPartDimPtr dmxConfigCreatePartDim(DMXConfigPairPtr pDim, + DMXConfigPairPtr pOffset); +extern void dmxConfigFreePartDim(DMXConfigPartDimPtr p); +extern DMXConfigFullDimPtr dmxConfigCreateFullDim(DMXConfigPartDimPtr pScrn, + DMXConfigPartDimPtr pRoot); +extern void dmxConfigFreeFullDim(DMXConfigFullDimPtr p); +extern DMXConfigDisplayPtr dmxConfigCreateDisplay(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pName, + DMXConfigFullDimPtr pDim, + DMXConfigPairPtr pOrigin, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeDisplay(DMXConfigDisplayPtr p); +extern DMXConfigWallPtr dmxConfigCreateWall(DMXConfigTokenPtr pStart, + DMXConfigPairPtr pWallDim, + DMXConfigPairPtr pDisplayDim, + DMXConfigStringPtr pNameList, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeWall(DMXConfigWallPtr p); +extern DMXConfigOptionPtr dmxConfigCreateOption(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pOption, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeOption(DMXConfigOptionPtr p); +extern DMXConfigParamPtr dmxConfigCreateParam(DMXConfigTokenPtr pStart, + DMXConfigTokenPtr pOpen, + DMXConfigStringPtr pParam, + DMXConfigTokenPtr pClose, + DMXConfigTokenPtr pEnd); +extern void dmxConfigFreeParam(DMXConfigParamPtr p); +extern const char **dmxConfigLookupParam(DMXConfigParamPtr p, + const char *key, + int *argc); +extern DMXConfigSubPtr dmxConfigCreateSub(DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigDisplayPtr display, + DMXConfigWallPtr wall, + DMXConfigOptionPtr option, + DMXConfigParamPtr param); +extern void dmxConfigFreeSub(DMXConfigSubPtr sub); +extern DMXConfigSubPtr dmxConfigSubComment(DMXConfigCommentPtr comment); +extern DMXConfigSubPtr dmxConfigSubDisplay(DMXConfigDisplayPtr display); +extern DMXConfigSubPtr dmxConfigSubWall(DMXConfigWallPtr wall); +extern DMXConfigSubPtr dmxConfigSubOption(DMXConfigOptionPtr option); +extern DMXConfigSubPtr dmxConfigSubParam(DMXConfigParamPtr param); +extern DMXConfigSubPtr dmxConfigAddSub(DMXConfigSubPtr head, + DMXConfigSubPtr sub); +extern DMXConfigVirtualPtr dmxConfigCreateVirtual(DMXConfigTokenPtr pStart, + DMXConfigStringPtr pName, + DMXConfigPairPtr pDim, + DMXConfigTokenPtr pOpen, + DMXConfigSubPtr pSubentry, + DMXConfigTokenPtr pClose); +extern void dmxConfigFreeVirtual(DMXConfigVirtualPtr virtual); +extern DMXConfigEntryPtr dmxConfigCreateEntry(DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigVirtualPtr virtual); +extern void dmxConfigFreeEntry(DMXConfigEntryPtr entry); +extern DMXConfigEntryPtr dmxConfigAddEntry(DMXConfigEntryPtr head, + DMXConfigType type, + DMXConfigCommentPtr comment, + DMXConfigVirtualPtr virtual); +extern DMXConfigEntryPtr dmxConfigEntryComment(DMXConfigCommentPtr comment); +extern DMXConfigEntryPtr dmxConfigEntryVirtual(DMXConfigVirtualPtr virtual); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpict.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * This file provides access to the externally visible RENDER support + * functions, global variables and macros for DMX. + * + * FIXME: Move function definitions for non-externally visible function + * to .c file. */ + +#ifndef DMXPICT_H +#define DMXPICT_H + +/** Picture private structure */ +typedef struct _dmxPictPriv { + Picture pict; /**< Picture ID from back-end server */ + Mask savedMask; /**< Mask of picture attributes saved for + * lazy window creation. */ +} dmxPictPrivRec, *dmxPictPrivPtr; + + +/** Glyph Set private structure */ +typedef struct _dmxGlyphPriv { + GlyphSet *glyphSets; /**< Glyph Set IDs from back-end server */ +} dmxGlyphPrivRec, *dmxGlyphPrivPtr; + + +extern void dmxInitRender(void); +extern void dmxResetRender(void); + +extern Bool dmxPictureInit(ScreenPtr pScreen, + PictFormatPtr formats, int nformats); + +extern void dmxCreatePictureList(WindowPtr pWindow); +extern Bool dmxDestroyPictureList(WindowPtr pWindow); + +extern int dmxCreatePicture(PicturePtr pPicture); +extern void dmxDestroyPicture(PicturePtr pPicture); +extern int dmxChangePictureClip(PicturePtr pPicture, int clipType, + pointer value, int n); +extern void dmxDestroyPictureClip(PicturePtr pPicture); +extern void dmxChangePicture(PicturePtr pPicture, Mask mask); +extern void dmxValidatePicture(PicturePtr pPicture, Mask mask); +extern void dmxComposite(CARD8 op, + PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst, + INT16 xSrc, INT16 ySrc, + INT16 xMask, INT16 yMask, + INT16 xDst, INT16 yDst, + CARD16 width, CARD16 height); +extern void dmxGlyphs(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int nlists, GlyphListPtr lists, GlyphPtr *glyphs); +extern void dmxCompositeRects(CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, xRectangle *rects); +extern Bool dmxInitIndexed(ScreenPtr pScreen, PictFormatPtr pFormat); +extern void dmxCloseIndexed(ScreenPtr pScreen, PictFormatPtr pFormat); +extern void dmxUpdateIndexed(ScreenPtr pScreen, PictFormatPtr pFormat, + int ndef, xColorItem *pdef); +extern void dmxTrapezoids(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int ntrap, xTrapezoid *traps); +extern void dmxTriangles(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int ntri, xTriangle *tris); +extern void dmxTriStrip(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int npoint, xPointFixed *points); +extern void dmxTriFan(CARD8 op, + PicturePtr pSrc, PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, INT16 ySrc, + int npoint, xPointFixed *points); + +extern Bool dmxBEFreeGlyphSet(ScreenPtr pScreen, GlyphSetPtr glyphSet); +extern Bool dmxBEFreePicture(PicturePtr pPicture); + +extern int dmxPictPrivateIndex; /**< Index for picture private data */ +extern int dmxGlyphSetPrivateIndex; /**< Index for glyphset private data */ + + +/** Get the picture private data given a picture pointer */ +#define DMX_GET_PICT_PRIV(_pPict) \ + (dmxPictPrivPtr)(_pPict)->devPrivates[dmxPictPrivateIndex].ptr + +/** Set the glyphset private data given a glyphset pointer */ +#define DMX_SET_GLYPH_PRIV(_pGlyph, _pPriv) \ + GlyphSetSetPrivate((_pGlyph), dmxGlyphSetPrivateIndex, (_pPriv)) +/** Get the glyphset private data given a glyphset pointer */ +#define DMX_GET_GLYPH_PRIV(_pGlyph) \ + (dmxGlyphPrivPtr)GlyphSetGetPrivate((_pGlyph), dmxGlyphSetPrivateIndex) + +#endif /* DMXPICT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpixmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpixmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxpixmap.h (revision 51223) @@ -0,0 +1,67 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for pixmap support. \see dmxpixmap.c */ + +#ifndef DMXPIXMAP_H +#define DMXPIXMAP_H + +#include "pixmapstr.h" + +/** Pixmap private area. */ +typedef struct _dmxPixPriv { + Pixmap pixmap; + XImage *detachedImage; +} dmxPixPrivRec, *dmxPixPrivPtr; + + +extern Bool dmxInitPixmap(ScreenPtr pScreen); + +extern PixmapPtr dmxCreatePixmap(ScreenPtr pScreen, + int width, int height, int depth); +extern Bool dmxDestroyPixmap(PixmapPtr pPixmap); +extern RegionPtr dmxBitmapToRegion(PixmapPtr pPixmap); + +extern void dmxBECreatePixmap(PixmapPtr pPixmap); +extern Bool dmxBEFreePixmap(PixmapPtr pPixmap); + +/** Private index. \see dmxpicmap.h \see dmxscrinit.c */ +extern int dmxPixPrivateIndex; + +/** Get pixmap private pointer. */ +#define DMX_GET_PIXMAP_PRIV(_pPix) \ + (dmxPixPrivPtr)(_pPix)->devPrivates[dmxPixPrivateIndex].ptr + +#endif /* DMXPIXMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprint.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to DMX configuration file pretty-printer. \see dmxprint.c */ + +#ifndef _DMXPRINT_H_ +#define _DMXPRINT_H_ + +void dmxConfigPrint(FILE *str, DMXConfigEntryPtr entry); +void dmxConfigVirtualPrint(FILE *str, DMXConfigVirtualPtr p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxprop.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2002,2003 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for property support. \see dmxprop.c */ + +#ifndef _DMXPROP_H_ +#define _DMXPROP_H_ +extern int dmxPropertyDisplay(DMXScreenInfo *dmxScreen); +extern void dmxPropertyWindow(DMXScreenInfo *dmxScreen); +extern void *dmxPropertyIterate(DMXScreenInfo *start, + void *(*f)(DMXScreenInfo *dmxScreen, + void *closure), + void *closure); +extern int dmxPropertySameDisplay(DMXScreenInfo *dmxScreen, const char *name); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxscrinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxscrinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxscrinit.h (revision 51223) @@ -0,0 +1,52 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * + */ + +/** \file + * Interface for screen initialization. \see dmxscrinit.c */ + +#ifndef DMXSCRINIT_H +#define DMXSCRINIT_H + +#include "scrnintstr.h" + +/** Private index. \see dmxscrrinit.c \see input/dmxconcole.c */ +extern int dmxScreenPrivateIndex; + +extern Bool dmxScreenInit(int idx, ScreenPtr pScreen, int argc, char *argv[]); + +extern void dmxBEScreenInit(int idx, ScreenPtr pScreen); +extern void dmxBECloseScreen(ScreenPtr pScreen); + +#endif /* DMXSCRINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxshadow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxshadow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxshadow.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * David H. Dawes + * + */ + +/** \file + * Interface for shadow framebuffer support. \see dmxshadow.c */ + +#ifndef DMXSHADOW_H +#define DMXSHADOW_H + +#include "shadow.h" +#include "scrnintstr.h" + +extern void dmxShadowUpdateProc(ScreenPtr pScreen, shadowBufPtr pBuf); + +#endif /* DMXSHADOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsigio.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsigio.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsigio.h (revision 51223) @@ -0,0 +1,46 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to SIGIO handling support. \see dmxsigio.c */ + +#ifndef _DMXSIGIO_H_ +#define _DMXSIGIO_H_ +extern void dmxSigioBlock(void); +extern void dmxSigioUnblock(void); +extern void dmxSigioEnableInput(void); +extern void dmxSigioDisableInput(void); +extern void dmxSigioRegister(DMXInputInfo *dmxInput, int fd); +extern void dmxSigioUnregister(DMXInputInfo *dmxInput); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxstat.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxstat.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxstat.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for statistic gathering interface. \see dmxstat.c */ + +#ifndef _DMXSTAT_H_ +#define _DMXSTAT_H_ + +#define DMX_STAT_LENGTH 10 /**< number of events for moving average */ +#define DMX_STAT_INTERVAL 1000 /**< msec between printouts */ +#define DMX_STAT_BINS 3 /**< number of bins */ +#define DMX_STAT_BIN0 10000 /**< us for bin[0] */ +#define DMX_STAT_BINMULT 100 /**< multiplier for next bin[] */ + +extern int dmxStatInterval; /**< Only for dmxstat.c and dmxsync.c */ +extern void dmxStatActivate(const char *interval, const char *displays); +extern DMXStatInfo *dmxStatAlloc(void); +extern void dmxStatFree(DMXStatInfo *); +extern void dmxStatInit(void); +extern void dmxStatSync(DMXScreenInfo *dmxScreen, + struct timeval *stop, struct timeval *start, + unsigned long pending); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsync.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsync.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxsync.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface for sync support. \see dmxsync.c */ + +#ifndef _DMXSYNC_H_ +#define _DMXSYNC_H_ + +extern void dmxSyncActivate(const char *interval); +extern void dmxSyncInit(void); +extern void dmxSync(DMXScreenInfo *dmxScreen, Bool now); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxvisual.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxvisual.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxvisual.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for visual support. \see dmxvisual.c */ + +#ifndef DMXVISUAL_H +#define DMXVISUAL_H + +#include "scrnintstr.h" + +extern Visual *dmxLookupVisual(ScreenPtr pScreen, VisualPtr pVisual); +extern Visual *dmxLookupVisualFromID(ScreenPtr pScreen, VisualID vid); +extern Colormap dmxColormapFromDefaultVisual(ScreenPtr pScreen, + Visual *visual); + +#endif /* DMXVISUAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxwindow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxwindow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dmxwindow.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XFree86$ */ +/* + * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +/** \file + * Interface for window support. \see dmxwindow.c */ + +#ifndef DMXWINDOW_H +#define DMXWINDOW_H + +#include "windowstr.h" + +/** Window private area. */ +typedef struct _dmxWinPriv { + Window window; + Bool offscreen; + Bool mapped; + Bool restacked; + unsigned long attribMask; + Colormap cmap; + Visual *visual; +#ifdef SHAPE + Bool isShaped; +#endif +#ifdef RENDER + Bool hasPict; +#endif +#ifdef GLXEXT + void *swapGroup; + int barrier; + void (*windowDestroyed)(WindowPtr); + void (*windowUnmapped)(WindowPtr); +#endif +} dmxWinPrivRec, *dmxWinPrivPtr; + + +extern Bool dmxInitWindow(ScreenPtr pScreen); + +extern Window dmxCreateRootWindow(WindowPtr pWindow); + +extern void dmxGetDefaultWindowAttributes(WindowPtr pWindow, + Colormap *cmap, + Visual **visual); +extern void dmxCreateAndRealizeWindow(WindowPtr pWindow, Bool doSync); + +extern Bool dmxCreateWindow(WindowPtr pWindow); +extern Bool dmxDestroyWindow(WindowPtr pWindow); +extern Bool dmxPositionWindow(WindowPtr pWindow, int x, int y); +extern Bool dmxChangeWindowAttributes(WindowPtr pWindow, unsigned long mask); +extern Bool dmxRealizeWindow(WindowPtr pWindow); +extern Bool dmxUnrealizeWindow(WindowPtr pWindow); +extern void dmxRestackWindow(WindowPtr pWindow, WindowPtr pOldNextSib); +extern void dmxWindowExposures(WindowPtr pWindow, RegionPtr prgn, + RegionPtr other_exposed); +extern void dmxPaintWindowBackground(WindowPtr pWindow, RegionPtr pRegion, + int what); +extern void dmxPaintWindowBorder(WindowPtr pWindow, RegionPtr pRegion, + int what); +extern void dmxCopyWindow(WindowPtr pWindow, DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +extern void dmxResizeWindow(WindowPtr pWindow, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); +extern void dmxReparentWindow(WindowPtr pWindow, WindowPtr pPriorParent); + +extern void dmxChangeBorderWidth(WindowPtr pWindow, unsigned int width); + +extern void dmxResizeScreenWindow(ScreenPtr pScreen, + int x, int y, int w, int h); +extern void dmxResizeRootWindow(WindowPtr pRoot, + int x, int y, int w, int h); + +extern Bool dmxBEDestroyWindow(WindowPtr pWindow); + +#ifdef SHAPE +/* Support for shape extension */ +extern void dmxSetShape(WindowPtr pWindow); +#endif + +/** Private index. \see dmxwindow.c \see dmxscrinit.c */ +extern int dmxWinPrivateIndex; + +/** Get window private pointer. */ +#define DMX_GET_WINDOW_PRIV(_pWin) \ + ((dmxWinPrivPtr)(_pWin)->devPrivates[dmxWinPrivateIndex].ptr) + +/* All of these macros are only used in dmxwindow.c */ +#define DMX_WINDOW_FUNC_PROLOGUE(_pGC) \ +do { \ + dmxGCPrivPtr pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_UNWRAP(funcs, pGCPriv, (_pGC)); \ + if (pGCPriv->ops) \ + DMX_UNWRAP(ops, pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_WINDOW_FUNC_EPILOGUE(_pGC) \ +do { \ + dmxGCPrivPtr pGCPriv = DMX_GET_GC_PRIV(_pGC); \ + DMX_WRAP(funcs, &dmxGCFuncs, pGCPriv, (_pGC)); \ + if (pGCPriv->ops) \ + DMX_WRAP(ops, &dmxGCOps, pGCPriv, (_pGC)); \ +} while (0) + +#define DMX_WINDOW_X1(_pWin) \ + ((_pWin)->drawable.x - wBorderWidth(_pWin)) +#define DMX_WINDOW_Y1(_pWin) \ + ((_pWin)->drawable.y - wBorderWidth(_pWin)) +#define DMX_WINDOW_X2(_pWin) \ + ((_pWin)->drawable.x + wBorderWidth(_pWin) + (_pWin)->drawable.width) +#define DMX_WINDOW_Y2(_pWin) \ + ((_pWin)->drawable.y + wBorderWidth(_pWin) + (_pWin)->drawable.height) + +#define DMX_WINDOW_OFFSCREEN(_pWin) \ + (DMX_WINDOW_X1(_pWin) >= (_pWin)->drawable.pScreen->width || \ + DMX_WINDOW_Y1(_pWin) >= (_pWin)->drawable.pScreen->height || \ + DMX_WINDOW_X2(_pWin) <= 0 || \ + DMX_WINDOW_Y2(_pWin) <= 0) + +#endif /* DMXWINDOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/do-not-use-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/do-not-use-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/do-not-use-config.h (revision 51223) @@ -0,0 +1,629 @@ +/* include/do-not-use-config.h. Generated by configure. */ +/* include/do-not-use-config.h.in. Generated from configure.ac by autoheader. */ + +/* Build AIGLX loader */ +#define AIGLX 1 + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Define to 1 if `struct sockaddr_in' has a `sin_len' member */ +/* #undef BSD44SOCKETS */ + +/* Builder address */ +#define BUILDERADDR "xorg@lists.freedesktop.org" + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/usr/local/lib/X11/fonts/misc/,/usr/local/lib/X11/fonts/TTF/,/usr/local/lib/X11/fonts/OTF,/usr/local/lib/X11/fonts/Type1/,/usr/local/lib/X11/fonts/CID/,/usr/local/lib/X11/fonts/100dpi/,/usr/local/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP + systems. This function is required for `alloca.c' support on those systems. + */ +/* #undef CRAY_STACKSEG_END */ + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* Simple debug messages */ +/* #undef CYGDEBUG */ + +/* Debug window manager */ +/* #undef CYGMULTIWINDOW_DEBUG */ + +/* Debug messages for window handling */ +/* #undef CYGWINDOWING_DEBUG */ + +/* Define to 1 if using `alloca.c'. */ +/* #undef C_ALLOCA */ + +/* Support Damage extension */ +#define DAMAGE 1 + +/* Support DBE extension */ +#define DBE 1 + +/* Use ddxBeforeReset */ +/* #undef DDXBEFORERESET */ + +/* Use OsVendorFatalError */ +/* #undef DDXOSFATALERROR */ + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Use OsVendorVErrorF */ +/* #undef DDXOSVERRORF */ + +/* Use GetTimeInMillis */ +/* #undef DDXTIME */ + +/* Default log location */ +#define DEFAULT_LOGPREFIX "/usr/local/var/log/Xorg." + +/* Default module search path */ +#define DEFAULT_MODULE_PATH "/usr/local/lib/xorg/modules" + +/* Support DGA extension */ +#define DGA 1 + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Use libdl-based loader */ +#define DLOPEN_SUPPORT 1 + +/* Support DPMS extension */ +#define DPMSExtension 1 + +/* Built-in output drivers (none) */ +#define DRIVERS {} + +/* Default DRI driver path */ +#define DRI_DRIVER_PATH "/usr/local/lib/dri" + +/* Build Extended-Visual-Information extension */ +#define EVI 1 + +/* Build FontCache extension */ +/* #undef FONTCACHE */ + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* System has /dev/xf86 aperture driver */ +/* #undef HAS_APERTURE_DRV */ + +/* Cygwin has /dev/windows for signaling new win32 messages */ +/* #undef HAS_DEVWINDOWS */ + +/* Have the `getdtablesize' function. */ +#define HAS_GETDTABLESIZE 1 + +/* Have the `getifaddrs' function. */ +#define HAS_GETIFADDRS 1 + +/* Have the `getpeereid' function. */ +/* #undef HAS_GETPEEREID */ + +/* Have the `getpeerucred' function. */ +/* #undef HAS_GETPEERUCRED */ + +/* Have the `mmap' function. */ +#define HAS_MMAP 1 + +/* Define to 1 if NetBSD built-in MTRR support is available */ +/* #undef HAS_MTRR_BUILTIN */ + +/* MTRR support available */ +#define HAS_MTRR_SUPPORT 1 + +/* Support SHM */ +#define HAS_SHM 1 + +/* Use Windows sockets */ +/* #undef HAS_WINSOCK */ + +/* Define to 1 if you have `alloca', as a function or macro. */ +#define HAVE_ALLOCA 1 + +/* Define to 1 if you have and it should be used (not on Ultrix). + */ +#define HAVE_ALLOCA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_MTRR_H 1 + +/* Define to 1 if you have the `authdes_create' function. */ +#define HAVE_AUTHDES_CREATE 1 + +/* Define to 1 if you have the `authdes_seccreate' function. */ +/* #undef HAVE_AUTHDES_SECCREATE */ + +/* Has backtrace support */ +#define HAVE_BACKTRACE 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +#define HAVE_DIRENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you don't have `vprintf' but do have `_doprnt.' */ +/* #undef HAVE_DOPRNT */ + +/* Define to 1 if you have the header file. */ +#define HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `geteuid' function. */ +#define HAVE_GETEUID 1 + +/* Define to 1 if you have the `getopt' function. */ +#define HAVE_GETOPT 1 + +/* Define to 1 if you have the `getopt_long' function. */ +#define HAVE_GETOPT_LONG 1 + +/* Define to 1 if you have the `getuid' function. */ +#define HAVE_GETUID 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `m' library (-lm). */ +#define HAVE_LIBM 1 + +/* Define to 1 if you have the `link' function. */ +#define HAVE_LINK 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_AGPGART_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APM_BIOS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_FB_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_MACHINE_MTRR_H */ + +/* Define to 1 if you have the `memmove' function. */ +#define HAVE_MEMMOVE 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have the `memset' function. */ +#define HAVE_MEMSET 1 + +/* Define to 1 if you have the `mkstemp' function. */ +#define HAVE_MKSTEMP 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_NDBM_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. */ +/* #undef HAVE_NDIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_RPCSVC_DBM_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SDL_SDL_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the `strchr' function. */ +#define HAVE_STRCHR 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the `strrchr' function. */ +#define HAVE_STRRCHR 1 + +/* Define to 1 if you have the `strtol' function. */ +#define HAVE_STRTOL 1 + +/* Define to 1 if SYSV IPC is available */ +#define HAVE_SYSV_IPC 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_AGPIO_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_DIR_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_IO_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_LINKER_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_MEMRANGE_H */ + +/* Define to 1 if you have the header file, and it defines `DIR'. + */ +/* #undef HAVE_SYS_NDIR_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_SYS_VM86_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to 1 if you have the `vprintf' function. */ +#define HAVE_VPRINTF 1 + +/* Define to 1 if you have the `vsnprintf' function. */ +#define HAVE_VSNPRINTF 1 + +/* Define to 1 if you have the `walkcontext' function. */ +/* #undef HAVE_WALKCONTEXT */ + +/* Built-in input drivers (none) */ +#define IDRIVERS {} + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Build kdrive ddx */ +/* #undef KDRIVEDDXACTIONS */ + +/* Build fbdev-based kdrive server */ +/* #undef KDRIVEFBDEV */ + +/* Build Kdrive X server */ +/* #undef KDRIVESERVER */ + +/* Build VESA-based kdrive servers */ +/* #undef KDRIVEVESA */ + +/* Support LBX extension */ +/* #undef LBX */ + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM extension */ +#define MITSHM 1 + +/* Build Multibuffer extension */ +/* #undef MULTIBUFFER */ + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Do not have `strcasecmp'. */ +/* #undef NEED_STRCASECMP */ + +/* Need XFree86 helper functions */ +#define NEED_XF86_PROTOTYPES 1 + +/* Need XFree86 typedefs */ +#define NEED_XF86_TYPES 1 + +/* Define to 1 if modules should avoid the libcwrapper */ +#define NO_LIBCWRAPPER 1 + +/* Operating System Name */ +#define OSNAME "Linux 2.6.16-1.2122_FC6smp i686" + +/* Operating System Vendor */ +#define OSVENDOR "" + +/* Name of package */ +#define PACKAGE "xorg-server" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "https://bugs.freedesktop.org/enter_bug.cgi?product=xorg" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "xorg-server" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "xorg-server 1.1.0" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "xorg-server" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "1.1.0" + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PC console */ +/* #undef PCVT_SUPPORT */ + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Overall prefix */ +#define PROJECTROOT "/usr/local" + +/* Support RANDR extension */ +#define RANDR 1 + +/* Make PROJECT_ROOT relative to the xserver location */ +/* #undef RELOCATE_PROJECTROOT */ + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Define as the return type of signal handlers (`int' or `void'). */ +/* #undef RETSIGTYPE */ + +/* Default RGB path */ +#define RGB_DB "/usr/local/share/X11/rgb" + +/* Build Rootless code */ +/* #undef ROOTLESS */ + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Support Secure RPC ("SUN-DES-1") authentication for X11 clients */ +#define SECURE_RPC 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* The size of a `unsigned long', as computed by sizeof. */ +#define SIZEOF_UNSIGNED_LONG 4 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ +/* #undef STACK_DIRECTION */ + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Build TOG-CUP extension */ +#define TOGCUP 1 + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* NetBSD PIO alpha IO */ +/* #undef USE_ALPHA_PIO */ + +/* BSD AMD64 iopl */ +/* #undef USE_AMD64_IOPL */ + +/* BSD /dev/io */ +/* #undef USE_DEV_IO */ + +/* BSD i386 iopl */ +/* #undef USE_I386_IOPL */ + +/* Use built-in RGB color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* Version number of package */ +#define VERSION "1.1.0" + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +/* Build APPGROUP extension */ +#define XAPPGROUP 1 + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Build Security extension */ +#define XCSECURITY 1 + +/* Support XDM Control Protocol */ +#define XDMCP 1 + +/* Build XEvIE extension */ +#define XEVIE 1 + +/* Support XF86 Big font extension */ +#define XF86BIGFONT 1 + +/* Name of configuration file */ +#define XF86CONFIGFILE "xorg.conf" + +/* Build DRI extension */ +#define XF86DRI 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Support XFixes extension */ +#define XFIXES 1 + +/* Building XFree86 server */ +#define XFree86Server 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Use loadable XGL modules */ +/* #undef XGL_MODULAR */ + +/* Default XGL module search path */ +/* #undef XGL_MODULE_PATH */ + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Path to XKB data */ +#define XKB_BASE_DIRECTORY "/usr/local/share/X11/xkb" + +/* Path to XKB bin dir */ +#define XKB_BIN_DIRECTORY "/usr/local/bin" + +/* Disable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Path to XKB output dir */ +#define XKM_OUTPUT_DIR "/usr/local/share/X11/xkb/compiled/" + +/* Building Xorg server */ +#define XORGSERVER 1 + +/* Vendor release */ +#define XORG_DATE "22 May 2006" + +/* Vendor man version */ +#define XORG_MAN_VERSION "Version 7.1" + +/* Vendor release */ +#define XORG_RELEASE "Release 7.1" + +/* Building Xorg server */ +#define XORG_SERVER 1 + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((1) * 100000) + ((0) * 1000) + 0) + +/* Build Print extension */ +#define XPRINT 1 + +/* Support FreeType rasterizer in Xprint for nearly all font file formats */ +/* #undef XP_USE_FREETYPE */ + +/* Support Record extension */ +#define XRECORD 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Build Xsdl server */ +/* #undef XSDLSERVER */ + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv extension */ +#define XV 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Short vendor name */ +#define XVENDORNAMESHORT "X.Org" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* Build Xv extension */ +#define XvExtension 1 + +/* Build XvMC extension */ +#define XvMCExtension 1 + +/* Define to 1 if `lex' declares `yytext' as a `char *' by default, not a + `char[]'. */ +#define YYTEXT_POINTER 1 + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 + +/* Define to 1 if unsigned long is 64 bits. */ +/* #undef _XSERVER64 */ + +/* Solaris 8 or later */ +/* #undef __SOL8__ */ + +/* Vendor web address for support */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Name of configuration file */ +#define __XCONFIGFILE__ "xorg.conf" + +/* Default XKB rules */ +#define __XKBDEFRULES__ "xorg" + +/* Name of X server */ +#define __XSERVERNAME__ "Xorg" + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ + +/* Define to `int' if does not define. */ +/* #undef pid_t */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dpmsproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dpmsproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dpmsproc.h (revision 51223) @@ -0,0 +1,16 @@ +/* $XFree86: xc/programs/Xserver/Xext/dpmsproc.h,v 1.3 2001/10/28 03:32:50 tsi Exp $ */ + +/* Prototypes for functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _DPMSPROC_H_ +#define _DPMSPROC_H_ + +void DPMSSet(int level); +int DPMSGet(int *plevel); +Bool DPMSSupported(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dri.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dri.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dri.h (revision 51223) @@ -0,0 +1,129 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/dri.h,v 1.18 2001/03/21 16:21:40 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright (c) 2002 Apple Computer, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Jens Owen + * + */ + +/* Prototypes for AppleDRI functions */ + +#ifndef _DRI_H_ +#define _DRI_H_ + +#include +#include "scrnintstr.h" +#define _APPLEDRI_SERVER_ +#include "appledri.h" +#include "Xplugin.h" + +typedef void (*ClipNotifyPtr)( WindowPtr, int, int ); + + +/* + * These functions can be wrapped by the DRI. Each of these have + * generic default funcs (initialized in DRICreateInfoRec) and can be + * overridden by the driver in its [driver]DRIScreenInit function. + */ +typedef struct { + WindowExposuresProcPtr WindowExposures; + CopyWindowProcPtr CopyWindow; + ValidateTreeProcPtr ValidateTree; + PostValidateTreeProcPtr PostValidateTree; + ClipNotifyProcPtr ClipNotify; +} DRIWrappedFuncsRec, *DRIWrappedFuncsPtr; + +typedef struct { + xp_surface_id id; + int kind; +} DRISurfaceNotifyArg; + +extern Bool DRIScreenInit(ScreenPtr pScreen); + +extern Bool DRIFinishScreenInit(ScreenPtr pScreen); + +extern void DRICloseScreen(ScreenPtr pScreen); + +extern Bool DRIExtensionInit(void); + +extern void DRIReset(void); + +extern Bool DRIQueryDirectRenderingCapable(ScreenPtr pScreen, + Bool *isCapable); + +extern Bool DRIAuthConnection(ScreenPtr pScreen, unsigned int magic); + +extern Bool DRICreateSurface(ScreenPtr pScreen, + Drawable id, + DrawablePtr pDrawable, + xp_client_id client_id, + xp_surface_id *surface_id, + unsigned int key[2], + void (*notify) (void *arg, void *data), + void *notify_data); + +extern Bool DRIDestroySurface(ScreenPtr pScreen, + Drawable id, + DrawablePtr pDrawable, + void (*notify) (void *arg, void *data), + void *notify_data); + +extern Bool DRIDrawablePrivDelete(pointer pResource, + XID id); + +extern DRIWrappedFuncsRec *DRIGetWrappedFuncs(ScreenPtr pScreen); + +extern void DRICopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +extern int DRIValidateTree(WindowPtr pParent, + WindowPtr pChild, + VTKind kind); + +extern void DRIPostValidateTree(WindowPtr pParent, + WindowPtr pChild, + VTKind kind); + +extern void DRIClipNotify(WindowPtr pWin, + int dx, + int dy); + +extern void DRIWindowExposures(WindowPtr pWin, + RegionPtr prgn, + RegionPtr bsreg); + +extern void DRISurfaceNotify (xp_surface_id id, int kind); + +extern void DRIQueryVersion(int *majorVersion, + int *minorVersion, + int *patchVersion); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dristruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dristruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dristruct.h (revision 51223) @@ -0,0 +1,82 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/dristruct.h,v 1.10 2001/03/21 16:21:40 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright (c) 2002 Apple Computer, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Jens Owen + * + */ + +#ifndef DRI_STRUCT_H +#define DRI_STRUCT_H + +#include "dri.h" +#include "x-list.h" + +#define DRI_MAX_DRAWABLES 256 + +#define DRI_DRAWABLE_PRIV_FROM_WINDOW(pWin) \ + ((DRIWindowPrivIndex < 0) ? \ + NULL : \ + ((DRIDrawablePrivPtr)((pWin)->devPrivates[DRIWindowPrivIndex].ptr))) + +#define DRI_DRAWABLE_PRIV_FROM_PIXMAP(pPix) \ + ((DRIPixmapPrivIndex < 0) ? \ + NULL : \ + ((DRIDrawablePrivPtr)((pPix)->devPrivates[DRIPixmapPrivIndex].ptr))) + +typedef struct _DRIDrawablePrivRec +{ + xp_surface_id sid; + int drawableIndex; + DrawablePtr pDraw; + ScreenPtr pScreen; + int refCount; + unsigned int key[2]; + x_list *notifiers; /* list of (FUN . DATA) */ +} DRIDrawablePrivRec, *DRIDrawablePrivPtr; + +#define DRI_SCREEN_PRIV(pScreen) \ + ((DRIScreenPrivIndex < 0) ? \ + NULL : \ + ((DRIScreenPrivPtr)((pScreen)->devPrivates[DRIScreenPrivIndex].ptr))) + +#define DRI_SCREEN_PRIV_FROM_INDEX(screenIndex) ((DRIScreenPrivPtr) \ + (screenInfo.screens[screenIndex]->devPrivates[DRIScreenPrivIndex].ptr)) + + +typedef struct _DRIScreenPrivRec +{ + Bool directRenderingSupport; + int nrWindows; + DRIWrappedFuncsRec wrap; + DrawablePtr DRIDrawables[DRI_MAX_DRAWABLES]; +} DRIScreenPrivRec, *DRIScreenPrivPtr; + +#endif /* DRI_STRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dummylib.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dummylib.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/dummylib.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/dummylib/dummylib.h,v 1.1 2000/02/13 03:06:38 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _DUMMY_LIB_H +#define _DUMMY_LIB_H + +#endif /* _DUMMY_LIB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/e8870PCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/e8870PCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/e8870PCI.h (revision 51223) @@ -0,0 +1,42 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/e8870PCI.h,v 1.1 2003/02/23 20:26:49 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_E8870_H +#define PCI_E8870_H 1 + +#include +#include + +Bool xorgProbeE8870(scanpciWrapperOpt flags); +void xf86PreScanE8870(void); +void xf86PostScanE8870(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/edid.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/edid.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/edid.h (revision 51223) @@ -0,0 +1,464 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/edid.h,v 1.6 2000/04/17 16:29:55 eich Exp $ */ + +/* edid.h: defines to parse an EDID block + * + * This file contains all information to interpret a standard EDIC block + * transmitted by a display device via DDC (Display Data Channel). So far + * there is no information to deal with optional EDID blocks. + * DDC is a Trademark of VESA (Video Electronics Standard Association). + * + * Copyright 1998 by Egbert Eich + */ + +#ifndef _EDID_H_ +#define _EDID_H_ + +#include "vdif.h" + +/* read complete EDID record */ +#define EDID1_LEN 128 +#define BITS_PER_BYTE 9 +#define NUM BITS_PER_BYTE*EDID1_LEN +#define HEADER 6 + +#define STD_TIMINGS 8 +#define DET_TIMINGS 4 + +#ifdef _PARSE_EDID_ + +/* header: 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 */ +#define HEADER_SECTION 0 +#define HEADER_LENGTH 8 + +/* vendor section */ +#define VENDOR_SECTION (HEADER_SECTION + HEADER_LENGTH) +#define V_MANUFACTURER 0 +#define V_PROD_ID (V_MANUFACTURER + 2) +#define V_SERIAL (V_PROD_ID + 2) +#define V_WEEK (V_SERIAL + 4) +#define V_YEAR (V_WEEK + 1) +#define VENDOR_LENGTH (V_YEAR + 1) + +/* EDID version */ +#define VERSION_SECTION (VENDOR_SECTION + VENDOR_LENGTH) +#define V_VERSION 0 +#define V_REVISION (V_VERSION + 1) +#define VERSION_LENGTH (V_REVISION + 1) + +/* display information */ +#define DISPLAY_SECTION (VERSION_SECTION + VERSION_LENGTH) +#define D_INPUT 0 +#define D_HSIZE (D_INPUT + 1) +#define D_VSIZE (D_HSIZE + 1) +#define D_GAMMA (D_VSIZE + 1) +#define FEAT_S (D_GAMMA + 1) +#define D_RG_LOW (FEAT_S + 1) +#define D_BW_LOW (D_RG_LOW + 1) +#define D_REDX (D_BW_LOW + 1) +#define D_REDY (D_REDX + 1) +#define D_GREENX (D_REDY + 1) +#define D_GREENY (D_GREENX + 1) +#define D_BLUEX (D_GREENY + 1) +#define D_BLUEY (D_BLUEX + 1) +#define D_WHITEX (D_BLUEY + 1) +#define D_WHITEY (D_WHITEX + 1) +#define DISPLAY_LENGTH (D_WHITEY + 1) + +/* supported VESA and other standard timings */ +#define ESTABLISHED_TIMING_SECTION (DISPLAY_SECTION + DISPLAY_LENGTH) +#define E_T1 0 +#define E_T2 (E_T1 + 1) +#define E_TMANU (E_T2 + 1) +#define E_TIMING_LENGTH (E_TMANU + 1) + +/* non predefined standard timings supported by display */ +#define STD_TIMING_SECTION (ESTABLISHED_TIMING_SECTION + E_TIMING_LENGTH) +#define STD_TIMING_INFO_LEN 2 +#define STD_TIMING_INFO_NUM STD_TIMINGS +#define STD_TIMING_LENGTH (STD_TIMING_INFO_LEN * STD_TIMING_INFO_NUM) + +/* detailed timing info of non standard timings */ +#define DET_TIMING_SECTION (STD_TIMING_SECTION + STD_TIMING_LENGTH) +#define DET_TIMING_INFO_LEN 18 +#define MONITOR_DESC_LEN DET_TIMING_INFO_LEN +#define DET_TIMING_INFO_NUM DET_TIMINGS +#define DET_TIMING_LENGTH (DET_TIMING_INFO_LEN * DET_TIMING_INFO_NUM) + +/* number of EDID sections to follow */ +#define NO_EDID (DET_TIMING_SECTION + DET_TIMING_LENGTH) +/* one byte checksum */ +#define CHECKSUM (NO_EDID + 1) + +#if (CHECKSUM != (EDID1_LEN - 1)) +# error "EDID1 length != 128!" +#endif + + +#define SECTION(x,y) (Uchar *)(x + y) +#define GET_ARRAY(y) ((Uchar *)(c + y)) +#define GET(y) *(Uchar *)(c + y) + +/* extract information from vendor section */ +#define _PROD_ID(x) x[0] + (x[1] << 8); +#define PROD_ID _PROD_ID(GET_ARRAY(V_PROD_ID)) +#define _SERIAL_NO(x) x[0] + (x[1] << 8) + (x[2] << 16) + (x[3] << 24) +#define SERIAL_NO _SERIAL_NO(GET_ARRAY(V_SERIAL)) +#define _YEAR(x) (x & 0xFF) + 1990 +#define YEAR _YEAR(GET(V_YEAR)) +#define WEEK GET(V_WEEK) & 0xFF +#define _L1(x) ((x[0] & 0x7C) >> 2) + '@' +#define _L2(x) ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@' +#define _L3(x) (x[1] & 0x1F) + '@'; +#define L1 _L1(GET_ARRAY(V_MANUFACTURER)) +#define L2 _L2(GET_ARRAY(V_MANUFACTURER)) +#define L3 _L3(GET_ARRAY(V_MANUFACTURER)) + +/* extract information from version section */ +#define VERSION GET(V_VERSION) +#define REVISION GET(V_REVISION) + +/* extract information from display section */ +#define _INPUT_TYPE(x) ((x & 0x80) >> 7) +#define INPUT_TYPE _INPUT_TYPE(GET(D_INPUT)) +#define _INPUT_VOLTAGE(x) ((x & 0x60) >> 5) +#define INPUT_VOLTAGE _INPUT_VOLTAGE(GET(D_INPUT)) +#define _SETUP(x) ((x & 0x10) >> 4) +#define SETUP _SETUP(GET(D_INPUT)) +#define _SYNC(x) (x & 0x0F) +#define SYNC _SYNC(GET(D_INPUT)) +#define _DFP(x) (x & 0x01) +#define DFP _DFP(GET(D_INPUT)) +#define _GAMMA(x) (x == 0xff ? 1.0 : ((x + 100.0)/100.0)) +#define GAMMA _GAMMA(GET(D_GAMMA)) +#define HSIZE_MAX GET(D_HSIZE) +#define VSIZE_MAX GET(D_VSIZE) +#define _DPMS(x) ((x & 0xE0) >> 5) +#define DPMS _DPMS(GET(FEAT_S)) +#define _DISPLAY_TYPE(x) ((x & 0x18) >> 3) +#define DISPLAY_TYPE _DISPLAY_TYPE(GET(FEAT_S)) +#define _MSC(x) (x & 0x7) +#define MSC _MSC(GET(FEAT_S)) + + +/* color characteristics */ +#define CC_L(x,y) ((x & (0x03 << y)) >> y) +#define CC_H(x) (x << 2) +#define I_CC(x,y,z) CC_H(y) | CC_L(x,z) +#define F_CC(x) ((x)/1024.0) +#define REDX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDX)),6)) +#define REDY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDY)),4)) +#define GREENX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENX)),2)) +#define GREENY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENY)),0)) +#define BLUEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEX)),6)) +#define BLUEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEY)),4)) +#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2)) +#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0)) + +/* extract information from standard timing section */ +#define T1 GET(E_T1) +#define T2 GET(E_T2) +#define T_MANU GET(E_TMANU) + +/* extract information from estabished timing section */ +#define _VALID_TIMING(x) !(((x[0] == 0x01) && (x[1] == 0x01)) \ + || ((x[0] == 0x00) && (x[1] == 0x00)) \ + || ((x[0] == 0x20) && (x[1] == 0x20)) ) +#define VALID_TIMING _VALID_TIMING(c) +#define _HSIZE1(x) ((x[0] + 31) * 8) +#define HSIZE1 _HSIZE1(c) +#define RATIO(x) ((x[1] & 0xC0) >> 6) +#define RATIO1_1 0 +/* EDID Ver. 1.3 redefined this */ +#define RATIO16_10 RATIO1_1 +#define RATIO4_3 1 +#define RATIO5_4 2 +#define RATIO16_9 3 +#define _VSIZE1(x,y,r) switch(RATIO(x)){ \ + case RATIO1_1: y = ((v->version > 1 || v->revision > 2) \ + ? (_HSIZE1(x) * 10) / 16 : _HSIZE1(x)); break; \ + case RATIO4_3: y = _HSIZE1(x) * 3 / 4; break; \ + case RATIO5_4: y = _HSIZE1(x) * 4 / 5; break; \ + case RATIO16_9: y = _HSIZE1(x) * 9 / 16; break; \ + } +#define VSIZE1(x) _VSIZE1(c,x,v) +#define _REFRESH_R(x) (x[1] & 0x3F) + 60 +#define REFRESH_R _REFRESH_R(c) +#define _ID_LOW(x) x[0] +#define ID_LOW _ID_LOW(c) +#define _ID_HIGH(x) (x[1] << 8) +#define ID_HIGH _ID_HIGH(c) +#define STD_TIMING_ID (ID_LOW | ID_HIGH) +#define _NEXT_STD_TIMING(x) (x = (x + STD_TIMING_INFO_LEN)) +#define NEXT_STD_TIMING _NEXT_STD_TIMING(c) + + +/* EDID Ver. >= 1.2 */ +#define _IS_MONITOR_DESC(x) (x[0] == 0 && x[1] == 0 && x[2] == 0 && x[4] == 0) +#define IS_MONITOR_DESC _IS_MONITOR_DESC(c) +#define _PIXEL_CLOCK(x) (x[0] + (x[1] << 8)) * 10000 +#define PIXEL_CLOCK _PIXEL_CLOCK(c) +#define _H_ACTIVE(x) (x[2] + ((x[4] & 0xF0) << 4)) +#define H_ACTIVE _H_ACTIVE(c) +#define _H_BLANK(x) (x[3] + ((x[4] & 0x0F) << 8)) +#define H_BLANK _H_BLANK(c) +#define _V_ACTIVE(x) (x[5] + ((x[7] & 0xF0) << 4)) +#define V_ACTIVE _V_ACTIVE(c) +#define _V_BLANK(x) (x[6] + ((x[7] & 0x0F) << 8)) +#define V_BLANK _V_BLANK(c) +#define _H_SYNC_OFF(x) (x[8] + ((x[11] & 0xC0) << 2)) +#define H_SYNC_OFF _H_SYNC_OFF(c) +#define _H_SYNC_WIDTH(x) (x[9] + ((x[11] & 0x30) << 4)) +#define H_SYNC_WIDTH _H_SYNC_WIDTH(c) +#define _V_SYNC_OFF(x) ((x[10] >> 4) + ((x[11] & 0x0C) << 2)) +#define V_SYNC_OFF _V_SYNC_OFF(c) +#define _V_SYNC_WIDTH(x) ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)) +#define V_SYNC_WIDTH _V_SYNC_WIDTH(c) +#define _H_SIZE(x) (x[12] + ((x[14] & 0xF0) << 4)) +#define H_SIZE _H_SIZE(c) +#define _V_SIZE(x) (x[13] + ((x[14] & 0x0F) << 8)) +#define V_SIZE _V_SIZE(c) +#define _H_BORDER(x) (x[15]) +#define H_BORDER _H_BORDER(c) +#define _V_BORDER(x) (x[16]) +#define V_BORDER _V_BORDER(c) +#define _INTERLACED(x) ((x[17] & 0x80) >> 7) +#define INTERLACED _INTERLACED(c) +#define _STEREO(x) ((x[17] & 0x60) >> 5) +#define STEREO _STEREO(c) +#define _STEREO1(x) (x[17] & 0x1) +#define STEREO1 _STEREO(c) +#define _SYNC_T(x) ((x[17] & 0x18) >> 3) +#define SYNC_T _SYNC_T(c) +#define _MISC(x) ((x[17] & 0x06) >> 1) +#define MISC _MISC(c) + +#define _MONITOR_DESC_TYPE(x) x[3] +#define MONITOR_DESC_TYPE _MONITOR_DESC_TYPE(c) +#define SERIAL_NUMBER 0xFF +#define ASCII_STR 0xFE +#define MONITOR_RANGES 0xFD +#define _MIN_V(x) x[5] +#define MIN_V _MIN_V(c) +#define _MAX_V(x) x[6] +#define MAX_V _MAX_V(c) +#define _MIN_H(x) x[7] +#define MIN_H _MIN_H(c) +#define _MAX_H(x) x[8] +#define MAX_H _MAX_H(c) +#define _MAX_CLOCK(x) x[9] +#define MAX_CLOCK _MAX_CLOCK(c) +#define _HAVE_2ND_GTF(x) (x[10] == 0x02) +#define HAVE_2ND_GTF _HAVE_2ND_GTF(c) +#define _F_2ND_GTF(x) (x[12] * 2) +#define F_2ND_GTF _F_2ND_GTF(c) +#define _C_2ND_GTF(x) (x[13] / 2) +#define C_2ND_GTF _C_2ND_GTF(c) +#define _M_2ND_GTF(x) (x[14] + (x[15] << 8)) +#define M_2ND_GTF _M_2ND_GTF(c) +#define _K_2ND_GTF(x) (x[16]) +#define K_2ND_GTF _K_2ND_GTF(c) +#define _J_2ND_GTF(x) (x[17] / 2) +#define J_2ND_GTF _J_2ND_GTF(c) +#define MONITOR_NAME 0xFC +#define ADD_COLOR_POINT 0xFB +#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2)) +#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0)) +#define _WHITEX_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 1)),2)) +#define _WHITEY_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 2)),0)) +#define _WHITE_INDEX1(x) x[5] +#define WHITE_INDEX1 _WHITE_INDEX1(c) +#define _WHITE_INDEX2(x) x[10] +#define WHITE_INDEX2 _WHITE_INDEX2(c) +#define WHITEX1 _WHITEX_ADD(c,6) +#define WHITEY1 _WHITEY_ADD(c,6) +#define WHITEX2 _WHITEX_ADD(c,12) +#define WHITEY2 _WHITEY_ADD(c,12) +#define _WHITE_GAMMA1(x) _GAMMA(x[9]) +#define WHITE_GAMMA1 _WHITE_GAMMA1(c) +#define _WHITE_GAMMA2(x) _GAMMA(x[14]) +#define WHITE_GAMMA2 _WHITE_GAMMA2(c) +#define ADD_STD_TIMINGS 0xFA +#define ADD_DUMMY 0x10 + +#define _NEXT_DT_MD_SECTION(x) (x = (x + DET_TIMING_INFO_LEN)) +#define NEXT_DT_MD_SECTION _NEXT_DT_MD_SECTION(c) + +#endif /* _PARSE_EDID_ */ + +/* input type */ +#define DIGITAL(x) x + +/* DFP */ +#define DFP1(x) x + +/* input voltage level */ +#define V070 0 /* 0.700V/0.300V */ +#define V071 1 /* 0.714V/0.286V */ +#define V100 2 /* 1.000V/0.400V */ +#define V007 3 /* 0.700V/0.000V */ + +/* Signal level setup */ +#define SIG_SETUP(x) (x) + +/* sync characteristics */ +#define SEP_SYNC(x) (x & 0x08) +#define COMP_SYNC(x) (x & 0x04) +#define SYNC_O_GREEN(x) (x & 0x02) +#define SYNC_SERR(x) (x & 0x01) + +/* DPMS features */ +#define DPMS_STANDBY(x) (x & 0x04) +#define DPMS_SUSPEND(x) (x & 0x02) +#define DPMS_OFF(x) (x & 0x01) + +/* display type */ +#define DISP_MONO 0 +#define DISP_RGB 1 +#define DISP_MULTCOLOR 2 + +/* Msc stuff EDID Ver > 1.1 */ +#define STD_COLOR_SPACE(x) (x & 0x4) +#define PREFERRED_TIMING_MODE(x) (x & 0x2) +#define GFT_SUPPORTED(x) (x & 0x1) + +/* detailed timing misc */ +#define IS_INTERLACED(x) (x) +#define IS_STEREO(x) (x) +#define IS_RIGHT_STEREO(x) (x & 0x01) +#define IS_LEFT_STEREO(x) (x & 0x02) +#define IS_4WAY_STEREO(x) (x & 0x03) +#define IS_RIGHT_ON_SYNC(x) IS_RIGHT_STEREO(x) +#define IS_LEFT_ON_SYNC(x) IS_LEFT_STEREO(x) + + +typedef unsigned int Uint; +typedef unsigned char Uchar; + +struct vendor { + char name[4]; + int prod_id; + Uint serial; + int week; + int year; +}; + +struct edid_version { + int version; + int revision; +}; + +struct disp_features { + unsigned int input_type:1; + unsigned int input_voltage:2; + unsigned int input_setup:1; + unsigned int input_sync:5; + unsigned int input_dfp:1; + int hsize; + int vsize; + float gamma; + unsigned int dpms:3; + unsigned int display_type:2; + unsigned int msc:3; + float redx; + float redy; + float greenx; + float greeny; + float bluex; + float bluey; + float whitex; + float whitey; +}; + +struct established_timings { + Uchar t1; + Uchar t2; + Uchar t_manu; +}; + +struct std_timings { + int hsize; + int vsize; + int refresh; + CARD16 id; +}; + +struct detailed_timings { + int clock; + int h_active; + int h_blanking; + int v_active; + int v_blanking; + int h_sync_off; + int h_sync_width; + int v_sync_off; + int v_sync_width; + int h_size; + int v_size; + int h_border; + int v_border; + unsigned int interlaced:1; + unsigned int stereo:2; + unsigned int sync:2; + unsigned int misc:2; + unsigned int stereo_1:1; +}; + +#define DT 0 +#define DS_SERIAL 0xFF +#define DS_ASCII_STR 0xFE +#define DS_NAME 0xFC +#define DS_RANGES 0xFD +#define DS_WHITE_P 0xFB +#define DS_STD_TIMINGS 0xFA +#define DS_DUMMY 0x10 +#define DS_UNKOWN 0x100 /* type is an int */ + +struct monitor_ranges { + int min_v; + int max_v; + int min_h; + int max_h; + int max_clock; + int gtf_2nd_f; + int gtf_2nd_c; + int gtf_2nd_m; + int gtf_2nd_k; + int gtf_2nd_j; +}; + +struct whitePoints{ + int index; + float white_x; + float white_y; + float white_gamma; +}; + +struct detailed_monitor_section { + int type; + union { + struct detailed_timings d_timings; + Uchar serial[13]; + Uchar ascii_data[13]; + Uchar name[13]; + struct monitor_ranges ranges; + struct std_timings std_t[5]; + struct whitePoints wp[2]; + } section; +}; + +typedef struct { + int scrnIndex; + struct vendor vendor; + struct edid_version ver; + struct disp_features features; + struct established_timings timings1; + struct std_timings timings2[8]; + struct detailed_monitor_section det_mon[4]; + xf86vdifPtr vdif; + int no_sections; + Uchar *rawData; +} xf86Monitor, *xf86MonPtr; + +extern xf86MonPtr ConfiguredMonitor; + +#endif /* _EDID_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elf.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elf.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elf.h (revision 51223) @@ -0,0 +1,712 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/elf.h,v 1.16 2003/06/12 14:12:34 eich Exp $ */ + +typedef unsigned int Elf32_Addr; +typedef unsigned short Elf32_Half; +typedef unsigned int Elf32_Off; +typedef long Elf32_Sword; +typedef unsigned int Elf32_Word; + +typedef unsigned long Elf64_Addr; +typedef unsigned short Elf64_Half; +typedef unsigned long Elf64_Off; +typedef int Elf64_Sword; +typedef unsigned int Elf64_Word; +typedef unsigned long Elf64_Xword; +typedef long Elf64_Sxword; + +/* These constants are for the segment types stored in the image headers */ +#define PT_NULL 0 +#define PT_LOAD 1 +#define PT_DYNAMIC 2 +#define PT_INTERP 3 +#define PT_NOTE 4 +#define PT_SHLIB 5 +#define PT_PHDR 6 +#define PT_LOPROC 0x70000000 +#define PT_HIPROC 0x7fffffff + +/* These constants define the different elf file types */ +#define ET_NONE 0 +#define ET_REL 1 +#define ET_EXEC 2 +#define ET_DYN 3 +#define ET_CORE 4 +#define ET_LOPROC 5 +#define ET_HIPROC 6 + +/* These constants define the various ELF target machines */ +#define EM_NONE 0 +#define EM_M32 1 +#define EM_SPARC 2 +#define EM_386 3 +#define EM_68K 4 +#define EM_88K 5 +#define EM_486 6 /* Perhaps disused */ +#define EM_860 7 +#define EM_MIPS 8 +#define EM_MIPS_RS4_BE 10 +#define EM_PARISC 15 +#define EM_SPARC32PLUS 18 +#define EM_PPC 20 +#define EM_SPARCV9 43 +#define EM_IA_64 50 +#define EM_ALPHA 0x9026 + +/* This is the info that is needed to parse the dynamic section of the file */ +#define DT_NULL 0 +#define DT_NEEDED 1 +#define DT_PLTRELSZ 2 +#define DT_PLTGOT 3 +#define DT_HASH 4 +#define DT_STRTAB 5 +#define DT_SYMTAB 6 +#define DT_RELA 7 +#define DT_RELASZ 8 +#define DT_RELAENT 9 +#define DT_STRSZ 10 +#define DT_SYMENT 11 +#define DT_INIT 12 +#define DT_FINI 13 +#define DT_SONAME 14 +#define DT_RPATH 15 +#define DT_SYMBOLIC 16 +#define DT_REL 17 +#define DT_RELSZ 18 +#define DT_RELENT 19 +#define DT_PLTREL 20 +#define DT_DEBUG 21 +#define DT_TEXTREL 22 +#define DT_JMPREL 23 +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* This info is needed when parsing the symbol table */ +#define STB_LOCAL 0 +#define STB_GLOBAL 1 +#define STB_WEAK 2 + +#define STT_NOTYPE 0 +#define STT_OBJECT 1 +#define STT_FUNC 2 +#define STT_SECTION 3 +#define STT_FILE 4 +#define STT_LOPROC 13 +#define STT_HIPROC 15 + +#define ELF32_ST_BIND(x) ((x) >> 4) +#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) + +#define ELF64_ST_BIND(x) ELF32_ST_BIND (x) +#define ELF64_ST_TYPE(x) ELF32_ST_TYPE (x) + +typedef struct dynamic32 { + Elf32_Sword d_tag; + union { + Elf32_Sword d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; + +typedef struct dynamic64 { + Elf64_Sxword d_tag; + union { + Elf64_Xword d_val; + Elf64_Addr d_ptr; + } d_un; +} Elf64_Dyn; + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef QNX4 +extern Elf32_Dyn _DYNAMIC[]; +#endif + +/* The following are used with relocations */ +#define ELF32_R_SYM(x) ((x) >> 8) +#define ELF32_R_TYPE(x) ((x) & 0xff) + +#define ELF64_R_SYM(x) ((x) >> 32) +#define ELF64_R_TYPE(x) ((x) & 0xffffffff) + +/* x86 Relocation Types */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +/* AMD64 Relocation Types */ +#define R_X86_64_NONE 0 +#define R_X86_64_64 1 +#define R_X86_64_PC32 2 +#define R_X86_64_GOT32 3 +#define R_X86_64_PLT32 4 +#define R_X86_64_COPY 5 +#define R_X86_64_GLOB_DAT 6 +#define R_X86_64_JUMP_SLOT 7 +#define R_X86_64_RELATIVE 8 +#define R_X86_64_GOTPCREL 9 +#define R_X86_64_32 10 +#define R_X86_64_32S 11 +#define R_X86_64_16 12 +#define R_X86_64_PC16 13 +#define R_X86_64_8 14 +#define R_X86_64_PC8 15 +#define R_X86_64_GNU_VTINHERIT 250 +#define R_X86_64_GNU_VTENTRY 251 + +/* sparc Relocation Types */ +#define R_SPARC_NONE 0 +#define R_SPARC_8 1 +#define R_SPARC_16 2 +#define R_SPARC_32 3 +#define R_SPARC_DISP8 4 +#define R_SPARC_DISP16 5 +#define R_SPARC_DISP32 6 +#define R_SPARC_WDISP30 7 +#define R_SPARC_WDISP22 8 +#define R_SPARC_HI22 9 +#define R_SPARC_22 10 +#define R_SPARC_13 11 +#define R_SPARC_LO10 12 +#define R_SPARC_GOT10 13 +#define R_SPARC_GOT13 14 +#define R_SPARC_GOT22 15 +#define R_SPARC_PC10 16 +#define R_SPARC_PC22 17 +#define R_SPARC_WPLT30 18 +#define R_SPARC_COPY 19 +#define R_SPARC_GLOB_DAT 20 +#define R_SPARC_JMP_SLOT 21 +#define R_SPARC_RELATIVE 22 +#define R_SPARC_UA32 23 +#define R_SPARC_PLT32 24 +#define R_SPARC_HIPLT22 25 +#define R_SPARC_LOPLT10 26 +#define R_SPARC_PCPLT32 27 +#define R_SPARC_PCPLT22 28 +#define R_SPARC_PCPLT10 29 +#define R_SPARC_10 30 +#define R_SPARC_11 31 +#define R_SPARC_64 32 +#define R_SPARC_OLO10 33 +#define R_SPARC_HH22 34 +#define R_SPARC_HM10 35 +#define R_SPARC_LM22 36 +#define R_SPARC_PC_HH22 37 +#define R_SPARC_PC_HM10 38 +#define R_SPARC_PC_LM22 39 +#define R_SPARC_WDISP16 40 +#define R_SPARC_WDISP19 41 +#define R_SPARC_GLOB_JMP 42 +#define R_SPARC_7 43 +#define R_SPARC_5 44 +#define R_SPARC_6 45 +#define R_SPARC_DISP64 46 +#define R_SPARC_PLT64 47 +#define R_SPARC_HIX22 48 +#define R_SPARC_LOX10 49 +#define R_SPARC_H44 50 +#define R_SPARC_M44 51 +#define R_SPARC_L44 52 +#define R_SPARC_REGISTER 53 +#define R_SPARC_UA64 54 +#define R_SPARC_UA16 55 +#define R_SPARC_NUM 56 + +/* m68k Relocation Types */ +#define R_68K_NONE 0 /* No reloc */ +#define R_68K_32 1 /* Direct 32 bit */ +#define R_68K_16 2 /* Direct 16 bit */ +#define R_68K_8 3 /* Direct 8 bit */ +#define R_68K_PC32 4 /* PC relative 32 bit */ +#define R_68K_PC16 5 /* PC relative 16 bit */ +#define R_68K_PC8 6 /* PC relative 8 bit */ +#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ +#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ +#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ +#define R_68K_GOT32O 10 /* 32 bit GOT offset */ +#define R_68K_GOT16O 11 /* 16 bit GOT offset */ +#define R_68K_GOT8O 12 /* 8 bit GOT offset */ +#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ +#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ +#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ +#define R_68K_PLT32O 16 /* 32 bit PLT offset */ +#define R_68K_PLT16O 17 /* 16 bit PLT offset */ +#define R_68K_PLT8O 18 /* 8 bit PLT offset */ +#define R_68K_COPY 19 /* Copy symbol at runtime */ +#define R_68K_GLOB_DAT 20 /* Create GOT entry */ +#define R_68K_JMP_SLOT 21 /* Create PLT entry */ +#define R_68K_RELATIVE 22 /* Adjust by program base */ + +/* Alpha Relocation Types */ +#define R_ALPHA_NONE 0 /* No reloc */ +#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ +#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ +#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ +#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ +#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ +#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ +#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define R_ALPHA_OP_PUSH 12 /* OP stack push */ +#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */ +#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */ +#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */ +#define R_ALPHA_GPVALUE 16 +#define R_ALPHA_GPRELHIGH 17 +#define R_ALPHA_GPRELLOW 18 +#define R_ALPHA_GPREL16 19 +#define R_ALPHA_IMMED_GP_HI32 20 +#define R_ALPHA_IMMED_SCN_HI32 21 +#define R_ALPHA_IMMED_BR_HI32 22 +#define R_ALPHA_IMMED_LO32 23 +#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ +#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ +#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ +#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ +#define R_ALPHA_BRSGP 28 /* Calc displacement for BRS */ + +/* IA-64 relocations. */ +#define R_IA64_NONE 0x00 /* none */ +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ +#define R_IA64_LTV32MSB 0x70 /* symbol + addend, data4 MSB */ +#define R_IA64_LTV32LSB 0x71 /* symbol + addend, data4 LSB */ +#define R_IA64_LTV64MSB 0x72 /* symbol + addend, data8 MSB */ +#define R_IA64_LTV64LSB 0x73 /* symbol + addend, data8 LSB */ +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ + +#define R_IA64_TYPE(R) ((R) & -8) +#define R_IA64_FORMAT(R) ((R) & 7) + +/* + * Apparantly, Linux and PowerMAXOS use different version of ELF as the + * Relocation types are very different. + */ +#if defined(PowerMAX_OS) +/* PPC Relocation Types */ +#define R_PPC_NONE 0 +#define R_PPC_COPY 1 +#define R_PPC_GOTP_ENT 2 +#define R_PPC_8 4 +#define R_PPC_8S 5 +#define R_PPC_16S 7 +#define R_PPC_14 8 +#define R_PPC_DISP14 9 +#define R_PPC_24 10 +#define R_PPC_DISP24 11 +#define R_PPC_PLT_DISP24 14 +#define R_PPC_BBASED_16HU 15 +#define R_PPC_BBASED_32 16 +#define R_PPC_BBASED_32UA 17 +#define R_PPC_BBASED_16H 18 +#define R_PPC_BBASED_16L 19 +#define R_PPC_ABDIFF_16HU 23 +#define R_PPC_ABDIFF_32 24 +#define R_PPC_ABDIFF_32UA 25 +#define R_PPC_ABDIFF_16H 26 +#define R_PPC_ABDIFF_16L 27 +#define R_PPC_ABDIFF_16 28 +#define R_PPC_16HU 31 +#define R_PPC_32 32 +#define R_PPC_32UA 33 +#define R_PPC_16H 34 +#define R_PPC_16L 35 +#define R_PPC_16 36 +#define R_PPC_GOT_16HU 39 +#define R_PPC_GOT_32 40 +#define R_PPC_GOT_32UA 41 +#define R_PPC_GOT_16H 42 +#define R_PPC_GOT_16L 43 +#define R_PPC_GOT_16 44 +#define R_PPC_GOTP_16HU 47 +#define R_PPC_GOTP_32 48 +#define R_PPC_GOTP_32UA 49 +#define R_PPC_GOTP_16H 50 +#define R_PPC_GOTP_16L 51 +#define R_PPC_GOTP_16 52 +#define R_PPC_PLT_16HU 55 +#define R_PPC_PLT_32 56 +#define R_PPC_PLT_32UA 57 +#define R_PPC_PLT_16H 58 +#define R_PPC_PLT_16L 59 +#define R_PPC_PLT_16 60 +#define R_PPC_ABREL_16HU 63 +#define R_PPC_ABREL_32 64 +#define R_PPC_ABREL_32UA 65 +#define R_PPC_ABREL_16H 66 +#define R_PPC_ABREL_16L 67 +#define R_PPC_ABREL_16 68 +#define R_PPC_GOT_ABREL_16HU 71 +#define R_PPC_GOT_ABREL_32 72 +#define R_PPC_GOT_ABREL_32UA 73 +#define R_PPC_GOT_ABREL_16H 74 +#define R_PPC_GOT_ABREL_16L 75 +#define R_PPC_GOT_ABREL_16 76 +#define R_PPC_GOTP_ABREL_16HU 79 +#define R_PPC_GOTP_ABREL_32 80 +#define R_PPC_GOTP_ABREL_32UA 81 +#define R_PPC_GOTP_ABREL_16H 82 +#define R_PPC_GOTP_ABREL_16L 83 +#define R_PPC_GOTP_ABREL_16 84 +#define R_PPC_PLT_ABREL_16HU 87 +#define R_PPC_PLT_ABREL_32 88 +#define R_PPC_PLT_ABREL_32UA 89 +#define R_PPC_PLT_ABREL_16H 90 +#define R_PPC_PLT_ABREL_16L 91 +#define R_PPC_PLT_ABREL_16 92 +#define R_PPC_SREL_16HU 95 +#define R_PPC_SREL_32 96 +#define R_PPC_SREL_32UA 97 +#define R_PPC_SREL_16H 98 +#define R_PPC_SREL_16L 99 +#else +/* + * The Linux version + */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 +#define R_PPC_ADDR24 2 +#define R_PPC_ADDR16 3 +#define R_PPC_ADDR16_LO 4 +#define R_PPC_ADDR16_HI 5 +#define R_PPC_ADDR16_HA 6 +#define R_PPC_ADDR14 7 +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 +#define R_PPC_REL14 11 +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +#endif + +/* ARM relocs. */ +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_PC24 1 /* PC relative 26 bit branch */ +#define R_ARM_ABS32 2 /* Direct 32 bit */ +#define R_ARM_REL32 3 /* PC relative 32 bit */ +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 /* Direct 16 bit */ +#define R_ARM_ABS12 6 /* Direct 12 bit */ +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 /* Direct 8 bit */ +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 +#define R_ARM_COPY 20 /* Copy symbol at runtime */ +#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ +#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ +#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ +#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ +#define R_ARM_GOT32 26 /* 32 bit GOT entry */ +#define R_ARM_PLT32 27 /* 32 bit PLT address */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ +#define R_ARM_THM_PC9 103 /* thumb conditional branch */ +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS22 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + +typedef struct elf32_rel { + Elf32_Addr r_offset; + Elf32_Word r_info; +} Elf32_Rel; + +typedef struct elf64_rel { + Elf64_Addr r_offset; + Elf64_Xword r_info; +} Elf64_Rel; + +typedef struct elf32_rela { + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; +} Elf32_Rela; + +typedef struct elf64_rela { + Elf64_Addr r_offset; + Elf64_Xword r_info; + Elf64_Sxword r_addend; +} Elf64_Rela; + +typedef struct elf32_sym { + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_Sym; + +typedef struct elf64_sym { + Elf64_Word st_name; + unsigned char st_info; + unsigned char st_other; + Elf64_Half st_shndx; + Elf64_Addr st_value; + Elf64_Xword st_size; +} Elf64_Sym; + +#define EI_NIDENT 16 + +typedef struct elf32hdr { + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; /* Entry point */ + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; +} Elf32_Ehdr; + +typedef struct elf64hdr { + unsigned char e_ident[EI_NIDENT]; + Elf64_Half e_type; + Elf64_Half e_machine; + Elf64_Word e_version; + Elf64_Addr e_entry; + Elf64_Off e_phoff; + Elf64_Off e_shoff; + Elf64_Word e_flags; + Elf64_Half e_ehsize; + Elf64_Half e_phentsize; + Elf64_Half e_phnum; + Elf64_Half e_shentsize; + Elf64_Half e_shnum; + Elf64_Half e_shstrndx; +} Elf64_Ehdr; + +/* These constants define the permissions on sections in the program + header, p_flags. */ +#define PF_R 0x4 +#define PF_W 0x2 +#define PF_X 0x1 + +typedef struct elf_phdr { + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; +} Elf32_Phdr; + +typedef struct { + Elf64_Word p_type; + Elf64_Word p_flags; + Elf64_Off p_offset; + Elf64_Addr p_vaddr; + Elf64_Addr p_paddr; + Elf64_Xword p_filesz; + Elf64_Xword p_memsz; + Elf64_Xword p_align; +} Elf64_Phdr; + +/* sh_type */ +#define SHT_NULL 0 +#define SHT_PROGBITS 1 +#define SHT_SYMTAB 2 +#define SHT_STRTAB 3 +#define SHT_RELA 4 +#define SHT_HASH 5 +#define SHT_DYNAMIC 6 +#define SHT_NOTE 7 +#define SHT_NOBITS 8 +#define SHT_REL 9 +#define SHT_SHLIB 10 +#define SHT_DYNSYM 11 +#define SHT_NUM 12 +#define SHT_LOPROC 0x70000000 +#define SHT_HIPROC 0x7fffffff +#define SHT_LOUSER 0x80000000 +#define SHT_HIUSER 0xffffffff + +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* sh_flags */ +#define SHF_WRITE 0x1 +#define SHF_ALLOC 0x2 +#define SHF_EXECINSTR 0x4 +#define SHF_MASKPROC 0xf0000000 + +/* special section indexes */ +#define SHN_UNDEF 0 +#define SHN_LORESERVE 0xff00 +#define SHN_LOPROC 0xff00 +#define SHN_HIPROC 0xff1f +#define SHN_ABS 0xfff1 +#define SHN_COMMON 0xfff2 +#define SHN_HIRESERVE 0xffff + +typedef struct { + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +} Elf32_Shdr; + +typedef struct { + Elf64_Word sh_name; + Elf64_Word sh_type; + Elf64_Xword sh_flags; + Elf64_Addr sh_addr; + Elf64_Off sh_offset; + Elf64_Xword sh_size; + Elf64_Word sh_link; + Elf64_Word sh_info; + Elf64_Xword sh_addralign; + Elf64_Xword sh_entsize; +} Elf64_Shdr; + +#define EI_MAG0 0 /* e_ident[] indexes */ +#define EI_MAG1 1 +#define EI_MAG2 2 +#define EI_MAG3 3 +#define EI_CLASS 4 +#define EI_DATA 5 +#define EI_VERSION 6 +#define EI_PAD 7 + +#define ELFMAG0 0x7f /* EI_MAG */ +#define ELFMAG1 'E' +#define ELFMAG2 'L' +#define ELFMAG3 'F' +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define ELFDLMAG 3 +#define ELFDLOFF 16 + +#define ELFCLASSNONE 0 /* EI_CLASS */ +#define ELFCLASS32 1 +#define ELFCLASS64 2 +#define ELFCLASSNUM 3 + +#define ELFDATANONE 0 /* e_ident[EI_DATA] */ +#define ELFDATA2LSB 1 +#define ELFDATA2MSB 2 + +#define EV_NONE 0 /* e_version, EI_VERSION */ +#define EV_CURRENT 1 +#define EV_NUM 2 + +/* Notes used in ET_CORE */ +#define NT_PRSTATUS 1 +#define NT_PRFPREG 2 +#define NT_PRPSINFO 3 +#define NT_TASKSTRUCT 4 + +/* Note header in a PT_NOTE section */ +typedef struct elf_note { + Elf32_Word n_namesz; /* Name size */ + Elf32_Word n_descsz; /* Content size */ + Elf32_Word n_type; /* Content type */ +} Elf32_Nhdr; + +#define ELF_START_MMAP 0x80000000 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elfloader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elfloader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/elfloader.h (revision 51223) @@ -0,0 +1,38 @@ +/* + * + * Copyright 1997,1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/elfloader.h,v 1.3 1998/09/20 14:41:05 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _ELFLOADER_H +#define _ELFLOADER_H +/* elfloader.c */ +extern void *ELFLoadModule(loaderPtr, int, LOOKUP **, int flags); +extern void ELFResolveSymbols(void *); +extern int ELFCheckForUnresolved(void *); +extern char *ELFAddressToSection(void *, unsigned long); +extern void ELFUnloadModule(void *); +#endif /* _ELFLOADER_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa.h (revision 51223) @@ -0,0 +1,718 @@ +/* + * + * Copyright (C) 2000 Keith Packard + * 2004 Eric Anholt + * 2005 Zack Rusin + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of copyright holders not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Copyright holders make no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + */ + +/** @file + * This is the header containing the public API of EXA for exa drivers. + */ + +#ifndef EXA_H +#define EXA_H + +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "windowstr.h" +#include "gcstruct.h" +#include "picturestr.h" + +#define EXA_VERSION_MAJOR 2 +#define EXA_VERSION_MINOR 0 +#define EXA_VERSION_RELEASE 0 + +typedef struct _ExaOffscreenArea ExaOffscreenArea; + +typedef void (*ExaOffscreenSaveProc) (ScreenPtr pScreen, ExaOffscreenArea *area); + +typedef enum _ExaOffscreenState { + ExaOffscreenAvail, + ExaOffscreenRemovable, + ExaOffscreenLocked +} ExaOffscreenState; + +struct _ExaOffscreenArea { + int base_offset; /* allocation base */ + int offset; /* aligned offset */ + int size; /* total allocation size */ + int score; + pointer privData; + + ExaOffscreenSaveProc save; + + ExaOffscreenState state; + + ExaOffscreenArea *next; +}; + +/** + * The ExaDriver structure is allocated through exaDriverAlloc(), and then + * fllled in by drivers. + */ +typedef struct _ExaDriver { + /** + * exa_major and exa_minor should be set by the driver to the version of + * EXA which the driver was compiled for (or configures itself at runtime to + * support). This allows EXA to extend the structure for new features + * without breaking ABI for drivers compiled against older versions. + */ + int exa_major, exa_minor; + + /** + * memoryBase is the address of the beginning of framebuffer memory. + * The visible screen should be within memoryBase to memoryBase + + * memorySize. + */ + CARD8 *memoryBase; + + /** + * offScreenBase is the offset from memoryBase of the beginning of the area + * to be managed by EXA's linear offscreen memory manager. + * + * In XFree86 DDX drivers, this is probably: + * (pScrn->displayWidth * cpp * pScrn->virtualY) + */ + unsigned long offScreenBase; + + /** + * memorySize is the length (in bytes) of framebuffer memory beginning + * from memoryBase. + * + * The offscreen memory manager will manage the area beginning at + * (memoryBase + offScreenBase), with a length of (memorySize - + * offScreenBase) + * + * In XFree86 DDX drivers, this is probably (pScrn->videoRam * 1024) + */ + unsigned long memorySize; + + /** + * pixmapOffsetAlign is the byte alignment necessary for pixmap offsets + * within framebuffer. + * + * Hardware typically has a required alignment of offsets, which may or may + * not be a power of two. EXA will ensure that pixmaps managed by the + * offscreen memory manager meet this alignment requirement. + */ + int pixmapOffsetAlign; + + /** + * pixmapPitchAlign is the byte alignment necessary for pixmap pitches + * within the framebuffer. + * + * Hardware typically has a required alignment of pitches for acceleration. + * For 3D hardware, Composite acceleration often requires that source and + * mask pixmaps (textures) have a power-of-two pitch, which can be demanded + * using EXA_OFFSCREEN_ALIGN_POT. These pitch requirements only apply to + * pixmaps managed by the offscreen memory manager. Thus, it is up to the + * driver to ensure that the visible screen has an appropriate pitch for + * acceleration. + */ + int pixmapPitchAlign; + + /** + * The flags field is bitfield of boolean values controlling EXA's behavior. + * + * The flags in clude EXA_OFFSCREEN_PIXMAPS, EXA_OFFSCREEN_ALIGN_POT, and + * EXA_TWO_BITBLT_DIRECTIONS. + */ + int flags; + + /** @{ */ + /** + * maxX controls the X coordinate limitation for rendering from the card. + * The driver should never receive a request for rendering beyond maxX + * in the X direction from the origin of a pixmap. + */ + int maxX; + + /** + * maxY controls the Y coordinate limitation for rendering from the card. + * The driver should never receive a request for rendering beyond maxY + * in the Y direction from the origin of a pixmap. + */ + int maxY; + /** @} */ + + /* private */ + ExaOffscreenArea *offScreenAreas; + Bool needsSync; + int lastMarker; + + /** @name Solid + * @{ + */ + /** + * PrepareSolid() sets up the driver for doing a solid fill. + * @param pPixmap Destination pixmap + * @param alu raster operation + * @param planemask write mask for the fill + * @param fg "foreground" color for the fill + * + * This call should set up the driver for doing a series of solid fills + * through the Solid() call. The alu raster op is one of the GX* + * graphics functions listed in X.h, and typically maps to a similar + * single-byte "ROP" setting in all hardware. The planemask controls + * which bits of the destination should be affected, and will only represent + * the bits up to the depth of pPixmap. The fg is the pixel value of the + * foreground color referred to in ROP descriptions. + * + * Note that many drivers will need to store some of the data in the driver + * private record, for sending to the hardware with each drawing command. + * + * The PrepareSolid() call is required of all drivers, but it may fail for any + * reason. Failure results in a fallback to software rendering. + */ + Bool (*PrepareSolid) (PixmapPtr pPixmap, + int alu, + Pixel planemask, + Pixel fg); + + /** + * Solid() performs a solid fill set up in the last PrepareSolid() call. + * + * @param pPixmap destination pixmap + * @param x1 left coordinate + * @param y1 top coordinate + * @param x2 right coordinate + * @param y2 bottom coordinate + * + * Performs the fill set up by the last PrepareSolid() call, covering the + * area from (x1,y1) to (x2,y2) in pPixmap. Note that the coordinates are + * in the coordinate space of the destination pixmap, so the driver will + * need to set up the hardware's offset and pitch for the destination + * coordinates according to the pixmap's offset and pitch within + * framebuffer. This likely means using exaGetPixmapOffset() and + * exaGetPixmapPitch(). + * + * This call is required if PrepareSolid() ever succeeds. + */ + void (*Solid) (PixmapPtr pPixmap, int x1, int y1, int x2, int y2); + + /** + * DoneSolid() finishes a set of solid fills. + * + * @param pPixmap destination pixmap. + * + * The DoneSolid() call is called at the end of a series of consecutive + * Solid() calls following a successful PrepareSolid(). This allows drivers + * to finish up emitting drawing commands that were buffered, or clean up + * state from PrepareSolid(). + * + * This call is required if PrepareSolid() ever succeeds. + */ + void (*DoneSolid) (PixmapPtr pPixmap); + /** @} */ + + /** @name Copy + * @{ + */ + /** + * PrepareCopy() sets up the driver for doing a copy within offscreen + * memory. + * + * @param pSrcPixmap source pixmap + * @param pDstPixmap destination pixmap + * @param dx X copy direction + * @param dy Y copy direction + * @param alu raster operation + * @param planemask write mask for the fill + * + * This call should set up the driver for doing a series of copies from the + * the pSrcPixmap to the pDstPixmap. The dx flag will be positive if the + * hardware should do the copy from the left to the right, and dy will be + * positive if the copy should be done from the top to the bottom. This + * is to deal with self-overlapping copies when pSrcPixmap == pDstPixmap. + * If your hardware can only support blits that are (left to right, top to + * bottom) or (right to left, bottom to top), then you should set + * #EXA_TWO_BITBLT_DIRECTIONS, and EXA will break down Copy operations to + * ones that meet those requirements. The alu raster op is one of the GX* + * graphics functions listed in X.h, and typically maps to a similar + * single-byte "ROP" setting in all hardware. The planemask controls which + * bits of the destination should be affected, and will only represent the + * bits up to the depth of pPixmap. + * + * Note that many drivers will need to store some of the data in the driver + * private record, for sending to the hardware with each drawing command. + * + * The PrepareCopy() call is required of all drivers, but it may fail for any + * reason. Failure results in a fallback to software rendering. + */ + Bool (*PrepareCopy) (PixmapPtr pSrcPixmap, + PixmapPtr pDstPixmap, + int dx, + int dy, + int alu, + Pixel planemask); + + /** + * Copy() performs a copy set up in the last PrepareCopy call. + * + * @param pDstPixmap destination pixmap + * @param srcX source X coordinate + * @param srcY source Y coordinate + * @param dstX destination X coordinate + * @param dstY destination Y coordinate + * @param width width of the rectangle to be copied + * @param height height of the rectangle to be copied. + * + * Performs the copy set up by the last PrepareCopy() call, copying the + * rectangle from (srcX, srcY) to (srcX + width, srcY + width) in the source + * pixmap to the same-sized rectangle at (dstX, dstY) in the destination + * pixmap. Those rectangles may overlap in memory, if + * pSrcPixmap == pDstPixmap. Note that this call does not receive the + * pSrcPixmap as an argument -- if it's needed in this function, it should + * be stored in the driver private during PrepareCopy(). As with Solid(), + * the coordinates are in the coordinate space of each pixmap, so the driver + * will need to set up source and destination pitches and offsets from those + * pixmaps, probably using exaGetPixmapOffset() and exaGetPixmapPitch(). + * + * This call is required if PrepareCopy ever succeeds. + */ + void (*Copy) (PixmapPtr pDstPixmap, + int srcX, + int srcY, + int dstX, + int dstY, + int width, + int height); + + /** + * DoneCopy() finishes a set of copies. + * + * @param pPixmap destination pixmap. + * + * The DoneCopy() call is called at the end of a series of consecutive + * Copy() calls following a successful PrepareCopy(). This allows drivers + * to finish up emitting drawing commands that were buffered, or clean up + * state from PrepareCopy(). + * + * This call is required if PrepareCopy() ever succeeds. + */ + void (*DoneCopy) (PixmapPtr pDstPixmap); + /** @} */ + + /** @name Composite + * @{ + */ + /** + * CheckComposite() checks to see if a composite operation could be + * accelerated. + * + * @param op Render operation + * @param pSrcPicture source Picture + * @param pMaskPicture mask picture + * @param pDstPicture destination Picture + * + * The CheckComposite() call checks if the driver could handle acceleration + * of op with the given source, mask, and destination pictures. This allows + * drivers to check source and destination formats, supported operations, + * transformations, and component alpha state, and send operations it can't + * support to software rendering early on. This avoids costly pixmap + * migration to the wrong places when the driver can't accelerate + * operations. Note that because migration hasn't happened, the driver + * can't know during CheckComposite() what the offsets and pitches of the + * pixmaps are going to be. + * + * See PrepareComposite() for more details on likely issues that drivers + * will have in accelerating Composite operations. + * + * The CheckComposite() call is recommended if PrepareComposite() is + * implemented, but is not required. + */ + Bool (*CheckComposite) (int op, + PicturePtr pSrcPicture, + PicturePtr pMaskPicture, + PicturePtr pDstPicture); + + /** + * PrepareComposite() sets up the driver for doing a Composite operation + * described in the Render extension protocol spec. + * + * @param op Render operation + * @param pSrcPicture source Picture + * @param pMaskPicture mask picture + * @param pDstPicture destination Picture + * @param pSrc source pixmap + * @param pMask mask pixmap + * @param pDst destination pixmap + * + * This call should set up the driver for doing a series of Composite + * operations, as described in the Render protocol spec, with the given + * pSrcPicture, pMaskPicture, and pDstPicture. The pSrc, pMask, and + * pDst are the pixmaps containing the pixel data, and should be used for + * setting the offset and pitch used for the coordinate spaces for each of + * the Pictures. + * + * Notes on interpreting Picture structures: + * - The Picture structures will always have a valid pDrawable. + * - The Picture structures will never have alphaMap set. + * - The mask Picture (and therefore pMask) may be NULL, in which case the + * operation is simply src OP dst instead of src IN mask OP dst, and + * mask coordinates should be ignored. + * - pMarkPicture may have componentAlpha set, which greatly changes + * the behavior of the Composite operation. componentAlpha has no effect + * when set on pSrcPicture or pDstPicture. + * - The source and mask Pictures may have a transformation set + * (Picture->transform != NULL), which means that the source coordinates + * should be transformed by that transformation, resulting in scaling, + * rotation, etc. The PictureTransformPoint() call can transform + * coordinates for you. Transforms have no effect on Pictures when used + * as a destination. + * - The source and mask pictures may have a filter set. PictFilterNearest + * and PictFilterBilinear are defined in the Render protocol, but others + * may be encountered, and must be handled correctly (usually by + * PrepareComposite failing, and falling back to software). Filters have + * no effect on Pictures when used as a destination. + * - The source and mask Pictures may have repeating set, which must be + * respected. Many chipsets will be unable to support repeating on + * pixmaps that have a width or height that is not a power of two. + * + * If your hardware can't support source pictures (textures) with + * non-power-of-two pitches, you should set #EXA_OFFSCREEN_ALIGN_POT. + * + * Note that many drivers will need to store some of the data in the driver + * private record, for sending to the hardware with each drawing command. + * + * The PrepareComposite() call is not required. However, it is highly + * recommended for performance of antialiased font rendering and performance + * of cairo applications. Failure results in a fallback to software + * rendering. + */ + Bool (*PrepareComposite) (int op, + PicturePtr pSrcPicture, + PicturePtr pMaskPicture, + PicturePtr pDstPicture, + PixmapPtr pSrc, + PixmapPtr pMask, + PixmapPtr pDst); + + /** + * Composite() performs a Composite operation set up in the last + * PrepareComposite() call. + * + * @param pDstPixmap destination pixmap + * @param srcX source X coordinate + * @param srcY source Y coordinate + * @param maskX source X coordinate + * @param maskY source Y coordinate + * @param dstX destination X coordinate + * @param dstY destination Y coordinate + * @param width destination rectangle width + * @param height destination rectangle height + * + * Performs the Composite operation set up by the last PrepareComposite() + * call, to the rectangle from (dstX, dstY) to (dstX + width, dstY + height) + * in the destination Pixmap. Note that if a transformation was set on + * the source or mask Pictures, the source rectangles may not be the same + * size as the destination rectangles and filtering. Getting the coordinate + * transformation right at the subpixel level can be tricky, and rendercheck + * can test this for you. + * + * This call is required if PrepareComposite() ever succeeds. + */ + void (*Composite) (PixmapPtr pDst, + int srcX, + int srcY, + int maskX, + int maskY, + int dstX, + int dstY, + int width, + int height); + + /** + * DoneComposite() finishes a set of Composite operations. + * + * @param pPixmap destination pixmap. + * + * The DoneComposite() call is called at the end of a series of consecutive + * Composite() calls following a successful PrepareComposite(). This allows + * drivers to finish up emitting drawing commands that were buffered, or + * clean up state from PrepareComposite(). + * + * This call is required if PrepareComposite() ever succeeds. + */ + void (*DoneComposite) (PixmapPtr pDst); + /** @} */ + + /** + * UploadToScreen() loads a rectangle of data from src into pDst. + * + * @param pDst destination pixmap + * @param x destination X coordinate. + * @param y destination Y coordinate + * @param width width of the rectangle to be copied + * @param height height of the rectangle to be copied + * @param src pointer to the beginning of the source data + * @param src_pitch pitch (in bytes) of the lines of source data. + * + * UploadToScreen() copies data in system memory beginning at src (with + * pitch src_pitch) into the destination pixmap from (x, y) to + * (x + width, y + height). This is typically done with hostdata uploads, + * where the CPU sets up a blit command on the hardware with instructions + * that the blit data will be fed through some sort of aperture on the card. + * + * If UploadToScreen() is performed asynchronously, it is up to the driver + * to call exaMarkSync(). This is in contrast to most other acceleration + * calls in EXA. + * + * UploadToScreen() can aid in pixmap migration, but is most important for + * the performance of exaGlyphs() (antialiased font drawing) by allowing + * pipelining of data uploads, avoiding a sync of the card after each glyph. + * + * @return TRUE if the driver successfully uploaded the data. FALSE + * indicates that EXA should fall back to doing the upload in software. + * + * UploadToScreen() is not required, but is recommended if Composite + * acceleration is supported. + */ + Bool (*UploadToScreen) (PixmapPtr pDst, + int x, + int y, + int w, + int h, + char *src, + int src_pitch); + + /** + * UploadToScratch() is used to upload a pixmap to a scratch area for + * acceleration. + * + * @param pSrc source pixmap in host memory + * @param pDst fake, scratch pixmap to be set up in offscreen memory. + * + * The UploadToScratch() call was added to support Xati before Xati had + * support for hostdata uploads and before exaGlyphs() was written. It + * behaves incorrectly (uses an invalid pixmap as pDst), + * and UploadToScreen() should be implemented instead. + * + * Drivers implementing UploadToScratch() had to set up space (likely in a + * statically allocated area) in offscreen memory, copy pSrc to that + * scratch area, and adust pDst->devKind for the pitch and + * pDst->devPrivate.ptr for the pointer to that scratch area. The driver + * was responsible for syncing (as it was implemented using memcpy() in + * Xati), and only the data from the last UploadToScratch() was guaranteed + * to be valid at any given time. + * + * UploadToScratch() should not be implemented by drivers, and will likely + * be removed in a future version of EXA. + */ + Bool (*UploadToScratch) (PixmapPtr pSrc, + PixmapPtr pDst); + + /** + * DownloadFromScreen() loads a rectangle of data from pSrc into dst + * + * @param pSrc source pixmap + * @param x source X coordinate. + * @param y source Y coordinate + * @param width width of the rectangle to be copied + * @param height height of the rectangle to be copied + * @param dst pointer to the beginning of the destination data + * @param dst_pitch pitch (in bytes) of the lines of destination data. + * + * DownloadFromScreen() copies data from offscreen memory in pSrc from + * (x, y) to (x + width, y + height), to system memory starting at + * dst (with pitch dst_pitch). This would usually be done + * using scatter-gather DMA, supported by a DRM call, or by blitting to AGP + * and then synchronously reading from AGP. Because the implementation + * might be synchronous, EXA leaves it up to the driver to call + * exaMarkSync() if DownloadFromScreen() was asynchronous. This is in + * contrast to most other acceleration calls in EXA. + * + * DownloadFromScreen() can aid in the largest bottleneck in pixmap + * migration, which is the read from framebuffer when evicting pixmaps from + * framebuffer memory. Thus, it is highly recommended, even though + * implementations are typically complicated. + * + * @return TRUE if the driver successfully downloaded the data. FALSE + * indicates that EXA should fall back to doing the download in software. + * + * DownloadFromScreen() is not required, but is highly recommended. + */ + Bool (*DownloadFromScreen)(PixmapPtr pSrc, + int x, int y, + int w, int h, + char *dst, int dst_pitch); + + /** + * MarkSync() requests that the driver mark a synchronization point, + * returning an driver-defined integer marker which could be requested for + * synchronization to later in WaitMarker(). This might be used in the + * future to avoid waiting for full hardware stalls before accessing pixmap + * data with the CPU, but is not important in the current incarnation of + * EXA. + * + * Note that drivers should call exaMarkSync() when they have done some + * acceleration, rather than their own MarkSync() handler, as otherwise EXA + * will be unaware of the driver's acceleration and not sync to it during + * fallbacks. + * + * MarkSync() is optional. + */ + int (*MarkSync) (ScreenPtr pScreen); + + /** + * WaitMarker() waits for all rendering before the given marker to have + * completed. If the driver does not implement MarkSync(), marker is + * meaningless, and all rendering by the hardware should be completed before + * WaitMarker() returns. + * + * Note that drivers should call exaWaitSync() to wait for all acceleration + * to finish, as otherwise EXA will be unaware of the driver having + * synchronized, resulting in excessive WaitMarker() calls. + * + * WaitMarker() is required of all drivers. + */ + void (*WaitMarker) (ScreenPtr pScreen, int marker); + + /** @{ */ + /** + * PrepareAccess() is called before CPU access to an offscreen pixmap. + * + * @param pPix the pixmap being accessed + * @param index the index of the pixmap being accessed. + * + * PrepareAccess() will be called before CPU access to an offscreen pixmap. + * This can be used to set up hardware surfaces for byteswapping or + * untiling, or to adjust the pixmap's devPrivate.ptr for the purpose of + * making CPU access use a different aperture. + * + * The index is one of #EXA_PREPARE_DEST, #EXA_PREPARE_SRC, or + * #EXA_PREPARE_MASK, indicating which pixmap is in question. Since only up + * to three pixmaps will have PrepareAccess() called on them per operation, + * drivers can have a small, statically-allocated space to maintain state + * for PrepareAccess() and FinishAccess() in. Note that the same pixmap may + * have PrepareAccess() called on it more than once, for example when doing + * a copy within the same pixmap (so it gets PrepareAccess as() + * #EXA_PREPARE_DEST and then as #EXA_PREPARE_SRC). + * + * PrepareAccess() may fail. An example might be the case of hardware that + * can set up 1 or 2 surfaces for CPU access, but not 3. If PrepareAccess() + * fails, EXA will migrate the pixmap to system memory. + * DownloadFromScreen() must be implemented and must not fail if a driver + * wishes to fail in PrepareAccess(). PrepareAccess() must not fail when + * pPix is the visible screen, because the visible screen can not be + * migrated. + * + * @return TRUE if PrepareAccess() successfully prepared the pixmap for CPU + * drawing. + * @return FALSE if PrepareAccess() is unsuccessful and EXA should use + * DownloadFromScreen() to migate the pixmap out. + */ + Bool (*PrepareAccess)(PixmapPtr pPix, int index); + + /** + * FinishAccess() is called after CPU access to an offscreen pixmap. + * + * @param pPix the pixmap being accessed + * @param index the index of the pixmap being accessed. + * + * FinishAccess() will be called after finishing CPU access of an offscreen + * pixmap set up by PrepareAccess(). Note that the FinishAccess() will not be + * called if PrepareAccess() failed and the pixmap was migrated out. + */ + void (*FinishAccess)(PixmapPtr pPix, int index); + + /** @name PrepareAccess() and FinishAccess() indices + * @{ + */ + /** + * EXA_PREPARE_DEST is the index for a pixmap that may be drawn to or + * read from. + */ + #define EXA_PREPARE_DEST 0 + /** + * EXA_PREPARE_SRC is the index for a pixmap that may be read from + */ + #define EXA_PREPARE_SRC 1 + /** + * EXA_PREPARE_SRC is the index for a second pixmap that may be read + * from. + */ + #define EXA_PREPARE_MASK 2 + /** @} */ + /** @} */ +} ExaDriverRec, *ExaDriverPtr; + +/** @name EXA driver flags + * @{ + */ +/** + * EXA_OFFSCREEN_PIXMAPS indicates to EXA that the driver can support + * offscreen pixmaps. + */ +#define EXA_OFFSCREEN_PIXMAPS (1 << 0) + +/** + * EXA_OFFSCREEN_ALIGN_POT indicates to EXA that the driver needs pixmaps + * to have a power-of-two pitch. + */ +#define EXA_OFFSCREEN_ALIGN_POT (1 << 1) + +/** + * EXA_TWO_BITBLT_DIRECTIONS indicates to EXA that the driver can only + * support copies that are (left-to-right, top-to-bottom) or + * (right-to-left, bottom-to-top). + */ +#define EXA_TWO_BITBLT_DIRECTIONS (1 << 2) +/** @} */ + +ExaDriverPtr +exaDriverAlloc(void); + +Bool +exaDriverInit(ScreenPtr pScreen, + ExaDriverPtr pScreenInfo); + +void +exaDriverFini(ScreenPtr pScreen); + +void +exaMarkSync(ScreenPtr pScreen); +void +exaWaitSync(ScreenPtr pScreen); + +ExaOffscreenArea * +exaOffscreenAlloc(ScreenPtr pScreen, int size, int align, + Bool locked, + ExaOffscreenSaveProc save, + pointer privData); + +ExaOffscreenArea * +exaOffscreenFree(ScreenPtr pScreen, ExaOffscreenArea *area); + +unsigned long +exaGetPixmapOffset(PixmapPtr pPix); + +unsigned long +exaGetPixmapPitch(PixmapPtr pPix); + +unsigned long +exaGetPixmapSize(PixmapPtr pPix); + +void +exaEnableDisableFBAccess (int index, Bool enable); + +#endif /* EXA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa_priv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa_priv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exa_priv.h (revision 51223) @@ -0,0 +1,420 @@ +/* + * + * Copyright (C) 2000 Keith Packard, member of The XFree86 Project, Inc. + * 2005 Zack Rusin, Trolltech + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + */ + +#ifndef EXAPRIV_H +#define EXAPRIV_H + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "exa.h" + +#include +#define NEED_EVENTS +#include +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "windowstr.h" +#include "servermd.h" +#include "mibstore.h" +#include "colormapst.h" +#include "gcstruct.h" +#include "input.h" +#include "mipointer.h" +#include "mi.h" +#include "dix.h" +#include "fb.h" +#include "fboverlay.h" +#ifdef RENDER +#include "fbpict.h" +#endif + +#define DEBUG_TRACE_FALL 0 +#define DEBUG_MIGRATE 0 +#define DEBUG_PIXMAP 0 +#define DEBUG_OFFSCREEN 0 + +#if DEBUG_TRACE_FALL +#define EXA_FALLBACK(x) \ +do { \ + ErrorF("EXA fallback at %s: ", __FUNCTION__); \ + ErrorF x; \ +} while (0) +#else +#define EXA_FALLBACK(x) +#endif + +#if DEBUG_PIXMAP +#define DBG_PIXMAP(a) ErrorF a +#else +#define DBG_PIXMAP(a) +#endif + +#ifndef EXA_MAX_FB +#define EXA_MAX_FB FB_OVERLAY_MAX +#endif + +/** + * This is the list of migration heuristics supported by EXA. See + * exaDoMigration() for what their implementations do. + */ +enum ExaMigrationHeuristic { + ExaMigrationGreedy, + ExaMigrationAlways +}; + +typedef void (*EnableDisableFBAccessProcPtr)(int, Bool); +typedef struct { + ExaDriverPtr info; + CreateGCProcPtr SavedCreateGC; + CloseScreenProcPtr SavedCloseScreen; + GetImageProcPtr SavedGetImage; + GetSpansProcPtr SavedGetSpans; + PaintWindowBackgroundProcPtr SavedPaintWindowBackground; + CreatePixmapProcPtr SavedCreatePixmap; + DestroyPixmapProcPtr SavedDestroyPixmap; + PaintWindowBorderProcPtr SavedPaintWindowBorder; + CopyWindowProcPtr SavedCopyWindow; +#ifdef RENDER + CompositeProcPtr SavedComposite; + RasterizeTrapezoidProcPtr SavedRasterizeTrapezoid; + AddTrianglesProcPtr SavedAddTriangles; + GlyphsProcPtr SavedGlyphs; +#endif + Bool swappedOut; + enum ExaMigrationHeuristic migration; + Bool hideOffscreenPixmapData; +} ExaScreenPrivRec, *ExaScreenPrivPtr; + +/* + * This is the only completely portable way to + * compute this info. + */ +#ifndef BitsPerPixel +#define BitsPerPixel(d) (\ + PixmapWidthPaddingInfo[d].notPower2 ? \ + (PixmapWidthPaddingInfo[d].bytesPerPixel * 8) : \ + ((1 << PixmapWidthPaddingInfo[d].padBytesLog2) * 8 / \ + (PixmapWidthPaddingInfo[d].padRoundUp+1))) +#endif + +extern int exaScreenPrivateIndex; +extern int exaPixmapPrivateIndex; +#define ExaGetScreenPriv(s) ((ExaScreenPrivPtr)(s)->devPrivates[exaScreenPrivateIndex].ptr) +#define ExaScreenPriv(s) ExaScreenPrivPtr pExaScr = ExaGetScreenPriv(s) + +/** Align an offset to an arbitrary alignment */ +#define EXA_ALIGN(offset, align) (((offset) + (align) - 1) - \ + (((offset) + (align) - 1) % (align))) +/** Align an offset to a power-of-two alignment */ +#define EXA_ALIGN2(offset, align) (((offset) + (align) - 1) & ~((align) - 1)) + +/** + * Returns TRUE if the given planemask covers all the significant bits in the + * pixel values for pDrawable. + */ +#define EXA_PM_IS_SOLID(_pDrawable, _pm) \ + (((_pm) & FbFullMask((_pDrawable)->depth)) == \ + FbFullMask((_pDrawable)->depth)) + +#define EXA_PIXMAP_SCORE_MOVE_IN 10 +#define EXA_PIXMAP_SCORE_MAX 20 +#define EXA_PIXMAP_SCORE_MOVE_OUT -10 +#define EXA_PIXMAP_SCORE_MIN -20 +#define EXA_PIXMAP_SCORE_PINNED 1000 +#define EXA_PIXMAP_SCORE_INIT 1001 + +#define ExaGetPixmapPriv(p) ((ExaPixmapPrivPtr)(p)->devPrivates[exaPixmapPrivateIndex].ptr) +#define ExaSetPixmapPriv(p,a) ((p)->devPrivates[exaPixmapPrivateIndex].ptr = (pointer) (a)) +#define ExaPixmapPriv(p) ExaPixmapPrivPtr pExaPixmap = ExaGetPixmapPriv(p) + +typedef struct { + ExaOffscreenArea *area; + int score; /**< score for the move-in vs move-out heuristic */ + + CARD8 *sys_ptr; /**< pointer to pixmap data in system memory */ + int sys_pitch; /**< pitch of pixmap in system memory */ + + CARD8 *fb_ptr; /**< pointer to pixmap data in framebuffer memory */ + int fb_pitch; /**< pitch of pixmap in framebuffer memory */ + unsigned int fb_size; /**< size of pixmap in framebuffer memory */ + + /** + * If area is NULL, then dirty == TRUE means that the pixmap has been + * modified, so the contents are defined. Used to avoid uploads of + * undefined data. + * + * If area is non-NULL, then dirty == TRUE means that the pixmap data at + * pPixmap->devPrivate.ptr (either fb_ptr or sys_ptr) has been changed + * compared to the copy in the other location. This is used to avoid + * uploads/downloads of unmodified data. + */ + Bool dirty; +} ExaPixmapPrivRec, *ExaPixmapPrivPtr; + +typedef struct _ExaMigrationRec { + Bool as_dst; + Bool as_src; + PixmapPtr pPix; +} ExaMigrationRec, *ExaMigrationPtr; + +/** + * exaDDXDriverInit must be implemented by the DDX using EXA, and is the place + * to set EXA options or hook in screen functions to handle using EXA as the AA. + */ +void exaDDXDriverInit (ScreenPtr pScreen); + +/* exa_unaccel.c */ +void +exaPrepareAccessGC(GCPtr pGC); + +void +exaFinishAccessGC(GCPtr pGC); + +void +ExaCheckFillSpans (DrawablePtr pDrawable, GCPtr pGC, int nspans, + DDXPointPtr ppt, int *pwidth, int fSorted); + +void +ExaCheckSetSpans (DrawablePtr pDrawable, GCPtr pGC, char *psrc, + DDXPointPtr ppt, int *pwidth, int nspans, int fSorted); + +void +ExaCheckPutImage (DrawablePtr pDrawable, GCPtr pGC, int depth, + int x, int y, int w, int h, int leftPad, int format, + char *bits); + +RegionPtr +ExaCheckCopyArea (DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, int dstx, int dsty); + +RegionPtr +ExaCheckCopyPlane (DrawablePtr pSrc, DrawablePtr pDst, GCPtr pGC, + int srcx, int srcy, int w, int h, int dstx, int dsty, + unsigned long bitPlane); + +void +ExaCheckPolyPoint (DrawablePtr pDrawable, GCPtr pGC, int mode, int npt, + DDXPointPtr pptInit); + +void +ExaCheckPolylines (DrawablePtr pDrawable, GCPtr pGC, + int mode, int npt, DDXPointPtr ppt); + +void +ExaCheckPolySegment (DrawablePtr pDrawable, GCPtr pGC, + int nsegInit, xSegment *pSegInit); + +void +ExaCheckPolyArc (DrawablePtr pDrawable, GCPtr pGC, + int narcs, xArc *pArcs); + +void +ExaCheckPolyFillRect (DrawablePtr pDrawable, GCPtr pGC, + int nrect, xRectangle *prect); + +void +ExaCheckImageGlyphBlt (DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); + +void +ExaCheckPolyGlyphBlt (DrawablePtr pDrawable, GCPtr pGC, + int x, int y, unsigned int nglyph, + CharInfoPtr *ppci, pointer pglyphBase); + +void +ExaCheckPushPixels (GCPtr pGC, PixmapPtr pBitmap, + DrawablePtr pDrawable, + int w, int h, int x, int y); + +void +ExaCheckGetImage (DrawablePtr pDrawable, + int x, int y, int w, int h, + unsigned int format, unsigned long planeMask, + char *d); + +void +ExaCheckGetSpans (DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pdstStart); + +void +ExaCheckSaveAreas (PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +ExaCheckRestoreAreas (PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +ExaCheckPaintWindow (WindowPtr pWin, RegionPtr pRegion, int what); + +CARD32 +exaGetPixmapFirstPixel (PixmapPtr pPixmap); + +/* exa_accel.c */ +void +exaCopyWindow(WindowPtr pWin, DDXPointRec ptOldOrg, RegionPtr prgnSrc); + +void +exaPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + +void +exaGetImage (DrawablePtr pDrawable, int x, int y, int w, int h, + unsigned int format, unsigned long planeMask, char *d); + +void +exaGetSpans (DrawablePtr pDrawable, int wMax, DDXPointPtr ppt, int *pwidth, + int nspans, char *pdstStart); + +extern const GCOps exaOps; + +#ifdef RENDER +void +ExaCheckComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +#endif + +/* exaoffscreen.c */ +void +ExaOffscreenMarkUsed (PixmapPtr pPixmap); + +void +ExaOffscreenSwapOut (ScreenPtr pScreen); + +void +ExaOffscreenSwapIn (ScreenPtr pScreen); + +Bool +exaOffscreenInit(ScreenPtr pScreen); + +void +ExaOffscreenFini (ScreenPtr pScreen); + +/* exa.c */ +void +exaPrepareAccess(DrawablePtr pDrawable, int index); + +void +exaFinishAccess(DrawablePtr pDrawable, int index); + +void +exaDrawableDirty(DrawablePtr pDrawable); + +Bool +exaDrawableIsOffscreen (DrawablePtr pDrawable); + +Bool +exaPixmapIsOffscreen(PixmapPtr p); + +PixmapPtr +exaGetOffscreenPixmap (DrawablePtr pDrawable, int *xp, int *yp); + +PixmapPtr +exaGetDrawablePixmap(DrawablePtr pDrawable); + +RegionPtr +exaCopyArea(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable, GCPtr pGC, + int srcx, int srcy, int width, int height, int dstx, int dsty); + +void +exaCopyNtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +/* exa_render.c */ +void +exaComposite(CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +exaRasterizeTrapezoid (PicturePtr pPicture, xTrapezoid *trap, + int x_off, int y_off); + +void +exaAddTriangles (PicturePtr pPicture, INT16 x_off, INT16 y_off, int ntri, + xTriangle *tris); + +void +exaGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +/* exa_migration.c */ +void +exaDoMigration (ExaMigrationPtr pixmaps, int npixmaps, Bool can_accel); + +void +exaMoveInPixmap (PixmapPtr pPixmap); + +void +exaMoveOutPixmap (PixmapPtr pPixmap); + +#endif /* EXAPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exevents.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exevents.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exevents.h (revision 51223) @@ -0,0 +1,183 @@ +/* $XFree86: xc/programs/Xserver/include/exevents.h,v 3.1 1996/04/15 11:34:29 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/******************************************************************** + * Interface of 'exevents.c' + */ + +#ifndef EXEVENTS_H +#define EXEVENTS_H + +extern void RegisterOtherDevice ( + DeviceIntPtr /* device */); + +extern void ProcessOtherEvent ( + xEventPtr /* FIXME deviceKeyButtonPointer * xE */, + DeviceIntPtr /* other */, + int /* count */); + +extern int InitProximityClassDeviceStruct( + DeviceIntPtr /* dev */); + +extern void InitValuatorAxisStruct( + DeviceIntPtr /* dev */, + int /* axnum */, + int /* minval */, + int /* maxval */, + int /* resolution */, + int /* min_res */, + int /* max_res */); + +extern void DeviceFocusEvent( + DeviceIntPtr /* dev */, + int /* type */, + int /* mode */, + int /* detail */, + WindowPtr /* pWin */); + +extern int GrabButton( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + BYTE /* this_device_mode */, + BYTE /* other_devices_mode */, + CARD16 /* modifiers */, + DeviceIntPtr /* modifier_device */, + CARD8 /* button */, + Window /* grabWindow */, + BOOL /* ownerEvents */, + Cursor /* rcursor */, + Window /* rconfineTo */, + Mask /* eventMask */); + +extern int GrabKey( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + BYTE /* this_device_mode */, + BYTE /* other_devices_mode */, + CARD16 /* modifiers */, + DeviceIntPtr /* modifier_device */, + CARD8 /* key */, + Window /* grabWindow */, + BOOL /* ownerEvents */, + Mask /* mask */); + +extern int SelectForWindow( + DeviceIntPtr /* dev */, + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + Mask /* exclusivemasks */, + Mask /* validmasks */); + +extern int AddExtensionClient ( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + int /* mskidx */); + +extern void RecalculateDeviceDeliverableEvents( + WindowPtr /* pWin */); + +extern int InputClientGone( + WindowPtr /* pWin */, + XID /* id */); + +extern int SendEvent ( + ClientPtr /* client */, + DeviceIntPtr /* d */, + Window /* dest */, + Bool /* propagate */, + xEvent * /* ev */, + Mask /* mask */, + int /* count */); + +extern int SetButtonMapping ( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* nElts */, + BYTE * /* map */); + +extern int SetModifierMapping( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + int /* len */, + int /* rlen */, + int /* numKeyPerModifier */, + KeyCode * /* inputMap */, + KeyClassPtr * /* k */); + +extern void SendDeviceMappingNotify( + CARD8 /* request, */, + KeyCode /* firstKeyCode */, + CARD8 /* count */, + DeviceIntPtr /* dev */); + +extern int ChangeKeyMapping( + ClientPtr /* client */, + DeviceIntPtr /* dev */, + unsigned /* len */, + int /* type */, + KeyCode /* firstKeyCode */, + CARD8 /* keyCodes */, + CARD8 /* keySymsPerKeyCode */, + KeySym * /* map */); + +extern void DeleteWindowFromAnyExtEvents( + WindowPtr /* pWin */, + Bool /* freeResources */); + +extern void DeleteDeviceFromAnyExtEvents( + WindowPtr /* pWin */, + DeviceIntPtr /* dev */); + +extern int MaybeSendDeviceMotionNotifyHint ( + deviceKeyButtonPointer * /* pEvents */, + Mask /* mask */); + +extern void CheckDeviceGrabAndHintWindow ( + WindowPtr /* pWin */, + int /* type */, + deviceKeyButtonPointer * /* xE */, + GrabPtr /* grab */, + ClientPtr /* client */, + Mask /* deliveryMask */); + +extern Mask DeviceEventMaskForClient( + DeviceIntPtr /* dev */, + WindowPtr /* pWin */, + ClientPtr /* client */); + +extern void MaybeStopDeviceHint( + DeviceIntPtr /* dev */, + ClientPtr /* client */); + +extern int DeviceEventSuppressForWindow( + WindowPtr /* pWin */, + ClientPtr /* client */, + Mask /* mask */, + int /* maskndx */); + +#endif /* EXEVENTS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exglobals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exglobals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/exglobals.h (revision 51223) @@ -0,0 +1,79 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/***************************************************************** + * + * Globals referenced elsewhere in the server. + * + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef EXGLOBALS_H +#define EXGLOBALS_H 1 + +extern int IReqCode; +extern int BadDevice; +extern int BadEvent; +extern int BadMode; +extern int DeviceBusy; +extern int BadClass; + +extern Mask DevicePointerMotionMask; +extern Mask DevicePointerMotionHintMask; +extern Mask DeviceFocusChangeMask; +extern Mask DeviceStateNotifyMask; +extern Mask ChangeDeviceNotifyMask; +extern Mask DeviceMappingNotifyMask; +extern Mask DeviceOwnerGrabButtonMask; +extern Mask DeviceButtonGrabMask; +extern Mask DeviceButtonMotionMask; +extern Mask PropagateMask[]; + +extern int DeviceValuator; +extern int DeviceKeyPress; +extern int DeviceKeyRelease; +extern int DeviceButtonPress; +extern int DeviceButtonRelease; +extern int DeviceMotionNotify; +extern int DeviceFocusIn; +extern int DeviceFocusOut; +extern int ProximityIn; +extern int ProximityOut; +extern int DeviceStateNotify; +extern int DeviceKeyStateNotify; +extern int DeviceButtonStateNotify; +extern int DeviceMappingNotify; +extern int ChangeDeviceNotify; + +extern int RT_INPUTCLIENT; + +#if 0 +/* FIXME: in dix */ +extern InputInfo inputInfo; +#endif + +#endif /* EXGLOBALS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extension.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extension.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extension.h (revision 51223) @@ -0,0 +1,67 @@ +/* $Xorg: extension.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/extension.h,v 1.5 2001/12/14 19:59:54 dawes Exp $ */ + +#ifndef EXTENSION_H +#define EXTENSION_H + +_XFUNCPROTOBEGIN + +extern unsigned short StandardMinorOpcode(ClientPtr /*client*/); + +extern unsigned short MinorOpcodeOfRequest(ClientPtr /*client*/); + +extern void InitExtensions(int argc, char **argv); + +extern void InitVisualWrap(void); + +extern void CloseDownExtensions(void); + +_XFUNCPROTOEND + +#endif /* EXTENSION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extinit.h (revision 51223) @@ -0,0 +1,166 @@ +/* $XFree86: xc/programs/Xserver/include/extinit.h,v 3.2 2001/08/01 00:44:58 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +/******************************************************************** + * Interface of extinit.c + */ + +#ifndef EXTINIT_H +#define EXTINIT_H + +#include "extnsionst.h" + +void +XInputExtensionInit( + void + ); + + +int +ProcIDispatch ( + ClientPtr /* client */ + ); + +int +SProcIDispatch( + ClientPtr /* client */ + ); + +void +SReplyIDispatch ( + ClientPtr /* client */, + int /* len */, + xGrabDeviceReply * /* rep */ + ); + +void +SEventIDispatch ( + xEvent * /* from */, + xEvent * /* to */ + ); + +void +SEventDeviceValuator ( + deviceValuator * /* from */, + deviceValuator * /* to */ + ); + +void +SEventFocus ( + deviceFocus * /* from */, + deviceFocus * /* to */ + ); + +void +SDeviceStateNotifyEvent ( + deviceStateNotify * /* from */, + deviceStateNotify * /* to */ + ); + +void +SDeviceKeyStateNotifyEvent ( + deviceKeyStateNotify * /* from */, + deviceKeyStateNotify * /* to */ + ); + +void +SDeviceButtonStateNotifyEvent ( + deviceButtonStateNotify * /* from */, + deviceButtonStateNotify * /* to */ + ); + +void +SChangeDeviceNotifyEvent ( + changeDeviceNotify * /* from */, + changeDeviceNotify * /* to */ + ); + +void +SDeviceMappingNotifyEvent ( + deviceMappingNotify * /* from */, + deviceMappingNotify * /* to */ + ); + +void +FixExtensionEvents ( + ExtensionEntry * /* extEntry */ + ); + +void +RestoreExtensionEvents ( + void + ); + +void +IResetProc( + ExtensionEntry * /* unused */ + ); + +void +AssignTypeAndName ( + DeviceIntPtr /* dev */, + Atom /* type */, + char * /* name */ + ); + +void +MakeDeviceTypeAtoms ( + void +); + +DeviceIntPtr +LookupDeviceIntRec ( + CARD8 /* id */ + ); + +void +SetExclusiveAccess ( + Mask /* mask */ + ); + +void +AllowPropagateSuppress ( + Mask /* mask */ + ); + +Mask +GetNextExtEventMask ( + void +); + +void +SetMaskForExtEvent( + Mask /* mask */, + int /* event */ + ); + +void +SetEventInfo( + Mask /* mask */, + int /* constant */ + ); + +#endif /* EXTINIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extnsionst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extnsionst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/extnsionst.h (revision 51223) @@ -0,0 +1,152 @@ +/* $Xorg: extnsionst.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/extnsionst.h,v 3.8 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef EXTENSIONSTRUCT_H +#define EXTENSIONSTRUCT_H + +#include "misc.h" +#include "screenint.h" +#include "extension.h" +#include "gc.h" + +typedef struct _ExtensionEntry { + int index; + void (* CloseDown)( /* called at server shutdown */ + struct _ExtensionEntry * /* extension */); + char *name; /* extension name */ + int base; /* base request number */ + int eventBase; + int eventLast; + int errorBase; + int errorLast; + int num_aliases; + char **aliases; + pointer extPrivate; + unsigned short (* MinorOpcode)( /* called for errors */ + ClientPtr /* client */); +#ifdef XCSECURITY + Bool secure; /* extension visible to untrusted clients? */ +#endif +} ExtensionEntry; + +/* + * The arguments may be different for extension event swapping functions. + * Deal with this by casting when initializing the event's EventSwapVector[] + * entries. + */ +typedef void (*EventSwapPtr) (xEvent *, xEvent *); + +extern EventSwapPtr EventSwapVector[128]; + +extern void NotImplemented ( /* FIXME: this may move to another file... */ + xEvent *, + xEvent *); + +typedef void (* ExtensionLookupProc)( +#ifdef EXTENSION_PROC_ARGS + EXTENSION_PROC_ARGS +#else + /* args no longer indeterminate */ + char *name, + GCPtr pGC +#endif +); + +typedef struct _ProcEntry { + char *name; + ExtensionLookupProc proc; +} ProcEntryRec, *ProcEntryPtr; + +typedef struct _ScreenProcEntry { + int num; + ProcEntryPtr procList; +} ScreenProcEntry; + +#define SetGCVector(pGC, VectorElement, NewRoutineAddress, Atom) \ + pGC->VectorElement = NewRoutineAddress; + +#define GetGCValue(pGC, GCElement) (pGC->GCElement) + + +extern ExtensionEntry *AddExtension( + char* /*name*/, + int /*NumEvents*/, + int /*NumErrors*/, + int (* /*MainProc*/)(ClientPtr /*client*/), + int (* /*SwappedMainProc*/)(ClientPtr /*client*/), + void (* /*CloseDownProc*/)(ExtensionEntry * /*extension*/), + unsigned short (* /*MinorOpcodeProc*/)(ClientPtr /*client*/) +); + +extern Bool AddExtensionAlias( + char* /*alias*/, + ExtensionEntry * /*extension*/); + +extern ExtensionEntry *CheckExtension(const char *extname); + +extern ExtensionLookupProc LookupProc( + char* /*name*/, + GCPtr /*pGC*/); + +extern Bool RegisterProc( + char* /*name*/, + GCPtr /*pGC*/, + ExtensionLookupProc /*proc*/); + +extern Bool RegisterScreenProc( + char* /*name*/, + ScreenPtr /*pScreen*/, + ExtensionLookupProc /*proc*/); + +extern void DeclareExtensionSecurity( + char * /*extname*/, + Bool /*secure*/); + +#endif /* EXTENSIONSTRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fastblt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fastblt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fastblt.h (revision 51223) @@ -0,0 +1,98 @@ +/* $Xorg: fastblt.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mfb/fastblt.h,v 1.4 2001/01/17 22:37:01 dawes Exp $ */ + +/* + * Fast bitblt macros for certain hardware. If your machine has an addressing + * mode of small constant + register, you'll probably want this magic specific + * code. It's 25% faster for the R2000. I haven't studied the Sparc + * instruction set, but I suspect it also has this addressing mode. Also, + * unrolling the loop by 32 is possibly excessive for mfb. The number of times + * the loop is actually looped through is pretty small. + */ + +/* + * WARNING: These macros make *a lot* of assumptions about + * the environment they are invoked in. Plenty of implicit + * arguments, lots of side effects. Don't use them casually. + */ + +#define SwitchOdd(n) case n: BodyOdd(n) +#define SwitchEven(n) case n: BodyEven(n) + +/* to allow mfb and cfb to share code... */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef BitRight +#define BitRight(a,b) SCRRIGHT(a,b) +#define BitLeft(a,b) SCRLEFT(a,b) +#endif + +#ifdef LARGE_INSTRUCTION_CACHE +#define UNROLL 8 +#define PackedLoop \ + switch (nl & (UNROLL-1)) { \ + SwitchOdd( 7) SwitchEven( 6) SwitchOdd( 5) SwitchEven( 4) \ + SwitchOdd( 3) SwitchEven( 2) SwitchOdd( 1) \ + } \ + while ((nl -= UNROLL) >= 0) { \ + LoopReset \ + BodyEven( 8) \ + BodyOdd( 7) BodyEven( 6) BodyOdd( 5) BodyEven( 4) \ + BodyOdd( 3) BodyEven( 2) BodyOdd( 1) \ + } +#else +#define UNROLL 4 +#define PackedLoop \ + switch (nl & (UNROLL-1)) { \ + SwitchOdd( 3) SwitchEven( 2) SwitchOdd( 1) \ + } \ + while ((nl -= UNROLL) >= 0) { \ + LoopReset \ + BodyEven( 4) \ + BodyOdd( 3) BodyEven( 2) BodyOdd( 1) \ + } +#endif + +#define DuffL(counter,label,body) \ + switch (counter & 3) { \ + label: \ + body \ + case 3: \ + body \ + case 2: \ + body \ + case 1: \ + body \ + case 0: \ + if ((counter -= 4) >= 0) \ + goto label; \ + } Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb.h (revision 51223) @@ -0,0 +1,2054 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fb.h,v 1.36tsi Exp $ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XdotOrg: xserver/xorg/fb/fb.h,v 1.13 2005/10/02 08:28:26 anholt Exp $ */ + +#ifndef _FB_H_ +#define _FB_H_ + +#include +#include "scrnintstr.h" +#include "pixmap.h" +#include "pixmapstr.h" +#include "region.h" +#include "gcstruct.h" +#include "colormap.h" +#include "miscstruct.h" +#include "servermd.h" +#include "windowstr.h" +#include "mi.h" +#include "migc.h" +#include "mibstore.h" +#ifdef RENDER +#include "picturestr.h" +#else +#include "picture.h" +#endif + +/* + * This single define controls the basic size of data manipulated + * by this software; it must be log2(sizeof (FbBits) * 8) + */ + +#ifndef FB_SHIFT +#define FB_SHIFT LOG2_BITMAP_PAD +#endif + +#if FB_SHIFT < LOG2_BITMAP_PAD + error FB_SHIFT must be >= LOG2_BITMAP_PAD +#endif + +#define FB_UNIT (1 << FB_SHIFT) +#define FB_HALFUNIT (1 << (FB_SHIFT-1)) +#define FB_MASK (FB_UNIT - 1) +#define FB_ALLONES ((FbBits) -1) + +#if GLYPHPADBYTES != 4 +#error "GLYPHPADBYTES must be 4" +#endif +#if GETLEFTBITS_ALIGNMENT != 1 +#error "GETLEFTBITS_ALIGNMENT must be 1" +#endif +/* whether to bother to include 24bpp support */ +#ifndef FBNO24BIT +#define FB_24BIT +#endif + +/* + * Unless otherwise instructed, fb includes code to advertise 24bpp + * windows with 32bpp image format for application compatibility + */ + +#ifdef FB_24BIT +#ifndef FBNO24_32 +#define FB_24_32BIT +#endif +#endif + +#define FB_STIP_SHIFT LOG2_BITMAP_PAD +#define FB_STIP_UNIT (1 << FB_STIP_SHIFT) +#define FB_STIP_MASK (FB_STIP_UNIT - 1) +#define FB_STIP_ALLONES ((FbStip) -1) + +#define FB_STIP_ODDSTRIDE(s) (((s) & (FB_MASK >> FB_STIP_SHIFT)) != 0) +#define FB_STIP_ODDPTR(p) ((((long) (p)) & (FB_MASK >> 3)) != 0) + +#define FbStipStrideToBitsStride(s) (((s) >> (FB_SHIFT - FB_STIP_SHIFT))) +#define FbBitsStrideToStipStride(s) (((s) << (FB_SHIFT - FB_STIP_SHIFT))) + +#define FbFullMask(n) ((n) == FB_UNIT ? FB_ALLONES : ((((FbBits) 1) << n) - 1)) + +#if FB_SHIFT == 6 +# ifdef WIN32 +typedef unsigned __int64 FbBits; +# else +# if defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || defined(_LP64) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + defined (__powerpc64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef unsigned long FbBits; +# else +typedef unsigned long long FbBits; +# endif +# endif +#endif + +#if FB_SHIFT == 5 +typedef CARD32 FbBits; +#endif + +#if FB_SHIFT == 4 +typedef CARD16 FbBits; +#endif + +#if LOG2_BITMAP_PAD == FB_SHIFT +typedef FbBits FbStip; +#else +# if LOG2_BITMAP_PAD == 5 +typedef CARD32 FbStip; +# endif +#endif + +typedef int FbStride; + + +#ifdef FB_DEBUG +extern void fbValidateDrawable(DrawablePtr d); +extern void fbInitializeDrawable(DrawablePtr d); +extern void fbSetBits (FbStip *bits, int stride, FbStip data); +#define FB_HEAD_BITS (FbStip) (0xbaadf00d) +#define FB_TAIL_BITS (FbStip) (0xbaddf0ad) +#else +#define fbValidateDrawable(d) +#define fdInitializeDrawable(d) +#endif + +#include "fbrop.h" + +#if BITMAP_BIT_ORDER == LSBFirst +#define FbScrLeft(x,n) ((x) >> (n)) +#define FbScrRight(x,n) ((x) << (n)) +/* #define FbLeftBits(x,n) ((x) & ((((FbBits) 1) << (n)) - 1)) */ +#define FbLeftStipBits(x,n) ((x) & ((((FbStip) 1) << (n)) - 1)) +#define FbStipMoveLsb(x,s,n) (FbStipRight (x,(s)-(n))) +#define FbPatternOffsetBits 0 +#else +#define FbScrLeft(x,n) ((x) << (n)) +#define FbScrRight(x,n) ((x) >> (n)) +/* #define FbLeftBits(x,n) ((x) >> (FB_UNIT - (n))) */ +#define FbLeftStipBits(x,n) ((x) >> (FB_STIP_UNIT - (n))) +#define FbStipMoveLsb(x,s,n) (x) +#define FbPatternOffsetBits (sizeof (FbBits) - 1) +#endif + +#include "micoord.h" + +#define FbStipLeft(x,n) FbScrLeft(x,n) +#define FbStipRight(x,n) FbScrRight(x,n) + +#define FbRotLeft(x,n) FbScrLeft(x,n) | (n ? FbScrRight(x,FB_UNIT-n) : 0) +#define FbRotRight(x,n) FbScrRight(x,n) | (n ? FbScrLeft(x,FB_UNIT-n) : 0) + +#define FbRotStipLeft(x,n) FbStipLeft(x,n) | (n ? FbStipRight(x,FB_STIP_UNIT-n) : 0) +#define FbRotStipRight(x,n) FbStipRight(x,n) | (n ? FbStipLeft(x,FB_STIP_UNIT-n) : 0) + +#define FbLeftMask(x) ( ((x) & FB_MASK) ? \ + FbScrRight(FB_ALLONES,(x) & FB_MASK) : 0) +#define FbRightMask(x) ( ((FB_UNIT - (x)) & FB_MASK) ? \ + FbScrLeft(FB_ALLONES,(FB_UNIT - (x)) & FB_MASK) : 0) + +#define FbLeftStipMask(x) ( ((x) & FB_STIP_MASK) ? \ + FbStipRight(FB_STIP_ALLONES,(x) & FB_STIP_MASK) : 0) +#define FbRightStipMask(x) ( ((FB_STIP_UNIT - (x)) & FB_STIP_MASK) ? \ + FbScrLeft(FB_STIP_ALLONES,(FB_STIP_UNIT - (x)) & FB_STIP_MASK) : 0) + +#define FbBitsMask(x,w) (FbScrRight(FB_ALLONES,(x) & FB_MASK) & \ + FbScrLeft(FB_ALLONES,(FB_UNIT - ((x) + (w))) & FB_MASK)) + +#define FbStipMask(x,w) (FbStipRight(FB_STIP_ALLONES,(x) & FB_STIP_MASK) & \ + FbStipLeft(FB_STIP_ALLONES,(FB_STIP_UNIT - ((x)+(w))) & FB_STIP_MASK)) + + +#define FbMaskBits(x,w,l,n,r) { \ + n = (w); \ + r = FbRightMask((x)+n); \ + l = FbLeftMask(x); \ + if (l) { \ + n -= FB_UNIT - ((x) & FB_MASK); \ + if (n < 0) { \ + n = 0; \ + l &= r; \ + r = 0; \ + } \ + } \ + n >>= FB_SHIFT; \ +} + +#ifdef FBNOPIXADDR +#define FbMaskBitsBytes(x,w,copy,l,lb,n,r,rb) FbMaskBits(x,w,l,n,r) +#define FbDoLeftMaskByteRRop(dst,lb,l,and,xor) { \ + *dst = FbDoMaskRRop(*dst,and,xor,l); \ +} +#define FbDoRightMaskByteRRop(dst,rb,r,and,xor) { \ + *dst = FbDoMaskRRop(*dst,and,xor,r); \ +} +#else + +#define FbByteMaskInvalid 0x10 + +#define FbPatternOffset(o,t) ((o) ^ (FbPatternOffsetBits & ~(sizeof (t) - 1))) + +#define FbPtrOffset(p,o,t) ((t *) ((CARD8 *) (p) + (o))) +#define FbSelectPatternPart(xor,o,t) ((xor) >> (FbPatternOffset (o,t) << 3)) +#define FbStorePart(dst,off,t,xor) (*FbPtrOffset(dst,off,t) = \ + FbSelectPart(xor,off,t)) +#ifndef FbSelectPart +#define FbSelectPart(x,o,t) FbSelectPatternPart(x,o,t) +#endif + +#define FbMaskBitsBytes(x,w,copy,l,lb,n,r,rb) { \ + n = (w); \ + lb = 0; \ + rb = 0; \ + r = FbRightMask((x)+n); \ + if (r) { \ + /* compute right byte length */ \ + if ((copy) && (((x) + n) & 7) == 0) { \ + rb = (((x) + n) & FB_MASK) >> 3; \ + } else { \ + rb = FbByteMaskInvalid; \ + } \ + } \ + l = FbLeftMask(x); \ + if (l) { \ + /* compute left byte length */ \ + if ((copy) && ((x) & 7) == 0) { \ + lb = ((x) & FB_MASK) >> 3; \ + } else { \ + lb = FbByteMaskInvalid; \ + } \ + /* subtract out the portion painted by leftMask */ \ + n -= FB_UNIT - ((x) & FB_MASK); \ + if (n < 0) { \ + if (lb != FbByteMaskInvalid) { \ + if (rb == FbByteMaskInvalid) { \ + lb = FbByteMaskInvalid; \ + } else if (rb) { \ + lb |= (rb - lb) << (FB_SHIFT - 3); \ + rb = 0; \ + } \ + } \ + n = 0; \ + l &= r; \ + r = 0; \ + }\ + } \ + n >>= FB_SHIFT; \ +} + +#if FB_SHIFT == 6 +#define FbDoLeftMaskByteRRop6Cases(dst,xor) \ + case (sizeof (FbBits) - 7) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (5 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 7) | (6 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 7): \ + FbStorePart(dst,sizeof (FbBits) - 7,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 6) | (5 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 6): \ + FbStorePart(dst,sizeof (FbBits) - 6,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 5) | (4 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 5): \ + FbStorePart(dst,sizeof (FbBits) - 5,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + break; \ + case (sizeof (FbBits) - 4) | (3 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD16,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 4): \ + FbStorePart(dst,sizeof (FbBits) - 4,CARD32,xor); \ + break; + +#define FbDoRightMaskByteRRop6Cases(dst,xor) \ + case 4: \ + FbStorePart(dst,0,CARD32,xor); \ + break; \ + case 5: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD8,xor); \ + break; \ + case 6: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD16,xor); \ + break; \ + case 7: \ + FbStorePart(dst,0,CARD32,xor); \ + FbStorePart(dst,4,CARD16,xor); \ + FbStorePart(dst,6,CARD8,xor); \ + break; +#else +#define FbDoLeftMaskByteRRop6Cases(dst,xor) +#define FbDoRightMaskByteRRop6Cases(dst,xor) +#endif + +#define FbDoLeftMaskByteRRop(dst,lb,l,and,xor) { \ + switch (lb) { \ + FbDoLeftMaskByteRRop6Cases(dst,xor) \ + case (sizeof (FbBits) - 3) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 3) | (2 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case (sizeof (FbBits) - 2) | (1 << (FB_SHIFT - 3)): \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD8,xor); \ + break; \ + case sizeof (FbBits) - 3: \ + FbStorePart(dst,sizeof (FbBits) - 3,CARD8,xor); \ + case sizeof (FbBits) - 2: \ + FbStorePart(dst,sizeof (FbBits) - 2,CARD16,xor); \ + break; \ + case sizeof (FbBits) - 1: \ + FbStorePart(dst,sizeof (FbBits) - 1,CARD8,xor); \ + break; \ + default: \ + *dst = FbDoMaskRRop(*dst, and, xor, l); \ + break; \ + } \ +} + + +#define FbDoRightMaskByteRRop(dst,rb,r,and,xor) { \ + switch (rb) { \ + case 1: \ + FbStorePart(dst,0,CARD8,xor); \ + break; \ + case 2: \ + FbStorePart(dst,0,CARD16,xor); \ + break; \ + case 3: \ + FbStorePart(dst,0,CARD16,xor); \ + FbStorePart(dst,2,CARD8,xor); \ + break; \ + FbDoRightMaskByteRRop6Cases(dst,xor) \ + default: \ + *dst = FbDoMaskRRop (*dst, and, xor, r); \ + } \ +} +#endif + +#define FbMaskStip(x,w,l,n,r) { \ + n = (w); \ + r = FbRightStipMask((x)+n); \ + l = FbLeftStipMask(x); \ + if (l) { \ + n -= FB_STIP_UNIT - ((x) & FB_STIP_MASK); \ + if (n < 0) { \ + n = 0; \ + l &= r; \ + r = 0; \ + } \ + } \ + n >>= FB_STIP_SHIFT; \ +} + +/* + * These macros are used to transparently stipple + * in copy mode; the expected usage is with 'n' constant + * so all of the conditional parts collapse into a minimal + * sequence of partial word writes + * + * 'n' is the bytemask of which bytes to store, 'a' is the address + * of the FbBits base unit, 'o' is the offset within that unit + * + * The term "lane" comes from the hardware term "byte-lane" which + */ + +#define FbLaneCase1(n,a,o) ((n) == 0x01 ? \ + (*(CARD8 *) ((a)+FbPatternOffset(o,CARD8)) = \ + fgxor) : 0) +#define FbLaneCase2(n,a,o) ((n) == 0x03 ? \ + (*(CARD16 *) ((a)+FbPatternOffset(o,CARD16)) = \ + fgxor) : \ + ((void)FbLaneCase1((n)&1,a,o), \ + FbLaneCase1((n)>>1,a,(o)+1))) +#define FbLaneCase4(n,a,o) ((n) == 0x0f ? \ + (*(CARD32 *) ((a)+FbPatternOffset(o,CARD32)) = \ + fgxor) : \ + ((void)FbLaneCase2((n)&3,a,o), \ + FbLaneCase2((n)>>2,a,(o)+2))) +#define FbLaneCase8(n,a,o) ((n) == 0x0ff ? (*(FbBits *) ((a)+(o)) = fgxor) : \ + ((void)FbLaneCase4((n)&15,a,o), \ + FbLaneCase4((n)>>4,a,(o)+4))) + +#if FB_SHIFT == 6 +#define FbLaneCase(n,a) FbLaneCase8(n,(CARD8 *) (a),0) +#endif + +#if FB_SHIFT == 5 +#define FbLaneCase(n,a) FbLaneCase4(n,(CARD8 *) (a),0) +#endif + +/* Rotate a filled pixel value to the specified alignement */ +#define FbRot24(p,b) (FbScrRight(p,b) | FbScrLeft(p,24-(b))) +#define FbRot24Stip(p,b) (FbStipRight(p,b) | FbStipLeft(p,24-(b))) + +/* step a filled pixel value to the next/previous FB_UNIT alignment */ +#define FbNext24Pix(p) (FbRot24(p,(24-FB_UNIT%24))) +#define FbPrev24Pix(p) (FbRot24(p,FB_UNIT%24)) +#define FbNext24Stip(p) (FbRot24(p,(24-FB_STIP_UNIT%24))) +#define FbPrev24Stip(p) (FbRot24(p,FB_STIP_UNIT%24)) + +/* step a rotation value to the next/previous rotation value */ +#if FB_UNIT == 64 +#define FbNext24Rot(r) ((r) == 16 ? 0 : (r) + 8) +#define FbPrev24Rot(r) ((r) == 0 ? 16 : (r) - 8) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define FbFirst24Rot(x) (((x) + 8) % 24) +#else +#define FbFirst24Rot(x) ((x) % 24) +#endif + +#endif + +#if FB_UNIT == 32 +#define FbNext24Rot(r) ((r) == 0 ? 16 : (r) - 8) +#define FbPrev24Rot(r) ((r) == 16 ? 0 : (r) + 8) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define FbFirst24Rot(x) (((x) + 16) % 24) +#else +#define FbFirst24Rot(x) ((x) % 24) +#endif +#endif + +#define FbNext24RotStip(r) ((r) == 0 ? 16 : (r) - 8) +#define FbPrev24RotStip(r) ((r) == 16 ? 0 : (r) + 8) + +/* Whether 24-bit specific code is needed for this filled pixel value */ +#define FbCheck24Pix(p) ((p) == FbNext24Pix(p)) + +/* Macros for dealing with dashing */ + +#define FbDashDeclare \ + unsigned char *__dash, *__firstDash, *__lastDash + +#define FbDashInit(pGC,pPriv,dashOffset,dashlen,even) { \ + (even) = TRUE; \ + __firstDash = (pGC)->dash; \ + __lastDash = __firstDash + (pGC)->numInDashList; \ + (dashOffset) %= (pPriv)->dashLength; \ + \ + __dash = __firstDash; \ + while ((dashOffset) >= ((dashlen) = *__dash)) \ + { \ + (dashOffset) -= (dashlen); \ + (even) = 1-(even); \ + if (++__dash == __lastDash) \ + __dash = __firstDash; \ + } \ + (dashlen) -= (dashOffset); \ +} + +#define FbDashNext(dashlen) { \ + if (++__dash == __lastDash) \ + __dash = __firstDash; \ + (dashlen) = *__dash; \ +} + +/* as numInDashList is always even, this case can skip a test */ + +#define FbDashNextEven(dashlen) { \ + (dashlen) = *++__dash; \ +} + +#define FbDashNextOdd(dashlen) FbDashNext(dashlen) + +#define FbDashStep(dashlen,even) { \ + if (!--(dashlen)) { \ + FbDashNext(dashlen); \ + (even) = 1-(even); \ + } \ +} + +/* XXX fb*PrivateIndex should be static, but it breaks the ABI */ + +extern int fbGCPrivateIndex; +extern int fbGetGCPrivateIndex(void); +#ifndef FB_NO_WINDOW_PIXMAPS +extern int fbWinPrivateIndex; +extern int fbGetWinPrivateIndex(void); +#endif +extern const GCOps fbGCOps; +extern const GCFuncs fbGCFuncs; + +#ifdef TEKX11 +#define FB_OLD_GC +#define FB_OLD_SCREEN +#endif + +#ifdef FB_OLD_SCREEN +# define FB_OLD_MISCREENINIT /* miScreenInit requires 14 args, not 13 */ +extern WindowPtr *WindowTable; +#endif + +#ifdef FB_24_32BIT +#define FB_SCREEN_PRIVATE +#endif + +#ifdef FB_SCREEN_PRIVATE +extern int fbScreenPrivateIndex; +extern int fbGetScreenPrivateIndex(void); + +/* private field of a screen */ +typedef struct { + unsigned char win32bpp; /* window bpp for 32-bpp images */ + unsigned char pix32bpp; /* pixmap bpp for 32-bpp images */ +} FbScreenPrivRec, *FbScreenPrivPtr; + +#define fbGetScreenPrivate(pScreen) ((FbScreenPrivPtr) \ + (pScreen)->devPrivates[fbGetScreenPrivateIndex()].ptr) +#endif + +/* private field of GC */ +typedef struct { +#ifdef FB_OLD_GC + unsigned char pad1; + unsigned char pad2; + unsigned char pad3; + unsigned fExpose:1; + unsigned freeCompClip:1; + PixmapPtr pRotatedPixmap; + RegionPtr pCompositeClip; +#endif + FbBits and, xor; /* reduced rop values */ + FbBits bgand, bgxor; /* for stipples */ + FbBits fg, bg, pm; /* expanded and filled */ + unsigned int dashLength; /* total of all dash elements */ + unsigned char oneRect; /* clip list is single rectangle */ + unsigned char evenStipple; /* stipple is even */ + unsigned char bpp; /* current drawable bpp */ +} FbGCPrivRec, *FbGCPrivPtr; + +#define fbGetGCPrivate(pGC) ((FbGCPrivPtr)\ + (pGC)->devPrivates[fbGetGCPrivateIndex()].ptr) + +#ifdef FB_OLD_GC +#define fbGetCompositeClip(pGC) (fbGetGCPrivate(pGC)->pCompositeClip) +#define fbGetExpose(pGC) (fbGetGCPrivate(pGC)->fExpose) +#define fbGetFreeCompClip(pGC) (fbGetGCPrivate(pGC)->freeCompClip) +#define fbGetRotatedPixmap(pGC) (fbGetGCPrivate(pGC)->pRotatedPixmap) +#else +#define fbGetCompositeClip(pGC) ((pGC)->pCompositeClip) +#define fbGetExpose(pGC) ((pGC)->fExpose) +#define fbGetFreeCompClip(pGC) ((pGC)->freeCompClip) +#define fbGetRotatedPixmap(pGC) ((pGC)->pRotatedPixmap) +#endif + +#define fbGetScreenPixmap(s) ((PixmapPtr) (s)->devPrivate) +#ifdef FB_NO_WINDOW_PIXMAPS +#define fbGetWindowPixmap(d) fbGetScreenPixmap(((DrawablePtr) (d))->pScreen) +#else +#define fbGetWindowPixmap(pWin) ((PixmapPtr)\ + ((WindowPtr) (pWin))->devPrivates[fbGetWinPrivateIndex()].ptr) +#endif + +#ifdef ROOTLESS +#define __fbPixDrawableX(pPix) ((pPix)->drawable.x) +#define __fbPixDrawableY(pPix) ((pPix)->drawable.y) +#else +#define __fbPixDrawableX(pPix) 0 +#define __fbPixDrawableY(pPix) 0 +#endif + +#ifdef COMPOSITE +#define __fbPixOffXWin(pPix) (__fbPixDrawableX(pPix) - (pPix)->screen_x) +#define __fbPixOffYWin(pPix) (__fbPixDrawableY(pPix) - (pPix)->screen_y) +#else +#define __fbPixOffXWin(pPix) (__fbPixDrawableX(pPix)) +#define __fbPixOffYWin(pPix) (__fbPixDrawableY(pPix)) +#endif +#define __fbPixOffXPix(pPix) (__fbPixDrawableX(pPix)) +#define __fbPixOffYPix(pPix) (__fbPixDrawableY(pPix)) + +#define fbGetDrawable(pDrawable, pointer, stride, bpp, xoff, yoff) { \ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) { \ + _pPix = fbGetWindowPixmap(pDrawable); \ + (xoff) = __fbPixOffXWin(_pPix); \ + (yoff) = __fbPixOffYWin(_pPix); \ + } else { \ + _pPix = (PixmapPtr) (pDrawable); \ + (xoff) = __fbPixOffXPix(_pPix); \ + (yoff) = __fbPixOffYPix(_pPix); \ + } \ + (pointer) = (FbBits *) _pPix->devPrivate.ptr; \ + (stride) = ((int) _pPix->devKind) / sizeof (FbBits); (void)(stride); \ + (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ +} + +#define fbGetStipDrawable(pDrawable, pointer, stride, bpp, xoff, yoff) { \ + PixmapPtr _pPix; \ + if ((pDrawable)->type != DRAWABLE_PIXMAP) { \ + _pPix = fbGetWindowPixmap(pDrawable); \ + (xoff) = __fbPixOffXWin(_pPix); \ + (yoff) = __fbPixOffYWin(_pPix); \ + } else { \ + _pPix = (PixmapPtr) (pDrawable); \ + (xoff) = __fbPixOffXPix(_pPix); \ + (yoff) = __fbPixOffYPix(_pPix); \ + } \ + (pointer) = (FbStip *) _pPix->devPrivate.ptr; \ + (stride) = ((int) _pPix->devKind) / sizeof (FbStip); (void)(stride); \ + (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ +} + +/* + * XFree86 empties the root BorderClip when the VT is inactive, + * here's a macro which uses that to disable GetImage and GetSpans + */ + +#define fbWindowEnabled(pWin) \ + REGION_NOTEMPTY((pWin)->drawable.pScreen, \ + &WindowTable[(pWin)->drawable.pScreen->myNum]->borderClip) + +#define fbDrawableEnabled(pDrawable) \ + ((pDrawable)->type == DRAWABLE_PIXMAP ? \ + TRUE : fbWindowEnabled((WindowPtr) pDrawable)) + +#ifdef FB_OLD_SCREEN +#define BitsPerPixel(d) (\ + ((1 << PixmapWidthPaddingInfo[d].padBytesLog2) * 8 / \ + (PixmapWidthPaddingInfo[d].padRoundUp+1))) +#endif + +#define FbPowerOfTwo(w) (((w) & ((w) - 1)) == 0) +/* + * Accelerated tiles are power of 2 width <= FB_UNIT + */ +#define FbEvenTile(w) ((w) <= FB_UNIT && FbPowerOfTwo(w)) +/* + * Accelerated stipples are power of 2 width and <= FB_UNIT/dstBpp + * with dstBpp a power of 2 as well + */ +#define FbEvenStip(w,bpp) ((w) * (bpp) <= FB_UNIT && FbPowerOfTwo(w) && FbPowerOfTwo(bpp)) + +/* + * fb24_32.c + */ +void +fb24_32GetSpans(DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart); + +void +fb24_32SetSpans (DrawablePtr pDrawable, + GCPtr pGC, + char *src, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted); + +void +fb24_32PutZImage (DrawablePtr pDrawable, + RegionPtr pClip, + int alu, + FbBits pm, + int x, + int y, + int width, + int height, + CARD8 *src, + FbStride srcStride); + +void +fb24_32GetImage (DrawablePtr pDrawable, + int x, + int y, + int w, + int h, + unsigned int format, + unsigned long planeMask, + char *d); + +void +fb24_32CopyMtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +PixmapPtr +fb24_32ReformatTile(PixmapPtr pOldTile, int bitsPerPixel); + +Bool +fb24_32CreateScreenResources(ScreenPtr pScreen); + +Bool +fb24_32ModifyPixmapHeader (PixmapPtr pPixmap, + int width, + int height, + int depth, + int bitsPerPixel, + int devKind, + pointer pPixData); + +/* + * fballpriv.c + */ +Bool +fbAllocatePrivates(ScreenPtr pScreen, int *pGCIndex); + +/* + * fbarc.c + */ + +void +fbPolyArc (DrawablePtr pDrawable, + GCPtr pGC, + int narcs, + xArc *parcs); + +/* + * fbbits.c + */ + +void +fbBresSolid8(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash8 (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots8 (FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc8 (FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph8 (FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline8 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment8 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +void +fbBresSolid16(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash16(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots16(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc16(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph16(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline16 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment16 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + + +void +fbBresSolid24(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash24(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots24(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc24(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph24(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); + +void +fbPolyline24 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment24 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + + +void +fbBresSolid32(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbBresDash32(DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbDots32(FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor); + +void +fbArc32(FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int dx, + int dy, + FbBits and, + FbBits xor); + +void +fbGlyph32(FbBits *dstLine, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int height, + int shift); +void +fbPolyline32 (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig); + +void +fbPolySegment32 (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +/* + * fbblt.c + */ +void +fbBlt (FbBits *src, + FbStride srcStride, + int srcX, + + FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp, + + Bool reverse, + Bool upsidedown); + +void +fbBlt24 (FbBits *srcLine, + FbStride srcStride, + int srcX, + + FbBits *dstLine, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + + Bool reverse, + Bool upsidedown); + +void +fbBltStip (FbStip *src, + FbStride srcStride, /* in FbStip units, not FbBits units */ + int srcX, + + FbStip *dst, + FbStride dstStride, /* in FbStip units, not FbBits units */ + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp); + +/* + * fbbltone.c + */ +void +fbBltOne (FbStip *src, + FbStride srcStride, + int srcX, + FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbBits fgand, + FbBits fbxor, + FbBits bgand, + FbBits bgxor); + +#ifdef FB_24BIT +void +fbBltOne24 (FbStip *src, + FbStride srcStride, /* FbStip units per scanline */ + int srcX, /* bit position of source */ + FbBits *dst, + FbStride dstStride, /* FbBits units per scanline */ + int dstX, /* bit position of dest */ + int dstBpp, /* bits per destination unit */ + + int width, /* width in bits of destination */ + int height, /* height in scanlines */ + + FbBits fgand, /* rrop values */ + FbBits fgxor, + FbBits bgand, + FbBits bgxor); +#endif + +void +fbBltPlane (FbBits *src, + FbStride srcStride, + int srcX, + int srcBpp, + + FbStip *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbStip fgand, + FbStip fgxor, + FbStip bgand, + FbStip bgxor, + Pixel planeMask); + +/* + * fbbstore.c + */ +void +fbSaveAreas(PixmapPtr pPixmap, + RegionPtr prgnSave, + int xorg, + int yorg, + WindowPtr pWin); + +void +fbRestoreAreas(PixmapPtr pPixmap, + RegionPtr prgnRestore, + int xorg, + int yorg, + WindowPtr pWin); + +/* + * fbcmap.c + */ +int +fbListInstalledColormaps(ScreenPtr pScreen, Colormap *pmaps); + +void +fbInstallColormap(ColormapPtr pmap); + +void +fbUninstallColormap(ColormapPtr pmap); + +void +fbResolveColor(unsigned short *pred, + unsigned short *pgreen, + unsigned short *pblue, + VisualPtr pVisual); + +Bool +fbInitializeColormap(ColormapPtr pmap); + +int +fbExpandDirectColors (ColormapPtr pmap, + int ndef, + xColorItem *indefs, + xColorItem *outdefs); + +Bool +fbCreateDefColormap(ScreenPtr pScreen); + +void +fbClearVisualTypes(void); + +Bool +fbSetVisualTypes (int depth, int visuals, int bitsPerRGB); + +Bool +fbSetVisualTypesAndMasks (int depth, int visuals, int bitsPerRGB, + Pixel redMask, Pixel greenMask, Pixel blueMask); + +Bool +fbInitVisuals (VisualPtr *visualp, + DepthPtr *depthp, + int *nvisualp, + int *ndepthp, + int *rootDepthp, + VisualID *defaultVisp, + unsigned long sizes, + int bitsPerRGB); + +/* + * fbcopy.c + */ + +typedef void (*fbCopyProc) (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pDstBox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyNtoN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopy1toN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyNto1 (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyRegion (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + RegionPtr pDstRegion, + int dx, + int dy, + fbCopyProc copyProc, + Pixel bitPlane, + void *closure); + +RegionPtr +fbDoCopy (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut, + fbCopyProc copyProc, + Pixel bitplane, + void *closure); + +RegionPtr +fbCopyArea (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut); + +RegionPtr +fbCopyPlane (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut, + unsigned long bitplane); + +/* + * fbfill.c + */ +void +fbFill (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int width, + int height); + +void +fbSolidBoxClipped (DrawablePtr pDrawable, + RegionPtr pClip, + int xa, + int ya, + int xb, + int yb, + FbBits and, + FbBits xor); + +/* + * fbfillrect.c + */ +void +fbPolyFillRect(DrawablePtr pDrawable, + GCPtr pGC, + int nrectInit, + xRectangle *prectInit); + +#define fbPolyFillArc miPolyFillArc + +#define fbFillPolygon miFillPolygon + +/* + * fbfillsp.c + */ +void +fbFillSpans (DrawablePtr pDrawable, + GCPtr pGC, + int nInit, + DDXPointPtr pptInit, + int *pwidthInit, + int fSorted); + + +/* + * fbgc.c + */ + +Bool +fbCreateGC(GCPtr pGC); + +void +fbPadPixmap (PixmapPtr pPixmap); + +void +fbValidateGC(GCPtr pGC, unsigned long changes, DrawablePtr pDrawable); + +/* + * fbgetsp.c + */ +void +fbGetSpans(DrawablePtr pDrawable, + int wMax, + DDXPointPtr ppt, + int *pwidth, + int nspans, + char *pchardstStart); + +/* + * fbglyph.c + */ + +Bool +fbGlyphIn (RegionPtr pRegion, + int x, + int y, + int width, + int height); + +void +fbPolyGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase); + +void +fbImageGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase); + +/* + * fbimage.c + */ + +void +fbPutImage (DrawablePtr pDrawable, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage); + +void +fbPutZImage (DrawablePtr pDrawable, + RegionPtr pClip, + int alu, + FbBits pm, + int x, + int y, + int width, + int height, + FbStip *src, + FbStride srcStride); + +void +fbPutXYImage (DrawablePtr pDrawable, + RegionPtr pClip, + FbBits fg, + FbBits bg, + FbBits pm, + int alu, + Bool opaque, + + int x, + int y, + int width, + int height, + + FbStip *src, + FbStride srcStride, + int srcX); + +void +fbGetImage (DrawablePtr pDrawable, + int x, + int y, + int w, + int h, + unsigned int format, + unsigned long planeMask, + char *d); +/* + * fbline.c + */ + +void +fbZeroLine (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ppt); + +void +fbZeroSegment (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSegs); + +void +fbPolyLine (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ppt); + +void +fbFixCoordModePrevious (int npt, + DDXPointPtr ppt); + +void +fbPolySegment (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg); + +#define fbPolyRectangle miPolyRectangle + +/* + * fbpict.c + */ + +Bool +fbPictureInit (ScreenPtr pScreen, + PictFormatPtr formats, + int nformats); + +/* + * fbpixmap.c + */ + +PixmapPtr +fbCreatePixmapBpp (ScreenPtr pScreen, int width, int height, int depth, int bpp); + +PixmapPtr +fbCreatePixmap (ScreenPtr pScreen, int width, int height, int depth); + +Bool +fbDestroyPixmap (PixmapPtr pPixmap); + +RegionPtr +fbPixmapToRegion(PixmapPtr pPix); + +/* + * fbpoint.c + */ + +void +fbDots (FbBits *dstOrig, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *pts, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits andOrig, + FbBits xorOrig); + +void +fbPolyPoint (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + xPoint *pptInit); + +/* + * fbpush.c + */ +void +fbPushPattern (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + + int width, + int height); + +void +fbPushFill (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + int width, + int height); + +void +fbPush1toN (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbPushImage (DrawablePtr pDrawable, + GCPtr pGC, + + FbStip *src, + FbStride srcStride, + int srcX, + + int x, + int y, + int width, + int height); + +void +fbPushPixels (GCPtr pGC, + PixmapPtr pBitmap, + DrawablePtr pDrawable, + int dx, + int dy, + int xOrg, + int yOrg); + + +/* + * fbscreen.c + */ + +Bool +fbCloseScreen (int indx, ScreenPtr pScreen); + +Bool +fbRealizeFont(ScreenPtr pScreen, FontPtr pFont); + +Bool +fbUnrealizeFont(ScreenPtr pScreen, FontPtr pFont); + +void +fbQueryBestSize (int class, + unsigned short *width, unsigned short *height, + ScreenPtr pScreen); + +#ifndef FB_OLD_SCREEN +PixmapPtr +_fbGetWindowPixmap (WindowPtr pWindow); + +void +_fbSetWindowPixmap (WindowPtr pWindow, PixmapPtr pPixmap); +#endif + +Bool +fbSetupScreen(ScreenPtr pScreen, + pointer pbits, /* pointer to screen bitmap */ + int xsize, /* in pixels */ + int ysize, + int dpix, /* dots per inch */ + int dpiy, + int width, /* pixel width of frame buffer */ + int bpp); /* bits per pixel of frame buffer */ + +Bool +fbFinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +Bool +fbScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +void +fbInitializeBackingStore (ScreenPtr pScreen); + +/* + * fbseg.c + */ +typedef void FbBres (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +FbBres fbBresSolid, fbBresDash, fbBresFill, fbBresFillDash; +/* + * fbsetsp.c + */ + +void +fbSetSpans (DrawablePtr pDrawable, + GCPtr pGC, + char *src, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted); + +FbBres * +fbSelectBres (DrawablePtr pDrawable, + GCPtr pGC); + +void +fbBres (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x, + int y, + int e, + int e1, + int e3, + int len); + +void +fbSegment (DrawablePtr pDrawable, + GCPtr pGC, + int xa, + int ya, + int xb, + int yb, + Bool drawLast, + int *dashOffset); + + +/* + * fbsolid.c + */ + +void +fbSolid (FbBits *dst, + FbStride dstStride, + int dstX, + int bpp, + + int width, + int height, + + FbBits and, + FbBits xor); + +#ifdef FB_24BIT +void +fbSolid24 (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits and, + FbBits xor); +#endif + +/* + * fbstipple.c + */ + +void +fbTransparentSpan (FbBits *dst, + FbBits stip, + FbBits fgxor, + int n); + +void +fbEvenStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipHeight, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +void +fbOddStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipWidth, + int stipHeight, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +void +fbStipple (FbBits *dst, + FbStride dstStride, + int dstX, + int dstBpp, + + int width, + int height, + + FbStip *stip, + FbStride stipStride, + int stipWidth, + int stipHeight, + Bool even, + + FbBits fgand, + FbBits fgxor, + FbBits bgand, + FbBits bgxor, + + int xRot, + int yRot); + +/* + * fbtile.c + */ + +void +fbEvenTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + int tileHeight, + + int alu, + FbBits pm, + int xRot, + int yRot); + +void +fbOddTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + FbStride tileStride, + int tileWidth, + int tileHeight, + + int alu, + FbBits pm, + int bpp, + + int xRot, + int yRot); + +void +fbTile (FbBits *dst, + FbStride dstStride, + int dstX, + + int width, + int height, + + FbBits *tile, + FbStride tileStride, + int tileWidth, + int tileHeight, + + int alu, + FbBits pm, + int bpp, + + int xRot, + int yRot); + +/* + * fbutil.c + */ +FbBits +fbReplicatePixel (Pixel p, int bpp); + +void +fbReduceRasterOp (int rop, FbBits fg, FbBits pm, FbBits *andp, FbBits *xorp); + +/* + * fbwindow.c + */ + +Bool +fbCreateWindow(WindowPtr pWin); + +Bool +fbDestroyWindow(WindowPtr pWin); + +Bool +fbMapWindow(WindowPtr pWindow); + +Bool +fbPositionWindow(WindowPtr pWin, int x, int y); + +Bool +fbUnmapWindow(WindowPtr pWindow); + +void +fbCopyWindowProc (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + BoxPtr pbox, + int nbox, + int dx, + int dy, + Bool reverse, + Bool upsidedown, + Pixel bitplane, + void *closure); + +void +fbCopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +Bool +fbChangeWindowAttributes(WindowPtr pWin, unsigned long mask); + +void +fbFillRegionSolid (DrawablePtr pDrawable, + RegionPtr pRegion, + FbBits and, + FbBits xor); + +void +fbFillRegionTiled (DrawablePtr pDrawable, + RegionPtr pRegion, + PixmapPtr pTile); + +void +fbPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + + +#endif /* _FB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb24_32.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb24_32.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fb24_32.h (revision 51223) @@ -0,0 +1,53 @@ +/* + * $XFree86$ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _FB24_32_H_ +#define _FB24_32_H_ + +Bool +fb24_32FinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +Bool +fb24_32ScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbbits.h (revision 51223) @@ -0,0 +1,962 @@ +/* + * $XFree86$ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file defines functions for drawing some primitives using + * underlying datatypes instead of masks + */ + +#define isClipped(c,ul,lr) ((((c) - (ul)) | ((lr) - (c))) & 0x80008000) + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifdef BITSMUL +#define MUL BITSMUL +#else +#define MUL 1 +#endif + +#ifdef BITSSTORE +#define STORE(b,x) BITSSTORE(b,x) +#else +#define STORE(b,x) (*(b) = (x)) +#endif + +#ifdef BITSRROP +#define RROP(b,a,x) BITSRROP(b,a,x) +#else +#define RROP(b,a,x) (*(b) = FbDoRRop (*(b), (a), (x))) +#endif + +#ifdef BITSUNIT +#define UNIT BITSUNIT +#define USE_SOLID +#else +#define UNIT BITS +#endif + +/* + * Define the following before including this file: + * + * BRESSOLID name of function for drawing a solid segment + * BRESDASH name of function for drawing a dashed segment + * DOTS name of function for drawing dots + * ARC name of function for drawing a solid arc + * BITS type of underlying unit + */ + +#ifdef BRESSOLID +void +BRESSOLID (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x1, + int y1, + int e, + int e1, + int e3, + int len) +{ + FbBits *dst; + FbStride dstStride; + int dstBpp; + int dstXoff, dstYoff; + FbGCPrivPtr pPriv = fbGetGCPrivate (pGC); + UNIT *bits; + FbStride bitsStride; + FbStride majorStep, minorStep; + BITS xor = (BITS) pPriv->xor; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bits = ((UNIT *) (dst + ((y1 + dstYoff) * dstStride))) + (x1 + dstXoff) * MUL; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + if (signdy < 0) + bitsStride = -bitsStride; + if (axis == X_AXIS) + { + majorStep = signdx * MUL; + minorStep = bitsStride; + } + else + { + majorStep = bitsStride; + minorStep = signdx * MUL; + } + while (len--) + { + STORE(bits,xor); + bits += majorStep; + e += e1; + if (e >= 0) + { + bits += minorStep; + e += e3; + } + } +} +#endif + +#ifdef BRESDASH +void +BRESDASH (DrawablePtr pDrawable, + GCPtr pGC, + int dashOffset, + int signdx, + int signdy, + int axis, + int x1, + int y1, + int e, + int e1, + int e3, + int len) +{ + FbBits *dst; + FbStride dstStride; + int dstBpp; + int dstXoff, dstYoff; + FbGCPrivPtr pPriv = fbGetGCPrivate (pGC); + UNIT *bits; + FbStride bitsStride; + FbStride majorStep, minorStep; + BITS xorfg, xorbg; + FbDashDeclare; + int dashlen; + Bool even; + Bool doOdd; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + doOdd = pGC->lineStyle == LineDoubleDash; + xorfg = (BITS) pPriv->xor; + xorbg = (BITS) pPriv->bgxor; + + FbDashInit (pGC, pPriv, dashOffset, dashlen, even); + + bits = ((UNIT *) (dst + ((y1 + dstYoff) * dstStride))) + (x1 + dstXoff) * MUL; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + if (signdy < 0) + bitsStride = -bitsStride; + if (axis == X_AXIS) + { + majorStep = signdx * MUL; + minorStep = bitsStride; + } + else + { + majorStep = bitsStride; + minorStep = signdx * MUL; + } + if (dashlen >= len) + dashlen = len; + if (doOdd) + { + if (!even) + goto doubleOdd; + for (;;) + { + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorfg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextEven(dashlen); + + if (dashlen >= len) + dashlen = len; +doubleOdd: + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorbg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextOdd(dashlen); + + if (dashlen >= len) + dashlen = len; + } + } + else + { + if (!even) + goto onOffOdd; + for (;;) + { + len -= dashlen; + while (dashlen--) + { + STORE(bits,xorfg); + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextEven (dashlen); + + if (dashlen >= len) + dashlen = len; +onOffOdd: + len -= dashlen; + while (dashlen--) + { + bits += majorStep; + if ((e += e1) >= 0) + { + e += e3; + bits += minorStep; + } + } + if (!len) + break; + + FbDashNextOdd (dashlen); + + if (dashlen >= len) + dashlen = len; + } + } +} +#endif + +#ifdef DOTS +void +DOTS (FbBits *dst, + FbStride dstStride, + int dstBpp, + BoxPtr pBox, + xPoint *ptsOrig, + int npt, + int xorg, + int yorg, + int xoff, + int yoff, + FbBits and, + FbBits xor) +{ + INT32 *pts = (INT32 *) ptsOrig; + UNIT *bits = (UNIT *) dst; + UNIT *point; + BITS bxor = (BITS) xor; + BITS band = (BITS) and; + FbStride bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + INT32 ul, lr; + INT32 pt; + + ul = coordToInt(pBox->x1 - xorg, pBox->y1 - yorg); + lr = coordToInt(pBox->x2 - xorg - 1, pBox->y2 - yorg - 1); + + bits += bitsStride * (yorg + yoff) + (xorg + xoff) * MUL; + + if (and == 0) + { + while (npt--) + { + pt = *pts++; + if (!isClipped(pt,ul,lr)) + { + point = bits + intToY(pt) * bitsStride + intToX(pt) * MUL; + STORE(point,bxor); + } + } + } + else + { + while (npt--) + { + pt = *pts++; + if (!isClipped(pt,ul,lr)) + { + point = bits + intToY(pt) * bitsStride + intToX(pt) * MUL; + RROP(point,band,bxor); + } + } + } +} +#endif + +#ifdef ARC + +#define ARCCOPY(d) STORE(d,xorBits) +#define ARCRROP(d) RROP(d,andBits,xorBits) + +void +ARC (FbBits *dst, + FbStride dstStride, + int dstBpp, + xArc *arc, + int drawX, + int drawY, + FbBits and, + FbBits xor) +{ + UNIT *bits; + FbStride bitsStride; + miZeroArcRec info; + Bool do360; + int x; + UNIT *yorgp, *yorgop; + BITS andBits, xorBits; + int yoffset, dyoffset; + int y, a, b, d, mask; + int k1, k3, dx, dy; + + bits = (UNIT *) dst; + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + andBits = (BITS) and; + xorBits = (BITS) xor; + do360 = miZeroArcSetup(arc, &info, TRUE); + yorgp = bits + ((info.yorg + drawY) * bitsStride); + yorgop = bits + ((info.yorgo + drawY) * bitsStride); + info.xorg = (info.xorg + drawX) * MUL; + info.xorgo = (info.xorgo + drawX) * MUL; + MIARCSETUP(); + yoffset = y ? bitsStride : 0; + dyoffset = 0; + mask = info.initialMask; + + if (!(arc->width & 1)) + { + if (andBits == 0) + { + if (mask & 2) + ARCCOPY(yorgp + info.xorgo); + if (mask & 8) + ARCCOPY(yorgop + info.xorgo); + } + else + { + if (mask & 2) + ARCRROP(yorgp + info.xorgo); + if (mask & 8) + ARCRROP(yorgop + info.xorgo); + } + } + if (!info.end.x || !info.end.y) + { + mask = info.end.mask; + info.end = info.altend; + } + if (do360 && (arc->width == arc->height) && !(arc->width & 1)) + { + int xoffset = bitsStride; + UNIT *yorghb = yorgp + (info.h * bitsStride) + info.xorg; + UNIT *yorgohb = yorghb - info.h * MUL; + + yorgp += info.xorg; + yorgop += info.xorg; + yorghb += info.h * MUL; + while (1) + { + if (andBits == 0) + { + ARCCOPY(yorgp + yoffset + x * MUL); + ARCCOPY(yorgp + yoffset - x * MUL); + ARCCOPY(yorgop - yoffset - x * MUL); + ARCCOPY(yorgop - yoffset + x * MUL); + } + else + { + ARCRROP(yorgp + yoffset + x * MUL); + ARCRROP(yorgp + yoffset - x * MUL); + ARCRROP(yorgop - yoffset - x * MUL); + ARCRROP(yorgop - yoffset + x * MUL); + } + if (a < 0) + break; + if (andBits == 0) + { + ARCCOPY(yorghb - xoffset - y * MUL); + ARCCOPY(yorgohb - xoffset + y * MUL); + ARCCOPY(yorgohb + xoffset + y * MUL); + ARCCOPY(yorghb + xoffset - y * MUL); + } + else + { + ARCRROP(yorghb - xoffset - y * MUL); + ARCRROP(yorgohb - xoffset + y * MUL); + ARCRROP(yorgohb + xoffset + y * MUL); + ARCRROP(yorghb + xoffset - y * MUL); + } + xoffset += bitsStride; + MIARCCIRCLESTEP(yoffset += bitsStride;); + } + yorgp -= info.xorg; + yorgop -= info.xorg; + x = info.w; + yoffset = info.h * bitsStride; + } + else if (do360) + { + while (y < info.h || x < info.w) + { + MIARCOCTANTSHIFT(dyoffset = bitsStride;); + if (andBits == 0) + { + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + else + { + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + MIARCSTEP(yoffset += dyoffset;, yoffset += bitsStride;); + } + } + else + { + while (y < info.h || x < info.w) + { + MIARCOCTANTSHIFT(dyoffset = bitsStride;); + if ((x == info.start.x) || (y == info.start.y)) + { + mask = info.start.mask; + info.start = info.altstart; + } + if (andBits == 0) + { + if (mask & 1) + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 2) + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 4) + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + else + { + if (mask & 1) + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 2) + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 4) + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + if ((x == info.end.x) || (y == info.end.y)) + { + mask = info.end.mask; + info.end = info.altend; + } + MIARCSTEP(yoffset += dyoffset;, yoffset += bitsStride;); + } + } + if ((x == info.start.x) || (y == info.start.y)) + mask = info.start.mask; + if (andBits == 0) + { + if (mask & 1) + ARCCOPY(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 4) + ARCCOPY(yorgop - yoffset + info.xorgo - x * MUL); + if (arc->height & 1) + { + if (mask & 2) + ARCCOPY(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCCOPY(yorgop - yoffset + info.xorg + x * MUL); + } + } + else + { + if (mask & 1) + ARCRROP(yorgp + yoffset + info.xorg + x * MUL); + if (mask & 4) + ARCRROP(yorgop - yoffset + info.xorgo - x * MUL); + if (arc->height & 1) + { + if (mask & 2) + ARCRROP(yorgp + yoffset + info.xorgo - x * MUL); + if (mask & 8) + ARCRROP(yorgop - yoffset + info.xorg + x * MUL); + } + } +} +#undef ARCCOPY +#undef ARCRROP +#endif + +#ifdef GLYPH +#if BITMAP_BIT_ORDER == LSBFirst +# define WRITE_ADDR1(n) (n) +# define WRITE_ADDR2(n) (n) +# define WRITE_ADDR4(n) (n) +#else +# define WRITE_ADDR1(n) ((n) ^ 3) +# define WRITE_ADDR2(n) ((n) ^ 2) +# define WRITE_ADDR4(n) ((n)) +#endif + +#define WRITE1(d,n,fg) ((d)[WRITE_ADDR1(n)] = (BITS) (fg)) + +#ifdef BITS2 +# define WRITE2(d,n,fg) (*((BITS2 *) &((d)[WRITE_ADDR2(n)])) = (BITS2) (fg)) +#else +# define WRITE2(d,n,fg) WRITE1(d,(n)+1,WRITE1(d,n,fg)) +#endif + +#ifdef BITS4 +# define WRITE4(d,n,fg) (*((BITS4 *) &((d)[WRITE_ADDR4(n)])) = (BITS4) (fg)) +#else +# define WRITE4(d,n,fg) WRITE2(d,(n)+2,WRITE2(d,n,fg)) +#endif + +void +GLYPH (FbBits *dstBits, + FbStride dstStride, + int dstBpp, + FbStip *stipple, + FbBits fg, + int x, + int height) +{ + int lshift; + FbStip bits; + BITS *dstLine; + BITS *dst; + int n; + int shift; + + dstLine = (BITS *) dstBits; + dstLine += x & ~3; + dstStride *= (sizeof (FbBits) / sizeof (BITS)); + shift = x & 3; + lshift = 4 - shift; + while (height--) + { + bits = *stipple++; + dst = (BITS *) dstLine; + n = lshift; + while (bits) + { + switch (FbStipMoveLsb (FbLeftStipBits (bits, n), 4, n)) { + case 0: + break; + case 1: + WRITE1(dst,0,fg); + break; + case 2: + WRITE1(dst,1,fg); + break; + case 3: + WRITE2(dst,0,fg); + break; + case 4: + WRITE1(dst,2,fg); + break; + case 5: + WRITE1(dst,0,fg); + WRITE1(dst,2,fg); + break; + case 6: + WRITE1(dst,1,fg); + WRITE1(dst,2,fg); + break; + case 7: + WRITE2(dst,0,fg); + WRITE1(dst,2,fg); + break; + case 8: + WRITE1(dst,3,fg); + break; + case 9: + WRITE1(dst,0,fg); + WRITE1(dst,3,fg); + break; + case 10: + WRITE1(dst,1,fg); + WRITE1(dst,3,fg); + break; + case 11: + WRITE2(dst,0,fg); + WRITE1(dst,3,fg); + break; + case 12: + WRITE2(dst,2,fg); + break; + case 13: + WRITE1(dst,0,fg); + WRITE2(dst,2,fg); + break; + case 14: + WRITE1(dst,1,fg); + WRITE2(dst,2,fg); + break; + case 15: + WRITE4(dst,0,fg); + break; + } + bits = FbStipLeft (bits, n); + n = 4; + dst += 4; + } + dstLine += dstStride; + } +} +#undef WRITE_ADDR1 +#undef WRITE_ADDR2 +#undef WRITE_ADDR4 +#undef WRITE1 +#undef WRITE2 +#undef WRITE4 + +#endif + +#ifdef POLYLINE +void +POLYLINE (DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr ptsOrig) +{ + INT32 *pts = (INT32 *) ptsOrig; + int xoff = pDrawable->x; + int yoff = pDrawable->y; + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + BoxPtr pBox = REGION_EXTENTS (pDrawable->pScreen, fbGetCompositeClip (pGC)); + + FbBits *dst; + int dstStride; + int dstBpp; + int dstXoff, dstYoff; + + UNIT *bits, *bitsBase; + FbStride bitsStride; + BITS xor = fbGetGCPrivate(pGC)->xor; + BITS and = fbGetGCPrivate(pGC)->and; + int dashoffset = 0; + + INT32 ul, lr; + INT32 pt1, pt2; + + int e, e1, e3, len; + int stepmajor, stepminor; + int octant; + + if (mode == CoordModePrevious) + fbFixCoordModePrevious (npt, ptsOrig); + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + bitsBase = ((UNIT *) dst) + (yoff + dstYoff) * bitsStride + (xoff + dstXoff) * MUL; + ul = coordToInt(pBox->x1 - xoff, pBox->y1 - yoff); + lr = coordToInt(pBox->x2 - xoff - 1, pBox->y2 - yoff - 1); + + pt1 = *pts++; + npt--; + pt2 = *pts++; + npt--; + for (;;) + { + if (isClipped (pt1, ul, lr) | isClipped (pt2, ul, lr)) + { + fbSegment (pDrawable, pGC, + intToX(pt1) + xoff, intToY(pt1) + yoff, + intToX(pt2) + xoff, intToY(pt2) + yoff, + npt == 0 && pGC->capStyle != CapNotLast, + &dashoffset); + if (!npt) + return; + pt1 = pt2; + pt2 = *pts++; + npt--; + } + else + { + bits = bitsBase + intToY(pt1) * bitsStride + intToX(pt1) * MUL; + for (;;) + { + CalcLineDeltas (intToX(pt1), intToY(pt1), + intToX(pt2), intToY(pt2), + len, e1, stepmajor, stepminor, 1, bitsStride, + octant); + stepmajor *= MUL; + if (len < e1) + { + e3 = len; + len = e1; + e1 = e3; + + e3 = stepminor; + stepminor = stepmajor; + stepmajor = e3; + SetYMajorOctant(octant); + } + e = -len; + e1 <<= 1; + e3 = e << 1; + FIXUP_ERROR (e, octant, bias); + if (and == 0) + { + while (len--) + { + STORE(bits,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + else + { + while (len--) + { + RROP(bits,and,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + if (!npt) + { + if (pGC->capStyle != CapNotLast && + pt2 != *((INT32 *) ptsOrig)) + { + RROP(bits,and,xor); + } + return; + } + pt1 = pt2; + pt2 = *pts++; + --npt; + if (isClipped (pt2, ul, lr)) + break; + } + } + } +} +#endif + +#ifdef POLYSEGMENT +void +POLYSEGMENT (DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pseg) +{ + INT32 *pts = (INT32 *) pseg; + int xoff = pDrawable->x; + int yoff = pDrawable->y; + unsigned int bias = miGetZeroLineBias(pDrawable->pScreen); + BoxPtr pBox = REGION_EXTENTS (pDrawable->pScreen, fbGetCompositeClip (pGC)); + + FbBits *dst; + int dstStride; + int dstBpp; + int dstXoff, dstYoff; + + UNIT *bits, *bitsBase; + FbStride bitsStride; + FbBits xorBits = fbGetGCPrivate(pGC)->xor; + FbBits andBits = fbGetGCPrivate(pGC)->and; + BITS xor = xorBits; + BITS and = andBits; + int dashoffset = 0; + + INT32 ul, lr; + INT32 pt1, pt2; + + int e, e1, e3, len; + int stepmajor, stepminor; + int octant; + Bool capNotLast; + + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + bitsStride = dstStride * (sizeof (FbBits) / sizeof (UNIT)); + bitsBase = ((UNIT *) dst) + (yoff + dstYoff) * bitsStride + (xoff + dstXoff) * MUL; + ul = coordToInt(pBox->x1 - xoff, pBox->y1 - yoff); + lr = coordToInt(pBox->x2 - xoff - 1, pBox->y2 - yoff - 1); + + capNotLast = pGC->capStyle == CapNotLast; + + while (nseg--) + { + pt1 = *pts++; + pt2 = *pts++; + if (isClipped (pt1, ul, lr) | isClipped (pt2, ul, lr)) + { + fbSegment (pDrawable, pGC, + intToX(pt1) + xoff, intToY(pt1) + yoff, + intToX(pt2) + xoff, intToY(pt2) + yoff, + !capNotLast, &dashoffset); + } + else + { + CalcLineDeltas (intToX(pt1), intToY(pt1), + intToX(pt2), intToY(pt2), + len, e1, stepmajor, stepminor, 1, bitsStride, + octant); + if (e1 == 0 && len > 3 +#if MUL != 1 + && FbCheck24Pix(and) && FbCheck24Pix(xor) +#endif + ) + { + int x1, x2; + FbBits *dstLine; + int dstX, width; + FbBits startmask, endmask; + int nmiddle; + + if (stepmajor < 0) + { + x1 = intToX(pt2); + x2 = intToX(pt1) + 1; + if (capNotLast) + x1++; + } + else + { + x1 = intToX(pt1); + x2 = intToX(pt2); + if (!capNotLast) + x2++; + } + dstX = (x1 + xoff + dstXoff) * (sizeof (UNIT) * 8 * MUL); + width = (x2 - x1) * (sizeof (UNIT) * 8 * MUL); + + dstLine = dst + (intToY(pt1) + yoff + dstYoff) * dstStride; + dstLine += dstX >> FB_SHIFT; + dstX &= FB_MASK; + FbMaskBits (dstX, width, startmask, nmiddle, endmask); + if (startmask) + { + *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, startmask); + dstLine++; + } + if (!andBits) + while (nmiddle--) + *dstLine++ = xorBits; + else + while (nmiddle--) + { + *dstLine = FbDoRRop (*dstLine, andBits, xorBits); + dstLine++; + } + if (endmask) + *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, endmask); + } + else + { + stepmajor *= MUL; + bits = bitsBase + intToY(pt1) * bitsStride + intToX(pt1) * MUL; + if (len < e1) + { + e3 = len; + len = e1; + e1 = e3; + + e3 = stepminor; + stepminor = stepmajor; + stepmajor = e3; + SetYMajorOctant(octant); + } + e = -len; + e1 <<= 1; + e3 = e << 1; + FIXUP_ERROR (e, octant, bias); + if (!capNotLast) + len++; + if (and == 0) + { + while (len--) + { + STORE(bits,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + else + { + while (len--) + { + RROP(bits,and,xor); + bits += stepmajor; + e += e1; + if (e >= 0) + { + bits += stepminor; + e += e3; + } + } + } + } + } + } +} +#endif + +#undef MUL +#undef STORE +#undef RROP +#undef UNIT +#undef USE_SOLID + +#undef isClipped Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbdevhw.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbdevhw.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbdevhw.h (revision 51223) @@ -0,0 +1,61 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/fbdevhw/fbdevhw.h,v 1.11 2001/10/01 13:44:12 eich Exp $ */ + +#ifndef _FBDEVHW_H_ +#define _FBDEVHW_H_ + +#include "xf86str.h" +#include "colormapst.h" + +#define FBDEVHW_PACKED_PIXELS 0 /* Packed Pixels */ +#define FBDEVHW_PLANES 1 /* Non interleaved planes */ +#define FBDEVHW_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FBDEVHW_TEXT 3 /* Text/attributes */ +#define FBDEVHW_VGA_PLANES 4 /* EGA/VGA planes */ + +Bool fbdevHWGetRec(ScrnInfoPtr pScrn); +void fbdevHWFreeRec(ScrnInfoPtr pScrn); + +Bool fbdevHWProbe(pciVideoPtr pPci, char *device, char **namep); +Bool fbdevHWInit(ScrnInfoPtr pScrn, pciVideoPtr pPci, char *device); + +char* fbdevHWGetName(ScrnInfoPtr pScrn); +int fbdevHWGetDepth(ScrnInfoPtr pScrn, int *fbbpp); +int fbdevHWGetLineLength(ScrnInfoPtr pScrn); +int fbdevHWGetType(ScrnInfoPtr pScrn); +int fbdevHWGetVidmem(ScrnInfoPtr pScrn); + +void* fbdevHWMapVidmem(ScrnInfoPtr pScrn); +int fbdevHWLinearOffset(ScrnInfoPtr pScrn); +Bool fbdevHWUnmapVidmem(ScrnInfoPtr pScrn); +void* fbdevHWMapMMIO(ScrnInfoPtr pScrn); +Bool fbdevHWUnmapMMIO(ScrnInfoPtr pScrn); + +void fbdevHWSetVideoModes(ScrnInfoPtr pScrn); +DisplayModePtr fbdevHWGetBuildinMode(ScrnInfoPtr pScrn); +void fbdevHWUseBuildinMode(ScrnInfoPtr pScrn); +Bool fbdevHWModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode); +void fbdevHWSave(ScrnInfoPtr pScrn); +void fbdevHWRestore(ScrnInfoPtr pScrn); + +void fbdevHWLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); + +ModeStatus fbdevHWValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags); +Bool fbdevHWSwitchMode(int scrnIndex, DisplayModePtr mode, int flags); +void fbdevHWAdjustFrame(int scrnIndex, int x, int y, int flags); +Bool fbdevHWEnterVT(int scrnIndex, int flags); +void fbdevHWLeaveVT(int scrnIndex, int flags); +void fbdevHWDPMSSet(ScrnInfoPtr pScrn, int mode, int flags); + +Bool fbdevHWSaveScreen(ScreenPtr pScreen, int mode); + +xf86SwitchModeProc *fbdevHWSwitchModeWeak(void); +xf86AdjustFrameProc *fbdevHWAdjustFrameWeak(void); +xf86EnterVTProc *fbdevHWEnterVTWeak(void); +xf86LeaveVTProc *fbdevHWLeaveVTWeak(void); +xf86ValidModeProc *fbdevHWValidModeWeak(void); +xf86DPMSSetProc *fbdevHWDPMSSetWeak(void); +xf86LoadPaletteProc *fbdevHWLoadPaletteWeak(void); +SaveScreenProcPtr fbdevHWSaveScreenWeak(void); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbedgeimp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbedgeimp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbedgeimp.h (revision 51223) @@ -0,0 +1,143 @@ +/* + * $Id: fbedgeimp.h,v 1.2 2005/07/01 22:43:07 daniels Exp $ + * + * Copyright © 2004 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef rasterizeSpan +#endif + +static void +rasterizeEdges (FbBits *buf, + int width, + int stride, + RenderEdge *l, + RenderEdge *r, + xFixed t, + xFixed b) +{ + xFixed y = t; + FbBits *line; + + line = buf + xFixedToInt (y) * stride; + + for (;;) + { + xFixed lx, rx; + int lxi, rxi; + + /* clip X */ + lx = l->x; + if (lx < 0) + lx = 0; + rx = r->x; + if (xFixedToInt (rx) >= width) + rx = IntToxFixed (width); + + /* Skip empty (or backwards) sections */ + if (rx > lx) + { + + /* Find pixel bounds for span */ + lxi = xFixedToInt (lx); + rxi = xFixedToInt (rx); + +#if N_BITS == 1 + { + FbBits *a = line; + FbBits startmask, endmask; + int nmiddle; + int width = rxi - lxi; + int x = lxi; + + a += x >> FB_SHIFT; + x &= FB_MASK; + + FbMaskBits (x, width, startmask, nmiddle, endmask); + if (startmask) + *a++ |= startmask; + while (nmiddle--) + *a++ = FB_ALLONES; + if (endmask) + *a |= endmask; + } +#else + { + DefineAlpha(line,lxi); + int lxs, rxs; + + /* Sample coverage for edge pixels */ + lxs = RenderSamplesX (lx, N_BITS); + rxs = RenderSamplesX (rx, N_BITS); + + /* Add coverage across row */ + if (lxi == rxi) + { + AddAlpha (rxs - lxs); + } + else + { + int xi; + + AddAlpha (N_X_FRAC(N_BITS) - lxs); + StepAlpha; + for (xi = lxi + 1; xi < rxi; xi++) + { + AddAlpha (N_X_FRAC(N_BITS)); + StepAlpha; + } + /* Do not add in a 0 alpha here. This check is necessary + * to avoid a buffer overrun when rx is exactly on a pixel + * boundary. + */ + if (rxs != 0) + AddAlpha (rxs); + } + } +#endif + } + + if (y == b) + break; + +#if N_BITS > 1 + if (xFixedFrac (y) != Y_FRAC_LAST(N_BITS)) + { + RenderEdgeStepSmall (l); + RenderEdgeStepSmall (r); + y += STEP_Y_SMALL(N_BITS); + } + else +#endif + { + RenderEdgeStepBig (l); + RenderEdgeStepBig (r); + y += STEP_Y_BIG(N_BITS); + line += stride; + } + } +} + +#undef rasterizeSpan Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbmmx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbmmx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbmmx.h (revision 51223) @@ -0,0 +1,220 @@ +/* + * Copyright © 2004 Red Hat, Inc. + * Copyright © 2005 Trolltech AS + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Red Hat not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Red Hat makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS + * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Author: Søren Sandmann (sandmann@redhat.com) + * Lars Knoll (lars@trolltech.com) + * + * Based on work by Owen Taylor + */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifdef USE_MMX + +#if !defined(__amd64__) && !defined(__x86_64__) +Bool fbHaveMMX(void); +#else +#define fbHaveMMX() TRUE +#endif + +#else +#define fbHaveMMX() FALSE +#endif + +#ifdef USE_MMX + +void fbComposeSetupMMX(void); + +void fbCompositeSolidMask_nx8888x0565Cmmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrcAdd_8888x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8888x8888Cmmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrcAdd_8000x8000mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888RevNPx8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888RevNPx0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolid_nx8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolid_nx0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSolidMask_nx8x0565mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +void fbCompositeSrc_8888x8x8888mmx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +Bool fbCopyAreammx (DrawablePtr pSrc, + DrawablePtr pDst, + int src_x, + int src_y, + int dst_x, + int dst_y, + int width, + int height); +void fbCompositeCopyAreammx (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); +Bool fbSolidFillmmx (DrawablePtr pDraw, + int x, + int y, + int width, + int height, + FbBits xor); + +#endif /* USE_MMX */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fboverlay.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fboverlay.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fboverlay.h (revision 51223) @@ -0,0 +1,129 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fboverlay.h,v 1.4tsi Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _FBOVERLAY_H_ +#define _FBOVERLAY_H_ + +extern int fbOverlayGeneration; +extern int fbOverlayScreenPrivateIndex; /* XXX should be static */ +extern int fbOverlayGetScreenPrivateIndex(void); + +#ifndef FB_OVERLAY_MAX +#define FB_OVERLAY_MAX 2 +#endif + +typedef void (*fbOverlayPaintKeyProc) (DrawablePtr, RegionPtr, CARD32, int); + +typedef struct _fbOverlayLayer { + union { + struct { + pointer pbits; + int width; + int depth; + } init; + struct { + PixmapPtr pixmap; + RegionRec region; + } run; + } u; + CARD32 key; /* special pixel value */ +} FbOverlayLayer; + +typedef struct _fbOverlayScrPriv { + int nlayers; + fbOverlayPaintKeyProc PaintKey; + fbCopyProc CopyWindow; + FbOverlayLayer layer[FB_OVERLAY_MAX]; +} FbOverlayScrPrivRec, *FbOverlayScrPrivPtr; + +#define fbOverlayGetScrPriv(s) \ + ((fbOverlayGetScreenPrivateIndex() != -1) ? \ + (s)->devPrivates[fbOverlayGetScreenPrivateIndex()].ptr : NULL) +Bool +fbOverlayCreateWindow(WindowPtr pWin); + +Bool +fbOverlayCloseScreen (int iScreen, ScreenPtr pScreen); + +int +fbOverlayWindowLayer(WindowPtr pWin); + +Bool +fbOverlayCreateScreenResources(ScreenPtr pScreen); + +void +fbOverlayPaintKey (DrawablePtr pDrawable, + RegionPtr pRegion, + CARD32 pixel, + int layer); +void +fbOverlayUpdateLayerRegion (ScreenPtr pScreen, + int layer, + RegionPtr prgn); + + +void +fbOverlayCopyWindow(WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc); + +void +fbOverlayWindowExposures (WindowPtr pWin, + RegionPtr prgn, + RegionPtr other_exposed); + +void +fbOverlayPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + + +Bool +fbOverlaySetupScreen(ScreenPtr pScreen, + pointer pbits1, + pointer pbits2, + int xsize, + int ysize, + int dpix, + int dpiy, + int width1, + int width2, + int bpp1, + int bpp2); + +Bool +fbOverlayFinishScreenInit(ScreenPtr pScreen, + pointer pbits1, + pointer pbits2, + int xsize, + int ysize, + int dpix, + int dpiy, + int width1, + int width2, + int bpp1, + int bpp2, + int depth1, + int depth2); + +#endif /* _FBOVERLAY_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpict.h (revision 51223) @@ -0,0 +1,612 @@ +/* + * $XFree86: xc/programs/Xserver/fb/fbpict.h,v 1.7 2001/07/18 10:15:02 keithp Exp $ + * + * Copyright © 2000 Keith Packard, member of The XFree86 Project, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _FBPICT_H_ +#define _FBPICT_H_ + +#include "renderedge.h" + +#define FbIntMult(a,b,t) ( (t) = (a) * (b) + 0x80, ( ( ( (t)>>8 ) + (t) )>>8 ) ) +#define FbIntDiv(a,b) (((CARD16) (a) * 255) / (b)) + +#define FbGet8(v,i) ((CARD16) (CARD8) ((v) >> i)) + +/* + * There are two ways of handling alpha -- either as a single unified value or + * a separate value for each component, hence each macro must have two + * versions. The unified alpha version has a 'U' at the end of the name, + * the component version has a 'C'. Similarly, functions which deal with + * this difference will have two versions using the same convention. + */ + +#define FbOverU(x,y,i,a,t) ((t) = FbIntMult(FbGet8(y,i),(a),(t)) + FbGet8(x,i),\ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + +#define FbOverC(x,y,i,a,t) ((t) = FbIntMult(FbGet8(y,i),FbGet8(a,i),(t)) + FbGet8(x,i),\ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + +#define FbInU(x,i,a,t) ((CARD32) FbIntMult(FbGet8(x,i),(a),(t)) << (i)) + +#define FbInC(x,i,a,t) ((CARD32) FbIntMult(FbGet8(x,i),FbGet8(a,i),(t)) << (i)) + +#define FbGen(x,y,i,ax,ay,t,u,v) ((t) = (FbIntMult(FbGet8(y,i),ay,(u)) + \ + FbIntMult(FbGet8(x,i),ax,(v))),\ + (CARD32) ((CARD8) ((t) | \ + (0 - ((t) >> 8)))) << (i)) + +#define FbAdd(x,y,i,t) ((t) = FbGet8(x,i) + FbGet8(y,i), \ + (CARD32) ((CARD8) ((t) | (0 - ((t) >> 8)))) << (i)) + + +#define Alpha(x) ((x) >> 24) +#define Red(x) (((x) >> 16) & 0xff) +#define Green(x) (((x) >> 8) & 0xff) +#define Blue(x) ((x) & 0xff) + +#define fbComposeGetSolid(pict, bits, fmt) { \ + FbBits *__bits__; \ + FbStride __stride__; \ + int __bpp__; \ + int __xoff__,__yoff__; \ +\ + fbGetDrawable((pict)->pDrawable,__bits__,__stride__,__bpp__,__xoff__,__yoff__); \ + switch (__bpp__) { \ + case 32: \ + (bits) = *(CARD32 *) __bits__; \ + break; \ + case 24: \ + (bits) = Fetch24 ((CARD8 *) __bits__); \ + break; \ + case 16: \ + (bits) = *(CARD16 *) __bits__; \ + (bits) = cvt0565to8888(bits); \ + break; \ + default: \ + return; \ + } \ + /* If necessary, convert RGB <--> BGR. */ \ + if (PICT_FORMAT_TYPE((pict)->format) != PICT_FORMAT_TYPE(fmt)) \ + { \ + (bits) = (((bits) & 0xff000000) | \ + (((bits) & 0x00ff0000) >> 16) | \ + (((bits) & 0x0000ff00) >> 0) | \ + (((bits) & 0x000000ff) << 16)); \ + } \ + /* manage missing src alpha */ \ + if ((pict)->pFormat->direct.alphaMask == 0) \ + (bits) |= 0xff000000; \ +} + +#define fbComposeGetStart(pict,x,y,type,stride,line,mul) {\ + FbBits *__bits__; \ + FbStride __stride__; \ + int __bpp__; \ + int __xoff__,__yoff__; \ +\ + fbGetDrawable((pict)->pDrawable,__bits__,__stride__,__bpp__,__xoff__,__yoff__); \ + (stride) = __stride__ * sizeof (FbBits) / sizeof (type); \ + (line) = ((type *) __bits__) + (stride) * ((y) + __yoff__) + (mul) * ((x) + __xoff__); \ +} +#define cvt8888to0565(s) ((((s) >> 3) & 0x001f) | \ + (((s) >> 5) & 0x07e0) | \ + (((s) >> 8) & 0xf800)) +#define cvt0565to8888(s) (((((s) << 3) & 0xf8) | (((s) >> 2) & 0x7)) | \ + ((((s) << 5) & 0xfc00) | (((s) >> 1) & 0x300)) | \ + ((((s) << 8) & 0xf80000) | (((s) << 3) & 0x70000))) + +#if IMAGE_BYTE_ORDER == MSBFirst +#define Fetch24(a) ((unsigned long) (a) & 1 ? \ + ((*(a) << 16) | *((CARD16 *) ((a)+1))) : \ + ((*((CARD16 *) (a)) << 8) | *((a)+2))) +#define Store24(a,v) ((unsigned long) (a) & 1 ? \ + ((*(a) = (CARD8) ((v) >> 16)), \ + (*((CARD16 *) ((a)+1)) = (CARD16) (v))) : \ + ((*((CARD16 *) (a)) = (CARD16) ((v) >> 8)), \ + (*((a)+2) = (CARD8) (v)))) +#else +#define Fetch24(a) ((unsigned long) (a) & 1 ? \ + ((*(a)) | (*((CARD16 *) ((a)+1)) << 8)) : \ + ((*((CARD16 *) (a))) | (*((a)+2) << 16))) +#define Store24(a,v) ((unsigned long) (a) & 1 ? \ + ((*(a) = (CARD8) (v)), \ + (*((CARD16 *) ((a)+1)) = (CARD16) ((v) >> 8))) : \ + ((*((CARD16 *) (a)) = (CARD16) (v)),\ + (*((a)+2) = (CARD8) ((v) >> 16)))) +#endif + +/* + The methods below use some tricks to be able to do two color + components at the same time. +*/ + +/* + x_c = (x_c * a) / 255 +*/ +#define FbByteMul(x, a) do { \ + CARD32 t = ((x & 0xff00ff) * a) + 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + \ + x = (((x >> 8) & 0xff00ff) * a) + 0x800080; \ + x = (x + ((x >> 8) & 0xff00ff)); \ + x &= 0xff00ff00; \ + x += t; \ + } while (0) + +/* + x_c = (x_c * a) / 255 + y +*/ +#define FbByteMulAdd(x, a, y) do { \ + CARD32 t = ((x & 0xff00ff) * a) + 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + t += y & 0xff00ff; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + \ + x = (((x >> 8) & 0xff00ff) * a) + 0x800080; \ + x = (x + ((x >> 8) & 0xff00ff)) >> 8; \ + x &= 0xff00ff; \ + x += (y >> 8) & 0xff00ff; \ + x |= 0x1000100 - ((x >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x <<= 8; \ + x += t; \ + } while (0) + +/* + x_c = (x_c * a + y_c * b) / 255 +*/ +#define FbByteAddMul(x, a, y, b) do { \ + CARD32 t; \ + CARD32 r = (x >> 24) * a + (y >> 24) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + t = (x & 0xff00) * a + (y & 0xff00) * b; \ + t += (t >> 8) + 0x8000; \ + t >>= 16; \ + \ + t |= r << 16; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + t <<= 8; \ + \ + r = ((x >> 16) & 0xff) * a + ((y >> 16) & 0xff) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + x = (x & 0xff) * a + (y & 0xff) * b + 0x80; \ + x += (x >> 8); \ + x >>= 8; \ + x |= r << 16; \ + x |= 0x1000100 - ((x >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x |= t; \ +} while (0) + +/* + x_c = (x_c * a + y_c *b) / 256 +*/ +#define FbByteAddMul_256(x, a, y, b) do { \ + CARD32 t = (x & 0xff00ff) * a + (y & 0xff00ff) * b; \ + t >>= 8; \ + t &= 0xff00ff; \ + \ + x = ((x >> 8) & 0xff00ff) * a + ((y >> 8) & 0xff00ff) * b; \ + x &= 0xff00ff00; \ + x += t; \ +} while (0) +/* + x_c = (x_c * a_c) / 255 +*/ +#define FbByteMulC(x, a) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff) * (a & 0xff); \ + r |= (x & 0xff0000) * ((a >> 16) & 0xff); \ + r += 0x800080; \ + r = (r + ((r >> 8) & 0xff00ff)) >> 8; \ + r &= 0xff00ff; \ + \ + x >>= 8; \ + t = (x & 0xff) * ((a >> 8) & 0xff); \ + t |= (x & 0xff0000) * (a >> 24); \ + t += 0x800080; \ + t = t + ((t >> 8) & 0xff00ff); \ + x = r | (t & 0xff00ff00); \ + \ + } while (0) + +/* + x_c = (x_c * a) / 255 + y +*/ +#define FbByteMulAddC(x, a, y) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff) * (a & 0xff); \ + r |= (x & 0xff0000) * ((a >> 16) & 0xff); \ + r += 0x800080; \ + r = (r + ((r >> 8) & 0xff00ff)) >> 8; \ + r &= 0xff00ff; \ + r += y & 0xff00ff; \ + r |= 0x1000100 - ((r >> 8) & 0xff00ff); \ + r &= 0xff00ff; \ + \ + x >>= 8; \ + t = (x & 0xff) * ((a >> 8) & 0xff); \ + t |= (x & 0xff0000) * (a >> 24); \ + t += 0x800080; \ + t = (t + ((t >> 8) & 0xff00ff)) >> 8; \ + t &= 0xff00ff; \ + t += (y >> 8) & 0xff00ff; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + x = r | (t << 8); \ + } while (0) + +/* + x_c = (x_c * a_c + y_c * b) / 255 +*/ +#define FbByteAddMulC(x, a, y, b) do { \ + CARD32 t; \ + CARD32 r = (x >> 24) * (a >> 24) + (y >> 24) * b; \ + r += (r >> 8) + 0x80; \ + r >>= 8; \ + \ + t = (x & 0xff00) * ((a >> 8) & 0xff) + (y & 0xff00) * b; \ + t += (t >> 8) + 0x8000; \ + t >>= 16; \ + \ + t |= r << 16; \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + t &= 0xff00ff; \ + t <<= 8; \ + \ + r = ((x >> 16) & 0xff) * ((a >> 16) & 0xff) + ((y >> 16) & 0xff) * b + 0x80; \ + r += (r >> 8); \ + r >>= 8; \ + \ + x = (x & 0xff) * (a & 0xff) + (y & 0xff) * b + 0x80; \ + x += (x >> 8); \ + x >>= 8; \ + x |= r << 16; \ + x |= 0x1000100 - ((x >> 8) & 0xff00ff); \ + x &= 0xff00ff; \ + x |= t; \ + } while (0) + +/* + x_c = min(x_c + y_c, 255) +*/ +#define FbByteAdd(x, y) do { \ + CARD32 t; \ + CARD32 r = (x & 0xff00ff) + (y & 0xff00ff); \ + r |= 0x1000100 - ((r >> 8) & 0xff00ff); \ + r &= 0xff00ff; \ + \ + t = ((x >> 8) & 0xff00ff) + ((y >> 8) & 0xff00ff); \ + t |= 0x1000100 - ((t >> 8) & 0xff00ff); \ + r |= (t & 0xff00ff) << 8; \ + x = r; \ + } while (0) + +#define div_255(x) (((x) + 0x80 + (((x) + 0x80) >> 8)) >> 8) + +#if defined(__i386__) && defined(__GNUC__) +#define FASTCALL __attribute__((regparm(3))) +#else +#define FASTCALL +#endif + +#if defined(__GNUC__) +#define INLINE __inline__ +#else +#define INLINE +#endif + +typedef struct _FbComposeData { + CARD8 op; + PicturePtr src; + PicturePtr mask; + PicturePtr dest; + INT16 xSrc; + INT16 ySrc; + INT16 xMask; + INT16 yMask; + INT16 xDest; + INT16 yDest; + CARD16 width; + CARD16 height; +} FbComposeData; + +typedef FASTCALL void (*CombineMaskU) (CARD32 *src, const CARD32 *mask, int width); +typedef FASTCALL void (*CombineFuncU) (CARD32 *dest, const CARD32 *src, int width); +typedef FASTCALL void (*CombineFuncC) (CARD32 *dest, CARD32 *src, CARD32 *mask, int width); + +typedef struct _FbComposeFunctions { + CombineFuncU *combineU; + CombineFuncC *combineC; + CombineMaskU combineMaskU; +} FbComposeFunctions; + +/* fbcompose.c */ + +void +fbCompositeGeneral (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +/* fbedge.c */ +void +fbRasterizeEdges (FbBits *buf, + int bpp, + int width, + int stride, + RenderEdge *l, + RenderEdge *r, + xFixed t, + xFixed b); + +/* fbpict.c */ +CARD32 +fbOver (CARD32 x, CARD32 y); + +CARD32 +fbOver24 (CARD32 x, CARD32 y); + +CARD32 +fbIn (CARD32 x, CARD8 y); + +void +fbCompositeSolidMask_nx8x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8x0888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8888x8888C (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx8888x0565C (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x0888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_8888x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrc_0565x0565 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_8000x8000 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_8888x8888 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSrcAdd_1000x1000 (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbCompositeSolidMask_nx1xn (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +fbComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +/* fbtrap.c */ + +void +fbAddTraps (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntrap, + xTrap *traps); + +void +fbRasterizeTrapezoid (PicturePtr alpha, + xTrapezoid *trap, + int x_off, + int y_off); + +void +fbAddTriangles (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntri, + xTriangle *tris); + +#endif /* _FBPICT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpriv.h (revision 51223) @@ -0,0 +1,266 @@ +/* + * copyed from from linux kernel 2.2.4 + * removed internal stuff (#ifdef __KERNEL__) + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/fbdevhw/fbpriv.h,v 1.2 2000/01/21 02:30:02 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _LINUX_FB_H +#define _LINUX_FB_H + +#include + +/* Definitions of frame buffers */ + +#define FB_MAJOR 29 + +#define FB_MODES_SHIFT 5 /* 32 modes per framebuffer */ +#define FB_NUM_MINORS 256 /* 256 Minors */ +#define FB_MAX (FB_NUM_MINORS / (1 << FB_MODES_SHIFT)) +#define GET_FB_IDX(node) (MINOR(node) >> FB_MODES_SHIFT) + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +/* 0x4607-0x460B are defined below */ +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 + +#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ +#define FB_TYPE_PLANES 1 /* Non interleaved planes */ +#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FB_TYPE_TEXT 3 /* Text/attributes */ + +#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ +#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ +#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ +#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ +#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ + +#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ +#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ +#define FB_VISUAL_TRUECOLOR 2 /* True color */ +#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ +#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ +#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ + +#define FB_ACCEL_NONE 0 /* no hardware accelerator */ +#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ +#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ +#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ +#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ +#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ +#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ +#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ +#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ +#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ +#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ +#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ +#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ +#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ +#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ +#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ +#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ +#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ +#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ +#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ +#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ +#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ +#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ +#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ +#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ +#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ +#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ +#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ +#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ +#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ +#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ + +struct fb_fix_screeninfo { + char id[16]; /* identification string eg "TT Builtin" */ + char *smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + __u32 smem_len; /* Length of frame buffer mem */ + __u32 type; /* see FB_TYPE_* */ + __u32 type_aux; /* Interleave for interleaved Planes */ + __u32 visual; /* see FB_VISUAL_* */ + __u16 xpanstep; /* zero if no hardware panning */ + __u16 ypanstep; /* zero if no hardware panning */ + __u16 ywrapstep; /* zero if no hardware ywrap */ + __u32 line_length; /* length of a line in bytes */ + char *mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + __u32 mmio_len; /* Length of Memory Mapped I/O */ + __u32 accel; /* Type of acceleration available */ + __u16 reserved[3]; /* Reserved for future compatibility */ +}; + +/* Interpretation of offset for color fields: All offsets are from the right, + * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you + * can use the offset as right argument to <<). A pixel afterwards is a bit + * stream and is written to video memory as that unmodified. This implies + * big-endian byte order if bits_per_pixel is greater than 8. + */ +struct fb_bitfield { + __u32 offset; /* beginning of bitfield */ + __u32 length; /* length of bitfield */ + __u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ + +#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ +#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ +#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ +#define FB_ACTIVATE_MASK 15 + /* values */ +#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ +#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ +#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ + +#define FB_ACCELF_TEXT 1 /* text mode acceleration */ + +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +struct fb_var_screeninfo { + __u32 xres; /* visible resolution */ + __u32 yres; + __u32 xres_virtual; /* virtual resolution */ + __u32 yres_virtual; + __u32 xoffset; /* offset from virtual to visible */ + __u32 yoffset; /* resolution */ + + __u32 bits_per_pixel; /* guess what */ + __u32 grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ + + __u32 nonstd; /* != 0 Non standard pixel format */ + + __u32 activate; /* see FB_ACTIVATE_* */ + + __u32 height; /* height of picture in mm */ + __u32 width; /* width of picture in mm */ + + __u32 accel_flags; /* acceleration flags (hints) */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + __u32 pixclock; /* pixel clock in ps (pico seconds) */ + __u32 left_margin; /* time from sync to picture */ + __u32 right_margin; /* time from picture to sync */ + __u32 upper_margin; /* time from sync to picture */ + __u32 lower_margin; + __u32 hsync_len; /* length of horizontal sync */ + __u32 vsync_len; /* length of vertical sync */ + __u32 sync; /* see FB_SYNC_* */ + __u32 vmode; /* see FB_VMODE_* */ + __u32 reserved[6]; /* Reserved for future compatibility */ +}; + +struct fb_cmap { + __u32 start; /* First entry */ + __u32 len; /* Number of entries */ + __u16 *red; /* Red values */ + __u16 *green; + __u16 *blue; + __u16 *transp; /* transparency, can be NULL */ +}; + +struct fb_con2fbmap { + __u32 console; + __u32 framebuffer; +}; + +struct fb_monspecs { + __u32 hfmin; /* hfreq lower limit (Hz) */ + __u32 hfmax; /* hfreq upper limit (Hz) */ + __u16 vfmin; /* vfreq lower limit (Hz) */ + __u16 vfmax; /* vfreq upper limit (Hz) */ + unsigned dpms : 1; /* supports DPMS */ +}; + +#if 1 + +#define FBCMD_GET_CURRENTPAR 0xDEAD0005 +#define FBCMD_SET_CURRENTPAR 0xDEAD8005 + +#endif + + +#if 1 /* Preliminary */ + + /* + * Hardware Cursor + */ + +#define FBIOGET_FCURSORINFO 0x4607 +#define FBIOGET_VCURSORINFO 0x4608 +#define FBIOPUT_VCURSORINFO 0x4609 +#define FBIOGET_CURSORSTATE 0x460A +#define FBIOPUT_CURSORSTATE 0x460B + + +struct fb_fix_cursorinfo { + __u16 crsr_width; /* width and height of the cursor in */ + __u16 crsr_height; /* pixels (zero if no cursor) */ + __u16 crsr_xsize; /* cursor size in display pixels */ + __u16 crsr_ysize; + __u16 crsr_color1; /* colormap entry for cursor color1 */ + __u16 crsr_color2; /* colormap entry for cursor color2 */ +}; + +struct fb_var_cursorinfo { + __u16 width; + __u16 height; + __u16 xspot; + __u16 yspot; + __u8 data[1]; /* field with [height][width] */ +}; + +struct fb_cursorstate { + __s16 xoffset; + __s16 yoffset; + __u16 mode; +}; + +#define FB_CURSOR_OFF 0 +#define FB_CURSOR_ON 1 +#define FB_CURSOR_FLASH 2 + +#endif /* Preliminary */ + +#endif /* _LINUX_FB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpseudocolor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpseudocolor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbpseudocolor.h (revision 51223) @@ -0,0 +1,20 @@ +#ifndef _FB_XX_H_ +# define _FB_XX_H_ + +typedef void (*xxSyncFunc)(ScreenPtr); +extern Bool xxSetup(ScreenPtr pScreen, int myDepth, + int baseDepth, char *addr, xxSyncFunc sync); +extern void xxPrintVisuals(void); + + +#endif /* _FB_XX_H_ */ + + + + + + + + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbrop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbrop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fbrop.h (revision 51223) @@ -0,0 +1,139 @@ +/* + * Id: fbrop.h,v 1.1 1999/11/02 03:54:45 keithp Exp $ + * + * Copyright © 1998 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* $XFree86: xc/programs/Xserver/fb/fbrop.h,v 1.3 2000/02/14 19:20:30 dawes Exp $ */ + +#ifndef _FBROP_H_ +#define _FBROP_H_ + +typedef struct _mergeRopBits { + FbBits ca1, cx1, ca2, cx2; +} FbMergeRopRec, *FbMergeRopPtr; + +extern const FbMergeRopRec FbMergeRopBits[16]; + +#define FbDeclareMergeRop() FbBits _ca1, _cx1, _ca2, _cx2; +#define FbDeclarePrebuiltMergeRop() FbBits _cca, _ccx; + +#define FbInitializeMergeRop(alu,pm) {\ + const FbMergeRopRec *_bits; \ + _bits = &FbMergeRopBits[alu]; \ + _ca1 = _bits->ca1 & pm; \ + _cx1 = _bits->cx1 | ~pm; \ + _ca2 = _bits->ca2 & pm; \ + _cx2 = _bits->cx2 & pm; \ +} + +#define FbDestInvarientRop(alu,pm) ((pm) == FB_ALLONES && \ + (((alu) >> 1 & 5) == ((alu) & 5))) + +#define FbDestInvarientMergeRop() (_ca1 == 0 && _cx1 == 0) + +/* AND has higher precedence than XOR */ + +#define FbDoMergeRop(src, dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (((src) & _ca2) ^ _cx2)) + +#define FbDoDestInvarientMergeRop(src) (((src) & _ca2) ^ _cx2) + +#define FbDoMaskMergeRop(src, dst, mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1) | ~(mask))) ^ ((((src) & _ca2) ^ _cx2) & (mask))) + +#define FbDoLeftMaskByteMergeRop(dst, src, lb, l) { \ + FbBits __xor = ((src) & _ca2) ^ _cx2; \ + FbDoLeftMaskByteRRop(dst,lb,l,((src) & _ca1) ^ _cx1,__xor); \ +} + +#define FbDoRightMaskByteMergeRop(dst, src, rb, r) { \ + FbBits __xor = ((src) & _ca2) ^ _cx2; \ + FbDoRightMaskByteRRop(dst,rb,r,((src) & _ca1) ^ _cx1,__xor); \ +} + +#define FbDoRRop(dst, and, xor) (((dst) & (and)) ^ (xor)) + +#define FbDoMaskRRop(dst, and, xor, mask) \ + (((dst) & ((and) | ~(mask))) ^ (xor & mask)) + +/* + * Take a single bit (0 or 1) and generate a full mask + */ +#define fbFillFromBit(b,t) (~((t) ((b) & 1)-1)) + +#define fbXorT(rop,fg,pm,t) ((((fg) & fbFillFromBit((rop) >> 1,t)) | \ + (~(fg) & fbFillFromBit((rop) >> 3,t))) & (pm)) + +#define fbAndT(rop,fg,pm,t) ((((fg) & fbFillFromBit (rop ^ (rop>>1),t)) | \ + (~(fg) & fbFillFromBit((rop>>2) ^ (rop>>3),t))) | \ + ~(pm)) + +#define fbXor(rop,fg,pm) fbXorT(rop,fg,pm,FbBits) + +#define fbAnd(rop,fg,pm) fbAndT(rop,fg,pm,FbBits) + +#define fbXorStip(rop,fg,pm) fbXorT(rop,fg,pm,FbStip) + +#define fbAndStip(rop,fg,pm) fbAndT(rop,fg,pm,FbStip) + +/* + * Stippling operations; + */ + +extern const FbBits fbStipple16Bits[256]; /* half of table */ +#define FbStipple16Bits(b) \ + (fbStipple16Bits[(b)&0xff] | fbStipple16Bits[(b) >> 8] << FB_HALFUNIT) +extern const FbBits fbStipple8Bits[256]; +extern const FbBits fbStipple4Bits[16]; +extern const FbBits fbStipple2Bits[4]; +extern const FbBits fbStipple1Bits[2]; +extern const FbBits *const fbStippleTable[]; + +#define FbStippleRRop(dst, b, fa, fx, ba, bx) \ + (FbDoRRop(dst, fa, fx) & b) | (FbDoRRop(dst, ba, bx) & ~b) + +#define FbStippleRRopMask(dst, b, fa, fx, ba, bx, m) \ + (FbDoMaskRRop(dst, fa, fx, m) & (b)) | (FbDoMaskRRop(dst, ba, bx, m) & ~(b)) + +#define FbDoLeftMaskByteStippleRRop(dst, b, fa, fx, ba, bx, lb, l) { \ + FbBits __xor = ((fx) & (b)) | ((bx) & ~(b)); \ + FbDoLeftMaskByteRRop(dst, lb, l, ((fa) & (b)) | ((ba) & ~(b)), __xor); \ +} + +#define FbDoRightMaskByteStippleRRop(dst, b, fa, fx, ba, bx, rb, r) { \ + FbBits __xor = ((fx) & (b)) | ((bx) & ~(b)); \ + FbDoRightMaskByteRRop(dst, rb, r, ((fa) & (b)) | ((ba) & ~(b)), __xor); \ +} + +#define FbOpaqueStipple(b, fg, bg) (((fg) & (b)) | ((bg) & ~(b))) + +/* + * Compute rop for using tile code for 1-bit dest stipples; modifies + * existing rop to flip depending on pixel values + */ +#define FbStipple1RopPick(alu,b) (((alu) >> (2 - (((b) & 1) << 1))) & 3) + +#define FbOpaqueStipple1Rop(alu,fg,bg) (FbStipple1RopPick(alu,fg) | \ + (FbStipple1RopPick(alu,bg) << 2)) + +#define FbStipple1Rop(alu,fg) (FbStipple1RopPick(alu,fg) | 4) + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fi1236.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fi1236.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fi1236.h (revision 51223) @@ -0,0 +1,122 @@ +#ifndef __FI1236_H__ +#define __FI1236_H__ + +#include "xf86i2c.h" + +/* why someone has defined NUM someplace else is beyoung me.. */ +#undef NUM + +typedef struct { + CARD32 fcar; /* 16 * fcar_Mhz */ + CARD32 min_freq; /* 16 * min_freq_Mhz */ + CARD32 max_freq; /* 16 * max_freq_Mhz */ + + CARD32 threshold1; /* 16 * Value_Mhz */ + CARD32 threshold2; /* 16 * Value_Mhz */ + + CARD8 band_low; + CARD8 band_mid; + CARD8 band_high; + CARD8 control; + } FI1236_parameters; + + +typedef struct { + /* what we want */ + /* all frequencies are in Mhz */ + double f_rf; /* frequency to tune to */ + double f_if1; /* first intermediate frequency */ + double f_if2; /* second intermediate frequency */ + double f_ref; /* reference frequency */ + double f_ifbw; /* bandwidth */ + double f_step; /* step */ + + /* what we compute */ + double f_lo1; + double f_lo2; + int LO1I; + int LO2I; + int SEL; + int STEP; + int NUM; + } MT2032_parameters; + +typedef struct { + I2CDevRec d; + int type; + + void* afc_source; /* The AFC source may be another chip like TDA988x */ + + int afc_delta; + CARD32 original_frequency; + Bool afc_timer_installed; + int afc_count; + int last_afc_hint; + + double video_if; + FI1236_parameters parm; + int xogc; /* for MT2032 */ + + struct { + CARD8 div1; + CARD8 div2; + CARD8 control; + CARD8 band; + CARD8 aux; /* this is for MK3 tuners */ + } tuner_data; + } FI1236Rec, *FI1236Ptr; + +#define TUNER_TYPE_FI1236 0 +#define TUNER_TYPE_FI1216 1 +#define TUNER_TYPE_TEMIC_FN5AL 2 +#define TUNER_TYPE_MT2032 3 +#define TUNER_TYPE_FI1246 4 +#define TUNER_TYPE_FI1256 5 +#define TUNER_TYPE_FI1236W 6 +#define TUNER_TYPE_FM1216ME 7 + +#define FI1236_ADDR(a) ((a)->d.SlaveAddr) + +#define FI1236_ADDR_1 0xC6 +#define FI1236_ADDR_2 0xC0 + +#define TUNER_TUNED 0 +#define TUNER_JUST_BELOW 1 +#define TUNER_JUST_ABOVE -1 +#define TUNER_OFF 4 +#define TUNER_STILL_TUNING 5 + + +FI1236Ptr Detect_FI1236(I2CBusPtr b, I2CSlaveAddr addr); +void FI1236_set_tuner_type(FI1236Ptr f, int type); +void TUNER_set_frequency(FI1236Ptr f, CARD32 frequency); +int FI1236_AFC(FI1236Ptr f); +int TUNER_get_afc_hint(FI1236Ptr f); +void fi1236_dump_status(FI1236Ptr f); + +#define FI1236SymbolsList \ + "Detect_FI1236", \ + "FI1236_set_tuner_type", \ + "TUNER_set_frequency" + +#ifdef XFree86LOADER + +#define xf86_Detect_FI1236 ((FI1236Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_FI1236")) +#define xf86_FI1236_set_tuner_type ((void (*)(FI1236Ptr, int))LoaderSymbol("FI1236_set_tuner_type")) +#define xf86_TUNER_set_frequency ((void (*)(FI1236Ptr, CARD32))LoaderSymbol("TUNER_set_frequency")) +#define xf86_FI1236_AFC ((int (*)(FI1236Ptr))LoaderSymbol("FI1236_AFC")) +#define xf86_TUNER_get_afc_hint ((int (*)(FI1236Ptr))LoaderSymbol("TUNER_get_afc_hint")) +#define xf86_fi1236_dump_status ((void (*)(FI1236Ptr))LoaderSymbol("fi1236_dump_status")) + +#else + +#define xf86_Detect_FI1236 Detect_FI1236 +#define xf86_FI1236_set_tuner_type FI1236_set_tuner_type +#define xf86_TUNER_set_frequency TUNER_set_frequency +#define xf86_FI1236_AFC FI1236_AFC +#define xf86_TUNER_get_afc_hint TUNER_get_afc_hint +#define xf86_fi1236_dump_status fi1236_dump_status + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fourcc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fourcc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fourcc.h (revision 51223) @@ -0,0 +1,161 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/fourcc.h,v 1.5 2003/08/24 17:36:48 dawes Exp $ */ + +/* + * Copyright (c) 2000-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + This header file contains listings of STANDARD guids for video formats. + Please do not place non-registered, or incomplete entries in this file. + A list of some popular fourcc's are at: http://www.webartz.com/fourcc/ + For an explanation of fourcc <-> guid mappings see RFC2361. +*/ + +#ifndef _XF86_FOURCC_H_ +#define _XF86_FOURCC_H_ 1 + +#define FOURCC_YUY2 0x32595559 +#define XVIMAGE_YUY2 \ + { \ + FOURCC_YUY2, \ + XvYUV, \ + LSBFirst, \ + {'Y','U','Y','2', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'Y','U','Y','V', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_YV12 0x32315659 +#define XVIMAGE_YV12 \ + { \ + FOURCC_YV12, \ + XvYUV, \ + LSBFirst, \ + {'Y','V','1','2', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 12, \ + XvPlanar, \ + 3, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 2, 2, \ + {'Y','V','U', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_I420 0x30323449 +#define XVIMAGE_I420 \ + { \ + FOURCC_I420, \ + XvYUV, \ + LSBFirst, \ + {'I','4','2','0', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 12, \ + XvPlanar, \ + 3, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 2, 2, \ + {'Y','U','V', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + + +#define FOURCC_UYVY 0x59565955 +#define XVIMAGE_UYVY \ + { \ + FOURCC_UYVY, \ + XvYUV, \ + LSBFirst, \ + {'U','Y','V','Y', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'U','Y','V','Y', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_IA44 0x34344149 +#define XVIMAGE_IA44 \ + { \ + FOURCC_IA44, \ + XvYUV, \ + LSBFirst, \ + {'I','A','4','4', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 1, 1, \ + 1, 1, 1, \ + {'A','I', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_AI44 0x34344941 +#define XVIMAGE_AI44 \ + { \ + FOURCC_AI44, \ + XvYUV, \ + LSBFirst, \ + {'A','I','4','4', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 1, 1, \ + 1, 1, 1, \ + {'I','A', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#endif /* _XF86_FOURCC_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu.h (revision 51223) @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu_regs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu_regs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/fpu_regs.h (revision 51223) @@ -0,0 +1,119 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#ifdef PACK +# pragma PACK +#endif + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab.h (revision 51223) @@ -0,0 +1,676 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/g_disptab.h,v 1.3 2001/03/21 16:29:35 dawes Exp $ */ +/* DO NOT EDIT - THIS FILE IS AUTOMATICALLY GENERATED */ +#ifndef _GLX_g_disptab_h_ +#define _GLX_g_disptab_h_ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: This software was created using the +** OpenGL(R) version 1.2.1 Sample Implementation published by SGI, but has +** not been independently verified as being compliant with the OpenGL(R) +** version 1.2.1 Specification. +*/ + +extern int __glXRender(__GLXclientState*, GLbyte*); +extern int __glXRenderLarge(__GLXclientState*, GLbyte*); +extern int __glXSendLargeCommand(__GLXclientState *cl, GLXContextTag contextTag); +extern int __glXCreateContext(__GLXclientState*, GLbyte*); +extern int __glXCreateNewContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyContext(__GLXclientState*, GLbyte*); +extern int __glXMakeCurrent(__GLXclientState*, GLbyte*); +extern int __glXMakeContextCurrent(__GLXclientState*, GLbyte*); +extern int __glXCreatePbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyPbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXGetDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXChangeDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXIsDirect(__GLXclientState*, GLbyte*); +extern int __glXQueryVersion(__GLXclientState*, GLbyte*); +extern int __glXWaitGL(__GLXclientState*, GLbyte*); +extern int __glXWaitX(__GLXclientState*, GLbyte*); +extern int __glXCopyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapBuffers(__GLXclientState*, GLbyte*); +extern int __glXUseXFont(__GLXclientState*, GLbyte*); +extern int __glXCreateGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXCreatePixmap(__GLXclientState *cl, GLbyte *pc); +extern int __glXGetVisualConfigs(__GLXclientState*, GLbyte*); +extern int __glXDestroyGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXVendorPrivate(__GLXclientState*, GLbyte*); +extern int __glXVendorPrivateWithReply(__GLXclientState*, GLbyte*); +extern int __glXQueryExtensionsString(__GLXclientState*, GLbyte*); +extern int __glXQueryServerString(__GLXclientState*, GLbyte*); +extern int __glXClientInfo(__GLXclientState*, GLbyte*); +extern int __glXGetFBConfigs(__GLXclientState*, GLbyte*); +extern int __glXCreateWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXDestroyWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXQueryContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDisp_NewList(__GLXclientState*, GLbyte*); +extern int __glXDisp_EndList(__GLXclientState*, GLbyte*); +extern int __glXDisp_DeleteLists(__GLXclientState*, GLbyte*); +extern int __glXDisp_GenLists(__GLXclientState*, GLbyte*); +extern int __glXDisp_FeedbackBuffer(__GLXclientState*, GLbyte*); +extern int __glXDisp_SelectBuffer(__GLXclientState*, GLbyte*); +extern int __glXDisp_RenderMode(__GLXclientState*, GLbyte*); +extern int __glXDisp_Finish(__GLXclientState*, GLbyte*); +extern int __glXDisp_PixelStoref(__GLXclientState*, GLbyte*); +extern int __glXDisp_PixelStorei(__GLXclientState*, GLbyte*); +extern int __glXDisp_ReadPixels(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetBooleanv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetClipPlane(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetDoublev(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetError(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetFloatv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetIntegerv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetLightfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetLightiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapdv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMapiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMaterialfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMaterialiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapuiv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPixelMapusv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetPolygonStipple(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetString(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexEnvfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexEnviv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGendv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGenfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexGeniv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexImage(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexLevelParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetTexLevelParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsEnabled(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsList(__GLXclientState*, GLbyte*); +extern int __glXDisp_Flush(__GLXclientState*, GLbyte*); +extern int __glXDisp_AreTexturesResident(__GLXclientState*, GLbyte*); +extern int __glXDisp_DeleteTextures(__GLXclientState*, GLbyte*); +extern int __glXDisp_GenTextures(__GLXclientState*, GLbyte*); +extern int __glXDisp_IsTexture(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTable(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTableParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetColorTableParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionFilter(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetConvolutionParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetSeparableFilter(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogram(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogramParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetHistogramParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmax(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmaxParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDisp_GetMinmaxParameteriv(__GLXclientState*, GLbyte*); + +extern void __glXDisp_CallList(GLbyte*); +extern void __glXDisp_CallLists(GLbyte*); +extern void __glXDisp_ListBase(GLbyte*); +extern void __glXDisp_Begin(GLbyte*); +extern void __glXDisp_Bitmap(GLbyte*); +extern void __glXDisp_Color3bv(GLbyte*); +extern void __glXDisp_Color3dv(GLbyte*); +extern void __glXDisp_Color3fv(GLbyte*); +extern void __glXDisp_Color3iv(GLbyte*); +extern void __glXDisp_Color3sv(GLbyte*); +extern void __glXDisp_Color3ubv(GLbyte*); +extern void __glXDisp_Color3uiv(GLbyte*); +extern void __glXDisp_Color3usv(GLbyte*); +extern void __glXDisp_Color4bv(GLbyte*); +extern void __glXDisp_Color4dv(GLbyte*); +extern void __glXDisp_Color4fv(GLbyte*); +extern void __glXDisp_Color4iv(GLbyte*); +extern void __glXDisp_Color4sv(GLbyte*); +extern void __glXDisp_Color4ubv(GLbyte*); +extern void __glXDisp_Color4uiv(GLbyte*); +extern void __glXDisp_Color4usv(GLbyte*); +extern void __glXDisp_EdgeFlagv(GLbyte*); +extern void __glXDisp_End(GLbyte*); +extern void __glXDisp_Indexdv(GLbyte*); +extern void __glXDisp_Indexfv(GLbyte*); +extern void __glXDisp_Indexiv(GLbyte*); +extern void __glXDisp_Indexsv(GLbyte*); +extern void __glXDisp_Normal3bv(GLbyte*); +extern void __glXDisp_Normal3dv(GLbyte*); +extern void __glXDisp_Normal3fv(GLbyte*); +extern void __glXDisp_Normal3iv(GLbyte*); +extern void __glXDisp_Normal3sv(GLbyte*); +extern void __glXDisp_RasterPos2dv(GLbyte*); +extern void __glXDisp_RasterPos2fv(GLbyte*); +extern void __glXDisp_RasterPos2iv(GLbyte*); +extern void __glXDisp_RasterPos2sv(GLbyte*); +extern void __glXDisp_RasterPos3dv(GLbyte*); +extern void __glXDisp_RasterPos3fv(GLbyte*); +extern void __glXDisp_RasterPos3iv(GLbyte*); +extern void __glXDisp_RasterPos3sv(GLbyte*); +extern void __glXDisp_RasterPos4dv(GLbyte*); +extern void __glXDisp_RasterPos4fv(GLbyte*); +extern void __glXDisp_RasterPos4iv(GLbyte*); +extern void __glXDisp_RasterPos4sv(GLbyte*); +extern void __glXDisp_Rectdv(GLbyte*); +extern void __glXDisp_Rectfv(GLbyte*); +extern void __glXDisp_Rectiv(GLbyte*); +extern void __glXDisp_Rectsv(GLbyte*); +extern void __glXDisp_TexCoord1dv(GLbyte*); +extern void __glXDisp_TexCoord1fv(GLbyte*); +extern void __glXDisp_TexCoord1iv(GLbyte*); +extern void __glXDisp_TexCoord1sv(GLbyte*); +extern void __glXDisp_TexCoord2dv(GLbyte*); +extern void __glXDisp_TexCoord2fv(GLbyte*); +extern void __glXDisp_TexCoord2iv(GLbyte*); +extern void __glXDisp_TexCoord2sv(GLbyte*); +extern void __glXDisp_TexCoord3dv(GLbyte*); +extern void __glXDisp_TexCoord3fv(GLbyte*); +extern void __glXDisp_TexCoord3iv(GLbyte*); +extern void __glXDisp_TexCoord3sv(GLbyte*); +extern void __glXDisp_TexCoord4dv(GLbyte*); +extern void __glXDisp_TexCoord4fv(GLbyte*); +extern void __glXDisp_TexCoord4iv(GLbyte*); +extern void __glXDisp_TexCoord4sv(GLbyte*); +extern void __glXDisp_Vertex2dv(GLbyte*); +extern void __glXDisp_Vertex2fv(GLbyte*); +extern void __glXDisp_Vertex2iv(GLbyte*); +extern void __glXDisp_Vertex2sv(GLbyte*); +extern void __glXDisp_Vertex3dv(GLbyte*); +extern void __glXDisp_Vertex3fv(GLbyte*); +extern void __glXDisp_Vertex3iv(GLbyte*); +extern void __glXDisp_Vertex3sv(GLbyte*); +extern void __glXDisp_Vertex4dv(GLbyte*); +extern void __glXDisp_Vertex4fv(GLbyte*); +extern void __glXDisp_Vertex4iv(GLbyte*); +extern void __glXDisp_Vertex4sv(GLbyte*); +extern void __glXDisp_ClipPlane(GLbyte*); +extern void __glXDisp_ColorMaterial(GLbyte*); +extern void __glXDisp_CullFace(GLbyte*); +extern void __glXDisp_Fogf(GLbyte*); +extern void __glXDisp_Fogfv(GLbyte*); +extern void __glXDisp_Fogi(GLbyte*); +extern void __glXDisp_Fogiv(GLbyte*); +extern void __glXDisp_FrontFace(GLbyte*); +extern void __glXDisp_Hint(GLbyte*); +extern void __glXDisp_Lightf(GLbyte*); +extern void __glXDisp_Lightfv(GLbyte*); +extern void __glXDisp_Lighti(GLbyte*); +extern void __glXDisp_Lightiv(GLbyte*); +extern void __glXDisp_LightModelf(GLbyte*); +extern void __glXDisp_LightModelfv(GLbyte*); +extern void __glXDisp_LightModeli(GLbyte*); +extern void __glXDisp_LightModeliv(GLbyte*); +extern void __glXDisp_LineStipple(GLbyte*); +extern void __glXDisp_LineWidth(GLbyte*); +extern void __glXDisp_Materialf(GLbyte*); +extern void __glXDisp_Materialfv(GLbyte*); +extern void __glXDisp_Materiali(GLbyte*); +extern void __glXDisp_Materialiv(GLbyte*); +extern void __glXDisp_PointSize(GLbyte*); +extern void __glXDisp_PolygonMode(GLbyte*); +extern void __glXDisp_PolygonStipple(GLbyte*); +extern void __glXDisp_Scissor(GLbyte*); +extern void __glXDisp_ShadeModel(GLbyte*); +extern void __glXDisp_TexParameterf(GLbyte*); +extern void __glXDisp_TexParameterfv(GLbyte*); +extern void __glXDisp_TexParameteri(GLbyte*); +extern void __glXDisp_TexParameteriv(GLbyte*); +extern void __glXDisp_TexImage1D(GLbyte*); +extern void __glXDisp_TexImage2D(GLbyte*); +extern void __glXDisp_TexEnvf(GLbyte*); +extern void __glXDisp_TexEnvfv(GLbyte*); +extern void __glXDisp_TexEnvi(GLbyte*); +extern void __glXDisp_TexEnviv(GLbyte*); +extern void __glXDisp_TexGend(GLbyte*); +extern void __glXDisp_TexGendv(GLbyte*); +extern void __glXDisp_TexGenf(GLbyte*); +extern void __glXDisp_TexGenfv(GLbyte*); +extern void __glXDisp_TexGeni(GLbyte*); +extern void __glXDisp_TexGeniv(GLbyte*); +extern void __glXDisp_InitNames(GLbyte*); +extern void __glXDisp_LoadName(GLbyte*); +extern void __glXDisp_PassThrough(GLbyte*); +extern void __glXDisp_PopName(GLbyte*); +extern void __glXDisp_PushName(GLbyte*); +extern void __glXDisp_DrawBuffer(GLbyte*); +extern void __glXDisp_Clear(GLbyte*); +extern void __glXDisp_ClearAccum(GLbyte*); +extern void __glXDisp_ClearIndex(GLbyte*); +extern void __glXDisp_ClearColor(GLbyte*); +extern void __glXDisp_ClearStencil(GLbyte*); +extern void __glXDisp_ClearDepth(GLbyte*); +extern void __glXDisp_StencilMask(GLbyte*); +extern void __glXDisp_ColorMask(GLbyte*); +extern void __glXDisp_DepthMask(GLbyte*); +extern void __glXDisp_IndexMask(GLbyte*); +extern void __glXDisp_Accum(GLbyte*); +extern void __glXDisp_Disable(GLbyte*); +extern void __glXDisp_Enable(GLbyte*); +extern void __glXDisp_PopAttrib(GLbyte*); +extern void __glXDisp_PushAttrib(GLbyte*); +extern void __glXDisp_Map1d(GLbyte*); +extern void __glXDisp_Map1f(GLbyte*); +extern void __glXDisp_Map2d(GLbyte*); +extern void __glXDisp_Map2f(GLbyte*); +extern void __glXDisp_MapGrid1d(GLbyte*); +extern void __glXDisp_MapGrid1f(GLbyte*); +extern void __glXDisp_MapGrid2d(GLbyte*); +extern void __glXDisp_MapGrid2f(GLbyte*); +extern void __glXDisp_EvalCoord1dv(GLbyte*); +extern void __glXDisp_EvalCoord1fv(GLbyte*); +extern void __glXDisp_EvalCoord2dv(GLbyte*); +extern void __glXDisp_EvalCoord2fv(GLbyte*); +extern void __glXDisp_EvalMesh1(GLbyte*); +extern void __glXDisp_EvalPoint1(GLbyte*); +extern void __glXDisp_EvalMesh2(GLbyte*); +extern void __glXDisp_EvalPoint2(GLbyte*); +extern void __glXDisp_AlphaFunc(GLbyte*); +extern void __glXDisp_BlendFunc(GLbyte*); +extern void __glXDisp_LogicOp(GLbyte*); +extern void __glXDisp_StencilFunc(GLbyte*); +extern void __glXDisp_StencilOp(GLbyte*); +extern void __glXDisp_DepthFunc(GLbyte*); +extern void __glXDisp_PixelZoom(GLbyte*); +extern void __glXDisp_PixelTransferf(GLbyte*); +extern void __glXDisp_PixelTransferi(GLbyte*); +extern void __glXDisp_PixelMapfv(GLbyte*); +extern void __glXDisp_PixelMapuiv(GLbyte*); +extern void __glXDisp_PixelMapusv(GLbyte*); +extern void __glXDisp_ReadBuffer(GLbyte*); +extern void __glXDisp_CopyPixels(GLbyte*); +extern void __glXDisp_DrawPixels(GLbyte*); +extern void __glXDisp_DepthRange(GLbyte*); +extern void __glXDisp_Frustum(GLbyte*); +extern void __glXDisp_LoadIdentity(GLbyte*); +extern void __glXDisp_LoadMatrixf(GLbyte*); +extern void __glXDisp_LoadMatrixd(GLbyte*); +extern void __glXDisp_MatrixMode(GLbyte*); +extern void __glXDisp_MultMatrixf(GLbyte*); +extern void __glXDisp_MultMatrixd(GLbyte*); +extern void __glXDisp_Ortho(GLbyte*); +extern void __glXDisp_PopMatrix(GLbyte*); +extern void __glXDisp_PushMatrix(GLbyte*); +extern void __glXDisp_Rotated(GLbyte*); +extern void __glXDisp_Rotatef(GLbyte*); +extern void __glXDisp_Scaled(GLbyte*); +extern void __glXDisp_Scalef(GLbyte*); +extern void __glXDisp_Translated(GLbyte*); +extern void __glXDisp_Translatef(GLbyte*); +extern void __glXDisp_Viewport(GLbyte*); +extern void __glXDisp_PolygonOffset(GLbyte*); +extern void __glXDisp_DrawArrays(GLbyte*); +extern void __glXDisp_Indexubv(GLbyte*); +extern void __glXDisp_ColorSubTable(GLbyte*); +extern void __glXDisp_CopyColorSubTable(GLbyte*); +extern void __glXDisp_ActiveTextureARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord1svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord2svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord3svARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4dvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4fvARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4ivARB(GLbyte*); +extern void __glXDisp_MultiTexCoord4svARB(GLbyte*); + +extern int __glXSwapRender(__GLXclientState*, GLbyte*); +extern int __glXSwapRenderLarge(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateContext(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateNewContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapMakeCurrent(__GLXclientState*, GLbyte*); +extern int __glXSwapMakeContextCurrent(__GLXclientState*, GLbyte*); +extern int __glXSwapCreatePbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyPbuffer(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapGetDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapChangeDrawableAttributes(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapIsDirect(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryVersion(__GLXclientState*, GLbyte*); +extern int __glXSwapWaitGL(__GLXclientState*, GLbyte*); +extern int __glXSwapWaitX(__GLXclientState*, GLbyte*); +extern int __glXSwapCopyContext(__GLXclientState*, GLbyte*); +extern int __glXSwapSwapBuffers(__GLXclientState*, GLbyte*); +extern int __glXSwapUseXFont(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXSwapCreatePixmap(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapGetVisualConfigs(__GLXclientState*, GLbyte*); +extern int __glXSwapDestroyGLXPixmap(__GLXclientState*, GLbyte*); +extern int __glXSwapVendorPrivate(__GLXclientState*, GLbyte*); +extern int __glXSwapVendorPrivateWithReply(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryExtensionsString(__GLXclientState*, GLbyte*); +extern int __glXSwapQueryServerString(__GLXclientState*, GLbyte*); +extern int __glXSwapClientInfo(__GLXclientState*, GLbyte*); +extern int __glXSwapGetFBConfigs(__GLXclientState*, GLbyte*); +extern int __glXSwapCreateWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapDestroyWindow(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapQueryContext(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_NewList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_EndList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_DeleteLists(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GenLists(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_FeedbackBuffer(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_SelectBuffer(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_RenderMode(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_Finish(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_PixelStoref(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_PixelStorei(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_ReadPixels(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetBooleanv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetClipPlane(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetDoublev(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetError(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetFloatv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetIntegerv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetLightfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetLightiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapdv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMapiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMaterialfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMaterialiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapuiv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPixelMapusv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetPolygonStipple(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetString(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexEnvfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexEnviv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGendv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGenfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexGeniv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexImage(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexLevelParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetTexLevelParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsEnabled(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsList(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_Flush(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_AreTexturesResident(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_DeleteTextures(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GenTextures(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_IsTexture(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTable(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTableParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetColorTableParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionFilter(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetConvolutionParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetSeparableFilter(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogram(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogramParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetHistogramParameteriv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmax(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmaxParameterfv(__GLXclientState*, GLbyte*); +extern int __glXDispSwap_GetMinmaxParameteriv(__GLXclientState*, GLbyte*); + +extern void __glXDispSwap_CallList(GLbyte*); +extern void __glXDispSwap_CallLists(GLbyte*); +extern void __glXDispSwap_ListBase(GLbyte*); +extern void __glXDispSwap_Begin(GLbyte*); +extern void __glXDispSwap_Bitmap(GLbyte*); +extern void __glXDispSwap_Color3bv(GLbyte*); +extern void __glXDispSwap_Color3dv(GLbyte*); +extern void __glXDispSwap_Color3fv(GLbyte*); +extern void __glXDispSwap_Color3iv(GLbyte*); +extern void __glXDispSwap_Color3sv(GLbyte*); +extern void __glXDispSwap_Color3ubv(GLbyte*); +extern void __glXDispSwap_Color3uiv(GLbyte*); +extern void __glXDispSwap_Color3usv(GLbyte*); +extern void __glXDispSwap_Color4bv(GLbyte*); +extern void __glXDispSwap_Color4dv(GLbyte*); +extern void __glXDispSwap_Color4fv(GLbyte*); +extern void __glXDispSwap_Color4iv(GLbyte*); +extern void __glXDispSwap_Color4sv(GLbyte*); +extern void __glXDispSwap_Color4ubv(GLbyte*); +extern void __glXDispSwap_Color4uiv(GLbyte*); +extern void __glXDispSwap_Color4usv(GLbyte*); +extern void __glXDispSwap_EdgeFlagv(GLbyte*); +extern void __glXDispSwap_End(GLbyte*); +extern void __glXDispSwap_Indexdv(GLbyte*); +extern void __glXDispSwap_Indexfv(GLbyte*); +extern void __glXDispSwap_Indexiv(GLbyte*); +extern void __glXDispSwap_Indexsv(GLbyte*); +extern void __glXDispSwap_Normal3bv(GLbyte*); +extern void __glXDispSwap_Normal3dv(GLbyte*); +extern void __glXDispSwap_Normal3fv(GLbyte*); +extern void __glXDispSwap_Normal3iv(GLbyte*); +extern void __glXDispSwap_Normal3sv(GLbyte*); +extern void __glXDispSwap_RasterPos2dv(GLbyte*); +extern void __glXDispSwap_RasterPos2fv(GLbyte*); +extern void __glXDispSwap_RasterPos2iv(GLbyte*); +extern void __glXDispSwap_RasterPos2sv(GLbyte*); +extern void __glXDispSwap_RasterPos3dv(GLbyte*); +extern void __glXDispSwap_RasterPos3fv(GLbyte*); +extern void __glXDispSwap_RasterPos3iv(GLbyte*); +extern void __glXDispSwap_RasterPos3sv(GLbyte*); +extern void __glXDispSwap_RasterPos4dv(GLbyte*); +extern void __glXDispSwap_RasterPos4fv(GLbyte*); +extern void __glXDispSwap_RasterPos4iv(GLbyte*); +extern void __glXDispSwap_RasterPos4sv(GLbyte*); +extern void __glXDispSwap_Rectdv(GLbyte*); +extern void __glXDispSwap_Rectfv(GLbyte*); +extern void __glXDispSwap_Rectiv(GLbyte*); +extern void __glXDispSwap_Rectsv(GLbyte*); +extern void __glXDispSwap_TexCoord1dv(GLbyte*); +extern void __glXDispSwap_TexCoord1fv(GLbyte*); +extern void __glXDispSwap_TexCoord1iv(GLbyte*); +extern void __glXDispSwap_TexCoord1sv(GLbyte*); +extern void __glXDispSwap_TexCoord2dv(GLbyte*); +extern void __glXDispSwap_TexCoord2fv(GLbyte*); +extern void __glXDispSwap_TexCoord2iv(GLbyte*); +extern void __glXDispSwap_TexCoord2sv(GLbyte*); +extern void __glXDispSwap_TexCoord3dv(GLbyte*); +extern void __glXDispSwap_TexCoord3fv(GLbyte*); +extern void __glXDispSwap_TexCoord3iv(GLbyte*); +extern void __glXDispSwap_TexCoord3sv(GLbyte*); +extern void __glXDispSwap_TexCoord4dv(GLbyte*); +extern void __glXDispSwap_TexCoord4fv(GLbyte*); +extern void __glXDispSwap_TexCoord4iv(GLbyte*); +extern void __glXDispSwap_TexCoord4sv(GLbyte*); +extern void __glXDispSwap_Vertex2dv(GLbyte*); +extern void __glXDispSwap_Vertex2fv(GLbyte*); +extern void __glXDispSwap_Vertex2iv(GLbyte*); +extern void __glXDispSwap_Vertex2sv(GLbyte*); +extern void __glXDispSwap_Vertex3dv(GLbyte*); +extern void __glXDispSwap_Vertex3fv(GLbyte*); +extern void __glXDispSwap_Vertex3iv(GLbyte*); +extern void __glXDispSwap_Vertex3sv(GLbyte*); +extern void __glXDispSwap_Vertex4dv(GLbyte*); +extern void __glXDispSwap_Vertex4fv(GLbyte*); +extern void __glXDispSwap_Vertex4iv(GLbyte*); +extern void __glXDispSwap_Vertex4sv(GLbyte*); +extern void __glXDispSwap_ClipPlane(GLbyte*); +extern void __glXDispSwap_ColorMaterial(GLbyte*); +extern void __glXDispSwap_CullFace(GLbyte*); +extern void __glXDispSwap_Fogf(GLbyte*); +extern void __glXDispSwap_Fogfv(GLbyte*); +extern void __glXDispSwap_Fogi(GLbyte*); +extern void __glXDispSwap_Fogiv(GLbyte*); +extern void __glXDispSwap_FrontFace(GLbyte*); +extern void __glXDispSwap_Hint(GLbyte*); +extern void __glXDispSwap_Lightf(GLbyte*); +extern void __glXDispSwap_Lightfv(GLbyte*); +extern void __glXDispSwap_Lighti(GLbyte*); +extern void __glXDispSwap_Lightiv(GLbyte*); +extern void __glXDispSwap_LightModelf(GLbyte*); +extern void __glXDispSwap_LightModelfv(GLbyte*); +extern void __glXDispSwap_LightModeli(GLbyte*); +extern void __glXDispSwap_LightModeliv(GLbyte*); +extern void __glXDispSwap_LineStipple(GLbyte*); +extern void __glXDispSwap_LineWidth(GLbyte*); +extern void __glXDispSwap_Materialf(GLbyte*); +extern void __glXDispSwap_Materialfv(GLbyte*); +extern void __glXDispSwap_Materiali(GLbyte*); +extern void __glXDispSwap_Materialiv(GLbyte*); +extern void __glXDispSwap_PointSize(GLbyte*); +extern void __glXDispSwap_PolygonMode(GLbyte*); +extern void __glXDispSwap_PolygonStipple(GLbyte*); +extern void __glXDispSwap_Scissor(GLbyte*); +extern void __glXDispSwap_ShadeModel(GLbyte*); +extern void __glXDispSwap_TexParameterf(GLbyte*); +extern void __glXDispSwap_TexParameterfv(GLbyte*); +extern void __glXDispSwap_TexParameteri(GLbyte*); +extern void __glXDispSwap_TexParameteriv(GLbyte*); +extern void __glXDispSwap_TexImage1D(GLbyte*); +extern void __glXDispSwap_TexImage2D(GLbyte*); +extern void __glXDispSwap_TexEnvf(GLbyte*); +extern void __glXDispSwap_TexEnvfv(GLbyte*); +extern void __glXDispSwap_TexEnvi(GLbyte*); +extern void __glXDispSwap_TexEnviv(GLbyte*); +extern void __glXDispSwap_TexGend(GLbyte*); +extern void __glXDispSwap_TexGendv(GLbyte*); +extern void __glXDispSwap_TexGenf(GLbyte*); +extern void __glXDispSwap_TexGenfv(GLbyte*); +extern void __glXDispSwap_TexGeni(GLbyte*); +extern void __glXDispSwap_TexGeniv(GLbyte*); +extern void __glXDispSwap_InitNames(GLbyte*); +extern void __glXDispSwap_LoadName(GLbyte*); +extern void __glXDispSwap_PassThrough(GLbyte*); +extern void __glXDispSwap_PopName(GLbyte*); +extern void __glXDispSwap_PushName(GLbyte*); +extern void __glXDispSwap_DrawBuffer(GLbyte*); +extern void __glXDispSwap_Clear(GLbyte*); +extern void __glXDispSwap_ClearAccum(GLbyte*); +extern void __glXDispSwap_ClearIndex(GLbyte*); +extern void __glXDispSwap_ClearColor(GLbyte*); +extern void __glXDispSwap_ClearStencil(GLbyte*); +extern void __glXDispSwap_ClearDepth(GLbyte*); +extern void __glXDispSwap_StencilMask(GLbyte*); +extern void __glXDispSwap_ColorMask(GLbyte*); +extern void __glXDispSwap_DepthMask(GLbyte*); +extern void __glXDispSwap_IndexMask(GLbyte*); +extern void __glXDispSwap_Accum(GLbyte*); +extern void __glXDispSwap_Disable(GLbyte*); +extern void __glXDispSwap_Enable(GLbyte*); +extern void __glXDispSwap_PopAttrib(GLbyte*); +extern void __glXDispSwap_PushAttrib(GLbyte*); +extern void __glXDispSwap_Map1d(GLbyte*); +extern void __glXDispSwap_Map1f(GLbyte*); +extern void __glXDispSwap_Map2d(GLbyte*); +extern void __glXDispSwap_Map2f(GLbyte*); +extern void __glXDispSwap_MapGrid1d(GLbyte*); +extern void __glXDispSwap_MapGrid1f(GLbyte*); +extern void __glXDispSwap_MapGrid2d(GLbyte*); +extern void __glXDispSwap_MapGrid2f(GLbyte*); +extern void __glXDispSwap_EvalCoord1dv(GLbyte*); +extern void __glXDispSwap_EvalCoord1fv(GLbyte*); +extern void __glXDispSwap_EvalCoord2dv(GLbyte*); +extern void __glXDispSwap_EvalCoord2fv(GLbyte*); +extern void __glXDispSwap_EvalMesh1(GLbyte*); +extern void __glXDispSwap_EvalPoint1(GLbyte*); +extern void __glXDispSwap_EvalMesh2(GLbyte*); +extern void __glXDispSwap_EvalPoint2(GLbyte*); +extern void __glXDispSwap_AlphaFunc(GLbyte*); +extern void __glXDispSwap_BlendFunc(GLbyte*); +extern void __glXDispSwap_LogicOp(GLbyte*); +extern void __glXDispSwap_StencilFunc(GLbyte*); +extern void __glXDispSwap_StencilOp(GLbyte*); +extern void __glXDispSwap_DepthFunc(GLbyte*); +extern void __glXDispSwap_PixelZoom(GLbyte*); +extern void __glXDispSwap_PixelTransferf(GLbyte*); +extern void __glXDispSwap_PixelTransferi(GLbyte*); +extern void __glXDispSwap_PixelMapfv(GLbyte*); +extern void __glXDispSwap_PixelMapuiv(GLbyte*); +extern void __glXDispSwap_PixelMapusv(GLbyte*); +extern void __glXDispSwap_ReadBuffer(GLbyte*); +extern void __glXDispSwap_CopyPixels(GLbyte*); +extern void __glXDispSwap_DrawPixels(GLbyte*); +extern void __glXDispSwap_DepthRange(GLbyte*); +extern void __glXDispSwap_Frustum(GLbyte*); +extern void __glXDispSwap_LoadIdentity(GLbyte*); +extern void __glXDispSwap_LoadMatrixf(GLbyte*); +extern void __glXDispSwap_LoadMatrixd(GLbyte*); +extern void __glXDispSwap_MatrixMode(GLbyte*); +extern void __glXDispSwap_MultMatrixf(GLbyte*); +extern void __glXDispSwap_MultMatrixd(GLbyte*); +extern void __glXDispSwap_Ortho(GLbyte*); +extern void __glXDispSwap_PopMatrix(GLbyte*); +extern void __glXDispSwap_PushMatrix(GLbyte*); +extern void __glXDispSwap_Rotated(GLbyte*); +extern void __glXDispSwap_Rotatef(GLbyte*); +extern void __glXDispSwap_Scaled(GLbyte*); +extern void __glXDispSwap_Scalef(GLbyte*); +extern void __glXDispSwap_Translated(GLbyte*); +extern void __glXDispSwap_Translatef(GLbyte*); +extern void __glXDispSwap_Viewport(GLbyte*); +extern void __glXDispSwap_PolygonOffset(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); +extern void __glXDispSwap_Indexubv(GLbyte*); +extern void __glXDispSwap_ColorSubTable(GLbyte*); +extern void __glXDispSwap_CopyColorSubTable(GLbyte*); +extern void __glXDispSwap_ActiveTextureARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord1svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord2svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord3svARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4dvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4fvARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4ivARB(GLbyte*); +extern void __glXDispSwap_MultiTexCoord4svARB(GLbyte*); + +extern void __glXDispSwap_TexSubImage1D(GLbyte*); +extern void __glXDispSwap_TexSubImage2D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_ConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_ConvolutionParameterfv(GLbyte*); +extern void __glXDispSwap_ConvolutionParameteriv(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter1D(GLbyte*); +extern void __glXDispSwap_CopyConvolutionFilter2D(GLbyte*); +extern void __glXDispSwap_SeparableFilter2D(GLbyte*); +extern void __glXDispSwap_TexImage3D(GLbyte*); +extern void __glXDispSwap_TexSubImage3D(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); +extern void __glXDispSwap_PrioritizeTextures(GLbyte*); +extern void __glXDispSwap_CopyTexImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage1D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage2D(GLbyte*); +extern void __glXDispSwap_CopyTexSubImage3D(GLbyte*); + +#define __GLX_MIN_GLXCMD_OPCODE 1 +#define __GLX_MAX_GLXCMD_OPCODE 20 +#define __GLX_MIN_RENDER_OPCODE 1 +#define __GLX_MAX_RENDER_OPCODE 213 +#define __GLX_MIN_SINGLE_OPCODE 1 +#define __GLX_MAX_SINGLE_OPCODE 159 +#define __GLX_SINGLE_TABLE_SIZE 160 +#define __GLX_RENDER_TABLE_SIZE 214 + +#define __GLX_MIN_RENDER_OPCODE_EXT 4096 +#define __GLX_MAX_RENDER_OPCODE_EXT 4123 + +extern __GLXdispatchSingleProcPtr __glXSingleTable[__GLX_SINGLE_TABLE_SIZE]; +extern __GLXdispatchSingleProcPtr __glXSwapSingleTable[__GLX_SINGLE_TABLE_SIZE]; +#endif /* _GLX_g_disptab_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab_EXT.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab_EXT.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/g_disptab_EXT.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/g_disptab_EXT.h,v 1.5 2004/01/28 18:11:50 alanh Exp $ */ +/* DO NOT EDIT - THIS FILE IS AUTOMATICALLY GENERATED */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _GLX_g_disptab_EXT_h_ +#define _GLX_g_disptab_EXT_h_ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: This software was created using the +** OpenGL(R) version 1.2.1 Sample Implementation published by SGI, but has +** not been independently verified as being compliant with the OpenGL(R) +** version 1.2.1 Specification. +*/ + +#define __GLX_MIN_RENDER_OPCODE_EXT 2053 +#define __GLX_MAX_RENDER_OPCODE_EXT 4325 +#define __GLX_MIN_VENDPRIV_OPCODE_EXT 11 +#define __GLX_MAX_VENDPRIV_OPCODE_EXT 14 +#define __GLX_VENDPRIV_TABLE_SIZE_EXT (__GLX_MAX_VENDPRIV_OPCODE_EXT - __GLX_MIN_VENDPRIV_OPCODE_EXT + 1) +#define __GLX_RENDER_TABLE_SIZE_EXT (__GLX_MAX_RENDER_OPCODE_EXT - __GLX_MIN_RENDER_OPCODE_EXT + 1) +extern __GLXdispatchRenderProcPtr __glXRenderTable_EXT[__GLX_RENDER_TABLE_SIZE_EXT]; +extern __GLXdispatchVendorPrivProcPtr __glXVendorPrivTable_EXT[__GLX_VENDPRIV_TABLE_SIZE_EXT]; +extern __GLXdispatchRenderProcPtr __glXSwapRenderTable_EXT[__GLX_RENDER_TABLE_SIZE_EXT]; +extern __GLXdispatchVendorPrivProcPtr __glXSwapVendorPrivTable_EXT[__GLX_VENDPRIV_TABLE_SIZE_EXT]; +#endif /* _GLX_g_disptab_EXT_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gc.h (revision 51223) @@ -0,0 +1,178 @@ +/* $XFree86: xc/programs/Xserver/include/gc.h,v 1.5 2001/12/14 19:59:54 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: gc.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef GC_H +#define GC_H + +#include /* for GContext, Mask */ +#include /* for Bool */ +#include +#include "screenint.h" /* for ScreenPtr */ +#include "pixmap.h" /* for DrawablePtr */ + +/* clientClipType field in GC */ +#define CT_NONE 0 +#define CT_PIXMAP 1 +#define CT_REGION 2 +#define CT_UNSORTED 6 +#define CT_YSORTED 10 +#define CT_YXSORTED 14 +#define CT_YXBANDED 18 + +#define GCQREASON_VALIDATE 1 +#define GCQREASON_CHANGE 2 +#define GCQREASON_COPY_SRC 3 +#define GCQREASON_COPY_DST 4 +#define GCQREASON_DESTROY 5 + +#define GC_CHANGE_SERIAL_BIT (((unsigned long)1)<<31) +#define GC_CALL_VALIDATE_BIT (1L<<30) +#define GCExtensionInterest (1L<<29) + +#define DRAWABLE_SERIAL_BITS (~(GC_CHANGE_SERIAL_BIT)) + +#define MAX_SERIAL_NUM (1L<<28) + +#define NEXT_SERIAL_NUMBER ((++globalSerialNumber) > MAX_SERIAL_NUM ? \ + (globalSerialNumber = 1): globalSerialNumber) + +typedef struct _GCInterest *GCInterestPtr; +typedef struct _GC *GCPtr; +typedef struct _GCOps *GCOpsPtr; + +extern void ValidateGC( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/); + +extern int ChangeGC( + GCPtr/*pGC*/, + BITS32 /*mask*/, + XID* /*pval*/); + +extern int DoChangeGC( + GCPtr/*pGC*/, + BITS32 /*mask*/, + XID* /*pval*/, + int /*fPointer*/); + +typedef union { + CARD32 val; + pointer ptr; +} ChangeGCVal, *ChangeGCValPtr; + +extern int dixChangeGC( + ClientPtr /*client*/, + GCPtr /*pGC*/, + BITS32 /*mask*/, + CARD32 * /*pval*/, + ChangeGCValPtr /*pCGCV*/); + +extern GCPtr CreateGC( + DrawablePtr /*pDrawable*/, + BITS32 /*mask*/, + XID* /*pval*/, + int* /*pStatus*/); + +extern int CopyGC( + GCPtr/*pgcSrc*/, + GCPtr/*pgcDst*/, + BITS32 /*mask*/); + +extern int FreeGC( + pointer /*pGC*/, + XID /*gid*/); + +extern void SetGCMask( + GCPtr /*pGC*/, + Mask /*selectMask*/, + Mask /*newDataMask*/); + +extern GCPtr CreateScratchGC( + ScreenPtr /*pScreen*/, + unsigned /*depth*/); + +extern void FreeGCperDepth( + int /*screenNum*/); + +extern Bool CreateGCperDepth( + int /*screenNum*/); + +extern Bool CreateDefaultStipple( + int /*screenNum*/); + +extern void FreeDefaultStipple( + int /*screenNum*/); + +extern int SetDashes( + GCPtr /*pGC*/, + unsigned /*offset*/, + unsigned /*ndash*/, + unsigned char* /*pdash*/); + +extern int VerifyRectOrder( + int /*nrects*/, + xRectangle* /*prects*/, + int /*ordering*/); + +extern int SetClipRects( + GCPtr /*pGC*/, + int /*xOrigin*/, + int /*yOrigin*/, + int /*nrects*/, + xRectangle* /*prects*/, + int /*ordering*/); + +extern GCPtr GetScratchGC( + unsigned /*depth*/, + ScreenPtr /*pScreen*/); + +extern void FreeScratchGC( + GCPtr /*pGC*/); + +#endif /* GC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gcstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gcstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gcstruct.h (revision 51223) @@ -0,0 +1,328 @@ +/* $Xorg: gcstruct.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + + +/* $XFree86: xc/programs/Xserver/include/gcstruct.h,v 1.7 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef GCSTRUCT_H +#define GCSTRUCT_H + +#include "gc.h" + +#include "regionstr.h" +#include "region.h" +#include "pixmap.h" +#include "screenint.h" +#include + +/* + * functions which modify the state of the GC + */ + +typedef struct _GCFuncs { + void (* ValidateGC)( + GCPtr /*pGC*/, + unsigned long /*stateChanges*/, + DrawablePtr /*pDrawable*/); + + void (* ChangeGC)( + GCPtr /*pGC*/, + unsigned long /*mask*/); + + void (* CopyGC)( + GCPtr /*pGCSrc*/, + unsigned long /*mask*/, + GCPtr /*pGCDst*/); + + void (* DestroyGC)( + GCPtr /*pGC*/); + + void (* ChangeClip)( + GCPtr /*pGC*/, + int /*type*/, + pointer /*pvalue*/, + int /*nrects*/); + + void (* DestroyClip)( + GCPtr /*pGC*/); + + void (* CopyClip)( + GCPtr /*pgcDst*/, + GCPtr /*pgcSrc*/); + DevUnion devPrivate; +} GCFuncs; + +/* + * graphics operations invoked through a GC + */ + +typedef struct _GCOps { + void (* FillSpans)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/); + + void (* SetSpans)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/); + + void (* PutImage)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pBits*/); + + RegionPtr (* CopyArea)( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*w*/, + int /*h*/, + int /*dstx*/, + int /*dsty*/); + + RegionPtr (* CopyPlane)( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/); + void (* PolyPoint)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/); + + void (* Polylines)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/); + + void (* PolySegment)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegs*/); + + void (* PolyRectangle)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrects*/, + xRectangle * /*pRects*/); + + void (* PolyArc)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/); + + void (* FillPolygon)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*pPts*/); + + void (* PolyFillRect)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/); + + void (* PolyFillArc)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/); + + int (* PolyText8)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/); + + int (* PolyText16)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/); + + void (* ImageText8)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/); + + void (* ImageText16)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/); + + void (* ImageGlyphBlt)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/); + + void (* PolyGlyphBlt)( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/); + + void (* PushPixels)( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDst*/, + int /*w*/, + int /*h*/, + int /*x*/, + int /*y*/); + +#ifdef NEED_LINEHELPER + void (* LineHelper)(); +#endif + + DevUnion devPrivate; +} GCOps; + +/* there is padding in the bit fields because the Sun compiler doesn't + * force alignment to 32-bit boundaries. losers. + */ +typedef struct _GC { + ScreenPtr pScreen; + unsigned char depth; + unsigned char alu; + unsigned short lineWidth; + unsigned short dashOffset; + unsigned short numInDashList; + unsigned char *dash; + unsigned int lineStyle : 2; + unsigned int capStyle : 2; + unsigned int joinStyle : 2; + unsigned int fillStyle : 2; + unsigned int fillRule : 1; + unsigned int arcMode : 1; + unsigned int subWindowMode : 1; + unsigned int graphicsExposures : 1; + unsigned int clientClipType : 2; /* CT_ */ + unsigned int miTranslate:1; /* should mi things translate? */ + unsigned int tileIsPixel:1; /* tile is solid pixel */ + unsigned int fExpose:1; /* Call exposure handling */ + unsigned int freeCompClip:1; /* Free composite clip */ + unsigned int unused:14; /* see comment above */ + unsigned long planemask; + unsigned long fgPixel; + unsigned long bgPixel; + /* + * alas -- both tile and stipple must be here as they + * are independently specifiable + */ + PixUnion tile; + PixmapPtr stipple; + DDXPointRec patOrg; /* origin for (tile, stipple) */ + struct _Font *font; + DDXPointRec clipOrg; + DDXPointRec lastWinOrg; /* position of window last validated */ + pointer clientClip; + unsigned long stateChanges; /* masked with GC_ */ + unsigned long serialNumber; + GCFuncs *funcs; + GCOps *ops; + DevUnion *devPrivates; + /* + * The following were moved here from private storage to allow device- + * independent access to them from screen wrappers. + * --- 1997.11.03 Marc Aurele La France (tsi@xfree86.org) + */ + PixmapPtr pRotatedPixmap; /* tile/stipple rotated for alignment */ + RegionPtr pCompositeClip; + /* fExpose & freeCompClip defined above */ +} GC; + +#endif /* GCSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getbmap.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETBMAP_H +#define GETBMAP_H 1 + +int SProcXGetDeviceButtonMapping(ClientPtr /* client */ + ); + +int ProcXGetDeviceButtonMapping(ClientPtr /* client */ + ); + +void SRepXGetDeviceButtonMapping(ClientPtr /* client */ , + int /* size */ , + xGetDeviceButtonMappingReply * /* rep */ + ); + +#endif /* GETBMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getdctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getdctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getdctl.h (revision 51223) @@ -0,0 +1,50 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETDCTL_H +#define GETDCTL_H 1 + +int SProcXGetDeviceControl(ClientPtr /* client */ + ); + +int ProcXGetDeviceControl(ClientPtr /* client */ + ); + +void CopySwapDeviceResolution(ClientPtr /* client */ , + ValuatorClassPtr /* v */ , + char * /* buf */ , + int /* length */ + ); + +void SRepXGetDeviceControl(ClientPtr /* client */ , + int /* size */ , + xGetDeviceControlReply * /* rep */ + ); + +#endif /* GETDCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfctl.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfctl.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfctl.h (revision 51223) @@ -0,0 +1,74 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETFCTL_H +#define GETFCTL_H 1 + +int SProcXGetFeedbackControl(ClientPtr /* client */ + ); + +int ProcXGetFeedbackControl(ClientPtr /* client */ + ); + +void CopySwapKbdFeedback(ClientPtr /* client */ , + KbdFeedbackPtr /* k */ , + char ** /* buf */ + ); + +void CopySwapPtrFeedback(ClientPtr /* client */ , + PtrFeedbackPtr /* p */ , + char ** /* buf */ + ); + +void CopySwapIntegerFeedback(ClientPtr /* client */ , + IntegerFeedbackPtr /* i */ , + char ** /* buf */ + ); + +void CopySwapStringFeedback(ClientPtr /* client */ , + StringFeedbackPtr /* s */ , + char ** /* buf */ + ); + +void CopySwapLedFeedback(ClientPtr /* client */ , + LedFeedbackPtr /* l */ , + char ** /* buf */ + ); + +void CopySwapBellFeedback(ClientPtr /* client */ , + BellFeedbackPtr /* b */ , + char ** /* buf */ + ); + +void SRepXGetFeedbackControl(ClientPtr /* client */ , + int /* size */ , + xGetFeedbackControlReply * /* rep */ + ); + +#endif /* GETFCTL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfocus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfocus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getfocus.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETFOCUS_H +#define GETFOCUS_H 1 + +int SProcXGetDeviceFocus(ClientPtr /* client */ + ); + +int ProcXGetDeviceFocus(ClientPtr /* client */ + ); + +void SRepXGetDeviceFocus(ClientPtr /* client */ , + int /* size */ , + xGetDeviceFocusReply * /* rep */ + ); + +#endif /* GETFOCUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getkmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getkmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getkmap.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETKMAP_H +#define GETKMAP_H 1 + +int SProcXGetDeviceKeyMapping(ClientPtr /* client */ + ); + +int ProcXGetDeviceKeyMapping(ClientPtr /* client */ + ); + +void SRepXGetDeviceKeyMapping(ClientPtr /* client */ , + int /* size */ , + xGetDeviceKeyMappingReply * /* rep */ + ); + +#endif /* GETKMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getmmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getmmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getmmap.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETMMAP_H +#define GETMMAP_H 1 + +int SProcXGetDeviceModifierMapping(ClientPtr /* client */ + ); + +int ProcXGetDeviceModifierMapping(ClientPtr /* client */ + ); + +void SRepXGetDeviceModifierMapping(ClientPtr /* client */ , + int /* size */ , + xGetDeviceModifierMappingReply * /* rep */ + ); + +#endif /* GETMMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getprop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getprop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getprop.h (revision 51223) @@ -0,0 +1,51 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETPROP_H +#define GETPROP_H 1 + +int SProcXGetDeviceDontPropagateList(ClientPtr /* client */ + ); + +int ProcXGetDeviceDontPropagateList(ClientPtr /* client */ + ); + +XEventClass *ClassFromMask(XEventClass * /* buf */ , + Mask /* mask */ , + int /* maskndx */ , + CARD16 * /* count */ , + int /* mode */ + ); + +void SRepXGetDeviceDontPropagateList(ClientPtr /* client */ , + int /* size */ , + xGetDeviceDontPropagateListReply * /* rep */ + ); + +#endif /* GETPROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getselev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getselev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getselev.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETSELEV_H +#define GETSELEV_H 1 + +int SProcXGetSelectedExtensionEvents(ClientPtr /* client */ + ); + +int ProcXGetSelectedExtensionEvents(ClientPtr /* client */ + ); + +void SRepXGetSelectedExtensionEvents(ClientPtr /* client */ , + int /* size */ , + xGetSelectedExtensionEventsReply * /* rep */ + ); + +#endif /* GETSELEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getvers.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getvers.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/getvers.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GETVERS_H +#define GETVERS_H 1 + +int SProcXGetExtensionVersion(ClientPtr /* client */ + ); + +int ProcXGetExtensionVersion(ClientPtr /* client */ + ); + +void SRepXGetExtensionVersion(ClientPtr /* client */ , + int /* size */ , + xGetExtensionVersionReply * /* rep */ + ); + +#endif /* GETVERS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glcontextmodes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glcontextmodes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glcontextmodes.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * (C) Copyright IBM Corporation 2003 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEM, IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * \file glcontextmodes.h + * \author Ian Romanick + */ + +#ifndef GLCONTEXTMODES_H +#define GLCONTEXTMODES_H + +#include "GL/internal/glcore.h" + +#if !defined(IN_MINI_GLX) +extern GLint _gl_convert_from_x_visual_type( int visualType ); +extern GLint _gl_convert_to_x_visual_type( int visualType ); +extern void _gl_copy_visual_to_context_mode( __GLcontextModes * mode, + const __GLXvisualConfig * config ); +extern int _gl_get_context_mode_data( const __GLcontextModes *mode, + int attribute, int *value_return ); +#endif /* !defined(IN_MINI_GLX) */ + +extern __GLcontextModes * _gl_context_modes_create( unsigned count, + size_t minimum_size ); +extern void _gl_context_modes_destroy( __GLcontextModes * modes ); +extern __GLcontextModes * _gl_context_modes_find_visual( + __GLcontextModes * modes, int vid ); +extern GLboolean _gl_context_modes_are_same( const __GLcontextModes * a, + const __GLcontextModes * b ); + +#endif /* GLCONTEXTMODES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/globals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/globals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/globals.h (revision 51223) @@ -0,0 +1,192 @@ +/* $XdotOrg: xserver/xorg/include/globals.h,v 1.10.10.1 2006/04/05 21:23:06 fredrik Exp $ */ +/* $XFree86: xc/programs/Xserver/include/globals.h,v 1.3 1999/09/25 14:38:21 dawes Exp $ */ + +#ifndef _XSERV_GLOBAL_H_ +#define _XSERV_GLOBAL_H_ + +#include "window.h" /* for WindowPtr */ + +/* Global X server variables that are visible to mi, dix, os, and ddx */ + +extern CARD32 defaultScreenSaverTime; +extern CARD32 defaultScreenSaverInterval; +extern CARD32 ScreenSaverTime; +extern CARD32 ScreenSaverInterval; + +#ifdef SCREENSAVER +extern Bool screenSaverSuspended; +#endif + +extern char *defaultFontPath; +extern char *rgbPath; +extern int monitorResolution; +extern Bool loadableFonts; +extern int defaultColorVisualClass; + +extern Bool Must_have_memory; +extern WindowPtr *WindowTable; +extern int GrabInProgress; +extern Bool noTestExtensions; + +extern DDXPointRec dixScreenOrigins[MAXSCREENS]; + +#ifdef DPMSExtension +extern CARD32 defaultDPMSStandbyTime; +extern CARD32 defaultDPMSSuspendTime; +extern CARD32 defaultDPMSOffTime; +extern CARD32 DPMSStandbyTime; +extern CARD32 DPMSSuspendTime; +extern CARD32 DPMSOffTime; +extern CARD16 DPMSPowerLevel; +extern Bool defaultDPMSEnabled; +extern Bool DPMSEnabled; +extern Bool DPMSEnabledSwitch; +extern Bool DPMSDisabledSwitch; +extern Bool DPMSCapableFlag; +#endif + +#ifdef PANORAMIX +extern Bool PanoramiXMapped; +extern Bool PanoramiXVisibilityNotifySent; +extern Bool PanoramiXWindowExposureSent; +extern Bool PanoramiXOneExposeRequest; +#endif + +#ifdef BIGREQS +extern Bool noBigReqExtension; +#endif + +#ifdef COMPOSITE +extern Bool noCompositeExtension; +#endif + +#ifdef DAMAGE +extern Bool noDamageExtension; +#endif + +#ifdef DBE +extern Bool noDbeExtension; +#endif + +#ifdef DPMSExtension +extern Bool noDPMSExtension; +#endif + +#ifdef EVI +extern Bool noEVIExtension; +#endif + +#ifdef FONTCACHE +extern Bool noFontCacheExtension; +#endif + +#ifdef GLXEXT +extern Bool noGlxExtension; +#endif + +#ifdef LBX +extern Bool noLbxExtension; +#endif + +#ifdef SCREENSAVER +extern Bool noScreenSaverExtension; +#endif + +#ifdef MITSHM +extern Bool noMITShmExtension; +#endif + +#ifdef MITMISC +extern Bool noMITMiscExtension; +#endif + +#ifdef MULTIBUFFER +extern Bool noMultibufferExtension; +#endif + +#ifdef RANDR +extern Bool noRRExtension; +#endif + +#ifdef RENDER +extern Bool noRenderExtension; +#endif + +#ifdef SHAPE +extern Bool noShapeExtension; +#endif + +#ifdef XCSECURITY +extern Bool noSecurityExtension; +#endif + +#ifdef XSYNC +extern Bool noSyncExtension; +#endif + +#ifdef TOGCUP +extern Bool noXcupExtension; +#endif + +#ifdef RES +extern Bool noResExtension; +#endif + +#ifdef XAPPGROUP +extern Bool noXagExtension; +#endif + +#ifdef XCMISC +extern Bool noXCMiscExtension; +#endif + +#ifdef XEVIE +extern Bool noXevieExtension; +#endif + +#ifdef XF86BIGFONT +extern Bool noXFree86BigfontExtension; +#endif + +#ifdef XFreeXDGA +extern Bool noXFree86DGAExtension; +#endif + +#ifdef XF86DRI +extern Bool noXFree86DRIExtension; +#endif + +#ifdef XF86MISC +extern Bool noXFree86MiscExtension; +#endif + +#ifdef XF86VIDMODE +extern Bool noXFree86VidModeExtension; +#endif + +#ifdef XFIXES +extern Bool noXFixesExtension; +#endif + +#ifdef XKB +/* |noXkbExtension| is defined in xc/programs/Xserver/xkb/xkbInit.c */ +extern Bool noXkbExtension; +#endif + +#ifdef PANORAMIX +extern Bool noPanoramiXExtension; +#endif + +#ifdef XINPUT +extern Bool noXInputExtension; +#endif + +#ifdef XIDLE +extern Bool noXIdleExtension; +#endif + +#ifdef XV +extern Bool noXvExtension; +#endif + +#endif /* !_XSERV_GLOBAL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glwindows.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glwindows.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glwindows.h (revision 51223) @@ -0,0 +1,64 @@ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +typedef struct { + unsigned enableDebug : 1; + unsigned enableTrace : 1; + unsigned dumpPFD : 1; + unsigned dumpHWND : 1; + unsigned dumpDC : 1; +} glWinDebugSettingsRec, *glWinDebugSettingsPtr; +extern glWinDebugSettingsRec glWinDebugSettings; + +typedef struct { + int num_vis; + __GLcontextModes *modes; + void **priv; + + /* wrapped screen functions */ + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + CopyWindowProcPtr CopyWindow; +} glWinScreenRec; + +extern glWinScreenRec glWinScreens[MAXSCREENS]; + +#define glWinGetScreenPriv(pScreen) &glWinScreens[pScreen->myNum] +#define glWinScreenPriv(pScreen) glWinScreenRec *pScreenPriv = glWinGetScreenPriv(pScreen); + +#if 1 +#define GLWIN_TRACE() if (glWinDebugSettings.enableTrace) ErrorF("%s:%d: Trace\n", __FUNCTION__, __LINE__ ) +#define GLWIN_TRACE_MSG(msg, args...) if (glWinDebugSettings.enableTrace) ErrorF("%s:%d: " msg, __FUNCTION__, __LINE__, ##args ) +#define GLWIN_DEBUG_MSG(msg, args...) if (glWinDebugSettings.enableDebug) ErrorF("%s:%d: " msg, __FUNCTION__, __LINE__, ##args ) +#define GLWIN_DEBUG_MSG2(msg, args...) if (glWinDebugSettings.enableDebug) ErrorF(msg, ##args ) +#else +#define GLWIN_TRACE() +#define GLWIN_TRACE_MSG(a, ...) +#define GLWIN_DEBUG_MSG(a, ...) +#define GLWIN_DEBUG_MSG2(a, ...) +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glx_ansic.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glx_ansic.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glx_ansic.h (revision 51223) @@ -0,0 +1,112 @@ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _glx_ansic_h_ +#define _glx_ansic_h_ + +/* $XFree86: xc/programs/Xserver/GL/include/GL/glx_ansic.h,v 1.5 2001/03/21 20:49:08 dawes Exp $ */ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +*/ + +/* +** this needs to check whether we're using XFree86 at all, and then +** which version we're using. Use these macros if version is 3.9+, else +** use normal commands below. +*/ + +/* +** turns out this include file only exists for XFree86 3.9+ +** I notice that not having it is not an error and does not stop the build, +** but having it will allow opengl and glx to be built for 3.9+. We no longer +** need an explicit define in the Makefile, just point to the correct X source +** tree and all should be taken care of. +*/ + +#ifdef XFree86Server + +#ifndef assert +#define assert(a) +#endif + +#else + +#if defined(Lynx) && defined(__assert_h) +#undef __assert_h +#endif +#ifdef assert +#undef assert +#endif +#include + +#endif + + +#define GLX_STDOUT stdout +#define GLX_STDERR stderr +#define __glXPrintf printf +#define __glXFprintf fprintf +#define __glXSprintf sprintf +#define __glXVfprintf vfprintf +#define __glXVsprintf vsprintf +#define __glXFopen fopen +#define __glXFclose fclose +#define __glXCos(x) cos(x) +#define __glXSin(x) sin(x) +#define __glXAtan(x) atan(x) +#define __glXAbs(x) abs(x) +#define __glXLog(x) log(x) +#define __glXCeil(x) ceil(x) +#define __glXFloor(x) floor(x) +#define __glXSqrt(x) sqrt(x) +#define __glXPow(x, y) pow(x, y) +#define __glXMemmove(dest, src, n) memmove(dest, src, n) +#define __glXMemcpy(dest, src, n) memcpy(dest, src, n) +#define __glXMemset(s, c, n) memset(s, c, n) +#define __glXStrdup(str) xstrdup(str) +#define __glXStrcpy(dest, src) strcpy(dest, src) +#define __glXStrncpy(dest, src, n) strncpy(dest, src, n) +#define __glXStrcat(dest, src) strcat(dest, src) +#define __glXStrncat(dest, src, n) strncat(dest, src, n) +#define __glXStrcmp(s1, s2) strcmp(s1, s2) +#define __glXStrncmp(s1, s2, n) strncmp(s1, s2, n) +#define __glXStrlen(str) strlen(str) +#define __glXAbort() abort() +#define __glXStrtok(s, delim) strtok(s, delim) +#define __glXStrcspn(s, reject) strcspn(s, reject) +#define __glXGetenv(a) getenv(a) +#define __glXAtoi(a) atoi(a) + +#endif /* _glx_ansic_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxcontext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxcontext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxcontext.h (revision 51223) @@ -0,0 +1,117 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxcontext.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_context_h_ +#define _GLX_context_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +typedef struct __GLXcontextRec __GLXcontext; + +#include "GL/internal/glcore.h" + +struct __GLXcontextRec { + /* + ** list of context structs + */ + struct __GLXcontextRec *last; + struct __GLXcontextRec *next; + + /* + ** Pointer to screen info data for this context. This is set + ** when the context is created. + */ + ScreenPtr pScreen; + __GLXscreenInfo *pGlxScreen; + + /* + ** This context is created with respect to this visual. + */ + VisualRec *pVisual; + __GLXvisualConfig *pGlxVisual; + __GLXFBConfig *pFBConfig; + + /* + ** The XID of this context. + */ + XID id; + XID *real_ids; + + /* + ** The XID of the shareList context. + */ + XID share_id; + + /* + ** Visual id. + */ + VisualID vid; + VisualID *real_vids; + + /* + ** screen number. + */ + GLint screen; + + /* + ** Whether this context's ID still exists. + */ + GLboolean idExists; + + /* + ** Whether this context is current for some client. + */ + GLboolean isCurrent; + + /* + ** Buffers for feedback and selection. + */ + GLfloat *feedbackBuf; + GLint feedbackBufSize; /* number of elements allocated */ + GLuint *selectBuf; + GLint selectBufSize; /* number of elements allocated */ + + /* + ** Set only if current drawable is a glx pixmap. + */ + __GLXpixmap *pGlxPixmap; + __GLXpixmap *pGlxReadPixmap; + __glXWindow *pGlxWindow; + __glXWindow *pGlxReadWindow; + __glXPbuffer *pGlxPbuffer; + __glXPbuffer *pGlxReadPbuffer; + +}; + +#endif /* !__GLX_context_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxdrawable.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxdrawable.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxdrawable.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxdrawable.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_drawable_h_ +#define _GLX_drawable_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +typedef struct { + + DrawablePtr pDraw; + __GLXvisualConfig *pGlxVisual; + __GLXscreenInfo *pGlxScreen; + __GLXFBConfig *pFBConfig; + ScreenPtr pScreen; + Bool idExists; + int refcnt; + XID *be_xids; + +} __GLXpixmap; + +struct __GLXdrawablePrivateRec { + /* + ** list of drawable private structs + */ + struct __GLXdrawablePrivateRec *last; + struct __GLXdrawablePrivateRec *next; + + DrawablePtr pDraw; + XID drawId; + __GLXpixmap *pGlxPixmap; + + /* + ** Either DRAWABLE_PIXMAP or DRAWABLE_WINDOW, copied from pDraw above. + ** Needed by the resource freer because pDraw might already have been + ** freed. + */ + int type; + + /* + ** Configuration of the visual to which this drawable was created. + */ + __GLXvisualConfig *pGlxVisual; + + /* + ** cached drawable size and origin + */ + GLint xorigin, yorigin; + GLint width, height; + + /* + ** list of contexts bound to this drawable + */ + struct __GLXcontextRec *glxc; + + /* + ** "methods" that the drawble should be able to respond to. + */ + void (*freeBuffers)(struct __GLXdrawablePrivateRec *); + void (*updatePalette)(struct __GLXdrawablePrivateRec *); + GLboolean (*swapBuffers)(struct __GLXdrawablePrivateRec *); + + /* + ** The GL drawable (information shared between GLX and the GL core) + */ + __GLdrawablePrivate glPriv; + + /* + ** reference count + */ + int refCount; +}; + +typedef struct { + DrawablePtr pDraw; + int type; + Bool idExists; + int refcnt; /* contexts bound */ + __GLXFBConfig *pGlxFBConfig; + ScreenPtr pScreen; +} __glXWindow; + + +typedef struct { + __GLXscreenInfo *pGlxScreen; + __GLXFBConfig *pFBConfig; + ScreenPtr pScreen; + Bool idExists; + int refcnt; + XID *be_xids; +} __glXPbuffer; + +#endif /* !__GLX_drawable_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxerror.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxerror.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxerror.h (revision 51223) @@ -0,0 +1,58 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxerror.h,v 1.3 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _GLX_error_h_ +#define _GLX_error_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +/* +** Error codes. These have the extension error base added to them +** when the extension initializes. +*/ +extern int __glXerrorBase; +extern int __glXBadContext; +extern int __glXBadContextState; +extern int __glXBadDrawable; +extern int __glXBadPixmap; +extern int __glXBadCurrentWindow; +extern int __glXBadContextTag; +extern int __glXBadRenderRequest; +extern int __glXBadLargeRequest; +extern int __glXUnsupportedPrivateRequest; +extern int __glXBadFBConfig; +extern int __glXBadPbuffer; + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxext.h (revision 51223) @@ -0,0 +1,98 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxext.h,v 1.4 2001/03/21 16:29:36 dawes Exp $ */ +#ifndef _glxext_h_ +#define _glxext_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +/* + * Added by VA Linux for XFree86 4.0.x + */ +typedef struct { + int type; + void (*resetExtension)(void); + Bool (*initVisuals)( + VisualPtr * visualp, + DepthPtr * depthp, + int * nvisualp, + int * ndepthp, + int * rootDepthp, + VisualID * defaultVisp, + unsigned long sizes, + int bitsPerRGB + ); + void (*setVisualConfigs)( + int nconfigs, + __GLXvisualConfig *configs, + void **privates + ); +} __GLXextensionInfo; + +extern GLboolean __glXFreeContext(__GLXcontext *glxc); +extern void __glXFlushContextCache(void); + +extern void __glXFreeGLXWindow(__glXWindow *pGlxWindow); +extern void __glXFreeGLXPixmap( __GLXpixmap *pGlxPixmap ); + +extern void __glXNoSuchRenderOpcode(GLbyte*); +extern int __glXNoSuchSingleOpcode(__GLXclientState*, GLbyte*); +extern void __glXErrorCallBack(__GLinterface *gc, GLenum code); +extern void __glXClearErrorOccured(void); +extern GLboolean __glXErrorOccured(void); +extern void __glXResetLargeCommandStatus(__GLXclientState*); + +extern int __glXQueryContextInfoEXT(__GLXclientState *cl, GLbyte *pc); +extern int __glXSwapQueryContextInfoEXT(__GLXclientState *cl, char *pc); + +extern void GlxExtensionInit(void); + +extern Bool __glXCoreType(void); + +extern int GlxInitVisuals( +#if NeedFunctionPrototypes + VisualPtr * visualp, + DepthPtr * depthp, + int * nvisualp, + int * ndepthp, + int * rootDepthp, + VisualID * defaultVisp, + unsigned long sizes, + int bitsPerRGB, + int preferredVis +#endif +); + +#endif /* _glxext_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxfbconfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxfbconfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxfbconfig.h (revision 51223) @@ -0,0 +1,43 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLXFBCONFIG_H + +#include + +int AreFBConfigsMatch( __GLXFBConfig *c1, __GLXFBConfig *c2 ); +__GLXFBConfig *FindMatchingFBConfig( __GLXFBConfig *c, __GLXFBConfig *configs, int nconfigs ); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxscreens.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxscreens.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxscreens.h (revision 51223) @@ -0,0 +1,63 @@ +#ifndef _GLX_screens_h_ +#define _GLX_screens_h_ + +/* $XFree86: xc/programs/Xserver/GL/glx/glxscreens.h,v 1.4 2001/03/21 16:29:37 dawes Exp $ */ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "GL/internal/glcore.h" + + + +typedef struct { + + __GLXvisualConfig *pGlxVisual; + GLint numVisuals; + GLint numGLXVisuals; + GLint *isGLXvis; + + char *GLXvendor; + char *GLXversion; + char *GLXextensions; + +} __GLXscreenInfo; + + +extern void __glXScreenInit(GLint); +extern void __glXScreenReset(void); + +extern char *__glXGetServerString( unsigned int name ); + +#endif /* !__GLX_screens_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxserver.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxserver.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxserver.h (revision 51223) @@ -0,0 +1,327 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxserver.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef _GLX_server_h_ +#define _GLX_server_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "dmx.h" + +#include +#include +#include +#include +#include +#include +#include +#include "GL/glx_ansic.h" + + +/* +** The X header misc.h defines these math functions. +*/ +#undef abs +#undef fabs + +#define GL_GLEXT_PROTOTYPES /* we want prototypes */ +#include +#include +#include + +/* For glxscreens.h */ +typedef struct __GLXdrawablePrivateRec __GLXdrawablePrivate; + +#include "glxscreens.h" +#include "glxdrawable.h" +#include "glxcontext.h" +#include "glxerror.h" + + +#define GLX_SERVER_MAJOR_VERSION 1 +#define GLX_SERVER_MINOR_VERSION 3 + +#ifndef True +#define True 1 +#endif +#ifndef False +#define False 0 +#endif + +/* +** GLX resources. +typedef XID GLXContextID; +typedef XID GLXPixmap; +typedef XID GLXDrawable; +typedef XID GLXWindow; +typedef XID GLXPbuffer; + +typedef struct __GLXcontextRec *GLXContext; +*/ +typedef struct __GLXclientStateRec __GLXclientState; + +extern __GLXscreenInfo *__glXActiveScreens; +extern GLint __glXNumActiveScreens; + +/************************************************************************/ + +/* +** The last context used (from the server's persective) is cached. +*/ +extern __GLXcontext *__glXLastContext; +extern __GLXcontext *__glXForceCurrent(__GLXclientState*, GLXContextTag, int*); + +/* +** Macros to set, unset, and retrieve the flag that says whether a context +** has unflushed commands. +*/ +#define __GLX_NOTE_UNFLUSHED_CMDS(glxc) glxc->hasUnflushedCommands = GL_TRUE +#define __GLX_NOTE_FLUSHED_CMDS(glxc) glxc->hasUnflushedCommands = GL_FALSE +#define __GLX_HAS_UNFLUSHED_CMDS(glxc) (glxc->hasUnflushedCommands) + +/************************************************************************/ + +typedef struct { + int elem_size; /* element size in bytes */ + int nelems; /* number of elements to swap */ + void (*swapfunc)(GLbyte *pc); +} __GLXRenderSwapInfo; + +/* +** State kept per client. +*/ +struct __GLXclientStateRec { + /* + ** Whether this structure is currently being used to support a client. + */ + Bool inUse; + + /* + ** Buffer for returned data. + */ + GLbyte *returnBuf; + GLint returnBufSize; + + /* + ** Keep a list of all the contexts that are current for this client's + ** threads. + */ + __GLXcontext **currentContexts; + DrawablePtr *currentDrawables; + GLint numCurrentContexts; + + /* Back pointer to X client record */ + ClientPtr client; + + int GLClientmajorVersion; + int GLClientminorVersion; + char *GLClientextensions; + + GLXContextTag *be_currentCTag; + Display **be_displays; + + /* + ** Keep track of large rendering commands, which span multiple requests. + */ + GLint largeCmdBytesSoFar; /* bytes received so far */ + GLint largeCmdBytesTotal; /* total bytes expected */ + GLint largeCmdRequestsSoFar; /* requests received so far */ + GLint largeCmdRequestsTotal; /* total requests expected */ + void (*largeCmdRequestsSwapProc)(GLbyte *); + __GLXRenderSwapInfo *largeCmdRequestsSwap_info; + GLbyte *largeCmdBuf; + GLint largeCmdBufSize; + GLint largeCmdMaxReqDataSize; + +}; + +extern __GLXclientState *__glXClients[]; + +/************************************************************************/ + +/* +** Dispatch tables. +*/ +typedef void (*__GLXdispatchRenderProcPtr)(GLbyte *); +typedef int (*__GLXdispatchSingleProcPtr)(__GLXclientState *, GLbyte *); +typedef int (*__GLXdispatchVendorPrivProcPtr)(__GLXclientState *, GLbyte *); +extern __GLXdispatchSingleProcPtr __glXSingleTable[]; +extern __GLXdispatchVendorPrivProcPtr __glXVendorPrivTable_EXT[]; +extern __GLXdispatchSingleProcPtr __glXSwapSingleTable[]; +extern __GLXdispatchVendorPrivProcPtr __glXSwapVendorPrivTable_EXT[]; +extern __GLXdispatchRenderProcPtr __glXSwapRenderTable[]; + +extern __GLXRenderSwapInfo __glXSwapRenderTable_EXT[]; + +/* + * Dispatch for GLX commands. + */ +typedef int (*__GLXprocPtr)(__GLXclientState *, char *pc); +extern __GLXprocPtr __glXProcTable[]; + +/* + * Tables for computing the size of each rendering command. + */ +typedef struct { + int bytes; + int (*varsize)(GLbyte *pc, Bool swap); +} __GLXrenderSizeData; +extern __GLXrenderSizeData __glXRenderSizeTable[]; +extern __GLXrenderSizeData __glXRenderSizeTable_EXT[]; + +/************************************************************************/ + +/* +** X resources. +*/ +extern RESTYPE __glXContextRes; +extern RESTYPE __glXClientRes; +extern RESTYPE __glXPixmapRes; +extern RESTYPE __glXDrawableRes; +extern RESTYPE __glXWindowRes; +extern RESTYPE __glXPbufferRes; + +/************************************************************************/ + +/* +** Prototypes. +*/ + + +extern char *__glXcombine_strings(const char *, const char *); + +extern void __glXDisp_DrawArrays(GLbyte*); +extern void __glXDispSwap_DrawArrays(GLbyte*); + + +/* +** Routines for sending swapped replies. +*/ + +extern void __glXSwapMakeCurrentReply(ClientPtr client, + xGLXMakeCurrentReadSGIReply *reply); + +extern void __glXSwapIsDirectReply(ClientPtr client, + xGLXIsDirectReply *reply); +extern void __glXSwapQueryVersionReply(ClientPtr client, + xGLXQueryVersionReply *reply); +extern void __glXSwapQueryContextInfoEXTReply(ClientPtr client, + xGLXQueryContextInfoEXTReply *reply, + int *buf); +extern void glxSwapQueryExtensionsStringReply(ClientPtr client, + xGLXQueryExtensionsStringReply *reply, char *buf); +extern void glxSwapQueryServerStringReply(ClientPtr client, + xGLXQueryServerStringReply *reply, char *buf); +extern void __glXSwapQueryContextReply(ClientPtr client, + xGLXQueryContextReply *reply, int *buf); +extern void __glXSwapGetDrawableAttributesReply(ClientPtr client, + xGLXGetDrawableAttributesReply *reply, int *buf); +extern void __glXSwapQueryMaxSwapBarriersSGIXReply(ClientPtr client, + xGLXQueryMaxSwapBarriersSGIXReply *reply); + +/* + * Routines for computing the size of variably-sized rendering commands. + */ + +extern int __glXTypeSize(GLenum enm); +extern int __glXImageSize(GLenum format, GLenum type, GLsizei w, GLsizei h, + GLint rowLength, GLint skipRows, GLint alignment); +extern int __glXImage3DSize(GLenum format, GLenum type, + GLsizei w, GLsizei h, GLsizei d, + GLint imageHeight, GLint rowLength, + GLint skipImages, GLint skipRows, + GLint alignment); + +extern int __glXCallListsReqSize(GLbyte *pc, Bool swap); +extern int __glXBitmapReqSize(GLbyte *pc, Bool swap); +extern int __glXFogfvReqSize(GLbyte *pc, Bool swap); +extern int __glXFogivReqSize(GLbyte *pc, Bool swap); +extern int __glXLightfvReqSize(GLbyte *pc, Bool swap); +extern int __glXLightivReqSize(GLbyte *pc, Bool swap); +extern int __glXLightModelfvReqSize(GLbyte *pc, Bool swap); +extern int __glXLightModelivReqSize(GLbyte *pc, Bool swap); +extern int __glXMaterialfvReqSize(GLbyte *pc, Bool swap); +extern int __glXMaterialivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexParameterivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage1DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage2DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexEnvfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexEnvivReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGendvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGenfvReqSize(GLbyte *pc, Bool swap); +extern int __glXTexGenivReqSize(GLbyte *pc, Bool swap); +extern int __glXMap1dReqSize(GLbyte *pc, Bool swap); +extern int __glXMap1fReqSize(GLbyte *pc, Bool swap); +extern int __glXMap2dReqSize(GLbyte *pc, Bool swap); +extern int __glXMap2fReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapfvReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapuivReqSize(GLbyte *pc, Bool swap); +extern int __glXPixelMapusvReqSize(GLbyte *pc, Bool swap); +extern int __glXDrawPixelsReqSize(GLbyte *pc, Bool swap); +extern int __glXDrawArraysSize(GLbyte *pc, Bool swap); +extern int __glXPrioritizeTexturesReqSize(GLbyte *pc, Bool swap); +extern int __glXTexSubImage1DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexSubImage2DReqSize(GLbyte *pc, Bool swap); +extern int __glXTexImage3DReqSize(GLbyte *pc, Bool swap ); +extern int __glXTexSubImage3DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionFilter1DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionFilter2DReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionParameterivReqSize(GLbyte *pc, Bool swap); +extern int __glXConvolutionParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXSeparableFilter2DReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableReqSize(GLbyte *pc, Bool swap); +extern int __glXColorSubTableReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableParameterfvReqSize(GLbyte *pc, Bool swap); +extern int __glXColorTableParameterivReqSize(GLbyte *pc, Bool swap); + +/* + * Routines for computing the size of returned data. + */ +extern int __glXConvolutionParameterivSize(GLenum pname); +extern int __glXConvolutionParameterfvSize(GLenum pname); +extern int __glXColorTableParameterfvSize(GLenum pname); +extern int __glXColorTableParameterivSize(GLenum pname); + +extern void __glXFreeGLXWindow(__glXWindow *pGlxWindow); +extern void __glXFreeGLXPbuffer(__glXPbuffer *pGlxPbuffer); + +extern int __glXVersionMajor; +extern int __glXVersionMinor; + +#define __GLX_IS_VERSION_SUPPORTED(major,minor) \ + ( (__glXVersionMajor > (major)) || \ + ((__glXVersionMajor == (major)) && (__glXVersionMinor >= (minor))) ) + +#endif /* !__GLX_server_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxsingle.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxsingle.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxsingle.h (revision 51223) @@ -0,0 +1,59 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef __GLXSINGLE_H +#define __GLXSINGLE_H + +extern int __glXForwardSingleReq( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReply( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReply( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardSingleReqSwap( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardPipe0WithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardPipe0WithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXForwardAllWithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXForwardAllWithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXDisp_ReadPixels(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_GetTexImage(__GLXclientState *cl, GLbyte *pc); +extern int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxswap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxswap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxswap.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/* + * Copyright 2003 Red Hat Inc., Raleigh, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifndef __GLX_swap_h__ +#define __GLX_swap_h__ + +extern int JoinSwapGroupSGIX(DrawablePtr pDraw, DrawablePtr pMember); +extern int SGSwapBuffers(__GLXclientState *cl, XID drawId, GLXContextTag tag, + DrawablePtr pDraw); + +extern void SwapBarrierInit(void); +extern void SwapBarrierReset(void); +extern int QueryMaxSwapBarriersSGIX(int screen); +extern int BindSwapBarrierSGIX(DrawablePtr pDraw, int barrier); + +#endif /* !__GLX_swap_h__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxutil.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxutil.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxutil.h (revision 51223) @@ -0,0 +1,54 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/glxutil.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef _glxcmds_h_ +#define _glxcmds_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +extern void __glXNop(void); + +/* memory management */ +extern void *__glXMalloc(size_t size); +extern void *__glXCalloc(size_t numElements, size_t elementSize); +extern void *__glXRealloc(void *addr, size_t newSize); +extern void __glXFree(void *ptr); + +/* context helper routines */ +extern __GLXcontext *__glXLookupContextByTag(__GLXclientState*, GLXContextTag); +extern DrawablePtr __glXLookupDrawableByTag(__GLXclientState *cl, GLXContextTag tag); + + +#endif /* _glxcmds_h_ */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvendor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvendor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvendor.h (revision 51223) @@ -0,0 +1,55 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef __GLXVENDOR_H +#define __GLXVENDOR_H + +extern int __glXVForwardSingleReq( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReply( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReply( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardSingleReqSwap( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardPipe0WithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardPipe0WithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +extern int __glXVForwardAllWithReplySwap( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapsv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapiv( __GLXclientState *cl, GLbyte *pc ); +extern int __glXVForwardAllWithReplySwapdv( __GLXclientState *cl, GLbyte *pc ); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvisuals.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvisuals.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glxvisuals.h (revision 51223) @@ -0,0 +1,55 @@ +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#ifndef _GLX_VISUALS_H +#define _GLX_VISUALS_H + +int glxVisualsMatch( __GLXvisualConfig *v1, __GLXvisualConfig *v2 ); + +VisualID glxMatchGLXVisualInConfigList( __GLXvisualConfig *pGlxVisual, __GLXvisualConfig *configs, int nconfigs ); + +VisualID glxMatchVisualInConfigList( ScreenPtr pScreen, VisualPtr pVisual, __GLXvisualConfig *configs, int nconfigs ); + +VisualPtr glxMatchVisual( ScreenPtr pScreen, VisualPtr pVisual, ScreenPtr pMatchScreen ); + +void glxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, + void **privates); + +Bool glxInitVisuals(int *nvisualp, VisualPtr *visualp, + VisualID *defaultVisp, + int ndepth, DepthPtr pdepth, + int rootDepth); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glyphstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glyphstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/glyphstr.h (revision 51223) @@ -0,0 +1,171 @@ +/* + * $XFree86: xc/programs/Xserver/render/glyphstr.h,v 1.3 2000/11/20 07:13:13 keithp Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _GLYPHSTR_H_ +#define _GLYPHSTR_H_ + +#include +#include "picture.h" +#include "screenint.h" +#include "regionstr.h" +#include "miscstruct.h" + +#define GlyphFormat1 0 +#define GlyphFormat4 1 +#define GlyphFormat8 2 +#define GlyphFormat16 3 +#define GlyphFormat32 4 +#define GlyphFormatNum 5 + +typedef struct _Glyph { + CARD32 refcnt; + DevUnion *devPrivates; + CARD32 size; /* info + bitmap */ + xGlyphInfo info; + /* bits follow */ +} GlyphRec, *GlyphPtr; + +typedef struct _GlyphRef { + CARD32 signature; + GlyphPtr glyph; +} GlyphRefRec, *GlyphRefPtr; + +#define DeletedGlyph ((GlyphPtr) 1) + +typedef struct _GlyphHashSet { + CARD32 entries; + CARD32 size; + CARD32 rehash; +} GlyphHashSetRec, *GlyphHashSetPtr; + +typedef struct _GlyphHash { + GlyphRefPtr table; + GlyphHashSetPtr hashSet; + CARD32 tableEntries; +} GlyphHashRec, *GlyphHashPtr; + +typedef struct _GlyphSet { + CARD32 refcnt; + PictFormatPtr format; + int fdepth; + GlyphHashRec hash; + int maxPrivate; + pointer *devPrivates; +} GlyphSetRec, *GlyphSetPtr; + +#define GlyphSetGetPrivate(pGlyphSet,n) \ + ((n) > (pGlyphSet)->maxPrivate ? \ + (pointer) 0 : \ + (pGlyphSet)->devPrivates[n]) + +#define GlyphSetSetPrivate(pGlyphSet,n,ptr) \ + ((n) > (pGlyphSet)->maxPrivate ? \ + _GlyphSetSetNewPrivate(pGlyphSet, n, ptr) : \ + ((((pGlyphSet)->devPrivates[n] = (ptr)) != 0) || TRUE)) + +typedef struct _GlyphList { + INT16 xOff; + INT16 yOff; + CARD8 len; + PictFormatPtr format; +} GlyphListRec, *GlyphListPtr; + +extern GlyphHashRec globalGlyphs[GlyphFormatNum]; + +GlyphHashSetPtr +FindGlyphHashSet (CARD32 filled); + +int +AllocateGlyphSetPrivateIndex (void); + +void +ResetGlyphSetPrivateIndex (void); + +Bool +_GlyphSetSetNewPrivate (GlyphSetPtr glyphSet, int n, pointer ptr); + +void +ResetGlyphPrivates (void); + +int +AllocateGlyphPrivateIndex (void); + +Bool +AllocateGlyphPrivate (ScreenPtr pScreen, + int index2, + unsigned amount); + +Bool +GlyphInit (ScreenPtr pScreen); + +Bool +GlyphFinishInit (ScreenPtr pScreen); + +void +GlyphUninit (ScreenPtr pScreen); + +GlyphHashSetPtr +FindGlyphHashSet (CARD32 filled); + +GlyphRefPtr +FindGlyphRef (GlyphHashPtr hash, CARD32 signature, Bool match, GlyphPtr compare); + +CARD32 +HashGlyph (GlyphPtr glyph); + +void +FreeGlyph (GlyphPtr glyph, int format); + +void +AddGlyph (GlyphSetPtr glyphSet, GlyphPtr glyph, Glyph id); + +Bool +DeleteGlyph (GlyphSetPtr glyphSet, Glyph id); + +GlyphPtr +FindGlyph (GlyphSetPtr glyphSet, Glyph id); + +GlyphPtr +AllocateGlyph (xGlyphInfo *gi, int format); + +Bool +AllocateGlyphHash (GlyphHashPtr hash, GlyphHashSetPtr hashSet); + +Bool +ResizeGlyphHash (GlyphHashPtr hash, CARD32 change, Bool global); + +Bool +ResizeGlyphSet (GlyphSetPtr glyphSet, CARD32 change); + +GlyphSetPtr +AllocateGlyphSet (int fdepth, PictFormatPtr format); + +int +FreeGlyphSet (pointer value, + XID gid); + + + +#endif /* _GLYPHSTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdev.h (revision 51223) @@ -0,0 +1,52 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEV_H +#define GRABDEV_H 1 + +int SProcXGrabDevice(ClientPtr /* client */ + ); + +int ProcXGrabDevice(ClientPtr /* client */ + ); + +int CreateMaskFromList(ClientPtr /* client */ , + XEventClass * /* list */ , + int /* count */ , + struct tmask /* mask */ [], + DeviceIntPtr /* dev */ , + int /* req */ + ); + +void SRepXGrabDevice(ClientPtr /* client */ , + int /* size */ , + xGrabDeviceReply * /* rep */ + ); + +#endif /* GRABDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevb.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEVB_H +#define GRABDEVB_H 1 + +int SProcXGrabDeviceButton(ClientPtr /* client */ + ); + +int ProcXGrabDeviceButton(ClientPtr /* client */ + ); + +#endif /* GRABDEVB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevk.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevk.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/grabdevk.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GRABDEVK_H +#define GRABDEVK_H 1 + +int SProcXGrabDeviceKey(ClientPtr /* client */ + ); + +int ProcXGrabDeviceKey(ClientPtr /* client */ + ); + +#endif /* GRABDEVK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gtmotion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gtmotion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/gtmotion.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef GTMOTION_H +#define GTMOTION_H 1 + +int SProcXGetDeviceMotionEvents(ClientPtr /* client */ + ); + +int ProcXGetDeviceMotionEvents(ClientPtr /* client */ + ); + +void SRepXGetDeviceMotionEvents(ClientPtr /* client */ , + int /* size */ , + xGetDeviceMotionEventsReply * /* rep */ + ); + +#endif /* GTMOTION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/hash.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/hash.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/hash.h (revision 51223) @@ -0,0 +1,40 @@ +/* + * + * Copyright 1995-1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/hash.h,v 1.2.2.2 1998/07/04 13:32:45 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _HASH_H +#define _HASH_H + +#include "loader.h" + +typedef struct _HashIterator { + itemPtr pItem; + int bucket; +} HashIteratorRec, *HashIteratorPtr; + +#endif /* _HASH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/help.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/help.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/help.h (revision 51223) @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +/* help string definitions */ +#define HELP_DEVICES "helpDevices" /* Configure Layout */ +#define HELP_SCREEN "helpScreen" /* Configure Screen */ +#define HELP_MODELINE "helpModeline" /* Configure Modeline */ +#define HELP_ACCESSX "helpAccessX" /* Configure AccessX */ + +/* + * Prototypes + */ +void Help(char*); +void HelpCancelAction(Widget, XEvent*, String*, Cardinal*); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/i2c_def.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/i2c_def.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/i2c_def.h (revision 51223) @@ -0,0 +1,29 @@ +#ifndef __I2C_DEF_H__ +#define __I2C_DEF_H__ + +/* the following are a workaround for possible loader bug.. + WATCH function types ! */ +#if XFree86LOADER + +#define CreateI2CBusRec ((pointer (*)(void))LoaderSymbol("xf86CreateI2CBusRec")) +#define DestroyI2CBusRec ((pointer (*)(I2CBusPtr, Bool, Bool))LoaderSymbol("xf86DestroyI2CBusRec")) +#define I2CBusInit ((Bool (*)(pointer))LoaderSymbol("xf86I2CBusInit")) +#define I2C_WriteRead ((Bool (*)(I2CDevPtr, I2CByte *, int, I2CByte *, int))LoaderSymbol("xf86I2CWriteRead")) +#define CreateI2CDevRec ((pointer (*)(void))LoaderSymbol("xf86CreateI2CDevRec")) +#define I2CDevInit ((Bool (*)(I2CDevPtr))LoaderSymbol("xf86I2CDevInit")) +#define I2CProbeAddress ((Bool (*)(I2CBusPtr,I2CSlaveAddr))LoaderSymbol("xf86I2CProbeAddress")) + +#else + +#define CreateI2CBusRec xf86CreateI2CBusRec +#define DestroyI2CBusRec xf86DestroyI2CBusRec +#define I2CBusInit xf86I2CBusInit +#define I2C_WriteRead xf86I2CWriteRead +#define CreateI2CDevRec xf86CreateI2CDevRec +#define I2CDevInit xf86I2CDevInit +#define I2CProbeAddress xf86I2CProbeAddress + +#endif + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ia64Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ia64Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ia64Pci.h (revision 51223) @@ -0,0 +1,46 @@ +/* + * Copyright 2004, Egbert Eich + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * EGBERT EICH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CON- + * NECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Egbert Eich shall not + * be used in advertising or otherwise to promote the sale, use or other deal- + *ings in this Software without prior written authorization from Egbert Eich. + * + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _IA64_PCI_H +# define _IA64_PCI_H + +#include "Pci.h" + +typedef enum { + NONE_CHIPSET, + I460GX_CHIPSET, + E8870_CHIPSET, + ZX1_CHIPSET, + ALTIX_CHIPSET +} IA64Chipset; + +# ifdef OS_PROBE_PCI_CHIPSET +extern IA64Chipset OS_PROBE_PCI_CHIPSET(scanpciWrapperOpt flags); +# endif +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ibmTrace.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ibmTrace.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ibmTrace.h (revision 51223) @@ -0,0 +1,10 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ibmTrace.h,v 1.1.2.1 1998/06/27 14:48:30 dawes Exp $ */ + + + + + +/* $XConsortium: ibmTrace.h /main/3 1996/02/21 17:56:27 kaleb $ */ + +#define TRACE(x) /* empty */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_dispatch.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_dispatch.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_dispatch.h (revision 51223) @@ -0,0 +1,931 @@ +/* DO NOT EDIT - This file generated automatically by glX_proto_recv.py (from Mesa) script */ + +/* + * (C) Copyright IBM Corporation 2005 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * IBM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined( _INDIRECT_DISPATCH_H_ ) +# define _INDIRECT_DISPATCH_H_ + +# if (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 3)) && defined(__ELF__) +# define HIDDEN __attribute__((visibility("hidden"))) +# else +# define HIDDEN +# endif +struct __GLXclientStateRec; + +extern HIDDEN void __glXDisp_MapGrid1d(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MapGrid1d(GLbyte * pc); +extern HIDDEN void __glXDisp_MapGrid1f(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MapGrid1f(GLbyte * pc); +extern HIDDEN int __glXDisp_NewList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_NewList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_LoadIdentity(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LoadIdentity(GLbyte * pc); +extern HIDDEN void __glXDisp_SampleCoverageARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SampleCoverageARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ConvolutionFilter1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionFilter1D(GLbyte * pc); +extern HIDDEN void __glXDisp_BeginQueryARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BeginQueryARB(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos3dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos3dv(GLbyte * pc); +extern HIDDEN void __glXDisp_PointParameteriNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PointParameteriNV(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord1iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord1iv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord4sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord4sv(GLbyte * pc); +extern HIDDEN void __glXDisp_ActiveTextureARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ActiveTextureARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4ubvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4ubvNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramNamedParameterdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramNamedParameterdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Histogram(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Histogram(GLbyte * pc); +extern HIDDEN int __glXDisp_GetMapfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMapfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_PolygonStipple(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PolygonStipple(GLbyte * pc); +extern HIDDEN int __glXDisp_GetPixelMapfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetPixelMapfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Color3uiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3uiv(GLbyte * pc); +extern HIDDEN int __glXDisp_IsEnabled(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsEnabled(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib4svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_EvalCoord2fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalCoord2fv(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramEnvParameter4dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramEnvParameter4dvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetMapiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMapiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Indexubv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Indexubv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetQueryivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetQueryivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexImage3D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexImage3D(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3ubv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3ubv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetQueryObjectivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetQueryObjectivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Vertex3dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex3dv(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexSubImage2DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexSubImage2DARB(GLbyte * pc); +extern HIDDEN void __glXDisp_LightModeliv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LightModeliv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib1svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs1dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs1dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Normal3bv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Normal3bv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexGeniv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGeniv(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex3iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex3iv(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyConvolutionFilter1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyConvolutionFilter1D(GLbyte * pc); +extern HIDDEN void __glXDisp_BlendColor(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BlendColor(GLbyte * pc); +extern HIDDEN void __glXDisp_CallLists(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CallLists(GLbyte * pc); +extern HIDDEN void __glXDisp_Normal3iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Normal3iv(GLbyte * pc); +extern HIDDEN void __glXDisp_PassThrough(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PassThrough(GLbyte * pc); +extern HIDDEN void __glXDisp_Viewport(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Viewport(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NusvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NusvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_PrioritizeTextures(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PrioritizeTextures(GLbyte * pc); +extern HIDDEN void __glXDisp_ResetHistogram(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ResetHistogram(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramNamedParameterfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramNamedParameterfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_PointParameterfEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PointParameterfEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramParameter4dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramParameter4dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord2sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord2sv(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex4dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex4dv(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexImage3DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexImage3DARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3sv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetConvolutionParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Vertex2dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex2dv(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord1fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord1fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord3iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord3iv(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3fv(GLbyte * pc); +extern HIDDEN void __glXDisp_PointSize(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PointSize(GLbyte * pc); +extern HIDDEN void __glXDisp_PopName(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PopName(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NbvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NbvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex4sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex4sv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexEnvfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexEnvfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexEnvi(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexEnvi(GLbyte * pc); +extern HIDDEN int __glXDisp_GetClipPlane(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetClipPlane(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttribs3dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs3dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs4fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs4fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Scaled(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Scaled(GLbyte * pc); +extern HIDDEN void __glXDisp_Scalef(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Scalef(GLbyte * pc); +extern HIDDEN void __glXDisp_AlphaFunc(GLbyte * pc); +extern HIDDEN void __glXDispSwap_AlphaFunc(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord2iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord2iv(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexImage1DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexImage1DARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Rotated(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rotated(GLbyte * pc); +extern HIDDEN int __glXDisp_ReadPixels(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_ReadPixels(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_EdgeFlagv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EdgeFlagv(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4iv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexParameterf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexParameterf(GLbyte * pc); +extern HIDDEN void __glXDisp_TexParameteri(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexParameteri(GLbyte * pc); +extern HIDDEN void __glXDisp_DrawPixels(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DrawPixels(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord2svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord2svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs3fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs3fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_GenerateMipmapEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_GenerateMipmapEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_GenLists(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenLists(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_MapGrid2d(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MapGrid2d(GLbyte * pc); +extern HIDDEN void __glXDisp_MapGrid2f(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MapGrid2f(GLbyte * pc); +extern HIDDEN void __glXDisp_Scissor(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Scissor(GLbyte * pc); +extern HIDDEN void __glXDisp_Fogf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Fogf(GLbyte * pc); +extern HIDDEN void __glXDisp_TexSubImage1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexSubImage1D(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4usv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4usv(GLbyte * pc); +extern HIDDEN void __glXDisp_Fogi(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Fogi(GLbyte * pc); +extern HIDDEN void __glXDisp_DepthRange(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DepthRange(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos3iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos3iv(GLbyte * pc); +extern HIDDEN void __glXDisp_PixelMapfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelMapfv(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3usv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3usv(GLbyte * pc); +extern HIDDEN void __glXDisp_DrawBuffersARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DrawBuffersARB(GLbyte * pc); +extern HIDDEN int __glXDisp_AreTexturesResident(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_AreTexturesResident(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_IsRenderbufferEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsRenderbufferEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ColorTableParameteriv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorTableParameteriv(GLbyte * pc); +extern HIDDEN void __glXDisp_PointParameterfvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PointParameterfvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3bv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3bv(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3bvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3bvEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramLocalParameterfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramLocalParameterfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_RenderbufferStorageEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RenderbufferStorageEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_ColorTable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorTable(GLbyte * pc); +extern HIDDEN void __glXDisp_Accum(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Accum(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexImage(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexImage(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ConvolutionFilter2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionFilter2D(GLbyte * pc); +extern HIDDEN int __glXDisp_Finish(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_Finish(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ClearStencil(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClearStencil(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib3dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ConvolutionParameteriv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionParameteriv(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos2fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos2fv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord1fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord1fv(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramEnvParameter4fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramEnvParameter4fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos4fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos4fv(GLbyte * pc); +extern HIDDEN void __glXDisp_ClearIndex(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClearIndex(GLbyte * pc); +extern HIDDEN void __glXDisp_LoadMatrixd(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LoadMatrixd(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos2dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos2dv(GLbyte * pc); +extern HIDDEN void __glXDisp_ConvolutionParameterfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionParameterfv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexGendv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexGendv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_LoadProgramNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LoadProgramNV(GLbyte * pc); +extern HIDDEN int __glXDisp_EndList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_EndList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib4fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_EvalCoord1fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalCoord1fv(GLbyte * pc); +extern HIDDEN void __glXDisp_EvalMesh2(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalMesh2(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex4fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex4fv(GLbyte * pc); +extern HIDDEN int __glXDisp_CheckFramebufferStatusEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_CheckFramebufferStatusEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetVertexAttribivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMinmax(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmax(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Normal3fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Normal3fv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4ivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4ivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_End(GLbyte * pc); +extern HIDDEN void __glXDispSwap_End(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs2dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs2dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord3fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord3fvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramParameterfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramParameterfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexSubImage2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexSubImage2D(GLbyte * pc); +extern HIDDEN void __glXDisp_DeleteRenderbuffersEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DeleteRenderbuffersEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_TexGenfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGenfv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4bvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4bvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_FramebufferTexture3DEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FramebufferTexture3DEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_BlendEquation(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BlendEquation(GLbyte * pc); +extern HIDDEN int __glXDisp_GetError(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetError(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexCoord3dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord3dv(GLbyte * pc); +extern HIDDEN void __glXDisp_Indexdv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Indexdv(GLbyte * pc); +extern HIDDEN void __glXDisp_PushName(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PushName(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord2dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord2dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramNamedParameter4fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramNamedParameter4fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord1svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord1svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_EndQueryARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EndQueryARB(GLbyte * pc); +extern HIDDEN void __glXDisp_DepthMask(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DepthMask(GLbyte * pc); +extern HIDDEN int __glXDisp_GetMaterialiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMaterialiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_StencilOp(GLbyte * pc); +extern HIDDEN void __glXDispSwap_StencilOp(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord3svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord3svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_TexEnvfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexEnvfv(GLbyte * pc); +extern HIDDEN void __glXDisp_LoadMatrixf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LoadMatrixf(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4bv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4bv(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3usvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3usvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib2fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramLocalParameter4dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramLocalParameter4dvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_DeleteLists(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_DeleteLists(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_LogicOp(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LogicOp(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord4fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord4fv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib2dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_FramebufferRenderbufferEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FramebufferRenderbufferEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib1dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1dvNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GenTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_FramebufferTexture1DEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FramebufferTexture1DEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramParameter4fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramParameter4fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos2sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos2sv(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4ubv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4ubv(GLbyte * pc); +extern HIDDEN void __glXDisp_DrawBuffer(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DrawBuffer(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord2fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord2fv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord1sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord1sv(GLbyte * pc); +extern HIDDEN void __glXDisp_DepthFunc(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DepthFunc(GLbyte * pc); +extern HIDDEN void __glXDisp_PixelMapusv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelMapusv(GLbyte * pc); +extern HIDDEN void __glXDisp_PointParameterivNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PointParameterivNV(GLbyte * pc); +extern HIDDEN void __glXDisp_BlendFunc(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BlendFunc(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord3dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord3dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramNamedParameter4dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramNamedParameter4dvNV(GLbyte * pc); +extern HIDDEN int __glXDisp_Flush(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_Flush(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Color4uiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4uiv(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos3sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos3sv(GLbyte * pc); +extern HIDDEN void __glXDisp_BindFramebufferEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BindFramebufferEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_PushAttrib(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PushAttrib(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4usvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4usvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_TexParameteriv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexParameteriv(GLbyte * pc); +extern HIDDEN void __glXDisp_WindowPos3fvMESA(GLbyte * pc); +extern HIDDEN void __glXDispSwap_WindowPos3fvMESA(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib1svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos3fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos3fv(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyTexSubImage3D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyTexSubImage3D(GLbyte * pc); +extern HIDDEN int __glXDisp_GetColorTable(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTable(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_SelectBuffer(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_SelectBuffer(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Indexiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Indexiv(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyColorTable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyColorTable(GLbyte * pc); +extern HIDDEN int __glXDisp_GetHistogramParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogramParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Frustum(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Frustum(GLbyte * pc); +extern HIDDEN int __glXDisp_GetString(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetString(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexEnvf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexEnvf(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord3ivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord3ivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib1dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1dvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_DeleteTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_DeleteTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetTexLevelParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexLevelParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ClearAccum(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClearAccum(GLbyte * pc); +extern HIDDEN int __glXDisp_GetVertexAttribfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_SecondaryColor3ivEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3ivEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord4iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord4iv(GLbyte * pc); +extern HIDDEN void __glXDisp_PolygonOffset(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PolygonOffset(GLbyte * pc); +extern HIDDEN void __glXDisp_SampleMaskSGIS(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SampleMaskSGIS(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4ubvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4ubvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyTexImage2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyTexImage2D(GLbyte * pc); +extern HIDDEN void __glXDisp_Lightfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Lightfv(GLbyte * pc); +extern HIDDEN void __glXDisp_ClearDepth(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClearDepth(GLbyte * pc); +extern HIDDEN void __glXDisp_ColorSubTable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorSubTable(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4fv(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord4ivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord4ivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Lightiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Lightiv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetQueryObjectuivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetQueryObjectuivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetTexParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GenRenderbuffersEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenRenderbuffersEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib2dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs2svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs2svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib2fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Rectdv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rectdv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Materialiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Materialiv(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3fvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3fvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_PolygonMode(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PolygonMode(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexSubImage1DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexSubImage1DARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetVertexAttribivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetProgramStringARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramStringARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexGeni(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGeni(GLbyte * pc); +extern HIDDEN void __glXDisp_TexGenf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGenf(GLbyte * pc); +extern HIDDEN void __glXDisp_TexGend(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGend(GLbyte * pc); +extern HIDDEN int __glXDisp_GetPolygonStipple(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetPolygonStipple(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetVertexAttribfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribfvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib2svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs1fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs1fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NuivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NuivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4sv(GLbyte * pc); +extern HIDDEN int __glXDisp_IsProgramNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsProgramNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_PixelZoom(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelZoom(GLbyte * pc); +extern HIDDEN void __glXDisp_ColorTableParameterfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorTableParameterfv(GLbyte * pc); +extern HIDDEN void __glXDisp_PixelMapuiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelMapuiv(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3dv(GLbyte * pc); +extern HIDDEN int __glXDisp_IsTexture(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsTexture(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_DeleteQueriesARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_DeleteQueriesARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMapdv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMapdv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_SamplePatternSGIS(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SamplePatternSGIS(GLbyte * pc); +extern HIDDEN int __glXDisp_PixelStoref(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_PixelStoref(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_IsQueryARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsQueryARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_PixelStorei(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_PixelStorei(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_EvalCoord2dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalCoord2dv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib3svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ColorMaterial(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorMaterial(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexSubImage3DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexSubImage3DARB(GLbyte * pc); +extern HIDDEN int __glXDisp_IsFramebufferEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsFramebufferEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetVertexAttribdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetSeparableFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetSeparableFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_RequestResidentProgramsNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RequestResidentProgramsNV(GLbyte * pc); +extern HIDDEN int __glXDisp_FeedbackBuffer(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_FeedbackBuffer(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_RasterPos2iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos2iv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexImage1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexImage1D(GLbyte * pc); +extern HIDDEN void __glXDisp_FrontFace(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FrontFace(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3ubvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3ubvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ExecuteProgramNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ExecuteProgramNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Normal3dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Normal3dv(GLbyte * pc); +extern HIDDEN void __glXDisp_Lightf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Lightf(GLbyte * pc); +extern HIDDEN void __glXDisp_MatrixMode(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MatrixMode(GLbyte * pc); +extern HIDDEN void __glXDisp_FramebufferTexture2DEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FramebufferTexture2DEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_GetPixelMapusv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetPixelMapusv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Lighti(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Lighti(GLbyte * pc); +extern HIDDEN int __glXDisp_GetFramebufferAttachmentParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetFramebufferAttachmentParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_MultiTexCoord4dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord4dvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetDoublev(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetDoublev(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_MultMatrixd(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultMatrixd(GLbyte * pc); +extern HIDDEN void __glXDisp_MultMatrixf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultMatrixf(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord4fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord4fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_TrackMatrixNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TrackMatrixNV(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos4sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos4sv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NsvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NsvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib3fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ClearColor(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClearColor(GLbyte * pc); +extern HIDDEN void __glXDisp_DeleteFramebuffersEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DeleteFramebuffersEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_TexEnviv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexEnviv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexSubImage3D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexSubImage3D(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3uivEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3uivEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_GetColorTableParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTableParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Bitmap(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Bitmap(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexLevelParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexLevelParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GenFramebuffersEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenFramebuffersEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetProgramParameterdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramParameterdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Vertex2sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex2sv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetIntegerv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetIntegerv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetProgramEnvParameterfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramEnvParameterfvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetTrackMatrixivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTrackMatrixivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib3svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3svNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexEnviv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexEnviv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_SeparableFilter2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SeparableFilter2D(GLbyte * pc); +extern HIDDEN void __glXDisp_Map1d(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Map1d(GLbyte * pc); +extern HIDDEN void __glXDisp_Map1f(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Map1f(GLbyte * pc); +extern HIDDEN void __glXDisp_CompressedTexImage2DARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CompressedTexImage2DARB(GLbyte * pc); +extern HIDDEN void __glXDisp_TexImage2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexImage2D(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramParameters4fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramParameters4fvNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramivNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMinmaxParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmaxParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_PixelTransferf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelTransferf(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyTexImage1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyTexImage1D(GLbyte * pc); +extern HIDDEN void __glXDisp_PushMatrix(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PushMatrix(GLbyte * pc); +extern HIDDEN void __glXDisp_Fogiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Fogiv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord1dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord1dv(GLbyte * pc); +extern HIDDEN void __glXDisp_PixelTransferi(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PixelTransferi(GLbyte * pc); +extern HIDDEN int __glXDisp_GetVertexAttribdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetVertexAttribdvNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib3fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Rotatef(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rotatef(GLbyte * pc); +extern HIDDEN void __glXDisp_Clear(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Clear(GLbyte * pc); +extern HIDDEN void __glXDisp_ReadBuffer(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ReadBuffer(GLbyte * pc); +extern HIDDEN void __glXDisp_ConvolutionParameteri(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionParameteri(GLbyte * pc); +extern HIDDEN void __glXDisp_Ortho(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Ortho(GLbyte * pc); +extern HIDDEN void __glXDisp_ListBase(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ListBase(GLbyte * pc); +extern HIDDEN void __glXDisp_ConvolutionParameterf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ConvolutionParameterf(GLbyte * pc); +extern HIDDEN int __glXDisp_GetColorTableParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTableParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ShadeModel(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ShadeModel(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs2fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs2fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Rectiv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rectiv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib1fvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1fvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3dvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3dvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex2fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex2fv(GLbyte * pc); +extern HIDDEN void __glXDisp_BindRenderbufferEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BindRenderbufferEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex3sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex3sv(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramLocalParameter4fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramLocalParameter4fvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_DeleteProgramsNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_DeleteProgramsNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_EvalMesh1(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalMesh1(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord1dvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord1dvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex2iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex2iv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramStringNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramStringNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_LineWidth(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LineWidth(GLbyte * pc); +extern HIDDEN void __glXDisp_TexGendv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexGendv(GLbyte * pc); +extern HIDDEN void __glXDisp_ResetMinmax(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ResetMinmax(GLbyte * pc); +extern HIDDEN int __glXDisp_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetConvolutionParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttribs4dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs4dvNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GetMaterialfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMaterialfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_CallList(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CallList(GLbyte * pc); +extern HIDDEN void __glXDisp_Materialfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Materialfv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord3fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord3fv(GLbyte * pc); +extern HIDDEN void __glXDisp_FogCoordfvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FogCoordfvEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord1ivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord1ivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord2ivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord2ivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyTexSubImage2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyTexSubImage2D(GLbyte * pc); +extern HIDDEN void __glXDisp_Color3iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color3iv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramLocalParameterdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramLocalParameterdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetHistogramParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogramParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetConvolutionFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetProgramivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramivARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_BlendFuncSeparateEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BlendFuncSeparateEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramParameters4dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramParameters4dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_EvalPoint2(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalPoint2(GLbyte * pc); +extern HIDDEN void __glXDisp_EvalPoint1(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalPoint1(GLbyte * pc); +extern HIDDEN void __glXDisp_PopMatrix(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PopMatrix(GLbyte * pc); +extern HIDDEN int __glXDisp_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetTexGeniv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexGeniv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Map2d(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Map2d(GLbyte * pc); +extern HIDDEN void __glXDisp_Map2f(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Map2f(GLbyte * pc); +extern HIDDEN void __glXDisp_ProgramStringARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ProgramStringARB(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos4dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos4dv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetCompressedTexImageARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetCompressedTexImageARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetTexGenfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexGenfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetHistogram(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogram(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_ActiveStencilFaceEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ActiveStencilFaceEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_Materialf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Materialf(GLbyte * pc); +extern HIDDEN void __glXDisp_Materiali(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Materiali(GLbyte * pc); +extern HIDDEN void __glXDisp_Indexsv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Indexsv(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord4svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord4svARB(GLbyte * pc); +extern HIDDEN void __glXDisp_LightModelfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LightModelfv(GLbyte * pc); +extern HIDDEN void __glXDisp_TexCoord2dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord2dv(GLbyte * pc); +extern HIDDEN int __glXDisp_GenQueriesARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenQueriesARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_EvalCoord1dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_EvalCoord1dv(GLbyte * pc); +extern HIDDEN void __glXDisp_Translated(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Translated(GLbyte * pc); +extern HIDDEN void __glXDisp_Translatef(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Translatef(GLbyte * pc); +extern HIDDEN void __glXDisp_StencilMask(GLbyte * pc); +extern HIDDEN void __glXDispSwap_StencilMask(GLbyte * pc); +extern HIDDEN int __glXDisp_GetLightiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetLightiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_IsList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsList(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_RenderMode(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_RenderMode(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_LoadName(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LoadName(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs4ubvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs4ubvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyTexSubImage1D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyTexSubImage1D(GLbyte * pc); +extern HIDDEN void __glXDisp_CullFace(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CullFace(GLbyte * pc); +extern HIDDEN void __glXDisp_BindTexture(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BindTexture(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs3svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs3svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_StencilFunc(GLbyte * pc); +extern HIDDEN void __glXDispSwap_StencilFunc(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyPixels(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyPixels(GLbyte * pc); +extern HIDDEN void __glXDisp_Rectsv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rectsv(GLbyte * pc); +extern HIDDEN void __glXDisp_CopyConvolutionFilter2D(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyConvolutionFilter2D(GLbyte * pc); +extern HIDDEN void __glXDisp_TexParameterfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexParameterfv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4uivARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4uivARB(GLbyte * pc); +extern HIDDEN void __glXDisp_ClipPlane(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ClipPlane(GLbyte * pc); +extern HIDDEN int __glXDisp_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetPixelMapuiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetPixelMapuiv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Indexfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Indexfv(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3svEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3svEXT(GLbyte * pc); +extern HIDDEN void __glXDisp_IndexMask(GLbyte * pc); +extern HIDDEN void __glXDispSwap_IndexMask(GLbyte * pc); +extern HIDDEN void __glXDisp_BindProgramNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BindProgramNV(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4svARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetFloatv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetFloatv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexCoord3sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord3sv(GLbyte * pc); +extern HIDDEN void __glXDisp_PopAttrib(GLbyte * pc); +extern HIDDEN void __glXDispSwap_PopAttrib(GLbyte * pc); +extern HIDDEN void __glXDisp_Fogfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Fogfv(GLbyte * pc); +extern HIDDEN void __glXDisp_InitNames(GLbyte * pc); +extern HIDDEN void __glXDispSwap_InitNames(GLbyte * pc); +extern HIDDEN void __glXDisp_Normal3sv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Normal3sv(GLbyte * pc); +extern HIDDEN void __glXDisp_Minmax(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Minmax(GLbyte * pc); +extern HIDDEN void __glXDisp_FogCoorddvEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_FogCoorddvEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_GetBooleanv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetBooleanv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Hint(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Hint(GLbyte * pc); +extern HIDDEN void __glXDisp_Color4dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Color4dv(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib2svARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2svARB(GLbyte * pc); +extern HIDDEN int __glXDisp_AreProgramsResidentNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_AreProgramsResidentNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_CopyColorSubTable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_CopyColorSubTable(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib4NubvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4NubvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib3dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib3dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex4iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex4iv(GLbyte * pc); +extern HIDDEN int __glXDisp_GetProgramEnvParameterdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetProgramEnvParameterdvARB(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_TexCoord4dv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_TexCoord4dv(GLbyte * pc); +extern HIDDEN void __glXDisp_Begin(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Begin(GLbyte * pc); +extern HIDDEN void __glXDisp_LightModeli(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LightModeli(GLbyte * pc); +extern HIDDEN void __glXDisp_Rectfv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Rectfv(GLbyte * pc); +extern HIDDEN void __glXDisp_LightModelf(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LightModelf(GLbyte * pc); +extern HIDDEN int __glXDisp_GetTexParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetTexParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetLightfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetLightfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_Disable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Disable(GLbyte * pc); +extern HIDDEN void __glXDisp_MultiTexCoord2fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_MultiTexCoord2fvARB(GLbyte * pc); +extern HIDDEN int __glXDisp_GetRenderbufferParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetRenderbufferParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_DrawArrays(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DrawArrays(GLbyte * pc); +extern HIDDEN void __glXDisp_ColorMask(GLbyte * pc); +extern HIDDEN void __glXDispSwap_ColorMask(GLbyte * pc); +extern HIDDEN void __glXDisp_RasterPos4iv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_RasterPos4iv(GLbyte * pc); +extern HIDDEN void __glXDisp_Enable(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Enable(GLbyte * pc); +extern HIDDEN void __glXDisp_LineStipple(GLbyte * pc); +extern HIDDEN void __glXDispSwap_LineStipple(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs4svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs4svNV(GLbyte * pc); +extern HIDDEN int __glXDisp_GetMinmaxParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmaxParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib1fvARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib1fvARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttribs1svNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttribs1svNV(GLbyte * pc); +extern HIDDEN void __glXDisp_Vertex3fv(GLbyte * pc); +extern HIDDEN void __glXDispSwap_Vertex3fv(GLbyte * pc); +extern HIDDEN int __glXDisp_GenProgramsNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenProgramsNV(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_VertexAttrib4dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib4dvNV(GLbyte * pc); + +# undef HIDDEN + +#endif /* !defined( _INDIRECT_DISPATCH_H_ ) */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_reqsize.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_reqsize.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_reqsize.h (revision 51223) @@ -0,0 +1,121 @@ +/* DO NOT EDIT - This file generated automatically by glX_proto_size.py (from Mesa) script */ + +/* + * (C) Copyright IBM Corporation 2005 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * IBM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined( _INDIRECT_REQSIZE_H_ ) +# define _INDIRECT_REQSIZE_H_ + +# if (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 3)) && defined(__ELF__) +# define HIDDEN __attribute__((visibility("hidden"))) +# else +# define HIDDEN +# endif + +# if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 96) +# define PURE __attribute__((pure)) +# else +# define PURE +# endif + +extern PURE HIDDEN int __glXCallListsReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXBitmapReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXFogfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXFogivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXLightfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXLightivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXLightModelfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXLightModelivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMaterialfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMaterialivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPolygonStippleReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexParameterfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexParameterivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexImage1DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexImage2DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexEnvfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexEnvivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexGendvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexGenfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexGenivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMap1dReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMap1fReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMap2dReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXMap2fReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPixelMapfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPixelMapuivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPixelMapusvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXDrawPixelsReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXDrawArraysReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPrioritizeTexturesReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexSubImage1DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexSubImage2DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXColorTableReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXColorTableParameterfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXColorTableParameterivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXColorSubTableReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXConvolutionFilter1DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXConvolutionFilter2DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXConvolutionParameterfvReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXConvolutionParameterivReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXSeparableFilter2DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexImage3DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXTexSubImage3DReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXDrawBuffersARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPointParameterfvEXTReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexImage3DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexImage2DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexImage1DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexSubImage3DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexSubImage2DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXCompressedTexSubImage1DARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXLoadProgramNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXProgramParameters4dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXProgramParameters4fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXRequestResidentProgramsNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs1dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs1fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs1svNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs2dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs2fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs2svNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs3dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs3fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs3svNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs4dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs4fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs4svNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXVertexAttribs4ubvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXPointParameterivNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXProgramStringARBReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXProgramNamedParameter4fvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXProgramNamedParameter4dvNVReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXDeleteRenderbuffersEXTReqSize(const GLbyte *pc, Bool swap); +extern PURE HIDDEN int __glXDeleteFramebuffersEXTReqSize(const GLbyte *pc, Bool swap); + +# undef HIDDEN +# undef PURE + +#endif /* !defined( _INDIRECT_REQSIZE_H_ ) */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_size_get.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_size_get.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_size_get.h (revision 51223) @@ -0,0 +1,99 @@ +/* DO NOT EDIT - This file generated automatically by glX_proto_size.py (from Mesa) script */ + +/* + * (C) Copyright IBM Corporation 2004 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * IBM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined( _INDIRECT_SIZE_GET_H_ ) +# define _INDIRECT_SIZE_GET_H_ + +/** + * \file + * Prototypes for functions used to determine the number of data elements in + * various GLX protocol messages. + * + * \author Ian Romanick + */ + +# if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 96) +# define PURE __attribute__((pure)) +# else +# define PURE +# endif + +# if defined(__i386__) && defined(__GNUC__) && !defined(__CYGWIN__) && !defined(__MINGW32__) +# define FASTCALL __attribute__((fastcall)) +# else +# define FASTCALL +# endif + +# if (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 3)) && defined(__ELF__) +# define INTERNAL __attribute__((visibility("internal"))) +# else +# define INTERNAL +# endif + +extern INTERNAL PURE FASTCALL GLint __glGetBooleanv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetDoublev_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetFloatv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetIntegerv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetLightfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetLightiv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetMaterialfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetMaterialiv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexEnvfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexEnviv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexGendv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexGenfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexGeniv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexLevelParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetTexLevelParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetConvolutionParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetConvolutionParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetHistogramParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetHistogramParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetMinmaxParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetMinmaxParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetProgramivNV_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribdvARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribfvARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribivARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetProgramivARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetQueryivARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetQueryObjectivARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetQueryObjectuivARB_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribdvNV_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribfvNV_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribivNV_size(GLenum); +extern INTERNAL PURE FASTCALL GLint __glGetFramebufferAttachmentParameterivEXT_size(GLenum); + +# undef PURE +# undef FASTCALL +# undef INTERNAL + +#endif /* !defined( _INDIRECT_SIZE_GET_H_ ) */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_util.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_util.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/indirect_util.h (revision 51223) @@ -0,0 +1,43 @@ +/* + * (C) Copyright IBM Corporation 2005 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * IBM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __GLX_INDIRECT_UTIL_H__ +#define __GLX_INDIRECT_UTIL_H__ + +extern GLint __glGetBooleanv_variable_size( GLenum e ); + +extern void * __glXGetAnswerBuffer( __GLXclientState * cl, + size_t required_size, void * local_buffer, size_t local_size, + unsigned alignment ); + +extern void __glXSendReply( ClientPtr client, const void * data, + size_t elements, size_t element_size, GLboolean always_array, + CARD32 retval ); + +extern void __glXSendReplySwap( ClientPtr client, const void * data, + size_t elements, size_t element_size, GLboolean always_array, + CARD32 retval ); + +#endif /* __GLX_INDIRECT_UTIL_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/input.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/input.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/input.h (revision 51223) @@ -0,0 +1,391 @@ +/* $Xorg: input.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/include/input.h,v 3.8 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef INPUT_H +#define INPUT_H + +#include "misc.h" +#include "screenint.h" +#include +#include +#include "window.h" /* for WindowPtr */ + +#define DEVICE_INIT 0 +#define DEVICE_ON 1 +#define DEVICE_OFF 2 +#define DEVICE_CLOSE 3 + +#define MAP_LENGTH 256 +#define DOWN_LENGTH 32 /* 256/8 => number of bytes to hold 256 bits */ +#define NullGrab ((GrabPtr)NULL) +#define PointerRootWin ((WindowPtr)PointerRoot) +#define NoneWin ((WindowPtr)None) +#define NullDevice ((DevicePtr)NULL) + +#ifndef FollowKeyboard +#define FollowKeyboard 3 +#endif +#ifndef FollowKeyboardWin +#define FollowKeyboardWin ((WindowPtr) FollowKeyboard) +#endif +#ifndef RevertToFollowKeyboard +#define RevertToFollowKeyboard 3 +#endif + +typedef unsigned long Leds; +typedef struct _OtherClients *OtherClientsPtr; +typedef struct _InputClients *InputClientsPtr; +typedef struct _DeviceIntRec *DeviceIntPtr; + +typedef int (*DeviceProc)( + DeviceIntPtr /*device*/, + int /*what*/); + +typedef void (*ProcessInputProc)( + xEventPtr /*events*/, + DeviceIntPtr /*device*/, + int /*count*/); + +typedef Bool (*DeviceHandleProc)( + DeviceIntPtr /*device*/, + void* /*data*/ + ); + +typedef void (*DeviceUnwrapProc)( + DeviceIntPtr /*device*/, + DeviceHandleProc /*proc*/, + void* /*data*/ + ); + +typedef struct _DeviceRec { + pointer devicePrivate; + ProcessInputProc processInputProc; /* current */ + ProcessInputProc realInputProc; /* deliver */ + ProcessInputProc enqueueInputProc; /* enqueue */ + Bool on; /* used by DDX to keep state */ +} DeviceRec, *DevicePtr; + +typedef struct { + int click, bell, bell_pitch, bell_duration; + Bool autoRepeat; + unsigned char autoRepeats[32]; + Leds leds; + unsigned char id; +} KeybdCtrl; + +typedef struct { + KeySym *map; + KeyCode minKeyCode, + maxKeyCode; + int mapWidth; +} KeySymsRec, *KeySymsPtr; + +typedef struct { + int num, den, threshold; + unsigned char id; +} PtrCtrl; + +typedef struct { + int resolution, min_value, max_value; + int integer_displayed; + unsigned char id; +} IntegerCtrl; + +typedef struct { + int max_symbols, num_symbols_supported; + int num_symbols_displayed; + KeySym *symbols_supported; + KeySym *symbols_displayed; + unsigned char id; +} StringCtrl; + +typedef struct { + int percent, pitch, duration; + unsigned char id; +} BellCtrl; + +typedef struct { + Leds led_values; + Mask led_mask; + unsigned char id; +} LedCtrl; + +extern int AllocateDevicePrivateIndex(void); +extern Bool AllocateDevicePrivate(DeviceIntPtr device, int index); +extern void ResetDevicePrivateIndex(void); + +extern KeybdCtrl defaultKeyboardControl; +extern PtrCtrl defaultPointerControl; + +#undef AddInputDevice +extern DevicePtr AddInputDevice( + DeviceProc /*deviceProc*/, + Bool /*autoStart*/); + +#define AddInputDevice(deviceProc, autoStart) \ + _AddInputDevice(deviceProc, autoStart) + +extern DeviceIntPtr _AddInputDevice( + DeviceProc /*deviceProc*/, + Bool /*autoStart*/); + +extern Bool EnableDevice( + DeviceIntPtr /*device*/); + +extern Bool DisableDevice( + DeviceIntPtr /*device*/); + +extern int InitAndStartDevices(void); + +extern void CloseDownDevices(void); + +extern void RemoveDevice( + DeviceIntPtr /*dev*/); + +extern int NumMotionEvents(void); + +#undef RegisterPointerDevice +extern void RegisterPointerDevice( + DevicePtr /*device*/); + +#define RegisterPointerDevice(device) \ + _RegisterPointerDevice(device) + +extern void _RegisterPointerDevice( + DeviceIntPtr /*device*/); + +#undef RegisterKeyboardDevice +extern void RegisterKeyboardDevice( + DevicePtr /*device*/); + +#define RegisterKeyboardDevice(device) \ + _RegisterKeyboardDevice(device) + +extern void _RegisterKeyboardDevice( + DeviceIntPtr /*device*/); + +extern DevicePtr LookupKeyboardDevice(void); + +extern DevicePtr LookupPointerDevice(void); + +extern DevicePtr LookupDevice( + int /* id */); + +extern void QueryMinMaxKeyCodes( + KeyCode* /*minCode*/, + KeyCode* /*maxCode*/); + +extern Bool SetKeySymsMap( + KeySymsPtr /*dst*/, + KeySymsPtr /*src*/); + +extern Bool InitKeyClassDeviceStruct( + DeviceIntPtr /*device*/, + KeySymsPtr /*pKeySyms*/, + CARD8 /*pModifiers*/[]); + +extern Bool InitButtonClassDeviceStruct( + DeviceIntPtr /*device*/, + int /*numButtons*/, + CARD8* /*map*/); + +typedef int (*ValuatorMotionProcPtr)( + DeviceIntPtr /*pdevice*/, + xTimecoord * /*coords*/, + unsigned long /*start*/, + unsigned long /*stop*/, + ScreenPtr /*pScreen*/); + +extern Bool InitValuatorClassDeviceStruct( + DeviceIntPtr /*device*/, + int /*numAxes*/, + ValuatorMotionProcPtr /* motionProc */, + int /*numMotionEvents*/, + int /*mode*/); + +extern Bool InitFocusClassDeviceStruct( + DeviceIntPtr /*device*/); + +typedef void (*BellProcPtr)( + int /*percent*/, + DeviceIntPtr /*device*/, + pointer /*ctrl*/, + int); + +typedef void (*KbdCtrlProcPtr)( + DeviceIntPtr /*device*/, + KeybdCtrl * /*ctrl*/); + +extern Bool InitKbdFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + BellProcPtr /*bellProc*/, + KbdCtrlProcPtr /*controlProc*/); + +typedef void (*PtrCtrlProcPtr)( + DeviceIntPtr /*device*/, + PtrCtrl * /*ctrl*/); + +extern Bool InitPtrFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + PtrCtrlProcPtr /*controlProc*/); + +typedef void (*StringCtrlProcPtr)( + DeviceIntPtr /*device*/, + StringCtrl * /*ctrl*/); + +extern Bool InitStringFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + StringCtrlProcPtr /*controlProc*/, + int /*max_symbols*/, + int /*num_symbols_supported*/, + KeySym* /*symbols*/); + +typedef void (*BellCtrlProcPtr)( + DeviceIntPtr /*device*/, + BellCtrl * /*ctrl*/); + +extern Bool InitBellFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + BellProcPtr /*bellProc*/, + BellCtrlProcPtr /*controlProc*/); + +typedef void (*LedCtrlProcPtr)( + DeviceIntPtr /*device*/, + LedCtrl * /*ctrl*/); + +extern Bool InitLedFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + LedCtrlProcPtr /*controlProc*/); + +typedef void (*IntegerCtrlProcPtr)( + DeviceIntPtr /*device*/, + IntegerCtrl * /*ctrl*/); + + +extern Bool InitIntegerFeedbackClassDeviceStruct( + DeviceIntPtr /*device*/, + IntegerCtrlProcPtr /*controlProc*/); + +extern Bool InitPointerDeviceStruct( + DevicePtr /*device*/, + CARD8* /*map*/, + int /*numButtons*/, + ValuatorMotionProcPtr /*motionProc*/, + PtrCtrlProcPtr /*controlProc*/, + int /*numMotionEvents*/); + +extern Bool InitKeyboardDeviceStruct( + DevicePtr /*device*/, + KeySymsPtr /*pKeySyms*/, + CARD8 /*pModifiers*/[], + BellProcPtr /*bellProc*/, + KbdCtrlProcPtr /*controlProc*/); + +extern void SendMappingNotify( + unsigned int /*request*/, + unsigned int /*firstKeyCode*/, + unsigned int /*count*/, + ClientPtr /* client */); + +extern Bool BadDeviceMap( + BYTE* /*buff*/, + int /*length*/, + unsigned /*low*/, + unsigned /*high*/, + XID* /*errval*/); + +extern Bool AllModifierKeysAreUp( + DeviceIntPtr /*device*/, + CARD8* /*map1*/, + int /*per1*/, + CARD8* /*map2*/, + int /*per2*/); + +extern void NoteLedState( + DeviceIntPtr /*keybd*/, + int /*led*/, + Bool /*on*/); + +extern void MaybeStopHint( + DeviceIntPtr /*device*/, + ClientPtr /*client*/); + +extern void ProcessPointerEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*mouse*/, + int /*count*/); + +extern void ProcessKeyboardEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*keybd*/, + int /*count*/); + +#ifdef XKB +extern void CoreProcessPointerEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*mouse*/, + int /*count*/); + +extern void CoreProcessKeyboardEvent( + xEventPtr /*xE*/, + DeviceIntPtr /*keybd*/, + int /*count*/); +#endif + +extern Bool LegalModifier( + unsigned int /*key*/, + DevicePtr /*pDev*/); + +extern void ProcessInputEvents(void); + +extern void InitInput( + int /*argc*/, + char ** /*argv*/); + +#endif /* INPUT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/inputstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/inputstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/inputstr.h (revision 51223) @@ -0,0 +1,314 @@ +/* $XFree86: xc/programs/Xserver/include/inputstr.h,v 1.6 2003/04/27 21:31:04 herrb Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ + +/* $Xorg: inputstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef INPUTSTRUCT_H +#define INPUTSTRUCT_H + +#include "input.h" +#include "window.h" +#include "dixstruct.h" + +#define BitIsOn(ptr, bit) (((BYTE *) (ptr))[(bit)>>3] & (1 << ((bit) & 7))) + +#define SameClient(obj,client) \ + (CLIENT_BITS((obj)->resource) == (client)->clientAsMask) + +#define MAX_DEVICES 20 + +#define EMASKSIZE MAX_DEVICES + +/* Kludge: OtherClients and InputClients must be compatible, see code */ + +typedef struct _OtherClients { + OtherClientsPtr next; + XID resource; /* id for putting into resource manager */ + Mask mask; +} OtherClients; + +typedef struct _InputClients { + InputClientsPtr next; + XID resource; /* id for putting into resource manager */ + Mask mask[EMASKSIZE]; +} InputClients; + +typedef struct _OtherInputMasks { + Mask deliverableEvents[EMASKSIZE]; + Mask inputEvents[EMASKSIZE]; + Mask dontPropagateMask[EMASKSIZE]; + InputClientsPtr inputClients; +} OtherInputMasks; + +/* + * The following structure gets used for both active and passive grabs. For + * active grabs some of the fields (e.g. modifiers) are not used. However, + * that is not much waste since there aren't many active grabs (one per + * keyboard/pointer device) going at once in the server. + */ + +#define MasksPerDetailMask 8 /* 256 keycodes and 256 possible + modifier combinations, but only + 3 buttons. */ + + typedef struct _DetailRec { /* Grab details may be bit masks */ + unsigned short exact; + Mask *pMask; + } DetailRec; + + typedef struct _GrabRec { + GrabPtr next; /* for chain of passive grabs */ + XID resource; + DeviceIntPtr device; + WindowPtr window; + unsigned ownerEvents:1; + unsigned keyboardMode:1; + unsigned pointerMode:1; + unsigned coreGrab:1; /* grab is on core device */ + unsigned coreMods:1; /* modifiers are on core keyboard */ + CARD8 type; /* event type */ + DetailRec modifiersDetail; + DeviceIntPtr modifierDevice; + DetailRec detail; /* key or button */ + WindowPtr confineTo; /* always NULL for keyboards */ + CursorPtr cursor; /* always NULL for keyboards */ + Mask eventMask; +} GrabRec; + +typedef struct _KeyClassRec { + CARD8 down[DOWN_LENGTH]; + KeyCode *modifierKeyMap; + KeySymsRec curKeySyms; + int modifierKeyCount[8]; + CARD8 modifierMap[MAP_LENGTH]; + CARD8 maxKeysPerModifier; + unsigned short state; + unsigned short prev_state; +#ifdef XKB + struct _XkbSrvInfo *xkbInfo; +#endif +} KeyClassRec, *KeyClassPtr; + +typedef struct _AxisInfo { + int resolution; + int min_resolution; + int max_resolution; + int min_value; + int max_value; +} AxisInfo, *AxisInfoPtr; + +typedef struct _ValuatorClassRec { + ValuatorMotionProcPtr GetMotionProc; + int numMotionEvents; + WindowPtr motionHintWindow; + AxisInfoPtr axes; + unsigned short numAxes; + int *axisVal; + CARD8 mode; +} ValuatorClassRec, *ValuatorClassPtr; + +typedef struct _ButtonClassRec { + CARD8 numButtons; + CARD8 buttonsDown; /* number of buttons currently down */ + unsigned short state; + Mask motionMask; + CARD8 down[DOWN_LENGTH]; + CARD8 map[MAP_LENGTH]; +#ifdef XKB + union _XkbAction * xkb_acts; +#endif +} ButtonClassRec, *ButtonClassPtr; + +typedef struct _FocusClassRec { + WindowPtr win; + int revert; + TimeStamp time; + WindowPtr *trace; + int traceSize; + int traceGood; +} FocusClassRec, *FocusClassPtr; + +typedef struct _ProximityClassRec { + char pad; +} ProximityClassRec, *ProximityClassPtr; + +typedef struct _KbdFeedbackClassRec *KbdFeedbackPtr; +typedef struct _PtrFeedbackClassRec *PtrFeedbackPtr; +typedef struct _IntegerFeedbackClassRec *IntegerFeedbackPtr; +typedef struct _StringFeedbackClassRec *StringFeedbackPtr; +typedef struct _BellFeedbackClassRec *BellFeedbackPtr; +typedef struct _LedFeedbackClassRec *LedFeedbackPtr; + +typedef struct _KbdFeedbackClassRec { + BellProcPtr BellProc; + KbdCtrlProcPtr CtrlProc; + KeybdCtrl ctrl; + KbdFeedbackPtr next; +#ifdef XKB + struct _XkbSrvLedInfo *xkb_sli; +#endif +} KbdFeedbackClassRec; + +typedef struct _PtrFeedbackClassRec { + PtrCtrlProcPtr CtrlProc; + PtrCtrl ctrl; + PtrFeedbackPtr next; +} PtrFeedbackClassRec; + +typedef struct _IntegerFeedbackClassRec { + IntegerCtrlProcPtr CtrlProc; + IntegerCtrl ctrl; + IntegerFeedbackPtr next; +} IntegerFeedbackClassRec; + +typedef struct _StringFeedbackClassRec { + StringCtrlProcPtr CtrlProc; + StringCtrl ctrl; + StringFeedbackPtr next; +} StringFeedbackClassRec; + +typedef struct _BellFeedbackClassRec { + BellProcPtr BellProc; + BellCtrlProcPtr CtrlProc; + BellCtrl ctrl; + BellFeedbackPtr next; +} BellFeedbackClassRec; + +typedef struct _LedFeedbackClassRec { + LedCtrlProcPtr CtrlProc; + LedCtrl ctrl; + LedFeedbackPtr next; +#ifdef XKB + struct _XkbSrvLedInfo *xkb_sli; +#endif +} LedFeedbackClassRec; + +/* states for devices */ + +#define NOT_GRABBED 0 +#define THAWED 1 +#define THAWED_BOTH 2 /* not a real state */ +#define FREEZE_NEXT_EVENT 3 +#define FREEZE_BOTH_NEXT_EVENT 4 +#define FROZEN 5 /* any state >= has device frozen */ +#define FROZEN_NO_EVENT 5 +#define FROZEN_WITH_EVENT 6 +#define THAW_OTHERS 7 + +typedef struct _DeviceIntRec { + DeviceRec public; + DeviceIntPtr next; + TimeStamp grabTime; + Bool startup; /* true if needs to be turned on at + server intialization time */ + DeviceProc deviceProc; /* proc(DevicePtr, DEVICE_xx). It is + used to initialize, turn on, or + turn off the device */ + Bool inited; /* TRUE if INIT returns Success */ + GrabPtr grab; /* the grabber - used by DIX */ + struct { + Bool frozen; + int state; + GrabPtr other; /* if other grab has this frozen */ + xEvent *event; /* saved to be replayed */ + int evcount; + } sync; + Atom type; + char *name; + CARD8 id; + CARD8 activatingKey; + Bool fromPassiveGrab; + GrabRec activeGrab; + void (*ActivateGrab) ( + DeviceIntPtr /*device*/, + GrabPtr /*grab*/, + TimeStamp /*time*/, + Bool /*autoGrab*/); + void (*DeactivateGrab)( + DeviceIntPtr /*device*/); + KeyClassPtr key; + ValuatorClassPtr valuator; + ButtonClassPtr button; + FocusClassPtr focus; + ProximityClassPtr proximity; + KbdFeedbackPtr kbdfeed; + PtrFeedbackPtr ptrfeed; + IntegerFeedbackPtr intfeed; + StringFeedbackPtr stringfeed; + BellFeedbackPtr bell; + LedFeedbackPtr leds; +#ifdef XKB + struct _XkbInterest * xkb_interest; +#endif + DevUnion *devPrivates; + int nPrivates; + DeviceUnwrapProc unwrapProc; +} DeviceIntRec; + +typedef struct { + int numDevices; /* total number of devices */ + DeviceIntPtr devices; /* all devices turned on */ + DeviceIntPtr off_devices; /* all devices turned off */ + DeviceIntPtr keyboard; /* the main one for the server */ + DeviceIntPtr pointer; +} InputInfo; + +extern InputInfo inputInfo; + +/* for keeping the events for devices grabbed synchronously */ +typedef struct _QdEvent *QdEventPtr; +typedef struct _QdEvent { + QdEventPtr next; + DeviceIntPtr device; + ScreenPtr pScreen; /* what screen the pointer was on */ + unsigned long months; /* milliseconds is in the event */ + xEvent *event; + int evcount; +} QdEventRec; + +#endif /* INPUTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/int10Defines.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/int10Defines.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/int10Defines.h (revision 51223) @@ -0,0 +1,90 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/int10Defines.h,v 1.4 2003/08/24 17:37:03 dawes Exp $ */ +/* + * Copyright (c) 2000-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _INT10DEFINES_H_ +#define _INT10DEFINES_H_ 1 + +#ifdef _VM86_LINUX + +#include + +#define CPU_R(type,name,num) \ + (((type *)&(((struct vm86_struct *)REG->cpuRegs)->regs.name))[num]) +#define CPU_RD(name,num) CPU_R(CARD32,name,num) +#define CPU_RW(name,num) CPU_R(CARD16,name,num) +#define CPU_RB(name,num) CPU_R(CARD8,name,num) + +#define X86_EAX CPU_RD(eax,0) +#define X86_EBX CPU_RD(ebx,0) +#define X86_ECX CPU_RD(ecx,0) +#define X86_EDX CPU_RD(edx,0) +#define X86_ESI CPU_RD(esi,0) +#define X86_EDI CPU_RD(edi,0) +#define X86_EBP CPU_RD(ebp,0) +#define X86_EIP CPU_RD(eip,0) +#define X86_ESP CPU_RD(esp,0) +#define X86_EFLAGS CPU_RD(eflags,0) + +#define X86_FLAGS CPU_RW(eflags,0) +#define X86_AX CPU_RW(eax,0) +#define X86_BX CPU_RW(ebx,0) +#define X86_CX CPU_RW(ecx,0) +#define X86_DX CPU_RW(edx,0) +#define X86_SI CPU_RW(esi,0) +#define X86_DI CPU_RW(edi,0) +#define X86_BP CPU_RW(ebp,0) +#define X86_IP CPU_RW(eip,0) +#define X86_SP CPU_RW(esp,0) +#define X86_CS CPU_RW(cs,0) +#define X86_DS CPU_RW(ds,0) +#define X86_ES CPU_RW(es,0) +#define X86_SS CPU_RW(ss,0) +#define X86_FS CPU_RW(fs,0) +#define X86_GS CPU_RW(gs,0) + +#define X86_AL CPU_RB(eax,0) +#define X86_BL CPU_RB(ebx,0) +#define X86_CL CPU_RB(ecx,0) +#define X86_DL CPU_RB(edx,0) + +#define X86_AH CPU_RB(eax,1) +#define X86_BH CPU_RB(ebx,1) +#define X86_CH CPU_RB(ecx,1) +#define X86_DH CPU_RB(edx,1) + +#elif defined(_X86EMU) + +#include "xf86x86emu.h" + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keyboard-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keyboard-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keyboard-cfg.h (revision 51223) @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/keyboard-cfg.h,v 1.2 2000/06/13 23:15:51 dawes Exp $ + */ + +#include "config.h" +#include + +#ifndef _xf86cfg_keyboard_h +#define _xf86cfg_keyboard_h + +/* + * All file names are from XProjectRoot or XWINHOME environment variable. + */ +#define XkbConfigDir "share/X11/xkb/" +#define XkbConfigFile "X0-config.keyboard" + +/* + * Types + */ +typedef struct { + char **name; + char **desc; + int nelem; +} XF86XkbDescInfo; + +typedef struct { + XF86ConfInputPtr conf; + XkbDescPtr xkb; + XkbRF_VarDefsRec defs; + XkbConfigRtrnRec config; +} XkbInfo; + +/* + * Prototypes + */ +XtPointer KeyboardConfig(XtPointer); +void KeyboardModelAndLayout(XF86SetupInfo*); +void InitializeKeyboard(void); +Bool UpdateKeyboard(Bool); +Bool WriteXKBConfiguration(char*, XkbConfigRtrnPtr); + +/* + * Initialization + */ +extern XkbInfo *xkb_info; + +#endif /* _xf86cfg_keyboard_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keysym2ucs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keysym2ucs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/keysym2ucs.h (revision 51223) @@ -0,0 +1,37 @@ +/* $XFree86: $ + * + * This module converts keysym values into the corresponding ISO 10646 + * (UCS, Unicode) values. + * + * The array keysymtab[] contains pairs of X11 keysym values for graphical + * characters and the corresponding Unicode value. The function + * keysym2ucs() maps a keysym onto a Unicode value using a binary search, + * therefore keysymtab[] must remain SORTED by keysym value. + * + * The keysym -> UTF-8 conversion will hopefully one day be provided + * by Xlib via XmbLookupString() and should ideally not have to be + * done in X applications. But we are not there yet. + * + * We allow to represent any UCS character in the range U-00000000 to + * U-00FFFFFF by a keysym value in the range 0x01000000 to 0x01ffffff. + * This admittedly does not cover the entire 31-bit space of UCS, but + * it does cover all of the characters up to U-10FFFF, which can be + * represented by UTF-16, and more, and it is very unlikely that higher + * UCS codes will ever be assigned by ISO. So to get Unicode character + * U+ABCD you can directly use keysym 0x0100abcd. + * + * Author: Markus G. Kuhn , University of Cambridge, April 2001 + * + * Special thanks to Richard Verhoeven for preparing + * an initial draft of the mapping table. + * + * This software is in the public domain. Share and enjoy! + */ + +#ifndef KEYSYM2UCS_H +#define KEYSYM2UCS_H 1 + +extern long keysym2ucs(int keysym); +extern int ucs2keysym(long ucs); + +#endif /* KEYSYM2UCS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxdata.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxdata.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxdata.h (revision 51223) @@ -0,0 +1,48 @@ +/* $Xorg: lbxdata.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* + * Copyright 1994 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXDATA_H_ +#define _LBXDATA_H_ +#define NEED_REPLIES +#include +#include +#define _XLBX_SERVER_ +#include +#include "dixfontstr.h" + +extern int lbx_font_private; + +typedef struct _fonttaginfo { + XID tid; + FontPtr pfont; + unsigned long size; + int compression; + xLbxFontInfo *fontinfo; +} FontTagInfoRec, *FontTagInfoPtr; + +#endif /* _LBXDATA_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxserve.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxserve.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxserve.h (revision 51223) @@ -0,0 +1,289 @@ +/* $Xorg: lbxserve.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * Copyright 1992 Network Computing Devices + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of NCD. not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. NCD. makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * NCD. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL NCD. + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxserve.h,v 1.4 2001/08/01 00:44:58 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXSERVE_H_ + +#include "colormap.h" +#include "property.h" + +#define _LBXSERVE_H_ +#define _XLBX_SERVER_ +#include +#include +#include + +#define MAX_LBX_CLIENTS MAXCLIENTS +#define MAX_NUM_PROXIES (MAXCLIENTS >> 1) + +typedef struct _LbxClient *LbxClientPtr; +typedef struct _LbxProxy *LbxProxyPtr; + +typedef struct _LbxClient { + CARD32 id; + ClientPtr client; + LbxProxyPtr proxy; + Bool ignored; + Bool input_blocked; + int reqs_pending; + long bytes_in_reply; + long bytes_remaining; + Drawable drawableCache[GFX_CACHE_SIZE]; + GContext gcontextCache[GFX_CACHE_SIZE]; + pointer gfx_buffer; /* tmp buffer for unpacking gfx requests */ + unsigned long gb_size; +} LbxClientRec; + +typedef struct _connectionOutput *OSBufPtr; + +typedef struct _LbxProxy { + LbxProxyPtr next; + /* this array is indexed by lbx proxy index */ + LbxClientPtr lbxClients[MAX_LBX_CLIENTS]; + LbxClientPtr curRecv, + curDix; + int fd; + int pid; /* proxy ID */ + int uid; + int numClients; + int maxIndex; + Bool aborted; + int grabClient; + pointer compHandle; + Bool dosquishing; + Bool useTags; + LBXDeltasRec indeltas; + LBXDeltasRec outdeltas; + char *iDeltaBuf; + char *replyBuf; + char *oDeltaBuf; + OSBufPtr ofirst; + OSBufPtr olast; + CARD32 cur_send_id; + + LbxStreamOpts streamOpts; + + int numBitmapCompMethods; + unsigned char *bitmapCompMethods; /* array of indices */ + int numPixmapCompMethods; + unsigned char *pixmapCompMethods; /* array of indices */ + int **pixmapCompDepths; /* depths supported from each method */ + + struct _ColormapRec *grabbedCmaps; /* chained via lbx private */ + int motion_allowed_events; + lbxMotionCache motionCache; +} LbxProxyRec; + +/* This array is indexed by server client index, not lbx proxy index */ + +extern LbxClientPtr lbxClients[MAXCLIENTS]; + +#define LbxClient(client) (lbxClients[(client)->index]) +#define LbxProxy(client) (LbxClient(client)->proxy) +#define LbxMaybeProxy(client) (LbxClient(client) ? LbxProxy(client) : 0) +#define LbxProxyID(client) (LbxProxy(client)->pid) +#define LbxProxyClient(proxy) ((proxy)->lbxClients[0]->client) + +extern int LbxEventCode; + + +/* os/connection.c */ +extern ClientPtr AllocLbxClientConnection ( ClientPtr client, + LbxProxyPtr proxy ); +extern void LbxProxyConnection ( ClientPtr client, LbxProxyPtr proxy ); + +/* os/libxio.c */ +extern int UncompressedWriteToClient ( ClientPtr who, int count, char *buf ); +extern void LbxForceOutput ( LbxProxyPtr proxy ); +extern void SwitchClientInput ( ClientPtr client, Bool pending ); +extern int PrepareLargeReqBuffer ( ClientPtr client ); +extern Bool AppendFakeRequest ( ClientPtr client, char *data, int count ); +extern void LbxFreeOsBuffers ( LbxProxyPtr proxy ); +extern Bool AllocateLargeReqBuffer ( ClientPtr client, int size ); +extern Bool AddToLargeReqBuffer ( ClientPtr client, char *data, int size ); +extern void LbxPrimeInput ( ClientPtr client, LbxProxyPtr proxy ); + +/* lbxcmap.c */ +extern int LbxCmapInit ( void ); +extern Bool LbxCheckColorRequest ( ClientPtr client, ColormapPtr pmap, + xReq *req ); +extern int LbxCheckCmapGrabbed ( ColormapPtr pmap ); +extern void LbxDisableSmartGrab ( ColormapPtr pmap ); +extern void LbxBeginFreeCellsEvent ( ColormapPtr pmap ); +extern void LbxAddFreeCellToEvent ( ColormapPtr pmap, Pixel pixel ); +extern void LbxEndFreeCellsEvent ( ColormapPtr pmap ); +extern void LbxSortPixelList ( Pixel *pixels, int count ); +extern int ProcLbxGrabCmap ( ClientPtr client ); +extern void LbxReleaseCmap ( ColormapPtr pmap, Bool smart ); +extern int ProcLbxReleaseCmap ( ClientPtr client ); +extern int ProcLbxAllocColor ( ClientPtr client ); +extern int ProcLbxIncrementPixel ( ClientPtr client ); + +/* lbxdix.h */ +extern void LbxDixInit ( void ); +extern void LbxResetTags ( void ); +extern int LbxSendConnSetup ( ClientPtr client, char *reason ); +extern int LbxGetModifierMapping ( ClientPtr client ); +extern int LbxGetKeyboardMapping ( ClientPtr client ); +extern int LbxQueryFont ( ClientPtr client ); +extern int LbxTagData ( ClientPtr client, XID tag, unsigned long len, + pointer data ); +extern int LbxInvalidateTag ( ClientPtr client, XID tag ); +extern void LbxAllowMotion ( ClientPtr client, int num ); +extern void LbxFlushModifierMapTag ( void ); +extern void LbxFlushKeyboardMapTag ( void ); +extern void LbxFreeFontTag ( FontPtr pfont ); +extern void LbxSendInvalidateTag ( ClientPtr client, XID tag, int tagtype ); +extern Bool LbxFlushQTag ( XID tag ); +extern void ProcessQTagZombies ( void ); +extern void LbxQueryTagData ( ClientPtr client, int owner_pid, XID tag, + int tagtype ); + +/* lbxexts.c */ +extern Bool LbxAddExtension ( char *name, int opcode, int ev_base, + int err_base ); +extern Bool LbxAddExtensionAlias ( int idx, char *alias ); +extern void LbxDeclareExtensionSecurity ( char *extname, Bool secure ); +extern Bool LbxRegisterExtensionGenerationMasks ( int idx, int num_reqs, + char *rep_mask, + char *ev_mask ); +extern int LbxQueryExtension ( ClientPtr client, char *ename, int nlen ); +extern void LbxCloseDownExtensions ( void ); +extern void LbxSetReqMask ( CARD8 *mask, int req, Bool on ); + +/* lbxgfx.c */ +extern int LbxDecodePoly( ClientPtr client, CARD8 xreqtype, + int (*decode_rtn)(char *, char *, short *) ); +extern int LbxDecodeFillPoly ( ClientPtr client ); +extern int LbxDecodeCopyArea ( ClientPtr client ); +extern int LbxDecodeCopyPlane ( ClientPtr client ); +extern int LbxDecodePolyText ( ClientPtr client ); +extern int LbxDecodeImageText ( ClientPtr client ); +extern int LbxDecodePutImage ( ClientPtr client ); +extern int LbxDecodeGetImage ( ClientPtr client ); +extern int LbxDecodePoints ( char *in, char *inend, short *out ); +extern int LbxDecodeSegment ( char *in, char *inend, short *out ); +extern int LbxDecodeRectangle ( char *in, char *inend, short *out ); +extern int LbxDecodeArc ( char *in, char *inend, short *out ); + +/* lbxmain.c */ +extern LbxProxyPtr LbxPidToProxy ( int pid ); +extern void LbxReencodeOutput ( ClientPtr client, char *pbuf, int *pcount, + char *cbuf, int *ccount ); +extern void LbxExtensionInit ( void ); +extern void LbxCloseClient ( ClientPtr client ); +extern void LbxSetForBlock ( LbxClientPtr lbxClient ); +extern int ProcLbxDispatch ( ClientPtr client ); +extern int ProcLbxSwitch ( ClientPtr client ); +extern int ProcLbxQueryVersion ( ClientPtr client ); +extern int ProcLbxStartProxy ( ClientPtr client ); +extern int ProcLbxStopProxy ( ClientPtr client ); +extern int ProcLbxBeginLargeRequest ( ClientPtr client ); +extern int ProcLbxLargeRequestData ( ClientPtr client ); +extern int ProcLbxEndLargeRequest ( ClientPtr client ); +extern int ProcLbxInternAtoms ( ClientPtr client ); +extern int ProcLbxGetWinAttrAndGeom ( ClientPtr client ); +extern int ProcLbxNewClient ( ClientPtr client ); +extern int ProcLbxEstablishConnection ( ClientPtr client ); +extern int ProcLbxCloseClient ( ClientPtr client ); +extern int ProcLbxModifySequence ( ClientPtr client ); +extern int ProcLbxAllowMotion ( ClientPtr client ); +extern int ProcLbxGetModifierMapping ( ClientPtr client ); +extern int ProcLbxGetKeyboardMapping ( ClientPtr client ); +extern int ProcLbxQueryFont ( ClientPtr client ); +extern int ProcLbxChangeProperty ( ClientPtr client ); +extern int ProcLbxGetProperty ( ClientPtr client ); +extern int ProcLbxTagData ( ClientPtr client ); +extern int ProcLbxInvalidateTag ( ClientPtr client ); +extern int ProcLbxPolyPoint ( ClientPtr client ); +extern int ProcLbxPolyLine ( ClientPtr client ); +extern int ProcLbxPolySegment ( ClientPtr client ); +extern int ProcLbxPolyRectangle ( ClientPtr client ); +extern int ProcLbxPolyArc ( ClientPtr client ); +extern int ProcLbxFillPoly ( ClientPtr client ); +extern int ProcLbxPolyFillRectangle ( ClientPtr client ); +extern int ProcLbxPolyFillArc ( ClientPtr client ); +extern int ProcLbxCopyArea ( ClientPtr client ); +extern int ProcLbxCopyPlane ( ClientPtr client ); +extern int ProcLbxPolyText ( ClientPtr client ); +extern int ProcLbxImageText ( ClientPtr client ); +extern int ProcLbxQueryExtension ( ClientPtr client ); +extern int ProcLbxPutImage ( ClientPtr client ); +extern int ProcLbxGetImage ( ClientPtr client ); +extern int ProcLbxSync ( ClientPtr client ); + +/* lbxprop.c */ +extern int LbxChangeProperty ( ClientPtr client ); +extern int LbxGetProperty ( ClientPtr client ); +extern void LbxStallPropRequest ( ClientPtr client, PropertyPtr pProp ); +extern int LbxChangeWindowProperty ( ClientPtr client, WindowPtr pWin, + Atom property, Atom type, int format, + int mode, unsigned long len, + Bool have_data, pointer value, + Bool sendevent, XID *tag ); +/* lbxsquish.c */ +extern int LbxSquishEvent ( char *buf ); + +/* lbwswap.c */ +extern int SProcLbxDispatch( ClientPtr client ); +extern int SProcLbxSwitch ( ClientPtr client ); +extern int SProcLbxBeginLargeRequest ( ClientPtr client ); +extern int SProcLbxLargeRequestData ( ClientPtr client ); +extern int SProcLbxEndLargeRequest ( ClientPtr client ); +extern void LbxWriteSConnSetupPrefix ( ClientPtr pClient, + xLbxConnSetupPrefix *pcsp ); +extern void LbxSwapFontInfo ( xLbxFontInfo *pr, Bool compressed ); + +/* lbxzerorep.c */ +extern void ZeroReplyPadBytes ( char *buf, int reqType ); + +#endif /* _LBXSERVE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxsrvopts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxsrvopts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxsrvopts.h (revision 51223) @@ -0,0 +1,67 @@ +/* $Xorg: lbxsrvopts.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* + * Copyright 1994 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxsrvopts.h,v 1.2 2000/05/18 23:46:24 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBX_SRVOPTS_H_ +#define _LBX_SRVOPTS_H_ + +#include + +typedef struct _LbxNegOpts { + int nopts; + short proxyDeltaN; + short proxyDeltaMaxLen; + short serverDeltaN; + short serverDeltaMaxLen; + LbxStreamOpts streamOpts; + int numBitmapCompMethods; + unsigned char *bitmapCompMethods; /* array of indices */ + int numPixmapCompMethods; + unsigned char *pixmapCompMethods; /* array of indices */ + int **pixmapCompDepths; /* depths supported from each method */ + Bool squish; + Bool useTags; +} LbxNegOptsRec; + +typedef LbxNegOptsRec *LbxNegOptsPtr; + + +extern void LbxOptionInit ( LbxNegOptsPtr pno ); +extern int LbxOptionParse ( LbxNegOptsPtr pno, unsigned char *popt, + int optlen, unsigned char *preply ); +extern LbxBitmapCompMethod * +LbxSrvrLookupBitmapCompMethod ( LbxProxyPtr proxy, int methodOpCode ); +extern LbxPixmapCompMethod * +LbxSrvrLookupPixmapCompMethod ( LbxProxyPtr proxy, int methodOpCode ); +extern LbxBitmapCompMethod * +LbxSrvrFindPreferredBitmapCompMethod ( LbxProxyPtr proxy ); +extern LbxPixmapCompMethod * +LbxSrvrFindPreferredPixmapCompMethod ( LbxProxyPtr proxy, int format, int depth ); + + +#endif /* _LBX_SRVOPTS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxtags.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxtags.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lbxtags.h (revision 51223) @@ -0,0 +1,86 @@ +/* $Xorg: lbxtags.h,v 1.4 2001/02/09 02:05:17 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * Copyright 1993 Network Computing Devices, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and + * its documentation for any purpose is hereby granted without fee, provided + * that the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name Network Computing Devices, Inc. not be + * used in advertising or publicity pertaining to distribution of this + * software without specific, written prior permission. + * + * THIS SOFTWARE IS PROVIDED `AS-IS'. NETWORK COMPUTING DEVICES, INC., + * DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING WITHOUT + * LIMITATION ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, OR NONINFRINGEMENT. IN NO EVENT SHALL NETWORK + * COMPUTING DEVICES, INC., BE LIABLE FOR ANY DAMAGES WHATSOEVER, INCLUDING + * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOSS OF USE, DATA, + * OR PROFITS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF, AND REGARDLESS OF + * WHETHER IN AN ACTION IN CONTRACT, TORT OR NEGLIGENCE, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* $XFree86: xc/programs/Xserver/lbx/lbxtags.h,v 1.3 2001/01/17 22:37:00 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _LBXTAGS_H_ +#define _LBXTAGS_H_ +#include "lbxserve.h" + +#include "os.h" +#include "opaque.h" +#include "resource.h" +#include +#include + +typedef struct _tagdata { + XID tid; + short data_type; + unsigned char sent_to_proxy[(MAX_NUM_PROXIES + 7) / 8]; + int size; + pointer tdata; + XID *global; +} TagDataRec; + +typedef struct _tagdata *TagData; + +extern void TagInit ( void ); +extern XID TagNewTag ( void ); +extern void TagClearProxy ( XID tid, int pid ); +extern void TagMarkProxy ( XID tid, int pid ); +extern Bool TagProxyMarked ( XID tid, int pid ); +extern XID TagSaveTag ( int dtype, int size, pointer data, XID *global ); +extern void TagDeleteTag ( XID tid ); +extern TagData TagGetTag ( XID tid ); +extern void LbxFlushTags ( LbxProxyPtr proxy ); + +#endif /* _LBXTAGS_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/listdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/listdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/listdev.h (revision 51223) @@ -0,0 +1,82 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef LISTDEV_H +#define LISTDEV_H 1 + +int SProcXListInputDevices(ClientPtr /* client */ + ); + +int ProcXListInputDevices(ClientPtr /* client */ + ); + +void SizeDeviceInfo(DeviceIntPtr /* d */ , + int * /* namesize */ , + int * /* size */ + ); + +void ListDeviceInfo(ClientPtr /* client */ , + DeviceIntPtr /* d */ , + xDeviceInfoPtr /* dev */ , + char ** /* devbuf */ , + char ** /* classbuf */ , + char ** /* namebuf */ + ); + +void CopyDeviceName(char ** /* namebuf */ , + char * /* name */ + ); + +void CopySwapDevice(ClientPtr /* client */ , + DeviceIntPtr /* d */ , + int /* num_classes */ , + char ** /* buf */ + ); + +void CopySwapKeyClass(ClientPtr /* client */ , + KeyClassPtr /* k */ , + char ** /* buf */ + ); + +void CopySwapButtonClass(ClientPtr /* client */ , + ButtonClassPtr /* b */ , + char ** /* buf */ + ); + +int CopySwapValuatorClass(ClientPtr /* client */ , + ValuatorClassPtr /* v */ , + char ** /* buf */ + ); + +void SRepXListInputDevices(ClientPtr /* client */ , + int /* size */ , + xListInputDevicesReply * /* rep */ + ); + +#endif /* LISTDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lk201kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lk201kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lk201kbd.h (revision 51223) @@ -0,0 +1,159 @@ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: lk201kbd.h,v 1.4 2001/02/09 02:04:45 xorgcvs Exp $ */ + +#define MIN_LK201_KEY 86 +#define MAX_LK201_KEY 251 +#define LK201_GLYPHS_PER_KEY 2 + +#define KEY_F1 86 +#define KEY_F2 87 +#define KEY_F3 88 +#define KEY_F4 89 +#define KEY_F5 90 +#define KEY_F6 100 +#define KEY_F7 101 +#define KEY_F8 102 +#define KEY_F9 103 +#define KEY_F10 104 +#define KEY_F11 113 +#define KEY_F12 114 +#define KEY_F13 115 +#define KEY_F14 116 +#define KEY_HELP 124 +#define KEY_MENU 125 +#define KEY_F17 128 +#define KEY_F18 129 +#define KEY_F19 130 +#define KEY_F20 131 +#define KEY_FIND 138 +#define KEY_INSERT_HERE 139 +#define KEY_REMOVE 140 +#define KEY_SELECT 141 +#define KEY_PREV_SCREEN 142 +#define KEY_NEXT_SCREEN 143 +#define KEY_KP_0 146 /* key pad */ +#define KEY_KP_PERIOD 148 /* key pad */ +#define KEY_KP_ENTER 149 /* key pad */ +#define KEY_KP_1 150 /* key pad */ +#define KEY_KP_2 151 /* key pad */ +#define KEY_KP_3 152 /* key pad */ +#define KEY_KP_4 153 /* key pad */ +#define KEY_KP_5 154 /* key pad */ +#define KEY_KP_6 155 /* key pad */ +#define KEY_KP_COMMA 156 /* key pad */ +#define KEY_KP_7 157 /* key pad */ +#define KEY_KP_8 158 /* key pad */ +#define KEY_KP_9 159 /* key pad */ +#define KEY_KP_HYPHEN 160 +#define KEY_KP_PF1 161 +#define KEY_KP_PF2 162 +#define KEY_KP_PF3 163 +#define KEY_KP_PF4 164 +#define KEY_LEFT 167 +#define KEY_RIGHT 168 +#define KEY_DOWN 169 +#define KEY_UP 170 +#define KEY_SHIFT 174 +#define KEY_CTRL 175 +#define KEY_LOCK 176 +#define KEY_COMPOSE 177 +#define KEY_APPLE 177 +#define KEY_META 177 +#define KEY_DELETE 188 +#define KEY_RETURN 189 +#define KEY_TAB 190 +#define KEY_TILDE 191 +#define KEY_TR_1 192 /* Top Row */ +#define KEY_Q 193 +#define KEY_A 194 +#define KEY_Z 195 +#define KEY_TR_2 197 +#define KEY_W 198 +#define KEY_S 199 +#define KEY_X 200 +#define KEY_LANGLE_RANGLE 201 /* xxx */ +#define KEY_TR_3 203 +#define KEY_E 204 +#define KEY_D 205 +#define KEY_C 206 +#define KEY_TR_4 208 +#define KEY_R 209 +#define KEY_F 210 +#define KEY_V 211 +#define KEY_SPACE 212 +#define KEY_TR_5 214 +#define KEY_T 215 +#define KEY_G 216 +#define KEY_B 217 +#define KEY_TR_6 219 +#define KEY_Y 220 +#define KEY_H 221 +#define KEY_N 222 +#define KEY_TR_7 224 +#define KEY_U 225 +#define KEY_J 226 +#define KEY_M 227 +#define KEY_TR_8 229 +#define KEY_I 230 +#define KEY_K 231 +#define KEY_COMMA 232 /* xxx */ +#define KEY_TR_9 234 +#define KEY_O 235 +#define KEY_L 236 +#define KEY_PERIOD 237 /* xxx */ +#define KEY_TR_0 239 +#define KEY_P 240 +#define KEY_SEMICOLON 242 /* xxx */ +#define KEY_QMARK 243 +#define KEY_PLUS 245 /* xxx */ +#define KEY_RBRACE 246 +#define KEY_VBAR 247 /* xxx */ +#define KEY_UBAR 249 /* xxx */ +#define KEY_LBRACE 250 +#define KEY_QUOTE 251 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-keyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-keyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-keyboard.h (revision 51223) @@ -0,0 +1,64 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux keyboard driver. \see lnx-keyboard.c */ + +#ifndef _LNX_KEYBOARD_H_ +#define _LNX_KEYBOARD_H_ + +extern pointer kbdLinuxCreatePrivate(DeviceIntPtr pKeyboard); +extern void kbdLinuxDestroyPrivate(pointer private); + +extern void kbdLinuxInit(DevicePtr pDev); +extern void kbdLinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int kbdLinuxOn(DevicePtr pDev); +extern void kbdLinuxOff(DevicePtr pDev); + +extern void kbdLinuxVTPreSwitch(pointer p); +extern void kbdLinuxVTPostSwitch(pointer p); +extern int kbdLinuxVTSwitch(pointer p, int vt, + dmxVTSwitchReturnProcPtr switch_return, + pointer switch_return_data); + +extern void kbdLinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); + +extern void kbdLinuxCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +extern void kbdLinuxBell(DevicePtr pDev, int percent, + int volume, int pitch, int duration); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ms.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ms.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ms.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux MS mouse driver. \see lnx-ms.c */ + +#ifndef _LNX_MS_H_ +#define _LNX_MS_H_ + +extern pointer msLinuxCreatePrivate(DeviceIntPtr pMouse); +extern void msLinuxDestroyPrivate(pointer priv); +extern void msLinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void msLinuxInit(DevicePtr pDev); +extern void msLinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int msLinuxOn(DevicePtr pDev); +extern void msLinuxOff(DevicePtr pDev); +extern void msLinuxCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern void msLinuxVTPreSwitch(pointer p); +extern void msLinuxVTPostSwitch(pointer p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ps2.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ps2.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx-ps2.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2001 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to Linux PS/2 mouse driver. \see lnx-ps2.c */ + +#ifndef _LNX_PS2_H_ +#define _LNX_PS2_H_ + +extern pointer ps2LinuxCreatePrivate(DeviceIntPtr pMouse); +extern void ps2LinuxDestroyPrivate(pointer priv); +extern void ps2LinuxRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void ps2LinuxInit(DevicePtr pDev); +extern void ps2LinuxGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int ps2LinuxOn(DevicePtr pDev); +extern void ps2LinuxOff(DevicePtr pDev); +extern void ps2LinuxCtrl(DevicePtr pDev, PtrCtrl *ctrl); +extern void ps2LinuxVTPreSwitch(pointer p); +extern void ps2LinuxVTPostSwitch(pointer p); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx.h (revision 51223) @@ -0,0 +1,55 @@ +/* $XFree86: Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef LNX_H_ +# ifdef __alpha__ +extern unsigned long _bus_base __P ((void)) __attribute__ ((const)); +extern unsigned long _bus_base_sparse __P ((void)) __attribute__ ((const)); +extern int iopl __P ((int __level)); + +/* new pciconfig_iobase syscall added in 2.2.15 and 2.3.99 */ +# include +# include +extern long (*_iobase)(unsigned, int, int, int); + +/* + * _iobase deals with the case the __NR_pciconfig_iobase is either undefined + * or unsupported by the kernel, but we need to make sure that the `which' + * argument symbols are defined. + */ +# ifndef IOBASE_HOSE +# define IOBASE_HOSE 0 +# endif +# ifndef IOBASE_SPARSE_MEM +# define IOBASE_SPARSE_MEM 1 +# endif +# ifndef IOBASE_DENSE_MEM +# define IOBASE_DENSE_MEM 2 +# endif +# ifndef IOBASE_SPARSE_IO +# define IOBASE_SPARSE_IO 3 +# endif +# ifndef IOBASE_DENSE_IO +# define IOBASE_DENSE_IO 4 +# endif +# ifndef IOBASE_ROOT_BUS +# define IOBASE_ROOT_BUS 5 +# endif +# ifndef IOBASE_FROM_HOSE +# define IOBASE_FROM_HOSE 0x10000 +# endif +# endif /* __alpha__ */ + +# if defined(DO_OS_FONTRESTORE) +Bool lnx_savefont(void); +Bool lnx_restorefont(void); +Bool lnx_switchaway(void); +void lnx_freefontdata(void); +# endif + +#define LNX_H_ + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/lnx_kbd.h (revision 51223) @@ -0,0 +1,5 @@ +/* $XFree86$ */ + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loader.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loader.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loader.h (revision 51223) @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/loader.h,v 1.6 2001/07/07 01:43:58 paulo Exp $ + */ + +#ifdef USE_MODULES +#ifndef LOADER_PRIVATE +#include "config.h" +#include "stubs.h" + +#else + +#ifndef XFree86LOADER +#define XFree86LOADER /* not really */ +#endif +#define IN_LOADER + +#include "xf86.h" +#include "xf86str.h" +#include "xf86Opt.h" +#include "xf86Module.h" + +#ifndef XINPUT +#define XINPUT +#endif +#include "xf86Xinput.h" + +#include +#include "loaderProcs.h" + +#include + +void LoaderDefaultFunc(void); +#endif + +#ifndef _xf86cfg_loader_h +#define _xf86cfg_loader_h + +void xf86cfgLoaderInit(void); +void xf86cfgLoaderInitList(int); +void xf86cfgLoaderFreeList(void); +int xf86cfgCheckModule(void); + +#ifndef LOADER_PRIVATE +/* common/xf86Opt.h */ +typedef struct { + double freq; + int units; +} OptFrequency; + +typedef union { + unsigned long num; + char * str; + double realnum; + Bool xbool; + OptFrequency freq; +} ValueUnion; + +typedef enum { + OPTV_NONE = 0, + OPTV_INTEGER, + OPTV_STRING, /* a non-empty string */ + OPTV_ANYSTR, /* Any string, including an empty one */ + OPTV_REAL, + OPTV_BOOLEAN, + OPTV_FREQ +} OptionValueType; + +typedef enum { + OPTUNITS_HZ = 1, + OPTUNITS_KHZ, + OPTUNITS_MHZ +} OptFreqUnits; + +typedef struct { + int token; + const char* name; + OptionValueType type; + ValueUnion value; + Bool found; +} OptionInfoRec, *OptionInfoPtr; + +/* fontmod.h */ +typedef void (*InitFont)(void); + +typedef struct { + InitFont initFunc; + char * name; + void *module; +} FontModule; + +extern FontModule *FontModuleList; + +typedef struct { + int token; /* id of the token */ + const char * name; /* token name */ +} SymTabRec, *SymTabPtr; +#endif /* !LOADER_PRIVATE */ + +typedef enum { + NullModule = 0, + VideoModule, + InputModule, + GenericModule, + FontRendererModule +} ModuleType; + +typedef struct _xf86cfgModuleOptions { + char *name; + ModuleType type; + OptionInfoPtr option; + int vendor; + SymTabPtr chipsets; + struct _xf86cfgModuleOptions *next; +} xf86cfgModuleOptions; + +extern xf86cfgModuleOptions *module_options; + +/* When adding a new code to the LEGEND, also update checkerLegend + * in loader.c + */ +extern char **checkerLegend; +extern int *checkerErrors; +#define CHECKER_OPTIONS_FILE_MISSING 1 +#define CHECKER_OPTION_DESCRIPTION_MISSING 2 +#define CHECKER_LOAD_FAILED 3 +#define CHECKER_RECOGNIZED_AS 4 +#define CHECKER_NO_OPTIONS_AVAILABLE 5 +#define CHECKER_NO_VENDOR_CHIPSET 6 +#define CHECKER_CANNOT_VERIFY_CHIPSET 7 +#define CHECKER_OPTION_UNUSED 8 +#define CHECKER_NOMATCH_CHIPSET_STRINGS 9 +#define CHECKER_CHIPSET_NOT_LISTED 10 +#define CHECKER_CHIPSET_NOT_SUPPORTED 11 +#define CHECKER_CHIPSET_NO_VENDOR 12 +#define CHECKER_NO_CHIPSETS 13 +#define CHECKER_FILE_MODULE_NAME_MISMATCH 14 + +#define CHECKER_LAST_MESSAGE 14 + +extern void CheckMsg(int, char*, ...); + +#ifndef LOADER_PRIVATE +int LoaderInitializeOptions(void); +#endif +#endif /* USE_MODULES */ + +#endif /* _xf86cfg_loader_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loaderProcs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loaderProcs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/loaderProcs.h (revision 51223) @@ -0,0 +1,127 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/loaderProcs.h,v 1.21 2003/10/15 16:29:04 dawes Exp $ */ + +/* + * + * Copyright 1995-1998 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _LOADERPROCS_H +#define _LOADERPROCS_H + +#define IN_LOADER +#include "xf86Module.h" +#include + +typedef struct module_desc { + struct module_desc *child; + struct module_desc *sib; + struct module_desc *parent; + struct module_desc *demand_next; + char *name; + char *filename; + char *identifier; + XID client_id; + int in_use; + int handle; + ModuleSetupProc SetupProc; + ModuleTearDownProc TearDownProc; + void *TearDownData; /* returned from SetupProc */ + const char *path; + const XF86ModuleVersionInfo *VersionInfo; +} ModuleDesc, *ModuleDescPtr; + +/* + * Extenal API for the loader + */ + +void LoaderInit(void); + +ModuleDescPtr LoadDriver(const char *, const char *, int, pointer, int *, + int *); +ModuleDescPtr LoadModule(const char *, const char *, const char **, + const char **, pointer, const XF86ModReqInfo *, + int *, int *); +ModuleDescPtr LoadSubModule(ModuleDescPtr, const char *, + const char **, const char **, pointer, + const XF86ModReqInfo *, int *, int *); +ModuleDescPtr LoadSubModuleLocal(ModuleDescPtr, const char *, + const char **, const char **, + pointer, const XF86ModReqInfo *, + int *, int *); +ModuleDescPtr DuplicateModule(ModuleDescPtr mod, ModuleDescPtr parent); +void LoadFont(FontModule *); +void UnloadModule(ModuleDescPtr); +void UnloadSubModule(ModuleDescPtr); +void UnloadDriver(ModuleDescPtr); +void FreeModuleDesc(ModuleDescPtr mod); +ModuleDescPtr NewModuleDesc(const char *); +ModuleDescPtr AddSibling(ModuleDescPtr head, ModuleDescPtr new); +void LoaderSetPath(const char *path); +void LoaderSortExtensions(void); + +void LoaderVReqSymLists(const char **, va_list args); +void LoaderVReqSymbols(const char *, va_list args); +void LoaderVRefSymLists(const char **, va_list args); +void LoaderVRefSymbols(const char *, va_list args); + +void LoaderShowStack(void); +void *LoaderSymbolHandle(const char *, int); +int LoaderUnload(int); +unsigned long LoaderGetModuleVersion(ModuleDescPtr mod); + +void LoaderResetOptions(void); +void LoaderSetOptions(unsigned long); +void LoaderClearOptions(unsigned long); + +/* Options for LoaderSetOptions */ +#define LDR_OPT_ABI_MISMATCH_NONFATAL 0x0001 + +#endif /* _LOADERPROCS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/maskbits.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/maskbits.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/maskbits.h (revision 51223) @@ -0,0 +1,691 @@ +/* $XFree86: xc/programs/Xserver/mfb/maskbits.h,v 3.8tsi Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.1, 1/24/89 */ +/*********************************************************** +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: maskbits.h,v 1.3 2000/08/17 19:53:34 cpqbld Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include +#include "servermd.h" + + +/* the following notes use the following conventions: +SCREEN LEFT SCREEN RIGHT +in this file and maskbits.c, left and right refer to screen coordinates, +NOT bit numbering in registers. + +starttab[n] + bits[0,n-1] = 0 bits[n,PLST] = 1 +endtab[n] = + bits[0,n-1] = 1 bits[n,PLST] = 0 + +startpartial[], endpartial[] + these are used as accelerators for doing putbits and masking out +bits that are all contained between longword boudaries. the extra +256 bytes of data seems a small price to pay -- code is smaller, +and narrow things (e.g. window borders) go faster. + +the names may seem misleading; they are derived not from which end +of the word the bits are turned on, but at which end of a scanline +the table tends to be used. + +look at the tables and macros to understand boundary conditions. +(careful readers will note that starttab[n] = ~endtab[n] for n != 0) + +----------------------------------------------------------------------- +these two macros depend on the screen's bit ordering. +in both of them x is a screen position. they are used to +combine bits collected from multiple longwords into a +single destination longword, and to unpack a single +source longword into multiple destinations. + +SCRLEFT(dst, x) + takes dst[x, PPW] and moves them to dst[0, PPW-x] + the contents of the rest of dst are 0. + this is a right shift on LSBFirst (forward-thinking) + machines like the VAX, and left shift on MSBFirst + (backwards) machines like the 680x0 and pc/rt. + +SCRRIGHT(dst, x) + takes dst[0,x] and moves them to dst[PPW-x, PPW] + the contents of the rest of dst are 0. + this is a left shift on LSBFirst, right shift + on MSBFirst. + + +the remaining macros are cpu-independent; all bit order dependencies +are built into the tables and the two macros above. + +maskbits(x, w, startmask, endmask, nlw) + for a span of width w starting at position x, returns +a mask for ragged bits at start, mask for ragged bits at end, +and the number of whole longwords between the ends. + +maskpartialbits(x, w, mask) + works like maskbits(), except all the bits are in the + same longword (i.e. (x&PIM + w) <= PPW) + +maskPPWbits(x, w, startmask, endmask, nlw) + as maskbits, but does not calculate nlw. it is used by + mfbGlyphBlt to put down glyphs <= PPW bits wide. + +------------------------------------------------------------------- + +NOTE + any pointers passed to the following 4 macros are + guranteed to be PPW-bit aligned. + The only non-PPW-bit-aligned references ever made are + to font glyphs, and those are made with getleftbits() + and getshiftedleftbits (qq.v.) + + For 64-bit server, it is assumed that we will never have font padding + of more than 4 bytes. The code uses int's to access the fonts + intead of longs. + +getbits(psrc, x, w, dst) + starting at position x in psrc (x < PPW), collect w + bits and put them in the screen left portion of dst. + psrc is a longword pointer. this may span longword boundaries. + it special-cases fetching all w bits from one longword. + + +--------+--------+ +--------+ + | | m |n| | ==> | m |n| | + +--------+--------+ +--------+ + x x+w 0 w + psrc psrc+1 dst + m = PPW - x + n = w - m + + implementation: + get m bits, move to screen-left of dst, zeroing rest of dst; + get n bits from next word, move screen-right by m, zeroing + lower m bits of word. + OR the two things together. + +putbits(src, x, w, pdst) + starting at position x in pdst, put down the screen-leftmost + w bits of src. pdst is a longword pointer. this may + span longword boundaries. + it special-cases putting all w bits into the same longword. + + +--------+ +--------+--------+ + | m |n| | ==> | | m |n| | + +--------+ +--------+--------+ + 0 w x x+w + dst pdst pdst+1 + m = PPW - x + n = w - m + + implementation: + get m bits, shift screen-right by x, zero screen-leftmost x + bits; zero rightmost m bits of *pdst and OR in stuff + from before the semicolon. + shift src screen-left by m, zero bits n-PPW; + zero leftmost n bits of *(pdst+1) and OR in the + stuff from before the semicolon. + +putbitsrop(src, x, w, pdst, ROP) + like putbits but calls DoRop with the rasterop ROP (see mfb.h for + DoRop) + +putbitsrrop(src, x, w, pdst, ROP) + like putbits but calls DoRRop with the reduced rasterop ROP + (see mfb.h for DoRRop) + +----------------------------------------------------------------------- + The two macros below are used only for getting bits from glyphs +in fonts, and glyphs in fonts are gotten only with the following two +mcros. + You should tune these macros toyour font format and cpu +byte ordering. + +NOTE +getleftbits(psrc, w, dst) + get the leftmost w (w<=32) bits from *psrc and put them + in dst. this is used by the mfbGlyphBlt code for glyphs + <=PPW bits wide. + psrc is declared (unsigned char *) + + psrc is NOT guaranteed to be PPW-bit aligned. on many + machines this will cause problems, so there are several + versions of this macro. + + this macro is called ONLY for getting bits from font glyphs, + and depends on the server-natural font padding. + + for blazing text performance, you want this macro + to touch memory as infrequently as possible (e.g. + fetch longwords) and as efficiently as possible + (e.g. don't fetch misaligned longwords) + +getshiftedleftbits(psrc, offset, w, dst) + used by the font code; like getleftbits, but shifts the + bits SCRLEFT by offset. + this is implemented portably, calling getleftbits() + and SCRLEFT(). + psrc is declared (unsigned char *). +*/ + +/* to match CFB and allow algorithm sharing ... + * name mfb32 mfb64 explanation + * ---- ------ ----- ----------- + * PGSZ 32 64 pixel group size (in bits; same as PPW for mfb) + * PGSZB 4 8 pixel group size (in bytes) + * PPW 32 64 pixels per word (pixels per pixel group) + * PLST 31 63 index of last pixel in a word (should be PPW-1) + * PIM 0x1f 0x3f pixel index mask (index within a pixel group) + * PWSH 5 6 pixel-to-word shift (should be log2(PPW)) + * + * The MFB_ versions are here so that cfb can include maskbits.h to get + * the bitmap constants without conflicting with its own P* constants. + * + * Keith Packard (keithp@suse.com): + * Note mfb64 is no longer supported; it requires DIX support + * for realigning images which costs too much + */ + +/* warning: PixelType definition duplicated in mfb.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ +#ifndef MfbBits +#define MfbBits CARD32 +#endif + +#define MFB_PGSZB 4 +#define MFB_PPW (MFB_PGSZB<<3) /* assuming 8 bits per byte */ +#define MFB_PGSZ MFB_PPW +#define MFB_PLST (MFB_PPW-1) +#define MFB_PIM MFB_PLST + +/* set PWSH = log2(PPW) using brute force */ + +#if MFB_PPW == 32 +#define MFB_PWSH 5 +#endif /* MFB_PPW == 32 */ + +/* XXX don't use these five */ +extern PixelType starttab[]; +extern PixelType endtab[]; +extern PixelType partmasks[MFB_PPW][MFB_PPW]; +extern PixelType rmask[]; +extern PixelType mask[]; +/* XXX use these five */ +extern PixelType mfbGetstarttab(int); +extern PixelType mfbGetendtab(int); +extern PixelType mfbGetpartmasks(int, int); +extern PixelType mfbGetrmask(int); +extern PixelType mfbGetmask(int); + +#ifndef MFB_CONSTS_ONLY + +#define PGSZB MFB_PGSZB +#define PPW MFB_PPW +#define PGSZ MFB_PGSZ +#define PLST MFB_PLST +#define PIM MFB_PIM +#define PWSH MFB_PWSH + +#define BitLeft(b,s) SCRLEFT(b,s) +#define BitRight(b,s) SCRRIGHT(b,s) + +#ifdef XFree86Server +#define LONG2CHARSSAMEORDER(x) ((MfbBits)(x)) +#define LONG2CHARSDIFFORDER( x ) ( ( ( ( x ) & (MfbBits)0x000000FF ) << 0x18 ) \ + | ( ( ( x ) & (MfbBits)0x0000FF00 ) << 0x08 ) \ + | ( ( ( x ) & (MfbBits)0x00FF0000 ) >> 0x08 ) \ + | ( ( ( x ) & (MfbBits)0xFF000000 ) >> 0x18 ) ) +#endif /* XFree86Server */ + +#if (BITMAP_BIT_ORDER == IMAGE_BYTE_ORDER) +#define LONG2CHARS(x) ((MfbBits)(x)) +#else +/* + * the unsigned case below is for compilers like + * the Danbury C and i386cc + */ +#define LONG2CHARS( x ) ( ( ( ( x ) & (MfbBits)0x000000FF ) << 0x18 ) \ + | ( ( ( x ) & (MfbBits)0x0000FF00 ) << 0x08 ) \ + | ( ( ( x ) & (MfbBits)0x00FF0000 ) >> 0x08 ) \ + | ( ( ( x ) & (MfbBits)0xFF000000 ) >> 0x18 ) ) +#endif /* BITMAP_BIT_ORDER */ + +#ifdef STRICT_ANSI_SHIFT +#define SHL(x,y) ((y) >= PPW ? 0 : LONG2CHARS(LONG2CHARS(x) << (y))) +#define SHR(x,y) ((y) >= PPW ? 0 : LONG2CHARS(LONG2CHARS(x) >> (y))) +#else +#define SHL(x,y) LONG2CHARS(LONG2CHARS(x) << (y)) +#define SHR(x,y) LONG2CHARS(LONG2CHARS(x) >> (y)) +#endif + +#if (BITMAP_BIT_ORDER == MSBFirst) /* pc/rt, 680x0 */ +#define SCRLEFT(lw, n) SHL((PixelType)(lw),(n)) +#define SCRRIGHT(lw, n) SHR((PixelType)(lw),(n)) +#else /* vax, intel */ +#define SCRLEFT(lw, n) SHR((PixelType)(lw),(n)) +#define SCRRIGHT(lw, n) SHL((PixelType)(lw),(n)) +#endif + +#define DoRRop(alu, src, dst) \ +(((alu) == RROP_BLACK) ? ((dst) & ~(src)) : \ + ((alu) == RROP_WHITE) ? ((dst) | (src)) : \ + ((alu) == RROP_INVERT) ? ((dst) ^ (src)) : \ + (dst)) + +/* A generalized form of a x4 Duff's Device */ +#define Duff(counter, block) { \ + while (counter >= 4) {\ + { block; } \ + { block; } \ + { block; } \ + { block; } \ + counter -= 4; \ + } \ + switch (counter & 3) { \ + case 3: { block; } \ + case 2: { block; } \ + case 1: { block; } \ + case 0: \ + counter = 0; \ + } \ +} + +#define maskbits(x, w, startmask, endmask, nlw) \ + startmask = mfbGetstarttab((x) & PIM); \ + endmask = mfbGetendtab(((x)+(w)) & PIM); \ + if (startmask) \ + nlw = (((w) - (PPW - ((x) & PIM))) >> PWSH); \ + else \ + nlw = (w) >> PWSH; + +#define maskpartialbits(x, w, mask) \ + mask = mfbGetpartmasks((x) & PIM, (w) & PIM); + +#define maskPPWbits(x, w, startmask, endmask) \ + startmask = mfbGetstarttab((x) & PIM); \ + endmask = mfbGetendtab(((x)+(w)) & PIM); + +#ifdef __GNUC__ /* XXX don't want for Alpha? */ +#ifdef vax +#define FASTGETBITS(psrc,x,w,dst) \ + __asm ("extzv %1,%2,%3,%0" \ + : "=g" (dst) \ + : "g" (x), "g" (w), "m" (*(char *)(psrc))) +#define getbits(psrc,x,w,dst) FASTGETBITS(psrc,x,w,dst) + +#define FASTPUTBITS(src, x, w, pdst) \ + __asm ("insv %3,%1,%2,%0" \ + : "=m" (*(char *)(pdst)) \ + : "g" (x), "g" (w), "g" (src)) +#define putbits(src, x, w, pdst) FASTPUTBITS(src, x, w, pdst) +#endif /* vax */ +#ifdef mc68020 +#define FASTGETBITS(psrc, x, w, dst) \ + __asm ("bfextu %3{%1:%2},%0" \ + : "=d" (dst) : "di" (x), "di" (w), "o" (*(char *)(psrc))) + +#define getbits(psrc,x,w,dst) \ +{ \ + FASTGETBITS(psrc, x, w, dst);\ + dst = SHL(dst,(32-(w))); \ +} + +#define FASTPUTBITS(src, x, w, pdst) \ + __asm ("bfins %3,%0{%1:%2}" \ + : "=o" (*(char *)(pdst)) \ + : "di" (x), "di" (w), "d" (src), "0" (*(char *) (pdst))) + +#define putbits(src, x, w, pdst) FASTPUTBITS(SHR((src),32-(w)), x, w, pdst) + +#endif /* mc68020 */ +#endif /* __GNUC__ */ + +/* The following flag is used to override a bugfix for sun 3/60+CG4 machines, + */ + +/* We don't need to be careful about this unless we're dealing with sun3's + * We will default its usage for those who do not know anything, but will + * override its effect if the machine doesn't look like a sun3 + */ +#if !defined(mc68020) || !defined(sun) +#define NO_3_60_CG4 +#endif + +/* This is gross. We want to #define u_putbits as something which can be used + * in the case of the 3/60+CG4, but if we use /bin/cc or are on another + * machine type, we want nothing to do with u_putbits. What a hastle. Here + * I used slo_putbits as something which either u_putbits or putbits could be + * defined as. + * + * putbits gets it iff it is not already defined with FASTPUTBITS above. + * u_putbits gets it if we have FASTPUTBITS (putbits) from above and have not + * overridden the NO_3_60_CG4 flag. + */ + +#define slo_putbits(src, x, w, pdst) \ +{ \ + register int n = (x)+(w)-PPW; \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | \ + (SCRRIGHT(src, x) & tmpmask); \ + } \ + else \ + { \ + register int d = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (SCRRIGHT((src), x)); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | \ + (SCRLEFT(src, d) & mfbGetendtab(n)); \ + } \ +} + +#if defined(putbits) && !defined(NO_3_60_CG4) +#define u_putbits(src, x, w, pdst) slo_putbits(src, x, w, pdst) +#else +#define u_putbits(src, x, w, pdst) putbits(src, x, w, pdst) +#endif + +#if !defined(putbits) +#define putbits(src, x, w, pdst) slo_putbits(src, x, w, pdst) +#endif + +/* Now if we have not gotten any really good bitfield macros, try some + * moderately fast macros. Alas, I don't know how to do asm instructions + * without gcc. + */ + +#ifndef getbits +#define getbits(psrc, x, w, dst) \ +{ \ + dst = SCRLEFT(*(psrc), (x)); \ + if ( ((x) + (w)) > PPW) \ + dst |= (SCRRIGHT(*((psrc)+1), PPW-(x))); \ +} +#endif + +/* We have to special-case putbitsrop because of 3/60+CG4 combos + */ + +#define u_putbitsrop(src, x, w, pdst, rop) \ +{\ + register PixelType t1, t2; \ + register int n = (x)+(w)-PPW; \ + \ + t1 = SCRRIGHT((src), (x)); \ + DoRop(t2, rop, t1, *(pdst)); \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ + } \ + else \ + { \ + int m = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (t2 & mfbGetstarttab(x)); \ + t1 = SCRLEFT((src), m); \ + DoRop(t2, rop, t1, (pdst)[1]); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | (t2 & mfbGetendtab(n)); \ + } \ +} + +/* If our getbits and putbits are FAST enough, + * do this brute force, it's faster + */ + +#if defined(FASTPUTBITS) && defined(FASTGETBITS) && defined(NO_3_60_CG4) +#if (BITMAP_BIT_ORDER == MSBFirst) +#define putbitsrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp, _tmp2; \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp2 = SCRRIGHT(src, PPW-(w)); \ + DoRop(_tmp, rop, _tmp2, _tmp) \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#define putbitsrrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp, _tmp2; \ + \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp2 = SCRRIGHT(src, PPW-(w)); \ + _tmp= DoRRop(rop, _tmp2, _tmp); \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#undef u_putbitsrop +#else +#define putbitsrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp; \ + FASTGETBITS(pdst, x, w, _tmp); \ + DoRop(_tmp, rop, src, _tmp) \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#define putbitsrrop(src, x, w, pdst, rop) \ +{ \ + register PixelType _tmp; \ + \ + FASTGETBITS(pdst, x, w, _tmp); \ + _tmp= DoRRop(rop, src, _tmp); \ + FASTPUTBITS(_tmp, x, w, pdst); \ +} +#undef u_putbitsrop +#endif +#endif + +#ifndef putbitsrop +#define putbitsrop(src, x, w, pdst, rop) u_putbitsrop(src, x, w, pdst, rop) +#endif + +#ifndef putbitsrrop +#define putbitsrrop(src, x, w, pdst, rop) \ +{\ + register PixelType t1, t2; \ + register int n = (x)+(w)-PPW; \ + \ + t1 = SCRRIGHT((src), (x)); \ + t2 = DoRRop(rop, t1, *(pdst)); \ + \ + if (n <= 0) \ + { \ + register PixelType tmpmask; \ + \ + maskpartialbits((x), (w), tmpmask); \ + *(pdst) = (*(pdst) & ~tmpmask) | (t2 & tmpmask); \ + } \ + else \ + { \ + int m = PPW-(x); \ + *(pdst) = (*(pdst) & mfbGetendtab(x)) | (t2 & mfbGetstarttab(x)); \ + t1 = SCRLEFT((src), m); \ + t2 = DoRRop(rop, t1, (pdst)[1]); \ + (pdst)[1] = ((pdst)[1] & mfbGetstarttab(n)) | (t2 & mfbGetendtab(n)); \ + } \ +} +#endif + +#if GETLEFTBITS_ALIGNMENT == 1 +#define getleftbits(psrc, w, dst) dst = *((CARD32 *)(pointer) psrc) +#endif /* GETLEFTBITS_ALIGNMENT == 1 */ + +#if GETLEFTBITS_ALIGNMENT == 2 +#define getleftbits(psrc, w, dst) \ + { \ + if ( ((int)(psrc)) & 0x01 ) \ + getbits( ((CARD32 *)(((char *)(psrc))-1)), 8, (w), (dst) ); \ + else \ + getbits(psrc, 0, w, dst); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 2 */ + +#if GETLEFTBITS_ALIGNMENT == 4 +#define getleftbits(psrc, w, dst) \ + { \ + int off, off_b; \ + off_b = (off = ( ((int)(psrc)) & 0x03)) << 3; \ + getbits( \ + (CARD32 *)( ((char *)(psrc)) - off), \ + (off_b), (w), (dst) \ + ); \ + } +#endif /* GETLEFTBITS_ALIGNMENT == 4 */ + + +#define getshiftedleftbits(psrc, offset, w, dst) \ + getleftbits((psrc), (w), (dst)); \ + dst = SCRLEFT((dst), (offset)); + +/* FASTGETBITS and FASTPUTBITS are not necessarily correct implementations of + * getbits and putbits, but they work if used together. + * + * On a MSBFirst machine, a cpu bitfield extract instruction (like bfextu) + * could normally assign its result to a 32-bit word register in the screen + * right position. This saves canceling register shifts by not fighting the + * natural cpu byte order. + * + * Unfortunately, these fail on a 3/60+CG4 and cannot be used unmodified. Sigh. + */ +#if defined(FASTGETBITS) && defined(FASTPUTBITS) +#ifdef NO_3_60_CG4 +#define u_FASTPUT(aa, bb, cc, dd) FASTPUTBITS(aa, bb, cc, dd) +#else +#define u_FASTPUT(aa, bb, cc, dd) u_putbits(SCRLEFT(aa, PPW-(cc)), bb, cc, dd) +#endif + +#define getandputbits(psrc, srcbit, dstbit, width, pdst) \ +{ \ + register PixelType _tmpbits; \ + FASTGETBITS(psrc, srcbit, width, _tmpbits); \ + u_FASTPUT(_tmpbits, dstbit, width, pdst); \ +} + +#define getandputrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpsrc, _tmpdst; \ + FASTGETBITS(pdst, dstbit, width, _tmpdst); \ + FASTGETBITS(psrc, srcbit, width, _tmpsrc); \ + DoRop(_tmpdst, rop, _tmpsrc, _tmpdst); \ + u_FASTPUT(_tmpdst, dstbit, width, pdst); \ +} + +#define getandputrrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpsrc, _tmpdst; \ + FASTGETBITS(pdst, dstbit, width, _tmpdst); \ + FASTGETBITS(psrc, srcbit, width, _tmpsrc); \ + _tmpdst = DoRRop(rop, _tmpsrc, _tmpdst); \ + u_FASTPUT(_tmpdst, dstbit, width, pdst); \ +} + +#define getandputbits0(psrc, srcbit, width, pdst) \ + getandputbits(psrc, srcbit, 0, width, pdst) + +#define getandputrop0(psrc, srcbit, width, pdst, rop) \ + getandputrop(psrc, srcbit, 0, width, pdst, rop) + +#define getandputrrop0(psrc, srcbit, width, pdst, rop) \ + getandputrrop(psrc, srcbit, 0, width, pdst, rop) + + +#else /* Slow poke */ + +/* pairs of getbits/putbits happen frequently. Some of the code can + * be shared or avoided in a few specific instances. It gets us a + * small advantage, so we do it. The getandput...0 macros are the only ones + * which speed things here. The others are here for compatibility w/the above + * FAST ones + */ + +#define getandputbits(psrc, srcbit, dstbit, width, pdst) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits); \ + putbits(_tmpbits, dstbit, width, pdst); \ +} + +#define getandputrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits) \ + putbitsrop(_tmpbits, dstbit, width, pdst, rop) \ +} + +#define getandputrrop(psrc, srcbit, dstbit, width, pdst, rop) \ +{ \ + register PixelType _tmpbits; \ + getbits(psrc, srcbit, width, _tmpbits) \ + putbitsrrop(_tmpbits, dstbit, width, pdst, rop) \ +} + + +#define getandputbits0(psrc, sbindex, width, pdst) \ +{ /* unroll the whole damn thing to see how it * behaves */ \ + register int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + + +#define getandputrop0(psrc, sbindex, width, pdst, rop) \ +{ \ + register int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + DoRop(_src, rop, _src, *(pdst)); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + +#define getandputrrop0(psrc, sbindex, width, pdst, rop) \ +{ \ + int _flag = PPW - (sbindex); \ + register PixelType _src; \ + \ + _src = SCRLEFT (*(psrc), (sbindex)); \ + if ((width) > _flag) \ + _src |= SCRRIGHT (*((psrc) + 1), _flag); \ + _src = DoRRop(rop, _src, *(pdst)); \ + \ + *(pdst) = (*(pdst) & mfbGetstarttab((width))) | (_src & mfbGetendtab((width))); \ +} + +#endif /* FASTGETBITS && FASTPUTBITS */ + +#endif /* MFB_CONSTS_ONLY */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/memrange.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/memrange.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/memrange.h (revision 51223) @@ -0,0 +1,72 @@ +/* + * Memory range attribute operations, peformed on /dev/mem + * + * $FreeBSD: src/sys/sys/memrange.h,v 1.4 1999/12/29 04:24:44 peter Exp $ + */ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _MEMRANGE_H +#define _MEMRANGE_H + +/* Memory range attributes */ +#define MDF_UNCACHEABLE (1<<0) /* region not cached */ +#define MDF_WRITECOMBINE (1<<1) /* region supports "write combine" + * action */ +#define MDF_WRITETHROUGH (1<<2) /* write-through cached */ +#define MDF_WRITEBACK (1<<3) /* write-back cached */ +#define MDF_WRITEPROTECT (1<<4) /* read-only region */ +#define MDF_ATTRMASK (0x00ffffff) + +#define MDF_FIXBASE (1<<24) /* fixed base */ +#define MDF_FIXLEN (1<<25) /* fixed length */ +#define MDF_FIRMWARE (1<<26) /* set by firmware (XXX not useful?) */ +#define MDF_ACTIVE (1<<27) /* currently active */ +#define MDF_BOGUS (1<<28) /* we don't like it */ +#define MDF_FIXACTIVE (1<<29) /* can't be turned off */ +#define MDF_BUSY (1<<30) /* range is in use */ + +struct mem_range_desc { + u_int64_t mr_base; + u_int64_t mr_len; + int mr_flags; + char mr_owner[8]; +}; + +struct mem_range_op { + struct mem_range_desc *mo_desc; + int mo_arg[2]; +#define MEMRANGE_SET_UPDATE 0 +#define MEMRANGE_SET_REMOVE 1 + /* XXX want a flag that says "set and undo when I exit" */ +}; +#define MEMRANGE_GET _IOWR('m', 50, struct mem_range_op) +#define MEMRANGE_SET _IOW('m', 51, struct mem_range_op) + +#ifdef _KERNEL + +struct mem_range_softc; +struct mem_range_ops { + void (*init) __P((struct mem_range_softc * sc)); + int (*set) __P((struct mem_range_softc * sc, struct mem_range_desc * mrd, int *arg)); + void (*initAP) __P((struct mem_range_softc * sc)); +}; + +struct mem_range_softc { + struct mem_range_ops *mr_op; + int mr_cap; + int mr_ndesc; + struct mem_range_desc *mr_desc; +}; + +extern struct mem_range_softc mem_range_softc; + +extern int mem_range_attr_get __P((struct mem_range_desc * mrd, int *arg)); +extern int mem_range_attr_set __P((struct mem_range_desc * mrd, int *arg)); +extern void mem_range_AP_init __P((void)); +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mergerop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mergerop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mergerop.h (revision 51223) @@ -0,0 +1,400 @@ +/* + * $Xorg: mergerop.h,v 1.4 2001/02/09 02:05:18 xorgcvs Exp $ + * +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ +/* $XFree86: xc/programs/Xserver/mfb/mergerop.h,v 3.13 2001/10/28 03:34:13 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _MERGEROP_H_ +#define _MERGEROP_H_ + +#ifndef GXcopy +#include +#endif + +typedef struct _mergeRopBits { + MfbBits ca1, cx1, ca2, cx2; +} mergeRopRec, *mergeRopPtr; + +extern mergeRopRec mergeRopBits[16]; +extern mergeRopPtr mergeGetRopBits(int i); + +#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ) /* cfb */ +#define DeclareMergeRop() MfbBits _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0; +#define DeclarePrebuiltMergeRop() MfbBits _cca, _ccx; +#if PSZ == 24 /* both for PGSZ == 32 and 64 */ +#define DeclareMergeRop24() \ + MfbBits _ca1u[4], _cx1u[4], _ca2u[4], _cx2u[4]; + /* int _unrollidx[3]={0,0,1,2};*/ +#define DeclarePrebuiltMergeRop24() MfbBits _ccau[4], _ccxu[4]; +#endif /* PSZ == 24 */ +#else /* mfb */ +#define DeclareMergeRop() MfbBits _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0; +#define DeclarePrebuiltMergeRop() MfbBits _cca, _ccx; +#endif + +#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ) /* cfb */ +#define InitializeMergeRop(alu,pm) {\ + MfbBits _pm; \ + mergeRopPtr _bits; \ + _pm = PFILL(pm); \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1 & _pm; \ + _cx1 = _bits->cx1 | ~_pm; \ + _ca2 = _bits->ca2 & _pm; \ + _cx2 = _bits->cx2 & _pm; \ +} +#if PSZ == 24 +#if (BITMAP_BIT_ORDER == MSBFirst) +#define InitializeMergeRop24(alu,pm) {\ + register int i; \ + register MfbBits _pm = (pm) & 0xFFFFFF; \ + mergeRopPtr _bits = mergeGetRopBits(alu); \ + MfbBits _bits_ca1 = _bits->ca1; \ + MfbBits _bits_cx1 = _bits->cx1; \ + MfbBits _bits_ca2 = _bits->ca2; \ + MfbBits _bits_cx2 = _bits->cx2; \ + _pm = (_pm << 8) | (_pm >> 16); \ + for(i = 0; i < 4; i++){ \ + _ca1u[i] = _bits_ca1 & _pm; \ + _cx1u[i] = _bits_cx1 | ~_pm; \ + _ca2u[i] = _bits_ca2 & _pm; \ + _cx2u[i] = _bits_cx2 & _pm; \ + _pm = (_pm << 16)|(_pm >> 8); \ + } \ +} +#else /*(BITMAP_BIT_ORDER == LSBFirst)*/ +#define InitializeMergeRop24(alu,pm) {\ + register int i; \ + register MfbBits _pm = (pm) & cfbmask[0]; \ + mergeRopPtr _bits = mergeGetRopBits(alu); \ + MfbBits _bits_ca1 = _bits->ca1 & cfbmask[0]; \ + MfbBits _bits_cx1 = _bits->cx1 & cfbmask[0]; \ + MfbBits _bits_ca2 = _bits->ca2 & cfbmask[0]; \ + MfbBits _bits_cx2 = _bits->cx2 & cfbmask[0]; \ + _pm |= (_pm << 24); \ + _bits_ca1 |= (_bits->ca1 << 24); \ + _bits_cx1 |= (_bits->cx1 << 24); \ + _bits_ca2 |= (_bits->ca2 << 24); \ + _bits_cx2 |= (_bits->cx2 << 24); \ + for(i = 0; i < 4; i++){ \ + _ca1u[i] = _bits_ca1 & _pm; \ + _cx1u[i] = _bits_cx1 | ~_pm; \ + _ca2u[i] = _bits_ca2 & _pm; \ + _cx2u[i] = _bits_cx2 & _pm; \ + _pm = (_pm << 16)|(_pm >> 8); \ + } \ +} +#endif /*(BITMAP_BIT_ORDER == MSBFirst)*/ +#endif /* PSZ == 24 */ +#else /* mfb */ +#define InitializeMergeRop(alu,pm) {\ + mergeRopPtr _bits; \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1; \ + _cx1 = _bits->cx1; \ + _ca2 = _bits->ca2; \ + _cx2 = _bits->cx2; \ +} +#endif + +/* AND has higher precedence than XOR */ + +#define DoMergeRop(src, dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (((src) & _ca2) ^ _cx2)) + +#define DoMergeRop24u(src, dst, i) \ +(((dst) & (((src) & _ca1u[i]) ^ _cx1u[i])) ^ (((src) & _ca2u[i]) ^ _cx2u[i])) + +#define DoMaskMergeRop24(src, dst, mask, index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src0 = (src);\ + MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \ + MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | (((*(dst)) & cfbmask[idx]) & \ + (((( _src1 |(~mask))<>cfb24Shift[idx])&cfbmask[idx]) ^ \ + (((_src2 &(mask))>>cfb24Shift[idx])&cfbmask[idx])))); \ + (dst)--; \ + } + +#define DoMaskMergeRop(src, dst, mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1) | ~(mask))) ^ ((((src) & _ca2) ^ _cx2) & (mask))) + +#define DoMaskMergeRop24u(src, dst, mask, i) \ +(((dst) & ((((src) & _ca1u[(i)]) ^ _cx1u[(i)]) | ~(mask))) ^ ((((src) & _ca2u[(i)]) ^ _cx2u[(i)]) & (mask))) + +#define DoMergeRop24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src0 = (src);\ + MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \ + MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \ + ((_src1 << cfb24Shift[idx])&cfbmask[idx])) ^ \ + ((_src2 << cfb24Shift[idx])&cfbmask[idx]))); \ + idx++; \ + (dst)++; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \ + ((_src1 >> cfb24Shift[idx])&cfbmask[idx])) ^ \ + ((_src2 >> cfb24Shift[idx])&cfbmask[idx]))); \ + (dst)--; \ + } + +#define DoPrebuiltMergeRop(dst) (((dst) & _cca) ^ _ccx) + +#define DoPrebuiltMergeRop24(dst,index) { \ + register int idx = ((index) & 3)<< 1; \ + *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) &\ + (( _cca <>cfb24Shift[idx])&cfbmask[idx])) ^ \ + (( _ccx >>cfb24Shift[idx])&cfbmask[idx]))); \ + (dst)--; \ + } + +#define DoMaskPrebuiltMergeRop(dst,mask) \ + (((dst) & (_cca | ~(mask))) ^ (_ccx & (mask))) + +#define PrebuildMergeRop(src) ((_cca = ((src) & _ca1) ^ _cx1), \ + (_ccx = ((src) & _ca2) ^ _cx2)) + +#ifndef MROP +#define MROP 0 +#endif + +#define Mclear (1<> cfb24Shift[(idx)<<1])| \ + ((*((pix)+1) & cfbmask[((idx)<<1)+1]) << cfb24Shift[((idx)<<1)+1])) + +#define MROP_SOLID24P(src,dst,sindex, index) \ + MROP_SOLID24(MROP_PIXEL24(src,sindex),dst,index) + +#define MROP_MASK24P(src,dst,mask,sindex,index) \ + MROP_MASK24(MROP_PIXEL24(src,sindex),dst,mask,index) + +#if (MROP) == Mcopy +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) (src) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src<>cfb24Shift[idx])&cfbmask[idx]); \ + } +#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((src) & (mask))) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src&(mask))>>cfb24Shift[idx])&cfbmask[idx])); \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Copy) +#endif + +#if (MROP) == McopyInverted +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) (~(src)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = ~(src); \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src << cfb24Shift[idx])&cfbmask[idx]); \ + idx++; \ + (dst)++; \ + *(dst) = (*(dst) & cfbrmask[idx])|((_src >>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((~(src)) & (mask))) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = ~(src); \ + *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \ + (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx])) | \ + ((((_src & (mask))>>cfb24Shift[idx])&cfbmask[idx])); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,CopyInverted) +#endif + +#if (MROP) == Mxor +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) ((src) ^ (dst)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) ^= ((_src << cfb24Shift[idx])&cfbmask[idx]); \ + idx++; \ + (dst)++; \ + *(dst) ^= ((_src >>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((src) & (mask)) ^ (dst)) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) ^= ((((src)&(mask))<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Xor) +#endif + +#if (MROP) == Mor +#define MROP_DECLARE() +#define MROP_DECLARE_REG() +#define MROP_INITIALIZE(alu,pm) +#define MROP_SOLID(src,dst) ((src) | (dst)) +#define MROP_SOLID24(src,dst,index) {\ + register int idx = ((index) & 3)<< 1; \ + *(dst) |= (((src)<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_MASK(src,dst,mask) (((src) & (mask)) | (dst)) +#define MROP_MASK24(src,dst,mask,index) {\ + register int idx = ((index) & 3)<< 1; \ + MfbBits _src = (src); \ + *(dst) |= (((_src &(mask))<>cfb24Shift[idx])&cfbmask[idx]); \ + (dst)--; \ + } +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,Or) +#endif + +#if (MROP) == (Mcopy|Mxor|MandReverse|Mor) +#define MROP_DECLARE() MfbBits _ca1 = 0, _cx1 = 0; +#define MROP_DECLARE_REG() register MROP_DECLARE() +#define MROP_INITIALIZE(alu,pm) { \ + mergeRopPtr _bits; \ + _bits = mergeGetRopBits(alu); \ + _ca1 = _bits->ca1; \ + _cx1 = _bits->cx1; \ +} +#define MROP_SOLID(src,dst) \ + (((dst) & (((src) & _ca1) ^ _cx1)) ^ (src)) +#define MROP_MASK(src,dst,mask) \ + (((dst) & ((((src) & _ca1) ^ _cx1)) | (~(mask)) ^ ((src) & (mask)))) +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,CopyXorAndReverseOr) +#define MROP_PREBUILD(src) PrebuildMergeRop(src) +#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop() +#define MROP_PREBUILT_SOLID(src,dst) DoPrebuiltMergeRop(dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) DoPrebuiltMergeRop24(dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) DoMaskPrebuiltMergeRop(dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) DoMaskPrebuiltMergeRop24(dst,mask,index) +#endif + +#if (MROP) == 0 +#if !defined(PSZ) || (PSZ != 24) +#define MROP_DECLARE() DeclareMergeRop() +#define MROP_DECLARE_REG() register DeclareMergeRop() +#define MROP_INITIALIZE(alu,pm) InitializeMergeRop(alu,pm) +#define MROP_SOLID(src,dst) DoMergeRop(src,dst) +#define MROP_MASK(src,dst,mask) DoMaskMergeRop(src, dst, mask) +#else +#define MROP_DECLARE() \ + DeclareMergeRop() \ + DeclareMergeRop24() +#define MROP_DECLARE_REG() \ + register DeclareMergeRop()\ + DeclareMergeRop24() +#define MROP_INITIALIZE(alu,pm) \ + InitializeMergeRop(alu,pm)\ + InitializeMergeRop24(alu,pm) +#define MROP_SOLID(src,dst) DoMergeRop24u(src,dst,((int)(&(dst)-pdstBase) % 3)) +#define MROP_MASK(src,dst,mask) DoMaskMergeRop24u(src, dst, mask,((int)(&(dst) - pdstBase)%3)) +#endif +#define MROP_SOLID24(src,dst,index) DoMergeRop24(src,dst,index) +#define MROP_MASK24(src,dst,mask,index) DoMaskMergeRop24(src, dst, mask,index) +#define MROP_NAME(prefix) MROP_NAME_CAT(prefix,General) +#define MROP_PREBUILD(src) PrebuildMergeRop(src) +#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop() +#define MROP_PREBUILT_SOLID(src,dst) DoPrebuiltMergeRop(dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) DoPrebuiltMergeRop24(dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) DoMaskPrebuiltMergeRop(dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) \ + DoMaskPrebuiltMergeRop24(dst,mask,index) +#endif + +#ifndef MROP_PREBUILD +#define MROP_PREBUILD(src) +#define MROP_PREBUILT_DECLARE() +#define MROP_PREBUILT_SOLID(src,dst) MROP_SOLID(src,dst) +#define MROP_PREBUILT_SOLID24(src,dst,index) MROP_SOLID24(src,dst,index) +#define MROP_PREBUILT_MASK(src,dst,mask) MROP_MASK(src,dst,mask) +#define MROP_PREBUILT_MASK24(src,dst,mask,index) MROP_MASK24(src,dst,mask,index) +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define MROP_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define MROP_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfb.h (revision 51223) @@ -0,0 +1,1151 @@ +/* $XFree86: xc/programs/Xserver/mfb/mfb.h,v 1.21 2003/07/16 03:35:16 dawes Exp $ */ +/* Combined Purdue/PurduePlus patches, level 2.0, 1/17/89 */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: mfb.h,v 1.4 2001/02/09 02:05:18 xorgcvs Exp $ */ + +#if !defined(_MFB_H_) || defined(MFB_PROTOTYPES_ONLY) +#ifndef MFB_PROTOTYPES_ONLY +#define _MFB_H_ +#endif + +/* Monochrome Frame Buffer definitions + written by drewry, september 1986 +*/ +#include "pixmap.h" +#include "region.h" +#include "gc.h" +#include "colormap.h" +#include "miscstruct.h" +#include "mibstore.h" + +extern int InverseAlu[]; +extern int mfbGetInverseAlu(int i); + +/* warning: PixelType definition duplicated in maskbits.h */ +#ifndef PixelType +#define PixelType CARD32 +#endif /* PixelType */ +#ifndef MfbBits +#define MfbBits CARD32 +#endif + +/* mfbbitblt.c */ + +extern void mfbDoBitblt( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); + +extern RegionPtr mfbCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/ +); + +extern Bool mfbRegisterCopyPlaneProc( + ScreenPtr /*pScreen*/, + RegionPtr (* /*proc*/)( + DrawablePtr /* pSrcDrawable */, + DrawablePtr /* pDstDrawable */, + GCPtr /* pGC */, + int /* srcx */, + int /* srcy */, + int /* width */, + int /* height */, + int /* dstx */, + int /* dsty */, + unsigned long /* bitPlane */ + ) +); + +extern RegionPtr mfbCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr/*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); +/* mfbbltC.c */ + +extern void mfbDoBitbltCopy( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltCI.c */ + +extern void mfbDoBitbltCopyInverted( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltG.c */ + +extern void mfbDoBitbltGeneral( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltO.c */ + +extern void mfbDoBitbltOr( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbltX.c */ + +extern void mfbDoBitbltXor( + DrawablePtr /*pSrc*/, + DrawablePtr /*pDst*/, + int /*alu*/, + RegionPtr /*prgnDst*/, + DDXPointPtr /*pptSrc*/ +); +/* mfbbres.c */ + +extern void mfbBresS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* mfbbresd.c */ + +extern void mfbBresD( + int /*fgrop*/, + int /*bgrop*/, + int * /*pdashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pdashOffset*/, + int /*isDoubleDash*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*signdx*/, + int /*signdy*/, + int /*axis*/, + int /*x1*/, + int /*y1*/, + int /*e*/, + int /*e1*/, + int /*e2*/, + int /*len*/ +); +/* mfbbstore.c */ + +extern void mfbSaveAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); + +extern void mfbRestoreAreas( + PixmapPtr /*pPixmap*/, + RegionPtr /*prgnRestore*/, + int /*xorg*/, + int /*yorg*/, + WindowPtr /*pWin*/ +); +/* mfbclip.c */ + +extern RegionPtr mfbPixmapToRegion( + PixmapPtr /*pPix*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef RegionPtr (*mfbPixmapToRegionProc)(PixmapPtr); + +extern mfbPixmapToRegionProc *mfbPixmapToRegionWeak(void); +#endif + +/* mfbcmap.c */ + +extern int mfbListInstalledColormaps( + ScreenPtr /*pScreen*/, + Colormap * /*pmaps*/ +); + +extern void mfbInstallColormap( + ColormapPtr /*pmap*/ +); + +extern void mfbUninstallColormap( + ColormapPtr /*pmap*/ +); + +extern void mfbResolveColor( + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/, + VisualPtr /*pVisual*/ +); + +extern Bool mfbCreateColormap( + ColormapPtr /*pMap*/ +); + +extern void mfbDestroyColormap( + ColormapPtr /*pMap*/ +); + +extern Bool mfbCreateDefColormap( + ScreenPtr /*pScreen*/ +); +/* mfbfillarc.c */ + +extern void mfbPolyFillArcSolid( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); +/* mfbfillrct.c */ + +extern void mfbPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); +/* mfbfillsp.c */ + +extern void mfbBlackSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbWhiteSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbInvertSolidFS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbWhiteStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbBlackStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbInvertStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbUnnaturalTileFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); + +extern void mfbUnnaturalStippleFS( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*nInit*/, + DDXPointPtr /*pptInit*/, + int * /*pwidthInit*/, + int /*fSorted*/ +); +/* mfbfont.c */ + +extern Bool mfbRealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +extern Bool mfbUnrealizeFont( + ScreenPtr /*pscr*/, + FontPtr /*pFont*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbRealizeFontProc)(ScreenPtr, FontPtr); +typedef void (*mfbUnrealizeFontProc)(ScreenPtr, FontPtr); + +extern mfbRealizeFontProc *mfbRealizeFontWeak(void); +extern mfbUnrealizeFontProc *mfbUnrealizeFontWeak(void); +#endif + +/* mfbgc.c */ + +extern Bool mfbCreateGC( + GCPtr /*pGC*/ +); + +extern void mfbValidateGC( + GCPtr /*pGC*/, + unsigned long /*changes*/, + DrawablePtr /*pDrawable*/ +); + +extern int mfbReduceRop( + int /*alu*/, + Pixel /*src*/ +); + +/* mfbgetsp.c */ + +extern void mfbGetSpans( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/ +); +/* mfbhrzvert.c */ + +extern void mfbHorzS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); + +extern void mfbVertS( + int /*rop*/, + PixelType * /*addrl*/, + int /*nlwidth*/, + int /*x1*/, + int /*y1*/, + int /*len*/ +); +/* mfbigbblak.c */ + +extern void mfbImageGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbigbwht.c */ + +extern void mfbImageGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbimage.c */ + +extern void mfbPutImage( + DrawablePtr /*dst*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +extern void mfbGetImage( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); +/* mfbline.c */ + +extern void mfbLineSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +extern void mfbLineSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pptInit*/ +); + +/* mfbmisc.c */ + +extern void mfbQueryBestSize( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbQueryBestSizeProc)(int, unsigned short *, unsigned short *, + ScreenPtr); + +extern mfbQueryBestSizeProc *mfbQueryBestSizeWeak(void); +#endif + +/* mfbpablack.c */ + +extern void mfbSolidBlackArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleBlackArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); +/* mfbpainv.c */ + +extern void mfbSolidInvertArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleInvertArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); +/* mfbpawhite.c */ + +extern void mfbSolidWhiteArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ +); + +extern void mfbStippleWhiteArea( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*pstipple*/ +); + +/* mfbpgbinv.c */ + +extern void mfbPolyGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpgbinv.c */ + +extern void mfbPolyGlyphBltInvert( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpgbwht.c */ + +extern void mfbPolyGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbpixmap.c */ + +extern PixmapPtr mfbCreatePixmap( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/ +); + +extern Bool mfbDestroyPixmap( + PixmapPtr /*pPixmap*/ +); + +extern PixmapPtr mfbCopyPixmap( + PixmapPtr /*pSrc*/ +); + +extern void mfbPadPixmap( + PixmapPtr /*pPixmap*/ +); + +extern void mfbXRotatePixmap( + PixmapPtr /*pPix*/, + int /*rw*/ +); + +extern void mfbYRotatePixmap( + PixmapPtr /*pPix*/, + int /*rh*/ +); + +extern void mfbCopyRotatePixmap( + PixmapPtr /*psrcPix*/, + PixmapPtr * /*ppdstPix*/, + int /*xrot*/, + int /*yrot*/ +); +/* mfbplyblack.c */ + +extern void mfbFillPolyBlack( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* mfbplyinv.c */ + +extern void mfbFillPolyInvert( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mfbpntwin.c */ + +extern void mfbFillPolyWhite( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); +/* mfbpntwin.c */ + +extern void mfbPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*pRegion*/, + int /*what*/ +); +/* mfbpolypnt.c */ + +extern void mfbPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); +/* mfbpushpxl.c */ + +extern void mfbSolidPP( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +extern void mfbPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +typedef void (*mfbPushPixelsProc)(GCPtr, PixmapPtr, DrawablePtr, int, int, + int, int); + +extern mfbPushPixelsProc *mfbPushPixelsWeak(void); +#endif + +/* mfbscrclse.c */ + +extern Bool mfbCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); +/* mfbscrinit.c */ + +extern Bool mfbAllocatePrivates( + ScreenPtr /*pScreen*/, + int * /*pWinIndex*/, + int * /*pGCIndex*/ +); + +extern Bool mfbScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/ +); + +extern PixmapPtr mfbGetWindowPixmap( + WindowPtr /*pWin*/ +); + +extern void mfbSetWindowPixmap( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/ +); + +extern void mfbFillInScreen(ScreenPtr pScreen); + +/* mfbseg.c */ + +extern void mfbSegmentSS( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); + +extern void mfbSegmentSD( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSeg*/ +); +/* mfbsetsp.c */ + +extern void mfbSetScanline( + int /*y*/, + int /*xOrigin*/, + int /*xStart*/, + int /*xEnd*/, + PixelType * /*psrc*/, + int /*alu*/, + PixelType * /*pdstBase*/, + int /*widthDst*/ +); + +extern void mfbSetSpans( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + char * /*psrc*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + int /*fSorted*/ +); +/* mfbteblack.c */ + +extern void mfbTEGlyphBltBlack( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbtewhite.c */ + +extern void mfbTEGlyphBltWhite( + DrawablePtr /*pDrawable*/, + GCPtr/*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); +/* mfbtileC.c */ + +extern void mfbTileAreaPPWCopy( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); +/* mfbtileG.c */ + +extern void mfbTileAreaPPWGeneral( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); + +extern void mfbTileAreaPPW( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*ptile*/ +); +/* mfbwindow.c */ + +extern Bool mfbCreateWindow( + WindowPtr /*pWin*/ +); + +extern Bool mfbDestroyWindow( + WindowPtr /*pWin*/ +); + +extern Bool mfbMapWindow( + WindowPtr /*pWindow*/ +); + +extern Bool mfbPositionWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/ +); + +extern Bool mfbUnmapWindow( + WindowPtr /*pWindow*/ +); + +extern void mfbCopyWindow( + WindowPtr /*pWin*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/ +); + +extern Bool mfbChangeWindowAttributes( + WindowPtr /*pWin*/, + unsigned long /*mask*/ +); +/* mfbzerarc.c */ + +extern void mfbZeroPolyArcSS( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#ifndef MFB_PROTOTYPES_ONLY +/* + private filed of pixmap + pixmap.devPrivate = (PixelType *)pointer_to_bits + pixmap.devKind = width_of_pixmap_in_bytes + + private field of screen + a pixmap, for which we allocate storage. devPrivate is a pointer to +the bits in the hardware framebuffer. note that devKind can be poked to +make the code work for framebuffers that are wider than their +displayable screen (e.g. the early vsII, which displayed 960 pixels +across, but was 1024 in the hardware.) + + private field of GC +*/ +typedef void (*mfbFillAreaProcPtr)( + DrawablePtr /*pDraw*/, + int /*nbox*/, + BoxPtr /*pbox*/, + int /*alu*/, + PixmapPtr /*nop*/ + ); + +typedef struct { + unsigned char rop; /* reduction of rasterop to 1 of 3 */ + unsigned char ropOpStip; /* rop for opaque stipple */ + unsigned char ropFillArea; /* == alu, rop, or ropOpStip */ + unsigned char unused1[sizeof(long) - 3]; /* Alignment */ + mfbFillAreaProcPtr FillArea; /* fills regions; look at the code */ + } mfbPrivGC; +typedef mfbPrivGC *mfbPrivGCPtr; +#endif + +/* XXX these should be static, but it breaks the ABI */ +extern int mfbGCPrivateIndex; /* index into GC private array */ +extern int mfbGetGCPrivateIndex(void); +extern int mfbWindowPrivateIndex; /* index into Window private array */ +extern int mfbGetWindowPrivateIndex(void); +#ifdef PIXMAP_PER_WINDOW +extern int frameWindowPrivateIndex; /* index into Window private array */ +extern int frameGetWindowPrivateIndex(void); +#endif + +#ifndef MFB_PROTOTYPES_ONLY +/* private field of window */ +typedef struct { + unsigned char fastBorder; /* non-zero if border tile is 32 bits wide */ + unsigned char fastBackground; + unsigned short unused; /* pad for alignment with Sun compiler */ + DDXPointRec oldRotate; + PixmapPtr pRotatedBackground; + PixmapPtr pRotatedBorder; + } mfbPrivWin; + +/* Common macros for extracting drawing information */ + +#define mfbGetTypedWidth(pDrawable,wtype) (\ + (((pDrawable)->type == DRAWABLE_WINDOW) ? \ + (int) (((PixmapPtr)((pDrawable)->pScreen->devPrivate))->devKind) : \ + (int)(((PixmapPtr)pDrawable)->devKind)) / sizeof (wtype)) + +#define mfbGetByteWidth(pDrawable) mfbGetTypedWidth(pDrawable, unsigned char) + +#define mfbGetPixelWidth(pDrawable) mfbGetTypedWidth(pDrawable, PixelType) + +#define mfbGetTypedWidthAndPointer(pDrawable, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix; \ + if ((pDrawable)->type == DRAWABLE_WINDOW) \ + _pPix = (PixmapPtr) (pDrawable)->pScreen->devPrivate; \ + else \ + _pPix = (PixmapPtr) (pDrawable); \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define mfbGetByteWidthAndPointer(pDrawable, width, pointer) \ + mfbGetTypedWidthAndPointer(pDrawable, width, pointer, unsigned char, unsigned char) + +#define mfbGetPixelWidthAndPointer(pDrawable, width, pointer) \ + mfbGetTypedWidthAndPointer(pDrawable, width, pointer, PixelType, PixelType) + +#define mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, wtype, ptype) {\ + PixmapPtr _pPix = (PixmapPtr) (pWin)->drawable.pScreen->devPrivate; \ + (pointer) = (ptype *) _pPix->devPrivate.ptr; \ + (width) = ((int) _pPix->devKind) / sizeof (wtype); \ +} + +#define mfbGetWindowPixelWidthAndPointer(pWin, width, pointer) \ + mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, PixelType, PixelType) + +#define mfbGetWindowByteWidthAndPointer(pWin, width, pointer) \ + mfbGetWindowTypedWidthAndPointer(pWin, width, pointer, char, char) + +/* mfb uses the following macros to calculate addresses in drawables. + * To support banked framebuffers, the macros come in four flavors. + * All four collapse into the same definition on unbanked devices. + * + * mfbScanlineFoo - calculate address and do bank switching + * mfbScanlineFooNoBankSwitch - calculate address, don't bank switch + * mfbScanlineFooSrc - calculate address, switch source bank + * mfbScanlineFooDst - calculate address, switch destination bank + */ + +/* The NoBankSwitch versions are the same for banked and unbanked cases */ + +#define mfbScanlineIncNoBankSwitch(_ptr, _off) _ptr += (_off) +#define mfbScanlineOffsetNoBankSwitch(_ptr, _off) ((_ptr) + (_off)) +#define mfbScanlineDeltaNoBankSwitch(_ptr, _y, _w) \ + mfbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w)) +#define mfbScanlineNoBankSwitch(_ptr, _x, _y, _w) \ + mfbScanlineOffsetNoBankSwitch(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + +#ifdef MFB_LINE_BANK + +#include "mfblinebank.h" /* get macro definitions from this file */ + +#else /* !MFB_LINE_BANK - unbanked case */ + +#define mfbScanlineInc(_ptr, _off) mfbScanlineIncNoBankSwitch(_ptr, _off) +#define mfbScanlineIncSrc(_ptr, _off) mfbScanlineInc(_ptr, _off) +#define mfbScanlineIncDst(_ptr, _off) mfbScanlineInc(_ptr, _off) + +#define mfbScanlineOffset(_ptr, _off) mfbScanlineOffsetNoBankSwitch(_ptr, _off) +#define mfbScanlineOffsetSrc(_ptr, _off) mfbScanlineOffset(_ptr, _off) +#define mfbScanlineOffsetDst(_ptr, _off) mfbScanlineOffset(_ptr, _off) + +#define mfbScanlineSrc(_ptr, _x, _y, _w) mfbScanline(_ptr, _x, _y, _w) +#define mfbScanlineDst(_ptr, _x, _y, _w) mfbScanline(_ptr, _x, _y, _w) + +#define mfbScanlineDeltaSrc(_ptr, _y, _w) mfbScanlineDelta(_ptr, _y, _w) +#define mfbScanlineDeltaDst(_ptr, _y, _w) mfbScanlineDelta(_ptr, _y, _w) + +#endif /* MFB_LINE_BANK */ + +#define mfbScanlineDelta(_ptr, _y, _w) \ + mfbScanlineOffset(_ptr, (_y) * (_w)) + +#define mfbScanline(_ptr, _x, _y, _w) \ + mfbScanlineOffset(_ptr, (_y) * (_w) + ((_x) >> MFB_PWSH)) + + +/* precomputed information about each glyph for GlyphBlt code. + this saves recalculating the per glyph information for each box. +*/ +typedef struct _pos{ + int xpos; /* xposition of glyph's origin */ + int xchar; /* x position mod 32 */ + int leftEdge; + int rightEdge; + int topEdge; + int bottomEdge; + PixelType *pdstBase; /* longword with character origin */ + int widthGlyph; /* width in bytes of this glyph */ +} TEXTPOS; + +/* reduced raster ops for mfb */ +#define RROP_BLACK GXclear +#define RROP_WHITE GXset +#define RROP_NOP GXnoop +#define RROP_INVERT GXinvert + +/* macros for mfbbitblt.c, mfbfillsp.c + these let the code do one switch on the rop per call, rather +than a switch on the rop per item (span or rectangle.) +*/ + +#define fnCLEAR(src, dst) (0) +#define fnAND(src, dst) (src & dst) +#define fnANDREVERSE(src, dst) (src & ~dst) +#define fnCOPY(src, dst) (src) +#define fnANDINVERTED(src, dst) (~src & dst) +#define fnNOOP(src, dst) (dst) +#define fnXOR(src, dst) (src ^ dst) +#define fnOR(src, dst) (src | dst) +#define fnNOR(src, dst) (~(src | dst)) +#define fnEQUIV(src, dst) (~src ^ dst) +#define fnINVERT(src, dst) (~dst) +#define fnORREVERSE(src, dst) (src | ~dst) +#define fnCOPYINVERTED(src, dst)(~src) +#define fnORINVERTED(src, dst) (~src | dst) +#define fnNAND(src, dst) (~(src & dst)) +#undef fnSET +#define fnSET(src, dst) (MfbBits)(~0) + +/* Using a "switch" statement is much faster in most cases + * since the compiler can do a look-up table or multi-way branch + * instruction, depending on the architecture. The result on + * A Sun 3/50 is at least 2.5 times faster, assuming a uniform + * distribution of RasterOp operation types. + * + * However, doing some profiling on a running system reveals + * GXcopy is the operation over 99.5% of the time and + * GXxor is the next most frequent (about .4%), so we make special + * checks for those first. + * + * Note that this requires a change to the "calling sequence" + * since we can't engineer a "switch" statement to have an lvalue. + */ +#undef DoRop +#define DoRop(result, alu, src, dst) \ +{ \ + if (alu == GXcopy) \ + result = fnCOPY (src, dst); \ + else if (alu == GXxor) \ + result = fnXOR (src, dst); \ + else \ + switch (alu) \ + { \ + case GXclear: \ + result = fnCLEAR (src, dst); \ + break; \ + case GXand: \ + result = fnAND (src, dst); \ + break; \ + case GXandReverse: \ + result = fnANDREVERSE (src, dst); \ + break; \ + case GXandInverted: \ + result = fnANDINVERTED (src, dst); \ + break; \ + default: \ + case GXnoop: \ + result = fnNOOP (src, dst); \ + break; \ + case GXor: \ + result = fnOR (src, dst); \ + break; \ + case GXnor: \ + result = fnNOR (src, dst); \ + break; \ + case GXequiv: \ + result = fnEQUIV (src, dst); \ + break; \ + case GXinvert: \ + result = fnINVERT (src, dst); \ + break; \ + case GXorReverse: \ + result = fnORREVERSE (src, dst); \ + break; \ + case GXcopyInverted: \ + result = fnCOPYINVERTED (src, dst); \ + break; \ + case GXorInverted: \ + result = fnORINVERTED (src, dst); \ + break; \ + case GXnand: \ + result = fnNAND (src, dst); \ + break; \ + case GXset: \ + result = fnSET (src, dst); \ + break; \ + } \ +} + + +/* C expression fragments for various operations. These get passed in + * as -D's on the compile command line. See mfb/Imakefile. This + * fixes XBUG 6319. + * + * This seems like a good place to point out that mfb's use of the + * words black and white is an unfortunate misnomer. In mfb code, black + * means zero, and white means one. + */ +#define MFB_OPEQ_WHITE |= +#define MFB_OPEQ_BLACK &=~ +#define MFB_OPEQ_INVERT ^= +#define MFB_EQWHOLEWORD_WHITE =~0 +#define MFB_EQWHOLEWORD_BLACK =0 +#define MFB_EQWHOLEWORD_INVERT ^=~0 +#define MFB_OP_WHITE /* nothing */ +#define MFB_OP_BLACK ~ + +#endif /* MFB_PROTOTYPES_ONLY */ +#endif /* _MFB_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbmap.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/mfbmap.h,v 1.1.2.2 1998/06/08 15:13:15 dawes Exp $ */ + +#ifndef _MFBMAP_H +#define _MFBMAP_H + +#define InverseAlu xf1bppInverseAlu +#define endtab xf1bppendtab +#define mask xf1bppmask +#define mergeRopBits xf1bppmergeRopBits +#define mergeGetRopBits xf1bppmergeGetRopBits +#define mfbAllocatePrivates xf1bppAllocatePrivates +#define mfbBSFuncRec xf1bppBSFuncRec +#define mfbBlackSolidFS xf1bppBlackSolidFS +#define mfbBlackStippleFS xf1bppBlackStippleFS +#define mfbBresD xf1bppBresD +#define mfbBresS xf1bppBresS +#define mfbChangeWindowAttributes xf1bppChangeWindowAttributes +#define mfbCloseScreen xf1bppCloseScreen +#define mfbCopyArea xf1bppCopyArea +#define mfbCopyPixmap xf1bppCopyPixmap +#define mfbCopyPlane xf1bppCopyPlane +#define mfbCopyRotatePixmap xf1bppCopyRotatePixmap +#define mfbCopyWindow xf1bppCopyWindow +#define mfbCreateColormap xf1bppCreateColormap +#define mfbCreateDefColormap xf1bppCreateDefColormap +#define mfbCreateGC xf1bppCreateGC +#define mfbCreatePixmap xf1bppCreatePixmap +#define mfbCreateWindow xf1bppCreateWindow +#define mfbDestroyColormap xf1bppDestroyColormap +#define mfbDestroyPixmap xf1bppDestroyPixmap +#define mfbDestroyWindow xf1bppDestroyWindow +#define mfbDoBitblt xf1bppDoBitblt +#define mfbDoBitbltCopy xf1bppDoBitbltCopy +#define mfbDoBitbltCopyInverted xf1bppDoBitbltCopyInverted +#define mfbDoBitbltGeneral xf1bppDoBitbltGeneral +#define mfbDoBitbltOr xf1bppDoBitbltOr +#define mfbDoBitbltXor xf1bppDoBitbltXor +#define mfbFillInScreen xf1bppFillInScreen +#define mfbFillPolyBlack xf1bppFillPolyBlack +#define mfbFillPolyInvert xf1bppFillPolyInvert +#define mfbFillPolyWhite xf1bppFillPolyWhite +#define mfbGCPrivateIndex xf1bppGCPrivateIndex +#define mfbGetGCPrivateIndex xf1bppGetGCPrivateIndex +#define mfbGetImage xf1bppGetImage +#define mfbGetInverseAlu xf1bppGetInverseAlu +#define mfbGetSpans xf1bppGetSpans +#define mfbGetWindowPixmap xf1bppGetWindowPixmap +#define mfbGetWindowPrivateIndex xf1bppGetWindowPrivateIndex +#define mfbGetmask xf1bppGetmask +#define mfbGetpartmasks xf1bppGetpartmasks +#define mfbGetrmask xf1bppGetrmask +#define mfbGetstarttab xf1bppGetstarttab +#define mfbGetendtab xf1bppGetendtab +#define mfbHorzS xf1bppHorzS +#define mfbImageGlyphBltBlack xf1bppImageGlyphBltBlack +#define mfbImageGlyphBltWhite xf1bppImageGlyphBltWhite +#define mfbInstallColormap xf1bppInstallColormap +#define mfbInvertSolidFS xf1bppInvertSolidFS +#define mfbInvertStippleFS xf1bppInvertStippleFS +#define mfbLineSD xf1bppLineSD +#define mfbLineSS xf1bppLineSS +#define mfbListInstalledColormaps xf1bppListInstalledColormaps +#define mfbMapWindow xf1bppMapWindow +#define mfbPadPixmap xf1bppPadPixmap +#define mfbPaintWindow xf1bppPaintWindow +#define mfbPixmapToRegion xf1bppPixmapToRegion +#define mfbPixmapToRegionWeak xf1bppPixmapToRegionWeak +#define mfbPolyFillArcSolid xf1bppPolyFillArcSolid +#define mfbPolyFillRect xf1bppPolyFillRect +#define mfbPolyGlyphBltBlack xf1bppPolyGlyphBltBlack +#define mfbPolyGlyphBltInvert xf1bppPolyGlyphBltInvert +#define mfbPolyGlyphBltWhite xf1bppPolyGlyphBltWhite +#define mfbPolyPoint xf1bppPolyPoint +#define mfbPositionWindow xf1bppPositionWindow +#define mfbPushPixels xf1bppPushPixels +#define mfbPushPixelsWeak xf1bppPushPixelsWeak +#define mfbPutImage xf1bppPutImage +#define mfbQueryBestSize xf1bppQueryBestSize +#define mfbQueryBestSizeWeak xf1bppQueryBestSizeWeak +#define mfbRealizeFont xf1bppRealizeFont +#define mfbRealizeFontWeak xf1bppRealizeFontWeak +#define mfbReduceRop xf1bppReduceRop +#define mfbRegisterCopyPlaneProc xf1bppRegisterCopyPlaneProc +#define mfbResolveColor xf1bppResolveColor +#define mfbRestoreAreas xf1bppRestoreAreas +#define mfbSaveAreas xf1bppSaveAreas +#define mfbScreenInit xf1bppScreenInit +#define mfbSegmentSD xf1bppSegmentSD +#define mfbSegmentSS xf1bppSegmentSS +#define mfbSetScanline xf1bppSetScanline +#define mfbSetSpans xf1bppSetSpans +#define mfbSetWindowPixmap xf1bppSetWindowPixmap +#define mfbSolidBlackArea xf1bppSolidBlackArea +#define mfbSolidInvertArea xf1bppSolidInvertArea +#define mfbSolidPP xf1bppSolidPP +#define mfbSolidWhiteArea xf1bppSolidWhiteArea +#define mfbStippleBlackArea xf1bppStippleBlackArea +#define mfbStippleInvertArea xf1bppStippleInvertArea +#define mfbStippleWhiteArea xf1bppStippleWhiteArea +#define mfbTEGlyphBltBlack xf1bppTEGlyphBltBlack +#define mfbTEGlyphBltWhite xf1bppTEGlyphBltWhite +#define mfbTileAreaPPW xf1bppTileAreaPPW +#define mfbTileAreaPPWCopy xf1bppTileAreaPPWCopy +#define mfbTileAreaPPWGeneral xf1bppTileAreaPPWGeneral +#define mfbTileFS xf1bppTileFS +#define mfbUninstallColormap xf1bppUninstallColormap +#define mfbUnmapWindow xf1bppUnmapWindow +#define mfbUnnaturalStippleFS xf1bppUnnaturalStippleFS +#define mfbUnnaturalTileFS xf1bppUnnaturalTileFS +#define mfbUnrealizeFont xf1bppUnrealizeFont +#define mfbUnrealizeFontWeak xf1bppUnrealizeFontWeak +#define mfbValidateGC xf1bppValidateGC +#define mfbVertS xf1bppVertS +#define mfbWhiteSolidFS xf1bppWhiteSolidFS +#define mfbWhiteStippleFS xf1bppWhiteStippleFS +#define mfbWindowPrivateIndex xf1bppWindowPrivateIndex +#define mfbXRotatePixmap xf1bppXRotatePixmap +#define mfbYRotatePixmap xf1bppYRotatePixmap +#define mfbZeroPolyArcSS xf1bppZeroPolyArcSS +#define partmasks xf1bpppartmasks +#define rmask xf1bpprmask +#define starttab xf1bppstarttab + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbunmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbunmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mfbunmap.h (revision 51223) @@ -0,0 +1,116 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/mfbunmap.h,v 1.1.2.1 1998/06/27 14:48:24 dawes Exp $ */ + +#ifdef _MFBMAP_H +#undef _MFBMAP_H + +#undef InverseAlu +#undef endtab +#undef mask +#undef mergeRopBits +#undef mergeGetRopBits +#undef mfbAllocatePrivates +#undef mfbBSFuncRec +#undef mfbBlackSolidFS +#undef mfbBlackStippleFS +#undef mfbBresD +#undef mfbBresS +#undef mfbChangeWindowAttributes +#undef mfbCloseScreen +#undef mfbCopyArea +#undef mfbCopyPixmap +#undef mfbCopyPlane +#undef mfbCopyRotatePixmap +#undef mfbCopyWindow +#undef mfbCreateColormap +#undef mfbCreateDefColormap +#undef mfbCreateGC +#undef mfbCreatePixmap +#undef mfbCreateWindow +#undef mfbDestroyColormap +#undef mfbDestroyPixmap +#undef mfbDestroyWindow +#undef mfbDoBitblt +#undef mfbDoBitbltCopy +#undef mfbDoBitbltCopyInverted +#undef mfbDoBitbltGeneral +#undef mfbDoBitbltOr +#undef mfbDoBitbltXor +#undef mfbFillPolyBlack +#undef mfbFillPolyInvert +#undef mfbFillPolyWhite +#undef mfbGCPrivateIndex +#undef mfbGetImage +#undef mfbGetInverseAlu +#undef mfbGetSpans +#undef mfbGetWindowPixmap +#undef mfbHorzS +#undef mfbImageGlyphBltBlack +#undef mfbImageGlyphBltWhite +#undef mfbInstallColormap +#undef mfbInvertSolidFS +#undef mfbInvertStippleFS +#undef mfbLineSD +#undef mfbLineSS +#undef mfbListInstalledColormaps +#undef mfbMapWindow +#undef mfbPadPixmap +#undef mfbPaintWindow +#undef mfbPixmapToRegion +#undef mfbPixmapToRegionWeak +#undef mfbPolyFillArcSolid +#undef mfbPolyFillRect +#undef mfbPolyGlyphBltBlack +#undef mfbPolyGlyphBltInvert +#undef mfbPolyGlyphBltWhite +#undef mfbPolyPoint +#undef mfbPositionWindow +#undef mfbPushPixels +#undef mfbPushPixelsWeak +#undef mfbPutImage +#undef mfbQueryBestSize +#undef mfbQueryBestSizeWeak +#undef mfbRealizeFont +#undef mfbRealizeFontWeak +#undef mfbReduceRop +#undef mfbRegisterCopyPlaneProc +#undef mfbResolveColor +#undef mfbRestoreAreas +#undef mfbSaveAreas +#undef mfbScreenInit +#undef mfbSegmentSD +#undef mfbSegmentSS +#undef mfbSetScanline +#undef mfbSetSpans +#undef mfbSetWindowPixmap +#undef mfbSolidBlackArea +#undef mfbSolidInvertArea +#undef mfbSolidPP +#undef mfbSolidWhiteArea +#undef mfbStippleBlackArea +#undef mfbStippleInvertArea +#undef mfbStippleWhiteArea +#undef mfbTEGlyphBltBlack +#undef mfbTEGlyphBltWhite +#undef mfbTileAreaPPW +#undef mfbTileAreaPPWCopy +#undef mfbTileAreaPPWGeneral +#undef mfbTileFS +#undef mfbUninstallColormap +#undef mfbUnmapWindow +#undef mfbUnnaturalStippleFS +#undef mfbUnnaturalTileFS +#undef mfbUnrealizeFont +#undef mfbUnrealizeFontWeak +#undef mfbValidateGC +#undef mfbVertS +#undef mfbWhiteSolidFS +#undef mfbWhiteStippleFS +#undef mfbWindowPrivateIndex +#undef mfbXRotatePixmap +#undef mfbYRotatePixmap +#undef mfbZeroPolyArcSS +#undef partmasks +#undef rmask +#undef starttab + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mi.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mi.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mi.h (revision 51223) @@ -0,0 +1,635 @@ +/* $Xorg: mi.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/mi/mi.h,v 3.9 2001/08/06 20:51:16 dawes Exp $ */ + +#ifndef MI_H +#define MI_H +#include +#include "region.h" +#include "validate.h" +#include "window.h" +#include "gc.h" +#include +#include "input.h" +#include "cursor.h" + +#define MiBits CARD32 + +typedef struct _miDash *miDashPtr; +#define EVEN_DASH 0 +#define ODD_DASH ~0 + +/* miarc.c */ + +extern void miPolyArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* mibitblt.c */ + +extern RegionPtr miCopyArea( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*xIn*/, + int /*yIn*/, + int /*widthSrc*/, + int /*heightSrc*/, + int /*xOut*/, + int /*yOut*/ +); + +extern void miOpqStipDrawable( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + RegionPtr /*prgnSrc*/, + MiBits * /*pbits*/, + int /*srcx*/, + int /*w*/, + int /*h*/, + int /*dstx*/, + int /*dsty*/ +); + +extern RegionPtr miCopyPlane( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*bitPlane*/ +); + +extern void miGetImage( + DrawablePtr /*pDraw*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/ +); + +extern void miPutImage( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*depth*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*leftPad*/, + int /*format*/, + char * /*pImage*/ +); + +/* micursor.c */ + +extern void miRecolorCursor( + ScreenPtr /*pScr*/, + CursorPtr /*pCurs*/, + Bool /*displayed*/ +); + +/* midash.c */ + +extern miDashPtr miDashLine( + int /*npt*/, + DDXPointPtr /*ppt*/, + unsigned int /*nDash*/, + unsigned char * /*pDash*/, + unsigned int /*offset*/, + int * /*pnseg*/ +); + +extern void miStepDash( + int /*dist*/, + int * /*pDashIndex*/, + unsigned char * /*pDash*/, + int /*numInDashList*/, + int * /*pDashOffset*/ +); + +/* mieq.c */ + + +#ifndef INPUT_H +typedef struct _DeviceRec *DevicePtr; +#endif + +extern Bool mieqInit( + DevicePtr /*pKbd*/, + DevicePtr /*pPtr*/ +); + +extern void mieqEnqueue( + xEventPtr /*e*/ +); + +extern void mieqSwitchScreen( + ScreenPtr /*pScreen*/, + Bool /*fromDIX*/ +); + +extern void mieqProcessInputEvents( + void +); + +/* miexpose.c */ + +extern RegionPtr miHandleExposures( + DrawablePtr /*pSrcDrawable*/, + DrawablePtr /*pDstDrawable*/, + GCPtr /*pGC*/, + int /*srcx*/, + int /*srcy*/, + int /*width*/, + int /*height*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/ +); + +extern void miSendGraphicsExpose( + ClientPtr /*client*/, + RegionPtr /*pRgn*/, + XID /*drawable*/, + int /*major*/, + int /*minor*/ +); + +extern void miSendExposures( + WindowPtr /*pWin*/, + RegionPtr /*pRgn*/, + int /*dx*/, + int /*dy*/ +); + +extern void miWindowExposures( + WindowPtr /*pWin*/, + RegionPtr /*prgn*/, + RegionPtr /*other_exposed*/ +); + +extern void miPaintWindow( + WindowPtr /*pWin*/, + RegionPtr /*prgn*/, + int /*what*/ +); + +extern void miClearDrawable( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/ +); + +/* mifillrct.c */ + +extern void miPolyFillRect( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*nrectFill*/, + xRectangle * /*prectInit*/ +); + +/* miglblt.c */ + +extern void miPolyGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +extern void miImageGlyphBlt( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + unsigned int /*nglyph*/, + CharInfoPtr * /*ppci*/, + pointer /*pglyphBase*/ +); + +/* mipoly.c */ + +extern void miFillPolygon( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*shape*/, + int /*mode*/, + int /*count*/, + DDXPointPtr /*pPts*/ +); + +/* mipolycon.c */ + +extern Bool miFillConvexPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mipolygen.c */ + +extern Bool miFillGeneralPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + DDXPointPtr /*ptsIn*/ +); + +/* mipolypnt.c */ + +extern void miPolyPoint( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + xPoint * /*pptInit*/ +); + +/* mipolyrect.c */ + +extern void miPolyRectangle( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nrects*/, + xRectangle * /*pRects*/ +); + +/* mipolyseg.c */ + +extern void miPolySegment( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*nseg*/, + xSegment * /*pSegs*/ +); + +/* mipolytext.c */ + +extern int miPolyText( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/, + FontEncoding /*fontEncoding*/ +); + +extern int miPolyText8( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/ +); + +extern int miPolyText16( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/ +); + +extern int miImageText( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/, + FontEncoding /*fontEncoding*/ +); + +extern void miImageText8( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + char * /*chars*/ +); + +extern void miImageText16( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*x*/, + int /*y*/, + int /*count*/, + unsigned short * /*chars*/ +); + +/* mipushpxl.c */ + +extern void miPushPixels( + GCPtr /*pGC*/, + PixmapPtr /*pBitMap*/, + DrawablePtr /*pDrawable*/, + int /*dx*/, + int /*dy*/, + int /*xOrg*/, + int /*yOrg*/ +); + +/* miregion.c */ + +/* see also region.h */ + +extern Bool miRectAlloc( + RegionPtr /*pRgn*/, + int /*n*/ +); + +extern void miSetExtents( + RegionPtr /*pReg*/ +); + +extern int miFindMaxBand( + RegionPtr /*prgn*/ +); + +#ifdef DEBUG +extern Bool miValidRegion( + RegionPtr /*prgn*/ +); +#endif + +extern Bool miRegionDataCopy(RegionPtr dst, RegionPtr src); +extern Bool miRegionBroken(RegionPtr pReg); + +/* miscrinit.c */ + +extern Bool miModifyPixmapHeader( + PixmapPtr /*pPixmap*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/ +); + +extern Bool miCloseScreen( + int /*index*/, + ScreenPtr /*pScreen*/ +); + +extern Bool miCreateScreenResources( + ScreenPtr /*pScreen*/ +); + +extern Bool miScreenDevPrivateInit( + ScreenPtr /*pScreen*/, + int /*width*/, + pointer /*pbits*/ +); + +extern Bool miScreenInit( + ScreenPtr /*pScreen*/, + pointer /*pbits*/, + int /*xsize*/, + int /*ysize*/, + int /*dpix*/, + int /*dpiy*/, + int /*width*/, + int /*rootDepth*/, + int /*numDepths*/, + DepthPtr /*depths*/, + VisualID /*rootVisual*/, + int /*numVisuals*/, + VisualPtr /*visuals*/ +); + +extern int miAllocateGCPrivateIndex( + void +); + +extern PixmapPtr miGetScreenPixmap( + ScreenPtr pScreen +); + +extern void miSetScreenPixmap( + PixmapPtr pPix +); + +/* mivaltree.c */ + +extern int miShapedWindowIn( + ScreenPtr /*pScreen*/, + RegionPtr /*universe*/, + RegionPtr /*bounding*/, + BoxPtr /*rect*/, + int /*x*/, + int /*y*/ +); + +typedef void +(*SetRedirectBorderClipProcPtr) (WindowPtr pWindow, RegionPtr pRegion); + +typedef RegionPtr +(*GetRedirectBorderClipProcPtr) (WindowPtr pWindow); + +void +miRegisterRedirectBorderClipProc (SetRedirectBorderClipProcPtr setBorderClip, + GetRedirectBorderClipProcPtr getBorderClip); + +extern int miValidateTree( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/ +); + +extern void miWideLine( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pPts*/ +); + +extern void miWideDash( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + int /*mode*/, + int /*npt*/, + DDXPointPtr /*pPts*/ +); + +extern void miMiter( + void +); + +extern void miNotMiter( + void +); + +/* miwindow.c */ + +extern void miClearToBackground( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/ +); + +extern Bool miChangeSaveUnder( + WindowPtr /*pWin*/, + WindowPtr /*first*/ +); + +extern void miPostChangeSaveUnder( + WindowPtr /*pWin*/, + WindowPtr /*pFirst*/ +); + +extern void miMarkWindow( + WindowPtr /*pWin*/ +); + +extern Bool miMarkOverlappedWindows( + WindowPtr /*pWin*/, + WindowPtr /*pFirst*/, + WindowPtr * /*ppLayerWin*/ +); + +extern void miHandleValidateExposures( + WindowPtr /*pWin*/ +); + +extern void miMoveWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + WindowPtr /*pNextSib*/, + VTKind /*kind*/ +); + +extern void miSlideAndSizeWindow( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + WindowPtr /*pSib*/ +); + +extern WindowPtr miGetLayerWindow( + WindowPtr /*pWin*/ +); + +extern void miSetShape( + WindowPtr /*pWin*/ +); + +extern void miChangeBorderWidth( + WindowPtr /*pWin*/, + unsigned int /*width*/ +); + +extern void miMarkUnrealizedWindow( + WindowPtr /*pChild*/, + WindowPtr /*pWin*/, + Bool /*fromConfigure*/ +); + +extern void miSegregateChildren(WindowPtr pWin, RegionPtr pReg, int depth); + +/* mizerarc.c */ + +extern void miZeroPolyArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +/* mizerline.c */ + +extern void miZeroLine( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*mode*/, + int /*nptInit*/, + DDXPointRec * /*pptInit*/ +); + +extern void miZeroDashLine( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*mode*/, + int /*nptInit*/, + DDXPointRec * /*pptInit*/ +); + +extern void miPolyFillArc( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + int /*narcs*/, + xArc * /*parcs*/ +); + +#endif /* MI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibank.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibank.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibank.h (revision 51223) @@ -0,0 +1,119 @@ +/* + * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of Marc Aurele La France not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. Marc Aurele La France makes no representations + * about the suitability of this software for any purpose. It is provided + * "as-is" without express or implied warranty. + * + * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/mi/mibank.h,v 1.10 2003/01/01 19:16:42 tsi Exp $ */ + +#ifndef __MIBANK_H__ +#define __MIBANK_H__ 1 + +#include "scrnintstr.h" + +/* + * Banking external interface. + */ + +/* + * This is the banking function type. The return value is normally zero. + * Non-zero returns can be used to implement the likes of scanline interleave, + * etc. + */ +typedef int miBankProc( + ScreenPtr /*pScreen*/, + unsigned int /*iBank*/ +); + +typedef miBankProc *miBankProcPtr; + +typedef struct _miBankInfo +{ + /* + * Banking refers to the use of one or more apertures (in the server's + * address space) to access various parts of a potentially larger hardware + * frame buffer. + * + * Three different banking schemes are supported: + * + * Single banking is indicated when pBankA and pBankB are equal and all + * three miBankProcPtr's point to the same function. Here, both reads and + * writes through the aperture access the same hardware location. + * + * Shared banking is indicated when pBankA and pBankB are equal but the + * source and destination functions differ. Here reads through the + * aperture do not necessarily access the same hardware location as writes. + * + * Double banking is indicated when pBankA and pBankB differ. Here two + * independent apertures are used to provide read/write access to + * potentially different hardware locations. + * + * Any other combination will result in no banking. + */ + miBankProcPtr SetSourceBank; /* Set pBankA bank number */ + miBankProcPtr SetDestinationBank; /* Set pBankB bank number */ + miBankProcPtr SetSourceAndDestinationBanks; /* Set both bank numbers */ + + pointer pBankA; /* First aperture location */ + pointer pBankB; /* First or second aperture location */ + + /* + * BankSize is in units of sizeof(char) and is the size of each bank. + */ + unsigned long BankSize; + + /* + * nBankDepth is the colour depth associated with the maximum number of a + * pixel's bits that are simultaneously accessible through the frame buffer + * aperture. + */ + unsigned int nBankDepth; +} miBankInfoRec, *miBankInfoPtr; + +Bool +miInitializeBanking( + ScreenPtr /*pScreen*/, + unsigned int /*xsize*/, + unsigned int /*ysize*/, + unsigned int /*width*/, + miBankInfoPtr /*pBankInfo*/ +); + +Bool +miModifyBanking( + ScreenPtr /*pScreen*/, + miBankInfoPtr /*pBankInfo*/ +); + +/* + * This function determines the minimum screen width, given a initial estimate + * and various screen attributes. DDX needs to determine this width before + * initializing the screen. + */ +int +miScanLineWidth( + unsigned int /*xsize*/, + unsigned int /*ysize*/, + unsigned int /*width*/, + unsigned long /*BankSize*/, + PixmapFormatRec * /*pBankFormat*/, + unsigned int /*nWidthUnit*/ +); + +#endif /* __MIBANK_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstore.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstore.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstore.h (revision 51223) @@ -0,0 +1,30 @@ +/*- + * mibstore.h -- + * Header file for users of the MI backing-store scheme. + * + * Copyright (c) 1987 by the Regents of the University of California + * + * Permission to use, copy, modify, and distribute this + * software and its documentation for any purpose and without + * fee is hereby granted, provided that the above copyright + * notice appear in all copies. The University of California + * makes no representations about the suitability of this + * software for any purpose. It is provided "as is" without + * express or implied warranty. + * + * "$Xorg: mibstore.h,v 1.3 2000/08/17 19:53:37 cpqbld Exp $ + */ + + +/* $XFree86: xc/programs/Xserver/mi/mibstore.h,v 1.4 2001/01/17 22:37:06 dawes Exp $ */ + +#ifndef _MIBSTORE_H +#define _MIBSTORE_H + +#include "screenint.h" + +extern void miInitializeBackingStore( + ScreenPtr /*pScreen*/ +); + +#endif /* _MIBSTORE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstorest.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstorest.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mibstorest.h (revision 51223) @@ -0,0 +1,93 @@ +/* + * mibstorest.h + * + * internal structure definitions for mi backing store + */ + +/* $Xorg: mibstorest.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ + +/* $XFree86: xc/programs/Xserver/mi/mibstorest.h,v 1.4 2001/01/17 22:37:06 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "mibstore.h" +#include "regionstr.h" + +/* + * One of these structures is allocated per GC used with a backing-store + * drawable. + */ + +typedef struct { + GCPtr pBackingGC; /* Copy of the GC but with graphicsExposures + * set FALSE and the clientClip set to + * clip output to the valid regions of the + * backing pixmap. */ + int guarantee; /* GuaranteeNothing, etc. */ + unsigned long serialNumber; /* clientClip computed time */ + unsigned long stateChanges; /* changes in parent gc since last copy */ + GCOps *wrapOps; /* wrapped ops */ + GCFuncs *wrapFuncs; /* wrapped funcs */ +} miBSGCRec, *miBSGCPtr; + +/* + * one of these structures is allocated per Window with backing store + */ + +typedef struct { + PixmapPtr pBackingPixmap; /* Pixmap for saved areas */ + short x; /* origin of pixmap relative to window */ + short y; + RegionRec SavedRegion; /* Valid area in pBackingPixmap */ + char viewable; /* Tracks pWin->viewable so SavedRegion may + * be initialized correctly when the window + * is first mapped */ + char status; /* StatusNoPixmap, etc. */ + char backgroundState; /* background type */ + PixUnion background; /* background pattern */ +} miBSWindowRec, *miBSWindowPtr; + +#define StatusNoPixmap 1 /* pixmap has not been created */ +#define StatusVirtual 2 /* pixmap is virtual, tiled with background */ +#define StatusVDirty 3 /* pixmap is virtual, visiblt has contents */ +#define StatusBadAlloc 4 /* pixmap create failed, do not try again */ +#define StatusContents 5 /* pixmap is created, has valid contents */ + +typedef struct { + /* + * screen func wrappers + */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + CreateGCProcPtr CreateGC; + DestroyWindowProcPtr DestroyWindow; +} miBSScreenRec, *miBSScreenPtr; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micmap.h (revision 51223) @@ -0,0 +1,65 @@ +/* $XFree86: xc/programs/Xserver/mi/micmap.h,v 1.5 1999/06/14 07:32:11 dawes Exp $ */ + +#include "colormapst.h" + +#ifndef _MICMAP_H_ +#define _MICMAP_H_ + +extern ColormapPtr miInstalledMaps[MAXSCREENS]; + +typedef Bool (* miInitVisualsProcPtr)(VisualPtr *, DepthPtr *, int *, int *, + int *, VisualID *, unsigned long, int, + int); + +extern miInitVisualsProcPtr miInitVisualsProc; + +int miListInstalledColormaps(ScreenPtr pScreen, Colormap *pmaps); +void miInstallColormap(ColormapPtr pmap); +void miUninstallColormap(ColormapPtr pmap); + +void miResolveColor(unsigned short *, unsigned short *, unsigned short *, + VisualPtr); +Bool miInitializeColormap(ColormapPtr); +int miExpandDirectColors(ColormapPtr, int, xColorItem *, xColorItem *); +Bool miCreateDefColormap(ScreenPtr); +void miClearVisualTypes(void); +Bool miSetVisualTypes(int, int, int, int); +Bool miSetPixmapDepths(void); +Bool miSetVisualTypesAndMasks(int depth, int visuals, int bitsPerRGB, + int preferredCVC, + Pixel redMask, Pixel greenMask, Pixel blueMask); +int miGetDefaultVisualMask(int); +Bool miInitVisuals(VisualPtr *, DepthPtr *, int *, int *, int *, VisualID *, + unsigned long, int, int); +void miResetInitVisuals(void); + +void miHookInitVisuals(void (**old)(miInitVisualsProcPtr *), + void (*new)(miInitVisualsProcPtr *)); + + +#define MAX_PSEUDO_DEPTH 10 +#define MIN_TRUE_DEPTH 6 + +#define StaticGrayMask (1 << StaticGray) +#define GrayScaleMask (1 << GrayScale) +#define StaticColorMask (1 << StaticColor) +#define PseudoColorMask (1 << PseudoColor) +#define TrueColorMask (1 << TrueColor) +#define DirectColorMask (1 << DirectColor) + +#define ALL_VISUALS (StaticGrayMask|\ + GrayScaleMask|\ + StaticColorMask|\ + PseudoColorMask|\ + TrueColorMask|\ + DirectColorMask) + +#define LARGE_VISUALS (TrueColorMask|\ + DirectColorMask) + +#define SMALL_VISUALS (StaticGrayMask|\ + GrayScaleMask|\ + StaticColorMask|\ + PseudoColorMask) + +#endif /* _MICMAP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micoord.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micoord.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/micoord.h (revision 51223) @@ -0,0 +1,71 @@ +/* $XFree86: xc/programs/Xserver/mi/micoord.h,v 1.7 2003/10/29 22:57:48 tsi Exp $ */ +/* + * Copyright (C) 2000 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + * + */ + +#ifndef _MICOORD_H_ +#define _MICOORD_H_ 1 + +#include "servermd.h" + +/* Macros which handle a coordinate in a single register */ + +/* + * Most compilers will convert divisions by 65536 into shifts, if signed + * shifts exist. If your machine does arithmetic shifts and your compiler + * can't get it right, add to this line. + */ + +/* + * mips compiler - what a joke - it CSEs the 65536 constant into a reg + * forcing as to use div instead of shift. Let's be explicit. + */ + +#if defined(mips) || defined(sgi) || \ + defined(sparc) || defined(__sparc64__) || \ + defined(__alpha) || defined(__alpha__) || \ + defined(__i386__) || defined(i386) || \ + defined(__ia64__) || defined(ia64) || \ + defined(__s390x__) || defined(__s390__) || \ + defined(__amd64__) || defined(amd64) || defined(__amd64) +#define GetHighWord(x) (((int) (x)) >> 16) +#else +#define GetHighWord(x) (((int) (x)) / 65536) +#endif + +#if IMAGE_BYTE_ORDER == MSBFirst +#define intToCoord(i,x,y) (((x) = GetHighWord(i)), ((y) = (int) ((short) (i)))) +#define coordToInt(x,y) (((x) << 16) | ((y) & 0xffff)) +#define intToX(i) (GetHighWord(i)) +#define intToY(i) ((int) ((short) i)) +#else +#define intToCoord(i,x,y) (((x) = (int) ((short) (i))), ((y) = GetHighWord(i))) +#define coordToInt(x,y) (((y) << 16) | ((x) & 0xffff)) +#define intToX(i) ((int) ((short) (i))) +#define intToY(i) (GetHighWord(i)) +#endif + +#endif /* _MICOORD_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbe.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbe.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbe.h (revision 51223) @@ -0,0 +1,51 @@ +/* $Xorg: midbe.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for users of machine-independent DBE code + * + *****************************************************************************/ +/* $XFree86$ */ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIDBE_H +#define MIDBE_H + +/* EXTERNS */ + +extern Bool miDbeInit( + ScreenPtr pScreen, + DbeScreenPrivPtr pDbeScreenPriv +); + +#endif /* MIDBE_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/midbestr.h (revision 51223) @@ -0,0 +1,100 @@ +/* $Xorg: midbestr.h,v 1.3 2000/08/17 19:48:16 cpqbld Exp $ */ +/****************************************************************************** + * + * Copyright (c) 1994, 1995 Hewlett-Packard Company + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL HEWLETT-PACKARD COMPANY BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR + * THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the Hewlett-Packard + * Company shall not be used in advertising or otherwise to promote the + * sale, use or other dealings in this Software without prior written + * authorization from the Hewlett-Packard Company. + * + * Header file for users of machine-independent DBE code + * + *****************************************************************************/ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIDBE_STRUCT_H +#define MIDBE_STRUCT_H + + +/* DEFINES */ + +#define MI_DBE_WINDOW_PRIV_PRIV(pDbeWindowPriv) \ + (((miDbeWindowPrivPrivIndex < 0) || (!pDbeWindowPriv)) ? \ + NULL : \ + ((MiDbeWindowPrivPrivPtr) \ + ((pDbeWindowPriv)->devPrivates[miDbeWindowPrivPrivIndex].ptr))) + +#define MI_DBE_WINDOW_PRIV_PRIV_FROM_WINDOW(pWin)\ + MI_DBE_WINDOW_PRIV_PRIV(DBE_WINDOW_PRIV(pWin)) + +#define MI_DBE_SCREEN_PRIV_PRIV(pDbeScreenPriv) \ + (((miDbeScreenPrivPrivIndex < 0) || (!pDbeScreenPriv)) ? \ + NULL : \ + ((MiDbeScreenPrivPrivPtr) \ + ((pDbeScreenPriv)->devPrivates[miDbeScreenPrivPrivIndex].ptr))) + + +/* TYPEDEFS */ + +typedef struct _MiDbeWindowPrivPrivRec +{ + /* Place machine-specific fields in here. + * Since this is mi code, we do not really have machine-specific fields. + */ + + /* Pointer to a drawable that contains the contents of the back buffer. + */ + PixmapPtr pBackBuffer; + + /* Pointer to a drawable that contains the contents of the front buffer. + * This pointer is only used for the XdbeUntouched swap action. For that + * swap action, we need to copy the front buffer (window) contents into + * this drawable, copy the contents of current back buffer drawable (the + * back buffer) into the window, swap the front and back drawable pointers, + * and then swap the drawable/resource associations in the resource + * database. + */ + PixmapPtr pFrontBuffer; + + /* Pointer back to our window private with which we are associated. */ + DbeWindowPrivPtr pDbeWindowPriv; + +} MiDbeWindowPrivPrivRec, *MiDbeWindowPrivPrivPtr; + +typedef struct _MiDbeScreenPrivPrivRec +{ + /* Place machine-specific fields in here. + * Since this is mi code, we do not really have machine-specific fields. + */ + + /* Pointer back to our screen private with which we are associated. */ + DbeScreenPrivPtr pDbeScreenPriv; + +} MiDbeScreenPrivPrivRec, *MiDbeScreenPrivPrivPtr; + +#endif /* MIDBE_STRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifillarc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifillarc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifillarc.h (revision 51223) @@ -0,0 +1,216 @@ +/* $XFree86: xc/programs/Xserver/mi/mifillarc.h,v 3.6 2001/10/25 12:03:47 alanh Exp $ */ +/************************************************************ + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +********************************************************/ + +/* $Xorg: mifillarc.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ + +#ifndef __MIFILLARC_H__ +#define __MIFILLARC_H__ + +#define FULLCIRCLE (360 * 64) + +typedef struct _miFillArc { + int xorg, yorg; + int y; + int dx, dy; + int e; + int ym, yk, xm, xk; +} miFillArcRec; + +/* could use 64-bit integers */ +typedef struct _miFillArcD { + int xorg, yorg; + int y; + int dx, dy; + double e; + double ym, yk, xm, xk; +} miFillArcDRec; + +#define miFillArcEmpty(arc) (!(arc)->angle2 || \ + !(arc)->width || !(arc)->height || \ + (((arc)->width == 1) && ((arc)->height & 1))) + +#define miCanFillArc(arc) (((arc)->width == (arc)->height) || \ + (((arc)->width <= 800) && ((arc)->height <= 800))) + +#define MIFILLARCSETUP() \ + x = 0; \ + y = info.y; \ + e = info.e; \ + xk = info.xk; \ + xm = info.xm; \ + yk = info.yk; \ + ym = info.ym; \ + dx = info.dx; \ + dy = info.dy; \ + xorg = info.xorg; \ + yorg = info.yorg + +#define MIFILLARCSTEP(slw) \ + e += yk; \ + while (e >= 0) \ + { \ + x++; \ + xk -= xm; \ + e += xk; \ + } \ + y--; \ + yk -= ym; \ + slw = (x << 1) + dx; \ + if ((e == xk) && (slw > 1)) \ + slw-- + +#define MIFILLCIRCSTEP(slw) MIFILLARCSTEP(slw) +#define MIFILLELLSTEP(slw) MIFILLARCSTEP(slw) + +#define miFillArcLower(slw) (((y + dy) != 0) && ((slw > 1) || (e != xk))) + +typedef struct _miSliceEdge { + int x; + int stepx; + int deltax; + int e; + int dy; + int dx; +} miSliceEdgeRec, *miSliceEdgePtr; + +typedef struct _miArcSlice { + miSliceEdgeRec edge1, edge2; + int min_top_y, max_top_y; + int min_bot_y, max_bot_y; + Bool edge1_top, edge2_top; + Bool flip_top, flip_bot; +} miArcSliceRec; + +#define MIARCSLICESTEP(edge) \ + edge.x -= edge.stepx; \ + edge.e -= edge.dx; \ + if (edge.e <= 0) \ + { \ + edge.x -= edge.deltax; \ + edge.e += edge.dy; \ + } + +#define miFillSliceUpper(slice) \ + ((y >= slice.min_top_y) && (y <= slice.max_top_y)) + +#define miFillSliceLower(slice) \ + ((y >= slice.min_bot_y) && (y <= slice.max_bot_y)) + +#define MIARCSLICEUPPER(xl,xr,slice,slw) \ + xl = xorg - x; \ + xr = xl + slw - 1; \ + if (slice.edge1_top && (slice.edge1.x < xr)) \ + xr = slice.edge1.x; \ + if (slice.edge2_top && (slice.edge2.x > xl)) \ + xl = slice.edge2.x; + +#define MIARCSLICELOWER(xl,xr,slice,slw) \ + xl = xorg - x; \ + xr = xl + slw - 1; \ + if (!slice.edge1_top && (slice.edge1.x > xl)) \ + xl = slice.edge1.x; \ + if (!slice.edge2_top && (slice.edge2.x < xr)) \ + xr = slice.edge2.x; + +#define MIWIDEARCSETUP(x,y,dy,slw,e,xk,xm,yk,ym) \ + x = 0; \ + y = slw >> 1; \ + yk = y << 3; \ + xm = 8; \ + ym = 8; \ + if (dy) \ + { \ + xk = 0; \ + if (slw & 1) \ + e = -1; \ + else \ + e = -(y << 2) - 2; \ + } \ + else \ + { \ + y++; \ + yk += 4; \ + xk = -4; \ + if (slw & 1) \ + e = -(y << 2) - 3; \ + else \ + e = - (y << 3); \ + } + +#define MIFILLINARCSTEP(slw) \ + ine += inyk; \ + while (ine >= 0) \ + { \ + inx++; \ + inxk -= inxm; \ + ine += inxk; \ + } \ + iny--; \ + inyk -= inym; \ + slw = (inx << 1) + dx; \ + if ((ine == inxk) && (slw > 1)) \ + slw-- + +#define miFillInArcLower(slw) (((iny + dy) != 0) && \ + ((slw > 1) || (ine != inxk))) + +extern int miFreeArcCache( + pointer /*data*/, + XID /*id*/ +); + +extern struct finalSpan *realAllocSpan( + void +); + +extern void miFillArcSetup( + xArc * /*arc*/, + miFillArcRec * /*info*/ +); + +extern void miFillArcDSetup( + xArc * /*arc*/, + miFillArcDRec * /*info*/ +); + +extern void miEllipseAngleToSlope( + int /*angle*/, + int /*width*/, + int /*height*/, + int * /*dxp*/, + int * /*dyp*/, + double * /*d_dxp*/, + double * /*d_dyp*/ +); + +extern void miFillArcSliceSetup( + xArc * /*arc*/, + miArcSliceRec * /*slice*/, + GCPtr /*pGC*/ +); + +#endif /* __MIFILLARC_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifpoly.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifpoly.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mifpoly.h (revision 51223) @@ -0,0 +1,111 @@ +/* $Xorg: mifpoly.h,v 1.4 2001/02/09 02:05:20 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/mi/mifpoly.h,v 1.3 2001/10/25 12:03:47 alanh Exp $ */ + +#ifndef __MIFPOLY_H__ +#define __MIFPOLY_H__ + +#define EPSILON 0.000001 +#define ISEQUAL(a,b) (Fabs((a) - (b)) <= EPSILON) +#define UNEQUAL(a,b) (Fabs((a) - (b)) > EPSILON) +#define WITHINHALF(a, b) (((a) - (b) > 0.0) ? (a) - (b) < 0.5 : \ + (b) - (a) <= 0.5) +#define ROUNDTOINT(x) ((int) (((x) > 0.0) ? ((x) + 0.5) : ((x) - 0.5))) +#define ISZERO(x) (Fabs((x)) <= EPSILON) +#define PTISEQUAL(a,b) (ISEQUAL(a.x,b.x) && ISEQUAL(a.y,b.y)) +#define PTUNEQUAL(a,b) (UNEQUAL(a.x,b.x) || UNEQUAL(a.y,b.y)) +#define PtEqual(a, b) (((a).x == (b).x) && ((a).y == (b).y)) + +#define NotEnd 0 +#define FirstEnd 1 +#define SecondEnd 2 + +#define SQSECANT 108.856472512142 /* 1/sin^2(11/2) - for 11o miter cutoff */ +#define D2SECANT 5.21671526231167 /* 1/2*sin(11/2) - max extension per width */ + +#ifdef NOINLINEICEIL +#define ICEIL(x) ((int)ceil(x)) +#else +#ifdef __GNUC__ +static __inline int ICEIL(double x) +{ + int _cTmp = x; + return ((x == _cTmp) || (x < 0.0)) ? _cTmp : _cTmp+1; +} +#else +#define ICEIL(x) ((((x) == (_cTmp = (x))) || ((x) < 0.0)) ? _cTmp : _cTmp+1) +#define ICEILTEMPDECL static int _cTmp; +#endif +#endif + +/* Point with sub-pixel positioning. In this case we use doubles, but + * see mifpolycon.c for other suggestions + */ +typedef struct _SppPoint { + double x, y; +} SppPointRec, *SppPointPtr; + +typedef struct _SppArc { + double x, y, width, height; + double angle1, angle2; +} SppArcRec, *SppArcPtr; + +/* mifpolycon.c */ + +extern void miFillSppPoly( + DrawablePtr /*dst*/, + GCPtr /*pgc*/, + int /*count*/, + SppPointPtr /*ptsIn*/, + int /*xTrans*/, + int /*yTrans*/, + double /*xFtrans*/, + double /*yFtrans*/ +); + +#endif /* __MIFPOLY_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/migc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/migc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/migc.h (revision 51223) @@ -0,0 +1,74 @@ +/* $Xorg: migc.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1993, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ + +/* $XFree86: xc/programs/Xserver/mi/migc.h,v 1.7 2001/08/06 20:51:18 dawes Exp $ */ + +extern void miChangeGC( + GCPtr /*pGC*/, + unsigned long /*mask*/ +); + +extern void miDestroyGC( + GCPtr /*pGC*/ +); + +extern GCOpsPtr miCreateGCOps( + GCOpsPtr /*prototype*/ +); + +extern void miDestroyGCOps( + GCOpsPtr /*ops*/ +); + +extern void miDestroyClip( + GCPtr /*pGC*/ +); + +extern void miChangeClip( + GCPtr /*pGC*/, + int /*type*/, + pointer /*pvalue*/, + int /*nrects*/ +); + +extern void miCopyClip( + GCPtr /*pgcDst*/, + GCPtr /*pgcSrc*/ +); + +extern void miCopyGC( + GCPtr /*pGCSrc*/, + unsigned long /*changes*/, + GCPtr /*pGCDst*/ +); + +extern void miComputeCompositeClip( + GCPtr /*pGC*/, + DrawablePtr /*pDrawable*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miline.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miline.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miline.h (revision 51223) @@ -0,0 +1,174 @@ +/* $Xorg: miline.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1994, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/miline.h,v 1.6 2001/08/06 20:51:19 dawes Exp $ */ + +#ifndef MILINE_H + +#include "screenint.h" + +/* + * Public definitions used for configuring basic pixelization aspects + * of the sample implementation line-drawing routines provided in + * {mfb,mi,cfb*} at run-time. + */ + +#define XDECREASING 4 +#define YDECREASING 2 +#define YMAJOR 1 + +#define OCTANT1 (1 << (YDECREASING)) +#define OCTANT2 (1 << (YDECREASING|YMAJOR)) +#define OCTANT3 (1 << (XDECREASING|YDECREASING|YMAJOR)) +#define OCTANT4 (1 << (XDECREASING|YDECREASING)) +#define OCTANT5 (1 << (XDECREASING)) +#define OCTANT6 (1 << (XDECREASING|YMAJOR)) +#define OCTANT7 (1 << (YMAJOR)) +#define OCTANT8 (1 << (0)) + +#define XMAJOROCTANTS (OCTANT1 | OCTANT4 | OCTANT5 | OCTANT8) + +#define DEFAULTZEROLINEBIAS (OCTANT2 | OCTANT3 | OCTANT4 | OCTANT5) + +/* + * Devices can configure the rendering of routines in mi, mfb, and cfb* + * by specifying a thin line bias to be applied to a particular screen + * using the following function. The bias parameter is an OR'ing of + * the appropriate OCTANT constants defined above to indicate which + * octants to bias a line to prefer an axial step when the Bresenham + * error term is exactly zero. The octants are mapped as follows: + * + * \ | / + * \ 3 | 2 / + * \ | / + * 4 \ | / 1 + * \|/ + * ----------- + * /|\ + * 5 / | \ 8 + * / | \ + * / 6 | 7 \ + * / | \ + * + * For more information, see "Ambiguities in Incremental Line Rastering," + * Jack E. Bresenham, IEEE CG&A, May 1987. + */ + +extern void miSetZeroLineBias( + ScreenPtr /* pScreen */, + unsigned int /* bias */ +); + +/* + * Private definitions needed for drawing thin (zero width) lines + * Used by the mi, mfb, and all cfb* components. + */ + +#define X_AXIS 0 +#define Y_AXIS 1 + +#define OUT_LEFT 0x08 +#define OUT_RIGHT 0x04 +#define OUT_ABOVE 0x02 +#define OUT_BELOW 0x01 + +#define OUTCODES(_result, _x, _y, _pbox) \ + if ( (_x) < (_pbox)->x1) (_result) |= OUT_LEFT; \ + else if ( (_x) >= (_pbox)->x2) (_result) |= OUT_RIGHT; \ + if ( (_y) < (_pbox)->y1) (_result) |= OUT_ABOVE; \ + else if ( (_y) >= (_pbox)->y2) (_result) |= OUT_BELOW; + +#define MIOUTCODES(outcode, x, y, xmin, ymin, xmax, ymax) \ +{\ + if (x < xmin) outcode |= OUT_LEFT;\ + if (x > xmax) outcode |= OUT_RIGHT;\ + if (y < ymin) outcode |= OUT_ABOVE;\ + if (y > ymax) outcode |= OUT_BELOW;\ +} + +#define SWAPINT(i, j) \ +{ register int _t = i; i = j; j = _t; } + +#define SWAPPT(i, j) \ +{ DDXPointRec _t; _t = i; i = j; j = _t; } + +#define SWAPINT_PAIR(x1, y1, x2, y2)\ +{ int t = x1; x1 = x2; x2 = t;\ + t = y1; y1 = y2; y2 = t;\ +} + +#define miGetZeroLineBias(_pScreen) \ + ((miZeroLineScreenIndex < 0) ? \ + 0 : ((_pScreen)->devPrivates[miZeroLineScreenIndex].uval)) + +#define CalcLineDeltas(_x1,_y1,_x2,_y2,_adx,_ady,_sx,_sy,_SX,_SY,_octant) \ + (_octant) = 0; \ + (_sx) = (_SX); \ + if (((_adx) = (_x2) - (_x1)) < 0) { \ + (_adx) = -(_adx); \ + (_sx = -(_sx)); \ + (_octant) |= XDECREASING; \ + } \ + (_sy) = (_SY); \ + if (((_ady) = (_y2) - (_y1)) < 0) { \ + (_ady) = -(_ady); \ + (_sy = -(_sy)); \ + (_octant) |= YDECREASING; \ + } + +#define SetYMajorOctant(_octant) ((_octant) |= YMAJOR) + +#define FIXUP_ERROR(_e, _octant, _bias) \ + (_e) -= (((_bias) >> (_octant)) & 1) + +#define IsXMajorOctant(_octant) (!((_octant) & YMAJOR)) +#define IsYMajorOctant(_octant) ((_octant) & YMAJOR) +#define IsXDecreasingOctant(_octant) ((_octant) & XDECREASING) +#define IsYDecreasingOctant(_octant) ((_octant) & YDECREASING) + +extern int miZeroLineScreenIndex; + +extern int miZeroClipLine( + int /*xmin*/, + int /*ymin*/, + int /*xmax*/, + int /*ymax*/, + int * /*new_x1*/, + int * /*new_y1*/, + int * /*new_x2*/, + int * /*new_y2*/, + unsigned int /*adx*/, + unsigned int /*ady*/, + int * /*pt1_clipped*/, + int * /*pt2_clipped*/, + int /*octant*/, + unsigned int /*bias*/, + int /*oc1*/, + int /*oc2*/ +); + +#endif /* MILINE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mioverlay.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mioverlay.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mioverlay.h (revision 51223) @@ -0,0 +1,33 @@ +/* $XFree86: xc/programs/Xserver/mi/mioverlay.h,v 3.3 2000/02/29 00:16:03 mvojkovi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef __MIOVERLAY_H +#define __MIOVERLAY_H + +typedef void (*miOverlayTransFunc)(ScreenPtr, int, BoxPtr); +typedef Bool (*miOverlayInOverlayFunc)(WindowPtr); + +Bool +miInitOverlay( + ScreenPtr pScreen, + miOverlayInOverlayFunc inOverlay, + miOverlayTransFunc trans +); + +Bool +miOverlayGetPrivateClips( + WindowPtr pWin, + RegionPtr *borderClip, + RegionPtr *clipList +); + +Bool miOverlayCollectUnderlayRegions(WindowPtr, RegionPtr*); +void miOverlayComputeCompositeClip(GCPtr, WindowPtr); +Bool miOverlayCopyUnderlay(ScreenPtr); +void miOverlaySetTransFunction(ScreenPtr, miOverlayTransFunc); +void miOverlaySetRootClip(ScreenPtr, Bool); + +#endif /* __MIOVERLAY_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipict.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipict.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipict.h (revision 51223) @@ -0,0 +1,230 @@ +/* + * $XFree86: xc/programs/Xserver/render/mipict.h,v 1.12 2002/11/05 05:34:40 keithp Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _MIPICT_H_ +#define _MIPICT_H_ + +#include "picturestr.h" + +#define MI_MAX_INDEXED 256 /* XXX depth must be <= 8 */ + +#if MI_MAX_INDEXED <= 256 +typedef CARD8 miIndexType; +#endif + +typedef struct _miIndexed { + Bool color; + CARD32 rgba[MI_MAX_INDEXED]; + miIndexType ent[32768]; +} miIndexedRec, *miIndexedPtr; + +#define miCvtR8G8B8to15(s) ((((s) >> 3) & 0x001f) | \ + (((s) >> 6) & 0x03e0) | \ + (((s) >> 9) & 0x7c00)) +#define miIndexToEnt15(mif,rgb15) ((mif)->ent[rgb15]) +#define miIndexToEnt24(mif,rgb24) miIndexToEnt15(mif,miCvtR8G8B8to15(rgb24)) + +#define miIndexToEntY24(mif,rgb24) ((mif)->ent[CvtR8G8B8toY15(rgb24)]) + +int +miCreatePicture (PicturePtr pPicture); + +void +miDestroyPicture (PicturePtr pPicture); + +void +miDestroyPictureClip (PicturePtr pPicture); + +int +miChangePictureClip (PicturePtr pPicture, + int type, + pointer value, + int n); + +void +miChangePicture (PicturePtr pPicture, + Mask mask); + +void +miValidatePicture (PicturePtr pPicture, + Mask mask); + +int +miChangePictureTransform (PicturePtr pPicture, + PictTransform *transform); + +int +miChangePictureFilter (PicturePtr pPicture, + int filter, + xFixed *params, + int nparams); + +Bool +miClipPicture (RegionPtr pRegion, + PicturePtr pPicture, + INT16 xReg, + INT16 yReg, + INT16 xPict, + INT16 yPict); + +Bool +miComputeCompositeRegion (RegionPtr pRegion, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +Bool +miPictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); + +Bool +miRealizeGlyph (ScreenPtr pScreen, + GlyphPtr glyph); + +void +miUnrealizeGlyph (ScreenPtr pScreen, + GlyphPtr glyph); + +void +miGlyphExtents (int nlist, + GlyphListPtr list, + GlyphPtr *glyphs, + BoxPtr extents); + +void +miGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +void +miRenderColorToPixel (PictFormatPtr pPict, + xRenderColor *color, + CARD32 *pixel); + +void +miRenderPixelToColor (PictFormatPtr pPict, + CARD32 pixel, + xRenderColor *color); + +Bool +miIsSolidAlpha (PicturePtr pSrc); + +void +miCompositeRects (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +void +miTrapezoidBounds (int ntrap, xTrapezoid *traps, BoxPtr box); + +void +miTrapezoids (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +void +miPointFixedBounds (int npoint, xPointFixed *points, BoxPtr bounds); + +void +miTriangleBounds (int ntri, xTriangle *tris, BoxPtr bounds); + +void +miRasterizeTriangle (PicturePtr pMask, + xTriangle *tri, + int x_off, + int y_off); + +void +miTriangles (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntri, + xTriangle *tris); + +void +miTriStrip (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +void +miTriFan (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +PicturePtr +miCreateAlphaPicture (ScreenPtr pScreen, + PicturePtr pDst, + PictFormatPtr pPictFormat, + CARD16 width, + CARD16 height); + +Bool +miInitIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat); + +void +miCloseIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat); + +void +miUpdateIndexed (ScreenPtr pScreen, + PictFormatPtr pFormat, + int ndef, + xColorItem *pdef); + +#endif /* _MIPICT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointer.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointer.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointer.h (revision 51223) @@ -0,0 +1,162 @@ +/* + * mipointer.h + * + */ + +/* $Xorg: mipointer.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mipointer.h,v 3.8 2001/08/06 20:51:19 dawes Exp $ */ + +#ifndef MIPOINTER_H +#define MIPOINTER_H + +#include "cursor.h" +#include "input.h" + +typedef struct _miPointerSpriteFuncRec { + Bool (*RealizeCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */ + ); + Bool (*UnrealizeCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */ + ); + void (*SetCursor)( + ScreenPtr /* pScr */, + CursorPtr /* pCurs */, + int /* x */, + int /* y */ + ); + void (*MoveCursor)( + ScreenPtr /* pScr */, + int /* x */, + int /* y */ + ); +} miPointerSpriteFuncRec, *miPointerSpriteFuncPtr; + +typedef struct _miPointerScreenFuncRec { + Bool (*CursorOffScreen)( + ScreenPtr* /* ppScr */, + int* /* px */, + int* /* py */ + ); + void (*CrossScreen)( + ScreenPtr /* pScr */, + int /* entering */ + ); + void (*WarpCursor)( + ScreenPtr /* pScr */, + int /* x */, + int /* y */ + ); + void (*EnqueueEvent)( + xEventPtr /* event */ + ); + void (*NewEventScreen)( + ScreenPtr /* pScr */, + Bool /* fromDIX */ + ); +} miPointerScreenFuncRec, *miPointerScreenFuncPtr; + +extern Bool miDCInitialize( + ScreenPtr /*pScreen*/, + miPointerScreenFuncPtr /*screenFuncs*/ +); + +extern Bool miPointerInitialize( + ScreenPtr /*pScreen*/, + miPointerSpriteFuncPtr /*spriteFuncs*/, + miPointerScreenFuncPtr /*screenFuncs*/, + Bool /*waitForUpdate*/ +); + +extern void miPointerWarpCursor( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/ +); + +extern int miPointerGetMotionBufferSize( + void +); + +extern int miPointerGetMotionEvents( + DeviceIntPtr /*pPtr*/, + xTimecoord * /*coords*/, + unsigned long /*start*/, + unsigned long /*stop*/, + ScreenPtr /*pScreen*/ +); + +extern void miPointerUpdate( + void +); + +extern void miPointerDeltaCursor( + int /*dx*/, + int /*dy*/, + unsigned long /*time*/ +); + +extern void miPointerAbsoluteCursor( + int /*x*/, + int /*y*/, + unsigned long /*time*/ +); + +extern void miPointerPosition( + int * /*x*/, + int * /*y*/ +); + +#undef miRegisterPointerDevice +extern void miRegisterPointerDevice( + ScreenPtr /*pScreen*/, + DevicePtr /*pDevice*/ +); + +extern void miPointerSetNewScreen( + int, /*screen_no*/ + int, /*x*/ + int /*y*/ +); +extern ScreenPtr miPointerCurrentScreen( + void +); + +#define miRegisterPointerDevice(pScreen,pDevice) \ + _miRegisterPointerDevice(pScreen,pDevice) + +extern void _miRegisterPointerDevice( + ScreenPtr /*pScreen*/, + DeviceIntPtr /*pDevice*/ +); + +extern int miPointerScreenIndex; + +#endif /* MIPOINTER_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointrst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointrst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipointrst.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * mipointrst.h + * + */ + +/* $Xorg: mipointrst.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mipointrst.h,v 1.3 2001/04/19 14:14:07 tsi Exp $ */ + +#include "mipointer.h" +#include "scrnintstr.h" + +#define MOTION_SIZE 256 + +typedef struct { + xTimecoord event; + ScreenPtr pScreen; +} miHistoryRec, *miHistoryPtr; + +typedef struct { + ScreenPtr pScreen; /* current screen */ + ScreenPtr pSpriteScreen;/* screen containing current sprite */ + CursorPtr pCursor; /* current cursor */ + CursorPtr pSpriteCursor;/* cursor on screen */ + BoxRec limits; /* current constraints */ + Bool confined; /* pointer can't change screens */ + int x, y; /* hot spot location */ + int devx, devy; /* sprite position */ + DevicePtr pPointer; /* pointer device structure */ + miHistoryRec history[MOTION_SIZE]; + int history_start, history_end; +} miPointerRec, *miPointerPtr; + +typedef struct { + miPointerSpriteFuncPtr spriteFuncs; /* sprite-specific methods */ + miPointerScreenFuncPtr screenFuncs; /* screen-specific methods */ + CloseScreenProcPtr CloseScreen; + Bool waitForUpdate; /* don't move cursor in SIGIO */ + Bool showTransparent; /* show empty cursors */ +} miPointerScreenRec, *miPointerScreenPtr; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipoly.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipoly.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mipoly.h (revision 51223) @@ -0,0 +1,218 @@ +/* $Xorg: mipoly.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/mipoly.h,v 1.2 2001/08/06 20:51:19 dawes Exp $ */ + + +/* + * fill.h + * + * Created by Brian Kelleher; Oct 1985 + * + * Include file for filled polygon routines. + * + * These are the data structures needed to scan + * convert regions. Two different scan conversion + * methods are available -- the even-odd method, and + * the winding number method. + * The even-odd rule states that a point is inside + * the polygon if a ray drawn from that point in any + * direction will pass through an odd number of + * path segments. + * By the winding number rule, a point is decided + * to be inside the polygon if a ray drawn from that + * point in any direction passes through a different + * number of clockwise and counter-clockwise path + * segments. + * + * These data structures are adapted somewhat from + * the algorithm in (Foley/Van Dam) for scan converting + * polygons. + * The basic algorithm is to start at the top (smallest y) + * of the polygon, stepping down to the bottom of + * the polygon by incrementing the y coordinate. We + * keep a list of edges which the current scanline crosses, + * sorted by x. This list is called the Active Edge Table (AET) + * As we change the y-coordinate, we update each entry in + * in the active edge table to reflect the edges new xcoord. + * This list must be sorted at each scanline in case + * two edges intersect. + * We also keep a data structure known as the Edge Table (ET), + * which keeps track of all the edges which the current + * scanline has not yet reached. The ET is basically a + * list of ScanLineList structures containing a list of + * edges which are entered at a given scanline. There is one + * ScanLineList per scanline at which an edge is entered. + * When we enter a new edge, we move it from the ET to the AET. + * + * From the AET, we can implement the even-odd rule as in + * (Foley/Van Dam). + * The winding number rule is a little trickier. We also + * keep the EdgeTableEntries in the AET linked by the + * nextWETE (winding EdgeTableEntry) link. This allows + * the edges to be linked just as before for updating + * purposes, but only uses the edges linked by the nextWETE + * link as edges representing spans of the polygon to + * drawn (as with the even-odd rule). + */ + +/* + * for the winding number rule + */ +#define CLOCKWISE 1 +#define COUNTERCLOCKWISE -1 + +typedef struct _EdgeTableEntry { + int ymax; /* ycoord at which we exit this edge. */ + BRESINFO bres; /* Bresenham info to run the edge */ + struct _EdgeTableEntry *next; /* next in the list */ + struct _EdgeTableEntry *back; /* for insertion sort */ + struct _EdgeTableEntry *nextWETE; /* for winding num rule */ + int ClockWise; /* flag for winding number rule */ +} EdgeTableEntry; + + +typedef struct _ScanLineList{ + int scanline; /* the scanline represented */ + EdgeTableEntry *edgelist; /* header node */ + struct _ScanLineList *next; /* next in the list */ +} ScanLineList; + + +typedef struct { + int ymax; /* ymax for the polygon */ + int ymin; /* ymin for the polygon */ + ScanLineList scanlines; /* header node */ +} EdgeTable; + + +/* + * Here is a struct to help with storage allocation + * so we can allocate a big chunk at a time, and then take + * pieces from this heap when we need to. + */ +#define SLLSPERBLOCK 25 + +typedef struct _ScanLineListBlock { + ScanLineList SLLs[SLLSPERBLOCK]; + struct _ScanLineListBlock *next; +} ScanLineListBlock; + +/* + * number of points to buffer before sending them off + * to scanlines() : Must be an even number + */ +#define NUMPTSTOBUFFER 200 + + + +/* + * + * a few macros for the inner loops of the fill code where + * performance considerations don't allow a procedure call. + * + * Evaluate the given edge at the given scanline. + * If the edge has expired, then we leave it and fix up + * the active edge table; otherwise, we increment the + * x value to be ready for the next scanline. + * The winding number rule is in effect, so we must notify + * the caller when the edge has been removed so he + * can reorder the Winding Active Edge Table. + */ +#define EVALUATEEDGEWINDING(pAET, pPrevAET, y, fixWAET) { \ + if (pAET->ymax == y) { /* leaving this edge */ \ + pPrevAET->next = pAET->next; \ + pAET = pPrevAET->next; \ + fixWAET = 1; \ + if (pAET) \ + pAET->back = pPrevAET; \ + } \ + else { \ + BRESINCRPGONSTRUCT(pAET->bres); \ + pPrevAET = pAET; \ + pAET = pAET->next; \ + } \ +} + + +/* + * Evaluate the given edge at the given scanline. + * If the edge has expired, then we leave it and fix up + * the active edge table; otherwise, we increment the + * x value to be ready for the next scanline. + * The even-odd rule is in effect. + */ +#define EVALUATEEDGEEVENODD(pAET, pPrevAET, y) { \ + if (pAET->ymax == y) { /* leaving this edge */ \ + pPrevAET->next = pAET->next; \ + pAET = pPrevAET->next; \ + if (pAET) \ + pAET->back = pPrevAET; \ + } \ + else { \ + BRESINCRPGONSTRUCT(pAET->bres); \ + pPrevAET = pAET; \ + pAET = pAET->next; \ + } \ +} + +/* mipolyutil.c */ + +extern Bool miInsertEdgeInET( + EdgeTable * /*ET*/, + EdgeTableEntry * /*ETE*/, + int /*scanline*/, + ScanLineListBlock ** /*SLLBlock*/, + int * /*iSLLBlock*/ +); + +extern Bool miCreateETandAET( + int /*count*/, + DDXPointPtr /*pts*/, + EdgeTable * /*ET*/, + EdgeTableEntry * /*AET*/, + EdgeTableEntry * /*pETEs*/, + ScanLineListBlock * /*pSLLBlock*/ +); + +extern void miloadAET( + EdgeTableEntry * /*AET*/, + EdgeTableEntry * /*ETEs*/ +); + +extern void micomputeWAET( + EdgeTableEntry * /*AET*/ +); + +extern int miInsertionSort( + EdgeTableEntry * /*AET*/ +); + +extern void miFreeStorage( + ScanLineListBlock * /*pSLLBlock*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misc.h (revision 51223) @@ -0,0 +1,269 @@ +/* $XFree86: xc/programs/Xserver/include/misc.h,v 3.28 2001/12/14 19:59:55 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +Copyright 1992, 1993 Data General Corporation; +Copyright 1992, 1993 OMRON Corporation + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that the +above copyright notice appear in all copies and that both that copyright +notice and this permission notice appear in supporting documentation, and that +neither the name OMRON or DATA GENERAL be used in advertising or publicity +pertaining to distribution of the software without specific, written prior +permission of the party whose name is to be used. Neither OMRON or +DATA GENERAL make any representation about the suitability of this software +for any purpose. It is provided "as is" without express or implied warranty. + +OMRON AND DATA GENERAL EACH DISCLAIM ALL WARRANTIES WITH REGARD TO THIS +SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, +IN NO EVENT SHALL OMRON OR DATA GENERAL BE LIABLE FOR ANY SPECIAL, INDIRECT +OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE +OF THIS SOFTWARE. + +******************************************************************/ +/* $Xorg: misc.h,v 1.5 2001/02/09 02:05:15 xorgcvs Exp $ */ +#ifndef MISC_H +#define MISC_H 1 +/* + * X internal definitions + * + */ + +extern unsigned long globalSerialNumber; +extern unsigned long serverGeneration; + +#include +#include +#include +#include +#include + +#ifndef IN_MODULE +#ifndef NULL +#include +#endif +#endif + +#ifndef MAXSCREENS +#define MAXSCREENS 16 +#endif +#define MAXCLIENTS 256 +#define MAXDITS 1 +#define MAXEXTENSIONS 128 +#define MAXFORMATS 8 +#define MAXVISUALS_PER_SCREEN 50 + +typedef unsigned long PIXEL; +typedef unsigned long ATOM; + + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif + +#ifndef _XTYPEDEF_CALLBACKLISTPTR +typedef struct _CallbackList *CallbackListPtr; /* also in dix.h */ +#define _XTYPEDEF_CALLBACKLISTPTR +#endif + +typedef struct _xReq *xReqPtr; + +#include "os.h" /* for ALLOCATE_LOCAL and DEALLOCATE_LOCAL */ +#ifndef IN_MODULE +#include /* for bcopy, bzero, and bcmp */ +#endif + +#define NullBox ((BoxPtr)0) +#define MILLI_PER_MIN (1000 * 60) +#define MILLI_PER_SECOND (1000) + + /* this next is used with None and ParentRelative to tell + PaintWin() what to use to paint the background. Also used + in the macro IS_VALID_PIXMAP */ + +#define USE_BACKGROUND_PIXEL 3 +#define USE_BORDER_PIXEL 3 + + +/* byte swap a 32-bit literal */ +#define lswapl(x) ((((x) & 0xff) << 24) |\ + (((x) & 0xff00) << 8) |\ + (((x) & 0xff0000) >> 8) |\ + (((x) >> 24) & 0xff)) + +/* byte swap a short literal */ +#define lswaps(x) ((((x) & 0xff) << 8) | (((x) >> 8) & 0xff)) + +#undef min +#undef max + +#define min(a, b) (((a) < (b)) ? (a) : (b)) +#define max(a, b) (((a) > (b)) ? (a) : (b)) +#ifndef IN_MODULE +/* abs() is a function, not a macro; include the file declaring + * it in case we haven't done that yet. + */ +#include +#endif /* IN_MODULE */ +#ifndef Fabs +#define Fabs(a) ((a) > 0.0 ? (a) : -(a)) /* floating absolute value */ +#endif +#define sign(x) ((x) < 0 ? -1 : ((x) > 0 ? 1 : 0)) +/* this assumes b > 0 */ +#define modulus(a, b, d) if (((d) = (a) % (b)) < 0) (d) += (b) +/* + * return the least significant bit in x which is set + * + * This works on 1's complement and 2's complement machines. + * If you care about the extra instruction on 2's complement + * machines, change to ((x) & (-(x))) + */ +#define lowbit(x) ((x) & (~(x) + 1)) + +#ifndef IN_MODULE +/* XXX Not for modules */ +#include +#if !defined(MAXSHORT) || !defined(MINSHORT) || \ + !defined(MAXINT) || !defined(MININT) +/* + * Some implementations #define these through , so preclude + * #include'ing it later. + */ + +#include +#endif +#undef MAXSHORT +#define MAXSHORT SHRT_MAX +#undef MINSHORT +#define MINSHORT SHRT_MIN +#undef MAXINT +#define MAXINT INT_MAX +#undef MININT +#define MININT INT_MIN + +#include +#include +#include /* for fopen, etc... */ + +#endif + +/* some macros to help swap requests, replies, and events */ + +#define LengthRestB(stuff) \ + ((client->req_len << 2) - sizeof(*stuff)) + +#define LengthRestS(stuff) \ + ((client->req_len << 1) - (sizeof(*stuff) >> 1)) + +#define LengthRestL(stuff) \ + (client->req_len - (sizeof(*stuff) >> 2)) + +#define SwapRestS(stuff) \ + SwapShorts((short *)(stuff + 1), LengthRestS(stuff)) + +#define SwapRestL(stuff) \ + SwapLongs((CARD32 *)(stuff + 1), LengthRestL(stuff)) + +/* byte swap a 32-bit value */ +#define swapl(x, n) { \ + n = ((char *) (x))[0];\ + ((char *) (x))[0] = ((char *) (x))[3];\ + ((char *) (x))[3] = n;\ + n = ((char *) (x))[1];\ + ((char *) (x))[1] = ((char *) (x))[2];\ + ((char *) (x))[2] = n; } + +/* byte swap a short */ +#define swaps(x, n) { \ + n = ((char *) (x))[0];\ + ((char *) (x))[0] = ((char *) (x))[1];\ + ((char *) (x))[1] = n; } + +/* copy 32-bit value from src to dst byteswapping on the way */ +#define cpswapl(src, dst) { \ + ((char *)&(dst))[0] = ((char *) &(src))[3];\ + ((char *)&(dst))[1] = ((char *) &(src))[2];\ + ((char *)&(dst))[2] = ((char *) &(src))[1];\ + ((char *)&(dst))[3] = ((char *) &(src))[0]; } + +/* copy short from src to dst byteswapping on the way */ +#define cpswaps(src, dst) { \ + ((char *) &(dst))[0] = ((char *) &(src))[1];\ + ((char *) &(dst))[1] = ((char *) &(src))[0]; } + +extern void SwapLongs( + CARD32 *list, + unsigned long count); + +extern void SwapShorts( + short *list, + unsigned long count); + +extern void MakePredeclaredAtoms(void); + +extern int Ones( + unsigned long /*mask*/); + +typedef struct _xPoint *DDXPointPtr; +typedef struct _Box *BoxPtr; +typedef struct _xEvent *xEventPtr; +typedef struct _xRectangle *xRectanglePtr; +typedef struct _GrabRec *GrabPtr; + +/* typedefs from other places - duplicated here to minimize the amount + * of unnecessary junk that one would normally have to include to get + * these symbols defined + */ + +#ifndef _XTYPEDEF_CHARINFOPTR +typedef struct _CharInfo *CharInfoPtr; /* also in fonts/include/font.h */ +#define _XTYPEDEF_CHARINFOPTR +#endif + +#endif /* MISC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscanfill.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscanfill.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscanfill.h (revision 51223) @@ -0,0 +1,151 @@ +/* $Xorg: miscanfill.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SCANFILLINCLUDED +#define SCANFILLINCLUDED +/* + * scanfill.h + * + * Written by Brian Kelleher; Jan 1985 + * + * This file contains a few macros to help track + * the edge of a filled object. The object is assumed + * to be filled in scanline order, and thus the + * algorithm used is an extension of Bresenham's line + * drawing algorithm which assumes that y is always the + * major axis. + * Since these pieces of code are the same for any filled shape, + * it is more convenient to gather the library in one + * place, but since these pieces of code are also in + * the inner loops of output primitives, procedure call + * overhead is out of the question. + * See the author for a derivation if needed. + */ + + + +/* + * In scan converting polygons, we want to choose those pixels + * which are inside the polygon. Thus, we add .5 to the starting + * x coordinate for both left and right edges. Now we choose the + * first pixel which is inside the pgon for the left edge and the + * first pixel which is outside the pgon for the right edge. + * Draw the left pixel, but not the right. + * + * How to add .5 to the starting x coordinate: + * If the edge is moving to the right, then subtract dy from the + * error term from the general form of the algorithm. + * If the edge is moving to the left, then add dy to the error term. + * + * The reason for the difference between edges moving to the left + * and edges moving to the right is simple: If an edge is moving + * to the right, then we want the algorithm to flip immediately. + * If it is moving to the left, then we don't want it to flip until + * we traverse an entire pixel. + */ +#define BRESINITPGON(dy, x1, x2, xStart, d, m, m1, incr1, incr2) { \ + int dx; /* local storage */ \ +\ + /* \ + * if the edge is horizontal, then it is ignored \ + * and assumed not to be processed. Otherwise, do this stuff. \ + */ \ + if ((dy) != 0) { \ + xStart = (x1); \ + dx = (x2) - xStart; \ + if (dx < 0) { \ + m = dx / (dy); \ + m1 = m - 1; \ + incr1 = -2 * dx + 2 * (dy) * m1; \ + incr2 = -2 * dx + 2 * (dy) * m; \ + d = 2 * m * (dy) - 2 * dx - 2 * (dy); \ + } else { \ + m = dx / (dy); \ + m1 = m + 1; \ + incr1 = 2 * dx - 2 * (dy) * m1; \ + incr2 = 2 * dx - 2 * (dy) * m; \ + d = -2 * m * (dy) + 2 * dx; \ + } \ + } \ +} + + +#define BRESINCRPGON(d, minval, m, m1, incr1, incr2) { \ + if (m1 > 0) { \ + if (d > 0) { \ + minval += m1; \ + d += incr1; \ + } \ + else { \ + minval += m; \ + d += incr2; \ + } \ + } else {\ + if (d >= 0) { \ + minval += m1; \ + d += incr1; \ + } \ + else { \ + minval += m; \ + d += incr2; \ + } \ + } \ +} + + + +/* + * This structure contains all of the information needed + * to run the bresenham algorithm. + * The variables may be hardcoded into the declarations + * instead of using this structure to make use of + * register declarations. + */ +typedef struct { + int minor; /* minor axis */ + int d; /* decision variable */ + int m, m1; /* slope and slope+1 */ + int incr1, incr2; /* error increments */ +} BRESINFO; + + +#define BRESINITPGONSTRUCT(dmaj, min1, min2, bres) \ + BRESINITPGON(dmaj, min1, min2, bres.minor, bres.d, \ + bres.m, bres.m1, bres.incr1, bres.incr2) + +#define BRESINCRPGONSTRUCT(bres) \ + BRESINCRPGON(bres.d, bres.minor, bres.m, bres.m1, bres.incr1, bres.incr2) + + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscstruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscstruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miscstruct.h (revision 51223) @@ -0,0 +1,80 @@ +/* $Xorg: miscstruct.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/miscstruct.h,v 3.4 2003/04/27 21:31:04 herrb Exp $ */ + +#ifndef MISCSTRUCT_H +#define MISCSTRUCT_H 1 + +#include "misc.h" +#include +#include "gc.h" + +typedef xPoint DDXPointRec; + +typedef struct _Box { + short x1, y1, x2, y2; +} BoxRec; + +typedef union _DevUnion { + pointer ptr; + long val; + unsigned long uval; + RegionPtr (*fptr)( + DrawablePtr /* pSrcDrawable */, + DrawablePtr /* pDstDrawable */, + GCPtr /* pGC */, + int /* srcx */, + int /* srcy */, + int /* width */, + int /* height */, + int /* dstx */, + int /* dsty */, + unsigned long /* bitPlane */); +} DevUnion; + +#endif /* MISCSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispans.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispans.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispans.h (revision 51223) @@ -0,0 +1,117 @@ +/* $XFree86: xc/programs/Xserver/mi/mispans.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ +/*********************************************************** + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1989 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: mispans.h,v 1.4 2001/02/09 02:05:21 xorgcvs Exp $ */ + +typedef struct { + int count; /* number of spans */ + DDXPointPtr points; /* pointer to list of start points */ + int *widths; /* pointer to list of widths */ +} Spans; + +typedef struct { + int size; /* Total number of *Spans allocated */ + int count; /* Number of *Spans actually in group */ + Spans *group; /* List of Spans */ + int ymin, ymax; /* Min, max y values encountered */ +} SpanGroup; + +/* Initialize SpanGroup. MUST BE DONE before use. */ +extern void miInitSpanGroup( + SpanGroup * /*spanGroup*/ +); + +/* Add a Spans to a SpanGroup. The spans MUST BE in y-sorted order */ +extern void miAppendSpans( + SpanGroup * /*spanGroup*/, + SpanGroup * /*otherGroup*/, + Spans * /*spans*/ +); + +/* Paint a span group, possibly with some overlap */ +extern void miFillSpanGroup( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + SpanGroup * /*spanGroup*/ +); + +/* Paint a span group, insuring that each pixel is painted at most once */ +extern void miFillUniqueSpanGroup( + DrawablePtr /*pDraw*/, + GCPtr /*pGC*/, + SpanGroup * /*spanGroup*/ +); + +/* Free up data in a span group. MUST BE DONE or you'll suffer memory leaks */ +extern void miFreeSpanGroup( + SpanGroup * /*spanGroup*/ +); + +extern void miSubtractSpans( + SpanGroup * /*spanGroup*/, + Spans * /*sub*/ +); + +extern void miDisposeSpanGroup( + SpanGroup * /*spanGroup*/ +); + +extern int miClipSpans( + RegionPtr /*prgnDst*/, + DDXPointPtr /*ppt*/, + int * /*pwidth*/, + int /*nspans*/, + DDXPointPtr /*pptNew*/, + int * /*pwidthNew*/, + int /*fSorted*/ +); + +/* Rops which must use span groups */ +#define miSpansCarefulRop(rop) (((rop) & 0xc) == 0x8 || ((rop) & 0x3) == 0x2) +#define miSpansEasyRop(rop) (!miSpansCarefulRop(rop)) + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misprite.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misprite.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/misprite.h (revision 51223) @@ -0,0 +1,96 @@ +/* + * misprite.h + * + * software-sprite/sprite drawing interface spec + * + * mi versions of these routines exist. + */ + +/* $Xorg: misprite.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/misprite.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ + +typedef struct { + Bool (*RealizeCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/ +); + Bool (*UnrealizeCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/ +); + Bool (*PutUpCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + int /*x*/, + int /*y*/, + unsigned long /*source*/, + unsigned long /*mask*/ +); + Bool (*SaveUnderCursor)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/ +); + Bool (*RestoreUnderCursor)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/ +); + Bool (*MoveCursor)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*dx*/, + int /*dy*/, + unsigned long /*source*/, + unsigned long /*mask*/ +); + Bool (*ChangeSave)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + int /*dx*/, + int /*dy*/ +); + +} miSpriteCursorFuncRec, *miSpriteCursorFuncPtr; + +extern Bool miSpriteInitialize( + ScreenPtr /*pScreen*/, + miSpriteCursorFuncPtr /*cursorFuncs*/, + miPointerScreenFuncPtr /*screenFuncs*/ +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispritest.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispritest.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mispritest.h (revision 51223) @@ -0,0 +1,134 @@ +/* + * mispritest.h + * + * mi sprite structures + */ + +/* $Xorg: mispritest.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/mi/mispritest.h,v 1.4 2001/01/17 22:37:07 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _MISPRITEST_H_ +#define _MISPRITEST_H_ + +# include "misprite.h" +#ifdef RENDER +# include "picturestr.h" +#endif +# include "damage.h" + +/* + * per screen information + */ + +typedef struct { + /* screen procedures */ + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + SourceValidateProcPtr SourceValidate; + + /* window procedures */ + CopyWindowProcPtr CopyWindow; + + /* backing store procedures */ + SaveDoomedAreasProcPtr SaveDoomedAreas; + + /* colormap procedures */ + InstallColormapProcPtr InstallColormap; + StoreColorsProcPtr StoreColors; + + /* os layer procedures */ + ScreenBlockHandlerProcPtr BlockHandler; + + CursorPtr pCursor; + int x; /* cursor hotspot */ + int y; + BoxRec saved; /* saved area from the screen */ + Bool isUp; /* cursor in frame buffer */ + Bool shouldBeUp; /* cursor should be displayed */ + WindowPtr pCacheWin; /* window the cursor last seen in */ + Bool isInCacheWin; + Bool checkPixels; /* check colormap collision */ + xColorItem colors[2]; + ColormapPtr pInstalledMap; + ColormapPtr pColormap; + VisualPtr pVisual; + miSpriteCursorFuncPtr funcs; + DamagePtr pDamage; /* damage tracking structure */ +} miSpriteScreenRec, *miSpriteScreenPtr; + +#define SOURCE_COLOR 0 +#define MASK_COLOR 1 + +#define miSpriteIsUpTRUE(pScreen, pScreenPriv) if (!pScreenPriv->isUp) { \ + pScreenPriv->isUp = TRUE; \ + DamageRegister (&(*pScreen->GetScreenPixmap) (pScreen)->drawable, pScreenPriv->pDamage); \ +} + +#define miSpriteIsUpFALSE(pScreen, pScreenPriv) if (pScreenPriv->isUp) { \ + DamageUnregister (&(*pScreen->GetScreenPixmap) (pScreen)->drawable, pScreenPriv->pDamage); \ + pScreenPriv->isUp = FALSE; \ +} + +/* + * Overlap BoxPtr and Box elements + */ +#define BOX_OVERLAP(pCbox,X1,Y1,X2,Y2) \ + (((pCbox)->x1 <= (X2)) && ((X1) <= (pCbox)->x2) && \ + ((pCbox)->y1 <= (Y2)) && ((Y1) <= (pCbox)->y2)) + +/* + * Overlap BoxPtr, origins, and rectangle + */ +#define ORG_OVERLAP(pCbox,xorg,yorg,x,y,w,h) \ + BOX_OVERLAP((pCbox),(x)+(xorg),(y)+(yorg),(x)+(xorg)+(w),(y)+(yorg)+(h)) + +/* + * Overlap BoxPtr, origins and RectPtr + */ +#define ORGRECT_OVERLAP(pCbox,xorg,yorg,pRect) \ + ORG_OVERLAP((pCbox),(xorg),(yorg),(pRect)->x,(pRect)->y, \ + (int)((pRect)->width), (int)((pRect)->height)) +/* + * Overlap BoxPtr and horizontal span + */ +#define SPN_OVERLAP(pCbox,y,x,w) BOX_OVERLAP((pCbox),(x),(y),(x)+(w),(y)) + +#define LINE_SORT(x1,y1,x2,y2) \ +{ int _t; \ + if (x1 > x2) { _t = x1; x1 = x2; x2 = _t; } \ + if (y1 > y2) { _t = y1; y1 = y2; y2 = _t; } } + +#define LINE_OVERLAP(pCbox,x1,y1,x2,y2,lw2) \ + BOX_OVERLAP((pCbox), (x1)-(lw2), (y1)-(lw2), (x2)+(lw2), (y2)+(lw2)) + +#endif /* _MISPRITEST_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mistruct.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mistruct.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mistruct.h (revision 51223) @@ -0,0 +1,65 @@ +/* $Xorg: mistruct.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef MISTRUCT_H +#define MISTRUCT_H + +#include "mi.h" +#include "regionstr.h" + +/* information about dashes */ +typedef struct _miDash { + DDXPointRec pt; + int e1, e2; /* keep these, so we don't have to do it again */ + int e; /* bresenham error term for this point on line */ + int which; + int newLine;/* 0 if part of same original line as previous dash */ + } miDashRec; + +#endif /* MISTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mivalidate.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mivalidate.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mivalidate.h (revision 51223) @@ -0,0 +1,55 @@ +/* $Xorg: mivalidate.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/* + +Copyright 1993, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86$ */ + + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef MIVALIDATE_H +#define MIVALIDATE_H + +#include "regionstr.h" + +typedef union _Validate { + struct BeforeValidate { + DDXPointRec oldAbsCorner; /* old window position */ + RegionPtr borderVisible; /* visible region of border, */ + /* non-null when size changes */ + Bool resized; /* unclipped winSize has changed - */ + /* don't call SaveDoomedAreas */ + } before; + struct AfterValidate { + RegionRec exposed; /* exposed regions, absolute pos */ + RegionRec borderExposed; + } after; +} ValidateRec; + +#endif /* MIVALIDATE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miwideline.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miwideline.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/miwideline.h (revision 51223) @@ -0,0 +1,224 @@ +/* $Xorg: miwideline.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ +/* + +Copyright 1988, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/mi/miwideline.h,v 1.11 2001/10/25 12:03:47 alanh Exp $ */ + +/* Author: Keith Packard, MIT X Consortium */ + +#include "mispans.h" +#include "mifpoly.h" /* for ICEIL */ + +/* + * interface data to span-merging polygon filler + */ + +typedef struct _SpanData { + SpanGroup fgGroup, bgGroup; +} SpanDataRec, *SpanDataPtr; + +#define AppendSpanGroup(pGC, pixel, spanPtr, spanData) { \ + SpanGroup *group, *othergroup = NULL; \ + if (pixel == pGC->fgPixel) \ + { \ + group = &spanData->fgGroup; \ + if (pGC->lineStyle == LineDoubleDash) \ + othergroup = &spanData->bgGroup; \ + } \ + else \ + { \ + group = &spanData->bgGroup; \ + othergroup = &spanData->fgGroup; \ + } \ + miAppendSpans (group, othergroup, spanPtr); \ +} + +/* + * Polygon edge description for integer wide-line routines + */ + +typedef struct _PolyEdge { + int height; /* number of scanlines to process */ + int x; /* starting x coordinate */ + int stepx; /* fixed integral dx */ + int signdx; /* variable dx sign */ + int e; /* initial error term */ + int dy; + int dx; +} PolyEdgeRec, *PolyEdgePtr; + +#define SQSECANT 108.856472512142 /* 1/sin^2(11/2) - miter limit constant */ + +/* + * types for general polygon routines + */ + +typedef struct _PolyVertex { + double x, y; +} PolyVertexRec, *PolyVertexPtr; + +typedef struct _PolySlope { + int dx, dy; + double k; /* x0 * dy - y0 * dx */ +} PolySlopeRec, *PolySlopePtr; + +/* + * Line face description for caps/joins + */ + +typedef struct _LineFace { + double xa, ya; + int dx, dy; + int x, y; + double k; +} LineFaceRec, *LineFacePtr; + +/* + * macros for polygon fillers + */ + +#define MIPOLYRELOADLEFT if (!left_height && left_count) { \ + left_height = left->height; \ + left_x = left->x; \ + left_stepx = left->stepx; \ + left_signdx = left->signdx; \ + left_e = left->e; \ + left_dy = left->dy; \ + left_dx = left->dx; \ + --left_count; \ + ++left; \ + } + +#define MIPOLYRELOADRIGHT if (!right_height && right_count) { \ + right_height = right->height; \ + right_x = right->x; \ + right_stepx = right->stepx; \ + right_signdx = right->signdx; \ + right_e = right->e; \ + right_dy = right->dy; \ + right_dx = right->dx; \ + --right_count; \ + ++right; \ + } + +#define MIPOLYSTEPLEFT left_x += left_stepx; \ + left_e += left_dx; \ + if (left_e > 0) \ + { \ + left_x += left_signdx; \ + left_e -= left_dy; \ + } + +#define MIPOLYSTEPRIGHT right_x += right_stepx; \ + right_e += right_dx; \ + if (right_e > 0) \ + { \ + right_x += right_signdx; \ + right_e -= right_dy; \ + } + +#define MILINESETPIXEL(pDrawable, pGC, pixel, oldPixel) { \ + oldPixel = pGC->fgPixel; \ + if (pixel != oldPixel) { \ + DoChangeGC (pGC, GCForeground, (XID *) &pixel, FALSE); \ + ValidateGC (pDrawable, pGC); \ + } \ +} +#define MILINERESETPIXEL(pDrawable, pGC, pixel, oldPixel) { \ + if (pixel != oldPixel) { \ + DoChangeGC (pGC, GCForeground, (XID *) &oldPixel, FALSE); \ + ValidateGC (pDrawable, pGC); \ + } \ +} + +extern void miFillPolyHelper( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + unsigned long /*pixel*/, + SpanDataPtr /*spanData*/, + int /*y*/, + int /*overall_height*/, + PolyEdgePtr /*left*/, + PolyEdgePtr /*right*/, + int /*left_count*/, + int /*right_count*/ +); +extern int miRoundJoinFace( + LineFacePtr /*face*/, + PolyEdgePtr /*edge*/, + Bool * /*leftEdge*/ +); + +extern void miRoundJoinClip( + LineFacePtr /*pLeft*/, + LineFacePtr /*pRight*/, + PolyEdgePtr /*edge1*/, + PolyEdgePtr /*edge2*/, + int * /*y1*/, + int * /*y2*/, + Bool * /*left1*/, + Bool * /*left2*/ +); + +extern int miRoundCapClip( + LineFacePtr /*face*/, + Bool /*isInt*/, + PolyEdgePtr /*edge*/, + Bool * /*leftEdge*/ +); + +extern void miLineProjectingCap( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + unsigned long /*pixel*/, + SpanDataPtr /*spanData*/, + LineFacePtr /*face*/, + Bool /*isLeft*/, + double /*xorg*/, + double /*yorg*/, + Bool /*isInt*/ +); + +extern SpanDataPtr miSetupSpanData( + GCPtr /*pGC*/, + SpanDataPtr /*spanData*/, + int /*npt*/ +); + +extern void miCleanupSpanData( + DrawablePtr /*pDrawable*/, + GCPtr /*pGC*/, + SpanDataPtr /*spanData*/ +); + +extern int miPolyBuildEdge(double x0, double y0, double k, int dx, int dy, + int xi, int yi, int left, PolyEdgePtr edge); +extern int miPolyBuildPoly(PolyVertexPtr vertices, PolySlopePtr slopes, + int count, int xi, int yi, PolyEdgePtr left, + PolyEdgePtr right, int *pnleft, int *pnright, + int *h); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mizerarc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mizerarc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mizerarc.h (revision 51223) @@ -0,0 +1,134 @@ +/* $XFree86: xc/programs/Xserver/mi/mizerarc.h,v 1.2 2001/08/06 20:51:20 dawes Exp $ */ +/************************************************************ + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +********************************************************/ + +/* $Xorg: mizerarc.h,v 1.4 2001/02/09 02:05:22 xorgcvs Exp $ */ + +typedef struct { + int x; + int y; + int mask; +} miZeroArcPtRec; + +typedef struct { + int x, y, k1, k3, a, b, d, dx, dy; + int alpha, beta; + int xorg, yorg; + int xorgo, yorgo; + int w, h; + int initialMask; + miZeroArcPtRec start, altstart, end, altend; + int firstx, firsty; + int startAngle, endAngle; +} miZeroArcRec; + +#define miCanZeroArc(arc) (((arc)->width == (arc)->height) || \ + (((arc)->width <= 800) && ((arc)->height <= 800))) + +#define MIARCSETUP() \ + x = info.x; \ + y = info.y; \ + k1 = info.k1; \ + k3 = info.k3; \ + a = info.a; \ + b = info.b; \ + d = info.d; \ + dx = info.dx; \ + dy = info.dy + +#define MIARCOCTANTSHIFT(clause) \ + if (a < 0) \ + { \ + if (y == info.h) \ + { \ + d = -1; \ + a = b = k1 = 0; \ + } \ + else \ + { \ + dx = (k1 << 1) - k3; \ + k1 = dx - k1; \ + k3 = -k3; \ + b = b + a - (k1 >> 1); \ + d = b + ((-a) >> 1) - d + (k3 >> 3); \ + if (dx < 0) \ + a = -((-dx) >> 1) - a; \ + else \ + a = (dx >> 1) - a; \ + dx = 0; \ + dy = 1; \ + clause \ + } \ + } + +#define MIARCSTEP(move1,move2) \ + b -= k1; \ + if (d < 0) \ + { \ + x += dx; \ + y += dy; \ + a += k1; \ + d += b; \ + move1 \ + } \ + else \ + { \ + x++; \ + y++; \ + a += k3; \ + d -= a; \ + move2 \ + } + +#define MIARCCIRCLESTEP(clause) \ + b -= k1; \ + x++; \ + if (d < 0) \ + { \ + a += k1; \ + d += b; \ + } \ + else \ + { \ + y++; \ + a += k3; \ + d -= a; \ + clause \ + } + +/* mizerarc.c */ + +extern Bool miZeroArcSetup( + xArc * /*arc*/, + miZeroArcRec * /*info*/, + Bool /*ok360*/ +); + +extern DDXPointPtr miZeroArcPts( + xArc * /*arc*/, + DDXPointPtr /*pts*/ +); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/modinit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/modinit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/modinit.h (revision 51223) @@ -0,0 +1,149 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/dixmods/extmod/modinit.h,v 1.5 2005/07/03 07:01:06 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/Xext/extmod/modinit.h,v 1.1 2003/07/16 01:38:33 dawes Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef INITARGS +#define INITARGS void +#endif + +#ifdef SHAPE +extern void ShapeExtensionInit(INITARGS); +#define _SHAPE_SERVER_ /* don't want Xlib structures */ +#include +#endif + +#ifdef MULTIBUFFER +extern void MultibufferExtensionInit(INITARGS); +#define _MULTIBUF_SERVER_ /* don't want Xlib structures */ +#include +#endif + +#ifdef MITMISC +extern void MITMiscExtensionInit(INITARGS); +#define _MITMISC_SERVER_ +#include +#endif + +#ifdef XTEST +extern void XTestExtensionInit(INITARGS); +#define _XTEST_SERVER_ +#include +#include +#endif + +#if 1 +extern void XTestExtension1Init(INITARGS); +#endif + +#ifdef BIGREQS +extern void BigReqExtensionInit(INITARGS); +#include +#endif + +#ifdef XSYNC +extern void SyncExtensionInit(INITARGS); +#define _SYNC_SERVER +#include +#include +#endif + +#ifdef SCREENSAVER +extern void ScreenSaverExtensionInit (INITARGS); +#include +#endif + +#ifdef XCMISC +extern void XCMiscExtensionInit(INITARGS); +#include +#endif + +#ifdef XF86VIDMODE +extern void XFree86VidModeExtensionInit(INITARGS); +#define _XF86VIDMODE_SERVER_ +#include +#endif + +#ifdef XF86MISC +extern void XFree86MiscExtensionInit(INITARGS); +#define _XF86MISC_SERVER_ +#define _XF86MISC_SAVER_COMPAT_ +#include +#endif + +#ifdef XFreeXDGA +extern void XFree86DGAExtensionInit(INITARGS); +extern void XFree86DGARegister(INITARGS); +#define _XF86DGA_SERVER_ +#include +#endif + +#ifdef DPMSExtension +extern void DPMSExtensionInit(INITARGS); +#include +#endif + +#ifdef FONTCACHE +extern void FontCacheExtensionInit(INITARGS); +#define _FONTCACHE_SERVER_ +#include "fontcacheP.h" +#include "fontcachstr.h" +#endif + +#ifdef TOGCUP +extern void XcupExtensionInit(INITARGS); +#define _XCUP_SERVER_ +#include +#endif + +#ifdef EVI +extern void EVIExtensionInit(INITARGS); +#define _XEVI_SERVER_ +#include +#endif + +#ifdef XV +extern void XvExtensionInit(INITARGS); +extern void XvMCExtensionInit(INITARGS); +extern void XvRegister(INITARGS); +#include +#include +#endif + +#ifdef RES +extern void ResExtensionInit(INITARGS); +#include +#endif + +#ifdef SHM +extern void ShmExtensionInit(INITARGS); +#include +extern void ShmSetPixmapFormat( + ScreenPtr pScreen, + int format); +extern void ShmRegisterFuncs( + ScreenPtr pScreen, + ShmFuncsPtr funcs); +#endif + +#if 1 +extern void SecurityExtensionInit(INITARGS); +#endif + +#if 1 +extern void XagExtensionInit(INITARGS); +#endif + +#if 1 +extern void XpExtensionInit(INITARGS); +#endif + +#if 1 +extern void PanoramiXExtensionInit(int argc, char *argv[]); +#endif + +#if 1 +extern void XkbExtensionInit(INITARGS); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/monitor-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/monitor-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/monitor-cfg.h (revision 51223) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/monitor-cfg.h,v 1.1 2000/04/04 22:37:00 dawes Exp $ + */ + +#include "config.h" + +#ifndef _xf86cfg_monitor_h +#define _xf86cfg_monitor_h + +/* + * Prototypes + */ +XtPointer MonitorConfig(XtPointer); +void MonitorLayout(XF86SetupInfo*); +void MonitorVidtune(XF86SetupInfo*); +int string_to_parser_range(char*, parser_range*, int); +#define PARSER_RANGE_SIZE 256 +/* string must have at least 256 bytes */ +int parser_range_to_string(char*, parser_range*, int); + +#endif /* _xf86cfg_monitor_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mouse-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mouse-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/mouse-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86$ + */ + +#include "config.h" + +#ifndef _xf86cfg_mouse_h +#define _xf86cfg_mouse_h + +/* + * Prototypes + */ +XtPointer MouseConfig(XtPointer); +void MouseDeviceAndProtocol(XF86SetupInfo*); + +#endif /* _xf86cfg_mouse_h */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/msp3430.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/msp3430.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/msp3430.h (revision 51223) @@ -0,0 +1,126 @@ +#ifndef __MSP3430_H__ +#define __MSP3430_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int standard; + int connector; + int mode; + + CARD8 hardware_version, major_revision, product_code, rom_version; +#ifdef MSP_DEBUG + CARD8 registers_present[256]; +#endif + + CARD16 chip_id; + CARD8 chip_family; + Bool recheck; /*reinitialization needed after channel change */ + CARD8 c_format; /*current state of audio format */ + CARD16 c_standard; /*current state of standard register */ + CARD8 c_source; /*current state of source register */ + CARD8 c_matrix; /*current state of matrix register */ + CARD8 c_fmmatrix; /*current state of fmmatrix register */ + int c_mode; /* current state of mode for autoswitchimg */ + CARD8 volume; + } MSP3430Rec, * MSP3430Ptr; + + +#define MSP3430_ADDR_1 0x80 +#define MSP3430_ADDR_2 0x84 +#define MSP3430_ADDR_3 0x88 + +#define MSP3430_PAL 1 +#define MSP3430_NTSC 2 +#define MSP3430_PAL_DK1 (0x100 | MSP3430_PAL) +#define MSP3430_SECAM 3 + +#define MSP3430_CONNECTOR_1 1 /* tuner on AIW cards */ +#define MSP3430_CONNECTOR_2 2 /* SVideo on AIW cards */ +#define MSP3430_CONNECTOR_3 3 /* composite on AIW cards */ + +#define MSP3430_ADDR(a) ((a)->d.SlaveAddr) + +#define MSP3430_FAST_MUTE 0xFF +/* a handy volume transform function, -1000..1000 -> 0x01..0x7F */ +#define MSP3430_VOLUME(value) (0x01+(0x7F-0x01)*log(value+1001)/log(2001)) + +/*----------------------------------------------------------*/ + +/* MSP chip families */ +#define MSPFAMILY_UNKNOWN 0 +#define MSPFAMILY_34x0D 1 +#define MSPFAMILY_34x5D 2 +#define MSPFAMILY_34x0G 3 +#define MSPFAMILY_34x5G 4 + +/* values for MSP standard */ +#define MSPSTANDARD_UNKNOWN 0x00 +#define MSPSTANDARD_AUTO 0x01 +#define MSPSTANDARD_FM_M 0x02 +#define MSPSTANDARD_FM_BG 0x03 +#define MSPSTANDARD_FM_DK1 0x04 +#define MSPSTANDARD_FM_DK2 0x04 +#define MSPSTANDARD_NICAM_BG 0x08 +#define MSPSTANDARD_NICAM_L 0x09 +#define MSPSTANDARD_NICAM_I 0x0A +#define MSPSTANDARD_NICAM_DK 0x0B + +/* values for MSP format */ +#define MSPFORMAT_UNKNOWN 0x00 +#define MSPFORMAT_FM 0x10 +#define MSPFORMAT_1xFM 0x00|MSPFORMAT_FM +#define MSPFORMAT_2xFM 0x01|MSPFORMAT_FM +#define MSPFORMAT_NICAM 0x20 +#define MSPFORMAT_NICAM_FM 0x00|MSPFORMAT_NICAM +#define MSPFORMAT_NICAM_AM 0x01|MSPFORMAT_NICAM +#define MSPFORMAT_SCART 0x30 + +/* values for MSP mode */ +#define MSPMODE_UNKNOWN 0 +/* automatic modes */ +#define MSPMODE_STEREO_AB 1 +#define MSPMODE_STEREO_A 2 +#define MSPMODE_STEREO_B 3 +/* forced modes */ +#define MSPMODE_MONO 4 +#define MSPMODE_STEREO 5 +#define MSPMODE_AB 6 +#define MSPMODE_A 7 +#define MSPMODE_B 8 +/*----------------------------------------------------------*/ + +void InitMSP3430(MSP3430Ptr m); +MSP3430Ptr DetectMSP3430(I2CBusPtr b, I2CSlaveAddr addr); +void ResetMSP3430(MSP3430Ptr m); +void MSP3430SetVolume (MSP3430Ptr m, CARD8 value); +void MSP3430SetSAP (MSP3430Ptr m, int mode); + +#define MSP3430SymbolsList \ + "InitMSP3430", \ + "DetectMSP3430", \ + "ResetMSP3430", \ + "MSP3430SetVolume", \ + "MSP3430SetSAP" + +#ifdef XFree86LOADER + +#define xf86_DetectMSP3430 ((MSP3430Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("DetectMSP3430")) +#define xf86_ResetMSP3430 ((void (*)(MSP3430Ptr))LoaderSymbol("ResetMSP3430")) +#define xf86_MSP3430SetVolume ((void (*)(MSP3430Ptr, CARD8))LoaderSymbol("MSP3430SetVolume")) +#define xf86_MSP3430SetSAP ((void (*)(MSP3430Ptr, int))LoaderSymbol("MSP3430SetSAP")) +#define xf86_InitMSP3430 ((void (*)(MSP3430Ptr))LoaderSymbol("InitMSP3430")) + +#else + +#define xf86_DetectMSP3430 DetectMSP3430 +#define xf86_ResetMSP3430 ResetMSP3430 +#define xf86_MSP3430SetVolume MSP3430SetVolume +#define xf86_MSP3430SetSAP MSP3430SetSAP +#define xf86_InitMSP3430 InitMSP3430 + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opaque.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opaque.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opaque.h (revision 51223) @@ -0,0 +1,83 @@ +/* $Xorg: opaque.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/* + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86: xc/programs/Xserver/include/opaque.h,v 1.13 2003/07/24 13:50:25 eich Exp $ */ + +#ifndef OPAQUE_H +#define OPAQUE_H + +#include + +#include "globals.h" + +extern char *defaultTextFont; +extern char *defaultCursorFont; +extern int MaxClients; +extern volatile char isItTimeToYield; +extern volatile char dispatchException; + +/* bit values for dispatchException */ +#define DE_RESET 1 +#define DE_TERMINATE 2 +#define DE_PRIORITYCHANGE 4 /* set when a client's priority changes */ + +extern CARD32 TimeOutValue; +extern int ScreenSaverBlanking; +extern int ScreenSaverAllowExposures; +extern int defaultScreenSaverBlanking; +extern int defaultScreenSaverAllowExposures; +extern int argcGlobal; +extern char **argvGlobal; +extern char *display; + +extern int defaultBackingStore; +extern Bool disableBackingStore; +extern Bool enableBackingStore; +extern Bool disableSaveUnders; +extern Bool PartialNetwork; +#ifndef NOLOGOHACK +extern int logoScreenSaver; +#endif +#ifdef RLIMIT_DATA +extern int limitDataSpace; +#endif +#ifdef RLIMIT_STACK +extern int limitStackSpace; +#endif +#ifdef RLIMIT_NOFILE +extern int limitNoFile; +#endif +extern Bool permitOldBugs; +extern Bool defeatAccessControl; +extern long maxBigRequestSize; +extern Bool blackRoot; + +extern Bool CoreDump; + + +#endif /* OPAQUE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opendev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opendev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/opendev.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef OPENDEV_H +#define OPENDEV_H 1 + +int SProcXOpenDevice(ClientPtr /* client */ + ); + +int ProcXOpenDevice(ClientPtr /* client */ + ); + +void SRepXOpenDevice(ClientPtr /* client */ , + int /* size */ , + xOpenDeviceReply * /* rep */ + ); + +#endif /* OPENDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ops.h (revision 51223) @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/options.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/options.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/options.h (revision 51223) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/options.h,v 1.6 2001/06/01 18:43:50 tsi Exp $ + */ + +#include "config.h" +#ifdef USE_MODULES +#include "loader.h" +#endif + +/* + * Prototypes + */ +#ifdef USE_MODULES +void OptionsPopup(XF86OptionPtr*, char*, OptionInfoPtr); +void ModuleOptionsPopup(Widget, XtPointer, XtPointer); +#else +void OptionsPopup(XF86OptionPtr*); +#endif +void OptionsCancelAction(Widget, XEvent*, String*, Cardinal*); +void ModuleOptionsCancelAction(Widget, XEvent*, String*, Cardinal*); +char *GetOptionDescription(char *module, char *option); +Bool InitializeOptionsDatabase(void); + +void CreateOptionsShell(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/os.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/os.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/os.h (revision 51223) @@ -0,0 +1,537 @@ +/* $XFree86: xc/programs/Xserver/include/os.h,v 3.54 2003/10/30 21:21:06 herrb Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +/* $Xorg: os.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef OS_H +#define OS_H + +#include "misc.h" +#define ALLOCATE_LOCAL_FALLBACK(_size) Xalloc((unsigned long)(_size)) +#define DEALLOCATE_LOCAL_FALLBACK(_ptr) Xfree((pointer)(_ptr)) +#include +#include + +#define NullFID ((FID) 0) + +#define SCREEN_SAVER_ON 0 +#define SCREEN_SAVER_OFF 1 +#define SCREEN_SAVER_FORCER 2 +#define SCREEN_SAVER_CYCLE 3 + +#ifndef MAX_REQUEST_SIZE +#define MAX_REQUEST_SIZE 65535 +#endif +#ifndef MAX_BIG_REQUEST_SIZE +#define MAX_BIG_REQUEST_SIZE 4194303 +#endif + +typedef pointer FID; +typedef struct _FontPathRec *FontPathPtr; +typedef struct _NewClientRec *NewClientPtr; + +#ifndef xalloc +#define xnfalloc(size) XNFalloc((unsigned long)(size)) +#define xnfcalloc(_num, _size) XNFcalloc((unsigned long)(_num)*(unsigned long)(_size)) +#define xnfrealloc(ptr, size) XNFrealloc((pointer)(ptr), (unsigned long)(size)) + +#define xalloc(size) Xalloc((unsigned long)(size)) +#define xcalloc(_num, _size) Xcalloc((unsigned long)(_num)*(unsigned long)(_size)) +#define xrealloc(ptr, size) Xrealloc((pointer)(ptr), (unsigned long)(size)) +#define xfree(ptr) Xfree((pointer)(ptr)) +#define xstrdup(s) Xstrdup(s) +#define xnfstrdup(s) XNFstrdup(s) +#endif + +#ifndef IN_MODULE +#ifdef __SCO__ +#include +#endif +#include +#endif + +/* have to put $(SIGNAL_DEFINES) in DEFINES in Imakefile to get this right */ +#ifdef SIGNALRETURNSINT +#define SIGVAL int +#else +#define SIGVAL void +#endif + +extern Bool OsDelayInitColors; +extern void (*OsVendorVErrorFProc)(const char *, va_list args); + +extern int WaitForSomething( + int* /*pClientsReady*/ +); + +#ifdef LBX +#define ReadRequestFromClient(client) ((client)->readRequest(client)) +extern int StandardReadRequestFromClient(ClientPtr /*client*/); + +extern int ClientConnectionNumber(ClientPtr /*client*/); +#else +extern int ReadRequestFromClient(ClientPtr /*client*/); +#endif /* LBX */ + +extern Bool InsertFakeRequest( + ClientPtr /*client*/, + char* /*data*/, + int /*count*/); + +extern void ResetCurrentRequest(ClientPtr /*client*/); + +extern void FlushAllOutput(void); + +extern void FlushIfCriticalOutputPending(void); + +extern void SetCriticalOutputPending(void); + +extern int WriteToClient(ClientPtr /*who*/, int /*count*/, char* /*buf*/); + +extern void ResetOsBuffers(void); + +extern void InitConnectionLimits(void); + +extern void CreateWellKnownSockets(void); + +extern void ResetWellKnownSockets(void); + +extern void CloseWellKnownConnections(void); + +extern XID AuthorizationIDOfClient(ClientPtr /*client*/); + +extern char *ClientAuthorized( + ClientPtr /*client*/, + unsigned int /*proto_n*/, + char* /*auth_proto*/, + unsigned int /*string_n*/, + char* /*auth_string*/); + +extern Bool EstablishNewConnections( + ClientPtr /*clientUnused*/, + pointer /*closure*/); + +extern void CheckConnections(void); + +extern void CloseDownConnection(ClientPtr /*client*/); + +extern void AddEnabledDevice(int /*fd*/); + +extern void RemoveEnabledDevice(int /*fd*/); + +extern void OnlyListenToOneClient(ClientPtr /*client*/); + +extern void ListenToAllClients(void); + +extern void IgnoreClient(ClientPtr /*client*/); + +extern void AttendClient(ClientPtr /*client*/); + +extern void MakeClientGrabImpervious(ClientPtr /*client*/); + +extern void MakeClientGrabPervious(ClientPtr /*client*/); + +#ifdef LBX +extern void CloseDownFileDescriptor(ClientPtr /* client */); +#endif + +extern void AvailableClientInput(ClientPtr /* client */); + +extern CARD32 GetTimeInMillis(void); + +extern void AdjustWaitForDelay( + pointer /*waitTime*/, + unsigned long /*newdelay*/); + +typedef struct _OsTimerRec *OsTimerPtr; + +typedef CARD32 (*OsTimerCallback)( + OsTimerPtr /* timer */, + CARD32 /* time */, + pointer /* arg */); + +extern void TimerInit(void); + +extern Bool TimerForce(OsTimerPtr /* timer */); + +#define TimerAbsolute (1<<0) +#define TimerForceOld (1<<1) + +extern OsTimerPtr TimerSet( + OsTimerPtr /* timer */, + int /* flags */, + CARD32 /* millis */, + OsTimerCallback /* func */, + pointer /* arg */); + +extern void TimerCheck(void); +extern void TimerCancel(OsTimerPtr /* pTimer */); +extern void TimerFree(OsTimerPtr /* pTimer */); + +extern void SetScreenSaverTimer(void); +extern void FreeScreenSaverTimer(void); + +extern SIGVAL AutoResetServer(int /*sig*/); + +extern SIGVAL GiveUp(int /*sig*/); + +extern void UseMsg(void); + +extern void InitGlobals(void); + +extern void ProcessCommandLine(int /*argc*/, char* /*argv*/[]); + +extern int set_font_authorizations( + char ** /* authorizations */, + int * /*authlen */, + pointer /* client */); + +#ifndef _HAVE_XALLOC_DECLS +#define _HAVE_XALLOC_DECLS +extern pointer Xalloc(unsigned long /*amount*/); +extern pointer Xcalloc(unsigned long /*amount*/); +extern pointer Xrealloc(pointer /*ptr*/, unsigned long /*amount*/); +extern void Xfree(pointer /*ptr*/); +#endif + +extern pointer XNFalloc(unsigned long /*amount*/); +extern pointer XNFcalloc(unsigned long /*amount*/); +extern pointer XNFrealloc(pointer /*ptr*/, unsigned long /*amount*/); + +extern void OsInitAllocator(void); + +extern char *Xstrdup(const char *s); +extern char *XNFstrdup(const char *s); +extern char *Xprintf(const char *fmt, ...); +extern char *Xvprintf(const char *fmt, va_list va); +extern char *XNFprintf(const char *fmt, ...); +extern char *XNFvprintf(const char *fmt, va_list va); + +typedef SIGVAL (*OsSigHandlerPtr)(int /* sig */); + +extern OsSigHandlerPtr OsSignal(int /* sig */, OsSigHandlerPtr /* handler */); + +extern int auditTrailLevel; + +#ifdef SERVER_LOCK +extern void LockServer(void); +extern void UnlockServer(void); +#endif + +extern int OsLookupColor( + int /*screen*/, + char * /*name*/, + unsigned /*len*/, + unsigned short * /*pred*/, + unsigned short * /*pgreen*/, + unsigned short * /*pblue*/); + +extern void OsInit(void); + +extern void OsCleanup(Bool); + +extern void OsVendorFatalError(void); + +extern void OsVendorInit(void); + +extern int OsInitColors(void); + +void OsBlockSignals (void); + +void OsReleaseSignals (void); + +#if !defined(WIN32) && !defined(__UNIXOS2__) +extern int System(char *); +extern pointer Popen(char *, char *); +extern int Pclose(pointer); +extern pointer Fopen(char *, char *); +extern int Fclose(pointer); +#else +#define System(a) system(a) +#define Popen(a,b) popen(a,b) +#define Pclose(a) pclose(a) +#define Fopen(a,b) fopen(a,b) +#define Fclose(a) fclose(a) +#endif + +extern void CheckUserParameters(int argc, char **argv, char **envp); +extern void CheckUserAuthorization(void); + +extern int AddHost( + ClientPtr /*client*/, + int /*family*/, + unsigned /*length*/, + pointer /*pAddr*/); + +extern Bool ForEachHostInFamily ( + int /*family*/, + Bool (* /*func*/ )( + unsigned char * /* addr */, + short /* len */, + pointer /* closure */), + pointer /*closure*/); + +extern int RemoveHost( + ClientPtr /*client*/, + int /*family*/, + unsigned /*length*/, + pointer /*pAddr*/); + +extern int GetHosts( + pointer * /*data*/, + int * /*pnHosts*/, + int * /*pLen*/, + BOOL * /*pEnabled*/); + +typedef struct sockaddr * sockaddrPtr; + +extern int InvalidHost(sockaddrPtr /*saddr*/, int /*len*/, ClientPtr client); + +extern int LocalClient(ClientPtr /* client */); + +extern int LocalClientCred(ClientPtr, int *, int *); + +extern int ChangeAccessControl(ClientPtr /*client*/, int /*fEnabled*/); + +extern int GetAccessControl(void); + + +extern void AddLocalHosts(void); + +extern void ResetHosts(char *display); + +extern void EnableLocalHost(void); + +extern void DisableLocalHost(void); + +extern void AccessUsingXdmcp(void); + +extern void DefineSelf(int /*fd*/); + +extern void AugmentSelf(pointer /*from*/, int /*len*/); + +extern void InitAuthorization(char * /*filename*/); + +/* extern int LoadAuthorization(void); */ + +extern void RegisterAuthorizations(void); + +extern XID AuthorizationToID ( + unsigned short name_length, + char *name, + unsigned short data_length, + char *data); + +extern int AuthorizationFromID ( + XID id, + unsigned short *name_lenp, + char **namep, + unsigned short *data_lenp, + char **datap); + +extern XID CheckAuthorization( + unsigned int /*namelength*/, + char * /*name*/, + unsigned int /*datalength*/, + char * /*data*/, + ClientPtr /*client*/, + char ** /*reason*/ +); + +extern void ResetAuthorization(void); + +extern int RemoveAuthorization ( + unsigned short name_length, + char *name, + unsigned short data_length, + char *data); + +extern int AddAuthorization( + unsigned int /*name_length*/, + char * /*name*/, + unsigned int /*data_length*/, + char * /*data*/); + +extern XID GenerateAuthorization( + unsigned int /* name_length */, + char * /* name */, + unsigned int /* data_length */, + char * /* data */, + unsigned int * /* data_length_return */, + char ** /* data_return */); + +#ifdef COMMANDLINE_CHALLENGED_OPERATING_SYSTEMS +extern void ExpandCommandLine(int * /*pargc*/, char *** /*pargv*/); +#endif + +extern void ddxInitGlobals(void); + +extern int ddxProcessArgument(int /*argc*/, char * /*argv*/ [], int /*i*/); + +extern void ddxUseMsg(void); + +/* + * idiom processing stuff + */ + +extern xReqPtr PeekNextRequest(xReqPtr req, ClientPtr client, Bool readmore); + +extern void SkipRequests(xReqPtr req, ClientPtr client, int numskipped); + +/* int ReqLen(xReq *req, ClientPtr client) + * Given a pointer to a *complete* request, return its length in bytes. + * Note that if the request is a big request (as defined in the Big + * Requests extension), the macro lies by returning 4 less than the + * length that it actually occupies in the request buffer. This is so you + * can blindly compare the length with the various sz_ constants + * in Xproto.h without having to know/care about big requests. + */ +#define ReqLen(_pxReq, _client) \ + ((_pxReq->length ? \ + (_client->swapped ? lswaps(_pxReq->length) : _pxReq->length) \ + : ((_client->swapped ? \ + lswapl(((CARD32*)_pxReq)[1]) : ((CARD32*)_pxReq)[1])-1) \ + ) << 2) + +/* otherReqTypePtr CastxReq(xReq *req, otherReqTypePtr) + * Cast the given request to one of type otherReqTypePtr to access + * fields beyond the length field. + */ +#define CastxReq(_pxReq, otherReqTypePtr) \ + (_pxReq->length ? (otherReqTypePtr)_pxReq \ + : (otherReqTypePtr)(((CARD32*)_pxReq)+1)) + +/* stuff for SkippedRequestsCallback */ +extern CallbackListPtr SkippedRequestsCallback; +typedef struct { + xReqPtr req; + ClientPtr client; + int numskipped; +} SkippedRequestInfoRec; + +/* stuff for ReplyCallback */ +extern CallbackListPtr ReplyCallback; +typedef struct { + ClientPtr client; + pointer replyData; + unsigned long dataLenBytes; + unsigned long bytesRemaining; + Bool startOfReply; +} ReplyInfoRec; + +/* stuff for FlushCallback */ +extern CallbackListPtr FlushCallback; + +extern void AbortDDX(void); +extern void ddxGiveUp(void); +extern int TimeSinceLastInputEvent(void); + +/* Logging. */ +typedef enum _LogParameter { + XLOG_FLUSH, + XLOG_SYNC, + XLOG_VERBOSITY, + XLOG_FILE_VERBOSITY +} LogParameter; + +/* Flags for log messages. */ +typedef enum { + X_PROBED, /* Value was probed */ + X_CONFIG, /* Value was given in the config file */ + X_DEFAULT, /* Value is a default */ + X_CMDLINE, /* Value was given on the command line */ + X_NOTICE, /* Notice */ + X_ERROR, /* Error message */ + X_WARNING, /* Warning message */ + X_INFO, /* Informational message */ + X_NONE, /* No prefix */ + X_NOT_IMPLEMENTED, /* Not implemented */ + X_UNKNOWN = -1 /* unknown -- this must always be last */ +} MessageType; + +/* XXX Need to check which GCC versions have the format(printf) attribute. */ +#if defined(__GNUC__) && \ + ((__GNUC__ > 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ > 4))) +#define _printf_attribute(a,b) __attribute((format(__printf__,a,b))) +#else +#define _printf_attribute(a,b) /**/ +#endif + +extern const char *LogInit(const char *fname, const char *backup); +extern void LogClose(void); +extern Bool LogSetParameter(LogParameter param, int value); +extern void LogVWrite(int verb, const char *f, va_list args); +extern void LogWrite(int verb, const char *f, ...) _printf_attribute(2,3); +extern void LogVMessageVerb(MessageType type, int verb, const char *format, + va_list args); +extern void LogMessageVerb(MessageType type, int verb, const char *format, + ...) _printf_attribute(3,4); +extern void LogMessage(MessageType type, const char *format, ...) + _printf_attribute(2,3); +extern void FreeAuditTimer(void); +extern void AuditF(const char *f, ...) _printf_attribute(1,2); +extern void VAuditF(const char *f, va_list args); +extern void FatalError(const char *f, ...) _printf_attribute(1,2) +#if defined(__GNUC__) && \ + ((__GNUC__ > 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ > 4))) +__attribute((noreturn)) +#endif +; + +extern void VErrorF(const char *f, va_list args); +extern void ErrorF(const char *f, ...) _printf_attribute(1,2); +extern void Error(char *str); +extern void LogPrintMarkers(void); + +#if defined(NEED_SNPRINTF) && !defined(IN_MODULE) +extern int snprintf(char *str, size_t size, const char *format, ...) + _printf_attribute(3,4); +extern int vsnprintf(char *str, size_t size, const char *format, va_list ap); +#endif + +#endif /* OS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/oscolor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/oscolor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/oscolor.h (revision 51223) @@ -0,0 +1,1508 @@ +static const unsigned char BuiltinColorNames[] = { + "alice blue\0" + "AliceBlue\0" + "antique white\0" + "AntiqueWhite\0" + "AntiqueWhite1\0" + "AntiqueWhite2\0" + "AntiqueWhite3\0" + "AntiqueWhite4\0" + "aquamarine\0" + "aquamarine1\0" + "aquamarine2\0" + "aquamarine3\0" + "aquamarine4\0" + "azure\0" + "azure1\0" + "azure2\0" + "azure3\0" + "azure4\0" + "beige\0" + "bisque\0" + "bisque1\0" + "bisque2\0" + "bisque3\0" + "bisque4\0" + "black\0" + "blanched almond\0" + "BlanchedAlmond\0" + "blue\0" + "blue violet\0" + "blue1\0" + "blue2\0" + "blue3\0" + "blue4\0" + "BlueViolet\0" + "brown\0" + "brown1\0" + "brown2\0" + "brown3\0" + "brown4\0" + "burlywood\0" + "burlywood1\0" + "burlywood2\0" + "burlywood3\0" + "burlywood4\0" + "cadet blue\0" + "CadetBlue\0" + "CadetBlue1\0" + "CadetBlue2\0" + "CadetBlue3\0" + "CadetBlue4\0" + "chartreuse\0" + "chartreuse1\0" + "chartreuse2\0" + "chartreuse3\0" + "chartreuse4\0" + "chocolate\0" + "chocolate1\0" + "chocolate2\0" + "chocolate3\0" + "chocolate4\0" + "coral\0" + "coral1\0" + "coral2\0" + "coral3\0" + "coral4\0" + "cornflower blue\0" + "CornflowerBlue\0" + "cornsilk\0" + "cornsilk1\0" + "cornsilk2\0" + "cornsilk3\0" + "cornsilk4\0" + "cyan\0" + "cyan1\0" + "cyan2\0" + "cyan3\0" + "cyan4\0" + "dark blue\0" + "dark cyan\0" + "dark goldenrod\0" + "dark gray\0" + "dark green\0" + "dark grey\0" + "dark khaki\0" + "dark magenta\0" + "dark olive green\0" + "dark orange\0" + "dark orchid\0" + "dark red\0" + "dark salmon\0" + "dark sea green\0" + "dark slate blue\0" + "dark slate gray\0" + "dark slate grey\0" + "dark turquoise\0" + "dark violet\0" + "DarkBlue\0" + "DarkCyan\0" + "DarkGoldenrod\0" + "DarkGoldenrod1\0" + "DarkGoldenrod2\0" + "DarkGoldenrod3\0" + "DarkGoldenrod4\0" + "DarkGray\0" + "DarkGreen\0" + "DarkGrey\0" + "DarkKhaki\0" + "DarkMagenta\0" + "DarkOliveGreen\0" + "DarkOliveGreen1\0" + "DarkOliveGreen2\0" + "DarkOliveGreen3\0" + "DarkOliveGreen4\0" + "DarkOrange\0" + "DarkOrange1\0" + "DarkOrange2\0" + "DarkOrange3\0" + "DarkOrange4\0" + "DarkOrchid\0" + "DarkOrchid1\0" + "DarkOrchid2\0" + "DarkOrchid3\0" + "DarkOrchid4\0" + "DarkRed\0" + "DarkSalmon\0" + "DarkSeaGreen\0" + "DarkSeaGreen1\0" + "DarkSeaGreen2\0" + "DarkSeaGreen3\0" + "DarkSeaGreen4\0" + "DarkSlateBlue\0" + "DarkSlateGray\0" + "DarkSlateGray1\0" + "DarkSlateGray2\0" + "DarkSlateGray3\0" + "DarkSlateGray4\0" + "DarkSlateGrey\0" + "DarkTurquoise\0" + "DarkViolet\0" + "deep pink\0" + "deep sky blue\0" + "DeepPink\0" + "DeepPink1\0" + "DeepPink2\0" + "DeepPink3\0" + "DeepPink4\0" + "DeepSkyBlue\0" + "DeepSkyBlue1\0" + "DeepSkyBlue2\0" + "DeepSkyBlue3\0" + "DeepSkyBlue4\0" + "dim gray\0" + "dim grey\0" + "DimGray\0" + "DimGrey\0" + "dodger blue\0" + "DodgerBlue\0" + "DodgerBlue1\0" + "DodgerBlue2\0" + "DodgerBlue3\0" + "DodgerBlue4\0" + "firebrick\0" + "firebrick1\0" + "firebrick2\0" + "firebrick3\0" + "firebrick4\0" + "floral white\0" + "FloralWhite\0" + "forest green\0" + "ForestGreen\0" + "gainsboro\0" + "ghost white\0" + "GhostWhite\0" + "gold\0" + "gold1\0" + "gold2\0" + "gold3\0" + "gold4\0" + "goldenrod\0" + "goldenrod1\0" + "goldenrod2\0" + "goldenrod3\0" + "goldenrod4\0" + "gray\0" + "gray0\0" + "gray1\0" + "gray10\0" + "gray100\0" + "gray11\0" + "gray12\0" + "gray13\0" + "gray14\0" + "gray15\0" + "gray16\0" + "gray17\0" + "gray18\0" + "gray19\0" + "gray2\0" + "gray20\0" + "gray21\0" + "gray22\0" + "gray23\0" + "gray24\0" + "gray25\0" + "gray26\0" + "gray27\0" + "gray28\0" + "gray29\0" + "gray3\0" + "gray30\0" + "gray31\0" + "gray32\0" + "gray33\0" + "gray34\0" + "gray35\0" + "gray36\0" + "gray37\0" + "gray38\0" + "gray39\0" + "gray4\0" + "gray40\0" + "gray41\0" + "gray42\0" + "gray43\0" + "gray44\0" + "gray45\0" + "gray46\0" + "gray47\0" + "gray48\0" + "gray49\0" + "gray5\0" + "gray50\0" + "gray51\0" + "gray52\0" + "gray53\0" + "gray54\0" + "gray55\0" + "gray56\0" + "gray57\0" + "gray58\0" + "gray59\0" + "gray6\0" + "gray60\0" + "gray61\0" + "gray62\0" + "gray63\0" + "gray64\0" + "gray65\0" + "gray66\0" + "gray67\0" + "gray68\0" + "gray69\0" + "gray7\0" + "gray70\0" + "gray71\0" + "gray72\0" + "gray73\0" + "gray74\0" + "gray75\0" + "gray76\0" + "gray77\0" + "gray78\0" + "gray79\0" + "gray8\0" + "gray80\0" + "gray81\0" + "gray82\0" + "gray83\0" + "gray84\0" + "gray85\0" + "gray86\0" + "gray87\0" + "gray88\0" + "gray89\0" + "gray9\0" + "gray90\0" + "gray91\0" + "gray92\0" + "gray93\0" + "gray94\0" + "gray95\0" + "gray96\0" + "gray97\0" + "gray98\0" + "gray99\0" + "green\0" + "green yellow\0" + "green1\0" + "green2\0" + "green3\0" + "green4\0" + "GreenYellow\0" + "grey\0" + "grey0\0" + "grey1\0" + "grey10\0" + "grey100\0" + "grey11\0" + "grey12\0" + "grey13\0" + "grey14\0" + "grey15\0" + "grey16\0" + "grey17\0" + "grey18\0" + "grey19\0" + "grey2\0" + "grey20\0" + "grey21\0" + "grey22\0" + "grey23\0" + "grey24\0" + "grey25\0" + "grey26\0" + "grey27\0" + "grey28\0" + "grey29\0" + "grey3\0" + "grey30\0" + "grey31\0" + "grey32\0" + "grey33\0" + "grey34\0" + "grey35\0" + "grey36\0" + "grey37\0" + "grey38\0" + "grey39\0" + "grey4\0" + "grey40\0" + "grey41\0" + "grey42\0" + "grey43\0" + "grey44\0" + "grey45\0" + "grey46\0" + "grey47\0" + "grey48\0" + "grey49\0" + "grey5\0" + "grey50\0" + "grey51\0" + "grey52\0" + "grey53\0" + "grey54\0" + "grey55\0" + "grey56\0" + "grey57\0" + "grey58\0" + "grey59\0" + "grey6\0" + "grey60\0" + "grey61\0" + "grey62\0" + "grey63\0" + "grey64\0" + "grey65\0" + "grey66\0" + "grey67\0" + "grey68\0" + "grey69\0" + "grey7\0" + "grey70\0" + "grey71\0" + "grey72\0" + "grey73\0" + "grey74\0" + "grey75\0" + "grey76\0" + "grey77\0" + "grey78\0" + "grey79\0" + "grey8\0" + "grey80\0" + "grey81\0" + "grey82\0" + "grey83\0" + "grey84\0" + "grey85\0" + "grey86\0" + "grey87\0" + "grey88\0" + "grey89\0" + "grey9\0" + "grey90\0" + "grey91\0" + "grey92\0" + "grey93\0" + "grey94\0" + "grey95\0" + "grey96\0" + "grey97\0" + "grey98\0" + "grey99\0" + "honeydew\0" + "honeydew1\0" + "honeydew2\0" + "honeydew3\0" + "honeydew4\0" + "hot pink\0" + "HotPink\0" + "HotPink1\0" + "HotPink2\0" + "HotPink3\0" + "HotPink4\0" + "indian red\0" + "IndianRed\0" + "IndianRed1\0" + "IndianRed2\0" + "IndianRed3\0" + "IndianRed4\0" + "ivory\0" + "ivory1\0" + "ivory2\0" + "ivory3\0" + "ivory4\0" + "khaki\0" + "khaki1\0" + "khaki2\0" + "khaki3\0" + "khaki4\0" + "lavender\0" + "lavender blush\0" + "LavenderBlush\0" + "LavenderBlush1\0" + "LavenderBlush2\0" + "LavenderBlush3\0" + "LavenderBlush4\0" + "lawn green\0" + "LawnGreen\0" + "lemon chiffon\0" + "LemonChiffon\0" + "LemonChiffon1\0" + "LemonChiffon2\0" + "LemonChiffon3\0" + "LemonChiffon4\0" + "light blue\0" + "light coral\0" + "light cyan\0" + "light goldenrod\0" + "light goldenrod yellow\0" + "light gray\0" + "light green\0" + "light grey\0" + "light pink\0" + "light salmon\0" + "light sea green\0" + "light sky blue\0" + "light slate blue\0" + "light slate gray\0" + "light slate grey\0" + "light steel blue\0" + "light yellow\0" + "LightBlue\0" + "LightBlue1\0" + "LightBlue2\0" + "LightBlue3\0" + "LightBlue4\0" + "LightCoral\0" + "LightCyan\0" + "LightCyan1\0" + "LightCyan2\0" + "LightCyan3\0" + "LightCyan4\0" + "LightGoldenrod\0" + "LightGoldenrod1\0" + "LightGoldenrod2\0" + "LightGoldenrod3\0" + "LightGoldenrod4\0" + "LightGoldenrodYellow\0" + "LightGray\0" + "LightGreen\0" + "LightGrey\0" + "LightPink\0" + "LightPink1\0" + "LightPink2\0" + "LightPink3\0" + "LightPink4\0" + "LightSalmon\0" + "LightSalmon1\0" + "LightSalmon2\0" + "LightSalmon3\0" + "LightSalmon4\0" + "LightSeaGreen\0" + "LightSkyBlue\0" + "LightSkyBlue1\0" + "LightSkyBlue2\0" + "LightSkyBlue3\0" + "LightSkyBlue4\0" + "LightSlateBlue\0" + "LightSlateGray\0" + "LightSlateGrey\0" + "LightSteelBlue\0" + "LightSteelBlue1\0" + "LightSteelBlue2\0" + "LightSteelBlue3\0" + "LightSteelBlue4\0" + "LightYellow\0" + "LightYellow1\0" + "LightYellow2\0" + "LightYellow3\0" + "LightYellow4\0" + "lime green\0" + "LimeGreen\0" + "linen\0" + "magenta\0" + "magenta1\0" + "magenta2\0" + "magenta3\0" + "magenta4\0" + "maroon\0" + "maroon1\0" + "maroon2\0" + "maroon3\0" + "maroon4\0" + "medium aquamarine\0" + "medium blue\0" + "medium orchid\0" + "medium purple\0" + "medium sea green\0" + "medium slate blue\0" + "medium spring green\0" + "medium turquoise\0" + "medium violet red\0" + "MediumAquamarine\0" + "MediumBlue\0" + "MediumOrchid\0" + "MediumOrchid1\0" + "MediumOrchid2\0" + "MediumOrchid3\0" + "MediumOrchid4\0" + "MediumPurple\0" + "MediumPurple1\0" + "MediumPurple2\0" + "MediumPurple3\0" + "MediumPurple4\0" + "MediumSeaGreen\0" + "MediumSlateBlue\0" + "MediumSpringGreen\0" + "MediumTurquoise\0" + "MediumVioletRed\0" + "midnight blue\0" + "MidnightBlue\0" + "mint cream\0" + "MintCream\0" + "misty rose\0" + "MistyRose\0" + "MistyRose1\0" + "MistyRose2\0" + "MistyRose3\0" + "MistyRose4\0" + "moccasin\0" + "navajo white\0" + "NavajoWhite\0" + "NavajoWhite1\0" + "NavajoWhite2\0" + "NavajoWhite3\0" + "NavajoWhite4\0" + "navy\0" + "navy blue\0" + "NavyBlue\0" + "old lace\0" + "OldLace\0" + "olive drab\0" + "OliveDrab\0" + "OliveDrab1\0" + "OliveDrab2\0" + "OliveDrab3\0" + "OliveDrab4\0" + "orange\0" + "orange red\0" + "orange1\0" + "orange2\0" + "orange3\0" + "orange4\0" + "OrangeRed\0" + "OrangeRed1\0" + "OrangeRed2\0" + "OrangeRed3\0" + "OrangeRed4\0" + "orchid\0" + "orchid1\0" + "orchid2\0" + "orchid3\0" + "orchid4\0" + "pale goldenrod\0" + "pale green\0" + "pale turquoise\0" + "pale violet red\0" + "PaleGoldenrod\0" + "PaleGreen\0" + "PaleGreen1\0" + "PaleGreen2\0" + "PaleGreen3\0" + "PaleGreen4\0" + "PaleTurquoise\0" + "PaleTurquoise1\0" + "PaleTurquoise2\0" + "PaleTurquoise3\0" + "PaleTurquoise4\0" + "PaleVioletRed\0" + "PaleVioletRed1\0" + "PaleVioletRed2\0" + "PaleVioletRed3\0" + "PaleVioletRed4\0" + "papaya whip\0" + "PapayaWhip\0" + "peach puff\0" + "PeachPuff\0" + "PeachPuff1\0" + "PeachPuff2\0" + "PeachPuff3\0" + "PeachPuff4\0" + "peru\0" + "pink\0" + "pink1\0" + "pink2\0" + "pink3\0" + "pink4\0" + "plum\0" + "plum1\0" + "plum2\0" + "plum3\0" + "plum4\0" + "powder blue\0" + "PowderBlue\0" + "purple\0" + "purple1\0" + "purple2\0" + "purple3\0" + "purple4\0" + "red\0" + "red1\0" + "red2\0" + "red3\0" + "red4\0" + "rosy brown\0" + "RosyBrown\0" + "RosyBrown1\0" + "RosyBrown2\0" + "RosyBrown3\0" + "RosyBrown4\0" + "royal blue\0" + "RoyalBlue\0" + "RoyalBlue1\0" + "RoyalBlue2\0" + "RoyalBlue3\0" + "RoyalBlue4\0" + "saddle brown\0" + "SaddleBrown\0" + "salmon\0" + "salmon1\0" + "salmon2\0" + "salmon3\0" + "salmon4\0" + "sandy brown\0" + "SandyBrown\0" + "sea green\0" + "SeaGreen\0" + "SeaGreen1\0" + "SeaGreen2\0" + "SeaGreen3\0" + "SeaGreen4\0" + "seashell\0" + "seashell1\0" + "seashell2\0" + "seashell3\0" + "seashell4\0" + "sienna\0" + "sienna1\0" + "sienna2\0" + "sienna3\0" + "sienna4\0" + "sky blue\0" + "SkyBlue\0" + "SkyBlue1\0" + "SkyBlue2\0" + "SkyBlue3\0" + "SkyBlue4\0" + "slate blue\0" + "slate gray\0" + "slate grey\0" + "SlateBlue\0" + "SlateBlue1\0" + "SlateBlue2\0" + "SlateBlue3\0" + "SlateBlue4\0" + "SlateGray\0" + "SlateGray1\0" + "SlateGray2\0" + "SlateGray3\0" + "SlateGray4\0" + "SlateGrey\0" + "snow\0" + "snow1\0" + "snow2\0" + "snow3\0" + "snow4\0" + "spring green\0" + "SpringGreen\0" + "SpringGreen1\0" + "SpringGreen2\0" + "SpringGreen3\0" + "SpringGreen4\0" + "steel blue\0" + "SteelBlue\0" + "SteelBlue1\0" + "SteelBlue2\0" + "SteelBlue3\0" + "SteelBlue4\0" + "tan\0" + "tan1\0" + "tan2\0" + "tan3\0" + "tan4\0" + "thistle\0" + "thistle1\0" + "thistle2\0" + "thistle3\0" + "thistle4\0" + "tomato\0" + "tomato1\0" + "tomato2\0" + "tomato3\0" + "tomato4\0" + "turquoise\0" + "turquoise1\0" + "turquoise2\0" + "turquoise3\0" + "turquoise4\0" + "violet\0" + "violet red\0" + "VioletRed\0" + "VioletRed1\0" + "VioletRed2\0" + "VioletRed3\0" + "VioletRed4\0" + "wheat\0" + "wheat1\0" + "wheat2\0" + "wheat3\0" + "wheat4\0" + "white\0" + "white smoke\0" + "WhiteSmoke\0" + "yellow\0" + "yellow green\0" + "yellow1\0" + "yellow2\0" + "yellow3\0" + "yellow4\0" + "YellowGreen\0" +}; +static const BuiltinColor BuiltinColors[] = { + { 240, 248, 255, 0 }, /* alice blue */ + { 240, 248, 255, 11 }, /* AliceBlue */ + { 250, 235, 215, 21 }, /* antique white */ + { 250, 235, 215, 35 }, /* AntiqueWhite */ + { 255, 239, 219, 48 }, /* AntiqueWhite1 */ + { 238, 223, 204, 62 }, /* AntiqueWhite2 */ + { 205, 192, 176, 76 }, /* AntiqueWhite3 */ + { 139, 131, 120, 90 }, /* AntiqueWhite4 */ + { 127, 255, 212, 104 }, /* aquamarine */ + { 127, 255, 212, 115 }, /* aquamarine1 */ + { 118, 238, 198, 127 }, /* aquamarine2 */ + { 102, 205, 170, 139 }, /* aquamarine3 */ + { 69, 139, 116, 151 }, /* aquamarine4 */ + { 240, 255, 255, 163 }, /* azure */ + { 240, 255, 255, 169 }, /* azure1 */ + { 224, 238, 238, 176 }, /* azure2 */ + { 193, 205, 205, 183 }, /* azure3 */ + { 131, 139, 139, 190 }, /* azure4 */ + { 245, 245, 220, 197 }, /* beige */ + { 255, 228, 196, 203 }, /* bisque */ + { 255, 228, 196, 210 }, /* bisque1 */ + { 238, 213, 183, 218 }, /* bisque2 */ + { 205, 183, 158, 226 }, /* bisque3 */ + { 139, 125, 107, 234 }, /* bisque4 */ + { 0, 0, 0, 242 }, /* black */ + { 255, 235, 205, 248 }, /* blanched almond */ + { 255, 235, 205, 264 }, /* BlanchedAlmond */ + { 0, 0, 255, 279 }, /* blue */ + { 138, 43, 226, 284 }, /* blue violet */ + { 0, 0, 255, 296 }, /* blue1 */ + { 0, 0, 238, 302 }, /* blue2 */ + { 0, 0, 205, 308 }, /* blue3 */ + { 0, 0, 139, 314 }, /* blue4 */ + { 138, 43, 226, 320 }, /* BlueViolet */ + { 165, 42, 42, 331 }, /* brown */ + { 255, 64, 64, 337 }, /* brown1 */ + { 238, 59, 59, 344 }, /* brown2 */ + { 205, 51, 51, 351 }, /* brown3 */ + { 139, 35, 35, 358 }, /* brown4 */ + { 222, 184, 135, 365 }, /* burlywood */ + { 255, 211, 155, 375 }, /* burlywood1 */ + { 238, 197, 145, 386 }, /* burlywood2 */ + { 205, 170, 125, 397 }, /* burlywood3 */ + { 139, 115, 85, 408 }, /* burlywood4 */ + { 95, 158, 160, 419 }, /* cadet blue */ + { 95, 158, 160, 430 }, /* CadetBlue */ + { 152, 245, 255, 440 }, /* CadetBlue1 */ + { 142, 229, 238, 451 }, /* CadetBlue2 */ + { 122, 197, 205, 462 }, /* CadetBlue3 */ + { 83, 134, 139, 473 }, /* CadetBlue4 */ + { 127, 255, 0, 484 }, /* chartreuse */ + { 127, 255, 0, 495 }, /* chartreuse1 */ + { 118, 238, 0, 507 }, /* chartreuse2 */ + { 102, 205, 0, 519 }, /* chartreuse3 */ + { 69, 139, 0, 531 }, /* chartreuse4 */ + { 210, 105, 30, 543 }, /* chocolate */ + { 255, 127, 36, 553 }, /* chocolate1 */ + { 238, 118, 33, 564 }, /* chocolate2 */ + { 205, 102, 29, 575 }, /* chocolate3 */ + { 139, 69, 19, 586 }, /* chocolate4 */ + { 255, 127, 80, 597 }, /* coral */ + { 255, 114, 86, 603 }, /* coral1 */ + { 238, 106, 80, 610 }, /* coral2 */ + { 205, 91, 69, 617 }, /* coral3 */ + { 139, 62, 47, 624 }, /* coral4 */ + { 100, 149, 237, 631 }, /* cornflower blue */ + { 100, 149, 237, 647 }, /* CornflowerBlue */ + { 255, 248, 220, 662 }, /* cornsilk */ + { 255, 248, 220, 671 }, /* cornsilk1 */ + { 238, 232, 205, 681 }, /* cornsilk2 */ + { 205, 200, 177, 691 }, /* cornsilk3 */ + { 139, 136, 120, 701 }, /* cornsilk4 */ + { 0, 255, 255, 711 }, /* cyan */ + { 0, 255, 255, 716 }, /* cyan1 */ + { 0, 238, 238, 722 }, /* cyan2 */ + { 0, 205, 205, 728 }, /* cyan3 */ + { 0, 139, 139, 734 }, /* cyan4 */ + { 0, 0, 139, 740 }, /* dark blue */ + { 0, 139, 139, 750 }, /* dark cyan */ + { 184, 134, 11, 760 }, /* dark goldenrod */ + { 169, 169, 169, 775 }, /* dark gray */ + { 0, 100, 0, 785 }, /* dark green */ + { 169, 169, 169, 796 }, /* dark grey */ + { 189, 183, 107, 806 }, /* dark khaki */ + { 139, 0, 139, 817 }, /* dark magenta */ + { 85, 107, 47, 830 }, /* dark olive green */ + { 255, 140, 0, 847 }, /* dark orange */ + { 153, 50, 204, 859 }, /* dark orchid */ + { 139, 0, 0, 871 }, /* dark red */ + { 233, 150, 122, 880 }, /* dark salmon */ + { 143, 188, 143, 892 }, /* dark sea green */ + { 72, 61, 139, 907 }, /* dark slate blue */ + { 47, 79, 79, 923 }, /* dark slate gray */ + { 47, 79, 79, 939 }, /* dark slate grey */ + { 0, 206, 209, 955 }, /* dark turquoise */ + { 148, 0, 211, 970 }, /* dark violet */ + { 0, 0, 139, 982 }, /* DarkBlue */ + { 0, 139, 139, 991 }, /* DarkCyan */ + { 184, 134, 11, 1000 }, /* DarkGoldenrod */ + { 255, 185, 15, 1014 }, /* DarkGoldenrod1 */ + { 238, 173, 14, 1029 }, /* DarkGoldenrod2 */ + { 205, 149, 12, 1044 }, /* DarkGoldenrod3 */ + { 139, 101, 8, 1059 }, /* DarkGoldenrod4 */ + { 169, 169, 169, 1074 }, /* DarkGray */ + { 0, 100, 0, 1083 }, /* DarkGreen */ + { 169, 169, 169, 1093 }, /* DarkGrey */ + { 189, 183, 107, 1102 }, /* DarkKhaki */ + { 139, 0, 139, 1112 }, /* DarkMagenta */ + { 85, 107, 47, 1124 }, /* DarkOliveGreen */ + { 202, 255, 112, 1139 }, /* DarkOliveGreen1 */ + { 188, 238, 104, 1155 }, /* DarkOliveGreen2 */ + { 162, 205, 90, 1171 }, /* DarkOliveGreen3 */ + { 110, 139, 61, 1187 }, /* DarkOliveGreen4 */ + { 255, 140, 0, 1203 }, /* DarkOrange */ + { 255, 127, 0, 1214 }, /* DarkOrange1 */ + { 238, 118, 0, 1226 }, /* DarkOrange2 */ + { 205, 102, 0, 1238 }, /* DarkOrange3 */ + { 139, 69, 0, 1250 }, /* DarkOrange4 */ + { 153, 50, 204, 1262 }, /* DarkOrchid */ + { 191, 62, 255, 1273 }, /* DarkOrchid1 */ + { 178, 58, 238, 1285 }, /* DarkOrchid2 */ + { 154, 50, 205, 1297 }, /* DarkOrchid3 */ + { 104, 34, 139, 1309 }, /* DarkOrchid4 */ + { 139, 0, 0, 1321 }, /* DarkRed */ + { 233, 150, 122, 1329 }, /* DarkSalmon */ + { 143, 188, 143, 1340 }, /* DarkSeaGreen */ + { 193, 255, 193, 1353 }, /* DarkSeaGreen1 */ + { 180, 238, 180, 1367 }, /* DarkSeaGreen2 */ + { 155, 205, 155, 1381 }, /* DarkSeaGreen3 */ + { 105, 139, 105, 1395 }, /* DarkSeaGreen4 */ + { 72, 61, 139, 1409 }, /* DarkSlateBlue */ + { 47, 79, 79, 1423 }, /* DarkSlateGray */ + { 151, 255, 255, 1437 }, /* DarkSlateGray1 */ + { 141, 238, 238, 1452 }, /* DarkSlateGray2 */ + { 121, 205, 205, 1467 }, /* DarkSlateGray3 */ + { 82, 139, 139, 1482 }, /* DarkSlateGray4 */ + { 47, 79, 79, 1497 }, /* DarkSlateGrey */ + { 0, 206, 209, 1511 }, /* DarkTurquoise */ + { 148, 0, 211, 1525 }, /* DarkViolet */ + { 255, 20, 147, 1536 }, /* deep pink */ + { 0, 191, 255, 1546 }, /* deep sky blue */ + { 255, 20, 147, 1560 }, /* DeepPink */ + { 255, 20, 147, 1569 }, /* DeepPink1 */ + { 238, 18, 137, 1579 }, /* DeepPink2 */ + { 205, 16, 118, 1589 }, /* DeepPink3 */ + { 139, 10, 80, 1599 }, /* DeepPink4 */ + { 0, 191, 255, 1609 }, /* DeepSkyBlue */ + { 0, 191, 255, 1621 }, /* DeepSkyBlue1 */ + { 0, 178, 238, 1634 }, /* DeepSkyBlue2 */ + { 0, 154, 205, 1647 }, /* DeepSkyBlue3 */ + { 0, 104, 139, 1660 }, /* DeepSkyBlue4 */ + { 105, 105, 105, 1673 }, /* dim gray */ + { 105, 105, 105, 1682 }, /* dim grey */ + { 105, 105, 105, 1691 }, /* DimGray */ + { 105, 105, 105, 1699 }, /* DimGrey */ + { 30, 144, 255, 1707 }, /* dodger blue */ + { 30, 144, 255, 1719 }, /* DodgerBlue */ + { 30, 144, 255, 1730 }, /* DodgerBlue1 */ + { 28, 134, 238, 1742 }, /* DodgerBlue2 */ + { 24, 116, 205, 1754 }, /* DodgerBlue3 */ + { 16, 78, 139, 1766 }, /* DodgerBlue4 */ + { 178, 34, 34, 1778 }, /* firebrick */ + { 255, 48, 48, 1788 }, /* firebrick1 */ + { 238, 44, 44, 1799 }, /* firebrick2 */ + { 205, 38, 38, 1810 }, /* firebrick3 */ + { 139, 26, 26, 1821 }, /* firebrick4 */ + { 255, 250, 240, 1832 }, /* floral white */ + { 255, 250, 240, 1845 }, /* FloralWhite */ + { 34, 139, 34, 1857 }, /* forest green */ + { 34, 139, 34, 1870 }, /* ForestGreen */ + { 220, 220, 220, 1882 }, /* gainsboro */ + { 248, 248, 255, 1892 }, /* ghost white */ + { 248, 248, 255, 1904 }, /* GhostWhite */ + { 255, 215, 0, 1915 }, /* gold */ + { 255, 215, 0, 1920 }, /* gold1 */ + { 238, 201, 0, 1926 }, /* gold2 */ + { 205, 173, 0, 1932 }, /* gold3 */ + { 139, 117, 0, 1938 }, /* gold4 */ + { 218, 165, 32, 1944 }, /* goldenrod */ + { 255, 193, 37, 1954 }, /* goldenrod1 */ + { 238, 180, 34, 1965 }, /* goldenrod2 */ + { 205, 155, 29, 1976 }, /* goldenrod3 */ + { 139, 105, 20, 1987 }, /* goldenrod4 */ + { 190, 190, 190, 1998 }, /* gray */ + { 0, 0, 0, 2003 }, /* gray0 */ + { 3, 3, 3, 2009 }, /* gray1 */ + { 26, 26, 26, 2015 }, /* gray10 */ + { 255, 255, 255, 2022 }, /* gray100 */ + { 28, 28, 28, 2030 }, /* gray11 */ + { 31, 31, 31, 2037 }, /* gray12 */ + { 33, 33, 33, 2044 }, /* gray13 */ + { 36, 36, 36, 2051 }, /* gray14 */ + { 38, 38, 38, 2058 }, /* gray15 */ + { 41, 41, 41, 2065 }, /* gray16 */ + { 43, 43, 43, 2072 }, /* gray17 */ + { 46, 46, 46, 2079 }, /* gray18 */ + { 48, 48, 48, 2086 }, /* gray19 */ + { 5, 5, 5, 2093 }, /* gray2 */ + { 51, 51, 51, 2099 }, /* gray20 */ + { 54, 54, 54, 2106 }, /* gray21 */ + { 56, 56, 56, 2113 }, /* gray22 */ + { 59, 59, 59, 2120 }, /* gray23 */ + { 61, 61, 61, 2127 }, /* gray24 */ + { 64, 64, 64, 2134 }, /* gray25 */ + { 66, 66, 66, 2141 }, /* gray26 */ + { 69, 69, 69, 2148 }, /* gray27 */ + { 71, 71, 71, 2155 }, /* gray28 */ + { 74, 74, 74, 2162 }, /* gray29 */ + { 8, 8, 8, 2169 }, /* gray3 */ + { 77, 77, 77, 2175 }, /* gray30 */ + { 79, 79, 79, 2182 }, /* gray31 */ + { 82, 82, 82, 2189 }, /* gray32 */ + { 84, 84, 84, 2196 }, /* gray33 */ + { 87, 87, 87, 2203 }, /* gray34 */ + { 89, 89, 89, 2210 }, /* gray35 */ + { 92, 92, 92, 2217 }, /* gray36 */ + { 94, 94, 94, 2224 }, /* gray37 */ + { 97, 97, 97, 2231 }, /* gray38 */ + { 99, 99, 99, 2238 }, /* gray39 */ + { 10, 10, 10, 2245 }, /* gray4 */ + { 102, 102, 102, 2251 }, /* gray40 */ + { 105, 105, 105, 2258 }, /* gray41 */ + { 107, 107, 107, 2265 }, /* gray42 */ + { 110, 110, 110, 2272 }, /* gray43 */ + { 112, 112, 112, 2279 }, /* gray44 */ + { 115, 115, 115, 2286 }, /* gray45 */ + { 117, 117, 117, 2293 }, /* gray46 */ + { 120, 120, 120, 2300 }, /* gray47 */ + { 122, 122, 122, 2307 }, /* gray48 */ + { 125, 125, 125, 2314 }, /* gray49 */ + { 13, 13, 13, 2321 }, /* gray5 */ + { 127, 127, 127, 2327 }, /* gray50 */ + { 130, 130, 130, 2334 }, /* gray51 */ + { 133, 133, 133, 2341 }, /* gray52 */ + { 135, 135, 135, 2348 }, /* gray53 */ + { 138, 138, 138, 2355 }, /* gray54 */ + { 140, 140, 140, 2362 }, /* gray55 */ + { 143, 143, 143, 2369 }, /* gray56 */ + { 145, 145, 145, 2376 }, /* gray57 */ + { 148, 148, 148, 2383 }, /* gray58 */ + { 150, 150, 150, 2390 }, /* gray59 */ + { 15, 15, 15, 2397 }, /* gray6 */ + { 153, 153, 153, 2403 }, /* gray60 */ + { 156, 156, 156, 2410 }, /* gray61 */ + { 158, 158, 158, 2417 }, /* gray62 */ + { 161, 161, 161, 2424 }, /* gray63 */ + { 163, 163, 163, 2431 }, /* gray64 */ + { 166, 166, 166, 2438 }, /* gray65 */ + { 168, 168, 168, 2445 }, /* gray66 */ + { 171, 171, 171, 2452 }, /* gray67 */ + { 173, 173, 173, 2459 }, /* gray68 */ + { 176, 176, 176, 2466 }, /* gray69 */ + { 18, 18, 18, 2473 }, /* gray7 */ + { 179, 179, 179, 2479 }, /* gray70 */ + { 181, 181, 181, 2486 }, /* gray71 */ + { 184, 184, 184, 2493 }, /* gray72 */ + { 186, 186, 186, 2500 }, /* gray73 */ + { 189, 189, 189, 2507 }, /* gray74 */ + { 191, 191, 191, 2514 }, /* gray75 */ + { 194, 194, 194, 2521 }, /* gray76 */ + { 196, 196, 196, 2528 }, /* gray77 */ + { 199, 199, 199, 2535 }, /* gray78 */ + { 201, 201, 201, 2542 }, /* gray79 */ + { 20, 20, 20, 2549 }, /* gray8 */ + { 204, 204, 204, 2555 }, /* gray80 */ + { 207, 207, 207, 2562 }, /* gray81 */ + { 209, 209, 209, 2569 }, /* gray82 */ + { 212, 212, 212, 2576 }, /* gray83 */ + { 214, 214, 214, 2583 }, /* gray84 */ + { 217, 217, 217, 2590 }, /* gray85 */ + { 219, 219, 219, 2597 }, /* gray86 */ + { 222, 222, 222, 2604 }, /* gray87 */ + { 224, 224, 224, 2611 }, /* gray88 */ + { 227, 227, 227, 2618 }, /* gray89 */ + { 23, 23, 23, 2625 }, /* gray9 */ + { 229, 229, 229, 2631 }, /* gray90 */ + { 232, 232, 232, 2638 }, /* gray91 */ + { 235, 235, 235, 2645 }, /* gray92 */ + { 237, 237, 237, 2652 }, /* gray93 */ + { 240, 240, 240, 2659 }, /* gray94 */ + { 242, 242, 242, 2666 }, /* gray95 */ + { 245, 245, 245, 2673 }, /* gray96 */ + { 247, 247, 247, 2680 }, /* gray97 */ + { 250, 250, 250, 2687 }, /* gray98 */ + { 252, 252, 252, 2694 }, /* gray99 */ + { 0, 255, 0, 2701 }, /* green */ + { 173, 255, 47, 2707 }, /* green yellow */ + { 0, 255, 0, 2720 }, /* green1 */ + { 0, 238, 0, 2727 }, /* green2 */ + { 0, 205, 0, 2734 }, /* green3 */ + { 0, 139, 0, 2741 }, /* green4 */ + { 173, 255, 47, 2748 }, /* GreenYellow */ + { 190, 190, 190, 2760 }, /* grey */ + { 0, 0, 0, 2765 }, /* grey0 */ + { 3, 3, 3, 2771 }, /* grey1 */ + { 26, 26, 26, 2777 }, /* grey10 */ + { 255, 255, 255, 2784 }, /* grey100 */ + { 28, 28, 28, 2792 }, /* grey11 */ + { 31, 31, 31, 2799 }, /* grey12 */ + { 33, 33, 33, 2806 }, /* grey13 */ + { 36, 36, 36, 2813 }, /* grey14 */ + { 38, 38, 38, 2820 }, /* grey15 */ + { 41, 41, 41, 2827 }, /* grey16 */ + { 43, 43, 43, 2834 }, /* grey17 */ + { 46, 46, 46, 2841 }, /* grey18 */ + { 48, 48, 48, 2848 }, /* grey19 */ + { 5, 5, 5, 2855 }, /* grey2 */ + { 51, 51, 51, 2861 }, /* grey20 */ + { 54, 54, 54, 2868 }, /* grey21 */ + { 56, 56, 56, 2875 }, /* grey22 */ + { 59, 59, 59, 2882 }, /* grey23 */ + { 61, 61, 61, 2889 }, /* grey24 */ + { 64, 64, 64, 2896 }, /* grey25 */ + { 66, 66, 66, 2903 }, /* grey26 */ + { 69, 69, 69, 2910 }, /* grey27 */ + { 71, 71, 71, 2917 }, /* grey28 */ + { 74, 74, 74, 2924 }, /* grey29 */ + { 8, 8, 8, 2931 }, /* grey3 */ + { 77, 77, 77, 2937 }, /* grey30 */ + { 79, 79, 79, 2944 }, /* grey31 */ + { 82, 82, 82, 2951 }, /* grey32 */ + { 84, 84, 84, 2958 }, /* grey33 */ + { 87, 87, 87, 2965 }, /* grey34 */ + { 89, 89, 89, 2972 }, /* grey35 */ + { 92, 92, 92, 2979 }, /* grey36 */ + { 94, 94, 94, 2986 }, /* grey37 */ + { 97, 97, 97, 2993 }, /* grey38 */ + { 99, 99, 99, 3000 }, /* grey39 */ + { 10, 10, 10, 3007 }, /* grey4 */ + { 102, 102, 102, 3013 }, /* grey40 */ + { 105, 105, 105, 3020 }, /* grey41 */ + { 107, 107, 107, 3027 }, /* grey42 */ + { 110, 110, 110, 3034 }, /* grey43 */ + { 112, 112, 112, 3041 }, /* grey44 */ + { 115, 115, 115, 3048 }, /* grey45 */ + { 117, 117, 117, 3055 }, /* grey46 */ + { 120, 120, 120, 3062 }, /* grey47 */ + { 122, 122, 122, 3069 }, /* grey48 */ + { 125, 125, 125, 3076 }, /* grey49 */ + { 13, 13, 13, 3083 }, /* grey5 */ + { 127, 127, 127, 3089 }, /* grey50 */ + { 130, 130, 130, 3096 }, /* grey51 */ + { 133, 133, 133, 3103 }, /* grey52 */ + { 135, 135, 135, 3110 }, /* grey53 */ + { 138, 138, 138, 3117 }, /* grey54 */ + { 140, 140, 140, 3124 }, /* grey55 */ + { 143, 143, 143, 3131 }, /* grey56 */ + { 145, 145, 145, 3138 }, /* grey57 */ + { 148, 148, 148, 3145 }, /* grey58 */ + { 150, 150, 150, 3152 }, /* grey59 */ + { 15, 15, 15, 3159 }, /* grey6 */ + { 153, 153, 153, 3165 }, /* grey60 */ + { 156, 156, 156, 3172 }, /* grey61 */ + { 158, 158, 158, 3179 }, /* grey62 */ + { 161, 161, 161, 3186 }, /* grey63 */ + { 163, 163, 163, 3193 }, /* grey64 */ + { 166, 166, 166, 3200 }, /* grey65 */ + { 168, 168, 168, 3207 }, /* grey66 */ + { 171, 171, 171, 3214 }, /* grey67 */ + { 173, 173, 173, 3221 }, /* grey68 */ + { 176, 176, 176, 3228 }, /* grey69 */ + { 18, 18, 18, 3235 }, /* grey7 */ + { 179, 179, 179, 3241 }, /* grey70 */ + { 181, 181, 181, 3248 }, /* grey71 */ + { 184, 184, 184, 3255 }, /* grey72 */ + { 186, 186, 186, 3262 }, /* grey73 */ + { 189, 189, 189, 3269 }, /* grey74 */ + { 191, 191, 191, 3276 }, /* grey75 */ + { 194, 194, 194, 3283 }, /* grey76 */ + { 196, 196, 196, 3290 }, /* grey77 */ + { 199, 199, 199, 3297 }, /* grey78 */ + { 201, 201, 201, 3304 }, /* grey79 */ + { 20, 20, 20, 3311 }, /* grey8 */ + { 204, 204, 204, 3317 }, /* grey80 */ + { 207, 207, 207, 3324 }, /* grey81 */ + { 209, 209, 209, 3331 }, /* grey82 */ + { 212, 212, 212, 3338 }, /* grey83 */ + { 214, 214, 214, 3345 }, /* grey84 */ + { 217, 217, 217, 3352 }, /* grey85 */ + { 219, 219, 219, 3359 }, /* grey86 */ + { 222, 222, 222, 3366 }, /* grey87 */ + { 224, 224, 224, 3373 }, /* grey88 */ + { 227, 227, 227, 3380 }, /* grey89 */ + { 23, 23, 23, 3387 }, /* grey9 */ + { 229, 229, 229, 3393 }, /* grey90 */ + { 232, 232, 232, 3400 }, /* grey91 */ + { 235, 235, 235, 3407 }, /* grey92 */ + { 237, 237, 237, 3414 }, /* grey93 */ + { 240, 240, 240, 3421 }, /* grey94 */ + { 242, 242, 242, 3428 }, /* grey95 */ + { 245, 245, 245, 3435 }, /* grey96 */ + { 247, 247, 247, 3442 }, /* grey97 */ + { 250, 250, 250, 3449 }, /* grey98 */ + { 252, 252, 252, 3456 }, /* grey99 */ + { 240, 255, 240, 3463 }, /* honeydew */ + { 240, 255, 240, 3472 }, /* honeydew1 */ + { 224, 238, 224, 3482 }, /* honeydew2 */ + { 193, 205, 193, 3492 }, /* honeydew3 */ + { 131, 139, 131, 3502 }, /* honeydew4 */ + { 255, 105, 180, 3512 }, /* hot pink */ + { 255, 105, 180, 3521 }, /* HotPink */ + { 255, 110, 180, 3529 }, /* HotPink1 */ + { 238, 106, 167, 3538 }, /* HotPink2 */ + { 205, 96, 144, 3547 }, /* HotPink3 */ + { 139, 58, 98, 3556 }, /* HotPink4 */ + { 205, 92, 92, 3565 }, /* indian red */ + { 205, 92, 92, 3576 }, /* IndianRed */ + { 255, 106, 106, 3586 }, /* IndianRed1 */ + { 238, 99, 99, 3597 }, /* IndianRed2 */ + { 205, 85, 85, 3608 }, /* IndianRed3 */ + { 139, 58, 58, 3619 }, /* IndianRed4 */ + { 255, 255, 240, 3630 }, /* ivory */ + { 255, 255, 240, 3636 }, /* ivory1 */ + { 238, 238, 224, 3643 }, /* ivory2 */ + { 205, 205, 193, 3650 }, /* ivory3 */ + { 139, 139, 131, 3657 }, /* ivory4 */ + { 240, 230, 140, 3664 }, /* khaki */ + { 255, 246, 143, 3670 }, /* khaki1 */ + { 238, 230, 133, 3677 }, /* khaki2 */ + { 205, 198, 115, 3684 }, /* khaki3 */ + { 139, 134, 78, 3691 }, /* khaki4 */ + { 230, 230, 250, 3698 }, /* lavender */ + { 255, 240, 245, 3707 }, /* lavender blush */ + { 255, 240, 245, 3722 }, /* LavenderBlush */ + { 255, 240, 245, 3736 }, /* LavenderBlush1 */ + { 238, 224, 229, 3751 }, /* LavenderBlush2 */ + { 205, 193, 197, 3766 }, /* LavenderBlush3 */ + { 139, 131, 134, 3781 }, /* LavenderBlush4 */ + { 124, 252, 0, 3796 }, /* lawn green */ + { 124, 252, 0, 3807 }, /* LawnGreen */ + { 255, 250, 205, 3817 }, /* lemon chiffon */ + { 255, 250, 205, 3831 }, /* LemonChiffon */ + { 255, 250, 205, 3844 }, /* LemonChiffon1 */ + { 238, 233, 191, 3858 }, /* LemonChiffon2 */ + { 205, 201, 165, 3872 }, /* LemonChiffon3 */ + { 139, 137, 112, 3886 }, /* LemonChiffon4 */ + { 173, 216, 230, 3900 }, /* light blue */ + { 240, 128, 128, 3911 }, /* light coral */ + { 224, 255, 255, 3923 }, /* light cyan */ + { 238, 221, 130, 3934 }, /* light goldenrod */ + { 250, 250, 210, 3950 }, /* light goldenrod yellow */ + { 211, 211, 211, 3973 }, /* light gray */ + { 144, 238, 144, 3984 }, /* light green */ + { 211, 211, 211, 3996 }, /* light grey */ + { 255, 182, 193, 4007 }, /* light pink */ + { 255, 160, 122, 4018 }, /* light salmon */ + { 32, 178, 170, 4031 }, /* light sea green */ + { 135, 206, 250, 4047 }, /* light sky blue */ + { 132, 112, 255, 4062 }, /* light slate blue */ + { 119, 136, 153, 4079 }, /* light slate gray */ + { 119, 136, 153, 4096 }, /* light slate grey */ + { 176, 196, 222, 4113 }, /* light steel blue */ + { 255, 255, 224, 4130 }, /* light yellow */ + { 173, 216, 230, 4143 }, /* LightBlue */ + { 191, 239, 255, 4153 }, /* LightBlue1 */ + { 178, 223, 238, 4164 }, /* LightBlue2 */ + { 154, 192, 205, 4175 }, /* LightBlue3 */ + { 104, 131, 139, 4186 }, /* LightBlue4 */ + { 240, 128, 128, 4197 }, /* LightCoral */ + { 224, 255, 255, 4208 }, /* LightCyan */ + { 224, 255, 255, 4218 }, /* LightCyan1 */ + { 209, 238, 238, 4229 }, /* LightCyan2 */ + { 180, 205, 205, 4240 }, /* LightCyan3 */ + { 122, 139, 139, 4251 }, /* LightCyan4 */ + { 238, 221, 130, 4262 }, /* LightGoldenrod */ + { 255, 236, 139, 4277 }, /* LightGoldenrod1 */ + { 238, 220, 130, 4293 }, /* LightGoldenrod2 */ + { 205, 190, 112, 4309 }, /* LightGoldenrod3 */ + { 139, 129, 76, 4325 }, /* LightGoldenrod4 */ + { 250, 250, 210, 4341 }, /* LightGoldenrodYellow */ + { 211, 211, 211, 4362 }, /* LightGray */ + { 144, 238, 144, 4372 }, /* LightGreen */ + { 211, 211, 211, 4383 }, /* LightGrey */ + { 255, 182, 193, 4393 }, /* LightPink */ + { 255, 174, 185, 4403 }, /* LightPink1 */ + { 238, 162, 173, 4414 }, /* LightPink2 */ + { 205, 140, 149, 4425 }, /* LightPink3 */ + { 139, 95, 101, 4436 }, /* LightPink4 */ + { 255, 160, 122, 4447 }, /* LightSalmon */ + { 255, 160, 122, 4459 }, /* LightSalmon1 */ + { 238, 149, 114, 4472 }, /* LightSalmon2 */ + { 205, 129, 98, 4485 }, /* LightSalmon3 */ + { 139, 87, 66, 4498 }, /* LightSalmon4 */ + { 32, 178, 170, 4511 }, /* LightSeaGreen */ + { 135, 206, 250, 4525 }, /* LightSkyBlue */ + { 176, 226, 255, 4538 }, /* LightSkyBlue1 */ + { 164, 211, 238, 4552 }, /* LightSkyBlue2 */ + { 141, 182, 205, 4566 }, /* LightSkyBlue3 */ + { 96, 123, 139, 4580 }, /* LightSkyBlue4 */ + { 132, 112, 255, 4594 }, /* LightSlateBlue */ + { 119, 136, 153, 4609 }, /* LightSlateGray */ + { 119, 136, 153, 4624 }, /* LightSlateGrey */ + { 176, 196, 222, 4639 }, /* LightSteelBlue */ + { 202, 225, 255, 4654 }, /* LightSteelBlue1 */ + { 188, 210, 238, 4670 }, /* LightSteelBlue2 */ + { 162, 181, 205, 4686 }, /* LightSteelBlue3 */ + { 110, 123, 139, 4702 }, /* LightSteelBlue4 */ + { 255, 255, 224, 4718 }, /* LightYellow */ + { 255, 255, 224, 4730 }, /* LightYellow1 */ + { 238, 238, 209, 4743 }, /* LightYellow2 */ + { 205, 205, 180, 4756 }, /* LightYellow3 */ + { 139, 139, 122, 4769 }, /* LightYellow4 */ + { 50, 205, 50, 4782 }, /* lime green */ + { 50, 205, 50, 4793 }, /* LimeGreen */ + { 250, 240, 230, 4803 }, /* linen */ + { 255, 0, 255, 4809 }, /* magenta */ + { 255, 0, 255, 4817 }, /* magenta1 */ + { 238, 0, 238, 4826 }, /* magenta2 */ + { 205, 0, 205, 4835 }, /* magenta3 */ + { 139, 0, 139, 4844 }, /* magenta4 */ + { 176, 48, 96, 4853 }, /* maroon */ + { 255, 52, 179, 4860 }, /* maroon1 */ + { 238, 48, 167, 4868 }, /* maroon2 */ + { 205, 41, 144, 4876 }, /* maroon3 */ + { 139, 28, 98, 4884 }, /* maroon4 */ + { 102, 205, 170, 4892 }, /* medium aquamarine */ + { 0, 0, 205, 4910 }, /* medium blue */ + { 186, 85, 211, 4922 }, /* medium orchid */ + { 147, 112, 219, 4936 }, /* medium purple */ + { 60, 179, 113, 4950 }, /* medium sea green */ + { 123, 104, 238, 4967 }, /* medium slate blue */ + { 0, 250, 154, 4985 }, /* medium spring green */ + { 72, 209, 204, 5005 }, /* medium turquoise */ + { 199, 21, 133, 5022 }, /* medium violet red */ + { 102, 205, 170, 5040 }, /* MediumAquamarine */ + { 0, 0, 205, 5057 }, /* MediumBlue */ + { 186, 85, 211, 5068 }, /* MediumOrchid */ + { 224, 102, 255, 5081 }, /* MediumOrchid1 */ + { 209, 95, 238, 5095 }, /* MediumOrchid2 */ + { 180, 82, 205, 5109 }, /* MediumOrchid3 */ + { 122, 55, 139, 5123 }, /* MediumOrchid4 */ + { 147, 112, 219, 5137 }, /* MediumPurple */ + { 171, 130, 255, 5150 }, /* MediumPurple1 */ + { 159, 121, 238, 5164 }, /* MediumPurple2 */ + { 137, 104, 205, 5178 }, /* MediumPurple3 */ + { 93, 71, 139, 5192 }, /* MediumPurple4 */ + { 60, 179, 113, 5206 }, /* MediumSeaGreen */ + { 123, 104, 238, 5221 }, /* MediumSlateBlue */ + { 0, 250, 154, 5237 }, /* MediumSpringGreen */ + { 72, 209, 204, 5255 }, /* MediumTurquoise */ + { 199, 21, 133, 5271 }, /* MediumVioletRed */ + { 25, 25, 112, 5287 }, /* midnight blue */ + { 25, 25, 112, 5301 }, /* MidnightBlue */ + { 245, 255, 250, 5314 }, /* mint cream */ + { 245, 255, 250, 5325 }, /* MintCream */ + { 255, 228, 225, 5335 }, /* misty rose */ + { 255, 228, 225, 5346 }, /* MistyRose */ + { 255, 228, 225, 5356 }, /* MistyRose1 */ + { 238, 213, 210, 5367 }, /* MistyRose2 */ + { 205, 183, 181, 5378 }, /* MistyRose3 */ + { 139, 125, 123, 5389 }, /* MistyRose4 */ + { 255, 228, 181, 5400 }, /* moccasin */ + { 255, 222, 173, 5409 }, /* navajo white */ + { 255, 222, 173, 5422 }, /* NavajoWhite */ + { 255, 222, 173, 5434 }, /* NavajoWhite1 */ + { 238, 207, 161, 5447 }, /* NavajoWhite2 */ + { 205, 179, 139, 5460 }, /* NavajoWhite3 */ + { 139, 121, 94, 5473 }, /* NavajoWhite4 */ + { 0, 0, 128, 5486 }, /* navy */ + { 0, 0, 128, 5491 }, /* navy blue */ + { 0, 0, 128, 5501 }, /* NavyBlue */ + { 253, 245, 230, 5510 }, /* old lace */ + { 253, 245, 230, 5519 }, /* OldLace */ + { 107, 142, 35, 5527 }, /* olive drab */ + { 107, 142, 35, 5538 }, /* OliveDrab */ + { 192, 255, 62, 5548 }, /* OliveDrab1 */ + { 179, 238, 58, 5559 }, /* OliveDrab2 */ + { 154, 205, 50, 5570 }, /* OliveDrab3 */ + { 105, 139, 34, 5581 }, /* OliveDrab4 */ + { 255, 165, 0, 5592 }, /* orange */ + { 255, 69, 0, 5599 }, /* orange red */ + { 255, 165, 0, 5610 }, /* orange1 */ + { 238, 154, 0, 5618 }, /* orange2 */ + { 205, 133, 0, 5626 }, /* orange3 */ + { 139, 90, 0, 5634 }, /* orange4 */ + { 255, 69, 0, 5642 }, /* OrangeRed */ + { 255, 69, 0, 5652 }, /* OrangeRed1 */ + { 238, 64, 0, 5663 }, /* OrangeRed2 */ + { 205, 55, 0, 5674 }, /* OrangeRed3 */ + { 139, 37, 0, 5685 }, /* OrangeRed4 */ + { 218, 112, 214, 5696 }, /* orchid */ + { 255, 131, 250, 5703 }, /* orchid1 */ + { 238, 122, 233, 5711 }, /* orchid2 */ + { 205, 105, 201, 5719 }, /* orchid3 */ + { 139, 71, 137, 5727 }, /* orchid4 */ + { 238, 232, 170, 5735 }, /* pale goldenrod */ + { 152, 251, 152, 5750 }, /* pale green */ + { 175, 238, 238, 5761 }, /* pale turquoise */ + { 219, 112, 147, 5776 }, /* pale violet red */ + { 238, 232, 170, 5792 }, /* PaleGoldenrod */ + { 152, 251, 152, 5806 }, /* PaleGreen */ + { 154, 255, 154, 5816 }, /* PaleGreen1 */ + { 144, 238, 144, 5827 }, /* PaleGreen2 */ + { 124, 205, 124, 5838 }, /* PaleGreen3 */ + { 84, 139, 84, 5849 }, /* PaleGreen4 */ + { 175, 238, 238, 5860 }, /* PaleTurquoise */ + { 187, 255, 255, 5874 }, /* PaleTurquoise1 */ + { 174, 238, 238, 5889 }, /* PaleTurquoise2 */ + { 150, 205, 205, 5904 }, /* PaleTurquoise3 */ + { 102, 139, 139, 5919 }, /* PaleTurquoise4 */ + { 219, 112, 147, 5934 }, /* PaleVioletRed */ + { 255, 130, 171, 5948 }, /* PaleVioletRed1 */ + { 238, 121, 159, 5963 }, /* PaleVioletRed2 */ + { 205, 104, 137, 5978 }, /* PaleVioletRed3 */ + { 139, 71, 93, 5993 }, /* PaleVioletRed4 */ + { 255, 239, 213, 6008 }, /* papaya whip */ + { 255, 239, 213, 6020 }, /* PapayaWhip */ + { 255, 218, 185, 6031 }, /* peach puff */ + { 255, 218, 185, 6042 }, /* PeachPuff */ + { 255, 218, 185, 6052 }, /* PeachPuff1 */ + { 238, 203, 173, 6063 }, /* PeachPuff2 */ + { 205, 175, 149, 6074 }, /* PeachPuff3 */ + { 139, 119, 101, 6085 }, /* PeachPuff4 */ + { 205, 133, 63, 6096 }, /* peru */ + { 255, 192, 203, 6101 }, /* pink */ + { 255, 181, 197, 6106 }, /* pink1 */ + { 238, 169, 184, 6112 }, /* pink2 */ + { 205, 145, 158, 6118 }, /* pink3 */ + { 139, 99, 108, 6124 }, /* pink4 */ + { 221, 160, 221, 6130 }, /* plum */ + { 255, 187, 255, 6135 }, /* plum1 */ + { 238, 174, 238, 6141 }, /* plum2 */ + { 205, 150, 205, 6147 }, /* plum3 */ + { 139, 102, 139, 6153 }, /* plum4 */ + { 176, 224, 230, 6159 }, /* powder blue */ + { 176, 224, 230, 6171 }, /* PowderBlue */ + { 160, 32, 240, 6182 }, /* purple */ + { 155, 48, 255, 6189 }, /* purple1 */ + { 145, 44, 238, 6197 }, /* purple2 */ + { 125, 38, 205, 6205 }, /* purple3 */ + { 85, 26, 139, 6213 }, /* purple4 */ + { 255, 0, 0, 6221 }, /* red */ + { 255, 0, 0, 6225 }, /* red1 */ + { 238, 0, 0, 6230 }, /* red2 */ + { 205, 0, 0, 6235 }, /* red3 */ + { 139, 0, 0, 6240 }, /* red4 */ + { 188, 143, 143, 6245 }, /* rosy brown */ + { 188, 143, 143, 6256 }, /* RosyBrown */ + { 255, 193, 193, 6266 }, /* RosyBrown1 */ + { 238, 180, 180, 6277 }, /* RosyBrown2 */ + { 205, 155, 155, 6288 }, /* RosyBrown3 */ + { 139, 105, 105, 6299 }, /* RosyBrown4 */ + { 65, 105, 225, 6310 }, /* royal blue */ + { 65, 105, 225, 6321 }, /* RoyalBlue */ + { 72, 118, 255, 6331 }, /* RoyalBlue1 */ + { 67, 110, 238, 6342 }, /* RoyalBlue2 */ + { 58, 95, 205, 6353 }, /* RoyalBlue3 */ + { 39, 64, 139, 6364 }, /* RoyalBlue4 */ + { 139, 69, 19, 6375 }, /* saddle brown */ + { 139, 69, 19, 6388 }, /* SaddleBrown */ + { 250, 128, 114, 6400 }, /* salmon */ + { 255, 140, 105, 6407 }, /* salmon1 */ + { 238, 130, 98, 6415 }, /* salmon2 */ + { 205, 112, 84, 6423 }, /* salmon3 */ + { 139, 76, 57, 6431 }, /* salmon4 */ + { 244, 164, 96, 6439 }, /* sandy brown */ + { 244, 164, 96, 6451 }, /* SandyBrown */ + { 46, 139, 87, 6462 }, /* sea green */ + { 46, 139, 87, 6472 }, /* SeaGreen */ + { 84, 255, 159, 6481 }, /* SeaGreen1 */ + { 78, 238, 148, 6491 }, /* SeaGreen2 */ + { 67, 205, 128, 6501 }, /* SeaGreen3 */ + { 46, 139, 87, 6511 }, /* SeaGreen4 */ + { 255, 245, 238, 6521 }, /* seashell */ + { 255, 245, 238, 6530 }, /* seashell1 */ + { 238, 229, 222, 6540 }, /* seashell2 */ + { 205, 197, 191, 6550 }, /* seashell3 */ + { 139, 134, 130, 6560 }, /* seashell4 */ + { 160, 82, 45, 6570 }, /* sienna */ + { 255, 130, 71, 6577 }, /* sienna1 */ + { 238, 121, 66, 6585 }, /* sienna2 */ + { 205, 104, 57, 6593 }, /* sienna3 */ + { 139, 71, 38, 6601 }, /* sienna4 */ + { 135, 206, 235, 6609 }, /* sky blue */ + { 135, 206, 235, 6618 }, /* SkyBlue */ + { 135, 206, 255, 6626 }, /* SkyBlue1 */ + { 126, 192, 238, 6635 }, /* SkyBlue2 */ + { 108, 166, 205, 6644 }, /* SkyBlue3 */ + { 74, 112, 139, 6653 }, /* SkyBlue4 */ + { 106, 90, 205, 6662 }, /* slate blue */ + { 112, 128, 144, 6673 }, /* slate gray */ + { 112, 128, 144, 6684 }, /* slate grey */ + { 106, 90, 205, 6695 }, /* SlateBlue */ + { 131, 111, 255, 6705 }, /* SlateBlue1 */ + { 122, 103, 238, 6716 }, /* SlateBlue2 */ + { 105, 89, 205, 6727 }, /* SlateBlue3 */ + { 71, 60, 139, 6738 }, /* SlateBlue4 */ + { 112, 128, 144, 6749 }, /* SlateGray */ + { 198, 226, 255, 6759 }, /* SlateGray1 */ + { 185, 211, 238, 6770 }, /* SlateGray2 */ + { 159, 182, 205, 6781 }, /* SlateGray3 */ + { 108, 123, 139, 6792 }, /* SlateGray4 */ + { 112, 128, 144, 6803 }, /* SlateGrey */ + { 255, 250, 250, 6813 }, /* snow */ + { 255, 250, 250, 6818 }, /* snow1 */ + { 238, 233, 233, 6824 }, /* snow2 */ + { 205, 201, 201, 6830 }, /* snow3 */ + { 139, 137, 137, 6836 }, /* snow4 */ + { 0, 255, 127, 6842 }, /* spring green */ + { 0, 255, 127, 6855 }, /* SpringGreen */ + { 0, 255, 127, 6867 }, /* SpringGreen1 */ + { 0, 238, 118, 6880 }, /* SpringGreen2 */ + { 0, 205, 102, 6893 }, /* SpringGreen3 */ + { 0, 139, 69, 6906 }, /* SpringGreen4 */ + { 70, 130, 180, 6919 }, /* steel blue */ + { 70, 130, 180, 6930 }, /* SteelBlue */ + { 99, 184, 255, 6940 }, /* SteelBlue1 */ + { 92, 172, 238, 6951 }, /* SteelBlue2 */ + { 79, 148, 205, 6962 }, /* SteelBlue3 */ + { 54, 100, 139, 6973 }, /* SteelBlue4 */ + { 210, 180, 140, 6984 }, /* tan */ + { 255, 165, 79, 6988 }, /* tan1 */ + { 238, 154, 73, 6993 }, /* tan2 */ + { 205, 133, 63, 6998 }, /* tan3 */ + { 139, 90, 43, 7003 }, /* tan4 */ + { 216, 191, 216, 7008 }, /* thistle */ + { 255, 225, 255, 7016 }, /* thistle1 */ + { 238, 210, 238, 7025 }, /* thistle2 */ + { 205, 181, 205, 7034 }, /* thistle3 */ + { 139, 123, 139, 7043 }, /* thistle4 */ + { 255, 99, 71, 7052 }, /* tomato */ + { 255, 99, 71, 7059 }, /* tomato1 */ + { 238, 92, 66, 7067 }, /* tomato2 */ + { 205, 79, 57, 7075 }, /* tomato3 */ + { 139, 54, 38, 7083 }, /* tomato4 */ + { 64, 224, 208, 7091 }, /* turquoise */ + { 0, 245, 255, 7101 }, /* turquoise1 */ + { 0, 229, 238, 7112 }, /* turquoise2 */ + { 0, 197, 205, 7123 }, /* turquoise3 */ + { 0, 134, 139, 7134 }, /* turquoise4 */ + { 238, 130, 238, 7145 }, /* violet */ + { 208, 32, 144, 7152 }, /* violet red */ + { 208, 32, 144, 7163 }, /* VioletRed */ + { 255, 62, 150, 7173 }, /* VioletRed1 */ + { 238, 58, 140, 7184 }, /* VioletRed2 */ + { 205, 50, 120, 7195 }, /* VioletRed3 */ + { 139, 34, 82, 7206 }, /* VioletRed4 */ + { 245, 222, 179, 7217 }, /* wheat */ + { 255, 231, 186, 7223 }, /* wheat1 */ + { 238, 216, 174, 7230 }, /* wheat2 */ + { 205, 186, 150, 7237 }, /* wheat3 */ + { 139, 126, 102, 7244 }, /* wheat4 */ + { 255, 255, 255, 7251 }, /* white */ + { 245, 245, 245, 7257 }, /* white smoke */ + { 245, 245, 245, 7269 }, /* WhiteSmoke */ + { 255, 255, 0, 7280 }, /* yellow */ + { 154, 205, 50, 7287 }, /* yellow green */ + { 255, 255, 0, 7300 }, /* yellow1 */ + { 238, 238, 0, 7308 }, /* yellow2 */ + { 205, 205, 0, 7316 }, /* yellow3 */ + { 139, 139, 0, 7324 }, /* yellow4 */ + { 154, 205, 50, 7332 }, /* YellowGreen */ +}; Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/osdep.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/osdep.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/osdep.h (revision 51223) @@ -0,0 +1,360 @@ +/* $XFree86: xc/programs/Xserver/os/osdep.h,v 3.17 2002/05/31 18:46:06 dawes Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: osdep.h,v 1.5 2001/02/09 02:05:23 xorgcvs Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _OSDEP_H_ +#define _OSDEP_H_ 1 + +#define BOTIMEOUT 200 /* in milliseconds */ +#define BUFSIZE 4096 +#define BUFWATERMARK 8192 +#ifndef MAXBUFSIZE +#define MAXBUFSIZE (1 << 22) +#endif + +#include + +#ifndef sgi /* SGI defines OPEN_MAX in a useless way */ +#ifndef X_NOT_POSIX +#ifdef _POSIX_SOURCE +#include +#else +#define _POSIX_SOURCE +#include +#undef _POSIX_SOURCE +#endif +#else /* X_NOT_POSIX */ +#ifdef WIN32 +#define _POSIX_ +#include +#undef _POSIX_ +#endif +#endif /* X_NOT_POSIX */ +#endif + +#ifdef __QNX__ +#define NOFILES_MAX 256 +#endif +#ifndef OPEN_MAX +#ifdef SVR4 +#define OPEN_MAX 256 +#else +#include +#ifndef OPEN_MAX +#if defined(NOFILE) && !defined(NOFILES_MAX) +#define OPEN_MAX NOFILE +#else +#if !defined(__UNIXOS2__) && !defined(WIN32) +#define OPEN_MAX NOFILES_MAX +#else +#define OPEN_MAX 256 +#endif +#endif +#endif +#endif +#endif + +#include + +/* + * MAXSOCKS is used only for initialising MaxClients when no other method + * like sysconf(_SC_OPEN_MAX) is not supported. + */ + +#if OPEN_MAX <= 256 +#define MAXSOCKS (OPEN_MAX - 1) +#else +#define MAXSOCKS 256 +#endif + +/* MAXSELECT is the number of fds that select() can handle */ +#define MAXSELECT (sizeof(fd_set) * NBBY) + +#ifndef HAS_GETDTABLESIZE +#if !defined(hpux) && !defined(SVR4) && !defined(SYSV) +#define HAS_GETDTABLESIZE +#endif +#endif + +#include + +typedef Bool (*ValidatorFunc)(ARRAY8Ptr Auth, ARRAY8Ptr Data, int packet_type); +typedef Bool (*GeneratorFunc)(ARRAY8Ptr Auth, ARRAY8Ptr Data, int packet_type); +typedef Bool (*AddAuthorFunc)(unsigned name_length, char *name, unsigned data_length, char *data); + +typedef struct _connectionInput { + struct _connectionInput *next; + char *buffer; /* contains current client input */ + char *bufptr; /* pointer to current start of data */ + int bufcnt; /* count of bytes in buffer */ + int lenLastReq; + int size; +} ConnectionInput, *ConnectionInputPtr; + +typedef struct _connectionOutput { + struct _connectionOutput *next; + int size; + unsigned char *buf; + int count; +#ifdef LBX + Bool nocompress; +#endif +} ConnectionOutput, *ConnectionOutputPtr; + +#ifdef K5AUTH +typedef struct _k5_state { + int stageno; /* current stage of auth protocol */ + pointer srvcreds; /* server credentials */ + pointer srvname; /* server principal name */ + pointer ktname; /* key table: principal-key pairs */ + pointer skey; /* session key */ +} k5_state; +#endif + +#ifdef LBX +typedef struct _LbxProxy *OsProxyPtr; +#endif + +struct _osComm; + +#define AuthInitArgs void +typedef void (*AuthInitFunc) (AuthInitArgs); + +#define AuthAddCArgs unsigned short data_length, char *data, XID id +typedef int (*AuthAddCFunc) (AuthAddCArgs); + +#define AuthCheckArgs unsigned short data_length, char *data, ClientPtr client, char **reason +typedef XID (*AuthCheckFunc) (AuthCheckArgs); + +#define AuthFromIDArgs XID id, unsigned short *data_lenp, char **datap +typedef int (*AuthFromIDFunc) (AuthFromIDArgs); + +#define AuthGenCArgs unsigned data_length, char *data, XID id, unsigned *data_length_return, char **data_return +typedef XID (*AuthGenCFunc) (AuthGenCArgs); + +#define AuthRemCArgs unsigned short data_length, char *data +typedef int (*AuthRemCFunc) (AuthRemCArgs); + +#define AuthRstCArgs void +typedef int (*AuthRstCFunc) (AuthRstCArgs); + +#define AuthToIDArgs unsigned short data_length, char *data +typedef XID (*AuthToIDFunc) (AuthToIDArgs); + +typedef void (*OsCloseFunc)(ClientPtr); + +typedef int (*OsFlushFunc)(ClientPtr who, struct _osComm * oc, char* extraBuf, int extraCount); + +typedef struct _osComm { + int fd; + ConnectionInputPtr input; + ConnectionOutputPtr output; + XID auth_id; /* authorization id */ +#ifdef K5AUTH + k5_state authstate; /* state of setup auth conversation */ +#endif + CARD32 conn_time; /* timestamp if not established, else 0 */ + struct _XtransConnInfo *trans_conn; /* transport connection object */ +#ifdef LBX + OsProxyPtr proxy; + ConnectionInputPtr largereq; + OsCloseFunc Close; + OsFlushFunc Flush; +#endif +} OsCommRec, *OsCommPtr; + +#ifdef LBX +#define FlushClient(who, oc, extraBuf, extraCount) \ + (*(oc)->Flush)(who, oc, extraBuf, extraCount) +extern int StandardFlushClient( + ClientPtr /*who*/, + OsCommPtr /*oc*/, + char* /*extraBuf*/, + int /*extraCount*/ +); +extern int LbxFlushClient(ClientPtr /*who*/, OsCommPtr /*oc*/, + char * /*extraBuf*/, int /*extraCount*/); +#else +extern int FlushClient( + ClientPtr /*who*/, + OsCommPtr /*oc*/, + char* /*extraBuf*/, + int /*extraCount*/ +); +#endif + +extern void FreeOsBuffers( + OsCommPtr /*oc*/ +); + +#include "dix.h" + +extern ConnectionInputPtr AllocateInputBuffer(void); + +extern ConnectionOutputPtr AllocateOutputBuffer(void); + +extern fd_set AllSockets; +extern fd_set AllClients; +extern fd_set LastSelectMask; +extern fd_set WellKnownConnections; +extern fd_set EnabledDevices; +extern fd_set ClientsWithInput; +extern fd_set ClientsWriteBlocked; +extern fd_set OutputPending; +extern fd_set IgnoredClientsWithInput; + +#ifndef WIN32 +extern int *ConnectionTranslation; +#else +extern int GetConnectionTranslation(int conn); +extern void SetConnectionTranslation(int conn, int client); +extern void ClearConnectionTranslation(); +#endif + +extern Bool NewOutputPending; +extern Bool AnyClientsWriteBlocked; +extern Bool CriticalOutputPending; + +extern int timesThisConnection; +extern ConnectionInputPtr FreeInputs; +extern ConnectionOutputPtr FreeOutputs; +extern OsCommPtr AvailableInput; + +extern WorkQueuePtr workQueue; + +/* added by raphael */ +#ifdef WIN32 +typedef long int fd_mask; +#endif +#define ffs mffs +extern int mffs(fd_mask); + +/* in auth.c */ +extern void GenerateRandomData (int len, char *buf); + +/* in mitauth.c */ +extern XID MitCheckCookie (AuthCheckArgs); +extern XID MitGenerateCookie (AuthGenCArgs); +extern XID MitToID (AuthToIDArgs); +extern int MitAddCookie (AuthAddCArgs); +extern int MitFromID (AuthFromIDArgs); +extern int MitRemoveCookie (AuthRemCArgs); +extern int MitResetCookie (AuthRstCArgs); + +/* in xdmauth.c */ +#ifdef HASXDMAUTH +extern XID XdmCheckCookie (AuthCheckArgs); +extern XID XdmToID (AuthToIDArgs); +extern int XdmAddCookie (AuthAddCArgs); +extern int XdmFromID (AuthFromIDArgs); +extern int XdmRemoveCookie (AuthRemCArgs); +extern int XdmResetCookie (AuthRstCArgs); +#endif + +/* in rpcauth.c */ +#ifdef SECURE_RPC +extern void SecureRPCInit (AuthInitArgs); +extern XID SecureRPCCheck (AuthCheckArgs); +extern XID SecureRPCToID (AuthToIDArgs); +extern int SecureRPCAdd (AuthAddCArgs); +extern int SecureRPCFromID (AuthFromIDArgs); +extern int SecureRPCRemove (AuthRemCArgs); +extern int SecureRPCReset (AuthRstCArgs); +#endif + +/* in k5auth.c */ +#ifdef K5AUTH +extern XID K5Check (AuthCheckArgs); +extern XID K5ToID (AuthToIDArgs); +extern int K5Add (AuthAddCArgs); +extern int K5FromID (AuthFromIDArgs); +extern int K5Remove (AuthRemCArgs); +extern int K5Reset (AuthRstCArgs); +#endif + +/* in secauth.c */ +extern XID AuthSecurityCheck (AuthCheckArgs); + +/* in xdmcp.c */ +extern void XdmcpUseMsg (void); +extern int XdmcpOptions(int argc, char **argv, int i); +extern void XdmcpSetAuthentication (ARRAY8Ptr name); +extern void XdmcpRegisterConnection ( + int type, + char *address, + int addrlen); +extern void XdmcpRegisterAuthorizations (void); +extern void XdmcpRegisterAuthorization (char *name, int namelen); +extern void XdmcpRegisterDisplayClass (char *name, int length); +extern void XdmcpInit (void); +extern void XdmcpReset (void); +extern void XdmcpOpenDisplay(int sock); +extern void XdmcpCloseDisplay(int sock); +extern void XdmcpRegisterAuthentication ( + char *name, + int namelen, + char *data, + int datalen, + ValidatorFunc Validator, + GeneratorFunc Generator, + AddAuthorFunc AddAuth); +extern int XdmcpCheckAuthentication (ARRAY8Ptr Name, ARRAY8Ptr Data, int packet_type); +extern int XdmcpAddAuthorization (ARRAY8Ptr name, ARRAY8Ptr data); + +struct sockaddr_in; +extern void XdmcpRegisterBroadcastAddress (struct sockaddr_in *addr); + +#ifdef HASXDMAUTH +extern void XdmAuthenticationInit (char *cookie, int cookie_length); +#endif + +#endif /* _OSDEP_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiX.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiX.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiX.h (revision 51223) @@ -0,0 +1,115 @@ +/* $TOG: panoramiX.h /main/4 1998/03/17 06:51:02 kaleb $ */ +/* $XdotOrg: xserver/xorg/Xext/panoramiX.h,v 1.5 2005/07/03 07:01:04 daniels Exp $ */ +/***************************************************************** + +Copyright (c) 1991, 1997 Digital Equipment Corporation, Maynard, Massachusetts. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +DIGITAL EQUIPMENT CORPORATION BE LIABLE FOR ANY CLAIM, DAMAGES, INCLUDING, +BUT NOT LIMITED TO CONSEQUENTIAL OR INCIDENTAL DAMAGES, OR OTHER LIABILITY, +WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of Digital Equipment Corporation +shall not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from Digital +Equipment Corporation. + +******************************************************************/ + +/* $XFree86: xc/programs/Xserver/Xext/panoramiX.h,v 1.5 2001/01/03 02:54:17 keithp Exp $ */ + +/* THIS IS NOT AN X PROJECT TEAM SPECIFICATION */ + +/* + * PanoramiX definitions + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PANORAMIX_H_ +#define _PANORAMIX_H_ + +#include +#include "gcstruct.h" + + +typedef struct _PanoramiXData { + int x; + int y; + int width; + int height; +} PanoramiXData; + +typedef struct _PanoramiXInfo { + XID id ; +} PanoramiXInfo; + +typedef struct { + PanoramiXInfo info[MAXSCREENS]; + RESTYPE type; + union { + struct { + char visibility; + char class; + char root; + } win; + struct { + Bool shared; + } pix; +#ifdef RENDER + struct { + Bool root; + } pict; +#endif + char raw_data[4]; + } u; +} PanoramiXRes; + +#define FOR_NSCREENS_FORWARD(j) for(j = 0; j < PanoramiXNumScreens; j++) +#define FOR_NSCREENS_BACKWARD(j) for(j = PanoramiXNumScreens - 1; j >= 0; j--) +#define FOR_NSCREENS(j) FOR_NSCREENS_FORWARD(j) + +#define BREAK_IF(a) if ((a)) break +#define IF_RETURN(a,b) if ((a)) return (b) + +#define FORCE_ROOT(a) { \ + int _j; \ + for (_j = PanoramiXNumScreens - 1; _j; _j--) \ + if ((a).root == WindowTable[_j]->drawable.id) \ + break; \ + (a).rootX += panoramiXdataPtr[_j].x; \ + (a).rootY += panoramiXdataPtr[_j].y; \ + (a).root = WindowTable[0]->drawable.id; \ +} + +#define FORCE_WIN(a) { \ + if ((win = PanoramiXFindIDOnAnyScreen(XRT_WINDOW, a))) { \ + (a) = win->info[0].id; /* Real ID */ \ + } \ +} + +#define FORCE_CMAP(a) { \ + if ((win = PanoramiXFindIDOnAnyScreen(XRT_COLORMAP, a))) { \ + (a) = win->info[0].id; /* Real ID */ \ + } \ +} + +#define IS_SHARED_PIXMAP(r) (((r)->type == XRT_PIXMAP) && (r)->u.pix.shared) + +#define SKIP_FAKE_WINDOW(a) if(!LookupIDByType(a, XRT_WINDOW)) return + +#endif /* _PANORAMIX_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXh.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXh.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXh.h (revision 51223) @@ -0,0 +1,78 @@ +/* $XFree86: xc/programs/Xserver/Xext/panoramiXh.h,v 1.2 2003/09/13 21:33:03 dawes Exp $ */ + +/* + * Server dispatcher function replacements + */ + +extern int PanoramiXCreateWindow(ClientPtr client); +extern int PanoramiXChangeWindowAttributes(ClientPtr client); +extern int PanoramiXDestroyWindow(ClientPtr client); +extern int PanoramiXDestroySubwindows(ClientPtr client); +extern int PanoramiXChangeSaveSet(ClientPtr client); +extern int PanoramiXReparentWindow(ClientPtr client); +extern int PanoramiXMapWindow(ClientPtr client); +extern int PanoramiXMapSubwindows(ClientPtr client); +extern int PanoramiXUnmapWindow(ClientPtr client); +extern int PanoramiXUnmapSubwindows(ClientPtr client); +extern int PanoramiXConfigureWindow(ClientPtr client); +extern int PanoramiXCirculateWindow(ClientPtr client); +extern int PanoramiXGetGeometry(ClientPtr client); +extern int PanoramiXTranslateCoords(ClientPtr client); +extern int PanoramiXCreatePixmap(ClientPtr client); +extern int PanoramiXFreePixmap(ClientPtr client); +extern int PanoramiXCreateGC(ClientPtr client); +extern int PanoramiXChangeGC(ClientPtr client); +extern int PanoramiXCopyGC(ClientPtr client); +extern int PanoramiXCopyColormapAndFree(ClientPtr client); +extern int PanoramiXSetDashes(ClientPtr client); +extern int PanoramiXSetClipRectangles(ClientPtr client); +extern int PanoramiXFreeGC(ClientPtr client); +extern int PanoramiXClearToBackground(ClientPtr client); +extern int PanoramiXCopyArea(ClientPtr client); +extern int PanoramiXCopyPlane(ClientPtr client); +extern int PanoramiXPolyPoint(ClientPtr client); +extern int PanoramiXPolyLine(ClientPtr client); +extern int PanoramiXPolySegment(ClientPtr client); +extern int PanoramiXPolyRectangle(ClientPtr client); +extern int PanoramiXPolyArc(ClientPtr client); +extern int PanoramiXFillPoly(ClientPtr client); +extern int PanoramiXPolyFillArc(ClientPtr client); +extern int PanoramiXPolyFillRectangle(ClientPtr client); +extern int PanoramiXPutImage(ClientPtr client); +extern int PanoramiXGetImage(ClientPtr client); +extern int PanoramiXPolyText8(ClientPtr client); +extern int PanoramiXPolyText16(ClientPtr client); +extern int PanoramiXImageText8(ClientPtr client); +extern int PanoramiXImageText16(ClientPtr client); +extern int PanoramiXCreateColormap(ClientPtr client); +extern int PanoramiXFreeColormap(ClientPtr client); +extern int PanoramiXInstallColormap(ClientPtr client); +extern int PanoramiXUninstallColormap(ClientPtr client); +extern int PanoramiXAllocColor(ClientPtr client); +extern int PanoramiXAllocNamedColor(ClientPtr client); +extern int PanoramiXAllocColorCells(ClientPtr client); +extern int PanoramiXStoreNamedColor(ClientPtr client); +extern int PanoramiXFreeColors(ClientPtr client); +extern int PanoramiXStoreColors(ClientPtr client); +extern int PanoramiXAllocColorPlanes(ClientPtr client); + +#define PROC_EXTERN(pfunc) extern int pfunc(ClientPtr) + +PROC_EXTERN(ProcPanoramiXQueryVersion); +PROC_EXTERN(ProcPanoramiXGetState); +PROC_EXTERN(ProcPanoramiXGetScreenCount); +PROC_EXTERN(ProcPanoramiXGetScreenSize); + +PROC_EXTERN(ProcXineramaQueryScreens); +PROC_EXTERN(ProcXineramaIsActive); +extern Bool XineramaCreateGC(GCPtr pGC); + +extern int SProcPanoramiXDispatch(ClientPtr client); + +extern char *ConnectionInfo; +extern int connBlockScreenStart; +extern xConnSetupPrefix connSetupPrefix; + +extern ScreenInfo *GlobalScrInfo; +extern int (* SavedProcVector[256]) (ClientPtr client); + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXsrv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXsrv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/panoramiXsrv.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86: xc/programs/Xserver/Xext/panoramiXsrv.h,v 1.8 2001/08/01 00:44:44 tsi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _PANORAMIXSRV_H_ +#define _PANORAMIXSRV_H_ + +#include "panoramiX.h" + +extern int PanoramiXNumScreens; +extern PanoramiXData *panoramiXdataPtr; +extern int PanoramiXPixWidth; +extern int PanoramiXPixHeight; +extern RegionRec PanoramiXScreenRegion; +extern XID *PanoramiXVisualTable; + +extern void PanoramiXConsolidate(void); +extern Bool PanoramiXCreateConnectionBlock(void); +extern PanoramiXRes * PanoramiXFindIDByScrnum(RESTYPE, XID, int); +extern PanoramiXRes * PanoramiXFindIDOnAnyScreen(RESTYPE, XID); +extern WindowPtr PanoramiXChangeWindow(int, WindowPtr); +extern Bool XineramaRegisterConnectionBlockCallback(void (*func)(void)); +extern int XineramaDeleteResource(pointer, XID); + +extern void XineramaReinitData(ScreenPtr); + +extern RegionRec XineramaScreenRegions[MAXSCREENS]; + +extern unsigned long XRC_DRAWABLE; +extern unsigned long XRT_WINDOW; +extern unsigned long XRT_PIXMAP; +extern unsigned long XRT_GC; +extern unsigned long XRT_COLORMAP; + +extern void XineramaGetImageData( + DrawablePtr *pDrawables, + int left, + int top, + int width, + int height, + unsigned int format, + unsigned long planemask, + char *data, + int pitch, + Bool isRoot +); + +#endif /* _PANORAMIXSRV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/parser.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/parser.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/parser.h (revision 51223) @@ -0,0 +1,89 @@ +/* A Bison parser, made by GNU Bison 2.1. */ + +/* Skeleton parser for Yacc-like parsing with Bison, + Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* As a special exception, when this file is copied by Bison into a + Bison output file, you may use that output file without restriction. + This special exception was added by the Free Software Foundation + in version 1.24 of Bison. */ + +/* Tokens. */ +#ifndef YYTOKENTYPE +# define YYTOKENTYPE + /* Put the tokens into the symbol table, so that GDB and other debuggers + know about them. */ + enum yytokentype { + T_VIRTUAL = 258, + T_DISPLAY = 259, + T_WALL = 260, + T_OPTION = 261, + T_PARAM = 262, + T_STRING = 263, + T_DIMENSION = 264, + T_OFFSET = 265, + T_ORIGIN = 266, + T_COMMENT = 267, + T_LINE_COMMENT = 268 + }; +#endif +/* Tokens. */ +#define T_VIRTUAL 258 +#define T_DISPLAY 259 +#define T_WALL 260 +#define T_OPTION 261 +#define T_PARAM 262 +#define T_STRING 263 +#define T_DIMENSION 264 +#define T_OFFSET 265 +#define T_ORIGIN 266 +#define T_COMMENT 267 +#define T_LINE_COMMENT 268 + + + + +#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED) +#line 56 "parser.y" +typedef union YYSTYPE { + DMXConfigTokenPtr token; + DMXConfigStringPtr string; + DMXConfigNumberPtr number; + DMXConfigPairPtr pair; + DMXConfigFullDimPtr fdim; + DMXConfigPartDimPtr pdim; + DMXConfigDisplayPtr display; + DMXConfigWallPtr wall; + DMXConfigOptionPtr option; + DMXConfigParamPtr param; + DMXConfigCommentPtr comment; + DMXConfigSubPtr subentry; + DMXConfigVirtualPtr virtual; + DMXConfigEntryPtr entry; +} YYSTYPE; +/* Line 1447 of yacc.c. */ +#line 81 "parser.h" +# define yystype YYSTYPE /* obsolescent; will be withdrawn */ +# define YYSTYPE_IS_DECLARED 1 +# define YYSTYPE_IS_TRIVIAL 1 +#endif + +extern YYSTYPE yylval; + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picture.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picture.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picture.h (revision 51223) @@ -0,0 +1,247 @@ +/* + * $XFree86: xc/programs/Xserver/render/picture.h,v 1.20tsi Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _PICTURE_H_ +#define _PICTURE_H_ + +typedef struct _DirectFormat *DirectFormatPtr; +typedef struct _PictFormat *PictFormatPtr; +typedef struct _Picture *PicturePtr; + +/* + * While the protocol is generous in format support, the + * sample implementation allows only packed RGB and GBR + * representations for data to simplify software rendering, + */ +#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \ + ((type) << 16) | \ + ((a) << 12) | \ + ((r) << 8) | \ + ((g) << 4) | \ + ((b))) + +/* + * gray/color formats use a visual index instead of argb + */ +#define PICT_VISFORMAT(bpp,type,vi) (((bpp) << 24) | \ + ((type) << 16) | \ + ((vi))) + +#define PICT_FORMAT_BPP(f) (((f) >> 24) ) +#define PICT_FORMAT_TYPE(f) (((f) >> 16) & 0xff) +#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f) +#define PICT_FORMAT_R(f) (((f) >> 8) & 0x0f) +#define PICT_FORMAT_G(f) (((f) >> 4) & 0x0f) +#define PICT_FORMAT_B(f) (((f) ) & 0x0f) +#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) +#define PICT_FORMAT_VIS(f) (((f) ) & 0xffff) + +#define PICT_TYPE_OTHER 0 +#define PICT_TYPE_A 1 +#define PICT_TYPE_ARGB 2 +#define PICT_TYPE_ABGR 3 +#define PICT_TYPE_COLOR 4 +#define PICT_TYPE_GRAY 5 + +#define PICT_FORMAT_COLOR(f) (PICT_FORMAT_TYPE(f) & 2) + +/* 32bpp formats */ +#define PICT_a8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8) +#define PICT_x8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_a8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8) +#define PICT_x8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8) + +/* 24bpp formats */ +#define PICT_r8g8b8 PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_b8g8r8 PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8) + +/* 16bpp formats */ +#define PICT_r5g6b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5) +#define PICT_b5g6r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5) + +#define PICT_a1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5) +#define PICT_x1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5) +#define PICT_a1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5) +#define PICT_x1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5) +#define PICT_a4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +#define PICT_x4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4) +#define PICT_a4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4) +#define PICT_x4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4) + +/* 8bpp formats */ +#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0) +#define PICT_r3g3b2 PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2) +#define PICT_b2g3r3 PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2) +#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2) +#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2) + +#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0) + +#define PICT_x4a4 PICT_FORMAT(8,PICT_TYPE_A,4,0,0,0) +#define PICT_x4r1g2b1 PICT_FORMAT(8,PICT_TYPE_ARGB,0,1,2,1) +#define PICT_x4b1g2r1 PICT_FORMAT(8,PICT_TYPE_ABGR,0,1,2,1) +#define PICT_x4a1r1g1b1 PICT_FORMAT(8,PICT_TYPE_ARGB,1,1,1,1) +#define PICT_x4a1b1g1r1 PICT_FORMAT(8,PICT_TYPE_ABGR,1,1,1,1) + +#define PICT_x4c4 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_x4g4 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0) + +/* 4bpp formats */ +#define PICT_a4 PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0) +#define PICT_r1g2b1 PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1) +#define PICT_b1g2r1 PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1) +#define PICT_a1r1g1b1 PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1) +#define PICT_a1b1g1r1 PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1) + +#define PICT_c4 PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_g4 PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0) + +/* 1bpp formats */ +#define PICT_a1 PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0) + +#define PICT_g1 PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0) + +/* + * For dynamic indexed visuals (GrayScale and PseudoColor), these control the + * selection of colors allocated for drawing to Pictures. The default + * policy depends on the size of the colormap: + * + * Size Default Policy + * ---------------------------- + * < 64 PolicyMono + * < 256 PolicyGray + * 256 PolicyColor (only on PseudoColor) + * + * The actual allocation code lives in miindex.c, and so is + * austensibly server dependent, but that code does: + * + * PolicyMono Allocate no additional colors, use black and white + * PolicyGray Allocate 13 gray levels (11 cells used) + * PolicyColor Allocate a 4x4x4 cube and 13 gray levels (71 cells used) + * PolicyAll Allocate as big a cube as possible, fill with gray (all) + * + * Here's a picture to help understand how many colors are + * actually allocated (this is just the gray ramp): + * + * gray level + * all 0000 1555 2aaa 4000 5555 6aaa 8000 9555 aaaa bfff d555 eaaa ffff + * b/w 0000 ffff + * 4x4x4 5555 aaaa + * extra 1555 2aaa 4000 6aaa 8000 9555 bfff d555 eaaa + * + * The default colormap supplies two gray levels (black/white), the + * 4x4x4 cube allocates another two and nine more are allocated to fill + * in the 13 levels. When the 4x4x4 cube is not allocated, a total of + * 11 cells are allocated. + */ + +#define PictureCmapPolicyInvalid -1 +#define PictureCmapPolicyDefault 0 +#define PictureCmapPolicyMono 1 +#define PictureCmapPolicyGray 2 +#define PictureCmapPolicyColor 3 +#define PictureCmapPolicyAll 4 + +extern int PictureCmapPolicy; + +int PictureParseCmapPolicy (const char *name); + +extern int RenderErrBase; +extern int RenderClientPrivateIndex; + +/* Fixed point updates from Carl Worth, USC, Information Sciences Institute */ + +#if defined(WIN32) && !defined(__GNUC__) +typedef __int64 xFixed_32_32; +#else +# if defined (_LP64) || \ + defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef long xFixed_32_32; +# else +# if defined(__GNUC__) && \ + ((__GNUC__ > 2) || \ + ((__GNUC__ == 2) && defined(__GNUC_MINOR__) && (__GNUC_MINOR__ > 7))) +__extension__ +# endif +typedef long long int xFixed_32_32; +# endif +#endif + +typedef xFixed_32_32 xFixed_48_16; + +#define MAX_FIXED_48_16 ((xFixed_48_16) 0x7fffffff) +#define MIN_FIXED_48_16 (-((xFixed_48_16) 1 << 31)) + +typedef CARD32 xFixed_1_31; +typedef CARD32 xFixed_1_16; +typedef INT32 xFixed_16_16; + +/* + * An unadorned "xFixed" is the same as xFixed_16_16, + * (since it's quite common in the code) + */ +typedef xFixed_16_16 xFixed; +#define XFIXED_BITS 16 + +#define xFixedToInt(f) (int) ((f) >> XFIXED_BITS) +#define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) +#define xFixedE ((xFixed) 1) +#define xFixed1 (IntToxFixed(1)) +#define xFixed1MinusE (xFixed1 - xFixedE) +#define xFixedFrac(f) ((f) & xFixed1MinusE) +#define xFixedFloor(f) ((f) & ~xFixed1MinusE) +#define xFixedCeil(f) xFixedFloor((f) + xFixed1MinusE) + +#define xFixedFraction(f) ((f) & xFixed1MinusE) +#define xFixedMod2(f) ((f) & (xFixed1 | xFixed1MinusE)) + +/* whether 't' is a well defined not obviously empty trapezoid */ +#define xTrapezoidValid(t) ((t)->left.p1.y != (t)->left.p2.y && \ + (t)->right.p1.y != (t)->right.p2.y && \ + (int) ((t)->bottom - (t)->top) > 0) + +/* + * Standard NTSC luminance conversions: + * + * y = r * 0.299 + g * 0.587 + b * 0.114 + * + * Approximate this for a bit more speed: + * + * y = (r * 153 + g * 301 + b * 58) / 512 + * + * This gives 17 bits of luminance; to get 15 bits, lop the low two + */ + +#define CvtR8G8B8toY15(s) (((((s) >> 16) & 0xff) * 153 + \ + (((s) >> 8) & 0xff) * 301 + \ + (((s) ) & 0xff) * 58) >> 2) + +#endif /* _PICTURE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picturestr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picturestr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/picturestr.h (revision 51223) @@ -0,0 +1,671 @@ +/* + * $Id: picturestr.h,v 1.14 2005/08/24 11:18:33 daniels Exp $ + * + * Copyright © 2000 SuSE, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of SuSE not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. SuSE makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE + * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Author: Keith Packard, SuSE, Inc. + */ + +#ifndef _PICTURESTR_H_ +#define _PICTURESTR_H_ + +#include "glyphstr.h" +#include "scrnintstr.h" +#include "resource.h" + +typedef struct _DirectFormat { + CARD16 red, redMask; + CARD16 green, greenMask; + CARD16 blue, blueMask; + CARD16 alpha, alphaMask; +} DirectFormatRec; + +typedef struct _IndexFormat { + VisualID vid; + ColormapPtr pColormap; + int nvalues; + xIndexValue *pValues; + void *devPrivate; +} IndexFormatRec; + +typedef struct _PictFormat { + CARD32 id; + CARD32 format; /* except bpp */ + unsigned char type; + unsigned char depth; + DirectFormatRec direct; + IndexFormatRec index; +} PictFormatRec; + +typedef struct _PictVector { + xFixed vector[3]; +} PictVector, *PictVectorPtr; + +typedef struct _PictTransform { + xFixed matrix[3][3]; +} PictTransform, *PictTransformPtr; + +#define PICT_GRADIENT_STOPTABLE_SIZE 1024 +#define SourcePictTypeSolidFill 0 +#define SourcePictTypeLinear 1 +#define SourcePictTypeRadial 2 +#define SourcePictTypeConical 3 + +typedef struct _PictSolidFill { + unsigned int type; + CARD32 color; +} PictSolidFill, *PictSolidFillPtr; + +typedef struct _PictGradientStop { + xFixed x; + xRenderColor color; +} PictGradientStop, *PictGradientStopPtr; + +typedef struct _PictGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; +} PictGradient, *PictGradientPtr; + +typedef struct _PictLinearGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + xPointFixed p1; + xPointFixed p2; +} PictLinearGradient, *PictLinearGradientPtr; + +typedef struct _PictRadialGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + double fx; + double fy; + double dx; + double dy; + double a; + double m; + double b; +} PictRadialGradient, *PictRadialGradientPtr; + +typedef struct _PictConicalGradient { + unsigned int type; + int nstops; + PictGradientStopPtr stops; + CARD32 colorTable[PICT_GRADIENT_STOPTABLE_SIZE]; + xPointFixed center; + xFixed angle; +} PictConicalGradient, *PictConicalGradientPtr; + +typedef union _SourcePict { + unsigned int type; + PictSolidFill solidFill; + PictGradient gradient; + PictLinearGradient linear; + PictRadialGradient radial; + PictConicalGradient conical; +} SourcePict, *SourcePictPtr; + +typedef struct _Picture { + DrawablePtr pDrawable; + PictFormatPtr pFormat; + CARD32 format; /* PICT_FORMAT */ + int refcnt; + CARD32 id; + PicturePtr pNext; /* chain on same drawable */ + + unsigned int repeat : 1; + unsigned int graphicsExposures : 1; + unsigned int subWindowMode : 1; + unsigned int polyEdge : 1; + unsigned int polyMode : 1; + unsigned int freeCompClip : 1; + unsigned int clientClipType : 2; + unsigned int componentAlpha : 1; + unsigned int repeatType : 2; + unsigned int unused : 21; + + PicturePtr alphaMap; + DDXPointRec alphaOrigin; + + DDXPointRec clipOrigin; + pointer clientClip; + + Atom dither; + + unsigned long stateChanges; + unsigned long serialNumber; + + RegionPtr pCompositeClip; + + DevUnion *devPrivates; + + PictTransform *transform; + + int filter; + xFixed *filter_params; + int filter_nparams; + SourcePictPtr pSourcePict; +} PictureRec; + +typedef Bool (*PictFilterValidateParamsProcPtr) (PicturePtr pPicture, int id, + xFixed *params, int nparams); +typedef struct { + char *name; + int id; + PictFilterValidateParamsProcPtr ValidateParams; +} PictFilterRec, *PictFilterPtr; + +#define PictFilterNearest 0 +#define PictFilterBilinear 1 + +#define PictFilterFast 2 +#define PictFilterGood 3 +#define PictFilterBest 4 + +#define PictFilterConvolution 5 + +typedef struct { + char *alias; + int alias_id; + int filter_id; +} PictFilterAliasRec, *PictFilterAliasPtr; + +typedef int (*CreatePictureProcPtr) (PicturePtr pPicture); +typedef void (*DestroyPictureProcPtr) (PicturePtr pPicture); +typedef int (*ChangePictureClipProcPtr) (PicturePtr pPicture, + int clipType, + pointer value, + int n); +typedef void (*DestroyPictureClipProcPtr)(PicturePtr pPicture); + +typedef int (*ChangePictureTransformProcPtr) (PicturePtr pPicture, + PictTransform *transform); + +typedef int (*ChangePictureFilterProcPtr) (PicturePtr pPicture, + int filter, + xFixed *params, + int nparams); + +typedef void (*DestroyPictureFilterProcPtr) (PicturePtr pPicture); + +typedef void (*ChangePictureProcPtr) (PicturePtr pPicture, + Mask mask); +typedef void (*ValidatePictureProcPtr) (PicturePtr pPicture, + Mask mask); +typedef void (*CompositeProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +typedef void (*GlyphsProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlists, + GlyphListPtr lists, + GlyphPtr *glyphs); + +typedef void (*CompositeRectsProcPtr) (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +typedef void (*RasterizeTrapezoidProcPtr)(PicturePtr pMask, + xTrapezoid *trap, + int x_off, + int y_off); + +typedef void (*TrapezoidsProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +typedef void (*TrianglesProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntri, + xTriangle *tris); + +typedef void (*TriStripProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +typedef void (*TriFanProcPtr) (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoint, + xPointFixed *points); + +typedef Bool (*InitIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat); + +typedef void (*CloseIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat); + +typedef void (*UpdateIndexedProcPtr) (ScreenPtr pScreen, + PictFormatPtr pFormat, + int ndef, + xColorItem *pdef); + +typedef void (*AddTrapsProcPtr) (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntrap, + xTrap *traps); + +typedef void (*AddTrianglesProcPtr) (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntri, + xTriangle *tris); + +typedef Bool (*RealizeGlyphProcPtr) (ScreenPtr pScreen, + GlyphPtr glyph); + +typedef void (*UnrealizeGlyphProcPtr) (ScreenPtr pScreen, + GlyphPtr glyph); + +typedef struct _PictureScreen { + int totalPictureSize; + unsigned int *PicturePrivateSizes; + int PicturePrivateLen; + + PictFormatPtr formats; + PictFormatPtr fallback; + int nformats; + + CreatePictureProcPtr CreatePicture; + DestroyPictureProcPtr DestroyPicture; + ChangePictureClipProcPtr ChangePictureClip; + DestroyPictureClipProcPtr DestroyPictureClip; + + ChangePictureProcPtr ChangePicture; + ValidatePictureProcPtr ValidatePicture; + + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; + CompositeRectsProcPtr CompositeRects; + + DestroyWindowProcPtr DestroyWindow; + CloseScreenProcPtr CloseScreen; + + StoreColorsProcPtr StoreColors; + + InitIndexedProcPtr InitIndexed; + CloseIndexedProcPtr CloseIndexed; + UpdateIndexedProcPtr UpdateIndexed; + + int subpixel; + + PictFilterPtr filters; + int nfilters; + PictFilterAliasPtr filterAliases; + int nfilterAliases; + + ChangePictureTransformProcPtr ChangePictureTransform; + ChangePictureFilterProcPtr ChangePictureFilter; + DestroyPictureFilterProcPtr DestroyPictureFilter; + + TrapezoidsProcPtr Trapezoids; + TrianglesProcPtr Triangles; + TriStripProcPtr TriStrip; + TriFanProcPtr TriFan; + + RasterizeTrapezoidProcPtr RasterizeTrapezoid; + + AddTrianglesProcPtr AddTriangles; + + AddTrapsProcPtr AddTraps; + + int totalGlyphPrivateSize; + unsigned int *glyphPrivateSizes; + int glyphPrivateLen; + int glyphPrivateOffset; + + RealizeGlyphProcPtr RealizeGlyph; + UnrealizeGlyphProcPtr UnrealizeGlyph; + +} PictureScreenRec, *PictureScreenPtr; + +extern int PictureScreenPrivateIndex; +extern int PictureWindowPrivateIndex; +extern RESTYPE PictureType; +extern RESTYPE PictFormatType; +extern RESTYPE GlyphSetType; + +#define GetPictureScreen(s) ((PictureScreenPtr) ((s)->devPrivates[PictureScreenPrivateIndex].ptr)) +#define GetPictureScreenIfSet(s) ((PictureScreenPrivateIndex != -1) ? GetPictureScreen(s) : NULL) +#define SetPictureScreen(s,p) ((s)->devPrivates[PictureScreenPrivateIndex].ptr = (pointer) (p)) +#define GetPictureWindow(w) ((PicturePtr) ((w)->devPrivates[PictureWindowPrivateIndex].ptr)) +#define SetPictureWindow(w,p) ((w)->devPrivates[PictureWindowPrivateIndex].ptr = (pointer) (p)) + +#define GetGlyphPrivatesForScreen(glyph, s) \ + ((glyph)->devPrivates + (GetPictureScreen (s))->glyphPrivateOffset) + +#define VERIFY_PICTURE(pPicture, pid, client, mode, err) {\ + pPicture = SecurityLookupIDByType(client, pid, PictureType, mode);\ + if (!pPicture) { \ + client->errorValue = pid; \ + return err; \ + } \ +} + +#define VERIFY_ALPHA(pPicture, pid, client, mode, err) {\ + if (pid == None) \ + pPicture = 0; \ + else { \ + VERIFY_PICTURE(pPicture, pid, client, mode, err); \ + } \ +} \ + +void +ResetPicturePrivateIndex (void); + +int +AllocatePicturePrivateIndex (void); + +Bool +AllocatePicturePrivate (ScreenPtr pScreen, int index2, unsigned int amount); + +Bool +PictureDestroyWindow (WindowPtr pWindow); + +Bool +PictureCloseScreen (int Index, ScreenPtr pScreen); + +void +PictureStoreColors (ColormapPtr pColormap, int ndef, xColorItem *pdef); + +Bool +PictureInitIndexedFormats (ScreenPtr pScreen); + +Bool +PictureSetSubpixelOrder (ScreenPtr pScreen, int subpixel); + +int +PictureGetSubpixelOrder (ScreenPtr pScreen); + +PictFormatPtr +PictureCreateDefaultFormats (ScreenPtr pScreen, int *nformatp); + +PictFormatPtr +PictureMatchVisual (ScreenPtr pScreen, int depth, VisualPtr pVisual); + +PictFormatPtr +PictureMatchFormat (ScreenPtr pScreen, int depth, CARD32 format); + +Bool +PictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); + +int +PictureGetFilterId (char *filter, int len, Bool makeit); + +char * +PictureGetFilterName (int id); + +int +PictureAddFilter (ScreenPtr pScreen, + char *filter, + PictFilterValidateParamsProcPtr ValidateParams); + +Bool +PictureSetFilterAlias (ScreenPtr pScreen, char *filter, char *alias); + +Bool +PictureSetDefaultFilters (ScreenPtr pScreen); + +void +PictureResetFilters (ScreenPtr pScreen); + +PictFilterPtr +PictureFindFilter (ScreenPtr pScreen, char *name, int len); + +int +SetPictureFilter (PicturePtr pPicture, char *name, int len, xFixed *params, int nparams); + +Bool +PictureFinishInit (void); + +void +SetPictureToDefaults (PicturePtr pPicture); + +PicturePtr +AllocatePicture (ScreenPtr pScreen); + +#if 0 +Bool +miPictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats); +#endif + + +PicturePtr +CreatePicture (Picture pid, + DrawablePtr pDrawable, + PictFormatPtr pFormat, + Mask mask, + XID *list, + ClientPtr client, + int *error); + +int +ChangePicture (PicturePtr pPicture, + Mask vmask, + XID *vlist, + DevUnion *ulist, + ClientPtr client); + +int +SetPictureClipRects (PicturePtr pPicture, + int xOrigin, + int yOrigin, + int nRect, + xRectangle *rects); + +int +SetPictureClipRegion (PicturePtr pPicture, + int xOrigin, + int yOrigin, + RegionPtr pRegion); + +int +SetPictureTransform (PicturePtr pPicture, + PictTransform *transform); + +void +CopyPicture (PicturePtr pSrc, + Mask mask, + PicturePtr pDst); + +void +ValidatePicture(PicturePtr pPicture); + +int +FreePicture (pointer pPicture, + XID pid); + +int +FreePictFormat (pointer pPictFormat, + XID pid); + +void +CompositePicture (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + +void +CompositeGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr lists, + GlyphPtr *glyphs); + +void +CompositeRects (CARD8 op, + PicturePtr pDst, + xRenderColor *color, + int nRect, + xRectangle *rects); + +void +CompositeTrapezoids (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntrap, + xTrapezoid *traps); + +void +CompositeTriangles (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int ntriangles, + xTriangle *triangles); + +void +CompositeTriStrip (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoints, + xPointFixed *points); + +void +CompositeTriFan (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int npoints, + xPointFixed *points); + +Bool +PictureTransformPoint (PictTransformPtr transform, + PictVectorPtr vector); + +Bool +PictureTransformPoint3d (PictTransformPtr transform, + PictVectorPtr vector); + +void RenderExtensionInit (void); + +Bool +AnimCurInit (ScreenPtr pScreen); + +int +AnimCursorCreate (CursorPtr *cursors, CARD32 *deltas, int ncursor, CursorPtr *ppCursor); + +void +AddTraps (PicturePtr pPicture, + INT16 xOff, + INT16 yOff, + int ntraps, + xTrap *traps); + +PicturePtr +CreateSolidPicture (Picture pid, + xRenderColor *color, + int *error); + +PicturePtr +CreateLinearGradientPicture (Picture pid, + xPointFixed *p1, + xPointFixed *p2, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +PicturePtr +CreateRadialGradientPicture (Picture pid, + xPointFixed *inner, + xPointFixed *outer, + xFixed innerRadius, + xFixed outerRadius, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +PicturePtr +CreateConicalGradientPicture (Picture pid, + xPointFixed *center, + xFixed angle, + int nStops, + xFixed *stops, + xRenderColor *colors, + int *error); + +#ifdef PANORAMIX +void PanoramiXRenderInit (void); +void PanoramiXRenderReset (void); +#endif + +#endif /* _PICTURESTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmap.h (revision 51223) @@ -0,0 +1,110 @@ +/* $Xorg: pixmap.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef PIXMAP_H +#define PIXMAP_H + +#include "misc.h" +#include "screenint.h" + +/* types for Drawable */ +#define DRAWABLE_WINDOW 0 +#define DRAWABLE_PIXMAP 1 +#define UNDRAWABLE_WINDOW 2 +#define DRAWABLE_BUFFER 3 + +/* flags to PaintWindow() */ +#define PW_BACKGROUND 0 +#define PW_BORDER 1 + +#define NullPixmap ((PixmapPtr)0) + +typedef struct _Drawable *DrawablePtr; +typedef struct _Pixmap *PixmapPtr; + +typedef union _PixUnion { + PixmapPtr pixmap; + unsigned long pixel; +} PixUnion; + +#define SamePixUnion(a,b,isPixel)\ + ((isPixel) ? (a).pixel == (b).pixel : (a).pixmap == (b).pixmap) + +#define EqualPixUnion(as, a, bs, b) \ + ((as) == (bs) && (SamePixUnion (a, b, as))) + +#define OnScreenDrawable(type) \ + ((type == DRAWABLE_WINDOW) || (type == DRAWABLE_BUFFER)) + +#define WindowDrawable(type) \ + ((type == DRAWABLE_WINDOW) || (type == UNDRAWABLE_WINDOW)) + +extern PixmapPtr GetScratchPixmapHeader( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/); + +extern void FreeScratchPixmapHeader( + PixmapPtr /*pPixmap*/); + +extern Bool CreateScratchPixmapsForScreen( + int /*scrnum*/); + +extern void FreeScratchPixmapsForScreen( + int /*scrnum*/); + +extern PixmapPtr AllocatePixmap( + ScreenPtr /*pScreen*/, + int /*pixDataSize*/); + +#endif /* PIXMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmapstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmapstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pixmapstr.h (revision 51223) @@ -0,0 +1,99 @@ +/* $Xorg: pixmapstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef PIXMAPSTRUCT_H +#define PIXMAPSTRUCT_H +#include +#include "pixmap.h" +#include "screenint.h" +#include "regionstr.h" + +/* + * The padN members are unfortunate ABI BC. See fdo bug #6924. + */ + +typedef struct _Drawable { + unsigned char type; /* DRAWABLE_ */ + unsigned char class; /* specific to type */ + unsigned char depth; + unsigned char bitsPerPixel; +#if defined(_XSERVER64) + XID pad0; +#endif + XID id; /* resource id */ +#if defined(_XSERVER64) + XID pad1; +#endif + short x; /* window: screen absolute, pixmap: 0 */ + short y; /* window: screen absolute, pixmap: 0 */ + unsigned short width; + unsigned short height; + ScreenPtr pScreen; + unsigned long serialNumber; +} DrawableRec; + +/* + * PIXMAP -- device dependent + */ + +typedef struct _Pixmap { + DrawableRec drawable; + int refcnt; + int devKind; + DevUnion devPrivate; +#ifdef PIXPRIV + DevUnion *devPrivates; /* real devPrivates like gcs & windows */ +#endif +#ifdef COMPOSITE + short screen_x; + short screen_y; +#endif +} PixmapRec; + +#endif /* PIXMAPSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcGCstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcGCstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcGCstr.h (revision 51223) @@ -0,0 +1,95 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ppcGCstr.h,v 1.3 2003/02/18 21:29:59 tsi Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/*********************************************************** + Copyright IBM Corporation 1988 + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of IBM not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XConsortium: ppcGCstr.h /main/3 1996/02/21 17:57:42 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "gc.h" +#include "mfb.h" + +typedef struct { + unsigned long planemask ; + unsigned long fgPixel ; + unsigned long bgPixel ; + int alu ; + int fillStyle ; + } ppcReducedRrop ; + +/* ************************************************************************ */ + +/* private field of GC */ +typedef struct { +/* The next five (5) fields MUST CORRESPOND to + * the fields of a "mfbPrivGC" struct + * ----- BEGINNING OF "DO-NOT-CHANGE" REGION ----- + */ + unsigned char rop ; /* reduction of rasterop to 1 of 3 */ + unsigned char ropOpStip ; /* rop for opaque stipple */ + unsigned char ropFillArea ; /* == alu, rop, or ropOpStip */ + unsigned char unused[sizeof(long) - 3]; + mfbFillAreaProcPtr FillArea; /* fills regions; look at the code */ +/* ----- END OF "DO-NOT-CHANGE" REGION ----- */ + ppcReducedRrop colorRrop ; + short lastDrawableType ; /* was last drawable a window or a pixmap? */ + short lastDrawableDepth ; /* was last drawable 1 or 8 planes? */ + pointer devPriv ; /* Private area for device specific stuff */ + } ppcPrivGC ; +typedef ppcPrivGC *ppcPrivGCPtr ; + +/* ppcCReduce.c */ +void xf4bppGetReducedColorRrop( + GCPtr, + int, + ppcReducedRrop * +); + +/* vgaGC.c */ +void xf4bppChangeGCtype( + GCPtr, + ppcPrivGCPtr +); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcSpMcro.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcSpMcro.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ppcSpMcro.h (revision 51223) @@ -0,0 +1,45 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/ppcSpMcro.h,v 1.1.2.1 1998/06/27 14:48:49 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ +/* $XConsortium: ppcSpMcro.h /main/3 1996/02/21 17:58:36 kaleb $ */ + +/* This screwy macro is used in all the spans routines and you find + it all over the place, so it is a macro just to tidy things up. +*/ + +#define SETSPANPTRS(IN,N,IPW,PW,IPPT,PPT,FPW,FPPT,FSORT) \ + { \ + N = IN * miFindMaxBand(pGC->pCompositeClip); \ + if(!(PW = (int *)ALLOCATE_LOCAL(N * sizeof(int)))) \ + return; \ + if(!(PPT = (DDXPointRec *)ALLOCATE_LOCAL(N * sizeof(DDXPointRec)))) \ + { \ + DEALLOCATE_LOCAL(PW); \ + return; \ + } \ + FPW = PW; \ + FPPT = PPT; \ + N = miClipSpans(pGC->pCompositeClip, IPPT, IPW, IN, \ + PPT, PW, FSORT); \ + } + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_asm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_asm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_asm.h (revision 51223) @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C++ 10.6 or later +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Inline assembler versions of the primitive operand +* functions for faster performance. At the moment this is +* x86 inline assembler, but these functions could be replaced +* with native inline assembler for each supported processor +* platform. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_ASM_H +#define __X86EMU_PRIM_ASM_H + +#ifdef __WATCOMC__ + +#ifndef VALIDATE +#define __HAVE_INLINE_ASSEMBLER__ +#endif + +u32 get_flags_asm(void); +#pragma aux get_flags_asm = \ + "pushf" \ + "pop eax" \ + value [eax] \ + modify exact [eax]; + +u16 aaa_word_asm(u32 *flags,u16 d); +#pragma aux aaa_word_asm = \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aas_word_asm(u32 *flags,u16 d); +#pragma aux aas_word_asm = \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aad_word_asm(u32 *flags,u16 d); +#pragma aux aad_word_asm = \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aam_word_asm(u32 *flags,u8 d); +#pragma aux aam_word_asm = \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [ax] \ + modify exact [ax]; + +u8 adc_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux adc_byte_asm = \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 adc_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux adc_word_asm = \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 adc_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux adc_long_asm = \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 add_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux add_byte_asm = \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 add_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux add_word_asm = \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 add_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux add_long_asm = \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 and_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux and_byte_asm = \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 and_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux and_word_asm = \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 and_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux and_long_asm = \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux cmp_byte_asm = \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 cmp_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux cmp_word_asm = \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 cmp_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux cmp_long_asm = \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 daa_byte_asm(u32 *flags,u8 d); +#pragma aux daa_byte_asm = \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 das_byte_asm(u32 *flags,u8 d); +#pragma aux das_byte_asm = \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 dec_byte_asm(u32 *flags,u8 d); +#pragma aux dec_byte_asm = \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 dec_word_asm(u32 *flags,u16 d); +#pragma aux dec_word_asm = \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 dec_long_asm(u32 *flags,u32 d); +#pragma aux dec_long_asm = \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 inc_byte_asm(u32 *flags,u8 d); +#pragma aux inc_byte_asm = \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 inc_word_asm(u32 *flags,u16 d); +#pragma aux inc_word_asm = \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 inc_long_asm(u32 *flags,u32 d); +#pragma aux inc_long_asm = \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 or_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux or_byte_asm = \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 or_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux or_word_asm = \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 or_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux or_long_asm = \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 neg_byte_asm(u32 *flags,u8 d); +#pragma aux neg_byte_asm = \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 neg_word_asm(u32 *flags,u16 d); +#pragma aux neg_word_asm = \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 neg_long_asm(u32 *flags,u32 d); +#pragma aux neg_long_asm = \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 not_byte_asm(u32 *flags,u8 d); +#pragma aux not_byte_asm = \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 not_word_asm(u32 *flags,u16 d); +#pragma aux not_word_asm = \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 not_long_asm(u32 *flags,u32 d); +#pragma aux not_long_asm = \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcl_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcl_word_asm = \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcl_long_asm = \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcr_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcr_word_asm = \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcr_long_asm = \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rol_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rol_byte_asm = \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rol_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rol_word_asm = \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rol_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rol_long_asm = \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 ror_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux ror_byte_asm = \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 ror_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux ror_word_asm = \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 ror_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux ror_long_asm = \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shl_byte_asm = \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shl_word_asm = \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shl_long_asm = \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shr_byte_asm = \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shr_word_asm = \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shr_long_asm = \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 sar_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sar_byte_asm = \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 sar_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux sar_word_asm = \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 sar_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux sar_long_asm = \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shld_word_asm = \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shld_long_asm = \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shrd_word_asm = \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shrd_long_asm = \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sbb_byte_asm = \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sbb_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sbb_word_asm = \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sbb_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sbb_long_asm = \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 sub_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sub_byte_asm = \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sub_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sub_word_asm = \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sub_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sub_long_asm = \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void test_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux test_byte_asm = \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + modify exact [al bl]; + +void test_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux test_word_asm = \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + modify exact [ax bx]; + +void test_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux test_long_asm = \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + modify exact [eax ebx]; + +u8 xor_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux xor_byte_asm = \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 xor_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux xor_word_asm = \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 xor_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux xor_long_asm = \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux imul_byte_asm = \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux imul_word_asm = \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux imul_long_asm = \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux mul_byte_asm = \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux mul_word_asm = \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux mul_long_asm = \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux idiv_byte_asm = \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux idiv_word_asm = \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux idiv_long_asm = \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux div_byte_asm = \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux div_word_asm = \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux div_long_asm = \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +#endif + +#endif /* __X86EMU_PRIM_ASM_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_ops.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_ops.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/prim_ops.h (revision 51223) @@ -0,0 +1,141 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/property.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/property.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/property.h (revision 51223) @@ -0,0 +1,74 @@ +/* $Xorg: property.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/property.h,v 1.3 2001/12/14 19:59:55 dawes Exp $ */ + +#ifndef PROPERTY_H +#define PROPERTY_H + +#include "window.h" + +typedef struct _Property *PropertyPtr; + +extern int ChangeWindowProperty( + WindowPtr /*pWin*/, + Atom /*property*/, + Atom /*type*/, + int /*format*/, + int /*mode*/, + unsigned long /*len*/, + pointer /*value*/, + Bool /*sendevent*/); + +extern int DeleteProperty( + WindowPtr /*pWin*/, + Atom /*propName*/); + +extern void DeleteAllWindowProperties( + WindowPtr /*pWin*/); + +#endif /* PROPERTY_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/propertyst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/propertyst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/propertyst.h (revision 51223) @@ -0,0 +1,76 @@ +/* $Xorg: propertyst.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/propertyst.h,v 3.2 2001/01/17 22:36:57 dawes Exp $ */ + +#ifndef PROPERTYSTRUCT_H +#define PROPERTYSTRUCT_H +#include "misc.h" +#include "property.h" +/* + * PROPERTY -- property element + */ + +typedef struct _Property { + struct _Property *next; + ATOM propertyName; + ATOM type; /* ignored by server */ + short format; /* format of data for swapping - 8,16,32 */ + long size; /* size of data in (format/8) bytes */ + pointer data; /* private to client */ +#if defined(LBX) || defined(LBX_COMPAT) + /* If space is at a premium and binary compatibility is not + * an issue, you may want to put the owner_pid next to format + * so that the two shorts pack together without padding. + */ + short owner_pid; /* proxy that has the data */ + XID tag_id; +#endif +} PropertyRec; + +#endif /* PROPERTYSTRUCT_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pseudoramiX.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pseudoramiX.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/pseudoramiX.h (revision 51223) @@ -0,0 +1,10 @@ +/* + * Minimal implementation of PanoramiX/Xinerama + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/pseudoramiX.h,v 1.3 2004/07/02 01:30:33 torrey Exp $ */ + +extern int noPseudoramiXExtension; + +void PseudoramiXAddScreen(int x, int y, int w, int h); +void PseudoramiXExtensionInit(int argc, char *argv[]); +void PseudoramiXResetScreens(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/psout.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/psout.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/psout.h (revision 51223) @@ -0,0 +1,335 @@ +/* $Xorg: psout.h,v 1.6 2001/02/09 02:04:37 xorgcvs Exp $ */ +/* + +Copyright 1996, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + +*/ +/* + * (c) Copyright 1996 Hewlett-Packard Company + * (c) Copyright 1996 International Business Machines Corp. + * (c) Copyright 1996 Sun Microsystems, Inc. + * (c) Copyright 1996 Novell, Inc. + * (c) Copyright 1996 Digital Equipment Corp. + * (c) Copyright 1996 Fujitsu Limited + * (c) Copyright 1996 Hitachi, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject + * to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the names of the copyright holders + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * from said copyright holders. + */ + +/******************************************************************* +** +** ********************************************************* +** * +** * File: psout.h +** * +** * Contents: Include file for psout.c +** * +** * Created By: Roger Helmendach (Liberty Systems) +** * +** * Copyright: Copyright 1996 The Open Group, Inc. +** * +** ********************************************************* +** +********************************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _psout_ +#define _psout_ + +#include + +typedef enum PsCapEnum_ { PsCButt=0, PsCRound, PsCSquare } PsCapEnum; +typedef enum PsJoinEnum_ { PsJMiter=0, PsJRound, PsJBevel } PsJoinEnum; +typedef enum PsArcEnum_ { PsChord, PsPieSlice } PsArcEnum; +typedef enum PsRuleEnum_ { PsEvenOdd, PsNZWinding } PsRuleEnum; +typedef enum PsFillEnum_ { PsSolid=0, PsTile, PsStip, PsOpStip } PsFillEnum; + +typedef struct PsPointRec_ +{ + int x; + int y; +} PsPointRec; + +typedef PsPointRec *PsPointPtr; + +typedef struct PsRectRec_ +{ + int x; + int y; + int w; + int h; +} PsRectRec; + +typedef PsRectRec *PsRectPtr; + +typedef struct PsArcRec_ +{ + int x; + int y; + int w; + int h; + int a1; + int a2; + PsArcEnum style; +} PsArcRec; + +typedef PsArcRec *PsArcPtr; + +#define PSOUT_RECT 0 +#define PSOUT_ARC 1 +#define PSOUT_POINTS 2 + +typedef struct PsElmRec_ +{ + int type; + int nPoints; + union + { + PsRectRec rect; + PsArcRec arc; + PsPointPtr points; + } c; +} PsElmRec; + +typedef PsElmRec *PsElmPtr; + +typedef struct PsClipRec_ +{ + int nRects; + PsRectPtr rects; + int nElms; + PsElmPtr elms; + int nOutterClips; + PsRectPtr outterClips; +} PsClipRec; + +typedef PsClipRec *PsClipPtr; + +typedef enum PsFTDownloadFontType_ +{ + PsFontBitmap=0, + PsFontType1, + PsFontType3 +} PsFTDownloadFontType; + +/* Define |PsOutColor| color type which can hold one RGB value + * (note: this needs to be |signed| long/long long to represent + * special values such as |PSOUTCOLOR_NOCOLOR|) + */ +#ifdef PSOUT_USE_DEEPCOLOR +/* 64bit |PsOutColor| which can hold 16bit R-,G-,B-values */ +#ifdef WIN32 +typedef signed __int64 PsOutColor; +#else +# if defined(__alpha__) || defined(__alpha) || \ + defined(ia64) || defined(__ia64__) || \ + defined(__sparc64__) || defined(_LP64) || \ + defined(__s390x__) || \ + defined(amd64) || defined (__amd64__) || \ + defined (__powerpc64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +typedef signed long PsOutColor; +# else +typedef signed long long PsOutColor; +# endif /* native 64bit platform */ +#endif /* WIN32 */ + +#define PSOUTCOLOR_TO_REDBITS(clr) ((clr) >> 32) +#define PSOUTCOLOR_TO_GREENBITS(clr) (((clr) >> 16) & 0xFFFF) +#define PSOUTCOLOR_TO_BLUEBITS(clr) ((clr) & 0xFFFF) +#define PSOUTCOLOR_BITS_TO_PSFLOAT(b) ((float)(b) / 65535.) +#define PSOUTCOLOR_WHITE (0xFFFFFFFFFFFFLL) +#define PSOUTCOLOR_NOCOLOR (-1LL) +#define PSOUTCOLOR_TO_RGB24BIT(clr) (((PSOUTCOLOR_TO_REDBITS(clr) >> 8) << 16) | \ + ((PSOUTCOLOR_TO_GREENBITS(clr) >> 8) << 8) | \ + ((PSOUTCOLOR_TO_BLUEBITS(clr) >> 8) << 0)) +#else +/* 32bit |PsOutColor| which can hold 8bit R-,G-,B-values */ +typedef signed long PsOutColor; +#define PSOUTCOLOR_TO_REDBITS(clr) ((clr) >> 16) +#define PSOUTCOLOR_TO_GREENBITS(clr) (((clr) >> 8) & 0xFF) +#define PSOUTCOLOR_TO_BLUEBITS(clr) ((clr) & 0xFF) +#define PSOUTCOLOR_BITS_TO_PSFLOAT(b) ((float)(b) / 255.) +#define PSOUTCOLOR_WHITE (0xFFFFFF) +#define PSOUTCOLOR_NOCOLOR (-1) +#define PSOUTCOLOR_TO_RGB24BIT(clr) ((PSOUTCOLOR_TO_REDBITS(clr) << 16) | \ + (PSOUTCOLOR_TO_GREENBITS(clr) << 8) | \ + (PSOUTCOLOR_TO_BLUEBITS(clr) << 0)) +#endif /* PSOUT_USE_DEEPCOLOR */ + +#ifdef USE_PSOUT_PRIVATE +typedef void *voidPtr; + +typedef struct PsPatRec_ +{ + PsFillEnum type; + voidPtr tag; +} PsPatRec; + +typedef PsPatRec *PsPatPtr; + +typedef struct PsOutRec_ +{ + FILE *Fp; + char Buf[16384]; + PsOutColor CurColor; + int LineWidth; + PsCapEnum LineCap; + PsJoinEnum LineJoin; + int NDashes; + int *Dashes; + int DashOffset; + PsOutColor LineBClr; + PsRuleEnum FillRule; + char *FontName; + int FontSize; + float FontMtx[4]; + int ImageFormat; + int RevImage; + int NPatterns; + int MxPatterns; + PsPatPtr Patterns; + int ClipType; + PsClipRec Clip; + int InFrame; + int XOff; + int YOff; + + PsFillEnum InTile; + int ImgSkip; + PsOutColor ImgBClr; + PsOutColor ImgFClr; + int ImgX; + int ImgY; + int ImgW; + int ImgH; + int SclW; + int SclH; + + Bool isRaw; + + int pagenum; + + int start_image; +} PsOutRec; + +typedef struct PsOutRec_ *PsOutPtr; + +extern void S_Flush(PsOutPtr self); +extern void S_OutNum(PsOutPtr self, float num); +extern void S_OutTok(PsOutPtr self, char *tok, int cr); +#else +typedef struct PsOutRec_ *PsOutPtr; +#endif /* USE_PSOUT_PRIVATE */ + +extern PsOutPtr PsOut_BeginFile(FILE *fp, char *title, int orient, int count, int plex, + int res, int wd, int ht, Bool raw); +extern void PsOut_EndFile(PsOutPtr self, int closeFile); +extern void PsOut_BeginPage(PsOutPtr self, int orient, int count, int plex, + int res, int wd, int ht); +extern void PsOut_EndPage(PsOutPtr self); +extern void PsOut_DirtyAttributes(PsOutPtr self); +extern void PsOut_Comment(PsOutPtr self, char *comment); +extern void PsOut_Offset(PsOutPtr self, int x, int y); + +extern void PsOut_Clip(PsOutPtr self, int clpTyp, PsClipPtr clpinf); + +extern void PsOut_Color(PsOutPtr self, PsOutColor clr); +extern void PsOut_FillRule(PsOutPtr self, PsRuleEnum rule); +extern void PsOut_LineAttrs(PsOutPtr self, int wd, PsCapEnum cap, + PsJoinEnum join, int nDsh, int *dsh, int dshOff, + PsOutColor bclr); +extern void PsOut_TextAttrs(PsOutPtr self, char *fnam, int siz, int iso); +extern void PsOut_TextAttrsMtx(PsOutPtr self, char *fnam, float *mtx, int iso); + +extern void PsOut_Polygon(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_FillRect(PsOutPtr self, int x, int y, int w, int h); +extern void PsOut_FillArc(PsOutPtr self, int x, int y, int w, int h, + float ang1, float ang2, PsArcEnum style); + +extern void PsOut_Lines(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_Points(PsOutPtr self, int nPts, PsPointPtr pts); +extern void PsOut_DrawRect(PsOutPtr self, int x, int y, int w, int h); +extern void PsOut_DrawArc(PsOutPtr self, int x, int y, int w, int h, + float ang1, float ang2); + +extern void PsOut_Text(PsOutPtr self, int x, int y, char *text, int textl, + PsOutColor bclr); +extern void PsOut_Text16(PsOutPtr self, int x, int y, unsigned short *text, int textl, PsOutColor bclr); + +extern void PsOut_BeginImage(PsOutPtr self, PsOutColor bclr, PsOutColor fclr, int x, int y, + int w, int h, int sw, int sh, int format); +extern void PsOut_BeginImageIM(PsOutPtr self, PsOutColor bclr, PsOutColor fclr, int x, int y, + int w, int h, int sw, int sh, int format); +extern void PsOut_EndImage(PsOutPtr self); +extern void PsOut_OutImageBytes(PsOutPtr self, int nBytes, char *bytes); + +extern void PsOut_BeginFrame(PsOutPtr self, int xoff, int yoff, int x, int y, + int w, int h); +extern void PsOut_EndFrame(PsOutPtr self); + +extern int PsOut_BeginPattern(PsOutPtr self, void *tag, int w, int h, + PsFillEnum type, PsOutColor bclr, PsOutColor fclr); +extern void PsOut_EndPattern(PsOutPtr self); +extern void PsOut_SetPattern(PsOutPtr self, void *tag, PsFillEnum type); + +extern void PsOut_RawData(PsOutPtr self, char *data, int len); + +extern int PsOut_DownloadType1(PsOutPtr self, const char *auditmsg, const char *name, const char *fname); + +extern int PsOut_DownloadFreeType1(PsOutPtr self, const char *psfontname, FontPtr pFont, long block_offset); +extern int PsOut_DownloadFreeType3(PsOutPtr self, const char *psfontname, FontPtr pFont, long block_offset); + +extern int PsOut_DownloadFreeType(PsOutPtr self, PsFTDownloadFontType downloadfonttype, const char *psfontname, FontPtr pFont, long block_offset); +extern void PsOut_Get_FreeType_Glyph_Name( char *destbuf, FontPtr pFont, unsigned long x11fontindex); +extern void PsOut_FreeType_Text(FontPtr pFont, PsOutPtr self, int x, int y, char *text, int textl); +extern void PsOut_FreeType_Text16(FontPtr pFont, PsOutPtr self, int x, int y, unsigned short *text, int textl); + +extern void PsOut_FreeType_TextAttrs16(PsOutPtr self, char *fnam, int siz, int iso); +extern void PsOut_FreeType_TextAttrsMtx16(PsOutPtr self, char *fnam, float *mtx, int iso); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartz.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartz.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartz.h (revision 51223) @@ -0,0 +1,131 @@ +/* + * quartz.h + * + * External interface of the Quartz display modes seen by the generic, mode + * independent parts of the Darwin X server. + */ +/* + * Copyright (c) 2001-2003 Greg Parker and Torrey T. Lyons. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XdotOrg: xserver/xorg/hw/darwin/quartz/quartz.h,v 1.4 2005/07/01 22:43:07 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/quartz.h,v 1.7 2003/11/12 20:21:51 torrey Exp $ */ + +#ifndef _QUARTZ_H +#define _QUARTZ_H + +#include "quartzPasteboard.h" + +#include "screenint.h" +#include "window.h" + +/*------------------------------------------ + Quartz display mode function types + ------------------------------------------*/ + +/* + * Display mode initialization + */ +typedef void (*DisplayInitProc)(void); +typedef Bool (*AddScreenProc)(int index, ScreenPtr pScreen); +typedef Bool (*SetupScreenProc)(int index, ScreenPtr pScreen); +typedef void (*InitInputProc)(int argc, char **argv); + +/* + * Cursor functions + */ +typedef Bool (*InitCursorProc)(ScreenPtr pScreen); +typedef void (*CursorUpdateProc)(void); + +/* + * Suspend and resume X11 activity + */ +typedef void (*SuspendScreenProc)(ScreenPtr pScreen); +typedef void (*ResumeScreenProc)(ScreenPtr pScreen, int x, int y); +typedef void (*CaptureScreensProc)(void); +typedef void (*ReleaseScreensProc)(void); + +/* + * Screen state change support + */ +typedef void (*ScreenChangedProc)(void); +typedef void (*AddPseudoramiXScreensProc)(int *x, int *y, int *width, int *height); +typedef void (*UpdateScreenProc)(ScreenPtr pScreen); + +/* + * Rootless helper functions + */ +typedef Bool (*IsX11WindowProc)(void *nsWindow, int windowNumber); +typedef void (*HideWindowsProc)(Bool hide); + +/* + * Rootless functions for optional export to GLX layer + */ +typedef void * (*FrameForWindowProc)(WindowPtr pWin, Bool create); +typedef WindowPtr (*TopLevelParentProc)(WindowPtr pWindow); +typedef Bool (*CreateSurfaceProc) + (ScreenPtr pScreen, Drawable id, DrawablePtr pDrawable, + unsigned int client_id, unsigned int *surface_id, + unsigned int key[2], void (*notify) (void *arg, void *data), + void *notify_data); +typedef Bool (*DestroySurfaceProc) + (ScreenPtr pScreen, Drawable id, DrawablePtr pDrawable, + void (*notify) (void *arg, void *data), void *notify_data); + +/* + * Quartz display mode function list + */ +typedef struct _QuartzModeProcs { + DisplayInitProc DisplayInit; + AddScreenProc AddScreen; + SetupScreenProc SetupScreen; + InitInputProc InitInput; + + InitCursorProc InitCursor; + CursorUpdateProc CursorUpdate; // Not used if NULL + + SuspendScreenProc SuspendScreen; + ResumeScreenProc ResumeScreen; + CaptureScreensProc CaptureScreens; // Only called in fullscreen + ReleaseScreensProc ReleaseScreens; // Only called in fullscreen + + ScreenChangedProc ScreenChanged; + AddPseudoramiXScreensProc AddPseudoramiXScreens; + UpdateScreenProc UpdateScreen; + + IsX11WindowProc IsX11Window; + HideWindowsProc HideWindows; + + FrameForWindowProc FrameForWindow; + TopLevelParentProc TopLevelParent; + CreateSurfaceProc CreateSurface; + DestroySurfaceProc DestroySurface; +} QuartzModeProcsRec, *QuartzModeProcsPtr; + +extern QuartzModeProcsPtr quartzProcs; + +Bool QuartzLoadDisplayBundle(const char *dpyBundleName); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzAudio.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzAudio.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzAudio.h (revision 51223) @@ -0,0 +1,41 @@ +// +// QuartzAudio.h +// +// X Window bell support using CoreAudio or AppKit. +// Greg Parker gparker@cs.stanford.edu 19 Feb 2001 +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzAudio.h,v 1.2 2001/04/01 20:45:43 tsi Exp $ */ + +#ifndef _QUARTZAUDIO_H +#define _QUARTZAUDIO_H + +#include "input.h" + +void QuartzAudioInit(void); +void QuartzBell(int volume, DeviceIntPtr pDevice, pointer ctrl, int class); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCommon.h (revision 51223) @@ -0,0 +1,108 @@ +/* $XdotOrg: xserver/xorg/hw/darwin/quartz/quartzCommon.h,v 1.4 2005/07/01 22:43:07 daniels Exp $ */ +/* + * quartzCommon.h + * + * Common definitions used internally by all Quartz modes + * + * This file should be included before any X11 or IOKit headers + * so that it can avoid symbol conflicts. + * + * Copyright (c) 2001-2004 Torrey T. Lyons and Greg Parker. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/quartzCommon.h,v 1.15 2004/06/08 22:58:10 torrey Exp $ */ + +#ifndef _QUARTZCOMMON_H +#define _QUARTZCOMMON_H + +// QuickDraw in ApplicationServices has the following conflicts with +// the basic X server headers. Use QD_ to use the QuickDraw +// definition of any of these symbols, or the normal name for the +// X11 definition. +#define Cursor QD_Cursor +#define WindowPtr QD_WindowPtr +#define Picture QD_Picture +#include +#undef Cursor +#undef WindowPtr +#undef Picture + +// Quartz specific per screen storage structure +typedef struct { + // List of CoreGraphics displays that this X11 screen covers. + // This is more than one CG display for video mirroring and + // rootless PseudoramiX mode. + // No CG display will be covered by more than one X11 screen. + int displayCount; + CGDirectDisplayID *displayIDs; +} QuartzScreenRec, *QuartzScreenPtr; + +#define QUARTZ_PRIV(pScreen) \ + ((QuartzScreenPtr)pScreen->devPrivates[quartzScreenIndex].ptr) + +// Data stored at startup for Cocoa front end +extern int quartzEventWriteFD; +extern int quartzStartClients; + +// User preferences used by Quartz modes +extern int quartzRootless; +extern int quartzUseSysBeep; +extern int quartzUseAGL; +extern int quartzEnableKeyEquivalents; + +// Other shared data +extern int quartzServerVisible; +extern int quartzServerQuitting; +extern int quartzScreenIndex; +extern int aquaMenuBarHeight; + +// Name of GLX bundle for native OpenGL +extern const char *quartzOpenGLBundle; + +void QuartzReadPreferences(void); +void QuartzMessageMainThread(unsigned msg, void *data, unsigned length); +void QuartzMessageServerThread(int type, int argc, ...); +void QuartzSetWindowMenu(int nitems, const char **items, + const char *shortcuts); +void QuartzFSCapture(void); +void QuartzFSRelease(void); +int QuartzFSUseQDCursor(int depth); +void QuartzBlockHandler(void *blockData, void *pTimeout, void *pReadmask); +void QuartzWakeupHandler(void *blockData, int result, void *pReadmask); + +// Messages that can be sent to the main thread. +enum { + kQuartzServerHidden, + kQuartzServerStarted, + kQuartzServerDied, + kQuartzCursorUpdate, + kQuartzPostEvent, + kQuartzSetWindowMenu, + kQuartzSetWindowMenuCheck, + kQuartzSetFrontProcess, + kQuartzSetCanQuit +}; + +#endif /* _QUARTZCOMMON_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzCursor.h (revision 51223) @@ -0,0 +1,43 @@ +/* + * quartzCursor.h + * + * External interface for Quartz hardware cursor + */ +/* + * Copyright (c) 2001 Torrey T. Lyons and Greg Parker. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzCursor.h,v 1.2 2001/09/23 04:04:49 torrey Exp $ */ + +#ifndef QUARTZCURSOR_H +#define QUARTZCURSOR_H + +#include "screenint.h" + +Bool QuartzInitCursor(ScreenPtr pScreen); +void QuartzSuspendXCursor(ScreenPtr pScreen); +void QuartzResumeXCursor(ScreenPtr pScreen, int x, int y); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzPasteboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzPasteboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/quartzPasteboard.h (revision 51223) @@ -0,0 +1,45 @@ +/* + QuartzPasteboard.h + + Mac OS X pasteboard <-> X cut buffer + Greg Parker gparker@cs.stanford.edu March 8, 2001 +*/ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/bundle/quartzPasteboard.h,v 1.1 2001/03/15 22:24:27 torrey Exp $ */ + +#ifndef _QUARTZPASTEBOARD_H +#define _QUARTZPASTEBOARD_H + +// Aqua->X +void QuartzReadPasteboard(); +char * QuartzReadCocoaPasteboard(void); // caller must free string + +// X->Aqua +void QuartzWritePasteboard(); +void QuartzWriteCocoaPasteboard(char *text); + +#endif /* _QUARTZPASTEBOARD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/queryst.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/queryst.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/queryst.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef QUERYST_H +#define QUERYST_H 1 + +int SProcXQueryDeviceState(ClientPtr /* client */ + ); + +int ProcXQueryDeviceState(ClientPtr /* client */ + ); + +void SRepXQueryDeviceState(ClientPtr /* client */ , + int /* size */ , + xQueryDeviceStateReply * /* rep */ + ); + +#endif /* QUERYST_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/randrstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/randrstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/randrstr.h (revision 51223) @@ -0,0 +1,145 @@ +/* + * $XFree86: xc/programs/Xserver/randr/randrstr.h,v 1.5 2002/09/29 23:39:45 keithp Exp $ + * + * Copyright © 2000 Compaq Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Compaq not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Compaq makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * COMPAQ DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL COMPAQ BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _RANDRSTR_H_ +#define _RANDRSTR_H_ + +#include + +typedef struct _rrScreenRate { + int rate; + Bool referenced; + Bool oldReferenced; +} RRScreenRate, *RRScreenRatePtr; + +typedef struct _rrScreenSize { + int id; + short width, height; + short mmWidth, mmHeight; + RRScreenRatePtr pRates; + int nRates; + int nRatesInUse; + Bool referenced; + Bool oldReferenced; +} RRScreenSize, *RRScreenSizePtr; + +typedef Bool (*RRSetConfigProcPtr) (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +typedef Bool (*RRGetInfoProcPtr) (ScreenPtr pScreen, Rotation *rotations); +typedef Bool (*RRCloseScreenProcPtr) ( int i, ScreenPtr pscreen); + +typedef struct _rrScrPriv { + RRSetConfigProcPtr rrSetConfig; + RRGetInfoProcPtr rrGetInfo; + + TimeStamp lastSetTime; /* last changed by client */ + TimeStamp lastConfigTime; /* possible configs changed */ + RRCloseScreenProcPtr CloseScreen; + + /* + * Configuration information + */ + Rotation rotations; + + int nSizes; + int nSizesInUse; + RRScreenSizePtr pSizes; + + /* + * Current state + */ + Rotation rotation; + int size; + int rate; +} rrScrPrivRec, *rrScrPrivPtr; + +extern int rrPrivIndex; + +#define rrGetScrPriv(pScr) ((rrScrPrivPtr) (pScr)->devPrivates[rrPrivIndex].ptr) +#define rrScrPriv(pScr) rrScrPrivPtr pScrPriv = rrGetScrPriv(pScr) +#define SetRRScreen(s,p) ((s)->devPrivates[rrPrivIndex].ptr = (pointer) (p)) + +/* Initialize the extension */ +void +RRExtensionInit (void); + +/* + * Then, register the specific size with the screen + */ + +RRScreenSizePtr +RRRegisterSize (ScreenPtr pScreen, + short width, + short height, + short mmWidth, + short mmHeight); + +Bool RRRegisterRate (ScreenPtr pScreen, + RRScreenSizePtr pSize, + int rate); + +/* + * Finally, set the current configuration of the screen + */ + +void +RRSetCurrentConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +Bool RRScreenInit(ScreenPtr pScreen); + +Rotation +RRGetRotation (ScreenPtr pScreen); + +int +RRSetScreenConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr pSize); + +Bool +miRandRInit (ScreenPtr pScreen); + +Bool +miRRGetInfo (ScreenPtr pScreen, Rotation *rotations); + +Bool +miRRSetConfig (ScreenPtr pScreen, + Rotation rotation, + int rate, + RRScreenSizePtr size); + +Bool +miRRGetScreenInfo (ScreenPtr pScreen); + +#endif /* _RANDRSTR_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/region.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/region.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/region.h (revision 51223) @@ -0,0 +1,54 @@ +/* $Xorg: region.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#ifndef REGION_H +#define REGION_H + +#include "regionstr.h" + +#endif /* REGION_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regionstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regionstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regionstr.h (revision 51223) @@ -0,0 +1,327 @@ +/* $XdotOrg: xserver/xorg/include/regionstr.h,v 1.8 2006/03/28 00:18:31 ajax Exp $ */ +/* $Xorg: regionstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/regionstr.h,v 1.12tsi Exp $ */ + +#ifndef REGIONSTRUCT_H +#define REGIONSTRUCT_H + +typedef struct _Region RegionRec, *RegionPtr; + +#include "miscstruct.h" + +/* Return values from RectIn() */ + +#define rgnOUT 0 +#define rgnIN 1 +#define rgnPART 2 + +#define NullRegion ((RegionPtr)0) + +/* + * clip region + */ + +typedef struct _RegData { + long size; + long numRects; +/* BoxRec rects[size]; in memory but not explicitly declared */ +} RegDataRec, *RegDataPtr; + +struct _Region { + BoxRec extents; + RegDataPtr data; +}; + +extern BoxRec miEmptyBox; +extern RegDataRec miEmptyData; +extern RegDataRec miBrokenData; + +#define REGION_NIL(reg) ((reg)->data && !(reg)->data->numRects) +/* not a region */ +#define REGION_NAR(reg) ((reg)->data == &miBrokenData) +#define REGION_NUM_RECTS(reg) ((reg)->data ? (reg)->data->numRects : 1) +#define REGION_SIZE(reg) ((reg)->data ? (reg)->data->size : 0) +#define REGION_RECTS(reg) ((reg)->data ? (BoxPtr)((reg)->data + 1) \ + : &(reg)->extents) +#define REGION_BOXPTR(reg) ((BoxPtr)((reg)->data + 1)) +#define REGION_BOX(reg,i) (®ION_BOXPTR(reg)[i]) +#define REGION_TOP(reg) REGION_BOX(reg, (reg)->data->numRects) +#define REGION_END(reg) REGION_BOX(reg, (reg)->data->numRects - 1) +#define REGION_SZOF(n) (sizeof(RegDataRec) + ((n) * sizeof(BoxRec))) + +#define REGION_CREATE(_pScreen, _rect, _size) \ + miRegionCreate(_rect, _size) + +#define REGION_COPY(_pScreen, dst, src) \ + miRegionCopy(dst, src) + +#define REGION_DESTROY(_pScreen, _pReg) \ + miRegionDestroy(_pReg) + +#define REGION_INTERSECT(_pScreen, newReg, reg1, reg2) \ + miIntersect(newReg, reg1, reg2) + +#define REGION_UNION(_pScreen, newReg, reg1, reg2) \ + miUnion(newReg, reg1, reg2) + +#define REGION_SUBTRACT(_pScreen, newReg, reg1, reg2) \ + miSubtract(newReg, reg1, reg2) + +#define REGION_INVERSE(_pScreen, newReg, reg1, invRect) \ + miInverse(newReg, reg1, invRect) + +#define REGION_TRANSLATE(_pScreen, _pReg, _x, _y) \ + miTranslateRegion(_pReg, _x, _y) + +#define RECT_IN_REGION(_pScreen, _pReg, prect) \ + miRectIn(_pReg, prect) + +#define POINT_IN_REGION(_pScreen, _pReg, _x, _y, prect) \ + miPointInRegion(_pReg, _x, _y, prect) + +#define REGION_APPEND(_pScreen, dstrgn, rgn) \ + miRegionAppend(dstrgn, rgn) + +#define REGION_VALIDATE(_pScreen, badreg, pOverlap) \ + miRegionValidate(badreg, pOverlap) + +#define BITMAP_TO_REGION(_pScreen, pPix) \ + (*(_pScreen)->BitmapToRegion)(pPix) /* no mi version?! */ + +#define RECTS_TO_REGION(_pScreen, nrects, prect, ctype) \ + miRectsToRegion(nrects, prect, ctype) + +#define REGION_EQUAL(_pScreen, _pReg1, _pReg2) \ + miRegionEqual(_pReg1, _pReg2) + +#define REGION_BREAK(_pScreen, _pReg) \ + miRegionBreak(_pReg) + +#ifdef DONT_INLINE_REGION_OPS + +#define REGION_INIT(_pScreen, _pReg, _rect, _size) \ + miRegionInit(_pReg, _rect, _size) + +#define REGION_UNINIT(_pScreen, _pReg) \ + miRegionUninit(_pReg) + +#define REGION_RESET(_pScreen, _pReg, _pBox) \ + miRegionReset(_pReg, _pBox) + +#define REGION_NOTEMPTY(_pScreen, _pReg) \ + miRegionNotEmpty(_pReg) + +#define REGION_BROKEN(_pScreen, _pReg) \ + miRegionBroken(_pReg) + +#define REGION_EMPTY(_pScreen, _pReg) \ + miRegionEmpty(_pReg) + +#define REGION_EXTENTS(_pScreen, _pReg) \ + miRegionExtents(_pReg) + +#else /* inline certain simple region ops for performance */ + +#define REGION_INIT(_pScreen, _pReg, _rect, _size) \ +{ \ + if (_rect) \ + { \ + (_pReg)->extents = *(_rect); \ + (_pReg)->data = (RegDataPtr)NULL; \ + } \ + else \ + { \ + (_pReg)->extents = miEmptyBox; \ + if (((_size) > 1) && ((_pReg)->data = \ + (RegDataPtr)xalloc(REGION_SZOF(_size)))) \ + { \ + (_pReg)->data->size = (_size); \ + (_pReg)->data->numRects = 0; \ + } \ + else \ + (_pReg)->data = &miEmptyData; \ + } \ + } + + +#define REGION_UNINIT(_pScreen, _pReg) \ +{ \ + if ((_pReg)->data && (_pReg)->data->size) { \ + xfree((_pReg)->data); \ + (_pReg)->data = NULL; \ + } \ +} + +#define REGION_RESET(_pScreen, _pReg, _pBox) \ +{ \ + (_pReg)->extents = *(_pBox); \ + REGION_UNINIT(_pScreen, _pReg); \ + (_pReg)->data = (RegDataPtr)NULL; \ +} + +#define REGION_NOTEMPTY(_pScreen, _pReg) \ + !REGION_NIL(_pReg) + +#define REGION_BROKEN(_pScreen, _pReg) \ + REGION_NAR(_pReg) + +#define REGION_EMPTY(_pScreen, _pReg) \ +{ \ + REGION_UNINIT(_pScreen, _pReg); \ + (_pReg)->extents.x2 = (_pReg)->extents.x1; \ + (_pReg)->extents.y2 = (_pReg)->extents.y1; \ + (_pReg)->data = &miEmptyData; \ +} + +#define REGION_EXTENTS(_pScreen, _pReg) \ + (&(_pReg)->extents) + +#define REGION_NULL(_pScreen, _pReg) \ +{ \ + (_pReg)->extents = miEmptyBox; \ + (_pReg)->data = &miEmptyData; \ +} + +#endif /* DONT_INLINE_REGION_OPS */ + +#ifndef REGION_NULL +#define REGION_NULL(_pScreen, _pReg) \ + REGION_INIT(_pScreen, _pReg, NullBox, 1) +#endif + +/* moved from mi.h */ + +extern RegionPtr miRegionCreate( + BoxPtr /*rect*/, + int /*size*/); + +extern void miRegionInit( + RegionPtr /*pReg*/, + BoxPtr /*rect*/, + int /*size*/); + +extern void miRegionDestroy( + RegionPtr /*pReg*/); + +extern void miRegionUninit( + RegionPtr /*pReg*/); + +extern Bool miRegionCopy( + RegionPtr /*dst*/, + RegionPtr /*src*/); + +extern Bool miIntersect( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +extern Bool miUnion( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + RegionPtr /*reg2*/); + +extern Bool miRegionAppend( + RegionPtr /*dstrgn*/, + RegionPtr /*rgn*/); + +extern Bool miRegionValidate( + RegionPtr /*badreg*/, + Bool * /*pOverlap*/); + +extern RegionPtr miRectsToRegion( + int /*nrects*/, + xRectanglePtr /*prect*/, + int /*ctype*/); + +extern Bool miSubtract( + RegionPtr /*regD*/, + RegionPtr /*regM*/, + RegionPtr /*regS*/); + +extern Bool miInverse( + RegionPtr /*newReg*/, + RegionPtr /*reg1*/, + BoxPtr /*invRect*/); + +extern int miRectIn( + RegionPtr /*region*/, + BoxPtr /*prect*/); + +extern void miTranslateRegion( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/); + +extern void miRegionReset( + RegionPtr /*pReg*/, + BoxPtr /*pBox*/); + +extern Bool miRegionBreak( + RegionPtr /*pReg*/); + +extern Bool miPointInRegion( + RegionPtr /*pReg*/, + int /*x*/, + int /*y*/, + BoxPtr /*box*/); + +extern Bool miRegionEqual( + RegionPtr /*pReg1*/, + RegionPtr /*pReg2*/); + +extern Bool miRegionNotEmpty( + RegionPtr /*pReg*/); + +extern void miRegionEmpty( + RegionPtr /*pReg*/); + +extern BoxPtr miRegionExtents( + RegionPtr /*pReg*/); + +#endif /* REGIONSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/regs.h (revision 51223) @@ -0,0 +1,337 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK +#endif + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* BIG_ENDIAN */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + u32 mode; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ +#endif + u8 intno; + u8 __pad[3]; + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +private - private data pointer +x86 - X86 registers +****************************************************************************/ +typedef struct { + unsigned long mem_base; + unsigned long mem_size; + void* private; + X86EMU_regs x86; + } X86EMU_sysEnv; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +void printk(const char *fmt, ...); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/renderedge.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/renderedge.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/renderedge.h (revision 51223) @@ -0,0 +1,120 @@ +/* + * $Id: renderedge.h,v 1.3 2005/07/03 07:02:08 daniels Exp $ + * + * Copyright © 2004 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RENDEREDGE_H_ +#define _RENDEREDGE_H_ + +#include "picturestr.h" + +#define MAX_ALPHA(n) ((1 << (n)) - 1) +#define N_Y_FRAC(n) ((n) == 1 ? 1 : (1 << ((n)/2)) - 1) +#define N_X_FRAC(n) ((1 << ((n)/2)) + 1) + +#define STEP_Y_SMALL(n) (xFixed1 / N_Y_FRAC(n)) +#define STEP_Y_BIG(n) (xFixed1 - (N_Y_FRAC(n) - 1) * STEP_Y_SMALL(n)) + +#define Y_FRAC_FIRST(n) (STEP_Y_SMALL(n) / 2) +#define Y_FRAC_LAST(n) (Y_FRAC_FIRST(n) + (N_Y_FRAC(n) - 1) * STEP_Y_SMALL(n)) + +#define STEP_X_SMALL(n) (xFixed1 / N_X_FRAC(n)) +#define STEP_X_BIG(n) (xFixed1 - (N_X_FRAC(n) - 1) * STEP_X_SMALL(n)) + +#define X_FRAC_FIRST(n) (STEP_X_SMALL(n) / 2) +#define X_FRAC_LAST(n) (X_FRAC_FIRST(n) + (N_X_FRAC(n) - 1) * STEP_X_SMALL(n)) + +#define RenderSamplesX(x,n) ((n) == 1 ? 0 : (xFixedFrac (x) + X_FRAC_FIRST(n)) / STEP_X_SMALL(n)) + +/* + * An edge structure. This represents a single polygon edge + * and can be quickly stepped across small or large gaps in the + * sample grid + */ + +typedef struct { + xFixed x; + xFixed e; + xFixed stepx; + xFixed signdx; + xFixed dy; + xFixed dx; + + xFixed stepx_small; + xFixed stepx_big; + xFixed dx_small; + xFixed dx_big; +} RenderEdge; + +/* + * Step across a small sample grid gap + */ +#define RenderEdgeStepSmall(edge) { \ + edge->x += edge->stepx_small; \ + edge->e += edge->dx_small; \ + if (edge->e > 0) \ + { \ + edge->e -= edge->dy; \ + edge->x += edge->signdx; \ + } \ +} + +/* + * Step across a large sample grid gap + */ +#define RenderEdgeStepBig(edge) { \ + edge->x += edge->stepx_big; \ + edge->e += edge->dx_big; \ + if (edge->e > 0) \ + { \ + edge->e -= edge->dy; \ + edge->x += edge->signdx; \ + } \ +} + +xFixed +RenderSampleCeilY (xFixed y, int bpp); + +xFixed +RenderSampleFloorY (xFixed y, int bpp); + +void +RenderEdgeStep (RenderEdge *e, int n); + +void +RenderEdgeInit (RenderEdge *e, + int bpp, + xFixed y_start, + xFixed x_top, + xFixed y_top, + xFixed x_bot, + xFixed y_bot); + +void +RenderLineFixedEdgeInit (RenderEdge *e, + int bpp, + xFixed y, + xLineFixed *line, + int x_off, + int y_off); + +#endif /* _RENDEREDGE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/resource.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/resource.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/resource.h (revision 51223) @@ -0,0 +1,274 @@ +/* $Xorg: resource.h,v 1.5 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987, 1989 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/resource.h,v 1.11 2002/03/06 21:14:04 mvojkovi Exp $ */ + +#ifndef RESOURCE_H +#define RESOURCE_H 1 +#include "misc.h" + +/***************************************************************** + * STUFF FOR RESOURCES + *****************************************************************/ + +/* classes for Resource routines */ + +typedef unsigned long RESTYPE; + +#define RC_VANILLA ((RESTYPE)0) +#define RC_CACHED ((RESTYPE)1<<31) +#define RC_DRAWABLE ((RESTYPE)1<<30) +/* Use class RC_NEVERRETAIN for resources that should not be retained + * regardless of the close down mode when the client dies. (A client's + * event selections on objects that it doesn't own are good candidates.) + * Extensions can use this too! + */ +#define RC_NEVERRETAIN ((RESTYPE)1<<29) +#define RC_LASTPREDEF RC_NEVERRETAIN +#define RC_ANY (~(RESTYPE)0) + +/* types for Resource routines */ + +#define RT_WINDOW ((RESTYPE)1|RC_CACHED|RC_DRAWABLE) +#define RT_PIXMAP ((RESTYPE)2|RC_CACHED|RC_DRAWABLE) +#define RT_GC ((RESTYPE)3|RC_CACHED) +#undef RT_FONT +#undef RT_CURSOR +#define RT_FONT ((RESTYPE)4) +#define RT_CURSOR ((RESTYPE)5) +#define RT_COLORMAP ((RESTYPE)6) +#define RT_CMAPENTRY ((RESTYPE)7) +#define RT_OTHERCLIENT ((RESTYPE)8|RC_NEVERRETAIN) +#define RT_PASSIVEGRAB ((RESTYPE)9|RC_NEVERRETAIN) +#define RT_LASTPREDEF ((RESTYPE)9) +#define RT_NONE ((RESTYPE)0) + +/* bits and fields within a resource id */ +#define RESOURCE_AND_CLIENT_COUNT 29 /* 29 bits for XIDs */ +#if MAXCLIENTS == 64 +#define RESOURCE_CLIENT_BITS 6 +#endif +#if MAXCLIENTS == 128 +#define RESOURCE_CLIENT_BITS 7 +#endif +#if MAXCLIENTS == 256 +#define RESOURCE_CLIENT_BITS 8 +#endif +#if MAXCLIENTS == 512 +#define RESOURCE_CLIENT_BITS 9 +#endif +/* client field offset */ +#define CLIENTOFFSET (RESOURCE_AND_CLIENT_COUNT - RESOURCE_CLIENT_BITS) +/* resource field */ +#define RESOURCE_ID_MASK ((1 << CLIENTOFFSET) - 1) +/* client field */ +#define RESOURCE_CLIENT_MASK (((1 << RESOURCE_CLIENT_BITS) - 1) << CLIENTOFFSET) +/* extract the client mask from an XID */ +#define CLIENT_BITS(id) ((id) & RESOURCE_CLIENT_MASK) +/* extract the client id from an XID */ +#define CLIENT_ID(id) ((int)(CLIENT_BITS(id) >> CLIENTOFFSET)) +#define SERVER_BIT (Mask)0x40000000 /* use illegal bit */ + +#ifdef INVALID +#undef INVALID /* needed on HP/UX */ +#endif + +/* Invalid resource id */ +#define INVALID (0) + +#define BAD_RESOURCE 0xe0000000 + +typedef int (*DeleteType)( + pointer /*value*/, + XID /*id*/); + +typedef void (*FindResType)( + pointer /*value*/, + XID /*id*/, + pointer /*cdata*/); + +typedef void (*FindAllRes)( + pointer /*value*/, + XID /*id*/, + RESTYPE /*type*/, + pointer /*cdata*/); + +typedef Bool (*FindComplexResType)( + pointer /*value*/, + XID /*id*/, + pointer /*cdata*/); + +extern RESTYPE CreateNewResourceType( + DeleteType /*deleteFunc*/); + +extern RESTYPE CreateNewResourceClass(void); + +extern Bool InitClientResources( + ClientPtr /*client*/); + +extern XID FakeClientID( + int /*client*/); + +/* Quartz support on Mac OS X uses the CarbonCore + framework whose AddResource function conflicts here. */ +#ifdef __DARWIN__ +#define AddResource Darwin_X_AddResource +#endif +extern Bool AddResource( + XID /*id*/, + RESTYPE /*type*/, + pointer /*value*/); + +extern void FreeResource( + XID /*id*/, + RESTYPE /*skipDeleteFuncType*/); + +extern void FreeResourceByType( + XID /*id*/, + RESTYPE /*type*/, + Bool /*skipFree*/); + +extern Bool ChangeResourceValue( + XID /*id*/, + RESTYPE /*rtype*/, + pointer /*value*/); + +extern void FindClientResourcesByType( + ClientPtr /*client*/, + RESTYPE /*type*/, + FindResType /*func*/, + pointer /*cdata*/); + +extern void FindAllClientResources( + ClientPtr /*client*/, + FindAllRes /*func*/, + pointer /*cdata*/); + +extern void FreeClientNeverRetainResources( + ClientPtr /*client*/); + +extern void FreeClientResources( + ClientPtr /*client*/); + +extern void FreeAllResources(void); + +extern Bool LegalNewID( + XID /*id*/, + ClientPtr /*client*/); + +extern pointer LookupIDByType( + XID /*id*/, + RESTYPE /*rtype*/); + +extern pointer LookupIDByClass( + XID /*id*/, + RESTYPE /*classes*/); + +extern pointer LookupClientResourceComplex( + ClientPtr client, + RESTYPE type, + FindComplexResType func, + pointer cdata); + +/* These are the access modes that can be passed in the last parameter + * to SecurityLookupIDByType/Class. The Security extension doesn't + * currently make much use of these; they're mainly provided as an + * example of what you might need for discretionary access control. + * You can or these values together to indicate multiple modes + * simultaneously. + */ + +#define SecurityUnknownAccess 0 /* don't know intentions */ +#define SecurityReadAccess (1<<0) /* inspecting the object */ +#define SecurityWriteAccess (1<<1) /* changing the object */ +#define SecurityDestroyAccess (1<<2) /* destroying the object */ + +#ifdef XCSECURITY + +extern pointer SecurityLookupIDByType( + ClientPtr /*client*/, + XID /*id*/, + RESTYPE /*rtype*/, + Mask /*access_mode*/); + +extern pointer SecurityLookupIDByClass( + ClientPtr /*client*/, + XID /*id*/, + RESTYPE /*classes*/, + Mask /*access_mode*/); + +#else /* not XCSECURITY */ + +#define SecurityLookupIDByType(client, id, rtype, access_mode) \ + LookupIDByType(id, rtype) + +#define SecurityLookupIDByClass(client, id, classes, access_mode) \ + LookupIDByClass(id, classes) + +#endif /* XCSECURITY */ + +extern void GetXIDRange( + int /*client*/, + Bool /*server*/, + XID * /*minp*/, + XID * /*maxp*/); + +extern unsigned int GetXIDList( + ClientPtr /*client*/, + unsigned int /*count*/, + XID * /*pids*/); + +extern RESTYPE lastResourceType; +extern RESTYPE TypeMask; + +#ifdef XResExtension +extern Atom *ResourceNames; +void RegisterResourceName(RESTYPE type, char* name); +#endif + +#endif /* RESOURCE_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rgb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rgb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rgb.h (revision 51223) @@ -0,0 +1,54 @@ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: rgb.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ + +#ifndef RGB_H +#define RGB_H +typedef struct _RGB { + unsigned short red, green, blue; + } RGB; +#endif /* RGB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rlAccel.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rlAccel.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rlAccel.h (revision 51223) @@ -0,0 +1,141 @@ +/* + * Rootless Acceleration Code + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessCommon.c,v 1.4 2003/10/18 00:00:34 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "fb.h" + +/* + * rlBlt.c + */ +void +rlBlt (FbBits *srcLine, + FbStride srcStride, + int srcX, + + ScreenPtr pDstScreen, + FbBits *dstLine, + FbStride dstStride, + int dstX, + + int width, + int height, + + int alu, + FbBits pm, + int bpp, + + Bool reverse, + Bool upsidedown); + +/* + * rlCopy.c + */ +RegionPtr +rlCopyArea (DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GCPtr pGC, + int xIn, + int yIn, + int widthSrc, + int heightSrc, + int xOut, + int yOut); + +/* + * rlFill.c + */ +void +rlFill (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + int width, + int height); + +void +rlSolidBoxClipped (DrawablePtr pDrawable, + RegionPtr pClip, + int x1, + int y1, + int x2, + int y2, + FbBits and, + FbBits xor); + +/* + * rlFillRect.c + */ +void +rlPolyFillRect(DrawablePtr pDrawable, + GCPtr pGC, + int nrect, + xRectangle *prect); + +/* + * rlFillSpans.c + */ +void +rlFillSpans (DrawablePtr pDrawable, + GCPtr pGC, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted); + +/* + * rlGlyph.c + */ +void +rlImageGlyphBlt (DrawablePtr pDrawable, + GCPtr pGC, + int x, + int y, + unsigned int nglyph, + CharInfoPtr *ppciInit, + pointer pglyphBase); + +/* + * rlSolid.c + */ +void +rlSolid (ScreenPtr pScreen, + FbBits *dst, + FbStride dstStride, + int dstX, + int bpp, + + int width, + int height, + + FbBits and, + FbBits xor); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootless.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootless.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootless.h (revision 51223) @@ -0,0 +1,436 @@ +/* + * External interface to generic rootless mode + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootless.h,v 1.7 2004/07/02 01:30:33 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESS_H +#define _ROOTLESS_H + +#include "rootlessConfig.h" +#include "mi.h" +#include "gcstruct.h" + +/* + Each top-level rootless window has a one-to-one correspondence to a physical + on-screen window. The physical window is refered to as a "frame". + */ + +typedef void * RootlessFrameID; + +/* + * RootlessWindowRec + * This structure stores the per-frame data used by the rootless code. + * Each top-level X window has one RootlessWindowRec associated with it. + */ +typedef struct _RootlessWindowRec { + // Position and size includes the window border + // Position is in per-screen coordinates + int x, y; + unsigned int width, height; + unsigned int borderWidth; + + RootlessFrameID wid; // implementation specific frame id + WindowPtr win; // underlying X window + + // Valid only when drawing (ie. is_drawing is set) + char *pixelData; + int bytesPerRow; + + PixmapPtr pixmap; + PixmapPtr oldPixmap; + +#ifdef ROOTLESS_TRACK_DAMAGE + RegionRec damage; +#endif + + unsigned int is_drawing :1; // Currently drawing? + unsigned int is_reorder_pending :1; +} RootlessWindowRec, *RootlessWindowPtr; + + +/* Offset for screen-local to global coordinate transforms */ +#ifdef ROOTLESS_GLOBAL_COORDS +extern int rootlessGlobalOffsetX; +extern int rootlessGlobalOffsetY; +#endif + +/* The minimum number of bytes or pixels for which to use the + implementation's accelerated functions. */ +extern unsigned int rootless_CopyBytes_threshold; +extern unsigned int rootless_FillBytes_threshold; +extern unsigned int rootless_CompositePixels_threshold; +extern unsigned int rootless_CopyWindow_threshold; + +/* Operations used by CompositePixels */ +enum rl_composite_op_enum { + RL_COMPOSITE_SRC = 0, + RL_COMPOSITE_OVER, +}; + +/* Data formats for depth field and composite functions */ +enum rl_depth_enum { + RL_DEPTH_NIL = 0, /* null source when compositing */ + RL_DEPTH_ARGB8888, + RL_DEPTH_RGB555, + RL_DEPTH_A8, /* for masks when compositing */ + RL_DEPTH_INDEX8, +}; + +/* Macro to form the composite function for CompositePixels */ +#define RL_COMPOSITE_FUNCTION(op, src_depth, mask_depth, dest_depth) \ + (((op) << 24) | ((src_depth) << 16) \ + | ((mask_depth) << 8) | ((dest_depth) << 0)) + +/* Gravity for window contents during resizing */ +enum rl_gravity_enum { + RL_GRAVITY_NONE = 0, /* no gravity, fill everything */ + RL_GRAVITY_NORTH_WEST = 1, /* anchor to top-left corner */ + RL_GRAVITY_NORTH_EAST = 2, /* anchor to top-right corner */ + RL_GRAVITY_SOUTH_EAST = 3, /* anchor to bottom-right corner */ + RL_GRAVITY_SOUTH_WEST = 4, /* anchor to bottom-left corner */ +}; + + +/*------------------------------------------ + Rootless Implementation Functions + ------------------------------------------*/ + +/* + * Create a new frame. + * The frame is created unmapped. + * + * pFrame RootlessWindowPtr for this frame should be completely + * initialized before calling except for pFrame->wid, which + * is set by this function. + * pScreen Screen on which to place the new frame + * newX, newY Position of the frame. These will be identical to pFrame-x, + * pFrame->y unless ROOTLESS_GLOBAL_COORDS is set. + * pNewShape Shape for the frame (in frame-local coordinates). NULL for + * unshaped frames. + */ +typedef Bool (*RootlessCreateFrameProc) + (RootlessWindowPtr pFrame, ScreenPtr pScreen, int newX, int newY, + RegionPtr pNewShape); + +/* + * Destroy a frame. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + */ +typedef void (*RootlessDestroyFrameProc) + (RootlessFrameID wid); + +/* + * Move a frame on screen. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + * pScreen Screen to move the new frame to + * newX, newY New position of the frame + */ +typedef void (*RootlessMoveFrameProc) + (RootlessFrameID wid, ScreenPtr pScreen, int newX, int newY); + +/* + * Resize and move a frame. + * Drawing is stopped and all updates are flushed before this is called. + * + * wid Frame id + * pScreen Screen to move the new frame to + * newX, newY New position of the frame + * newW, newH New size of the frame + * gravity Gravity for window contents (rl_gravity_enum). This is always + * RL_GRAVITY_NONE unless ROOTLESS_RESIZE_GRAVITY is set. + */ +typedef void (*RootlessResizeFrameProc) + (RootlessFrameID wid, ScreenPtr pScreen, + int newX, int newY, unsigned int newW, unsigned int newH, + unsigned int gravity); + +/* + * Change frame ordering (AKA stacking, layering). + * Drawing is stopped before this is called. Unmapped frames are mapped by + * setting their ordering. + * + * wid Frame id + * nextWid Frame id of frame that is now above this one or NULL if this + * frame is at the top. + */ +typedef void (*RootlessRestackFrameProc) + (RootlessFrameID wid, RootlessFrameID nextWid); + +/* + * Change frame's shape. + * Drawing is stopped before this is called. + * + * wid Frame id + * pNewShape New shape for the frame (in frame-local coordinates) + * or NULL if now unshaped. + */ +typedef void (*RootlessReshapeFrameProc) + (RootlessFrameID wid, RegionPtr pNewShape); + +/* + * Unmap a frame. + * + * wid Frame id + */ +typedef void (*RootlessUnmapFrameProc) + (RootlessFrameID wid); + +/* + * Start drawing to a frame. + * Prepare a frame for direct access to its backing buffer. + * + * wid Frame id + * pixelData Address of the backing buffer (returned) + * bytesPerRow Width in bytes of the backing buffer (returned) + */ +typedef void (*RootlessStartDrawingProc) + (RootlessFrameID wid, char **pixelData, int *bytesPerRow); + +/* + * Stop drawing to a frame. + * No drawing to the frame's backing buffer will occur until drawing + * is started again. + * + * wid Frame id + * flush Flush drawing updates for this frame to the screen. This + * will always be FALSE if ROOTLESS_TRACK_DAMAGE is set. + */ +typedef void (*RootlessStopDrawingProc) + (RootlessFrameID wid, Bool flush); + +/* + * Flush drawing updates to the screen. + * Drawing is stopped before this is called. + * + * wid Frame id + * pDamage Region containing all the changed pixels in frame-lcoal + * coordinates. This is clipped to the window's clip. This + * will be NULL if ROOTLESS_TRACK_DAMAGE is not set. + */ +typedef void (*RootlessUpdateRegionProc) + (RootlessFrameID wid, RegionPtr pDamage); + +/* + * Mark damaged rectangles as requiring redisplay to screen. + * This will only be called if ROOTLESS_TRACK_DAMAGE is not set. + * + * wid Frame id + * nrects Number of damaged rectangles + * rects Array of damaged rectangles in frame-local coordinates + * shift_x, Vector to shift rectangles by + * shift_y + */ +typedef void (*RootlessDamageRectsProc) + (RootlessFrameID wid, int nrects, const BoxRec *rects, + int shift_x, int shift_y); + +/* + * Switch the window associated with a frame. (Optional) + * When a framed window is reparented, the frame is resized and set to + * use the new top-level parent. If defined this function will be called + * afterwards for implementation specific bookkeeping. + * + * pFrame Frame whose window has switched + * oldWin Previous window wrapped by this frame + */ +typedef void (*RootlessSwitchWindowProc) + (RootlessWindowPtr pFrame, WindowPtr oldWin); + +/* + * Check if window should be reordered. (Optional) + * The underlying window system may animate windows being ordered in. + * We want them to be mapped but remain ordered out until the animation + * completes. If defined this function will be called to check if a + * framed window should be reordered now. If this function returns + * FALSE, the window will still be mapped from the X11 perspective, but + * the RestackFrame function will not be called for its frame. + * + * pFrame Frame to reorder + */ +typedef Bool (*RootlessDoReorderWindowProc) + (RootlessWindowPtr pFrame); + +/* + * Copy bytes. (Optional) + * Source and destinate may overlap and the right thing should happen. + * + * width Bytes to copy per row + * height Number of rows + * src Source data + * srcRowBytes Width of source in bytes + * dst Destination data + * dstRowBytes Width of destination in bytes + */ +typedef void (*RootlessCopyBytesProc) + (unsigned int width, unsigned int height, + const void *src, unsigned int srcRowBytes, + void *dst, unsigned int dstRowBytes); + +/* + * Fill memory with 32-bit pattern. (Optional) + * + * width Bytes to fill per row + * height Number of rows + * value 32-bit pattern to fill with + * dst Destination data + * dstRowBytes Width of destination in bytes + */ +typedef void (*RootlessFillBytesProc) + (unsigned int width, unsigned int height, unsigned int value, + void *dst, unsigned int dstRowBytes); + +/* + * Composite pixels from source and mask to destination. (Optional) + * + * width, height Size of area to composite to in pizels + * function Composite function built with RL_COMPOSITE_FUNCTION + * src Source data + * srcRowBytes Width of source in bytes (Passing NULL means source + * is a single pixel. + * mask Mask data + * maskRowBytes Width of mask in bytes + * dst Destination data + * dstRowBytes Width of destination in bytes + * + * For src and dst, the first element of the array is the color data. If + * the second element is non-null it implies there is alpha data (which + * may be meshed or planar). Data without alpha is assumed to be opaque. + * + * An X11 error code is returned. + */ +typedef int (*RootlessCompositePixelsProc) + (unsigned int width, unsigned int height, unsigned int function, + void *src[2], unsigned int srcRowBytes[2], + void *mask, unsigned int maskRowBytes, + void *dst[2], unsigned int dstRowBytes[2]); + +/* + * Copy area in frame to another part of frame. (Optional) + * + * wid Frame id + * dstNrects Number of rectangles to copy + * dstRects Array of rectangles to copy + * dx, dy Number of pixels away to copy area + */ +typedef void (*RootlessCopyWindowProc) + (RootlessFrameID wid, int dstNrects, const BoxRec *dstRects, + int dx, int dy); + +/* + * Rootless implementation function list + */ +typedef struct _RootlessFrameProcs { + RootlessCreateFrameProc CreateFrame; + RootlessDestroyFrameProc DestroyFrame; + + RootlessMoveFrameProc MoveFrame; + RootlessResizeFrameProc ResizeFrame; + RootlessRestackFrameProc RestackFrame; + RootlessReshapeFrameProc ReshapeFrame; + RootlessUnmapFrameProc UnmapFrame; + + RootlessStartDrawingProc StartDrawing; + RootlessStopDrawingProc StopDrawing; + RootlessUpdateRegionProc UpdateRegion; +#ifndef ROOTLESS_TRACK_DAMAGE + RootlessDamageRectsProc DamageRects; +#endif + + /* Optional frame functions */ + RootlessSwitchWindowProc SwitchWindow; + RootlessDoReorderWindowProc DoReorderWindow; + + /* Optional acceleration functions */ + RootlessCopyBytesProc CopyBytes; + RootlessFillBytesProc FillBytes; + RootlessCompositePixelsProc CompositePixels; + RootlessCopyWindowProc CopyWindow; +} RootlessFrameProcsRec, *RootlessFrameProcsPtr; + + +/* + * Initialize rootless mode on the given screen. + */ +Bool RootlessInit(ScreenPtr pScreen, RootlessFrameProcsPtr procs); + +/* + * Initialize acceleration for rootless mode on a given screen. + * Note: RootlessAccelInit() must be called before DamageSetup() + * and RootlessInit() must be called afterwards. + */ +Bool RootlessAccelInit(ScreenPtr pScreen); + +/* + * Return the frame ID for the physical window displaying the given window. + * + * create If true and the window has no frame, attempt to create one + */ +RootlessFrameID RootlessFrameForWindow(WindowPtr pWin, Bool create); + +/* + * Return the top-level parent of a window. + * The root is the top-level parent of itself, even though the root is + * not otherwise considered to be a top-level window. + */ +WindowPtr TopLevelParent(WindowPtr pWindow); + +/* + * Prepare a window for direct access to its backing buffer. + */ +void RootlessStartDrawing(WindowPtr pWindow); + +/* + * Finish drawing to a window's backing buffer. + * + * flush If true and ROOTLESS_TRACK_DAMAGE is set, damaged areas + * are flushed to the screen. + */ +void RootlessStopDrawing(WindowPtr pWindow, Bool flush); + +/* + * Alocate a new screen pixmap. + * miCreateScreenResources does not do this properly with a null + * framebuffer pointer. + */ +void RootlessUpdateScreenPixmap(ScreenPtr pScreen); + +/* + * Reposition all windows on a screen to their correct positions. + */ +void RootlessRepositionWindows(ScreenPtr pScreen); + +#endif /* _ROOTLESS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessCommon.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessCommon.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessCommon.h (revision 51223) @@ -0,0 +1,261 @@ +/* + * Common internal rootless definitions and code + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * Copyright (c) 2002-2004 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessCommon.h,v 1.5 2004/07/02 01:30:33 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSCOMMON_H +#define _ROOTLESSCOMMON_H + +#include "rootless.h" +#include "fb.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + + +// Debug output, or not. +#ifdef ROOTLESSDEBUG +#define RL_DEBUG_MSG ErrorF +#else +#define RL_DEBUG_MSG(a, ...) +#endif + + +// Global variables +extern int rootlessGCPrivateIndex; +extern int rootlessScreenPrivateIndex; +extern int rootlessWindowPrivateIndex; + + +// RootlessGCRec: private per-gc data +typedef struct { + GCFuncs *originalFuncs; + GCOps *originalOps; +} RootlessGCRec; + + +// RootlessScreenRec: per-screen private data +typedef struct _RootlessScreenRec { + // Rootless implementation functions + RootlessFrameProcsPtr imp; + + // Wrapped screen functions + CreateScreenResourcesProcPtr CreateScreenResources; + CloseScreenProcPtr CloseScreen; + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + RestackWindowProcPtr RestackWindow; + ReparentWindowProcPtr ReparentWindow; + ChangeBorderWidthProcPtr ChangeBorderWidth; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + + CreateGCProcPtr CreateGC; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + GetImageProcPtr GetImage; + SourceValidateProcPtr SourceValidate; + + MarkOverlappedWindowsProcPtr MarkOverlappedWindows; + ValidateTreeProcPtr ValidateTree; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif + +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif + + void *pixmap_data; + unsigned int pixmap_data_size; + + void *redisplay_timer; + unsigned int redisplay_timer_set :1; + unsigned int redisplay_queued :1; + unsigned int redisplay_expired :1; +} RootlessScreenRec, *RootlessScreenPtr; + + +#undef MIN +#define MIN(x,y) ((x) < (y) ? (x) : (y)) +#undef MAX +#define MAX(x,y) ((x) > (y) ? (x) : (y)) + +// "Definition of the Porting Layer for the X11 Sample Server" says +// unwrap and rewrap of screen functions is unnecessary, but +// screen->CreateGC changes after a call to cfbCreateGC. + +#define SCREEN_UNWRAP(screen, fn) \ + screen->fn = SCREENREC(screen)->fn; + +#define SCREEN_WRAP(screen, fn) \ + SCREENREC(screen)->fn = screen->fn; \ + screen->fn = Rootless##fn + + +// Accessors for screen and window privates + +#define SCREENREC(pScreen) \ + ((RootlessScreenRec *)(pScreen)->devPrivates[rootlessScreenPrivateIndex].ptr) + +#define WINREC(pWin) \ + ((RootlessWindowRec *)(pWin)->devPrivates[rootlessWindowPrivateIndex].ptr) + + +// Call a rootless implementation function. +// Many rootless implementation functions are allowed to be NULL. +#define CallFrameProc(pScreen, proc, params) \ + if (SCREENREC(pScreen)->frameProcs.proc) { \ + RL_DEBUG_MSG("calling frame proc " #proc " "); \ + SCREENREC(pScreen)->frameProcs.proc params; \ + } + + +// BoxRec manipulators +// Copied from shadowfb + +#define TRIM_BOX(box, pGC) { \ + BoxPtr extents = &pGC->pCompositeClip->extents;\ + if(box.x1 < extents->x1) box.x1 = extents->x1; \ + if(box.x2 > extents->x2) box.x2 = extents->x2; \ + if(box.y1 < extents->y1) box.y1 = extents->y1; \ + if(box.y2 > extents->y2) box.y2 = extents->y2; \ +} + +#define TRANSLATE_BOX(box, pDraw) { \ + box.x1 += pDraw->x; \ + box.x2 += pDraw->x; \ + box.y1 += pDraw->y; \ + box.y2 += pDraw->y; \ +} + +#define TRIM_AND_TRANSLATE_BOX(box, pDraw, pGC) { \ + TRANSLATE_BOX(box, pDraw); \ + TRIM_BOX(box, pGC); \ +} + +#define BOX_NOT_EMPTY(box) \ + (((box.x2 - box.x1) > 0) && ((box.y2 - box.y1) > 0)) + + +// HUGE_ROOT and NORMAL_ROOT +// We don't want to clip windows to the edge of the screen. +// HUGE_ROOT temporarily makes the root window really big. +// This is needed as a wrapper around any function that calls +// SetWinSize or SetBorderSize which clip a window against its +// parents, including the root. + +extern RegionRec rootlessHugeRoot; + +#define HUGE_ROOT(pWin) \ + do { \ + WindowPtr w = pWin; \ + while (w->parent) \ + w = w->parent; \ + saveRoot = w->winSize; \ + w->winSize = rootlessHugeRoot; \ + } while (0) + +#define NORMAL_ROOT(pWin) \ + do { \ + WindowPtr w = pWin; \ + while (w->parent) \ + w = w->parent; \ + w->winSize = saveRoot; \ + } while (0) + + +// Returns TRUE if this window is a top-level window (i.e. child of the root) +// The root is not a top-level window. +#define IsTopLevel(pWin) \ + ((pWin) && (pWin)->parent && !(pWin)->parent->parent) + +// Returns TRUE if this window is a root window +#define IsRoot(pWin) \ + ((pWin) == WindowTable[(pWin)->drawable.pScreen->myNum]) + + +/* + * SetPixmapBaseToScreen + * Move the given pixmap's base address to where pixel (0, 0) + * would be if the pixmap's actual data started at (x, y). + * Can't access the bits before the first word of the drawable's data in + * rootless mode, so make sure our base address is always 32-bit aligned. + */ +#define SetPixmapBaseToScreen(pix, _x, _y) { \ + PixmapPtr _pPix = (PixmapPtr) (pix); \ + _pPix->devPrivate.ptr = (char *) (_pPix->devPrivate.ptr) - \ + ((int)(_x) * _pPix->drawable.bitsPerPixel/8 + \ + (int)(_y) * _pPix->devKind); \ + if (_pPix->drawable.bitsPerPixel != FB_UNIT) { \ + unsigned _diff = ((unsigned) _pPix->devPrivate.ptr) & \ + (FB_UNIT / CHAR_BIT - 1); \ + _pPix->devPrivate.ptr = (char *) (_pPix->devPrivate.ptr) - \ + _diff; \ + _pPix->drawable.x = _diff / \ + (_pPix->drawable.bitsPerPixel / CHAR_BIT); \ + } \ +} + + +// Returns TRUE if this window is visible inside a frame +// (e.g. it is visible and has a top-level or root parent) +Bool IsFramedWindow(WindowPtr pWin); + +// Routines that cause regions to get redrawn. +// DamageRegion and DamageRect are in global coordinates. +// DamageBox is in window-local coordinates. +void RootlessDamageRegion(WindowPtr pWindow, RegionPtr pRegion); +void RootlessDamageRect(WindowPtr pWindow, int x, int y, int w, int h); +void RootlessDamageBox(WindowPtr pWindow, BoxPtr pBox); +void RootlessRedisplay(WindowPtr pWindow); +void RootlessRedisplayScreen(ScreenPtr pScreen); + +void RootlessQueueRedisplay(ScreenPtr pScreen); + +// Move a window to its proper location on the screen. +void RootlessRepositionWindow(WindowPtr pWin); + +// Move the window to it's correct place in the physical stacking order. +void RootlessReorderWindow(WindowPtr pWin); + +#endif /* _ROOTLESSCOMMON_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessConfig.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessConfig.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessConfig.h (revision 51223) @@ -0,0 +1,68 @@ +/* + * Platform specific rootless configuration + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessConfig.h,v 1.1 2003/04/15 01:05:44 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSCONFIG_H +#define _ROOTLESSCONFIG_H + +#ifdef __DARWIN__ + +# define ROOTLESS_ACCEL TRUE +# define ROOTLESS_GLOBAL_COORDS TRUE +# define ROOTLESS_PROTECT_ALPHA TRUE +# define ROOTLESS_REDISPLAY_DELAY 10 +# define ROOTLESS_RESIZE_GRAVITY TRUE +# undef ROOTLESS_TRACK_DAMAGE + +/* Bit mask for alpha channel with a particular number of bits per + pixel. Note that we only care for 32bpp data. Mac OS X uses planar + alpha for 16bpp. */ +# define RootlessAlphaMask(bpp) ((bpp) == 32 ? 0xFF000000 : 0) + +#endif /* __DARWIN__ */ + +#if defined(__CYGWIN__) || defined(WIN32) + +# define ROOTLESS_ACCEL YES +# define ROOTLESS_GLOBAL_COORDS TRUE +# define ROOTLESS_PROTECT_ALPHA NO +# define ROOTLESS_REDISPLAY_DELAY 10 +# undef ROOTLESS_RESIZE_GRAVITY +# undef ROOTLESS_TRACK_DAMAGE +/*# define ROOTLESSDEBUG*/ + +# define RootlessAlphaMask(bpp) ((bpp) == 32 ? 0xFF000000 : 0) + +#endif /* __CYGWIN__ */ + +#endif /* _ROOTLESSCONFIG_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessWindow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessWindow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/rootlessWindow.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * Rootless window management + */ +/* + * Copyright (c) 2001 Greg Parker. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/rootlessWindow.h,v 1.1 2003/04/15 01:05:44 torrey Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _ROOTLESSWINDOW_H +#define _ROOTLESSWINDOW_H + +#include "rootlessCommon.h" + + +Bool RootlessCreateWindow(WindowPtr pWin); +Bool RootlessDestroyWindow(WindowPtr pWin); + +#ifdef SHAPE +void RootlessSetShape(WindowPtr pWin); +#endif // SHAPE + +Bool RootlessChangeWindowAttributes(WindowPtr pWin, unsigned long vmask); +Bool RootlessPositionWindow(WindowPtr pWin, int x, int y); +Bool RootlessRealizeWindow(WindowPtr pWin); +Bool RootlessUnrealizeWindow(WindowPtr pWin); +void RootlessRestackWindow(WindowPtr pWin, WindowPtr pOldNextSib); +void RootlessCopyWindow(WindowPtr pWin,DDXPointRec ptOldOrg,RegionPtr prgnSrc); +void RootlessMoveWindow(WindowPtr pWin,int x,int y,WindowPtr pSib,VTKind kind); +void RootlessResizeWindow(WindowPtr pWin, int x, int y, + unsigned int w, unsigned int h, WindowPtr pSib); +void RootlessReparentWindow(WindowPtr pWin, WindowPtr pPriorParent); +void RootlessPaintWindowBackground(WindowPtr pWin, RegionPtr pRegion, + int what); +void RootlessPaintWindowBorder(WindowPtr pWin, RegionPtr pRegion, + int what); +void RootlessChangeBorderWidth(WindowPtr pWin, unsigned int width); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/safeAlpha.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/safeAlpha.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/safeAlpha.h (revision 51223) @@ -0,0 +1,45 @@ +/* + * Replacement functions to protect the alpha channel + */ +/* + * Copyright (c) 2002-2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/miext/rootless/safeAlpha/safeAlpha.h,v 1.2 2003/10/18 00:00:34 torrey Exp $ */ + +#ifndef _SAFEALPHA_H +#define _SAFEALPHA_H + +#include "picturestr.h" + +void SafeAlphaPaintWindow(WindowPtr pWin, RegionPtr pRegion, int what); + +#ifdef RENDER +void +SafeAlphaComposite(CARD8 op, PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst, + INT16 xSrc, INT16 ySrc, INT16 xMask, INT16 yMask, + INT16 xDst, INT16 yDst, CARD16 width, CARD16 height); +#endif /* RENDER */ + +#endif /* _SAFEALPHA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sarea.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sarea.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sarea.h (revision 51223) @@ -0,0 +1,94 @@ +/* $XFree86: xc/programs/Xserver/GL/dri/sarea.h,v 1.11 2002/10/30 12:52:03 alanh Exp $ */ +/** + * \file sarea.h + * SAREA definitions. + * + * \author Kevin E. Martin + * \author Jens Owen + * \author Rickard E. (Rik) Faith + */ + +/* + * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/GL/dri/sarea.h,v 1.11 2002/10/30 12:52:03 alanh Exp $ */ + +#ifndef _SAREA_H_ +#define _SAREA_H_ + +#include "xf86drm.h" + +/* SAREA area needs to be at least a page */ +#if defined(__alpha__) +#define SAREA_MAX 0x2000 +#elif defined(__ia64__) +#define SAREA_MAX 0x10000 /* 64kB */ +#else +/* Intel 830M driver needs at least 8k SAREA */ +#define SAREA_MAX 0x2000 +#endif + +#define SAREA_MAX_DRAWABLES 256 + +#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 + +/** + * SAREA per drawable information. + * + * \sa _XF86DRISAREA. + */ +typedef struct _XF86DRISAREADrawable { + unsigned int stamp; + unsigned int flags; +} XF86DRISAREADrawableRec, *XF86DRISAREADrawablePtr; + +/** + * SAREA frame information. + * + * \sa _XF86DRISAREA. + */ +typedef struct _XF86DRISAREAFrame { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; +} XF86DRISAREAFrameRec, *XF86DRISAREAFramePtr; + +/** + * SAREA definition. + */ +typedef struct _XF86DRISAREA { + /** first thing is always the DRM locking structure */ + drmLock lock; + /** \todo Use readers/writer lock for drawable_lock */ + drmLock drawable_lock; + XF86DRISAREADrawableRec drawableTable[SAREA_MAX_DRAWABLES]; + XF86DRISAREAFrameRec frame; + drm_context_t dummy_context; +} XF86DRISAREARec, *XF86DRISAREAPtr; + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sco_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sco_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sco_kbd.h (revision 51223) @@ -0,0 +1,20 @@ +/* $XFree86$ */ +#ifndef SCO_KBD_HDR +#define SCO_KBD_HDR + +typedef struct { + int use_tcs; + int use_kd; + int no_nmap; + int no_emap; + int orig_getsc; + int orig_kbm; + struct termios kbdtty; + keymap_t keymap, noledmap; + uchar_t *sc_mapbuf; + uchar_t *sc_mapbuf2; +} ScoKbdPrivRec, *ScoKbdPrivPtr; + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); +#endif /* SCO_KBD_HDR */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scoasm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scoasm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scoasm.h (revision 51223) @@ -0,0 +1,143 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/scoasm.h,v 3.1 2003/08/24 17:36:49 dawes Exp $ */ + +/* + * Copyright (c) 1996 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * scoasm.h - used to define inline versions of certain functions which + * do NOT appear in sys/inline.h. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if defined(__SCO__) && defined(__USLC__) +#ifndef _SCOASM_HDR_INC +#define _SCOASM_HDR_INC + +asm void outl(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + outl (%dx) +%reg port; mem val; + movl port, %edx + movl val, %eax + outl (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + outl (%dx) +%mem port,val; + movw port, %dx + movl val, %eax + outl (%dx) +} + +asm void outw(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + data16 + outl (%dx) +%reg port; mem val; + movl port, %edx + movw val, %ax + data16 + outl (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + data16 + outl (%dx) +%mem port,val; + movw port, %dx + movw val, %ax + data16 + outl (%dx) +} + +asm void outb(port,val) +{ +%reg port,val; + movl port, %edx + movl val, %eax + outb (%dx) +%reg port; mem val; + movl port, %edx + movb val, %al + outb (%dx) +%mem port; reg val; + movw port, %dx + movl val, %eax + outb (%dx) +%mem port,val; + movw port, %dx + movb val, %al + outb (%dx) +} + +asm int inl(port) +{ +%reg port; + movl port, %edx + inl (%dx) +%mem port; + movw port, %dx + inl (%dx) +} + +asm int inw(port) +{ +%reg port; + subl %eax, %eax + movl port, %edx + data16 + inl (%dx) +%mem port; + subl %eax, %eax + movw port, %dx + data16 + inl (%dx) +} + +asm int inb(port) +{ +%reg port; + subl %eax, %eax + movl port, %edx + inb (%dx) +%mem port; + subl %eax, %eax + movw port, %dx + inb (%dx) +} + +#endif /* _SCOASM_HDR_INC */ +#endif /* __SCO__ && __USLC__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen-cfg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen-cfg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen-cfg.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/screen-cfg.h,v 1.1 2000/04/04 22:37:02 dawes Exp $ + */ + +#include "config.h" +#include "screen.h" + +#ifndef _xf86cfg_screencfg_h +#define _xf86cfg_screencfg_h + +/* + * Prototypes + */ +XtPointer ScreenConfig(XtPointer); +void ScreenDialog(XF86SetupInfo*); + +#endif /* _xf86cfg_screencfg_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screen.h (revision 51223) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/screen.h,v 1.1 2000/04/04 22:37:02 dawes Exp $ + */ + +#include "xf86config.h" +#include "config.h" + +#ifndef _xf86cfg_screen_h +#define _xf86cfg_screen_h + +/* + * Prototypes + */ +void AddScreen(xf86cfgDevice*, xf86cfgDevice*); +void RemoveScreen(xf86cfgDevice*, xf86cfgDevice*); + +void DrawScreen(Display*, Drawable, int, int, int, int, Bool, int); +void DrawScreenMask(Display*, Drawable, GC, int, int, int, int, int); +void CreateScreenWidget(xf86cfgScreen*); +void SetScreenRotate(xf86cfgScreen*); + +void AdjustScreenUI(void); +void UpdateScreenUI(void); + +#endif /* _xf86cfg_screen_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screenint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screenint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/screenint.h (revision 51223) @@ -0,0 +1,113 @@ +/* $Xorg: screenint.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/screenint.h,v 1.5 2001/12/14 19:59:56 dawes Exp $ */ + +#ifndef SCREENINT_H +#define SCREENINT_H + +#include "misc.h" + +typedef struct _PixmapFormat *PixmapFormatPtr; +typedef struct _Visual *VisualPtr; +typedef struct _Depth *DepthPtr; +typedef struct _Screen *ScreenPtr; + +extern void ResetScreenPrivates(void); + +extern int AllocateScreenPrivateIndex(void); + +extern void ResetWindowPrivates(void); + +extern int AllocateWindowPrivateIndex(void); + +extern Bool AllocateWindowPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +extern void ResetGCPrivates(void); + +extern int AllocateGCPrivateIndex(void); + +extern Bool AllocateGCPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +extern int AddScreen( + Bool (* /*pfnInit*/)( + int /*index*/, + ScreenPtr /*pScreen*/, + int /*argc*/, + char ** /*argv*/), + int /*argc*/, + char** /*argv*/); + +#ifdef PIXPRIV + +extern void ResetPixmapPrivates(void); + +extern int AllocatePixmapPrivateIndex(void); + +extern Bool AllocatePixmapPrivate( + ScreenPtr /* pScreen */, + int /* index */, + unsigned /* amount */); + +#endif /* PIXPRIV */ + +extern void ResetColormapPrivates(void); + + +typedef struct _ColormapRec *ColormapPtr; +typedef int (*InitCmapPrivFunc)(ColormapPtr, int); + +extern int AllocateColormapPrivateIndex( + InitCmapPrivFunc /* initPrivFunc */); + +#endif /* SCREENINT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scrnintstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scrnintstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/scrnintstr.h (revision 51223) @@ -0,0 +1,609 @@ +/* $Xorg: scrnintstr.h,v 1.4 2001/02/09 02:05:15 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/scrnintstr.h,v 1.12 2003/04/27 21:31:05 herrb Exp $ */ + +#ifndef SCREENINTSTRUCT_H +#define SCREENINTSTRUCT_H + +#include "screenint.h" +#include "regionstr.h" +#include "bstore.h" +#include "colormap.h" +#include "cursor.h" +#include "validate.h" +#include +#include "dix.h" + +typedef struct _PixmapFormat { + unsigned char depth; + unsigned char bitsPerPixel; + unsigned char scanlinePad; + } PixmapFormatRec; + +typedef struct _Visual { + VisualID vid; + short class; + short bitsPerRGBValue; + short ColormapEntries; + short nplanes;/* = log2 (ColormapEntries). This does not + * imply that the screen has this many planes. + * it may have more or fewer */ + unsigned long redMask, greenMask, blueMask; + int offsetRed, offsetGreen, offsetBlue; + } VisualRec; + +typedef struct _Depth { + unsigned char depth; + short numVids; + VisualID *vids; /* block of visual ids for this depth */ + } DepthRec; + + +/* + * There is a typedef for each screen function pointer so that code that + * needs to declare a screen function pointer (e.g. in a screen private + * or as a local variable) can easily do so and retain full type checking. + */ + +typedef Bool (* CloseScreenProcPtr)( + int /*index*/, + ScreenPtr /*pScreen*/); + +typedef void (* QueryBestSizeProcPtr)( + int /*class*/, + unsigned short * /*pwidth*/, + unsigned short * /*pheight*/, + ScreenPtr /*pScreen*/); + +typedef Bool (* SaveScreenProcPtr)( + ScreenPtr /*pScreen*/, + int /*on*/); + +typedef void (* GetImageProcPtr)( + DrawablePtr /*pDrawable*/, + int /*sx*/, + int /*sy*/, + int /*w*/, + int /*h*/, + unsigned int /*format*/, + unsigned long /*planeMask*/, + char * /*pdstLine*/); + +typedef void (* GetSpansProcPtr)( + DrawablePtr /*pDrawable*/, + int /*wMax*/, + DDXPointPtr /*ppt*/, + int* /*pwidth*/, + int /*nspans*/, + char * /*pdstStart*/); + +typedef void (* PointerNonInterestBoxProcPtr)( + ScreenPtr /*pScreen*/, + BoxPtr /*pBox*/); + +typedef void (* SourceValidateProcPtr)( + DrawablePtr /*pDrawable*/, + int /*x*/, + int /*y*/, + int /*width*/, + int /*height*/); + +typedef Bool (* CreateWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* DestroyWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* PositionWindowProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/); + +typedef Bool (* ChangeWindowAttributesProcPtr)( + WindowPtr /*pWindow*/, + unsigned long /*mask*/); + +typedef Bool (* RealizeWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef Bool (* UnrealizeWindowProcPtr)( + WindowPtr /*pWindow*/); + +typedef void (* RestackWindowProcPtr)( + WindowPtr /*pWindow*/, + WindowPtr /*pOldNextSib*/); + +typedef int (* ValidateTreeProcPtr)( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/); + +typedef void (* PostValidateTreeProcPtr)( + WindowPtr /*pParent*/, + WindowPtr /*pChild*/, + VTKind /*kind*/); + +typedef void (* WindowExposuresProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgn*/, + RegionPtr /*other_exposed*/); + +typedef void (* PaintWindowProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*pRegion*/, + int /*what*/); + +typedef PaintWindowProcPtr PaintWindowBackgroundProcPtr; +typedef PaintWindowProcPtr PaintWindowBorderProcPtr; + +typedef void (* CopyWindowProcPtr)( + WindowPtr /*pWindow*/, + DDXPointRec /*ptOldOrg*/, + RegionPtr /*prgnSrc*/); + +typedef void (* ClearToBackgroundProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/); + +typedef void (* ClipNotifyProcPtr)( + WindowPtr /*pWindow*/, + int /*dx*/, + int /*dy*/); + +typedef PixmapPtr (* CreatePixmapProcPtr)( + ScreenPtr /*pScreen*/, + int /*width*/, + int /*height*/, + int /*depth*/); + +typedef Bool (* DestroyPixmapProcPtr)( + PixmapPtr /*pPixmap*/); + +typedef void (* SaveDoomedAreasProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgnSave*/, + int /*xorg*/, + int /*yorg*/); + +typedef RegionPtr (* RestoreAreasProcPtr)( + WindowPtr /*pWindow*/, + RegionPtr /*prgnRestore*/); + +typedef void (* ExposeCopyProcPtr)( + WindowPtr /*pSrc*/, + DrawablePtr /*pDst*/, + GCPtr /*pGC*/, + RegionPtr /*prgnExposed*/, + int /*srcx*/, + int /*srcy*/, + int /*dstx*/, + int /*dsty*/, + unsigned long /*plane*/); + +typedef RegionPtr (* TranslateBackingStoreProcPtr)( + WindowPtr /*pWindow*/, + int /*windx*/, + int /*windy*/, + RegionPtr /*oldClip*/, + int /*oldx*/, + int /*oldy*/); + +typedef RegionPtr (* ClearBackingStoreProcPtr)( + WindowPtr /*pWindow*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/, + Bool /*generateExposures*/); + +typedef void (* DrawGuaranteeProcPtr)( + WindowPtr /*pWindow*/, + GCPtr /*pGC*/, + int /*guarantee*/); + +typedef Bool (* RealizeFontProcPtr)( + ScreenPtr /*pScreen*/, + FontPtr /*pFont*/); + +typedef Bool (* UnrealizeFontProcPtr)( + ScreenPtr /*pScreen*/, + FontPtr /*pFont*/); + +typedef void (* ConstrainCursorProcPtr)( + ScreenPtr /*pScreen*/, + BoxPtr /*pBox*/); + +typedef void (* CursorLimitsProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + BoxPtr /*pHotBox*/, + BoxPtr /*pTopLeftBox*/); + +typedef Bool (* DisplayCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef Bool (* RealizeCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef Bool (* UnrealizeCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/); + +typedef void (* RecolorCursorProcPtr)( + ScreenPtr /*pScreen*/, + CursorPtr /*pCursor*/, + Bool /*displayed*/); + +typedef Bool (* SetCursorPositionProcPtr)( + ScreenPtr /*pScreen*/, + int /*x*/, + int /*y*/, + Bool /*generateEvent*/); + +typedef Bool (* CreateGCProcPtr)( + GCPtr /*pGC*/); + +typedef Bool (* CreateColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* DestroyColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* InstallColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef void (* UninstallColormapProcPtr)( + ColormapPtr /*pColormap*/); + +typedef int (* ListInstalledColormapsProcPtr) ( + ScreenPtr /*pScreen*/, + XID* /*pmaps */); + +typedef void (* StoreColorsProcPtr)( + ColormapPtr /*pColormap*/, + int /*ndef*/, + xColorItem * /*pdef*/); + +typedef void (* ResolveColorProcPtr)( + unsigned short* /*pred*/, + unsigned short* /*pgreen*/, + unsigned short* /*pblue*/, + VisualPtr /*pVisual*/); + +typedef RegionPtr (* BitmapToRegionProcPtr)( + PixmapPtr /*pPix*/); + +typedef void (* SendGraphicsExposeProcPtr)( + ClientPtr /*client*/, + RegionPtr /*pRgn*/, + XID /*drawable*/, + int /*major*/, + int /*minor*/); + +typedef void (* ScreenBlockHandlerProcPtr)( + int /*screenNum*/, + pointer /*blockData*/, + pointer /*pTimeout*/, + pointer /*pReadmask*/); + +typedef void (* ScreenWakeupHandlerProcPtr)( + int /*screenNum*/, + pointer /*wakeupData*/, + unsigned long /*result*/, + pointer /*pReadMask*/); + +typedef Bool (* CreateScreenResourcesProcPtr)( + ScreenPtr /*pScreen*/); + +typedef Bool (* ModifyPixmapHeaderProcPtr)( + PixmapPtr /*pPixmap*/, + int /*width*/, + int /*height*/, + int /*depth*/, + int /*bitsPerPixel*/, + int /*devKind*/, + pointer /*pPixData*/); + +typedef PixmapPtr (* GetWindowPixmapProcPtr)( + WindowPtr /*pWin*/); + +typedef void (* SetWindowPixmapProcPtr)( + WindowPtr /*pWin*/, + PixmapPtr /*pPix*/); + +typedef PixmapPtr (* GetScreenPixmapProcPtr)( + ScreenPtr /*pScreen*/); + +typedef void (* SetScreenPixmapProcPtr)( + PixmapPtr /*pPix*/); + +typedef void (* MarkWindowProcPtr)( + WindowPtr /*pWin*/); + +typedef Bool (* MarkOverlappedWindowsProcPtr)( + WindowPtr /*parent*/, + WindowPtr /*firstChild*/, + WindowPtr * /*pLayerWin*/); + +typedef Bool (* ChangeSaveUnderProcPtr)( + WindowPtr /*pLayerWin*/, + WindowPtr /*firstChild*/); + +typedef void (* PostChangeSaveUnderProcPtr)( + WindowPtr /*pLayerWin*/, + WindowPtr /*firstChild*/); + +typedef void (* MoveWindowProcPtr)( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + WindowPtr /*pSib*/, + VTKind /*kind*/); + +typedef void (* ResizeWindowProcPtr)( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + WindowPtr /*pSib*/ +); + +typedef WindowPtr (* GetLayerWindowProcPtr)( + WindowPtr /*pWin*/ +); + +typedef void (* HandleExposuresProcPtr)( + WindowPtr /*pWin*/); + +typedef void (* ReparentWindowProcPtr)( + WindowPtr /*pWin*/, + WindowPtr /*pPriorParent*/); + +#ifdef SHAPE +typedef void (* SetShapeProcPtr)( + WindowPtr /*pWin*/); +#endif /* SHAPE */ + +typedef void (* ChangeBorderWidthProcPtr)( + WindowPtr /*pWin*/, + unsigned int /*width*/); + +typedef void (* MarkUnrealizedWindowProcPtr)( + WindowPtr /*pChild*/, + WindowPtr /*pWin*/, + Bool /*fromConfigure*/); + +typedef struct _Screen { + int myNum; /* index of this instance in Screens[] */ + ATOM id; + short width, height; + short mmWidth, mmHeight; + short numDepths; + unsigned char rootDepth; + DepthPtr allowedDepths; + unsigned long rootVisual; + unsigned long defColormap; + short minInstalledCmaps, maxInstalledCmaps; + char backingStoreSupport, saveUnderSupport; + unsigned long whitePixel, blackPixel; + unsigned long rgf; /* array of flags; she's -- HUNGARIAN */ + GCPtr GCperDepth[MAXFORMATS+1]; + /* next field is a stipple to use as default in + a GC. we don't build default tiles of all depths + because they are likely to be of a color + different from the default fg pixel, so + we don't win anything by building + a standard one. + */ + PixmapPtr PixmapPerDepth[1]; + pointer devPrivate; + short numVisuals; + VisualPtr visuals; + int WindowPrivateLen; + unsigned *WindowPrivateSizes; + unsigned totalWindowSize; + int GCPrivateLen; + unsigned *GCPrivateSizes; + unsigned totalGCSize; + + /* Random screen procedures */ + + CloseScreenProcPtr CloseScreen; + QueryBestSizeProcPtr QueryBestSize; + SaveScreenProcPtr SaveScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PointerNonInterestBoxProcPtr PointerNonInterestBox; + SourceValidateProcPtr SourceValidate; + + /* Window Procedures */ + + CreateWindowProcPtr CreateWindow; + DestroyWindowProcPtr DestroyWindow; + PositionWindowProcPtr PositionWindow; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + RealizeWindowProcPtr RealizeWindow; + UnrealizeWindowProcPtr UnrealizeWindow; + ValidateTreeProcPtr ValidateTree; + PostValidateTreeProcPtr PostValidateTree; + WindowExposuresProcPtr WindowExposures; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + ClearToBackgroundProcPtr ClearToBackground; + ClipNotifyProcPtr ClipNotify; + RestackWindowProcPtr RestackWindow; + + /* Pixmap procedures */ + + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + + /* Backing store procedures */ + + SaveDoomedAreasProcPtr SaveDoomedAreas; + RestoreAreasProcPtr RestoreAreas; + ExposeCopyProcPtr ExposeCopy; + TranslateBackingStoreProcPtr TranslateBackingStore; + ClearBackingStoreProcPtr ClearBackingStore; + DrawGuaranteeProcPtr DrawGuarantee; + /* + * A read/write copy of the lower level backing store vector is needed now + * that the functions can be wrapped. + */ + BSFuncRec BackingStoreFuncs; + + /* Font procedures */ + + RealizeFontProcPtr RealizeFont; + UnrealizeFontProcPtr UnrealizeFont; + + /* Cursor Procedures */ + + ConstrainCursorProcPtr ConstrainCursor; + CursorLimitsProcPtr CursorLimits; + DisplayCursorProcPtr DisplayCursor; + RealizeCursorProcPtr RealizeCursor; + UnrealizeCursorProcPtr UnrealizeCursor; + RecolorCursorProcPtr RecolorCursor; + SetCursorPositionProcPtr SetCursorPosition; + + /* GC procedures */ + + CreateGCProcPtr CreateGC; + + /* Colormap procedures */ + + CreateColormapProcPtr CreateColormap; + DestroyColormapProcPtr DestroyColormap; + InstallColormapProcPtr InstallColormap; + UninstallColormapProcPtr UninstallColormap; + ListInstalledColormapsProcPtr ListInstalledColormaps; + StoreColorsProcPtr StoreColors; + ResolveColorProcPtr ResolveColor; + + /* Region procedures */ + + BitmapToRegionProcPtr BitmapToRegion; + SendGraphicsExposeProcPtr SendGraphicsExpose; + + /* os layer procedures */ + + ScreenBlockHandlerProcPtr BlockHandler; + ScreenWakeupHandlerProcPtr WakeupHandler; + + pointer blockData; + pointer wakeupData; + + /* anybody can get a piece of this array */ + DevUnion *devPrivates; + + CreateScreenResourcesProcPtr CreateScreenResources; + ModifyPixmapHeaderProcPtr ModifyPixmapHeader; + + GetWindowPixmapProcPtr GetWindowPixmap; + SetWindowPixmapProcPtr SetWindowPixmap; + GetScreenPixmapProcPtr GetScreenPixmap; + SetScreenPixmapProcPtr SetScreenPixmap; + + PixmapPtr pScratchPixmap; /* scratch pixmap "pool" */ + +#ifdef PIXPRIV + int PixmapPrivateLen; + unsigned int *PixmapPrivateSizes; + unsigned int totalPixmapSize; +#endif + + MarkWindowProcPtr MarkWindow; + MarkOverlappedWindowsProcPtr MarkOverlappedWindows; + ChangeSaveUnderProcPtr ChangeSaveUnder; + PostChangeSaveUnderProcPtr PostChangeSaveUnder; + MoveWindowProcPtr MoveWindow; + ResizeWindowProcPtr ResizeWindow; + GetLayerWindowProcPtr GetLayerWindow; + HandleExposuresProcPtr HandleExposures; + ReparentWindowProcPtr ReparentWindow; + +#ifdef SHAPE + SetShapeProcPtr SetShape; +#endif /* SHAPE */ + + ChangeBorderWidthProcPtr ChangeBorderWidth; + MarkUnrealizedWindowProcPtr MarkUnrealizedWindow; + +} ScreenRec; + +typedef struct _ScreenInfo { + int imageByteOrder; + int bitmapScanlineUnit; + int bitmapScanlinePad; + int bitmapBitOrder; + int numPixmapFormats; + PixmapFormatRec + formats[MAXFORMATS]; + int arraySize; + int numScreens; + ScreenPtr screens[MAXSCREENS]; + int numVideoScreens; +} ScreenInfo; + +extern ScreenInfo screenInfo; + +extern void InitOutput( + ScreenInfo * /*pScreenInfo*/, + int /*argc*/, + char ** /*argv*/); + +#endif /* SCREENINTSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selectev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selectev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selectev.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SELECTEV_H +#define SELECTEV_H 1 + +int SProcXSelectExtensionEvent(ClientPtr /* client */ + ); + +int ProcXSelectExtensionEvent(ClientPtr /* client */ + ); + +#endif /* SELECTEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selection.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selection.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/selection.h (revision 51223) @@ -0,0 +1,69 @@ +/* $Xorg: selection.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ + +#ifndef SELECTION_H +#define SELECTION_H 1 + +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ + +#include "dixstruct.h" +/* + * + * Selection data structures + */ + +typedef struct _Selection { + Atom selection; + TimeStamp lastTimeChanged; + Window window; + WindowPtr pWin; + ClientPtr client; +} Selection; + +#endif /* SELECTION_H */ + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sendexev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sendexev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sendexev.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SENDEXEV_H +#define SENDEXEV_H 1 + +int SProcXSendExtensionEvent(ClientPtr /* client */ + ); + +int ProcXSendExtensionEvent(ClientPtr /* client */ + ); + +#endif /* SENDEXEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/servermd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/servermd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/servermd.h (revision 51223) @@ -0,0 +1,583 @@ +/* $XFree86: xc/programs/Xserver/include/servermd.h,v 3.56tsi Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $Xorg: servermd.h,v 1.3 2000/08/17 19:53:31 cpqbld Exp $ */ +/* $XdotOrg: xserver/xorg/include/servermd.h,v 1.9 2005/11/15 00:29:23 ajax Exp $ */ + +#ifndef SERVERMD_H +#define SERVERMD_H 1 + +/* + * Machine dependent values: + * GLYPHPADBYTES should be chosen with consideration for the space-time + * trade-off. Padding to 0 bytes means that there is no wasted space + * in the font bitmaps (both on disk and in memory), but that access of + * the bitmaps will cause odd-address memory references. Padding to + * 2 bytes would ensure even address memory references and would + * be suitable for a 68010-class machine, but at the expense of wasted + * space in the font bitmaps. Padding to 4 bytes would be good + * for real 32 bit machines, etc. Be sure that you tell the font + * compiler what kind of padding you want because its defines are + * kept separate from this. See server/include/font.h for how + * GLYPHPADBYTES is used. + * + * Along with this, you should choose an appropriate value for + * GETLEFTBITS_ALIGNMENT, which is used in ddx/mfb/maskbits.h. This + * constant choses what kind of memory references are guarenteed during + * font access; either 1, 2 or 4, for byte, word or longword access, + * respectively. For instance, if you have decided to to have + * GLYPHPADBYTES == 4, then it is pointless for you to have a + * GETLEFTBITS_ALIGNMENT > 1, because the padding of the fonts has already + * guarenteed you that your fonts are longword aligned. On the other + * hand, even if you have chosen GLYPHPADBYTES == 1 to save space, you may + * also decide that the computing involved in aligning the pointer is more + * costly than an odd-address access; you choose GETLEFTBITS_ALIGNMENT == 1. + * + * Next, choose the tuning parameters which are appropriate for your + * hardware; these modify the behaviour of the raw frame buffer code + * in ddx/mfb and ddx/cfb. Defining these incorrectly will not cause + * the server to run incorrectly, but defining these correctly will + * cause some noticeable speed improvements: + * + * AVOID_MEMORY_READ - (8-bit cfb only) + * When stippling pixels on the screen (polytext and pushpixels), + * don't read long words from the display and mask in the + * appropriate values. Rather, perform multiple byte/short/long + * writes as appropriate. This option uses many more instructions + * but runs much faster when the destination is much slower than + * the CPU and at least 1 level of write buffer is availible (2 + * is much better). Defined currently for SPARC and MIPS. + * + * FAST_CONSTANT_OFFSET_MODE - (cfb and mfb) + * This define is used on machines which have no auto-increment + * addressing mode, but do have an effectively free constant-offset + * addressing mode. Currently defined for MIPS and SPARC, even though + * I remember the cg6 as performing better without it (cg3 definitely + * performs better with it). + * + * LARGE_INSTRUCTION_CACHE - + * This define increases the number of times some loops are + * unrolled. On 68020 machines (with 256 bytes of i-cache), + * this define will slow execution down as instructions miss + * the cache frequently. On machines with real i-caches, this + * reduces loop overhead, causing a slight performance improvement. + * Currently defined for MIPS and SPARC + * + * FAST_UNALIGNED_READS - + * For machines with more memory bandwidth than CPU, this + * define uses unaligned reads for 8-bit BitBLT instead of doing + * aligned reads and combining the results with shifts and + * logical-ors. Currently defined for 68020 and vax. + * PLENTIFUL_REGISTERS - + * For machines with > 20 registers. Currently used for + * unrolling the text painting code a bit more. Currently + * defined for MIPS. + * SHARED_IDCACHE - + * For non-Harvard RISC machines, those which share the same + * CPU memory bus for instructions and data. This unrolls some + * solid fill loops which are otherwise best left rolled up. + * Currently defined for SPARC. + */ + +#ifdef vax + +#define IMAGE_BYTE_ORDER LSBFirst /* Values for the VAX only */ +#define BITMAP_BIT_ORDER LSBFirst +#define GLYPHPADBYTES 1 +#define GETLEFTBITS_ALIGNMENT 4 +#define FAST_UNALIGNED_READS + +#endif /* vax */ + +#ifdef __arm32__ + +#define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#define LARGE_INSTRUCTION_CACHE +#define AVOID_MEMORY_READ + +#endif /* __arm32__ */ + +#if defined (hpux) || defined __hppa__ + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 /* to make fb work */ +#define GETLEFTBITS_ALIGNMENT 1 /* PA forces longs to 4 */ + /* byte boundries */ +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* hpux || __hppa__ */ + +#if defined(__powerpc__) || defined(__ppc__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +/* XXX Should this be for Lynx only? */ +#ifdef Lynx +#define BITMAP_SCANLINE_UNIT 8 +#endif + +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define PLENTIFUL_REGISTERS +#define AVOID_MEMORY_READ + +#define FAST_MEMCPY + +#endif /* PowerPC */ + +#if defined(__sh__) + +#if defined(__BIG_ENDIAN__) +# define IMAGE_BYTE_ORDER MSBFirst +# define BITMAP_BIT_ORDER MSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#else +# define IMAGE_BYTE_ORDER LSBFirst +# define BITMAP_BIT_ORDER LSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#endif + +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* SuperH */ + + +#if (defined(sun) && (defined(__sparc) || defined(sparc))) || \ + (defined(__uxp__) && (defined(sparc) || defined(mc68000))) || \ + defined(__sparc__) || defined(__mc68000__) + +#if defined(__sparc) || defined(__sparc__) +# if !defined(sparc) +# define sparc 1 +# endif +#endif + +#if defined(sun386) || defined(sun5) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the SUN only */ +# define BITMAP_BIT_ORDER LSBFirst +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the SUN only */ +# define BITMAP_BIT_ORDER MSBFirst +#endif + +#ifdef sparc +# define AVOID_MEMORY_READ +# define LARGE_INSTRUCTION_CACHE +# define FAST_CONSTANT_OFFSET_MODE +# define SHARED_IDCACHE +#endif + +#ifdef mc68020 +#define FAST_UNALIGNED_READS +#endif + +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#endif /* sun && !(i386 && SVR4) */ + + +#if defined(AIXV3) + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the RISC/6000 */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define PLENTIFUL_REGISTERS +#define AVOID_MEMORY_READ + +#define FAST_MEMCPY +#endif /* AIXV3 */ + +#if defined(ibm032) || defined (ibm) + +#ifdef i386 +# define IMAGE_BYTE_ORDER LSBFirst /* Value for PS/2 only */ +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the RT only*/ +#endif +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 1 +#define GETLEFTBITS_ALIGNMENT 4 +/* ibm pcc doesn't understand pragmas. */ + +#ifdef i386 +#define BITMAP_SCANLINE_UNIT 8 +#endif + +#endif /* ibm */ + +#if defined (M4310) || defined(M4315) || defined(M4317) || defined(M4319) || defined(M4330) + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for Pegasus only */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define FAST_UNALIGNED_READS + +#endif /* tektronix */ + +#ifdef macII + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the MacII only */ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +/* might want FAST_UNALIGNED_READS for frame buffers with < 1us latency */ + +#endif /* macII */ + +#if (defined(mips) || defined(__mips)) && !defined(sgi) + +#if defined(MIPSEL) || defined(__MIPSEL__) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the PMAX only */ +# define BITMAP_BIT_ORDER LSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#else +# define IMAGE_BYTE_ORDER MSBFirst /* Values for the MIPS only */ +# define BITMAP_BIT_ORDER MSBFirst +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +#endif + +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif /* mips */ + +#if defined(__alpha) || defined(__alpha__) || defined(__alphaCross) +# define IMAGE_BYTE_ORDER LSBFirst /* Values for the Alpha only */ + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define FAST_CONSTANT_OFFSET_MODE +# define LARGE_INSTRUCTION_CACHE +# define PLENTIFUL_REGISTERS + +#endif /* alpha */ + +#if defined (linux) && defined (__s390__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define BITMAP_SCANLINE_UNIT 8 +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_UNALIGNED_READ + +#define FAST_MEMCPY + +#endif /* linux/s390 */ + +#if defined (linux) && defined (__s390x__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#define BITMAP_SCANLINE_UNIT 8 +#define LARGE_INSTRUCTION_CACHE +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_UNALIGNED_READ + +#define FAST_MEMCPY +#endif /* linux/s390x */ + + +#if defined(__ia64__) || defined(ia64) +# define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define FAST_CONSTANT_OFFSET_MODE +# define LARGE_INSTRUCTION_CACHE +# define PLENTIFUL_REGISTERS + +#endif /* ia64 */ + +#if defined(__amd64__) || defined(amd64) || defined(__amd64) +# define IMAGE_BYTE_ORDER LSBFirst + +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif + +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif + +# define GLYPHPADBYTES 4 +# define GETLEFTBITS_ALIGNMENT 1 +# define LARGE_INSTRUCTION_CACHE +# define FAST_CONSTANT_OFFSET_MODE +/* ???? */ +# define FAST_UNALIGNED_READS +#endif /* AMD64 */ + +#ifdef stellar + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the stellar only*/ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 4 +#define IMAGE_BUFSIZE (64*1024) +/* + * Use SysV random number generator. + */ +#define random rand + +#endif /* stellar */ + +#ifdef luna + +#define IMAGE_BYTE_ORDER MSBFirst /* Values for the OMRON only*/ +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#ifndef mc68000 +#define FAST_CONSTANT_OFFSET_MODE +#define AVOID_MEMORY_READ +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS +#endif + +#endif /* luna */ + +#if (defined(SVR4) && defined(i386)) || \ + defined(__alpha__) || defined(__alpha) || \ + defined(__i386__) || defined(__i386) || \ + defined(__UNIXOS2__) || \ + defined(__OS2ELF__) || \ + defined(__QNX__) || \ + defined(__s390x__) || defined(__s390__) + +#ifndef IMAGE_BYTE_ORDER +#define IMAGE_BYTE_ORDER LSBFirst +#endif + +#ifndef BITMAP_BIT_ORDER +# if defined(XF86MONOVGA) || defined(XF86VGA16) || defined(XF86MONO) +# define BITMAP_BIT_ORDER MSBFirst +# else +# define BITMAP_BIT_ORDER LSBFirst +# endif +#endif + +#ifndef BITMAP_SCANLINE_UNIT +# if defined(XF86MONOVGA) || defined(XF86VGA16) +# define BITMAP_SCANLINE_UNIT 8 +# endif +#endif + +#ifndef GLYPHPADBYTES +#define GLYPHPADBYTES 4 +#endif + +#define GETLEFTBITS_ALIGNMENT 1 +#define AVOID_MEMORY_READ +#ifdef XSVGA +#define AVOID_GLYPHBLT +#define FAST_CONSTANT_OFFSET_MODE +#define FAST_MEMCPY +#define NO_ONE_RECT +#endif + +#endif /* SVR4 / BSD / i386 */ + +#if defined (linux) && defined (__mc68000__) + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define FAST_UNALIGNED_READS +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 + +#endif /* linux/m68k */ + +#ifdef sgi + +#define IMAGE_BYTE_ORDER MSBFirst +#define BITMAP_BIT_ORDER MSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#define AVOID_MEMORY_READ +#define FAST_CONSTANT_OFFSET_MODE +#define LARGE_INSTRUCTION_CACHE +#define PLENTIFUL_REGISTERS + +#endif + +/* linux on the Compaq Itsy */ +#if defined(linux) && defined(__arm__) +#define IMAGE_BYTE_ORDER LSBFirst +#define BITMAP_BIT_ORDER LSBFirst +#define GLYPHPADBYTES 4 +#define GETLEFTBITS_ALIGNMENT 1 +#endif + +/* size of buffer to use with GetImage, measured in bytes. There's obviously + * a trade-off between the amount of stack (or whatever ALLOCATE_LOCAL gives + * you) used and the number of times the ddx routine has to be called. + */ +#ifndef IMAGE_BUFSIZE +#define IMAGE_BUFSIZE (64*1024) +#endif + +/* pad scanline to a longword */ +#ifndef BITMAP_SCANLINE_UNIT +#define BITMAP_SCANLINE_UNIT 32 +#endif + +#ifndef BITMAP_SCANLINE_PAD +#define BITMAP_SCANLINE_PAD 32 +#define LOG2_BITMAP_PAD 5 +#define LOG2_BYTES_PER_SCANLINE_PAD 2 +#endif + +/* + * This returns the number of padding units, for depth d and width w. + * For bitmaps this can be calculated with the macros above. + * Other depths require either grovelling over the formats field of the + * screenInfo or hardwired constants. + */ + +typedef struct _PaddingInfo { + int padRoundUp; /* pixels per pad unit - 1 */ + int padPixelsLog2; /* log 2 (pixels per pad unit) */ + int padBytesLog2; /* log 2 (bytes per pad unit) */ + int notPower2; /* bitsPerPixel not a power of 2 */ + int bytesPerPixel; /* only set when notPower2 is TRUE */ + int bitsPerPixel; /* bits per pixel */ +} PaddingInfo; +extern PaddingInfo PixmapWidthPaddingInfo[]; + +/* The only portable way to get the bpp from the depth is to look it up */ +#define BitsPerPixel(d) (PixmapWidthPaddingInfo[d].bitsPerPixel) + +#define PixmapWidthInPadUnits(w, d) \ + (PixmapWidthPaddingInfo[d].notPower2 ? \ + (((int)(w) * PixmapWidthPaddingInfo[d].bytesPerPixel + \ + PixmapWidthPaddingInfo[d].bytesPerPixel) >> \ + PixmapWidthPaddingInfo[d].padBytesLog2) : \ + ((int)((w) + PixmapWidthPaddingInfo[d].padRoundUp) >> \ + PixmapWidthPaddingInfo[d].padPixelsLog2)) + +/* + * Return the number of bytes to which a scanline of the given + * depth and width will be padded. + */ +#define PixmapBytePad(w, d) \ + (PixmapWidthInPadUnits(w, d) << PixmapWidthPaddingInfo[d].padBytesLog2) + +#define BitmapBytePad(w) \ + (((int)((w) + BITMAP_SCANLINE_PAD - 1) >> LOG2_BITMAP_PAD) << LOG2_BYTES_PER_SCANLINE_PAD) + +#define PixmapWidthInPadUnitsProto(w, d) PixmapWidthInPadUnits(w, d) +#define PixmapBytePadProto(w, d) PixmapBytePad(w, d) +#define BitmapBytePadProto(w) BitmapBytePad(w) + +#endif /* SERVERMD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/set.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/set.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/set.h (revision 51223) @@ -0,0 +1,150 @@ +/* $Xorg: set.h,v 1.4 2001/02/09 02:05:27 xorgcvs Exp $ */ + +/* + +Copyright 1995, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + +*/ +/* $XFree86$ */ + +/* + A Set Abstract Data Type (ADT) for the RECORD Extension + David P. Wiggins + 7/25/95 + + The RECORD extension server code needs to maintain sets of numbers + that designate protocol message types. In most cases the interval of + numbers starts at 0 and does not exceed 255, but in a few cases (minor + opcodes of extension requests) the maximum is 65535. This disparity + suggests that a single set representation may not be suitable for all + sets, especially given that server memory is precious. We introduce a + set ADT to hide implementation differences so that multiple + simultaneous set representations can exist. A single interface is + presented to the set user regardless of the implementation in use for + a particular set. + + The existing RECORD SI appears to require only four set operations: + create (given a list of members), destroy, see if a particular number + is a member of the set, and iterate over the members of a set. Though + many more set operations are imaginable, to keep the code space down, + we won't provide any more operations than are needed. + + The following types and functions/macros define the ADT. +*/ + +/* an interval of set members */ +typedef struct { + CARD16 first; + CARD16 last; +} RecordSetInterval; + +typedef struct _RecordSetRec *RecordSetPtr; /* primary set type */ + +typedef void *RecordSetIteratePtr; + +/* table of function pointers for set operations. + set users should never declare a variable of this type. +*/ +typedef struct { + void (*DestroySet)( + RecordSetPtr pSet +); + unsigned long (*IsMemberOfSet)( + RecordSetPtr pSet, + int possible_member +); + RecordSetIteratePtr (*IterateSet)( + RecordSetPtr pSet, + RecordSetIteratePtr pIter, + RecordSetInterval *interval +); +} RecordSetOperations; + +/* "base class" for sets. + set users should never declare a variable of this type. + */ +typedef struct _RecordSetRec { + RecordSetOperations *ops; +} RecordSetRec; + +RecordSetPtr RecordCreateSet( + RecordSetInterval *intervals, + int nintervals, + void *pMem, + int memsize +); +/* + RecordCreateSet creates and returns a new set having members specified + by intervals and nintervals. nintervals is the number of RecordSetInterval + structures pointed to by intervals. The elements belonging to the new + set are determined as follows. For each RecordSetInterval structure, the + elements between first and last inclusive are members of the new set. + If a RecordSetInterval's first field is greater than its last field, the + results are undefined. It is valid to create an empty set (nintervals == + 0). If RecordCreateSet returns NULL, the set could not be created due + to resource constraints. +*/ + +int RecordSetMemoryRequirements( + RecordSetInterval * /*pIntervals*/, + int /*nintervals*/, + int * /*alignment*/ +); + +#define RecordDestroySet(_pSet) \ + /* void */ (*_pSet->ops->DestroySet)(/* RecordSetPtr */ _pSet) +/* + RecordDestroySet frees all resources used by _pSet. _pSet should not be + used after it is destroyed. +*/ + +#define RecordIsMemberOfSet(_pSet, _m) \ + /* unsigned long */ (*_pSet->ops->IsMemberOfSet)(/* RecordSetPtr */ _pSet, \ + /* int */ _m) +/* + RecordIsMemberOfSet returns a non-zero value if _m is a member of + _pSet, else it returns zero. +*/ + +#define RecordIterateSet(_pSet, _pIter, _interval) \ + /* RecordSetIteratePtr */ (*_pSet->ops->IterateSet)(/* RecordSetPtr */ _pSet,\ + /* RecordSetIteratePtr */ _pIter, /* RecordSetInterval */ _interval) +/* + RecordIterateSet returns successive intervals of members of _pSet. If + _pIter is NULL, the first interval of set members is copied into _interval. + The return value should be passed as _pIter in the next call to + RecordIterateSet to obtain the next interval. When the return value is + NULL, there were no more intervals in the set, and nothing is copied into + the _interval parameter. Intervals appear in increasing numerical order + with no overlap between intervals. As such, the list of intervals produced + by RecordIterateSet may not match the list of intervals that were passed + in RecordCreateSet. Typical usage: + + pIter = NULL; + while (pIter = RecordIterateSet(pSet, pIter, &interval)) + { + process interval; + } +*/ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setbmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setbmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setbmap.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETBMAP_H +#define SETBMAP_H 1 + +int SProcXSetDeviceButtonMapping(ClientPtr /* client */ + ); + +int ProcXSetDeviceButtonMapping(ClientPtr /* client */ + ); + +void SRepXSetDeviceButtonMapping(ClientPtr /* client */ , + int /* size */ , + xSetDeviceButtonMappingReply * /* rep */ + ); + +#endif /* SETBMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setdval.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setdval.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setdval.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETDVAL_H +#define SETDVAL_H 1 + +int SProcXSetDeviceValuators(ClientPtr /* client */ + ); + +int ProcXSetDeviceValuators(ClientPtr /* client */ + ); + +void SRepXSetDeviceValuators(ClientPtr /* client */ , + int /* size */ , + xSetDeviceValuatorsReply * /* rep */ + ); + +#endif /* SETDVAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setfocus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setfocus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setfocus.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETFOCUS_H +#define SETFOCUS_H 1 + +int SProcXSetDeviceFocus(ClientPtr /* client */ + ); + +int ProcXSetDeviceFocus(ClientPtr /* client */ + ); + +#endif /* SETFOCUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmmap.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETMMAP_H +#define SETMMAP_H 1 + +int SProcXSetDeviceModifierMapping(ClientPtr /* client */ + ); + +int ProcXSetDeviceModifierMapping(ClientPtr /* client */ + ); + +void SRepXSetDeviceModifierMapping(ClientPtr /* client */ , + int /* size */ , + xSetDeviceModifierMappingReply * /* rep */ + ); + +#endif /* SETMMAP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/setmode.h (revision 51223) @@ -0,0 +1,44 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SETMODE_H +#define SETMODE_H 1 + +int SProcXSetDeviceMode(ClientPtr /* client */ + ); + +int ProcXSetDeviceMode(ClientPtr /* client */ + ); + +void SRepXSetDeviceMode(ClientPtr /* client */ , + int /* size */ , + xSetDeviceModeReply * /* rep */ + ); + +#endif /* SETMODE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadow.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadow.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadow.h (revision 51223) @@ -0,0 +1,186 @@ +/* + * $XFree86: xc/programs/Xserver/miext/shadow/shadow.h,v 1.6tsi Exp $ + * + * Copyright © 2000 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SHADOW_H_ +#define _SHADOW_H_ + +#include "scrnintstr.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +#include "damage.h" +#include "damagestr.h" +typedef struct _shadowBuf *shadowBufPtr; + +typedef void (*ShadowUpdateProc) (ScreenPtr pScreen, + shadowBufPtr pBuf); + +#define SHADOW_WINDOW_RELOCATE 1 +#define SHADOW_WINDOW_READ 2 +#define SHADOW_WINDOW_WRITE 4 + +typedef void *(*ShadowWindowProc) (ScreenPtr pScreen, + CARD32 row, + CARD32 offset, + int mode, + CARD32 *size, + void *closure); + +/* BC hack: do not move the damage member. see shadow.c for explanation. */ +typedef struct _shadowBuf { + DamagePtr pDamage; + ShadowUpdateProc update; + ShadowWindowProc window; + RegionRec damage; + PixmapPtr pPixmap; + void *closure; + int randr; + + /* screen wrappers */ + GetImageProcPtr GetImage; + CloseScreenProcPtr CloseScreen; +} shadowBufRec; + +/* Match defines from randr extension */ +#define SHADOW_ROTATE_0 1 +#define SHADOW_ROTATE_90 2 +#define SHADOW_ROTATE_180 4 +#define SHADOW_ROTATE_270 8 +#define SHADOW_ROTATE_ALL (SHADOW_ROTATE_0|SHADOW_ROTATE_90|\ + SHADOW_ROTATE_180|SHADOW_ROTATE_270) +#define SHADOW_REFLECT_X 16 +#define SHADOW_REFLECT_Y 32 +#define SHADOW_REFLECT_ALL (SHADOW_REFLECT_X|SHADOW_REFLECT_Y) + +extern int shadowScrPrivateIndex; + +#define shadowGetBuf(pScr) ((shadowBufPtr) (pScr)->devPrivates[shadowScrPrivateIndex].ptr) +#define shadowBuf(pScr) shadowBufPtr pBuf = shadowGetBuf(pScr) +#define shadowDamage(pBuf) DamageRegion(pBuf->pDamage) + +Bool +shadowSetup (ScreenPtr pScreen); + +Bool +shadowAdd (ScreenPtr pScreen, + PixmapPtr pPixmap, + ShadowUpdateProc update, + ShadowWindowProc window, + int randr, + void *closure); + +void +shadowRemove (ScreenPtr pScreen, PixmapPtr pPixmap); + +shadowBufPtr +shadowFindBuf (WindowPtr pWindow); + +Bool +shadowInit (ScreenPtr pScreen, ShadowUpdateProc update, ShadowWindowProc window); + +void * +shadowAlloc (int width, int height, int bpp); + +void +shadowUpdatePacked (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdatePlanar4 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdatePlanar4x8 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotatePacked (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_90YX (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_90 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_180 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16_270YX (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32_270 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate8 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate16 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +shadowUpdateRotate32 (ScreenPtr pScreen, + shadowBufPtr pBuf); + +typedef void (* shadowUpdateProc)(ScreenPtr, shadowBufPtr); + +shadowUpdateProc shadowUpdatePackedWeak(void); +shadowUpdateProc shadowUpdatePlanar4Weak(void); +shadowUpdateProc shadowUpdatePlanar4x8Weak(void); +shadowUpdateProc shadowUpdateRotatePackedWeak(void); + +#endif /* _SHADOW_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadowfb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadowfb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shadowfb.h (revision 51223) @@ -0,0 +1,44 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/shadowfb/shadowfb.h,v 1.3 2002/10/16 22:12:54 alanh Exp $ */ + +#ifndef _SHADOWFB_H +#define _SHADOWFB_H + +#include "xf86str.h" + +/* + * User defined callback function. Passed a pointer to the ScrnInfo struct, + * the number of dirty rectangles, and a pointer to the first dirty rectangle + * in the array. + */ +typedef void (*RefreshAreaFuncPtr)(ScrnInfoPtr, int, BoxPtr); + +/* + * ShadowFBInit initializes the shadowfb subsystem. refreshArea is a pointer + * to a user supplied callback function. This function will be called after + * any operation that modifies the framebuffer. The newly dirtied rectangles + * are passed to the callback. + * + * Returns FALSE in the event of an error. + */ +Bool +ShadowFBInit ( + ScreenPtr pScreen, + RefreshAreaFuncPtr refreshArea +); + +/* + * ShadowFBInit2 is a more featureful refinement of the original shadowfb. + * ShadowFBInit2 allows you to specify two callbacks, one to be called + * immediately before an operation that modifies the framebuffer, and another + * to be called immediately after. + * + * Returns FALSE in the event of an error + */ +Bool +ShadowFBInit2 ( + ScreenPtr pScreen, + RefreshAreaFuncPtr preRefreshArea, + RefreshAreaFuncPtr postRefreshArea +); + +#endif /* _SHADOWFB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shmint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shmint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shmint.h (revision 51223) @@ -0,0 +1,44 @@ +/* + * $Id: shmint.h,v 3.2 2005/04/20 18:30:29 clee Exp $ + * + * Copyright © 2003 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SHMINT_H_ +#define _SHMINT_H_ + +#define _XSHM_SERVER_ +#include + +#include "screenint.h" +#include "pixmap.h" +#include "gc.h" + +void +ShmRegisterFuncs(ScreenPtr pScreen, ShmFuncsPtr funcs); + +void +ShmSetPixmapFormat(ScreenPtr pScreen, int format); + +void +ShmRegisterFbFuncs(ScreenPtr pScreen); + +#endif /* _SHMINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpack.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpack.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpack.h (revision 51223) @@ -0,0 +1,188 @@ +/* + * $XFree86: xc/programs/Xserver/miext/shadow/shrotpack.h,v 1.3 2001/05/29 04:54:13 keithp Exp $ + * + * Copyright © 2000 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Thanks to Daniel Chemko for making the 90 and 180 + * orientations work. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include + +#include +#include "scrnintstr.h" +#include "windowstr.h" +#include +#include "dixfontstr.h" +#include +#include "mi.h" +#include "regionstr.h" +#include "globals.h" +#include "gcstruct.h" +#include "shadow.h" +#include "fb.h" + +#define DANDEBUG 0 + +#if ROTATE == 270 + +#define SCRLEFT(x,y,w,h) (pScreen->height - ((y) + (h))) +#define SCRY(x,y,w,h) (x) +#define SCRWIDTH(x,y,w,h) (h) +#define FIRSTSHA(x,y,w,h) (((y) + (h) - 1) * shaStride + (x)) +#define STEPDOWN(x,y,w,h) ((w)--) +#define NEXTY(x,y,w,h) ((x)++) +#define SHASTEPX(stride) -(stride) +#define SHASTEPY(stride) (1) + +#elif ROTATE == 90 + +#define SCRLEFT(x,y,w,h) (y) +#define SCRY(x,y,w,h) (pScreen->width - ((x) + (w)) - 1) +#define SCRWIDTH(x,y,w,h) (h) +#define FIRSTSHA(x,y,w,h) ((y) * shaStride + (x + w - 1)) +#define STEPDOWN(x,y,w,h) ((w)--) +#define NEXTY(x,y,w,h) ((void)(x)) +#define SHASTEPX(stride) (stride) +#define SHASTEPY(stride) (-1) + +#elif ROTATE == 180 + +#define SCRLEFT(x,y,w,h) (pScreen->width - ((x) + (w))) +#define SCRY(x,y,w,h) (pScreen->height - ((y) + (h)) - 1) +#define SCRWIDTH(x,y,w,h) (w) +#define FIRSTSHA(x,y,w,h) ((y + h - 1) * shaStride + (x + w - 1)) +#define STEPDOWN(x,y,w,h) ((h)--) +#define NEXTY(x,y,w,h) ((void)(y)) +#define SHASTEPX(stride) (-1) +#define SHASTEPY(stride) -(stride) + +#else + +#define SCRLEFT(x,y,w,h) (x) +#define SCRY(x,y,w,h) (y) +#define SCRWIDTH(x,y,w,h) (w) +#define FIRSTSHA(x,y,w,h) ((y) * shaStride + (x)) +#define STEPDOWN(x,y,w,h) ((h)--) +#define NEXTY(x,y,w,h) ((y)++) +#define SHASTEPX(stride) (1) +#define SHASTEPY(stride) (stride) + +#endif + +void +FUNC (ScreenPtr pScreen, + shadowBufPtr pBuf) +{ + RegionPtr damage = shadowDamage (pBuf); + PixmapPtr pShadow = pBuf->pPixmap; + int nbox = REGION_NUM_RECTS (damage); + BoxPtr pbox = REGION_RECTS (damage); + FbBits *shaBits; + Data *shaBase, *shaLine, *sha; + FbStride shaStride; + int scrBase, scrLine, scr; + int shaBpp; + int shaXoff, shaYoff; /* XXX assumed to be zero */ + int x, y, w, h, width; + int i; + Data *winBase = NULL, *win; + CARD32 winSize; + + fbGetDrawable (&pShadow->drawable, shaBits, shaStride, shaBpp, shaXoff, shaYoff); + shaBase = (Data *) shaBits; + shaStride = shaStride * sizeof (FbBits) / sizeof (Data); +#if (DANDEBUG > 1) + ErrorF ("-> Entering Shadow Update:\r\n |- Origins: pShadow=%x, pScreen=%x, damage=%x\r\n |- Metrics: shaStride=%d, shaBase=%x, shaBpp=%d\r\n | \n", pShadow, pScreen, damage, shaStride, shaBase, shaBpp); +#endif + while (nbox--) + { + x = pbox->x1; + y = pbox->y1; + w = (pbox->x2 - pbox->x1); + h = pbox->y2 - pbox->y1; + +#if (DANDEBUG > 2) + ErrorF (" |-> Redrawing box - Metrics: X=%d, Y=%d, Width=%d, Height=%d\n", x, y, w, h); +#endif + scrLine = SCRLEFT(x,y,w,h); + shaLine = shaBase + FIRSTSHA(x,y,w,h); + + while (STEPDOWN(x,y,w,h)) + { + winSize = 0; + scrBase = 0; + width = SCRWIDTH(x,y,w,h); + scr = scrLine; + sha = shaLine; +#if (DANDEBUG > 3) + ErrorF (" | |-> StepDown - Metrics: width=%d, scr=%x, sha=%x\n", width, scr, sha); +#endif + while (width) + { + /* how much remains in this window */ + i = scrBase + winSize - scr; + if (i <= 0 || scr < scrBase) + { + winBase = (Data *) (*pBuf->window) (pScreen, + SCRY(x,y,w,h), + scr * sizeof (Data), + SHADOW_WINDOW_WRITE, + &winSize, + pBuf->closure); + if(!winBase) + return; + scrBase = scr; + winSize /= sizeof (Data); + i = winSize; +#if(DANDEBUG > 4) + ErrorF (" | | |-> Starting New Line - Metrics: winBase=%x, scrBase=%x, winSize=%d\r\n | | | Xstride=%d, Ystride=%d, w=%d h=%d\n", winBase, scrBase, winSize, SHASTEPX(shaStride), SHASTEPY(shaStride), w, h); +#endif + } + win = winBase + (scr - scrBase); + if (i > width) + i = width; + width -= i; + scr += i; +#if(DANDEBUG > 5) + ErrorF (" | | |-> Writing Line - Metrics: win=%x, sha=%x\n", win, sha); +#endif + while (i--) + { +#if(DANDEBUG > 6) + ErrorF (" | | |-> Writing Pixel - Metrics: win=%x, sha=%d, remaining=%d\n", win, sha, i); +#endif + *win++ = *sha; + sha += SHASTEPX(shaStride); + } /* i */ + } /* width */ + shaLine += SHASTEPY(shaStride); + NEXTY(x,y,w,h); + } /* STEPDOWN */ + pbox++; + } /* nbox */ +} Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpackYX.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpackYX.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/shrotpackYX.h (revision 51223) @@ -0,0 +1,162 @@ +/* + * $Id: shrotpackYX.h,v 1.2 2005/08/08 06:25:22 keithp Exp $ + * + * Copyright © 2004 Philip Blundell + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Philip Blundell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Philip Blundell makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * PHILIP BLUNDELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL PHILIP BLUNDELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include "scrnintstr.h" +#include "windowstr.h" +#include "dixfontstr.h" +#include "mi.h" +#include "regionstr.h" +#include "globals.h" +#include "gcstruct.h" +#include "shadow.h" +#include "fb.h" + +#if ROTATE == 270 + +#define WINSTEPX(stride) (stride) +#define WINSTART(x,y) (((pScreen->height - 1) - y) + (x * winStride)) +#define WINSTEPY() -1 + +#elif ROTATE == 90 + +#define WINSTEPX(stride) (-stride) +#define WINSTEPY() 1 +#define WINSTART(x,y) (((pScreen->width - 1 - x) * winStride) + y) + +#else + +#error This rotation is not supported here + +#endif + +#ifdef __arm__ +#define PREFETCH +#endif + +void +FUNC (ScreenPtr pScreen, + shadowBufPtr pBuf); + +void +FUNC (ScreenPtr pScreen, + shadowBufPtr pBuf) +{ + RegionPtr damage = shadowDamage(pBuf); + PixmapPtr pShadow = pBuf->pPixmap; + int nbox = REGION_NUM_RECTS (damage); + BoxPtr pbox = REGION_RECTS (damage); + FbBits *shaBits; + Data *shaBase, *shaLine, *sha; + FbStride shaStride, winStride; + int shaBpp; + int shaXoff, shaYoff; /* XXX assumed to be zero */ + int x, y, w, h; + Data *winBase, *win, *winLine; + CARD32 winSize; + + fbGetDrawable (&pShadow->drawable, shaBits, shaStride, shaBpp, shaXoff, shaYoff); + shaBase = (Data *) shaBits; + shaStride = shaStride * sizeof (FbBits) / sizeof (Data); + + winBase = (Data *) (*pBuf->window) (pScreen, 0, 0, + SHADOW_WINDOW_WRITE, + &winSize, pBuf->closure); + winStride = (Data *) (*pBuf->window) (pScreen, 1, 0, + SHADOW_WINDOW_WRITE, + &winSize, pBuf->closure) - winBase; + + while (nbox--) + { + x = pbox->x1; + y = pbox->y1; + w = (pbox->x2 - pbox->x1); + h = pbox->y2 - pbox->y1; + + shaLine = shaBase + (y * shaStride) + x; +#ifdef PREFETCH + __builtin_prefetch (shaLine); +#endif + winLine = winBase + WINSTART(x, y); + + while (h--) + { + sha = shaLine; + win = winLine; + + while (sha < (shaLine + w - 16)) + { +#ifdef PREFETCH + __builtin_prefetch (sha + shaStride); +#endif + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + *win = *sha++; + win += WINSTEPX(winStride); + } + + while (sha < (shaLine + w)) + { + *win = *sha++; + win += WINSTEPX(winStride); + } + + y++; + shaLine += shaStride; + winLine += WINSTEPY(); + } + pbox++; + } /* nbox */ +} Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/singlesize.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/singlesize.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/singlesize.h (revision 51223) @@ -0,0 +1,60 @@ +/* $XFree86$ */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _singlesize_h_ +#define _singlesize_h_ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#include "indirect_size.h" + +extern GLint __glReadPixels_size(GLenum format, GLenum type, + GLint width, GLint height); +extern GLint __glGetMap_size(GLenum pname, GLenum query); +extern GLint __glGetMapdv_size(GLenum target, GLenum query); +extern GLint __glGetMapfv_size(GLenum target, GLenum query); +extern GLint __glGetMapiv_size(GLenum target, GLenum query); +extern GLint __glGetPixelMap_size(GLenum map); +extern GLint __glGetPixelMapfv_size(GLenum map); +extern GLint __glGetPixelMapuiv_size(GLenum map); +extern GLint __glGetPixelMapusv_size(GLenum map); +extern GLint __glGetTexImage_size(GLenum target, GLint level, GLenum format, + GLenum type, GLint width, GLint height, + GLint depth); + +#endif /* _singlesize_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/site.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/site.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/site.h (revision 51223) @@ -0,0 +1,139 @@ +/* $Xorg: site.h,v 1.6 2001/02/09 02:05:16 xorgcvs Exp $ */ +/************************************************************ + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +********************************************************/ +/* $XFree86: xc/programs/Xserver/include/site.h,v 1.8 2001/12/19 21:37:35 dawes Exp $ */ + +#ifndef SITE_H +#define SITE_H +/* + * The vendor string identifies the vendor responsible for the + * server executable. + */ +#ifndef VENDOR_STRING +#define VENDOR_STRING "The X.Org Group" +#endif + +/* + * The vendor release number identifies, for the purpose of submitting + * traceable bug reports, the release number of software produced + * by the vendor. + */ +#ifndef VENDOR_RELEASE +#define VENDOR_RELEASE 6600 +#endif + +/* + * The following constants are provided solely as a last line of defense. The + * normal build ALWAYS overrides them using a special rule given in + * server/dix/Imakefile. If you want to change either of these constants, + * you should set the DefaultFontPath or DefaultRGBDatabase configuration + * parameters. + * DO NOT CHANGE THESE VALUES OR THE DIX IMAKEFILE! + */ +#ifndef COMPILEDDEFAULTFONTPATH +#define COMPILEDDEFAULTFONTPATH "/usr/lib/X11/fonts/misc/" +#endif +#ifndef RGB_DB +#define RGB_DB "/usr/lib/X11/rgb" +#endif + +/* + * The following constants contain default values for all of the variables + * that can be initialized on the server command line or in the environment. + */ +#define COMPILEDDEFAULTFONT "fixed" +#define COMPILEDCURSORFONT "cursor" +#ifndef COMPILEDDISPLAYCLASS +#define COMPILEDDISPLAYCLASS "MIT-unspecified" +#endif +#define DEFAULT_TIMEOUT 60 /* seconds */ +#define DEFAULT_KEYBOARD_CLICK 0 +#define DEFAULT_BELL 50 +#define DEFAULT_BELL_PITCH 400 +#define DEFAULT_BELL_DURATION 100 +#ifdef XKB +#define DEFAULT_AUTOREPEAT TRUE +#else +#define DEFAULT_AUTOREPEAT FALSE +#endif +#define DEFAULT_AUTOREPEATS {\ + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\ + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + +#define DEFAULT_LEDS 0x0 /* all off */ +#define DEFAULT_LEDS_MASK 0xffffffff /* 32 */ +#define DEFAULT_INT_RESOLUTION 1000 +#define DEFAULT_INT_MIN_VALUE 0 +#define DEFAULT_INT_MAX_VALUE 100 +#define DEFAULT_INT_DISPLAYED 0 + +#define DEFAULT_PTR_NUMERATOR 2 +#define DEFAULT_PTR_DENOMINATOR 1 +#define DEFAULT_PTR_THRESHOLD 4 + +#define DEFAULT_SCREEN_SAVER_TIME (10 * (60 * 1000)) +#define DEFAULT_SCREEN_SAVER_INTERVAL (10 * (60 * 1000)) +#define DEFAULT_SCREEN_SAVER_BLANKING PreferBlanking +#define DEFAULT_SCREEN_SAVER_EXPOSURES AllowExposures +#ifndef NOLOGOHACK +#define DEFAULT_LOGO_SCREEN_SAVER 1 +#endif +#ifndef DEFAULT_ACCESS_CONTROL +#define DEFAULT_ACCESS_CONTROL TRUE +#endif + +/* Default logging parameters. */ +#ifndef DEFAULT_LOG_VERBOSITY +#define DEFAULT_LOG_VERBOSITY 0 +#endif +#ifndef DEFAULT_LOG_FILE_VERBOSITY +#define DEFAULT_LOG_FILE_VERBOSITY 3 +#endif + +#endif /* SITE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sleepuntil.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sleepuntil.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sleepuntil.h (revision 51223) @@ -0,0 +1,47 @@ +/* $XFree86: xc/programs/Xserver/Xext/sleepuntil.h,v 1.2 2003/11/17 22:20:27 dawes Exp $ */ +/* + * Copyright (C) 2001 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _SLEEPUNTIL_H_ +#define _SLEEPUNTIL_H_ 1 + +#include "dix.h" + +extern int ClientSleepUntil( + ClientPtr client, + TimeStamp *revive, + void (*notifyFunc)( + ClientPtr /* client */, + pointer /* closure */ + ), + pointer Closure +); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/spooler.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/spooler.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/spooler.h (revision 51223) @@ -0,0 +1,76 @@ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef SPOOLER_H +#define SPOOLER_H 1 + +/* $Xorg: spooler.h,v 1.1 2003/09/14 1:19:56 gisburn Exp $ */ +/* +Copyright (c) 2003-2004 Roland Mainz + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the names of the copyright holders shall +not be used in advertising or otherwise to promote the sale, use or other +dealings in this Software without prior written authorization from said +copyright holders. +*/ + +/* + * Define platform-specific default spooler type + */ +#if defined(sun) +#define XPDEFAULTSPOOLERNAMELIST "solaris" +#elif defined(AIXV4) +#define XPDEFAULTSPOOLERNAMELIST "aix4" +#elif defined(hpux) +#define XPDEFAULTSPOOLERNAMELIST "hpux" +#elif defined(__osf__) +#define XPDEFAULTSPOOLERNAMELIST "osf" +#elif defined(__uxp__) +#define XPDEFAULTSPOOLERNAMELIST "uxp" +#elif defined(CSRG_BASED) || defined(linux) +/* ToDo: This should be "cups:bsd" in the future, but for now + * the search order first-bsd-then-cups is better for backwards + * compatibility. + */ +#define XPDEFAULTSPOOLERNAMELIST "bsd:cups" +#else +#define XPDEFAULTSPOOLERNAMELIST "other" +#endif + +typedef struct +{ + const char *name; + const char *list_queues_command; + const char *spool_command; +} XpSpoolerType, *XpSpoolerTypePtr; + +/* prototypes */ +extern XpSpoolerTypePtr XpSpoolerNameToXpSpoolerType(char *name); +extern void XpSetSpoolerTypeNameList(char *namelist); +extern char *XpGetSpoolerTypeNameList(void); + +/* global vars */ +extern XpSpoolerTypePtr spooler_type; +extern XpSpoolerType xpstm[]; + +#endif /* !SPOOLER_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stip68kgnu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stip68kgnu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stip68kgnu.h (revision 51223) @@ -0,0 +1,123 @@ +/* + * $Xorg: stip68kgnu.h,v 1.4 2001/02/09 02:04:39 xorgcvs Exp $ + * +Copyright 1990, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + * + * Author: Keith Packard, MIT X Consortium + */ +/* $XFree86: xc/programs/Xserver/cfb/stip68kgnu.h,v 3.3 2001/01/17 22:36:37 dawes Exp $ */ + +/* + * Stipple stack macro for 68k GCC + */ + +#define STIPPLE(addr,stipple,value,width,count,shift) \ + __asm volatile ( \ + "lea 5f,%/a1\n\ + moveq #28,%/d2\n\ + addl %2,%/d2\n\ + moveq #28,%/d3\n\ + subql #4,%2\n\ + negl %2\n\ +1:\n\ + movel %0,%/a0\n\ + addl %6,%0\n\ + movel %3@+,%/d1\n\ + jeq 3f\n\ + movel %/d1,%/d0\n\ + lsrl %/d2,%/d0\n\ + lsll #5,%/d0\n\ + lsll %2,%/d1\n\ + jmp %/a1@(%/d0:l)\n\ +2:\n\ + addl #4,%/a0\n\ + movel %/d1,%/d0\n\ + lsrl %/d3,%/d0\n\ + lsll #5,%/d0\n\ + lsll #4,%/d1\n\ + jmp %/a1@(%/d0:l)\n\ +5:\n\ + jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x20\n\ + moveb %5,%/a0@(3)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x40\n\ + moveb %5,%/a0@(2)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x60\n\ + movew %5,%/a0@(2)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f\n\ + . = 5b + 0x80\n\ + moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xa0\n\ + moveb %5,%/a0@(3) ; moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xc0\n\ + movew %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0xe0\n\ + movew %5,%/a0@(2) ; moveb %5,%/a0@(1)\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x100\n\ + moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x120\n\ + moveb %5,%/a0@(3) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x140\n\ + moveb %5,%/a0@(2) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x160\n\ + movew %5,%/a0@(2) ; moveb %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x180\n\ + movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1a0\n\ + moveb %5,%/a0@(3) ; movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1c0\n\ + moveb %5,%/a0@(2) ; movew %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; dbra %1,1b ; jra 4f ;\n\ + . = 5b + 0x1e0\n\ + movel %5,%/a0@\n\ + andl %/d1,%/d1 ; jne 2b ; \n\ +3: dbra %1,1b ; \n\ +4:\n"\ + : "=a" (addr), /* %0 */ \ + "=d" (count), /* %1 */ \ + "=d" (shift), /* %2 */ \ + "=a" (stipple) /* %3 */ \ + : "0" (addr), /* %4 */ \ + "d" (value), /* %5 */ \ + "a" (width), /* %6 */ \ + "1" (count-1), /* %7 */ \ + "2" (shift), /* %8 */ \ + "3" (stipple) /* %9 */ \ + : /* ctemp */ "d0", \ + /* c */ "d1", \ + /* lshift */ "d2", \ + /* rshift */ "d3", \ + /* atemp */ "a0", \ + /* case */ "a1") Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stubs.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stubs.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/stubs.h (revision 51223) @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/stubs.h,v 1.2 2000/10/23 21:16:52 tsi Exp $ + */ + +#ifndef _xf86cfg_stubs_h +#define _xf86cfg_stubs_h + +#include + +int ErrorF(const char*, ...); +int VErrorF(const char*, va_list); +#if defined(USE_MODULES) +extern int xf86Verbose; +#endif + +#endif /* _xf86cfg_stubs_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sun_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sun_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sun_kbd.h (revision 51223) @@ -0,0 +1,72 @@ +/* Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, and/or sell copies of the Software, and to permit persons + * to whom the Software is furnished to do so, provided that the above + * copyright notice(s) and this permission notice appear in all copies of + * the Software and that both the above copyright notice(s) and this + * permission notice appear in supporting documentation. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT + * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL + * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING + * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION + * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Except as contained in this notice, the name of a copyright holder + * shall not be used in advertising or otherwise to promote the sale, use + * or other dealings in this Software without prior written authorization + * of the copyright holder. + */ + +#ifndef _XORG_SUN_KBD_H_ +#define _XORG_SUN_KBD_H_ + +/* + * Keyboard common implementation routines shared by "keyboard" driver + * in sun_io.c and "kbd" driver in sun_kbd.c + */ + +typedef struct { + int kbdFD; + const char * devName; + int ktype; /* Keyboard type from KIOCTYPE */ + Bool kbdActive; /* Have we set kbd modes for X? */ + int otranslation; /* Original translation mode */ + int odirect; /* Original "direct" mode setting */ + unsigned char oleds; /* Original LED state */ + const char * strmod; /* Streams module pushed on kbd device */ + const char * audioDevName; /* Audio device path to use for bell + or NULL to use keyboard beeper */ + enum {AB_INITIALIZING, AB_NORMAL} audioState; + const unsigned char *keyMap; +} sunKbdPrivRec, *sunKbdPrivPtr; + +/* sun_kbd.c */ +extern int sunKbdOpen (const char *devName, pointer options); +extern int sunKbdInit (sunKbdPrivPtr priv, int kbdFD, + const char *devName, pointer options); +extern int sunKbdOn (sunKbdPrivPtr priv); +extern int sunKbdOff (sunKbdPrivPtr priv); + +extern void sunKbdSoundBell (sunKbdPrivPtr priv, + int loudness, int pitch, int duration); + +extern void sunKbdSetLeds (sunKbdPrivPtr priv, int leds); +extern int sunKbdGetLeds (sunKbdPrivPtr priv); +extern void sunKbdSetRepeat (sunKbdPrivPtr priv, char rad); + +/* sun_kbdEv.c */ +#include +extern void sunPostKbdEvent (int ktype, Firm_event *event); + +extern const unsigned char *sunGetKbdMapping(int ktype); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swaprep.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swaprep.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swaprep.h (revision 51223) @@ -0,0 +1,322 @@ +/* $XFree86: xc/programs/Xserver/include/swaprep.h,v 3.0 1996/04/15 11:34:34 dawes Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef SWAPREP_H +#define SWAPREP_H 1 + +extern void Swap32Write( + ClientPtr /* pClient */, + int /* size */, + CARD32 * /* pbuf */); + +extern void CopySwap32Write( + ClientPtr /* pClient */, + int /* size */, + CARD32 * /* pbuf */); + +extern void CopySwap16Write( + ClientPtr /* pClient */, + int /* size */, + short * /* pbuf */); + +extern void SGenericReply( + ClientPtr /* pClient */, + int /* size */, + xGenericReply * /* pRep */); + +extern void SGetWindowAttributesReply( + ClientPtr /* pClient */, + int /* size */, + xGetWindowAttributesReply * /* pRep */); + +extern void SGetGeometryReply( + ClientPtr /* pClient */, + int /* size */, + xGetGeometryReply * /* pRep */); + +extern void SQueryTreeReply( + ClientPtr /* pClient */, + int /* size */, + xQueryTreeReply * /* pRep */); + +extern void SInternAtomReply( + ClientPtr /* pClient */, + int /* size */, + xInternAtomReply * /* pRep */); + +extern void SGetAtomNameReply( + ClientPtr /* pClient */, + int /* size */, + xGetAtomNameReply * /* pRep */); + +extern void SGetPropertyReply( + ClientPtr /* pClient */, + int /* size */, + xGetPropertyReply * /* pRep */); + +extern void SListPropertiesReply( + ClientPtr /* pClient */, + int /* size */, + xListPropertiesReply * /* pRep */); + +extern void SGetSelectionOwnerReply( + ClientPtr /* pClient */, + int /* size */, + xGetSelectionOwnerReply * /* pRep */); + +extern void SQueryPointerReply( + ClientPtr /* pClient */, + int /* size */, + xQueryPointerReply * /* pRep */); + +extern void SwapTimecoord( + xTimecoord * /* pCoord */); + +extern void SwapTimeCoordWrite( + ClientPtr /* pClient */, + int /* size */, + xTimecoord * /* pRep */); + +extern void SGetMotionEventsReply( + ClientPtr /* pClient */, + int /* size */, + xGetMotionEventsReply * /* pRep */); + +extern void STranslateCoordsReply( + ClientPtr /* pClient */, + int /* size */, + xTranslateCoordsReply * /* pRep */); + +extern void SGetInputFocusReply( + ClientPtr /* pClient */, + int /* size */, + xGetInputFocusReply * /* pRep */); + +extern void SQueryKeymapReply( + ClientPtr /* pClient */, + int /* size */, + xQueryKeymapReply * /* pRep */); + +#ifdef LBX +extern void SwapCharInfo( + xCharInfo * /* pInfo */); +#endif + +#ifdef LBX +extern void SwapFont( + xQueryFontReply * /* pr */, + Bool /* hasGlyphs */); +#endif + +extern void SQueryFontReply( + ClientPtr /* pClient */, + int /* size */, + xQueryFontReply * /* pRep */); + +extern void SQueryTextExtentsReply( + ClientPtr /* pClient */, + int /* size */, + xQueryTextExtentsReply * /* pRep */); + +extern void SListFontsReply( + ClientPtr /* pClient */, + int /* size */, + xListFontsReply * /* pRep */); + +extern void SListFontsWithInfoReply( + ClientPtr /* pClient */, + int /* size */, + xListFontsWithInfoReply * /* pRep */); + +extern void SGetFontPathReply( + ClientPtr /* pClient */, + int /* size */, + xGetFontPathReply * /* pRep */); + +extern void SGetImageReply( + ClientPtr /* pClient */, + int /* size */, + xGetImageReply * /* pRep */); + +extern void SListInstalledColormapsReply( + ClientPtr /* pClient */, + int /* size */, + xListInstalledColormapsReply * /* pRep */); + +extern void SAllocColorReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorReply * /* pRep */); + +extern void SAllocNamedColorReply( + ClientPtr /* pClient */, + int /* size */, + xAllocNamedColorReply * /* pRep */); + +extern void SAllocColorCellsReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorCellsReply * /* pRep */); + +extern void SAllocColorPlanesReply( + ClientPtr /* pClient */, + int /* size */, + xAllocColorPlanesReply * /* pRep */); + +extern void SwapRGB( + xrgb * /* prgb */); + +extern void SQColorsExtend( + ClientPtr /* pClient */, + int /* size */, + xrgb * /* prgb */); + +extern void SQueryColorsReply( + ClientPtr /* pClient */, + int /* size */, + xQueryColorsReply * /* pRep */); + +extern void SLookupColorReply( + ClientPtr /* pClient */, + int /* size */, + xLookupColorReply * /* pRep */); + +extern void SQueryBestSizeReply( + ClientPtr /* pClient */, + int /* size */, + xQueryBestSizeReply * /* pRep */); + +extern void SListExtensionsReply( + ClientPtr /* pClient */, + int /* size */, + xListExtensionsReply * /* pRep */); + +extern void SGetKeyboardMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetKeyboardMappingReply * /* pRep */); + +extern void SGetPointerMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetPointerMappingReply * /* pRep */); + +extern void SGetModifierMappingReply( + ClientPtr /* pClient */, + int /* size */, + xGetModifierMappingReply * /* pRep */); + +extern void SGetKeyboardControlReply( + ClientPtr /* pClient */, + int /* size */, + xGetKeyboardControlReply * /* pRep */); + +extern void SGetPointerControlReply( + ClientPtr /* pClient */, + int /* size */, + xGetPointerControlReply * /* pRep */); + +extern void SGetScreenSaverReply( + ClientPtr /* pClient */, + int /* size */, + xGetScreenSaverReply * /* pRep */); + +extern void SLHostsExtend( + ClientPtr /* pClient */, + int /* size */, + char * /* buf */); + +extern void SListHostsReply( + ClientPtr /* pClient */, + int /* size */, + xListHostsReply * /* pRep */); + +extern void SErrorEvent( + xError * /* from */, + xError * /* to */); + +extern void SwapConnSetupInfo( + char * /* pInfo */, + char * /* pInfoTBase */); + +extern void WriteSConnectionInfo( + ClientPtr /* pClient */, + unsigned long /* size */, + char * /* pInfo */); + +extern void SwapConnSetup( + xConnSetup * /* pConnSetup */, + xConnSetup * /* pConnSetupT */); + +extern void SwapWinRoot( + xWindowRoot * /* pRoot */, + xWindowRoot * /* pRootT */); + +extern void SwapVisual( + xVisualType * /* pVis */, + xVisualType * /* pVisT */); + +extern void SwapConnSetupPrefix( + xConnSetupPrefix * /* pcspFrom */, + xConnSetupPrefix * /* pcspTo */); + +extern void WriteSConnSetupPrefix( + ClientPtr /* pClient */, + xConnSetupPrefix * /* pcsp */); + +#undef SWAPREP_PROC +#define SWAPREP_PROC(func) void func(xEvent * /* from */, xEvent * /* to */) + +SWAPREP_PROC(SCirculateEvent); +SWAPREP_PROC(SClientMessageEvent); +SWAPREP_PROC(SColormapEvent); +SWAPREP_PROC(SConfigureNotifyEvent); +SWAPREP_PROC(SConfigureRequestEvent); +SWAPREP_PROC(SCreateNotifyEvent); +SWAPREP_PROC(SDestroyNotifyEvent); +SWAPREP_PROC(SEnterLeaveEvent); +SWAPREP_PROC(SExposeEvent); +SWAPREP_PROC(SFocusEvent); +SWAPREP_PROC(SGraphicsExposureEvent); +SWAPREP_PROC(SGravityEvent); +SWAPREP_PROC(SKeyButtonPtrEvent); +SWAPREP_PROC(SKeymapNotifyEvent); +SWAPREP_PROC(SMapNotifyEvent); +SWAPREP_PROC(SMapRequestEvent); +SWAPREP_PROC(SMappingEvent); +SWAPREP_PROC(SNoExposureEvent); +SWAPREP_PROC(SPropertyEvent); +SWAPREP_PROC(SReparentEvent); +SWAPREP_PROC(SResizeRequestEvent); +SWAPREP_PROC(SSelectionClearEvent); +SWAPREP_PROC(SSelectionNotifyEvent); +SWAPREP_PROC(SSelectionRequestEvent); +SWAPREP_PROC(SUnmapNotifyEvent); +SWAPREP_PROC(SVisibilityEvent); + +#undef SWAPREP_PROC + +#endif /* SWAPREP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swapreq.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swapreq.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/swapreq.h (revision 51223) @@ -0,0 +1,120 @@ +/* $XFree86: xc/programs/Xserver/include/swapreq.h,v 1.3 2003/04/27 21:31:05 herrb Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifndef SWAPREQ_H +#define SWAPREQ_H 1 + +/* The first two are in misc.h */ +#if 0 +extern void SwapLongs ( + CARD32 * /* list */, + unsigned long /* count */); + +extern void SwapShorts ( + short * /* list */, + unsigned long /* count */); +#endif + +extern void SwapColorItem( + xColorItem * /* pItem */); + +extern void SwapConnClientPrefix( + xConnClientPrefix * /* pCCP */); + +#undef SWAPREQ_PROC + +#define SWAPREQ_PROC(func) int func(ClientPtr /* client */) + +SWAPREQ_PROC(SProcAllocColor); +SWAPREQ_PROC(SProcAllocColorCells); +SWAPREQ_PROC(SProcAllocColorPlanes); +SWAPREQ_PROC(SProcAllocNamedColor); +SWAPREQ_PROC(SProcChangeActivePointerGrab); +SWAPREQ_PROC(SProcChangeGC); +SWAPREQ_PROC(SProcChangeHosts); +SWAPREQ_PROC(SProcChangeKeyboardControl); +SWAPREQ_PROC(SProcChangeKeyboardMapping); +SWAPREQ_PROC(SProcChangePointerControl); +SWAPREQ_PROC(SProcChangeProperty); +SWAPREQ_PROC(SProcChangeWindowAttributes); +SWAPREQ_PROC(SProcClearToBackground); +SWAPREQ_PROC(SProcConfigureWindow); +SWAPREQ_PROC(SProcConvertSelection); +SWAPREQ_PROC(SProcCopyArea); +SWAPREQ_PROC(SProcCopyColormapAndFree); +SWAPREQ_PROC(SProcCopyGC); +SWAPREQ_PROC(SProcCopyPlane); +SWAPREQ_PROC(SProcCreateColormap); +SWAPREQ_PROC(SProcCreateCursor); +SWAPREQ_PROC(SProcCreateGC); +SWAPREQ_PROC(SProcCreateGlyphCursor); +SWAPREQ_PROC(SProcCreatePixmap); +SWAPREQ_PROC(SProcCreateWindow); +SWAPREQ_PROC(SProcDeleteProperty); +SWAPREQ_PROC(SProcFillPoly); +SWAPREQ_PROC(SProcFreeColors); +SWAPREQ_PROC(SProcGetImage); +SWAPREQ_PROC(SProcGetMotionEvents); +SWAPREQ_PROC(SProcGetProperty); +SWAPREQ_PROC(SProcGrabButton); +SWAPREQ_PROC(SProcGrabKey); +SWAPREQ_PROC(SProcGrabKeyboard); +SWAPREQ_PROC(SProcGrabPointer); +SWAPREQ_PROC(SProcImageText); +SWAPREQ_PROC(SProcInternAtom); +SWAPREQ_PROC(SProcListFonts); +SWAPREQ_PROC(SProcListFontsWithInfo); +SWAPREQ_PROC(SProcLookupColor); +SWAPREQ_PROC(SProcNoOperation); +SWAPREQ_PROC(SProcOpenFont); +SWAPREQ_PROC(SProcPoly); +SWAPREQ_PROC(SProcPolyText); +SWAPREQ_PROC(SProcPutImage); +SWAPREQ_PROC(SProcQueryBestSize); +SWAPREQ_PROC(SProcQueryColors); +SWAPREQ_PROC(SProcQueryExtension); +SWAPREQ_PROC(SProcRecolorCursor); +SWAPREQ_PROC(SProcReparentWindow); +SWAPREQ_PROC(SProcResourceReq); +SWAPREQ_PROC(SProcRotateProperties); +SWAPREQ_PROC(SProcSendEvent); +SWAPREQ_PROC(SProcSetClipRectangles); +SWAPREQ_PROC(SProcSetDashes); +SWAPREQ_PROC(SProcSetFontPath); +SWAPREQ_PROC(SProcSetInputFocus); +SWAPREQ_PROC(SProcSetScreenSaver); +SWAPREQ_PROC(SProcSetSelectionOwner); +SWAPREQ_PROC(SProcSimpleReq); +SWAPREQ_PROC(SProcStoreColors); +SWAPREQ_PROC(SProcStoreNamedColor); +SWAPREQ_PROC(SProcTranslateCoords); +SWAPREQ_PROC(SProcUngrabButton); +SWAPREQ_PROC(SProcUngrabKey); +SWAPREQ_PROC(SProcWarpPointer); + +#undef SWAPREQ_PROC + +#endif /* SWAPREQ_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sym.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sym.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/sym.h (revision 51223) @@ -0,0 +1,50 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/loader/sym.h,v 1.6 2000/10/24 00:06:55 anderson Exp $ */ + +/* + * + * Copyright 1995,96 by Metro Link, Inc. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Metro Link, Inc. not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Metro Link, Inc. makes no + * representations about the suitability of this software for any purpose. + * It is provided "as is" without express or implied warranty. + * + * METRO LINK, INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL METRO LINK, INC. BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _SYM_H +#define _SYM_H + +/* + * This structure is used to pass in symbol information that is being + * added to the symbol table. + */ + +typedef void (*funcptr) (void); + +typedef struct { + char *symName; + funcptr offset; +} LOOKUP; + +#define SYMFUNC( func ) { #func, (funcptr)&func }, +#define SYMFUNCALIAS( name, func ) { name, (funcptr)&func }, +#define SYMVAR( var ) { #var, (funcptr)&var }, +#define SYMVARALIAS( name, var ) { name, (funcptr)&var }, + +#endif /* _SYM_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda8425.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda8425.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda8425.h (revision 51223) @@ -0,0 +1,53 @@ +#ifndef __TDA8425_H__ +#define __TDA8425_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int mux; + int stereo; + int v_left; + int v_right; + int bass; + int treble; + int src_sel; + Bool mute; + } TDA8425Rec, *TDA8425Ptr; + +#define TDA8425_ADDR_1 0x82 + +/* the third parameter is meant to force detection of tda8425. + This is because tda8425 is write-only and complete implementation + of I2C protocol is not always available. Besides address there is no good + way to autodetect it so we have to _know_ it is there anyway */ + +TDA8425Ptr Detect_tda8425(I2CBusPtr b, I2CSlaveAddr addr,Bool force); +Bool tda8425_init(TDA8425Ptr t); +void tda8425_setaudio(TDA8425Ptr t); +void tda8425_mute(TDA8425Ptr t, Bool mute); + +#define TDA8425SymbolsList \ + "Detect_tda8425", \ + "tda8425_init", \ + "tda8425_setaudio", \ + "tda8425_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda8425 ((TDA8425Ptr (*)(I2CBusPtr, I2CSlaveAddr,Bool))LoaderSymbol("Detect_tda8425")) +#define xf86_tda8425_init ((Bool (*)(TDA8425Ptr))LoaderSymbol("tda8425_init")) +#define xf86_tda8425_setaudio ((void (*)(TDA8425Ptr))LoaderSymbol("tda8425_setaudio")) +#define xf86_tda8425_mute ((void (*)(TDA8425Ptr, Bool))LoaderSymbol("tda8425_mute")) + +#else + +#define xf86_Detect_tda8425 Detect_tda8425 +#define xf86_tda8425_init tda8425_init +#define xf86_tda8425_setaudio tda8425_setaudio +#define xf86_tda8425_mute tda8425_mute + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9850.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9850.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9850.h (revision 51223) @@ -0,0 +1,52 @@ +#ifndef __TDA9850_H__ +#define __TDA9850_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + int mux; + int stereo; + int sap; + Bool mute; + Bool sap_mute; + } TDA9850Rec, *TDA9850Ptr; + +#define TDA9850_ADDR_1 0xB4 + +TDA9850Ptr Detect_tda9850(I2CBusPtr b, I2CSlaveAddr addr); +Bool tda9850_init(TDA9850Ptr t); +void tda9850_setaudio(TDA9850Ptr t); +void tda9850_mute(TDA9850Ptr t, Bool mute); +void tda9850_sap_mute(TDA9850Ptr t, Bool sap_mute); +CARD16 tda9850_getstatus(TDA9850Ptr t); + +#define TDA9850SymbolsList \ + "Detect_tda9850", \ + "tda9850_init", \ + "tda9850_setaudio", \ + "tda9850_mute", \ + "tda9850_sap_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda9850 ((TDA9850Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_tda9850")) +#define xf86_tda9850_init ((Bool (*)(TDA9850Ptr))LoaderSymbol("tda9850_init")) +#define xf86_tda9850_setaudio ((void (*)(TDA9850Ptr))LoaderSymbol("tda9850_setaudio")) +#define xf86_tda9850_mute ((void (*)(TDA9850Ptr, Bool))LoaderSymbol("tda9850_mute")) +#define xf86_tda9850_sap_mute ((void (*)(TDA9850Ptr, Bool))LoaderSymbol("tda9850_sap_mute")) +#define xf86_tda9850_getstatus ((CARD16 (*)(TDA9850Ptr))LoaderSymbol("tda9850_getstatus")) + +#else + +#define xf86_Detect_tda9850 Detect_tda9850 +#define xf86_tda9850_init tda9850_init +#define xf86_tda9850_setaudio tda9850_setaudio +#define xf86_tda9850_mute tda9850_mute +#define xf86_tda9850_sap_mute tda9850_sap_mute +#define xf86_tda9850_getstatus tda9850_getstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9885.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9885.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/tda9885.h (revision 51223) @@ -0,0 +1,72 @@ +#ifndef __TDA9885_H__ +#define __TDA9885_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + /* write-only parameters */ + /* B DATA */ + CARD8 sound_trap; + CARD8 auto_mute_fm; + CARD8 carrier_mode; + CARD8 modulation; + CARD8 forced_mute_audio; + CARD8 port1; + CARD8 port2; + /* C DATA */ + CARD8 top_adjustment; + CARD8 deemphasis; + CARD8 audio_gain; + /* E DATA */ + CARD8 standard_sound_carrier; + CARD8 standard_video_if; + CARD8 minimum_gain; + CARD8 gating; + CARD8 vif_agc; + /* read-only values */ + + CARD8 after_reset; + CARD8 afc_status; + CARD8 vif_level; + CARD8 afc_win; + CARD8 fm_carrier; + } TDA9885Rec, *TDA9885Ptr; + +#define TDA9885_ADDR_1 0x86 +#define TDA9885_ADDR_2 0x84 +#define TDA9885_ADDR_3 0x96 +#define TDA9885_ADDR_4 0x94 + +TDA9885Ptr Detect_tda9885(I2CBusPtr b, I2CSlaveAddr addr); +Bool tda9885_init(TDA9885Ptr t); +void tda9885_setparameters(TDA9885Ptr t); +void tda9885_getstatus(TDA9885Ptr t); +void tda9885_dumpstatus(TDA9885Ptr t); + +#define TDA9885SymbolsList \ + "Detect_tda9885", \ + "tda9885_init", \ + "tda9885_setaudio", \ + "tda9885_mute" + +#ifdef XFree86LOADER + +#define xf86_Detect_tda9885 ((TDA9885Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_tda9885")) +#define xf86_tda9885_init ((Bool (*)(TDA9885Ptr))LoaderSymbol("tda9885_init")) +#define xf86_tda9885_setparameters ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_setparameters")) +#define xf86_tda9885_getstatus ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_getstatus")) +#define xf86_tda9885_dumpstatus ((void (*)(TDA9885Ptr))LoaderSymbol("tda9885_dumpstatus")) + +#else + +#define xf86_Detect_tda9885 Detect_tda9885 +#define xf86_tda9885_init tda9885_init +#define xf86_tda9885_setparameters tda9885_setparameters +#define xf86_tda9885_getstatus tda9885_getstatus +#define xf86_tda9885_dumpstatus tda9885_dumpstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/types.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/types.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/types.h (revision 51223) @@ -0,0 +1,106 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#ifndef NO_SYS_HEADERS +#include +#endif + +/* + * The following kludge is an attempt to work around typedef conflicts with + * . + */ +#define u8 x86emuu8 +#define u16 x86emuu16 +#define u32 x86emuu32 +#define u64 x86emuu64 +#define s8 x86emus8 +#define s16 x86emus16 +#define s32 x86emus32 +#define s64 x86emus64 +#define uint x86emuuint +#define sint x86emusint + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#undef __HAS_LONG_LONG__ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +/* Taken from Xmd.h */ +#undef NUM32 +#if defined (_LP64) || \ + defined(__alpha) || defined(__alpha__) || \ + defined(__ia64__) || defined(ia64) || \ + defined(__sparc64__) || \ + defined(__s390x__) || \ + (defined(__hppa__) && defined(__LP64)) || \ + defined(__amd64__) || defined(amd64) || \ + (defined(__sgi) && (_MIPS_SZLONG == 64)) +#define NUM32 int +#else +#define NUM32 long +#endif + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned NUM32 u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef NUM32 s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +typedef unsigned int uint; +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#undef NUM32 + +#endif /* __X86EMU_TYPES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/uda1380.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/uda1380.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/uda1380.h (revision 51223) @@ -0,0 +1,90 @@ +/************************************************************************************* + * $Id: uda1380.h,v 1.2 2005/07/01 22:43:11 daniels Exp $ + * + * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this + * software and associated documentation files (the "Software"), to deal in the Software + * without restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the author shall not be used in advertising or + * otherwise to promote the sale, use or other dealings in this Software without prior written + * authorization from the author. + * + * $Log: uda1380.h,v $ + * Revision 1.2 2005/07/01 22:43:11 daniels + * Change all misc.h and os.h references to . + * + * + ************************************************************************************/ + +#ifndef __UDA1380_H__ +#define __UDA1380_H__ + +#include "xf86i2c.h" + +typedef struct { + I2CDevRec d; + + CARD16 analog_mixer_settings; /* register 0x03 */ + + } UDA1380Rec, *UDA1380Ptr; + +#define UDA1380_ADDR_1 0x30 +#define UDA1380_ADDR_2 0x34 + +UDA1380Ptr Detect_uda1380(I2CBusPtr b, I2CSlaveAddr addr); +Bool uda1380_init(UDA1380Ptr t); +void uda1380_shutdown(UDA1380Ptr t); +void uda1380_setvolume(UDA1380Ptr t, INT32); +void uda1380_mute(UDA1380Ptr t, Bool); +void uda1380_setparameters(UDA1380Ptr t); +void uda1380_getstatus(UDA1380Ptr t); +void uda1380_dumpstatus(UDA1380Ptr t); + +#define UDA1380SymbolsList \ + "Detect_uda1380", \ + "uda1380_init", \ + "uda1380_shutdown", \ + "uda1380_setvolume", \ + "uda1380_mute", \ + "uda1380_setparameters", \ + "uda1380_getstatus", \ + "uda1380_dumpstatus" + +#ifdef XFree86LOADER + +#define xf86_Detect_uda1380 ((UDA1380Ptr (*)(I2CBusPtr, I2CSlaveAddr))LoaderSymbol("Detect_uda1380")) +#define xf86_uda1380_init ((Bool (*)(UDA1380Ptr))LoaderSymbol("uda1380_init")) +#define xf86_uda1380_shutdown ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_shutdown")) +#define xf86_uda1380_setvolume ((void (*)(UDA1380Ptr, CARD16))LoaderSymbol("uda1380_setvolume")) +#define xf86_uda1380_mute ((void (*)(UDA1380Ptr, Bool))LoaderSymbol("uda1380_mute")) +#define xf86_uda1380_setparameters ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_setparameters")) +#define xf86_uda1380_getstatus ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_getstatus")) +#define xf86_uda1380_dumpstatus ((void (*)(UDA1380Ptr))LoaderSymbol("uda1380_dumpstatus")) + +#else + +#define xf86_Detect_uda1380 Detect_uda1380 +#define xf86_uda1380_init uda1380_init +#define xf86_uda1380_shutdown uda1380_shutdown +#define xf86_uda1380_setvolume uda1380_setvolume +#define xf86_uda1380_mute uda1380_mute +#define xf86_uda1380_setparameters uda1380_setparameters +#define xf86_uda1380_getstatus uda1380_getstatus +#define xf86_uda1380_dumpstatus uda1380_dumpstatus + +#endif + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdev.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdev.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdev.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEV_H +#define UNGRDEV_H 1 + +int SProcXUngrabDevice(ClientPtr /* client */ + ); + +int ProcXUngrabDevice(ClientPtr /* client */ + ); + +#endif /* UNGRDEV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevb.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEVB_H +#define UNGRDEVB_H 1 + +int SProcXUngrabDeviceButton(ClientPtr /* client */ + ); + +int ProcXUngrabDeviceButton(ClientPtr /* client */ + ); + +#endif /* UNGRDEVB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevk.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevk.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/ungrdevk.h (revision 51223) @@ -0,0 +1,39 @@ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef UNGRDEVK_H +#define UNGRDEVK_H 1 + +int SProcXUngrabDeviceKey(ClientPtr /* client */ + ); + +int ProcXUngrabDeviceKey(ClientPtr /* client */ + ); + +#endif /* UNGRDEVK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/unpack.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/unpack.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/unpack.h (revision 51223) @@ -0,0 +1,234 @@ +/* $XFree86: xc/programs/Xserver/GL/glx/unpack.h,v 1.3 2001/03/21 16:29:37 dawes Exp $ */ +#ifndef __GLX_unpack_h__ +#define __GLX_unpack_h__ + +/* +** License Applicability. Except to the extent portions of this file are +** made subject to an alternative license as permitted in the SGI Free +** Software License B, Version 1.1 (the "License"), the contents of this +** file are subject only to the provisions of the License. You may not use +** this file except in compliance with the License. You may obtain a copy +** of the License at Silicon Graphics, Inc., attn: Legal Services, 1600 +** Amphitheatre Parkway, Mountain View, CA 94043-1351, or at: +** +** http://oss.sgi.com/projects/FreeB +** +** Note that, as provided in the License, the Software is distributed on an +** "AS IS" basis, with ALL EXPRESS AND IMPLIED WARRANTIES AND CONDITIONS +** DISCLAIMED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES AND +** CONDITIONS OF MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS FOR A +** PARTICULAR PURPOSE, AND NON-INFRINGEMENT. +** +** Original Code. The Original Code is: OpenGL Sample Implementation, +** Version 1.2.1, released January 26, 2000, developed by Silicon Graphics, +** Inc. The Original Code is Copyright (c) 1991-2000 Silicon Graphics, Inc. +** Copyright in any portions created by third parties is as indicated +** elsewhere herein. All Rights Reserved. +** +** Additional Notice Provisions: The application programming interfaces +** established by SGI in conjunction with the Original Code are The +** OpenGL(R) Graphics System: A Specification (Version 1.2.1), released +** April 1, 1999; The OpenGL(R) Graphics System Utility Library (Version +** 1.3), released November 4, 1998; and OpenGL(R) Graphics with the X +** Window System(R) (Version 1.3), released October 19, 1998. This software +** was created using the OpenGL(R) version 1.2.1 Sample Implementation +** published by SGI, but has not been independently verified as being +** compliant with the OpenGL(R) version 1.2.1 Specification. +** +*/ + +#define __GLX_PAD(s) (((s)+3) & (GLuint)~3) + +/* +** Fetch the context-id out of a SingleReq request pointed to by pc. +*/ +#define __GLX_GET_SINGLE_CONTEXT_TAG(pc) (((xGLXSingleReq*)pc)->contextTag) +#define __GLX_GET_VENDPRIV_CONTEXT_TAG(pc) (((xGLXVendorPrivateReq*)pc)->contextTag) + +/* +** Fetch a double from potentially unaligned memory. +*/ +#ifdef __GLX_ALIGN64 +#define __GLX_MEM_COPY(dst,src,n) memcpy(dst,src,n) +#define __GLX_GET_DOUBLE(dst,src) __GLX_MEM_COPY(&dst,src,8) +#else +#define __GLX_GET_DOUBLE(dst,src) (dst) = *((GLdouble*)(src)) +#endif + +extern void __glXMemInit(void); + +extern xGLXSingleReply __glXReply; + +#define __GLX_BEGIN_REPLY(size) \ + __glXReply.length = __GLX_PAD(size) >> 2; \ + __glXReply.type = X_Reply; \ + __glXReply.sequenceNumber = client->sequence; + +#define __GLX_SEND_HEADER() \ + WriteToClient( client, sz_xGLXSingleReply, (char *)&__glXReply); + +#define __GLX_PUT_RETVAL(a) \ + __glXReply.retval = (a); + +#define __GLX_PUT_SIZE(a) \ + __glXReply.size = (a); + +#define __GLX_PUT_RENDERMODE(m) \ + __glXReply.pad3 = (m) + +/* +** Get a buffer to hold returned data, with the given alignment. If we have +** to realloc, allocate size+align, in case the pointer has to be bumped for +** alignment. The answerBuffer should already be aligned. +** +** NOTE: the cast (long)res below assumes a long is large enough to hold a +** pointer. +*/ +#define __GLX_GET_ANSWER_BUFFER(res,cl,size,align) \ + if ((size) > sizeof(answerBuffer)) { \ + int bump; \ + if ((cl)->returnBufSize < (size)+(align)) { \ + (cl)->returnBuf = (GLbyte*)Xrealloc((cl)->returnBuf, \ + (size)+(align)); \ + if (!(cl)->returnBuf) { \ + return BadAlloc; \ + } \ + (cl)->returnBufSize = (size)+(align); \ + } \ + res = (char*)cl->returnBuf; \ + bump = (long)(res) % (align); \ + if (bump) res += (align) - (bump); \ + } else { \ + res = (char *)answerBuffer; \ + } + +#define __GLX_PUT_BYTE() \ + *(GLbyte *)&__glXReply.pad3 = *(GLbyte *)answer + +#define __GLX_PUT_SHORT() \ + *(GLshort *)&__glXReply.pad3 = *(GLshort *)answer + +#define __GLX_PUT_INT() \ + *(GLint *)&__glXReply.pad3 = *(GLint *)answer + +#define __GLX_PUT_FLOAT() \ + *(GLfloat *)&__glXReply.pad3 = *(GLfloat *)answer + +#define __GLX_PUT_DOUBLE() \ + *(GLdouble *)&__glXReply.pad3 = *(GLdouble *)answer + +#define __GLX_SEND_BYTE_ARRAY(len) \ + WriteToClient(client, __GLX_PAD((len)*__GLX_SIZE_INT8), (char *)answer) + +#define __GLX_SEND_SHORT_ARRAY(len) \ + WriteToClient(client, __GLX_PAD((len)*__GLX_SIZE_INT16), (char *)answer) + +#define __GLX_SEND_INT_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_INT32, (char *)answer) + +#define __GLX_SEND_FLOAT_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_FLOAT32, (char *)answer) + +#define __GLX_SEND_DOUBLE_ARRAY(len) \ + WriteToClient(client, (len)*__GLX_SIZE_FLOAT64, (char *)answer) + + +#define __GLX_SEND_VOID_ARRAY(len) __GLX_SEND_BYTE_ARRAY(len) +#define __GLX_SEND_UBYTE_ARRAY(len) __GLX_SEND_BYTE_ARRAY(len) +#define __GLX_SEND_USHORT_ARRAY(len) __GLX_SEND_SHORT_ARRAY(len) +#define __GLX_SEND_UINT_ARRAY(len) __GLX_SEND_INT_ARRAY(len) + +/* +** PERFORMANCE NOTE: +** Machine dependent optimizations abound here; these swapping macros can +** conceivably be replaced with routines that do the job faster. +*/ +#define __GLX_DECLARE_SWAP_VARIABLES \ + GLbyte sw; \ + GLbyte *swapPC; \ + GLbyte *swapEnd + + +#define __GLX_SWAP_INT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = sw; + +#define __GLX_SWAP_SHORT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = sw; + +#define __GLX_SWAP_DOUBLE(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[7]; \ + ((GLbyte *)(pc))[7] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[6]; \ + ((GLbyte *)(pc))[6] = sw; \ + sw = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = ((GLbyte *)(pc))[5]; \ + ((GLbyte *)(pc))[5] = sw; \ + sw = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = ((GLbyte *)(pc))[4]; \ + ((GLbyte *)(pc))[4] = sw; + +#define __GLX_SWAP_FLOAT(pc) \ + sw = ((GLbyte *)(pc))[0]; \ + ((GLbyte *)(pc))[0] = ((GLbyte *)(pc))[3]; \ + ((GLbyte *)(pc))[3] = sw; \ + sw = ((GLbyte *)(pc))[1]; \ + ((GLbyte *)(pc))[1] = ((GLbyte *)(pc))[2]; \ + ((GLbyte *)(pc))[2] = sw; + +#define __GLX_SWAP_INT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_INT32;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_INT(swapPC); \ + swapPC += __GLX_SIZE_INT32; \ + } + +#define __GLX_SWAP_SHORT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_INT16;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_SHORT(swapPC); \ + swapPC += __GLX_SIZE_INT16; \ + } + +#define __GLX_SWAP_DOUBLE_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_FLOAT64;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_DOUBLE(swapPC); \ + swapPC += __GLX_SIZE_FLOAT64; \ + } + +#define __GLX_SWAP_FLOAT_ARRAY(pc, count) \ + swapPC = ((GLbyte *)(pc)); \ + swapEnd = ((GLbyte *)(pc)) + (count)*__GLX_SIZE_FLOAT32;\ + while (swapPC < swapEnd) { \ + __GLX_SWAP_FLOAT(swapPC); \ + swapPC += __GLX_SIZE_FLOAT32; \ + } + +#define __GLX_SWAP_REPLY_HEADER() \ + __GLX_SWAP_SHORT(&__glXReply.sequenceNumber); \ + __GLX_SWAP_INT(&__glXReply.length); + +#define __GLX_SWAP_REPLY_RETVAL() \ + __GLX_SWAP_INT(&__glXReply.retval) + +#define __GLX_SWAP_REPLY_SIZE() \ + __GLX_SWAP_INT(&__glXReply.size) + +#endif /* !__GLX_unpack_h__ */ + + + + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-common.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-common.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-common.h (revision 51223) @@ -0,0 +1,56 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to common USB support. \see usb-common.c \see usb-mouse.c + * \see usb-keyboard.c \see usb-other.c */ + +#ifndef _USB_COMMON_H_ +#define _USB_COMMON_H_ +typedef enum { + usbMouse, + usbKeyboard, + usbOther +} usbType; + +extern pointer usbCreatePrivate(DeviceIntPtr pDevice); +extern void usbDestroyPrivate(pointer priv); +extern void usbRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + int minButton, + DMXBlockType block); +extern void usbInit(DevicePtr pDev, usbType type); +extern void usbOff(DevicePtr pDev); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-keyboard.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-keyboard.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-keyboard.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB keyboard driver. \see usb-keyboard.c \see usb-common.c */ + +#ifndef _USB_KEYBOARD_H_ +#define _USB_KEYBOARD_H_ +extern void kbdUSBInit(DevicePtr pDev); +extern void kbdUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int kbdUSBOn(DevicePtr pDev); +extern void kbdUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void kbdUSBCtrl(DevicePtr pDev, KeybdCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-mouse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-mouse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-mouse.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB mouse driver. \see usb-mouse.c \see usb-common.c */ + +#ifndef _USB_MOU_H_ +#define _USB_MOU_H_ +extern void mouUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void mouUSBInit(DevicePtr pDev); +extern void mouUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int mouUSBOn(DevicePtr pDev); +extern void mouUSBCtrl(DevicePtr pDev, PtrCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-other.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-other.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-other.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Interface to USB generic driver. \see usb-other.c \see usb-common.c */ + +#ifndef _USB_OTHER_H_ +#define _USB_OTHER_H_ +extern void othUSBRead(DevicePtr pDev, + dmxMotionProcPtr motion, + dmxEnqueueProcPtr enqueue, + dmxCheckSpecialProcPtr checkspecial, + DMXBlockType block); +extern void othUSBInit(DevicePtr pDev); +extern void othUSBGetInfo(DevicePtr pDev, DMXLocalInitInfoPtr info); +extern int othUSBOn(DevicePtr pDev); +extern void othUSBCtrl(DevicePtr pDev, PtrCtrl *ctrl); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-private.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-private.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb-private.h (revision 51223) @@ -0,0 +1,118 @@ +/* $XFree86$ */ +/* + * Copyright 2002 Red Hat Inc., Durham, North Carolina. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL RED HAT AND/OR THEIR SUPPLIERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * Authors: + * Rickard E. (Rik) Faith + * + */ + +/** \file + * Private header file for USB support. This file provides + * Linux-specific include files and the definition of the private + * structure. \see usb-common.c \see usb-keyboard.c \see usb-mouse.c + * \see usb-other.c */ + +#ifndef _USB_PRIVATE_H_ +#define _USB_PRIVATE_H_ + +#include "dmxinputinit.h" +#include "inputstr.h" +#include +#include +#include +#include "usb-common.h" + + /* Support for force feedback was + * introduced in Linxu 2.4.10 */ +#ifndef EV_MSC +#define EV_MSC 0x04 +#endif +#ifndef EV_FF +#define EV_FF 0x15 +#endif +#ifndef LED_SLEEP +#define LED_SLEEP 0x05 +#endif +#ifndef LED_SUSPEND +#define LED_SUSPEND 0x06 +#endif +#ifndef LED_MUTE +#define LED_MUTE 0x07 +#endif +#ifndef LED_MISC +#define LED_MISC 0x08 +#endif +#ifndef BTN_DEAD +#define BTN_DEAD 0x12f +#endif +#ifndef BTN_THUMBL +#define BTN_THUMBL 0x13d +#endif +#ifndef BTN_THUMBR +#define BTN_THUMBR 0x13e +#endif +#ifndef MSC_SERIAL +#define MSC_SERIAL 0x00 +#endif +#ifndef MSC_MAX +#define MSC_MAX 0x07 +#endif + + /* Support for older kernels. */ +#ifndef ABS_WHEEL +#define ABS_WHEEL 0x08 +#endif +#ifndef ABS_GAS +#define ABS_GAS 0x09 +#endif +#ifndef ABS_BRAKE +#define ABS_BRAKE 0x0a +#endif + +#define NUM_STATE_ENTRIES (256/32) + +/* Private area for USB devices. */ +typedef struct _myPrivate { + DeviceIntPtr pDevice; /**< Device (mouse or other) */ + int fd; /**< File descriptor */ + unsigned char mask[EV_MAX/8 + 1]; /**< Mask */ + int numRel, numAbs, numLeds; /**< Counts */ + int relmap[DMX_MAX_AXES]; /**< Relative axis map */ + int absmap[DMX_MAX_AXES]; /**< Absolute axis map */ + + CARD32 kbdState[NUM_STATE_ENTRIES]; /**< Keyboard state */ + DeviceIntPtr pKeyboard; /** Keyboard device */ + + int pitch; /**< Bell pitch */ + unsigned long duration; /**< Bell duration */ + + /* FIXME: dmxInput is never initialized */ + DMXInputInfo *dmxInput; /**< For pretty-printing */ +} myPrivate; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usb.h (revision 51223) @@ -0,0 +1,95 @@ +/* $NetBSD: usb.h,v 1.5 1999/07/02 15:46:53 simonb Exp $ */ + +/* + * Copyright (c) 1999 Lennart Augustsson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/libusb/usb.h,v 1.1.2.2 1999/12/03 10:12:43 hohndel Exp $ */ + +#define _DIAGASSERT(e) assert(e) + +typedef struct report_desc *report_desc_t; + +typedef struct hid_data *hid_data_t; + +typedef enum hid_kind { + hid_input, hid_output, hid_feature, hid_collection, hid_endcollection +}hid_kind_t; + +typedef struct hid_item { + /* Global */ + int _usage_page; + int logical_minimum; + int logical_maximum; + int physical_minimum; + int physical_maximum; + int unit_exponent; + int unit; + int report_size; + int report_ID; + int report_count; + /* Local */ + unsigned int usage; + int usage_minimum; + int usage_maximum; + int designator_index; + int designator_minimum; + int designator_maximum; + int string_index; + int string_minimum; + int string_maximum; + int set_delimiter; + /* Misc */ + int collection; + int collevel; + enum hid_kind kind; + unsigned int flags; + /* Absolute data position (bits) */ + unsigned int pos; + /* */ + struct hid_item *next; +} hid_item_t; + +#define HID_PAGE(u) ((u) >> 16) +#define HID_USAGE(u) ((u) & 0xffff) + +/* Obtaining a report descriptor, descr.c: */ +report_desc_t hid_get_report_desc __P((int file)); +void hid_dispose_report_desc __P((report_desc_t)); + +/* Parsing of a HID report descriptor, parse.c: */ +hid_data_t hid_start_parse __P((report_desc_t d, int kindset)); +void hid_end_parse __P((hid_data_t s)); +int hid_get_item __P((hid_data_t s, hid_item_t *h)); +int hid_report_size __P((report_desc_t d, enum hid_kind k, int *idp)); +int hid_locate __P((report_desc_t d, unsigned int usage, enum hid_kind k, hid_item_t *h)); + +/* Conversion to/from usage names, usage.c: */ +char *hid_usage_page __P((int i)); +char *hid_usage_in_page __P((unsigned int u)); +void hid_init __P((char *file)); + +/* Extracting/insertion of data, data.c: */ +int hid_get_data __P((void *p, hid_item_t *h)); +void hid_set_data __P((void *p, hid_item_t *h, int data)); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usbvar.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usbvar.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usbvar.h (revision 51223) @@ -0,0 +1,34 @@ +/* $NetBSD: usbvar.h,v 1.2 1999/05/11 21:15:46 augustss Exp $ */ + +/* + * Copyright (c) 1999 Lennart Augustsson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/libusb/usbvar.h,v 1.1.2.2 1999/12/03 10:12:43 hohndel Exp $ */ + +struct report_desc { + unsigned int size; + unsigned char data[1]; +}; + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_kbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_kbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_kbd.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/os-support/usl/usl_kbd.h,v 1.2 2005/11/08 06:33:30 jkj Exp $ */ +#ifndef SCO_KBD_HDR +#define SCO_KBD_HDR + +typedef struct { + int orig_kbm; + struct termio kbdtty; + keymap_t keymap, noledmap; + int xq; +} USLKbdPrivRec, *USLKbdPrivPtr; + +extern void KbdGetMapping(InputInfoPtr pInfo, KeySymsPtr pKeySyms, + CARD8 *pModMap); +#endif /* SCO_KBD_HDR */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_xqueue.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_xqueue.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/usl_xqueue.h (revision 51223) @@ -0,0 +1,9 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/os-support/usl/usl_xqueue.h,v 1.2 2005/11/08 06:33:30 jkj Exp $ */ + +#ifndef _XF86_USL_XQUEUE_H_ +#define _XF86_USL_XQUEUE_H_ + +extern int XqMseOnOff (InputInfoPtr pInfo, int on); +extern int XqKbdOnOff (InputInfoPtr pInfo, int on); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/validate.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/validate.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/validate.h (revision 51223) @@ -0,0 +1,42 @@ +/* $Xorg: validate.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ + +/* + +Copyright 1989, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. +*/ +/* $XFree86: xc/programs/Xserver/include/validate.h,v 1.4 2001/01/17 22:36:58 dawes Exp $ */ + +#ifndef VALIDATE_H +#define VALIDATE_H + +#include "miscstruct.h" +#include "regionstr.h" + +typedef enum { VTOther, VTStack, VTMove, VTUnmap, VTMap, VTBroken } VTKind; + +/* union _Validate is now device dependent; see mivalidate.h for an example */ +typedef union _Validate *ValidatePtr; + +#define UnmapValData ((ValidatePtr)1) + +#endif /* VALIDATE_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbe.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbe.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbe.h (revision 51223) @@ -0,0 +1,332 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/vbe/vbe.h,v 1.4 2004/01/07 04:28:06 dawes Exp $ */ + +/* + * XFree86 vbe module + * Copyright 2000 Egbert Eich + * + * The mode query/save/set/restore functions from the vesa driver + * have been moved here. + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * Authors: Paulo César Pereira de Andrade + */ + +#ifndef _VBE_H +#define _VBE_H +#include "xf86int10.h" +#include "xf86DDC.h" + +typedef enum { + DDC_UNCHECKED, + DDC_NONE, + DDC_1, + DDC_2, + DDC_1_2 +} +ddc_lvl; + +typedef struct { + xf86Int10InfoPtr pInt10; + int version; + pointer memory; + int real_mode_base; + int num_pages; + Bool init_int10; + ddc_lvl ddc; + Bool ddc_blank; +} vbeInfoRec, *vbeInfoPtr; + +#define VBE_VERSION_MAJOR(x) *((CARD8*)(&x) + 1) +#define VBE_VERSION_MINOR(x) (CARD8)(x) + +vbeInfoPtr VBEInit(xf86Int10InfoPtr pInt, int entityIndex); +vbeInfoPtr VBEExtendedInit(xf86Int10InfoPtr pInt, int entityIndex, int Flags); +void vbeFree(vbeInfoPtr pVbe); +xf86MonPtr vbeDoEDID(vbeInfoPtr pVbe, pointer pDDCModule); + +#pragma pack(1) + +typedef struct vbeControllerInfoBlock { + CARD8 VbeSignature[4]; + CARD16 VbeVersion; + CARD32 OemStringPtr; + CARD8 Capabilities[4]; + CARD32 VideoModePtr; + CARD16 TotalMem; + CARD16 OemSoftwareRev; + CARD32 OemVendorNamePtr; + CARD32 OemProductNamePtr; + CARD32 OemProductRevPtr; + CARD8 Scratch[222]; + CARD8 OemData[256]; +} vbeControllerInfoRec, *vbeControllerInfoPtr; + +#if defined(__GNUC__) || defined(__USLC__) || defined(__SUNPRO_C) +#pragma pack() /* All GCC versions recognise this syntax */ +#else +#pragma pack(0) +#endif + +#ifndef __GNUC__ +#define __attribute__(a) +#endif + +typedef struct _VbeInfoBlock VbeInfoBlock; +typedef struct _VbeModeInfoBlock VbeModeInfoBlock; +typedef struct _VbeCRTCInfoBlock VbeCRTCInfoBlock; + +/* + * INT 0 + */ + +struct _VbeInfoBlock { + /* VESA 1.2 fields */ + CARD8 VESASignature[4]; /* VESA */ + CARD16 VESAVersion; /* Higher byte major, lower byte minor */ + /*CARD32*/char *OEMStringPtr; /* Pointer to OEM string */ + CARD8 Capabilities[4]; /* Capabilities of the video environment */ + + /*CARD32*/CARD16 *VideoModePtr; /* pointer to supported Super VGA modes */ + + CARD16 TotalMemory; /* Number of 64kb memory blocks on board */ + /* if not VESA 2, 236 scratch bytes follow (256 bytes total size) */ + + /* VESA 2 fields */ + CARD16 OemSoftwareRev; /* VBE implementation Software revision */ + /*CARD32*/char *OemVendorNamePtr; /* Pointer to Vendor Name String */ + /*CARD32*/char *OemProductNamePtr; /* Pointer to Product Name String */ + /*CARD32*/char *OemProductRevPtr; /* Pointer to Product Revision String */ + CARD8 Reserved[222]; /* Reserved for VBE implementation */ + CARD8 OemData[256]; /* Data Area for OEM Strings */ +} __attribute__((packed)); + +/* Return Super VGA Information */ +VbeInfoBlock *VBEGetVBEInfo(vbeInfoPtr pVbe); +void VBEFreeVBEInfo(VbeInfoBlock *block); + +/* + * INT 1 + */ + +struct _VbeModeInfoBlock { + CARD16 ModeAttributes; /* mode attributes */ + CARD8 WinAAttributes; /* window A attributes */ + CARD8 WinBAttributes; /* window B attributes */ + CARD16 WinGranularity; /* window granularity */ + CARD16 WinSize; /* window size */ + CARD16 WinASegment; /* window A start segment */ + CARD16 WinBSegment; /* window B start segment */ + CARD32 WinFuncPtr; /* real mode pointer to window function */ + CARD16 BytesPerScanline; /* bytes per scanline */ + + /* Mandatory information for VBE 1.2 and above */ + CARD16 XResolution; /* horizontal resolution in pixels or characters */ + CARD16 YResolution; /* vertical resolution in pixels or characters */ + CARD8 XCharSize; /* character cell width in pixels */ + CARD8 YCharSize; /* character cell height in pixels */ + CARD8 NumberOfPlanes; /* number of memory planes */ + CARD8 BitsPerPixel; /* bits per pixel */ + CARD8 NumberOfBanks; /* number of banks */ + CARD8 MemoryModel; /* memory model type */ + CARD8 BankSize; /* bank size in KB */ + CARD8 NumberOfImages; /* number of images */ + CARD8 Reserved; /* 1 */ /* reserved for page function */ + + /* Direct color fields (required for direct/6 and YUV/7 memory models) */ + CARD8 RedMaskSize; /* size of direct color red mask in bits */ + CARD8 RedFieldPosition; /* bit position of lsb of red mask */ + CARD8 GreenMaskSize; /* size of direct color green mask in bits */ + CARD8 GreenFieldPosition; /* bit position of lsb of green mask */ + CARD8 BlueMaskSize; /* size of direct color blue mask in bits */ + CARD8 BlueFieldPosition; /* bit position of lsb of blue mask */ + CARD8 RsvdMaskSize; /* size of direct color reserved mask in bits */ + CARD8 RsvdFieldPosition; /* bit position of lsb of reserved mask */ + CARD8 DirectColorModeInfo; /* direct color mode attributes */ + + /* Mandatory information for VBE 2.0 and above */ + CARD32 PhysBasePtr; /* physical address for flat memory frame buffer */ + CARD32 Reserved32; /* 0 */ /* Reserved - always set to 0 */ + CARD16 Reserved16; /* 0 */ /* Reserved - always set to 0 */ + + /* Mandatory information for VBE 3.0 and above */ + CARD16 LinBytesPerScanLine; /* bytes per scan line for linear modes */ + CARD8 BnkNumberOfImagePages; /* number of images for banked modes */ + CARD8 LinNumberOfImagePages; /* number of images for linear modes */ + CARD8 LinRedMaskSize; /* size of direct color red mask (linear modes) */ + CARD8 LinRedFieldPosition; /* bit position of lsb of red mask (linear modes) */ + CARD8 LinGreenMaskSize; /* size of direct color green mask (linear modes) */ + CARD8 LinGreenFieldPosition; /* bit position of lsb of green mask (linear modes) */ + CARD8 LinBlueMaskSize; /* size of direct color blue mask (linear modes) */ + CARD8 LinBlueFieldPosition; /* bit position of lsb of blue mask (linear modes) */ + CARD8 LinRsvdMaskSize; /* size of direct color reserved mask (linear modes) */ + CARD8 LinRsvdFieldPosition; /* bit position of lsb of reserved mask (linear modes) */ + CARD32 MaxPixelClock; /* maximum pixel clock (in Hz) for graphics mode */ + CARD8 Reserved2[189]; /* remainder of VbeModeInfoBlock */ +} __attribute__((packed)); + +/* Return VBE Mode Information */ +VbeModeInfoBlock *VBEGetModeInfo(vbeInfoPtr pVbe, int mode); +void VBEFreeModeInfo(VbeModeInfoBlock *block); + +/* + * INT2 + */ + +#define CRTC_DBLSCAN (1<<0) +#define CRTC_INTERLACE (1<<1) +#define CRTC_NHSYNC (1<<2) +#define CRTC_NVSYNC (1<<3) + +struct _VbeCRTCInfoBlock { + CARD16 HorizontalTotal; /* Horizontal total in pixels */ + CARD16 HorizontalSyncStart; /* Horizontal sync start in pixels */ + CARD16 HorizontalSyncEnd; /* Horizontal sync end in pixels */ + CARD16 VerticalTotal; /* Vertical total in lines */ + CARD16 VerticalSyncStart; /* Vertical sync start in lines */ + CARD16 VerticalSyncEnd; /* Vertical sync end in lines */ + CARD8 Flags; /* Flags (Interlaced, Double Scan etc) */ + CARD32 PixelClock; /* Pixel clock in units of Hz */ + CARD16 RefreshRate; /* Refresh rate in units of 0.01 Hz */ + CARD8 Reserved[40]; /* remainder of ModeInfoBlock */ +} __attribute__((packed)); +/* VbeCRTCInfoBlock is in the VESA 3.0 specs */ + +Bool VBESetVBEMode(vbeInfoPtr pVbe, int mode, VbeCRTCInfoBlock *crtc); + +/* + * INT 3 + */ + +Bool VBEGetVBEMode(vbeInfoPtr pVbe, int *mode); + +/* + * INT 4 + */ + +/* Save/Restore Super VGA video state */ +/* function values are (values stored in VESAPtr): + * 0 := query & allocate amount of memory to save state + * 1 := save state + * 2 := restore state + * + * function 0 called automatically if function 1 called without + * a previous call to function 0. + */ + +typedef enum { + MODE_QUERY, + MODE_SAVE, + MODE_RESTORE +} vbeSaveRestoreFunction; + +Bool +VBESaveRestore(vbeInfoPtr pVbe, vbeSaveRestoreFunction fuction, + pointer *memory, int *size, int *real_mode_pages); + +/* + * INT 5 + */ + +Bool +VBEBankSwitch(vbeInfoPtr pVbe, unsigned int iBank, int window); + +/* + * INT 6 + */ + +typedef enum { + SCANWID_SET, + SCANWID_GET, + SCANWID_SET_BYTES, + SCANWID_GET_MAX +} vbeScanwidthCommand; + +#define VBESetLogicalScanline(pVbe, width) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_SET, width, \ + NULL, NULL, NULL) +#define VBESetLogicalScanlineBytes(pVbe, width) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_SET_BYTES, width, \ + NULL, NULL, NULL) +#define VBEGetLogicalScanline(pVbe, pixels, bytes, max) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_GET, 0, \ + pixels, bytes, max) +#define VBEGetMaxLogicalScanline(pVbe, pixels, bytes, max) \ + VBESetGetLogicalScanlineLength(pVbe, SCANWID_GET_MAX, 0, \ + pixels, bytes, max) +Bool VBESetGetLogicalScanlineLength(vbeInfoPtr pVbe, + vbeScanwidthCommand command, int width, + int *pixels, int *bytes, int *max); + +/* + * INT 7 + */ + +/* 16 bit code */ +Bool VBESetDisplayStart(vbeInfoPtr pVbe, int x, int y, Bool wait_retrace); +Bool VBEGetDisplayStart(vbeInfoPtr pVbe, int *x, int *y); + +/* + * INT 8 + */ + +/* if bits is 0, then it is a GET */ +int VBESetGetDACPaletteFormat(vbeInfoPtr pVbe, int bits); + +/* + * INT 9 + */ + +/* + * If getting a palette, the data argument is not used. It will return + * the data. + * If setting a palette, it will return the pointer received on success, + * NULL on failure. + */ +CARD32 *VBESetGetPaletteData(vbeInfoPtr pVbe, Bool set, int first, int num, + CARD32 *data, Bool secondary, Bool wait_retrace); +#define VBEFreePaletteData(data) xfree(data) + +/* + * INT A + */ + +typedef struct _VBEpmi { + int seg_tbl; + int tbl_off; + int tbl_len; +} VBEpmi; + +VBEpmi *VBEGetVBEpmi(vbeInfoPtr pVbe); +#define VESAFreeVBEpmi(pmi) xfree(pmi) + +/* high level helper functions */ + +typedef struct _vbeModeInfoRec { + int width; + int height; + int bpp; + int n; + struct _vbeModeInfoRec *next; +} vbeModeInfoRec, *vbeModeInfoPtr; + +vbeModeInfoPtr VBEBuildVbeModeList(vbeInfoPtr pVbe, + VbeInfoBlock *vbe); + +unsigned short VBECalcVbeModeIndex(vbeModeInfoPtr m, + DisplayModePtr mode, int bpp); + +typedef struct { + CARD8 *state; + CARD8 *pstate; + int statePage; + int stateSize; + int stateMode; +} vbeSaveRestoreRec, *vbeSaveRestorePtr; + +void +VBEVesaSaveRestore(vbeInfoPtr pVbe, vbeSaveRestorePtr vbe_sr, + vbeSaveRestoreFunction function); + +int VBEGetPixelClock(vbeInfoPtr pVbe, int mode, int Clock); +Bool VBEDPMSSet(vbeInfoPtr pVbe, int mode); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbeModes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbeModes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vbeModes.h (revision 51223) @@ -0,0 +1,91 @@ +/* + * Copyright © 2002 David Dawes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the author(s) shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * the author(s). + * + * Authors: David Dawes + * + * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/vbe/vbeModes.h,v 1.1 2002/08/06 13:46:28 dawes Exp $ + */ + +#ifndef _VBE_MODES_H + +/* + * This is intended to be stored in the DisplayModeRec's private area. + * It includes all the information necessary to VBE information. + */ +typedef struct _VbeModeInfoData { + int mode; + VbeModeInfoBlock *data; + VbeCRTCInfoBlock *block; +} VbeModeInfoData; + +#define V_DEPTH_1 0x001 +#define V_DEPTH_4 0x002 +#define V_DEPTH_8 0x004 +#define V_DEPTH_15 0x008 +#define V_DEPTH_16 0x010 +#define V_DEPTH_24_24 0x020 +#define V_DEPTH_24_32 0x040 +#define V_DEPTH_24 (V_DEPTH_24_24 | V_DEPTH_24_32) +#define V_DEPTH_30 0x080 +#define V_DEPTH_32 0x100 + +#define VBE_MODE_SUPPORTED(m) (((m)->ModeAttributes & 0x01) != 0) +#define VBE_MODE_COLOR(m) (((m)->ModeAttributes & 0x08) != 0) +#define VBE_MODE_GRAPHICS(m) (((m)->ModeAttributes & 0x10) != 0) +#define VBE_MODE_VGA(m) (((m)->ModeAttributes & 0x40) == 0) +#define VBE_MODE_LINEAR(m) (((m)->ModeAttributes & 0x80) != 0 && \ + ((m)->PhysBasePtr != 0)) + +#define VBE_MODE_USABLE(m, f) (VBE_MODE_SUPPORTED(m) || \ + (f & V_MODETYPE_BAD)) && \ + VBE_MODE_GRAPHICS(m) && \ + (VBE_MODE_VGA(m) || VBE_MODE_LINEAR(m)) + +#define V_MODETYPE_VBE 0x01 +#define V_MODETYPE_VGA 0x02 +#define V_MODETYPE_BAD 0x04 + +extern int VBEFindSupportedDepths(vbeInfoPtr pVbe, VbeInfoBlock *vbe, + int *flags24, int modeTypes); +extern DisplayModePtr VBEGetModePool(ScrnInfoPtr pScrn, vbeInfoPtr pVbe, + VbeInfoBlock *vbe, int modeTypes); +extern void VBESetModeNames(DisplayModePtr pMode); +extern void VBESetModeParameters(ScrnInfoPtr pScrn, vbeInfoPtr pVbe); + + +/* + * Note: These are alternatives to the standard helpers. They should + * usually just wrap the standard helpers. + */ +extern int VBEValidateModes(ScrnInfoPtr scrp, DisplayModePtr availModes, + char **modeNames, ClockRangePtr clockRanges, + int *linePitches, int minPitch, int maxPitch, + int pitchInc, int minHeight, int maxHeight, + int virtualX, int virtualY, int apertureSize, + LookupModeFlags strategy); +extern void VBEPrintModes(ScrnInfoPtr scrp); + +#endif /* VBE_MODES_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vdif.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vdif.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vdif.h (revision 51223) @@ -0,0 +1,175 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/vdif.h,v 1.4tsi Exp $ */ + +#ifndef _VDIF_H +#define _VDIF_H + +#define VDIF_MONITOR_MONOCHROME 0 +#define VDIF_MONITOR_COLOR 1 +#define VDIF_VIDEO_TTL 0 +#define VDIF_VIDEO_ANALOG 1 +#define VDIF_VIDEO_ECL 2 +#define VDIF_VIDEO_DECL 3 +#define VDIF_VIDEO_OTHER 4 +#define VDIF_SYNC_SEPARATE 0 +#define VDIF_SYNC_C 1 +#define VDIF_SYNC_CP 2 +#define VDIF_SYNC_G 3 +#define VDIF_SYNC_GP 4 +#define VDIF_SYNC_OTHER 5 +#define VDIF_SCAN_NONINTERLACED 0 +#define VDIF_SCAN_INTERLACED 1 +#define VDIF_SCAN_OTHER 2 +#define VDIF_POLARITY_NEGATIVE 0 +#define VDIF_POLARITY_POSITIVE 1 + +#include + +#undef CARD32 +#define CARD32 unsigned int /* ... on all supported platforms */ + +typedef struct _VDIF { /* Monitor Description: */ + CARD8 VDIFId[4]; /* alway "VDIF" */ + CARD32 FileLength; /* lenght of the whole file */ + CARD32 Checksum; /* sum of all bytes in the file after*/ + /* this field */ + CARD16 VDIFVersion; /* structure version number */ + CARD16 VDIFRevision; /* structure revision number */ + CARD16 Date[3]; /* file date Year/Month/Day */ + CARD16 DateManufactured[3]; /* date Year/Month/Day */ + CARD32 FileRevision; /* file revision string */ + CARD32 Manufacturer; /* ASCII ID of the manufacturer */ + CARD32 ModelNumber; /* ASCII ID of the model */ + CARD32 MinVDIFIndex; /* ASCII ID of Minimum VDIF index */ + CARD32 Version; /* ASCII ID of the model version */ + CARD32 SerialNumber; /* ASCII ID of the serial number */ + CARD8 MonitorType; /* Monochrome or Color */ + CARD8 CRTSize; /* inches */ + CARD8 BorderRed; /* percent */ + CARD8 BorderGreen; /* percent */ + CARD8 BorderBlue; /* percent */ + CARD8 Reserved1; /* padding */ + CARD16 Reserved2; /* padding */ + CARD32 RedPhosphorDecay; /* microseconds */ + CARD32 GreenPhosphorDecay; /* microseconds */ + CARD32 BluePhosphorDecay; /* microseconds */ + CARD16 WhitePoint_x; /* WhitePoint in CIExyY (scale 1000) */ + CARD16 WhitePoint_y; + CARD16 WhitePoint_Y; + CARD16 RedChromaticity_x; /* Red chromaticity in x,y */ + CARD16 RedChromaticity_y; + CARD16 GreenChromaticity_x; /* Green chromaticity in x,y */ + CARD16 GreenChromaticity_y; + CARD16 BlueChromaticity_x; /* Blue chromaticity in x,y */ + CARD16 BlueChromaticity_y; + CARD16 RedGamma; /* Gamme curve exponent (scale 1000) */ + CARD16 GreenGamma; + CARD16 BlueGamma; + CARD32 NumberOperationalLimits; + CARD32 OffsetOperationalLimits; + CARD32 NumberOptions; /* optinal sections (gamma table) */ + CARD32 OffsetOptions; + CARD32 OffsetStringTable; +} xf86VdifRec, *xf86VdifPtr; + +typedef enum { /* Tags for section identification */ + VDIF_OPERATIONAL_LIMITS_TAG = 1, + VDIF_PREADJUSTED_TIMING_TAG, + VDIF_GAMMA_TABLE_TAG +} VDIFScnTag; + +typedef struct _VDIFScnHdr { /* Generic Section Header: */ + CARD32 ScnLength; /* lenght of section */ + CARD32 ScnTag; /* tag for section identification */ +} VDIFScnHdrRec, *VDIFScnHdrPtr; + +typedef struct _VDIFLimits { /* Operational Limits: */ + VDIFScnHdrRec Header; /* common section info */ + CARD16 MaxHorPixel; /* pixels */ + CARD16 MaxVerPixel; /* lines */ + CARD16 MaxHorActiveLength; /* millimeters */ + CARD16 MaxVerActiveHeight; /* millimeters */ + CARD8 VideoType; /* TTL / Analog / ECL / DECL */ + CARD8 SyncType; /* TTL / Analog / ECL / DECL */ + CARD8 SyncConfiguration; /* separate / composite / other */ + CARD8 Reserved1; /* padding */ + CARD16 Reserved2; /* padding */ + CARD16 TerminationResistance; /* */ + CARD16 WhiteLevel; /* millivolts */ + CARD16 BlackLevel; /* millivolts */ + CARD16 BlankLevel; /* millivolts */ + CARD16 SyncLevel; /* millivolts */ + CARD32 MaxPixelClock; /* kiloHertz */ + CARD32 MinHorFrequency; /* Hertz */ + CARD32 MaxHorFrequency; /* Hertz */ + CARD32 MinVerFrequency; /* milliHertz */ + CARD32 MaxVerFrequency; /* milliHertz */ + CARD16 MinHorRetrace; /* nanoseconds */ + CARD16 MinVerRetrace; /* microseconds */ + CARD32 NumberPreadjustedTimings; + CARD32 OffsetNextLimits; +} xf86VdifLimitsRec, *xf86VdifLimitsPtr; + +typedef struct _VDIFTiming { /* Preadjusted Timing: */ + VDIFScnHdrRec Header; /* common section info */ + CARD32 PreadjustedTimingName; /* SVGA/SVPMI mode number */ + CARD16 HorPixel; /* pixels */ + CARD16 VerPixel; /* lines */ + CARD16 HorAddrLength; /* millimeters */ + CARD16 VerAddrHeight; /* millimeters */ + CARD8 PixelWidthRatio; /* gives H:V */ + CARD8 PixelHeightRatio; + CARD8 Reserved1; /* padding */ + CARD8 ScanType; /* noninterlaced / interlaced / other*/ + CARD8 HorSyncPolarity; /* negative / positive */ + CARD8 VerSyncPolarity; /* negative / positive */ + CARD16 CharacterWidth; /* pixels */ + CARD32 PixelClock; /* kiloHertz */ + CARD32 HorFrequency; /* Hertz */ + CARD32 VerFrequency; /* milliHertz */ + CARD32 HorTotalTime; /* nanoseconds */ + CARD32 VerTotalTime; /* microseconds */ + CARD16 HorAddrTime; /* nanoseconds */ + CARD16 HorBlankStart; /* nanoseconds */ + CARD16 HorBlankTime; /* nanoseconds */ + CARD16 HorSyncStart; /* nanoseconds */ + CARD16 HorSyncTime; /* nanoseconds */ + CARD16 VerAddrTime; /* microseconds */ + CARD16 VerBlankStart; /* microseconds */ + CARD16 VerBlankTime; /* microseconds */ + CARD16 VerSyncStart; /* microseconds */ + CARD16 VerSyncTime; /* microseconds */ +} xf86VdifTimingRec, *xf86VdifTimingPtr; + +typedef struct _VDIFGamma { /* Gamma Table: */ + VDIFScnHdrRec Header; /* common section info */ + CARD16 GammaTableEntries; /* count of grays or RGB 3-tuples */ + CARD16 Unused1; +} xf86VdifGammaRec, *xf86VdifGammaPtr; + +/* access macros */ +#define VDIF_OPERATIONAL_LIMITS(vdif) \ +((xf86VdifLimitsPtr)((char*)(vdif) + (vdif)->OffsetOperationalLimits)) +#define VDIF_NEXT_OPERATIONAL_LIMITS(limits) limits = \ + ((xf86VdifLimitsPtr)((char*)(limits) + (limits)->OffsetNextLimits)) +#define VDIF_PREADJUSTED_TIMING(limits) \ +((xf86VdifTimingPtr)((char*)(limits) + (limits)->Header.ScnLength)) +#define VDIF_NEXT_PREADJUSTED_TIMING(timing) timing = \ + ((xf86VdifTimingPtr)((char*)(timing) + (timing)->Header.ScnLength)) +#define VDIF_OPTIONS(vdif) \ + ((VDIFScnHdrPtr)((char*)(vdif) + (vdif)->OffsetOptions)) +#define VDIF_NEXT_OPTIONS(options) options = \ + ((xf86VdifGammaPtr)((char*)(options) + (options)->Header.ScnLength)) +#define VDIF_STRING(vdif, string) \ + ((char*)((char*)vdif + vdif->OffsetStringTable + (string))) + +typedef struct _vdif { + xf86VdifPtr vdif; + xf86VdifLimitsPtr *limits; + xf86VdifTimingPtr *timings; + xf86VdifGammaPtr *gamma; + char * strings; +} xf86vdif, *xf86vdifPtr; + +#undef CARD32 + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaHW.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaHW.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaHW.h (revision 51223) @@ -0,0 +1,237 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.h,v 1.31 2002/04/04 14:05:56 eich Exp $ */ + + +/* + * Copyright (c) 1997,1998 The XFree86 Project, Inc. + * + * Loosely based on code bearing the following copyright: + * + * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. + * + * Author: Dirk Hohndel + */ + +#ifndef _VGAHW_H +#define _VGAHW_H + +#include +#include "misc.h" +#include "input.h" +#include "scrnintstr.h" +#include "colormapst.h" + +#include "xf86str.h" +#include "xf86Pci.h" + +#include "xf86DDC.h" + +#include "globals.h" +#define DPMS_SERVER +#include + +extern int vgaHWGetIndex(void); + +/* + * access macro + */ +#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr)) + +/* Standard VGA registers */ +#define VGA_ATTR_INDEX 0x3C0 +#define VGA_ATTR_DATA_W 0x3C0 +#define VGA_ATTR_DATA_R 0x3C1 +#define VGA_IN_STAT_0 0x3C2 /* read */ +#define VGA_MISC_OUT_W 0x3C2 /* write */ +#define VGA_ENABLE 0x3C3 +#define VGA_SEQ_INDEX 0x3C4 +#define VGA_SEQ_DATA 0x3C5 +#define VGA_DAC_MASK 0x3C6 +#define VGA_DAC_READ_ADDR 0x3C7 +#define VGA_DAC_WRITE_ADDR 0x3C8 +#define VGA_DAC_DATA 0x3C9 +#define VGA_FEATURE_R 0x3CA /* read */ +#define VGA_MISC_OUT_R 0x3CC /* read */ +#define VGA_GRAPH_INDEX 0x3CE +#define VGA_GRAPH_DATA 0x3CF + +#define VGA_IOBASE_MONO 0x3B0 +#define VGA_IOBASE_COLOR 0x3D0 + +#define VGA_CRTC_INDEX_OFFSET 0x04 +#define VGA_CRTC_DATA_OFFSET 0x05 +#define VGA_IN_STAT_1_OFFSET 0x0A /* read */ +#define VGA_FEATURE_W_OFFSET 0x0A /* write */ + +/* default number of VGA registers stored internally */ +#define VGA_NUM_CRTC 25 +#define VGA_NUM_SEQ 5 +#define VGA_NUM_GFX 9 +#define VGA_NUM_ATTR 21 + +/* Flags for vgaHWSave() and vgaHWRestore() */ +#define VGA_SR_MODE 0x01 +#define VGA_SR_FONTS 0x02 +#define VGA_SR_CMAP 0x04 +#define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP) + +/* Defaults for the VGA memory window */ +#define VGA_DEFAULT_PHYS_ADDR 0xA0000 +#define VGA_DEFAULT_MEM_SIZE (64 * 1024) + +/* + * vgaRegRec contains settings of standard VGA registers. + */ +typedef struct { + unsigned char MiscOutReg; /* */ + unsigned char *CRTC; /* Crtc Controller */ + unsigned char *Sequencer; /* Video Sequencer */ + unsigned char *Graphics; /* Video Graphics */ + unsigned char *Attribute; /* Video Atribute */ + unsigned char DAC[768]; /* Internal Colorlookuptable */ + unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */ + unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */ + unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */ + unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */ +} vgaRegRec, *vgaRegPtr; + +typedef struct _vgaHWRec *vgaHWPtr; + +typedef void (*vgaHWWriteIndexProcPtr)(vgaHWPtr hwp, CARD8 indx, CARD8 value); +typedef CARD8 (*vgaHWReadIndexProcPtr)(vgaHWPtr hwp, CARD8 indx); +typedef void (*vgaHWWriteProcPtr)(vgaHWPtr hwp, CARD8 value); +typedef CARD8 (*vgaHWReadProcPtr)(vgaHWPtr hwp); +typedef void (*vgaHWMiscProcPtr)(vgaHWPtr hwp); + + +/* + * vgaHWRec contains per-screen information required by the vgahw module. + * + * Note, the palette referred to by the paletteEnabled, enablePalette and + * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed + * via the first 17 attribute registers and not the main 8-bit palette. + */ +typedef struct _vgaHWRec { + pointer Base; /* Address of "VGA" memory */ + int MapSize; /* Size of "VGA" memory */ + unsigned long MapPhys; /* phys location of VGA mem */ + int IOBase; /* I/O Base address */ + CARD8 * MMIOBase; /* Pointer to MMIO start */ + int MMIOOffset; /* base + offset + vgareg + = mmioreg */ + pointer FontInfo1; /* save area for fonts in + plane 2 */ + pointer FontInfo2; /* save area for fonts in + plane 3 */ + pointer TextInfo; /* save area for text */ + vgaRegRec SavedReg; /* saved registers */ + vgaRegRec ModeReg; /* register settings for + current mode */ + Bool ShowOverscan; + Bool paletteEnabled; + Bool cmapSaved; + ScrnInfoPtr pScrn; + vgaHWWriteIndexProcPtr writeCrtc; + vgaHWReadIndexProcPtr readCrtc; + vgaHWWriteIndexProcPtr writeGr; + vgaHWReadIndexProcPtr readGr; + vgaHWReadProcPtr readST00; + vgaHWReadProcPtr readST01; + vgaHWReadProcPtr readFCR; + vgaHWWriteProcPtr writeFCR; + vgaHWWriteIndexProcPtr writeAttr; + vgaHWReadIndexProcPtr readAttr; + vgaHWWriteIndexProcPtr writeSeq; + vgaHWReadIndexProcPtr readSeq; + vgaHWWriteProcPtr writeMiscOut; + vgaHWReadProcPtr readMiscOut; + vgaHWMiscProcPtr enablePalette; + vgaHWMiscProcPtr disablePalette; + vgaHWWriteProcPtr writeDacMask; + vgaHWReadProcPtr readDacMask; + vgaHWWriteProcPtr writeDacWriteAddr; + vgaHWWriteProcPtr writeDacReadAddr; + vgaHWWriteProcPtr writeDacData; + vgaHWReadProcPtr readDacData; + pointer ddc; + IOADDRESS PIOOffset; /* offset + vgareg + = pioreg */ + vgaHWReadProcPtr readEnable; + vgaHWWriteProcPtr writeEnable; + PCITAG Tag; +} vgaHWRec; + +/* Some macros that VGA drivers can use in their ChipProbe() function */ +#define VGAHW_GET_IOBASE() ((inb(VGA_MISC_OUT_R) & 0x01) ? \ + VGA_IOBASE_COLOR : VGA_IOBASE_MONO) + +#define OVERSCAN 0x11 /* Index of OverScan register */ + +/* Flags that define how overscan correction should take place */ +#define KGA_FIX_OVERSCAN 1 /* overcan correction required */ +#define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */ + /* of next scanline/frame */ +#define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */ + /* to total - 1 */ +#define BIT_PLANE 3 /* Which plane we write to in mono mode */ +#define BITS_PER_GUN 6 +#define COLORMAP_SIZE 256 + +#if defined(__powerpc__) +#define DACDelay(hw) /* No legacy VGA support */ +#else +#define DACDelay(hw) \ + do { \ + (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \ + (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \ + } while (0) +#endif + +/* Function Prototypes */ + +/* vgaHW.c */ + +typedef void vgaHWProtectProc(ScrnInfoPtr, Bool); +typedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool); + +void vgaHWSetStdFuncs(vgaHWPtr hwp); +void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset); +void vgaHWProtect(ScrnInfoPtr pScrn, Bool on); +vgaHWProtectProc *vgaHWProtectWeak(void); +Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode); +void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on); +vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void); +void vgaHWSeqReset(vgaHWPtr hwp, Bool start); +void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore); +void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags); +void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save); +void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save, int flags); +Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode); +Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC, int numSequencer, + int numGraphics, int numAttribute); +Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src); +Bool vgaHWGetHWRec(ScrnInfoPtr scrp); +void vgaHWFreeHWRec(ScrnInfoPtr scrp); +Bool vgaHWMapMem(ScrnInfoPtr scrp); +void vgaHWUnmapMem(ScrnInfoPtr scrp); +void vgaHWGetIOBase(vgaHWPtr hwp); +void vgaHWLock(vgaHWPtr hwp); +void vgaHWUnlock(vgaHWPtr hwp); +void vgaHWEnable(vgaHWPtr hwp); +void vgaHWDisable(vgaHWPtr hwp); +void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags); +Bool vgaHWHandleColormaps(ScreenPtr pScreen); +void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed); +CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits, + unsigned int Flags); +CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits, + unsigned int Flags); +Bool vgaHWAllocDefaultRegs(vgaRegPtr regp); + +DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void); +SaveScreenProcPtr vgaHWSaveScreenWeak(void); + +#endif /* _VGAHW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaReg.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaReg.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaReg.h (revision 51223) @@ -0,0 +1,140 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/vgaReg.h,v 1.3 1999/06/06 08:49:07 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ + +/* $XConsortium: vgaReg.h /main/4 1996/02/21 17:59:02 kaleb $ */ + +#define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value ) +#define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) +#define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) +/* GJA -- deleted RTIO and ATRIO case here, so that a PCIO #define became + * superfluous. + */ +#define SET_INDEXED_REGISTER(RegGroup, Index, Value) \ + (SET_BYTE_REGISTER(RegGroup, Index), \ + SET_BYTE_REGISTER((RegGroup) + 1, Value)) + +/* There is a jumper on the ega to change this to 0x200 instead !! */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if 0 /* This is now a stack variable, as needed */ +#define REGBASE 0x300 +#endif + +#define AttributeIndexRegister REGBASE + 0xC0 +#define AttributeDataWriteRegister REGBASE + 0xC0 +#define AttributeDataReadRegister REGBASE + 0xC1 +#define AttributeRegister AttributeIndexRegister +#define AttributeModeIndex 0x30 +#define OverScanColorIndex 0x31 +#define ColorPlaneEnableIndex 0x32 +#define HorizPelPanIndex 0x33 +#define ColorSelectIndex 0x34 +#ifndef PC98_EGC +#define SetVideoAttributeIndex( index ) \ + SET_INDEX_REGISTER( AttributeIndexRegister, index ) +#define SetVideoAttribute( index, value ) \ + SetVideoAttributeIndex( index ) ; \ + SET_BYTE_REGISTER( AttributeDataWriteRegister, value ) +#endif + + /* Graphics Registers 03CE & 03CF */ +#define GraphicsIndexRegister REGBASE + 0xCE +#define GraphicsDataRegister REGBASE + 0xCF +#define GraphicsRegister GraphicsIndexRegister +#define Set_ResetIndex 0x00 +#define Enb_Set_ResetIndex 0x01 +#define Color_CompareIndex 0x02 +#define Data_RotateIndex 0x03 +#define Read_Map_SelectIndex 0x04 +#define Graphics_ModeIndex 0x05 +#define MiscellaneousIndex 0x06 +#define Color_Dont_CareIndex 0x07 +#define Bit_MaskIndex 0x08 +#ifndef PC98_EGC +#define SetVideoGraphicsIndex( index ) \ + SET_INDEX_REGISTER( GraphicsIndexRegister, index ) +#define SetVideoGraphicsData( value ) \ + SET_INDEX_REGISTER( GraphicsDataRegister, value ) +#define SetVideoGraphics( index, value ) \ + SET_INDEXED_REGISTER( GraphicsRegister, index, value ) +#endif + +/* Sequencer Registers 03C4 & 03C5 */ +#define SequencerIndexRegister REGBASE + 0xC4 +#define SequencerDataRegister REGBASE + 0xC5 +#define SequencerRegister SequencerIndexRegister +#define Seq_ResetIndex 00 +#define Clock_ModeIndex 01 +#define Mask_MapIndex 02 +#define Char_Map_SelectIndex 03 +#define Memory_ModeIndex 04 +#ifndef PC98_EGC +#define SetVideoSequencerIndex( index ) \ + SET_INDEX_REGISTER( SequencerIndexRegister, index ) +#define SetVideoSequencer( index, value ) \ + SET_INDEXED_REGISTER( SequencerRegister, index, value ) +#endif + +/* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */ +/* for the Graphics' Data_Rotate Register */ +#define VGA_ROTATE_FUNC_SHIFT 3 +#define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */ +#define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */ +#define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */ +#define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */ +/* for the Graphics' Graphics_Mode Register */ +#define VGA_READ_MODE_SHIFT 3 +#define VGA_WRITE_MODE_0 0 +#define VGA_WRITE_MODE_1 1 +#define VGA_WRITE_MODE_2 2 +#define VGA_WRITE_MODE_3 3 +#define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT ) +#define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT ) + +#ifdef PC98_EGC +/* I/O port address define for extended EGC */ +#define EGC_PLANE 0x4a0 /* EGC active plane select */ +#define EGC_READ 0x4a2 /* EGC FGC,EGC,Read Plane */ +#define EGC_MODE 0x4a4 /* EGC Mode register & ROP */ +#define EGC_FGC 0x4a6 /* EGC Forground color */ +#define EGC_MASK 0x4a8 /* EGC Mask register */ +#define EGC_BGC 0x4aa /* EGC Background color */ +#define EGC_ADD 0x4ac /* EGC Dest/Source address */ +#define EGC_LENGTH 0x4ae /* EGC Bit length */ + +#define PALETTE_ADD 0xa8 /* Palette address */ +#define PALETTE_GRE 0xaa /* Palette Green */ +#define PALETTE_RED 0xac /* Palette Red */ +#define PALETTE_BLU 0xae /* Palette Blue */ + +#define EGC_AND_MODE 0x2c8c /* (S&P&D)|(~S&D) */ +#define EGC_AND_INV_MODE 0x2c2c /* (S&P&~D)|(~S&D) */ +#define EGC_OR_MODE 0x2cec /* S&(P|D)|(~S&D) */ +#define EGC_OR_INV_MODE 0x2cbc /* S&(P|~D)|(~S&D) */ +#define EGC_XOR_MODE 0x2c6c /* (S&(P&~D|~P&D))|(~S&D) */ +#define EGC_XOR_INV_MODE 0x2c9c /* (S&(P&D)|(~P&~D))|(~S&D) */ +#define EGC_COPY_MODE 0x2cac /* (S&P)|(~S&D) */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaVideo.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaVideo.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vgaVideo.h (revision 51223) @@ -0,0 +1,96 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/vgaVideo.h,v 1.1.2.1 1998/06/27 14:48:54 dawes Exp $ */ +/* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * +*/ + +/* $XConsortium: vgaVideo.h /main/4 1996/02/21 17:59:14 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "misc.h" /* GJA -- for pointer data type */ +#ifdef lint +#if defined(volatile) +#undef volatile +#endif +#define volatile /**/ +#if defined(const) +#undef const +#endif +#define const /**/ +#if defined(signed) +#undef signed +#endif +#define signed /**/ +#endif + +/* + * References to all pc ( i.e. '286 ) memory in the + * regions used by the [ev]ga server ( the 128K windows ) + * MUST be long-word ( i.e. 32-bit ) reads or writes. + * This definition will change for other memory architectures + * ( e.g. AIX-Rt ) + */ +typedef unsigned char VideoAdapterObject ; +typedef volatile VideoAdapterObject *VideoMemoryPtr ; +typedef volatile VideoAdapterObject *VgaMemoryPtr ; +#if !defined(BITMAP_BIT_ORDER) +#define BITMAP_BIT_ORDER MSBFirst +#endif + +#if !defined(IMAGE_BYTE_ORDER) +#define IMAGE_BYTE_ORDER LSBFirst +#endif + +/* Bit Ordering Macros */ +#if !defined(SCRLEFT8) +#define SCRLEFT8(lw, n) ( (unsigned char) (((unsigned char) lw) << (n)) ) +#endif +#if !defined(SCRRIGHT8) +#define SCRRIGHT8(lw, n) ( (unsigned char) (((unsigned char)lw) >> (n)) ) +#endif +/* These work ONLY on 8-bit wide Quantities !! */ +#define LeftmostBit ( SCRLEFT8( 0xFF, 7 ) & 0xFF ) +#define RightmostBit ( SCRRIGHT8( 0xFF, 7 ) & 0xFF ) + +/* + * [ev]ga video screen defines & macros + */ +#define VGA_BLACK_PIXEL 0 +#define VGA_WHITE_PIXEL 1 + +#define VGA_MAXPLANES 4 +#define VGA_ALLPLANES 0xFL + +#define VIDBASE(pDraw) ((volatile unsigned char *) \ + (((PixmapPtr)(((DrawablePtr)(pDraw))->pScreen->devPrivate))-> \ + devPrivate.ptr)) +#define BYTES_PER_LINE(pDraw) \ + ((int)((PixmapPtr)(((DrawablePtr)(pDraw))->pScreen->devPrivate))->devKind) + +#define ROW_OFFSET( x ) ( ( x ) >> 3 ) +#define BIT_OFFSET( x ) ( ( x ) & 0x7 ) +#define SCREENADDRESS( pWin, x, y ) \ + ( VIDBASE(pWin) + (y) * BYTES_PER_LINE(pWin) + ROW_OFFSET(x) ) + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmode.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmode.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmode.h (revision 51223) @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2000 by Conectiva S.A. (http://www.conectiva.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * CONECTIVA LINUX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Conectiva Linux shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from + * Conectiva Linux. + * + * Author: Paulo César Pereira de Andrade + * + * $XFree86: xc/programs/Xserver/hw/xfree86/xf86cfg/vidmode.h,v 1.1 2000/05/18 16:30:00 dawes Exp $ + */ + +#ifndef _xf86cfg_vidmode_h +#define _xf86cfg_vidmode_h + +#include "xf86config.h" +#include + +/* + * Types + */ +struct _xf86cfgVidMode { + XF86ConfMonitorPtr monitor; + int screen; + int num_infos; + XF86VidModeModeInfo **infos; +}; + +/* + * Prototypes + */ +Bool VideoModeInitialize(void); +void VideoModeConfigureStart(void); +void VideoModeConfigureEnd(void); +void VidmodeRestoreAction(Widget, XEvent*, String*, Cardinal*); +void CancelAddModeAction(Widget, XEvent*, String*, Cardinal*); +void CancelTestModeAction(Widget, XEvent*, String*, Cardinal*); +void InitializeVidmodes(void); + +/* + * Initialization + */ +extern Widget vtune; + +#endif /* _xf86cfg_vidmode_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmodeproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmodeproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/vidmodeproc.h (revision 51223) @@ -0,0 +1,78 @@ +/* $XFree86: xc/programs/Xserver/Xext/vidmodeproc.h,v 1.4 1999/12/13 01:39:40 robin Exp $ */ + +/* Prototypes for DGA functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _VIDMODEPROC_H_ +#define _VIDMODEPROC_H_ + + +typedef enum { + VIDMODE_H_DISPLAY, + VIDMODE_H_SYNCSTART, + VIDMODE_H_SYNCEND, + VIDMODE_H_TOTAL, + VIDMODE_H_SKEW, + VIDMODE_V_DISPLAY, + VIDMODE_V_SYNCSTART, + VIDMODE_V_SYNCEND, + VIDMODE_V_TOTAL, + VIDMODE_FLAGS, + VIDMODE_CLOCK +} VidModeSelectMode; + +typedef enum { + VIDMODE_MON_VENDOR, + VIDMODE_MON_MODEL, + VIDMODE_MON_NHSYNC, + VIDMODE_MON_NVREFRESH, + VIDMODE_MON_HSYNC_LO, + VIDMODE_MON_HSYNC_HI, + VIDMODE_MON_VREFRESH_LO, + VIDMODE_MON_VREFRESH_HI +} VidModeSelectMonitor; + +typedef union { + pointer ptr; + int i; + float f; +} vidMonitorValue; + +void XFree86VidModeExtensionInit(void); + +Bool VidModeAvailable(int scrnIndex); +Bool VidModeGetCurrentModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeGetFirstModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeGetNextModeline(int scrnIndex, pointer *mode, int *dotClock); +Bool VidModeDeleteModeline(int scrnIndex, pointer mode); +Bool VidModeZoomViewport(int scrnIndex, int zoom); +Bool VidModeGetViewPort(int scrnIndex, int *x, int *y); +Bool VidModeSetViewPort(int scrnIndex, int x, int y); +Bool VidModeSwitchMode(int scrnIndex, pointer mode); +Bool VidModeLockZoom(int scrnIndex, Bool lock); +Bool VidModeGetMonitor(int scrnIndex, pointer *monitor); +int VidModeGetNumOfClocks(int scrnIndex, Bool *progClock); +Bool VidModeGetClocks(int scrnIndex, int *Clocks); +ModeStatus VidModeCheckModeForMonitor(int scrnIndex, pointer mode); +ModeStatus VidModeCheckModeForDriver(int scrnIndex, pointer mode); +void VidModeSetCrtcForMode(int scrnIndex, pointer mode); +Bool VidModeAddModeline(int scrnIndex, pointer mode); +int VidModeGetDotClock(int scrnIndex, int Clock); +int VidModeGetNumOfModes(int scrnIndex); +Bool VidModeSetGamma(int scrnIndex, float red, float green, float blue); +Bool VidModeGetGamma(int scrnIndex, float *red, float *green, float *blue); +pointer VidModeCreateMode(void); +void VidModeCopyMode(pointer modefrom, pointer modeto); +int VidModeGetModeValue(pointer mode, int valtyp); +void VidModeSetModeValue(pointer mode, int valtyp, int val); +vidMonitorValue VidModeGetMonitorValue(pointer monitor, int valtyp, int indx); +Bool VidModeSetGammaRamp(int, int, CARD16 *, CARD16 *, CARD16 *); +Bool VidModeGetGammaRamp(int, int, CARD16 *, CARD16 *, CARD16 *); +int VidModeGetGammaRampSize(int scrnIndex); + +#endif + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/window.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/window.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/window.h (revision 51223) @@ -0,0 +1,276 @@ +/* $Xorg: window.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86$ */ + +#ifndef WINDOW_H +#define WINDOW_H + +#include "misc.h" +#include "region.h" +#include "screenint.h" +#include + +#define TOTALLY_OBSCURED 0 +#define UNOBSCURED 1 +#define OBSCURED 2 + +#define VisibilityNotViewable 3 + +/* return values for tree-walking callback procedures */ +#define WT_STOPWALKING 0 +#define WT_WALKCHILDREN 1 +#define WT_DONTWALKCHILDREN 2 +#define WT_NOMATCH 3 +#define NullWindow ((WindowPtr) 0) + +typedef struct _BackingStore *BackingStorePtr; +typedef struct _Window *WindowPtr; + +typedef int (*VisitWindowProcPtr)( + WindowPtr /*pWin*/, + pointer /*data*/); + +extern int TraverseTree( + WindowPtr /*pWin*/, + VisitWindowProcPtr /*func*/, + pointer /*data*/); + +extern int WalkTree( + ScreenPtr /*pScreen*/, + VisitWindowProcPtr /*func*/, + pointer /*data*/); + +extern WindowPtr AllocateWindow( + ScreenPtr /*pScreen*/); + +extern Bool CreateRootWindow( + ScreenPtr /*pScreen*/); + +extern void InitRootWindow( + WindowPtr /*pWin*/); + +extern void ClippedRegionFromBox( + WindowPtr /*pWin*/, + RegionPtr /*Rgn*/, + int /*x*/, + int /*y*/, + int /*w*/, + int /*h*/); + +typedef WindowPtr (* RealChildHeadProc) (WindowPtr pWin); + +void RegisterRealChildHeadProc (RealChildHeadProc proc); + +extern WindowPtr RealChildHead( + WindowPtr /*pWin*/); + +extern WindowPtr CreateWindow( + Window /*wid*/, + WindowPtr /*pParent*/, + int /*x*/, + int /*y*/, + unsigned int /*w*/, + unsigned int /*h*/, + unsigned int /*bw*/, + unsigned int /*class*/, + Mask /*vmask*/, + XID* /*vlist*/, + int /*depth*/, + ClientPtr /*client*/, + VisualID /*visual*/, + int* /*error*/); + +extern int DeleteWindow( + pointer /*pWin*/, + XID /*wid*/); + +extern void DestroySubwindows( + WindowPtr /*pWin*/, + ClientPtr /*client*/); + +/* Quartz support on Mac OS X uses the HIToolbox + framework whose ChangeWindowAttributes function conflicts here. */ +#ifdef __DARWIN__ +#define ChangeWindowAttributes Darwin_X_ChangeWindowAttributes +#endif +extern int ChangeWindowAttributes( + WindowPtr /*pWin*/, + Mask /*vmask*/, + XID* /*vlist*/, + ClientPtr /*client*/); + +/* Quartz support on Mac OS X uses the HIToolbox + framework whose GetWindowAttributes function conflicts here. */ +#ifdef __DARWIN__ +#define GetWindowAttributes(w,c,x) Darwin_X_GetWindowAttributes(w,c,x) +extern void Darwin_X_GetWindowAttributes( +#else +extern void GetWindowAttributes( +#endif + WindowPtr /*pWin*/, + ClientPtr /*client*/, + xGetWindowAttributesReply* /* wa */); + +extern RegionPtr CreateUnclippedWinSize( + WindowPtr /*pWin*/); + +extern void GravityTranslate( + int /*x*/, + int /*y*/, + int /*oldx*/, + int /*oldy*/, + int /*dw*/, + int /*dh*/, + unsigned /*gravity*/, + int* /*destx*/, + int* /*desty*/); + +extern int ConfigureWindow( + WindowPtr /*pWin*/, + Mask /*mask*/, + XID* /*vlist*/, + ClientPtr /*client*/); + +extern int CirculateWindow( + WindowPtr /*pParent*/, + int /*direction*/, + ClientPtr /*client*/); + +extern int ReparentWindow( + WindowPtr /*pWin*/, + WindowPtr /*pParent*/, + int /*x*/, + int /*y*/, + ClientPtr /*client*/); + +extern int MapWindow( + WindowPtr /*pWin*/, + ClientPtr /*client*/); + +extern void MapSubwindows( + WindowPtr /*pParent*/, + ClientPtr /*client*/); + +extern int UnmapWindow( + WindowPtr /*pWin*/, + Bool /*fromConfigure*/); + +extern void UnmapSubwindows( + WindowPtr /*pWin*/); + +extern void HandleSaveSet( + ClientPtr /*client*/); + +extern Bool VisibleBoundingBoxFromPoint( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/, + BoxPtr /*box*/); + +extern Bool PointInWindowIsVisible( + WindowPtr /*pWin*/, + int /*x*/, + int /*y*/); + +extern RegionPtr NotClippedByChildren( + WindowPtr /*pWin*/); + +extern void SendVisibilityNotify( + WindowPtr /*pWin*/); + +extern void SaveScreens( + int /*on*/, + int /*mode*/); + +extern WindowPtr FindWindowWithOptional( + WindowPtr /*w*/); + +extern void CheckWindowOptionalNeed( + WindowPtr /*w*/); + +extern Bool MakeWindowOptional( + WindowPtr /*pWin*/); + +extern void DisposeWindowOptional( + WindowPtr /*pWin*/); + +extern WindowPtr MoveWindowInStack( + WindowPtr /*pWin*/, + WindowPtr /*pNextSib*/); + +void SetWinSize( + WindowPtr /*pWin*/); + +void SetBorderSize( + WindowPtr /*pWin*/); + +void ResizeChildrenWinSize( + WindowPtr /*pWin*/, + int /*dx*/, + int /*dy*/, + int /*dw*/, + int /*dh*/); + +extern void SendShapeNotify( + WindowPtr /* pWin */, + int /* which */ ); + +extern RegionPtr CreateBoundingShape( + WindowPtr /* pWin */ ); + +extern RegionPtr CreateClipShape( + WindowPtr /* pWin */ ); + +extern void DisableMapUnmapEvents( + WindowPtr /* pWin */ ); +extern void EnableMapUnmapEvents( + WindowPtr /* pWin */ ); +extern Bool MapUnmapEventsEnabled( + WindowPtr /* pWin */ ); + +#endif /* WINDOW_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/windowstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/windowstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/windowstr.h (revision 51223) @@ -0,0 +1,234 @@ +/* $Xorg: windowstr.h,v 1.4 2001/02/09 02:05:16 xorgcvs Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/include/windowstr.h,v 1.6 2001/12/14 19:59:57 dawes Exp $ */ + +#ifndef WINDOWSTRUCT_H +#define WINDOWSTRUCT_H + +#include "window.h" +#include "pixmapstr.h" +#include "regionstr.h" +#include "cursor.h" +#include "property.h" +#include "resource.h" /* for ROOT_WINDOW_ID_BASE */ +#include "dix.h" +#include "miscstruct.h" +#include +#include "opaque.h" + +#define GuaranteeNothing 0 +#define GuaranteeVisBack 1 + +#define SameBackground(as, a, bs, b) \ + ((as) == (bs) && ((as) == None || \ + (as) == ParentRelative || \ + SamePixUnion(a,b,as == BackgroundPixel))) + +#define SameBorder(as, a, bs, b) \ + EqualPixUnion(as, a, bs, b) + +typedef struct _WindowOpt { + VisualID visual; /* default: same as parent */ + CursorPtr cursor; /* default: window.cursorNone */ + Colormap colormap; /* default: same as parent */ + Mask dontPropagateMask; /* default: window.dontPropagate */ + Mask otherEventMasks; /* default: 0 */ + struct _OtherClients *otherClients; /* default: NULL */ + struct _GrabRec *passiveGrabs; /* default: NULL */ + PropertyPtr userProps; /* default: NULL */ + unsigned long backingBitPlanes; /* default: ~0L */ + unsigned long backingPixel; /* default: 0 */ +#ifdef SHAPE + RegionPtr boundingShape; /* default: NULL */ + RegionPtr clipShape; /* default: NULL */ + RegionPtr inputShape; /* default: NULL */ +#endif +#ifdef XINPUT + struct _OtherInputMasks *inputMasks; /* default: NULL */ +#endif +} WindowOptRec, *WindowOptPtr; + +#define BackgroundPixel 2L +#define BackgroundPixmap 3L + +typedef struct _Window { + DrawableRec drawable; + WindowPtr parent; /* ancestor chain */ + WindowPtr nextSib; /* next lower sibling */ + WindowPtr prevSib; /* next higher sibling */ + WindowPtr firstChild; /* top-most child */ + WindowPtr lastChild; /* bottom-most child */ + RegionRec clipList; /* clipping rectangle for output */ + RegionRec borderClip; /* NotClippedByChildren + border */ + union _Validate *valdata; + RegionRec winSize; + RegionRec borderSize; + DDXPointRec origin; /* position relative to parent */ + unsigned short borderWidth; + unsigned short deliverableEvents; + Mask eventMask; + PixUnion background; + PixUnion border; + pointer backStorage; /* null when BS disabled */ + WindowOptPtr optional; + unsigned backgroundState:2; /* None, Relative, Pixel, Pixmap */ + unsigned borderIsPixel:1; + unsigned cursorIsNone:1; /* else real cursor (might inherit) */ + unsigned backingStore:2; + unsigned saveUnder:1; + unsigned DIXsaveUnder:1; + unsigned bitGravity:4; + unsigned winGravity:4; + unsigned overrideRedirect:1; + unsigned visibility:2; + unsigned mapped:1; + unsigned realized:1; /* ancestors are all mapped */ + unsigned viewable:1; /* realized && InputOutput */ + unsigned dontPropagate:3;/* index into DontPropagateMasks */ + unsigned forcedBS:1; /* system-supplied backingStore */ +#ifdef NEED_DBE_BUF_BITS +#define DBE_FRONT_BUFFER 1 +#define DBE_BACK_BUFFER 0 + unsigned dstBuffer:1; /* destination buffer for rendering */ + unsigned srcBuffer:1; /* source buffer for rendering */ +#endif +#ifdef COMPOSITE + unsigned redirectDraw:1; /* rendering is redirected from here */ +#endif + DevUnion *devPrivates; +} WindowRec; + +/* + * Ok, a bunch of macros for accessing the optional record + * fields (or filling the appropriate default value) + */ + +extern Mask DontPropagateMasks[]; + +#define wTrackParent(w,field) ((w)->optional ? \ + (w)->optional->field \ + : FindWindowWithOptional(w)->optional->field) +#define wUseDefault(w,field,def) ((w)->optional ? \ + (w)->optional->field \ + : def) + +#define wVisual(w) wTrackParent(w, visual) +#define wCursor(w) ((w)->cursorIsNone ? None : wTrackParent(w, cursor)) +#define wColormap(w) ((w)->drawable.class == InputOnly ? None : wTrackParent(w, colormap)) +#define wDontPropagateMask(w) wUseDefault(w, dontPropagateMask, DontPropagateMasks[(w)->dontPropagate]) +#define wOtherEventMasks(w) wUseDefault(w, otherEventMasks, 0) +#define wOtherClients(w) wUseDefault(w, otherClients, NULL) +#ifdef XINPUT +#define wOtherInputMasks(w) wUseDefault(w, inputMasks, NULL) +#else +#define wOtherInputMasks(w) NULL +#endif +#define wPassiveGrabs(w) wUseDefault(w, passiveGrabs, NULL) +#define wUserProps(w) wUseDefault(w, userProps, NULL) +#define wBackingBitPlanes(w) wUseDefault(w, backingBitPlanes, ~0L) +#define wBackingPixel(w) wUseDefault(w, backingPixel, 0) +#ifdef SHAPE +#define wBoundingShape(w) wUseDefault(w, boundingShape, NULL) +#define wClipShape(w) wUseDefault(w, clipShape, NULL) +#define wInputShape(w) wUseDefault(w, inputShape, NULL) +#endif +#define wClient(w) (clients[CLIENT_ID((w)->drawable.id)]) +#define wBorderWidth(w) ((int) (w)->borderWidth) + +/* true when w needs a border drawn. */ + +#ifdef SHAPE +#define HasBorder(w) ((w)->borderWidth || wClipShape(w)) +#else +#define HasBorder(w) ((w)->borderWidth) +#endif + +typedef struct _ScreenSaverStuff { + WindowPtr pWindow; + XID wid; + char blanked; + Bool (*ExternalScreenSaver)( + ScreenPtr /*pScreen*/, + int /*xstate*/, + Bool /*force*/); +} ScreenSaverStuffRec, *ScreenSaverStuffPtr; + +#define SCREEN_IS_BLANKED 0 +#define SCREEN_ISNT_SAVED 1 +#define SCREEN_IS_TILED 2 +#define SCREEN_IS_BLACK 3 + +#define HasSaverWindow(i) (savedScreenInfo[i].pWindow != NullWindow) + +extern int screenIsSaved; +extern ScreenSaverStuffRec savedScreenInfo[MAXSCREENS]; + +/* + * this is the configuration parameter "NO_BACK_SAVE" + * it means that any existant backing store should not + * be used to implement save unders. + */ + +#ifndef NO_BACK_SAVE +#define DO_SAVE_UNDERS(pWin) ((pWin)->drawable.pScreen->saveUnderSupport ==\ + USE_DIX_SAVE_UNDERS) +/* + * saveUnderSupport is set to this magic value when using DIXsaveUnders + */ + +#define USE_DIX_SAVE_UNDERS 0x40 +#endif + +extern int numSaveUndersViewable; +extern int deltaSaveUndersViewable; + +#ifdef XEVIE +extern WindowPtr xeviewin; +#endif + +#endif /* WINDOWSTRUCT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/wm3.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/wm3.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/wm3.h (revision 51223) @@ -0,0 +1,81 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/wm3.h,v 1.2 1998/07/25 16:59:46 dawes Exp $ */ + + + + + +/* $XConsortium: wm3.h /main/4 1996/02/21 17:59:24 kaleb $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "vgaReg.h" + +#ifdef PC98_EGC +#define VGA_ALLPLANES 0xFL +#endif + +/* Do call in Write Mode 3. + * We take care of the possibility that two passes are needed. + */ +#ifndef PC98_EGC +#define DO_WM3(pgc,call) \ + { int _tp, _fg, _bg, _alu; \ + _fg = pgc->fgPixel; _bg = pgc->bgPixel; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + if ( _tp ) { \ + _alu = pgc->alu; \ + pgc->alu = GXinvert; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + pgc->alu = _alu; \ + } \ + pgc->fgPixel = _fg; pgc->bgPixel = _bg; \ + } +#else +#define DO_WM3(pgc,call) \ + { int _tp, _fg, _bg; \ + _fg = pgc->fgPixel; _bg = pgc->bgPixel; \ + _tp = wm3_set_regs(pgc); \ + (call); \ + pgc->fgPixel = _fg; pgc->bgPixel = _bg; \ + } +#endif + +#ifndef PC98_EGC +#define WM3_SET_INK(ink) \ + SetVideoGraphics(Set_ResetIndex, ink) +#else +#define WM3_SET_INK(ink) \ + outw(EGC_FGC, ink) +#endif + +/* GJA -- Move a long word to screen memory. + * The reads into 'dummy' are here to load the VGA latches. + * This is a RMW operation except for trivial cases. + * Notice that we ignore the operation. + */ +#ifdef PC98_EGC +#define UPDRW(destp,src) \ + { volatile unsigned short *_dtmp = \ + (volatile unsigned short *)(destp); \ + unsigned int _stmp = (src); \ + *_dtmp = _stmp; _dtmp++; _stmp >>= 16; \ + *_dtmp = _stmp; } +#else +#define UPDRW(destp,src) \ + { volatile char *_dtmp = (volatile char *)(destp); \ + unsigned int _stmp = (src); \ + volatile int dummy; /* Bit bucket. */ \ + _stmp = ldl_u(&_stmp); \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; _dtmp++; _stmp >>= 8; \ + dummy = *_dtmp; *_dtmp = _stmp; } +#endif + +#define UPDRWB(destp,src) \ + { volatile int dummy; /* Bit bucket. */ \ + dummy = *(destp); *(destp) = (src); } Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hash.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hash.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hash.h (revision 51223) @@ -0,0 +1,62 @@ +/* x-hash.h -- basic hash table class + $Id$ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/x-hash.h,v 1.1 2003/04/30 23:15:42 torrey Exp $ */ + +#ifndef X_HASH_H +#define X_HASH_H 1 + +typedef struct x_hash_table_struct x_hash_table; + +typedef int (x_compare_fun) (const void *a, const void *b); +typedef unsigned int (x_hash_fun) (const void *k); +typedef void (x_destroy_fun) (void *x); +typedef void (x_hash_foreach_fun) (void *k, void *v, void *data); + +/* for X_PFX and X_EXTERN */ +#include "x-list.h" + +X_EXTERN x_hash_table *X_PFX (hash_table_new) (x_hash_fun *hash, + x_compare_fun *compare, + x_destroy_fun *key_destroy, + x_destroy_fun *value_destroy); +X_EXTERN void X_PFX (hash_table_free) (x_hash_table *h); + +X_EXTERN unsigned int X_PFX (hash_table_size) (x_hash_table *h); + +X_EXTERN void X_PFX (hash_table_insert) (x_hash_table *h, void *k, void *v); +X_EXTERN void X_PFX (hash_table_replace) (x_hash_table *h, void *k, void *v); +X_EXTERN void X_PFX (hash_table_remove) (x_hash_table *h, void *k); +X_EXTERN void *X_PFX (hash_table_lookup) (x_hash_table *h, + void *k, void **k_ret); +X_EXTERN void X_PFX (hash_table_foreach) (x_hash_table *h, + x_hash_foreach_fun *fun, + void *data); + +#endif /* X_HASH_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hook.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hook.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-hook.h (revision 51223) @@ -0,0 +1,44 @@ +/* x-hook.h -- lists of function,data pairs to call. + $Id$ + + Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: $ */ + +#ifndef X_HOOK_H +#define X_HOOK_H 1 + +#include "x-list.h" + +typedef void x_hook_function (void *arg, void *data); + +X_EXTERN x_list *X_PFX (hook_add) (x_list *lst, x_hook_function *fun, void *data); +X_EXTERN x_list *X_PFX (hook_remove) (x_list *lst, x_hook_function *fun, void *data); +X_EXTERN void X_PFX (hook_run) (x_list *lst, void *arg); +X_EXTERN void X_PFX (hook_free) (x_list *lst); + +#endif /* X_HOOK_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-list.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-list.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x-list.h (revision 51223) @@ -0,0 +1,79 @@ +/* x-list.h -- simple list type + $Id: x-list.h,v 1.10 2003/07/18 00:52:19 jharper Exp $ + + Copyright (c) 2002 Apple Computer, Inc. All rights reserved. + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation files + (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, + publish, distribute, sublicense, and/or sell copies of the Software, + and to permit persons to whom the Software is furnished to do so, + subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT + HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the above + copyright holders shall not be used in advertising or otherwise to + promote the sale, use or other dealings in this Software without + prior written authorization. */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/x-list.h,v 1.1 2003/04/30 23:15:42 torrey Exp $ */ + +#ifndef X_LIST_H +#define X_LIST_H 1 + +/* This is just a cons. */ + +typedef struct x_list_struct x_list; + +struct x_list_struct { + void *data; + x_list *next; +}; + +#ifndef X_PFX +# define X_PFX(x) x_ ## x +#endif + +#ifndef X_EXTERN +# define X_EXTERN __private_extern__ +#endif + +X_EXTERN void X_PFX (list_free_1) (x_list *node); +X_EXTERN x_list *X_PFX (list_prepend) (x_list *lst, void *data); + +X_EXTERN x_list *X_PFX (list_append) (x_list *lst, void *data); +X_EXTERN x_list *X_PFX (list_remove) (x_list *lst, void *data); +X_EXTERN void X_PFX (list_free) (x_list *lst); +X_EXTERN x_list *X_PFX (list_pop) (x_list *lst, void **data_ret); + +X_EXTERN x_list *X_PFX (list_copy) (x_list *lst); +X_EXTERN x_list *X_PFX (list_reverse) (x_list *lst); +X_EXTERN x_list *X_PFX (list_find) (x_list *lst, void *data); +X_EXTERN x_list *X_PFX (list_nth) (x_list *lst, int n); +X_EXTERN x_list *X_PFX (list_filter) (x_list *src, + int (*pred) (void *item, void *data), + void *data); +X_EXTERN x_list *X_PFX (list_map) (x_list *src, + void *(*fun) (void *item, void *data), + void *data); + +X_EXTERN unsigned int X_PFX (list_length) (x_list *lst); +X_EXTERN void X_PFX (list_foreach) (x_list *lst, void (*fun) + (void *data, void *user_data), + void *user_data); + +X_EXTERN x_list *X_PFX (list_sort) (x_list *lst, int (*less) (const void *, + const void *)); + +#endif /* X_LIST_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emu.h (revision 51223) @@ -0,0 +1,198 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK /* Don't pack structs with function pointers! */ +#endif + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef DEBUG +#define HALT_SYS() \ + printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ + X86EMU_halt_sys() +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_SAVE_IP_CS_F 0x000040 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_TRACECALL_REGS_F 0x004000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_EXIT 0x010000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emui.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emui.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/x86emui.h (revision 51223) @@ -0,0 +1,102 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" + +#ifndef NO_SYS_HEADERS +#include +#include +#include +#endif +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaa.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaa.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaa.h (revision 51223) @@ -0,0 +1,1402 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaa.h,v 1.38 2002/10/21 01:54:04 mvojkovi Exp $ */ + +#ifndef _XAA_H +#define _XAA_H + +/* + + ******** OPERATION SPECIFIC FLAGS ********* + + **** solid/dashed line flags **** + +--------- -------- +23 LINE_PATTERN_LSBFIRST_MSBJUSTIFIED +22 LINE_PATTERN_LSBFIRST_LSBJUSTIFIED +21 LINE_PATTERN_MSBFIRST_MSBJUSTIFIED +20 LINE_PATTERN_MSBFIRST_LSBJUSTIFIED +19 LINE_PATTERN_POWER_OF_2_ONLY +18 LINE_LIMIT_COORDS +17 . +16 . +--------- ------- + + **** screen to screen copy flags **** + +--------- -------- +23 ONLY_LEFT_TO_RIGHT_BITBLT +22 ONLY_TWO_BITBLT_DIRECTIONS +21 . +20 . +19 . +18 . +17 . +16 . +--------- ------- + + **** clipping flags **** + +--------- -------- +23 . +22 HARDWARE_CLIP_SCREEN_TO_SCREEN_COLOR_EXPAND +21 HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY +20 HARDWARE_CLIP_MONO_8x8_FILL +19 HARDWARE_CLIP_COLOR_8x8_FILL +18 HARDWARE_CLIP_SOLID_FILL +17 HARDWARE_CLIP_DASHED_LINE +16 HARDWARE_CLIP_SOLID_LINE +--------- ------- + + + **** hardware pattern flags **** + +--------- -------- +23 . +22 . +21 HARDWARE_PATTERN_SCREEN_ORIGIN +20 . +19 . +18 . +17 HARDWARE_PATTERN_PROGRAMMED_ORIGIN +16 HARDWARE_PATTERN_PROGRAMMED_BITS +--------- ------- + + **** write pixmap flags **** + +--------- -------- +23 . +22 . +21 . +20 . +19 . +18 . +17 . +16 CONVERT_32BPP_TO_24BPP +--------- ------- + + + ******** GENERIC FLAGS ********* + +--------- ------- +15 SYNC_AFTER_COLOR_EXPAND +14 CPU_TRANSFER_PAD_QWORD +13 . +12 LEFT_EDGE_CLIPPING_NEGATIVE_X +11 LEFT_EDGE_CLIPPING +10 CPU_TRANSFER_BASE_FIXED + 9 BIT_ORDER_IN_BYTE_MSBFIRST + 8 TRANSPARENCY_GXCOPY_ONLY +--------- ------- + 7 NO_TRANSPARENCY + 6 TRANSPARENCY_ONLY + 5 ROP_NEEDS_SOURCE + 4 TRIPLE_BITS_24BPP + 3 RGB_EQUAL + 2 NO_PLANEMASK + 1 NO_GXCOPY + 0 GXCOPY_ONLY +--------- ------- + + +*/ + +#include "gcstruct.h" +#include "pixmapstr.h" +#include "xf86str.h" +#include "regionstr.h" +#include "xf86fbman.h" + +#ifdef RENDER +#include "picturestr.h" +#endif + +/* Flags */ +#define PIXMAP_CACHE 0x00000001 +#define MICROSOFT_ZERO_LINE_BIAS 0x00000002 +#define OFFSCREEN_PIXMAPS 0x00000004 +#define LINEAR_FRAMEBUFFER 0x00000008 + + +/* GC fg, bg, and planemask restrictions */ +#define GXCOPY_ONLY 0x00000001 +#define NO_GXCOPY 0x00000002 +#define NO_PLANEMASK 0x00000004 +#define RGB_EQUAL 0x00000008 +#define TRIPLE_BITS_24BPP 0x00000010 +#define ROP_NEEDS_SOURCE 0x00000020 + +/* transparency restrictions */ +#define TRANSPARENCY_ONLY 0x00000040 +#define NO_TRANSPARENCY 0x00000080 +#define TRANSPARENCY_GXCOPY_ONLY 0x00000100 + +/* bit order restrictions */ +#define BIT_ORDER_IN_BYTE_MSBFIRST 0x00000200 +#define BIT_ORDER_IN_BYTE_LSBFIRST 0x00000000 + +/* transfer base restriction */ +#define CPU_TRANSFER_BASE_FIXED 0x00000400 + +/* skipleft restrictions */ +#define LEFT_EDGE_CLIPPING 0x00000800 +#define LEFT_EDGE_CLIPPING_NEGATIVE_X 0x00001000 + +/* data padding */ +#define CPU_TRANSFER_PAD_DWORD 0x00000000 +#define CPU_TRANSFER_PAD_QWORD 0x00004000 +#define SCANLINE_PAD_DWORD 0x00000000 + +#define SYNC_AFTER_COLOR_EXPAND 0x00008000 +#define SYNC_AFTER_IMAGE_WRITE SYNC_AFTER_COLOR_EXPAND + +/* hardware pattern */ +#define HARDWARE_PATTERN_PROGRAMMED_BITS 0x00010000 +#define HARDWARE_PATTERN_PROGRAMMED_ORIGIN 0x00020000 +#define HARDWARE_PATTERN_SCREEN_ORIGIN 0x00200000 + +/* copyarea flags */ +#define ONLY_TWO_BITBLT_DIRECTIONS 0x00400000 +#define ONLY_LEFT_TO_RIGHT_BITBLT 0x00800000 + +/* line flags */ +#define LINE_PATTERN_LSBFIRST_MSBJUSTIFIED 0x00800000 +#define LINE_PATTERN_LSBFIRST_LSBJUSTIFIED 0x00400000 +#define LINE_PATTERN_MSBFIRST_MSBJUSTIFIED 0x00200000 +#define LINE_PATTERN_MSBFIRST_LSBJUSTIFIED 0x00100000 +#define LINE_PATTERN_POWER_OF_2_ONLY 0x00080000 +#define LINE_LIMIT_COORDS 0x00040000 + +/* clipping flags */ +#define HARDWARE_CLIP_SCREEN_TO_SCREEN_COLOR_EXPAND 0x00400000 +#define HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY 0x00200000 +#define HARDWARE_CLIP_MONO_8x8_FILL 0x00100000 +#define HARDWARE_CLIP_COLOR_8x8_FILL 0x00080000 +#define HARDWARE_CLIP_SOLID_FILL 0x00040000 +#define HARDWARE_CLIP_DASHED_LINE 0x00020000 +#define HARDWARE_CLIP_SOLID_LINE 0x00010000 + +#define HARDWARE_CLIP_LINE 0x00000000 + + +/* image write flags */ +#define CONVERT_32BPP_TO_24BPP 0x00010000 + +/* pixmap cache flags */ +#define CACHE_MONO_8x8 0x00000001 +#define CACHE_COLOR_8x8 0x00000002 +#define DO_NOT_BLIT_STIPPLES 0x00000004 +#define DO_NOT_TILE_MONO_DATA 0x00000008 +#define DO_NOT_TILE_COLOR_DATA 0x00000010 + + +#define DEGREES_0 0 +#define DEGREES_90 1 +#define DEGREES_180 2 +#define DEGREES_270 3 + +#define OMIT_LAST 1 + +/* render flags */ + +#define XAA_RENDER_POWER_OF_2_TILE_ONLY 0x00000008 +#define XAA_RENDER_NO_SRC_ALPHA 0x00000004 +#define XAA_RENDER_IMPRECISE_ONLY 0x00000002 +#define XAA_RENDER_NO_TILE 0x00000001 + +#define XAA_RENDER_REPEAT 0x00000001 + +typedef void (* ValidateGCProcPtr)( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +typedef struct { + unsigned char *bits; + int width; + int height; + int yoff; + int srcwidth; + int start; + int end; +} NonTEGlyphInfo, *NonTEGlyphPtr; + + +typedef struct { + int x; + int y; + int w; + int h; + int orig_w; + int orig_h; + unsigned long serialNumber; + int pat0; + int pat1; + int fg; + int bg; + int trans_color; + DDXPointPtr offsets; + DevUnion devPrivate; +} XAACacheInfoRec, *XAACacheInfoPtr; + + +typedef struct _PixmapLink { + PixmapPtr pPix; + struct _PixmapLink *next; + FBAreaPtr area; +} PixmapLink, *PixmapLinkPtr; + +typedef struct _XAAInfoRec { + ScrnInfoPtr pScrn; + int Flags; + + void (*Sync)( + ScrnInfoPtr pScrn + ); + + /* Restore Accel State is a driver callback that is used + * when another screen on the same device has been active. + * This allows multihead on a single device to work. + * If The entityProp has IS_SHARED_ACCEL defined then this + * function is required. + */ + + void (*RestoreAccelState)( + ScrnInfoPtr pScrn + ); + + /***************** Low Level *****************/ + +/* Blits */ + void (*SetupForScreenToScreenCopy)( + ScrnInfoPtr pScrn, + int xdir, int ydir, + int rop, + unsigned int planemask, + int trans_color + ); + int ScreenToScreenCopyFlags; + + void (*SubsequentScreenToScreenCopy)( + ScrnInfoPtr pScrn, + int xsrc, int ysrc, + int xdst, int ydst, + int w, int h + ); + + +/* Solid fills */ + void (*SetupForSolidFill)( + ScrnInfoPtr pScrn, + int color, + int rop, + unsigned int planemask + ); + int SolidFillFlags; + + void (*SubsequentSolidFillRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h + ); + + void (*SubsequentSolidFillTrap)( + ScrnInfoPtr pScrn, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + + +/* Solid lines */ + + void (*SetupForSolidLine)( + ScrnInfoPtr pScrn, + int color, + int rop, + unsigned int planemask + ); + int SolidLineFlags; + + void (*SubsequentSolidTwoPointLine)( + ScrnInfoPtr pScrn, + int xa, int ya, int xb, int yb, int flags + ); + + void (*SubsequentSolidBresenhamLine)( + ScrnInfoPtr pScrn, + int x, int y, int absmaj, int absmin, int err, int len, int octant + ); + int SolidBresenhamLineErrorTermBits; + + void (*SubsequentSolidHorVertLine)( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir + ); + +/* Dashed lines */ + + void (*SetupForDashedLine)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask, + int length, + unsigned char *pattern + ); + int DashedLineFlags; + int DashPatternMaxLength; + + void (*SubsequentDashedTwoPointLine)( + ScrnInfoPtr pScrn, + int xa, int ya, int xb, int yb, int flags, int phase + ); + + void (*SubsequentDashedBresenhamLine)( + ScrnInfoPtr pScrn, + int x, int y, int absmaj, int absmin, int err, int len, int flags, + int phase + ); + int DashedBresenhamLineErrorTermBits; + +/* Clipper */ + + void (*SetClippingRectangle) ( + ScrnInfoPtr pScrn, + int left, int top, int right, int bottom + ); + int ClippingFlags; + + void (*DisableClipping)(ScrnInfoPtr pScrn); + +/* 8x8 mono pattern fills */ + void (*SetupForMono8x8PatternFill)( + ScrnInfoPtr pScrn, + int patx, int paty, + int fg, int bg, + int rop, + unsigned int planemask + ); + int Mono8x8PatternFillFlags; + + void (*SubsequentMono8x8PatternFillRect)( + ScrnInfoPtr pScrn, + int patx, int paty, + int x, int y, int w, int h + ); + + void (*SubsequentMono8x8PatternFillTrap)( + ScrnInfoPtr pScrn, + int patx, int paty, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + +/* 8x8 color pattern fills */ + + void (*SetupForColor8x8PatternFill)( + ScrnInfoPtr pScrn, + int patx, int paty, + int rop, + unsigned int planemask, + int transparency_color + ); + int Color8x8PatternFillFlags; + + void (*SubsequentColor8x8PatternFillRect)( + ScrnInfoPtr pScrn, + int patx, int paty, + int x, int y, int w, int h + ); + + void (*SubsequentColor8x8PatternFillTrap)( + ScrnInfoPtr pScrn, + int patx, int paty, + int y, int h, + int left, int dxL, int dyL, int eL, + int right, int dxR, int dyR, int eR + ); + + +/* Color expansion */ + + void (*SetupForCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int CPUToScreenColorExpandFillFlags; + + void (*SubsequentCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + unsigned char *ColorExpandBase; + int ColorExpandRange; + + +/* Scanline color expansion */ + + void (*SetupForScanlineCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int ScanlineCPUToScreenColorExpandFillFlags; + + void (*SubsequentScanlineCPUToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + void (*SubsequentColorExpandScanline)( + ScrnInfoPtr pScrn, + int bufno + ); + + int NumScanlineColorExpandBuffers; + unsigned char **ScanlineColorExpandBuffers; + +/* Screen to screen color expansion */ + + void (*SetupForScreenToScreenColorExpandFill) ( + ScrnInfoPtr pScrn, + int fg, int bg, + int rop, + unsigned int planemask + ); + int ScreenToScreenColorExpandFillFlags; + + void (*SubsequentScreenToScreenColorExpandFill)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int srcx, int srcy, int skipleft + ); + + +/* Image transfers */ + + void (*SetupForImageWrite)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int ImageWriteFlags; + + void (*SubsequentImageWriteRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + unsigned char *ImageWriteBase; + int ImageWriteRange; + +/* Scanline Image transfers */ + + void (*SetupForScanlineImageWrite)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int ScanlineImageWriteFlags; + + void (*SubsequentScanlineImageWriteRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + int skipleft + ); + + void (*SubsequentImageWriteScanline) ( + ScrnInfoPtr pScrn, + int bufno + ); + + int NumScanlineImageWriteBuffers; + unsigned char **ScanlineImageWriteBuffers; + + /* Image Reads - OBSOLETE AND NOT USED */ + + void (*SetupForImageRead) ( + ScrnInfoPtr pScrn, + int bpp, int depth + ); + int ImageReadFlags; + + unsigned char *ImageReadBase; + int ImageReadRange; + + void (*SubsequentImageReadRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h + ); + + + /***************** Mid Level *****************/ + void (*ScreenToScreenBitBlt)( + ScrnInfoPtr pScrn, + int nbox, + DDXPointPtr pptSrc, + BoxPtr pbox, + int xdir, int ydir, + int alu, + unsigned int planmask + ); + int ScreenToScreenBitBltFlags; + + void (*WriteBitmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask + ); + int WriteBitmapFlags; + + void (*FillSolidRects)( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox + ); + int FillSolidRectsFlags; + + void (*FillMono8x8PatternRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg + ); + int FillMono8x8PatternRectsFlags; + + void (*FillColor8x8PatternRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache + ); + int FillColor8x8PatternRectsFlags; + + void (*FillCacheBltRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache + ); + int FillCacheBltRectsFlags; + + void (*FillColorExpandRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillColorExpandRectsFlags; + + void (*FillCacheExpandRects)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillCacheExpandRectsFlags; + + void (*FillImageWriteRects)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillImageWriteRectsFlags; + + + void (*FillSolidSpans)( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted + ); + int FillSolidSpansFlags; + + void (*FillMono8x8PatternSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + int pat0, int pat1, + int xorg, int yorg + ); + int FillMono8x8PatternSpansFlags; + + void (*FillColor8x8PatternSpans)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg + ); + int FillColor8x8PatternSpansFlags; + + void (*FillCacheBltSpans)( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg + ); + int FillCacheBltSpansFlags; + + void (*FillColorExpandSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillColorExpandSpansFlags; + + void (*FillCacheExpandSpans)( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix + ); + int FillCacheExpandSpansFlags; + + void (*TEGlyphRenderer)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask + ); + int TEGlyphRendererFlags; + + void (*NonTEGlyphRenderer)( + ScrnInfoPtr pScrn, + int x, int y, int n, + NonTEGlyphPtr glyphs, + BoxPtr pbox, + int fg, int rop, + unsigned int planemask + ); + int NonTEGlyphRendererFlags; + + void (*WritePixmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth + ); + int WritePixmapFlags; + + void (*ReadPixmap) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *dst, + int dstwidth, + int bpp, int depth + ); + int ReadPixmapFlags; + + /***************** GC Level *****************/ + RegionPtr (*CopyArea)( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty + ); + int CopyAreaFlags; + + RegionPtr (*CopyPlane)( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, int srcy, + int width, int height, + int dstx, int dsty, + unsigned long bitPlane + ); + int CopyPlaneFlags; + + void (*PushPixelsSolid) ( + GCPtr pGC, + PixmapPtr pBitMap, + DrawablePtr pDrawable, + int dx, int dy, + int xOrg, int yOrg + ); + int PushPixelsFlags; + + /** PolyFillRect **/ + + void (*PolyFillRectSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectSolidFlags; + + void (*PolyFillRectStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectStippledFlags; + + void (*PolyFillRectOpaqueStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectOpaqueStippledFlags; + + void (*PolyFillRectTiled)( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit + ); + int PolyFillRectTiledFlags; + + /** FillSpans **/ + + void (*FillSpansSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansSolidFlags; + + void (*FillSpansStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansStippledFlags; + + void (*FillSpansOpaqueStippled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansOpaqueStippledFlags; + + void (*FillSpansTiled)( + DrawablePtr pDraw, + GCPtr pGC, + int nInit, + DDXPointPtr ppt, + int *pwidth, + int fSorted + ); + int FillSpansTiledFlags; + + int (*PolyText8TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int PolyText8TEFlags; + + int (*PolyText16TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int PolyText16TEFlags; + + void (*ImageText8TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int ImageText8TEFlags; + + void (*ImageText16TE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int ImageText16TEFlags; + + void (*ImageGlyphBltTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int ImageGlyphBltTEFlags; + + void (*PolyGlyphBltTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int PolyGlyphBltTEFlags; + + int (*PolyText8NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int PolyText8NonTEFlags; + + int (*PolyText16NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int PolyText16NonTEFlags; + + void (*ImageText8NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars + ); + int ImageText8NonTEFlags; + + void (*ImageText16NonTE) ( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars + ); + int ImageText16NonTEFlags; + + void (*ImageGlyphBltNonTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int ImageGlyphBltNonTEFlags; + + void (*PolyGlyphBltNonTE) ( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase + ); + int PolyGlyphBltNonTEFlags; + + void (*PolyRectangleThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int nRectsInit, + xRectangle *pRectsInit + ); + int PolyRectangleThinSolidFlags; + + void (*PolylinesWideSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesWideSolidFlags; + + void (*PolylinesThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesThinSolidFlags; + + void (*PolySegmentThinSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + ); + int PolySegmentThinSolidFlags; + + void (*PolylinesThinDashed)( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts + ); + int PolylinesThinDashedFlags; + + void (*PolySegmentThinDashed)( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg + ); + int PolySegmentThinDashedFlags; + + void (*FillPolygonSolid)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonSolidFlags; + + void (*FillPolygonStippled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonStippledFlags; + + void (*FillPolygonOpaqueStippled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonOpaqueStippledFlags; + + void (*FillPolygonTiled)( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn + ); + int FillPolygonTiledFlags; + + void (*PolyFillArcSolid)( + DrawablePtr pDraw, + GCPtr pGC, + int narcs, + xArc *parcs + ); + int PolyFillArcSolidFlags; + + void (*PutImage)( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage + ); + int PutImageFlags; + + /* Validation masks */ + + unsigned long FillSpansMask; + ValidateGCProcPtr ValidateFillSpans; + unsigned long SetSpansMask; + ValidateGCProcPtr ValidateSetSpans; + unsigned long PutImageMask; + ValidateGCProcPtr ValidatePutImage; + unsigned long CopyAreaMask; + ValidateGCProcPtr ValidateCopyArea; + unsigned long CopyPlaneMask; + ValidateGCProcPtr ValidateCopyPlane; + unsigned long PolyPointMask; + ValidateGCProcPtr ValidatePolyPoint; + unsigned long PolylinesMask; + ValidateGCProcPtr ValidatePolylines; + unsigned long PolySegmentMask; + ValidateGCProcPtr ValidatePolySegment; + unsigned long PolyRectangleMask; + ValidateGCProcPtr ValidatePolyRectangle; + unsigned long PolyArcMask; + ValidateGCProcPtr ValidatePolyArc; + unsigned long FillPolygonMask; + ValidateGCProcPtr ValidateFillPolygon; + unsigned long PolyFillRectMask; + ValidateGCProcPtr ValidatePolyFillRect; + unsigned long PolyFillArcMask; + ValidateGCProcPtr ValidatePolyFillArc; + unsigned long PolyText8Mask; + ValidateGCProcPtr ValidatePolyText8; + unsigned long PolyText16Mask; + ValidateGCProcPtr ValidatePolyText16; + unsigned long ImageText8Mask; + ValidateGCProcPtr ValidateImageText8; + unsigned long ImageText16Mask; + ValidateGCProcPtr ValidateImageText16; + unsigned long PolyGlyphBltMask; + ValidateGCProcPtr ValidatePolyGlyphBlt; + unsigned long ImageGlyphBltMask; + ValidateGCProcPtr ValidateImageGlyphBlt; + unsigned long PushPixelsMask; + ValidateGCProcPtr ValidatePushPixels; + + void (*ComputeDash)(GCPtr pGC); + + /* Pixmap Cache */ + + int PixmapCacheFlags; + Bool UsingPixmapCache; + Bool CanDoMono8x8; + Bool CanDoColor8x8; + + void (*InitPixmapCache)( + ScreenPtr pScreen, + RegionPtr areas, + pointer data + ); + void (*ClosePixmapCache)( + ScreenPtr pScreen + ); + + int (*StippledFillChooser)(GCPtr pGC); + int (*OpaqueStippledFillChooser)(GCPtr pGC); + int (*TiledFillChooser)(GCPtr pGC); + + int CachePixelGranularity; + int MaxCacheableTileWidth; + int MaxCacheableTileHeight; + int MaxCacheableStippleWidth; + int MaxCacheableStippleHeight; + + XAACacheInfoPtr (*CacheTile)( + ScrnInfoPtr Scrn, PixmapPtr pPix + ); + XAACacheInfoPtr (*CacheStipple)( + ScrnInfoPtr Scrn, PixmapPtr pPix, + int fg, int bg + ); + XAACacheInfoPtr (*CacheMonoStipple)( + ScrnInfoPtr Scrn, PixmapPtr pPix + ); + XAACacheInfoPtr (*CacheMono8x8Pattern)( + ScrnInfoPtr Scrn, int pat0, int pat1 + ); + XAACacheInfoPtr (*CacheColor8x8Pattern)( + ScrnInfoPtr Scrn, PixmapPtr pPix, + int fg, int bg + ); + + + int MonoPatternPitch; + int CacheWidthMono8x8Pattern; + int CacheHeightMono8x8Pattern; + + int ColorPatternPitch; + int CacheWidthColor8x8Pattern; + int CacheHeightColor8x8Pattern; + + int CacheColorExpandDensity; + + void (*WriteBitmapToCache) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg + ); + void (*WritePixmapToCache) ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth + ); + void (*WriteMono8x8PatternToCache)( + ScrnInfoPtr pScrn, + XAACacheInfoPtr pCache + ); + void (*WriteColor8x8PatternToCache)( + ScrnInfoPtr pScrn, + PixmapPtr pPix, + XAACacheInfoPtr pCache + ); + + char* PixmapCachePrivate; + + /* Miscellaneous */ + + GC ScratchGC; + int PreAllocSize; + unsigned char *PreAllocMem; + + CharInfoPtr CharInfo[255]; + NonTEGlyphInfo GlyphInfo[255]; + + unsigned int FullPlanemask; /* deprecated */ + + PixmapLinkPtr OffscreenPixmaps; + int maxOffPixWidth; + int maxOffPixHeight; + + XAACacheInfoRec ScratchCacheInfoRec; + + BoxPtr ClipBox; + + Bool NeedToSync; + + char *dgaSaves; + + /* These can be supplied to override the defaults */ + + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + BackingStoreSaveAreasProcPtr SaveAreas; + BackingStoreRestoreAreasProcPtr RestoreAreas; + + unsigned int offscreenDepths; + Bool offscreenDepthsInitialized; + + CARD32 FullPlanemasks[32]; + +#ifdef RENDER + Bool (*Composite) ( + CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height + ); + + Bool (*Glyphs) ( + CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs + ); + + /* The old SetupForCPUToScreenAlphaTexture function is no longer used because + * it doesn't pass in enough information to write a conforming + * implementation. See SetupForCPUToScreenAlphaTexture2. + */ + Bool (*SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags + ); + void (*SubsequentCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height + ); + int CPUToScreenAlphaTextureFlags; + CARD32 * CPUToScreenAlphaTextureFormats; + + /* The old SetupForCPUToScreenTexture function is no longer used because + * it doesn't pass in enough information to write a conforming + * implementation. See SetupForCPUToScreenTexture2. + */ + Bool (*SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texType, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags + ); + void (*SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height + ); + int CPUToScreenTextureFlags; + CARD32 * CPUToScreenTextureFormats; + + +#endif + + /* these were added for 4.3.0 */ + BoxRec SolidLineLimits; + BoxRec DashedLineLimits; + +#ifdef RENDER + /* These were added for X.Org 6.8.0 */ + Bool (*SetupForCPUToScreenAlphaTexture2) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + CARD32 maskFormat, + CARD32 dstFormat, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags + ); + CARD32 *CPUToScreenAlphaTextureDstFormats; + + Bool (*SetupForCPUToScreenTexture2) ( + ScrnInfoPtr pScrn, + int op, + CARD32 srcFormat, + CARD32 dstFormat, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags + ); + CARD32 *CPUToScreenTextureDstFormats; +#endif /* RENDER */ +} XAAInfoRec, *XAAInfoRecPtr; + +#define SET_SYNC_FLAG(infoRec) (infoRec)->NeedToSync = TRUE + + +Bool +XAAInit( + ScreenPtr pScreen, + XAAInfoRecPtr infoRec +); + +XAAInfoRecPtr XAACreateInfoRec(void); + +void +XAADestroyInfoRec( + XAAInfoRecPtr infoRec +); + +typedef void (*DepthChangeFuncPtr) (ScrnInfoPtr pScrn, int depth); + +Bool +XAAInitDualFramebufferOverlay( + ScreenPtr pScreen, + DepthChangeFuncPtr callback +); + +#endif /* _XAA_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaaWrapper.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaaWrapper.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaaWrapper.h (revision 51223) @@ -0,0 +1,10 @@ + +#ifndef _XAA_WRAPPER_H +# define _XAA_WRAPPER_H + +typedef void (*SyncFunc)(ScreenPtr); + +Bool xaaSetupWrapper(ScreenPtr pScreen, + XAAInfoRecPtr infoPtr, int depth, SyncFunc *func); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaacexp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaacexp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaacexp.h (revision 51223) @@ -0,0 +1,128 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaacexp.h,v 1.3 2000/01/21 02:30:06 dawes Exp $ */ + + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include + +#ifndef FIXEDBASE +#define CHECKRETURN(b) if(width <= ((b) * 32)) return(base + (b)) +#else +#define CHECKRETURN(b) if(width <= ((b) * 32)) return(base) +#endif + +#if X_BYTE_ORDER == X_BIG_ENDIAN +# define SHIFT_L(value, shift) ((value) >> (shift)) +# define SHIFT_R(value, shift) ((value) << (shift)) +#else +# define SHIFT_L(value, shift) ((value) << (shift)) +# define SHIFT_R(value, shift) ((value) >> (shift)) +#endif + +#ifndef MSBFIRST +# ifdef FIXEDBASE +# define WRITE_IN_BITORDER(dest, offset, data) *(dest) = data; +# else +# define WRITE_IN_BITORDER(dest, offset, data) *(dest + offset) = data; +# endif +#else +# ifdef FIXEDBASE +# define WRITE_IN_BITORDER(dest, offset, data) *(dest) = SWAP_BITS_IN_BYTES(data); +# else +# define WRITE_IN_BITORDER(dest, offset, data) *(dest + offset) = SWAP_BITS_IN_BYTES(data) +# endif +#endif + +#ifdef FIXEDBASE +# ifdef MSBFIRST +# define WRITE_BITS(b) *base = SWAP_BITS_IN_BYTES(b) +# define WRITE_BITS1(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; } +# define WRITE_BITS3(b) { \ + *base = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *base = byte_reversed_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_reversed_expand3[((b) & 0xFF000000) >> 24] << 8; } +# else +# define WRITE_BITS(b) *base = (b) +# define WRITE_BITS1(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; } +# define WRITE_BITS3(b) { \ + *base = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *base = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *base = byte_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_expand3[((b) & 0xFF000000) >> 24] << 8; } +# endif +#else +# ifdef MSBFIRST +# define WRITE_BITS(b) *(base++) = SWAP_BITS_IN_BYTES(b) +# define WRITE_BITS1(b) { \ + *(base++) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *(base) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + base += 2; } +# define WRITE_BITS3(b) { \ + *(base) = byte_reversed_expand3[(b) & 0xFF] | \ + byte_reversed_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_reversed_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_reversed_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *(base + 2) = byte_reversed_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_reversed_expand3[((b) & 0xFF000000) >> 24] << 8; \ + base += 3; } +# else +# define WRITE_BITS(b) *(base++) = (b) +# define WRITE_BITS1(b) { \ + *(base++) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; } +# define WRITE_BITS2(b) { \ + *(base) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + base += 2; } +# define WRITE_BITS3(b) { \ + *(base) = byte_expand3[(b) & 0xFF] | \ + byte_expand3[((b) & 0xFF00) >> 8] << 24; \ + *(base + 1) = byte_expand3[((b) & 0xFF00) >> 8] >> 8 | \ + byte_expand3[((b) & 0xFF0000) >> 16] << 16; \ + *(base + 2) = byte_expand3[((b) & 0xFF0000) >> 16] >> 16 | \ + byte_expand3[((b) & 0xFF000000) >> 24] << 8; \ + base += 3; } +# endif +#endif + +#ifdef FIXEDBASE +# ifdef MSBFIRST +# define EXPNAME(x) x##MSBFirstFixedBase +# else +# define EXPNAME(x) x##LSBFirstFixedBase +# endif +#else +# ifdef MSBFIRST +# define EXPNAME(x) x##MSBFirst +# else +# define EXPNAME(x) x##LSBFirst +# endif +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaalocal.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaalocal.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaalocal.h (revision 51223) @@ -0,0 +1,1773 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaalocal.h,v 1.36tsi Exp $ */ + +#ifndef _XAALOCAL_H +#define _XAALOCAL_H + +/* This file is very unorganized ! */ + + +#include "gcstruct.h" +#include "regionstr.h" +#include "xf86fbman.h" +#include "xaa.h" +#include "mi.h" +#ifdef RENDER +#include "picturestr.h" +#endif + +#define GCWhenForced (GCArcMode << 1) + +#define DO_COLOR_8x8 0x00000001 +#define DO_MONO_8x8 0x00000002 +#define DO_CACHE_BLT 0x00000003 +#define DO_COLOR_EXPAND 0x00000004 +#define DO_CACHE_EXPAND 0x00000005 +#define DO_IMAGE_WRITE 0x00000006 +#define DO_PIXMAP_COPY 0x00000007 +#define DO_SOLID 0x00000008 + + +typedef CARD32 * (*GlyphScanlineFuncPtr)( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +typedef CARD32 *(*StippleScanlineProcPtr)(CARD32*, CARD32*, int, int, int); + +typedef void (*RectFuncPtr) (ScrnInfoPtr, int, int, int, int, int, int, + XAACacheInfoPtr); +typedef void (*TrapFuncPtr) (ScrnInfoPtr, int, int, int, int, int, int, + int, int, int, int, int, int, + XAACacheInfoPtr); + + + +typedef struct _XAAScreen { + CreateGCProcPtr CreateGC; + CloseScreenProcPtr CloseScreen; + GetImageProcPtr GetImage; + GetSpansProcPtr GetSpans; + PaintWindowBackgroundProcPtr PaintWindowBackground; + PaintWindowBorderProcPtr PaintWindowBorder; + CopyWindowProcPtr CopyWindow; + WindowExposuresProcPtr WindowExposures; + BSFuncRec BackingStoreFuncs; + CreatePixmapProcPtr CreatePixmap; + DestroyPixmapProcPtr DestroyPixmap; + ChangeWindowAttributesProcPtr ChangeWindowAttributes; + XAAInfoRecPtr AccelInfoRec; + Bool (*EnterVT)(int, int); + void (*LeaveVT)(int, int); + int (*SetDGAMode)(int, int, DGADevicePtr); + void (*EnableDisableFBAccess)(int, Bool); +#ifdef RENDER + CompositeProcPtr Composite; + GlyphsProcPtr Glyphs; +#endif +} XAAScreenRec, *XAAScreenPtr; + +#define OPS_ARE_PIXMAP 0x00000001 +#define OPS_ARE_ACCEL 0x00000002 + +typedef struct _XAAGC { + GCOps *wrapOps; + GCFuncs *wrapFuncs; + GCOps *XAAOps; + int DashLength; + unsigned char* DashPattern; + unsigned long changes; + unsigned long flags; +} XAAGCRec, *XAAGCPtr; + +#define REDUCIBILITY_CHECKED 0x00000001 +#define REDUCIBLE_TO_8x8 0x00000002 +#define REDUCIBLE_TO_2_COLOR 0x00000004 +#define DIRTY 0x00010000 +#define OFFSCREEN 0x00020000 +#define DGA_PIXMAP 0x00040000 +#define SHARED_PIXMAP 0x00080000 +#define LOCKED_PIXMAP 0x00100000 + +#define REDUCIBILITY_MASK \ + (REDUCIBILITY_CHECKED | REDUCIBLE_TO_8x8 | REDUCIBLE_TO_2_COLOR) + +typedef struct _XAAPixmap { + unsigned long flags; + CARD32 pattern0; + CARD32 pattern1; + int fg; + int bg; + FBAreaPtr offscreenArea; + Bool freeData; +} XAAPixmapRec, *XAAPixmapPtr; + + +Bool +XAACreateGC( + GCPtr pGC +); + +Bool +XAAInitAccel( + ScreenPtr pScreen, + XAAInfoRecPtr infoRec +); + +RegionPtr +XAABitBlt( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + void (*doBitBlt)(DrawablePtr, DrawablePtr, GCPtr, RegionPtr, DDXPointPtr), + unsigned long bitPlane +); + +void +XAAScreenToScreenBitBlt( + ScrnInfoPtr pScrn, + int nbox, + DDXPointPtr pptSrc, + BoxPtr pbox, + int xdir, + int ydir, + int alu, + unsigned int planemask +); + +void +XAADoBitBlt( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAADoImageWrite( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAADoImageRead( + DrawablePtr pSrc, + DrawablePtr pDst, + GC *pGC, + RegionPtr prgnDst, + DDXPointPtr pptSrc +); + +void +XAACopyWindow( + WindowPtr pWin, + DDXPointRec ptOldOrg, + RegionPtr prgnSrc +); + + +RegionPtr +XAACopyArea( + DrawablePtr pSrcDrawable, + DrawablePtr pDstDrawable, + GC *pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty +); + +void +XAAValidateCopyArea( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePutImage( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateCopyPlane( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePushPixels( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateFillSpans( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePolyGlyphBlt( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidateImageGlyphBlt( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + +void +XAAValidatePolylines( + GCPtr pGC, + unsigned long changes, + DrawablePtr pDraw +); + + +RegionPtr +XAACopyPlaneColorExpansion( + DrawablePtr pSrc, + DrawablePtr pDst, + GCPtr pGC, + int srcx, + int srcy, + int width, + int height, + int dstx, + int dsty, + unsigned long bitPlane +); + + +void +XAAPushPixelsSolidColorExpansion( + GCPtr pGC, + PixmapPtr pBitMap, + DrawablePtr pDrawable, + int dx, + int dy, + int xOrg, + int yOrg +); + +void +XAAWriteBitmapColorExpandMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpandLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapColorExpand3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + + +void +XAAWriteBitmapScanlineColorExpandMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpandLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWriteBitmapScanlineColorExpand3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int skipleft, + int fg, int bg, + int rop, + unsigned int planemask +); + +void +XAAWritePixmap ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth +); + +void +XAAWritePixmapScanline ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int rop, + unsigned int planemask, + int transparency_color, + int bpp, int depth +); + +typedef void (*ClipAndRenderRectsFunc)(GCPtr, int, BoxPtr, int, int); + + +void +XAAClipAndRenderRects( + GCPtr pGC, + ClipAndRenderRectsFunc func, + int nrectFill, + xRectangle *prectInit, + int xorg, int yorg +); + + +typedef void (*ClipAndRenderSpansFunc)(GCPtr, int, DDXPointPtr, int*, + int, int, int); + +void +XAAClipAndRenderSpans( + GCPtr pGC, + DDXPointPtr ppt, + int *pwidth, + int nspans, + int fSorted, + ClipAndRenderSpansFunc func, + int xorg, + int yorg +); + + +void +XAAFillSolidRects( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox +); + +void +XAAFillMono8x8PatternRects( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg +); + +void +XAAFillMono8x8PatternRectsScreenOrigin( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int pat0, int pat1, + int xorg, int yorg +); + + +void +XAAFillColor8x8PatternRectsScreenOrigin( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorigin, int yorigin, + XAACacheInfoPtr pCache +); + +void +XAAFillColor8x8PatternRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorigin, int yorigin, + XAACacheInfoPtr pCache +); + +void +XAAFillCacheBltRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + XAACacheInfoPtr pCache +); + +void +XAAFillCacheExpandRects( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillImageWriteRects( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAPolyFillRect( + DrawablePtr pDraw, + GCPtr pGC, + int nrectFill, + xRectangle *prectInit +); + + +void +XAATEGlyphRendererMSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3MSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererLSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +void +XAATEGlyphRenderer3LSBFirstFixedBase ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRenderer3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +void +XAATEGlyphRendererScanlineMSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanline3MSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanlineLSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + +void +XAATEGlyphRendererScanline3LSBFirst ( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, int skipleft, int startline, + unsigned int **glyphs, int glyphWidth, + int fg, int bg, int rop, unsigned planemask +); + + +extern CARD32 *(*XAAGlyphScanlineFuncMSBFirstFixedBase[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncMSBFirst[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncLSBFirstFixedBase[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +extern CARD32 *(*XAAGlyphScanlineFuncLSBFirst[32])( + CARD32 *base, unsigned int **glyphp, int line, int nglyph, int width +); + +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncMSBFirstFixedBase(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncMSBFirst(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncLSBFirstFixedBase(void); +GlyphScanlineFuncPtr *XAAGetGlyphScanlineFuncLSBFirst(void); + +void +XAAFillColorExpandRectsLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsLSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3LSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRectsMSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandRects3MSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRectsLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRects3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRectsMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandRects3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int nBox, + BoxPtr pBox, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansLSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3LSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpansMSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillColorExpandSpans3MSBFirstFixedBase( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpansLSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpans3LSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAPutImage( + DrawablePtr pDraw, + GCPtr pGC, + int depth, + int x, + int y, + int w, + int h, + int leftPad, + int format, + char *pImage +); + +void +XAAFillScanlineColorExpandSpansMSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillScanlineColorExpandSpans3MSBFirst( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + + +extern CARD32 *(*XAAStippleScanlineFuncMSBFirstFixedBase[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncMSBFirst[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncLSBFirstFixedBase[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +extern CARD32 *(*XAAStippleScanlineFuncLSBFirst[6])( + CARD32* base, CARD32* src, int offset, int width, int dwords +); + +StippleScanlineProcPtr *XAAGetStippleScanlineFuncMSBFirstFixedBase(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncMSBFirst(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncLSBFirstFixedBase(void); +StippleScanlineProcPtr *XAAGetStippleScanlineFuncLSBFirst(void); + +int +XAAPolyText8TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +int +XAAPolyText16TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageText8TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +void +XAAImageText16TEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageGlyphBltTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +XAAPolyGlyphBltTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + + +int +XAAPolyText8NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +int +XAAPolyText16NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageText8NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + char *chars +); + +void +XAAImageText16NonTEColorExpansion( + DrawablePtr pDraw, + GCPtr pGC, + int x, int y, + int count, + unsigned short *chars +); + +void +XAAImageGlyphBltNonTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + +void +XAAPolyGlyphBltNonTEColorExpansion( + DrawablePtr pDrawable, + GCPtr pGC, + int xInit, int yInit, + unsigned int nglyph, + CharInfoPtr *ppci, + pointer pglyphBase +); + + +void XAANonTEGlyphRenderer( + ScrnInfoPtr pScrn, + int x, int y, int n, + NonTEGlyphPtr glyphs, + BoxPtr pbox, + int fg, int rop, + unsigned int planemask +); + +void +XAAFillSolidSpans( + ScrnInfoPtr pScrn, + int fg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted +); + +void +XAAFillMono8x8PatternSpans( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + int patx, int paty, + int xorg, int yorg +); + +void +XAAFillMono8x8PatternSpansScreenOrigin( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + int patx, int paty, + int xorg, int yorg +); + +void +XAAFillColor8x8PatternSpansScreenOrigin( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + XAACacheInfoPtr, + int xorigin, int yorigin +); + +void +XAAFillColor8x8PatternSpans( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, int fSorted, + XAACacheInfoPtr, + int xorigin, int yorigin +); + +void +XAAFillCacheBltSpans( + ScrnInfoPtr pScrn, + int rop, + unsigned int planemask, + int n, + DDXPointPtr points, + int *widths, + int fSorted, + XAACacheInfoPtr pCache, + int xorg, int yorg +); + +void +XAAFillCacheExpandSpans( + ScrnInfoPtr pScrn, + int fg, int bg, int rop, + unsigned int planemask, + int n, + DDXPointPtr ppt, + int *pwidth, + int fSorted, + int xorg, int yorg, + PixmapPtr pPix +); + +void +XAAFillSpans( + DrawablePtr pDrawable, + GC *pGC, + int nInit, + DDXPointPtr pptInit, + int *pwidth, + int fSorted +); + + +void +XAAInitPixmapCache( + ScreenPtr pScreen, + RegionPtr areas, + pointer data +); + +void +XAAWriteBitmapToCache( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg +); + +void +XAAWriteBitmapToCacheLinear( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int fg, int bg +); + +void +XAAWritePixmapToCache( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth +); + +void +XAAWritePixmapToCacheLinear( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned char *src, + int srcwidth, + int bpp, int depth +); + + +void +XAAPaintWindow( + WindowPtr pWin, + RegionPtr prgn, + int what +); + +void +XAASolidHorVertLineAsRects( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + +void +XAASolidHorVertLineAsTwoPoint( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + +void +XAASolidHorVertLineAsBresenham( + ScrnInfoPtr pScrn, + int x, int y, int len, int dir +); + + +void +XAAPolyRectangleThinSolid( + DrawablePtr pDrawable, + GCPtr pGC, + int nRectsInit, + xRectangle *pRectsInit +); + + +void +XAAPolylinesWideSolid ( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pPts +); + +void +XAAFillPolygonSolid( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + +void +XAAFillPolygonStippled( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + + +void +XAAFillPolygonTiled( + DrawablePtr pDrawable, + GCPtr pGC, + int shape, + int mode, + int count, + DDXPointPtr ptsIn +); + + +int +XAAIsEasyPolygon( + DDXPointPtr ptsIn, + int count, + BoxPtr extents, + int origin, + DDXPointPtr *topPoint, + int *topY, int *bottomY, + int shape +); + +void +XAAFillPolygonHelper( + ScrnInfoPtr pScrn, + DDXPointPtr ptsIn, + int count, + DDXPointPtr topPoint, + int y, + int maxy, + int origin, + RectFuncPtr RectFunc, + TrapFuncPtr TrapFunc, + int xorg, + int yorg, + XAACacheInfoPtr pCache +); + +void +XAAPolySegment( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg +); + +void +XAAPolyLines( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit +); + +void +XAAPolySegmentDashed( + DrawablePtr pDrawable, + GCPtr pGC, + int nseg, + xSegment *pSeg +); + +void +XAAPolyLinesDashed( + DrawablePtr pDrawable, + GCPtr pGC, + int mode, + int npt, + DDXPointPtr pptInit +); + + +void +XAAWriteMono8x8PatternToCache(ScrnInfoPtr pScrn, XAACacheInfoPtr pCache); + +void +XAAWriteColor8x8PatternToCache( + ScrnInfoPtr pScrn, + PixmapPtr pPix, + XAACacheInfoPtr pCache +); + +void +XAARotateMonoPattern( + int *pat0, int *pat1, + int xoffset, int yoffset, + Bool msbfirst +); + +void XAAComputeDash(GCPtr pGC); + +void XAAMoveDWORDS_FixedBase( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +void XAAMoveDWORDS_FixedSrc( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +void XAAMoveDWORDS( + register CARD32* dest, + register CARD32* src, + register int dwords +); + +int +XAAGetRectClipBoxes( + GCPtr pGC, + BoxPtr pboxClippedBase, + int nrectFill, + xRectangle *prectInit +); + +void +XAASetupOverlay8_32Planar(ScreenPtr); + +void +XAAPolyFillArcSolid(DrawablePtr pDraw, GCPtr pGC, int narcs, xArc *parcs); + +XAACacheInfoPtr +XAACacheTile(ScrnInfoPtr Scrn, PixmapPtr pPix); + +XAACacheInfoPtr +XAACacheMonoStipple(ScrnInfoPtr Scrn, PixmapPtr pPix); + +XAACacheInfoPtr +XAACachePlanarMonoStipple(ScrnInfoPtr Scrn, PixmapPtr pPix); + +typedef XAACacheInfoPtr (*XAACachePlanarMonoStippleProc)(ScrnInfoPtr, PixmapPtr); +XAACachePlanarMonoStippleProc XAAGetCachePlanarMonoStipple(void); + +XAACacheInfoPtr +XAACacheStipple(ScrnInfoPtr Scrn, PixmapPtr pPix, int fg, int bg); + +XAACacheInfoPtr +XAACacheMono8x8Pattern(ScrnInfoPtr Scrn, int pat0, int pat1); + +XAACacheInfoPtr +XAACacheColor8x8Pattern(ScrnInfoPtr Scrn, PixmapPtr pPix, int fg, int bg); + +void +XAATileCache(ScrnInfoPtr pScrn, XAACacheInfoPtr pCache, int w, int h); + +void XAAClosePixmapCache(ScreenPtr pScreen); +void XAAInvalidatePixmapCache(ScreenPtr pScreen); + +Bool XAACheckStippleReducibility(PixmapPtr pPixmap); +Bool XAACheckTileReducibility(PixmapPtr pPixmap, Bool checkMono); + +int XAAStippledFillChooser(GCPtr pGC); +int XAAOpaqueStippledFillChooser(GCPtr pGC); +int XAATiledFillChooser(GCPtr pGC); + +void XAAMoveInOffscreenPixmaps(ScreenPtr pScreen); +void XAAMoveOutOffscreenPixmaps(ScreenPtr pScreen); +void XAARemoveAreaCallback(FBAreaPtr area); +void XAAMoveOutOffscreenPixmap(PixmapPtr pPix); +Bool XAAInitStateWrap(ScreenPtr pScreen, XAAInfoRecPtr infoRec); + +#ifdef RENDER +void +XAAComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +Bool +XAADoComposite (CARD8 op, + PicturePtr pSrc, + PicturePtr pMask, + PicturePtr pDst, + INT16 xSrc, + INT16 ySrc, + INT16 xMask, + INT16 yMask, + INT16 xDst, + INT16 yDst, + CARD16 width, + CARD16 height); + + +void +XAAGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + +Bool +XAADoGlyphs (CARD8 op, + PicturePtr pSrc, + PicturePtr pDst, + PictFormatPtr maskFormat, + INT16 xSrc, + INT16 ySrc, + int nlist, + GlyphListPtr list, + GlyphPtr *glyphs); + + + +/* helpers */ +void +XAA_888_plus_PICT_a8_to_8888 ( + CARD32 color, + CARD8 *alphaPtr, /* in bytes */ + int alphaPitch, + CARD32 *dstPtr, + int dstPitch, /* in dwords */ + int width, + int height +); + +Bool +XAAGetRGBAFromPixel( + CARD32 pixel, + CARD16 *red, + CARD16 *green, + CARD16 *blue, + CARD16 *alpha, + CARD32 format +); + + +Bool +XAAGetPixelFromRGBA ( + CARD32 *pixel, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + CARD32 format +); + +#endif + +/* XXX should be static */ +extern GCOps XAAFallbackOps; +extern GCOps *XAAGetFallbackOps(void); +extern GCFuncs XAAGCFuncs; +extern int XAAScreenIndex; /* XXX DONTUSE */ +extern int XAAGCIndex; /* XXX DONTUSE */ +extern int XAAPixmapIndex; /* XXX DONTUSE */ +extern int XAAGetScreenIndex(void); +extern int XAAGetGCIndex(void); +extern int XAAGetPixmapIndex(void); + +extern unsigned int XAAShiftMasks[32]; + +extern unsigned int byte_expand3[256], byte_reversed_expand3[256]; + +CARD32 XAAReverseBitOrder(CARD32 data); + +#define GET_XAASCREENPTR_FROM_SCREEN(pScreen)\ + (pScreen)->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAASCREENPTR_FROM_GC(pGC)\ + (pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAASCREENPTR_FROM_DRAWABLE(pDraw)\ + (pDraw)->pScreen->devPrivates[XAAGetScreenIndex()].ptr + +#define GET_XAAINFORECPTR_FROM_SCREEN(pScreen)\ + ((XAAScreenPtr)((pScreen)->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_GC(pGC)\ +((XAAScreenPtr)((pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_DRAWABLE(pDraw)\ +((XAAScreenPtr)((pDraw)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define GET_XAAINFORECPTR_FROM_SCRNINFOPTR(pScrn)\ +((XAAScreenPtr)((pScrn)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec + +#define XAA_GET_PIXMAP_PRIVATE(pix)\ + (XAAPixmapPtr)((pix)->devPrivates[XAAGetPixmapIndex()].ptr) + +#define CHECK_RGB_EQUAL(c) (!((((c) >> 8) ^ (c)) & 0xffff)) + +#define CHECK_FG(pGC, flags) \ + (!(flags & RGB_EQUAL) || CHECK_RGB_EQUAL(pGC->fgPixel)) + +#define CHECK_BG(pGC, flags) \ + (!(flags & RGB_EQUAL) || CHECK_RGB_EQUAL(pGC->bgPixel)) + +#define CHECK_ROP(pGC, flags) \ + (!(flags & GXCOPY_ONLY) || (pGC->alu == GXcopy)) + +#define CHECK_ROPSRC(pGC, flags) \ + (!(flags & ROP_NEEDS_SOURCE) || ((pGC->alu != GXclear) && \ + (pGC->alu != GXnoop) && (pGC->alu != GXinvert) && \ + (pGC->alu != GXset))) + +#define CHECK_PLANEMASK(pGC, flags) \ + (!(flags & NO_PLANEMASK) || \ + ((pGC->planemask & infoRec->FullPlanemasks[pGC->depth - 1]) == \ + infoRec->FullPlanemasks[pGC->depth - 1])) + +#define CHECK_COLORS(pGC, flags) \ + (!(flags & RGB_EQUAL) || \ + (CHECK_RGB_EQUAL(pGC->fgPixel) && CHECK_RGB_EQUAL(pGC->bgPixel))) + +#define CHECK_NO_GXCOPY(pGC, flags) \ + ((pGC->alu != GXcopy) || !(flags & NO_GXCOPY) || \ + ((pGC->planemask & infoRec->FullPlanemask) != infoRec->FullPlanemask)) + +#define IS_OFFSCREEN_PIXMAP(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->offscreenArea) + +#define PIXMAP_IS_SHARED(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->flags & SHARED_PIXMAP) + +#define OFFSCREEN_PIXMAP_LOCKED(pPix)\ + ((XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pPix)))->flags & LOCKED_PIXMAP) + +#define XAA_DEPTH_BUG(pGC) \ + ((pGC->depth == 32) && (pGC->bgPixel == 0xffffffff)) + +#define DELIST_OFFSCREEN_PIXMAP(pPix) { \ + PixmapLinkPtr _pLink, _prev; \ + _pLink = infoRec->OffscreenPixmaps; \ + _prev = NULL; \ + while(_pLink) { \ + if(_pLink->pPix == pPix) { \ + if(_prev) _prev->next = _pLink->next; \ + else infoRec->OffscreenPixmaps = _pLink->next; \ + xfree(_pLink); \ + break; \ + } \ + _prev = _pLink; \ + _pLink = _pLink->next; \ + }} + + +#define SWAP_BITS_IN_BYTES(v) \ + (((0x01010101 & (v)) << 7) | ((0x02020202 & (v)) << 5) | \ + ((0x04040404 & (v)) << 3) | ((0x08080808 & (v)) << 1) | \ + ((0x10101010 & (v)) >> 1) | ((0x20202020 & (v)) >> 3) | \ + ((0x40404040 & (v)) >> 5) | ((0x80808080 & (v)) >> 7)) + +/* + * Moved XAAPixmapCachePrivate here from xaaPCache.c, since driver + * replacements for CacheMonoStipple need access to it + */ + +typedef struct { + int Num512x512; + int Current512; + XAACacheInfoPtr Info512; + int Num256x256; + int Current256; + XAACacheInfoPtr Info256; + int Num128x128; + int Current128; + XAACacheInfoPtr Info128; + int NumMono; + int CurrentMono; + XAACacheInfoPtr InfoMono; + int NumColor; + int CurrentColor; + XAACacheInfoPtr InfoColor; + int NumPartial; + int CurrentPartial; + XAACacheInfoPtr InfoPartial; + DDXPointRec MonoOffsets[64]; + DDXPointRec ColorOffsets[64]; +} XAAPixmapCachePrivate, *XAAPixmapCachePrivatePtr; + + +#endif /* _XAALOCAL_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaarop.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaarop.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaarop.h (revision 51223) @@ -0,0 +1,313 @@ +/* $XFree86$ */ + +/* + + int XAAHelpSolidROP(ScrnInfoPtr pScrn, int *fg, int pm, int *rop) + + For use with solid fills emulated by solid 8x8 patterns. You + give it the foreground, planemask and X rop and it will replace + the foreground with a new one and the rop with the appropriate + MS triadic raster op. The function will return which components + (S-P) need to be enabled. + + + int XAAHelpPatternROP(ScrnInfoPtr pScrn, int *fg, int *bg, int pm, int *rop) + + For use with 8x8 opaque pattern fills. You give it the foreground, + and background, planemask and X rop and it will replace the + foreground and background with new ones and the rop with the + appropriate MS triadic raster op. The function will return which + components (S-P) need to be enabled. + + + ROP_PAT - Means to enable 8x8 mono patterns (all bits + set for solid patterns). Set the foreground and + background as returned by the function. + + ROP_SRC - Means a source of color == planemask should be used. + + +*/ + +#ifndef _XAAROP_H +#define _XAAROP_H + +#define ROP_DST 0x00000001 +#define ROP_SRC 0x00000002 +#define ROP_PAT 0x00000004 + +#define ROP_0 0x00 +#define ROP_DPSoon 0x01 +#define ROP_DPSona 0x02 +#define ROP_PSon 0x03 +#define ROP_SDPona 0x04 +#define ROP_DPon 0x05 +#define ROP_PDSxnon 0x06 +#define ROP_PDSaon 0x07 +#define ROP_SDPnaa 0x08 +#define ROP_PDSxon 0x09 +#define ROP_DPna 0x0A +#define ROP_PSDnaon 0x0B +#define ROP_SPna 0x0C +#define ROP_PDSnaon 0x0D +#define ROP_PDSonon 0x0E +#define ROP_Pn 0x0F +#define ROP_PDSona 0x10 +#define ROP_DSon 0x11 +#define ROP_SDPxnon 0x12 +#define ROP_SDPaon 0x13 +#define ROP_DPSxnon 0x14 +#define ROP_DPSaon 0x15 +#define ROP_PSDPSanaxx 0x16 +#define ROP_SSPxDSxaxn 0x17 +#define ROP_SPxPDxa 0x18 +#define ROP_SDPSanaxn 0x19 +#define ROP_PDSPaox 0x1A +#define ROP_SDPSxaxn 0x1B +#define ROP_PSDPaox 0x1C +#define ROP_DSPDxaxn 0x1D +#define ROP_PDSox 0x1E +#define ROP_PDSoan 0x1F +#define ROP_DPSnaa 0x20 +#define ROP_SDPxon 0x21 +#define ROP_DSna 0x22 +#define ROP_SPDnaon 0x23 +#define ROP_SPxDSxa 0x24 +#define ROP_PDSPanaxn 0x25 +#define ROP_SDPSaox 0x26 +#define ROP_SDPSxnox 0x27 +#define ROP_DPSxa 0x28 +#define ROP_PSDPSaoxxn 0x29 +#define ROP_DPSana 0x2A +#define ROP_SSPxPDxaxn 0x2B +#define ROP_SPDSoax 0x2C +#define ROP_PSDnox 0x2D +#define ROP_PSDPxox 0x2E +#define ROP_PSDnoan 0x2F +#define ROP_PSna 0x30 +#define ROP_SDPnaon 0x31 +#define ROP_SDPSoox 0x32 +#define ROP_Sn 0x33 +#define ROP_SPDSaox 0x34 +#define ROP_SPDSxnox 0x35 +#define ROP_SDPox 0x36 +#define ROP_SDPoan 0x37 +#define ROP_PSDPoax 0x38 +#define ROP_SPDnox 0x39 +#define ROP_SPDSxox 0x3A +#define ROP_SPDnoan 0x3B +#define ROP_PSx 0x3C +#define ROP_SPDSonox 0x3D +#define ROP_SPDSnaox 0x3E +#define ROP_PSan 0x3F +#define ROP_PSDnaa 0x40 +#define ROP_DPSxon 0x41 +#define ROP_SDxPDxa 0x42 +#define ROP_SPDSanaxn 0x43 +#define ROP_SDna 0x44 +#define ROP_DPSnaon 0x45 +#define ROP_DSPDaox 0x46 +#define ROP_PSDPxaxn 0x47 +#define ROP_SDPxa 0x48 +#define ROP_PDSPDaoxxn 0x49 +#define ROP_DPSDoax 0x4A +#define ROP_PDSnox 0x4B +#define ROP_SDPana 0x4C +#define ROP_SSPxDSxoxn 0x4D +#define ROP_PDSPxox 0x4E +#define ROP_PDSnoan 0x4F +#define ROP_PDna 0x50 +#define ROP_DSPnaon 0x51 +#define ROP_DPSDaox 0x52 +#define ROP_SPDSxaxn 0x53 +#define ROP_DPSonon 0x54 +#define ROP_Dn 0x55 +#define ROP_DPSox 0x56 +#define ROP_DPSoan 0x57 +#define ROP_PDSPoax 0x58 +#define ROP_DPSnox 0x59 +#define ROP_DPx 0x5A +#define ROP_DPSDonox 0x5B +#define ROP_DPSDxox 0x5C +#define ROP_DPSnoan 0x5D +#define ROP_DPSDnaox 0x5E +#define ROP_DPan 0x5F +#define ROP_PDSxa 0x60 +#define ROP_DSPDSaoxxn 0x61 +#define ROP_DSPDoax 0x62 +#define ROP_SDPnox 0x63 +#define ROP_SDPSoax 0x64 +#define ROP_DSPnox 0x65 +#define ROP_DSx 0x66 +#define ROP_SDPSonox 0x67 +#define ROP_DSPDSonoxxn 0x68 +#define ROP_PDSxxn 0x69 +#define ROP_DPSax 0x6A +#define ROP_PSDPSoaxxn 0x6B +#define ROP_SDPax 0x6C +#define ROP_PDSPDoaxxn 0x6D +#define ROP_SDPSnoax 0x6E +#define ROP_PDSxnan 0x6F +#define ROP_PDSana 0x70 +#define ROP_SSDxPDxaxn 0x71 +#define ROP_SDPSxox 0x72 +#define ROP_SDPnoan 0x73 +#define ROP_DSPDxox 0x74 +#define ROP_DSPnoan 0x75 +#define ROP_SDPSnaox 0x76 +#define ROP_DSan 0x77 +#define ROP_PDSax 0x78 +#define ROP_DSPDSoaxxn 0x79 +#define ROP_DPSDnoax 0x7A +#define ROP_SDPxnan 0x7B +#define ROP_SPDSnoax 0x7C +#define ROP_DPSxnan 0x7D +#define ROP_SPxDSxo 0x7E +#define ROP_DPSaan 0x7F +#define ROP_DPSaa 0x80 +#define ROP_SPxDSxon 0x81 +#define ROP_DPSxna 0x82 +#define ROP_SPDSnoaxn 0x83 +#define ROP_SDPxna 0x84 +#define ROP_PDSPnoaxn 0x85 +#define ROP_DSPDSoaxx 0x86 +#define ROP_PDSaxn 0x87 +#define ROP_DSa 0x88 +#define ROP_SDPSnaoxn 0x89 +#define ROP_DSPnoa 0x8A +#define ROP_DSPDxoxn 0x8B +#define ROP_SDPnoa 0x8C +#define ROP_SDPSxoxn 0x8D +#define ROP_SSDxPDxax 0x8E +#define ROP_PDSanan 0x8F +#define ROP_PDSxna 0x90 +#define ROP_SDPSnoaxn 0x91 +#define ROP_DPSDPoaxx 0x92 +#define ROP_SPDaxn 0x93 +#define ROP_PSDPSoaxx 0x94 +#define ROP_DPSaxn 0x95 +#define ROP_DPSxx 0x96 +#define ROP_PSDPSonoxx 0x97 +#define ROP_SDPSonoxn 0x98 +#define ROP_DSxn 0x99 +#define ROP_DPSnax 0x9A +#define ROP_SDPSoaxn 0x9B +#define ROP_SPDnax 0x9C +#define ROP_DSPDoaxn 0x9D +#define ROP_DSPDSaoxx 0x9E +#define ROP_PDSxan 0x9F +#define ROP_DPa 0xA0 +#define ROP_PDSPnaoxn 0xA1 +#define ROP_DPSnoa 0xA2 +#define ROP_DPSDxoxn 0xA3 +#define ROP_PDSPonoxn 0xA4 +#define ROP_PDxn 0xA5 +#define ROP_DSPnax 0xA6 +#define ROP_PDSPoaxn 0xA7 +#define ROP_DPSoa 0xA8 +#define ROP_DPSoxn 0xA9 +#define ROP_D 0xAA +#define ROP_DPSono 0xAB +#define ROP_SPDSxax 0xAC +#define ROP_DPSDaoxn 0xAD +#define ROP_DSPnao 0xAE +#define ROP_DPno 0xAF +#define ROP_PDSnoa 0xB0 +#define ROP_PDSPxoxn 0xB1 +#define ROP_SSPxDSxox 0xB2 +#define ROP_SDPanan 0xB3 +#define ROP_PSDnax 0xB4 +#define ROP_DPSDoaxn 0xB5 +#define ROP_DPSDPaoxx 0xB6 +#define ROP_SDPxan 0xB7 +#define ROP_PSDPxax 0xB8 +#define ROP_DSPDaoxn 0xB9 +#define ROP_DPSnao 0xBA +#define ROP_DSno 0xBB +#define ROP_SPDSanax 0xBC +#define ROP_SDxPDxan 0xBD +#define ROP_DPSxo 0xBE +#define ROP_DPSano 0xBF +#define ROP_Psa 0xC0 +#define ROP_SPDSnaoxn 0xC1 +#define ROP_SPDSonoxn 0xC2 +#define ROP_PSxn 0xC3 +#define ROP_SPDnoa 0xC4 +#define ROP_SPDSxoxn 0xC5 +#define ROP_SDPnax 0xC6 +#define ROP_PSDPoaxn 0xC7 +#define ROP_SDPoa 0xC8 +#define ROP_SPDoxn 0xC9 +#define ROP_DPSDxax 0xCA +#define ROP_SPDSaoxn 0xCB +#define ROP_S 0xCC +#define ROP_SDPono 0xCD +#define ROP_SDPnao 0xCE +#define ROP_SPno 0xCF +#define ROP_PSDnoa 0xD0 +#define ROP_PSDPxoxn 0xD1 +#define ROP_PDSnax 0xD2 +#define ROP_SPDSoaxn 0xD3 +#define ROP_SSPxPDxax 0xD4 +#define ROP_DPSanan 0xD5 +#define ROP_PSDPSaoxx 0xD6 +#define ROP_DPSxan 0xD7 +#define ROP_PDSPxax 0xD8 +#define ROP_SDPSaoxn 0xD9 +#define ROP_DPSDanax 0xDA +#define ROP_SPxDSxan 0xDB +#define ROP_SPDnao 0xDC +#define ROP_SDno 0xDD +#define ROP_SDPxo 0xDE +#define ROP_SDPano 0xDF +#define ROP_PDSoa 0xE0 +#define ROP_PDSoxn 0xE1 +#define ROP_DSPDxax 0xE2 +#define ROP_PSDPaoxn 0xE3 +#define ROP_SDPSxax 0xE4 +#define ROP_PDSPaoxn 0xE5 +#define ROP_SDPSanax 0xE6 +#define ROP_SPxPDxan 0xE7 +#define ROP_SSPxDSxax 0xE8 +#define ROP_DSPDSanaxxn 0xE9 +#define ROP_DPSao 0xEA +#define ROP_DPSxno 0xEB +#define ROP_SDPao 0xEC +#define ROP_SDPxno 0xED +#define ROP_DSo 0xEE +#define ROP_SDPnoo 0xEF +#define ROP_P 0xF0 +#define ROP_PDSono 0xF1 +#define ROP_PDSnao 0xF2 +#define ROP_PSno 0xF3 +#define ROP_PSDnao 0xF4 +#define ROP_PDno 0xF5 +#define ROP_PDSxo 0xF6 +#define ROP_PDSano 0xF7 +#define ROP_PDSao 0xF8 +#define ROP_PDSxno 0xF9 +#define ROP_DPo 0xFA +#define ROP_DPSnoo 0xFB +#define ROP_PSo 0xFC +#define ROP_PSDnoo 0xFD +#define ROP_DPSoo 0xFE +#define ROP_1 0xFF + +#define NO_SRC_ROP(rop) \ + ((rop == GXnoop) || (rop == GXset) || (rop == GXclear) || (rop == GXinvert)) + +int XAAHelpSolidROP(ScrnInfoPtr pScrn, int *fg, int pm, int *rop); +int XAAHelpPatternROP(ScrnInfoPtr pScrn, int *fg, int *bg, int pm, int *rop); + +/* XXX These four should be static, but it breaks the 6.7.0 ABI. */ +extern int XAACopyROP[16]; +extern int XAACopyROP_PM[16]; +extern int XAAPatternROP[16]; +extern int XAAPatternROP_PM[16]; + +extern int XAAGetCopyROP(int i); +extern int XAAGetCopyROP_PM(int i); +extern int XAAGetPatternROP(int i); +extern int XAAGetPatternROP_PM(int i); + +#endif /* _XAAROP_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaawrap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaawrap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xaawrap.h (revision 51223) @@ -0,0 +1,82 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xaa/xaawrap.h,v 1.3 1998/10/25 07:12:14 dawes Exp $ */ + +#define XAA_SCREEN_PROLOGUE(pScreen, field)\ + ((pScreen)->field = \ + ((XAAScreenPtr) (pScreen)->devPrivates[XAAGetScreenIndex()].ptr)->field) + +#define XAA_SCREEN_EPILOGUE(pScreen, field, wrapper)\ + ((pScreen)->field = wrapper) + + +#define XAA_GC_FUNC_PROLOGUE(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr) (pGC)->devPrivates[XAAGetGCIndex()].ptr;\ + (pGC)->funcs = pGCPriv->wrapFuncs;\ + if(pGCPriv->flags)\ + (pGC)->ops = pGCPriv->wrapOps + +#define XAA_GC_FUNC_EPILOGUE(pGC)\ + pGCPriv->wrapFuncs = (pGC)->funcs;\ + (pGC)->funcs = &XAAGCFuncs;\ + if(pGCPriv->flags) {\ + pGCPriv->wrapOps = (pGC)->ops;\ + (pGC)->ops = (pGCPriv->flags & OPS_ARE_ACCEL) ? pGCPriv->XAAOps :\ + &XAAPixmapOps;\ + } + + +#define XAA_GC_OP_PROLOGUE(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + GCFuncs *oldFuncs = pGC->funcs;\ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + +#define XAA_GC_OP_PROLOGUE_WITH_RETURN(pGC)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + GCFuncs *oldFuncs = pGC->funcs;\ + if(!REGION_NUM_RECTS(pGC->pCompositeClip)) return; \ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + + +#define XAA_GC_OP_EPILOGUE(pGC)\ + pGCPriv->wrapOps = pGC->ops;\ + pGC->funcs = oldFuncs;\ + pGC->ops = pGCPriv->XAAOps + + +#define XAA_PIXMAP_OP_PROLOGUE(pGC, pDraw)\ + XAAGCPtr pGCPriv = (XAAGCPtr)(pGC->devPrivates[XAAGetGCIndex()].ptr);\ + XAAPixmapPtr pixPriv = XAA_GET_PIXMAP_PRIVATE((PixmapPtr)(pDraw));\ + GCFuncs *oldFuncs = pGC->funcs;\ + pGC->funcs = pGCPriv->wrapFuncs;\ + pGC->ops = pGCPriv->wrapOps + + +#define XAA_PIXMAP_OP_EPILOGUE(pGC)\ + pGCPriv->wrapOps = pGC->ops;\ + pGC->funcs = oldFuncs;\ + pGC->ops = &XAAPixmapOps;\ + pixPriv->flags |= DIRTY + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifdef RENDER +#define XAA_RENDER_PROLOGUE(pScreen,field)\ + (GetPictureScreen(pScreen)->field = \ + ((XAAScreenPtr) (pScreen)->devPrivates[XAAGetScreenIndex()].ptr)->field) + +#define XAA_RENDER_EPILOGUE(pScreen, field, wrapper)\ + (GetPictureScreen(pScreen)->field = wrapper) +#endif + +/* This also works fine for drawables */ + +#define SYNC_CHECK(pGC) {\ + XAAInfoRecPtr infoRec =\ +((XAAScreenPtr)((pGC)->pScreen->devPrivates[XAAGetScreenIndex()].ptr))->AccelInfoRec;\ + if(infoRec->NeedToSync) {\ + (*infoRec->Sync)(infoRec->pScrn);\ + infoRec->NeedToSync = FALSE;\ + }} Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf1bpp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf1bpp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf1bpp.h (revision 51223) @@ -0,0 +1,37 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf1bpp/xf1bpp.h,v 1.2 1998/07/25 16:59:25 dawes Exp $ */ +/* + * Copyright (C) 1994-1998 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifndef __XF1BPP_H__ +#define __XF1BPP_H__ + +#define MFB_PROTOTYPES_ONLY +#include "mfbmap.h" +#include "mfb.h" +#include "mfbunmap.h" +#undef MFB_PROTOTYPES_ONLY + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf4bpp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf4bpp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf4bpp.h (revision 51223) @@ -0,0 +1,653 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/xf4bpp.h,v 1.9 2003/11/03 05:11:57 tsi Exp $ */ + +#ifndef __XF4BPP_H__ +#define __XF4BPP_H__ + + +#include "windowstr.h" +#include "gcstruct.h" +#include "colormapst.h" +#include +#ifndef PixelType +#define PixelType CARD32 +#endif + +/* ppcArea.c */ +void xf4bppFillArea( + WindowPtr, + int, + BoxPtr, + GCPtr +); + +/* ppcBStore.c */ +void xf4bppSaveAreas( + PixmapPtr, + RegionPtr, + int, + int, + WindowPtr +); +void xf4bppRestoreAreas( + PixmapPtr, + RegionPtr, + int, + int, + WindowPtr +); + +/* ppcClip.c */ +void xf4bppDestroyClip( + GCPtr +); +void xf4bppChangeClip( + GCPtr, + int, + pointer, + int +); +void xf4bppCopyClip( + GCPtr, + GCPtr +); + +/* ppcCpArea.c */ +RegionPtr xf4bppCopyArea( + DrawablePtr, + DrawablePtr, + GCPtr, + int, + int, + int, + int, + int, + int +); + +/* ppcDepth.c */ +Bool xf4bppDepthOK( + DrawablePtr, + int +); + +/* ppcFillRct.c */ +void xf4bppPolyFillRect( + DrawablePtr, + GCPtr, + int, + xRectangle * +); + +/* ppcWindowFS.c */ +void xf4bppSolidWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppStippleWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppOpStippleWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppTileWindowFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); + +/* xf4bppPixmapFS.c */ +void xf4bppSolidPixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppStipplePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppOpStipplePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); +void xf4bppTilePixmapFS( + DrawablePtr, + GCPtr, + int, + DDXPointPtr, + int *, + int +); + +/* ppcGC.c */ +Bool xf4bppCreateGC( + GCPtr +); +void xf4bppDestroyGC( + GC * +); +void xf4bppValidateGC( + GCPtr, + unsigned long, + DrawablePtr +); + +/* ppcGetSp.c */ +void xf4bppGetSpans( + DrawablePtr, + int, + DDXPointPtr, + int *, + int, + char * +); + +/* ppcImg.c */ +void xf4bppGetImage( + DrawablePtr, + int, + int, + int, + int, + unsigned int, + unsigned long, + char * +); + +/* ppcLine.c */ +void xf4bppScrnZeroLine( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppScrnZeroDash( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppScrnZeroSegs( + DrawablePtr, + GCPtr, + int, + xSegment * +); + +/* ppcPixmap.c */ +PixmapPtr xf4bppCreatePixmap( + ScreenPtr, + int, + int, + int +); +PixmapPtr xf4bppCopyPixmap( + PixmapPtr +); + +/* ppcPntWin.c */ +void xf4bppPaintWindow( + WindowPtr, + RegionPtr, + int +); + +/* ppcPolyPnt.c */ +void xf4bppPolyPoint( + DrawablePtr, + GCPtr, + int, + int, + xPoint * +); + +/* ppcPolyRec.c */ +void xf4bppPolyRectangle( + DrawablePtr, + GCPtr, + int, + xRectangle * +); + +/* ppcQuery.c */ +void xf4bppQueryBestSize( + int, + unsigned short *, + unsigned short *, + ScreenPtr +); + +/* ppcRslvC.c */ +void xf4bppResolveColor( + unsigned short *, + unsigned short *, + unsigned short *, + VisualPtr +); +Bool xf4bppInitializeColormap( + ColormapPtr +); + +/* ppcSetSp.c */ +void xf4bppSetSpans( + DrawablePtr, + GCPtr, + char *, + DDXPointPtr, + int *, + int, + int +); + +/* ppcWindow.c */ +void xf4bppCopyWindow( + WindowPtr, + DDXPointRec, + RegionPtr +); +Bool xf4bppPositionWindow( + WindowPtr, + int, + int +); +Bool xf4bppUnrealizeWindow( + WindowPtr, + int, + int +); +Bool xf4bppDestroyWindow( + WindowPtr +); +Bool xf4bppCreateWindowForXYhardware( + WindowPtr +); + +/* emulOpStip.c */ +void xf4bppOpaqueStipple( + WindowPtr, + PixmapPtr, + unsigned long int, + unsigned long int, + int, + unsigned long int, + int, + int, + int, + int, + int, + int +); + +/* emulRepAre.c */ +void xf4bppReplicateArea( + WindowPtr, + int, + int, + int, + int, + int, + int, + int +); + +/* emulTile.c */ +void xf4bppTileRect( + WindowPtr, + PixmapPtr, + const int, + const unsigned long int, + int, + int, + int, + int, + int, + int +); + +/* vgaGC.c */ +Mask xf4bppChangeWindowGC( + GCPtr, + Mask +); + +/* vgaBitBlt.c */ +void xf4bppBitBlt( + WindowPtr, + int, + int, + int, + int, + int, + int, + int, + int +); + +/* vgaImages.c */ +void xf4bppDrawColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int, + const int, + const unsigned long int +); +void xf4bppReadColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int +); + +/* vgaLine.c */ +void xf4bppHorzLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int +); +void xf4bppVertLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int +); +void xf4bppBresLine( + WindowPtr, + unsigned long int, + int, + unsigned long int, + int, + int, + int, + int, + int, + int, + int, + int, + unsigned long int +); + +/* vgaStipple.c */ +void xf4bppFillStipple( + WindowPtr, + const PixmapPtr, + unsigned long int, + const int, + unsigned long int, + int, + int, + int, + int, + const int, + const int +); + +/* vgaSolid.c */ +void xf4bppFillSolid( + WindowPtr, + unsigned long int, + const int, + unsigned long int, + int, + const int, + int, + const int +); + +/* offscreen.c */ +void xf4bppOffBitBlt( + WindowPtr, + const int, + const int, + int, + int, + int, + int, + int, + int +); +void xf4bppOffDrawColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int, + const int, + const unsigned long int +); +void xf4bppOffReadColorImage( + WindowPtr, + int, + int, + int, + int, + unsigned char *, + int +); +void xf4bppOffFillSolid( + WindowPtr, + unsigned long int, + const int, + unsigned long int, + int, + const int, + int, + const int +); +void xf4bppOffDrawMonoImage( + WindowPtr, + unsigned char *, + int, + int, + int, + int, + unsigned long int, + int, + unsigned long int +); +void xf4bppOffFillStipple( + WindowPtr, + const PixmapPtr, + unsigned long int, + const int, + unsigned long int, + int, + int, + int, + int, + const int, + const int +); + +/* mfbimggblt.c */ +void xf4bppImageGlyphBlt( + DrawablePtr, + GCPtr, + int, + int, + unsigned int, + CharInfoPtr *, + pointer +); + +/* wm3.c */ +int wm3_set_regs( + GC * +); + +/* ppcIO.c */ +void xf4bppNeverCalled( + void +); +Bool xf4bppScreenInit( + ScreenPtr, + pointer, + int, + int, + int, + int, + int +); + +/* mfbfillarc.c */ +void xf4bppPolyFillArc( + DrawablePtr, + GCPtr, + int, + xArc * +); + +/* mfbzerarc.c */ +void xf4bppZeroPolyArc( + DrawablePtr, + GCPtr, + int, + xArc * +); + +/* mfbline.c */ +void xf4bppSegmentSS ( + DrawablePtr, + GCPtr, + int, + xSegment * +); +void xf4bppLineSS ( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); +void xf4bppSegmentSD ( + DrawablePtr, + GCPtr, + int, + xSegment * +); +void xf4bppLineSD ( + DrawablePtr, + GCPtr, + int, + int, + DDXPointPtr +); + +/* mfbbres.c */ +void xf4bppBresS( + PixelType *, + int, + int, + int, + int, + int, + int, + int, + int, + int, + int +); + +/* mfbbresd.c */ +void xf4bppBresD( + DrawablePtr, + int, int, + int *, + unsigned char *, + int, + int *, + int, + PixelType *, + int, int, int, int, int, int, + int, int, + int, int +); + +/* mfbhrzvert.c */ +void xf4bppHorzS( + PixelType *, + int, + int, + int, + int +); +void xf4bppVertS( + PixelType *, + int, + int, + int, + int +); + +#ifdef PC98_EGC + +/* egc_asm.s */ +unsigned char getbits_x( + int, + unsigned int, + pointer, + unsigned int +); +void wcopyr( + pointer, + pointer, + int, + pointer +); +void wcopyl( + pointer, + pointer, + int, + pointer +); +unsigned long int read8Z( + pointer +); + +#endif /* PC98_EGC */ + +#endif /* __XF4BPP_H__ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86.h (revision 51223) @@ -0,0 +1,442 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86.h,v 3.173 2004/01/27 01:31:44 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains declarations for public XFree86 functions and variables, + * and definitions of public macros. + * + * "public" means available to video drivers. + */ + +#ifndef _XF86_H +#define _XF86_H + +#include "xf86str.h" +#include "xf86Opt.h" +#include +#include +#ifdef RANDR +#include +#endif + +#include "propertyst.h" + +/* General parameters */ +extern int xf86DoConfigure; +extern Bool xf86DoConfigurePass1; +extern int xf86ScreenIndex; /* Index into pScreen.devPrivates */ +extern int xf86CreateRootWindowIndex; /* Index into pScreen.devPrivates */ +extern int xf86PixmapIndex; +extern Bool xf86ResAccessEnter; +extern ScrnInfoPtr *xf86Screens; /* List of pointers to ScrnInfoRecs */ +extern const unsigned char byte_reversed[256]; +extern ScrnInfoPtr xf86CurrentScreen; +extern Bool pciSlotClaimed; +extern Bool isaSlotClaimed; +extern Bool fbSlotClaimed; +#ifdef __sparc__ +extern Bool sbusSlotClaimed; +#endif +extern confDRIRec xf86ConfigDRI; +extern Bool xf86inSuspend; + +#define XF86SCRNINFO(p) ((ScrnInfoPtr)((p)->devPrivates[xf86ScreenIndex].ptr)) + +#define XF86FLIP_PIXELS() \ + do { \ + if (xf86GetFlipPixels()) { \ + pScreen->whitePixel = (pScreen->whitePixel) ? 0 : 1; \ + pScreen->blackPixel = (pScreen->blackPixel) ? 0 : 1; \ + } \ + while (0) + +#define BOOLTOSTRING(b) ((b) ? "TRUE" : "FALSE") + +#define PIX24TOBPP(p) (((p) == Pix24Use24) ? 24 : \ + (((p) == Pix24Use32) ? 32 : 0)) + +/* variables for debugging */ +#ifdef BUILDDEBUG +extern char* xf86p8bit[]; +extern CARD32 xf86DummyVar1; +extern CARD32 xf86DummyVar2; +extern CARD32 xf86DummyVar3; +#endif + +/* Function Prototypes */ +#ifndef _NO_XF86_PROTOTYPES + +/* xf86Bus.c */ + +Bool xf86CheckPciSlot(int bus, int device, int func); +int xf86ClaimPciSlot(int bus, int device, int func, DriverPtr drvp, + int chipset, GDevPtr dev, Bool active); +Bool xf86ParsePciBusString(const char *busID, int *bus, int *device, + int *func); +Bool xf86ComparePciBusString(const char *busID, int bus, int device, int func); +void xf86FormatPciBusNumber(int busnum, char *buffer); +pciVideoPtr *xf86GetPciVideoInfo(void); +pciConfigPtr *xf86GetPciConfigInfo(void); +void xf86SetPciVideo(pciVideoPtr, resType); +void xf86PrintResList(int verb, resPtr list); +resPtr xf86AddRangesToList(resPtr list, resRange *pRange, int entityIndex); +int xf86ClaimIsaSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +int xf86GetIsaInfoForScreen(int scrnIndex); +int xf86GetFbInfoForScreen(int scrnIndex); +Bool xf86ParseIsaBusString(const char *busID); +int xf86ClaimFbSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +int xf86ClaimNoSlot(DriverPtr drvp, int chipset, GDevPtr dev, Bool active); +void xf86EnableAccess(ScrnInfoPtr pScrn); +void xf86SetCurrentAccess(Bool Enable, ScrnInfoPtr pScrn); +Bool xf86IsPrimaryPci(pciVideoPtr pPci); +Bool xf86IsPrimaryIsa(void); +/* new RAC */ +resPtr xf86AddResToList(resPtr rlist, resRange *Range, int entityIndex); +resPtr xf86JoinResLists(resPtr rlist1, resPtr rlist2); +resPtr xf86DupResList(const resPtr rlist); +void xf86FreeResList(resPtr rlist); +void xf86ClaimFixedResources(resList list, int entityIndex); +Bool xf86DriverHasEntities(DriverPtr drvp); +void xf86AddEntityToScreen(ScrnInfoPtr pScrn, int entityIndex); +void xf86SetEntityInstanceForScreen(ScrnInfoPtr pScrn, int entityIndex, + int instance); +int xf86GetNumEntityInstances(int entityIndex); +GDevPtr xf86GetDevFromEntity(int entityIndex, int instance); +void xf86RemoveEntityFromScreen(ScrnInfoPtr pScrn, int entityIndex); +EntityInfoPtr xf86GetEntityInfo(int entityIndex); +pciVideoPtr xf86GetPciInfoForEntity(int entityIndex); +int xf86GetPciEntity(int bus, int dev, int func); +Bool xf86SetEntityFuncs(int entityIndex, EntityProc init, + EntityProc enter, EntityProc leave, pointer); +void xf86DeallocateResourcesForEntity(int entityIndex, unsigned long type); +resPtr xf86RegisterResources(int entityIndex, resList list, + unsigned long Access); +Bool xf86CheckPciMemBase(pciVideoPtr pPci, memType base); +void xf86SetAccessFuncs(EntityInfoPtr pEnt, xf86SetAccessFuncPtr funcs, + xf86SetAccessFuncPtr oldFuncs); +Bool xf86IsEntityPrimary(int entityIndex); +Bool xf86FixPciResource(int entityIndex, int prt, memType alignment, + unsigned long type); +resPtr xf86ReallocatePciResources(int entityIndex, resPtr pRes); +resPtr xf86SetOperatingState(resList list, int entityIndex, int mask); +void xf86EnterServerState(xf86State state); +resRange xf86GetBlock(unsigned long type, memType size, + memType window_start, memType window_end, + memType align_mask, resPtr avoid); +resRange xf86GetSparse(unsigned long type, memType fixed_bits, + memType decode_mask, memType address_mask, + resPtr avoid); +memType xf86ChkConflict(resRange *rgp, int entityIndex); +Bool xf86IsPciDevPresent(int bus, int dev, int func); +ScrnInfoPtr xf86FindScreenForEntity(int entityIndex); +Bool xf86NoSharedResources(int screenIndex, resType res); +resPtr xf86FindIntersectOfLists(resPtr l1, resPtr l2); +pciVideoPtr xf86FindPciDeviceVendor(CARD16 vendorID, CARD16 deviceID, + char n, pciVideoPtr pvp_exclude); +pciVideoPtr xf86FindPciClass(CARD8 intf, CARD8 subClass, CARD16 class, + char n, pciVideoPtr pvp_exclude); +#ifdef INCLUDE_DEPRECATED +void xf86EnablePciBusMaster(pciVideoPtr pPci, Bool enable); +#endif +void xf86RegisterStateChangeNotificationCallback(xf86StateChangeNotificationCallbackFunc func, pointer arg); +Bool xf86DeregisterStateChangeNotificationCallback(xf86StateChangeNotificationCallbackFunc func); +#ifdef async +Bool xf86QueueAsyncEvent(void (*func)(pointer),pointer arg); +#endif + +int xf86GetLastScrnFlag(int entityIndex); +void xf86SetLastScrnFlag(int entityIndex, int scrnIndex); +Bool xf86IsEntityShared(int entityIndex); +void xf86SetEntityShared(int entityIndex); +Bool xf86IsEntitySharable(int entityIndex); +void xf86SetEntitySharable(int entityIndex); +Bool xf86IsPrimInitDone(int entityIndex); +void xf86SetPrimInitDone(int entityIndex); +void xf86ClearPrimInitDone(int entityIndex); +int xf86AllocateEntityPrivateIndex(void); +DevUnion *xf86GetEntityPrivate(int entityIndex, int privIndex); + +/* xf86Configure.c */ +GDevPtr xf86AddBusDeviceToConfigure(const char *driver, BusType bus, + void *busData, int chipset); +GDevPtr xf86AddDeviceToConfigure(const char *driver, pciVideoPtr pVideo, + int chipset); + +/* xf86Cursor.c */ + +void xf86LockZoom(ScreenPtr pScreen, int lock); +void xf86InitViewport(ScrnInfoPtr pScr); +void xf86SetViewport(ScreenPtr pScreen, int x, int y); +void xf86ZoomViewport(ScreenPtr pScreen, int zoom); +Bool xf86SwitchMode(ScreenPtr pScreen, DisplayModePtr mode); +void *xf86GetPointerScreenFuncs(void); +void xf86InitOrigins(void); +void xf86ReconfigureLayout(void); + +/* xf86DPMS.c */ + +Bool xf86DPMSInit(ScreenPtr pScreen, DPMSSetProcPtr set, int flags); + +/* xf86DGA.c */ + +Bool DGAInit(ScreenPtr pScreen, DGAFunctionPtr funcs, DGAModePtr modes, + int num); +Bool DGAReInitModes(ScreenPtr pScreen, DGAModePtr modes, int num); +xf86SetDGAModeProc xf86SetDGAMode; + +/* xf86Events.c */ + +void SetTimeSinceLastInputEvent(void); +pointer xf86AddInputHandler(int fd, InputHandlerProc proc, pointer data); +int xf86RemoveInputHandler(pointer handler); +void xf86DisableInputHandler(pointer handler); +void xf86EnableInputHandler(pointer handler); +void xf86InterceptSignals(int *signo); +void xf86InterceptSigIll(void (*sigillhandler)(void)); +Bool xf86EnableVTSwitch(Bool new); +Bool xf86CommonSpecialKey(int key, Bool down, int modifiers); +void xf86ProcessActionEvent(ActionEvent action, void *arg); + +/* xf86Helper.c */ + +void xf86AddDriver(DriverPtr driver, pointer module, int flags); +void xf86DeleteDriver(int drvIndex); +ScrnInfoPtr xf86AllocateScreen(DriverPtr drv, int flags); +void xf86DeleteScreen(int scrnIndex, int flags); +int xf86AllocateScrnInfoPrivateIndex(void); +Bool xf86AddPixFormat(ScrnInfoPtr pScrn, int depth, int bpp, int pad); +Bool xf86SetDepthBpp(ScrnInfoPtr scrp, int depth, int bpp, int fbbpp, + int depth24flags); +void xf86PrintDepthBpp(ScrnInfoPtr scrp); +Bool xf86SetWeight(ScrnInfoPtr scrp, rgb weight, rgb mask); +Bool xf86SetDefaultVisual(ScrnInfoPtr scrp, int visual); +Bool xf86SetGamma(ScrnInfoPtr scrp, Gamma newGamma); +void xf86SetDpi(ScrnInfoPtr pScrn, int x, int y); +void xf86SetBlackWhitePixels(ScreenPtr pScreen); +void xf86EnableDisableFBAccess(int scrnIndex, Bool enable); +void xf86VDrvMsgVerb(int scrnIndex, MessageType type, int verb, + const char *format, va_list args); +void xf86DrvMsgVerb(int scrnIndex, MessageType type, int verb, + const char *format, ...) _printf_attribute(4,5); +void xf86DrvMsg(int scrnIndex, MessageType type, const char *format, ...) + _printf_attribute(3,4); +void xf86MsgVerb(MessageType type, int verb, const char *format, ...) + _printf_attribute(3,4); +void xf86Msg(MessageType type, const char *format, ...) _printf_attribute(2,3); +void xf86ErrorFVerb(int verb, const char *format, ...) _printf_attribute(2,3); +void xf86ErrorF(const char *format, ...) _printf_attribute(1,2); +const char *xf86TokenToString(SymTabPtr table, int token); +int xf86StringToToken(SymTabPtr table, const char *string); +void xf86ShowClocks(ScrnInfoPtr scrp, MessageType from); +void xf86PrintChipsets(const char *drvname, const char *drvmsg, + SymTabPtr chips); +int xf86MatchDevice(const char *drivername, GDevPtr **driversectlist); +int xf86MatchPciInstances(const char *driverName, int vendorID, + SymTabPtr chipsets, PciChipsets *PCIchipsets, + GDevPtr *devList, int numDevs, DriverPtr drvp, + int **foundEntities); +int xf86MatchIsaInstances(const char *driverName, SymTabPtr chipsets, + IsaChipsets *ISAchipsets, DriverPtr drvp, + FindIsaDevProc FindIsaDevice, GDevPtr *devList, + int numDevs, int **foundEntities); +void xf86GetClocks(ScrnInfoPtr pScrn, int num, + Bool (*ClockFunc)(ScrnInfoPtr, int), + void (*ProtectRegs)(ScrnInfoPtr, Bool), + void (*BlankScreen)(ScrnInfoPtr, Bool), + IOADDRESS vertsyncreg, int maskval, + int knownclkindex, int knownclkvalue); +void xf86SetPriority(Bool up); +const char *xf86GetVisualName(int visual); +int xf86GetVerbosity(void); +Pix24Flags xf86GetPix24(void); +int xf86GetDepth(void); +rgb xf86GetWeight(void); +Gamma xf86GetGamma(void); +Bool xf86GetFlipPixels(void); +const char *xf86GetServerName(void); +Bool xf86ServerIsExiting(void); +Bool xf86ServerIsResetting(void); +Bool xf86ServerIsInitialising(void); +Bool xf86ServerIsOnlyDetecting(void); +Bool xf86ServerIsOnlyProbing(void); +Bool xf86CaughtSignal(void); +Bool xf86GetVidModeAllowNonLocal(void); +Bool xf86GetVidModeEnabled(void); +Bool xf86GetModInDevAllowNonLocal(void); +Bool xf86GetModInDevEnabled(void); +Bool xf86GetAllowMouseOpenFail(void); +Bool xf86IsPc98(void); +void xf86DisableRandR(void); +CARD32 xf86GetVersion(void); +CARD32 xorgGetVersion(void); +CARD32 xf86GetModuleVersion(pointer module); +pointer xf86LoadDrvSubModule(DriverPtr drv, const char *name); +pointer xf86LoadSubModule(ScrnInfoPtr pScrn, const char *name); +pointer xf86LoadOneModule(char *name, pointer optlist); +void xf86UnloadSubModule(pointer mod); +Bool xf86LoaderCheckSymbol(const char *name); +void xf86LoaderReqSymLists(const char **, ...); +void xf86LoaderReqSymbols(const char *, ...); +void xf86LoaderRefSymLists(const char **, ...); +void xf86LoaderRefSymbols(const char *, ...); +void xf86SetBackingStore(ScreenPtr pScreen); +void xf86SetSilkenMouse(ScreenPtr pScreen); +int xf86NewSerialNumber(WindowPtr p, pointer unused); +pointer xf86FindXvOptions(int scrnIndex, int adapt_index, char *port_name, + char **adaptor_name, pointer *adaptor_options); +void xf86GetOS(const char **name, int *major, int *minor, int *teeny); +ScrnInfoPtr xf86ConfigPciEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex,PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +ScrnInfoPtr xf86ConfigIsaEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +ScrnInfoPtr xf86ConfigFbEntity(ScrnInfoPtr pScrn, int scrnFlag, + int entityIndex, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +/* Obsolete! don't use */ +Bool xf86ConfigActivePciEntity(ScrnInfoPtr pScrn, + int entityIndex,PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +/* Obsolete! don't use */ +Bool xf86ConfigActiveIsaEntity(ScrnInfoPtr pScrn, + int entityIndex, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigPciEntityInactive(EntityInfoPtr pEnt, PciChipsets *p_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigIsaEntityInactive(EntityInfoPtr pEnt, IsaChipsets *i_chip, + resList res, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +void xf86ConfigFbEntityInactive(EntityInfoPtr pEnt, EntityProc init, + EntityProc enter, EntityProc leave, + pointer private); +Bool xf86IsScreenPrimary(int scrnIndex); +int xf86RegisterRootWindowProperty(int ScrnIndex, Atom property, Atom type, + int format, unsigned long len, + pointer value); +Bool xf86IsUnblank(int mode); + +#ifdef XFree86LOADER +void xf86AddModuleInfo(ModuleInfoPtr info, pointer module); +void xf86DeleteModuleInfo(int idx); +#endif + +/* xf86Debug.c */ +#ifdef BUILDDEBUG + void xf86Break1(void); +void xf86Break2(void); +void xf86Break3(void); +CARD8 xf86PeekFb8(CARD8 *p); +CARD16 xf86PeekFb16(CARD16 *p); +CARD32 xf86PeekFb32(CARD32 *p); +void xf86PokeFb8(CARD8 *p, CARD8 v); +void xf86PokeFb16(CARD16 *p, CARD16 v); +void xf86PokeFb32(CARD16 *p, CARD32 v); +CARD8 xf86PeekMmio8(pointer Base, unsigned long Offset); +CARD16 xf86PeekMmio16(pointer Base, unsigned long Offset); +CARD32 xf86PeekMmio32(pointer Base, unsigned long Offset); +void xf86PokeMmio8(pointer Base, unsigned long Offset, CARD8 v); +void xf86PokeMmio16(pointer Base, unsigned long Offset, CARD16 v); +void xf86PokeMmio32(pointer Base, unsigned long Offset, CARD32 v); +extern void xf86SPTimestamp(xf86TsPtr* timestamp, char* string); +extern void xf86STimestamp(xf86TsPtr* timestamp); +#endif + +/* xf86Init.c */ + +PixmapFormatPtr xf86GetPixFormat(ScrnInfoPtr pScrn, int depth); +int xf86GetBppFromDepth(ScrnInfoPtr pScrn, int depth); + +/* xf86Mode.c */ + +int xf86GetNearestClock(ScrnInfoPtr scrp, int freq, Bool allowDiv2, + int DivFactor, int MulFactor, int *divider); +const char *xf86ModeStatusToString(ModeStatus status); +ModeStatus xf86LookupMode(ScrnInfoPtr scrp, DisplayModePtr modep, + ClockRangePtr clockRanges, LookupModeFlags strategy); +ModeStatus xf86CheckModeForMonitor(DisplayModePtr mode, MonPtr monitor); +ModeStatus xf86InitialCheckModeForDriver(ScrnInfoPtr scrp, DisplayModePtr mode, + ClockRangePtr clockRanges, + LookupModeFlags strategy, + int maxPitch, int virtualX, + int virtualY); +ModeStatus xf86CheckModeForDriver(ScrnInfoPtr scrp, DisplayModePtr mode, + int flags); +int xf86ValidateModes(ScrnInfoPtr scrp, DisplayModePtr availModes, + char **modeNames, ClockRangePtr clockRanges, + int *linePitches, int minPitch, int maxPitch, + int minHeight, int maxHeight, int pitchInc, + int virtualX, int virtualY, int apertureSize, + LookupModeFlags strategy); +void xf86DeleteMode(DisplayModePtr *modeList, DisplayModePtr mode); +void xf86PruneDriverModes(ScrnInfoPtr scrp); +void xf86SetCrtcForModes(ScrnInfoPtr scrp, int adjustFlags); +void xf86PrintModes(ScrnInfoPtr scrp); +void xf86ShowClockRanges(ScrnInfoPtr scrp, ClockRangePtr clockRanges); + +/* xf86Option.c */ + +void xf86CollectOptions(ScrnInfoPtr pScrn, pointer extraOpts); + + +/* xf86RandR.c */ +#ifdef RANDR +Bool xf86RandRInit (ScreenPtr pScreen); +void xf86RandRSetInitialMode (ScreenPtr pScreen); +Rotation xf86GetRotation(ScreenPtr pScreen); +Bool xf86RandRSetNewVirtualAndDimensions(ScreenPtr pScreen, + int newvirtX, int newvirtY, + int newmmWidth, int newmmHeight, Bool resetMode); +#endif + +/* xf86VidModeExtentionInit.c */ + +Bool VidModeExtensionInit(ScreenPtr pScreen); + +/* xf86Versions.c */ +CARD32 xf86GetBuiltinInterfaceVersion(BuiltinInterface iface, int flag); +Bool xf86RegisterBuiltinInterfaceVersion(BuiltinInterface iface, + CARD32 version, int flags); + + +#endif /* _NO_XF86_PROTOTYPES */ + +#endif /* _XF86_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Axp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Axp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Axp.h (revision 51223) @@ -0,0 +1,36 @@ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_AXP_H_ +#define _XF86_AXP_H_ + +typedef enum { + SYS_NONE, + TSUNAMI, + LCA, + APECS, + T2, + T2_GAMMA, + CIA, + MCPCIA, + JENSEN, + POLARIS, + PYXIS, + PYXIS_CIA, + IRONGATE +} axpDevice; + +typedef struct { + axpDevice id; + unsigned long hae_thresh; + unsigned long hae_mask; + unsigned long size; +} axpParams; + +extern axpParams xf86AXPParams[]; + +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Build.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Build.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Build.h (revision 51223) @@ -0,0 +1,1 @@ +#define BUILD_DATE 20060522 Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Bus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Bus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Bus.h (revision 51223) @@ -0,0 +1,162 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Bus.h,v 1.23 2003/08/24 17:36:50 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the bus-related data structures/types. + * Everything contained here is private to xf86Bus.c. In particular the + * video drivers must not include this file. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_BUS_H +#define _XF86_BUS_H + +#include "xf86pciBus.h" +#ifdef __sparc__ +#include "xf86sbusBus.h" +#endif + +typedef struct racInfo { + xf86AccessPtr mem_new; + xf86AccessPtr io_new; + xf86AccessPtr io_mem_new; + xf86SetAccessFuncPtr old; +} AccessFuncRec, *AccessFuncPtr; + + +typedef struct { + DriverPtr driver; + int chipset; + int entityProp; + EntityProc entityInit; + EntityProc entityEnter; + EntityProc entityLeave; + pointer private; + resPtr resources; + Bool active; + Bool inUse; + BusRec bus; + EntityAccessPtr access; + AccessFuncPtr rac; + pointer busAcc; + int lastScrnFlag; + DevUnion * entityPrivates; + int numInstances; + GDevPtr * devices; + IOADDRESS domainIO; +} EntityRec, *EntityPtr; + +/* asynchronous event handling */ +#ifdef async +typedef struct _AsyncQRec { + void (*func)(pointer); + pointer arg; + struct _AsyncQRec *next; +} AsyncQRec, *AsyncQPtr; +#endif + +#define NO_SEPARATE_IO_FROM_MEM 0x0001 +#define NO_SEPARATE_MEM_FROM_IO 0x0002 +#define NEED_VGA_ROUTED 0x0004 +#define NEED_VGA_ROUTED_SETUP 0x0008 +#define NEED_MEM 0x0010 +#define NEED_IO 0x0020 +#define NEED_MEM_SHARED 0x0040 +#define NEED_IO_SHARED 0x0080 +#define ACCEL_IS_SHARABLE 0x0100 +#define IS_SHARED_ACCEL 0x0200 +#define SA_PRIM_INIT_DONE 0x0400 +#define NEED_VGA_MEM 0x1000 +#define NEED_VGA_IO 0x2000 + +#define NEED_SHARED (NEED_MEM_SHARED | NEED_IO_SHARED) + +#define busType bus.type +#define pciBusId bus.id.pci +#define isaBusId bus.id.isa +#define sbusBusId bus.id.sbus + +struct x_BusAccRec; +typedef void (*BusAccProcPtr)(struct x_BusAccRec *ptr); + +typedef struct x_BusAccRec { + BusAccProcPtr set_f; + BusAccProcPtr enable_f; + BusAccProcPtr disable_f; + BusAccProcPtr save_f; + BusAccProcPtr restore_f; + struct x_BusAccRec *current; /* pointer to bridge open on this bus */ + struct x_BusAccRec *primary; /* pointer to the bus connecting to this */ + struct x_BusAccRec *next; /* this links the different buses together */ + BusType type; + BusType busdep_type; + /* Bus-specific fields */ + union { + struct { + int bus; + int primary_bus; + PCITAG acc; + pciBridgesSave save; + } pci; + } busdep; +} BusAccRec, *BusAccPtr; + +/* state change notification callback */ +typedef struct _stateChange { + xf86StateChangeNotificationCallbackFunc func; + pointer arg; + struct _stateChange *next; +} StateChangeNotificationRec, *StateChangeNotificationPtr; + + +extern EntityPtr *xf86Entities; +extern int xf86NumEntities; +extern xf86AccessRec AccessNULL; +extern BusRec primaryBus; +extern resPtr Acc; +extern resPtr osRes; +extern resPtr ResRange; +extern BusAccPtr xf86BusAccInfo; + +int xf86AllocateEntity(void); +BusType StringToBusType(const char* busID, const char **retID); +memType ChkConflict(resRange *rgp, resPtr res, xf86State state); +Bool xf86IsSubsetOf(resRange range, resPtr list); +Bool xf86IsListSubsetOf(resPtr list, resPtr BaseList); +resPtr xf86ExtractTypeFromList(resPtr list, unsigned long type); +resPtr findIntersect(resRange Range, resPtr list); +resPtr xf86FindIntersect(resRange Range, resPtr list); +void RemoveOverlaps(resPtr target, resPtr list, Bool pow2Alignment, + Bool useEstimated); +void xf86ConvertListToHost(int entityIndex, resPtr list); + +#endif /* _XF86_BUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Config.h (revision 51223) @@ -0,0 +1,63 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Config.h,v 1.7 2003/10/08 14:58:27 dawes Exp $ */ + +/* + * Copyright (c) 1997-2000 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86_config_h +#define _xf86_config_h + +#ifdef HAVE_PARSER_DECLS +/* + * global structure that holds the result of parsing the config file + */ +extern XF86ConfigPtr xf86configptr; +#endif + +typedef enum _ConfigStatus { + CONFIG_OK = 0, + CONFIG_PARSE_ERROR, + CONFIG_NOFILE +} ConfigStatus; + +/* + * prototypes + */ +char ** xf86ModulelistFromConfig(pointer **); +char ** xf86DriverlistFromConfig(void); +char ** xf86DriverlistFromCompile(void); +char ** xf86InputDriverlistFromConfig(void); +char ** xf86InputDriverlistFromCompile(void); +Bool xf86BuiltinInputDriver(const char *); +ConfigStatus xf86HandleConfigFile(Bool); + +Bool xf86AutoConfig(void); + +#endif /* _xf86_config_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Cursor.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Cursor.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Cursor.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86Cursor.h,v 1.10tsi Exp $ */ + +#ifndef _XF86CURSOR_H +#define _XF86CURSOR_H + +#include "xf86str.h" +#include "mipointer.h" + +typedef struct _xf86CursorInfoRec { + ScrnInfoPtr pScrn; + int Flags; + int MaxWidth; + int MaxHeight; + void (*SetCursorColors)(ScrnInfoPtr pScrn, int bg, int fg); + void (*SetCursorPosition)(ScrnInfoPtr pScrn, int x, int y); + void (*LoadCursorImage)(ScrnInfoPtr pScrn, unsigned char *bits); + void (*HideCursor)(ScrnInfoPtr pScrn); + void (*ShowCursor)(ScrnInfoPtr pScrn); + unsigned char* (*RealizeCursor)(struct _xf86CursorInfoRec *, CursorPtr); + Bool (*UseHWCursor)(ScreenPtr, CursorPtr); + +#ifdef ARGB_CURSOR + Bool (*UseHWCursorARGB) (ScreenPtr, CursorPtr); + void (*LoadCursorARGB) (ScrnInfoPtr, CursorPtr); +#endif + +} xf86CursorInfoRec, *xf86CursorInfoPtr; + +Bool xf86InitCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr); +xf86CursorInfoPtr xf86CreateCursorInfoRec(void); +void xf86DestroyCursorInfoRec(xf86CursorInfoPtr); +void xf86ForceHWCursor (ScreenPtr pScreen, Bool on); + +#define HARDWARE_CURSOR_INVERT_MASK 0x00000001 +#define HARDWARE_CURSOR_AND_SOURCE_WITH_MASK 0x00000002 +#define HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK 0x00000004 +#define HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED 0x00000008 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 0x00000010 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_8 0x00000020 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_16 0x00000040 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_32 0x00000080 +#define HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_64 0x00000100 +#define HARDWARE_CURSOR_TRUECOLOR_AT_8BPP 0x00000200 +#define HARDWARE_CURSOR_BIT_ORDER_MSBFIRST 0x00000400 +#define HARDWARE_CURSOR_NIBBLE_SWAPPED 0x00000800 +#define HARDWARE_CURSOR_SHOW_TRANSPARENT 0x00001000 +#define HARDWARE_CURSOR_UPDATE_UNHIDDEN 0x00002000 + +#endif /* _XF86CURSOR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86CursorPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86CursorPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86CursorPriv.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86CursorPriv.h,v 1.4tsi Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86CURSORPRIV_H +#define _XF86CURSORPRIV_H + +#include "xf86Cursor.h" +#include "mipointrst.h" + +typedef struct { + Bool SWCursor; + Bool isUp; + Bool showTransparent; + short HotX; + short HotY; + short x; + short y; + CursorPtr CurrentCursor, CursorToRestore; + xf86CursorInfoPtr CursorInfoPtr; + CloseScreenProcPtr CloseScreen; + RecolorCursorProcPtr RecolorCursor; + InstallColormapProcPtr InstallColormap; + QueryBestSizeProcPtr QueryBestSize; + miPointerSpriteFuncPtr spriteFuncs; + Bool PalettedCursor; + ColormapPtr pInstalledMap; + Bool (*SwitchMode)(int, DisplayModePtr,int); + xf86EnableDisableFBAccessProc *EnableDisableFBAccess; + CursorPtr SavedCursor; + + /* Number of requests to force HW cursor */ + int ForceHWCursorCount; + Bool HWCursorForced; + + pointer transparentData; +} xf86CursorScreenRec, *xf86CursorScreenPtr; + +void xf86SetCursor(ScreenPtr pScreen, CursorPtr pCurs, int x, int y); +void xf86SetTransparentCursor(ScreenPtr pScreen); +void xf86MoveCursor(ScreenPtr pScreen, int x, int y); +void xf86RecolorCursor(ScreenPtr pScreen, CursorPtr pCurs, Bool displayed); +Bool xf86InitHardwareCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr); + +CARD32 xf86ReverseBitOrder(CARD32 data); + +extern int xf86CursorScreenIndex; + +#endif /* _XF86CURSORPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86DDC.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86DDC.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86DDC.h (revision 51223) @@ -0,0 +1,62 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ddc/xf86DDC.h,v 1.10 2000/06/07 22:03:09 tsi Exp $ */ + +/* xf86DDC.h + * + * This file contains all information to interpret a standard EDIC block + * transmitted by a display device via DDC (Display Data Channel). So far + * there is no information to deal with optional EDID blocks. + * DDC is a Trademark of VESA (Video Electronics Standard Association). + * + * Copyright 1998 by Egbert Eich + */ + +#ifndef XF86_DDC_H +# define XF86_DDC_H + +#include "edid.h" +#include "xf86i2c.h" +#include "xf86str.h" + +/* speed up / slow down */ +typedef enum { + DDC_SLOW, + DDC_FAST +} xf86ddcSpeed; + +typedef void (* DDC1SetSpeedProc)(ScrnInfoPtr, xf86ddcSpeed); + +extern xf86MonPtr xf86DoEDID_DDC1( + int scrnIndex, + DDC1SetSpeedProc DDC1SetSpeed, + unsigned int (*DDC1Read)(ScrnInfoPtr) +); + +extern xf86MonPtr xf86DoEDID_DDC2( + int scrnIndex, + I2CBusPtr pBus +); + +extern xf86MonPtr xf86PrintEDID( + xf86MonPtr monPtr +); + +extern xf86MonPtr xf86InterpretEDID( + int screenIndex, Uchar *block +); + +extern xf86vdifPtr xf86InterpretVdif( + CARD8 *c +); + +extern Bool xf86SetDDCproperties( + ScrnInfoPtr pScreen, + xf86MonPtr DDC +); + +extern void xf86print_vdif( + xf86vdifPtr v +); + +#endif + + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Date.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Date.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Date.h (revision 51223) @@ -0,0 +1,38 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/common/xf86Date.h,v 1.6 2005/07/03 07:01:24 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Date.h,v 1.54 2003/12/19 04:52:10 dawes Exp $ */ +/* + * Copyright (c) 2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef XF86_DATE + +#define XF86_DATE "18 December 2003" + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86InPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86InPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86InPriv.h (revision 51223) @@ -0,0 +1,48 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86InPriv.h,v 1.5 2003/08/24 17:36:52 dawes Exp $ */ + +/* + * Copyright (c) 1999 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86InPriv_h +#define _xf86InPriv_h + +/* xf86Globals.c */ +#ifdef XFree86LOADER +extern InputDriverPtr *xf86InputDriverList; +#else +extern InputDriverPtr xf86InputDriverList[]; +#endif +extern int xf86NumInputDrivers; + +/* xf86Xinput.c */ +void xf86ActivateDevice(InputInfoPtr pInfo); + +#endif /* _xf86InPriv_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Keymap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Keymap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Keymap.h (revision 51223) @@ -0,0 +1,455 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Keymap.h,v 3.20 2003/08/24 17:36:53 dawes Exp $ */ + +/* + * Copyright (c) 1994-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * + * For Scancodes see notes in atKeynames.h !!!! + * + */ +/* $XConsortium: xf86Keymap.h /main/14 1996/02/21 17:38:47 kaleb $ */ + +static KeySym map[NUM_KEYCODES * GLYPHS_PER_KEY] = { + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#if !defined(__SOL8__) && (!defined(sun) || defined(i386)) + + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_Tab, XK_ISO_Left_Tab,NoSymbol, NoSymbol, + /* 0x10 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1c */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x1d */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x1e */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x28 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x2a */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x2c */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x34 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x35 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x36 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x37 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x38 */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x39 */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x3d */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x3f */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x48 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x49 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x4a */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x4c */ XK_KP_Begin, XK_KP_5, NoSymbol, NoSymbol, + /* 0x4d */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x4e */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x50 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x51 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x52 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x53 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x54 */ XK_Sys_Req, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_less, XK_greater, NoSymbol, NoSymbol, + /* 0x57 */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ XK_Home, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ XK_Up, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ XK_Prior, NoSymbol, NoSymbol, NoSymbol, + /* 0x5c */ XK_Left, NoSymbol, NoSymbol, NoSymbol, + /* 0x5d */ XK_Begin, NoSymbol, NoSymbol, NoSymbol, + /* 0x5e */ XK_Right, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ XK_End, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ XK_Down, NoSymbol, NoSymbol, NoSymbol, + /* 0x61 */ XK_Next, NoSymbol, NoSymbol, NoSymbol, + /* 0x62 */ XK_Insert, NoSymbol, NoSymbol, NoSymbol, + /* 0x63 */ XK_Delete, NoSymbol, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x66 */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x67 */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x69 */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x6a */ XK_Break, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ XK_Meta_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_Meta_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ XK_Menu, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ XK_F13, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ XK_F14, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ XK_F15, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ XK_F16, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ XK_F17, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ XK_backslash, XK_underscore, NoSymbol, NoSymbol, + /* 0x74 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ XK_Henkan, XK_Mode_switch, NoSymbol, NoSymbol, + /* 0x7a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ XK_Muhenkan, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x7e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + +#else /* SunOS */ + +/* Assumes a US English keyboard as default - sorry 'bout that + * + * Hopefully it'll be enough someone can have a sorta working + * keyboard, if they're not using XKB + * + * DWH 9/12/99 + */ + + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x10 */ XK_Tab, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1c */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1d */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x1e */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x28 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x2a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x2c */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x34 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x35 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x36 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x37 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x38 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x39 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x3d */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x3f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x48 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x49 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_Insert, NoSymbol, NoSymbol, NoSymbol, + /* 0x4c */ XK_Delete, NoSymbol, NoSymbol, NoSymbol, + /* 0x4d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_Left, NoSymbol, NoSymbol, NoSymbol, + /* 0x50 */ XK_Home, NoSymbol, NoSymbol, NoSymbol, + /* 0x51 */ XK_End, NoSymbol, NoSymbol, NoSymbol, + /* 0x52 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x53 */ XK_Up, NoSymbol, NoSymbol, NoSymbol, + /* 0x54 */ XK_Down, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ XK_Prior, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_Next, NoSymbol, NoSymbol, NoSymbol, + /* 0x57 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ XK_Right, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x5c */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x5d */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x5e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x61 */ NoSymbol, XK_KP_5, NoSymbol, NoSymbol, + /* 0x62 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x63 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x66 */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x67 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x69 */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x6a */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x74 */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x7a */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x7e */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x7f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + +#endif /* SunOS */ + +}; + +#if !defined(Lynx) && \ + !defined(__UNIXOS2__) && \ + !defined(__mips__) && \ + !defined(linux) && \ + !defined(CSRG_BASED) && \ + !defined(__CYGWIN__) && \ + !defined(__SOL8__) && \ + (!defined(sun) || defined(i386)) + +static KeySym map84[NUM_KEYCODES * GLYPHS_PER_KEY] = { + /* 0x00 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x01 */ XK_Escape, NoSymbol, NoSymbol, NoSymbol, + /* 0x02 */ XK_1, XK_exclam, NoSymbol, NoSymbol, + /* 0x03 */ XK_2, XK_at, NoSymbol, NoSymbol, + /* 0x04 */ XK_3, XK_numbersign, NoSymbol, NoSymbol, + /* 0x05 */ XK_4, XK_dollar, NoSymbol, NoSymbol, + /* 0x06 */ XK_5, XK_percent, NoSymbol, NoSymbol, + /* 0x07 */ XK_6, XK_asciicircum, NoSymbol, NoSymbol, + /* 0x08 */ XK_7, XK_ampersand, NoSymbol, NoSymbol, + /* 0x09 */ XK_8, XK_asterisk, NoSymbol, NoSymbol, + /* 0x0a */ XK_9, XK_parenleft, NoSymbol, NoSymbol, + /* 0x0b */ XK_0, XK_parenright, NoSymbol, NoSymbol, + /* 0x0c */ XK_minus, XK_underscore, NoSymbol, NoSymbol, + /* 0x0d */ XK_equal, XK_plus, NoSymbol, NoSymbol, + /* 0x0e */ XK_BackSpace, NoSymbol, NoSymbol, NoSymbol, + /* 0x0f */ XK_Tab, NoSymbol, NoSymbol, NoSymbol, + /* 0x10 */ XK_Q, NoSymbol, NoSymbol, NoSymbol, + /* 0x11 */ XK_W, NoSymbol, NoSymbol, NoSymbol, + /* 0x12 */ XK_E, NoSymbol, NoSymbol, NoSymbol, + /* 0x13 */ XK_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x14 */ XK_T, NoSymbol, NoSymbol, NoSymbol, + /* 0x15 */ XK_Y, NoSymbol, NoSymbol, NoSymbol, + /* 0x16 */ XK_U, NoSymbol, NoSymbol, NoSymbol, + /* 0x17 */ XK_I, NoSymbol, NoSymbol, NoSymbol, + /* 0x18 */ XK_O, NoSymbol, NoSymbol, NoSymbol, + /* 0x19 */ XK_P, NoSymbol, NoSymbol, NoSymbol, + /* 0x1a */ XK_bracketleft, XK_braceleft, NoSymbol, NoSymbol, + /* 0x1b */ XK_bracketright,XK_braceright, NoSymbol, NoSymbol, + /* 0x1c */ XK_Return, NoSymbol, NoSymbol, NoSymbol, + /* 0x1d */ XK_Control_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x1e */ XK_A, NoSymbol, NoSymbol, NoSymbol, + /* 0x1f */ XK_S, NoSymbol, NoSymbol, NoSymbol, + /* 0x20 */ XK_D, NoSymbol, NoSymbol, NoSymbol, + /* 0x21 */ XK_F, NoSymbol, NoSymbol, NoSymbol, + /* 0x22 */ XK_G, NoSymbol, NoSymbol, NoSymbol, + /* 0x23 */ XK_H, NoSymbol, NoSymbol, NoSymbol, + /* 0x24 */ XK_J, NoSymbol, NoSymbol, NoSymbol, + /* 0x25 */ XK_K, NoSymbol, NoSymbol, NoSymbol, + /* 0x26 */ XK_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x27 */ XK_semicolon, XK_colon, NoSymbol, NoSymbol, + /* 0x28 */ XK_quoteright, XK_quotedbl, NoSymbol, NoSymbol, + /* 0x29 */ XK_quoteleft, XK_asciitilde, NoSymbol, NoSymbol, + /* 0x2a */ XK_Shift_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x2b */ XK_backslash, XK_bar, NoSymbol, NoSymbol, + /* 0x2c */ XK_Z, NoSymbol, NoSymbol, NoSymbol, + /* 0x2d */ XK_X, NoSymbol, NoSymbol, NoSymbol, + /* 0x2e */ XK_C, NoSymbol, NoSymbol, NoSymbol, + /* 0x2f */ XK_V, NoSymbol, NoSymbol, NoSymbol, + /* 0x30 */ XK_B, NoSymbol, NoSymbol, NoSymbol, + /* 0x31 */ XK_N, NoSymbol, NoSymbol, NoSymbol, + /* 0x32 */ XK_M, NoSymbol, NoSymbol, NoSymbol, + /* 0x33 */ XK_comma, XK_less, NoSymbol, NoSymbol, + /* 0x34 */ XK_period, XK_greater, NoSymbol, NoSymbol, + /* 0x35 */ XK_slash, XK_question, NoSymbol, NoSymbol, + /* 0x36 */ XK_Shift_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x37 */ XK_KP_Multiply, NoSymbol, NoSymbol, NoSymbol, + /* 0x38 */ XK_Alt_L, XK_Meta_L, NoSymbol, NoSymbol, + /* 0x39 */ XK_space, NoSymbol, NoSymbol, NoSymbol, + /* 0x3a */ XK_Caps_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x3b */ XK_F1, NoSymbol, NoSymbol, NoSymbol, + /* 0x3c */ XK_F2, NoSymbol, NoSymbol, NoSymbol, + /* 0x3d */ XK_F3, NoSymbol, NoSymbol, NoSymbol, + /* 0x3e */ XK_F4, NoSymbol, NoSymbol, NoSymbol, + /* 0x3f */ XK_F5, NoSymbol, NoSymbol, NoSymbol, + /* 0x40 */ XK_F6, NoSymbol, NoSymbol, NoSymbol, + /* 0x41 */ XK_F7, NoSymbol, NoSymbol, NoSymbol, + /* 0x42 */ XK_F8, NoSymbol, NoSymbol, NoSymbol, + /* 0x43 */ XK_F9, NoSymbol, NoSymbol, NoSymbol, + /* 0x44 */ XK_F10, NoSymbol, NoSymbol, NoSymbol, + /* 0x45 */ XK_Num_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x46 */ XK_Scroll_Lock, NoSymbol, NoSymbol, NoSymbol, + /* 0x47 */ XK_KP_Home, XK_KP_7, NoSymbol, NoSymbol, + /* 0x48 */ XK_KP_Up, XK_KP_8, NoSymbol, NoSymbol, + /* 0x49 */ XK_KP_Prior, XK_KP_9, NoSymbol, NoSymbol, + /* 0x4a */ XK_KP_Subtract, NoSymbol, NoSymbol, NoSymbol, + /* 0x4b */ XK_KP_Left, XK_KP_4, NoSymbol, NoSymbol, + /* 0x4c */ NoSymbol, XK_KP_5, NoSymbol, NoSymbol, + /* 0x4d */ XK_KP_Right, XK_KP_6, NoSymbol, NoSymbol, + /* 0x4e */ XK_KP_Add, NoSymbol, NoSymbol, NoSymbol, + /* 0x4f */ XK_KP_End, XK_KP_1, NoSymbol, NoSymbol, + /* 0x50 */ XK_KP_Down, XK_KP_2, NoSymbol, NoSymbol, + /* 0x51 */ XK_KP_Next, XK_KP_3, NoSymbol, NoSymbol, + /* 0x52 */ XK_KP_Insert, XK_KP_0, NoSymbol, NoSymbol, + /* 0x53 */ XK_KP_Delete, XK_KP_Decimal, NoSymbol, NoSymbol, + /* 0x54 */ XK_Sys_Req, NoSymbol, NoSymbol, NoSymbol, + /* 0x55 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x56 */ XK_less, XK_greater, NoSymbol, NoSymbol, + /* 0x57 */ XK_F11, NoSymbol, NoSymbol, NoSymbol, + /* 0x58 */ XK_F12, NoSymbol, NoSymbol, NoSymbol, + /* 0x59 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x5f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x60 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x61 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x62 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x63 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x64 */ XK_KP_Enter, NoSymbol, NoSymbol, NoSymbol, + /* 0x65 */ XK_Control_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x66 */ XK_Pause, NoSymbol, NoSymbol, NoSymbol, + /* 0x67 */ XK_Print, NoSymbol, NoSymbol, NoSymbol, + /* 0x68 */ XK_KP_Divide, NoSymbol, NoSymbol, NoSymbol, + /* 0x69 */ XK_Alt_R, XK_Meta_R, NoSymbol, NoSymbol, + /* 0x6a */ XK_Break, NoSymbol, NoSymbol, NoSymbol, + /* 0x6b */ XK_Meta_L, NoSymbol, NoSymbol, NoSymbol, + /* 0x6c */ XK_Meta_R, NoSymbol, NoSymbol, NoSymbol, + /* 0x6d */ XK_Menu, NoSymbol, NoSymbol, NoSymbol, + /* 0x6e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x6f */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x70 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x71 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x72 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x73 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x74 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x75 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x76 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x77 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x78 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x79 */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7a */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7b */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7c */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7d */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, + /* 0x7e */ NoSymbol, NoSymbol, NoSymbol, NoSymbol, +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Module.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Module.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Module.h (revision 51223) @@ -0,0 +1,231 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Module.h,v 1.37 2003/08/24 17:36:54 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains the parts of the loader interface that are visible + * to modules. This is the only loader-related header that modules should + * include. + * + * It should include a bare minimum of other headers. + * + * Longer term, the module/loader code should probably live directly under + * Xserver/. + * + * XXX This file arguably belongs in xfree86/loader/. + */ + +#ifndef _XF86MODULE_H +#define _XF86MODULE_H + +#include "misc.h" +#include "xf86Version.h" +#ifndef NULL +#define NULL ((void *)0) +#endif + +typedef enum { + LD_RESOLV_IFDONE = 0, /* only check if no more + delays pending */ + LD_RESOLV_NOW = 1, /* finish one delay step */ + LD_RESOLV_FORCE = 2 /* force checking... */ +} LoaderResolveOptions; + +#define DEFAULT_LIST ((char *)-1) + +/* This indicates a special module that doesn't have the usual entry point */ +#define EXTERN_MODULE ((pointer)-1) + +/* Built-in ABI classes. These definitions must not be changed. */ +#define ABI_CLASS_NONE NULL +#define ABI_CLASS_ANSIC "X.Org ANSI C Emulation" +#define ABI_CLASS_VIDEODRV "X.Org Video Driver" +#define ABI_CLASS_XINPUT "X.Org XInput driver" +#define ABI_CLASS_EXTENSION "X.Org Server Extension" +#define ABI_CLASS_FONT "X.Org Font Renderer" + +#define ABI_MINOR_MASK 0x0000FFFF +#define ABI_MAJOR_MASK 0xFFFF0000 +#define GET_ABI_MINOR(v) ((v) & ABI_MINOR_MASK) +#define GET_ABI_MAJOR(v) (((v) & ABI_MAJOR_MASK) >> 16) +#define SET_ABI_VERSION(maj, min) \ + ((((maj) << 16) & ABI_MAJOR_MASK) | ((min) & ABI_MINOR_MASK)) + +/* + * ABI versions. Each version has a major and minor revision. Modules + * using lower minor revisions must work with servers of a higher minor + * revision. There is no compatibility between different major revisions. + * Whenever the ABI_ANSIC_VERSION is changed, the others must also be + * changed. The minor revision mask is 0x0000FFFF and the major revision + * mask is 0xFFFF0000. + */ +#define ABI_ANSIC_VERSION SET_ABI_VERSION(0, 3) +#define ABI_VIDEODRV_VERSION SET_ABI_VERSION(1, 0) +#define ABI_XINPUT_VERSION SET_ABI_VERSION(0, 6) +#define ABI_EXTENSION_VERSION SET_ABI_VERSION(0, 3) +#define ABI_FONT_VERSION SET_ABI_VERSION(0, 5) + +#define MODINFOSTRING1 0xef23fdc5 +#define MODINFOSTRING2 0x10dc023a + +#ifndef MODULEVENDORSTRING +#ifndef __OS2ELF__ +#define MODULEVENDORSTRING "X.Org Foundation" +#else +#define MODULEVENDORSTRING "X.Org Foundation - OS2" +#endif +#endif + +/* Error return codes for errmaj. New codes must only be added at the end. */ +typedef enum { + LDR_NOERROR = 0, + LDR_NOMEM, /* memory allocation failed */ + LDR_NOENT, /* Module file does not exist */ + LDR_NOSUBENT, /* pre-requsite file to be sub-loaded does not exist */ + LDR_NOSPACE, /* internal module array full */ + LDR_NOMODOPEN, /* module file could not be opened (check errmin) */ + LDR_UNKTYPE, /* file is not a recognized module type */ + LDR_NOLOAD, /* type specific loader failed */ + LDR_ONCEONLY, /* Module should only be loaded once (not an error) */ + LDR_NOPORTOPEN, /* could not open port (check errmin) */ + LDR_NOHARDWARE, /* could not query/initialize the hardware device */ + LDR_MISMATCH, /* the module didn't match the spec'd requirments */ + LDR_BADUSAGE, /* LoadModule is called with bad arguments */ + LDR_INVALID, /* The module doesn't have a valid ModuleData object */ + LDR_BADOS, /* The module doesn't support the OS */ + LDR_MODSPECIFIC /* A module-specific error in the SetupProc */ +} LoaderErrorCode; + +/* + * Some common module classes. The moduleclass can be used to identify + * that modules loaded are of the correct type. This is a finer + * classification than the ABI classes even though the default set of + * classes have the same names. For example, not all modules that require + * the video driver ABI are themselves video drivers. + */ +#define MOD_CLASS_NONE NULL +#define MOD_CLASS_VIDEODRV "X.Org Video Driver" +#define MOD_CLASS_XINPUT "X.Org XInput Driver" +#define MOD_CLASS_FONT "X.Org Font Renderer" +#define MOD_CLASS_EXTENSION "X.Org Server Extension" + +/* This structure is expected to be returned by the initfunc */ +typedef struct { + const char * modname; /* name of module, e.g. "foo" */ + const char * vendor; /* vendor specific string */ + CARD32 _modinfo1_; /* constant MODINFOSTRING1/2 to find */ + CARD32 _modinfo2_; /* infoarea with a binary editor or sign tool */ + CARD32 xf86version; /* contains XF86_VERSION_CURRENT */ + CARD8 majorversion; /* module-specific major version */ + CARD8 minorversion; /* module-specific minor version */ + CARD16 patchlevel; /* module-specific patch level */ + const char * abiclass; /* ABI class that the module uses */ + CARD32 abiversion; /* ABI version */ + const char * moduleclass; /* module class description */ + CARD32 checksum[4]; /* contains a digital signature of the */ + /* version info structure */ +} XF86ModuleVersionInfo; + +/* + * This structure can be used to callers of LoadModule and LoadSubModule to + * specify version and/or ABI requirements. + */ +typedef struct { + CARD8 majorversion; /* module-specific major version */ + CARD8 minorversion; /* moudle-specific minor version */ + CARD16 patchlevel; /* module-specific patch level */ + const char * abiclass; /* ABI class that the module uses */ + CARD32 abiversion; /* ABI version */ + const char * moduleclass; /* module class */ +} XF86ModReqInfo; + +/* values to indicate unspecified fields in XF86ModReqInfo. */ +#define MAJOR_UNSPEC 0xFF +#define MINOR_UNSPEC 0xFF +#define PATCH_UNSPEC 0xFFFF +#define ABI_VERS_UNSPEC 0xFFFFFFFF + +#define MODULE_VERSION_NUMERIC(maj, min, patch) \ + ((((maj) & 0xFF) << 24) | (((min) & 0xFF) << 16) | (patch & 0xFFFF)) +#define GET_MODULE_MAJOR_VERSION(vers) (((vers) >> 24) & 0xFF) +#define GET_MODULE_MINOR_VERSION(vers) (((vers) >> 16) & 0xFF) +#define GET_MODULE_PATCHLEVEL(vers) ((vers) & 0xFFFF) + +#define INITARGS void + +typedef void (*InitExtension)(INITARGS); + +typedef struct { + InitExtension initFunc; + const char * name; + Bool *disablePtr; + InitExtension setupFunc; + const char ** initDependencies; +} ExtensionModule; + +extern ExtensionModule *ExtensionModuleList; + +/* Prototypes for Loader functions that are exported to modules */ +#ifndef IN_LOADER +/* Prototypes with opaque pointers for use by modules */ +pointer LoadSubModule(pointer, const char *, const char **, + const char **, pointer, const XF86ModReqInfo *, + int *, int *); +pointer LoadSubModuleLocal(pointer, const char *, const char **, + const char **, pointer, const XF86ModReqInfo *, + int *, int *); +void UnloadSubModule(pointer); +void LoadFont(pointer); +void UnloadModule (pointer); +#endif +pointer LoaderSymbol(const char *); +pointer LoaderSymbolLocal(pointer module, const char *); +char **LoaderListDirs(const char **, const char **); +void LoaderFreeDirList(char **); +void LoaderErrorMsg(const char *, const char *, int, int); +void LoadExtension(ExtensionModule *, Bool); +void LoaderRefSymLists(const char **, ...); +void LoaderRefSymbols(const char *, ...); +void LoaderReqSymLists(const char **, ...); +void LoaderReqSymbols(const char *, ...); +int LoaderCheckUnresolved(int); +void LoaderGetOS(const char **name, int *major, int *minor, int *teeny); +int LoaderGetABIVersion(const char *abiclass); + +typedef pointer (*ModuleSetupProc)(pointer, pointer, int *, int *); +typedef void (*ModuleTearDownProc)(pointer); +#define MODULESETUPPROTO(func) pointer func(pointer, pointer, int*, int*) +#define MODULETEARDOWNPROTO(func) void func(pointer) + +typedef struct { + XF86ModuleVersionInfo * vers; + ModuleSetupProc setup; + ModuleTearDownProc teardown; +} XF86ModuleData; + +#endif /* _XF86STR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSKbd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSKbd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSKbd.h (revision 51223) @@ -0,0 +1,133 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSKbd.h,v 1.5tsi Exp $ */ +/* + * Copyright (c) 2002-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + * + * Author: Ivan Pascal. + */ + +#include "xf86Xinput.h" + +Bool ATScancode(InputInfoPtr pInfo, int *scanCode); + +/* Public interface to OS-specific keyboard support. */ + +typedef int (*KbdInitProc)(InputInfoPtr pInfo, int what); +typedef int (*KbdOnProc)(InputInfoPtr pInfo, int what); +typedef int (*KbdOffProc)(InputInfoPtr pInfo, int what); +typedef void (*BellProc)(InputInfoPtr pInfo, + int loudness, int pitch, int duration); +typedef void (*SetLedsProc)(InputInfoPtr pInfo, int leds); +typedef int (*GetLedsProc)(InputInfoPtr pInfo); +typedef void (*SetKbdRepeatProc)(InputInfoPtr pInfo, char rad); +typedef void (*KbdGetMappingProc)(InputInfoPtr pInfo, + KeySymsPtr pKeySyms, CARD8* pModMap); +typedef int (*GetSpecialKeyProc)(InputInfoPtr pInfo, int scanCode); +typedef Bool (*SpecialKeyProc)(InputInfoPtr pInfo, + int key, Bool down, int modifiers); +typedef int (*RemapScanCodeProc)(InputInfoPtr pInfo, int *scanCode); +typedef Bool (*OpenKeyboardProc)(InputInfoPtr pInfo); +typedef void (*PostEventProc)(InputInfoPtr pInfo, + unsigned int key, Bool down); +typedef struct { + int begin; + int end; + unsigned char *map; +} TransMapRec, *TransMapPtr; + +typedef struct { + KbdInitProc KbdInit; + KbdOnProc KbdOn; + KbdOffProc KbdOff; + BellProc Bell; + SetLedsProc SetLeds; + GetLedsProc GetLeds; + SetKbdRepeatProc SetKbdRepeat; + KbdGetMappingProc KbdGetMapping; + RemapScanCodeProc RemapScanCode; + GetSpecialKeyProc GetSpecialKey; + SpecialKeyProc SpecialKey; + + OpenKeyboardProc OpenKeyboard; + PostEventProc PostEvent; + + int rate; + int delay; + int bell_pitch; + int bell_duration; + Bool autoRepeat; + unsigned long leds; + unsigned long xledsMask; + unsigned long keyLeds; + int scanPrefix; + Bool vtSwitchSupported; + Bool CustomKeycodes; + Bool noXkb; + Bool isConsole; + TransMapPtr scancodeMap; + TransMapPtr specialMap; + + /* os specific */ + pointer private; + int kbdType; + int consType; + int wsKbdType; + Bool sunKbd; + Bool Panix106; + +} KbdDevRec, *KbdDevPtr; + +typedef enum { + PROT_STD, + PROT_XQUEUE, + PROT_WSCONS, + PROT_USB, + PROT_UNKNOWN_KBD +} KbdProtocolId; + +typedef struct { + const char *name; + KbdProtocolId id; +} KbdProtocolRec; + +Bool xf86OSKbdPreInit(InputInfoPtr pInfo); + +/* Adjust this when the kbd interface changes. */ + +/* + * History: + * + * 1.0.0 - Initial version. + */ + +#define OS_KBD_VERSION_MAJOR 1 +#define OS_KBD_VERSION_MINOR 0 +#define OS_KBD_VERSION_PATCH 0 + +#define OS_KBD_VERSION_CURRENT \ + BUILTIN_INTERFACE_VERSION_NUMERIC(OS_KBD_VERSION_MAJOR, \ + OS_KBD_VERSION_MINOR, \ + OS_KBD_VERSION_PATCH) + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSmouse.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSmouse.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSmouse.h (revision 51223) @@ -0,0 +1,295 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSmouse.h,v 1.24 2003/11/03 05:11:51 tsi Exp $ */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Public interface to OS-specific mouse support. */ + +#ifndef _XF86OSMOUSE_H_ +#define _XF86OSMOUSE_H_ + +#include "xf86Xinput.h" + +/* Mouse interface classes */ +#define MSE_NONE 0x00 +#define MSE_SERIAL 0x01 /* serial port */ +#define MSE_BUS 0x02 /* old bus mouse */ +#define MSE_PS2 0x04 /* standard read-only PS/2 */ +#define MSE_XPS2 0x08 /* extended PS/2 */ +#define MSE_AUTO 0x10 /* auto-detect (PnP) */ +#define MSE_MISC 0x20 /* The OS layer will identify the + * specific protocol names that are + * supported for this class. */ + +/* Mouse Protocol IDs. */ +typedef enum { + PROT_UNKNOWN = -2, + PROT_UNSUP = -1, /* protocol is not supported */ + PROT_MS = 0, + PROT_MSC, + PROT_MM, + PROT_LOGI, + PROT_LOGIMAN, + PROT_MMHIT, + PROT_GLIDE, + PROT_IMSERIAL, + PROT_THINKING, + PROT_ACECAD, + PROT_VALUMOUSESCROLL, + PROT_PS2, + PROT_GENPS2, + PROT_IMPS2, + PROT_EXPPS2, + PROT_THINKPS2, + PROT_MMPS2, + PROT_GLIDEPS2, + PROT_NETPS2, + PROT_NETSCPS2, + PROT_BM, + PROT_AUTO, + PROT_SYSMOUSE, + PROT_NUMPROTOS /* This must always be last. */ +} MouseProtocolID; + +struct _MouseDevRec; + +typedef int (*GetInterfaceTypesProc)(void); +typedef const char **(*BuiltinNamesProc)(void); +typedef Bool (*CheckProtocolProc)(const char *protocol); +typedef Bool (*BuiltinPreInitProc)(InputInfoPtr pInfo, const char *protocol, + int flags); +typedef const char *(*DefaultProtocolProc)(void); +typedef const char *(*SetupAutoProc)(InputInfoPtr pInfo, int *protoPara); +typedef void (*SetResProc)(InputInfoPtr pInfo, const char* protocol, int rate, + int res); +typedef const char *(*FindDeviceProc)(InputInfoPtr pInfo, const char *protocol, + int flags); +typedef const char *(*GuessProtocolProc)(InputInfoPtr pInfo, int flags); + +/* + * OSMouseInfoRec is used to pass information from the OSMouse layer to the + * OS-independent mouse driver. + */ +typedef struct { + GetInterfaceTypesProc SupportedInterfaces; + BuiltinNamesProc BuiltinNames; + CheckProtocolProc CheckProtocol; + BuiltinPreInitProc PreInit; + DefaultProtocolProc DefaultProtocol; + SetupAutoProc SetupAuto; + SetResProc SetPS2Res; + SetResProc SetBMRes; + SetResProc SetMiscRes; + FindDeviceProc FindDevice; + GuessProtocolProc GuessProtocol; +} OSMouseInfoRec, *OSMouseInfoPtr; + +/* + * SupportedInterfaces: Returns the mouse interface types that the OS support. + * If MSE_MISC is returned, then the BuiltinNames and + * CheckProtocol should be set. + * + * BuiltinNames: Returns the names of the protocols that are fully handled + * in the OS-specific code. These are names that don't appear + * directly in the main "mouse" driver. + * + * CheckProtocol: Checks if the protocol name given is supported by the + * OS. It should return TRUE for both "builtin" protocols and + * protocols of type MSE_MISC that are supported by the OS. + * + * PreInit: The PreInit function for protocols that are builtin. This + * function is passed the protocol name. + * + * DefaultProtocol: Returns the name of a default protocol that should be used + * for the OS when none has been supplied in the config file. + * This should only be set when there is a reasonable default. + * + * SetupAuto: This function can be used to do OS-specific protocol + * auto-detection. It returns the name of the detected protocol, + * or NULL when detection fails. It may also adjust one or more + * of the "protoPara" values for the detected protocol by setting + * then to something other than -1. SetupAuto gets called in two + * ways. The first is before any devices have been opened. This + * can be used when the protocol "Auto" always maps to a single + * protocol type. The second is with the device open, allowing + * OS-specific probing to be done. + * + * SetPS2Res: Set the resolution and sample rate for MSE_PS2 and MSE_XPS2 + * protocol types. + * + * SetBMRes: Set the resolution and sample rate for MSE_BM protocol types. + * + * SetMiscRes: Set the resolution and sample rate for MSE_MISC protocol types. + * + * FindDevice: This function gets called when no Device has been specified + * in the config file. OS-specific methods may be used to guess + * which input device to use. This function is called after the + * pre-open attempts at protocol discovery are done, but before + * the device is open. I.e., after the first SetupAuto() call, + * after the DefaultProtocol() call, but before the PreInit() + * call. Available protocol information may be used in locating + * the default input device. + * + * GuessProtocol: A last resort attempt at guessing the mouse protocol by + * whatever OS-specific means might be available. OS-independent + * things should be in the mouse driver. This function gets + * called after the mouse driver's OS-independent methods have + * failed. + */ + +extern OSMouseInfoPtr xf86OSMouseInit(int flags); + +/* Adjust this when the mouse interface changes. */ + +/* + * History: + * + * 1.0.0 - Everything up to when versioning was started. + * 1.1.0 - FindDevice and GuessProtocol added to OSMouseInfoRec + * 1.2.0 - xisbscale added to MouseDevRec + * + */ + +#define OS_MOUSE_VERSION_MAJOR 1 +#define OS_MOUSE_VERSION_MINOR 2 +#define OS_MOUSE_VERSION_PATCH 0 + +#define OS_MOUSE_VERSION_CURRENT \ + BUILTIN_INTERFACE_VERSION_NUMERIC(OS_MOUSE_VERSION_MAJOR, \ + OS_MOUSE_VERSION_MINOR, \ + OS_MOUSE_VERSION_PATCH) + +#define HAVE_GUESS_PROTOCOL \ + (xf86GetBuiltinInterfaceVersion(BUILTIN_IF_OSMOUSE, 0) >= \ + BUILTIN_INTERFACE_VERSION_NUMERIC(1, 1, 0)) + +#define HAVE_FIND_DEVICE \ + (xf86GetBuiltinInterfaceVersion(BUILTIN_IF_OSMOUSE, 0) >= \ + BUILTIN_INTERFACE_VERSION_NUMERIC(1, 1, 0)) + +/* Z axis mapping */ +#define MSE_NOZMAP 0 +#define MSE_MAPTOX -1 +#define MSE_MAPTOY -2 +#define MSE_MAPTOZ -3 +#define MSE_MAPTOW -4 + +/* Generalize for other axes. */ +#define MSE_NOAXISMAP MSE_NOZMAP + +#define MSE_MAXBUTTONS 24 +#define MSE_DFLTBUTTONS 3 + +/* + * Mouse device record. This is shared by the mouse driver and the OSMouse + * layer. + */ + +typedef void (*checkMovementsProc)(InputInfoPtr,int, int); +typedef void (*autoProbeProc)(InputInfoPtr, Bool, Bool); +typedef Bool (*collectDataProc)(struct _MouseDevRec *, unsigned char); +typedef Bool (*dataGoodProc)(struct _MouseDevRec *); + +typedef void (*PostMseEventProc)(InputInfoPtr pInfo, int buttons, + int dx, int dy, int dz, int dw); +typedef void (*MouseCommonOptProc)(InputInfoPtr pInfo); + +typedef struct _MouseDevRec { + PtrCtrlProcPtr Ctrl; + PostMseEventProc PostEvent; + MouseCommonOptProc CommonOptions; + DeviceIntPtr device; + const char * mseDevice; + const char * protocol; + MouseProtocolID protocolID; + MouseProtocolID oldProtocolID; /* hack */ + int class; + int mseModel; + int baudRate; + int oldBaudRate; + int sampleRate; + int lastButtons; + int threshold; /* acceleration */ + int num; + int den; + int buttons; /* # of buttons */ + int emulateState; /* automata state for 2 button mode */ + Bool emulate3Buttons; + Bool emulate3ButtonsSoft; + int emulate3Timeout;/* Timeout for 3 button emulation */ + Bool chordMiddle; + Bool flipXY; + int invX; + int invY; + int mouseFlags; /* Flags to Clear after opening + * mouse dev */ + int truebuttons; /* (not used) + * Arg to maintain before + * emulate3buttons timer callback */ + int resolution; + int negativeZ; /* button mask */ + int positiveZ; /* button mask */ + int negativeW; /* button mask */ + int positiveW; /* button mask */ + pointer buffer; /* usually an XISBuffer* */ + int protoBufTail; + unsigned char protoBuf[8]; + unsigned char protoPara[8]; + unsigned char inSync; /* driver in sync with datastream */ + pointer mousePriv; /* private area */ + InputInfoPtr pInfo; + int origProtocolID; + const char * origProtocol; + Bool emulate3Pending;/* timer waiting */ + CARD32 emulate3Expires;/* time to fire emulation code */ + Bool emulateWheel; + int wheelInertia; + int wheelButton; + int negativeX; /* Button values. Unlike the Z and */ + int positiveX; /* W equivalents, these are button */ + int negativeY; /* values rather than button masks. */ + int positiveY; + int wheelYDistance; + int wheelXDistance; + Bool autoProbe; + checkMovementsProc checkMovements; + autoProbeProc autoProbeMouse; + collectDataProc collectData; + dataGoodProc dataGood; + int angleOffset; + pointer pDragLock; /* drag lock area */ + int xisbscale; /* buffer size for 1 event */ + int wheelButtonTimeout;/* Timeout for the wheel button emulation */ + CARD32 wheelButtonExpires; + int doubleClickSourceButtonMask; + int doubleClickTargetButton; + int doubleClickTargetButtonMask; + int doubleClickOldSourceState; + int lastMappedButtons; + int buttonMap[MSE_MAXBUTTONS]; +} MouseDevRec, *MouseDevPtr; + +#endif /* _XF86OSMOUSE_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86OSpriv.h (revision 51223) @@ -0,0 +1,57 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86OSpriv.h,v 1.6 2003/08/24 17:37:03 dawes Exp $ */ +/* + * Copyright (c) 1999-2000 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86OSPRIV_H +#define _XF86OSPRIV_H + +typedef pointer (*MapMemProcPtr)(int, unsigned long, unsigned long, int); +typedef void (*UnmapMemProcPtr)(int, pointer, unsigned long); +typedef pointer (*SetWCProcPtr)(int, unsigned long, unsigned long, Bool, + MessageType); +typedef void (*ProtectMemProcPtr)(int, pointer, unsigned long, Bool); +typedef void (*UndoWCProcPtr)(int, pointer); +typedef void (*ReadSideEffectsProcPtr)(int, pointer, unsigned long); + +typedef struct { + Bool initialised; + MapMemProcPtr mapMem; + UnmapMemProcPtr unmapMem; + ProtectMemProcPtr protectMem; + SetWCProcPtr setWC; + UndoWCProcPtr undoWC; + ReadSideEffectsProcPtr readSideEffects; + Bool linearSupported; +} VidMemInfo, *VidMemInfoPtr; + +void xf86OSInitVidMem(VidMemInfoPtr); + +#endif /* _XF86OSPRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Opt.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Opt.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Opt.h (revision 51223) @@ -0,0 +1,114 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Opt.h,v 1.15 2003/10/08 14:30:38 dawes Exp $ */ + +/* + * Copyright (c) 1998-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* Option handling things that ModuleSetup procs can use */ + +#ifndef _XF86_OPT_H_ +#define _XF86_OPT_H_ + +typedef struct { + double freq; + int units; +} OptFrequency; + +typedef union { + unsigned long num; + char * str; + double realnum; + Bool bool; + OptFrequency freq; +} ValueUnion; + +typedef enum { + OPTV_NONE = 0, + OPTV_INTEGER, + OPTV_STRING, /* a non-empty string */ + OPTV_ANYSTR, /* Any string, including an empty one */ + OPTV_REAL, + OPTV_BOOLEAN, + OPTV_FREQ +} OptionValueType; + +typedef enum { + OPTUNITS_HZ = 1, + OPTUNITS_KHZ, + OPTUNITS_MHZ +} OptFreqUnits; + +typedef struct { + int token; + const char* name; + OptionValueType type; + ValueUnion value; + Bool found; +} OptionInfoRec, *OptionInfoPtr; + +int xf86SetIntOption(pointer optlist, const char *name, int deflt); +double xf86SetRealOption(pointer optlist, const char *name, double deflt); +char *xf86SetStrOption(pointer optlist, const char *name, char *deflt); +int xf86SetBoolOption(pointer list, const char *name, int deflt ); +int xf86CheckIntOption(pointer optlist, const char *name, int deflt); +double xf86CheckRealOption(pointer optlist, const char *name, double deflt); +char *xf86CheckStrOption(pointer optlist, const char *name, char *deflt); +int xf86CheckBoolOption(pointer list, const char *name, int deflt ); +pointer xf86AddNewOption(pointer head, const char *name, const char *val ); +pointer xf86NewOption(char *name, char *value ); +pointer xf86NextOption(pointer list ); +pointer xf86OptionListCreate(const char **options, int count, int used); +pointer xf86OptionListMerge(pointer head, pointer tail); +void xf86OptionListFree(pointer opt); +char *xf86OptionName(pointer opt); +char *xf86OptionValue(pointer opt); +void xf86OptionListReport(pointer parm); +pointer xf86FindOption(pointer options, const char *name); +char *xf86FindOptionValue(pointer options, const char *name); +void xf86MarkOptionUsed(pointer option); +void xf86MarkOptionUsedByName(pointer options, const char *name); +Bool xf86CheckIfOptionUsed(pointer option); +Bool xf86CheckIfOptionUsedByName(pointer options, const char *name); +void xf86ShowUnusedOptions(int scrnIndex, pointer options); +void xf86ProcessOptions(int scrnIndex, pointer options, OptionInfoPtr optinfo); +OptionInfoPtr xf86TokenToOptinfo(const OptionInfoRec *table, int token); +const char *xf86TokenToOptName(const OptionInfoRec *table, int token); +Bool xf86IsOptionSet(const OptionInfoRec *table, int token); +char *xf86GetOptValString(const OptionInfoRec *table, int token); +Bool xf86GetOptValInteger(const OptionInfoRec *table, int token, int *value); +Bool xf86GetOptValULong(const OptionInfoRec *table, int token, unsigned long *value); +Bool xf86GetOptValReal(const OptionInfoRec *table, int token, double *value); +Bool xf86GetOptValFreq(const OptionInfoRec *table, int token, + OptFreqUnits expectedUnits, double *value); +Bool xf86GetOptValBool(const OptionInfoRec *table, int token, Bool *value); +Bool xf86ReturnOptValBool(const OptionInfoRec *table, int token, Bool def); +int xf86NameCmp(const char *s1, const char *s2); +char *xf86NormalizeName(const char *s); +pointer xf86ReplaceIntOption(pointer optlist, const char *name, const int val); +pointer xf86ReplaceRealOption(pointer optlist, const char *name, const double val); +pointer xf86ReplaceBoolOption(pointer optlist, const char *name, const Bool val); +pointer xf86ReplaceStrOption(pointer optlist, const char *name, const char* val); +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Optrec.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Optrec.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Optrec.h (revision 51223) @@ -0,0 +1,113 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86Optrec.h,v 1.11 2003/08/24 17:37:08 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains the Option Record that is passed between the Parser, + * and Module setup procs. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86Optrec_h_ +#define _xf86Optrec_h_ +#include + +/* + * all records that need to be linked lists should contain a GenericList as + * their first field. + */ +typedef struct generic_list_rec +{ + void *next; +} +GenericListRec, *GenericListPtr, *glp; + +/* + * All options are stored using this data type. + */ +typedef struct +{ + GenericListRec list; + char *opt_name; + char *opt_val; + int opt_used; + char *opt_comment; +} +XF86OptionRec, *XF86OptionPtr; + + +XF86OptionPtr xf86addNewOption(XF86OptionPtr head, char *name, char *val); +XF86OptionPtr xf86optionListDup(XF86OptionPtr opt); +void xf86optionListFree(XF86OptionPtr opt); +char *xf86optionName(XF86OptionPtr opt); +char *xf86optionValue(XF86OptionPtr opt); +XF86OptionPtr xf86newOption(char *name, char *value); +XF86OptionPtr xf86nextOption(XF86OptionPtr list); +XF86OptionPtr xf86findOption(XF86OptionPtr list, const char *name); +char *xf86findOptionValue(XF86OptionPtr list, const char *name); +int xf86findOptionBoolean (XF86OptionPtr, const char *, int); +XF86OptionPtr xf86optionListCreate(const char **options, int count, int used); +XF86OptionPtr xf86optionListMerge(XF86OptionPtr head, XF86OptionPtr tail); +char *xf86configStrdup (const char *s); +int xf86nameCompare (const char *s1, const char *s2); +char *xf86uLongToString(unsigned long i); +void xf86debugListOptions(XF86OptionPtr); +XF86OptionPtr xf86parseOption(XF86OptionPtr head); +void xf86printOptionList(FILE *fp, XF86OptionPtr list, int tabs); + + +#endif /* _xf86Optrec_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Parser.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Parser.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Parser.h (revision 51223) @@ -0,0 +1,483 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86Parser.h,v 1.33 2003/10/08 14:58:30 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains the external interfaces for the XFree86 configuration + * file parser. + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86Parser_h_ +#define _xf86Parser_h_ + +#include "xf86Optrec.h" + +#define HAVE_PARSER_DECLS + +typedef struct +{ + char *file_logfile; + char *file_rgbpath; + char *file_modulepath; + char *file_inputdevs; + char *file_fontpath; + char *file_comment; +} +XF86ConfFilesRec, *XF86ConfFilesPtr; + +/* Values for load_type */ +#define XF86_LOAD_MODULE 0 +#define XF86_LOAD_DRIVER 1 + +typedef struct +{ + GenericListRec list; + int load_type; + char *load_name; + XF86OptionPtr load_opt; + char *load_comment; +} +XF86LoadRec, *XF86LoadPtr; + +typedef struct +{ + XF86LoadPtr mod_load_lst; + char *mod_comment; +} +XF86ConfModuleRec, *XF86ConfModulePtr; + +#define CONF_IMPLICIT_KEYBOARD "Implicit Core Keyboard" + +#define CONF_IMPLICIT_POINTER "Implicit Core Pointer" + +#define XF86CONF_PHSYNC 0x0001 +#define XF86CONF_NHSYNC 0x0002 +#define XF86CONF_PVSYNC 0x0004 +#define XF86CONF_NVSYNC 0x0008 +#define XF86CONF_INTERLACE 0x0010 +#define XF86CONF_DBLSCAN 0x0020 +#define XF86CONF_CSYNC 0x0040 +#define XF86CONF_PCSYNC 0x0080 +#define XF86CONF_NCSYNC 0x0100 +#define XF86CONF_HSKEW 0x0200 /* hskew provided */ +#define XF86CONF_BCAST 0x0400 +#define XF86CONF_CUSTOM 0x0800 /* timing numbers customized by editor */ +#define XF86CONF_VSCAN 0x1000 + +typedef struct +{ + GenericListRec list; + char *ml_identifier; + int ml_clock; + int ml_hdisplay; + int ml_hsyncstart; + int ml_hsyncend; + int ml_htotal; + int ml_vdisplay; + int ml_vsyncstart; + int ml_vsyncend; + int ml_vtotal; + int ml_vscan; + int ml_flags; + int ml_hskew; + char *ml_comment; +} +XF86ConfModeLineRec, *XF86ConfModeLinePtr; + +typedef struct +{ + GenericListRec list; + char *vp_identifier; + XF86OptionPtr vp_option_lst; + char *vp_comment; +} +XF86ConfVideoPortRec, *XF86ConfVideoPortPtr; + +typedef struct +{ + GenericListRec list; + char *va_identifier; + char *va_vendor; + char *va_board; + char *va_busid; + char *va_driver; + XF86OptionPtr va_option_lst; + XF86ConfVideoPortPtr va_port_lst; + char *va_fwdref; + char *va_comment; +} +XF86ConfVideoAdaptorRec, *XF86ConfVideoAdaptorPtr; + +#define CONF_MAX_HSYNC 8 +#define CONF_MAX_VREFRESH 8 + +typedef struct +{ + float hi, lo; +} +parser_range; + +typedef struct +{ + int red, green, blue; +} +parser_rgb; + +typedef struct +{ + GenericListRec list; + char *modes_identifier; + XF86ConfModeLinePtr mon_modeline_lst; + char *modes_comment; +} +XF86ConfModesRec, *XF86ConfModesPtr; + +typedef struct +{ + GenericListRec list; + char *ml_modes_str; + XF86ConfModesPtr ml_modes; +} +XF86ConfModesLinkRec, *XF86ConfModesLinkPtr; + +typedef struct +{ + GenericListRec list; + char *mon_identifier; + char *mon_vendor; + char *mon_modelname; + int mon_width; /* in mm */ + int mon_height; /* in mm */ + XF86ConfModeLinePtr mon_modeline_lst; + int mon_n_hsync; + parser_range mon_hsync[CONF_MAX_HSYNC]; + int mon_n_vrefresh; + parser_range mon_vrefresh[CONF_MAX_VREFRESH]; + float mon_gamma_red; + float mon_gamma_green; + float mon_gamma_blue; + XF86OptionPtr mon_option_lst; + XF86ConfModesLinkPtr mon_modes_sect_lst; + char *mon_comment; +} +XF86ConfMonitorRec, *XF86ConfMonitorPtr; + +#define CONF_MAXDACSPEEDS 4 +#define CONF_MAXCLOCKS 128 + +typedef struct +{ + GenericListRec list; + char *dev_identifier; + char *dev_vendor; + char *dev_board; + char *dev_chipset; + char *dev_busid; + char *dev_card; + char *dev_driver; + char *dev_ramdac; + int dev_dacSpeeds[CONF_MAXDACSPEEDS]; + int dev_videoram; + int dev_textclockfreq; + unsigned long dev_bios_base; + unsigned long dev_mem_base; + unsigned long dev_io_base; + char *dev_clockchip; + int dev_clocks; + int dev_clock[CONF_MAXCLOCKS]; + int dev_chipid; + int dev_chiprev; + int dev_irq; + int dev_screen; + XF86OptionPtr dev_option_lst; + char *dev_comment; +} +XF86ConfDeviceRec, *XF86ConfDevicePtr; + +typedef struct +{ + GenericListRec list; + char *mode_name; +} +XF86ModeRec, *XF86ModePtr; + +typedef struct +{ + GenericListRec list; + int disp_frameX0; + int disp_frameY0; + int disp_virtualX; + int disp_virtualY; + int disp_depth; + int disp_bpp; + char *disp_visual; + parser_rgb disp_weight; + parser_rgb disp_black; + parser_rgb disp_white; + XF86ModePtr disp_mode_lst; + XF86OptionPtr disp_option_lst; + char *disp_comment; +} +XF86ConfDisplayRec, *XF86ConfDisplayPtr; + +typedef struct +{ + XF86OptionPtr flg_option_lst; + char *flg_comment; +} +XF86ConfFlagsRec, *XF86ConfFlagsPtr; + +typedef struct +{ + GenericListRec list; + char *al_adaptor_str; + XF86ConfVideoAdaptorPtr al_adaptor; +} +XF86ConfAdaptorLinkRec, *XF86ConfAdaptorLinkPtr; + +typedef struct +{ + GenericListRec list; + char *scrn_identifier; + char *scrn_obso_driver; + int scrn_defaultdepth; + int scrn_defaultbpp; + int scrn_defaultfbbpp; + char *scrn_monitor_str; + XF86ConfMonitorPtr scrn_monitor; + char *scrn_device_str; + XF86ConfDevicePtr scrn_device; + XF86ConfAdaptorLinkPtr scrn_adaptor_lst; + XF86ConfDisplayPtr scrn_display_lst; + XF86OptionPtr scrn_option_lst; + char *scrn_comment; +} +XF86ConfScreenRec, *XF86ConfScreenPtr; + +typedef struct +{ + GenericListRec list; + char *inp_identifier; + char *inp_driver; + XF86OptionPtr inp_option_lst; + char *inp_comment; +} +XF86ConfInputRec, *XF86ConfInputPtr; + +typedef struct +{ + GenericListRec list; + XF86ConfInputPtr iref_inputdev; + char *iref_inputdev_str; + XF86OptionPtr iref_option_lst; +} +XF86ConfInputrefRec, *XF86ConfInputrefPtr; + +/* Values for adj_where */ +#define CONF_ADJ_OBSOLETE -1 +#define CONF_ADJ_ABSOLUTE 0 +#define CONF_ADJ_RIGHTOF 1 +#define CONF_ADJ_LEFTOF 2 +#define CONF_ADJ_ABOVE 3 +#define CONF_ADJ_BELOW 4 +#define CONF_ADJ_RELATIVE 5 + +typedef struct +{ + GenericListRec list; + int adj_scrnum; + XF86ConfScreenPtr adj_screen; + char *adj_screen_str; + XF86ConfScreenPtr adj_top; + char *adj_top_str; + XF86ConfScreenPtr adj_bottom; + char *adj_bottom_str; + XF86ConfScreenPtr adj_left; + char *adj_left_str; + XF86ConfScreenPtr adj_right; + char *adj_right_str; + int adj_where; + int adj_x; + int adj_y; + char *adj_refscreen; +} +XF86ConfAdjacencyRec, *XF86ConfAdjacencyPtr; + +typedef struct +{ + GenericListRec list; + char *inactive_device_str; + XF86ConfDevicePtr inactive_device; +} +XF86ConfInactiveRec, *XF86ConfInactivePtr; + +typedef struct +{ + GenericListRec list; + char *lay_identifier; + XF86ConfAdjacencyPtr lay_adjacency_lst; + XF86ConfInactivePtr lay_inactive_lst; + XF86ConfInputrefPtr lay_input_lst; + XF86OptionPtr lay_option_lst; + char *lay_comment; +} +XF86ConfLayoutRec, *XF86ConfLayoutPtr; + +typedef struct +{ + GenericListRec list; + char *vs_name; + char *vs_identifier; + XF86OptionPtr vs_option_lst; + char *vs_comment; +} +XF86ConfVendSubRec, *XF86ConfVendSubPtr; + +typedef struct +{ + GenericListRec list; + char *vnd_identifier; + XF86OptionPtr vnd_option_lst; + XF86ConfVendSubPtr vnd_sub_lst; + char *vnd_comment; +} +XF86ConfVendorRec, *XF86ConfVendorPtr; + +typedef struct +{ + GenericListRec list; + int buf_count; + int buf_size; + char *buf_flags; + char *buf_comment; +} +XF86ConfBuffersRec, *XF86ConfBuffersPtr; + +typedef struct +{ + char *dri_group_name; + int dri_group; + int dri_mode; + XF86ConfBuffersPtr dri_buffers_lst; + char *dri_comment; +} +XF86ConfDRIRec, *XF86ConfDRIPtr; + +typedef struct +{ + XF86OptionPtr ext_option_lst; + char *extensions_comment; +} +XF86ConfExtensionsRec, *XF86ConfExtensionsPtr; + +typedef struct +{ + XF86ConfFilesPtr conf_files; + XF86ConfModulePtr conf_modules; + XF86ConfFlagsPtr conf_flags; + XF86ConfVideoAdaptorPtr conf_videoadaptor_lst; + XF86ConfModesPtr conf_modes_lst; + XF86ConfMonitorPtr conf_monitor_lst; + XF86ConfDevicePtr conf_device_lst; + XF86ConfScreenPtr conf_screen_lst; + XF86ConfInputPtr conf_input_lst; + XF86ConfLayoutPtr conf_layout_lst; + XF86ConfVendorPtr conf_vendor_lst; + XF86ConfDRIPtr conf_dri; + XF86ConfExtensionsPtr conf_extensions; + char *conf_comment; +} +XF86ConfigRec, *XF86ConfigPtr; + +typedef struct +{ + int token; /* id of the token */ + char *name; /* pointer to the LOWERCASED name */ +} +xf86ConfigSymTabRec, *xf86ConfigSymTabPtr; + +/* + * prototypes for public functions + */ +extern const char *xf86openConfigFile (const char *, const char *, + const char *); +extern void xf86setBuiltinConfig(const char *config[]); +extern XF86ConfigPtr xf86readConfigFile (void); +extern void xf86closeConfigFile (void); +extern void xf86freeConfig (XF86ConfigPtr p); +extern int xf86writeConfigFile (const char *, XF86ConfigPtr); +XF86ConfDevicePtr xf86findDevice(const char *ident, XF86ConfDevicePtr p); +XF86ConfLayoutPtr xf86findLayout(const char *name, XF86ConfLayoutPtr list); +XF86ConfMonitorPtr xf86findMonitor(const char *ident, XF86ConfMonitorPtr p); +XF86ConfModesPtr xf86findModes(const char *ident, XF86ConfModesPtr p); +XF86ConfModeLinePtr xf86findModeLine(const char *ident, XF86ConfModeLinePtr p); +XF86ConfScreenPtr xf86findScreen(const char *ident, XF86ConfScreenPtr p); +XF86ConfInputPtr xf86findInput(const char *ident, XF86ConfInputPtr p); +XF86ConfInputPtr xf86findInputByDriver(const char *driver, XF86ConfInputPtr p); +XF86ConfVendorPtr xf86findVendor(const char *name, XF86ConfVendorPtr list); +XF86ConfVideoAdaptorPtr xf86findVideoAdaptor(const char *ident, + XF86ConfVideoAdaptorPtr p); + +GenericListPtr xf86addListItem(GenericListPtr head, GenericListPtr c_new); +int xf86itemNotSublist(GenericListPtr list_1, GenericListPtr list_2); + +int xf86pathIsAbsolute(const char *path); +int xf86pathIsSafe(const char *path); +char *xf86addComment(char *cur, char *add); + +#endif /* _xf86Parser_h_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Pci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Pci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Pci.h (revision 51223) @@ -0,0 +1,802 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Pci.h,v 1.39 2003/08/24 17:37:05 dawes Exp $ */ +/* + * Copyright 1998 by Concurrent Computer Corporation + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Concurrent Computer + * Corporation not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Concurrent Computer Corporation makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * Copyright 1998 by Metro Link Incorporated + * + * Permission to use, copy, modify, distribute, and sell this software + * and its documentation for any purpose is hereby granted without fee, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of Metro Link + * Incorporated not be used in advertising or publicity pertaining to + * distribution of the software without specific, written prior + * permission. Metro Link Incorporated makes no representations + * about the suitability of this software for any purpose. It is + * provided "as is" without express or implied warranty. + * + * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + * This file is derived in part from the original xf86_PCI.h that included + * following copyright message: + * + * Copyright 1995 by Robin Cutshaw + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +/* + * This file contains just the public interface to the PCI code. + * Drivers should use this file rather than Pci.h. + */ + +#ifndef _XF86PCI_H +#define _XF86PCI_H 1 +#include +#include +#include "misc.h" + +#define PCI_NOT_FOUND 0xFFFFFFFFU + +/* + * PCI cfg space definitions (e.g. stuff right out of the PCI spec) + */ + +/* Device identification register */ +#define PCI_ID_REG 0x00 + +/* Command and status register */ +#define PCI_CMD_STAT_REG 0x04 +#define PCI_CMD_BASE_REG 0x10 +#define PCI_CMD_BIOS_REG 0x30 +#define PCI_CMD_MASK 0xffff +#define PCI_CMD_IO_ENABLE 0x01 +#define PCI_CMD_MEM_ENABLE 0x02 +#define PCI_CMD_MASTER_ENABLE 0x04 +#define PCI_CMD_SPECIAL_ENABLE 0x08 +#define PCI_CMD_INVALIDATE_ENABLE 0x10 +#define PCI_CMD_PALETTE_ENABLE 0x20 +#define PCI_CMD_PARITY_ENABLE 0x40 +#define PCI_CMD_STEPPING_ENABLE 0x80 +#define PCI_CMD_SERR_ENABLE 0x100 +#define PCI_CMD_BACKTOBACK_ENABLE 0x200 +#define PCI_CMD_BIOS_ENABLE 0x01 + +/* base class */ +#define PCI_CLASS_REG 0x08 +#define PCI_CLASS_MASK 0xff000000 +#define PCI_CLASS_SHIFT 24 +#define PCI_CLASS_EXTRACT(x) \ + (((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT) + +/* base class values */ +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_COMMUNICATIONS 0x07 +#define PCI_CLASS_SYSPERIPH 0x08 +#define PCI_CLASS_INPUT 0x09 +#define PCI_CLASS_DOCKING 0x0a +#define PCI_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_SERIALBUS 0x0c +#define PCI_CLASS_WIRELESS 0x0d +#define PCI_CLASS_I2O 0x0e +#define PCI_CLASS_SATELLITE 0x0f +#define PCI_CLASS_CRYPT 0x10 +#define PCI_CLASS_DATA_ACQUISTION 0x11 +#define PCI_CLASS_UNDEFINED 0xff + +/* sub class */ +#define PCI_SUBCLASS_MASK 0x00ff0000 +#define PCI_SUBCLASS_SHIFT 16 +#define PCI_SUBCLASS_EXTRACT(x) \ + (((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT) + +/* Sub class values */ +/* 0x00 prehistoric subclasses */ +#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 + +/* 0x01 mass storage subclasses */ +#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 +#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 + +/* 0x02 network subclasses */ +#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 +#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 +#define PCI_SUBCLASS_NETWORK_FDDI 0x02 +#define PCI_SUBCLASS_NETWORK_MISC 0x80 + +/* 0x03 display subclasses */ +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 + +/* 0x04 multimedia subclasses */ +#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 +#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 +#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 + +/* 0x05 memory subclasses */ +#define PCI_SUBCLASS_MEMORY_RAM 0x00 +#define PCI_SUBCLASS_MEMORY_FLASH 0x01 +#define PCI_SUBCLASS_MEMORY_MISC 0x80 + +/* 0x06 bridge subclasses */ +#define PCI_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_SUBCLASS_BRIDGE_MC 0x03 +#define PCI_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 +#define PCI_SUBCLASS_BRIDGE_MISC 0x80 +#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01 + +/* 0x07 communications controller subclasses */ +#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 +#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 +#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02 +#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 +#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 + +/* 0x08 generic system peripherals subclasses */ +#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00 +#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01 +#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02 +#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03 +#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04 +#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80 + +/* 0x09 input device subclasses */ +#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 +#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 +#define PCI_SUBCLASS_INPUT_MOUSE 0x02 +#define PCI_SUBCLASS_INPUT_SCANNER 0x03 +#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 +#define PCI_SUBCLASS_INPUT_MISC 0x80 + +/* 0x0a docking station subclasses */ +#define PCI_SUBCLASS_DOCKING_GENERIC 0x00 +#define PCI_SUBCLASS_DOCKING_MISC 0x80 + +/* 0x0b processor subclasses */ +#define PCI_SUBCLASS_PROCESSOR_386 0x00 +#define PCI_SUBCLASS_PROCESSOR_486 0x01 +#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 +#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 +#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 +#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 +#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 + +/* 0x0c serial bus controller subclasses */ +#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00 +#define PCI_SUBCLASS_SERIAL_ACCESS 0x01 +#define PCI_SUBCLASS_SERIAL_SSA 0x02 +#define PCI_SUBCLASS_SERIAL_USB 0x03 +#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04 +#define PCI_SUBCLASS_SERIAL_SMBUS 0x05 + +/* 0x0d wireless controller subclasses */ +#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 +#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01 +#define PCI_SUBCLASS_WIRELESS_RF 0x02 +#define PCI_SUBCLASS_WIRELESS_MISC 0x80 + +/* 0x0e intelligent I/O controller subclasses */ +#define PCI_SUBCLASS_I2O_I2O 0x00 + +/* 0x0f satellite communications controller subclasses */ +#define PCI_SUBCLASS_SATELLITE_TV 0x01 +#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02 +#define PCI_SUBCLASS_SATELLITE_VOICE 0x03 +#define PCI_SUBCLASS_SATELLITE_DATA 0x04 + +/* 0x10 encryption/decryption controller subclasses */ +#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00 +#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10 +#define PCI_SUBCLASS_CRYPT_MISC 0x80 + +/* 0x11 data acquisition and signal processing controller subclasses */ +#define PCI_SUBCLASS_DATAACQ_DPIO 0x00 +#define PCI_SUBCLASS_DATAACQ_MISC 0x80 + + +/* Header */ +#define PCI_HEADER_MISC 0x0c +#define PCI_HEADER_MULTIFUNCTION 0x00800000 + +/* Interrupt configration register */ +#define PCI_INTERRUPT_REG 0x3c +#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 +#define PCI_INTERRUPT_PIN_EXTRACT(x) \ + ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) +#define PCI_INTERRUPT_PIN_NONE 0x00 +#define PCI_INTERRUPT_PIN_A 0x01 +#define PCI_INTERRUPT_PIN_B 0x02 +#define PCI_INTERRUPT_PIN_C 0x03 +#define PCI_INTERRUPT_PIN_D 0x04 + +#define PCI_INTERRUPT_LINE_MASK 0x000000ff +#define PCI_INTERRUPT_LINE_EXTRACT(x) \ + ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) +#define PCI_INTERRUPT_LINE_INSERT(x,v) \ + (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) + +/* Base registers */ +#define PCI_MAP_REG_START 0x10 +#define PCI_MAP_REG_END 0x28 +#define PCI_MAP_ROM_REG 0x30 + +#define PCI_MAP_MEMORY 0x00000000 +#define PCI_MAP_IO 0x00000001 + +#define PCI_MAP_MEMORY_TYPE 0x00000007 +#define PCI_MAP_IO_TYPE 0x00000003 + +#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 +#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 +#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 +#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 +#define PCI_MAP_MEMORY_CACHABLE 0x00000008 +#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e +#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 + +#define PCI_MAP_IO_ATTR_MASK 0x00000003 + +#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) +#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) + +#define PCI_MAP_IS64BITMEM(b) \ + (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT) + +#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) +#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1)) +#define PCIGETMEMORY64(b) \ + (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) + +#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc + +#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) + +#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 +#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 + +#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) + +/* PCI-PCI bridge mapping registers */ +#define PCI_PCI_BRIDGE_BUS_REG 0x18 +#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 +#define PCI_SECONDARY_BUS_MASK 0x0000ff00 +#define PCI_PRIMARY_BUS_MASK 0x000000ff + +#define PCI_PCI_BRIDGE_IO_REG 0x1c +#define PCI_PCI_BRIDGE_MEM_REG 0x20 +#define PCI_PCI_BRIDGE_PMEM_REG 0x24 + +#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00) +#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00) + +#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000) +#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000) + +#define PCI_PCI_BRIDGE_CONTROL_REG 0x3E +#define PCI_PCI_BRIDGE_PARITY_EN 0x01 +#define PCI_PCI_BRIDGE_SERR_EN 0x02 +#define PCI_PCI_BRIDGE_ISA_EN 0x04 +#define PCI_PCI_BRIDGE_VGA_EN 0x08 +#define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20 +#define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40 +#define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80 +/* header type 2 extensions */ +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 + +#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */ +#define PCI_CB_MEM_BASE_0_REG 0x1c +#define PCI_CB_MEM_LIMIT_0_REG 0x20 +#define PCI_CB_MEM_BASE_1_REG 0x24 +#define PCI_CB_MEM_LIMIT_1_REG 0x28 +#define PCI_CB_IO_BASE_0_REG 0x2c +#define PCI_CB_IO_LIMIT_0_REG 0x30 +#define PCI_CB_IO_BASE_1_REG 0x34 +#define PCI_CB_IO_LIMIT_1_REG 0x38 +#define PCI_CB_BRIDGE_CONTROL_REG 0x3E + +#define PCI_CB_IO_RANGE_MASK ~0x03 +#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK) +#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3) + +/* Subsystem identification register */ +#define PCI_SUBSYSTEM_ID_REG 0x2c + +/* User defined cfg space regs */ +#define PCI_REG_USERCONFIG 0x40 +#define PCI_OPTION_REG 0x40 + +/* + * Typedefs, etc... + */ + +/* Primitive Types */ +typedef unsigned long ADDRESS; /* Memory/PCI address */ +typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */ +typedef unsigned long PCITAG; + +/* + * PCI configuration space + */ +typedef struct pci_cfg_regs { + /* start of official PCI config space header */ + union { /* Offset 0x0 - 0x3 */ + CARD32 device_vendor; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 device; + CARD16 vendor; +#else + CARD16 vendor; + CARD16 device; +#endif + } dv; + } dv_id; + + union { /* Offset 0x4 - 0x8 */ + CARD32 status_command; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 status; + CARD16 command; +#else + CARD16 command; + CARD16 status; +#endif + } sc; + } stat_cmd; + + union { /* Offset 0x8 - 0xb */ + CARD32 class_revision; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 base_class; + CARD8 sub_class; + CARD8 prog_if; + CARD8 rev_id; +#else + CARD8 rev_id; + CARD8 prog_if; + CARD8 sub_class; + CARD8 base_class; +#endif + } cr; + } class_rev; + + union { /* Offset 0xc - 0xf */ + CARD32 bist_header_latency_cache; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 bist; + CARD8 header_type; + CARD8 latency_timer; + CARD8 cache_line_size; +#else + CARD8 cache_line_size; + CARD8 latency_timer; + CARD8 header_type; + CARD8 bist; +#endif + } bhlc; + } bhlc; + union { /* Offset 0x10 - 0x3b */ + struct { /* header type 2 */ + CARD32 cg_rsrvd1; /* 0x10 */ +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 secondary_status; /* 0x16 */ + CARD16 cg_rsrvd2; /* 0x14 */ + + union { + CARD32 cg_bus_reg; + struct { + CARD8 latency_timer; /* 0x1b */ + CARD8 subordinate_bus_number; /* 0x1a */ + CARD8 cardbus_bus_number; /* 0x19 */ + CARD8 primary_bus_number; /* 0x18 */ + } cgbr; + } cgbr; +#else + CARD16 cg_rsrvd2; /* 0x14 */ + CARD16 secondary_status; /* 0x16 */ + + union { + CARD32 cg_bus_reg; + struct { + CARD8 primary_bus_number; /* 0x18 */ + CARD8 cardbus_bus_number; /* 0x19 */ + CARD8 subordinate_bus_number; /* 0x1a */ + CARD8 latency_timer; /* 0x1b */ + } cgbr; + } cgbr; +#endif + CARD32 mem_base0; /* 0x1c */ + CARD32 mem_limit0; /* 0x20 */ + CARD32 mem_base1; /* 0x24 */ + CARD32 mem_limit1; /* 0x28 */ + CARD32 io_base0; /* 0x2c */ + CARD32 io_limit0; /* 0x30 */ + CARD32 io_base1; /* 0x34 */ + CARD32 io_limit1; /* 0x38 */ + } cg; + struct { + union { /* Offset 0x10 - 0x27 */ + struct { /* header type 0 */ + CARD32 dv_base0; + CARD32 dv_base1; + CARD32 dv_base2; + CARD32 dv_base3; + CARD32 dv_base4; + CARD32 dv_base5; + } dv; + struct { /* header type 1 */ + CARD32 bg_rsrvd[2]; +#if X_BYTE_ORDER == X_BIG_ENDIAN + union { + CARD32 pp_bus_reg; + struct { + CARD8 secondary_latency_timer; + CARD8 subordinate_bus_number; + CARD8 secondary_bus_number; + CARD8 primary_bus_number; + } ppbr; + } ppbr; + + CARD16 secondary_status; + CARD8 io_limit; + CARD8 io_base; + + CARD16 mem_limit; + CARD16 mem_base; + + CARD16 prefetch_mem_limit; + CARD16 prefetch_mem_base; +#else + union { + CARD32 pp_bus_reg; + struct { + CARD8 primary_bus_number; + CARD8 secondary_bus_number; + CARD8 subordinate_bus_number; + CARD8 secondary_latency_timer; + } ppbr; + } ppbr; + + CARD8 io_base; + CARD8 io_limit; + CARD16 secondary_status; + + CARD16 mem_base; + CARD16 mem_limit; + + CARD16 prefetch_mem_base; + CARD16 prefetch_mem_limit; +#endif + } bg; + } bc; + union { /* Offset 0x28 - 0x2b */ + CARD32 rsvd1; + CARD32 pftch_umem_base; + CARD32 cardbus_cis_ptr; + } um_c_cis; + union { /* Offset 0x2c - 0x2f */ + CARD32 subsys_card_vendor; + CARD32 pftch_umem_limit; + CARD32 rsvd2; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 subsys_card; + CARD16 subsys_vendor; +#else + CARD16 subsys_vendor; + CARD16 subsys_card; +#endif + } ssys; + } um_ssys_id; + union { /* Offset 0x30 - 0x33 */ + CARD32 baserom; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 io_ulimit; + CARD16 io_ubase; +#else + CARD16 io_ubase; + CARD16 io_ulimit; +#endif + } b_u_io; + } uio_rom; + struct { + CARD32 rsvd3; /* Offset 0x34 - 0x37 */ + CARD32 rsvd4; /* Offset 0x38 - 0x3b */ + } rsvd; + } cd; + } cx; + union { /* Offset 0x3c - 0x3f */ + union { /* header type 0 */ + CARD32 max_min_ipin_iline; + struct { +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD8 max_lat; + CARD8 min_gnt; + CARD8 int_pin; + CARD8 int_line; +#else + CARD8 int_line; + CARD8 int_pin; + CARD8 min_gnt; + CARD8 max_lat; +#endif + } mmii; + } mmii; + struct { /* header type 1 */ +#if X_BYTE_ORDER == X_BIG_ENDIAN + CARD16 bridge_control; /* upper 8 bits reserved */ + CARD8 rsvd2; + CARD8 rsvd1; +#else + CARD8 rsvd1; + CARD8 rsvd2; + CARD16 bridge_control; /* upper 8 bits reserved */ +#endif + } bctrl; + } bm; + union { /* Offset 0x40 - 0xff */ + CARD32 dwords[48]; + CARD8 bytes[192]; + } devspf; +} pciCfgRegs; + +typedef union pci_cfg_spc { + pciCfgRegs regs; + CARD32 dwords[256/sizeof(CARD32)]; + CARD8 bytes[256/sizeof(CARD8)]; +} pciCfgSpc; + +/* + * Data structure returned by xf86scanpci including contents of + * PCI config space header + */ +typedef struct pci_device { + PCITAG tag; + int busnum; + int devnum; + int funcnum; + pciCfgSpc cfgspc; + int basesize[7]; /* number of bits in base addr allocations */ + Bool minBasesize; + pointer businfo; /* pointer to secondary's bus info structure */ + Bool fakeDevice; /* Device added by system chipset support */ +} pciDevice, *pciConfigPtr; + +typedef enum { + PCI_MEM, + PCI_MEM_SIZE, + PCI_MEM_SPARSE_BASE, + PCI_MEM_SPARSE_MASK, + PCI_IO, + PCI_IO_SIZE, + PCI_IO_SPARSE_BASE, + PCI_IO_SPARSE_MASK +} PciAddrType; + +#define pci_device_vendor cfgspc.regs.dv_id.device_vendor +#define pci_vendor cfgspc.regs.dv_id.dv.vendor +#define pci_device cfgspc.regs.dv_id.dv.device +#define pci_status_command cfgspc.regs.stat_cmd.status_command +#define pci_command cfgspc.regs.stat_cmd.sc.command +#define pci_status cfgspc.regs.stat_cmd.sc.status +#define pci_class_revision cfgspc.regs.class_rev.class_revision +#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id +#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if +#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class +#define pci_base_class cfgspc.regs.class_rev.cr.base_class +#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache +#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size +#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer +#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type +#define pci_bist cfgspc.regs.bhlc.bhlc.bist +#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status +#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg +#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number +#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number +#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number +#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer +#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0 +#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0 +#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1 +#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1 +#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0 +#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0 +#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1 +#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1 +#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0 +#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1 +#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2 +#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3 +#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4 +#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5 +#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr +#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor +#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor +#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card +#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom +#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg +#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number +#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number +#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number +#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer +#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base +#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit +#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status +#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base +#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit +#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base +#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit +#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1 +#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2 +#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base +#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit +#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase +#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit +#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line +#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin +#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt +#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat +#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline +#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control +#define pci_user_config cfgspc.regs.devspf.dwords[0] +#define pci_user_config_0 cfgspc.regs.devspf.bytes[0] +#define pci_user_config_1 cfgspc.regs.devspf.bytes[1] +#define pci_user_config_2 cfgspc.regs.devspf.bytes[2] +#define pci_user_config_3 cfgspc.regs.devspf.bytes[3] + +typedef enum { + PCI_BIOS_PC = 0, + PCI_BIOS_OPEN_FIRMWARE, + PCI_BIOS_HP_PA_RISC, + PCI_BIOS_OTHER +} PciBiosType; + +/* Public PCI access functions */ +void pciInit(void); +PCITAG pciFindFirst(CARD32 id, CARD32 mask); +PCITAG pciFindNext(void); +CARD32 pciReadLong(PCITAG tag, int offset); +CARD16 pciReadWord(PCITAG tag, int offset); +CARD8 pciReadByte(PCITAG tag, int offset); +void pciWriteLong(PCITAG tag, int offset, CARD32 val); +void pciWriteWord(PCITAG tag, int offset, CARD16 val); +void pciWriteByte(PCITAG tag, int offset, CARD8 val); +void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val); +void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val); +ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr); +ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr); +PCITAG pciTag(int busnum, int devnum, int funcnum); +int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min); +CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg); +pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag, + ADDRESS Base, unsigned long Size); +int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg, + unsigned char *Buf, int Len); +pciConfigPtr *xf86scanpci(int flags); +pciConfigPtr xf86GetPciConfigFromTag(PCITAG Tag); + +extern int pciNumBuses; + +/* Domain access functions. Some of these probably shouldn't be public */ +int xf86GetPciDomain(PCITAG tag); +pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, + ADDRESS Base, unsigned long Size); +IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, + IOADDRESS Base, unsigned long Size); +int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, + unsigned char *Buf); + +typedef enum { + ROM_BASE_PRESET = -2, + ROM_BASE_BIOS, + ROM_BASE_MEM0 = 0, + ROM_BASE_MEM1, + ROM_BASE_MEM2, + ROM_BASE_MEM3, + ROM_BASE_MEM4, + ROM_BASE_MEM5, + ROM_BASE_FIND +} romBaseSource; + +#endif /* _XF86PCI_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciData.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciData.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciData.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86PciData.h,v 1.3 2003/08/24 17:37:10 dawes Exp $ */ + +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_DATA_H_ +#define PCI_DATA_H_ + +#define NOVENDOR 0xFFFF +#define NODEVICE 0xFFFF +#define NOSUBSYS 0xFFFF + +typedef Bool (*ScanPciSetupProcPtr)(void); +typedef void (*ScanPciCloseProcPtr)(void); +typedef int (*ScanPciFindByDeviceProcPtr)( + unsigned short vendor, unsigned short device, + unsigned short svendor, unsigned short subsys, + const char **vname, const char **dname, + const char **svname, const char **sname); +typedef int (*ScanPciFindBySubsysProcPtr)( + unsigned short svendor, unsigned short subsys, + const char **svname, const char **sname); + +/* + * Whoever loads this module needs to define these and initialise them + * after loading. + */ +extern ScanPciSetupProcPtr xf86SetupPciIds; +extern ScanPciCloseProcPtr xf86ClosePciIds; +extern ScanPciFindByDeviceProcPtr xf86FindPciNamesByDevice; +extern ScanPciFindBySubsysProcPtr xf86FindPciNamesBySubsys; + +Bool ScanPciSetupPciIds(void); +void ScanPciClosePciIds(void); +int ScanPciFindPciNamesByDevice(unsigned short vendor, unsigned short device, + unsigned short svendor, unsigned short subsys, + const char **vname, const char **dname, + const char **svname, const char **sname); +int ScanPciFindPciNamesBySubsys(unsigned short svendor, unsigned short subsys, + const char **svname, const char **sname); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciIds.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciIds.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciIds.h (revision 51223) @@ -0,0 +1,124831 @@ +/* $XdotOrg$ */ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0071[] = "Nebula Electronics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0095[] = "Silicon Image, Inc. (Wrong ID)"; +static const char pci_device_0095_0680[] = "Ultra ATA/133 IDE RAID CONTROLLER CARD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00a7[] = "Teles AG (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_018a[] = "LevelOne"; +static const char pci_device_018a_0106[] = "FPC-0106TX misprogrammed [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_021b[] = "Compaq Computer Corporation"; +static const char pci_device_021b_8139[] = "HNE-300 (RealTek RTL8139c) [iPaq Networking]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0270[] = "Hauppauge computer works Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0291[] = "Davicom Semiconductor, Inc."; +static const char pci_device_0291_8212[] = "DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_02ac[] = "SpeedStream"; +static const char pci_device_02ac_1012[] = "1012 PCMCIA 10/100 Ethernet Card [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0357[] = "TTTech AG"; +static const char pci_device_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0432[] = "SCM Microsystems, Inc."; +static const char pci_device_0432_0001[] = "Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_045e[] = "Microsoft"; +static const char pci_device_045e_006e[] = "MN-510 802.11b wireless USB paddle"; +static const char pci_device_045e_00c2[] = "MN-710 wireless USB paddle"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_04cf[] = "Myson Century, Inc"; +static const char pci_device_04cf_8818[] = "CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_050d[] = "Belkin"; +static const char pci_device_050d_7050[] = "F5D7050 802.11g Wireless USB Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05e3[] = "CyberDoor"; +static const char pci_device_05e3_0701[] = "CBD516"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_066f[] = "Sigmatel Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +static const char pci_device_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_067b[] = "Prolific Technology, Inc."; +static const char pci_device_067b_3507[] = "PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0721[] = "Sapphire, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_07e2[] = "ELMEG Communication Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b49[] = "ASCII Corporation"; +static const char pci_device_0b49_064f[] = "Trance Vibrator"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0046[] = "Smart Array 64xx"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409a[] = "Smart Array 641"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409b[] = "Smart Array 642"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409c[] = "Smart Array 6400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409d[] = "Smart Array 6400 EM"; +#endif +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_005a[] = "Remote Insight II board - Lights-Out"; +static const char pci_device_0e11_007c[] = "NC7770 1000BaseTX"; +static const char pci_device_0e11_007d[] = "NC6770 1000BaseTX"; +static const char pci_device_0e11_0085[] = "NC7780 1000BaseTX"; +static const char pci_device_0e11_00b1[] = "Remote Insight II board - PCI device"; +static const char pci_device_0e11_00bb[] = "NC7760"; +static const char pci_device_0e11_00ca[] = "NC7771"; +static const char pci_device_0e11_00cb[] = "NC7781"; +static const char pci_device_0e11_00cf[] = "NC7772"; +static const char pci_device_0e11_00d0[] = "NC7782"; +static const char pci_device_0e11_00d1[] = "NC7783"; +static const char pci_device_0e11_00e3[] = "NC7761"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_4030[] = "SMART-2/P"; +static const char pci_device_0e11_4031[] = "SMART-2SL"; +static const char pci_device_0e11_4032[] = "Smart Array 3200"; +static const char pci_device_0e11_4033[] = "Smart Array 3100ES"; +static const char pci_device_0e11_4034[] = "Smart Array 221"; +static const char pci_device_0e11_4040[] = "Integrated Array"; +static const char pci_device_0e11_4048[] = "Compaq Raid LC2"; +static const char pci_device_0e11_4050[] = "Smart Array 4200"; +static const char pci_device_0e11_4051[] = "Smart Array 4250ES"; +static const char pci_device_0e11_4058[] = "Smart Array 431"; +static const char pci_device_0e11_4070[] = "Smart Array 5300"; +static const char pci_device_0e11_4080[] = "Smart Array 5i"; +static const char pci_device_0e11_4082[] = "Smart Array 532"; +static const char pci_device_0e11_4083[] = "Smart Array 5312"; +static const char pci_device_0e11_4091[] = "Smart Array 6i"; +static const char pci_device_0e11_409a[] = "Smart Array 641"; +static const char pci_device_0e11_409b[] = "Smart Array 642"; +static const char pci_device_0e11_409c[] = "Smart Array 6400"; +static const char pci_device_0e11_409d[] = "Smart Array 6400 EM"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "FibreChannel HBA Tachyon"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10 T PCI UTP"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent Dual 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae43[] = "Netelligent Integrated 10/100 TX UTP"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Netelligent 10/100 TX Embedded UTP"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2 PCI UTP/Coax"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent 10/100 TX UTP"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4080[] = "Smart Array 5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4082[] = "Smart Array 532"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4083[] = "Smart Array 5312"; +#endif +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_b200[] = "Memory Hot-Plug Controller"; +static const char pci_device_0e11_b203[] = "Integrated Lights Out Controller"; +static const char pci_device_0e11_b204[] = "Integrated Lights Out Processor"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "LSI53C810AE PCI to SCSI I/O Processor"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0003_1000_1000[] = "LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide)"; +#endif +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0006_1000_1000[] = "LSI53C860E PCI to Ultra SCSI I/O Processor"; +#endif +static const char pci_device_1000_000a[] = "53c1510"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_1000_1000[] = "LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode)"; +#endif +static const char pci_device_1000_000b[] = "53C896/897"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_0e11_6004[] = "EOB003 Series SCSI host adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1000[] = "LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1010[] = "LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1020[] = "LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_13e9_1000[] = "6221L-4U"; +#endif +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1010[] = "LSI8951U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1020[] = "LSI8952U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3906[] = "DC-390U2B SCSI adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1000[] = "LSI53C876/E PCI to Dual Channel SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1010[] = "LSI22801 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1020[] = "LSI22802 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F/U Ultra Wide SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1050[] = "CT7 mainboard"; +#endif +static const char pci_device_1000_0010[] = "53C1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "RAID LC2 Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_1000_1000[] = "53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode)"; +#endif +static const char pci_device_1000_0012[] = "53c895a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0012_1000_1000[] = "LSI53C895A PCI to Ultra2 SCSI Controller"; +#endif +static const char pci_device_1000_0013[] = "53c875a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0013_1000_1000[] = "LSI53C875A PCI to Ultra SCSI Controller"; +#endif +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1000_1000[] = "LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1000[] = "LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1010[] = "Asus TR-DLS onboard 53C1010-66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_124b_1070[] = "PMC-USCSI3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1300[] = "P017 mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1310[] = "P017 mezzanine (64-bit PMC)"; +#endif +static const char pci_device_1000_0030[] = "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_0e11_00da[] = "ProLiant ML 350"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0123[] = "PowerEdge 2600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_014a[] = "PowerEdge 1750"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_016c[] = "PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_124b_1170[] = "PMC-USCSI320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1734_1052[] = "Primergy RX300 S2"; +#endif +static const char pci_device_1000_0031[] = "53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0032[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0032_1000_1000[] = "LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller"; +#endif +static const char pci_device_1000_0033[] = "1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0040[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0033[] = "MegaRAID SCSI 320-2XR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0066[] = "MegaRAID SCSI 320-2XRWS"; +#endif +static const char pci_device_1000_0041[] = "53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0050[] = "SAS1064 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0054[] = "SAS1068 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0056[] = "SAS1064E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_0058[] = "SAS1068E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005a[] = "SAS1066E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005c[] = "SAS1064A PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_005e[] = "SAS1066 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0060[] = "SAS1078 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0062_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#endif +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0407[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0530[] = "MegaRAID 530 SCSI 320-0X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0531[] = "MegaRAID 531 SCSI 320-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0532[] = "MegaRAID 532 SCSI 320-2X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0530[] = "MegaRAID Intel RAID Controller SRCZCRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0532[] = "MegaRAID Intel RAID Controller SRCU42X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0408[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0001[] = "MegaRAID SCSI 320-1E RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0002[] = "MegaRAID SCSI 320-2E RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1025_004d[] = "MegaRAID ACER ROMB-2E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0001[] = "PowerEdge RAID Controller PERC4e/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0002[] = "PowerEdge RAID Controller PERC4e/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1734_1065[] = "FSC MegaRAID PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_8086_0002[] = "MegaRAID Intel RAID Controller SRCU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0409[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3004[] = "MegaRAID SATA 300-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3008[] = "MegaRAID SATA 300-8X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3008[] = "MegaRAID RAID Controller SRCS28X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3431[] = "MegaRAID RAID Controller Alief SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3499[] = "MegaRAID RAID Controller Harwich SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0621[] = "FC909 Fibre Channel Adapter"; +static const char pci_device_1000_0622[] = "FC929 Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0622_1000_1020[] = "44929 O Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919 Fibre Channel Adapter"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0626_1000_1010[] = "7202-XP-LC Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X Fibre Channel Adapter"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0640[] = "FC949X Fibre Channel Adapter"; +static const char pci_device_1000_0642[] = "FC939X Fibre Channel Adapter"; +static const char pci_device_1000_0646[] = "FC949ES Fibre Channel Adapter"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0804[] = "SA2010"; +static const char pci_device_1000_0805[] = "SA2010ZC"; +static const char pci_device_1000_0806[] = "SA2020"; +static const char pci_device_1000_0807[] = "SA2020ZC"; +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0518[] = "MegaRAID 518 SCSI 320-2 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0520[] = "MegaRAID 520 SCSI 320-1 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0522[] = "MegaRAID 522 i4 133 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0523[] = "MegaRAID SATA 150-6 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_4523[] = "MegaRAID SATA 150-4 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_a520[] = "MegaRAID ZCR SCSI 320-0 Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "MegaRAID 518 DELL PERC 4/DC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "MegaRAID 520 DELL PERC 4/SC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0520[] = "MegaRAIDRAID Controller SRCU41L"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0523[] = "MegaRAID RAID Controller SRCS16"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_3150[] = "M24 1P [Radeon Mobility X600]"; +static const char pci_device_1002_3152[] = "M22 [Radeon Mobility X300]"; +static const char pci_device_1002_3154[] = "M24 1T [FireGL M24 GL]"; +static const char pci_device_1002_3e50[] = "RV380 0x3e50 [Radeon X600]"; +static const char pci_device_1002_3e54[] = "RV380 0x3e54 [FireGL V3200]"; +static const char pci_device_1002_3e70[] = "RV380 [Radeon X600] Secondary"; +static const char pci_device_1002_4136[] = "Radeon IGP 320 M"; +static const char pci_device_1002_4137[] = "Radeon IGP330/340/350"; +static const char pci_device_1002_4144[] = "R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "R300 AE [Radeon 9700 Pro]"; +static const char pci_device_1002_4146[] = "R300 AF [Radeon 9700 Pro]"; +static const char pci_device_1002_4147[] = "R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4148[] = "R350 AH [Radeon 9800]"; +static const char pci_device_1002_4149[] = "R350 AI [Radeon 9800]"; +static const char pci_device_1002_414a[] = "R350 AJ [Radeon 9800]"; +static const char pci_device_1002_414b[] = "R350 AK [Fire GL X2]"; +static const char pci_device_1002_4150[] = "RV350 AP [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0002[] = "R9600 Pro primary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_4722[] = "All-in-Wonder 2006 AGP Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1458_4024[] = "Giga-Byte GV-R96128D Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2064[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2066[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c19[] = "Sapphire Atlantis Radeon 9600 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c29[] = "GC-R9600PRO Primary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_17ee_2002[] = "Radeon 9600 256Mb Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_18bc_0101[] = "GC-R9600PRO Primary"; +#endif +static const char pci_device_1002_4151[] = "RV350 AQ [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4151_1043_c004[] = "A9600SE"; +#endif +static const char pci_device_1002_4152[] = "RV350 AR [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_0002[] = "Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_4772[] = "All-in-Wonder 9600 XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c002[] = "Radeon 9600 XT TVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c01a[] = "A9600XT/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_174b_7c29[] = "Sapphire Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1787_4002[] = "Radeon 9600 XT"; +#endif +static const char pci_device_1002_4153[] = "RV350 AS [Radeon 9550]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4153_1462_932c[] = "865PE Neo2-V (MS-6788) mainboard"; +#endif +static const char pci_device_1002_4154[] = "RV350 AT [Fire GL T2]"; +static const char pci_device_1002_4155[] = "RV350 AU [Fire GL T2]"; +static const char pci_device_1002_4156[] = "RV350 AV [Fire GL T2]"; +static const char pci_device_1002_4157[] = "RV350 AW [Fire GL T2]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4164[] = "R300 AD [Radeon 9500 Pro] (Secondary)"; +static const char pci_device_1002_4165[] = "R300 AE [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4166[] = "R300 AF [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4168[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4170[] = "RV350 AP [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_4723[] = "All-in-Wonder 2006 AGP Edition (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1458_4025[] = "Giga-Byte GV-R96128D Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_148c_2067[] = "PowerColor R96A-C3N (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_174b_7c28[] = "GC-R9600PRO Secondary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_17ee_2003[] = "Radeon 9600 256Mb Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_18bc_0100[] = "GC-R9600PRO Secondary"; +#endif +static const char pci_device_1002_4171[] = "RV350 AQ [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4171_1043_c005[] = "A9600SE (Secondary)"; +#endif +static const char pci_device_1002_4172[] = "RV350 AR [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_0003[] = "Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_4773[] = "All-in-Wonder 9600 XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c003[] = "A9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c01b[] = "A9600XT/TD (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_174b_7c28[] = "Sapphire Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1787_4003[] = "Radeon 9600 XT (Secondary)"; +#endif +static const char pci_device_1002_4173[] = "RV350 ? [Radeon 9550] (Secondary)"; +static const char pci_device_1002_4237[] = "Radeon 7000 IGP"; +static const char pci_device_1002_4242[] = "R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4243[] = "R200 BC [Radeon All in Wonder 8500]"; +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_1002_4336[] = "Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_103c_0024[] = "Pavilion ze4400 builtin Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_161f_2029[] = "eMachines M5312 builtin Video"; +#endif +static const char pci_device_1002_4337[] = "Radeon IGP 330M/340M/350M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_1014_053a[] = "ThinkPad R40e (2684-HVG) builtin VGA controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_103c_0850[] = "Radeon IGP 345M"; +#endif +static const char pci_device_1002_4341[] = "IXP150 AC'97 Audio Controller"; +static const char pci_device_1002_4345[] = "EHCI USB Controller"; +static const char pci_device_1002_4347[] = "OHCI USB Controller #1"; +static const char pci_device_1002_4348[] = "OHCI USB Controller #2"; +static const char pci_device_1002_4349[] = "ATI Dual Channel Bus Master PCI IDE Controller"; +static const char pci_device_1002_434d[] = "IXP AC'97 Modem"; +static const char pci_device_1002_4353[] = "ATI SMBus"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4363[] = "ATI SMBus"; +static const char pci_device_1002_436e[] = "ATI 436E Serial ATA Controller"; +static const char pci_device_1002_4370[] = "IXP SB400 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4371[] = "IXP SB400 PCI-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4371_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4372[] = "IXP SB400 SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4373[] = "IXP SB400 USB2 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4374[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4374_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4375[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4376[] = "Standard Dual Channel PCI IDE Controller ATI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4377[] = "IXP SB400 PCI-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4378[] = "ATI SB400 - AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4379[] = "ATI 4379 Serial ATA Controller"; +static const char pci_device_1002_437a[] = "ATI 437A Serial ATA Controller"; +static const char pci_device_1002_4437[] = "Radeon Mobility 7000 IGP"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1734_007a[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0084[] = "Rage 3D Pro AGP 2x XPERT 98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon RV250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon RV250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon RV250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "RV250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "RV250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "RV250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "RV250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "RV250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "RV250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "RV250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "RV250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon RV250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon RV250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4a48[] = "R420 JH [Radeon X800]"; +static const char pci_device_1002_4a49[] = "R420 JI [Radeon X800PRO]"; +static const char pci_device_1002_4a4a[] = "R420 JJ [Radeon X800SE]"; +static const char pci_device_1002_4a4b[] = "R420 JK [Radeon X800]"; +static const char pci_device_1002_4a4c[] = "R420 JL [Radeon X800]"; +static const char pci_device_1002_4a4d[] = "R420 JM [FireGL X3]"; +static const char pci_device_1002_4a4e[] = "M18 JN [Radeon Mobility 9800]"; +static const char pci_device_1002_4a50[] = "R420 JP [Radeon X800XT]"; +static const char pci_device_1002_4a70[] = "R420 [X800XT-PE] (Secondary)"; +static const char pci_device_1002_4b49[] = "R480 [Radeon X850XT]"; +static const char pci_device_1002_4b4b[] = "R480 [Radeon X850Pro]"; +static const char pci_device_1002_4b4c[] = "R481 [Radeon X850XT-PE]"; +static const char pci_device_1002_4b69[] = "R480 [Radeon X850XT secondary]"; +static const char pci_device_1002_4b6b[] = "R480 [Radeon X850Pro] (Secondary)"; +static const char pci_device_1002_4b6c[] = "R481 [Radeon X850XT-PE] Secondary"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e7[] = "Rage LT Pro (Compaq Presario 5240)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c46_1028_00b1[] = "Latitude C600"; +#endif +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b160[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m/A21m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00aa[] = "Latitude CPt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00bb[] = "Latitude CPx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_10e1_10cf[] = "Fujitsu Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1179_ff00[] = "Satellite 1715XCDS laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_13bd_1019[] = "PC-AR10"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c52_1033_8112[] = "Versa Note VXi"; +#endif +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_0e11_b111[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1509_1930[] = "Medion MD9703"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 Lf [FireGL 9000]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c6e[] = "Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_515e[] = "Radeon ES1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_5965[] = "Radeon ES1000"; +#endif +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1002_0002[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1681_0002[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro]"; +#endif +static const char pci_device_1002_4e46[] = "RV350 NF [Radeon 9600]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e48[] = "Radeon R350 [Radeon 9800 Pro]"; +static const char pci_device_1002_4e49[] = "Radeon R350 [Radeon 9800]"; +static const char pci_device_1002_4e4a[] = "RV350 NJ [Radeon 9800 XT]"; +static const char pci_device_1002_4e4b[] = "R350 NK [Fire GL X2]"; +static const char pci_device_1002_4e50[] = "RV350 [Mobility Radeon 9600 M10]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1734_1055[] = "Amilo M1420W"; +#endif +static const char pci_device_1002_4e51[] = "M10 NQ [Radeon Mobility 9600]"; +static const char pci_device_1002_4e52[] = "RV350 [Mobility Radeon 9600 M10]"; +static const char pci_device_1002_4e53[] = "M10 NS [Radeon Mobility 9600]"; +static const char pci_device_1002_4e54[] = "M10 NT [FireGL Mobility T2]"; +static const char pci_device_1002_4e56[] = "M11 NV [FireGL Mobility T2e]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9500 Pro] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1002_0003[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1681_0003[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary)"; +#endif +static const char pci_device_1002_4e66[] = "RV350 NF [Radeon 9600] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_4e68[] = "Radeon R350 [Radeon 9800 Pro] (Secondary)"; +static const char pci_device_1002_4e69[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4e6a[] = "RV350 NJ [Radeon 9800 XT] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e6a_1002_4e71[] = "ATI Technologies Inc M10 NQ [Radeon Mobility 9600]"; +#endif +static const char pci_device_1002_4e71[] = "M10 NQ [Radeon Mobility 9600] (secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1681_0010[] = "Radeon 8500 [3D Prophet 8500 128Mb]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5154[] = "R200 QT [Radeon 8500]"; +static const char pci_device_1002_5155[] = "R200 QU [Radeon 9100]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_103a[] = "Dell Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7146[] = "RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_029a[] = "Remote Supervisor Adapter II (RSA2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_02c8[] = "IBM eServer xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7c28[] = "Sapphire Radeon VE 7000 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_515e[] = "ES1000"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5346_1002_0048[] = "RAGE 128 16MB VGA TVOUT AMC PAL"; +#endif +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5460[] = "M22 [Radeon Mobility M300]"; +static const char pci_device_1002_5462[] = "M24 [Radeon Mobility X600]"; +static const char pci_device_1002_5464[] = "M22 [FireGL GL]"; +static const char pci_device_1002_5548[] = "R423 UH [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5549[] = "R423 UI [Radeon X800PRO (PCIE)]"; +static const char pci_device_1002_554a[] = "R423 UJ [Radeon X800LE (PCIE)]"; +static const char pci_device_1002_554b[] = "R423 UK [Radeon X800SE (PCIE)]"; +static const char pci_device_1002_554d[] = "R430 [Radeon X800 XL] (PCIe)"; +static const char pci_device_1002_554f[] = "R430 [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5550[] = "R423 [Fire GL V7100]"; +static const char pci_device_1002_5551[] = "R423 UQ [FireGL V7200 (PCIE)]"; +static const char pci_device_1002_5552[] = "R423 UR [FireGL V5100 (PCIE)]"; +static const char pci_device_1002_5554[] = "R423 UT [FireGL V7100 (PCIE)]"; +static const char pci_device_1002_556b[] = "Radeon R423 UK (PCIE) [X800 SE] (Secondary)"; +static const char pci_device_1002_556d[] = "R430 [Radeon X800 XL] (PCIe) Secondary"; +static const char pci_device_1002_556f[] = "R430 [Radeon X800 (PCIE) Secondary]"; +static const char pci_device_1002_564a[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564b[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_5652[] = "M26 [Radeon Mobility X700]"; +static const char pci_device_1002_5653[] = "Radeon Mobility X700 (PCIE)"; +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_5830[] = "RS300 Host Bridge"; +static const char pci_device_1002_5831[] = "RS300 Host Bridge"; +static const char pci_device_1002_5832[] = "RS300 Host Bridge"; +static const char pci_device_1002_5833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_5834[] = "Radeon 9100 IGP"; +static const char pci_device_1002_5835[] = "RS300M AGP [Radeon Mobility 9100IGP]"; +static const char pci_device_1002_5838[] = "Radeon 9100 IGP AGP Bridge"; +static const char pci_device_1002_5940[] = "RV280 [Radeon 9200 PRO] (Secondary)"; +static const char pci_device_1002_5941[] = "RV280 [Radeon 9200] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_1458_4019[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_174b_7c12[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_17af_200d[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_18bc_0050[] = "GeXcube GC-R9200-C3 (Secondary)"; +#endif +static const char pci_device_1002_5944[] = "RV280 [Radeon 9200 SE (PCI)]"; +static const char pci_device_1002_5950[] = "RS480 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5951[] = "ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge"; +static const char pci_device_1002_5954[] = "RS480 [Radeon Xpress 200G Series]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5954_1002_5954[] = "RV370 [Radeon Xpress 200G Series]"; +#endif +static const char pci_device_1002_5955[] = "ATI Radeon XPRESS 200M 5955 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_1002_5955[] = "RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5960[] = "RV280 [Radeon 9200 PRO]"; +static const char pci_device_1002_5961[] = "RV280 [Radeon 9200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1002_2f72[] = "All-in-Wonder 9200 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1019_4c30[] = "Radeon 9200 VIVO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_12ab_5961[] = "YUAN SMARTVGA Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1458_4018[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_174b_7c13[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_17af_200c[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0050[] = "Radeon 9200 Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0051[] = "GeXcube GC-R9200-C3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0053[] = "Radeon 9200 Game Buster VIVO"; +#endif +static const char pci_device_1002_5962[] = "RV280 [Radeon 9200]"; +static const char pci_device_1002_5964[] = "RV280 [Radeon 9200 SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1043_c006[] = "ASUS Radeon 9200 SE / TD / 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4018[] = "Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_147b_6191[] = "R9200SE-DT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_148c_2073[] = "CN-AG92E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_174b_7c13[] = "Sapphire Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1787_5964[] = "Excalibur 9200SE VIVO 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_17af_2012[] = "Radeon 9200 SE Excalibur"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0170[] = "Sapphire Radeon 9200 SE 128MB Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0173[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5969[] = "ES1000"; +static const char pci_device_1002_5974[] = "RS482 [Radeon Xpress 200]"; +static const char pci_device_1002_5975[] = "RS482 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a34[] = "RS480 PCI-X Root Port"; +static const char pci_device_1002_5a38[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a3f[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a41[] = "RS400 [Radeon Xpress 200]"; +static const char pci_device_1002_5a42[] = "RS400 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a61[] = "RC410 [Radeon Xpress 200]"; +static const char pci_device_1002_5a62[] = "RC410 [Radeon Xpress 200M]"; +static const char pci_device_1002_5b60[] = "RV370 5B60 [Radeon X300 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_002a[] = "Extreme AX300SE-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_032e[] = "Extreme AX300/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1462_0402[] = "RX300SE-TD128E (MS-8940)"; +#endif +static const char pci_device_1002_5b62[] = "RV370 5B62 [Radeon X600 (PCIE)]"; +static const char pci_device_1002_5b63[] = "RV370 [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b64[] = "RV370 5B64 [FireGL V3100 (PCIE)]"; +static const char pci_device_1002_5b65[] = "RV370 5B65 [FireGL D1100 (PCIE)]"; +static const char pci_device_1002_5b70[] = "RV370 [Radeon X300SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b70_1462_0403[] = "RX300SE-TD128E (MS-8940) (secondary display)"; +#endif +static const char pci_device_1002_5b72[] = "Radeon X600(RV380)"; +static const char pci_device_1002_5b73[] = "RV370 secondary [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b74[] = "RV370 5B64 [FireGL V3100 (PCIE)] (Secondary)"; +static const char pci_device_1002_5c61[] = "M9+ 5C61 [Radeon Mobility 9200 (AGP)]"; +static const char pci_device_1002_5c63[] = "M9+ 5C63 [Radeon Mobility 9200 (AGP)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5c63_1002_5c63[] = "Apple iBook G4 2004"; +#endif +static const char pci_device_1002_5d44[] = "RV280 [Radeon 9200 SE] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4019[] = "Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_174b_7c12[] = "Sapphire Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1787_5965[] = "Excalibur 9200SE VIVO 128M (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_17af_2013[] = "Radeon 9200 SE Excalibur (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0171[] = "Radeon 9200 SE 128MB Game Buster (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0172[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5d48[] = "M28 [Radeon Mobility X800XT]"; +static const char pci_device_1002_5d49[] = "M28 [Mobility FireGL V5100]"; +static const char pci_device_1002_5d4a[] = "Mobility Radeon X800"; +static const char pci_device_1002_5d4d[] = "R480 [Radeon X850XT Platinum (PCIE)]"; +static const char pci_device_1002_5d4f[] = "R480 [Radeon X800 GTO (PCIE)]"; +static const char pci_device_1002_5d52[] = "R480 [Radeon X850XT (PCIE)] (Primary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b12[] = "PowerColor X850XT PCIe Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b13[] = "PowerColor X850XT PCIe Secondary"; +#endif +static const char pci_device_1002_5d57[] = "R423 5F57 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_5d6d[] = "R480 [Radeon X850XT Platinum (PCIE)] (Secondary)"; +static const char pci_device_1002_5d6f[] = "R480 [Radeon X800 GTO (PCIE)] (Secondary)"; +static const char pci_device_1002_5d72[] = "R480 [Radeon X850XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5d77[] = "R423 5F57 [Radeon X800XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5e48[] = "RV410 [FireGL V5000]"; +static const char pci_device_1002_5e49[] = "RV410 [FireGL V3300]"; +static const char pci_device_1002_5e4a[] = "RV410 [Radeon X700XT]"; +static const char pci_device_1002_5e4b[] = "RV410 [Radeon X700 Pro (PCIE)]"; +static const char pci_device_1002_5e4c[] = "RV410 [Radeon X700SE]"; +static const char pci_device_1002_5e4d[] = "RV410 [Radeon X700 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e4d_148c_2116[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5e4f[] = "RV410 [Radeon X700]"; +static const char pci_device_1002_5e6b[] = "RV410 [Radeon X700 Pro (PCIE)] Secondary"; +static const char pci_device_1002_5e6d[] = "RV410 [Radeon X700 (PCIE)] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e6d_148c_2117[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_700f[] = "PCI Bridge [IGP 320M]"; +static const char pci_device_1002_7010[] = "PCI Bridge [IGP 340M]"; +static const char pci_device_1002_7100[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_7105[] = "R520 [FireGL]"; +static const char pci_device_1002_7109[] = "R520 [Radeon X1800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0322[] = "All-in-Wonder X1800XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0d02[] = "Radeon X1800 CrossFire Edition"; +#endif +static const char pci_device_1002_7120[] = "R520 [Radeon X1800] (Secondary)"; +static const char pci_device_1002_7129[] = "R520 [Radeon X1800] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0323[] = "All-in-Wonder X1800XL (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0d03[] = "Radeon X1800 CrossFire Edition (Secondary)"; +#endif +static const char pci_device_1002_7142[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7142_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7146[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7146_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7162[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7162_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_7166[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7166_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_71c0[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71c2[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71e0[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_71e2[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_7833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_7834[] = "Radeon 9100 PRO IGP"; +static const char pci_device_1002_7835[] = "Radeon Mobility 9200 IGP"; +static const char pci_device_1002_7838[] = "Radeon 9100 IGP PCI/AGP Bridge"; +static const char pci_device_1002_7c37[] = "RV350 AQ [Radeon 9600 SE]"; +static const char pci_device_1002_cab0[] = "AGP Bridge [IGP 320M]"; +static const char pci_device_1002_cab2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +static const char pci_device_1002_cab3[] = "R200 AGP Bridge [Mobility Radeon 7000 IGP]"; +static const char pci_device_1002_cbb2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_103c_0024[] = "Pavilion ze4400 builtin Network"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_12d9_000c[] = "Aculab E1/T1 PMXc cPCI carrier card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_1385_f311[] = "FA311 / FA312 (FA311 with WoL HW)"; +#endif +static const char pci_device_100b_0021[] = "PC87200 PCI to ISA Bridge"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0028[] = "Geode GX2 Host Bridge"; +static const char pci_device_100b_002a[] = "CS5535 South Bridge"; +static const char pci_device_100b_002b[] = "CS5535 ISA bridge"; +static const char pci_device_100b_002d[] = "CS5535 IDE"; +static const char pci_device_100b_002e[] = "CS5535 Audio"; +static const char pci_device_100b_002f[] = "CS5535 USB"; +static const char pci_device_100b_0030[] = "Geode GX2 Graphics Processor"; +static const char pci_device_100b_0035[] = "DP83065 [Saturn] 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_0510[] = "SC1100 Bridge"; +static const char pci_device_100b_0511[] = "SC1100 SMI"; +static const char pci_device_100b_0515[] = "SC1100 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "DEFPA"; +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0017[] = "PV-PCI Graphics Controller (ZLXp-L)"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1112[] = "DFE-570TX Quad Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_14cb_0100[] = "LNDL-100N 100Base-TX Ethernet PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX Gigabit Ethernet"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "Hewlett-Packard NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "IP Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0364[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4000[] = "MD 5620 [CLM Data Fax Voice]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_1136[] = "SiXPack 5.1+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "GXT1000 Graphics Adapter"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "SCSI RAID Adapter [ServeRAID]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0031[] = "2 Port Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0031_1014_0031[] = "2721 WAN IOA - 2 Port Sync Serial Adapter"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_0037[] = "82660 CPU to PCI Bridge"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003c[] = "GXT250P/GXT255P Graphics Adapter"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0054[] = "GXT500P/GXT550P Graphics Adapter"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_005e[] = "GXT800P Graphics Adapter"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_008b[] = "EADS PCI to PCI Bridge"; +static const char pci_device_1014_008e[] = "GXT3000P Graphics Adapter"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0091[] = "SSA Adapter"; +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_009f[] = "PCI 4758 Cryptographic Accelerator"; +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_00b7_1092_00b8[] = "FireGL1 AGP 32Mb"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1014_00b8[] = "GXT2000P Graphics Adapter"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0104[] = "Gigabit Ethernet-SX Adapter"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_015e[] = "622Mbps ATM PCI Adapter"; +static const char pci_device_1014_0160[] = "64bit/66MHz PCI ATM 155 MMF"; +static const char pci_device_1014_016e[] = "GXT4000P Graphics Adapter"; +static const char pci_device_1014_0170[] = "GXT6000P Graphics Adapter"; +static const char pci_device_1014_017d[] = "GXT300P Graphics Adapter"; +static const char pci_device_1014_0180[] = "Snipe chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0241[] = "iSeries 2757 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0264[] = "Quad Channel PCI-X U320 SCSI RAID Adapter (2780)"; +#endif +static const char pci_device_1014_0188[] = "EADS-X PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_01c1[] = "64bit/66MHz PCI ATM 155 UTP"; +static const char pci_device_1014_01e6[] = "Cryptographic Accelerator"; +static const char pci_device_1014_01ff[] = "10/100 Mbps Ethernet"; +static const char pci_device_1014_0219[] = "Multiport Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_021a[] = "Dual RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0251[] = "Internal Modem/RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0252[] = "Quad Internal Modem"; +#endif +static const char pci_device_1014_021b[] = "GXT6500P Graphics Adapter"; +static const char pci_device_1014_021c[] = "GXT4500P Graphics Adapter"; +static const char pci_device_1014_0233[] = "GXT135P Graphics Adapter"; +static const char pci_device_1014_0266[] = "PCI-X Dual Channel SCSI"; +static const char pci_device_1014_0268[] = "Gigabit Ethernet-SX Adapter (PCI-X)"; +static const char pci_device_1014_0269[] = "10/100/1000 Base-TX Ethernet Adapter (PCI-X)"; +static const char pci_device_1014_028c[] = "Citrine chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_028d[] = "Dual Channel PCI-X DDR SAS RAID Adapter (572E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02be[] = "Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02c0[] = "Dual Channel PCI-X DDR U320 SCSI Adapter (571A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_030d[] = "PCI-X DDR Auxiliary Cache Adapter (575B)"; +#endif +static const char pci_device_1014_02a1[] = "Calgary PCI-X Host Bridge"; +static const char pci_device_1014_02bd[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/571D)"; +#endif +static const char pci_device_1014_0302[] = "Winnipeg PCI-X Host Bridge"; +static const char pci_device_1014_0314[] = "ZISC 036 Neural accelerator card"; +static const char pci_device_1014_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_4022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_0009[] = "MegaRAID 428 Ultra RAID Controller (rev 03)"; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500/500LC RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0477[] = "MegaRAID 477 Elite 3100 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0494[] = "MegaRAID 494 Elite 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0503[] = "MegaRAID 503 Enterprise 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0511[] = "MegaRAID 511 i4 IDE RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0522[] = "MegaRAID 522 i4133 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_103c_60e7[] = "NetRAID-1M"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 [Athlon64/Opteron] HyperTransport Technology Configuration"; +static const char pci_device_1022_1101[] = "K8 [Athlon64/Opteron] Address Map"; +static const char pci_device_1022_1102[] = "K8 [Athlon64/Opteron] DRAM Controller"; +static const char pci_device_1022_1103[] = "K8 [Athlon64/Opteron] Miscellaneous Control"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1022_2000[] = "PCnet - Fast 79C971"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2702[] = "AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2703[] = "AT-2701FX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2003[] = "Am 1771 MBW [Alchemy]"; +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_2081[] = "Geode LX Video"; +static const char pci_device_1022_2082[] = "Geode LX AES Security Block"; +static const char pci_device_1022_208f[] = "CS5536 GeodeLink PCI South Bridge"; +static const char pci_device_1022_2090[] = "CS5536 [Geode companion] ISA"; +static const char pci_device_1022_2091[] = "CS5536 [Geode companion] FLASH"; +static const char pci_device_1022_2093[] = "CS5536 [Geode companion] Audio"; +static const char pci_device_1022_2094[] = "CS5536 [Geode companion] OHC"; +static const char pci_device_1022_2095[] = "CS5536 [Geode companion] EHC"; +static const char pci_device_1022_2096[] = "CS5536 [Geode companion] UDC"; +static const char pci_device_1022_2097[] = "CS5536 [Geode companion] UOC"; +static const char pci_device_1022_209a[] = "CS5536 [Geode companion] IDE"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700a[] = "AMD-IGR4 AGP Host to PCI Bridge"; +static const char pci_device_1022_700b[] = "AMD-IGR4 PCI to PCI Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X IOAPIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7458[] = "AMD-8132 PCI-X Bridge"; +static const char pci_device_1022_7459[] = "AMD-8132 PCI-X IOAPIC"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7460_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7464_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7468_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_1022_2b80[] = "AMD-8111 IDE [Quartet]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746b_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746d_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_device_1022_756b[] = "AMD-8111 ACPI"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_2001_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +#endif +static const char pci_device_1023_2100[] = "CyberBlade XP4m32"; +static const char pci_device_1023_2200[] = "XGI Volari XP5"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad R30/T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_1025[] = "Travelmate 352TE"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_1671[] = "M1671 Northbridge [ALADDiN-P4]"; +static const char pci_device_1025_1672[] = "Northbridge [CyberALADDiN-P4]"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge 2400"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge 4400"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge 2450"; +#endif +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Access Card III"; +static const char pci_device_1028_0008[] = "Remote Access Card III"; +static const char pci_device_1028_0009[] = "Remote Access Card III: BMC/SMIC device not present"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000c[] = "Embedded Remote Access or ERA/O"; +static const char pci_device_1028_000d[] = "Embedded Remote Access: BMC/SMIC device"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_0010[] = "Remote Access Card 4"; +static const char pci_device_1028_0011[] = "Remote Access Card 4 Daughter Card"; +static const char pci_device_1028_0012[] = "Remote Access Card 4 Daughter Card Virtual UART"; +static const char pci_device_1028_0013[] = "PowerEdge Expandable RAID controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016c[] = "PowerEdge Expandable RAID Controller 4e/Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016d[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016e[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016f[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_0170[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +static const char pci_device_1028_0014[] = "Remote Access Card 4 Daughter Card SMIC interface"; +static const char pci_device_1028_0015[] = "PowerEdge Expandable RAID controller 5"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +static const char pci_device_102a_001f[] = "AHA-2940U2/U2W /7890/7891 SCSI Controllers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_0106[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_102a_00c5[] = "AIC-7899 U160/m SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00c5_1028_00c5[] = "PowerEdge 2550/2650/4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_102a_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0106[] = "PowerEdge 4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0121[] = "PowerEdge 2650"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0100[] = "MGA 1064SG [Mystique]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0525[] = "G400/G450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d43[] = "Millennium G450 32Mb Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0850[] = "Parhelia 256MB AGP 4X"; +#endif +static const char pci_device_102b_0528[] = "Parhelia 8X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1020[] = "Parhelia 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1030[] = "Parhelia 256 MB Dual DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_14e1[] = "Parhelia PCI 256MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_2021[] = "QID Pro"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_2537[] = "Millenium P650/P750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1820[] = "Millennium P750 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1830[] = "Millennium P650 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1c10[] = "QID 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2811[] = "Millennium P650 Low-profile PCI 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2c11[] = "QID Low-profile PCI"; +#endif +static const char pci_device_102b_2538[] = "Millenium P650 PCIe"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_08c7[] = "Millennium P650 PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_0907[] = "Millennium P650 PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1047[] = "Millennium P650 LP PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1087[] = "Millennium P650 LP PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_2538[] = "Parhelia APVe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_3007[] = "QID Low-profile PCIe"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_000a[] = "TX3927 MIPS RISC PCI Controller"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +static const char pci_device_102f_0030[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller"; +static const char pci_device_102f_0031[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL"; +static const char pci_device_102f_0105[] = "TC86C001 [goku-s] IDE"; +static const char pci_device_102f_0106[] = "TC86C001 [goku-s] USB 1.1 Host"; +static const char pci_device_102f_0107[] = "TC86C001 [goku-s] USB Device Controller"; +static const char pci_device_102f_0108[] = "TC86C001 [goku-s] I2C/SIO/GPIO Controller"; +static const char pci_device_102f_0180[] = "TX4927/38 MIPS RISC PCI Controller"; +static const char pci_device_102f_0181[] = "TX4925 MIPS RISC PCI Controller"; +static const char pci_device_102f_0182[] = "TX4937 MIPS RISC PCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0000[] = "Vr4181A USB Host or Function Control Unit"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1033_0035[] = "Hama USB 2.0 CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_14c2_0105[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000a[] = "GlobeTrotter Fusion Quad Lite (PPP data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000b[] = "GlobeTrotter Fusion Quad Lite (GSM data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_807d_0035[] = "PCI-USB2 (OHCI subsystem)"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0072[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a5[] = "VRC4173"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00ce[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00df[] = "Vr4131"; +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_14c2_0205[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_807d_1043[] = "PCI-USB2 (EHCI subsystem)"; +#endif +static const char pci_device_1033_00e7[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00f2[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_00f3[] = "uPD6113x Multimedia Decoder/Processor [EMMA2]"; +static const char pci_device_1033_010c[] = "VR7701"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0003[] = "SiS AGP Port (virtual PCI-to-PCI bridge)"; +static const char pci_device_1039_0004[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_000a[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0016[] = "SiS961/2 SMBus Controller"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0180[] = "RAID bus controller 180 SATA/PATA [SiS]"; +static const char pci_device_1039_0181[] = "SATA"; +static const char pci_device_1039_0182[] = "182 SATA/RAID Controller"; +static const char pci_device_1039_0190[] = "190 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0191[] = "191 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0550[] = "550 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0648[] = "645xx"; +static const char pci_device_1039_0650[] = "650/M650 Host"; +static const char pci_device_1039_0651[] = "651 Host"; +static const char pci_device_1039_0655[] = "655 Host"; +static const char pci_device_1039_0660[] = "660 Host"; +static const char pci_device_1039_0661[] = "661FX/M661FX/M661MX Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0741[] = "741/741GX/M741 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0746[] = "746 Host"; +static const char pci_device_1039_0755[] = "755 Host"; +static const char pci_device_1039_0760[] = "760/M760 Host"; +static const char pci_device_1039_0761[] = "761/M761 Host"; +static const char pci_device_1039_0900[] = "SiS900 PCI Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_0963[] = "SiS963 [MuTIOL Media IO]"; +static const char pci_device_1039_0964[] = "SiS964 [MuTIOL Media IO]"; +static const char pci_device_1039_0965[] = "SiS965 [MuTIOL Media IO]"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "550 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "630/730 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_6306[] = "530/620 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "65x/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_6330[] = "661/741/760/761 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6330_1039_6330[] = "[M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter"; +#endif +static const char pci_device_1039_7001[] = "USB 1.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1462_5470[] = "K7SOM+ 5.2C Motherboard"; +#endif +static const char pci_device_1039_7002[] = "USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "AC'97 Sound Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7012_15bd_1001[] = "DFI 661FX motherboard"; +#endif +static const char pci_device_1039_7013[] = "AC'97 Modem Controller"; +static const char pci_device_1039_7016[] = "SiS7016 PCI Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +static const char pci_device_1039_7019[] = "SiS7019 Audio Accelerator"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1006[] = "Visualize FX6"; +static const char pci_device_103c_1008[] = "Visualize FX4"; +static const char pci_device_103c_100a[] = "Visualize FX2"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Superdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1301[] = "Diva RMP3"; +#endif +static const char pci_device_103c_1054[] = "PCI Local Bus Adapter"; +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_10f0[] = "rio System Bus Adapter"; +static const char pci_device_103c_10f1[] = "rio I/O Controller"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "zx1 Local Bus Adapter"; +static const char pci_device_103c_127c[] = "sx1000 I/O Controller"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_1291[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_12b4[] = "zx1 QuickSilver AGP8x Local Bus Adapter"; +static const char pci_device_103c_12fa[] = "BCM4306 802.11b/g Wireless LAN Controller"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +static const char pci_device_103c_3080[] = "Pavilion ze2028ea"; +static const char pci_device_103c_3220[] = "Hewlett-Packard Smart Array P600"; +static const char pci_device_103c_3230[] = "Hewlett-Packard Smart Array Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "PC Tech RZ1000"; +static const char pci_device_1042_1001[] = "PC Tech RZ1001"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "ASUSTeK Computer Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_10cf_105e[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1043_4015[] = "v7100 SDRAM [GeForce2 MX]"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +static const char pci_device_1043_4057[] = "v8200 GeForce 3"; +static const char pci_device_1043_8043[] = "v8240 PAL 128M [P4T] Motherboard"; +static const char pci_device_1043_807b[] = "v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI]"; +static const char pci_device_1043_80bb[] = "v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out]"; +static const char pci_device_1043_80c5[] = "nForce3 chipset motherboard [SK8N]"; +static const char pci_device_1043_80df[] = "v9520 Magic/T"; +static const char pci_device_1043_8187[] = "802.11a/b/g Wireless LAN Card"; +static const char pci_device_1043_8188[] = "Tiger Hybrid TV Capture Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Adaptec (formerly DPT)"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3410S Ultra160 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c032[] = "ASR-2005S I2O Zero Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c035[] = "ASR-2010S I2O Zero Channel"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCIAudio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0c60[] = "Gladiac MX"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +static const char pci_device_1048_8901[] = "Gloria XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1048_8901_1048_0935[] = "GLoria XL (Virge)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "STMicroelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0209[] = "STPC Consumer/Industrial North- and Southbridge"; +static const char pci_device_104a_020a[] = "STPC Atlas/ConsumerS/Consumer IIA Northbridge"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_021a[] = "STPC Consumer S Southbridge"; +static const char pci_device_104a_021b[] = "STPC Consumer IIA Southbridge"; +static const char pci_device_104a_0500[] = "ST70137 [Unicorn] ADSL DMT Transceiver"; +static const char pci_device_104a_0564[] = "STPC Client Northbridge"; +static const char pci_device_104a_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +static const char pci_device_104a_55cc[] = "STPC Client Southbridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a34[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a36[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a43[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a44[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_000f[] = "Studio DV500-1394"; +#endif +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_1043_808b[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8025[] = "TSB82AA2 IEEE-1394b Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8025_1458_1000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1043_808d[] = "A7V333 mainboard."; +#endif +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8029[] = "PCI4510 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1071_8160[] = "MIM2900"; +#endif +static const char pci_device_104c_802b[] = "PCI7410,7510,7610 OHCI-Lynx Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_014e[] = "PCI7410,7510,7610 OHCI-Lynx Controller (Dell Latitude D800)"; +#endif +static const char pci_device_104c_802e[] = "PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller"; +static const char pci_device_104c_8031[] = "PCIxx21/x515 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8032[] = "OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8033[] = "PCIxx21 Integrated FlashMedia Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8034[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8035[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Smart Card Controller (SMC)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8035_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_104c_8036[] = "PCI6515 Cardbus Controller"; +static const char pci_device_104c_8038[] = "PCI6515 SmartCard Controller"; +static const char pci_device_104c_8201[] = "PCI1620 Firmware Loading Function"; +static const char pci_device_104c_8204[] = "PCI7410,7510,7610 PCI Firmware Loading Function"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b00[] = "DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b01[] = "DWL-520+ 22Mbps PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_16ab_8501[] = "WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter"; +#endif +static const char pci_device_104c_8401[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_9000[] = "Wireless Interface (of unknown type)"; +static const char pci_device_104c_9065[] = "TMS320DM642"; +static const char pci_device_104c_9066[] = "ACX 111 54Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_104c_9066[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b04[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b05[] = "DWL-G650+ AirPlusG+ CardBus Wireless LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_13d1_aba0[] = "SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+"; +#endif +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6414 TMS320C6415 TMS320C6416"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_5000[] = "ASI50xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_6400[] = "ASI6400 Cobranet series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_8700[] = "ASI87xx Radio Tuner card"; +#endif +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac16_1014_0092[] = "ThinkPad 600"; +#endif +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_1014_0130[] = "Thinkpad T20/T22/A21m"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_0e11_b121[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_1028_0088[] = "Latitude CPi A400XT"; +#endif +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_ac44[] = "PCI4510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_104c_ac46[] = "PCI4520 PC card Cardbus Controller"; +static const char pci_device_104c_ac47[] = "PCI7510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac4a[] = "PCI7510,7610 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_0e11_004e[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_00b1[] = "Latitude C600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1033_80cd[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1095_10cf[] = "Fujitsu-Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook S-4510/C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac54[] = "PCI1620 PC Card Controller"; +static const char pci_device_104c_ac55[] = "PCI1520 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30/T40"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0528[] = "ThinkPad R40e (2684-HVG) Cardbus Controller"; +#endif +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_5100[] = "ASI51xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6100[] = "ASI61xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6200[] = "ASI62xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_8800[] = "ASI88xx Audio Adapter"; +#endif +static const char pci_device_104c_ac8d[] = "PCI 7620"; +static const char pci_device_104c_ac8e[] = "PCI7420 CardBus Controller"; +static const char pci_device_104c_ac8f[] = "PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8004[] = "DTL-H2500 [Playstation development board]"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1050_9921[] = "W99200F MPEG-1 Video Encoder"; +static const char pci_device_1050_9922[] = "W99200F/W9922PF MPEG-1/2 Video Encoder"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0008[] = "MPC8540"; +static const char pci_device_1057_0009[] = "MPC8560"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "DSP56301 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0101[] = "Transas Radar Imitator Board [RIM]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0102[] = "Transas Radar Imitator Board [RIM-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0202[] = "Transas Radar Integrator Board [RIB-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0611[] = "1 channel CAN bus Controller [CanPci-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0612[] = "2 channels CAN bus Controller [CanPci-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0613[] = "3 channels CAN bus Controller [CanPci-3]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0614[] = "4 channels CAN bus Controller [CanPci-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0621[] = "1 channel CAN bus Controller [CanPci2-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0622[] = "2 channels CAN bus Controller [CanPci2-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0810[] = "Transas VTS Radar Integrator Board [RIB-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4200[] = "ASI4215 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4300[] = "ASI43xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4400[] = "ASI4401 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0010[] = "Darla"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0020[] = "Gina"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0031[] = "Layla rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0040[] = "Darla24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0041[] = "Darla24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0072[] = "Mona rev.2"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/8266/8272"; +static const char pci_device_1057_18c1[] = "MPC8271/MPC8272"; +static const char pci_device_1057_3410[] = "DSP56361 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0060[] = "Layla24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0072[] = "Mona rev.2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0080[] = "Mia rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0081[] = "Mia rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0090[] = "Indigo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00a0[] = "Indigo IO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00b0[] = "Indigo DJ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0100[] = "3G"; +#endif +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_5608[] = "Wildcard X100P"; +static const char pci_device_1057_5803[] = "MPC5200"; +static const char pci_device_1057_5806[] = "MCF54 Coldfire"; +static const char pci_device_1057_5808[] = "MPC8220"; +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +static const char pci_device_1057_6405[] = "MPC184 Security Processor (S1 family)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "PDC20265 (FastTrak100 Lite/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3318[] = "PDC20318 (SATA150 TX4)"; +static const char pci_device_105a_3319[] = "PDC20319 (FastTrak S150 TX4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3319_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_105a_3371[] = "PDC20371 (FastTrak S150 TX2plus)"; +static const char pci_device_105a_3373[] = "PDC20378 (FastTrak 378/SATA 378)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1043_80f5[] = "K8V Deluxe/PC-DL Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1462_702e[] = "K8T NEO FIS2R motherboard"; +#endif +static const char pci_device_105a_3375[] = "PDC20375 (SATA150 TX2plus)"; +static const char pci_device_105a_3376[] = "PDC20376 (FastTrak 376)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3376_1043_809e[] = "A7V8X motherboard"; +#endif +static const char pci_device_105a_3515[] = "PDC40719"; +static const char pci_device_105a_3519[] = "PDC40519 (FastTrak TX4200)"; +static const char pci_device_105a_3570[] = "20771 (FastTrak TX2300)"; +static const char pci_device_105a_3571[] = "PDC20571 (FastTrak TX2200)"; +static const char pci_device_105a_3574[] = "PDC20579 SATAII 150 IDE Controller"; +static const char pci_device_105a_3577[] = "PDC40779 (SATA 300 779)"; +static const char pci_device_105a_3d17[] = "PDC20718 (SATA 300 TX4)"; +static const char pci_device_105a_3d18[] = "PDC20518/PDC40518 (SATAII 150 TX4)"; +static const char pci_device_105a_3d73[] = "PDC40775 (SATA 300 TX2plus)"; +static const char pci_device_105a_3d75[] = "PDC20575 (SATAII150 TX2plus)"; +static const char pci_device_105a_4d30[] = "PDC20267 (FastTrak100/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "FastTrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "PDC20262 (FastTrak66/Ultra66)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "FastTrak66"; +#endif +static const char pci_device_105a_4d68[] = "PDC20268 (Ultra100 TX2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d69_105a_4d68[] = "Ultra133TX2"; +#endif +static const char pci_device_105a_5275[] = "PDC20276 (MBFastTrak133 Lite)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1043_807e[] = "A7V333 motherboard."; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_1275[] = "MBFastTrak133 Lite (tm) Controller (RAID mode)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1458_b001[] = "MBUltra 133"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "PDC20270 (FastTrak100 LP/TX2/TX4)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6268_105a_4d68[] = "FastTrak100 TX2"; +#endif +static const char pci_device_105a_6269[] = "PDC20271 (FastTrak TX2000)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite)"; +static const char pci_device_105a_6622[] = "PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_6624[] = "PDC20621 [FastTrak SX4100]"; +static const char pci_device_105a_6626[] = "PDC20618 (Ultra 618)"; +static const char pci_device_105a_6629[] = "PDC20619 (FastTrak TX4000)"; +static const char pci_device_105a_7275[] = "PDC20277 (SBFastTrak133 Lite)"; +static const char pci_device_105a_8002[] = "SATAII150 SX8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_105d_0037[] = "Revolution IV-FP AGP (For SGI 1600SW)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_1067_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_1067_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PG"; +static const char pci_device_1069_0020[] = "DAC960LA"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0050[] = "AcceleRAID 352 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0052[] = "AcceleRAID 170 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0054[] = "AcceleRAID 160 support Device"; +#endif +static const char pci_device_1069_b166[] = "AcceleRAID 600/500/400/Sapphire support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0242[] = "iSeries 2872 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0266[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0278[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d3[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d4[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0200[] = "AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0202[] = "AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0204[] = "AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0206[] = "AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0030[] = "eXtremeRAID 3000 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0040[] = "eXtremeRAID 2000 support Device"; +#endif +static const char pci_device_1069_ba57[] = "eXtremeRAID 4000/5000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba57_1069_0072[] = "eXtremeRAID 5000 support Device"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000c[] = "DOS on Mac"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_106b_0031_106b_5811[] = "iBook G4 2004"; +#endif +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_0035[] = "UniNorth 2 PCI"; +static const char pci_device_106b_0036[] = "UniNorth 2 Internal PCI"; +static const char pci_device_106b_003b[] = "UniNorth/Intrepid ATA/100"; +static const char pci_device_106b_003e[] = "KeyLargo/Intrepid Mac I/O"; +static const char pci_device_106b_003f[] = "KeyLargo/Intrepid USB"; +static const char pci_device_106b_0040[] = "K2 KeyLargo USB"; +static const char pci_device_106b_0041[] = "K2 KeyLargo Mac/IO"; +static const char pci_device_106b_0042[] = "K2 FireWire"; +static const char pci_device_106b_0043[] = "K2 ATA/100"; +static const char pci_device_106b_0045[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0046[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0047[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0048[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0049[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_004b[] = "U3 AGP"; +static const char pci_device_106b_004c[] = "K2 GMAC (Sun GEM)"; +static const char pci_device_106b_004f[] = "Shasta Mac I/O"; +static const char pci_device_106b_0050[] = "Shasta IDE"; +static const char pci_device_106b_0051[] = "Shasta (Sun GEM)"; +static const char pci_device_106b_0052[] = "Shasta Firewire"; +static const char pci_device_106b_0053[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0054[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0055[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0058[] = "U3L AGP Bridge"; +static const char pci_device_106b_0059[] = "U3H AGP Bridge"; +static const char pci_device_106b_0066[] = "Intrepid2 AGP Bridge"; +static const char pci_device_106b_0067[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0068[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0069[] = "Intrepid2 ATA/100"; +static const char pci_device_106b_006a[] = "Intrepid2 Firewire"; +static const char pci_device_106b_006b[] = "Intrepid2 GMAC (Sun GEM)"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hynix Semiconductor"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +static const char pci_device_1071_8160[] = "Mitac 8060B Mobile Platform"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280 SCSI Host Adapter"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2200_1077_0002[] = "QLA2200"; +#endif +static const char pci_device_1077_2300[] = "QLA2300 64-bit Fibre Channel Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +static const char pci_device_1077_2322[] = "QLA2322 Fibre Channel Adapter"; +static const char pci_device_1077_2422[] = "QLA2422 Fibre Channel Adapter"; +static const char pci_device_1077_2432[] = "QLA2432 Fibre Channel Adapter"; +static const char pci_device_1077_3010[] = "QLA3010 Network Adapter"; +static const char pci_device_1077_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1077_4010[] = "QLA4010 iSCSI TOE Adapter"; +static const char pci_device_1077_4022[] = "QLA4022 iSCSI TOE Adapter"; +static const char pci_device_1077_6312[] = "QLA6312 Fibre Channel Adapter"; +static const char pci_device_1077_6322[] = "QLA6322 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +static const char pci_device_107d_2134[] = "WinFast 3D S320 II"; +static const char pci_device_107d_2971[] = "[GeForce FX 5900] WinFast A350 TDH MyViVo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_1648[] = "[bge] Gigabit Ethernet"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_8002[] = "Schizo+ PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +static const char pci_device_108e_a801[] = "Tomatillo PCI Bus Module"; +static const char pci_device_108e_abba[] = "Cassini 10/100/1000"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Compro Computer Services, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +static const char pci_device_1091_07a0[] = "Sun Expert3D-Lite Graphics Accelerator"; +static const char pci_device_1091_1091[] = "Sun Expert3D Graphics Accelerator"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1310[] = "PCI-6602"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_14e0[] = "PCI-6110"; +static const char pci_device_1093_14f0[] = "PCI-6111"; +static const char pci_device_1093_17d0[] = "PCI-6503"; +static const char pci_device_1093_1870[] = "PCI-6713"; +static const char pci_device_1093_1880[] = "PCI-6711"; +static const char pci_device_1093_18b0[] = "PCI-6052E"; +static const char pci_device_1093_2410[] = "PCI-6733"; +static const char pci_device_1093_2890[] = "PCI-6036E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_2a70[] = "PCI-6024E"; +static const char pci_device_1093_2a80[] = "PCI-6025E"; +static const char pci_device_1093_2c80[] = "PCI-6035E"; +static const char pci_device_1093_2ca0[] = "PCI-6034E"; +static const char pci_device_1093_70a9[] = "PCI-6528"; +static const char pci_device_1093_70b8[] = "PCI-6251 [M Series - High Speed Multifunction DAQ]"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "Silicon Image, Inc."; +static const char pci_device_1095_0240[] = "Adaptec AAR-1210SA SATA HostRAID Controller"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0648_1043_8025[] = "CUBX motherboard"; +#endif +static const char pci_device_1095_0649[] = "SiI 0649 Ultra ATA/100 PCI to ATA Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680 Ultra ATA-133 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0680_1095_3680[] = "Winic W-680 (Silicon Image 680 based)"; +#endif +static const char pci_device_1095_3112[] = "SiI 3112 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_3112[] = "SiI 3112 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_6112[] = "SiI 3112 SATARaid Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_9005_0250[] = "SATAConnect 1205SA Host Controller"; +#endif +static const char pci_device_1095_3114[] = "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_3114[] = "SiI 3114 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_6114[] = "SiI 3114 SATARaid Controller"; +#endif +static const char pci_device_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3124_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#endif +static const char pci_device_1095_3132[] = "SiI 3132 Serial ATA Raid II Controller"; +static const char pci_device_1095_3512[] = "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_3512[] = "SiI 3512 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_6512[] = "SiI 3512 SATARaid Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_032e[] = "Bt878 Video Capture"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0002[] = "TV98 Series (TV/No FM/Remote)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0003[] = "AverMedia UltraTV PCI 350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0761[] = "AverTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1822_0001[] = "VisionPlus DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0002[] = "Avermedia PCTV98 Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0761[] = "AVerTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1822_0001[] = "VisionPlus DVB Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_3052[] = "SmartPCI562 56K Modem"; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10a9_0009_10a9_8002[] = "AceNIC Gigabit Ethernet"; +#endif +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_100a[] = "IOC4 I/O controller"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_4001[] = "TIO-CE PCI Express Bridge"; +static const char pci_device_10a9_4002[] = "TIO-CE PCI Express Port"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +static const char pci_device_10a9_8010[] = "Broadcom e-net [SGI IO9/IO10 BaseIO]"; +static const char pci_device_10a9_8018[] = "Broadcom e-net [SGI A330 Server BaseIO]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1042[] = "Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2540[] = "IXXAT CAN-Interface PC-I 04/PCI"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_6540[] = "PCI6540/6466 PCI-PCI bridge (transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6540_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6541[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6541_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6542[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6542_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_8111[] = "PEX 8111 PCI Express-to-PCI Bridge"; +static const char pci_device_10b5_8114[] = "PEX 8114 PCI Express-to-PCI/PCI-X Bridge"; +static const char pci_device_10b5_8516[] = "PEX 8516 Versatile PCI Express Switch"; +static const char pci_device_10b5_8532[] = "PEX 8532 Versatile PCI Express Switch"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2862[] = "Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2906[] = "Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2940[] = "Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2977[] = "IXXAT iPC-I XC16/PCI CAN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2978[] = "SH ARC-PCIu SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3025[] = "Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3068[] = "Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3136[] = "4xS0-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3137[] = "S2M-E1-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1518_0200[] = "Kontron ThinkIO-C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1067[] = "IXXAT CAN i165"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1172[] = "IK220 (Heidenhain)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2221[] = "Alpermann+Velte PCL PCI LV: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH ARC-PCI SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2431[] = "Alpermann+Velte PCL PCI D: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2905[] = "Alpermann+Velte PCI TS: Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "MP9050"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1498_0362[] = "TPMC866 8 Channel Serial Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_2036[] = "OpenSwitch 6 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_3132[] = "OpenSwitch 12 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2696[] = "Innes Corp AM Radcap card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2717[] = "Innes Corp Auricon card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2844[] = "Innes Corp TVS Encoder card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12c7_4001[] = "Intel Dialogic DM/V960-4T1 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12d9_0002[] = "PCI Prosody Card rev 1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0011[] = "PIKA PrimeNet MM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0012[] = "PIKA PrimeNet MM cPCI 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0013[] = "PIKA PrimeNet MM cPCI 8 (without CAS Signaling)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0014[] = "PIKA PrimeNet MM cPCI 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0015[] = "PIKA Daytona MM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0016[] = "PIKA InLine MM"; +#endif +static const char pci_device_10b5_9056[] = "Francois"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9056_10b5_2979[] = "CellinkBlade 11 - CPCI board VoATM AAL1"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10eb[] = "(Agilent) E2777B 83K Series Optical Communication Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10ec[] = "(Agilent) E6978-66442 PCI CIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12d9_0002[] = "PCI Prosody Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12df_4422[] = "4422PCI [Do-All Telemetry Data Aquisition System]"; +#endif +static const char pci_device_10b5_bb04[] = "B&B 3PCIOSD1A Isolated PCI Serial"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_0013[] = "AR5212 802.11abg NIC (3CRDAG675)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_0013_10b7_2031[] = "3CRDAG675 11a/b/g Wireless PCI Adapter"; +#endif +static const char pci_device_10b7_0910[] = "3C910-A01"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +static const char pci_device_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +static const char pci_device_10b7_1700[] = "3c940 10/100/1000Base-T [Marvell]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_1043_80eb[] = "A7V600/P4P800/K8V motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0010[] = "3C940 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0020[] = "3C941 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 HomePNA [Tornado]"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3cCFE575CT CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6000[] = "3CRSHPW796 [OfficeConnect Wireless CardBus]"; +static const char pci_device_10b7_6001[] = "3com 3CRWE154G72 [Office Connect Wireless LAN Adapter]"; +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus [Cyclone]"; +static const char pci_device_10b7_6056[] = "3c556B CardBus [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3cCFE656 CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3cCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3cCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado]"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7770[] = "3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect]"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_80eb[] = "3c940B 10/100/1000Base-T"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 10Mbps Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC Etherlink XL [Cyclone]"; +static const char pci_device_10b7_900a[] = "3c900B-FL 10base-FL [Cyclone]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 Fast EtherLink XL [Cyclone]"; +static const char pci_device_10b7_9058[] = "3c905B Deluxe Etherlink 10/100/BNC [Cyclone]"; +static const char pci_device_10b7_905a[] = "3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0097[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_00fe[] = "Optiplex GX240"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_012a[] = "3C920 Integrated Fast Ethernet Controller [Latitude C640]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10f1_2466[] = "Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller)"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9201_1043_80ab[] = "A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller"; +#endif +static const char pci_device_10b7_9202[] = "3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9210[] = "3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX 910-A01 [tulip]"; +static const char pci_device_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-C 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "EtherLink Server 10/100 Dual Port A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "EtherLink Server 10/100 Dual Port B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990a[] = "3C990SVR [Typhoon Server]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83c170 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "83c175 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_2802[] = "SMC2802W [EZ Connect g]"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0101[] = "CMI8338/C3DX PCI Audio Device"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_0780[] = "Multi-IO Card"; +static const char pci_device_10b9_0782[] = "Multi-IO Card"; +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_1014_053b[] = "ThinkPad R40e (2684-HVG) PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALi M1533 Aladdin IV/V ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1573[] = "PCI to LPC Controller"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1672[] = "M1672 Northbridge [CyberALADDiN-P4]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_1689[] = "M1689 K8 Northbridge [Super K8 Single Chip]"; +static const char pci_device_10b9_1695[] = "M1695 K8 Northbridge [PCI Express and HyperTransport]"; +static const char pci_device_10b9_1697[] = "M1697 HTT Host Bridge"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_3323[] = "M3325 Video/Audio Decoder"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5228[] = "M5228 ALi ATA/RAID Controller"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_050f[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_053d[] = "ThinkPad R40e (2684-HVG) builtin IDE"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_103c_0024[] = "Pavilion ze4400 builtin IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_1014_0540[] = "ThinkPad R40e (2684-HVG) builtin USB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_103c_0024[] = "Pavilion ze4400 builtin USB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_104d_810f[] = "VAIO PCG-U1 USB/OHCI Revision 1.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5246[] = "AGP8X Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_524b[] = "PCI Express Root Port"; +static const char pci_device_10b9_524c[] = "PCI Express Root Port"; +static const char pci_device_10b9_524d[] = "PCI Express Root Port"; +static const char pci_device_10b9_524e[] = "PCI Express Root Port"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5263[] = "M5263 Ethernet Controller"; +static const char pci_device_10b9_5281[] = "ALi M5281 Serial ATA / RAID Host Controller"; +static const char pci_device_10b9_5287[] = "ULi 5287 SATA"; +static const char pci_device_10b9_5288[] = "ULi M5288 SATA"; +static const char pci_device_10b9_5289[] = "ULi 5289 SATA"; +static const char pci_device_10b9_5450[] = "Lucent Technologies Soft Modem AMR"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_053e[] = "ThinkPad R40e (2684-HVG) builtin Audio"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_103c_0024[] = "Pavilion ze4400 builtin Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_10b9_5451[] = "HP Compaq nc4010 (DY885AA#ABN)"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "M5457 AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_1014_0535[] = "ThinkPad R40e (2684-HVG) builtin modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_103c_0024[] = "Pavilion ze4400 builtin Modem Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5461[] = "High Definition Audio/AC'97 Host Controller"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 Power Management Controller [PMU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_0510[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_053c[] = "ThinkPad R40e (2684-HVG) Power Management Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_103c_0024[] = "Pavilion ze4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_10ba_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1028_0088[] = "Latitude CPi A"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_0088[] = "Latitude CPi A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mai Logic Incorporated"; +static const char pci_device_10cc_0660[] = "Articia S Host Bridge"; +static const char pci_device_10cc_0661[] = "Articia S PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Fujitsu Limited."; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0431[] = "MX98715"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8626[] = "Macronix MX86251 + 3Dfx Voodoo Rush"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +static const char pci_device_10dd_0100[] = "Lightning 1200"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c19[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1c[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c21[] = "Synergy II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c28[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c29[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2a[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2b[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c31[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c32[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c33[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c34[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_107d_2134[] = "WinFast 3D S320 II + TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2e[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2f[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c30[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c20[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c21[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3b[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "Pixelview RIVA TNT2 M64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1569_002d[] = "Palit Microsystems Daytona TNT2 M64"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0034[] = "MCP04 SMBus"; +static const char pci_device_10de_0035[] = "MCP04 IDE"; +static const char pci_device_10de_0036[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0037[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_0038[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_003a[] = "MCP04 AC'97 Audio Controller"; +static const char pci_device_10de_003b[] = "MCP04 USB Controller"; +static const char pci_device_10de_003c[] = "MCP04 USB Controller"; +static const char pci_device_10de_003d[] = "MCP04 PCI Bridge"; +static const char pci_device_10de_003e[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0040[] = "NV40 [GeForce 6800 Ultra]"; +static const char pci_device_10de_0041[] = "NV40 [GeForce 6800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0041_1043_817b[] = "V9999 Gamer Edition"; +#endif +static const char pci_device_10de_0042[] = "NV40.2 [GeForce 6800 LE]"; +static const char pci_device_10de_0043[] = "NV40.3"; +static const char pci_device_10de_0045[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0046[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0047[] = "NV40 [GeForce 6800 GS]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0047_1682_2109[] = "GeForce 6800 GS"; +#endif +static const char pci_device_10de_0048[] = "GeForce 6800 XT"; +static const char pci_device_10de_0049[] = "NV40GL"; +static const char pci_device_10de_004e[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_0050[] = "CK804 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0051[] = "CK804 ISA Bridge"; +static const char pci_device_10de_0052[] = "CK804 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0053[] = "CK804 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1458_5002[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0054[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0055[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1043_815a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_0056[] = "CK804 Ethernet Controller"; +static const char pci_device_10de_0057[] = "CK804 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1043_8141[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1458_e000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0058[] = "CK804 AC'97 Modem"; +static const char pci_device_10de_0059[] = "CK804 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_1043_812a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_005a[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005b[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005c[] = "CK804 PCI Bridge"; +static const char pci_device_10de_005d[] = "CK804 PCIE Bridge"; +static const char pci_device_10de_005e[] = "CK804 Memory Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1458_5000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005f[] = "CK804 Memory Controller"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +static const char pci_device_10de_0065[] = "nForce2 IDE"; +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0066_1043_80a7[] = "A7N8X Mainboard onboard nForce2 Ethernet"; +#endif +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +static const char pci_device_10de_006b[] = "nForce Audio Processing Unit"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006b_10de_006b[] = "nForce2 MCP Audio Processing Unit"; +#endif +static const char pci_device_10de_006c[] = "nForce2 External PCI Bridge"; +static const char pci_device_10de_006d[] = "nForce2 PCI Bridge"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +static const char pci_device_10de_0080[] = "MCP2A ISA bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0080_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0084[] = "MCP2A SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0084_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0085[] = "MCP2A IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0085_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0086[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_0087[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0087_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0088[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0088_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008a[] = "MCP2S AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_008a_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008b[] = "MCP2A PCI Bridge"; +static const char pci_device_10de_008c[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_008e[] = "nForce2 Serial ATA Controller"; +static const char pci_device_10de_0091[] = "GeForce 7800 GTX"; +static const char pci_device_10de_0092[] = "GeForce 7800 GT"; +static const char pci_device_10de_0099[] = "GeForce Go 7800 GTX"; +static const char pci_device_10de_009d[] = "Quadro FX 4500"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_00c0[] = "NV41.0"; +static const char pci_device_10de_00c1[] = "NV41.1 [GeForce 6800]"; +static const char pci_device_10de_00c2[] = "NV41.2 [GeForce 6800 LE]"; +static const char pci_device_10de_00c3[] = "GeForce 6800 XT"; +static const char pci_device_10de_00c8[] = "NV41.8 [GeForce Go 6800]"; +static const char pci_device_10de_00c9[] = "NV41.9 [GeForce Go 6800 Ultra]"; +static const char pci_device_10de_00cc[] = "NV41 [Quadro FX Go1400]"; +static const char pci_device_10de_00cd[] = "NV41 [Quadro FX 3450/4000 SDI]"; +static const char pci_device_10de_00ce[] = "NV41GL [Quadro FX 1400]"; +static const char pci_device_10de_00d0[] = "nForce3 LPC Bridge"; +static const char pci_device_10de_00d1[] = "nForce3 Host Bridge"; +static const char pci_device_10de_00d2[] = "nForce3 AGP Bridge"; +static const char pci_device_10de_00d3[] = "CK804 Memory Controller"; +static const char pci_device_10de_00d4[] = "nForce3 SMBus"; +static const char pci_device_10de_00d5[] = "nForce3 IDE"; +static const char pci_device_10de_00d6[] = "nForce3 Ethernet"; +static const char pci_device_10de_00d7[] = "nForce3 USB 1.1"; +static const char pci_device_10de_00d8[] = "nForce3 USB 2.0"; +static const char pci_device_10de_00d9[] = "nForce3 Audio"; +static const char pci_device_10de_00da[] = "nForce3 Audio"; +static const char pci_device_10de_00dd[] = "nForce3 PCI Bridge"; +static const char pci_device_10de_00df[] = "CK8S Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e0[] = "nForce3 250Gb LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e1[] = "nForce3 250Gb Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e2[] = "nForce3 250Gb AGP Host to PCI Bridge"; +static const char pci_device_10de_00e3[] = "CK8S Serial ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e4[] = "nForce 250Gb PCI System Management"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e5[] = "CK8S Parallel ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e6[] = "CK8S Ethernet Controller"; +static const char pci_device_10de_00e7[] = "CK8S USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e8[] = "nForce3 EHCI USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ea[] = "nForce3 250Gb AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ed[] = "nForce3 250Gb PCI-to-PCI Bridge"; +static const char pci_device_10de_00ee[] = "CK8S Serial ATA Controller (v2.5)"; +static const char pci_device_10de_00f0[] = "NV40 [GeForce 6800/GeForce 6800 Ultra]"; +static const char pci_device_10de_00f1[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1043_81a6[] = "N6600GT TD 128M AGP"; +#endif +static const char pci_device_10de_00f2[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f2_1682_211c[] = "GeForce 6600 256MB DDR DUAL DVI TV"; +#endif +static const char pci_device_10de_00f3[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_00f8[] = "NV45GL [Quadro FX 3400/4400]"; +static const char pci_device_10de_00f9[] = "NV40 [GeForce 6800 Ultra/GeForce 6800 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f9_1682_2120[] = "GEFORCE 6800 GT PCI-E"; +#endif +static const char pci_device_10de_00fa[] = "NV36 [GeForce PCX 5750]"; +static const char pci_device_10de_00fb[] = "NV35 [GeForce PCX 5900]"; +static const char pci_device_10de_00fc[] = "NV37GL [Quadro FX 330/GeForce PCX 5300]"; +static const char pci_device_10de_00fd[] = "NV37GL [Quadro FX 330/Quadro NVS280]"; +static const char pci_device_10de_00fe[] = "NV38GL [Quadro FX 1300]"; +static const char pci_device_10de_00ff[] = "NV18 [GeForce PCX 4300]"; +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c41[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c43[] = "ERAZOR X PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c48[] = "Synergy Force"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1048_0c42[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_107d_2822[] = "WinFast GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c40[] = "GLoria II-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c44[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c45[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4a[] = "GLoria II-64 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4b[] = "GLoria II-64 Pro DVII"; +#endif +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c60[] = "Gladiac MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c61[] = "Gladiac 511PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c63[] = "Gladiac 511TV-OUT 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c64[] = "Gladiac 511TV-OUT 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c65[] = "Gladiac 511TWIN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c66[] = "Gladiac 311"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_0091[] = "Dell OEM GeForce 2 MX 400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_00a1[] = "Apple OEM GeForce2 MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX/Go]"; +static const char pci_device_10de_0140[] = "NV43 [GeForce 6600 GT]"; +static const char pci_device_10de_0141[] = "NV43 [GeForce 6600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0141_1458_3124[] = "GV-NX66128DP Turbo Force Edition"; +#endif +static const char pci_device_10de_0142[] = "GeForce 6600 LE"; +static const char pci_device_10de_0144[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0145[] = "NV43 [GeForce 6610 XL]"; +static const char pci_device_10de_0146[] = "NV43 [Geforce Go 6600TE/6200TE]"; +static const char pci_device_10de_0147[] = "GeForce 6700 XL"; +static const char pci_device_10de_0148[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0149[] = "GeForce Go 6600 GT"; +static const char pci_device_10de_014e[] = "NV43GL [Quadro FX 540]"; +static const char pci_device_10de_014f[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c50[] = "Gladiac"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c52[] = "Gladiac-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2842[] = "WinFast GeForce 2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1462_5506[] = "Creative 3D Blaster Geforce2 Titanium"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0160[] = "GeForce 6500"; +static const char pci_device_10de_0161[] = "GeForce 6200 TurboCache(TM)"; +static const char pci_device_10de_0162[] = "GeForce 6200SE TurboCache(TM)"; +static const char pci_device_10de_0163[] = "GeForce 6200 LE"; +static const char pci_device_10de_0164[] = "NV44 [GeForce Go 6200]"; +static const char pci_device_10de_0165[] = "NV44 [Quadro NVS 285]"; +static const char pci_device_10de_0166[] = "GeForce Go 6400"; +static const char pci_device_10de_0167[] = "GeForce Go 6200"; +static const char pci_device_10de_0168[] = "GeForce Go 6400"; +static const char pci_device_10de_0169[] = "GeForce 6250"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10b0_0002[] = "Gainward Pro/600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10de_0008[] = "Apple OEM GeForce4 MX 440"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8852[] = "GeForce4 MX440 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_10de_0177[] = "NV17 [GeForce4 460 Go]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0179_10de_0179[] = "GeForce4 MX (Mac)"; +#endif +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 500 GoGL]"; +static const char pci_device_10de_017d[] = "NV17 [GeForce4 410 Go 16M]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_806f[] = "V9180 Magic"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8880[] = "MS-StarForce GeForce4 MX 440 with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8900[] = "MS-8890 GeForce 4 MX440 AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_9350[] = "MSI Geforce4 MX T8X with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_147b_8f0d[] = "Siluro GF4 MX-8X"; +#endif +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0185[] = "NV18 [GeForce4 MX 4000 AGP 8x]"; +static const char pci_device_10de_0186[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_0187[] = "NV18M [GeForce4 488 Go]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS AGP 8x]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_018c[] = "Quadro NVS 50 PC"; +static const char pci_device_10de_018d[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_01a0[] = "NVCrush11 [GeForce2 MX Integrated Graphics]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b0[] = "nForce Audio"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "nForce AC'97 Modem Controller"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01e0[] = "nForce2 AGP (different version?)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01e0_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01ea[] = "nForce2 Memory Controller 0"; +static const char pci_device_10de_01eb[] = "nForce2 Memory Controller 1"; +static const char pci_device_10de_01ec[] = "nForce2 Memory Controller 2"; +static const char pci_device_10de_01ed[] = "nForce2 Memory Controller 3"; +static const char pci_device_10de_01ee[] = "nForce2 Memory Controller 4"; +static const char pci_device_10de_01ef[] = "nForce2 Memory Controller 5"; +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1048_0c70[] = "GLADIAC 920"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0211[] = "GeForce 6800"; +static const char pci_device_10de_0212[] = "GeForce 6800 LE"; +static const char pci_device_10de_0215[] = "GeForce 6800 GT"; +static const char pci_device_10de_0221[] = "GeForce 6200"; +static const char pci_device_10de_0240[] = "C51PV [GeForce 6150]"; +static const char pci_device_10de_0241[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0242[] = "C51G [GeForce 6100]"; +static const char pci_device_10de_0243[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0244[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0245[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0246[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0247[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0248[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0249[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024a[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024b[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024c[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024d[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024e[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024f[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0251_1043_8023[] = "v8440 GeForce 4 Ti4400"; +#endif +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0260[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0261[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0262[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0263[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0264[] = "MCP51 SMBus"; +static const char pci_device_10de_0265[] = "MCP51 IDE"; +static const char pci_device_10de_0266[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0267[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0268[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_0269[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_026a[] = "MCP51 MCI"; +static const char pci_device_10de_026b[] = "MCP51 AC97 Audio Controller"; +static const char pci_device_10de_026c[] = "MCP51 High Definition Audio"; +static const char pci_device_10de_026d[] = "MCP51 USB Controller"; +static const char pci_device_10de_026e[] = "MCP51 USB Controller"; +static const char pci_device_10de_026f[] = "MCP51 PCI Bridge"; +static const char pci_device_10de_0270[] = "MCP51 Host Bridge"; +static const char pci_device_10de_0271[] = "MCP51 PMU"; +static const char pci_device_10de_0272[] = "MCP51 Memory Controller 0"; +static const char pci_device_10de_027e[] = "C51 Memory Controller 2"; +static const char pci_device_10de_027f[] = "C51 Memory Controller 3"; +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0286[] = "NV28 [GeForce4 Ti 4200 Go AGP 8x]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_028c[] = "NV28GLM [Quadro4 700 GoGL]"; +static const char pci_device_10de_02a0[] = "NV2A [XGPU]"; +static const char pci_device_10de_02f0[] = "C51 Host Bridge"; +static const char pci_device_10de_02f1[] = "C51 Host Bridge"; +static const char pci_device_10de_02f2[] = "C51 Host Bridge"; +static const char pci_device_10de_02f3[] = "C51 Host Bridge"; +static const char pci_device_10de_02f4[] = "C51 Host Bridge"; +static const char pci_device_10de_02f5[] = "C51 Host Bridge"; +static const char pci_device_10de_02f6[] = "C51 Host Bridge"; +static const char pci_device_10de_02f7[] = "C51 Host Bridge"; +static const char pci_device_10de_02f8[] = "C51 Memory Controller 5"; +static const char pci_device_10de_02f9[] = "C51 Memory Controller 4"; +static const char pci_device_10de_02fa[] = "C51 Memory Controller 0"; +static const char pci_device_10de_02fb[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fc[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fd[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fe[] = "C51 Memory Controller 1"; +static const char pci_device_10de_02ff[] = "C51 Host Bridge"; +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +static const char pci_device_10de_0311[] = "NV31 [GeForce FX 5600 Ultra]"; +static const char pci_device_10de_0312[] = "NV31 [GeForce FX 5600]"; +static const char pci_device_10de_0313[] = "NV31"; +static const char pci_device_10de_0314[] = "GeForce FX 5600SE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0314_1043_814a[] = "V9560XT/TD"; +#endif +static const char pci_device_10de_0316[] = "NV31M"; +static const char pci_device_10de_0317[] = "NV31M Pro"; +static const char pci_device_10de_031a[] = "NV31M [GeForce FX Go5600]"; +static const char pci_device_10de_031b[] = "NV31M [GeForce FX Go5650]"; +static const char pci_device_10de_031c[] = "NVIDIA Quadro FX Go700"; +static const char pci_device_10de_031d[] = "NV31GLM"; +static const char pci_device_10de_031e[] = "NV31GLM Pro"; +static const char pci_device_10de_031f[] = "NV31GLM Pro"; +static const char pci_device_10de_0320[] = "NV34 [GeForce FX 5200]"; +static const char pci_device_10de_0321[] = "NV34 [GeForce FX 5200 Ultra]"; +static const char pci_device_10de_0322[] = "NV34 [GeForce FX 5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9171[] = "MS-8917 (FX5200-T128)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9360[] = "MS-8936 (FX5200-T128)"; +#endif +static const char pci_device_10de_0323[] = "GeForce FX 5200SE"; +static const char pci_device_10de_0324[] = "NV34M [GeForce FX Go5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_10de_0325[] = "NV34M [GeForce FX Go5250]"; +static const char pci_device_10de_0326[] = "NV34 [GeForce FX 5500]"; +static const char pci_device_10de_0327[] = "NV34 [GeForce FX 5100]"; +static const char pci_device_10de_0328[] = "NV34M [GeForce FX Go5200 32M/64M]"; +static const char pci_device_10de_0329[] = "GeForce FX 5200 (Mac)"; +static const char pci_device_10de_032a[] = "NV34GL [Quadro NVS 280 PCI]"; +static const char pci_device_10de_032b[] = "NV34GL [Quadro FX 500/600 PCI]"; +static const char pci_device_10de_032c[] = "NV34GLM [GeForce FX Go 5300]"; +static const char pci_device_10de_032d[] = "NV34 [GeForce FX Go5100]"; +static const char pci_device_10de_032f[] = "NV34GL"; +static const char pci_device_10de_0330[] = "NV35 [GeForce FX 5900 Ultra]"; +static const char pci_device_10de_0331[] = "NV35 [GeForce FX 5900]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0331_1043_8145[] = "V9950GE"; +#endif +static const char pci_device_10de_0332[] = "NV35 [GeForce FX 5900XT]"; +static const char pci_device_10de_0333[] = "NV38 [GeForce FX 5950 Ultra]"; +static const char pci_device_10de_0334[] = "NV35 [GeForce FX 5900ZT]"; +static const char pci_device_10de_0338[] = "NV35GL [Quadro FX 3000]"; +static const char pci_device_10de_033f[] = "NV35GL [Quadro FX 700]"; +static const char pci_device_10de_0341[] = "NV36.1 [GeForce FX 5700 Ultra]"; +static const char pci_device_10de_0342[] = "NV36.2 [GeForce FX 5700]"; +static const char pci_device_10de_0343[] = "NV36 [GeForce FX 5700LE]"; +static const char pci_device_10de_0344[] = "NV36.4 [GeForce FX 5700VE]"; +static const char pci_device_10de_0345[] = "NV36.5"; +static const char pci_device_10de_0347[] = "NV36 [GeForce FX Go5700]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0347_103c_006a[] = "nx9500"; +#endif +static const char pci_device_10de_0348[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0349[] = "NV36M Pro"; +static const char pci_device_10de_034b[] = "NV36MAP"; +static const char pci_device_10de_034c[] = "NV36 [Quadro FX Go1000]"; +static const char pci_device_10de_034e[] = "NV36GL [Quadro FX 1100]"; +static const char pci_device_10de_034f[] = "NV36GL"; +static const char pci_device_10de_0360[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0361[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0362[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0363[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0364[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0365[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0366[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0367[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0368[] = "MCP55 SMBus"; +static const char pci_device_10de_0369[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036c[] = "MCP55 USB Controller"; +static const char pci_device_10de_036d[] = "MCP55 USB Controller"; +static const char pci_device_10de_036e[] = "MCP55 IDE"; +static const char pci_device_10de_0371[] = "MCP55 High Definition Audio"; +static const char pci_device_10de_0372[] = "MCP55 Ethernet"; +static const char pci_device_10de_0373[] = "MCP55 Ethernet"; +static const char pci_device_10de_037a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_037e[] = "MCP55 SATA Controller"; +static const char pci_device_10de_037f[] = "MCP55 SATA Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Host Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Host Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a1[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a5[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0b5[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d1[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d5[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e1[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e5[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0f5[] = "Neptune LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f701[] = "LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f801[] = "LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f901[] = "LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Host Adapter"; +static const char pci_device_10df_f981[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_f982[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_fa00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fb00[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc10[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc20[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fd00[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fe00[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_ff00[] = "Neptune LightPulse Fibre Channel Host Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0148[] = "Tsi148 [Tempe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +static const char pci_device_10e3_8260[] = "CA91L8200B [Dual PCI PowerSpan II]"; +static const char pci_device_10e3_8261[] = "CA91L8260B [Single PCI PowerSpan II]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +static const char pci_device_10e4_8029[] = "Realtek 8029 Network Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_1072[] = "INES GPIB-PCI (AMCC5920 based)"; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_814c[] = "Fastcom ESCC-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_81e6[] = "Multimedia video controller"; +static const char pci_device_10e8_8291[] = "Fastcom 232/8-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c4[] = "Fastcom 422/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c5[] = "Fastcom 422/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c6[] = "Fastcom IG422/1-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c7[] = "Fastcom IG232/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82ca[] = "Fastcom 232/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +static const char pci_device_10e8_82e2[] = "Fastcom DIO24H-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8851[] = "S5933 on Innes Corp FM Radio Capture card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +static const char pci_device_10ea_5252[] = "CyberPro5252"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_0139[] = "Zonet Zen3200"; +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1043_8109[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1113_ec01[] = "FNC-0107TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1458_e000[] = "GA-7VM400M/7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1462_788c[] = "865PE Neo2-V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_14cb_0200[] = "LNR-100 Family 10/100 Base-TX Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1799_5000[] = "F5D5000 PCI Card/Desktop Network PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_9001_1695[] = "Onboard RTL8101L 10/100 MBit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8169[] = "RTL-8169 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1259_c107[] = "CG-LAPCIGT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1458_e000[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1462_702c[] = "K8T NEO 2 motherboard"; +#endif +static const char pci_device_10ec_8180[] = "RTL8180L 802.11b MAC"; +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_0205[] = "Wildcard TE205P"; +static const char pci_device_10ee_0210[] = "Wildcard TE210P"; +static const char pci_device_10ee_0314[] = "Wildcard TE405P/TE410P (1st Gen)"; +static const char pci_device_10ee_0405[] = "Wildcard TE405P (2nd Gen)"; +static const char pci_device_10ee_0410[] = "Wildcard TE410P (2nd Gen)"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +static const char pci_device_10ee_3fc6[] = "RME Hammerfall DSP MADI"; +static const char pci_device_10ee_8381[] = "Ellips Santos Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft fuer Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +static const char pci_device_1101_9502[] = "Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_100a[] = "SB Live! 5.1 Digital OEM [SB0220]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8064[] = "SBLive! 5.1 Model SB0100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8065[] = "SBLive! 5.1 Digital Model SB0220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8067[] = "SBLive! 5.1 eMicro 28028"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0058[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_1007[] = "SB0240 Audigy 2 Platinum 6.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_2002[] = "SB Audigy 2 ZS (SB0350)"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_0007[] = "SB Audigy LS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_0007[] = "SBLive! 24bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1001[] = "SB0310 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1002[] = "SB0312 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1006[] = "SB0410 SBLive! 24-bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1462_1009[] = "K8N Diamond"; +#endif +static const char pci_device_1102_0008[] = "SB0400 Audigy2 Value"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0008_1102_0008[] = "EMU0404 Digital Audio System"; +#endif +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! MIDI/Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_7005[] = "SB Audigy LS MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1001[] = "SB0310 Audigy LS MIDI/Game port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1002[] = "SB0312 Audigy LS MIDI/Game port"; +#endif +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "Ectiva EV1938"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1033_80e5[] = "SlimTower-Jim (NEC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1071_7150[] = "Mitac 7150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_110a_5938[] = "Siemens Scenic Mobile 510PIII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100c[] = "Ceres-C (Sharp, Intel BX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100d[] = "Sharp, Intel Banister"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100e[] = "TwinHead P09S/P09S3 (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_f6f1[] = "Marlin (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_0e70[] = "P88TE (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_c401[] = "Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b400[] = "G400 - Geo (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b550[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b560[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b700[] = "G700/U700 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b795[] = "G795 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b797[] = "G797 (AlphaTop (Taiwan))"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372/372N"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0003[] = "HPT343 / HPT345 / HPT363 UDMA33"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0004[] = "HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0006[] = "HPT302"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0007[] = "HPT371 UDMA133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0008[] = "HPT374 UDMA/ATA133 RAID Controller"; +#endif +static const char pci_device_1103_0005[] = "HPT372A/372N"; +static const char pci_device_1103_0006[] = "HPT302"; +static const char pci_device_1103_0007[] = "HPT371/371N"; +static const char pci_device_1103_0008[] = "HPT374"; +static const char pci_device_1103_0009[] = "HPT372N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +static const char pci_device_1105_8401[] = "EM8401 REALmagic DVD/MPEG-2 A/V Decoder"; +static const char pci_device_1105_8470[] = "EM8470 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8471[] = "EM8471 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8475[] = "EM8475 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8475_1105_0001[] = "REALmagic X-Card"; +#endif +static const char pci_device_1105_8476[] = "EM8476 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8476_127d_0000[] = "CineView II"; +#endif +static const char pci_device_1105_8485[] = "EM8485 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8486[] = "EM8486 REALmagic DVD/MPEG-4 A/V Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_0238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_0259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_0269[] = "KT880 Host Bridge"; +static const char pci_device_1106_0282[] = "K8T800Pro Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0282_1043_80a3[] = "A8V Deluxe"; +#endif +static const char pci_device_1106_0290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_0296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1019_0987[] = "K7VZA (Rev. 1.0) Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0308[] = "PT894 Host Bridge"; +static const char pci_device_1106_0314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C576MV"; +static const char pci_device_1106_0571[] = "VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_808c[] = "A7V8X / A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80a1[] = "A7V8X-X motherboard rev. 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1849_0571[] = "K7VT2 / K7VT6 motherboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0591[] = "VT8237A SATA 2-Port Controller"; +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0605_1043_802c[] = "CUV4X mainboard"; +#endif +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_802c[] = "CUV4X mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_1208[] = "PT890 Host Bridge"; +static const char pci_device_1106_1238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_1258[] = "PT880 Host Bridge"; +static const char pci_device_1106_1259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_1269[] = "KT880 Host Bridge"; +static const char pci_device_1106_1282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_1290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_1296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_1308[] = "PT894 Host Bridge"; +static const char pci_device_1106_1314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_1571[] = "VT82C576M/VT82C586"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_2204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_2208[] = "PT890 Host Bridge"; +static const char pci_device_1106_2238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_2258[] = "PT880 Host Bridge"; +static const char pci_device_1106_2259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_2269[] = "KT880 Host Bridge"; +static const char pci_device_1106_2282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_2290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_2296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_2308[] = "PT894 Host Bridge"; +static const char pci_device_1106_2314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_287a[] = "VT8251 PCI to PCI Bridge"; +static const char pci_device_1106_287b[] = "VT8251 PCI to PCIE Bridge"; +static const char pci_device_1106_287c[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287d[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287e[] = "VT8251 Ultra VLINK Controller"; +static const char pci_device_1106_3022[] = "CLE266"; +static const char pci_device_1106_3038[] = "VT82xxxxx UHCI USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_8080[] = "A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_808c[] = "VT6202 USB2.0 4 port controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_182d_201d[] = "CN-029 USB2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1849_3038[] = "K7VT6"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_0574_086c[] = "K8N Diamond"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1043_808a[] = "A8V Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1458_1000[] = "GA-7VT600-1394 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_702d[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_971d[] = "MS-6917"; +#endif +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3053[] = "VT6105M [Rhine-III]"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_0097[] = "SoundMax Digital Integrated Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1043_1106[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3300[] = "MS-6330 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233/A/8235/8237 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_8095[] = "A7V8X Motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80b0[] = "A7V600/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX])"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_812a[] = "A8V Deluxe motherboard (Realtek ALC850 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_3059[] = "L7VMM2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4161[] = "K7VT2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1297_c160[] = "FX41 motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_0080[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_3800[] = "KT266 onboard audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1849_9761[] = "K7VT6 motherboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4005_4710[] = "MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4170_1106[] = "PCPartner P4M800-8237R Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4552_1106[] = "Soyo KT-600 Dragon Plus (Realtek ALC 650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_a0a0_01b6[] = "AK77-8XN onboard audio"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_13b9_1421[] = "LD-10/100AL PCI Fast Ethernet Adapter (rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_147b_1c09[] = "NV7 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_3005[] = "VT6103"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_300c[] = "Realtek ALC655 sound chip"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1849_3065[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3068[] = "AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3068_1462_309e[] = "MS-6309 Saturn Motherboard"; +#endif +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1849_3099[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80a1[] = "A7V8X-X motherboard rev 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_182d_201d[] = "CN-029 USB 2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1849_3104[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3106_1186_1403[] = "DFE-530TX rev C"; +#endif +static const char pci_device_1106_3108[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3113[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3116[] = "VT8375 [KM266/KL266] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3116_1297_f641[] = "FX41 motherboard"; +#endif +static const char pci_device_1106_3118[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3119[] = "VT6120/VT6121/VT6122 Gigabit Ethernet Adapter"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3147_1043_808c[] = "A7V333 motherboard"; +#endif +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3149[] = "VIA VT6420 SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1043_80ed[] = "A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1458_b003[] = "GA-7VM400AM(F) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1462_7020[] = "K8T Neo 2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1408[] = "KV7"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1849_3149[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3164[] = "VT6410 ATA133 RAID controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1043_80f4[] = "P4P800 Mainboard Deluxe ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1849_3177[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3178[] = "ProSavageDDR P4N333 Host Bridge"; +static const char pci_device_1106_3188[] = "VT8385 [K8T800 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_1043_80a3[] = "K8V Deluxe/K8V-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400/KT600 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1043_807f[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1849_3189[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_3205[] = "VT8378 [KM400/A] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3205_1458_5000[] = "GA-7VM400M Motherboard"; +#endif +static const char pci_device_1106_3208[] = "PT890 Host Bridge"; +static const char pci_device_1106_3213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3218[] = "K8T800M Host Bridge"; +static const char pci_device_1106_3227[] = "VT8237 ISA bridge [KT600/K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1106_3227[] = "DFI KT600-AL Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1458_5001[] = "GA-7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1849_3227[] = "K7VT4 motherboard"; +#endif +static const char pci_device_1106_3238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_3249[] = "VT6421 IDE RAID Controller"; +static const char pci_device_1106_3258[] = "PT880 Host Bridge"; +static const char pci_device_1106_3259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_3269[] = "KT880 Host Bridge"; +static const char pci_device_1106_3282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_3287[] = "VT8251 PCI to ISA Bridge"; +static const char pci_device_1106_3288[] = "VIA High Definition Audio Controller"; +static const char pci_device_1106_3290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_3296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_3337[] = "VT8237A PCI to ISA Bridge"; +static const char pci_device_1106_3344[] = "UniChrome Pro IGP"; +static const char pci_device_1106_3349[] = "VT8251 AHCI/SATA 4-Port Controller"; +static const char pci_device_1106_337a[] = "VT8237A PCI to PCI Bridge"; +static const char pci_device_1106_337b[] = "VT8237A PCI to PCIE Bridge"; +static const char pci_device_1106_4149[] = "VIA VT6420 (ATA133) Controller"; +static const char pci_device_1106_4204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_4208[] = "PT890 Host Bridge"; +static const char pci_device_1106_4238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_4258[] = "PT880 Host Bridge"; +static const char pci_device_1106_4259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_4269[] = "KT880 Host Bridge"; +static const char pci_device_1106_4282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_4290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_4296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_4308[] = "PT894 Host Bridge"; +static const char pci_device_1106_4314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_5208[] = "PT890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5238[] = "K8T890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5290[] = "K8M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5308[] = "PT894 I/O APIC Interrupt Controller"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_7204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_7205[] = "VT8378 [S3 UniChrome] Integrated Video"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_7205_1458_d000[] = "Gigabyte GA-7VM400(A)M(F) Motherboard"; +#endif +static const char pci_device_1106_7208[] = "PT890 Host Bridge"; +static const char pci_device_1106_7238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_7258[] = "PT880 Host Bridge"; +static const char pci_device_1106_7259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_7269[] = "KT880 Host Bridge"; +static const char pci_device_1106_7282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_7290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_7296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_7308[] = "PT894 Host Bridge"; +static const char pci_device_1106_7314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_8598_1019_0985[] = "P6VXA Motherboard"; +#endif +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_a208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b113[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b115[] = "VT8363/8365 [KT133/KM133] PCI Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +static const char pci_device_1106_b188[] = "VT8237 PCI bridge [K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_b188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_b198[] = "VT8237 PCI Bridge"; +static const char pci_device_1106_b213[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_c208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d104[] = "VT8237 Integrated Fast Ethernet Controller"; +static const char pci_device_1106_d208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f238[] = "K8T890 PCI to PCI Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_0006[] = "FSC PINC (I/O-APIC)"; +static const char pci_device_110a_0015[] = "FSC Multiprocessor Interrupt Controller"; +static const char pci_device_110a_001d[] = "FSC Copernicus Management Controller"; +static const char pci_device_110a_007b[] = "FSC Remote Service Controller, mailbox device"; +static const char pci_device_110a_007c[] = "FSC Remote Service Controller, shared memory device"; +static const char pci_device_110a_007d[] = "FSC Remote Service Controller, SMIC device"; +static const char pci_device_110a_2101[] = "HST SAPHIR V Primary PCI (ISDN/PMx)"; +static const char pci_device_110a_2102[] = "DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels"; +static const char pci_device_110a_2104[] = "Eicon Diva 2.02 compatible passive ISDN card"; +static const char pci_device_110a_3142[] = "SIMATIC NET CP 5613A1 (Profibus Adapter)"; +static const char pci_device_110a_4021[] = "SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter)"; +static const char pci_device_110a_4029[] = "SIMATIC NET CP 5613A2 (Profibus Adapter)"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_1113_2242[] = "EN2242 10/100 Ethernet Mini-PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "21x4x DEC-Tulip compatible Fast Ethernet"; +static const char pci_device_1113_d301[] = "CPWNA100 (Philips wireless PCMCIA)"; +static const char pci_device_1113_ec02[] = "SMC 1244TX v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +static const char pci_device_1114_0506[] = "at76c506 802.11b Wireless Network Adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6117/6517"; +static const char pci_device_1119_0007[] = "GDT 6127/6527"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557/6557-ECC"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0010[] = "GDT 6115/6515"; +static const char pci_device_1119_0011[] = "GDT 6125/6525"; +static const char pci_device_1119_0012[] = "GDT 6535"; +static const char pci_device_1119_0013[] = "GDT 6555/6555-ECC"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_02ff[] = "GDT MAXRP"; +static const char pci_device_1119_0300[] = "GDT NEWRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +static const char pci_device_111a_1203[] = "SpeedStream 1023 Wireless PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Technology, Inc."; +static const char pci_device_111d_0001[] = "IDT77201/77211 155Mbps ATM SAR Controller [NICStAR]"; +static const char pci_device_111d_0003[] = "IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0004[] = "IDT77V252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0005[] = "IDT77V222 155Mbps ATM MICRO ABR SAR Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +static const char pci_device_112f_0008[] = "PC-CamLink PCI framegrabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_5400[] = "TriMedia TM1000/1100"; +static const char pci_device_1131_5402[] = "TriMedia TM-1300"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_5402_1244_0f00[] = "Fritz!Card DSL"; +#endif +static const char pci_device_1131_5405[] = "TriMedia TM1500"; +static const char pci_device_1131_5406[] = "TriMedia TM1700"; +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_102b_48d0[] = "Matrox CronosPlus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1048_226b[] = "ELSA EX-VISION 300TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2001[] = "10MOONS PCI TV CAPTURE CARD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2005[] = "Techcom (India) TV Tuner Card (SSD-TV-670)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_050c[] = "Nagase Sangyo TransGear 3000TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_10ff[] = "AVerMedia DVD EZMaker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2108[] = "AverMedia AverTV/305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2115[] = "AverMedia AverTV Studio 305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_153b_1152[] = "Terratec Cinergy 200 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c100[] = "Compro VideoMate TV PVR/FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c901[] = "Videomate DVB-T200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_5168_0138[] = "LifeView FlyVIDEO2000"; +#endif +static const char pci_device_1131_7133[] = "SAA7133/SAA7135 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_0000_4091[] = "Beholder BeholdTV 409 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_002b_11bd[] = "Pinnacle PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1019_4cb5[] = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_0210[] = "FlyTV mini Asus Digimatrix"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4843[] = "ASUS TV-FM 7133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4845[] = "TV-FM 7135"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4862[] = "P7131 Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2001[] = "Proteus Pro [philips reference design]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2018[] = "Tiger reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_4ee9[] = "MonsterTV Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_11bd_002e[] = "PCTV 110i (saa7133)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_12ab_0800[] = "PURPLE TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1421_1370[] = "Instant TV (saa7135)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7330[] = "VFG7330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7350[] = "VFG7350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_1044[] = "AVerTVHD MCE A180"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_f31f[] = "Avermedia AVerTV GO 007 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1462_6231[] = "TV@Anywhere plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1489_0214[] = "LifeView FlyTV Platinum FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_14c0_1212[] = "LifeView FlyTV Platinum Mini2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1160[] = "Cinergy 250 PCI TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1162[] = "Terratec Cinergy 400 mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_185b_c100[] = "VideoMate TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_4e42_0212[] = "LifeView FlyTV Platinum Mini"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_4e42_0502[] = "Typhoon DVB-T Duo Digital/Analog Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0306[] = "LifeView FlyDVB-T DUO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0319[] = "LifeView FlyDVB Trio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5456_7135[] = "GoTView 7135 PCI"; +#endif +static const char pci_device_1131_7134[] = "SAA7134 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1019_4cb4[] = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_0210[] = "Digimatrix TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4840[] = "ASUS TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_2004[] = "EUROPA V3 reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_4e85[] = "SKNet Monster TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_6752[] = "EMPRESS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_7133[] = "AOPEN VA1000 POWER"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002b[] = "Pinnacle PCTV Stereo (saa7134)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002d[] = "Pinnacle PCTV 300i DVB-T + PAL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_9715[] = "AVerTV Studio 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70a[] = "Avermedia AVerTV 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70b[] = "AverMedia M156 / Medion 2819"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_d6ee[] = "Cardbus TV/Radio (E500)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1471_b7e9[] = "AVerTV Cardbus plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1142[] = "Terratec Cinergy 400 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1143[] = "Terratec Cinergy 600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1158[] = "Terratec Cinergy 600 TV MK3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1540_9524[] = "ProVideo PV952"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_16be_0003[] = "Medion 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c200[] = "Compro VideoMate Gold+ Pal"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c900[] = "Videomate DVB-T300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_a006[] = "KNC One TV-Station DVR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_fe01[] = "KNC One TV-Station RDS / Typhoon TV Tuner RDS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_4e42_0138[] = "LifeView FlyVIDEO3000"; +#endif +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_0000[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_ffff[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f56[] = "KNC1 DVB-S Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f60[] = "Fujitsu-Siemens Activy DVB-S Budget Rev AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f61[] = "Activy DVB-S Budget Rev GR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_5f61[] = "Activy DVB-T Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000f[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0000[] = "Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0001[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0002[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0003[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0004[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0006[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0008[] = "Technotrend/Hauppauge DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_000a[] = "Octal/Technotrend DVB-C for iTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1003[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-S DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1004[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-C DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1005[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100c[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100f[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1011[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1013[] = "SATELCO Multimedia DVB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1016[] = "WinTV-NOVA-SE DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1102[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +static const char pci_device_1131_9730[] = "SAA9730 Integrated Multimedia and Peripheral Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Networks Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "Diva Pro 2.0 S/T"; +static const char pci_device_1133_e002[] = "Diva 2.0 S/T PCI"; +static const char pci_device_1133_e003[] = "Diva Pro 2.0 U"; +static const char pci_device_1133_e004[] = "Diva 2.0 U PCI"; +static const char pci_device_1133_e005[] = "Diva 2.01 S/T PCI"; +static const char pci_device_1133_e006[] = "Diva CT S/T PCI"; +static const char pci_device_1133_e007[] = "Diva CT U PCI"; +static const char pci_device_1133_e008[] = "Diva CT Lite S/T PCI"; +static const char pci_device_1133_e009[] = "Diva CT Lite U PCI"; +static const char pci_device_1133_e00a[] = "Diva ISDN+V.90 PCI"; +static const char pci_device_1133_e00b[] = "Diva 2.02 PCI S/T"; +static const char pci_device_1133_e00c[] = "Diva 2.02 PCI U"; +static const char pci_device_1133_e00d[] = "Diva ISDN Pro 3.0 PCI"; +static const char pci_device_1133_e00e[] = "Diva ISDN+CT S/T PCI Rev 2"; +static const char pci_device_1133_e010[] = "Diva Server BRI-2M PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_110a_0021[] = "Fujitsu Siemens ISDN S0"; +#endif +static const char pci_device_1133_e011[] = "Diva Server BRI S/T Rev 2"; +static const char pci_device_1133_e012[] = "Diva Server 4BRI-8M PCI"; +static const char pci_device_1133_e013[] = "Diva Server 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_1300[] = "Diva Server V-4BRI-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_e013[] = "Diva Server 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e014[] = "Diva Server PRI-30M PCI"; +static const char pci_device_1133_e015[] = "DIVA Server PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e015_1133_e015[] = "Diva Server PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e016[] = "Diva Server Voice 4BRI PCI"; +static const char pci_device_1133_e017[] = "Diva Server Voice 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e017_1133_e017[] = "Diva Server Voice 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_1800[] = "Diva Server V-BRI-2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e019[] = "Diva Server Voice PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e019_1133_e019[] = "Diva Server Voice PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e01a[] = "Diva Server 2FX"; +static const char pci_device_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01b_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e01c[] = "Diva Server PRI Rev 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c01[] = "Diva Server PRI/E1/T1-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c02[] = "Diva Server PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c03[] = "Diva Server PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c04[] = "Diva Server PRI/E1/T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c05[] = "Diva Server V-PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c06[] = "Diva Server V-PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c07[] = "Diva Server PRI/E1/T1-8 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c08[] = "Diva Server PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c09[] = "Diva Server PRI/E1-30 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0a[] = "Diva Server PRI/E1/T1 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0b[] = "Diva Server V-PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0c[] = "Diva Server V-PRI/E1-30 Cornet NQ"; +#endif +static const char pci_device_1133_e01e[] = "Diva Server 2PRI"; +static const char pci_device_1133_e020[] = "Diva Server 4PRI"; +static const char pci_device_1133_e024[] = "Diva Server Analog-4P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_2400[] = "Diva Server V-Analog-4P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_e024[] = "Diva Server Analog-4P"; +#endif +static const char pci_device_1133_e028[] = "Diva Server Analog-8P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_2800[] = "Diva Server V-Analog-8P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_e028[] = "Diva Server Analog-8P"; +#endif +static const char pci_device_1133_e02a[] = "Diva Server IPM-300"; +static const char pci_device_1133_e02c[] = "Diva Server IPM-600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +static const char pci_device_1134_0002[] = "Dual PCI to RapidIO Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +static const char pci_device_1145_f020[] = "NinjaSCSI-32 Sony PCGA-DVD51"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "SysKonnect"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2971[] = "AT-2970LX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970TX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2973[] = "AT-2971SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2974[] = "AT-2971T Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2976[] = "AT-2970LX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970TX/2TX Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1148_4320[] = "SysKonnect SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0121[] = "Marvell RDK-8001 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0221[] = "Marvell RDK-8002 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0321[] = "Marvell RDK-8003 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0421[] = "Marvell RDK-8004 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0621[] = "Marvell RDK-8006 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0721[] = "Marvell RDK-8007 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0821[] = "Marvell RDK-8008 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0921[] = "Marvell RDK-8009 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1121[] = "Marvell RDK-8011 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1221[] = "Marvell RDK-8012 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_3221[] = "SK-9521 V2.0 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "SK-9Dxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_4500[] = "SK-9Mxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_9000[] = "SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45"; +static const char pci_device_1148_9843[] = "[Fujitsu] Gigabit Ethernet"; +static const char pci_device_1148_9e00[] = "SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2100[] = "SK-9E21 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_21d0[] = "SK-9E21D 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2200[] = "SK-9E22 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8100[] = "SK-9E81 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8200[] = "SK-9E82 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9100[] = "SK-9E91 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9200[] = "SK-9E92 Server Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0028[] = "ClassicBoard 4"; +static const char pci_device_114f_0029[] = "ClassicBoard 8"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p"; +static const char pci_device_114f_0043[] = "AccelePort 4p"; +static const char pci_device_114f_0044[] = "AccelePort 8p"; +static const char pci_device_114f_0045[] = "AccelePort 16p"; +static const char pci_device_114f_004e[] = "AccelePort 32p"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_00b0[] = "Digi Neo 4"; +static const char pci_device_114f_00b1[] = "Digi Neo 8"; +static const char pci_device_114f_00c8[] = "Digi Neo 2 DB9"; +static const char pci_device_114f_00c9[] = "Digi Neo 2 DB9 PRI"; +static const char pci_device_114f_00ca[] = "Digi Neo 2 RJ45"; +static const char pci_device_114f_00cb[] = "Digi Neo 2 RJ45 PRI"; +static const char pci_device_114f_00d0[] = "ClassicBoard 4 422"; +static const char pci_device_114f_00d1[] = "ClassicBoard 8 422"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0182[] = "RealPort2 CardBus Ethernet 10/100 (R2BE-100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_00d4[] = "Mini-PCI K56Flex Modem"; +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "Broadcom"; +static const char pci_device_1166_0000[] = "CMIC-LE"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0006[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-WS Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CMIC-LE Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0036[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0101[] = "CIOB-X2 PCI-X I/O Bridge"; +static const char pci_device_1166_0104[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0110[] = "CIOB-E I/O Bridge with Gigabit Ethernet"; +static const char pci_device_1166_0130[] = "HT1000 PCI-X bridge"; +static const char pci_device_1166_0132[] = "HT1000 PCI-Express bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0201_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0203_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0205[] = "HT1000 Legacy South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0212_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_c134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0214[] = "HT1000 Legacy IDE controller"; +static const char pci_device_1166_0217[] = "CSB6 IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0217_1028_4134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0220_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0221_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0223[] = "HT1000 USB Controller"; +static const char pci_device_1166_0225[] = "CSB5 LPC bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0227_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0230[] = "CSB5 LPC bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0230_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0234[] = "HT1000 LPC Bridge"; +static const char pci_device_1166_0240[] = "K2 SATA"; +static const char pci_device_1166_0241[] = "RAIDCore RC4000"; +static const char pci_device_1166_0242[] = "RAIDCore BC4000"; +static const char pci_device_1166_024a[] = "BCM5785 (HT1000) SATA Native SATA Mode"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0102[] = "Extended IDE Controller"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "CPU to PCI bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0601_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_060a_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC100 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +static const char pci_device_117c_0030[] = "Ultra320 SCSI Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8013[] = "ExpressPCI UL4D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8014[] = "ExpressPCI UL4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1987[] = "Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines )"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_14ef_0220[] = "PCD-RP-220S"; +#endif +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0511[] = "R5C511"; +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1180_0554[] = "R5C554"; +static const char pci_device_1180_0575[] = "R5C575 SD Bus Host Adapter"; +static const char pci_device_1180_0576[] = "R5C576 SD Bus Host Adapter"; +static const char pci_device_1180_0592[] = "R5C592 Memory Stick Bus Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0811[] = "R5C811"; +static const char pci_device_1180_0822[] = "R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0556[] = "Thinkpad X40"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_01a2[] = "Inspiron 9200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1043_1967[] = "ASUS V6800V"; +#endif +static const char pci_device_1180_0841[] = "R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394"; +static const char pci_device_1180_0852[] = "xD-Picture Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0852_1043_1967[] = "V6800V"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1025[] = "AirPlus Xtreme G DWL-G650 Adapter"; +static const char pci_device_1186_1026[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1043[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1303[] = "DFE-528TX 10/100 Fast Ethernet PCI Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1541[] = "DFE-680TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_2027[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3203[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3300[] = "DWL-510 2.4GHz Wireless PCI Adapter"; +static const char pci_device_1186_3a03[] = "AirPro DWL-A650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a04[] = "AirPro DWL-AB650 Multimode Wireless Cardbus Adapter"; +static const char pci_device_1186_3a05[] = "AirPro DWL-AB520 Multimode Wireless PCI Adapter"; +static const char pci_device_1186_3a07[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_3a08[] = "AirXpert DWL-AG520 Wireless PCI Adapter"; +static const char pci_device_1186_3a10[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a11[] = "AirXpert DWL-AG520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a12[] = "AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +static const char pci_device_1186_3a13[] = "AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a14[] = "AirPremier DWL-AG530 Wireless PCI Adapter"; +static const char pci_device_1186_3a63[] = "AirXpert DWL-AG660 Wireless Cardbus Adapter"; +static const char pci_device_1186_4000[] = "DL2000-based Gigabit Ethernet"; +static const char pci_device_1186_4300[] = "DGE-528T Gigabit Ethernet Adapter"; +static const char pci_device_1186_4c00[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_4c00_1186_4c00[] = "DGE-530T Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1186_8400[] = "D-Link DWL-650+ CardBus PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +static const char pci_device_1191_8060[] = "AEC6712 SCSI"; +static const char pci_device_1191_8080[] = "AEC67160 SCSI"; +static const char pci_device_1191_8081[] = "AEC67160S SCSI"; +static const char pci_device_1191_808a[] = "AEC67162 2-ch. LVD SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +static const char pci_device_1197_010c[] = "CompuScope 82G 8bit 2GS/s Analog Input Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Marvell Technology Group Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_138f[] = "W8300 802.11 Adapter (rev 07)"; +static const char pci_device_11ab_1fa6[] = "Marvell W8300 802.11 Adapter"; +static const char pci_device_11ab_1fa7[] = "88W8310 and 88W8000G [Libertas] 802.11g client chipset"; +static const char pci_device_11ab_1faa[] = "88w8335 [Libertas] 802.11b/g Wireless"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_1faa_1385_4e00[] = "WG511 v2 54MBit/ Wireless PC-Card"; +#endif +static const char pci_device_11ab_4320[] = "88E8001 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_0f38[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_8001[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_173c[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_811a[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_105b_0c19[] = "Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_10b8_b452[] = "EZ Card 1000 (SMC9452TXV.2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0121[] = "Marvell RDK-8001"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0321[] = "Marvell RDK-8003"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_1021[] = "Marvell RDK-8010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_5021[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_9521[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1458_e000[] = "Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_147b_1406[] = "Marvell 88E8001 Gigabit Ethernet Controller (Abit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_15d4_0047[] = "Marvell 88E8001 Gigabit Ethernet Controller (Iwill)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1695_9025[] = "Marvell 88E8001 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_17f2_1c03[] = "Marvell 88E8001 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_270f_2803[] = "Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)"; +#endif +static const char pci_device_11ab_4340[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4341[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4342[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4343[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4344[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4345[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4346[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4347[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4350[] = "88E8035 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1179_0001[] = "Marvell 88E8035 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_11ab_3521[] = "Marvell RDK-8035"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000d[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000f[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0011[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0012[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0016[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0017[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0018[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0019[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001c[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0020[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4351[] = "88E8036 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_107b_4009[] = "Marvell 88E8036 Fast Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_10f7_8338[] = "Marvell 88E8036 Fast Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_0001[] = "Marvell 88E8036 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff00[] = "Marvell 88E8036 Fast Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff10[] = "Marvell 88E8036 Fast Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_11ab_3621[] = "Marvell RDK-8036"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_13d1_ac12[] = "Abocom EFE3K - 10/100 Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_161f_203d[] = "Marvell 88E8036 Fast Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000d[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000f[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0011[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0012[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0016[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0017[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0018[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0019[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001c[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0020[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4352[] = "88E8038 PCI-E Fast Ethernet Controller"; +static const char pci_device_11ab_4360[] = "88E8052 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1043_8134[] = "Marvell 88E8052 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_107b_4009[] = "Marvell 88E8052 Gigabit Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_11ab_5221[] = "Marvell RDK-8052"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1458_e000[] = "Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1462_052c[] = "Marvell 88E8052 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1849_8052[] = "Marvell 88E8052 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_a0a0_0509[] = "Marvell 88E8052 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4361[] = "88E8050 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_107b_3015[] = "Marvell 88E8050 Gigabit Ethernet Controller (Gateway)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_11ab_5021[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3063[] = "D925XCVLK mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3439[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11ab_4362[] = "88E8053 PCI-E Gigabit Ethernet Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_103c_2a0d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1043_8142[] = "Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_109f_3197[] = "Marvell 88E8053 Gigabit Ethernet Controller (Trigem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10f7_8338[] = "Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10fd_a430[] = "Marvell 88E8053 Gigabit Ethernet Controller (SOYO)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_0001[] = "Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff00[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff10[] = "Marvell 88E8053 Gigabit Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_11ab_5321[] = "Marvell RDK-8053"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c240[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c241[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c242[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c243[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c244[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_13d1_ac11[] = "EGE5K - Giga Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1458_e000[] = "Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1462_058c[] = "Marvell 88E8053 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_14c0_0012[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1558_04a0[] = "Marvell 88E8053 Gigabit Ethernet Controller (Clevo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_15bd_1003[] = "Marvell 88E8053 Gigabit Ethernet Controller (DFI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203c[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1695_9029[] = "Marvell 88E8053 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17f2_2c08[] = "Marvell 88E8053 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17ff_0585[] = "Marvell 88E8053 Gigabit Ethernet Controller (Quanta)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1849_8053[] = "Marvell 88E8053 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000c[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0010[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0013[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0014[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0015[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001a[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001d[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001f[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0021[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0022[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_270f_2801[] = "Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_a0a0_0506[] = "Marvell 88E8053 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4363[] = "88E8055 PCI-E Gigabit Ethernet Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_5005[] = "Belkin F5D5005 Gigabit Desktop Network PCI Card"; +static const char pci_device_11ab_5040[] = "MV88SX5040 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5041[] = "MV88SX5041 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5080[] = "MV88SX5080 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5081[] = "MV88SX5081 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_6041[] = "MV88SX6041 4-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6081[] = "MV88SX6081 8-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6460[] = "MV64360/64361/64362 System Controller"; +static const char pci_device_11ab_6480[] = "MV64460/64461/64462 System Controller"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +static const char pci_device_11af_0001[] = "Cinema"; +static const char pci_device_11af_ee40[] = "Digidesign Audiomedia III"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +static const char pci_device_11bd_002e[] = "PCTV 40i"; +static const char pci_device_11bd_bede[] = "Pinnacle AV/DV Studio Capture Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Agere Systems"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2203[] = "PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2204[] = "PRO/100+ MiniPCI on Armada E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1033_80a8[] = "Versa Note Vxi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1468_0450[] = "Evo N600c"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_4005_144f[] = "LifeBook C Series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_048c[] = "V.92 56K WinModem"; +static const char pci_device_11c1_048f[] = "V.92 56k WinModem"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_8086_524c[] = "D865PERL mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +static const char pci_device_11c1_8110[] = "T8110 H.100/H.110 TDM switch"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_8110_12d9_000c[] = "E1/T1 PMXc cPCI carrier card"; +#endif +static const char pci_device_11c1_ab10[] = "WL60010 Wireless LAN MAC"; +static const char pci_device_11c1_ab11[] = "WL60040 Multimode Wireles LAN MAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab12[] = "WaveLAN 11abg Cardbus card (Model 1102)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab13[] = "WaveLAN 11abg MiniPCI card (Model 0512)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab15[] = "WaveLAN 11abg Cardbus card (Model 1106)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab16[] = "WaveLAN 11abg MiniPCI card (Model 0516)"; +#endif +static const char pci_device_11c1_ab20[] = "ORiNOCO PCI Adapter"; +static const char pci_device_11c1_ab21[] = "Agere Wireless PCI Adapter"; +static const char pci_device_11c1_ab30[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab30_14cd_2012[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#endif +static const char pci_device_11c1_ed00[] = "ET-131x PCI-E Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1535[] = "Blackfin BF535 processor"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +static const char pci_device_11d4_5340[] = "AD1881 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_12f8_8a02[] = "Tekram Video Kit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_13c2_0000[] = "MediaFocus Satellite TV Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1de1_9fff[] = "Video Kit C210"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_0001[] = "COM-ON-AIR Dosch&Amand DECT"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 32 port w/external I/F"; +static const char pci_device_11fe_0002[] = "RocketPort 8 port w/external I/F"; +static const char pci_device_11fe_0003[] = "RocketPort 16 port w/external I/F"; +static const char pci_device_11fe_0004[] = "RocketPort 4 port w/quad cable"; +static const char pci_device_11fe_0005[] = "RocketPort 8 port w/octa cable"; +static const char pci_device_11fe_0006[] = "RocketPort 8 port w/RJ11 connectors"; +static const char pci_device_11fe_0007[] = "RocketPort 4 port w/RJ11 connectors"; +static const char pci_device_11fe_0008[] = "RocketPort 8 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_0009[] = "RocketPort 16 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_000a[] = "RocketPort Plus 4 port"; +static const char pci_device_11fe_000b[] = "RocketPort Plus 8 port"; +static const char pci_device_11fe_000c[] = "RocketModem 6 port"; +static const char pci_device_11fe_000d[] = "RocketModem 4-port"; +static const char pci_device_11fe_000e[] = "RocketPort Plus 2 port RS232"; +static const char pci_device_11fe_000f[] = "RocketPort Plus 2 port RS422"; +static const char pci_device_11fe_0801[] = "RocketPort UPCI 32 port w/external I/F"; +static const char pci_device_11fe_0802[] = "RocketPort UPCI 8 port w/external I/F"; +static const char pci_device_11fe_0803[] = "RocketPort UPCI 16 port w/external I/F"; +static const char pci_device_11fe_0805[] = "RocketPort UPCI 8 port w/octa cable"; +static const char pci_device_11fe_080c[] = "RocketModem III 8 port"; +static const char pci_device_11fe_080d[] = "RocketModem III 4 port"; +static const char pci_device_11fe_0812[] = "RocketPort UPCI Plus 8 port RS422"; +static const char pci_device_11fe_0903[] = "RocketPort Compact PCI 16 port w/external I/F"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +static const char pci_device_11ff_0003[] = "AG-5"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 CardBus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 CardBus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 CardBus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 CardBus Controller"; +static const char pci_device_1217_6933[] = "OZ6933/711E1 CardBus/SmartCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ601/6912/711E0 CardBus/SmartCardBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1014_020c[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1217_7110[] = "OZ711Mx 4-in-1 MemoryCardBus Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7112[] = "OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller"; +static const char pci_device_1217_7113[] = "OZ711EC1 SmartCardBus Controller"; +static const char pci_device_1217_7114[] = "OZ711M1/MC1 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7134[] = "OZ711MP1/MS1 MemoryCardBus Controller"; +static const char pci_device_1217_71e2[] = "OZ711E2 SmartCardBus Controller"; +static const char pci_device_1217_7212[] = "OZ711M2 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7213[] = "OZ6933E CardBus Controller"; +static const char pci_device_1217_7223[] = "OZ711M3/MC3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7233[] = "OZ711MP3/MS3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3 2000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0057[] = "Voodoo3 3000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0003[] = "Voodoo5 PCI 5500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +static const char pci_device_1227_0006[] = "Raptor GFX 8P"; +static const char pci_device_1227_0023[] = "Raptor GFX [1100T]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000f[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_1809_0016[] = "Emuzed MAUI-III PCI PVR FM TV"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +static const char pci_device_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +static const char pci_device_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +static const char pci_device_1244_2700[] = "Fritz!Card DSL SL"; +static const char pci_device_1244_2900[] = "Fritz!Card DSL v2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infortrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +static const char pci_device_1259_a117[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a120[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204 Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125b_1400_1186_1100[] = "AX8814X Based PCI Fast Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0101[] = "Saturn 4520P"; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_153b_111b[] = "Terratec 128i PCI"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700/E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_0e11_0098[] = "Evo N600c"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00b1[] = "Latitude C600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Intersil Corporation"; +static const char pci_device_1260_3872[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3872_1468_0202[] = "LAN-Express IEEE 802.11b Wireless LAN"; +#endif +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3700[] = "DWL-520 Wireless PCI Adapter, Rev E1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1385_4105[] = "MA311 802.11b wireless adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_16a5_1601[] = "AIR.mate PC-400 PCI Wireless LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_3886[] = "ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3886_17cf_0037[] = "XG-901 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_3890[] = "ISL3890 [Prism GT/Prism Duette]/ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2802[] = "SMC2802W Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2835[] = "SMC2835W Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_a835[] = "SMC2835W V2 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_4203[] = "WN4201B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee03[] = "SMC2802W V2 Wireless PCI Adapter [ISL3886]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee08[] = "SMC2835W V3 EU Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1186_3202[] = "DWL-G650 A1 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1259_c104[] = "CG-WLCB54GT Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1385_4800[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_16a5_1605[] = "ALLNET ALL0271 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0014[] = "XG-600 and clones Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0020[] = "XG-900 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +static const char pci_device_1260_ffff[] = "ISL3886IK"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_ffff_1260_0000[] = "Senao 3054MP+ (J) mini-PCI WLAN 802.11g adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +static const char pci_device_126c_1211[] = "10/100BaseTX [RTL81xx]"; +static const char pci_device_126c_126c[] = "802.11b Wireless Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0501[] = "SM501 VoyagerGX Rev. AA"; +static const char pci_device_126f_0510[] = "SM501 VoyagerGX Rev. B"; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0730[] = "SM731 Cougar3DR"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1171[] = "ES1373 [AudioPCI] (also Creative Labs CT5803)"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_8001[] = "CT4751 board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_8001[] = "Sound Blaster 16PCI 4.1ch"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +static const char pci_device_1278_0710[] = "TPE5 PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0060[] = "TM8000 Northbridge"; +static const char pci_device_1279_0061[] = "TM8000 AGP bridge"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1005_127a[] = "AOpen FM56-P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9102[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8211[] = "ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller))"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8211_1043_8138[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_1283_8212[] = "IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8212_1283_0001[] = "IT/ITE8212 Dual channel ATA RAID controller"; +#endif +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8872[] = "IT8874F PCI Dual Serial Port Controller"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +static const char pci_device_12a3_8105[] = "T8105 H100 Digital Switch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_0002[] = "AU8830 [Vortex2] Based Sound Card With A3D Support"; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1014_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_10a9_8002[] = "Acenic Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +static const char pci_device_12ae_00fa[] = "Farallon PN9100-T Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "3Com Corp, Modem Division"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +static const char pci_device_12c4_0001[] = "Blue HEAT/PCI 8 (RS232/CL/RJ11)"; +static const char pci_device_12c4_0002[] = "Blue HEAT/PCI 4 (RS232)"; +static const char pci_device_12c4_0003[] = "Blue HEAT/PCI 2 (RS232)"; +static const char pci_device_12c4_0004[] = "Blue HEAT/PCI 8 (UNIV, RS485)"; +static const char pci_device_12c4_0005[] = "Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485)"; +static const char pci_device_12c4_0006[] = "Blue HEAT/PCI 4 (OPTO, RS485)"; +static const char pci_device_12c4_0007[] = "Blue HEAT/PCI 2+2 (RS232/485)"; +static const char pci_device_12c4_0008[] = "Blue HEAT/PCI 2 (OPTO, Tx, RS485)"; +static const char pci_device_12c4_0009[] = "Blue HEAT/PCI 2+6 (RS232/485)"; +static const char pci_device_12c4_000a[] = "Blue HEAT/PCI 8 (Tx, RS485)"; +static const char pci_device_12c4_000b[] = "Blue HEAT/PCI 4 (Tx, RS485)"; +static const char pci_device_12c4_000c[] = "Blue HEAT/PCI 2 (20 MHz, RS485)"; +static const char pci_device_12c4_000d[] = "Blue HEAT/PCI 2 PTM"; +static const char pci_device_12c4_0100[] = "NT960/PCI"; +static const char pci_device_12c4_0201[] = "cPCI Titan - 2 Port"; +static const char pci_device_12c4_0202[] = "cPCI Titan - 4 Port"; +static const char pci_device_12c4_0300[] = "CTI PCI UART 2 (RS232)"; +static const char pci_device_12c4_0301[] = "CTI PCI UART 4 (RS232)"; +static const char pci_device_12c4_0302[] = "CTI PCI UART 8 (RS232)"; +static const char pci_device_12c4_0310[] = "CTI PCI UART 1+1 (RS232/485)"; +static const char pci_device_12c4_0311[] = "CTI PCI UART 2+2 (RS232/485)"; +static const char pci_device_12c4_0312[] = "CTI PCI UART 4+4 (RS232/485)"; +static const char pci_device_12c4_0320[] = "CTI PCI UART 2"; +static const char pci_device_12c4_0321[] = "CTI PCI UART 4"; +static const char pci_device_12c4_0322[] = "CTI PCI UART 8"; +static const char pci_device_12c4_0330[] = "CTI PCI UART 2 (RS485)"; +static const char pci_device_12c4_0331[] = "CTI PCI UART 4 (RS485)"; +static const char pci_device_12c4_0332[] = "CTI PCI UART 8 (RS485)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +static const char pci_device_12d4_0200[] = "T1 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies Inc"; +static const char pci_device_12d5_0003[] = "BSP16"; +static const char pci_device_12d5_1000[] = "BSP15"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +static const char pci_device_12d8_8150[] = "PCI to PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +static const char pci_device_12d9_0002[] = "PCI Prosody"; +static const char pci_device_12d9_0004[] = "cPCI Prosody"; +static const char pci_device_12d9_0005[] = "Aculab E1/T1 PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +static const char pci_device_12de_0200[] = "CryptoSwift CS200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +static const char pci_device_12fb_0001[] = "PMC-MAI"; +static const char pci_device_12fb_00f5[] = "F5 Dakar"; +static const char pci_device_12fb_02ad[] = "PMC-2MAI"; +static const char pci_device_12fb_2adc[] = "ePMC-2ADC"; +static const char pci_device_12fb_3100[] = "PRO-3100"; +static const char pci_device_12fb_3500[] = "PRO-3500"; +static const char pci_device_12fb_4d4f[] = "Modena"; +static const char pci_device_12fb_8120[] = "ePMC-8120"; +static const char pci_device_12fb_da62[] = "Daytona C6201 PCI (Hurricane)"; +static const char pci_device_12fb_db62[] = "Ingliston XBIF"; +static const char pci_device_12fb_dc62[] = "Ingliston PLX9054"; +static const char pci_device_12fb_dd62[] = "Ingliston JTAG/ISP"; +static const char pci_device_12fb_eddc[] = "ePMC-MSDDC"; +static const char pci_device_12fb_fa01[] = "ePMC-FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Measurement Computing"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +static const char pci_device_1307_004d[] = "PCI-QUAD04"; +static const char pci_device_1307_0052[] = "PCI-DAS4020/12"; +static const char pci_device_1307_0054[] = "PCI-DIO96"; +static const char pci_device_1307_005e[] = "PCI-DAS6025"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "Linksys"; +static const char pci_device_1317_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_0985[] = "NC100 Network Everywhere Fast Ethernet 10/100"; +static const char pci_device_1317_1985[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_2850[] = "HSP MicroModem 56"; +static const char pci_device_1317_5120[] = "ADMtek ADM5120 OpenGate System-on-Chip"; +static const char pci_device_1317_8201[] = "ADMtek ADM8211 802.11b Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_10b8_2635[] = "SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_1317_8201[] = "SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card"; +#endif +static const char pci_device_1317_8211[] = "ADMtek ADM8211 802.11b Wireless Interface"; +static const char pci_device_1317_9511[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "GNIC-II PCI Gigabit Ethernet [Hamachi]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0801_1319_1319[] = "FM801 PCI Audio"; +#endif +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0802_1319_1319[] = "FM801 PCI Joystick"; +#endif +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_2081[] = "CyberSerial (8-port) ST16654"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +static const char pci_device_1331_0030[] = "ENP-2611"; +static const char pci_device_1331_8200[] = "82600 Host Bridge"; +static const char pci_device_1331_8201[] = "82600 IDE"; +static const char pci_device_1331_8202[] = "82600 USB"; +static const char pci_device_1331_8210[] = "82600 PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +static const char pci_device_1332_5425[] = "MM-5425CN PCI 64/66 Memory Module with Battery Backup"; +static const char pci_device_1332_6140[] = "MM-6140D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_2189[] = "HSP56 MicroModem"; +static const char pci_device_134d_2486[] = "2304WT V.92 MDC Modem"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7890_134d_0001[] = "PCT789 adapter"; +#endif +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_5101[] = "Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32)"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +static const char pci_device_1360_0101[] = "PCI32 DCF77 Radio Clock"; +static const char pci_device_1360_0102[] = "PCI509 DCF77 Radio Clock"; +static const char pci_device_1360_0103[] = "PCI510 DCF77 Radio Clock"; +static const char pci_device_1360_0201[] = "GPS167PCI GPS Receiver"; +static const char pci_device_1360_0202[] = "GPS168PCI GPS Receiver"; +static const char pci_device_1360_0203[] = "GPS169PCI GPS Receiver"; +static const char pci_device_1360_0301[] = "TCR510PCI IRIG Timecode Reader"; +static const char pci_device_1360_0302[] = "TCR167PCI IRIG Timecode Reader"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +static const char pci_device_136b_ff01[] = "KL5A72002 Motion JPEG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +static const char pci_device_1371_434e[] = "GigaCard Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1371_434e_1371_434e[] = "N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd."; +static const char pci_device_1374_0024[] = "Silicom Dual port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0025[] = "Silicom Quad port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0026[] = "Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0027[] = "Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0029[] = "Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002a[] = "Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002b[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002c[] = "Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002d[] = "Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002e[] = "Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002f[] = "Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0030[] = "Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0031[] = "Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter"; +static const char pci_device_1374_0032[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_0034[] = "Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0035[] = "Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0036[] = "Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0037[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0038[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0039[] = "Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_003a[] = "Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +static const char pci_device_137a_0001[] = "PCI-324 Audiowire Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +static const char pci_device_1382_0001[] = "ARC88 audio recording card"; +static const char pci_device_1382_2008[] = "Prodif 96 Pro sound system"; +static const char pci_device_1382_2088[] = "Marc 8 Midi sound system"; +static const char pci_device_1382_20c8[] = "Marc A sound system"; +static const char pci_device_1382_4008[] = "Marc 2 sound system"; +static const char pci_device_1382_4010[] = "Marc 2 Pro sound system"; +static const char pci_device_1382_4048[] = "Marc 4 MIDI sound system"; +static const char pci_device_1382_4088[] = "Marc 4 Digi sound system"; +static const char pci_device_1382_4248[] = "Marc X sound system"; +static const char pci_device_1382_4424[] = "TRACE D4 Sound System"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_0013[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_311a[] = "GA511 Gigabit Ethernet"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_4105[] = "MA311 802.11b wireless adapter"; +static const char pci_device_1385_4400[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4600[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4601[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4610[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4800[] = "WG511(v1) 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4900[] = "WG311v1 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4a00[] = "WAG311 802.11a/g Wireless PCI Adapter"; +static const char pci_device_1385_4b00[] = "WG511T 108 Mbps Wireless PC Card"; +static const char pci_device_1385_4c00[] = "WG311v2 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4d00[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4e00[] = "WG511v2 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4f00[] = "WG511U Double 108 Mbps Wireless PC Card"; +static const char pci_device_1385_5200[] = "GA511 Gigabit PC Card"; +static const char pci_device_1385_620a[] = "GA620 Gigabit Ethernet"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630 Gigabit Ethernet"; +static const char pci_device_1385_6b00[] = "WG311v3 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_6d00[] = "WPNT511 RangeMax™ 240 Mbps Wireless PC Card"; +static const char pci_device_1385_f004[] = "FA310TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1141[] = "Industrio CP-114"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_16b8[] = "ISDN network Controller [HFC-8S]"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1708[] = "ISDN Adapter (PCI Bus, D, C, ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +static const char pci_device_13a3_001d[] = "7956 Security Processor"; +static const char pci_device_13a3_0020[] = "7955 Security Processor"; +static const char pci_device_13a3_0026[] = "8155 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0152[] = "XR17C/D152 Dual PCI UART"; +static const char pci_device_13a8_0154[] = "XR17C154 Quad UART"; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink Adapter v1"; +static const char pci_device_13c0_0020[] = "SyncLink SCC Adapter"; +static const char pci_device_13c0_0030[] = "SyncLink Multiport Adapter"; +static const char pci_device_13c0_0210[] = "SyncLink Adapter v2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "5xxx/6xxx-series PATA-RAID"; +static const char pci_device_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13c1_1001_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#endif +static const char pci_device_13c1_1002[] = "9xxx-series SATA-RAID"; +static const char pci_device_13c1_1003[] = "9550SX SATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +static const char pci_device_13c6_0520[] = "CEI-520 A429 Card"; +static const char pci_device_13c6_0620[] = "CEI-620 A429 Card"; +static const char pci_device_13c6_0820[] = "CEI-820 A429 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card"; +static const char pci_device_13d0_2200[] = "B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab03[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +static const char pci_device_13d1_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Intraserver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc / IC Plus Corp"; +static const char pci_device_13f0_0200[] = "IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +static const char pci_device_13f0_1023[] = "IC Plus IP1000 Family Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0011[] = "CMI8738"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8035[] = "CUSI-FX motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1681_a000[] = "Gamesurround MUSE XL"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1240[] = "PCI-1240 4-channel stepper motor controller card"; +static const char pci_device_13fe_1600[] = "PCI-1612 4-port RS-232/422/485 PCI communication card"; +static const char pci_device_13fe_1733[] = "PCI-1733 32-channel isolated digital input card"; +static const char pci_device_13fe_1752[] = "PCI-1752"; +static const char pci_device_13fe_1754[] = "PCI-1754"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0110[] = "Lava DSerial-PCI Port A"; +static const char pci_device_1407_0111[] = "Lava DSerial-PCI Port B"; +static const char pci_device_1407_0120[] = "Quattro-PCI A"; +static const char pci_device_1407_0121[] = "Quattro-PCI B"; +static const char pci_device_1407_0180[] = "Lava Octo A"; +static const char pci_device_1407_0181[] = "Lava Octo B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0220[] = "Lava Quattro PCI Ports A/B"; +static const char pci_device_1407_0221[] = "Lava Quattro PCI Ports C/D"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "VIA Technologies Inc."; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24] PCI Multi-Channel I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_1712[] = "Hoontech ST Audio DSP 24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d630[] = "M-Audio Delta 1010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d631[] = "M-Audio Delta DiO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d632[] = "M-Audio Delta 66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d633[] = "M-Audio Delta 44"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d634[] = "M-Audio Delta Audiophile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d635[] = "M-Audio Delta TDIF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d637[] = "M-Audio Delta RBUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d638[] = "M-Audio Delta 410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63b[] = "M-Audio Delta 1010LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63c[] = "Digigram VX442"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1416_1712[] = "Hoontech ST Audio DSP 24 Media 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1115[] = "EWS88 MT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1125[] = "EWS88 MT (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112b[] = "EWS88 D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112c[] = "EWS88 D (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1130[] = "EWX 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1138[] = "DMX 6fire 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1151[] = "PHASE88"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_16ce_1040[] = "Edirol DA-2496"; +#endif +static const char pci_device_1412_1724[] = "VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_1724[] = "AMP Ltd AUDIO2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3630[] = "M-Audio Revolution 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3631[] = "M-Audio Revolution 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1145[] = "Aureon 7.1 Space"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1147[] = "Aureon 5.1 Sky"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1153[] = "Aureon 7.1 Universe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f641[] = "ZNF3-150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f645[] = "ZNF3-250"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2050[] = "CyberPro (4-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2051[] = "CyberSerial 4S Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9510[] = "OX16PCI954 (Quad 16950 UART) function 1 (Disabled)"; +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +static const char pci_device_1415_9523[] = "OX16PCI952 Integrated Parallel Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +static const char pci_device_1420_8002[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part)"; +static const char pci_device_1420_8003[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "Chelsio Communications Inc"; +static const char pci_device_1425_000b[] = "T210 Protocol Engine"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +static const char pci_device_142e_4020[] = "VM2-2 [Video Maker 2] MPEG1/2 Encoder"; +static const char pci_device_142e_4337[] = "VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +static const char pci_device_1432_9130[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "RTD Embedded Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8164[] = "PCI-8164"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +static const char pci_device_1458_0c11[] = "K8NS Pro Mainboard"; +static const char pci_device_1458_e911[] = "GN-WIAG02"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +static const char pci_device_1461_f436[] = "AVerTV Hybrid+FM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +static const char pci_device_1462_5501[] = "nVidia NV15DDR [GeForce2 Ti]"; +static const char pci_device_1462_6819[] = "Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G]"; +static const char pci_device_1462_6825[] = "PCI Card wireless 11g [PC54G]"; +static const char pci_device_1462_6834[] = "RaLink RT2500 802.11g [PC54G2]"; +static const char pci_device_1462_8725[] = "NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter"; +static const char pci_device_1462_9000[] = "NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter"; +static const char pci_device_1462_9110[] = "GeFORCE FX5200"; +static const char pci_device_1462_9119[] = "NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter"; +static const char pci_device_1462_9591[] = "nVidia Corporation NV36 [GeForce FX 5700LE]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +static const char pci_device_146c_1430[] = "FE-1430TX Fast Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +static const char pci_device_1497_1497[] = "SMA Technologie AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +static const char pci_device_1498_0330[] = "TPMC816 2 Channel CAN bus controller."; +static const char pci_device_1498_0385[] = "TPMC901 Extended CAN bus with 2/4/6 CAN controller"; +static const char pci_device_1498_21cd[] = "TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_30c8[] = "TPCI200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +static const char pci_device_149d_0001[] = "Video Toaster for PC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "PulsarSRB"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +static const char pci_device_14b9_a505[] = "Cisco Aironet CB20a 802.11a Wireless LAN Adapter"; +static const char pci_device_14b9_a506[] = "Cisco Aironet Mini PCI b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +static const char pci_device_14c1_8043[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alliance Semiconductor Corporation"; +static const char pci_device_14d9_0010[] = "AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon]"; +static const char pci_device_14d9_9000[] = "AS90L10204/10208 HyperTransport to PCI-X Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +static const char pci_device_14db_2182[] = "AFAVLAB Technology Inc. 8-port serial card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_0800[] = "Sentry5 Chipcommon I/O Controller"; +static const char pci_device_14e4_0804[] = "Sentry5 PCI Bridge"; +static const char pci_device_14e4_0805[] = "Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_0806[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_080b[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_080f[] = "Sentry5 DDR/SDR RAM Controller"; +static const char pci_device_14e4_0811[] = "Sentry5 External Interface Core"; +static const char pci_device_14e4_0816[] = "BCM3302 Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_1600[] = "NetXtreme BCM5752 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1601[] = "NetXtreme BCM5752M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128a[] = "1000Base-T (PCI) [A7061A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128b[] = "1000Base-SX (PCI) [A7073A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12a4[] = "Core Lan 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12c1[] = "IOX Core Lan 1000Base-T [A7109AX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_1300[] = "Core LAN/SCSI Combo [A6794A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8010[] = "IO9/IO10 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8011[] = "Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8012[] = "Gigabit Ethernet (Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_10a9_8010[] = "SGI IO9 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1734_100b[] = "Primergy RX300"; +#endif +static const char pci_device_14e4_164a[] = "NetXtreme II BCM5706 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3101[] = "NC370T Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164c[] = "NetXtreme II BCM5708 Gigabit Ethernet"; +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1653_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1654[] = "NetXtreme BCM5705_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3100[] = "NC1020 HP ProLiant Gigabit Server Adapter 32 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3226[] = "NC150T 4-port Gigabit Combo Switch & Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1659[] = "NetXtreme BCM5721 Gigabit Ethernet PCI Express"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1014_02c6[] = "eServer xSeries server mainboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7031[] = "NC320T PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7032[] = "NC320i PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1734_1061[] = "Primergy RX300 S2"; +#endif +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165d_1028_865d[] = "Latitude D400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_165e[] = "NetXtreme BCM5705M_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1668[] = "NetXtreme BCM5714 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1668_103c_7039[] = "NC324i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_166a[] = "NetXtreme BCM5780 Gigabit Ethernet"; +static const char pci_device_14e4_166b[] = "NetXtreme BCM5780S Gigabit Ethernet"; +static const char pci_device_14e4_166e[] = "570x 10/100 Integrated Controller"; +static const char pci_device_14e4_1677[] = "NetXtreme BCM5751 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0182[] = "Latitude D610"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_01ad[] = "Optiplex GX620"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1734_105d[] = "Scenic W620"; +#endif +static const char pci_device_14e4_1678[] = "NetXtreme BCM5715 Gigabit Ethernet"; +static const char pci_device_14e4_167d[] = "NetXtreme BCM5751M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167e[] = "NetXtreme BCM5751F Fast Ethernet PCI Express"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_103c_12bc[] = "HP d530 CMT (DG746A)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_169c[] = "NetXtreme BCM5788 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_169c_103c_308b[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_169d[] = "NetLink BCM5789 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16aa[] = "NetXtreme II BCM5706S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16aa_103c_3102[] = "NC370F Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16ac[] = "NetXtreme II BCM5708S Gigabit Ethernet"; +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702A3 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12c3[] = "Combo FC/GigE-SX [A9782A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12ca[] = "Combo FC/GigE-T [A9784A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_16dd[] = "NetLink BCM5781 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16f7[] = "NetXtreme BCM5753 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fd[] = "NetXtreme BCM5753M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fe[] = "NetXtreme BCM5753F Fast Ethernet PCI Express"; +static const char pci_device_14e4_170c[] = "BCM4401-B0 100Base-TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_170d[] = "NetXtreme BCM5901 100Base-TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170d_1014_0545[] = "ThinkPad R40e (2684-HVG) builtin ethernet controller"; +#endif +static const char pci_device_14e4_170e[] = "NetXtreme BCM5901 100Base-TX"; +static const char pci_device_14e4_3352[] = "BCM3352"; +static const char pci_device_14e4_3360[] = "BCM3360"; +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4303 802.11b Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1028_0407[] = "TrueMobile 1180 Onboard WLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1043_0120[] = "WL-103b Wireless LAN PC Card"; +#endif +static const char pci_device_14e4_4305[] = "BCM4307 V.90 56k Modem"; +static const char pci_device_14e4_4306[] = "BCM4307 Ethernet Controller"; +static const char pci_device_14e4_4307[] = "BCM4307 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4310[] = "BCM4310 Chipcommon I/OController"; +static const char pci_device_14e4_4312[] = "BCM4310 UART"; +static const char pci_device_14e4_4313[] = "BCM4310 Ethernet Controller"; +static const char pci_device_14e4_4315[] = "BCM4310 USB Controller"; +static const char pci_device_14e4_4318[] = "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_103c_1356[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0311[] = "Aspire 3022WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0312[] = "TravelMate 2410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_0449[] = "Gateway 7510GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_4318[] = "WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_16ec_0119[] = "U.S.Robotics Wireless MAXg PC Card"; +#endif +static const char pci_device_14e4_4319[] = "Dell Wireless 1470 DualBand WLAN"; +static const char pci_device_14e4_4320[] = "BCM4306 802.11b/g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0001[] = "TrueMobile 1300 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0003[] = "Wireless 1350 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12f4[] = "nx9500 Built-in Wireless"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12fa[] = "Presario R3000 802.11b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1043_100f[] = "WL-100G"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1057_7025[] = "WN825G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_106b_004e[] = "AirPort Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_144f_7050[] = "eMachines M6805 802.11g Built-in Wireless"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_14e4_4320[] = "Linksys WMP54G PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1737_4320[] = "WPC54G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7001[] = "Belkin F5D7001 High-Speed Mode Wireless G Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7010[] = "Belkin F5D7010 54g Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_185f_1220[] = "Acer TravelMate 290E WLAN Mini-PCI Card"; +#endif +static const char pci_device_14e4_4321[] = "BCM4306 802.11a Wireless LAN Controller"; +static const char pci_device_14e4_4322[] = "BCM4306 UART"; +static const char pci_device_14e4_4324[] = "BCM4309 802.11a/b/g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0001[] = "Truemobile 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0003[] = "Truemobile 1450 MiniPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_4325[] = "BCM43xG 802.11b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0003[] = "Wireless Notebook Adapter MN-720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0004[] = "Wireless PCI Adapter MN-730"; +#endif +static const char pci_device_14e4_4326[] = "BCM4307 Chipcommon I/O Controller?"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_1043_80a8[] = "A7V8X motherboard"; +#endif +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4403[] = "BCM4402 V.90 56k Modem"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4412 10/100BaseT"; +static const char pci_device_14e4_4430[] = "BCM44xx CardBus iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4432[] = "BCM4432 CardBus 10/100BaseT"; +static const char pci_device_14e4_4610[] = "BCM4610 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4611[] = "BCM4610 Sentry5 iLine32 HomePNA 1.0"; +static const char pci_device_14e4_4612[] = "BCM4610 Sentry5 V.90 56k Modem"; +static const char pci_device_14e4_4613[] = "BCM4610 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4614[] = "BCM4610 Sentry5 External Interface"; +static const char pci_device_14e4_4615[] = "BCM4610 Sentry5 USB Controller"; +static const char pci_device_14e4_4704[] = "BCM4704 PCI to SB Bridge"; +static const char pci_device_14e4_4705[] = "BCM4704 Sentry5 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4706[] = "BCM4704 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4707[] = "BCM4704 Sentry5 USB Controller"; +static const char pci_device_14e4_4708[] = "BCM4704 Crypto Accelerator"; +static const char pci_device_14e4_4710[] = "BCM4710 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4711[] = "BCM47xx Sentry5 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4712[] = "BCM47xx V.92 56k modem"; +static const char pci_device_14e4_4713[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4714[] = "BCM47xx Sentry5 External Interface"; +static const char pci_device_14e4_4715[] = "Sentry5 USB Controller"; +static const char pci_device_14e4_4716[] = "BCM47xx Sentry5 USB Host Controller"; +static const char pci_device_14e4_4717[] = "BCM47xx Sentry5 USB Device Controller"; +static const char pci_device_14e4_4718[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_4719[] = "BCM47xx/53xx RoboSwitch Core"; +static const char pci_device_14e4_4720[] = "BCM4712 MIPS CPU"; +static const char pci_device_14e4_5365[] = "BCM5365P Sentry5 Host Bridge"; +static const char pci_device_14e4_5600[] = "BCM5600 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5605[] = "BCM5605 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5615[] = "BCM5615 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5625[] = "BCM5625 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5645[] = "BCM5645 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5670[] = "BCM5670 8-Port 10GE Ethernet Switch Fabric"; +static const char pci_device_14e4_5680[] = "BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5690[] = "BCM5690 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5691[] = "BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5692[] = "BCM5692 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +static const char pci_device_14e4_5822[] = "BCM5822 Crypto Accelerator"; +static const char pci_device_14e4_5823[] = "BCM5823 Crypto Accelerator"; +static const char pci_device_14e4_5824[] = "BCM5824 Crypto Accelerator"; +static const char pci_device_14e4_5840[] = "BCM5840 Crypto Accelerator"; +static const char pci_device_14e4_5841[] = "BCM5841 Crypto Accelerator"; +static const char pci_device_14e4_5850[] = "BCM5850 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +static const char pci_device_14ea_ab07[] = "RTL81xx RealTek Ethernet"; +static const char pci_device_14ea_ab08[] = "FNW-3602-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1085[] = "HCF V90 56k Data/Fax/Voice/Spkp PCI Modem"; +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1620[] = "AccessRunner V2 PCI ADSL Arbitration Device"; +static const char pci_device_14f1_1621[] = "AccessRunner V2 PCI ADSL Interface Device"; +static const char pci_device_14f1_1622[] = "AccessRunner V2 PCI ADSL Yukon WAN Adapter"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1811[] = "Conextant MiniPCI Network Adapter"; +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2045_14f1_2045[] = "Generic SoftK56"; +#endif +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_2f02[] = "HSF 56k HSFi Data/Fax"; +static const char pci_device_14f1_2f11[] = "HSF 56k HSFi Modem"; +static const char pci_device_14f1_2f20[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +static const char pci_device_14f1_8800[] = "CX23880/1/2/3 PCI Video and Audio Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9001[] = "Nova-T DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9200[] = "Nova-SE2 DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9202[] = "Nova-S-Plus DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9402[] = "WinTV-HVR1100 DVB-T/Hybrid"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9802[] = "WinTV-HVR1100 DVB-T/Hybrid (Low Profile)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_00f8[] = "ATI TV Wonder Pro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_a101[] = "HDTV Wonder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6613[] = "Leadtek Winfast 2000XP Expert"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6620[] = "Leadtek Winfast DV2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_665f[] = "WinFast DTV1000-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d003[] = "IODATA GV-VCP3/PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d035[] = "IODATA GV/BCTV7E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1421_0334[] = "Instant TV DVB-T PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000a[] = "AVerTV 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000b[] = "AverTV Studio 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_8011[] = "UltraTV Media Center PCI 550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14c7_0107[] = "GDI Black Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0342[] = "Digital-Logic MICROSPACE Entertainment Center (MEC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_153b_1166[] = "Cinergy 1400 DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1540_2580[] = "Provideo PV259"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4811[] = "PixelView"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4813[] = "Club 3D ZAP1000 MCE Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a1[] = "KWorld/VStream XPert DVB-T with cx22702"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08b2[] = "KWorld DVB-S 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_a8a6[] = "digitalnow DNTV Live! DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1822_0025[] = "digitalnow DNTV Live! DVB-T Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d500[] = "FusionHDTV 5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d810[] = "FusionHDTV 3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db00[] = "FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db11[] = "FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db50[] = "FusionHDTV DVB-T Dual Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8801[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8801_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +static const char pci_device_14f1_8802[] = "CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8804[] = "CX23880/1/2/3 PCI Video and Audio Decoder [IR Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8804_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +static const char pci_device_14f1_8811[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +static const char pci_device_14f2_0120[] = "EV1000 bridge"; +static const char pci_device_14f2_0121[] = "EV1000 Parallel port"; +static const char pci_device_14f2_0122[] = "EV1000 Serial port"; +static const char pci_device_14f2_0123[] = "EV1000 Keyboard controller"; +static const char pci_device_14f2_0124[] = "EV1000 Mouse controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BroadLogic"; +static const char pci_device_14f3_2030[] = "2030 DVB-S Satellite Reciever"; +static const char pci_device_14f3_2050[] = "2050 DVB-T Terrestrial (Cable) Reciever"; +static const char pci_device_14f3_2060[] = "2060 ATSC Terrestrial (Cable) Reciever"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +static const char pci_device_14f8_2077[] = "TP-240 dual span E1 VoIP PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOLTERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "Quadrics Ltd"; +static const char pci_device_14fc_0000[] = "QsNet Elan3 Network Adapter"; +static const char pci_device_14fc_0001[] = "QsNetII Elan4 Network Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +static const char pci_device_1500_1360[] = "RTL81xx RealTek Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0800[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +static const char pci_device_1516_0891[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +static const char pci_device_151c_0003[] = "Prodif T 2496"; +static const char pci_device_151c_4000[] = "Prodif 88"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0c00[] = "RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0d00[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_1d00[] = "RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2000[] = "RockForceD1 1 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2100[] = "RockForceF1 1 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2200[] = "RockForceD2 2 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2300[] = "RockForceF2 2 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2400[] = "RockForceD4 4 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2500[] = "RockForceF4 4 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2600[] = "RockForceD8 8 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2700[] = "RockForceF8 8 Port V.34 Super-G3 Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_0510[] = "CB710 Memory Card Reader Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_0510_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_0520[] = "FLASH memory: ENE Technology Inc:"; +static const char pci_device_1524_0530[] = "ENE PCI Memory Stick Card Reader Controller"; +static const char pci_device_1524_0550[] = "ENE PCI Secure Digital Card Reader Controller"; +static const char pci_device_1524_0610[] = "PCI Smart Card Reader Controller"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1411[] = "CB-710/2/4 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1411_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1412[] = "CB-712/4 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +static const char pci_device_1524_1421[] = "CB-720/2/4 Cardbus Controller"; +static const char pci_device_1524_1422[] = "CB-722/4 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +static const char pci_device_1532_0020[] = "LonWorks PCLTA-20 PCI LonTalk Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +static const char pci_device_1538_0303[] = "ARS106S Ultra ATA 133/100/66 Host Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +static const char pci_device_153b_1144[] = "Aureon 5.1"; +static const char pci_device_153b_1147[] = "Aureon 5.1 Sky"; +static const char pci_device_153b_1158[] = "Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS Technologies, Inc."; +static const char pci_device_153f_0001[] = "SOC-it 101 System Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "Concurrent Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +static const char pci_device_1578_5615[] = "VPMK3 [Video Processor Mk III]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMware Inc"; +static const char pci_device_15ad_0405[] = "[VMware SVGA II] PCI Display Adapter"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +static const char pci_device_15ad_0720[] = "VMware High-Speed Virtual NIC [vmxnet]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technologies"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +static const char pci_device_15b3_5a44[] = "MT23108 InfiniHost"; +static const char pci_device_15b3_5a45[] = "MT23108 [Infinihost HCA Flash Recovery]"; +static const char pci_device_15b3_5a46[] = "MT23108 PCI Bridge"; +static const char pci_device_15b3_5e8d[] = "MT25204 [InfiniHost III Lx HCA Flash Recovery]"; +static const char pci_device_15b3_6274[] = "MT25204 [InfiniHost III Lx HCA]"; +static const char pci_device_15b3_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_15b3_6279[] = "MT25208 [InfiniHost III Ex HCA Flash Recovery]"; +static const char pci_device_15b3_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_1100[] = "E8001-66442 PCI Express CIC"; +static const char pci_device_15bc_2922[] = "64 Bit, 133MHz PCI-X Exerciser & Protocol Checker"; +static const char pci_device_15bc_2928[] = "64 Bit, 66MHz PCI Exerciser & Analyzer"; +static const char pci_device_15bc_2929[] = "64 Bit, 133MHz PCI-X Analyzer & Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +static const char pci_device_15c5_8010[] = "1394b - 1394 Firewire 3-Port Host Adapter Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +static const char pci_device_15e9_1841[] = "ADMA-100 DiscStaQ ATA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +static const char pci_device_15ec_3101[] = "FC3101 Profibus DP 1 Channel PCI"; +static const char pci_device_15ec_5102[] = "FC5102"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_0610[] = "FarSync T1U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0620[] = "FarSync T2U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0640[] = "FarSync T4U (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_1610[] = "FarSync TE1 (T1,E1)"; +static const char pci_device_1619_2610[] = "FarSync DSL-S1 (SHDSL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_161f[] = "Rioworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1626[] = "TDK Semiconductor Corp."; +static const char pci_device_1626_8410[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1637[] = "Linksys"; +static const char pci_device_1637_3874[] = "Linksys 802.11b WMP11 PCI Wireless card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_3052[] = "SmartLink SmartPCI562 56K Modem"; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165f[] = "Linux Media Labs, LLC"; +static const char pci_device_165f_1020[] = "LMLM4 MPEG-4 encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +static const char pci_device_1668_0100[] = "Mini-PCI bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_166d[] = "Broadcom Corporation"; +static const char pci_device_166d_0001[] = "SiByte BCM1125/1125H/1250 System-on-a-Chip PCI"; +static const char pci_device_166d_0002[] = "SiByte BCM1125H/1250 System-on-a-Chip HyperTransport"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1677[] = "Bernecker + Rainer"; +static const char pci_device_1677_104e[] = "5LS172.6 B&R Dual CAN Interface Card"; +static const char pci_device_1677_12d7[] = "5LS172.61 B&R Dual CAN Interface Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167b[] = "ZyDAS Technology Corp."; +static const char pci_device_167b_2102[] = "ZyDAS ZD1202"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_167b_2102_187e_3406[] = "ZyAIR B-122 CardBus 11Mbs Wireless LAN Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +static const char pci_device_1681_0010[] = "Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1682[] = "XFX Pine Group Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1688[] = "CastleNet Technology Inc."; +static const char pci_device_1688_1170[] = "WLAN 802.11b card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_168c[] = "Atheros Communications, Inc."; +static const char pci_device_168c_0007[] = "AR5000 802.11a Wireless Adapter"; +static const char pci_device_168c_0011[] = "AR5210 802.11a NIC"; +static const char pci_device_168c_0012[] = "AR5211 802.11ab NIC"; +static const char pci_device_168c_0013[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1113_d301[] = "Philips CPWNA100 Wireless CardBus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3202[] = "D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3203[] = "DWL-G520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a12[] = "D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a13[] = "D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a14[] = "D-Link AirPremier DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a17[] = "D-Link AirPremier DWL-G680 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a18[] = "D-Link AirPremier DWL-G550 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a63[] = "D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a94[] = "C54C Wireless 801.11g cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1385_4d00[] = "Netgear WG311T Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1458_e911[] = "Gigabyte GN-WIAG02"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_14b7_0a60[] = "8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_0013[] = "AirPlus XtremeG DWL-G650 Wireless PCMCIA Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1025[] = "DWL-G650B2 Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1027[] = "Netgate NL-3054CB ARIES b/g CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2026[] = "Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2041[] = "Netgate 5354MP Plus ARIES2 b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2042[] = "Netgate 5354MP Plus ARIES2 a/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_16ab_7302[] = "Trust Speedshare Turbo Pro Wireless PCI Adapter"; +#endif +static const char pci_device_168c_001a[] = "AR5005G 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a15[] = "D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a16[] = "D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a23[] = "D-Link AirPlus G DWL-G520+A Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a24[] = "D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_1052[] = "TP-Link TL-WN510G Wireless CardBus Adapter"; +#endif +static const char pci_device_168c_001b[] = "AR5006X 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a19[] = "D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a22[] = "D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter"; +#endif +static const char pci_device_168c_0020[] = "AR5005VL 802.11bg Wireless NIC"; +static const char pci_device_168c_1014[] = "AR5212 802.11abg NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1695[] = "EPoX Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_169c[] = "Netcell Corporation"; +static const char pci_device_169c_0044[] = "Revolution Storage Processing Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16a5[] = "Tekram Technology Co.,Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1100[] = "GL24110P"; +static const char pci_device_16ab_1101[] = "PLX9052 PCMCIA-to-PCI Wireless LAN"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +static const char pci_device_16ab_8501[] = "WL-8305 Wireless LAN PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ae[] = "Safenet Inc"; +static const char pci_device_16ae_1141[] = "SafeXcel-1141"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16af[] = "SparkLAN Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b4[] = "Aspex Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b8[] = "Sonnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c8[] = "Octasic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c9[] = "EONIC B.V. The Netherlands"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ca[] = "CENATEK Inc"; +static const char pci_device_16ca_0001[] = "Rocket Drive DL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16cd[] = "Densitron Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ce[] = "Roland Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16df[] = "PIKA Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e3[] = "European Space Agency"; +static const char pci_device_16e3_1e0f[] = "LEON2FT Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_00ff[] = "USR997900 10/100 Mbps PCI Network Card"; +static const char pci_device_16ec_0116[] = "USR997902 10/100/1000 Mbps PCI Network Card"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ed[] = "Sycron N. V."; +static const char pci_device_16ed_1001[] = "UMIO communication card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f3[] = "Jetway Information Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f4[] = "Vweb Corp"; +static const char pci_device_16f4_8000[] = "VW2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1702[] = "Internet Machines Corporation (IMC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave"; +static const char pci_device_170b_0100[] = "NSP2000-SSL crypto accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1725[] = "Vitesse Semiconductor"; +static const char pci_device_1725_7174[] = "VSC7174 PCI/PCI-X Serial ATA Host Bus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +static const char pci_device_172a_13c8[] = "AEP SureWare Runner 1000V3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1734[] = "Fujitsu Siemens Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +static const char pci_device_1737_0013[] = "WMP54G Wireless Pci Card"; +static const char pci_device_1737_0015[] = "WMP54GS Wireless Pci Card"; +static const char pci_device_1737_1032[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0015[] = "EG1032 v2 Instant Gigabit Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0024[] = "EG1032 v3 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_1064[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1064_1737_0016[] = "EG1064 v2 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1737_ab09[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03e9[] = "AC1001 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +static const char pci_device_173b_03eb[] = "AC1003 Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1749[] = "RLX Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174d[] = "WellX Telecom SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175c[] = "AudioScience Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1775[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1797[] = "JumpTec h, GMBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +static const char pci_device_1799_6001[] = "Wireless PCI Card - F5D6001"; +static const char pci_device_1799_6020[] = "Wireless PCMCIA Card - F5D6020"; +static const char pci_device_1799_6060[] = "Wireless PDA Card - F5D6060"; +static const char pci_device_1799_7000[] = "Wireless PCI Card - F5D7000"; +static const char pci_device_1799_7010[] = "BCM4306 802.11b/g Wireless Lan Controller F5D7010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_179c[] = "Data Patterns"; +static const char pci_device_179c_0557[] = "DP-PCI-557 [PCI 1553B]"; +static const char pci_device_179c_0566[] = "DP-PCI-566 [Intelligent PCI 1553B]"; +static const char pci_device_179c_5031[] = "DP-CPCI-5031-Synchro Module"; +static const char pci_device_179c_5121[] = "DP-CPCI-5121-IP Carrier"; +static const char pci_device_179c_5211[] = "DP-CPCI-5211-IP Carrier"; +static const char pci_device_179c_5679[] = "AGE Display Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17a0[] = "Genesys Logic, Inc"; +static const char pci_device_17a0_8033[] = "GL880S USB 1.1 controller"; +static const char pci_device_17a0_8034[] = "GL880S USB 2.0 controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17aa[] = "Lenovo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b3[] = "Hawking Technologies"; +static const char pci_device_17b3_ab08[] = "PN672TX 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b4[] = "Indra Networks, Inc."; +static const char pci_device_17b4_0011[] = "WebEnhance 100 GZIP Compression Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c0[] = "Wistron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c2[] = "Newisys, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cb[] = "Airgo Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cf[] = "Z-Com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d3[] = "Areca Technology Corp."; +static const char pci_device_17d3_1110[] = "ARC-1110 4-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1120[] = "ARC-1120 8-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1130[] = "ARC-1130 12-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1160[] = "ARC-1160 16-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1210[] = "ARC-1210 4-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1220[] = "ARC-1220 8-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1230[] = "ARC-1230 12-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1260[] = "ARC-1260 16-Port PCI-Express to SATA RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d5[] = "S2io Inc."; +static const char pci_device_17d5_5831[] = "Xframe 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5831_103c_12d5[] = "HP PCI-X 133MHz 10GbE SR Fiber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_17d5_5832[] = "Xframe II 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17de[] = "KWorld Computer Co. Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ee[] = "Connect Components Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17f2[] = "Albatron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17fe[] = "Linksys, A Division of Cisco Systems"; +static const char pci_device_17fe_2120[] = "WMP11v4 802.11b PCI card"; +static const char pci_device_17fe_2220[] = "[AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17fe_2220_17fe_2220[] = "WPC54G ver. 4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ff[] = "Benq Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1814[] = "RaLink"; +static const char pci_device_1814_0101[] = "Wireless PCI Adapter RT2400 / RT2460"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1043_0127[] = "WiFi-b add-on Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1462_6828[] = "PC11B2 (MS-6828) Wireless 11b PCI Card"; +#endif +static const char pci_device_1814_0200[] = "RT2500 802.11g PCI [PC54G2]"; +static const char pci_device_1814_0201[] = "RT2500 802.11g Cardbus/mini-PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1043_130f[] = "WL-130g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001e[] = "CWC-854 Wireless-G CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001f[] = "CWM-854 Wireless-G Mini PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_0020[] = "CWP-854 Wireless-G PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e381[] = "GN-WMKG 802.11b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e931[] = "GN-WIKG 802.11b/g mini-PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1462_6835[] = "Wireless 11G CardBus CB54G2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1737_0032[] = "WMP54G 2.0 PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_700a[] = "F5D7000 Wireless G Desktop Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_701a[] = "F5D7010 Wireless G Notebook Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_185f_22a0[] = "CN-WF513 Wireless Cardbus Adapter"; +#endif +static const char pci_device_1814_0301[] = "RT2561/RT61 802.11g PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0301_2561_1814[] = "Intellinet Wireless G PCI Adapter"; +#endif +static const char pci_device_1814_0401[] = "Ralink RT2600 802.11 MIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1820[] = "InfiniCon Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1822[] = "Twinhan Technology Co. Ltd"; +static const char pci_device_1822_4e35[] = "Mantis DTV PCI Bridge Controller [Ver 1.0]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182d[] = "SiteCom Europe BV"; +static const char pci_device_182d_3069[] = "ISDN PCI DC-105V2"; +static const char pci_device_182d_9790[] = "WL-121 Wireless Network Adapter 100g+ [Ver.3]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1830[] = "Credence Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_183b[] = "MikroM GmbH"; +static const char pci_device_183b_08a7[] = "MVC100 DVI"; +static const char pci_device_183b_08a8[] = "MVC101 SDI"; +static const char pci_device_183b_08a9[] = "MVC102 DVI+Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1849[] = "ASRock Incorporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1854[] = "LG Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185b[] = "Compro Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185f[] = "Wistron NeWeb Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1864[] = "SilverBack"; +static const char pci_device_1864_2110[] = "ISNAP 2110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1867[] = "Topspin Communications"; +static const char pci_device_1867_5a44[] = "MT23108 InfiniHost HCA"; +static const char pci_device_1867_5a45[] = "MT23108 InfiniHost HCA flash recovery"; +static const char pci_device_1867_5a46[] = "MT23108 InfiniHost HCA bridge"; +static const char pci_device_1867_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_1867_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_187e[] = "ZyXEL Communication Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1890[] = "Egenera, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1894[] = "KNC One"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1896[] = "B&B Electronics Manufacturing Company, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18a1[] = "Astute Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ac[] = "DViCO Corporation"; +static const char pci_device_18ac_d500[] = "FusionHDTV 5"; +static const char pci_device_18ac_d810[] = "FusionHDTV 3 Gold"; +static const char pci_device_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18b8[] = "Ammasso"; +static const char pci_device_18b8_b001[] = "AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18bc[] = "Info-Tek Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c8[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c9[] = "ARVOO Engineering BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ca[] = "XGI - Xabre Graphics Inc"; +static const char pci_device_18ca_0020[] = "Volari Z7"; +static const char pci_device_18ca_0040[] = "Volari V3XT/V5/V8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18d2[] = "Sitecom"; +static const char pci_device_18d2_3069[] = "DC-105v2 ISDN controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18dd[] = "Artimi Inc"; +static const char pci_device_18dd_4c6f[] = "Artimi RTMI-100 UWB adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18e6[] = "MPL AG"; +static const char pci_device_18e6_0001[] = "OSCI [Octal Serial Communication Interface]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ec[] = "Cesnet, z.s.p.o."; +static const char pci_device_18ec_c006[] = "COMBO6"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d004[] = "COMBO-2XFP"; +#endif +static const char pci_device_18ec_c045[] = "COMBO6E"; +static const char pci_device_18ec_c050[] = "COMBO-PTM"; +static const char pci_device_18ec_c058[] = "COMBO6X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d004[] = "COMBO-2XFP"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f7[] = "Commtech, Inc."; +static const char pci_device_18f7_0001[] = "Fastcom ESCC-PCI-335"; +static const char pci_device_18f7_0002[] = "Fastcom 422/4-PCI-335"; +static const char pci_device_18f7_0004[] = "Fastcom 422/2-PCI-335"; +static const char pci_device_18f7_0005[] = "Fastcom IGESCC-PCI-ISO/1"; +static const char pci_device_18f7_000a[] = "Fastcom 232/4-PCI-335"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18fb[] = "Resilience Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1923[] = "Sangoma Technologies Corp."; +static const char pci_device_1923_0100[] = "A104d QUAD T1/E1 AFT card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1924[] = "Level 5 Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_192e[] = "TransDimension"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1931[] = "Option N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1942[] = "ClearSpeed Technology plc"; +static const char pci_device_1942_e511[] = "CSX600 Advance Accelerator Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1957[] = "Freescale Semiconductor Inc"; +static const char pci_device_1957_0080[] = "MPC8349E"; +static const char pci_device_1957_0081[] = "MPC8349"; +static const char pci_device_1957_0082[] = "MPC8347E TBGA"; +static const char pci_device_1957_0083[] = "MPC8347 TBGA"; +static const char pci_device_1957_0084[] = "MPC8347E PBGA"; +static const char pci_device_1957_0085[] = "MPC8347 PBGA"; +static const char pci_device_1957_0086[] = "MPC8343E"; +static const char pci_device_1957_0087[] = "MPC8343"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1958[] = "Faster Technology, LLC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1966[] = "Orad Hi-Tec Systems"; +static const char pci_device_1966_1975[] = "DVG64 family"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196a[] = "Sensory Networks Inc."; +static const char pci_device_196a_0101[] = "NodalCore C-1000 Content Classification Accelerator"; +static const char pci_device_196a_0102[] = "NodalCore C-2000 Content Classification Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_197b[] = "JMicron Technologies, Inc."; +static const char pci_device_197b_2360[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2363[] = "JMicron 20360/20363 AHCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1989[] = "Montilio Inc."; +static const char pci_device_1989_0001[] = "RapidFile Bridge"; +static const char pci_device_1989_8001[] = "RapidFile"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1993[] = "Innominate Security Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19a8[] = "DAQDATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ac[] = "Kasten Chase Applied Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ae[] = "Progeny Systems Corporation"; +static const char pci_device_19ae_0520[] = "4135 HFT Interface Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19d4[] = "Quixant Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19e2[] = "Vector Informatik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc0[] = "Tumsan Oy"; +static const char pci_device_1fc0_0300[] = "E2200 Dual E1/Rawpipe Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc1[] = "PathScale, Inc"; +static const char pci_device_1fc1_000d[] = "InfiniPath HT-400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fce[] = "Cognio Inc."; +static const char pci_device_1fce_0001[] = "Spectrum Analyzer PC Card (SAgE)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0020[] = "HB6 Universal PCI-PCI bridge (transparent mode)"; +static const char pci_device_3388_0021[] = "HB6 Universal PCI-PCI bridge (non-transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1090[] = "Cx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3010[] = "PPCI mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3011[] = "PPCI mezzanine (64-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_4000[] = "PMCCARR1 carrier board"; +#endif +static const char pci_device_3388_0022[] = "HiNT HB4 PCI-PCI Bridge (PCI6150)"; +static const char pci_device_3388_0026[] = "HB2 PCI-PCI Bridge"; +static const char pci_device_3388_101a[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_101b[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3842[] = "eVga.com. Corp."; +static const char pci_device_3842_c370[] = "e-GeFORCE 6600 256 DDR PCI-e"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0002_0000_0000[] = "GLoria L"; +#endif +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0003_0000_0000[] = "GLoria XL"; +#endif +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_0000_0000[] = "GLoria XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0008_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1048_0a42[] = "GLoria XXL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_000d[] = "GLint R4 rev A"; +static const char pci_device_3d3d_0011[] = "GLint R4 rev B"; +static const char pci_device_3d3d_0012[] = "GLint R5 rev A"; +static const char pci_device_3d3d_0013[] = "GLint R5 rev B"; +static const char pci_device_3d3d_0020[] = "VP10 visual processor"; +static const char pci_device_3d3d_0022[] = "VP10 visual processor"; +static const char pci_device_3d3d_0024[] = "VP9 visual processor"; +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_07a1[] = "Wildcat III 6210"; +static const char pci_device_3d3d_07a2[] = "Sun XVR-500 Graphics Accelerator"; +static const char pci_device_3d3d_07a3[] = "Wildcat IV 7210"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4144[] = "Alpha Data"; +static const char pci_device_4144_0044[] = "ADM-XRCIIPro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4321[] = "Tata Power Strategic Electronics Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0016[] = "iTVC16 (CX23416) MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0003[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0009[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0807[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4001[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4009[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4801[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4803[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8003[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_c801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e807[] = "WinTV PVR 500 (1st unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e817[] = "WinTV PVR 500 (2nd unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0270_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_fff3[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_ffff[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_4070_8801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0092[] = "VideOh! AVC-2010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0093[] = "VideOh! AVC-2410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_ff92_0070[] = "PVR-550"; +#endif +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4000[] = "WinTV PVR-350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4001[] = "WinTV PVR-250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4800[] = "WinTV PVR-350 (V1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_12ab_0000[] = "MPG160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3ce[] = "M179"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3cf[] = "M179"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_494f[] = "ACCES I/O Products, Inc."; +static const char pci_device_494f_10e8[] = "LPCI-COM-8SM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +static const char pci_device_4c53_0000[] = "PLUSTEST device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3000[] = "PLUSTEST card (PC104+)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3001[] = "PLUSTEST card (PMC)"; +#endif +static const char pci_device_4c53_0001[] = "PLUSTEST-MM device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0001_4c53_3002[] = "PLUSTEST-MM card (PMC)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +static const char pci_device_5168_0301[] = "FlyDVB-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8110[] = "Savage 4 LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "Thinkpad T20/T22"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1179_0001[] = "86C584 SuperSavage/IXC Toshiba"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "VT8375 [ProSavage8 KM266/KL266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +static const char pci_device_544c_0350[] = "TL880-based HDTV/ATSC tuner"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +static const char pci_device_5654_3132[] = "OpenSwitch12"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5851[] = "Exacq Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin fuer Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +static const char pci_device_6666_0004[] = "PCCOM2"; +static const char pci_device_6666_0101[] = "PCI 8255/8254 I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7063[] = "pcHDTV"; +static const char pci_device_7063_2000[] = "HD-2000"; +static const char pci_device_7063_3000[] = "HD-3000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_807d[] = "Asustek Computer, Inc."; +#endif +static const char pci_vendor_8086[] = "Intel Corporation"; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145 Fast Ethernet"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0309[] = "80303 I/O Processor PCI-to-PCI Bridge"; +static const char pci_device_8086_030d[] = "80312 I/O Companion Chip PCI-to-PCI Bridge"; +static const char pci_device_8086_0326[] = "6700/6702PXH I/OxAPIC Interrupt Controller A"; +static const char pci_device_8086_0327[] = "6700PXH I/OxAPIC Interrupt Controller B"; +static const char pci_device_8086_0329[] = "6700PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_032a[] = "6700PXH PCI Express-to-PCI Bridge B"; +static const char pci_device_8086_032c[] = "6702PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_0330[] = "80332 [Dobson] I/O processor (A-Segment Bridge)"; +static const char pci_device_8086_0331[] = "80332 [Dobson] I/O processor (A-Segment IOAPIC)"; +static const char pci_device_8086_0332[] = "80332 [Dobson] I/O processor (B-Segment Bridge)"; +static const char pci_device_8086_0333[] = "80332 [Dobson] I/O processor (B-Segment IOAPIC)"; +static const char pci_device_8086_0334[] = "80332 [Dobson] I/O processor (ATU)"; +static const char pci_device_8086_0335[] = "80331 [Lindsay] I/O processor (PCI-X Bridge)"; +static const char pci_device_8086_0336[] = "80331 [Lindsay] I/O processor (ATU)"; +static const char pci_device_8086_0340[] = "41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge)"; +static const char pci_device_8086_0341[] = "41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge)"; +static const char pci_device_8086_0370[] = "80333 Segment-A PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0371[] = "80333 A-Bus IOAPIC"; +static const char pci_device_8086_0372[] = "80333 Segment-B PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0373[] = "80333 B-Bus IOAPIC"; +static const char pci_device_8086_0374[] = "80333 Address Translation Unit"; +static const char pci_device_8086_0482[] = "82375EB/SB PCI to EISA Bridge"; +static const char pci_device_8086_0483[] = "82424TX/ZX [Saturn] CPU to PCI bridge"; +static const char pci_device_8086_0484[] = "82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge"; +static const char pci_device_8086_0486[] = "82425EX/ZX [Aries] PCIset with ISA bridge"; +static const char pci_device_8086_04a3[] = "82434LX/NX [Mercury/Neptune] Processor to PCI bridge"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0500[] = "E8870 Processor bus control"; +static const char pci_device_8086_0501[] = "E8870 Memory controller"; +static const char pci_device_8086_0502[] = "E8870 Scalability Port 0"; +static const char pci_device_8086_0503[] = "E8870 Scalability Port 1"; +static const char pci_device_8086_0510[] = "E8870IO Hub Interface Port 0 registers (8-bit compatibility port)"; +static const char pci_device_8086_0511[] = "E8870IO Hub Interface Port 1 registers"; +static const char pci_device_8086_0512[] = "E8870IO Hub Interface Port 2 registers"; +static const char pci_device_8086_0513[] = "E8870IO Hub Interface Port 3 registers"; +static const char pci_device_8086_0514[] = "E8870IO Hub Interface Port 4 registers"; +static const char pci_device_8086_0515[] = "E8870IO General SIOH registers"; +static const char pci_device_8086_0516[] = "E8870IO RAS registers"; +static const char pci_device_8086_0530[] = "E8870SP Scalability Port 0 registers"; +static const char pci_device_8086_0531[] = "E8870SP Scalability Port 1 registers"; +static const char pci_device_8086_0532[] = "E8870SP Scalability Port 2 registers"; +static const char pci_device_8086_0533[] = "E8870SP Scalability Port 3 registers"; +static const char pci_device_8086_0534[] = "E8870SP Scalability Port 4 registers"; +static const char pci_device_8086_0535[] = "E8870SP Scalability Port 5 registers"; +static const char pci_device_8086_0536[] = "E8870SP Interleave registers 0 and 1"; +static const char pci_device_8086_0537[] = "E8870SP Interleave registers 2 and 3"; +static const char pci_device_8086_0600[] = "RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01af[] = "SRCZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01c1[] = "ICP Vortex GDT8546RZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01f7[] = "SCRU32"; +#endif +static const char pci_device_8086_061f[] = "80303 I/O Processor"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1002[] = "PRO/1000 F Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1028_011c[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_3108[] = "PRO/1000 XT Network Connection"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100a[] = "82540EM Gigabit Ethernet Controller"; +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1028_0123[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1079_891f[] = "82544GC Based Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_8086_110d[] = "82544GC Based Network Connection"; +#endif +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0265[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0267[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_026a[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1024_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_002e[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0151[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_107b_8920[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_028e[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1000[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_0e11_00db[] = "NC7170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1014_027c[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_18fb_7872[] = "RESlink-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1fc1_0026[] = "Niagara 2260 Bypass Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1012[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_101a[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1003[] = "PRO/1000 MF Server Adapter (LX)"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_0e11_00dc[] = "NC6170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1013[] = "82541EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_0013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1013[] = "IBM ThinkCentre Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1113[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1014[] = "82541ER Gigabit Ethernet Controller"; +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_1016[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1014_052c[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_8086_1016[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1017[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1017_8086_1017[] = "PR0/1000 MT Desktop Connection"; +#endif +static const char pci_device_8086_1018[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1018_8086_1018[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1019[] = "82547EI Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_1019[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_e000[] = "Intel Gigabit Ethernet (Kenai II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_1019[] = "PRO/1000 CT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_301f[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_101a[] = "82547EI Gigabit Ethernet Controller (Mobile)"; +static const char pci_device_8086_101d[] = "82546EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101d_8086_1000[] = "PRO/1000 MT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_101e[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1014_0549[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_8086_101e[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1026[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1000[] = "PRO/1000 MT Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1002[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1026[] = "PRO/1000 MT Server Connection"; +#endif +static const char pci_device_8086_1027[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_103c_3103[] = "NC310F PCI-X Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1001[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1002[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1003[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1027[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1028[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1028_8086_1028[] = "PRO/1000 MB Server Adapter"; +#endif +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_813c_104d[] = "Vaio PCG-GRV616G"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1038_0e11_0098[] = "Evo N600c"; +#endif +static const char pci_device_8086_1039[] = "82801DB PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1039_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_103a[] = "82801DB PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801DB PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801DB PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801DB PRO/100 VE (MOB) Ethernet Controller"; +static const char pci_device_8086_103e[] = "82801DB PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1043[] = "PRO/Wireless LAN 2100 3B Mini PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_8086_2527[] = "MIM2000/Centrino"; +#endif +static const char pci_device_8086_1048[] = "PRO/10GbE LR Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a01f[] = "PRO/10GbE LR Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a11f[] = "PRO/10GbE LR Server Adapter"; +#endif +static const char pci_device_8086_104b[] = "Ethernet Controller"; +static const char pci_device_8086_1050[] = "82562EZ 10/100 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_728c[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_758c[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3020[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_302f[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_1051[] = "82801EB/ER (ICH5/ICH5R) integrated LAN Controller"; +static const char pci_device_8086_1052[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1053[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_105e[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_105f[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1060[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1064[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1064_1043_80f8[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_1065[] = "82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1066[] = "82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1067[] = "82562 EM/EX/GX - PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1068[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_1069[] = "82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_106a[] = "82562G - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_106b[] = "82562G - PRO/100 VE Ethernet Controller Mobile"; +static const char pci_device_8086_1075[] = "82547GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_0075[] = "PRO/1000 CT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_1075[] = "PRO/1000 CT Network Connection"; +#endif +static const char pci_device_8086_1076[] = "82541GI/PI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_0076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1176[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1276[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1077[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_0077[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_1077[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1078[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1078_8086_1078[] = "PRO/1000 MT Network Connection"; +#endif +static const char pci_device_8086_1079[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12a6[] = "HP Dual Port 1000Base-T [A9900A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12cf[] = "HP Core Dual Port 1000Base-T [AB352A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1fc1_0027[] = "Niagara 2261 Failover NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_0079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1179[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_117a[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_103c_12a8[] = "HP Dual Port 1000base-SX [A9899A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_107a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_127a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107b[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_007b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_107b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +static const char pci_device_8086_107c[] = "82541PI Gigabit Ethernet Controller"; +static const char pci_device_8086_107d[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107e[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107f[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_1080[] = "FA82537EP 56K V.92 Data/Fax Modem PCI"; +static const char pci_device_8086_1081[] = "Enterprise Southbridge LAN Copper"; +static const char pci_device_8086_1082[] = "Enterprise Southbridge LAN fiber"; +static const char pci_device_8086_1083[] = "Enterprise Southbridge LAN SERDES"; +static const char pci_device_8086_1084[] = "Enterprise Southbridge IDE Redirection"; +static const char pci_device_8086_1085[] = "Enterprise Southbridge Serial Port Redirection"; +static const char pci_device_8086_1086[] = "Enterprise Southbridge IPMI/KCS0"; +static const char pci_device_8086_1087[] = "Enterprise Southbridge UHCI Redirection"; +static const char pci_device_8086_1089[] = "Enterprise Southbridge BT"; +static const char pci_device_8086_108a[] = "82546EB Gigabit Ethernet Controller"; +static const char pci_device_8086_108b[] = "82573V Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108c[] = "82573E Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_1096[] = "Enterprise Southbridge DPT LAN Copper"; +static const char pci_device_8086_1097[] = "Enterprise Southbridge DPT LAN fiber"; +static const char pci_device_8086_1098[] = "Enterprise Southbridge DPT LAN SERDES"; +static const char pci_device_8086_1099[] = "82546GB Quad Port Server Adapter"; +static const char pci_device_8086_109a[] = "82573L Gigabit Ethernet Controller"; +static const char pci_device_8086_1107[] = "PRO/1000 MF Server Adapter (LX)"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4532[] = "D815EEA2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "Intel IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "8255xER/82551IT Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1070[] = "PC6 mainboard"; +#endif +static const char pci_device_8086_1221[] = "82092AA PCI to PCMCIA Bridge"; +static const char pci_device_8086_1222[] = "82092AA IDE Controller"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2500/2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_108e_10cf[] = "EtherExpress PRO/100(B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_110a_008b[] = "82551QM Fast Ethernet Multifuction PCI/CardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_10e0[] = "PSL09 PrPMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3411[] = "SDS2 Mainboard"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB PIIX IDE Interface"; +static const char pci_device_8086_123b[] = "82380PB PCI to PCI Docking Bridge"; +static const char pci_device_8086_123c[] = "82380AB (MISA) Mobile PCI-to-ISA Bridge"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123e[] = "82466GX (IHPC) Integrated Hot-Plug Controller"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "82752 (752) AGP Graphics Accelerator"; +static const char pci_device_8086_124b[] = "82380FB (MPCI2) Mobile Docking Controller"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_4c53_1090[] = "Cx9/Vx9 mainboard"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, HP NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "HP NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1010[] = "CG1-RADIO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1020[] = "CU2-QUARTET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1040[] = "CU1-CHORUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_3100[] = "CX1-BAND"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1a30_1028_010e[] = "Optiplex GX240"; +#endif +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_1a38[] = "Server DMA Controller"; +static const char pci_device_8086_1a48[] = "PRO/10GbE SR Server Adapter"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_110a_0051[] = "Activy 2xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1734_1025[] = "Activy 3xx"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_8086_4532[] = "D815EEA2 mainboard"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2446[] = "82801BA/BAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801 Mobile PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0265[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0267[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_026a[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1179_ff01[] = "PRO/100 VE Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801 PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244e_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA LPC Interface Controller"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1013_5959[] = "Crystal WMD Audio Codec"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_101f_1025[] = "Acer 620 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1179_0001[] = "Toshiba Satellite 1110 Z15 internal Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_248b[] = "82801CA Ultra ATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c1[] = "82801DBL (ICH4-L) IDE Controller"; +static const char pci_device_8086_24c2[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1509_2990[] = "Averatec 5110H laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c3[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24c4[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c5[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_0e11_00b8[] = "Analog Devices Inc. codec [SoundMAX]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1458_a002[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24c6[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_8086_24c7[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24ca[] = "82801DBM (ICH4-M) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24cb[] = "82801DB (ICH4) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24cc[] = "82801DBM (ICH4-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cc_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24cd[] = "82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_011d[] = "Latitude D600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1509_1968[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24d0[] = "82801EB/ER (ICH5/ICH5R) LPC Interface Bridge"; +static const char pci_device_8086_24d1[] = "82801EB (ICH5) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1043_80a6[] = "P4P800 SE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1458_24d1[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d2[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1458_24d2[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d3[] = "82801EB/ER (ICH5/ICH5R) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1043_80a6[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d4[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d5[] = "82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_12bc[] = "Analog Devices codec [SoundMAX Integrated Digital Audio]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_80f3[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_810f[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1458_a002[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_0080[] = "65PE Neo2-V (MS-6788) mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_a000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e001[] = "Desktop Board D865GBF"; +#endif +static const char pci_device_8086_24d6[] = "82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d6_103c_006a[] = "nx9500"; +#endif +static const char pci_device_8086_24d7[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24db[] = "82801EB/ER (ICH5/ICH5R) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7580[] = "MSI 875P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_24db[] = "P4C800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24dc[] = "82801EB (ICH5) LPC Interface Bridge"; +static const char pci_device_8086_24dd[] = "82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1458_5006[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24de[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24df[] = "82801ER (ICH5R) SATA Controller"; +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "E7500 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "E7500/E7501 Host RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2543[] = "E7500/E7501 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2544[] = "E7500/E7501 Hub Interface B RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2544_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_2545[] = "E7500/E7501 Hub Interface C PCI-to-PCI Bridge"; +static const char pci_device_8086_2546[] = "E7500/E7501 Hub Interface C RASUM Controller"; +static const char pci_device_8086_2547[] = "E7500/E7501 Hub Interface D PCI-to-PCI Bridge"; +static const char pci_device_8086_2548[] = "E7500/E7501 Hub Interface D RASUM Controller"; +static const char pci_device_8086_254c[] = "E7501 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2550[] = "E7505 Memory Controller Hub"; +static const char pci_device_8086_2551[] = "E7505/E7205 Series RAS Controller"; +static const char pci_device_8086_2552[] = "E7505/E7205 PCI-to-AGP Bridge"; +static const char pci_device_8086_2553[] = "E7505 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2554[] = "E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller"; +static const char pci_device_8086_255d[] = "E7205 Memory Controller Hub"; +static const char pci_device_8086_2560[] = "82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1458_2560[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2570[] = "82865G/PE/P DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1043_80f2[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1458_2570[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +static const char pci_device_8086_2571[] = "82865G/PE/P PCI to AGP Controller"; +static const char pci_device_8086_2572[] = "82865G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1028_019d[] = "Dimension 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1043_80a5[] = "P5P800-MX Mainboard"; +#endif +static const char pci_device_8086_2573[] = "82865G/PE/P PCI to CSA Bridge"; +static const char pci_device_8086_2576[] = "82865G/PE/P Processor to I/O Memory Interface"; +static const char pci_device_8086_2578[] = "82875P/E7210 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1458_2578[] = "GA-8KNXP motherboard (875P)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1462_7580[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_15d9_4580[] = "P4SCE Motherboard"; +#endif +static const char pci_device_8086_2579[] = "82875P Processor to AGP Controller"; +static const char pci_device_8086_257b[] = "82875P/E7210 Processor to PCI to CSA Bridge"; +static const char pci_device_8086_257e[] = "82875P/E7210 Processor to I/O Memory Interface"; +static const char pci_device_8086_2580[] = "915G/P/GV/GL/PL/910GL Express Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1458_2580[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2581[] = "915G/P/GV/GL/PL/910GL Express PCI Express Root Port"; +static const char pci_device_8086_2582[] = "82915G/GV/910GL Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1028_1079[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1458_2582[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2584[] = "925X/XE Express Memory Controller Hub"; +static const char pci_device_8086_2585[] = "925X/XE Express PCI Express Root Port"; +static const char pci_device_8086_2588[] = "E7220/E7221 Memory Controller Hub"; +static const char pci_device_8086_2589[] = "E7220/E7221 PCI Express Root Port"; +static const char pci_device_8086_258a[] = "E7221 Integrated Graphics Controller"; +static const char pci_device_8086_2590[] = "Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_a304_81b7[] = "Vaio VGN-S3XP"; +#endif +static const char pci_device_8086_2591[] = "Mobile 915GM/PM Express PCI Express Root Port"; +static const char pci_device_8086_2592[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_25a1[] = "6300ESB LPC Interface Controller"; +static const char pci_device_8086_25a2[] = "6300ESB PATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a3[] = "6300ESB SATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a4[] = "6300ESB SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a6[] = "6300ESB AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_4c53_10b0[] = "CL9 mainboard"; +#endif +static const char pci_device_8086_25a7[] = "6300ESB AC'97 Modem Controller"; +static const char pci_device_8086_25a9[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25aa[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ab[] = "6300ESB Watchdog Timer"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ac[] = "6300ESB I/O Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ad[] = "6300ESB USB2 Enhanced Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ae[] = "6300ESB 64-bit PCI-X Bridge"; +static const char pci_device_8086_25b0[] = "6300ESB SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25c0[] = "Workstation Memory Controller Hub"; +static const char pci_device_8086_25d0[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25d4[] = "Server Memory Contoller Hub"; +static const char pci_device_8086_25d8[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25e2[] = "Server PCI Express x4 Port 2"; +static const char pci_device_8086_25e3[] = "Server PCI Express x4 Port 3"; +static const char pci_device_8086_25e4[] = "Server PCI Express x4 Port 4"; +static const char pci_device_8086_25e5[] = "Server PCI Express x4 Port 5"; +static const char pci_device_8086_25e6[] = "Server PCI Express x4 Port 6"; +static const char pci_device_8086_25e7[] = "Server PCI Express x4 Port 7"; +static const char pci_device_8086_25e8[] = "Server AMB Memory Mapped Registers"; +static const char pci_device_8086_25f0[] = "Server Error Reporting Registers"; +static const char pci_device_8086_25f1[] = "Reserved Registers"; +static const char pci_device_8086_25f3[] = "Reserved Registers"; +static const char pci_device_8086_25f5[] = "Server FBD Registers"; +static const char pci_device_8086_25f6[] = "Server FBD Registers"; +static const char pci_device_8086_25f7[] = "Server PCI Express x8 Port 2-3"; +static const char pci_device_8086_25f8[] = "Server PCI Express x8 Port 4-5"; +static const char pci_device_8086_25f9[] = "Server PCI Express x8 Port 6-7"; +static const char pci_device_8086_25fa[] = "Server PCI Express x16 Port 4-7"; +static const char pci_device_8086_2600[] = "E8500/E8501 Hub Interface 1.5"; +static const char pci_device_8086_2601[] = "E8500/E8501 PCI Express x4 Port D"; +static const char pci_device_8086_2602[] = "E8500/E8501 PCI Express x4 Port C0"; +static const char pci_device_8086_2603[] = "E8500/E8501 PCI Express x4 Port C1"; +static const char pci_device_8086_2604[] = "E8500/E8501 PCI Express x4 Port B0"; +static const char pci_device_8086_2605[] = "E8500/E8501 PCI Express x4 Port B1"; +static const char pci_device_8086_2606[] = "E8500/E8501 PCI Express x4 Port A0"; +static const char pci_device_8086_2607[] = "E8500/E8501 PCI Express x4 Port A1"; +static const char pci_device_8086_2608[] = "E8500/E8501 PCI Express x8 Port C"; +static const char pci_device_8086_2609[] = "E8500/E8501 PCI Express x8 Port B"; +static const char pci_device_8086_260a[] = "E8500/E8501 PCI Express x8 Port A"; +static const char pci_device_8086_260c[] = "E8500/E8501 IMI Registers"; +static const char pci_device_8086_2610[] = "E8500/E8501 Front Side Bus, Boot, and Interrupt Registers"; +static const char pci_device_8086_2611[] = "E8500/E8501 Address Mapping Registers"; +static const char pci_device_8086_2612[] = "E8500/E8501 RAS Registers"; +static const char pci_device_8086_2613[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2614[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2615[] = "E8500/E8501 Miscellaneous Registers"; +static const char pci_device_8086_2617[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2618[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2619[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261a[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261b[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261c[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261d[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261e[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2620[] = "E8500/E8501 eXternal Memory Bridge"; +static const char pci_device_8086_2621[] = "E8500/E8501 XMB Miscellaneous Registers"; +static const char pci_device_8086_2622[] = "E8500/E8501 XMB Memory Interleaving Registers"; +static const char pci_device_8086_2623[] = "E8500/E8501 XMB DDR Initialization and Calibration"; +static const char pci_device_8086_2624[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2625[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2626[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2627[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2640[] = "82801FB/FR (ICH6/ICH6R) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2641[] = "82801FBM (ICH6M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2641_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2642[] = "82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge"; +static const char pci_device_8086_2651[] = "82801FB/FW (ICH6/ICH6W) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1043_2601[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_8086_4147[] = "D915GAG Motherboard"; +#endif +static const char pci_device_8086_2652[] = "82801FR/FRW (ICH6R/ICH6RW) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2652_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_8086_2653[] = "82801FBM (ICH6M) SATA Controller"; +static const char pci_device_8086_2658[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1458_2558[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2659[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1458_2659[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265b[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1458_5006[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2660[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2660_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2662[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2"; +static const char pci_device_8086_2664[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3"; +static const char pci_device_8086_2666[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4"; +static const char pci_device_8086_2668[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2668_1043_814e[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_266a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1458_266a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_266c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller"; +static const char pci_device_8086_266d[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_1025_006a[] = "Conexant AC'97 CoDec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_266e[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1025_006a[] = "Realtek ALC 655 codec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0182[] = "Latitude D610 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1458_a002[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1734_105a[] = "Scenic W620"; +#endif +static const char pci_device_8086_266f[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1458_266f[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2670[] = "Enterprise Southbridge LPC"; +static const char pci_device_8086_2680[] = "Enterprise Southbridge SATA IDE"; +static const char pci_device_8086_2681[] = "Enterprise Southbridge SATA AHCI"; +static const char pci_device_8086_2682[] = "Enterprise Southbridge SATA RAID"; +static const char pci_device_8086_2683[] = "Enterprise Southbridge SATA RAID"; +static const char pci_device_8086_2688[] = "Enterprise Southbridge UHCI USB #1"; +static const char pci_device_8086_2689[] = "Enterprise Southbridge UHCI USB #2"; +static const char pci_device_8086_268a[] = "Enterprise Southbridge UHCI USB #3"; +static const char pci_device_8086_268b[] = "Enterprise Southbridge UHCI USB #4"; +static const char pci_device_8086_268c[] = "Enterprise Southbridge EHCI USB"; +static const char pci_device_8086_2690[] = "Enterprise Southbridge PCI Express Root Port 1"; +static const char pci_device_8086_2692[] = "Enterprise Southbridge PCI Express Root Port 2"; +static const char pci_device_8086_2694[] = "Enterprise Southbridge PCI Express Root Port 3"; +static const char pci_device_8086_2696[] = "Enterprise Southbridge PCI Express Root Port 4"; +static const char pci_device_8086_2698[] = "Enterprise Southbridge AC '97 Audio"; +static const char pci_device_8086_2699[] = "Enterprise Southbridge AC '97 Modem"; +static const char pci_device_8086_269a[] = "Enterprise Southbridge High Definition Audio"; +static const char pci_device_8086_269b[] = "Enterprise Southbridge SMBus"; +static const char pci_device_8086_269e[] = "Enterprise Southbridge PATA"; +static const char pci_device_8086_2770[] = "945G/GZ/P/PL Express Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2771[] = "945G/GZ/P/PL Express PCI Express Root Port"; +static const char pci_device_8086_2772[] = "945G/GZ Express Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2772_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2774[] = "955X Express Memory Controller Hub"; +static const char pci_device_8086_2775[] = "955X Express PCI Express Root Port"; +static const char pci_device_8086_2776[] = "945G/GZ Express Integrated Graphics Controller"; +static const char pci_device_8086_2778[] = "E7230 Memory Controller Hub"; +static const char pci_device_8086_2779[] = "E7230 PCI Express Root Port"; +static const char pci_device_8086_277a[] = "975X Express PCI Express Root Port"; +static const char pci_device_8086_277c[] = "975X Express Memory Controller Hub"; +static const char pci_device_8086_277d[] = "975X Express PCI Express Root Port"; +static const char pci_device_8086_2782[] = "82915G Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2792[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_27a0[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express Memory Controller Hub"; +static const char pci_device_8086_27a1[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express PCI Express Root Port"; +static const char pci_device_8086_27a2[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +static const char pci_device_8086_27a6[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +static const char pci_device_8086_27b0[] = "82801GH (ICH7DH) LPC Interface Bridge"; +static const char pci_device_8086_27b8[] = "82801GB/GR (ICH7 Family) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27b9[] = "82801GBM (ICH7-M) LPC Interface Bridge"; +static const char pci_device_8086_27bd[] = "82801GHM (ICH7-M DH) LPC Interface Bridge"; +static const char pci_device_8086_27c0[] = "82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controller IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c1[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller AHCI"; +static const char pci_device_8086_27c3[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c4[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller IDE"; +static const char pci_device_8086_27c5[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller AHCI"; +static const char pci_device_8086_27c6[] = "82801GHM (ICH7-M DH) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c8[] = "82801G (ICH7 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c9[] = "82801G (ICH7 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27ca[] = "82801G (ICH7 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cb[] = "82801G (ICH7 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cc[] = "82801G (ICH7 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27d0[] = "82801G (ICH7 Family) PCI Express Port 1"; +static const char pci_device_8086_27d2[] = "82801G (ICH7 Family) PCI Express Port 2"; +static const char pci_device_8086_27d4[] = "82801G (ICH7 Family) PCI Express Port 3"; +static const char pci_device_8086_27d6[] = "82801G (ICH7 Family) PCI Express Port 4"; +static const char pci_device_8086_27d8[] = "82801G (ICH7 Family) High Definition Audio Controller"; +static const char pci_device_8086_27da[] = "82801G (ICH7 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dc[] = "82801G (ICH7 Family) LAN Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27dc_8086_308d[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dd[] = "82801G (ICH7 Family) AC'97 Modem Controller"; +static const char pci_device_8086_27de[] = "82801G (ICH7 Family) AC'97 Audio Controller"; +static const char pci_device_8086_27df[] = "82801G (ICH7 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27e0[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 5"; +static const char pci_device_8086_27e2[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 6"; +static const char pci_device_8086_2810[] = "LPC Interface Controller"; +static const char pci_device_8086_2811[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2812[] = "LPC Interface Controller"; +static const char pci_device_8086_2814[] = "LPC Interface Controller"; +static const char pci_device_8086_2815[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2820[] = "SATA Controller 1 IDE"; +static const char pci_device_8086_2821[] = "SATA Controller AHCI"; +static const char pci_device_8086_2822[] = "SATA Controller RAID"; +static const char pci_device_8086_2824[] = "SATA Controller AHCI"; +static const char pci_device_8086_2825[] = "SATA Controller 2 IDE"; +static const char pci_device_8086_2828[] = "Mobile SATA Controller IDE"; +static const char pci_device_8086_2829[] = "Mobile SATA Controller AHCI"; +static const char pci_device_8086_282a[] = "Mobile SATA Controller RAID"; +static const char pci_device_8086_2830[] = "USB UHCI Controller #1"; +static const char pci_device_8086_2831[] = "USB UHCI Controller #2"; +static const char pci_device_8086_2832[] = "USB UHCI Controller #3"; +static const char pci_device_8086_2834[] = "USB UHCI Controller #4"; +static const char pci_device_8086_2835[] = "USB UHCI Controller #5"; +static const char pci_device_8086_2836[] = "USB2 EHCI Controller #1"; +static const char pci_device_8086_283a[] = "USB2 EHCI Controller #2"; +static const char pci_device_8086_283e[] = "SMBus Controller"; +static const char pci_device_8086_283f[] = "PCI Express Port 1"; +static const char pci_device_8086_2841[] = "PCI Express Port 2"; +static const char pci_device_8086_2843[] = "PCI Express Port 3"; +static const char pci_device_8086_2844[] = "PCI Express Port 4"; +static const char pci_device_8086_2847[] = "PCI Express Port 5"; +static const char pci_device_8086_2849[] = "PCI Express Port 6"; +static const char pci_device_8086_284b[] = "HD Audio Controller"; +static const char pci_device_8086_284f[] = "Thermal Subsystem"; +static const char pci_device_8086_2850[] = "Mobile IDE Controller"; +static const char pci_device_8086_2970[] = "Memory Controller Hub"; +static const char pci_device_8086_2971[] = "PCI Express Root Port"; +static const char pci_device_8086_2972[] = "Integrated Graphics Controller"; +static const char pci_device_8086_2973[] = "Integrated Graphics Controller"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3200[] = "GD31244 PCI-X SATA HBA"; +static const char pci_device_8086_3340[] = "82855PM Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_0890[] = "nc6000 laptop"; +#endif +static const char pci_device_8086_3341[] = "82855PM Processor to AGP Controller"; +static const char pci_device_8086_3500[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3501[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3504[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_3505[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_350c[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_350d[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_3510[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3511[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3514[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3515[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3518[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3519[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3581[] = "82852/82855 GM/GME/PM/GMV Processor to AGP Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3581_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_3582[] = "82852/855GM Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3584[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3585[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3590[] = "E7520 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1734_103e[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3591[] = "E7525/E7520 Error Reporting Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3592[] = "E7320 Memory Controller Hub"; +static const char pci_device_8086_3593[] = "E7320 Error Reporting Registers"; +static const char pci_device_8086_3594[] = "E7520 DMA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3594_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3595[] = "E7525/E7520/E7320 PCI Express Port A"; +static const char pci_device_8086_3596[] = "E7525/E7520/E7320 PCI Express Port A1"; +static const char pci_device_8086_3597[] = "E7525/E7520 PCI Express Port B"; +static const char pci_device_8086_3598[] = "E7520 PCI Express Port B1"; +static const char pci_device_8086_3599[] = "E7520 PCI Express Port C"; +static const char pci_device_8086_359a[] = "E7520 PCI Express Port C1"; +static const char pci_device_8086_359b[] = "E7525/E7520/E7320 Extended Configuration Registers"; +static const char pci_device_8086_359e[] = "E7525 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_359e_1028_0169[] = "Precision 470"; +#endif +static const char pci_device_8086_4220[] = "PRO/Wireless 2200BG"; +static const char pci_device_8086_4223[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_4224[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7050[] = "Intercast Video Capture Card"; +static const char pci_device_8086_7051[] = "PB 642365-003 (Business Video Conferencing Card)"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7110_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7111_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7112_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7113_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1060[] = "PC7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_8086_4341[] = "Cayman (CA810) Mainboard"; +#endif +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700/E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_15ad_1976[] = "virtualHW v3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_1033_0000[] = "Versa Note Vxi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_1033_80cc[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a2_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "82740 (i740) AGP Graphics Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_8500[] = "IXP4XX Intel Network Processor (IXP420/421/422/425/IXC1100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0ded[] = "mGuard-PCI AV#2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0dee[] = "mGuard-PCI AV#1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0def[] = "mGuard-PCI AV#0"; +#endif +static const char pci_device_8086_9000[] = "IXP2000 Family Network Processor"; +static const char pci_device_8086_9001[] = "IXP2400 Network Processor"; +static const char pci_device_8086_9004[] = "IXP2800 Network Processor"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12d9_000a[] = "PCI VoIP Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8401[] = "TRENDware International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8912[] = "TRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8c4a[] = "Winbond"; +static const char pci_device_8c4a_1980[] = "W89C940 misprogrammed [ne2k]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_0078[] = "AHA-2940U_CN"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7710[] = "ANA-7711F Network Accelerator Card (NAC) - Optical"; +static const char pci_device_9004_7711[] = "ANA-7711C Network Accelerator Card (NAC) - Copper"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409a = + {0x0e11, 0x409a, pci_subsys_0e11_0046_0e11_409a, 0}; +#undef pci_ss_info_0e11_409a +#define pci_ss_info_0e11_409a pci_ss_info_0e11_0046_0e11_409a +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409b = + {0x0e11, 0x409b, pci_subsys_0e11_0046_0e11_409b, 0}; +#undef pci_ss_info_0e11_409b +#define pci_ss_info_0e11_409b pci_ss_info_0e11_0046_0e11_409b +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409c = + {0x0e11, 0x409c, pci_subsys_0e11_0046_0e11_409c, 0}; +#undef pci_ss_info_0e11_409c +#define pci_ss_info_0e11_409c pci_ss_info_0e11_0046_0e11_409c +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409d = + {0x0e11, 0x409d, pci_subsys_0e11_0046_0e11_409d, 0}; +#undef pci_ss_info_0e11_409d +#define pci_ss_info_0e11_409d pci_ss_info_0e11_0046_0e11_409d +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4080 = + {0x0e11, 0x4080, pci_subsys_0e11_b178_0e11_4080, 0}; +#undef pci_ss_info_0e11_4080 +#define pci_ss_info_0e11_4080 pci_ss_info_0e11_b178_0e11_4080 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4082 = + {0x0e11, 0x4082, pci_subsys_0e11_b178_0e11_4082, 0}; +#undef pci_ss_info_0e11_4082 +#define pci_ss_info_0e11_4082 pci_ss_info_0e11_b178_0e11_4082 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4083 = + {0x0e11, 0x4083, pci_subsys_0e11_b178_0e11_4083, 0}; +#undef pci_ss_info_0e11_4083 +#define pci_ss_info_0e11_4083 pci_ss_info_0e11_b178_0e11_4083 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0003_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0003_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0003_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0006_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0006_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0006_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000a_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000a_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000a_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000b_0e11_6004 = + {0x0e11, 0x6004, pci_subsys_1000_000b_0e11_6004, 0}; +#undef pci_ss_info_0e11_6004 +#define pci_ss_info_0e11_6004 pci_ss_info_1000_000b_0e11_6004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000b_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000b_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000b_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000b_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000b_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000b_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000b_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_1000_000b_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_1000_000b_13e9_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000c_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000c_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000c_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000c_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3906 = + {0x1de1, 0x3906, pci_subsys_1000_000c_1de1_3906, 0}; +#undef pci_ss_info_1de1_3906 +#define pci_ss_info_1de1_3906 pci_ss_info_1000_000c_1de1_3906 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000f_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000f_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000f_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000f_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000f_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000f_1000_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1000_000f_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1000_000f_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1000_000f_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1000_000f_4c53_1050 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0010_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0010_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0010_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0012_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0012_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0012_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0013_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0013_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0013_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0020_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0020_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0021_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0021_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0021_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0021_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0021_124b_1070 = + {0x124b, 0x1070, pci_subsys_1000_0021_124b_1070, 0}; +#undef pci_ss_info_124b_1070 +#define pci_ss_info_124b_1070 pci_ss_info_1000_0021_124b_1070 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1000_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1000_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1300 = + {0x4c53, 0x1300, pci_subsys_1000_0021_4c53_1300, 0}; +#undef pci_ss_info_4c53_1300 +#define pci_ss_info_4c53_1300 pci_ss_info_1000_0021_4c53_1300 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1310 = + {0x4c53, 0x1310, pci_subsys_1000_0021_4c53_1310, 0}; +#undef pci_ss_info_4c53_1310 +#define pci_ss_info_4c53_1310 pci_ss_info_1000_0021_4c53_1310 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_0e11_00da = + {0x0e11, 0x00da, pci_subsys_1000_0030_0e11_00da, 0}; +#undef pci_ss_info_0e11_00da +#define pci_ss_info_0e11_00da pci_ss_info_1000_0030_0e11_00da +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0123 = + {0x1028, 0x0123, pci_subsys_1000_0030_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_1000_0030_1028_0123 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_014a = + {0x1028, 0x014a, pci_subsys_1000_0030_1028_014a, 0}; +#undef pci_ss_info_1028_014a +#define pci_ss_info_1028_014a pci_ss_info_1000_0030_1028_014a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_016c = + {0x1028, 0x016c, pci_subsys_1000_0030_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1000_0030_1028_016c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0183 = + {0x1028, 0x0183, pci_subsys_1000_0030_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_1000_0030_1028_0183 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0030_124b_1170 = + {0x124b, 0x1170, pci_subsys_1000_0030_124b_1170, 0}; +#undef pci_ss_info_124b_1170 +#define pci_ss_info_124b_1170 pci_ss_info_1000_0030_124b_1170 +static const pciSubsystemInfo pci_ss_info_1000_0030_1734_1052 = + {0x1734, 0x1052, pci_subsys_1000_0030_1734_1052, 0}; +#undef pci_ss_info_1734_1052 +#define pci_ss_info_1734_1052 pci_ss_info_1000_0030_1734_1052 +static const pciSubsystemInfo pci_ss_info_1000_0032_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0032_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0032_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0033 = + {0x1000, 0x0033, pci_subsys_1000_0040_1000_0033, 0}; +#undef pci_ss_info_1000_0033 +#define pci_ss_info_1000_0033 pci_ss_info_1000_0040_1000_0033 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0066 = + {0x1000, 0x0066, pci_subsys_1000_0040_1000_0066, 0}; +#undef pci_ss_info_1000_0066 +#define pci_ss_info_1000_0066 pci_ss_info_1000_0040_1000_0066 +static const pciSubsystemInfo pci_ss_info_1000_0062_1000_0062 = + {0x1000, 0x0062, pci_subsys_1000_0062_1000_0062, 0}; +#undef pci_ss_info_1000_0062 +#define pci_ss_info_1000_0062 pci_ss_info_1000_0062_1000_0062 +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0530 = + {0x1000, 0x0530, pci_subsys_1000_0407_1000_0530, 0}; +#undef pci_ss_info_1000_0530 +#define pci_ss_info_1000_0530 pci_ss_info_1000_0407_1000_0530 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0531 = + {0x1000, 0x0531, pci_subsys_1000_0407_1000_0531, 0}; +#undef pci_ss_info_1000_0531 +#define pci_ss_info_1000_0531 pci_ss_info_1000_0407_1000_0531 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0532 = + {0x1000, 0x0532, pci_subsys_1000_0407_1000_0532, 0}; +#undef pci_ss_info_1000_0532 +#define pci_ss_info_1000_0532 pci_ss_info_1000_0407_1000_0532 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_0407_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_0407_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_0407_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_0407_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0530 = + {0x8086, 0x0530, pci_subsys_1000_0407_8086_0530, 0}; +#undef pci_ss_info_8086_0530 +#define pci_ss_info_8086_0530 pci_ss_info_1000_0407_8086_0530 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0532 = + {0x8086, 0x0532, pci_subsys_1000_0407_8086_0532, 0}; +#undef pci_ss_info_8086_0532 +#define pci_ss_info_8086_0532 pci_ss_info_1000_0407_8086_0532 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0001 = + {0x1000, 0x0001, pci_subsys_1000_0408_1000_0001, 0}; +#undef pci_ss_info_1000_0001 +#define pci_ss_info_1000_0001 pci_ss_info_1000_0408_1000_0001 +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0002 = + {0x1000, 0x0002, pci_subsys_1000_0408_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_1000_0408_1000_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1025_004d = + {0x1025, 0x004d, pci_subsys_1000_0408_1025_004d, 0}; +#undef pci_ss_info_1025_004d +#define pci_ss_info_1025_004d pci_ss_info_1000_0408_1025_004d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0001 = + {0x1028, 0x0001, pci_subsys_1000_0408_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1000_0408_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0002 = + {0x1028, 0x0002, pci_subsys_1000_0408_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1000_0408_1028_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1734_1065 = + {0x1734, 0x1065, pci_subsys_1000_0408_1734_1065, 0}; +#undef pci_ss_info_1734_1065 +#define pci_ss_info_1734_1065 pci_ss_info_1000_0408_1734_1065 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_8086_0002 = + {0x8086, 0x0002, pci_subsys_1000_0408_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_1000_0408_8086_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3004 = + {0x1000, 0x3004, pci_subsys_1000_0409_1000_3004, 0}; +#undef pci_ss_info_1000_3004 +#define pci_ss_info_1000_3004 pci_ss_info_1000_0409_1000_3004 +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3008 = + {0x1000, 0x3008, pci_subsys_1000_0409_1000_3008, 0}; +#undef pci_ss_info_1000_3008 +#define pci_ss_info_1000_3008 pci_ss_info_1000_0409_1000_3008 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3008 = + {0x8086, 0x3008, pci_subsys_1000_0409_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_1000_0409_8086_3008 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3431 = + {0x8086, 0x3431, pci_subsys_1000_0409_8086_3431, 0}; +#undef pci_ss_info_8086_3431 +#define pci_ss_info_8086_3431 pci_ss_info_1000_0409_8086_3431 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3499 = + {0x8086, 0x3499, pci_subsys_1000_0409_8086_3499, 0}; +#undef pci_ss_info_8086_3499 +#define pci_ss_info_8086_3499 pci_ss_info_1000_0409_8086_3499 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0622_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_0622_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_0622_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_0626_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0626_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0626_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0518 = + {0x1000, 0x0518, pci_subsys_1000_1960_1000_0518, 0}; +#undef pci_ss_info_1000_0518 +#define pci_ss_info_1000_0518 pci_ss_info_1000_1960_1000_0518 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0520 = + {0x1000, 0x0520, pci_subsys_1000_1960_1000_0520, 0}; +#undef pci_ss_info_1000_0520 +#define pci_ss_info_1000_0520 pci_ss_info_1000_1960_1000_0520 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0522 = + {0x1000, 0x0522, pci_subsys_1000_1960_1000_0522, 0}; +#undef pci_ss_info_1000_0522 +#define pci_ss_info_1000_0522 pci_ss_info_1000_1960_1000_0522 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0523 = + {0x1000, 0x0523, pci_subsys_1000_1960_1000_0523, 0}; +#undef pci_ss_info_1000_0523 +#define pci_ss_info_1000_0523 pci_ss_info_1000_1960_1000_0523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_4523 = + {0x1000, 0x4523, pci_subsys_1000_1960_1000_4523, 0}; +#undef pci_ss_info_1000_4523 +#define pci_ss_info_1000_4523 pci_ss_info_1000_1960_1000_4523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_a520 = + {0x1000, 0xa520, pci_subsys_1000_1960_1000_a520, 0}; +#undef pci_ss_info_1000_a520 +#define pci_ss_info_1000_a520 pci_ss_info_1000_1960_1000_a520 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_1960_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_1960_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0520 = + {0x8086, 0x0520, pci_subsys_1000_1960_8086_0520, 0}; +#undef pci_ss_info_8086_0520 +#define pci_ss_info_8086_0520 pci_ss_info_1000_1960_8086_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0523 = + {0x8086, 0x0523, pci_subsys_1000_1960_8086_0523, 0}; +#undef pci_ss_info_8086_0523 +#define pci_ss_info_8086_0523 pci_ss_info_1000_1960_8086_0523 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4150_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4150_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4150_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4150_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_4722 = + {0x1002, 0x4722, pci_subsys_1002_4150_1002_4722, 0}; +#undef pci_ss_info_1002_4722 +#define pci_ss_info_1002_4722 pci_ss_info_1002_4150_1002_4722 +static const pciSubsystemInfo pci_ss_info_1002_4150_1458_4024 = + {0x1458, 0x4024, pci_subsys_1002_4150_1458_4024, 0}; +#undef pci_ss_info_1458_4024 +#define pci_ss_info_1458_4024 pci_ss_info_1002_4150_1458_4024 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2064 = + {0x148c, 0x2064, pci_subsys_1002_4150_148c_2064, 0}; +#undef pci_ss_info_148c_2064 +#define pci_ss_info_148c_2064 pci_ss_info_1002_4150_148c_2064 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2066 = + {0x148c, 0x2066, pci_subsys_1002_4150_148c_2066, 0}; +#undef pci_ss_info_148c_2066 +#define pci_ss_info_148c_2066 pci_ss_info_1002_4150_148c_2066 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c19 = + {0x174b, 0x7c19, pci_subsys_1002_4150_174b_7c19, 0}; +#undef pci_ss_info_174b_7c19 +#define pci_ss_info_174b_7c19 pci_ss_info_1002_4150_174b_7c19 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4150_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4150_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4150_17ee_2002 = + {0x17ee, 0x2002, pci_subsys_1002_4150_17ee_2002, 0}; +#undef pci_ss_info_17ee_2002 +#define pci_ss_info_17ee_2002 pci_ss_info_1002_4150_17ee_2002 +static const pciSubsystemInfo pci_ss_info_1002_4150_18bc_0101 = + {0x18bc, 0x0101, pci_subsys_1002_4150_18bc_0101, 0}; +#undef pci_ss_info_18bc_0101 +#define pci_ss_info_18bc_0101 pci_ss_info_1002_4150_18bc_0101 +static const pciSubsystemInfo pci_ss_info_1002_4151_1043_c004 = + {0x1043, 0xc004, pci_subsys_1002_4151_1043_c004, 0}; +#undef pci_ss_info_1043_c004 +#define pci_ss_info_1043_c004 pci_ss_info_1002_4151_1043_c004 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4152_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4152_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_4772 = + {0x1002, 0x4772, pci_subsys_1002_4152_1002_4772, 0}; +#undef pci_ss_info_1002_4772 +#define pci_ss_info_1002_4772 pci_ss_info_1002_4152_1002_4772 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c002 = + {0x1043, 0xc002, pci_subsys_1002_4152_1043_c002, 0}; +#undef pci_ss_info_1043_c002 +#define pci_ss_info_1043_c002 pci_ss_info_1002_4152_1043_c002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c01a = + {0x1043, 0xc01a, pci_subsys_1002_4152_1043_c01a, 0}; +#undef pci_ss_info_1043_c01a +#define pci_ss_info_1043_c01a pci_ss_info_1002_4152_1043_c01a +static const pciSubsystemInfo pci_ss_info_1002_4152_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4152_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4152_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4152_1787_4002 = + {0x1787, 0x4002, pci_subsys_1002_4152_1787_4002, 0}; +#undef pci_ss_info_1787_4002 +#define pci_ss_info_1787_4002 pci_ss_info_1002_4152_1787_4002 +static const pciSubsystemInfo pci_ss_info_1002_4153_1462_932c = + {0x1462, 0x932c, pci_subsys_1002_4153_1462_932c, 0}; +#undef pci_ss_info_1462_932c +#define pci_ss_info_1462_932c pci_ss_info_1002_4153_1462_932c +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4170_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4170_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_4723 = + {0x1002, 0x4723, pci_subsys_1002_4170_1002_4723, 0}; +#undef pci_ss_info_1002_4723 +#define pci_ss_info_1002_4723 pci_ss_info_1002_4170_1002_4723 +static const pciSubsystemInfo pci_ss_info_1002_4170_1458_4025 = + {0x1458, 0x4025, pci_subsys_1002_4170_1458_4025, 0}; +#undef pci_ss_info_1458_4025 +#define pci_ss_info_1458_4025 pci_ss_info_1002_4170_1458_4025 +static const pciSubsystemInfo pci_ss_info_1002_4170_148c_2067 = + {0x148c, 0x2067, pci_subsys_1002_4170_148c_2067, 0}; +#undef pci_ss_info_148c_2067 +#define pci_ss_info_148c_2067 pci_ss_info_1002_4170_148c_2067 +static const pciSubsystemInfo pci_ss_info_1002_4170_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4170_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4170_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4170_17ee_2003 = + {0x17ee, 0x2003, pci_subsys_1002_4170_17ee_2003, 0}; +#undef pci_ss_info_17ee_2003 +#define pci_ss_info_17ee_2003 pci_ss_info_1002_4170_17ee_2003 +static const pciSubsystemInfo pci_ss_info_1002_4170_18bc_0100 = + {0x18bc, 0x0100, pci_subsys_1002_4170_18bc_0100, 0}; +#undef pci_ss_info_18bc_0100 +#define pci_ss_info_18bc_0100 pci_ss_info_1002_4170_18bc_0100 +static const pciSubsystemInfo pci_ss_info_1002_4171_1043_c005 = + {0x1043, 0xc005, pci_subsys_1002_4171_1043_c005, 0}; +#undef pci_ss_info_1043_c005 +#define pci_ss_info_1043_c005 pci_ss_info_1002_4171_1043_c005 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4172_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4172_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_4773 = + {0x1002, 0x4773, pci_subsys_1002_4172_1002_4773, 0}; +#undef pci_ss_info_1002_4773 +#define pci_ss_info_1002_4773 pci_ss_info_1002_4172_1002_4773 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c003 = + {0x1043, 0xc003, pci_subsys_1002_4172_1043_c003, 0}; +#undef pci_ss_info_1043_c003 +#define pci_ss_info_1043_c003 pci_ss_info_1002_4172_1043_c003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c01b = + {0x1043, 0xc01b, pci_subsys_1002_4172_1043_c01b, 0}; +#undef pci_ss_info_1043_c01b +#define pci_ss_info_1043_c01b pci_ss_info_1002_4172_1043_c01b +static const pciSubsystemInfo pci_ss_info_1002_4172_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4172_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4172_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4172_1787_4003 = + {0x1787, 0x4003, pci_subsys_1002_4172_1787_4003, 0}; +#undef pci_ss_info_1787_4003 +#define pci_ss_info_1787_4003 pci_ss_info_1002_4172_1787_4003 +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4336_1002_4336 = + {0x1002, 0x4336, pci_subsys_1002_4336_1002_4336, 0}; +#undef pci_ss_info_1002_4336 +#define pci_ss_info_1002_4336 pci_ss_info_1002_4336_1002_4336 +static const pciSubsystemInfo pci_ss_info_1002_4336_103c_0024 = + {0x103c, 0x0024, pci_subsys_1002_4336_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_1002_4336_103c_0024 +static const pciSubsystemInfo pci_ss_info_1002_4336_161f_2029 = + {0x161f, 0x2029, pci_subsys_1002_4336_161f_2029, 0}; +#undef pci_ss_info_161f_2029 +#define pci_ss_info_161f_2029 pci_ss_info_1002_4336_161f_2029 +static const pciSubsystemInfo pci_ss_info_1002_4337_1014_053a = + {0x1014, 0x053a, pci_subsys_1002_4337_1014_053a, 0}; +#undef pci_ss_info_1014_053a +#define pci_ss_info_1014_053a pci_ss_info_1002_4337_1014_053a +static const pciSubsystemInfo pci_ss_info_1002_4337_103c_0850 = + {0x103c, 0x0850, pci_subsys_1002_4337_103c_0850, 0}; +#undef pci_ss_info_103c_0850 +#define pci_ss_info_103c_0850 pci_ss_info_1002_4337_103c_0850 +static const pciSubsystemInfo pci_ss_info_1002_4370_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4370_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4370_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4371_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4371_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4371_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4372_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4372_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4372_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4373_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4373_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4373_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4374_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4374_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4374_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4375_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4375_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4375_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4376_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4376_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4376_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4377_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4377_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4377_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4378_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4378_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4378_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00ce = + {0x1028, 0x00ce, pci_subsys_1002_4752_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_1002_4752_1028_00ce +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1002_4752_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1002_4752_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_0134 = + {0x1028, 0x0134, pci_subsys_1002_4752_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_1002_4752_1028_0134 +static const pciSubsystemInfo pci_ss_info_1002_4752_1734_007a = + {0x1734, 0x007a, pci_subsys_1002_4752_1734_007a, 0}; +#undef pci_ss_info_1734_007a +#define pci_ss_info_1734_007a pci_ss_info_1002_4752_1734_007a +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3411 = + {0x8086, 0x3411, pci_subsys_1002_4752_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_1002_4752_8086_3411 +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3427 = + {0x8086, 0x3427, pci_subsys_1002_4752_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_1002_4752_8086_3427 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_475a_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_475a_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e7 = + {0x0e11, 0xb0e7, pci_subsys_1002_4c42_0e11_b0e7, 0}; +#undef pci_ss_info_0e11_b0e7 +#define pci_ss_info_0e11_b0e7 pci_ss_info_1002_4c42_0e11_b0e7 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c46_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_1002_4c46_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_1002_4c46_1028_00b1 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b160 = + {0x0e11, 0xb160, pci_subsys_1002_4c4d_0e11_b160, 0}; +#undef pci_ss_info_0e11_b160 +#define pci_ss_info_0e11_b160 pci_ss_info_1002_4c4d_0e11_b160 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00aa = + {0x1028, 0x00aa, pci_subsys_1002_4c4d_1028_00aa, 0}; +#undef pci_ss_info_1028_00aa +#define pci_ss_info_1028_00aa pci_ss_info_1002_4c4d_1028_00aa +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00bb = + {0x1028, 0x00bb, pci_subsys_1002_4c4d_1028_00bb, 0}; +#undef pci_ss_info_1028_00bb +#define pci_ss_info_1028_00bb pci_ss_info_1002_4c4d_1028_00bb +static const pciSubsystemInfo pci_ss_info_1002_4c4d_10e1_10cf = + {0x10e1, 0x10cf, pci_subsys_1002_4c4d_10e1_10cf, 0}; +#undef pci_ss_info_10e1_10cf +#define pci_ss_info_10e1_10cf pci_ss_info_1002_4c4d_10e1_10cf +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1179_ff00 = + {0x1179, 0xff00, pci_subsys_1002_4c4d_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_1002_4c4d_1179_ff00 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_13bd_1019 = + {0x13bd, 0x1019, pci_subsys_1002_4c4d_13bd_1019, 0}; +#undef pci_ss_info_13bd_1019 +#define pci_ss_info_13bd_1019 pci_ss_info_1002_4c4d_13bd_1019 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c52_1033_8112 = + {0x1033, 0x8112, pci_subsys_1002_4c52_1033_8112, 0}; +#undef pci_ss_info_1033_8112 +#define pci_ss_info_1033_8112 pci_ss_info_1002_4c52_1033_8112 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_012a = + {0x1028, 0x012a, pci_subsys_1002_4c57_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_1002_4c57_1028_012a +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c59_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c59_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1509_1930 = + {0x1509, 0x1930, pci_subsys_1002_4c59_1509_1930, 0}; +#undef pci_ss_info_1509_1930 +#define pci_ss_info_1509_1930 pci_ss_info_1002_4c59_1509_1930 +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_515e = + {0x1002, 0x515e, pci_subsys_1002_4e44_1002_515e, 0}; +#undef pci_ss_info_1002_515e +#define pci_ss_info_1002_515e pci_ss_info_1002_4e44_1002_515e +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_5965 = + {0x1002, 0x5965, pci_subsys_1002_4e44_1002_5965, 0}; +#undef pci_ss_info_1002_5965 +#define pci_ss_info_1002_5965 pci_ss_info_1002_4e44_1002_5965 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4e45_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4e45_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1681_0002 = + {0x1681, 0x0002, pci_subsys_1002_4e45_1681_0002, 0}; +#undef pci_ss_info_1681_0002 +#define pci_ss_info_1681_0002 pci_ss_info_1002_4e45_1681_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1025_005a = + {0x1025, 0x005a, pci_subsys_1002_4e50_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1002_4e50_1025_005a +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_088c = + {0x103c, 0x088c, pci_subsys_1002_4e50_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1002_4e50_103c_088c +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_0890 = + {0x103c, 0x0890, pci_subsys_1002_4e50_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1002_4e50_103c_0890 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1734_1055 = + {0x1734, 0x1055, pci_subsys_1002_4e50_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_1002_4e50_1734_1055 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4e65_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4e65_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1681_0003 = + {0x1681, 0x0003, pci_subsys_1002_4e65_1681_0003, 0}; +#undef pci_ss_info_1681_0003 +#define pci_ss_info_1681_0003 pci_ss_info_1002_4e65_1681_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e6a_1002_4e71 = + {0x1002, 0x4e71, pci_subsys_1002_4e6a_1002_4e71, 0}; +#undef pci_ss_info_1002_4e71 +#define pci_ss_info_1002_4e71 pci_ss_info_1002_4e6a_1002_4e71 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_1681_0010 = + {0x1681, 0x0010, pci_subsys_1002_514c_1681_0010, 0}; +#undef pci_ss_info_1681_0010 +#define pci_ss_info_1681_0010 pci_ss_info_1002_514c_1681_0010 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_103a = + {0x1002, 0x103a, pci_subsys_1002_5157_1002_103a, 0}; +#undef pci_ss_info_1002_103a +#define pci_ss_info_1002_103a pci_ss_info_1002_5157_1002_103a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7146 = + {0x174b, 0x7146, pci_subsys_1002_5157_174b_7146, 0}; +#undef pci_ss_info_174b_7146 +#define pci_ss_info_174b_7146 pci_ss_info_1002_5157_174b_7146 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_029a = + {0x1014, 0x029a, pci_subsys_1002_5159_1014_029a, 0}; +#undef pci_ss_info_1014_029a +#define pci_ss_info_1014_029a pci_ss_info_1002_5159_1014_029a +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_02c8 = + {0x1014, 0x02c8, pci_subsys_1002_5159_1014_02c8, 0}; +#undef pci_ss_info_1014_02c8 +#define pci_ss_info_1014_02c8 pci_ss_info_1002_5159_1014_02c8 +static const pciSubsystemInfo pci_ss_info_1002_5159_1028_019a = + {0x1028, 0x019a, pci_subsys_1002_5159_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_1002_5159_1028_019a +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_5159_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_5159_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_5346_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5346_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5346_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5941_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5941_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5941_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5941_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5941_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5941_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5941_17af_200d = + {0x17af, 0x200d, pci_subsys_1002_5941_17af_200d, 0}; +#undef pci_ss_info_17af_200d +#define pci_ss_info_17af_200d pci_ss_info_1002_5941_17af_200d +static const pciSubsystemInfo pci_ss_info_1002_5941_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5941_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5941_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5950_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5950_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5950_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5954_1002_5954 = + {0x1002, 0x5954, pci_subsys_1002_5954_1002_5954, 0}; +#undef pci_ss_info_1002_5954 +#define pci_ss_info_1002_5954 pci_ss_info_1002_5954_1002_5954 +static const pciSubsystemInfo pci_ss_info_1002_5955_1002_5955 = + {0x1002, 0x5955, pci_subsys_1002_5955_1002_5955, 0}; +#undef pci_ss_info_1002_5955 +#define pci_ss_info_1002_5955 pci_ss_info_1002_5955_1002_5955 +static const pciSubsystemInfo pci_ss_info_1002_5955_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5955_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5955_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5961_1002_2f72 = + {0x1002, 0x2f72, pci_subsys_1002_5961_1002_2f72, 0}; +#undef pci_ss_info_1002_2f72 +#define pci_ss_info_1002_2f72 pci_ss_info_1002_5961_1002_2f72 +static const pciSubsystemInfo pci_ss_info_1002_5961_1019_4c30 = + {0x1019, 0x4c30, pci_subsys_1002_5961_1019_4c30, 0}; +#undef pci_ss_info_1019_4c30 +#define pci_ss_info_1019_4c30 pci_ss_info_1002_5961_1019_4c30 +static const pciSubsystemInfo pci_ss_info_1002_5961_12ab_5961 = + {0x12ab, 0x5961, pci_subsys_1002_5961_12ab_5961, 0}; +#undef pci_ss_info_12ab_5961 +#define pci_ss_info_12ab_5961 pci_ss_info_1002_5961_12ab_5961 +static const pciSubsystemInfo pci_ss_info_1002_5961_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5961_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5961_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5961_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5961_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5961_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5961_17af_200c = + {0x17af, 0x200c, pci_subsys_1002_5961_17af_200c, 0}; +#undef pci_ss_info_17af_200c +#define pci_ss_info_17af_200c pci_ss_info_1002_5961_17af_200c +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5961_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5961_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0051 = + {0x18bc, 0x0051, pci_subsys_1002_5961_18bc_0051, 0}; +#undef pci_ss_info_18bc_0051 +#define pci_ss_info_18bc_0051 pci_ss_info_1002_5961_18bc_0051 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0053 = + {0x18bc, 0x0053, pci_subsys_1002_5961_18bc_0053, 0}; +#undef pci_ss_info_18bc_0053 +#define pci_ss_info_18bc_0053 pci_ss_info_1002_5961_18bc_0053 +static const pciSubsystemInfo pci_ss_info_1002_5964_1043_c006 = + {0x1043, 0xc006, pci_subsys_1002_5964_1043_c006, 0}; +#undef pci_ss_info_1043_c006 +#define pci_ss_info_1043_c006 pci_ss_info_1002_5964_1043_c006 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5964_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5964_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5964_147b_6191 = + {0x147b, 0x6191, pci_subsys_1002_5964_147b_6191, 0}; +#undef pci_ss_info_147b_6191 +#define pci_ss_info_147b_6191 pci_ss_info_1002_5964_147b_6191 +static const pciSubsystemInfo pci_ss_info_1002_5964_148c_2073 = + {0x148c, 0x2073, pci_subsys_1002_5964_148c_2073, 0}; +#undef pci_ss_info_148c_2073 +#define pci_ss_info_148c_2073 pci_ss_info_1002_5964_148c_2073 +static const pciSubsystemInfo pci_ss_info_1002_5964_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5964_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5964_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5964_1787_5964 = + {0x1787, 0x5964, pci_subsys_1002_5964_1787_5964, 0}; +#undef pci_ss_info_1787_5964 +#define pci_ss_info_1787_5964 pci_ss_info_1002_5964_1787_5964 +static const pciSubsystemInfo pci_ss_info_1002_5964_17af_2012 = + {0x17af, 0x2012, pci_subsys_1002_5964_17af_2012, 0}; +#undef pci_ss_info_17af_2012 +#define pci_ss_info_17af_2012 pci_ss_info_1002_5964_17af_2012 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0170 = + {0x18bc, 0x0170, pci_subsys_1002_5964_18bc_0170, 0}; +#undef pci_ss_info_18bc_0170 +#define pci_ss_info_18bc_0170 pci_ss_info_1002_5964_18bc_0170 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0173 = + {0x18bc, 0x0173, pci_subsys_1002_5964_18bc_0173, 0}; +#undef pci_ss_info_18bc_0173 +#define pci_ss_info_18bc_0173 pci_ss_info_1002_5964_18bc_0173 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_002a = + {0x1043, 0x002a, pci_subsys_1002_5b60_1043_002a, 0}; +#undef pci_ss_info_1043_002a +#define pci_ss_info_1043_002a pci_ss_info_1002_5b60_1043_002a +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_032e = + {0x1043, 0x032e, pci_subsys_1002_5b60_1043_032e, 0}; +#undef pci_ss_info_1043_032e +#define pci_ss_info_1043_032e pci_ss_info_1002_5b60_1043_032e +static const pciSubsystemInfo pci_ss_info_1002_5b60_1462_0402 = + {0x1462, 0x0402, pci_subsys_1002_5b60_1462_0402, 0}; +#undef pci_ss_info_1462_0402 +#define pci_ss_info_1462_0402 pci_ss_info_1002_5b60_1462_0402 +static const pciSubsystemInfo pci_ss_info_1002_5b70_1462_0403 = + {0x1462, 0x0403, pci_subsys_1002_5b70_1462_0403, 0}; +#undef pci_ss_info_1462_0403 +#define pci_ss_info_1462_0403 pci_ss_info_1002_5b70_1462_0403 +static const pciSubsystemInfo pci_ss_info_1002_5c63_1002_5c63 = + {0x1002, 0x5c63, pci_subsys_1002_5c63_1002_5c63, 0}; +#undef pci_ss_info_1002_5c63 +#define pci_ss_info_1002_5c63 pci_ss_info_1002_5c63_1002_5c63 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5d44_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5d44_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5d44_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5d44_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5d44_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1787_5965 = + {0x1787, 0x5965, pci_subsys_1002_5d44_1787_5965, 0}; +#undef pci_ss_info_1787_5965 +#define pci_ss_info_1787_5965 pci_ss_info_1002_5d44_1787_5965 +static const pciSubsystemInfo pci_ss_info_1002_5d44_17af_2013 = + {0x17af, 0x2013, pci_subsys_1002_5d44_17af_2013, 0}; +#undef pci_ss_info_17af_2013 +#define pci_ss_info_17af_2013 pci_ss_info_1002_5d44_17af_2013 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0171 = + {0x18bc, 0x0171, pci_subsys_1002_5d44_18bc_0171, 0}; +#undef pci_ss_info_18bc_0171 +#define pci_ss_info_18bc_0171 pci_ss_info_1002_5d44_18bc_0171 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0172 = + {0x18bc, 0x0172, pci_subsys_1002_5d44_18bc_0172, 0}; +#undef pci_ss_info_18bc_0172 +#define pci_ss_info_18bc_0172 pci_ss_info_1002_5d44_18bc_0172 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b12 = + {0x1002, 0x0b12, pci_subsys_1002_5d52_1002_0b12, 0}; +#undef pci_ss_info_1002_0b12 +#define pci_ss_info_1002_0b12 pci_ss_info_1002_5d52_1002_0b12 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b13 = + {0x1002, 0x0b13, pci_subsys_1002_5d52_1002_0b13, 0}; +#undef pci_ss_info_1002_0b13 +#define pci_ss_info_1002_0b13 pci_ss_info_1002_5d52_1002_0b13 +static const pciSubsystemInfo pci_ss_info_1002_5e4d_148c_2116 = + {0x148c, 0x2116, pci_subsys_1002_5e4d_148c_2116, 0}; +#undef pci_ss_info_148c_2116 +#define pci_ss_info_148c_2116 pci_ss_info_1002_5e4d_148c_2116 +static const pciSubsystemInfo pci_ss_info_1002_5e6d_148c_2117 = + {0x148c, 0x2117, pci_subsys_1002_5e6d_148c_2117, 0}; +#undef pci_ss_info_148c_2117 +#define pci_ss_info_148c_2117 pci_ss_info_1002_5e6d_148c_2117 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7109_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7109_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0d02 = + {0x1002, 0x0d02, pci_subsys_1002_7109_1002_0d02, 0}; +#undef pci_ss_info_1002_0d02 +#define pci_ss_info_1002_0d02 pci_ss_info_1002_7109_1002_0d02 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7129_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7129_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0d03 = + {0x1002, 0x0d03, pci_subsys_1002_7129_1002_0d03, 0}; +#undef pci_ss_info_1002_0d03 +#define pci_ss_info_1002_0d03 pci_ss_info_1002_7129_1002_0d03 +static const pciSubsystemInfo pci_ss_info_1002_7142_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7142_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7142_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7146_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7146_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7146_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7162_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7162_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7162_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7166_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7166_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7166_1002_0323 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_100b_0020_103c_0024 = + {0x103c, 0x0024, pci_subsys_100b_0020_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_100b_0020_103c_0024 +static const pciSubsystemInfo pci_ss_info_100b_0020_12d9_000c = + {0x12d9, 0x000c, pci_subsys_100b_0020_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_100b_0020_12d9_000c +static const pciSubsystemInfo pci_ss_info_100b_0020_1385_f311 = + {0x1385, 0xf311, pci_subsys_100b_0020_1385_f311, 0}; +#undef pci_ss_info_1385_f311 +#define pci_ss_info_1385_f311 pci_ss_info_100b_0020_1385_f311 +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0019_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0019_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_14cb_0100 = + {0x14cb, 0x0100, pci_subsys_1011_0019_14cb_0100, 0}; +#undef pci_ss_info_14cb_0100 +#define pci_ss_info_14cb_0100 pci_ss_info_1011_0019_14cb_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1011_0046_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1011_0046_4c53_1050 +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_1011_0046_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_1011_0046_4c53_1051 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0364 = + {0x9005, 0x0364, pci_subsys_1011_0046_9005_0364, 0}; +#undef pci_ss_info_9005_0364 +#define pci_ss_info_9005_0364 pci_ss_info_1011_0046_9005_0364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_1136 = + {0x153b, 0x1136, pci_subsys_1013_6003_153b_1136, 0}; +#undef pci_ss_info_153b_1136 +#define pci_ss_info_153b_1136 pci_ss_info_1013_6003_153b_1136 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_0031_1014_0031 = + {0x1014, 0x0031, pci_subsys_1014_0031_1014_0031, 0}; +#undef pci_ss_info_1014_0031 +#define pci_ss_info_1014_0031 pci_ss_info_1014_0031_1014_0031 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +#endif +static const pciSubsystemInfo pci_ss_info_1014_00b7_1092_00b8 = + {0x1092, 0x00b8, pci_subsys_1014_00b7_1092_00b8, 0}; +#undef pci_ss_info_1092_00b8 +#define pci_ss_info_1092_00b8 pci_ss_info_1014_00b7_1092_00b8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0241 = + {0x1014, 0x0241, pci_subsys_1014_0180_1014_0241, 0}; +#undef pci_ss_info_1014_0241 +#define pci_ss_info_1014_0241 pci_ss_info_1014_0180_1014_0241 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0264 = + {0x1014, 0x0264, pci_subsys_1014_0180_1014_0264, 0}; +#undef pci_ss_info_1014_0264 +#define pci_ss_info_1014_0264 pci_ss_info_1014_0180_1014_0264 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_021a = + {0x1014, 0x021a, pci_subsys_1014_0219_1014_021a, 0}; +#undef pci_ss_info_1014_021a +#define pci_ss_info_1014_021a pci_ss_info_1014_0219_1014_021a +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0251 = + {0x1014, 0x0251, pci_subsys_1014_0219_1014_0251, 0}; +#undef pci_ss_info_1014_0251 +#define pci_ss_info_1014_0251 pci_ss_info_1014_0219_1014_0251 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0252 = + {0x1014, 0x0252, pci_subsys_1014_0219_1014_0252, 0}; +#undef pci_ss_info_1014_0252 +#define pci_ss_info_1014_0252 pci_ss_info_1014_0219_1014_0252 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_028d = + {0x1014, 0x028d, pci_subsys_1014_028c_1014_028d, 0}; +#undef pci_ss_info_1014_028d +#define pci_ss_info_1014_028d pci_ss_info_1014_028c_1014_028d +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02be = + {0x1014, 0x02be, pci_subsys_1014_028c_1014_02be, 0}; +#undef pci_ss_info_1014_02be +#define pci_ss_info_1014_02be pci_ss_info_1014_028c_1014_02be +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02c0 = + {0x1014, 0x02c0, pci_subsys_1014_028c_1014_02c0, 0}; +#undef pci_ss_info_1014_02c0 +#define pci_ss_info_1014_02c0 pci_ss_info_1014_028c_1014_02c0 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_030d = + {0x1014, 0x030d, pci_subsys_1014_028c_1014_030d, 0}; +#undef pci_ss_info_1014_030d +#define pci_ss_info_1014_030d pci_ss_info_1014_028c_1014_030d +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_1014_02bd_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_1014_02bd_1014_02c1 +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_1014_02bd_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_1014_02bd_1014_02c2 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0477 = + {0x101e, 0x0477, pci_subsys_101e_1960_101e_0477, 0}; +#undef pci_ss_info_101e_0477 +#define pci_ss_info_101e_0477 pci_ss_info_101e_1960_101e_0477 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0494 = + {0x101e, 0x0494, pci_subsys_101e_1960_101e_0494, 0}; +#undef pci_ss_info_101e_0494 +#define pci_ss_info_101e_0494 pci_ss_info_101e_1960_101e_0494 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0503 = + {0x101e, 0x0503, pci_subsys_101e_1960_101e_0503, 0}; +#undef pci_ss_info_101e_0503 +#define pci_ss_info_101e_0503 pci_ss_info_101e_1960_101e_0503 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0511 = + {0x101e, 0x0511, pci_subsys_101e_1960_101e_0511, 0}; +#undef pci_ss_info_101e_0511 +#define pci_ss_info_101e_0511 pci_ss_info_101e_1960_101e_0511 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0522 = + {0x101e, 0x0522, pci_subsys_101e_1960_101e_0522, 0}; +#undef pci_ss_info_101e_0522 +#define pci_ss_info_101e_0522 pci_ss_info_101e_1960_101e_0522 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_103c_60e7 = + {0x103c, 0x60e7, pci_subsys_101e_1960_103c_60e7, 0}; +#undef pci_ss_info_103c_60e7 +#define pci_ss_info_103c_60e7 pci_ss_info_101e_1960_103c_60e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_1022_2000 = + {0x1022, 0x2000, pci_subsys_1022_2000_1022_2000, 0}; +#undef pci_ss_info_1022_2000 +#define pci_ss_info_1022_2000 pci_ss_info_1022_2000_1022_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2702 = + {0x1259, 0x2702, pci_subsys_1022_2000_1259_2702, 0}; +#undef pci_ss_info_1259_2702 +#define pci_ss_info_1259_2702 pci_ss_info_1022_2000_1259_2702 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2703 = + {0x1259, 0x2703, pci_subsys_1022_2000_1259_2703, 0}; +#undef pci_ss_info_1259_2703 +#define pci_ss_info_1259_2703 pci_ss_info_1022_2000_1259_2703 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1022_2000_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1022_2000_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_1022_2000_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_1022_2000_4c53_1010 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_1022_2000_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_1022_2000_4c53_1020 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_1022_2000_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_1022_2000_4c53_1030 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_1022_2000_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_1022_2000_4c53_1040 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_1022_2000_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_1022_2000_4c53_1060 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7460_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7460_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7460_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7464_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7464_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7464_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7468_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7468_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7468_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7469_1022_2b80 = + {0x1022, 0x2b80, pci_subsys_1022_7469_1022_2b80, 0}; +#undef pci_ss_info_1022_2b80 +#define pci_ss_info_1022_2b80 pci_ss_info_1022_7469_1022_2b80 +static const pciSubsystemInfo pci_ss_info_1022_7469_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7469_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7469_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746b_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746b_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746b_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746d_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746d_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746d_161f_3017 +static const pciSubsystemInfo pci_ss_info_1023_2001_122d_1400 = + {0x122d, 0x1400, pci_subsys_1023_2001_122d_1400, 0}; +#undef pci_ss_info_122d_1400 +#define pci_ss_info_122d_1400 pci_ss_info_1023_2001_122d_1400 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_1025 = + {0x1014, 0x1025, pci_subsys_1023_8620_1014_1025, 0}; +#undef pci_ss_info_1014_1025 +#define pci_ss_info_1014_1025 pci_ss_info_1023_8620_1014_1025 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016c = + {0x1028, 0x016c, pci_subsys_1028_0013_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1028_0013_1028_016c +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016d = + {0x1028, 0x016d, pci_subsys_1028_0013_1028_016d, 0}; +#undef pci_ss_info_1028_016d +#define pci_ss_info_1028_016d pci_ss_info_1028_0013_1028_016d +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016e = + {0x1028, 0x016e, pci_subsys_1028_0013_1028_016e, 0}; +#undef pci_ss_info_1028_016e +#define pci_ss_info_1028_016e pci_ss_info_1028_0013_1028_016e +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016f = + {0x1028, 0x016f, pci_subsys_1028_0013_1028_016f, 0}; +#undef pci_ss_info_1028_016f +#define pci_ss_info_1028_016f pci_ss_info_1028_0013_1028_016f +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_0170 = + {0x1028, 0x0170, pci_subsys_1028_0013_1028_0170, 0}; +#undef pci_ss_info_1028_0170 +#define pci_ss_info_1028_0170 pci_ss_info_1028_0013_1028_0170 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_102a_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_102a_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_0106 = + {0x9005, 0x0106, pci_subsys_102a_001f_9005_0106, 0}; +#undef pci_ss_info_9005_0106 +#define pci_ss_info_9005_0106 pci_ss_info_102a_001f_9005_0106 +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_102a_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_102a_001f_9005_a180 +#endif +static const pciSubsystemInfo pci_ss_info_102a_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_102a_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_102a_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0106 = + {0x1028, 0x0106, pci_subsys_102a_00cf_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_102a_00cf_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0121 = + {0x1028, 0x0121, pci_subsys_102a_00cf_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_102a_00cf_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d43 = + {0x102b, 0x0d43, pci_subsys_102b_0525_102b_0d43, 0}; +#undef pci_ss_info_102b_0d43 +#define pci_ss_info_102b_0d43 pci_ss_info_102b_0525_102b_0d43 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0850 = + {0x102b, 0x0850, pci_subsys_102b_0527_102b_0850, 0}; +#undef pci_ss_info_102b_0850 +#define pci_ss_info_102b_0850 pci_ss_info_102b_0527_102b_0850 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1020 = + {0x102b, 0x1020, pci_subsys_102b_0528_102b_1020, 0}; +#undef pci_ss_info_102b_1020 +#define pci_ss_info_102b_1020 pci_ss_info_102b_0528_102b_1020 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1030 = + {0x102b, 0x1030, pci_subsys_102b_0528_102b_1030, 0}; +#undef pci_ss_info_102b_1030 +#define pci_ss_info_102b_1030 pci_ss_info_102b_0528_102b_1030 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_14e1 = + {0x102b, 0x14e1, pci_subsys_102b_0528_102b_14e1, 0}; +#undef pci_ss_info_102b_14e1 +#define pci_ss_info_102b_14e1 pci_ss_info_102b_0528_102b_14e1 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_2021 = + {0x102b, 0x2021, pci_subsys_102b_0528_102b_2021, 0}; +#undef pci_ss_info_102b_2021 +#define pci_ss_info_102b_2021 pci_ss_info_102b_0528_102b_2021 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1820 = + {0x102b, 0x1820, pci_subsys_102b_2537_102b_1820, 0}; +#undef pci_ss_info_102b_1820 +#define pci_ss_info_102b_1820 pci_ss_info_102b_2537_102b_1820 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1830 = + {0x102b, 0x1830, pci_subsys_102b_2537_102b_1830, 0}; +#undef pci_ss_info_102b_1830 +#define pci_ss_info_102b_1830 pci_ss_info_102b_2537_102b_1830 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1c10 = + {0x102b, 0x1c10, pci_subsys_102b_2537_102b_1c10, 0}; +#undef pci_ss_info_102b_1c10 +#define pci_ss_info_102b_1c10 pci_ss_info_102b_2537_102b_1c10 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2811 = + {0x102b, 0x2811, pci_subsys_102b_2537_102b_2811, 0}; +#undef pci_ss_info_102b_2811 +#define pci_ss_info_102b_2811 pci_ss_info_102b_2537_102b_2811 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2c11 = + {0x102b, 0x2c11, pci_subsys_102b_2537_102b_2c11, 0}; +#undef pci_ss_info_102b_2c11 +#define pci_ss_info_102b_2c11 pci_ss_info_102b_2537_102b_2c11 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_08c7 = + {0x102b, 0x08c7, pci_subsys_102b_2538_102b_08c7, 0}; +#undef pci_ss_info_102b_08c7 +#define pci_ss_info_102b_08c7 pci_ss_info_102b_2538_102b_08c7 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_0907 = + {0x102b, 0x0907, pci_subsys_102b_2538_102b_0907, 0}; +#undef pci_ss_info_102b_0907 +#define pci_ss_info_102b_0907 pci_ss_info_102b_2538_102b_0907 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1047 = + {0x102b, 0x1047, pci_subsys_102b_2538_102b_1047, 0}; +#undef pci_ss_info_102b_1047 +#define pci_ss_info_102b_1047 pci_ss_info_102b_2538_102b_1047 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1087 = + {0x102b, 0x1087, pci_subsys_102b_2538_102b_1087, 0}; +#undef pci_ss_info_102b_1087 +#define pci_ss_info_102b_1087 pci_ss_info_102b_2538_102b_1087 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_2538 = + {0x102b, 0x2538, pci_subsys_102b_2538_102b_2538, 0}; +#undef pci_ss_info_102b_2538 +#define pci_ss_info_102b_2538 pci_ss_info_102b_2538_102b_2538 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_3007 = + {0x102b, 0x3007, pci_subsys_102b_2538_102b_3007, 0}; +#undef pci_ss_info_102b_3007 +#define pci_ss_info_102b_3007 pci_ss_info_102b_2538_102b_3007 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_00c0_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_00c0_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_102c_00c0_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_102c_00c0_4c53_1010 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_102c_00c0_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_102c_00c0_4c53_1020 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_102c_00c0_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_102c_00c0_4c53_1030 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_00c0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_00c0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_00c0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_00c0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +static const pciSubsystemInfo pci_ss_info_102c_00e5_1179_0001 = + {0x1179, 0x0001, pci_subsys_102c_00e5_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_102c_00e5_1179_0001 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_0c30_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_0c30_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_0c30_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_0c30_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_0c30_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_0c30_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_102c_0c30_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_102c_0c30_4c53_1080 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1033_0035 = + {0x1033, 0x0035, pci_subsys_1033_0035_1033_0035, 0}; +#undef pci_ss_info_1033_0035 +#define pci_ss_info_1033_0035 pci_ss_info_1033_0035_1033_0035 +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_14c2_0105 = + {0x14c2, 0x0105, pci_subsys_1033_0035_14c2_0105, 0}; +#undef pci_ss_info_14c2_0105 +#define pci_ss_info_14c2_0105 pci_ss_info_1033_0035_14c2_0105 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000a = + {0x1931, 0x000a, pci_subsys_1033_0035_1931_000a, 0}; +#undef pci_ss_info_1931_000a +#define pci_ss_info_1931_000a pci_ss_info_1033_0035_1931_000a +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000b = + {0x1931, 0x000b, pci_subsys_1033_0035_1931_000b, 0}; +#undef pci_ss_info_1931_000b +#define pci_ss_info_1931_000b pci_ss_info_1033_0035_1931_000b +static const pciSubsystemInfo pci_ss_info_1033_0035_807d_0035 = + {0x807d, 0x0035, pci_subsys_1033_0035_807d_0035, 0}; +#undef pci_ss_info_807d_0035 +#define pci_ss_info_807d_0035 pci_ss_info_1033_0035_807d_0035 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_14c2_0205 = + {0x14c2, 0x0205, pci_subsys_1033_00e0_14c2_0205, 0}; +#undef pci_ss_info_14c2_0205 +#define pci_ss_info_14c2_0205 pci_ss_info_1033_00e0_14c2_0205 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1033_00e0_807d_1043 = + {0x807d, 0x1043, pci_subsys_1033_00e0_807d_1043, 0}; +#undef pci_ss_info_807d_1043 +#define pci_ss_info_807d_1043 pci_ss_info_1033_00e0_807d_1043 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_0900_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_0900_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_0900_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_0900_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_0900_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_5513_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_5513_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_5513_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6300_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_6300_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_6300_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_6330_1039_6330 = + {0x1039, 0x6330, pci_subsys_1039_6330_1039_6330, 0}; +#undef pci_ss_info_1039_6330 +#define pci_ss_info_1039_6330 pci_ss_info_1039_6330_1039_6330 +static const pciSubsystemInfo pci_ss_info_1039_7001_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_7001_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_7001_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7001_1462_5470 = + {0x1462, 0x5470, pci_subsys_1039_7001_1462_5470, 0}; +#undef pci_ss_info_1462_5470 +#define pci_ss_info_1462_5470 pci_ss_info_1039_7001_1462_5470 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7012_15bd_1001 = + {0x15bd, 0x1001, pci_subsys_1039_7012_15bd_1001, 0}; +#undef pci_ss_info_15bd_1001 +#define pci_ss_info_15bd_1001 pci_ss_info_1039_7012_15bd_1001 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1301 = + {0x103c, 0x1301, pci_subsys_103c_1048_103c_1301, 0}; +#undef pci_ss_info_103c_1301 +#define pci_ss_info_103c_1301 pci_ss_info_103c_1048_103c_1301 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1704 = + {0x0675, 0x1704, pci_subsys_1043_0675_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1043_0675_0675_1704 +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1707 = + {0x0675, 0x1707, pci_subsys_1043_0675_0675_1707, 0}; +#undef pci_ss_info_0675_1707 +#define pci_ss_info_0675_1707 pci_ss_info_1043_0675_0675_1707 +static const pciSubsystemInfo pci_ss_info_1043_0675_10cf_105e = + {0x10cf, 0x105e, pci_subsys_1043_0675_10cf_105e, 0}; +#undef pci_ss_info_10cf_105e +#define pci_ss_info_10cf_105e pci_ss_info_1043_0675_10cf_105e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c032 = + {0x1044, 0xc032, pci_subsys_1044_a511_1044_c032, 0}; +#undef pci_ss_info_1044_c032 +#define pci_ss_info_1044_c032 pci_ss_info_1044_a511_1044_c032 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c035 = + {0x1044, 0xc035, pci_subsys_1044_a511_1044_c035, 0}; +#undef pci_ss_info_1044_c035 +#define pci_ss_info_1044_c035 pci_ss_info_1044_a511_1044_c035 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1048_8901_1048_0935 = + {0x1048, 0x0935, pci_subsys_1048_8901_1048_0935, 0}; +#undef pci_ss_info_1048_0935 +#define pci_ss_info_1048_0935 pci_ss_info_1048_8901_1048_0935 +#endif +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a34 = + {0x1048, 0x0a34, pci_subsys_104c_3d07_1048_0a34, 0}; +#undef pci_ss_info_1048_0a34 +#define pci_ss_info_1048_0a34 pci_ss_info_104c_3d07_1048_0a34 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a36 = + {0x1048, 0x0a36, pci_subsys_104c_3d07_1048_0a36, 0}; +#undef pci_ss_info_1048_0a36 +#define pci_ss_info_1048_0a36 pci_ss_info_104c_3d07_1048_0a36 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a43 = + {0x1048, 0x0a43, pci_subsys_104c_3d07_1048_0a43, 0}; +#undef pci_ss_info_1048_0a43 +#define pci_ss_info_1048_0a43 pci_ss_info_104c_3d07_1048_0a43 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a44 = + {0x1048, 0x0a44, pci_subsys_104c_3d07_1048_0a44, 0}; +#undef pci_ss_info_1048_0a44 +#define pci_ss_info_1048_0a44 pci_ss_info_104c_3d07_1048_0a44 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_000f = + {0x11bd, 0x000f, pci_subsys_104c_8020_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_104c_8020_11bd_000f +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8023_103c_088c = + {0x103c, 0x088c, pci_subsys_104c_8023_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_104c_8023_103c_088c +static const pciSubsystemInfo pci_ss_info_104c_8023_1043_808b = + {0x1043, 0x808b, pci_subsys_104c_8023_1043_808b, 0}; +#undef pci_ss_info_1043_808b +#define pci_ss_info_1043_808b pci_ss_info_104c_8023_1043_808b +static const pciSubsystemInfo pci_ss_info_104c_8025_1458_1000 = + {0x1458, 0x1000, pci_subsys_104c_8025_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_104c_8025_1458_1000 +static const pciSubsystemInfo pci_ss_info_104c_8026_103c_006a = + {0x103c, 0x006a, pci_subsys_104c_8026_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_104c_8026_103c_006a +static const pciSubsystemInfo pci_ss_info_104c_8026_1043_808d = + {0x1043, 0x808d, pci_subsys_104c_8026_1043_808d, 0}; +#undef pci_ss_info_1043_808d +#define pci_ss_info_1043_808d pci_ss_info_104c_8026_1043_808d +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_8029_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_8029_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_8029_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_8029_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_8029_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_8029_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_8029_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_802b_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_802b_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_802b_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_802b_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8031_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8031_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8031_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8031_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8032_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8032_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8032_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8032_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8033_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8033_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8033_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8033_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8034_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8034_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8034_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8034_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8035_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8035_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8035_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_8204_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_8204_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_8204_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_8204_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b00 = + {0x1186, 0x3b00, pci_subsys_104c_8400_1186_3b00, 0}; +#undef pci_ss_info_1186_3b00 +#define pci_ss_info_1186_3b00 pci_ss_info_104c_8400_1186_3b00 +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b01 = + {0x1186, 0x3b01, pci_subsys_104c_8400_1186_3b01, 0}; +#undef pci_ss_info_1186_3b01 +#define pci_ss_info_1186_3b01 pci_ss_info_104c_8400_1186_3b01 +static const pciSubsystemInfo pci_ss_info_104c_8400_16ab_8501 = + {0x16ab, 0x8501, pci_subsys_104c_8400_16ab_8501, 0}; +#undef pci_ss_info_16ab_8501 +#define pci_ss_info_16ab_8501 pci_ss_info_104c_8400_16ab_8501 +static const pciSubsystemInfo pci_ss_info_104c_9066_104c_9066 = + {0x104c, 0x9066, pci_subsys_104c_9066_104c_9066, 0}; +#undef pci_ss_info_104c_9066 +#define pci_ss_info_104c_9066 pci_ss_info_104c_9066_104c_9066 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b04 = + {0x1186, 0x3b04, pci_subsys_104c_9066_1186_3b04, 0}; +#undef pci_ss_info_1186_3b04 +#define pci_ss_info_1186_3b04 pci_ss_info_104c_9066_1186_3b04 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b05 = + {0x1186, 0x3b05, pci_subsys_104c_9066_1186_3b05, 0}; +#undef pci_ss_info_1186_3b05 +#define pci_ss_info_1186_3b05 pci_ss_info_104c_9066_1186_3b05 +static const pciSubsystemInfo pci_ss_info_104c_9066_13d1_aba0 = + {0x13d1, 0xaba0, pci_subsys_104c_9066_13d1_aba0, 0}; +#undef pci_ss_info_13d1_aba0 +#define pci_ss_info_13d1_aba0 pci_ss_info_104c_9066_13d1_aba0 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_5000 = + {0x175c, 0x5000, pci_subsys_104c_a106_175c_5000, 0}; +#undef pci_ss_info_175c_5000 +#define pci_ss_info_175c_5000 pci_ss_info_104c_a106_175c_5000 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_6400 = + {0x175c, 0x6400, pci_subsys_104c_a106_175c_6400, 0}; +#undef pci_ss_info_175c_6400 +#define pci_ss_info_175c_6400 pci_ss_info_104c_a106_175c_6400 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_8700 = + {0x175c, 0x8700, pci_subsys_104c_a106_175c_8700, 0}; +#undef pci_ss_info_175c_8700 +#define pci_ss_info_175c_8700 pci_ss_info_104c_a106_175c_8700 +static const pciSubsystemInfo pci_ss_info_104c_ac16_1014_0092 = + {0x1014, 0x0092, pci_subsys_104c_ac16_1014_0092, 0}; +#undef pci_ss_info_1014_0092 +#define pci_ss_info_1014_0092 pci_ss_info_104c_ac16_1014_0092 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_1014_0130 = + {0x1014, 0x0130, pci_subsys_104c_ac1b_1014_0130, 0}; +#undef pci_ss_info_1014_0130 +#define pci_ss_info_1014_0130 pci_ss_info_104c_ac1b_1014_0130 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_0e11_b121 = + {0x0e11, 0xb121, pci_subsys_104c_ac1c_0e11_b121, 0}; +#undef pci_ss_info_0e11_b121 +#define pci_ss_info_0e11_b121 pci_ss_info_104c_ac1c_0e11_b121 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_1028_0088 = + {0x1028, 0x0088, pci_subsys_104c_ac1c_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_104c_ac1c_1028_0088 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_ac44_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_ac44_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_ac44_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_ac44_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_ac44_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_ac44_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac47_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac47_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac47_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac47_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac4a_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac4a_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac4a_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac4a_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac51_0e11_004e = + {0x0e11, 0x004e, pci_subsys_104c_ac51_0e11_004e, 0}; +#undef pci_ss_info_0e11_004e +#define pci_ss_info_0e11_004e pci_ss_info_104c_ac51_0e11_004e +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_104c_ac51_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_104c_ac51_1028_00b1 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_012a = + {0x1028, 0x012a, pci_subsys_104c_ac51_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_104c_ac51_1028_012a +static const pciSubsystemInfo pci_ss_info_104c_ac51_1033_80cd = + {0x1033, 0x80cd, pci_subsys_104c_ac51_1033_80cd, 0}; +#undef pci_ss_info_1033_80cd +#define pci_ss_info_1033_80cd pci_ss_info_104c_ac51_1033_80cd +static const pciSubsystemInfo pci_ss_info_104c_ac51_1095_10cf = + {0x1095, 0x10cf, pci_subsys_104c_ac51_1095_10cf, 0}; +#undef pci_ss_info_1095_10cf +#define pci_ss_info_1095_10cf pci_ss_info_104c_ac51_1095_10cf +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0528 = + {0x1014, 0x0528, pci_subsys_104c_ac56_1014_0528, 0}; +#undef pci_ss_info_1014_0528 +#define pci_ss_info_1014_0528 pci_ss_info_104c_ac56_1014_0528 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_5100 = + {0x175c, 0x5100, pci_subsys_104c_ac60_175c_5100, 0}; +#undef pci_ss_info_175c_5100 +#define pci_ss_info_175c_5100 pci_ss_info_104c_ac60_175c_5100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6100 = + {0x175c, 0x6100, pci_subsys_104c_ac60_175c_6100, 0}; +#undef pci_ss_info_175c_6100 +#define pci_ss_info_175c_6100 pci_ss_info_104c_ac60_175c_6100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6200 = + {0x175c, 0x6200, pci_subsys_104c_ac60_175c_6200, 0}; +#undef pci_ss_info_175c_6200 +#define pci_ss_info_175c_6200 pci_ss_info_104c_ac60_175c_6200 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_8800 = + {0x175c, 0x8800, pci_subsys_104c_ac60_175c_8800, 0}; +#undef pci_ss_info_175c_8800 +#define pci_ss_info_175c_8800 pci_ss_info_104c_ac60_175c_8800 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1702 = + {0x1043, 0x1702, pci_subsys_1050_6692_1043_1702, 0}; +#undef pci_ss_info_1043_1702 +#define pci_ss_info_1043_1702 pci_ss_info_1050_6692_1043_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1703 = + {0x1043, 0x1703, pci_subsys_1050_6692_1043_1703, 0}; +#undef pci_ss_info_1043_1703 +#define pci_ss_info_1043_1703 pci_ss_info_1050_6692_1043_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1707 = + {0x1043, 0x1707, pci_subsys_1050_6692_1043_1707, 0}; +#undef pci_ss_info_1043_1707 +#define pci_ss_info_1043_1707 pci_ss_info_1050_6692_1043_1707 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1702 = + {0x144f, 0x1702, pci_subsys_1050_6692_144f_1702, 0}; +#undef pci_ss_info_144f_1702 +#define pci_ss_info_144f_1702 pci_ss_info_1050_6692_144f_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1703 = + {0x144f, 0x1703, pci_subsys_1050_6692_144f_1703, 0}; +#undef pci_ss_info_144f_1703 +#define pci_ss_info_144f_1703 pci_ss_info_1050_6692_144f_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1707 = + {0x144f, 0x1707, pci_subsys_1050_6692_144f_1707, 0}; +#undef pci_ss_info_144f_1707 +#define pci_ss_info_144f_1707 pci_ss_info_1050_6692_144f_1707 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0101 = + {0x14fb, 0x0101, pci_subsys_1057_1801_14fb_0101, 0}; +#undef pci_ss_info_14fb_0101 +#define pci_ss_info_14fb_0101 pci_ss_info_1057_1801_14fb_0101 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0102 = + {0x14fb, 0x0102, pci_subsys_1057_1801_14fb_0102, 0}; +#undef pci_ss_info_14fb_0102 +#define pci_ss_info_14fb_0102 pci_ss_info_1057_1801_14fb_0102 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0202 = + {0x14fb, 0x0202, pci_subsys_1057_1801_14fb_0202, 0}; +#undef pci_ss_info_14fb_0202 +#define pci_ss_info_14fb_0202 pci_ss_info_1057_1801_14fb_0202 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0611 = + {0x14fb, 0x0611, pci_subsys_1057_1801_14fb_0611, 0}; +#undef pci_ss_info_14fb_0611 +#define pci_ss_info_14fb_0611 pci_ss_info_1057_1801_14fb_0611 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0612 = + {0x14fb, 0x0612, pci_subsys_1057_1801_14fb_0612, 0}; +#undef pci_ss_info_14fb_0612 +#define pci_ss_info_14fb_0612 pci_ss_info_1057_1801_14fb_0612 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0613 = + {0x14fb, 0x0613, pci_subsys_1057_1801_14fb_0613, 0}; +#undef pci_ss_info_14fb_0613 +#define pci_ss_info_14fb_0613 pci_ss_info_1057_1801_14fb_0613 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0614 = + {0x14fb, 0x0614, pci_subsys_1057_1801_14fb_0614, 0}; +#undef pci_ss_info_14fb_0614 +#define pci_ss_info_14fb_0614 pci_ss_info_1057_1801_14fb_0614 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0621 = + {0x14fb, 0x0621, pci_subsys_1057_1801_14fb_0621, 0}; +#undef pci_ss_info_14fb_0621 +#define pci_ss_info_14fb_0621 pci_ss_info_1057_1801_14fb_0621 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0622 = + {0x14fb, 0x0622, pci_subsys_1057_1801_14fb_0622, 0}; +#undef pci_ss_info_14fb_0622 +#define pci_ss_info_14fb_0622 pci_ss_info_1057_1801_14fb_0622 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0810 = + {0x14fb, 0x0810, pci_subsys_1057_1801_14fb_0810, 0}; +#undef pci_ss_info_14fb_0810 +#define pci_ss_info_14fb_0810 pci_ss_info_1057_1801_14fb_0810 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4200 = + {0x175c, 0x4200, pci_subsys_1057_1801_175c_4200, 0}; +#undef pci_ss_info_175c_4200 +#define pci_ss_info_175c_4200 pci_ss_info_1057_1801_175c_4200 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4300 = + {0x175c, 0x4300, pci_subsys_1057_1801_175c_4300, 0}; +#undef pci_ss_info_175c_4300 +#define pci_ss_info_175c_4300 pci_ss_info_1057_1801_175c_4300 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4400 = + {0x175c, 0x4400, pci_subsys_1057_1801_175c_4400, 0}; +#undef pci_ss_info_175c_4400 +#define pci_ss_info_175c_4400 pci_ss_info_1057_1801_175c_4400 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0010 = + {0xecc0, 0x0010, pci_subsys_1057_1801_ecc0_0010, 0}; +#undef pci_ss_info_ecc0_0010 +#define pci_ss_info_ecc0_0010 pci_ss_info_1057_1801_ecc0_0010 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0020 = + {0xecc0, 0x0020, pci_subsys_1057_1801_ecc0_0020, 0}; +#undef pci_ss_info_ecc0_0020 +#define pci_ss_info_ecc0_0020 pci_ss_info_1057_1801_ecc0_0020 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0031 = + {0xecc0, 0x0031, pci_subsys_1057_1801_ecc0_0031, 0}; +#undef pci_ss_info_ecc0_0031 +#define pci_ss_info_ecc0_0031 pci_ss_info_1057_1801_ecc0_0031 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0040 = + {0xecc0, 0x0040, pci_subsys_1057_1801_ecc0_0040, 0}; +#undef pci_ss_info_ecc0_0040 +#define pci_ss_info_ecc0_0040 pci_ss_info_1057_1801_ecc0_0040 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0041 = + {0xecc0, 0x0041, pci_subsys_1057_1801_ecc0_0041, 0}; +#undef pci_ss_info_ecc0_0041 +#define pci_ss_info_ecc0_0041 pci_ss_info_1057_1801_ecc0_0041 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_1801_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_1801_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_1801_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_1801_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_1801_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_1801_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_1801_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_1801_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_1801_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_1801_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_3410_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_3410_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_3410_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_3410_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0060 = + {0xecc0, 0x0060, pci_subsys_1057_3410_ecc0_0060, 0}; +#undef pci_ss_info_ecc0_0060 +#define pci_ss_info_ecc0_0060 pci_ss_info_1057_3410_ecc0_0060 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_3410_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_3410_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_3410_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_3410_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_3410_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_3410_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0080 = + {0xecc0, 0x0080, pci_subsys_1057_3410_ecc0_0080, 0}; +#undef pci_ss_info_ecc0_0080 +#define pci_ss_info_ecc0_0080 pci_ss_info_1057_3410_ecc0_0080 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0081 = + {0xecc0, 0x0081, pci_subsys_1057_3410_ecc0_0081, 0}; +#undef pci_ss_info_ecc0_0081 +#define pci_ss_info_ecc0_0081 pci_ss_info_1057_3410_ecc0_0081 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0090 = + {0xecc0, 0x0090, pci_subsys_1057_3410_ecc0_0090, 0}; +#undef pci_ss_info_ecc0_0090 +#define pci_ss_info_ecc0_0090 pci_ss_info_1057_3410_ecc0_0090 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00a0 = + {0xecc0, 0x00a0, pci_subsys_1057_3410_ecc0_00a0, 0}; +#undef pci_ss_info_ecc0_00a0 +#define pci_ss_info_ecc0_00a0 pci_ss_info_1057_3410_ecc0_00a0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00b0 = + {0xecc0, 0x00b0, pci_subsys_1057_3410_ecc0_00b0, 0}; +#undef pci_ss_info_ecc0_00b0 +#define pci_ss_info_ecc0_00b0 pci_ss_info_1057_3410_ecc0_00b0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0100 = + {0xecc0, 0x0100, pci_subsys_1057_3410_ecc0_0100, 0}; +#undef pci_ss_info_ecc0_0100 +#define pci_ss_info_ecc0_0100 pci_ss_info_1057_3410_ecc0_0100 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +#endif +static const pciSubsystemInfo pci_ss_info_105a_3319_8086_3427 = + {0x8086, 0x3427, pci_subsys_105a_3319_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_105a_3319_8086_3427 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_3373_1043_80f5 = + {0x1043, 0x80f5, pci_subsys_105a_3373_1043_80f5, 0}; +#undef pci_ss_info_1043_80f5 +#define pci_ss_info_1043_80f5 pci_ss_info_105a_3373_1043_80f5 +static const pciSubsystemInfo pci_ss_info_105a_3373_1462_702e = + {0x1462, 0x702e, pci_subsys_105a_3373_1462_702e, 0}; +#undef pci_ss_info_1462_702e +#define pci_ss_info_1462_702e pci_ss_info_105a_3373_1462_702e +static const pciSubsystemInfo pci_ss_info_105a_3376_1043_809e = + {0x1043, 0x809e, pci_subsys_105a_3376_1043_809e, 0}; +#undef pci_ss_info_1043_809e +#define pci_ss_info_1043_809e pci_ss_info_105a_3376_1043_809e +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_4d69_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d69_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d69_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_1043_807e = + {0x1043, 0x807e, pci_subsys_105a_5275_1043_807e, 0}; +#undef pci_ss_info_1043_807e +#define pci_ss_info_1043_807e pci_ss_info_105a_5275_1043_807e +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_1275 = + {0x105a, 0x1275, pci_subsys_105a_5275_105a_1275, 0}; +#undef pci_ss_info_105a_1275 +#define pci_ss_info_105a_1275 pci_ss_info_105a_5275_105a_1275 +static const pciSubsystemInfo pci_ss_info_105a_5275_1458_b001 = + {0x1458, 0xb001, pci_subsys_105a_5275_1458_b001, 0}; +#undef pci_ss_info_1458_b001 +#define pci_ss_info_1458_b001 pci_ss_info_105a_5275_1458_b001 +static const pciSubsystemInfo pci_ss_info_105a_6268_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_6268_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_6268_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_5348_105d_0037 = + {0x105d, 0x0037, pci_subsys_105d_5348_105d_0037, 0}; +#undef pci_ss_info_105d_0037 +#define pci_ss_info_105d_0037 pci_ss_info_105d_5348_105d_0037 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0050 = + {0x1069, 0x0050, pci_subsys_1069_0050_1069_0050, 0}; +#undef pci_ss_info_1069_0050 +#define pci_ss_info_1069_0050 pci_ss_info_1069_0050_1069_0050 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0052 = + {0x1069, 0x0052, pci_subsys_1069_0050_1069_0052, 0}; +#undef pci_ss_info_1069_0052 +#define pci_ss_info_1069_0052 pci_ss_info_1069_0050_1069_0052 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0054 = + {0x1069, 0x0054, pci_subsys_1069_0050_1069_0054, 0}; +#undef pci_ss_info_1069_0054 +#define pci_ss_info_1069_0054 pci_ss_info_1069_0050_1069_0054 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0242 = + {0x1014, 0x0242, pci_subsys_1069_b166_1014_0242, 0}; +#undef pci_ss_info_1014_0242 +#define pci_ss_info_1014_0242 pci_ss_info_1069_b166_1014_0242 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0266 = + {0x1014, 0x0266, pci_subsys_1069_b166_1014_0266, 0}; +#undef pci_ss_info_1014_0266 +#define pci_ss_info_1014_0266 pci_ss_info_1069_b166_1014_0266 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0278 = + {0x1014, 0x0278, pci_subsys_1069_b166_1014_0278, 0}; +#undef pci_ss_info_1014_0278 +#define pci_ss_info_1014_0278 pci_ss_info_1069_b166_1014_0278 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d3 = + {0x1014, 0x02d3, pci_subsys_1069_b166_1014_02d3, 0}; +#undef pci_ss_info_1014_02d3 +#define pci_ss_info_1014_02d3 pci_ss_info_1069_b166_1014_02d3 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d4 = + {0x1014, 0x02d4, pci_subsys_1069_b166_1014_02d4, 0}; +#undef pci_ss_info_1014_02d4 +#define pci_ss_info_1014_02d4 pci_ss_info_1069_b166_1014_02d4 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0200 = + {0x1069, 0x0200, pci_subsys_1069_b166_1069_0200, 0}; +#undef pci_ss_info_1069_0200 +#define pci_ss_info_1069_0200 pci_ss_info_1069_b166_1069_0200 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0202 = + {0x1069, 0x0202, pci_subsys_1069_b166_1069_0202, 0}; +#undef pci_ss_info_1069_0202 +#define pci_ss_info_1069_0202 pci_ss_info_1069_b166_1069_0202 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0204 = + {0x1069, 0x0204, pci_subsys_1069_b166_1069_0204, 0}; +#undef pci_ss_info_1069_0204 +#define pci_ss_info_1069_0204 pci_ss_info_1069_b166_1069_0204 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0206 = + {0x1069, 0x0206, pci_subsys_1069_b166_1069_0206, 0}; +#undef pci_ss_info_1069_0206 +#define pci_ss_info_1069_0206 pci_ss_info_1069_b166_1069_0206 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0030 = + {0x1069, 0x0030, pci_subsys_1069_ba56_1069_0030, 0}; +#undef pci_ss_info_1069_0030 +#define pci_ss_info_1069_0030 pci_ss_info_1069_ba56_1069_0030 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0040 = + {0x1069, 0x0040, pci_subsys_1069_ba56_1069_0040, 0}; +#undef pci_ss_info_1069_0040 +#define pci_ss_info_1069_0040 pci_ss_info_1069_ba56_1069_0040 +static const pciSubsystemInfo pci_ss_info_1069_ba57_1069_0072 = + {0x1069, 0x0072, pci_subsys_1069_ba57_1069_0072, 0}; +#undef pci_ss_info_1069_0072 +#define pci_ss_info_1069_0072 pci_ss_info_1069_ba57_1069_0072 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_106b_0031_106b_5811 = + {0x106b, 0x5811, pci_subsys_106b_0031_106b_5811, 0}; +#undef pci_ss_info_106b_5811 +#define pci_ss_info_106b_5811 pci_ss_info_106b_0031_106b_5811 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +static const pciSubsystemInfo pci_ss_info_1077_2200_1077_0002 = + {0x1077, 0x0002, pci_subsys_1077_2200_1077_0002, 0}; +#undef pci_ss_info_1077_0002 +#define pci_ss_info_1077_0002 pci_ss_info_1077_2200_1077_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0648_1043_8025 = + {0x1043, 0x8025, pci_subsys_1095_0648_1043_8025, 0}; +#undef pci_ss_info_1043_8025 +#define pci_ss_info_1043_8025 pci_ss_info_1095_0648_1043_8025 +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +static const pciSubsystemInfo pci_ss_info_1095_0680_1095_3680 = + {0x1095, 0x3680, pci_subsys_1095_0680_1095_3680, 0}; +#undef pci_ss_info_1095_3680 +#define pci_ss_info_1095_3680 pci_ss_info_1095_0680_1095_3680 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_3112 = + {0x1095, 0x3112, pci_subsys_1095_3112_1095_3112, 0}; +#undef pci_ss_info_1095_3112 +#define pci_ss_info_1095_3112 pci_ss_info_1095_3112_1095_3112 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_6112 = + {0x1095, 0x6112, pci_subsys_1095_3112_1095_6112, 0}; +#undef pci_ss_info_1095_6112 +#define pci_ss_info_1095_6112 pci_ss_info_1095_3112_1095_6112 +static const pciSubsystemInfo pci_ss_info_1095_3112_9005_0250 = + {0x9005, 0x0250, pci_subsys_1095_3112_9005_0250, 0}; +#undef pci_ss_info_9005_0250 +#define pci_ss_info_9005_0250 pci_ss_info_1095_3112_9005_0250 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_3114 = + {0x1095, 0x3114, pci_subsys_1095_3114_1095_3114, 0}; +#undef pci_ss_info_1095_3114 +#define pci_ss_info_1095_3114 pci_ss_info_1095_3114_1095_3114 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_6114 = + {0x1095, 0x6114, pci_subsys_1095_3114_1095_6114, 0}; +#undef pci_ss_info_1095_6114 +#define pci_ss_info_1095_6114 pci_ss_info_1095_3114_1095_6114 +static const pciSubsystemInfo pci_ss_info_1095_3124_1095_3124 = + {0x1095, 0x3124, pci_subsys_1095_3124_1095_3124, 0}; +#undef pci_ss_info_1095_3124 +#define pci_ss_info_1095_3124 pci_ss_info_1095_3124_1095_3124 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_3512 = + {0x1095, 0x3512, pci_subsys_1095_3512_1095_3512, 0}; +#undef pci_ss_info_1095_3512 +#define pci_ss_info_1095_3512 pci_ss_info_1095_3512_1095_3512 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_6512 = + {0x1095, 0x6512, pci_subsys_1095_3512_1095_6512, 0}; +#undef pci_ss_info_1095_6512 +#define pci_ss_info_1095_6512 pci_ss_info_1095_3512_1095_6512 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_036e_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_036e_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_036e_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_036e_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0003 = + {0x1461, 0x0003, pci_subsys_109e_036e_1461_0003, 0}; +#undef pci_ss_info_1461_0003 +#define pci_ss_info_1461_0003 pci_ss_info_109e_036e_1461_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_036e_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_036e_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_036e_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_036e_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_036e_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_036e_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_036e_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_036e_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_036e_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_0878_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_0878_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_0878_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_0878_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_0878_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_0878_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_0878_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_0878_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_0878_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_0878_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_0878_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_0878_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_0878_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10a9_0009_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_10a9_0009_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_10a9_0009_10a9_8002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_6540_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6540_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6540_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6541_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6541_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6541_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6542_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6542_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6542_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2862 = + {0x10b5, 0x2862, pci_subsys_10b5_9030_10b5_2862, 0}; +#undef pci_ss_info_10b5_2862 +#define pci_ss_info_10b5_2862 pci_ss_info_10b5_9030_10b5_2862 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2906 = + {0x10b5, 0x2906, pci_subsys_10b5_9030_10b5_2906, 0}; +#undef pci_ss_info_10b5_2906 +#define pci_ss_info_10b5_2906 pci_ss_info_10b5_9030_10b5_2906 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2940 = + {0x10b5, 0x2940, pci_subsys_10b5_9030_10b5_2940, 0}; +#undef pci_ss_info_10b5_2940 +#define pci_ss_info_10b5_2940 pci_ss_info_10b5_9030_10b5_2940 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2977 = + {0x10b5, 0x2977, pci_subsys_10b5_9030_10b5_2977, 0}; +#undef pci_ss_info_10b5_2977 +#define pci_ss_info_10b5_2977 pci_ss_info_10b5_9030_10b5_2977 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2978 = + {0x10b5, 0x2978, pci_subsys_10b5_9030_10b5_2978, 0}; +#undef pci_ss_info_10b5_2978 +#define pci_ss_info_10b5_2978 pci_ss_info_10b5_9030_10b5_2978 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3025 = + {0x10b5, 0x3025, pci_subsys_10b5_9030_10b5_3025, 0}; +#undef pci_ss_info_10b5_3025 +#define pci_ss_info_10b5_3025 pci_ss_info_10b5_9030_10b5_3025 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3068 = + {0x10b5, 0x3068, pci_subsys_10b5_9030_10b5_3068, 0}; +#undef pci_ss_info_10b5_3068 +#define pci_ss_info_10b5_3068 pci_ss_info_10b5_9030_10b5_3068 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3136 = + {0x1397, 0x3136, pci_subsys_10b5_9030_1397_3136, 0}; +#undef pci_ss_info_1397_3136 +#define pci_ss_info_1397_3136 pci_ss_info_10b5_9030_1397_3136 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3137 = + {0x1397, 0x3137, pci_subsys_10b5_9030_1397_3137, 0}; +#undef pci_ss_info_1397_3137 +#define pci_ss_info_1397_3137 pci_ss_info_10b5_9030_1397_3137 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1518_0200 = + {0x1518, 0x0200, pci_subsys_10b5_9030_1518_0200, 0}; +#undef pci_ss_info_1518_0200 +#define pci_ss_info_1518_0200 pci_ss_info_10b5_9030_1518_0200 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1067 = + {0x10b5, 0x1067, pci_subsys_10b5_9050_10b5_1067, 0}; +#undef pci_ss_info_10b5_1067 +#define pci_ss_info_10b5_1067 pci_ss_info_10b5_9050_10b5_1067 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1172 = + {0x10b5, 0x1172, pci_subsys_10b5_9050_10b5_1172, 0}; +#undef pci_ss_info_10b5_1172 +#define pci_ss_info_10b5_1172 pci_ss_info_10b5_9050_10b5_1172 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2221 = + {0x10b5, 0x2221, pci_subsys_10b5_9050_10b5_2221, 0}; +#undef pci_ss_info_10b5_2221 +#define pci_ss_info_10b5_2221 pci_ss_info_10b5_9050_10b5_2221 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2431 = + {0x10b5, 0x2431, pci_subsys_10b5_9050_10b5_2431, 0}; +#undef pci_ss_info_10b5_2431 +#define pci_ss_info_10b5_2431 pci_ss_info_10b5_9050_10b5_2431 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2905 = + {0x10b5, 0x2905, pci_subsys_10b5_9050_10b5_2905, 0}; +#undef pci_ss_info_10b5_2905 +#define pci_ss_info_10b5_2905 pci_ss_info_10b5_9050_10b5_2905 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1498_0362 = + {0x1498, 0x0362, pci_subsys_10b5_9050_1498_0362, 0}; +#undef pci_ss_info_1498_0362 +#define pci_ss_info_1498_0362 pci_ss_info_10b5_9050_1498_0362 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_2036 = + {0x5654, 0x2036, pci_subsys_10b5_9050_5654_2036, 0}; +#undef pci_ss_info_5654_2036 +#define pci_ss_info_5654_2036 pci_ss_info_10b5_9050_5654_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_3132 = + {0x5654, 0x3132, pci_subsys_10b5_9050_5654_3132, 0}; +#undef pci_ss_info_5654_3132 +#define pci_ss_info_5654_3132 pci_ss_info_10b5_9050_5654_3132 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2696 = + {0x10b5, 0x2696, pci_subsys_10b5_9054_10b5_2696, 0}; +#undef pci_ss_info_10b5_2696 +#define pci_ss_info_10b5_2696 pci_ss_info_10b5_9054_10b5_2696 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2717 = + {0x10b5, 0x2717, pci_subsys_10b5_9054_10b5_2717, 0}; +#undef pci_ss_info_10b5_2717 +#define pci_ss_info_10b5_2717 pci_ss_info_10b5_9054_10b5_2717 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2844 = + {0x10b5, 0x2844, pci_subsys_10b5_9054_10b5_2844, 0}; +#undef pci_ss_info_10b5_2844 +#define pci_ss_info_10b5_2844 pci_ss_info_10b5_9054_10b5_2844 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12c7_4001 = + {0x12c7, 0x4001, pci_subsys_10b5_9054_12c7_4001, 0}; +#undef pci_ss_info_12c7_4001 +#define pci_ss_info_12c7_4001 pci_ss_info_10b5_9054_12c7_4001 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9054_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9054_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0011 = + {0x16df, 0x0011, pci_subsys_10b5_9054_16df_0011, 0}; +#undef pci_ss_info_16df_0011 +#define pci_ss_info_16df_0011 pci_ss_info_10b5_9054_16df_0011 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0012 = + {0x16df, 0x0012, pci_subsys_10b5_9054_16df_0012, 0}; +#undef pci_ss_info_16df_0012 +#define pci_ss_info_16df_0012 pci_ss_info_10b5_9054_16df_0012 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0013 = + {0x16df, 0x0013, pci_subsys_10b5_9054_16df_0013, 0}; +#undef pci_ss_info_16df_0013 +#define pci_ss_info_16df_0013 pci_ss_info_10b5_9054_16df_0013 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0014 = + {0x16df, 0x0014, pci_subsys_10b5_9054_16df_0014, 0}; +#undef pci_ss_info_16df_0014 +#define pci_ss_info_16df_0014 pci_ss_info_10b5_9054_16df_0014 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0015 = + {0x16df, 0x0015, pci_subsys_10b5_9054_16df_0015, 0}; +#undef pci_ss_info_16df_0015 +#define pci_ss_info_16df_0015 pci_ss_info_10b5_9054_16df_0015 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0016 = + {0x16df, 0x0016, pci_subsys_10b5_9054_16df_0016, 0}; +#undef pci_ss_info_16df_0016 +#define pci_ss_info_16df_0016 pci_ss_info_10b5_9054_16df_0016 +static const pciSubsystemInfo pci_ss_info_10b5_9056_10b5_2979 = + {0x10b5, 0x2979, pci_subsys_10b5_9056_10b5_2979, 0}; +#undef pci_ss_info_10b5_2979 +#define pci_ss_info_10b5_2979 pci_ss_info_10b5_9056_10b5_2979 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10eb = + {0x103c, 0x10eb, pci_subsys_10b5_9080_103c_10eb, 0}; +#undef pci_ss_info_103c_10eb +#define pci_ss_info_103c_10eb pci_ss_info_10b5_9080_103c_10eb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10ec = + {0x103c, 0x10ec, pci_subsys_10b5_9080_103c_10ec, 0}; +#undef pci_ss_info_103c_10ec +#define pci_ss_info_103c_10ec pci_ss_info_10b5_9080_103c_10ec +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9080_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9080_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12df_4422 = + {0x12df, 0x4422, pci_subsys_10b5_9080_12df_4422, 0}; +#undef pci_ss_info_12df_4422 +#define pci_ss_info_12df_4422 pci_ss_info_10b5_9080_12df_4422 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_0013_10b7_2031 = + {0x10b7, 0x2031, pci_subsys_10b7_0013_10b7_2031, 0}; +#undef pci_ss_info_10b7_2031 +#define pci_ss_info_10b7_2031 pci_ss_info_10b7_0013_10b7_2031 +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_1700_1043_80eb = + {0x1043, 0x80eb, pci_subsys_10b7_1700_1043_80eb, 0}; +#undef pci_ss_info_1043_80eb +#define pci_ss_info_1043_80eb pci_ss_info_10b7_1700_1043_80eb +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0010 = + {0x10b7, 0x0010, pci_subsys_10b7_1700_10b7_0010, 0}; +#undef pci_ss_info_10b7_0010 +#define pci_ss_info_10b7_0010 pci_ss_info_10b7_1700_10b7_0010 +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0020 = + {0x10b7, 0x0020, pci_subsys_10b7_1700_10b7_0020, 0}; +#undef pci_ss_info_10b7_0020 +#define pci_ss_info_10b7_0020 pci_ss_info_10b7_1700_10b7_0020 +static const pciSubsystemInfo pci_ss_info_10b7_1700_147b_1407 = + {0x147b, 0x1407, pci_subsys_10b7_1700_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_10b7_1700_147b_1407 +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9200_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9200_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_00fe = + {0x1028, 0x00fe, pci_subsys_10b7_9200_1028_00fe, 0}; +#undef pci_ss_info_1028_00fe +#define pci_ss_info_1028_00fe pci_ss_info_10b7_9200_1028_00fe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_012a = + {0x1028, 0x012a, pci_subsys_10b7_9200_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_10b7_9200_1028_012a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10f1_2466 = + {0x10f1, 0x2466, pci_subsys_10b7_9200_10f1_2466, 0}; +#undef pci_ss_info_10f1_2466 +#define pci_ss_info_10f1_2466 pci_ss_info_10b7_9200_10f1_2466 +static const pciSubsystemInfo pci_ss_info_10b7_9201_1043_80ab = + {0x1043, 0x80ab, pci_subsys_10b7_9201_1043_80ab, 0}; +#undef pci_ss_info_1043_80ab +#define pci_ss_info_1043_80ab pci_ss_info_10b7_9201_1043_80ab +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_1014_053b = + {0x1014, 0x053b, pci_subsys_10b9_1533_1014_053b, 0}; +#undef pci_ss_info_1014_053b +#define pci_ss_info_1014_053b pci_ss_info_10b9_1533_1014_053b +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_050f = + {0x1014, 0x050f, pci_subsys_10b9_5229_1014_050f, 0}; +#undef pci_ss_info_1014_050f +#define pci_ss_info_1014_050f pci_ss_info_10b9_5229_1014_050f +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_053d = + {0x1014, 0x053d, pci_subsys_10b9_5229_1014_053d, 0}; +#undef pci_ss_info_1014_053d +#define pci_ss_info_1014_053d pci_ss_info_10b9_5229_1014_053d +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5229_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5229_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5229_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5237_1014_0540 = + {0x1014, 0x0540, pci_subsys_10b9_5237_1014_0540, 0}; +#undef pci_ss_info_1014_0540 +#define pci_ss_info_1014_0540 pci_ss_info_10b9_5237_1014_0540 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5237_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5237_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_104d_810f = + {0x104d, 0x810f, pci_subsys_10b9_5237_104d_810f, 0}; +#undef pci_ss_info_104d_810f +#define pci_ss_info_104d_810f pci_ss_info_10b9_5237_104d_810f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_053e = + {0x1014, 0x053e, pci_subsys_10b9_5451_1014_053e, 0}; +#undef pci_ss_info_1014_053e +#define pci_ss_info_1014_053e pci_ss_info_10b9_5451_1014_053e +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5451_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5451_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5451_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_10b9_5451 = + {0x10b9, 0x5451, pci_subsys_10b9_5451_10b9_5451, 0}; +#undef pci_ss_info_10b9_5451 +#define pci_ss_info_10b9_5451 pci_ss_info_10b9_5451_10b9_5451 +static const pciSubsystemInfo pci_ss_info_10b9_5457_1014_0535 = + {0x1014, 0x0535, pci_subsys_10b9_5457_1014_0535, 0}; +#undef pci_ss_info_1014_0535 +#define pci_ss_info_1014_0535 pci_ss_info_10b9_5457_1014_0535 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5457_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5457_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5457_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_0510 = + {0x1014, 0x0510, pci_subsys_10b9_7101_1014_0510, 0}; +#undef pci_ss_info_1014_0510 +#define pci_ss_info_1014_0510 pci_ss_info_10b9_7101_1014_0510 +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_053c = + {0x1014, 0x053c, pci_subsys_10b9_7101_1014_053c, 0}; +#undef pci_ss_info_1014_053c +#define pci_ss_info_1014_053c pci_ss_info_10b9_7101_1014_053c +#endif +static const pciSubsystemInfo pci_ss_info_10b9_7101_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_7101_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_7101_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_0005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_0005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_8005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_8005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c19 = + {0x1048, 0x0c19, pci_subsys_10de_0020_1048_0c19, 0}; +#undef pci_ss_info_1048_0c19 +#define pci_ss_info_1048_0c19 pci_ss_info_10de_0020_1048_0c19 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1c = + {0x1048, 0x0c1c, pci_subsys_10de_0020_1048_0c1c, 0}; +#undef pci_ss_info_1048_0c1c +#define pci_ss_info_1048_0c1c pci_ss_info_10de_0020_1048_0c1c +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_0028_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_0028_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c28 = + {0x1048, 0x0c28, pci_subsys_10de_0028_1048_0c28, 0}; +#undef pci_ss_info_1048_0c28 +#define pci_ss_info_1048_0c28 pci_ss_info_10de_0028_1048_0c28 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c29 = + {0x1048, 0x0c29, pci_subsys_10de_0028_1048_0c29, 0}; +#undef pci_ss_info_1048_0c29 +#define pci_ss_info_1048_0c29 pci_ss_info_10de_0028_1048_0c29 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2a = + {0x1048, 0x0c2a, pci_subsys_10de_0028_1048_0c2a, 0}; +#undef pci_ss_info_1048_0c2a +#define pci_ss_info_1048_0c2a pci_ss_info_10de_0028_1048_0c2a +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2b = + {0x1048, 0x0c2b, pci_subsys_10de_0028_1048_0c2b, 0}; +#undef pci_ss_info_1048_0c2b +#define pci_ss_info_1048_0c2b pci_ss_info_10de_0028_1048_0c2b +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c31 = + {0x1048, 0x0c31, pci_subsys_10de_0028_1048_0c31, 0}; +#undef pci_ss_info_1048_0c31 +#define pci_ss_info_1048_0c31 pci_ss_info_10de_0028_1048_0c31 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c32 = + {0x1048, 0x0c32, pci_subsys_10de_0028_1048_0c32, 0}; +#undef pci_ss_info_1048_0c32 +#define pci_ss_info_1048_0c32 pci_ss_info_10de_0028_1048_0c32 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c33 = + {0x1048, 0x0c33, pci_subsys_10de_0028_1048_0c33, 0}; +#undef pci_ss_info_1048_0c33 +#define pci_ss_info_1048_0c33 pci_ss_info_10de_0028_1048_0c33 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c34 = + {0x1048, 0x0c34, pci_subsys_10de_0028_1048_0c34, 0}; +#undef pci_ss_info_1048_0c34 +#define pci_ss_info_1048_0c34 pci_ss_info_10de_0028_1048_0c34 +static const pciSubsystemInfo pci_ss_info_10de_0028_107d_2134 = + {0x107d, 0x2134, pci_subsys_10de_0028_107d_2134, 0}; +#undef pci_ss_info_107d_2134 +#define pci_ss_info_107d_2134 pci_ss_info_10de_0028_107d_2134 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2e = + {0x1048, 0x0c2e, pci_subsys_10de_0029_1048_0c2e, 0}; +#undef pci_ss_info_1048_0c2e +#define pci_ss_info_1048_0c2e pci_ss_info_10de_0029_1048_0c2e +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2f = + {0x1048, 0x0c2f, pci_subsys_10de_0029_1048_0c2f, 0}; +#undef pci_ss_info_1048_0c2f +#define pci_ss_info_1048_0c2f pci_ss_info_10de_0029_1048_0c2f +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c30 = + {0x1048, 0x0c30, pci_subsys_10de_0029_1048_0c30, 0}; +#undef pci_ss_info_1048_0c30 +#define pci_ss_info_1048_0c30 pci_ss_info_10de_0029_1048_0c30 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c20 = + {0x1048, 0x0c20, pci_subsys_10de_002c_1048_0c20, 0}; +#undef pci_ss_info_1048_0c20 +#define pci_ss_info_1048_0c20 pci_ss_info_10de_002c_1048_0c20 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_002c_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_002c_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3b = + {0x1048, 0x0c3b, pci_subsys_10de_002d_1048_0c3b, 0}; +#undef pci_ss_info_1048_0c3b +#define pci_ss_info_1048_0c3b pci_ss_info_10de_002d_1048_0c3b +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_002d_1569_002d = + {0x1569, 0x002d, pci_subsys_10de_002d_1569_002d, 0}; +#undef pci_ss_info_1569_002d +#define pci_ss_info_1569_002d pci_ss_info_10de_002d_1569_002d +static const pciSubsystemInfo pci_ss_info_10de_0041_1043_817b = + {0x1043, 0x817b, pci_subsys_10de_0041_1043_817b, 0}; +#undef pci_ss_info_1043_817b +#define pci_ss_info_1043_817b pci_ss_info_10de_0041_1043_817b +static const pciSubsystemInfo pci_ss_info_10de_0047_1682_2109 = + {0x1682, 0x2109, pci_subsys_10de_0047_1682_2109, 0}; +#undef pci_ss_info_1682_2109 +#define pci_ss_info_1682_2109 pci_ss_info_10de_0047_1682_2109 +static const pciSubsystemInfo pci_ss_info_10de_0050_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0050_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0050_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0050_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0050_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0050_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0050_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0050_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0050_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0052_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0052_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0052_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0052_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0052_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0052_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0052_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0052_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0052_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0053_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0053_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0053_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0053_1458_5002 = + {0x1458, 0x5002, pci_subsys_10de_0053_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_10de_0053_1458_5002 +static const pciSubsystemInfo pci_ss_info_10de_0053_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0053_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0053_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0054_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0054_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0054_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0055_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0055_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0055_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0057_1043_8141 = + {0x1043, 0x8141, pci_subsys_10de_0057_1043_8141, 0}; +#undef pci_ss_info_1043_8141 +#define pci_ss_info_1043_8141 pci_ss_info_10de_0057_1043_8141 +static const pciSubsystemInfo pci_ss_info_10de_0057_1458_e000 = + {0x1458, 0xe000, pci_subsys_10de_0057_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10de_0057_1458_e000 +static const pciSubsystemInfo pci_ss_info_10de_0057_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0057_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0057_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0059_1043_812a = + {0x1043, 0x812a, pci_subsys_10de_0059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_10de_0059_1043_812a +static const pciSubsystemInfo pci_ss_info_10de_005a_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005a_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005a_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005a_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005a_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005a_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005a_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005a_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005a_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005b_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005b_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005b_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005b_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005b_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005b_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005b_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005b_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005b_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005e_1458_5000 = + {0x1458, 0x5000, pci_subsys_10de_005e_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_10de_005e_1458_5000 +static const pciSubsystemInfo pci_ss_info_10de_005e_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005e_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005e_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0066_1043_80a7 = + {0x1043, 0x80a7, pci_subsys_10de_0066_1043_80a7, 0}; +#undef pci_ss_info_1043_80a7 +#define pci_ss_info_1043_80a7 pci_ss_info_10de_0066_1043_80a7 +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_006b_10de_006b = + {0x10de, 0x006b, pci_subsys_10de_006b_10de_006b, 0}; +#undef pci_ss_info_10de_006b +#define pci_ss_info_10de_006b pci_ss_info_10de_006b_10de_006b +static const pciSubsystemInfo pci_ss_info_10de_0080_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0080_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0080_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0084_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0084_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0084_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0085_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0085_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0085_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0087_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0087_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0087_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0088_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0088_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0088_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_008a_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_008a_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_008a_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_00df_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00df_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00df_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e0_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e0_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e0_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e1_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e1_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e1_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e3_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e3_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e3_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e4_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e4_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e4_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e5_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e5_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e5_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e7_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e7_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e7_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e8_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e8_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e8_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00ea_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00ea_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00ea_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00f1_1043_81a6 = + {0x1043, 0x81a6, pci_subsys_10de_00f1_1043_81a6, 0}; +#undef pci_ss_info_1043_81a6 +#define pci_ss_info_1043_81a6 pci_ss_info_10de_00f1_1043_81a6 +static const pciSubsystemInfo pci_ss_info_10de_00f2_1682_211c = + {0x1682, 0x211c, pci_subsys_10de_00f2_1682_211c, 0}; +#undef pci_ss_info_1682_211c +#define pci_ss_info_1682_211c pci_ss_info_10de_00f2_1682_211c +static const pciSubsystemInfo pci_ss_info_10de_00f9_1682_2120 = + {0x1682, 0x2120, pci_subsys_10de_00f9_1682_2120, 0}; +#undef pci_ss_info_1682_2120 +#define pci_ss_info_1682_2120 pci_ss_info_10de_00f9_1682_2120 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c41 = + {0x1048, 0x0c41, pci_subsys_10de_0100_1048_0c41, 0}; +#undef pci_ss_info_1048_0c41 +#define pci_ss_info_1048_0c41 pci_ss_info_10de_0100_1048_0c41 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c43 = + {0x1048, 0x0c43, pci_subsys_10de_0100_1048_0c43, 0}; +#undef pci_ss_info_1048_0c43 +#define pci_ss_info_1048_0c43 pci_ss_info_10de_0100_1048_0c43 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c48 = + {0x1048, 0x0c48, pci_subsys_10de_0100_1048_0c48, 0}; +#undef pci_ss_info_1048_0c48 +#define pci_ss_info_1048_0c48 pci_ss_info_10de_0100_1048_0c48 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1048_0c42 = + {0x1048, 0x0c42, pci_subsys_10de_0101_1048_0c42, 0}; +#undef pci_ss_info_1048_0c42 +#define pci_ss_info_1048_0c42 pci_ss_info_10de_0101_1048_0c42 +static const pciSubsystemInfo pci_ss_info_10de_0101_107d_2822 = + {0x107d, 0x2822, pci_subsys_10de_0101_107d_2822, 0}; +#undef pci_ss_info_107d_2822 +#define pci_ss_info_107d_2822 pci_ss_info_10de_0101_107d_2822 +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c40 = + {0x1048, 0x0c40, pci_subsys_10de_0103_1048_0c40, 0}; +#undef pci_ss_info_1048_0c40 +#define pci_ss_info_1048_0c40 pci_ss_info_10de_0103_1048_0c40 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c44 = + {0x1048, 0x0c44, pci_subsys_10de_0103_1048_0c44, 0}; +#undef pci_ss_info_1048_0c44 +#define pci_ss_info_1048_0c44 pci_ss_info_10de_0103_1048_0c44 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c45 = + {0x1048, 0x0c45, pci_subsys_10de_0103_1048_0c45, 0}; +#undef pci_ss_info_1048_0c45 +#define pci_ss_info_1048_0c45 pci_ss_info_10de_0103_1048_0c45 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4a = + {0x1048, 0x0c4a, pci_subsys_10de_0103_1048_0c4a, 0}; +#undef pci_ss_info_1048_0c4a +#define pci_ss_info_1048_0c4a pci_ss_info_10de_0103_1048_0c4a +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4b = + {0x1048, 0x0c4b, pci_subsys_10de_0103_1048_0c4b, 0}; +#undef pci_ss_info_1048_0c4b +#define pci_ss_info_1048_0c4b pci_ss_info_10de_0103_1048_0c4b +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c60 = + {0x1048, 0x0c60, pci_subsys_10de_0110_1048_0c60, 0}; +#undef pci_ss_info_1048_0c60 +#define pci_ss_info_1048_0c60 pci_ss_info_10de_0110_1048_0c60 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c61 = + {0x1048, 0x0c61, pci_subsys_10de_0110_1048_0c61, 0}; +#undef pci_ss_info_1048_0c61 +#define pci_ss_info_1048_0c61 pci_ss_info_10de_0110_1048_0c61 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c63 = + {0x1048, 0x0c63, pci_subsys_10de_0110_1048_0c63, 0}; +#undef pci_ss_info_1048_0c63 +#define pci_ss_info_1048_0c63 pci_ss_info_10de_0110_1048_0c63 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c64 = + {0x1048, 0x0c64, pci_subsys_10de_0110_1048_0c64, 0}; +#undef pci_ss_info_1048_0c64 +#define pci_ss_info_1048_0c64 pci_ss_info_10de_0110_1048_0c64 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c65 = + {0x1048, 0x0c65, pci_subsys_10de_0110_1048_0c65, 0}; +#undef pci_ss_info_1048_0c65 +#define pci_ss_info_1048_0c65 pci_ss_info_10de_0110_1048_0c65 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c66 = + {0x1048, 0x0c66, pci_subsys_10de_0110_1048_0c66, 0}; +#undef pci_ss_info_1048_0c66 +#define pci_ss_info_1048_0c66 pci_ss_info_10de_0110_1048_0c66 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_0091 = + {0x10de, 0x0091, pci_subsys_10de_0110_10de_0091, 0}; +#undef pci_ss_info_10de_0091 +#define pci_ss_info_10de_0091 pci_ss_info_10de_0110_10de_0091 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_00a1 = + {0x10de, 0x00a1, pci_subsys_10de_0110_10de_00a1, 0}; +#undef pci_ss_info_10de_00a1 +#define pci_ss_info_10de_00a1 pci_ss_info_10de_0110_10de_00a1 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0141_1458_3124 = + {0x1458, 0x3124, pci_subsys_10de_0141_1458_3124, 0}; +#undef pci_ss_info_1458_3124 +#define pci_ss_info_1458_3124 pci_ss_info_10de_0141_1458_3124 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c50 = + {0x1048, 0x0c50, pci_subsys_10de_0150_1048_0c50, 0}; +#undef pci_ss_info_1048_0c50 +#define pci_ss_info_1048_0c50 pci_ss_info_10de_0150_1048_0c50 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c52 = + {0x1048, 0x0c52, pci_subsys_10de_0150_1048_0c52, 0}; +#undef pci_ss_info_1048_0c52 +#define pci_ss_info_1048_0c52 pci_ss_info_10de_0150_1048_0c52 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2842 = + {0x107d, 0x2842, pci_subsys_10de_0150_107d_2842, 0}; +#undef pci_ss_info_107d_2842 +#define pci_ss_info_107d_2842 pci_ss_info_10de_0150_107d_2842 +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0151_1462_5506 = + {0x1462, 0x5506, pci_subsys_10de_0151_1462_5506, 0}; +#undef pci_ss_info_1462_5506 +#define pci_ss_info_1462_5506 pci_ss_info_10de_0151_1462_5506 +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_10b0_0002 = + {0x10b0, 0x0002, pci_subsys_10de_0171_10b0_0002, 0}; +#undef pci_ss_info_10b0_0002 +#define pci_ss_info_10b0_0002 pci_ss_info_10de_0171_10b0_0002 +static const pciSubsystemInfo pci_ss_info_10de_0171_10de_0008 = + {0x10de, 0x0008, pci_subsys_10de_0171_10de_0008, 0}; +#undef pci_ss_info_10de_0008 +#define pci_ss_info_10de_0008 pci_ss_info_10de_0171_10de_0008 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8852 = + {0x1462, 0x8852, pci_subsys_10de_0171_1462_8852, 0}; +#undef pci_ss_info_1462_8852 +#define pci_ss_info_1462_8852 pci_ss_info_10de_0171_1462_8852 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0176_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_10de_0176_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_10de_0176_4c53_1090 +static const pciSubsystemInfo pci_ss_info_10de_0179_10de_0179 = + {0x10de, 0x0179, pci_subsys_10de_0179_10de_0179, 0}; +#undef pci_ss_info_10de_0179 +#define pci_ss_info_10de_0179 pci_ss_info_10de_0179_10de_0179 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_806f = + {0x1043, 0x806f, pci_subsys_10de_0181_1043_806f, 0}; +#undef pci_ss_info_1043_806f +#define pci_ss_info_1043_806f pci_ss_info_10de_0181_1043_806f +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8880 = + {0x1462, 0x8880, pci_subsys_10de_0181_1462_8880, 0}; +#undef pci_ss_info_1462_8880 +#define pci_ss_info_1462_8880 pci_ss_info_10de_0181_1462_8880 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8900 = + {0x1462, 0x8900, pci_subsys_10de_0181_1462_8900, 0}; +#undef pci_ss_info_1462_8900 +#define pci_ss_info_1462_8900 pci_ss_info_10de_0181_1462_8900 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_9350 = + {0x1462, 0x9350, pci_subsys_10de_0181_1462_9350, 0}; +#undef pci_ss_info_1462_9350 +#define pci_ss_info_1462_9350 pci_ss_info_10de_0181_1462_9350 +static const pciSubsystemInfo pci_ss_info_10de_0181_147b_8f0d = + {0x147b, 0x8f0d, pci_subsys_10de_0181_147b_8f0d, 0}; +#undef pci_ss_info_147b_8f0d +#define pci_ss_info_147b_8f0d pci_ss_info_10de_0181_147b_8f0d +static const pciSubsystemInfo pci_ss_info_10de_01e0_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_01e0_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_01e0_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0200_1048_0c70 = + {0x1048, 0x0c70, pci_subsys_10de_0200_1048_0c70, 0}; +#undef pci_ss_info_1048_0c70 +#define pci_ss_info_1048_0c70 pci_ss_info_10de_0200_1048_0c70 +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0251_1043_8023 = + {0x1043, 0x8023, pci_subsys_10de_0251_1043_8023, 0}; +#undef pci_ss_info_1043_8023 +#define pci_ss_info_1043_8023 pci_ss_info_10de_0251_1043_8023 +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +static const pciSubsystemInfo pci_ss_info_10de_0314_1043_814a = + {0x1043, 0x814a, pci_subsys_10de_0314_1043_814a, 0}; +#undef pci_ss_info_1043_814a +#define pci_ss_info_1043_814a pci_ss_info_10de_0314_1043_814a +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9171 = + {0x1462, 0x9171, pci_subsys_10de_0322_1462_9171, 0}; +#undef pci_ss_info_1462_9171 +#define pci_ss_info_1462_9171 pci_ss_info_10de_0322_1462_9171 +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9360 = + {0x1462, 0x9360, pci_subsys_10de_0322_1462_9360, 0}; +#undef pci_ss_info_1462_9360 +#define pci_ss_info_1462_9360 pci_ss_info_10de_0322_1462_9360 +static const pciSubsystemInfo pci_ss_info_10de_0324_1028_0196 = + {0x1028, 0x0196, pci_subsys_10de_0324_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_10de_0324_1028_0196 +static const pciSubsystemInfo pci_ss_info_10de_0324_1071_8160 = + {0x1071, 0x8160, pci_subsys_10de_0324_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10de_0324_1071_8160 +static const pciSubsystemInfo pci_ss_info_10de_0331_1043_8145 = + {0x1043, 0x8145, pci_subsys_10de_0331_1043_8145, 0}; +#undef pci_ss_info_1043_8145 +#define pci_ss_info_1043_8145 pci_ss_info_10de_0331_1043_8145 +static const pciSubsystemInfo pci_ss_info_10de_0347_103c_006a = + {0x103c, 0x006a, pci_subsys_10de_0347_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10de_0347_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +static const pciSubsystemInfo pci_ss_info_10ec_8139_0357_000a = + {0x0357, 0x000a, pci_subsys_10ec_8139_0357_000a, 0}; +#undef pci_ss_info_0357_000a +#define pci_ss_info_0357_000a pci_ss_info_10ec_8139_0357_000a +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_005a = + {0x1025, 0x005a, pci_subsys_10ec_8139_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_10ec_8139_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_103c_006a = + {0x103c, 0x006a, pci_subsys_10ec_8139_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10ec_8139_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_1043_8109 = + {0x1043, 0x8109, pci_subsys_10ec_8139_1043_8109, 0}; +#undef pci_ss_info_1043_8109 +#define pci_ss_info_1043_8109 pci_ss_info_10ec_8139_1043_8109 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1071_8160 = + {0x1071, 0x8160, pci_subsys_10ec_8139_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10ec_8139_1071_8160 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1113_ec01 = + {0x1113, 0xec01, pci_subsys_10ec_8139_1113_ec01, 0}; +#undef pci_ss_info_1113_ec01 +#define pci_ss_info_1113_ec01 pci_ss_info_10ec_8139_1113_ec01 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8139_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8139_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1462_788c = + {0x1462, 0x788c, pci_subsys_10ec_8139_1462_788c, 0}; +#undef pci_ss_info_1462_788c +#define pci_ss_info_1462_788c pci_ss_info_10ec_8139_1462_788c +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_14cb_0200 = + {0x14cb, 0x0200, pci_subsys_10ec_8139_14cb_0200, 0}; +#undef pci_ss_info_14cb_0200 +#define pci_ss_info_14cb_0200 pci_ss_info_10ec_8139_14cb_0200 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1799_5000 = + {0x1799, 0x5000, pci_subsys_10ec_8139_1799_5000, 0}; +#undef pci_ss_info_1799_5000 +#define pci_ss_info_1799_5000 pci_ss_info_10ec_8139_1799_5000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_9001_1695 = + {0x9001, 0x1695, pci_subsys_10ec_8139_9001_1695, 0}; +#undef pci_ss_info_9001_1695 +#define pci_ss_info_9001_1695 pci_ss_info_10ec_8139_9001_1695 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1259_c107 = + {0x1259, 0xc107, pci_subsys_10ec_8169_1259_c107, 0}; +#undef pci_ss_info_1259_c107 +#define pci_ss_info_1259_c107 pci_ss_info_10ec_8169_1259_c107 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +static const pciSubsystemInfo pci_ss_info_10ec_8169_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8169_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8169_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1462_702c = + {0x1462, 0x702c, pci_subsys_10ec_8169_1462_702c, 0}; +#undef pci_ss_info_1462_702c +#define pci_ss_info_1462_702c pci_ss_info_10ec_8169_1462_702c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_100a = + {0x1102, 0x100a, pci_subsys_1102_0002_1102_100a, 0}; +#undef pci_ss_info_1102_100a +#define pci_ss_info_1102_100a pci_ss_info_1102_0002_1102_100a +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8064 = + {0x1102, 0x8064, pci_subsys_1102_0002_1102_8064, 0}; +#undef pci_ss_info_1102_8064 +#define pci_ss_info_1102_8064 pci_ss_info_1102_0002_1102_8064 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8065 = + {0x1102, 0x8065, pci_subsys_1102_0002_1102_8065, 0}; +#undef pci_ss_info_1102_8065 +#define pci_ss_info_1102_8065 pci_ss_info_1102_0002_1102_8065 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8067 = + {0x1102, 0x8067, pci_subsys_1102_0002_1102_8067, 0}; +#undef pci_ss_info_1102_8067 +#define pci_ss_info_1102_8067 pci_ss_info_1102_0002_1102_8067 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0058 = + {0x1102, 0x0058, pci_subsys_1102_0004_1102_0058, 0}; +#undef pci_ss_info_1102_0058 +#define pci_ss_info_1102_0058 pci_ss_info_1102_0004_1102_0058 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_1007 = + {0x1102, 0x1007, pci_subsys_1102_0004_1102_1007, 0}; +#undef pci_ss_info_1102_1007 +#define pci_ss_info_1102_1007 pci_ss_info_1102_0004_1102_1007 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_2002 = + {0x1102, 0x2002, pci_subsys_1102_0004_1102_2002, 0}; +#undef pci_ss_info_1102_2002 +#define pci_ss_info_1102_2002 pci_ss_info_1102_0004_1102_2002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_0007 = + {0x1102, 0x0007, pci_subsys_1102_0007_1102_0007, 0}; +#undef pci_ss_info_1102_0007 +#define pci_ss_info_1102_0007 pci_ss_info_1102_0007_1102_0007 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_0007_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_0007_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_0007_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_0007_1102_1002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1006 = + {0x1102, 0x1006, pci_subsys_1102_0007_1102_1006, 0}; +#undef pci_ss_info_1102_1006 +#define pci_ss_info_1102_1006 pci_ss_info_1102_0007_1102_1006 +static const pciSubsystemInfo pci_ss_info_1102_0007_1462_1009 = + {0x1462, 0x1009, pci_subsys_1102_0007_1462_1009, 0}; +#undef pci_ss_info_1462_1009 +#define pci_ss_info_1462_1009 pci_ss_info_1102_0007_1462_1009 +static const pciSubsystemInfo pci_ss_info_1102_0008_1102_0008 = + {0x1102, 0x0008, pci_subsys_1102_0008_1102_0008, 0}; +#undef pci_ss_info_1102_0008 +#define pci_ss_info_1102_0008 pci_ss_info_1102_0008_1102_0008 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_7005_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_7005_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_7005_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_7005_1102_1002 +#endif +static const pciSubsystemInfo pci_ss_info_1102_8938_1033_80e5 = + {0x1033, 0x80e5, pci_subsys_1102_8938_1033_80e5, 0}; +#undef pci_ss_info_1033_80e5 +#define pci_ss_info_1033_80e5 pci_ss_info_1102_8938_1033_80e5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_8938_1071_7150 = + {0x1071, 0x7150, pci_subsys_1102_8938_1071_7150, 0}; +#undef pci_ss_info_1071_7150 +#define pci_ss_info_1071_7150 pci_ss_info_1102_8938_1071_7150 +static const pciSubsystemInfo pci_ss_info_1102_8938_110a_5938 = + {0x110a, 0x5938, pci_subsys_1102_8938_110a_5938, 0}; +#undef pci_ss_info_110a_5938 +#define pci_ss_info_110a_5938 pci_ss_info_1102_8938_110a_5938 +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100c = + {0x13bd, 0x100c, pci_subsys_1102_8938_13bd_100c, 0}; +#undef pci_ss_info_13bd_100c +#define pci_ss_info_13bd_100c pci_ss_info_1102_8938_13bd_100c +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100d = + {0x13bd, 0x100d, pci_subsys_1102_8938_13bd_100d, 0}; +#undef pci_ss_info_13bd_100d +#define pci_ss_info_13bd_100d pci_ss_info_1102_8938_13bd_100d +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100e = + {0x13bd, 0x100e, pci_subsys_1102_8938_13bd_100e, 0}; +#undef pci_ss_info_13bd_100e +#define pci_ss_info_13bd_100e pci_ss_info_1102_8938_13bd_100e +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_f6f1 = + {0x13bd, 0xf6f1, pci_subsys_1102_8938_13bd_f6f1, 0}; +#undef pci_ss_info_13bd_f6f1 +#define pci_ss_info_13bd_f6f1 pci_ss_info_1102_8938_13bd_f6f1 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_0e70 = + {0x14ff, 0x0e70, pci_subsys_1102_8938_14ff_0e70, 0}; +#undef pci_ss_info_14ff_0e70 +#define pci_ss_info_14ff_0e70 pci_ss_info_1102_8938_14ff_0e70 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_c401 = + {0x14ff, 0xc401, pci_subsys_1102_8938_14ff_c401, 0}; +#undef pci_ss_info_14ff_c401 +#define pci_ss_info_14ff_c401 pci_ss_info_1102_8938_14ff_c401 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b400 = + {0x156d, 0xb400, pci_subsys_1102_8938_156d_b400, 0}; +#undef pci_ss_info_156d_b400 +#define pci_ss_info_156d_b400 pci_ss_info_1102_8938_156d_b400 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b550 = + {0x156d, 0xb550, pci_subsys_1102_8938_156d_b550, 0}; +#undef pci_ss_info_156d_b550 +#define pci_ss_info_156d_b550 pci_ss_info_1102_8938_156d_b550 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b560 = + {0x156d, 0xb560, pci_subsys_1102_8938_156d_b560, 0}; +#undef pci_ss_info_156d_b560 +#define pci_ss_info_156d_b560 pci_ss_info_1102_8938_156d_b560 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b700 = + {0x156d, 0xb700, pci_subsys_1102_8938_156d_b700, 0}; +#undef pci_ss_info_156d_b700 +#define pci_ss_info_156d_b700 pci_ss_info_1102_8938_156d_b700 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b795 = + {0x156d, 0xb795, pci_subsys_1102_8938_156d_b795, 0}; +#undef pci_ss_info_156d_b795 +#define pci_ss_info_156d_b795 pci_ss_info_1102_8938_156d_b795 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b797 = + {0x156d, 0xb797, pci_subsys_1102_8938_156d_b797, 0}; +#undef pci_ss_info_156d_b797 +#define pci_ss_info_156d_b797 pci_ss_info_1102_8938_156d_b797 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0003 = + {0x1103, 0x0003, pci_subsys_1103_0004_1103_0003, 0}; +#undef pci_ss_info_1103_0003 +#define pci_ss_info_1103_0003 pci_ss_info_1103_0004_1103_0003 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0004 = + {0x1103, 0x0004, pci_subsys_1103_0004_1103_0004, 0}; +#undef pci_ss_info_1103_0004 +#define pci_ss_info_1103_0004 pci_ss_info_1103_0004_1103_0004 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0006 = + {0x1103, 0x0006, pci_subsys_1103_0004_1103_0006, 0}; +#undef pci_ss_info_1103_0006 +#define pci_ss_info_1103_0006 pci_ss_info_1103_0004_1103_0006 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0007 = + {0x1103, 0x0007, pci_subsys_1103_0004_1103_0007, 0}; +#undef pci_ss_info_1103_0007 +#define pci_ss_info_1103_0007 pci_ss_info_1103_0004_1103_0007 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0008 = + {0x1103, 0x0008, pci_subsys_1103_0004_1103_0008, 0}; +#undef pci_ss_info_1103_0008 +#define pci_ss_info_1103_0008 pci_ss_info_1103_0004_1103_0008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1105_8475_1105_0001 = + {0x1105, 0x0001, pci_subsys_1105_8475_1105_0001, 0}; +#undef pci_ss_info_1105_0001 +#define pci_ss_info_1105_0001 pci_ss_info_1105_8475_1105_0001 +static const pciSubsystemInfo pci_ss_info_1105_8476_127d_0000 = + {0x127d, 0x0000, pci_subsys_1105_8476_127d_0000, 0}; +#undef pci_ss_info_127d_0000 +#define pci_ss_info_127d_0000 pci_ss_info_1105_8476_127d_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_0282_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_0282_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_0282_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_0305_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_0305_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_0305_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0571_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0571_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_0571_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_0571_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_0571_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_0571_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_0571_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_0571_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_0571_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_0571_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_0571_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_0571_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0571_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_0571_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_0571_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_0571_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_0571_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_0571_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_0571_1849_0571 = + {0x1849, 0x0571, pci_subsys_1106_0571_1849_0571, 0}; +#undef pci_ss_info_1849_0571 +#define pci_ss_info_1849_0571 pci_ss_info_1106_0571_1849_0571 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0605_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0605_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0605_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0686_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0686_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0686_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0686_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0691_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0691_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3038_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3038_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3038_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3038_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_8080 = + {0x1043, 0x8080, pci_subsys_1106_3038_1043_8080, 0}; +#undef pci_ss_info_1043_8080 +#define pci_ss_info_1043_8080 pci_ss_info_1106_3038_1043_8080 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3038_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3038_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3038_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3038_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3038_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3038_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3038_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3038_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3038_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3038_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3038_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3038_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3038_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3038_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3038_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3038_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3038_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3038_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3038_1849_3038 = + {0x1849, 0x3038, pci_subsys_1106_3038_1849_3038, 0}; +#undef pci_ss_info_1849_3038 +#define pci_ss_info_1849_3038 pci_ss_info_1106_3038_1849_3038 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3044_0574_086c = + {0x0574, 0x086c, pci_subsys_1106_3044_0574_086c, 0}; +#undef pci_ss_info_0574_086c +#define pci_ss_info_0574_086c pci_ss_info_1106_3044_0574_086c +#endif +static const pciSubsystemInfo pci_ss_info_1106_3044_1025_005a = + {0x1025, 0x005a, pci_subsys_1106_3044_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1106_3044_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3044_1043_808a = + {0x1043, 0x808a, pci_subsys_1106_3044_1043_808a, 0}; +#undef pci_ss_info_1043_808a +#define pci_ss_info_1043_808a pci_ss_info_1106_3044_1043_808a +static const pciSubsystemInfo pci_ss_info_1106_3044_1458_1000 = + {0x1458, 0x1000, pci_subsys_1106_3044_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_1106_3044_1458_1000 +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_702d = + {0x1462, 0x702d, pci_subsys_1106_3044_1462_702d, 0}; +#undef pci_ss_info_1462_702d +#define pci_ss_info_1462_702d pci_ss_info_1106_3044_1462_702d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_971d = + {0x1462, 0x971d, pci_subsys_1106_3044_1462_971d, 0}; +#undef pci_ss_info_1462_971d +#define pci_ss_info_1462_971d pci_ss_info_1106_3044_1462_971d +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3057_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3057_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3057_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3057_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_0097 = + {0x0e11, 0x0097, pci_subsys_1106_3058_0e11_0097, 0}; +#undef pci_ss_info_0e11_0097 +#define pci_ss_info_0e11_0097 pci_ss_info_1106_3058_0e11_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3058_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3058_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3058_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3058_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3058_1043_1106 = + {0x1043, 0x1106, pci_subsys_1106_3058_1043_1106, 0}; +#undef pci_ss_info_1043_1106 +#define pci_ss_info_1043_1106 pci_ss_info_1106_3058_1043_1106 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3300 = + {0x1462, 0x3300, pci_subsys_1106_3058_1462_3300, 0}; +#undef pci_ss_info_1462_3300 +#define pci_ss_info_1462_3300 pci_ss_info_1106_3058_1462_3300 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3059_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3059_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_8095 = + {0x1043, 0x8095, pci_subsys_1106_3059_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_1106_3059_1043_8095 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3059_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3059_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80b0 = + {0x1043, 0x80b0, pci_subsys_1106_3059_1043_80b0, 0}; +#undef pci_ss_info_1043_80b0 +#define pci_ss_info_1043_80b0 pci_ss_info_1106_3059_1043_80b0 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_812a = + {0x1043, 0x812a, pci_subsys_1106_3059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_1106_3059_1043_812a +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_3059 = + {0x1106, 0x3059, pci_subsys_1106_3059_1106_3059, 0}; +#undef pci_ss_info_1106_3059 +#define pci_ss_info_1106_3059 pci_ss_info_1106_3059_1106_3059 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4161 = + {0x1106, 0x4161, pci_subsys_1106_3059_1106_4161, 0}; +#undef pci_ss_info_1106_4161 +#define pci_ss_info_1106_4161 pci_ss_info_1106_3059_1106_4161 +static const pciSubsystemInfo pci_ss_info_1106_3059_1297_c160 = + {0x1297, 0xc160, pci_subsys_1106_3059_1297_c160, 0}; +#undef pci_ss_info_1297_c160 +#define pci_ss_info_1297_c160 pci_ss_info_1106_3059_1297_c160 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_0080 = + {0x1462, 0x0080, pci_subsys_1106_3059_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_1106_3059_1462_0080 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_3800 = + {0x1462, 0x3800, pci_subsys_1106_3059_1462_3800, 0}; +#undef pci_ss_info_1462_3800 +#define pci_ss_info_1462_3800 pci_ss_info_1106_3059_1462_3800 +static const pciSubsystemInfo pci_ss_info_1106_3059_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3059_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3059_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3059_1849_9761 = + {0x1849, 0x9761, pci_subsys_1106_3059_1849_9761, 0}; +#undef pci_ss_info_1849_9761 +#define pci_ss_info_1849_9761 pci_ss_info_1106_3059_1849_9761 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3059_4005_4710 = + {0x4005, 0x4710, pci_subsys_1106_3059_4005_4710, 0}; +#undef pci_ss_info_4005_4710 +#define pci_ss_info_4005_4710 pci_ss_info_1106_3059_4005_4710 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3059_4170_1106 = + {0x4170, 0x1106, pci_subsys_1106_3059_4170_1106, 0}; +#undef pci_ss_info_4170_1106 +#define pci_ss_info_4170_1106 pci_ss_info_1106_3059_4170_1106 +static const pciSubsystemInfo pci_ss_info_1106_3059_4552_1106 = + {0x4552, 0x1106, pci_subsys_1106_3059_4552_1106, 0}; +#undef pci_ss_info_4552_1106 +#define pci_ss_info_4552_1106 pci_ss_info_1106_3059_4552_1106 +static const pciSubsystemInfo pci_ss_info_1106_3059_a0a0_01b6 = + {0xa0a0, 0x01b6, pci_subsys_1106_3059_a0a0_01b6, 0}; +#undef pci_ss_info_a0a0_01b6 +#define pci_ss_info_a0a0_01b6 pci_ss_info_1106_3059_a0a0_01b6 +static const pciSubsystemInfo pci_ss_info_1106_3065_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3065_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3065_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3065_13b9_1421 = + {0x13b9, 0x1421, pci_subsys_1106_3065_13b9_1421, 0}; +#undef pci_ss_info_13b9_1421 +#define pci_ss_info_13b9_1421 pci_ss_info_1106_3065_13b9_1421 +static const pciSubsystemInfo pci_ss_info_1106_3065_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_1106_3065_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_1106_3065_147b_1c09 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_3005 = + {0x1695, 0x3005, pci_subsys_1106_3065_1695_3005, 0}; +#undef pci_ss_info_1695_3005 +#define pci_ss_info_1695_3005 pci_ss_info_1106_3065_1695_3005 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_300c = + {0x1695, 0x300c, pci_subsys_1106_3065_1695_300c, 0}; +#undef pci_ss_info_1695_300c +#define pci_ss_info_1695_300c pci_ss_info_1106_3065_1695_300c +static const pciSubsystemInfo pci_ss_info_1106_3065_1849_3065 = + {0x1849, 0x3065, pci_subsys_1106_3065_1849_3065, 0}; +#undef pci_ss_info_1849_3065 +#define pci_ss_info_1849_3065 pci_ss_info_1106_3065_1849_3065 +static const pciSubsystemInfo pci_ss_info_1106_3068_1462_309e = + {0x1462, 0x309e, pci_subsys_1106_3068_1462_309e, 0}; +#undef pci_ss_info_1462_309e +#define pci_ss_info_1462_309e pci_ss_info_1106_3068_1462_309e +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3099_1849_3099 = + {0x1849, 0x3099, pci_subsys_1106_3099_1849_3099, 0}; +#undef pci_ss_info_1849_3099 +#define pci_ss_info_1849_3099 pci_ss_info_1106_3099_1849_3099 +static const pciSubsystemInfo pci_ss_info_1106_3104_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3104_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3104_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3104_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3104_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3104_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3104_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3104_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3104_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3104_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3104_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3104_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3104_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3104_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3104_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3104_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3104_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3104_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3104_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3104_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3104_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3104_1849_3104 = + {0x1849, 0x3104, pci_subsys_1106_3104_1849_3104, 0}; +#undef pci_ss_info_1849_3104 +#define pci_ss_info_1849_3104 pci_ss_info_1106_3104_1849_3104 +static const pciSubsystemInfo pci_ss_info_1106_3106_1186_1403 = + {0x1186, 0x1403, pci_subsys_1106_3106_1186_1403, 0}; +#undef pci_ss_info_1186_1403 +#define pci_ss_info_1186_1403 pci_ss_info_1106_3106_1186_1403 +static const pciSubsystemInfo pci_ss_info_1106_3116_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3116_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3116_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3147_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3147_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3147_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3149_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3149_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3149_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3149_1458_b003 = + {0x1458, 0xb003, pci_subsys_1106_3149_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_1106_3149_1458_b003 +static const pciSubsystemInfo pci_ss_info_1106_3149_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3149_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3149_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3149_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3149_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1408 = + {0x147b, 0x1408, pci_subsys_1106_3149_147b_1408, 0}; +#undef pci_ss_info_147b_1408 +#define pci_ss_info_147b_1408 pci_ss_info_1106_3149_147b_1408 +static const pciSubsystemInfo pci_ss_info_1106_3149_1849_3149 = + {0x1849, 0x3149, pci_subsys_1106_3149_1849_3149, 0}; +#undef pci_ss_info_1849_3149 +#define pci_ss_info_1849_3149 pci_ss_info_1106_3149_1849_3149 +static const pciSubsystemInfo pci_ss_info_1106_3164_1043_80f4 = + {0x1043, 0x80f4, pci_subsys_1106_3164_1043_80f4, 0}; +#undef pci_ss_info_1043_80f4 +#define pci_ss_info_1043_80f4 pci_ss_info_1106_3164_1043_80f4 +static const pciSubsystemInfo pci_ss_info_1106_3164_1462_7028 = + {0x1462, 0x7028, pci_subsys_1106_3164_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_1106_3164_1462_7028 +static const pciSubsystemInfo pci_ss_info_1106_3177_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3177_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3177_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3177_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3177_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3177_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3177_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3177_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3177_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3177_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3177_1849_3177 = + {0x1849, 0x3177, pci_subsys_1106_3177_1849_3177, 0}; +#undef pci_ss_info_1849_3177 +#define pci_ss_info_1849_3177 pci_ss_info_1106_3177_1849_3177 +static const pciSubsystemInfo pci_ss_info_1106_3188_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_3188_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_3188_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_3188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3188_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3189_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3189_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3189_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3189_1849_3189 = + {0x1849, 0x3189, pci_subsys_1106_3189_1849_3189, 0}; +#undef pci_ss_info_1849_3189 +#define pci_ss_info_1849_3189 pci_ss_info_1106_3189_1849_3189 +static const pciSubsystemInfo pci_ss_info_1106_3205_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3205_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3205_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3227_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3227_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3227_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3227_1106_3227 = + {0x1106, 0x3227, pci_subsys_1106_3227_1106_3227, 0}; +#undef pci_ss_info_1106_3227 +#define pci_ss_info_1106_3227 pci_ss_info_1106_3227_1106_3227 +static const pciSubsystemInfo pci_ss_info_1106_3227_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3227_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3227_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3227_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3227_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3227_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3227_1849_3227 = + {0x1849, 0x3227, pci_subsys_1106_3227_1849_3227, 0}; +#undef pci_ss_info_1849_3227 +#define pci_ss_info_1849_3227 pci_ss_info_1106_3227_1849_3227 +static const pciSubsystemInfo pci_ss_info_1106_7205_1458_d000 = + {0x1458, 0xd000, pci_subsys_1106_7205_1458_d000, 0}; +#undef pci_ss_info_1458_d000 +#define pci_ss_info_1458_d000 pci_ss_info_1106_7205_1458_d000 +static const pciSubsystemInfo pci_ss_info_1106_8598_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_8598_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_8598_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_b188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_b188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_b188_147b_1407 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_1113_2242 = + {0x1113, 0x2242, pci_subsys_1113_1216_1113_2242, 0}; +#undef pci_ss_info_1113_2242 +#define pci_ss_info_1113_2242 pci_ss_info_1113_1216_1113_2242 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_5402_1244_0f00 = + {0x1244, 0x0f00, pci_subsys_1131_5402_1244_0f00, 0}; +#undef pci_ss_info_1244_0f00 +#define pci_ss_info_1244_0f00 pci_ss_info_1131_5402_1244_0f00 +#endif +static const pciSubsystemInfo pci_ss_info_1131_7130_102b_48d0 = + {0x102b, 0x48d0, pci_subsys_1131_7130_102b_48d0, 0}; +#undef pci_ss_info_102b_48d0 +#define pci_ss_info_102b_48d0 pci_ss_info_1131_7130_102b_48d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7130_1048_226b = + {0x1048, 0x226b, pci_subsys_1131_7130_1048_226b, 0}; +#undef pci_ss_info_1048_226b +#define pci_ss_info_1048_226b pci_ss_info_1131_7130_1048_226b +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7130_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7130_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2005 = + {0x1131, 0x2005, pci_subsys_1131_7130_1131_2005, 0}; +#undef pci_ss_info_1131_2005 +#define pci_ss_info_1131_2005 pci_ss_info_1131_7130_1131_2005 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_050c = + {0x1461, 0x050c, pci_subsys_1131_7130_1461_050c, 0}; +#undef pci_ss_info_1461_050c +#define pci_ss_info_1461_050c pci_ss_info_1131_7130_1461_050c +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_10ff = + {0x1461, 0x10ff, pci_subsys_1131_7130_1461_10ff, 0}; +#undef pci_ss_info_1461_10ff +#define pci_ss_info_1461_10ff pci_ss_info_1131_7130_1461_10ff +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2108 = + {0x1461, 0x2108, pci_subsys_1131_7130_1461_2108, 0}; +#undef pci_ss_info_1461_2108 +#define pci_ss_info_1461_2108 pci_ss_info_1131_7130_1461_2108 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2115 = + {0x1461, 0x2115, pci_subsys_1131_7130_1461_2115, 0}; +#undef pci_ss_info_1461_2115 +#define pci_ss_info_1461_2115 pci_ss_info_1131_7130_1461_2115 +static const pciSubsystemInfo pci_ss_info_1131_7130_153b_1152 = + {0x153b, 0x1152, pci_subsys_1131_7130_153b_1152, 0}; +#undef pci_ss_info_153b_1152 +#define pci_ss_info_153b_1152 pci_ss_info_1131_7130_153b_1152 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7130_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7130_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c901 = + {0x185b, 0xc901, pci_subsys_1131_7130_185b_c901, 0}; +#undef pci_ss_info_185b_c901 +#define pci_ss_info_185b_c901 pci_ss_info_1131_7130_185b_c901 +static const pciSubsystemInfo pci_ss_info_1131_7130_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7130_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7130_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_0000_4091 = + {0x0000, 0x4091, pci_subsys_1131_7133_0000_4091, 0}; +#undef pci_ss_info_0000_4091 +#define pci_ss_info_0000_4091 pci_ss_info_1131_7133_0000_4091 +static const pciSubsystemInfo pci_ss_info_1131_7133_002b_11bd = + {0x002b, 0x11bd, pci_subsys_1131_7133_002b_11bd, 0}; +#undef pci_ss_info_002b_11bd +#define pci_ss_info_002b_11bd pci_ss_info_1131_7133_002b_11bd +static const pciSubsystemInfo pci_ss_info_1131_7133_1019_4cb5 = + {0x1019, 0x4cb5, pci_subsys_1131_7133_1019_4cb5, 0}; +#undef pci_ss_info_1019_4cb5 +#define pci_ss_info_1019_4cb5 pci_ss_info_1131_7133_1019_4cb5 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7133_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7133_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4843 = + {0x1043, 0x4843, pci_subsys_1131_7133_1043_4843, 0}; +#undef pci_ss_info_1043_4843 +#define pci_ss_info_1043_4843 pci_ss_info_1131_7133_1043_4843 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4845 = + {0x1043, 0x4845, pci_subsys_1131_7133_1043_4845, 0}; +#undef pci_ss_info_1043_4845 +#define pci_ss_info_1043_4845 pci_ss_info_1131_7133_1043_4845 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4862 = + {0x1043, 0x4862, pci_subsys_1131_7133_1043_4862, 0}; +#undef pci_ss_info_1043_4862 +#define pci_ss_info_1043_4862 pci_ss_info_1131_7133_1043_4862 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7133_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7133_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2018 = + {0x1131, 0x2018, pci_subsys_1131_7133_1131_2018, 0}; +#undef pci_ss_info_1131_2018 +#define pci_ss_info_1131_2018 pci_ss_info_1131_7133_1131_2018 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_4ee9 = + {0x1131, 0x4ee9, pci_subsys_1131_7133_1131_4ee9, 0}; +#undef pci_ss_info_1131_4ee9 +#define pci_ss_info_1131_4ee9 pci_ss_info_1131_7133_1131_4ee9 +static const pciSubsystemInfo pci_ss_info_1131_7133_11bd_002e = + {0x11bd, 0x002e, pci_subsys_1131_7133_11bd_002e, 0}; +#undef pci_ss_info_11bd_002e +#define pci_ss_info_11bd_002e pci_ss_info_1131_7133_11bd_002e +static const pciSubsystemInfo pci_ss_info_1131_7133_12ab_0800 = + {0x12ab, 0x0800, pci_subsys_1131_7133_12ab_0800, 0}; +#undef pci_ss_info_12ab_0800 +#define pci_ss_info_12ab_0800 pci_ss_info_1131_7133_12ab_0800 +static const pciSubsystemInfo pci_ss_info_1131_7133_1421_1370 = + {0x1421, 0x1370, pci_subsys_1131_7133_1421_1370, 0}; +#undef pci_ss_info_1421_1370 +#define pci_ss_info_1421_1370 pci_ss_info_1131_7133_1421_1370 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7330 = + {0x1435, 0x7330, pci_subsys_1131_7133_1435_7330, 0}; +#undef pci_ss_info_1435_7330 +#define pci_ss_info_1435_7330 pci_ss_info_1131_7133_1435_7330 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7350 = + {0x1435, 0x7350, pci_subsys_1131_7133_1435_7350, 0}; +#undef pci_ss_info_1435_7350 +#define pci_ss_info_1435_7350 pci_ss_info_1131_7133_1435_7350 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_1044 = + {0x1461, 0x1044, pci_subsys_1131_7133_1461_1044, 0}; +#undef pci_ss_info_1461_1044 +#define pci_ss_info_1461_1044 pci_ss_info_1131_7133_1461_1044 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_f31f = + {0x1461, 0xf31f, pci_subsys_1131_7133_1461_f31f, 0}; +#undef pci_ss_info_1461_f31f +#define pci_ss_info_1461_f31f pci_ss_info_1131_7133_1461_f31f +static const pciSubsystemInfo pci_ss_info_1131_7133_1462_6231 = + {0x1462, 0x6231, pci_subsys_1131_7133_1462_6231, 0}; +#undef pci_ss_info_1462_6231 +#define pci_ss_info_1462_6231 pci_ss_info_1131_7133_1462_6231 +static const pciSubsystemInfo pci_ss_info_1131_7133_1489_0214 = + {0x1489, 0x0214, pci_subsys_1131_7133_1489_0214, 0}; +#undef pci_ss_info_1489_0214 +#define pci_ss_info_1489_0214 pci_ss_info_1131_7133_1489_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_14c0_1212 = + {0x14c0, 0x1212, pci_subsys_1131_7133_14c0_1212, 0}; +#undef pci_ss_info_14c0_1212 +#define pci_ss_info_14c0_1212 pci_ss_info_1131_7133_14c0_1212 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1160 = + {0x153b, 0x1160, pci_subsys_1131_7133_153b_1160, 0}; +#undef pci_ss_info_153b_1160 +#define pci_ss_info_153b_1160 pci_ss_info_1131_7133_153b_1160 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1162 = + {0x153b, 0x1162, pci_subsys_1131_7133_153b_1162, 0}; +#undef pci_ss_info_153b_1162 +#define pci_ss_info_153b_1162 pci_ss_info_1131_7133_153b_1162 +static const pciSubsystemInfo pci_ss_info_1131_7133_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7133_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7133_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7133_4e42_0212 = + {0x4e42, 0x0212, pci_subsys_1131_7133_4e42_0212, 0}; +#undef pci_ss_info_4e42_0212 +#define pci_ss_info_4e42_0212 pci_ss_info_1131_7133_4e42_0212 +static const pciSubsystemInfo pci_ss_info_1131_7133_4e42_0502 = + {0x4e42, 0x0502, pci_subsys_1131_7133_4e42_0502, 0}; +#undef pci_ss_info_4e42_0502 +#define pci_ss_info_4e42_0502 pci_ss_info_1131_7133_4e42_0502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0306 = + {0x5168, 0x0306, pci_subsys_1131_7133_5168_0306, 0}; +#undef pci_ss_info_5168_0306 +#define pci_ss_info_5168_0306 pci_ss_info_1131_7133_5168_0306 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0319 = + {0x5168, 0x0319, pci_subsys_1131_7133_5168_0319, 0}; +#undef pci_ss_info_5168_0319 +#define pci_ss_info_5168_0319 pci_ss_info_1131_7133_5168_0319 +static const pciSubsystemInfo pci_ss_info_1131_7133_5456_7135 = + {0x5456, 0x7135, pci_subsys_1131_7133_5456_7135, 0}; +#undef pci_ss_info_5456_7135 +#define pci_ss_info_5456_7135 pci_ss_info_1131_7133_5456_7135 +static const pciSubsystemInfo pci_ss_info_1131_7134_1019_4cb4 = + {0x1019, 0x4cb4, pci_subsys_1131_7134_1019_4cb4, 0}; +#undef pci_ss_info_1019_4cb4 +#define pci_ss_info_1019_4cb4 pci_ss_info_1131_7134_1019_4cb4 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7134_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7134_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4840 = + {0x1043, 0x4840, pci_subsys_1131_7134_1043_4840, 0}; +#undef pci_ss_info_1043_4840 +#define pci_ss_info_1043_4840 pci_ss_info_1131_7134_1043_4840 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_2004 = + {0x1131, 0x2004, pci_subsys_1131_7134_1131_2004, 0}; +#undef pci_ss_info_1131_2004 +#define pci_ss_info_1131_2004 pci_ss_info_1131_7134_1131_2004 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_4e85 = + {0x1131, 0x4e85, pci_subsys_1131_7134_1131_4e85, 0}; +#undef pci_ss_info_1131_4e85 +#define pci_ss_info_1131_4e85 pci_ss_info_1131_7134_1131_4e85 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_6752 = + {0x1131, 0x6752, pci_subsys_1131_7134_1131_6752, 0}; +#undef pci_ss_info_1131_6752 +#define pci_ss_info_1131_6752 pci_ss_info_1131_7134_1131_6752 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_7133 = + {0x1131, 0x7133, pci_subsys_1131_7134_1131_7133, 0}; +#undef pci_ss_info_1131_7133 +#define pci_ss_info_1131_7133 pci_ss_info_1131_7134_1131_7133 +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7134_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7134_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002d = + {0x11bd, 0x002d, pci_subsys_1131_7134_11bd_002d, 0}; +#undef pci_ss_info_11bd_002d +#define pci_ss_info_11bd_002d pci_ss_info_1131_7134_11bd_002d +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_9715 = + {0x1461, 0x9715, pci_subsys_1131_7134_1461_9715, 0}; +#undef pci_ss_info_1461_9715 +#define pci_ss_info_1461_9715 pci_ss_info_1131_7134_1461_9715 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70a = + {0x1461, 0xa70a, pci_subsys_1131_7134_1461_a70a, 0}; +#undef pci_ss_info_1461_a70a +#define pci_ss_info_1461_a70a pci_ss_info_1131_7134_1461_a70a +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70b = + {0x1461, 0xa70b, pci_subsys_1131_7134_1461_a70b, 0}; +#undef pci_ss_info_1461_a70b +#define pci_ss_info_1461_a70b pci_ss_info_1131_7134_1461_a70b +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_d6ee = + {0x1461, 0xd6ee, pci_subsys_1131_7134_1461_d6ee, 0}; +#undef pci_ss_info_1461_d6ee +#define pci_ss_info_1461_d6ee pci_ss_info_1131_7134_1461_d6ee +static const pciSubsystemInfo pci_ss_info_1131_7134_1471_b7e9 = + {0x1471, 0xb7e9, pci_subsys_1131_7134_1471_b7e9, 0}; +#undef pci_ss_info_1471_b7e9 +#define pci_ss_info_1471_b7e9 pci_ss_info_1131_7134_1471_b7e9 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1142 = + {0x153b, 0x1142, pci_subsys_1131_7134_153b_1142, 0}; +#undef pci_ss_info_153b_1142 +#define pci_ss_info_153b_1142 pci_ss_info_1131_7134_153b_1142 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1143 = + {0x153b, 0x1143, pci_subsys_1131_7134_153b_1143, 0}; +#undef pci_ss_info_153b_1143 +#define pci_ss_info_153b_1143 pci_ss_info_1131_7134_153b_1143 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1158 = + {0x153b, 0x1158, pci_subsys_1131_7134_153b_1158, 0}; +#undef pci_ss_info_153b_1158 +#define pci_ss_info_153b_1158 pci_ss_info_1131_7134_153b_1158 +static const pciSubsystemInfo pci_ss_info_1131_7134_1540_9524 = + {0x1540, 0x9524, pci_subsys_1131_7134_1540_9524, 0}; +#undef pci_ss_info_1540_9524 +#define pci_ss_info_1540_9524 pci_ss_info_1131_7134_1540_9524 +static const pciSubsystemInfo pci_ss_info_1131_7134_16be_0003 = + {0x16be, 0x0003, pci_subsys_1131_7134_16be_0003, 0}; +#undef pci_ss_info_16be_0003 +#define pci_ss_info_16be_0003 pci_ss_info_1131_7134_16be_0003 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c200 = + {0x185b, 0xc200, pci_subsys_1131_7134_185b_c200, 0}; +#undef pci_ss_info_185b_c200 +#define pci_ss_info_185b_c200 pci_ss_info_1131_7134_185b_c200 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c900 = + {0x185b, 0xc900, pci_subsys_1131_7134_185b_c900, 0}; +#undef pci_ss_info_185b_c900 +#define pci_ss_info_185b_c900 pci_ss_info_1131_7134_185b_c900 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_a006 = + {0x1894, 0xa006, pci_subsys_1131_7134_1894_a006, 0}; +#undef pci_ss_info_1894_a006 +#define pci_ss_info_1894_a006 pci_ss_info_1131_7134_1894_a006 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_fe01 = + {0x1894, 0xfe01, pci_subsys_1131_7134_1894_fe01, 0}; +#undef pci_ss_info_1894_fe01 +#define pci_ss_info_1894_fe01 pci_ss_info_1131_7134_1894_fe01 +static const pciSubsystemInfo pci_ss_info_1131_7134_4e42_0138 = + {0x4e42, 0x0138, pci_subsys_1131_7134_4e42_0138, 0}; +#undef pci_ss_info_4e42_0138 +#define pci_ss_info_4e42_0138 pci_ss_info_1131_7134_4e42_0138 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_0000 = + {0x110a, 0x0000, pci_subsys_1131_7146_110a_0000, 0}; +#undef pci_ss_info_110a_0000 +#define pci_ss_info_110a_0000 pci_ss_info_1131_7146_110a_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_ffff = + {0x110a, 0xffff, pci_subsys_1131_7146_110a_ffff, 0}; +#undef pci_ss_info_110a_ffff +#define pci_ss_info_110a_ffff pci_ss_info_1131_7146_110a_ffff +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f56 = + {0x1131, 0x4f56, pci_subsys_1131_7146_1131_4f56, 0}; +#undef pci_ss_info_1131_4f56 +#define pci_ss_info_1131_4f56 pci_ss_info_1131_7146_1131_4f56 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f60 = + {0x1131, 0x4f60, pci_subsys_1131_7146_1131_4f60, 0}; +#undef pci_ss_info_1131_4f60 +#define pci_ss_info_1131_4f60 pci_ss_info_1131_7146_1131_4f60 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f61 = + {0x1131, 0x4f61, pci_subsys_1131_7146_1131_4f61, 0}; +#undef pci_ss_info_1131_4f61 +#define pci_ss_info_1131_4f61 pci_ss_info_1131_7146_1131_4f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_5f61 = + {0x1131, 0x5f61, pci_subsys_1131_7146_1131_5f61, 0}; +#undef pci_ss_info_1131_5f61 +#define pci_ss_info_1131_5f61 pci_ss_info_1131_7146_1131_5f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000f = + {0x11bd, 0x000f, pci_subsys_1131_7146_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_1131_7146_11bd_000f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_1131_7146_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_1131_7146_13c2_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0001 = + {0x13c2, 0x0001, pci_subsys_1131_7146_13c2_0001, 0}; +#undef pci_ss_info_13c2_0001 +#define pci_ss_info_13c2_0001 pci_ss_info_1131_7146_13c2_0001 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0002 = + {0x13c2, 0x0002, pci_subsys_1131_7146_13c2_0002, 0}; +#undef pci_ss_info_13c2_0002 +#define pci_ss_info_13c2_0002 pci_ss_info_1131_7146_13c2_0002 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0003 = + {0x13c2, 0x0003, pci_subsys_1131_7146_13c2_0003, 0}; +#undef pci_ss_info_13c2_0003 +#define pci_ss_info_13c2_0003 pci_ss_info_1131_7146_13c2_0003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0004 = + {0x13c2, 0x0004, pci_subsys_1131_7146_13c2_0004, 0}; +#undef pci_ss_info_13c2_0004 +#define pci_ss_info_13c2_0004 pci_ss_info_1131_7146_13c2_0004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0006 = + {0x13c2, 0x0006, pci_subsys_1131_7146_13c2_0006, 0}; +#undef pci_ss_info_13c2_0006 +#define pci_ss_info_13c2_0006 pci_ss_info_1131_7146_13c2_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0008 = + {0x13c2, 0x0008, pci_subsys_1131_7146_13c2_0008, 0}; +#undef pci_ss_info_13c2_0008 +#define pci_ss_info_13c2_0008 pci_ss_info_1131_7146_13c2_0008 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_000a = + {0x13c2, 0x000a, pci_subsys_1131_7146_13c2_000a, 0}; +#undef pci_ss_info_13c2_000a +#define pci_ss_info_13c2_000a pci_ss_info_1131_7146_13c2_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1003 = + {0x13c2, 0x1003, pci_subsys_1131_7146_13c2_1003, 0}; +#undef pci_ss_info_13c2_1003 +#define pci_ss_info_13c2_1003 pci_ss_info_1131_7146_13c2_1003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1004 = + {0x13c2, 0x1004, pci_subsys_1131_7146_13c2_1004, 0}; +#undef pci_ss_info_13c2_1004 +#define pci_ss_info_13c2_1004 pci_ss_info_1131_7146_13c2_1004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1005 = + {0x13c2, 0x1005, pci_subsys_1131_7146_13c2_1005, 0}; +#undef pci_ss_info_13c2_1005 +#define pci_ss_info_13c2_1005 pci_ss_info_1131_7146_13c2_1005 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100c = + {0x13c2, 0x100c, pci_subsys_1131_7146_13c2_100c, 0}; +#undef pci_ss_info_13c2_100c +#define pci_ss_info_13c2_100c pci_ss_info_1131_7146_13c2_100c +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100f = + {0x13c2, 0x100f, pci_subsys_1131_7146_13c2_100f, 0}; +#undef pci_ss_info_13c2_100f +#define pci_ss_info_13c2_100f pci_ss_info_1131_7146_13c2_100f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1011 = + {0x13c2, 0x1011, pci_subsys_1131_7146_13c2_1011, 0}; +#undef pci_ss_info_13c2_1011 +#define pci_ss_info_13c2_1011 pci_ss_info_1131_7146_13c2_1011 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1013 = + {0x13c2, 0x1013, pci_subsys_1131_7146_13c2_1013, 0}; +#undef pci_ss_info_13c2_1013 +#define pci_ss_info_13c2_1013 pci_ss_info_1131_7146_13c2_1013 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1016 = + {0x13c2, 0x1016, pci_subsys_1131_7146_13c2_1016, 0}; +#undef pci_ss_info_13c2_1016 +#define pci_ss_info_13c2_1016 pci_ss_info_1131_7146_13c2_1016 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1102 = + {0x13c2, 0x1102, pci_subsys_1131_7146_13c2_1102, 0}; +#undef pci_ss_info_13c2_1102 +#define pci_ss_info_13c2_1102 pci_ss_info_1131_7146_13c2_1102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e010_110a_0021 = + {0x110a, 0x0021, pci_subsys_1133_e010_110a_0021, 0}; +#undef pci_ss_info_110a_0021 +#define pci_ss_info_110a_0021 pci_ss_info_1133_e010_110a_0021 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_1300 = + {0x1133, 0x1300, pci_subsys_1133_e013_1133_1300, 0}; +#undef pci_ss_info_1133_1300 +#define pci_ss_info_1133_1300 pci_ss_info_1133_e013_1133_1300 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_e013 = + {0x1133, 0xe013, pci_subsys_1133_e013_1133_e013, 0}; +#undef pci_ss_info_1133_e013 +#define pci_ss_info_1133_e013 pci_ss_info_1133_e013_1133_e013 +static const pciSubsystemInfo pci_ss_info_1133_e015_1133_e015 = + {0x1133, 0xe015, pci_subsys_1133_e015_1133_e015, 0}; +#undef pci_ss_info_1133_e015 +#define pci_ss_info_1133_e015 pci_ss_info_1133_e015_1133_e015 +static const pciSubsystemInfo pci_ss_info_1133_e017_1133_e017 = + {0x1133, 0xe017, pci_subsys_1133_e017_1133_e017, 0}; +#undef pci_ss_info_1133_e017 +#define pci_ss_info_1133_e017 pci_ss_info_1133_e017_1133_e017 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_1800 = + {0x1133, 0x1800, pci_subsys_1133_e018_1133_1800, 0}; +#undef pci_ss_info_1133_1800 +#define pci_ss_info_1133_1800 pci_ss_info_1133_e018_1133_1800 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_e018 = + {0x1133, 0xe018, pci_subsys_1133_e018_1133_e018, 0}; +#undef pci_ss_info_1133_e018 +#define pci_ss_info_1133_e018 pci_ss_info_1133_e018_1133_e018 +static const pciSubsystemInfo pci_ss_info_1133_e019_1133_e019 = + {0x1133, 0xe019, pci_subsys_1133_e019_1133_e019, 0}; +#undef pci_ss_info_1133_e019 +#define pci_ss_info_1133_e019 pci_ss_info_1133_e019_1133_e019 +static const pciSubsystemInfo pci_ss_info_1133_e01b_1133_e01b = + {0x1133, 0xe01b, pci_subsys_1133_e01b_1133_e01b, 0}; +#undef pci_ss_info_1133_e01b +#define pci_ss_info_1133_e01b pci_ss_info_1133_e01b_1133_e01b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c01 = + {0x1133, 0x1c01, pci_subsys_1133_e01c_1133_1c01, 0}; +#undef pci_ss_info_1133_1c01 +#define pci_ss_info_1133_1c01 pci_ss_info_1133_e01c_1133_1c01 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c02 = + {0x1133, 0x1c02, pci_subsys_1133_e01c_1133_1c02, 0}; +#undef pci_ss_info_1133_1c02 +#define pci_ss_info_1133_1c02 pci_ss_info_1133_e01c_1133_1c02 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c03 = + {0x1133, 0x1c03, pci_subsys_1133_e01c_1133_1c03, 0}; +#undef pci_ss_info_1133_1c03 +#define pci_ss_info_1133_1c03 pci_ss_info_1133_e01c_1133_1c03 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c04 = + {0x1133, 0x1c04, pci_subsys_1133_e01c_1133_1c04, 0}; +#undef pci_ss_info_1133_1c04 +#define pci_ss_info_1133_1c04 pci_ss_info_1133_e01c_1133_1c04 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c05 = + {0x1133, 0x1c05, pci_subsys_1133_e01c_1133_1c05, 0}; +#undef pci_ss_info_1133_1c05 +#define pci_ss_info_1133_1c05 pci_ss_info_1133_e01c_1133_1c05 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c06 = + {0x1133, 0x1c06, pci_subsys_1133_e01c_1133_1c06, 0}; +#undef pci_ss_info_1133_1c06 +#define pci_ss_info_1133_1c06 pci_ss_info_1133_e01c_1133_1c06 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c07 = + {0x1133, 0x1c07, pci_subsys_1133_e01c_1133_1c07, 0}; +#undef pci_ss_info_1133_1c07 +#define pci_ss_info_1133_1c07 pci_ss_info_1133_e01c_1133_1c07 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c08 = + {0x1133, 0x1c08, pci_subsys_1133_e01c_1133_1c08, 0}; +#undef pci_ss_info_1133_1c08 +#define pci_ss_info_1133_1c08 pci_ss_info_1133_e01c_1133_1c08 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c09 = + {0x1133, 0x1c09, pci_subsys_1133_e01c_1133_1c09, 0}; +#undef pci_ss_info_1133_1c09 +#define pci_ss_info_1133_1c09 pci_ss_info_1133_e01c_1133_1c09 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0a = + {0x1133, 0x1c0a, pci_subsys_1133_e01c_1133_1c0a, 0}; +#undef pci_ss_info_1133_1c0a +#define pci_ss_info_1133_1c0a pci_ss_info_1133_e01c_1133_1c0a +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0b = + {0x1133, 0x1c0b, pci_subsys_1133_e01c_1133_1c0b, 0}; +#undef pci_ss_info_1133_1c0b +#define pci_ss_info_1133_1c0b pci_ss_info_1133_e01c_1133_1c0b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0c = + {0x1133, 0x1c0c, pci_subsys_1133_e01c_1133_1c0c, 0}; +#undef pci_ss_info_1133_1c0c +#define pci_ss_info_1133_1c0c pci_ss_info_1133_e01c_1133_1c0c +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_2400 = + {0x1133, 0x2400, pci_subsys_1133_e024_1133_2400, 0}; +#undef pci_ss_info_1133_2400 +#define pci_ss_info_1133_2400 pci_ss_info_1133_e024_1133_2400 +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_e024 = + {0x1133, 0xe024, pci_subsys_1133_e024_1133_e024, 0}; +#undef pci_ss_info_1133_e024 +#define pci_ss_info_1133_e024 pci_ss_info_1133_e024_1133_e024 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_2800 = + {0x1133, 0x2800, pci_subsys_1133_e028_1133_2800, 0}; +#undef pci_ss_info_1133_2800 +#define pci_ss_info_1133_2800 pci_ss_info_1133_e028_1133_2800 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_e028 = + {0x1133, 0xe028, pci_subsys_1133_e028_1133_e028, 0}; +#undef pci_ss_info_1133_e028 +#define pci_ss_info_1133_e028 pci_ss_info_1133_e028_1133_e028 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2971 = + {0x1259, 0x2971, pci_subsys_1148_4300_1259_2971, 0}; +#undef pci_ss_info_1259_2971 +#define pci_ss_info_1259_2971 pci_ss_info_1148_4300_1259_2971 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2973 = + {0x1259, 0x2973, pci_subsys_1148_4300_1259_2973, 0}; +#undef pci_ss_info_1259_2973 +#define pci_ss_info_1259_2973 pci_ss_info_1148_4300_1259_2973 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2974 = + {0x1259, 0x2974, pci_subsys_1148_4300_1259_2974, 0}; +#undef pci_ss_info_1259_2974 +#define pci_ss_info_1259_2974 pci_ss_info_1148_4300_1259_2974 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2976 = + {0x1259, 0x2976, pci_subsys_1148_4300_1259_2976, 0}; +#undef pci_ss_info_1259_2976 +#define pci_ss_info_1259_2976 pci_ss_info_1148_4300_1259_2976 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0121 = + {0x1148, 0x0121, pci_subsys_1148_4320_1148_0121, 0}; +#undef pci_ss_info_1148_0121 +#define pci_ss_info_1148_0121 pci_ss_info_1148_4320_1148_0121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0221 = + {0x1148, 0x0221, pci_subsys_1148_4320_1148_0221, 0}; +#undef pci_ss_info_1148_0221 +#define pci_ss_info_1148_0221 pci_ss_info_1148_4320_1148_0221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0321 = + {0x1148, 0x0321, pci_subsys_1148_4320_1148_0321, 0}; +#undef pci_ss_info_1148_0321 +#define pci_ss_info_1148_0321 pci_ss_info_1148_4320_1148_0321 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0421 = + {0x1148, 0x0421, pci_subsys_1148_4320_1148_0421, 0}; +#undef pci_ss_info_1148_0421 +#define pci_ss_info_1148_0421 pci_ss_info_1148_4320_1148_0421 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0621 = + {0x1148, 0x0621, pci_subsys_1148_4320_1148_0621, 0}; +#undef pci_ss_info_1148_0621 +#define pci_ss_info_1148_0621 pci_ss_info_1148_4320_1148_0621 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0721 = + {0x1148, 0x0721, pci_subsys_1148_4320_1148_0721, 0}; +#undef pci_ss_info_1148_0721 +#define pci_ss_info_1148_0721 pci_ss_info_1148_4320_1148_0721 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0821 = + {0x1148, 0x0821, pci_subsys_1148_4320_1148_0821, 0}; +#undef pci_ss_info_1148_0821 +#define pci_ss_info_1148_0821 pci_ss_info_1148_4320_1148_0821 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0921 = + {0x1148, 0x0921, pci_subsys_1148_4320_1148_0921, 0}; +#undef pci_ss_info_1148_0921 +#define pci_ss_info_1148_0921 pci_ss_info_1148_4320_1148_0921 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1121 = + {0x1148, 0x1121, pci_subsys_1148_4320_1148_1121, 0}; +#undef pci_ss_info_1148_1121 +#define pci_ss_info_1148_1121 pci_ss_info_1148_4320_1148_1121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1221 = + {0x1148, 0x1221, pci_subsys_1148_4320_1148_1221, 0}; +#undef pci_ss_info_1148_1221 +#define pci_ss_info_1148_1221 pci_ss_info_1148_4320_1148_1221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_3221 = + {0x1148, 0x3221, pci_subsys_1148_4320_1148_3221, 0}; +#undef pci_ss_info_1148_3221 +#define pci_ss_info_1148_3221 pci_ss_info_1148_4320_1148_3221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2100 = + {0x1148, 0x2100, pci_subsys_1148_9e00_1148_2100, 0}; +#undef pci_ss_info_1148_2100 +#define pci_ss_info_1148_2100 pci_ss_info_1148_9e00_1148_2100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_21d0 = + {0x1148, 0x21d0, pci_subsys_1148_9e00_1148_21d0, 0}; +#undef pci_ss_info_1148_21d0 +#define pci_ss_info_1148_21d0 pci_ss_info_1148_9e00_1148_21d0 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2200 = + {0x1148, 0x2200, pci_subsys_1148_9e00_1148_2200, 0}; +#undef pci_ss_info_1148_2200 +#define pci_ss_info_1148_2200 pci_ss_info_1148_9e00_1148_2200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8100 = + {0x1148, 0x8100, pci_subsys_1148_9e00_1148_8100, 0}; +#undef pci_ss_info_1148_8100 +#define pci_ss_info_1148_8100 pci_ss_info_1148_9e00_1148_8100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8200 = + {0x1148, 0x8200, pci_subsys_1148_9e00_1148_8200, 0}; +#undef pci_ss_info_1148_8200 +#define pci_ss_info_1148_8200 pci_ss_info_1148_9e00_1148_8200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9100 = + {0x1148, 0x9100, pci_subsys_1148_9e00_1148_9100, 0}; +#undef pci_ss_info_1148_9100 +#define pci_ss_info_1148_9100 pci_ss_info_1148_9e00_1148_9100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9200 = + {0x1148, 0x9200, pci_subsys_1148_9e00_1148_9200, 0}; +#undef pci_ss_info_1148_9200 +#define pci_ss_info_1148_9200 pci_ss_info_1148_9e00_1148_9200 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0003_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0003_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0201_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0201_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0201_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0203_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0203_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0203_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0212_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0212_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0212_4c53_1080 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_c134 = + {0x1028, 0xc134, pci_subsys_1166_0213_1028_c134, 0}; +#undef pci_ss_info_1028_c134 +#define pci_ss_info_1028_c134 pci_ss_info_1166_0213_1028_c134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0213_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0213_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0213_1734_1012 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0217_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0217_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0217_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0220_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0220_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0220_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0221_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0221_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0221_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0227_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0227_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0227_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0230_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0230_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0230_4c53_1080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0601_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0601_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0601_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_060a_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_060a_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_060a_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8013 = + {0x117c, 0x8013, pci_subsys_117c_0030_117c_8013, 0}; +#undef pci_ss_info_117c_8013 +#define pci_ss_info_117c_8013 pci_ss_info_117c_0030_117c_8013 +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8014 = + {0x117c, 0x8014, pci_subsys_117c_0030_117c_8014, 0}; +#undef pci_ss_info_117c_8014 +#define pci_ss_info_117c_8014 pci_ss_info_117c_0030_117c_8014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0476_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0476_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0476_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0476_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1987 = + {0x1043, 0x1987, pci_subsys_1180_0476_1043_1987, 0}; +#undef pci_ss_info_1043_1987 +#define pci_ss_info_1043_1987 pci_ss_info_1180_0476_1043_1987 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_14ef_0220 = + {0x14ef, 0x0220, pci_subsys_1180_0476_14ef_0220, 0}; +#undef pci_ss_info_14ef_0220 +#define pci_ss_info_14ef_0220 pci_ss_info_1180_0476_14ef_0220 +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0522_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0522_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0522_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0552_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0552_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0552_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0592_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0592_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0592_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0556 = + {0x1014, 0x0556, pci_subsys_1180_0822_1014_0556, 0}; +#undef pci_ss_info_1014_0556 +#define pci_ss_info_1014_0556 pci_ss_info_1180_0822_1014_0556 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0822_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0822_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_01a2 = + {0x1028, 0x01a2, pci_subsys_1180_0822_1028_01a2, 0}; +#undef pci_ss_info_1028_01a2 +#define pci_ss_info_1028_01a2 pci_ss_info_1180_0822_1028_01a2 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0822_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0822_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0822_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0852_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0852_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0852_1043_1967 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1303 = + {0x1186, 0x1303, pci_subsys_1186_1300_1186_1303, 0}; +#undef pci_ss_info_1186_1303 +#define pci_ss_info_1186_1303 pci_ss_info_1186_1300_1186_1303 +static const pciSubsystemInfo pci_ss_info_1186_4c00_1186_4c00 = + {0x1186, 0x4c00, pci_subsys_1186_4c00_1186_4c00, 0}; +#undef pci_ss_info_1186_4c00 +#define pci_ss_info_1186_4c00 pci_ss_info_1186_4c00_1186_4c00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_1faa_1385_4e00 = + {0x1385, 0x4e00, pci_subsys_11ab_1faa_1385_4e00, 0}; +#undef pci_ss_info_1385_4e00 +#define pci_ss_info_1385_4e00 pci_ss_info_11ab_1faa_1385_4e00 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_0f38 = + {0x1019, 0x0f38, pci_subsys_11ab_4320_1019_0f38, 0}; +#undef pci_ss_info_1019_0f38 +#define pci_ss_info_1019_0f38 pci_ss_info_11ab_4320_1019_0f38 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_8001 = + {0x1019, 0x8001, pci_subsys_11ab_4320_1019_8001, 0}; +#undef pci_ss_info_1019_8001 +#define pci_ss_info_1019_8001 pci_ss_info_11ab_4320_1019_8001 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_173c = + {0x1043, 0x173c, pci_subsys_11ab_4320_1043_173c, 0}; +#undef pci_ss_info_1043_173c +#define pci_ss_info_1043_173c pci_ss_info_11ab_4320_1043_173c +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_811a = + {0x1043, 0x811a, pci_subsys_11ab_4320_1043_811a, 0}; +#undef pci_ss_info_1043_811a +#define pci_ss_info_1043_811a pci_ss_info_11ab_4320_1043_811a +static const pciSubsystemInfo pci_ss_info_11ab_4320_105b_0c19 = + {0x105b, 0x0c19, pci_subsys_11ab_4320_105b_0c19, 0}; +#undef pci_ss_info_105b_0c19 +#define pci_ss_info_105b_0c19 pci_ss_info_11ab_4320_105b_0c19 +static const pciSubsystemInfo pci_ss_info_11ab_4320_10b8_b452 = + {0x10b8, 0xb452, pci_subsys_11ab_4320_10b8_b452, 0}; +#undef pci_ss_info_10b8_b452 +#define pci_ss_info_10b8_b452 pci_ss_info_11ab_4320_10b8_b452 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0121 = + {0x11ab, 0x0121, pci_subsys_11ab_4320_11ab_0121, 0}; +#undef pci_ss_info_11ab_0121 +#define pci_ss_info_11ab_0121 pci_ss_info_11ab_4320_11ab_0121 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0321 = + {0x11ab, 0x0321, pci_subsys_11ab_4320_11ab_0321, 0}; +#undef pci_ss_info_11ab_0321 +#define pci_ss_info_11ab_0321 pci_ss_info_11ab_4320_11ab_0321 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_1021 = + {0x11ab, 0x1021, pci_subsys_11ab_4320_11ab_1021, 0}; +#undef pci_ss_info_11ab_1021 +#define pci_ss_info_11ab_1021 pci_ss_info_11ab_4320_11ab_1021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4320_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4320_11ab_5021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_9521 = + {0x11ab, 0x9521, pci_subsys_11ab_4320_11ab_9521, 0}; +#undef pci_ss_info_11ab_9521 +#define pci_ss_info_11ab_9521 pci_ss_info_11ab_4320_11ab_9521 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4320_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4320_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4320_147b_1406 = + {0x147b, 0x1406, pci_subsys_11ab_4320_147b_1406, 0}; +#undef pci_ss_info_147b_1406 +#define pci_ss_info_147b_1406 pci_ss_info_11ab_4320_147b_1406 +static const pciSubsystemInfo pci_ss_info_11ab_4320_15d4_0047 = + {0x15d4, 0x0047, pci_subsys_11ab_4320_15d4_0047, 0}; +#undef pci_ss_info_15d4_0047 +#define pci_ss_info_15d4_0047 pci_ss_info_11ab_4320_15d4_0047 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1695_9025 = + {0x1695, 0x9025, pci_subsys_11ab_4320_1695_9025, 0}; +#undef pci_ss_info_1695_9025 +#define pci_ss_info_1695_9025 pci_ss_info_11ab_4320_1695_9025 +static const pciSubsystemInfo pci_ss_info_11ab_4320_17f2_1c03 = + {0x17f2, 0x1c03, pci_subsys_11ab_4320_17f2_1c03, 0}; +#undef pci_ss_info_17f2_1c03 +#define pci_ss_info_17f2_1c03 pci_ss_info_11ab_4320_17f2_1c03 +static const pciSubsystemInfo pci_ss_info_11ab_4320_270f_2803 = + {0x270f, 0x2803, pci_subsys_11ab_4320_270f_2803, 0}; +#undef pci_ss_info_270f_2803 +#define pci_ss_info_270f_2803 pci_ss_info_11ab_4320_270f_2803 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4350_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4350_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4350_11ab_3521 = + {0x11ab, 0x3521, pci_subsys_11ab_4350_11ab_3521, 0}; +#undef pci_ss_info_11ab_3521 +#define pci_ss_info_11ab_3521 pci_ss_info_11ab_4350_11ab_3521 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4350_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4350_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4350_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4350_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4350_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4350_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4350_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4350_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4350_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4350_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4350_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4350_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4350_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4350_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4350_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4350_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4350_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4350_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4350_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4350_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4350_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4350_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4350_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4350_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4351_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4351_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4351_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4351_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4351_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4351_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4351_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4351_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4351_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4351_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4351_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4351_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4351_11ab_3621 = + {0x11ab, 0x3621, pci_subsys_11ab_4351_11ab_3621, 0}; +#undef pci_ss_info_11ab_3621 +#define pci_ss_info_11ab_3621 pci_ss_info_11ab_4351_11ab_3621 +static const pciSubsystemInfo pci_ss_info_11ab_4351_13d1_ac12 = + {0x13d1, 0xac12, pci_subsys_11ab_4351_13d1_ac12, 0}; +#undef pci_ss_info_13d1_ac12 +#define pci_ss_info_13d1_ac12 pci_ss_info_11ab_4351_13d1_ac12 +static const pciSubsystemInfo pci_ss_info_11ab_4351_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4351_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4351_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4351_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4351_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4351_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4351_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4351_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4351_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4351_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4351_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4351_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4351_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4351_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4351_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4351_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4351_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4351_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4351_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4351_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4351_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4351_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4351_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4351_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4351_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4351_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4351_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1043_8134 = + {0x1043, 0x8134, pci_subsys_11ab_4360_1043_8134, 0}; +#undef pci_ss_info_1043_8134 +#define pci_ss_info_1043_8134 pci_ss_info_11ab_4360_1043_8134 +static const pciSubsystemInfo pci_ss_info_11ab_4360_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4360_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4360_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4360_11ab_5221 = + {0x11ab, 0x5221, pci_subsys_11ab_4360_11ab_5221, 0}; +#undef pci_ss_info_11ab_5221 +#define pci_ss_info_11ab_5221 pci_ss_info_11ab_4360_11ab_5221 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4360_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4360_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1462_052c = + {0x1462, 0x052c, pci_subsys_11ab_4360_1462_052c, 0}; +#undef pci_ss_info_1462_052c +#define pci_ss_info_1462_052c pci_ss_info_11ab_4360_1462_052c +static const pciSubsystemInfo pci_ss_info_11ab_4360_1849_8052 = + {0x1849, 0x8052, pci_subsys_11ab_4360_1849_8052, 0}; +#undef pci_ss_info_1849_8052 +#define pci_ss_info_1849_8052 pci_ss_info_11ab_4360_1849_8052 +static const pciSubsystemInfo pci_ss_info_11ab_4360_a0a0_0509 = + {0xa0a0, 0x0509, pci_subsys_11ab_4360_a0a0_0509, 0}; +#undef pci_ss_info_a0a0_0509 +#define pci_ss_info_a0a0_0509 pci_ss_info_11ab_4360_a0a0_0509 +static const pciSubsystemInfo pci_ss_info_11ab_4361_107b_3015 = + {0x107b, 0x3015, pci_subsys_11ab_4361_107b_3015, 0}; +#undef pci_ss_info_107b_3015 +#define pci_ss_info_107b_3015 pci_ss_info_11ab_4361_107b_3015 +static const pciSubsystemInfo pci_ss_info_11ab_4361_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4361_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4361_11ab_5021 +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3063 = + {0x8086, 0x3063, pci_subsys_11ab_4361_8086_3063, 0}; +#undef pci_ss_info_8086_3063 +#define pci_ss_info_8086_3063 pci_ss_info_11ab_4361_8086_3063 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3439 = + {0x8086, 0x3439, pci_subsys_11ab_4361_8086_3439, 0}; +#undef pci_ss_info_8086_3439 +#define pci_ss_info_8086_3439 pci_ss_info_11ab_4361_8086_3439 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4362_103c_2a0d = + {0x103c, 0x2a0d, pci_subsys_11ab_4362_103c_2a0d, 0}; +#undef pci_ss_info_103c_2a0d +#define pci_ss_info_103c_2a0d pci_ss_info_11ab_4362_103c_2a0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_4362_1043_8142 = + {0x1043, 0x8142, pci_subsys_11ab_4362_1043_8142, 0}; +#undef pci_ss_info_1043_8142 +#define pci_ss_info_1043_8142 pci_ss_info_11ab_4362_1043_8142 +static const pciSubsystemInfo pci_ss_info_11ab_4362_109f_3197 = + {0x109f, 0x3197, pci_subsys_11ab_4362_109f_3197, 0}; +#undef pci_ss_info_109f_3197 +#define pci_ss_info_109f_3197 pci_ss_info_11ab_4362_109f_3197 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4362_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4362_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10fd_a430 = + {0x10fd, 0xa430, pci_subsys_11ab_4362_10fd_a430, 0}; +#undef pci_ss_info_10fd_a430 +#define pci_ss_info_10fd_a430 pci_ss_info_11ab_4362_10fd_a430 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4362_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4362_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4362_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4362_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4362_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4362_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4362_11ab_5321 = + {0x11ab, 0x5321, pci_subsys_11ab_4362_11ab_5321, 0}; +#undef pci_ss_info_11ab_5321 +#define pci_ss_info_11ab_5321 pci_ss_info_11ab_4362_11ab_5321 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c240 = + {0x1297, 0xc240, pci_subsys_11ab_4362_1297_c240, 0}; +#undef pci_ss_info_1297_c240 +#define pci_ss_info_1297_c240 pci_ss_info_11ab_4362_1297_c240 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c241 = + {0x1297, 0xc241, pci_subsys_11ab_4362_1297_c241, 0}; +#undef pci_ss_info_1297_c241 +#define pci_ss_info_1297_c241 pci_ss_info_11ab_4362_1297_c241 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c242 = + {0x1297, 0xc242, pci_subsys_11ab_4362_1297_c242, 0}; +#undef pci_ss_info_1297_c242 +#define pci_ss_info_1297_c242 pci_ss_info_11ab_4362_1297_c242 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c243 = + {0x1297, 0xc243, pci_subsys_11ab_4362_1297_c243, 0}; +#undef pci_ss_info_1297_c243 +#define pci_ss_info_1297_c243 pci_ss_info_11ab_4362_1297_c243 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c244 = + {0x1297, 0xc244, pci_subsys_11ab_4362_1297_c244, 0}; +#undef pci_ss_info_1297_c244 +#define pci_ss_info_1297_c244 pci_ss_info_11ab_4362_1297_c244 +static const pciSubsystemInfo pci_ss_info_11ab_4362_13d1_ac11 = + {0x13d1, 0xac11, pci_subsys_11ab_4362_13d1_ac11, 0}; +#undef pci_ss_info_13d1_ac11 +#define pci_ss_info_13d1_ac11 pci_ss_info_11ab_4362_13d1_ac11 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4362_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4362_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1462_058c = + {0x1462, 0x058c, pci_subsys_11ab_4362_1462_058c, 0}; +#undef pci_ss_info_1462_058c +#define pci_ss_info_1462_058c pci_ss_info_11ab_4362_1462_058c +static const pciSubsystemInfo pci_ss_info_11ab_4362_14c0_0012 = + {0x14c0, 0x0012, pci_subsys_11ab_4362_14c0_0012, 0}; +#undef pci_ss_info_14c0_0012 +#define pci_ss_info_14c0_0012 pci_ss_info_11ab_4362_14c0_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1558_04a0 = + {0x1558, 0x04a0, pci_subsys_11ab_4362_1558_04a0, 0}; +#undef pci_ss_info_1558_04a0 +#define pci_ss_info_1558_04a0 pci_ss_info_11ab_4362_1558_04a0 +static const pciSubsystemInfo pci_ss_info_11ab_4362_15bd_1003 = + {0x15bd, 0x1003, pci_subsys_11ab_4362_15bd_1003, 0}; +#undef pci_ss_info_15bd_1003 +#define pci_ss_info_15bd_1003 pci_ss_info_11ab_4362_15bd_1003 +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203c = + {0x161f, 0x203c, pci_subsys_11ab_4362_161f_203c, 0}; +#undef pci_ss_info_161f_203c +#define pci_ss_info_161f_203c pci_ss_info_11ab_4362_161f_203c +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4362_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4362_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1695_9029 = + {0x1695, 0x9029, pci_subsys_11ab_4362_1695_9029, 0}; +#undef pci_ss_info_1695_9029 +#define pci_ss_info_1695_9029 pci_ss_info_11ab_4362_1695_9029 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17f2_2c08 = + {0x17f2, 0x2c08, pci_subsys_11ab_4362_17f2_2c08, 0}; +#undef pci_ss_info_17f2_2c08 +#define pci_ss_info_17f2_2c08 pci_ss_info_11ab_4362_17f2_2c08 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17ff_0585 = + {0x17ff, 0x0585, pci_subsys_11ab_4362_17ff_0585, 0}; +#undef pci_ss_info_17ff_0585 +#define pci_ss_info_17ff_0585 pci_ss_info_11ab_4362_17ff_0585 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1849_8053 = + {0x1849, 0x8053, pci_subsys_11ab_4362_1849_8053, 0}; +#undef pci_ss_info_1849_8053 +#define pci_ss_info_1849_8053 pci_ss_info_11ab_4362_1849_8053 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000b = + {0x1854, 0x000b, pci_subsys_11ab_4362_1854_000b, 0}; +#undef pci_ss_info_1854_000b +#define pci_ss_info_1854_000b pci_ss_info_11ab_4362_1854_000b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000c = + {0x1854, 0x000c, pci_subsys_11ab_4362_1854_000c, 0}; +#undef pci_ss_info_1854_000c +#define pci_ss_info_1854_000c pci_ss_info_11ab_4362_1854_000c +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0010 = + {0x1854, 0x0010, pci_subsys_11ab_4362_1854_0010, 0}; +#undef pci_ss_info_1854_0010 +#define pci_ss_info_1854_0010 pci_ss_info_11ab_4362_1854_0010 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0013 = + {0x1854, 0x0013, pci_subsys_11ab_4362_1854_0013, 0}; +#undef pci_ss_info_1854_0013 +#define pci_ss_info_1854_0013 pci_ss_info_11ab_4362_1854_0013 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0014 = + {0x1854, 0x0014, pci_subsys_11ab_4362_1854_0014, 0}; +#undef pci_ss_info_1854_0014 +#define pci_ss_info_1854_0014 pci_ss_info_11ab_4362_1854_0014 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0015 = + {0x1854, 0x0015, pci_subsys_11ab_4362_1854_0015, 0}; +#undef pci_ss_info_1854_0015 +#define pci_ss_info_1854_0015 pci_ss_info_11ab_4362_1854_0015 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001a = + {0x1854, 0x001a, pci_subsys_11ab_4362_1854_001a, 0}; +#undef pci_ss_info_1854_001a +#define pci_ss_info_1854_001a pci_ss_info_11ab_4362_1854_001a +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001b = + {0x1854, 0x001b, pci_subsys_11ab_4362_1854_001b, 0}; +#undef pci_ss_info_1854_001b +#define pci_ss_info_1854_001b pci_ss_info_11ab_4362_1854_001b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001d = + {0x1854, 0x001d, pci_subsys_11ab_4362_1854_001d, 0}; +#undef pci_ss_info_1854_001d +#define pci_ss_info_1854_001d pci_ss_info_11ab_4362_1854_001d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001f = + {0x1854, 0x001f, pci_subsys_11ab_4362_1854_001f, 0}; +#undef pci_ss_info_1854_001f +#define pci_ss_info_1854_001f pci_ss_info_11ab_4362_1854_001f +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0021 = + {0x1854, 0x0021, pci_subsys_11ab_4362_1854_0021, 0}; +#undef pci_ss_info_1854_0021 +#define pci_ss_info_1854_0021 pci_ss_info_11ab_4362_1854_0021 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0022 = + {0x1854, 0x0022, pci_subsys_11ab_4362_1854_0022, 0}; +#undef pci_ss_info_1854_0022 +#define pci_ss_info_1854_0022 pci_ss_info_11ab_4362_1854_0022 +static const pciSubsystemInfo pci_ss_info_11ab_4362_270f_2801 = + {0x270f, 0x2801, pci_subsys_11ab_4362_270f_2801, 0}; +#undef pci_ss_info_270f_2801 +#define pci_ss_info_270f_2801 pci_ss_info_11ab_4362_270f_2801 +static const pciSubsystemInfo pci_ss_info_11ab_4362_a0a0_0506 = + {0xa0a0, 0x0506, pci_subsys_11ab_4362_a0a0_0506, 0}; +#undef pci_ss_info_a0a0_0506 +#define pci_ss_info_a0a0_0506 pci_ss_info_11ab_4362_a0a0_0506 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2203 = + {0x8086, 0x2203, pci_subsys_11c1_0445_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_11c1_0445_8086_2203 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2204 = + {0x8086, 0x2204, pci_subsys_11c1_0445_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_11c1_0445_8086_2204 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_1033_80a8 = + {0x1033, 0x80a8, pci_subsys_11c1_0450_1033_80a8, 0}; +#undef pci_ss_info_1033_80a8 +#define pci_ss_info_1033_80a8 pci_ss_info_11c1_0450_1033_80a8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_1468_0450 = + {0x1468, 0x0450, pci_subsys_11c1_0450_1468_0450, 0}; +#undef pci_ss_info_1468_0450 +#define pci_ss_info_1468_0450 pci_ss_info_11c1_0450_1468_0450 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_4005_144f = + {0x4005, 0x144f, pci_subsys_11c1_0450_4005_144f, 0}; +#undef pci_ss_info_4005_144f +#define pci_ss_info_4005_144f pci_ss_info_11c1_0450_4005_144f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_5811_8086_524c = + {0x8086, 0x524c, pci_subsys_11c1_5811_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_11c1_5811_8086_524c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +static const pciSubsystemInfo pci_ss_info_11c1_8110_12d9_000c = + {0x12d9, 0x000c, pci_subsys_11c1_8110_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_11c1_8110_12d9_000c +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab12 = + {0x11c1, 0xab12, pci_subsys_11c1_ab11_11c1_ab12, 0}; +#undef pci_ss_info_11c1_ab12 +#define pci_ss_info_11c1_ab12 pci_ss_info_11c1_ab11_11c1_ab12 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab13 = + {0x11c1, 0xab13, pci_subsys_11c1_ab11_11c1_ab13, 0}; +#undef pci_ss_info_11c1_ab13 +#define pci_ss_info_11c1_ab13 pci_ss_info_11c1_ab11_11c1_ab13 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab15 = + {0x11c1, 0xab15, pci_subsys_11c1_ab11_11c1_ab15, 0}; +#undef pci_ss_info_11c1_ab15 +#define pci_ss_info_11c1_ab15 pci_ss_info_11c1_ab11_11c1_ab15 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab16 = + {0x11c1, 0xab16, pci_subsys_11c1_ab11_11c1_ab16, 0}; +#undef pci_ss_info_11c1_ab16 +#define pci_ss_info_11c1_ab16 pci_ss_info_11c1_ab11_11c1_ab16 +static const pciSubsystemInfo pci_ss_info_11c1_ab30_14cd_2012 = + {0x14cd, 0x2012, pci_subsys_11c1_ab30_14cd_2012, 0}; +#undef pci_ss_info_14cd_2012 +#define pci_ss_info_14cd_2012 pci_ss_info_11c1_ab30_14cd_2012 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_12f8_8a02 = + {0x12f8, 0x8a02, pci_subsys_11de_6057_12f8_8a02, 0}; +#undef pci_ss_info_12f8_8a02 +#define pci_ss_info_12f8_8a02 pci_ss_info_11de_6057_12f8_8a02 +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +static const pciSubsystemInfo pci_ss_info_11de_6120_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_11de_6120_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_11de_6120_13c2_0000 +static const pciSubsystemInfo pci_ss_info_11de_6120_1de1_9fff = + {0x1de1, 0x9fff, pci_subsys_11de_6120_1de1_9fff, 0}; +#undef pci_ss_info_1de1_9fff +#define pci_ss_info_1de1_9fff pci_ss_info_11de_6120_1de1_9fff +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1014_020c = + {0x1014, 0x020c, pci_subsys_1217_6972_1014_020c, 0}; +#undef pci_ss_info_1014_020c +#define pci_ss_info_1014_020c pci_ss_info_1217_6972_1014_020c +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7110_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7110_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7110_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7110_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7223_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7223_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7223_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7223_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0057 = + {0x121a, 0x0057, pci_subsys_121a_0005_121a_0057, 0}; +#undef pci_ss_info_121a_0057 +#define pci_ss_info_121a_0057 pci_ss_info_121a_0005_121a_0057 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0009_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0009_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000f = + {0x11bd, 0x000f, pci_subsys_123f_8120_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_123f_8120_11bd_000f +static const pciSubsystemInfo pci_ss_info_123f_8120_1809_0016 = + {0x1809, 0x0016, pci_subsys_123f_8120_1809_0016, 0}; +#undef pci_ss_info_1809_0016 +#define pci_ss_info_1809_0016 pci_ss_info_123f_8120_1809_0016 +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125b_1400_1186_1100 = + {0x1186, 0x1100, pci_subsys_125b_1400_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_125b_1400_1186_1100 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +static const pciSubsystemInfo pci_ss_info_125d_1969_153b_111b = + {0x153b, 0x111b, pci_subsys_125d_1969_153b_111b, 0}; +#undef pci_ss_info_153b_111b +#define pci_ss_info_153b_111b pci_ss_info_125d_1969_153b_111b +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_125d_1988_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_125d_1988_0e11_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_125d_1998_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_125d_1998_1028_00b1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3872_1468_0202 = + {0x1468, 0x0202, pci_subsys_1260_3872_1468_0202, 0}; +#undef pci_ss_info_1468_0202 +#define pci_ss_info_1468_0202 pci_ss_info_1260_3872_1468_0202 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3700 = + {0x1186, 0x3700, pci_subsys_1260_3873_1186_3700, 0}; +#undef pci_ss_info_1186_3700 +#define pci_ss_info_1186_3700 pci_ss_info_1260_3873_1186_3700 +static const pciSubsystemInfo pci_ss_info_1260_3873_1385_4105 = + {0x1385, 0x4105, pci_subsys_1260_3873_1385_4105, 0}; +#undef pci_ss_info_1385_4105 +#define pci_ss_info_1385_4105 pci_ss_info_1260_3873_1385_4105 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_16a5_1601 = + {0x16a5, 0x1601, pci_subsys_1260_3873_16a5_1601, 0}; +#undef pci_ss_info_16a5_1601 +#define pci_ss_info_16a5_1601 pci_ss_info_1260_3873_16a5_1601 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3886_17cf_0037 = + {0x17cf, 0x0037, pci_subsys_1260_3886_17cf_0037, 0}; +#undef pci_ss_info_17cf_0037 +#define pci_ss_info_17cf_0037 pci_ss_info_1260_3886_17cf_0037 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2802 = + {0x10b8, 0x2802, pci_subsys_1260_3890_10b8_2802, 0}; +#undef pci_ss_info_10b8_2802 +#define pci_ss_info_10b8_2802 pci_ss_info_1260_3890_10b8_2802 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2835 = + {0x10b8, 0x2835, pci_subsys_1260_3890_10b8_2835, 0}; +#undef pci_ss_info_10b8_2835 +#define pci_ss_info_10b8_2835 pci_ss_info_1260_3890_10b8_2835 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_a835 = + {0x10b8, 0xa835, pci_subsys_1260_3890_10b8_a835, 0}; +#undef pci_ss_info_10b8_a835 +#define pci_ss_info_10b8_a835 pci_ss_info_1260_3890_10b8_a835 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_4203 = + {0x1113, 0x4203, pci_subsys_1260_3890_1113_4203, 0}; +#undef pci_ss_info_1113_4203 +#define pci_ss_info_1113_4203 pci_ss_info_1260_3890_1113_4203 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee03 = + {0x1113, 0xee03, pci_subsys_1260_3890_1113_ee03, 0}; +#undef pci_ss_info_1113_ee03 +#define pci_ss_info_1113_ee03 pci_ss_info_1260_3890_1113_ee03 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee08 = + {0x1113, 0xee08, pci_subsys_1260_3890_1113_ee08, 0}; +#undef pci_ss_info_1113_ee08 +#define pci_ss_info_1113_ee08 pci_ss_info_1260_3890_1113_ee08 +static const pciSubsystemInfo pci_ss_info_1260_3890_1186_3202 = + {0x1186, 0x3202, pci_subsys_1260_3890_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_1260_3890_1186_3202 +static const pciSubsystemInfo pci_ss_info_1260_3890_1259_c104 = + {0x1259, 0xc104, pci_subsys_1260_3890_1259_c104, 0}; +#undef pci_ss_info_1259_c104 +#define pci_ss_info_1259_c104 pci_ss_info_1260_3890_1259_c104 +static const pciSubsystemInfo pci_ss_info_1260_3890_1385_4800 = + {0x1385, 0x4800, pci_subsys_1260_3890_1385_4800, 0}; +#undef pci_ss_info_1385_4800 +#define pci_ss_info_1385_4800 pci_ss_info_1260_3890_1385_4800 +static const pciSubsystemInfo pci_ss_info_1260_3890_16a5_1605 = + {0x16a5, 0x1605, pci_subsys_1260_3890_16a5_1605, 0}; +#undef pci_ss_info_16a5_1605 +#define pci_ss_info_16a5_1605 pci_ss_info_1260_3890_16a5_1605 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0014 = + {0x17cf, 0x0014, pci_subsys_1260_3890_17cf_0014, 0}; +#undef pci_ss_info_17cf_0014 +#define pci_ss_info_17cf_0014 pci_ss_info_1260_3890_17cf_0014 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0020 = + {0x17cf, 0x0020, pci_subsys_1260_3890_17cf_0020, 0}; +#undef pci_ss_info_17cf_0020 +#define pci_ss_info_17cf_0020 pci_ss_info_1260_3890_17cf_0020 +static const pciSubsystemInfo pci_ss_info_1260_ffff_1260_0000 = + {0x1260, 0x0000, pci_subsys_1260_ffff_1260_0000, 0}; +#undef pci_ss_info_1260_0000 +#define pci_ss_info_1260_0000 pci_ss_info_1260_ffff_1260_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_1371_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_1371_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4541 = + {0x8086, 0x4541, pci_subsys_1274_1371_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_1274_1371_8086_4541 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_5880_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_5880_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1005_127a = + {0x1005, 0x127a, pci_subsys_127a_1005_1005_127a, 0}; +#undef pci_ss_info_1005_127a +#define pci_ss_info_1005_127a pci_ss_info_127a_1005_1005_127a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1283_8211_1043_8138 = + {0x1043, 0x8138, pci_subsys_1283_8211_1043_8138, 0}; +#undef pci_ss_info_1043_8138 +#define pci_ss_info_1043_8138 pci_ss_info_1283_8211_1043_8138 +static const pciSubsystemInfo pci_ss_info_1283_8212_1283_0001 = + {0x1283, 0x0001, pci_subsys_1283_8212_1283_0001, 0}; +#undef pci_ss_info_1283_0001 +#define pci_ss_info_1283_0001 pci_ss_info_1283_8212_1283_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_1014_0104 = + {0x1014, 0x0104, pci_subsys_12ae_0001_1014_0104, 0}; +#undef pci_ss_info_1014_0104 +#define pci_ss_info_1014_0104 pci_ss_info_12ae_0001_1014_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_12ae_0002_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_12ae_0002_10a9_8002 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1317_8201_10b8_2635 = + {0x10b8, 0x2635, pci_subsys_1317_8201_10b8_2635, 0}; +#undef pci_ss_info_10b8_2635 +#define pci_ss_info_10b8_2635 pci_ss_info_1317_8201_10b8_2635 +static const pciSubsystemInfo pci_ss_info_1317_8201_1317_8201 = + {0x1317, 0x8201, pci_subsys_1317_8201_1317_8201, 0}; +#undef pci_ss_info_1317_8201 +#define pci_ss_info_1317_8201 pci_ss_info_1317_8201_1317_8201 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1319_0801_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0801_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0801_1319_1319 +static const pciSubsystemInfo pci_ss_info_1319_0802_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0802_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0802_1319_1319 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7890_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7890_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7890_134d_0001 +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1371_434e_1371_434e = + {0x1371, 0x434e, pci_subsys_1371_434e_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_1371_434e_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1704 = + {0x0675, 0x1704, pci_subsys_1397_2bd0_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1397_2bd0_0675_1704 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1708 = + {0x0675, 0x1708, pci_subsys_1397_2bd0_0675_1708, 0}; +#undef pci_ss_info_0675_1708 +#define pci_ss_info_0675_1708 pci_ss_info_1397_2bd0_0675_1708 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13c1_1001_13c1_1001 = + {0x13c1, 0x1001, pci_subsys_13c1_1001_13c1_1001, 0}; +#undef pci_ss_info_13c1_1001 +#define pci_ss_info_13c1_1001 pci_ss_info_13c1_1001_13c1_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8035 = + {0x1043, 0x8035, pci_subsys_13f6_0111_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_13f6_0111_1043_8035 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1681_a000 = + {0x1681, 0xa000, pci_subsys_13f6_0111_1681_a000, 0}; +#undef pci_ss_info_1681_a000 +#define pci_ss_info_1681_a000 pci_ss_info_13f6_0111_1681_a000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_1712 = + {0x1412, 0x1712, pci_subsys_1412_1712_1412_1712, 0}; +#undef pci_ss_info_1412_1712 +#define pci_ss_info_1412_1712 pci_ss_info_1412_1712_1412_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d630 = + {0x1412, 0xd630, pci_subsys_1412_1712_1412_d630, 0}; +#undef pci_ss_info_1412_d630 +#define pci_ss_info_1412_d630 pci_ss_info_1412_1712_1412_d630 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d631 = + {0x1412, 0xd631, pci_subsys_1412_1712_1412_d631, 0}; +#undef pci_ss_info_1412_d631 +#define pci_ss_info_1412_d631 pci_ss_info_1412_1712_1412_d631 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d632 = + {0x1412, 0xd632, pci_subsys_1412_1712_1412_d632, 0}; +#undef pci_ss_info_1412_d632 +#define pci_ss_info_1412_d632 pci_ss_info_1412_1712_1412_d632 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d633 = + {0x1412, 0xd633, pci_subsys_1412_1712_1412_d633, 0}; +#undef pci_ss_info_1412_d633 +#define pci_ss_info_1412_d633 pci_ss_info_1412_1712_1412_d633 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d634 = + {0x1412, 0xd634, pci_subsys_1412_1712_1412_d634, 0}; +#undef pci_ss_info_1412_d634 +#define pci_ss_info_1412_d634 pci_ss_info_1412_1712_1412_d634 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d635 = + {0x1412, 0xd635, pci_subsys_1412_1712_1412_d635, 0}; +#undef pci_ss_info_1412_d635 +#define pci_ss_info_1412_d635 pci_ss_info_1412_1712_1412_d635 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d637 = + {0x1412, 0xd637, pci_subsys_1412_1712_1412_d637, 0}; +#undef pci_ss_info_1412_d637 +#define pci_ss_info_1412_d637 pci_ss_info_1412_1712_1412_d637 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d638 = + {0x1412, 0xd638, pci_subsys_1412_1712_1412_d638, 0}; +#undef pci_ss_info_1412_d638 +#define pci_ss_info_1412_d638 pci_ss_info_1412_1712_1412_d638 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63b = + {0x1412, 0xd63b, pci_subsys_1412_1712_1412_d63b, 0}; +#undef pci_ss_info_1412_d63b +#define pci_ss_info_1412_d63b pci_ss_info_1412_1712_1412_d63b +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63c = + {0x1412, 0xd63c, pci_subsys_1412_1712_1412_d63c, 0}; +#undef pci_ss_info_1412_d63c +#define pci_ss_info_1412_d63c pci_ss_info_1412_1712_1412_d63c +static const pciSubsystemInfo pci_ss_info_1412_1712_1416_1712 = + {0x1416, 0x1712, pci_subsys_1412_1712_1416_1712, 0}; +#undef pci_ss_info_1416_1712 +#define pci_ss_info_1416_1712 pci_ss_info_1412_1712_1416_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1115 = + {0x153b, 0x1115, pci_subsys_1412_1712_153b_1115, 0}; +#undef pci_ss_info_153b_1115 +#define pci_ss_info_153b_1115 pci_ss_info_1412_1712_153b_1115 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1125 = + {0x153b, 0x1125, pci_subsys_1412_1712_153b_1125, 0}; +#undef pci_ss_info_153b_1125 +#define pci_ss_info_153b_1125 pci_ss_info_1412_1712_153b_1125 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112b = + {0x153b, 0x112b, pci_subsys_1412_1712_153b_112b, 0}; +#undef pci_ss_info_153b_112b +#define pci_ss_info_153b_112b pci_ss_info_1412_1712_153b_112b +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112c = + {0x153b, 0x112c, pci_subsys_1412_1712_153b_112c, 0}; +#undef pci_ss_info_153b_112c +#define pci_ss_info_153b_112c pci_ss_info_1412_1712_153b_112c +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1130 = + {0x153b, 0x1130, pci_subsys_1412_1712_153b_1130, 0}; +#undef pci_ss_info_153b_1130 +#define pci_ss_info_153b_1130 pci_ss_info_1412_1712_153b_1130 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1138 = + {0x153b, 0x1138, pci_subsys_1412_1712_153b_1138, 0}; +#undef pci_ss_info_153b_1138 +#define pci_ss_info_153b_1138 pci_ss_info_1412_1712_153b_1138 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1151 = + {0x153b, 0x1151, pci_subsys_1412_1712_153b_1151, 0}; +#undef pci_ss_info_153b_1151 +#define pci_ss_info_153b_1151 pci_ss_info_1412_1712_153b_1151 +static const pciSubsystemInfo pci_ss_info_1412_1712_16ce_1040 = + {0x16ce, 0x1040, pci_subsys_1412_1712_16ce_1040, 0}; +#undef pci_ss_info_16ce_1040 +#define pci_ss_info_16ce_1040 pci_ss_info_1412_1712_16ce_1040 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_1724 = + {0x1412, 0x1724, pci_subsys_1412_1724_1412_1724, 0}; +#undef pci_ss_info_1412_1724 +#define pci_ss_info_1412_1724 pci_ss_info_1412_1724_1412_1724 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3630 = + {0x1412, 0x3630, pci_subsys_1412_1724_1412_3630, 0}; +#undef pci_ss_info_1412_3630 +#define pci_ss_info_1412_3630 pci_ss_info_1412_1724_1412_3630 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3631 = + {0x1412, 0x3631, pci_subsys_1412_1724_1412_3631, 0}; +#undef pci_ss_info_1412_3631 +#define pci_ss_info_1412_3631 pci_ss_info_1412_1724_1412_3631 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1145 = + {0x153b, 0x1145, pci_subsys_1412_1724_153b_1145, 0}; +#undef pci_ss_info_153b_1145 +#define pci_ss_info_153b_1145 pci_ss_info_1412_1724_153b_1145 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1147 = + {0x153b, 0x1147, pci_subsys_1412_1724_153b_1147, 0}; +#undef pci_ss_info_153b_1147 +#define pci_ss_info_153b_1147 pci_ss_info_1412_1724_153b_1147 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1153 = + {0x153b, 0x1153, pci_subsys_1412_1724_153b_1153, 0}; +#undef pci_ss_info_153b_1153 +#define pci_ss_info_153b_1153 pci_ss_info_1412_1724_153b_1153 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f641 = + {0x270f, 0xf641, pci_subsys_1412_1724_270f_f641, 0}; +#undef pci_ss_info_270f_f641 +#define pci_ss_info_270f_f641 pci_ss_info_1412_1724_270f_f641 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f645 = + {0x270f, 0xf645, pci_subsys_1412_1724_270f_f645, 0}; +#undef pci_ss_info_270f_f645 +#define pci_ss_info_270f_f645 pci_ss_info_1412_1724_270f_f645 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2050 = + {0x131f, 0x2050, pci_subsys_1415_9501_131f_2050, 0}; +#undef pci_ss_info_131f_2050 +#define pci_ss_info_131f_2050 pci_ss_info_1415_9501_131f_2050 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2051 = + {0x131f, 0x2051, pci_subsys_1415_9501_131f_2051, 0}; +#undef pci_ss_info_131f_2051 +#define pci_ss_info_131f_2051 pci_ss_info_1415_9501_131f_2051 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128a = + {0x103c, 0x128a, pci_subsys_14e4_1645_103c_128a, 0}; +#undef pci_ss_info_103c_128a +#define pci_ss_info_103c_128a pci_ss_info_14e4_1645_103c_128a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128b = + {0x103c, 0x128b, pci_subsys_14e4_1645_103c_128b, 0}; +#undef pci_ss_info_103c_128b +#define pci_ss_info_103c_128b pci_ss_info_14e4_1645_103c_128b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12a4 = + {0x103c, 0x12a4, pci_subsys_14e4_1645_103c_12a4, 0}; +#undef pci_ss_info_103c_12a4 +#define pci_ss_info_103c_12a4 pci_ss_info_14e4_1645_103c_12a4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12c1 = + {0x103c, 0x12c1, pci_subsys_14e4_1645_103c_12c1, 0}; +#undef pci_ss_info_103c_12c1 +#define pci_ss_info_103c_12c1 pci_ss_info_14e4_1645_103c_12c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_1300 = + {0x103c, 0x1300, pci_subsys_14e4_1645_103c_1300, 0}; +#undef pci_ss_info_103c_1300 +#define pci_ss_info_103c_1300 pci_ss_info_14e4_1645_103c_1300 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1645_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1645_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8011 = + {0x10a9, 0x8011, pci_subsys_14e4_1645_10a9_8011, 0}; +#undef pci_ss_info_10a9_8011 +#define pci_ss_info_10a9_8011 pci_ss_info_14e4_1645_10a9_8011 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8012 = + {0x10a9, 0x8012, pci_subsys_14e4_1645_10a9_8012, 0}; +#undef pci_ss_info_10a9_8012 +#define pci_ss_info_10a9_8012 pci_ss_info_14e4_1645_10a9_8012 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1647_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1647_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1734_100b = + {0x1734, 0x100b, pci_subsys_14e4_1648_1734_100b, 0}; +#undef pci_ss_info_1734_100b +#define pci_ss_info_1734_100b pci_ss_info_14e4_1648_1734_100b +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3101 = + {0x103c, 0x3101, pci_subsys_14e4_164a_103c_3101, 0}; +#undef pci_ss_info_103c_3101 +#define pci_ss_info_103c_3101 pci_ss_info_14e4_164a_103c_3101 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1653_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1653_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1653_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1654_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1654_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3100 = + {0x103c, 0x3100, pci_subsys_14e4_1654_103c_3100, 0}; +#undef pci_ss_info_103c_3100 +#define pci_ss_info_103c_3100 pci_ss_info_14e4_1654_103c_3100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3226 = + {0x103c, 0x3226, pci_subsys_14e4_1654_103c_3226, 0}; +#undef pci_ss_info_103c_3226 +#define pci_ss_info_103c_3226 pci_ss_info_14e4_1654_103c_3226 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1014_02c6 = + {0x1014, 0x02c6, pci_subsys_14e4_1659_1014_02c6, 0}; +#undef pci_ss_info_1014_02c6 +#define pci_ss_info_1014_02c6 pci_ss_info_14e4_1659_1014_02c6 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7031 = + {0x103c, 0x7031, pci_subsys_14e4_1659_103c_7031, 0}; +#undef pci_ss_info_103c_7031 +#define pci_ss_info_103c_7031 pci_ss_info_14e4_1659_103c_7031 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7032 = + {0x103c, 0x7032, pci_subsys_14e4_1659_103c_7032, 0}; +#undef pci_ss_info_103c_7032 +#define pci_ss_info_103c_7032 pci_ss_info_14e4_1659_103c_7032 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1734_1061 = + {0x1734, 0x1061, pci_subsys_14e4_1659_1734_1061, 0}; +#undef pci_ss_info_1734_1061 +#define pci_ss_info_1734_1061 pci_ss_info_14e4_1659_1734_1061 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165d_1028_865d = + {0x1028, 0x865d, pci_subsys_14e4_165d_1028_865d, 0}; +#undef pci_ss_info_1028_865d +#define pci_ss_info_1028_865d pci_ss_info_14e4_165d_1028_865d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_088c = + {0x103c, 0x088c, pci_subsys_14e4_165e_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_14e4_165e_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_0890 = + {0x103c, 0x0890, pci_subsys_14e4_165e_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_14e4_165e_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_165e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_165e_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1668_103c_7039 = + {0x103c, 0x7039, pci_subsys_14e4_1668_103c_7039, 0}; +#undef pci_ss_info_103c_7039 +#define pci_ss_info_103c_7039 pci_ss_info_14e4_1668_103c_7039 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0179 = + {0x1028, 0x0179, pci_subsys_14e4_1677_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_14e4_1677_1028_0179 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0182 = + {0x1028, 0x0182, pci_subsys_14e4_1677_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_14e4_1677_1028_0182 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_01ad = + {0x1028, 0x01ad, pci_subsys_14e4_1677_1028_01ad, 0}; +#undef pci_ss_info_1028_01ad +#define pci_ss_info_1028_01ad pci_ss_info_14e4_1677_1028_01ad +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1677_1734_105d = + {0x1734, 0x105d, pci_subsys_14e4_1677_1734_105d, 0}; +#undef pci_ss_info_1734_105d +#define pci_ss_info_1734_105d pci_ss_info_14e4_1677_1734_105d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1696_103c_12bc = + {0x103c, 0x12bc, pci_subsys_14e4_1696_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_14e4_1696_103c_12bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_169c_103c_308b = + {0x103c, 0x308b, pci_subsys_14e4_169c_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_14e4_169c_103c_308b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16aa_103c_3102 = + {0x103c, 0x3102, pci_subsys_14e4_16aa_103c_3102, 0}; +#undef pci_ss_info_103c_3102 +#define pci_ss_info_103c_3102 pci_ss_info_14e4_16aa_103c_3102 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16c7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16c7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16c7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16c7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12c3 = + {0x103c, 0x12c3, pci_subsys_14e4_16c7_103c_12c3, 0}; +#undef pci_ss_info_103c_12c3 +#define pci_ss_info_103c_12c3 pci_ss_info_14e4_16c7_103c_12c3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12ca = + {0x103c, 0x12ca, pci_subsys_14e4_16c7_103c_12ca, 0}; +#undef pci_ss_info_103c_12ca +#define pci_ss_info_103c_12ca pci_ss_info_14e4_16c7_103c_12ca +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0188 = + {0x1028, 0x0188, pci_subsys_14e4_170c_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_14e4_170c_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0196 = + {0x1028, 0x0196, pci_subsys_14e4_170c_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_14e4_170c_1028_0196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_170c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_170c_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_170d_1014_0545 = + {0x1014, 0x0545, pci_subsys_14e4_170d_1014_0545, 0}; +#undef pci_ss_info_1014_0545 +#define pci_ss_info_1014_0545 pci_ss_info_14e4_170d_1014_0545 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4301_1028_0407 = + {0x1028, 0x0407, pci_subsys_14e4_4301_1028_0407, 0}; +#undef pci_ss_info_1028_0407 +#define pci_ss_info_1028_0407 pci_ss_info_14e4_4301_1028_0407 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4301_1043_0120 = + {0x1043, 0x0120, pci_subsys_14e4_4301_1043_0120, 0}; +#undef pci_ss_info_1043_0120 +#define pci_ss_info_1043_0120 pci_ss_info_14e4_4301_1043_0120 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4318_103c_1356 = + {0x103c, 0x1356, pci_subsys_14e4_4318_103c_1356, 0}; +#undef pci_ss_info_103c_1356 +#define pci_ss_info_103c_1356 pci_ss_info_14e4_4318_103c_1356 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0311 = + {0x1468, 0x0311, pci_subsys_14e4_4318_1468_0311, 0}; +#undef pci_ss_info_1468_0311 +#define pci_ss_info_1468_0311 pci_ss_info_14e4_4318_1468_0311 +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0312 = + {0x1468, 0x0312, pci_subsys_14e4_4318_1468_0312, 0}; +#undef pci_ss_info_1468_0312 +#define pci_ss_info_1468_0312 pci_ss_info_14e4_4318_1468_0312 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_0449 = + {0x14e4, 0x0449, pci_subsys_14e4_4318_14e4_0449, 0}; +#undef pci_ss_info_14e4_0449 +#define pci_ss_info_14e4_0449 pci_ss_info_14e4_4318_14e4_0449 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_4318 = + {0x14e4, 0x4318, pci_subsys_14e4_4318_14e4_4318, 0}; +#undef pci_ss_info_14e4_4318 +#define pci_ss_info_14e4_4318 pci_ss_info_14e4_4318_14e4_4318 +static const pciSubsystemInfo pci_ss_info_14e4_4318_16ec_0119 = + {0x16ec, 0x0119, pci_subsys_14e4_4318_16ec_0119, 0}; +#undef pci_ss_info_16ec_0119 +#define pci_ss_info_16ec_0119 pci_ss_info_14e4_4318_16ec_0119 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4320_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4320_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4320_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4320_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12f4 = + {0x103c, 0x12f4, pci_subsys_14e4_4320_103c_12f4, 0}; +#undef pci_ss_info_103c_12f4 +#define pci_ss_info_103c_12f4 pci_ss_info_14e4_4320_103c_12f4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12fa = + {0x103c, 0x12fa, pci_subsys_14e4_4320_103c_12fa, 0}; +#undef pci_ss_info_103c_12fa +#define pci_ss_info_103c_12fa pci_ss_info_14e4_4320_103c_12fa +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_1043_100f = + {0x1043, 0x100f, pci_subsys_14e4_4320_1043_100f, 0}; +#undef pci_ss_info_1043_100f +#define pci_ss_info_1043_100f pci_ss_info_14e4_4320_1043_100f +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1057_7025 = + {0x1057, 0x7025, pci_subsys_14e4_4320_1057_7025, 0}; +#undef pci_ss_info_1057_7025 +#define pci_ss_info_1057_7025 pci_ss_info_14e4_4320_1057_7025 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_106b_004e = + {0x106b, 0x004e, pci_subsys_14e4_4320_106b_004e, 0}; +#undef pci_ss_info_106b_004e +#define pci_ss_info_106b_004e pci_ss_info_14e4_4320_106b_004e +static const pciSubsystemInfo pci_ss_info_14e4_4320_144f_7050 = + {0x144f, 0x7050, pci_subsys_14e4_4320_144f_7050, 0}; +#undef pci_ss_info_144f_7050 +#define pci_ss_info_144f_7050 pci_ss_info_14e4_4320_144f_7050 +static const pciSubsystemInfo pci_ss_info_14e4_4320_14e4_4320 = + {0x14e4, 0x4320, pci_subsys_14e4_4320_14e4_4320, 0}; +#undef pci_ss_info_14e4_4320 +#define pci_ss_info_14e4_4320 pci_ss_info_14e4_4320_14e4_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1737_4320 = + {0x1737, 0x4320, pci_subsys_14e4_4320_1737_4320, 0}; +#undef pci_ss_info_1737_4320 +#define pci_ss_info_1737_4320 pci_ss_info_14e4_4320_1737_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7001 = + {0x1799, 0x7001, pci_subsys_14e4_4320_1799_7001, 0}; +#undef pci_ss_info_1799_7001 +#define pci_ss_info_1799_7001 pci_ss_info_14e4_4320_1799_7001 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7010 = + {0x1799, 0x7010, pci_subsys_14e4_4320_1799_7010, 0}; +#undef pci_ss_info_1799_7010 +#define pci_ss_info_1799_7010 pci_ss_info_14e4_4320_1799_7010 +static const pciSubsystemInfo pci_ss_info_14e4_4320_185f_1220 = + {0x185f, 0x1220, pci_subsys_14e4_4320_185f_1220, 0}; +#undef pci_ss_info_185f_1220 +#define pci_ss_info_185f_1220 pci_ss_info_14e4_4320_185f_1220 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4324_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4324_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4324_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4324_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0003 = + {0x1414, 0x0003, pci_subsys_14e4_4325_1414_0003, 0}; +#undef pci_ss_info_1414_0003 +#define pci_ss_info_1414_0003 pci_ss_info_14e4_4325_1414_0003 +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0004 = + {0x1414, 0x0004, pci_subsys_14e4_4325_1414_0004, 0}; +#undef pci_ss_info_1414_0004 +#define pci_ss_info_1414_0004 pci_ss_info_14e4_4325_1414_0004 +static const pciSubsystemInfo pci_ss_info_14e4_4401_1043_80a8 = + {0x1043, 0x80a8, pci_subsys_14e4_4401_1043_80a8, 0}; +#undef pci_ss_info_1043_80a8 +#define pci_ss_info_1043_80a8 pci_ss_info_14e4_4401_1043_80a8 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2045_14f1_2045 = + {0x14f1, 0x2045, pci_subsys_14f1_2045_14f1_2045, 0}; +#undef pci_ss_info_14f1_2045 +#define pci_ss_info_14f1_2045 pci_ss_info_14f1_2045_14f1_2045 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8800_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8800_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8800_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8800_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9001 = + {0x0070, 0x9001, pci_subsys_14f1_8800_0070_9001, 0}; +#undef pci_ss_info_0070_9001 +#define pci_ss_info_0070_9001 pci_ss_info_14f1_8800_0070_9001 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9200 = + {0x0070, 0x9200, pci_subsys_14f1_8800_0070_9200, 0}; +#undef pci_ss_info_0070_9200 +#define pci_ss_info_0070_9200 pci_ss_info_14f1_8800_0070_9200 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9202 = + {0x0070, 0x9202, pci_subsys_14f1_8800_0070_9202, 0}; +#undef pci_ss_info_0070_9202 +#define pci_ss_info_0070_9202 pci_ss_info_14f1_8800_0070_9202 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9402 = + {0x0070, 0x9402, pci_subsys_14f1_8800_0070_9402, 0}; +#undef pci_ss_info_0070_9402 +#define pci_ss_info_0070_9402 pci_ss_info_14f1_8800_0070_9402 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9802 = + {0x0070, 0x9802, pci_subsys_14f1_8800_0070_9802, 0}; +#undef pci_ss_info_0070_9802 +#define pci_ss_info_0070_9802 pci_ss_info_14f1_8800_0070_9802 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_00f8 = + {0x1002, 0x00f8, pci_subsys_14f1_8800_1002_00f8, 0}; +#undef pci_ss_info_1002_00f8 +#define pci_ss_info_1002_00f8 pci_ss_info_14f1_8800_1002_00f8 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_a101 = + {0x1002, 0xa101, pci_subsys_14f1_8800_1002_a101, 0}; +#undef pci_ss_info_1002_a101 +#define pci_ss_info_1002_a101 pci_ss_info_14f1_8800_1002_a101 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_8800_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8800_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8800_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6613 = + {0x107d, 0x6613, pci_subsys_14f1_8800_107d_6613, 0}; +#undef pci_ss_info_107d_6613 +#define pci_ss_info_107d_6613 pci_ss_info_14f1_8800_107d_6613 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6620 = + {0x107d, 0x6620, pci_subsys_14f1_8800_107d_6620, 0}; +#undef pci_ss_info_107d_6620 +#define pci_ss_info_107d_6620 pci_ss_info_14f1_8800_107d_6620 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8800_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8800_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_665f = + {0x107d, 0x665f, pci_subsys_14f1_8800_107d_665f, 0}; +#undef pci_ss_info_107d_665f +#define pci_ss_info_107d_665f pci_ss_info_14f1_8800_107d_665f +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d003 = + {0x10fc, 0xd003, pci_subsys_14f1_8800_10fc_d003, 0}; +#undef pci_ss_info_10fc_d003 +#define pci_ss_info_10fc_d003 pci_ss_info_14f1_8800_10fc_d003 +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d035 = + {0x10fc, 0xd035, pci_subsys_14f1_8800_10fc_d035, 0}; +#undef pci_ss_info_10fc_d035 +#define pci_ss_info_10fc_d035 pci_ss_info_14f1_8800_10fc_d035 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1421_0334 = + {0x1421, 0x0334, pci_subsys_14f1_8800_1421_0334, 0}; +#undef pci_ss_info_1421_0334 +#define pci_ss_info_1421_0334 pci_ss_info_14f1_8800_1421_0334 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000a = + {0x1461, 0x000a, pci_subsys_14f1_8800_1461_000a, 0}; +#undef pci_ss_info_1461_000a +#define pci_ss_info_1461_000a pci_ss_info_14f1_8800_1461_000a +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000b = + {0x1461, 0x000b, pci_subsys_14f1_8800_1461_000b, 0}; +#undef pci_ss_info_1461_000b +#define pci_ss_info_1461_000b pci_ss_info_14f1_8800_1461_000b +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_8011 = + {0x1461, 0x8011, pci_subsys_14f1_8800_1461_8011, 0}; +#undef pci_ss_info_1461_8011 +#define pci_ss_info_1461_8011 pci_ss_info_14f1_8800_1461_8011 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8800_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8800_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14c7_0107 = + {0x14c7, 0x0107, pci_subsys_14f1_8800_14c7_0107, 0}; +#undef pci_ss_info_14c7_0107 +#define pci_ss_info_14c7_0107 pci_ss_info_14f1_8800_14c7_0107 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8800_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8800_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0342 = + {0x14f1, 0x0342, pci_subsys_14f1_8800_14f1_0342, 0}; +#undef pci_ss_info_14f1_0342 +#define pci_ss_info_14f1_0342 pci_ss_info_14f1_8800_14f1_0342 +static const pciSubsystemInfo pci_ss_info_14f1_8800_153b_1166 = + {0x153b, 0x1166, pci_subsys_14f1_8800_153b_1166, 0}; +#undef pci_ss_info_153b_1166 +#define pci_ss_info_153b_1166 pci_ss_info_14f1_8800_153b_1166 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1540_2580 = + {0x1540, 0x2580, pci_subsys_14f1_8800_1540_2580, 0}; +#undef pci_ss_info_1540_2580 +#define pci_ss_info_1540_2580 pci_ss_info_14f1_8800_1540_2580 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4811 = + {0x1554, 0x4811, pci_subsys_14f1_8800_1554_4811, 0}; +#undef pci_ss_info_1554_4811 +#define pci_ss_info_1554_4811 pci_ss_info_14f1_8800_1554_4811 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4813 = + {0x1554, 0x4813, pci_subsys_14f1_8800_1554_4813, 0}; +#undef pci_ss_info_1554_4813 +#define pci_ss_info_1554_4813 pci_ss_info_14f1_8800_1554_4813 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8800_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8800_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8800_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8800_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08b2 = + {0x17de, 0x08b2, pci_subsys_14f1_8800_17de_08b2, 0}; +#undef pci_ss_info_17de_08b2 +#define pci_ss_info_17de_08b2 pci_ss_info_14f1_8800_17de_08b2 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_a8a6 = + {0x17de, 0xa8a6, pci_subsys_14f1_8800_17de_a8a6, 0}; +#undef pci_ss_info_17de_a8a6 +#define pci_ss_info_17de_a8a6 pci_ss_info_14f1_8800_17de_a8a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1822_0025 = + {0x1822, 0x0025, pci_subsys_14f1_8800_1822_0025, 0}; +#undef pci_ss_info_1822_0025 +#define pci_ss_info_1822_0025 pci_ss_info_14f1_8800_1822_0025 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8800_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8800_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8800_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8800_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8800_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8800_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8800_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8800_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db11 = + {0x18ac, 0xdb11, pci_subsys_14f1_8800_18ac_db11, 0}; +#undef pci_ss_info_18ac_db11 +#define pci_ss_info_18ac_db11 pci_ss_info_14f1_8800_18ac_db11 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db50 = + {0x18ac, 0xdb50, pci_subsys_14f1_8800_18ac_db50, 0}; +#undef pci_ss_info_18ac_db50 +#define pci_ss_info_18ac_db50 pci_ss_info_14f1_8800_18ac_db50 +static const pciSubsystemInfo pci_ss_info_14f1_8800_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8800_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8800_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8801_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8801_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8801_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8802_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8802_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8802_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8802_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8802_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8802_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8802_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8802_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8802_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8802_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8802_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8802_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8802_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8802_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8802_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8802_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8802_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8802_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8802_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8802_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8802_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8802_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8802_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8802_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8802_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8802_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8802_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8802_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8802_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8802_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8804_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8804_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8804_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8811_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8811_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8811_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8811_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8811_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8811_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8811_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8811_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8811_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8811_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8811_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8811_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8811_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8811_18ac_db00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0c00 = + {0x1522, 0x0c00, pci_subsys_1522_0100_1522_0c00, 0}; +#undef pci_ss_info_1522_0c00 +#define pci_ss_info_1522_0c00 pci_ss_info_1522_0100_1522_0c00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0d00 = + {0x1522, 0x0d00, pci_subsys_1522_0100_1522_0d00, 0}; +#undef pci_ss_info_1522_0d00 +#define pci_ss_info_1522_0d00 pci_ss_info_1522_0100_1522_0d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_1d00 = + {0x1522, 0x1d00, pci_subsys_1522_0100_1522_1d00, 0}; +#undef pci_ss_info_1522_1d00 +#define pci_ss_info_1522_1d00 pci_ss_info_1522_0100_1522_1d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2000 = + {0x1522, 0x2000, pci_subsys_1522_0100_1522_2000, 0}; +#undef pci_ss_info_1522_2000 +#define pci_ss_info_1522_2000 pci_ss_info_1522_0100_1522_2000 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2100 = + {0x1522, 0x2100, pci_subsys_1522_0100_1522_2100, 0}; +#undef pci_ss_info_1522_2100 +#define pci_ss_info_1522_2100 pci_ss_info_1522_0100_1522_2100 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2200 = + {0x1522, 0x2200, pci_subsys_1522_0100_1522_2200, 0}; +#undef pci_ss_info_1522_2200 +#define pci_ss_info_1522_2200 pci_ss_info_1522_0100_1522_2200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2300 = + {0x1522, 0x2300, pci_subsys_1522_0100_1522_2300, 0}; +#undef pci_ss_info_1522_2300 +#define pci_ss_info_1522_2300 pci_ss_info_1522_0100_1522_2300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2400 = + {0x1522, 0x2400, pci_subsys_1522_0100_1522_2400, 0}; +#undef pci_ss_info_1522_2400 +#define pci_ss_info_1522_2400 pci_ss_info_1522_0100_1522_2400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2500 = + {0x1522, 0x2500, pci_subsys_1522_0100_1522_2500, 0}; +#undef pci_ss_info_1522_2500 +#define pci_ss_info_1522_2500 pci_ss_info_1522_0100_1522_2500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2600 = + {0x1522, 0x2600, pci_subsys_1522_0100_1522_2600, 0}; +#undef pci_ss_info_1522_2600 +#define pci_ss_info_1522_2600 pci_ss_info_1522_0100_1522_2600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2700 = + {0x1522, 0x2700, pci_subsys_1522_0100_1522_2700, 0}; +#undef pci_ss_info_1522_2700 +#define pci_ss_info_1522_2700 pci_ss_info_1522_0100_1522_2700 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_0510_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_0510_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_0510_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_005a = + {0x1025, 0x005a, pci_subsys_1524_1410_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1524_1410_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1411_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_1411_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_1411_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_167b_2102_187e_3406 = + {0x187e, 0x3406, pci_subsys_167b_2102_187e_3406, 0}; +#undef pci_ss_info_187e_3406 +#define pci_ss_info_187e_3406 pci_ss_info_167b_2102_187e_3406 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_168c_0013_1113_d301 = + {0x1113, 0xd301, pci_subsys_168c_0013_1113_d301, 0}; +#undef pci_ss_info_1113_d301 +#define pci_ss_info_1113_d301 pci_ss_info_168c_0013_1113_d301 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3202 = + {0x1186, 0x3202, pci_subsys_168c_0013_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_168c_0013_1186_3202 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3203 = + {0x1186, 0x3203, pci_subsys_168c_0013_1186_3203, 0}; +#undef pci_ss_info_1186_3203 +#define pci_ss_info_1186_3203 pci_ss_info_168c_0013_1186_3203 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a12 = + {0x1186, 0x3a12, pci_subsys_168c_0013_1186_3a12, 0}; +#undef pci_ss_info_1186_3a12 +#define pci_ss_info_1186_3a12 pci_ss_info_168c_0013_1186_3a12 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a13 = + {0x1186, 0x3a13, pci_subsys_168c_0013_1186_3a13, 0}; +#undef pci_ss_info_1186_3a13 +#define pci_ss_info_1186_3a13 pci_ss_info_168c_0013_1186_3a13 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a14 = + {0x1186, 0x3a14, pci_subsys_168c_0013_1186_3a14, 0}; +#undef pci_ss_info_1186_3a14 +#define pci_ss_info_1186_3a14 pci_ss_info_168c_0013_1186_3a14 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a17 = + {0x1186, 0x3a17, pci_subsys_168c_0013_1186_3a17, 0}; +#undef pci_ss_info_1186_3a17 +#define pci_ss_info_1186_3a17 pci_ss_info_168c_0013_1186_3a17 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a18 = + {0x1186, 0x3a18, pci_subsys_168c_0013_1186_3a18, 0}; +#undef pci_ss_info_1186_3a18 +#define pci_ss_info_1186_3a18 pci_ss_info_168c_0013_1186_3a18 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a63 = + {0x1186, 0x3a63, pci_subsys_168c_0013_1186_3a63, 0}; +#undef pci_ss_info_1186_3a63 +#define pci_ss_info_1186_3a63 pci_ss_info_168c_0013_1186_3a63 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a94 = + {0x1186, 0x3a94, pci_subsys_168c_0013_1186_3a94, 0}; +#undef pci_ss_info_1186_3a94 +#define pci_ss_info_1186_3a94 pci_ss_info_168c_0013_1186_3a94 +static const pciSubsystemInfo pci_ss_info_168c_0013_1385_4d00 = + {0x1385, 0x4d00, pci_subsys_168c_0013_1385_4d00, 0}; +#undef pci_ss_info_1385_4d00 +#define pci_ss_info_1385_4d00 pci_ss_info_168c_0013_1385_4d00 +static const pciSubsystemInfo pci_ss_info_168c_0013_1458_e911 = + {0x1458, 0xe911, pci_subsys_168c_0013_1458_e911, 0}; +#undef pci_ss_info_1458_e911 +#define pci_ss_info_1458_e911 pci_ss_info_168c_0013_1458_e911 +static const pciSubsystemInfo pci_ss_info_168c_0013_14b7_0a60 = + {0x14b7, 0x0a60, pci_subsys_168c_0013_14b7_0a60, 0}; +#undef pci_ss_info_14b7_0a60 +#define pci_ss_info_14b7_0a60 pci_ss_info_168c_0013_14b7_0a60 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_0013 = + {0x168c, 0x0013, pci_subsys_168c_0013_168c_0013, 0}; +#undef pci_ss_info_168c_0013 +#define pci_ss_info_168c_0013 pci_ss_info_168c_0013_168c_0013 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1025 = + {0x168c, 0x1025, pci_subsys_168c_0013_168c_1025, 0}; +#undef pci_ss_info_168c_1025 +#define pci_ss_info_168c_1025 pci_ss_info_168c_0013_168c_1025 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1027 = + {0x168c, 0x1027, pci_subsys_168c_0013_168c_1027, 0}; +#undef pci_ss_info_168c_1027 +#define pci_ss_info_168c_1027 pci_ss_info_168c_0013_168c_1027 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2026 = + {0x168c, 0x2026, pci_subsys_168c_0013_168c_2026, 0}; +#undef pci_ss_info_168c_2026 +#define pci_ss_info_168c_2026 pci_ss_info_168c_0013_168c_2026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2041 = + {0x168c, 0x2041, pci_subsys_168c_0013_168c_2041, 0}; +#undef pci_ss_info_168c_2041 +#define pci_ss_info_168c_2041 pci_ss_info_168c_0013_168c_2041 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2042 = + {0x168c, 0x2042, pci_subsys_168c_0013_168c_2042, 0}; +#undef pci_ss_info_168c_2042 +#define pci_ss_info_168c_2042 pci_ss_info_168c_0013_168c_2042 +static const pciSubsystemInfo pci_ss_info_168c_0013_16ab_7302 = + {0x16ab, 0x7302, pci_subsys_168c_0013_16ab_7302, 0}; +#undef pci_ss_info_16ab_7302 +#define pci_ss_info_16ab_7302 pci_ss_info_168c_0013_16ab_7302 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a15 = + {0x1186, 0x3a15, pci_subsys_168c_001a_1186_3a15, 0}; +#undef pci_ss_info_1186_3a15 +#define pci_ss_info_1186_3a15 pci_ss_info_168c_001a_1186_3a15 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a16 = + {0x1186, 0x3a16, pci_subsys_168c_001a_1186_3a16, 0}; +#undef pci_ss_info_1186_3a16 +#define pci_ss_info_1186_3a16 pci_ss_info_168c_001a_1186_3a16 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a23 = + {0x1186, 0x3a23, pci_subsys_168c_001a_1186_3a23, 0}; +#undef pci_ss_info_1186_3a23 +#define pci_ss_info_1186_3a23 pci_ss_info_168c_001a_1186_3a23 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a24 = + {0x1186, 0x3a24, pci_subsys_168c_001a_1186_3a24, 0}; +#undef pci_ss_info_1186_3a24 +#define pci_ss_info_1186_3a24 pci_ss_info_168c_001a_1186_3a24 +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_1052 = + {0x168c, 0x1052, pci_subsys_168c_001a_168c_1052, 0}; +#undef pci_ss_info_168c_1052 +#define pci_ss_info_168c_1052 pci_ss_info_168c_001a_168c_1052 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a19 = + {0x1186, 0x3a19, pci_subsys_168c_001b_1186_3a19, 0}; +#undef pci_ss_info_1186_3a19 +#define pci_ss_info_1186_3a19 pci_ss_info_168c_001b_1186_3a19 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a22 = + {0x1186, 0x3a22, pci_subsys_168c_001b_1186_3a22, 0}; +#undef pci_ss_info_1186_3a22 +#define pci_ss_info_1186_3a22 pci_ss_info_168c_001b_1186_3a22 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0015 = + {0x1737, 0x0015, pci_subsys_1737_1032_1737_0015, 0}; +#undef pci_ss_info_1737_0015 +#define pci_ss_info_1737_0015 pci_ss_info_1737_1032_1737_0015 +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0024 = + {0x1737, 0x0024, pci_subsys_1737_1032_1737_0024, 0}; +#undef pci_ss_info_1737_0024 +#define pci_ss_info_1737_0024 pci_ss_info_1737_1032_1737_0024 +static const pciSubsystemInfo pci_ss_info_1737_1064_1737_0016 = + {0x1737, 0x0016, pci_subsys_1737_1064_1737_0016, 0}; +#undef pci_ss_info_1737_0016 +#define pci_ss_info_1737_0016 pci_ss_info_1737_1064_1737_0016 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_17d5_5831_103c_12d5 = + {0x103c, 0x12d5, pci_subsys_17d5_5831_103c_12d5, 0}; +#undef pci_ss_info_103c_12d5 +#define pci_ss_info_103c_12d5 pci_ss_info_17d5_5831_103c_12d5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17fe_2220_17fe_2220 = + {0x17fe, 0x2220, pci_subsys_17fe_2220_17fe_2220, 0}; +#undef pci_ss_info_17fe_2220 +#define pci_ss_info_17fe_2220 pci_ss_info_17fe_2220_17fe_2220 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1814_0101_1043_0127 = + {0x1043, 0x0127, pci_subsys_1814_0101_1043_0127, 0}; +#undef pci_ss_info_1043_0127 +#define pci_ss_info_1043_0127 pci_ss_info_1814_0101_1043_0127 +static const pciSubsystemInfo pci_ss_info_1814_0101_1462_6828 = + {0x1462, 0x6828, pci_subsys_1814_0101_1462_6828, 0}; +#undef pci_ss_info_1462_6828 +#define pci_ss_info_1462_6828 pci_ss_info_1814_0101_1462_6828 +static const pciSubsystemInfo pci_ss_info_1814_0201_1043_130f = + {0x1043, 0x130f, pci_subsys_1814_0201_1043_130f, 0}; +#undef pci_ss_info_1043_130f +#define pci_ss_info_1043_130f pci_ss_info_1814_0201_1043_130f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001e = + {0x1371, 0x001e, pci_subsys_1814_0201_1371_001e, 0}; +#undef pci_ss_info_1371_001e +#define pci_ss_info_1371_001e pci_ss_info_1814_0201_1371_001e +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001f = + {0x1371, 0x001f, pci_subsys_1814_0201_1371_001f, 0}; +#undef pci_ss_info_1371_001f +#define pci_ss_info_1371_001f pci_ss_info_1814_0201_1371_001f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_0020 = + {0x1371, 0x0020, pci_subsys_1814_0201_1371_0020, 0}; +#undef pci_ss_info_1371_0020 +#define pci_ss_info_1371_0020 pci_ss_info_1814_0201_1371_0020 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e381 = + {0x1458, 0xe381, pci_subsys_1814_0201_1458_e381, 0}; +#undef pci_ss_info_1458_e381 +#define pci_ss_info_1458_e381 pci_ss_info_1814_0201_1458_e381 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e931 = + {0x1458, 0xe931, pci_subsys_1814_0201_1458_e931, 0}; +#undef pci_ss_info_1458_e931 +#define pci_ss_info_1458_e931 pci_ss_info_1814_0201_1458_e931 +static const pciSubsystemInfo pci_ss_info_1814_0201_1462_6835 = + {0x1462, 0x6835, pci_subsys_1814_0201_1462_6835, 0}; +#undef pci_ss_info_1462_6835 +#define pci_ss_info_1462_6835 pci_ss_info_1814_0201_1462_6835 +static const pciSubsystemInfo pci_ss_info_1814_0201_1737_0032 = + {0x1737, 0x0032, pci_subsys_1814_0201_1737_0032, 0}; +#undef pci_ss_info_1737_0032 +#define pci_ss_info_1737_0032 pci_ss_info_1814_0201_1737_0032 +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_700a = + {0x1799, 0x700a, pci_subsys_1814_0201_1799_700a, 0}; +#undef pci_ss_info_1799_700a +#define pci_ss_info_1799_700a pci_ss_info_1814_0201_1799_700a +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_701a = + {0x1799, 0x701a, pci_subsys_1814_0201_1799_701a, 0}; +#undef pci_ss_info_1799_701a +#define pci_ss_info_1799_701a pci_ss_info_1814_0201_1799_701a +static const pciSubsystemInfo pci_ss_info_1814_0201_185f_22a0 = + {0x185f, 0x22a0, pci_subsys_1814_0201_185f_22a0, 0}; +#undef pci_ss_info_185f_22a0 +#define pci_ss_info_185f_22a0 pci_ss_info_1814_0201_185f_22a0 +static const pciSubsystemInfo pci_ss_info_1814_0301_2561_1814 = + {0x2561, 0x1814, pci_subsys_1814_0301_2561_1814, 0}; +#undef pci_ss_info_2561_1814 +#define pci_ss_info_2561_1814 pci_ss_info_1814_0301_2561_1814 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c006_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c006_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c006_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c006_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c006_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c006_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c006_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c006_18ec_d004 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c058_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c058_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c058_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c058_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c058_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c058_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c058_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c058_18ec_d004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_3388_0021_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_3388_0021_4c53_1050 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_3388_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_3388_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_3388_0021_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_3388_0021_4c53_1090 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_3388_0021_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_3388_0021_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3010 = + {0x4c53, 0x3010, pci_subsys_3388_0021_4c53_3010, 0}; +#undef pci_ss_info_4c53_3010 +#define pci_ss_info_4c53_3010 pci_ss_info_3388_0021_4c53_3010 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3011 = + {0x4c53, 0x3011, pci_subsys_3388_0021_4c53_3011, 0}; +#undef pci_ss_info_4c53_3011 +#define pci_ss_info_4c53_3011 pci_ss_info_3388_0021_4c53_3011 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_4000 = + {0x4c53, 0x4000, pci_subsys_3388_0021_4c53_4000, 0}; +#undef pci_ss_info_4c53_4000 +#define pci_ss_info_4c53_4000 pci_ss_info_3388_0021_4c53_4000 +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0002_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0002_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0002_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0003_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0003_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0003_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0006_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0006_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0006_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0006_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0008_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0008_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0008_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0009_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0009_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_3d3d_0009_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_3d3d_0009_13e9_1000 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0003 = + {0x0070, 0x0003, pci_subsys_4444_0016_0070_0003, 0}; +#undef pci_ss_info_0070_0003 +#define pci_ss_info_0070_0003 pci_ss_info_4444_0016_0070_0003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0009 = + {0x0070, 0x0009, pci_subsys_4444_0016_0070_0009, 0}; +#undef pci_ss_info_0070_0009 +#define pci_ss_info_0070_0009 pci_ss_info_4444_0016_0070_0009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0801 = + {0x0070, 0x0801, pci_subsys_4444_0016_0070_0801, 0}; +#undef pci_ss_info_0070_0801 +#define pci_ss_info_0070_0801 pci_ss_info_4444_0016_0070_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0807 = + {0x0070, 0x0807, pci_subsys_4444_0016_0070_0807, 0}; +#undef pci_ss_info_0070_0807 +#define pci_ss_info_0070_0807 pci_ss_info_4444_0016_0070_0807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0016_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0016_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4009 = + {0x0070, 0x4009, pci_subsys_4444_0016_0070_4009, 0}; +#undef pci_ss_info_0070_4009 +#define pci_ss_info_0070_4009 pci_ss_info_4444_0016_0070_4009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4801 = + {0x0070, 0x4801, pci_subsys_4444_0016_0070_4801, 0}; +#undef pci_ss_info_0070_4801 +#define pci_ss_info_0070_4801 pci_ss_info_4444_0016_0070_4801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4803 = + {0x0070, 0x4803, pci_subsys_4444_0016_0070_4803, 0}; +#undef pci_ss_info_0070_4803 +#define pci_ss_info_0070_4803 pci_ss_info_4444_0016_0070_4803 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8003 = + {0x0070, 0x8003, pci_subsys_4444_0016_0070_8003, 0}; +#undef pci_ss_info_0070_8003 +#define pci_ss_info_0070_8003 pci_ss_info_4444_0016_0070_8003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8801 = + {0x0070, 0x8801, pci_subsys_4444_0016_0070_8801, 0}; +#undef pci_ss_info_0070_8801 +#define pci_ss_info_0070_8801 pci_ss_info_4444_0016_0070_8801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_c801 = + {0x0070, 0xc801, pci_subsys_4444_0016_0070_c801, 0}; +#undef pci_ss_info_0070_c801 +#define pci_ss_info_0070_c801 pci_ss_info_4444_0016_0070_c801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e807 = + {0x0070, 0xe807, pci_subsys_4444_0016_0070_e807, 0}; +#undef pci_ss_info_0070_e807 +#define pci_ss_info_0070_e807 pci_ss_info_4444_0016_0070_e807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e817 = + {0x0070, 0xe817, pci_subsys_4444_0016_0070_e817, 0}; +#undef pci_ss_info_0070_e817 +#define pci_ss_info_0070_e817 pci_ss_info_4444_0016_0070_e817 +static const pciSubsystemInfo pci_ss_info_4444_0016_0270_0801 = + {0x0270, 0x0801, pci_subsys_4444_0016_0270_0801, 0}; +#undef pci_ss_info_0270_0801 +#define pci_ss_info_0270_0801 pci_ss_info_4444_0016_0270_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_fff3 = + {0x12ab, 0xfff3, pci_subsys_4444_0016_12ab_fff3, 0}; +#undef pci_ss_info_12ab_fff3 +#define pci_ss_info_12ab_fff3 pci_ss_info_4444_0016_12ab_fff3 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_ffff = + {0x12ab, 0xffff, pci_subsys_4444_0016_12ab_ffff, 0}; +#undef pci_ss_info_12ab_ffff +#define pci_ss_info_12ab_ffff pci_ss_info_4444_0016_12ab_ffff +static const pciSubsystemInfo pci_ss_info_4444_0016_4070_8801 = + {0x4070, 0x8801, pci_subsys_4444_0016_4070_8801, 0}; +#undef pci_ss_info_4070_8801 +#define pci_ss_info_4070_8801 pci_ss_info_4444_0016_4070_8801 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0092 = + {0x9005, 0x0092, pci_subsys_4444_0016_9005_0092, 0}; +#undef pci_ss_info_9005_0092 +#define pci_ss_info_9005_0092 pci_ss_info_4444_0016_9005_0092 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0093 = + {0x9005, 0x0093, pci_subsys_4444_0016_9005_0093, 0}; +#undef pci_ss_info_9005_0093 +#define pci_ss_info_9005_0093 pci_ss_info_4444_0016_9005_0093 +static const pciSubsystemInfo pci_ss_info_4444_0016_ff92_0070 = + {0xff92, 0x0070, pci_subsys_4444_0016_ff92_0070, 0}; +#undef pci_ss_info_ff92_0070 +#define pci_ss_info_ff92_0070 pci_ss_info_4444_0016_ff92_0070 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4000 = + {0x0070, 0x4000, pci_subsys_4444_0803_0070_4000, 0}; +#undef pci_ss_info_0070_4000 +#define pci_ss_info_0070_4000 pci_ss_info_4444_0803_0070_4000 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0803_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0803_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4800 = + {0x0070, 0x4800, pci_subsys_4444_0803_0070_4800, 0}; +#undef pci_ss_info_0070_4800 +#define pci_ss_info_0070_4800 pci_ss_info_4444_0803_0070_4800 +static const pciSubsystemInfo pci_ss_info_4444_0803_12ab_0000 = + {0x12ab, 0x0000, pci_subsys_4444_0803_12ab_0000, 0}; +#undef pci_ss_info_12ab_0000 +#define pci_ss_info_12ab_0000 pci_ss_info_4444_0803_12ab_0000 +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3ce = + {0x1461, 0xa3ce, pci_subsys_4444_0803_1461_a3ce, 0}; +#undef pci_ss_info_1461_a3ce +#define pci_ss_info_1461_a3ce pci_ss_info_4444_0803_1461_a3ce +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3cf = + {0x1461, 0xa3cf, pci_subsys_4444_0803_1461_a3cf, 0}; +#undef pci_ss_info_1461_a3cf +#define pci_ss_info_1461_a3cf pci_ss_info_4444_0803_1461_a3cf +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3000 = + {0x4c53, 0x3000, pci_subsys_4c53_0000_4c53_3000, 0}; +#undef pci_ss_info_4c53_3000 +#define pci_ss_info_4c53_3000 pci_ss_info_4c53_0000_4c53_3000 +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3001 = + {0x4c53, 0x3001, pci_subsys_4c53_0000_4c53_3001, 0}; +#undef pci_ss_info_4c53_3001 +#define pci_ss_info_4c53_3001 pci_ss_info_4c53_0000_4c53_3001 +static const pciSubsystemInfo pci_ss_info_4c53_0001_4c53_3002 = + {0x4c53, 0x3002, pci_subsys_4c53_0001_4c53_3002, 0}; +#undef pci_ss_info_4c53_3002 +#define pci_ss_info_4c53_3002 pci_ss_info_4c53_0001_4c53_3002 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8110 = + {0x1033, 0x8110, pci_subsys_5333_8a22_1033_8110, 0}; +#undef pci_ss_info_1033_8110 +#define pci_ss_info_1033_8110 pci_ss_info_5333_8a22_1033_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c12_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c12_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c12_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01af = + {0x8086, 0x01af, pci_subsys_8086_0600_8086_01af, 0}; +#undef pci_ss_info_8086_01af +#define pci_ss_info_8086_01af pci_ss_info_8086_0600_8086_01af +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01c1 = + {0x8086, 0x01c1, pci_subsys_8086_0600_8086_01c1, 0}; +#undef pci_ss_info_8086_01c1 +#define pci_ss_info_8086_01c1 pci_ss_info_8086_0600_8086_01c1 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01f7 = + {0x8086, 0x01f7, pci_subsys_8086_0600_8086_01f7, 0}; +#undef pci_ss_info_8086_01f7 +#define pci_ss_info_8086_01f7 pci_ss_info_8086_0600_8086_01f7 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1001_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1001_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_1008_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_1008_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_1008_1028_011c = + {0x1028, 0x011c, pci_subsys_8086_1008_1028_011c, 0}; +#undef pci_ss_info_1028_011c +#define pci_ss_info_1028_011c pci_ss_info_8086_1008_1028_011c +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_3108 = + {0x8086, 0x3108, pci_subsys_8086_1008_8086_3108, 0}; +#undef pci_ss_info_8086_3108 +#define pci_ss_info_8086_3108 pci_ss_info_8086_1008_8086_3108 +static const pciSubsystemInfo pci_ss_info_8086_1009_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1009_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1009_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100d_1028_0123 = + {0x1028, 0x0123, pci_subsys_8086_100d_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_8086_100d_1028_0123 +static const pciSubsystemInfo pci_ss_info_8086_100d_1079_891f = + {0x1079, 0x891f, pci_subsys_8086_100d_1079_891f, 0}; +#undef pci_ss_info_1079_891f +#define pci_ss_info_1079_891f pci_ss_info_8086_100d_1079_891f +static const pciSubsystemInfo pci_ss_info_8086_100d_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_100d_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_100d_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_100d_8086_110d = + {0x8086, 0x110d, pci_subsys_8086_100d_8086_110d, 0}; +#undef pci_ss_info_8086_110d +#define pci_ss_info_8086_110d pci_ss_info_8086_100d_8086_110d +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_100e_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_100e_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_100e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_100e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_100e_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_100e_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_100e_1024_0134 = + {0x1024, 0x0134, pci_subsys_8086_100e_1024_0134, 0}; +#undef pci_ss_info_1024_0134 +#define pci_ss_info_1024_0134 pci_ss_info_8086_100e_1024_0134 +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_002e = + {0x1028, 0x002e, pci_subsys_8086_100e_1028_002e, 0}; +#undef pci_ss_info_1028_002e +#define pci_ss_info_1028_002e pci_ss_info_8086_100e_1028_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0151 = + {0x1028, 0x0151, pci_subsys_8086_100e_1028_0151, 0}; +#undef pci_ss_info_1028_0151 +#define pci_ss_info_1028_0151 pci_ss_info_8086_100e_1028_0151 +static const pciSubsystemInfo pci_ss_info_8086_100e_107b_8920 = + {0x107b, 0x8920, pci_subsys_8086_100e_107b_8920, 0}; +#undef pci_ss_info_107b_8920 +#define pci_ss_info_107b_8920 pci_ss_info_8086_100e_107b_8920 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_100e_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_100e_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_100e_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_100e_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_100f_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_100f_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_028e = + {0x1014, 0x028e, pci_subsys_8086_100f_1014_028e, 0}; +#undef pci_ss_info_1014_028e +#define pci_ss_info_1014_028e pci_ss_info_8086_100f_1014_028e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_100f_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_100f_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_0e11_00db = + {0x0e11, 0x00db, pci_subsys_8086_1010_0e11_00db, 0}; +#undef pci_ss_info_0e11_00db +#define pci_ss_info_0e11_00db pci_ss_info_8086_1010_0e11_00db +static const pciSubsystemInfo pci_ss_info_8086_1010_1014_027c = + {0x1014, 0x027c, pci_subsys_8086_1010_1014_027c, 0}; +#undef pci_ss_info_1014_027c +#define pci_ss_info_1014_027c pci_ss_info_8086_1010_1014_027c +static const pciSubsystemInfo pci_ss_info_8086_1010_18fb_7872 = + {0x18fb, 0x7872, pci_subsys_8086_1010_18fb_7872, 0}; +#undef pci_ss_info_18fb_7872 +#define pci_ss_info_18fb_7872 pci_ss_info_8086_1010_18fb_7872 +static const pciSubsystemInfo pci_ss_info_8086_1010_1fc1_0026 = + {0x1fc1, 0x0026, pci_subsys_8086_1010_1fc1_0026, 0}; +#undef pci_ss_info_1fc1_0026 +#define pci_ss_info_1fc1_0026 pci_ss_info_8086_1010_1fc1_0026 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1010_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1010_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_1010_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_1010_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1010_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1010_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_1010_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_1010_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_1010_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_1010_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_1011_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1011_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1011_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1011_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1011_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1012_0e11_00dc = + {0x0e11, 0x00dc, pci_subsys_8086_1012_0e11_00dc, 0}; +#undef pci_ss_info_0e11_00dc +#define pci_ss_info_0e11_00dc pci_ss_info_8086_1012_0e11_00dc +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1013_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1013_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1013_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1013_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1113 = + {0x8086, 0x1113, pci_subsys_8086_1013_8086_1113, 0}; +#undef pci_ss_info_8086_1113 +#define pci_ss_info_8086_1113 pci_ss_info_8086_1013_8086_1113 +static const pciSubsystemInfo pci_ss_info_8086_1016_1014_052c = + {0x1014, 0x052c, pci_subsys_8086_1016_1014_052c, 0}; +#undef pci_ss_info_1014_052c +#define pci_ss_info_1014_052c pci_ss_info_8086_1016_1014_052c +static const pciSubsystemInfo pci_ss_info_8086_1016_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1016_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1016_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1016_8086_1016 = + {0x8086, 0x1016, pci_subsys_8086_1016_8086_1016, 0}; +#undef pci_ss_info_8086_1016 +#define pci_ss_info_8086_1016 pci_ss_info_8086_1016_8086_1016 +static const pciSubsystemInfo pci_ss_info_8086_1017_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1017_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1017_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1018_8086_1018 = + {0x8086, 0x1018, pci_subsys_8086_1018_8086_1018, 0}; +#undef pci_ss_info_8086_1018 +#define pci_ss_info_8086_1018 pci_ss_info_8086_1018_8086_1018 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_1019 = + {0x1458, 0x1019, pci_subsys_8086_1019_1458_1019, 0}; +#undef pci_ss_info_1458_1019 +#define pci_ss_info_1458_1019 pci_ss_info_8086_1019_1458_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_e000 = + {0x1458, 0xe000, pci_subsys_8086_1019_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_8086_1019_1458_e000 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_1019 = + {0x8086, 0x1019, pci_subsys_8086_1019_8086_1019, 0}; +#undef pci_ss_info_8086_1019 +#define pci_ss_info_8086_1019 pci_ss_info_8086_1019_8086_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_301f = + {0x8086, 0x301f, pci_subsys_8086_1019_8086_301f, 0}; +#undef pci_ss_info_8086_301f +#define pci_ss_info_8086_301f pci_ss_info_8086_1019_8086_301f +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1019_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1019_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_101d_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_101d_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_101d_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_101e_1014_0549 = + {0x1014, 0x0549, pci_subsys_8086_101e_1014_0549, 0}; +#undef pci_ss_info_1014_0549 +#define pci_ss_info_1014_0549 pci_ss_info_8086_101e_1014_0549 +static const pciSubsystemInfo pci_ss_info_8086_101e_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_101e_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_101e_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_101e_8086_101e = + {0x8086, 0x101e, pci_subsys_8086_101e_8086_101e, 0}; +#undef pci_ss_info_8086_101e +#define pci_ss_info_8086_101e pci_ss_info_8086_101e_8086_101e +static const pciSubsystemInfo pci_ss_info_8086_1026_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_1026_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_1026_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1026_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1026_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1026_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1026_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1026_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1026_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1026 = + {0x8086, 0x1026, pci_subsys_8086_1026_8086_1026, 0}; +#undef pci_ss_info_8086_1026 +#define pci_ss_info_8086_1026 pci_ss_info_8086_1026_8086_1026 +static const pciSubsystemInfo pci_ss_info_8086_1027_103c_3103 = + {0x103c, 0x3103, pci_subsys_8086_1027_103c_3103, 0}; +#undef pci_ss_info_103c_3103 +#define pci_ss_info_103c_3103 pci_ss_info_8086_1027_103c_3103 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1027_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1027_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1027_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1027_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1027_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1027_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1027 = + {0x8086, 0x1027, pci_subsys_8086_1027_8086_1027, 0}; +#undef pci_ss_info_8086_1027 +#define pci_ss_info_8086_1027 pci_ss_info_8086_1027_8086_1027 +static const pciSubsystemInfo pci_ss_info_8086_1028_8086_1028 = + {0x8086, 0x1028, pci_subsys_8086_1028_8086_1028, 0}; +#undef pci_ss_info_8086_1028 +#define pci_ss_info_8086_1028 pci_ss_info_8086_1028_8086_1028 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1031_813c_104d = + {0x813c, 0x104d, pci_subsys_8086_1031_813c_104d, 0}; +#undef pci_ss_info_813c_104d +#define pci_ss_info_813c_104d pci_ss_info_8086_1031_813c_104d +static const pciSubsystemInfo pci_ss_info_8086_1038_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_8086_1038_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_8086_1038_0e11_0098 +static const pciSubsystemInfo pci_ss_info_8086_1039_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_1039_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_1039_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1043_8086_2527 = + {0x8086, 0x2527, pci_subsys_8086_1043_8086_2527, 0}; +#undef pci_ss_info_8086_2527 +#define pci_ss_info_8086_2527 pci_ss_info_8086_1043_8086_2527 +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a01f = + {0x8086, 0xa01f, pci_subsys_8086_1048_8086_a01f, 0}; +#undef pci_ss_info_8086_a01f +#define pci_ss_info_8086_a01f pci_ss_info_8086_1048_8086_a01f +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a11f = + {0x8086, 0xa11f, pci_subsys_8086_1048_8086_a11f, 0}; +#undef pci_ss_info_8086_a11f +#define pci_ss_info_8086_a11f pci_ss_info_8086_1048_8086_a11f +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_728c = + {0x1462, 0x728c, pci_subsys_8086_1050_1462_728c, 0}; +#undef pci_ss_info_1462_728c +#define pci_ss_info_1462_728c pci_ss_info_8086_1050_1462_728c +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_758c = + {0x1462, 0x758c, pci_subsys_8086_1050_1462_758c, 0}; +#undef pci_ss_info_1462_758c +#define pci_ss_info_1462_758c pci_ss_info_8086_1050_1462_758c +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3020 = + {0x8086, 0x3020, pci_subsys_8086_1050_8086_3020, 0}; +#undef pci_ss_info_8086_3020 +#define pci_ss_info_8086_3020 pci_ss_info_8086_1050_8086_3020 +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_302f = + {0x8086, 0x302f, pci_subsys_8086_1050_8086_302f, 0}; +#undef pci_ss_info_8086_302f +#define pci_ss_info_8086_302f pci_ss_info_8086_1050_8086_302f +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1050_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1050_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_1064_1043_80f8 = + {0x1043, 0x80f8, pci_subsys_8086_1064_1043_80f8, 0}; +#undef pci_ss_info_1043_80f8 +#define pci_ss_info_1043_80f8 pci_ss_info_8086_1064_1043_80f8 +static const pciSubsystemInfo pci_ss_info_8086_1075_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1075_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1075_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_0075 = + {0x8086, 0x0075, pci_subsys_8086_1075_8086_0075, 0}; +#undef pci_ss_info_8086_0075 +#define pci_ss_info_8086_0075 pci_ss_info_8086_1075_8086_0075 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_1075 = + {0x8086, 0x1075, pci_subsys_8086_1075_8086_1075, 0}; +#undef pci_ss_info_8086_1075 +#define pci_ss_info_8086_1075 pci_ss_info_8086_1075_8086_1075 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1076_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1076_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_1076_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_1076_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_0076 = + {0x8086, 0x0076, pci_subsys_8086_1076_8086_0076, 0}; +#undef pci_ss_info_8086_0076 +#define pci_ss_info_8086_0076 pci_ss_info_8086_1076_8086_0076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1076 = + {0x8086, 0x1076, pci_subsys_8086_1076_8086_1076, 0}; +#undef pci_ss_info_8086_1076 +#define pci_ss_info_8086_1076 pci_ss_info_8086_1076_8086_1076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1176 = + {0x8086, 0x1176, pci_subsys_8086_1076_8086_1176, 0}; +#undef pci_ss_info_8086_1176 +#define pci_ss_info_8086_1176 pci_ss_info_8086_1076_8086_1176 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1276 = + {0x8086, 0x1276, pci_subsys_8086_1076_8086_1276, 0}; +#undef pci_ss_info_8086_1276 +#define pci_ss_info_8086_1276 pci_ss_info_8086_1076_8086_1276 +static const pciSubsystemInfo pci_ss_info_8086_1077_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1077_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1077_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_0077 = + {0x8086, 0x0077, pci_subsys_8086_1077_8086_0077, 0}; +#undef pci_ss_info_8086_0077 +#define pci_ss_info_8086_0077 pci_ss_info_8086_1077_8086_0077 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_1077 = + {0x8086, 0x1077, pci_subsys_8086_1077_8086_1077, 0}; +#undef pci_ss_info_8086_1077 +#define pci_ss_info_8086_1077 pci_ss_info_8086_1077_8086_1077 +static const pciSubsystemInfo pci_ss_info_8086_1078_8086_1078 = + {0x8086, 0x1078, pci_subsys_8086_1078_8086_1078, 0}; +#undef pci_ss_info_8086_1078 +#define pci_ss_info_8086_1078 pci_ss_info_8086_1078_8086_1078 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12a6 = + {0x103c, 0x12a6, pci_subsys_8086_1079_103c_12a6, 0}; +#undef pci_ss_info_103c_12a6 +#define pci_ss_info_103c_12a6 pci_ss_info_8086_1079_103c_12a6 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12cf = + {0x103c, 0x12cf, pci_subsys_8086_1079_103c_12cf, 0}; +#undef pci_ss_info_103c_12cf +#define pci_ss_info_103c_12cf pci_ss_info_8086_1079_103c_12cf +static const pciSubsystemInfo pci_ss_info_8086_1079_1fc1_0027 = + {0x1fc1, 0x0027, pci_subsys_8086_1079_1fc1_0027, 0}; +#undef pci_ss_info_1fc1_0027 +#define pci_ss_info_1fc1_0027 pci_ss_info_8086_1079_1fc1_0027 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1079_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1079_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_1079_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_1079_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_0079 = + {0x8086, 0x0079, pci_subsys_8086_1079_8086_0079, 0}; +#undef pci_ss_info_8086_0079 +#define pci_ss_info_8086_0079 pci_ss_info_8086_1079_8086_0079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1079 = + {0x8086, 0x1079, pci_subsys_8086_1079_8086_1079, 0}; +#undef pci_ss_info_8086_1079 +#define pci_ss_info_8086_1079 pci_ss_info_8086_1079_8086_1079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1179 = + {0x8086, 0x1179, pci_subsys_8086_1079_8086_1179, 0}; +#undef pci_ss_info_8086_1179 +#define pci_ss_info_8086_1179 pci_ss_info_8086_1079_8086_1179 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_117a = + {0x8086, 0x117a, pci_subsys_8086_1079_8086_117a, 0}; +#undef pci_ss_info_8086_117a +#define pci_ss_info_8086_117a pci_ss_info_8086_1079_8086_117a +static const pciSubsystemInfo pci_ss_info_8086_107a_103c_12a8 = + {0x103c, 0x12a8, pci_subsys_8086_107a_103c_12a8, 0}; +#undef pci_ss_info_103c_12a8 +#define pci_ss_info_103c_12a8 pci_ss_info_8086_107a_103c_12a8 +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_107a = + {0x8086, 0x107a, pci_subsys_8086_107a_8086_107a, 0}; +#undef pci_ss_info_8086_107a +#define pci_ss_info_8086_107a pci_ss_info_8086_107a_8086_107a +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_127a = + {0x8086, 0x127a, pci_subsys_8086_107a_8086_127a, 0}; +#undef pci_ss_info_8086_127a +#define pci_ss_info_8086_127a pci_ss_info_8086_107a_8086_127a +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_007b = + {0x8086, 0x007b, pci_subsys_8086_107b_8086_007b, 0}; +#undef pci_ss_info_8086_007b +#define pci_ss_info_8086_007b pci_ss_info_8086_107b_8086_007b +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_107b = + {0x8086, 0x107b, pci_subsys_8086_107b_8086_107b, 0}; +#undef pci_ss_info_8086_107b +#define pci_ss_info_8086_107b pci_ss_info_8086_107b_8086_107b +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1130_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1130_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1130_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1130_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1132_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1132_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_1132_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_1132_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1132_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1132_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_1209_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_1209_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_1209_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_1209_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1070 = + {0x4c53, 0x1070, pci_subsys_8086_1209_4c53_1070, 0}; +#undef pci_ss_info_4c53_1070 +#define pci_ss_info_4c53_1070 pci_ss_info_8086_1209_4c53_1070 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_00ce = + {0x1028, 0x00ce, pci_subsys_8086_1229_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_8086_1229_1028_00ce +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_108e_10cf = + {0x108e, 0x10cf, pci_subsys_8086_1229_108e_10cf, 0}; +#undef pci_ss_info_108e_10cf +#define pci_ss_info_108e_10cf pci_ss_info_8086_1229_108e_10cf +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_110a_008b = + {0x110a, 0x008b, pci_subsys_8086_1229_110a_008b, 0}; +#undef pci_ss_info_110a_008b +#define pci_ss_info_110a_008b pci_ss_info_8086_1229_110a_008b +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_8086_1229_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_8086_1229_13e9_1000 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1229_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1229_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_1229_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_1229_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3411 = + {0x8086, 0x3411, pci_subsys_8086_1229_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_8086_1229_8086_3411 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1461_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1461_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1461_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_8086_1960_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_8086_1960_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_8086_1960_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_8086_1960_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1040 = + {0xe4bf, 0x1040, pci_subsys_8086_1960_e4bf_1040, 0}; +#undef pci_ss_info_e4bf_1040 +#define pci_ss_info_e4bf_1040 pci_ss_info_8086_1960_e4bf_1040 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_3100 = + {0xe4bf, 0x3100, pci_subsys_8086_1960_e4bf_3100, 0}; +#undef pci_ss_info_e4bf_3100 +#define pci_ss_info_e4bf_3100 pci_ss_info_8086_1960_e4bf_3100 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1a30_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_1a30_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_1a30_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_110a_0051 = + {0x110a, 0x0051, pci_subsys_8086_2415_110a_0051, 0}; +#undef pci_ss_info_110a_0051 +#define pci_ss_info_110a_0051 pci_ss_info_8086_2415_110a_0051 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2415_1734_1025 = + {0x1734, 0x1025, pci_subsys_8086_2415_1734_1025, 0}; +#undef pci_ss_info_1734_1025 +#define pci_ss_info_1734_1025 pci_ss_info_8086_2415_1734_1025 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2442_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2442_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2442_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2442_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2442_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2442_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2442_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2442_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2442_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2443_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2443_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2443_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2443_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2443_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2443_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2444_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2444_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2444_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2444_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2444_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2444_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2444_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2445_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2445_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2448_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2448_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2448_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2448_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_2448_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_2448_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_2449_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_2449_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2449_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2449_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_2449_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_2449_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1179_ff01 = + {0x1179, 0xff01, pci_subsys_8086_2449_1179_ff01, 0}; +#undef pci_ss_info_1179_ff01 +#define pci_ss_info_1179_ff01 pci_ss_info_8086_2449_1179_ff01 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_244b_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_244b_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_244b_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_244b_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_244b_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_244b_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_244e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_244e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_244e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2482_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2482_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2482_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2482_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2482_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_2482_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_2482_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2484_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2484_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1013_5959 = + {0x1013, 0x5959, pci_subsys_8086_2485_1013_5959, 0}; +#undef pci_ss_info_1013_5959 +#define pci_ss_info_1013_5959 pci_ss_info_8086_2485_1013_5959 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_101f_1025 = + {0x101f, 0x1025, pci_subsys_8086_2486_101f_1025, 0}; +#undef pci_ss_info_101f_1025 +#define pci_ss_info_101f_1025 pci_ss_info_8086_2486_101f_1025 +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_2486_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_2486_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2487_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2487_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_248a_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_248a_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_248a_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_248a_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c0_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c0_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c2_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c2_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c2_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c2_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c2_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c2_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c2_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c2_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c2_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c2_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c2_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c2_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c2_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c2_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c2_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c2_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c2_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c2_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c2_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c2_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c2_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c2_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c2_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c2_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c2_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c2_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c3_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c3_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c3_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c3_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c3_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c3_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c3_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c3_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c3_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c3_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c3_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c3_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c3_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24c3_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24c3_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c3_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c3_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c3_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c3_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c3_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c4_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c4_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c4_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c4_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c4_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c4_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c4_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c4_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c4_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c4_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c4_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c4_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c4_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c4_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c4_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c4_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c4_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c4_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c4_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c4_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c4_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c4_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c4_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c5_0e11_00b8 = + {0x0e11, 0x00b8, pci_subsys_8086_24c5_0e11_00b8, 0}; +#undef pci_ss_info_0e11_00b8 +#define pci_ss_info_0e11_00b8 pci_ss_info_8086_24c5_0e11_00b8 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c5_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c5_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c5_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c5_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24c5_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24c5_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c5_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c5_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c5_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c5_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c5_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c5_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c5_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c5_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c5_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c5_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24c5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24c5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c5_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c5_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c6_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c6_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c6_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c6_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c6_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c6_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c6_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c6_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c6_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c6_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c6_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c7_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c7_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c7_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c7_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c7_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c7_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c7_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c7_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c7_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c7_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c7_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c7_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c7_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c7_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c7_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c7_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c7_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c7_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c7_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c7_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c7_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c7_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c7_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c7_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24ca_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24ca_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24ca_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24ca_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24ca_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24ca_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24ca_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24ca_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24ca_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24ca_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24ca_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24ca_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24ca_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24ca_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24ca_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24ca_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24ca_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cb_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cb_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cb_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cb_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24cb_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24cb_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cb_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cb_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24cc_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cc_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cc_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cd_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cd_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24cd_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24cd_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_011d = + {0x1028, 0x011d, pci_subsys_8086_24cd_1028_011d, 0}; +#undef pci_ss_info_1028_011d +#define pci_ss_info_1028_011d pci_ss_info_8086_24cd_1028_011d +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cd_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cd_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24cd_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24cd_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24cd_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24cd_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24cd_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24cd_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24cd_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24cd_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24cd_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24cd_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24cd_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24cd_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1509_1968 = + {0x1509, 0x1968, pci_subsys_8086_24cd_1509_1968, 0}; +#undef pci_ss_info_1509_1968 +#define pci_ss_info_1509_1968 pci_ss_info_8086_24cd_1509_1968 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cd_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cd_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cd_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cd_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d1_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d1_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d1_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d1_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d1_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d1_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d1_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d1_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d1_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d1_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1458_24d1 = + {0x1458, 0x24d1, pci_subsys_8086_24d1_1458_24d1, 0}; +#undef pci_ss_info_1458_24d1 +#define pci_ss_info_1458_24d1 pci_ss_info_8086_24d1_1458_24d1 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d1_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d1_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d1_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d1_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d1_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d1_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d1_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d1_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d1_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d1_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d1_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d2_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d2_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d2_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d2_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d2_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d2_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d2_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d2_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d2_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d2_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d2_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d2_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d2_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d2_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d2_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d2_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d2_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d2_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d2_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d2_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d2_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d2_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d2_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d2_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d2_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d2_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d2_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d2_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d2_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d2_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d2_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d3_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d3_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d3_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d3_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d3_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d3_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d3_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d3_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d3_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d3_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d3_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d3_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d3_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d3_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d3_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d3_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d3_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d3_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d3_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d3_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d4_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d4_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d4_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d4_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d4_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d4_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d4_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d4_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d4_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d4_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d4_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d4_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d4_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d4_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d4_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d4_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d4_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d4_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d4_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d4_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d4_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d4_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d4_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d4_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d4_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d4_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d4_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d4_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d4_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d4_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d4_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d5_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d5_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d5_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d5_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d5_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d5_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d5_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_80f3 = + {0x1043, 0x80f3, pci_subsys_8086_24d5_1043_80f3, 0}; +#undef pci_ss_info_1043_80f3 +#define pci_ss_info_1043_80f3 pci_ss_info_8086_24d5_1043_80f3 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_810f = + {0x1043, 0x810f, pci_subsys_8086_24d5_1043_810f, 0}; +#undef pci_ss_info_1043_810f +#define pci_ss_info_1043_810f pci_ss_info_8086_24d5_1043_810f +static const pciSubsystemInfo pci_ss_info_8086_24d5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24d5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24d5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_0080 = + {0x1462, 0x0080, pci_subsys_8086_24d5_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_8086_24d5_1462_0080 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d5_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d5_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_a000 = + {0x8086, 0xa000, pci_subsys_8086_24d5_8086_a000, 0}; +#undef pci_ss_info_8086_a000 +#define pci_ss_info_8086_a000 pci_ss_info_8086_24d5_8086_a000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e000 = + {0x8086, 0xe000, pci_subsys_8086_24d5_8086_e000, 0}; +#undef pci_ss_info_8086_e000 +#define pci_ss_info_8086_e000 pci_ss_info_8086_24d5_8086_e000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e001 = + {0x8086, 0xe001, pci_subsys_8086_24d5_8086_e001, 0}; +#undef pci_ss_info_8086_e001 +#define pci_ss_info_8086_e001 pci_ss_info_8086_24d5_8086_e001 +static const pciSubsystemInfo pci_ss_info_8086_24d6_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d6_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d6_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d7_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d7_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d7_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d7_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d7_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d7_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d7_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d7_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d7_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d7_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d7_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d7_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d7_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d7_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d7_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d7_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d7_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d7_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d7_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d7_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d7_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d7_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d7_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d7_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d7_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d7_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d7_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d7_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24db_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24db_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24db_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24db_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24db_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24db_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24db_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24db_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24db_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24db_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24db_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24db_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24db_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24db_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24db_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24db_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24db_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24db_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24db_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_24db_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_24db_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_24db_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24db_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24db_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24db_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24db_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24db_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_24db = + {0x8086, 0x24db, pci_subsys_8086_24db_8086_24db, 0}; +#undef pci_ss_info_8086_24db +#define pci_ss_info_8086_24db pci_ss_info_8086_24db_8086_24db +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24db_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24db_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24db_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24db_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24db_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24db_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24dd_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24dd_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24dd_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24dd_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24dd_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24dd_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24dd_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24dd_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24dd_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24dd_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24dd_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24dd_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24dd_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24dd_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24dd_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24dd_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_24dd_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_24dd_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24dd_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24dd_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24dd_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24dd_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24dd_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24dd_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24dd_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24dd_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24de_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24de_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24de_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24de_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24de_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24de_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24de_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24de_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24de_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24de_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24de_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24de_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24de_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24de_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24de_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24de_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24de_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24de_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24de_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24de_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24de_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24de_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24de_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24de_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24de_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24de_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24de_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2541_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2541_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_2541_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2541_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2541_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2544_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2544_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2544_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_254c_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_254c_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_254c_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_254c_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2560_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_2560_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_2560_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_2560_1458_2560 = + {0x1458, 0x2560, pci_subsys_8086_2560_1458_2560, 0}; +#undef pci_ss_info_1458_2560 +#define pci_ss_info_1458_2560 pci_ss_info_8086_2560_1458_2560 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_2562_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2562_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2562_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2570_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_2570_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_2570_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_2570_1043_80f2 = + {0x1043, 0x80f2, pci_subsys_8086_2570_1043_80f2, 0}; +#undef pci_ss_info_1043_80f2 +#define pci_ss_info_1043_80f2 pci_ss_info_8086_2570_1043_80f2 +static const pciSubsystemInfo pci_ss_info_8086_2570_1458_2570 = + {0x1458, 0x2570, pci_subsys_8086_2570_1458_2570, 0}; +#undef pci_ss_info_1458_2570 +#define pci_ss_info_1458_2570 pci_ss_info_8086_2570_1458_2570 +static const pciSubsystemInfo pci_ss_info_8086_2572_1028_019d = + {0x1028, 0x019d, pci_subsys_8086_2572_1028_019d, 0}; +#undef pci_ss_info_1028_019d +#define pci_ss_info_1028_019d pci_ss_info_8086_2572_1028_019d +static const pciSubsystemInfo pci_ss_info_8086_2572_1043_80a5 = + {0x1043, 0x80a5, pci_subsys_8086_2572_1043_80a5, 0}; +#undef pci_ss_info_1043_80a5 +#define pci_ss_info_1043_80a5 pci_ss_info_8086_2572_1043_80a5 +static const pciSubsystemInfo pci_ss_info_8086_2578_1458_2578 = + {0x1458, 0x2578, pci_subsys_8086_2578_1458_2578, 0}; +#undef pci_ss_info_1458_2578 +#define pci_ss_info_1458_2578 pci_ss_info_8086_2578_1458_2578 +static const pciSubsystemInfo pci_ss_info_8086_2578_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_2578_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_2578_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_2578_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_2578_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_2578_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1458_2580 = + {0x1458, 0x2580, pci_subsys_8086_2580_1458_2580, 0}; +#undef pci_ss_info_1458_2580 +#define pci_ss_info_1458_2580 pci_ss_info_8086_2580_1458_2580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2580_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2580_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2580_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2580_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2580_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2582_1028_1079 = + {0x1028, 0x1079, pci_subsys_8086_2582_1028_1079, 0}; +#undef pci_ss_info_1028_1079 +#define pci_ss_info_1028_1079 pci_ss_info_8086_2582_1028_1079 +static const pciSubsystemInfo pci_ss_info_8086_2582_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2582_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2582_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1458_2582 = + {0x1458, 0x2582, pci_subsys_8086_2582_1458_2582, 0}; +#undef pci_ss_info_1458_2582 +#define pci_ss_info_1458_2582 pci_ss_info_8086_2582_1458_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2582_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2582_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2590_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2590_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2590_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2590_a304_81b7 = + {0xa304, 0x81b7, pci_subsys_8086_2590_a304_81b7, 0}; +#undef pci_ss_info_a304_81b7 +#define pci_ss_info_a304_81b7 pci_ss_info_8086_2590_a304_81b7 +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2592_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2592_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2592_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2592_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2592_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a2_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a2_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a2_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a2_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a3_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a3_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a3_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a3_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a3_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a3_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a4_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a4_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a4_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a4_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a4_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a4_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a6_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a6_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a6_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a9_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a9_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a9_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a9_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a9_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a9_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25aa_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25aa_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25aa_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25aa_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ab_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ab_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ab_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ab_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ab_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ab_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ac_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ac_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ac_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ac_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ac_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ac_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ad_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ad_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ad_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ad_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ad_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ad_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25b0_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25b0_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25b0_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25b0_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_2640_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2640_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2640_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2640_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2640_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2640_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2641_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2641_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2641_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2651_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2651_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2651_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2651_1043_2601 = + {0x1043, 0x2601, pci_subsys_8086_2651_1043_2601, 0}; +#undef pci_ss_info_1043_2601 +#define pci_ss_info_1043_2601 pci_ss_info_8086_2651_1043_2601 +static const pciSubsystemInfo pci_ss_info_8086_2651_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2651_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2651_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2651_8086_4147 = + {0x8086, 0x4147, pci_subsys_8086_2651_8086_4147, 0}; +#undef pci_ss_info_8086_4147 +#define pci_ss_info_8086_4147 pci_ss_info_8086_2651_8086_4147 +static const pciSubsystemInfo pci_ss_info_8086_2652_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2652_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2652_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2658_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2658_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2658_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2658_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2658_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2658_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2658_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2658_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2658_1458_2558 = + {0x1458, 0x2558, pci_subsys_8086_2658_1458_2558, 0}; +#undef pci_ss_info_1458_2558 +#define pci_ss_info_1458_2558 pci_ss_info_8086_2658_1458_2558 +static const pciSubsystemInfo pci_ss_info_8086_2658_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2658_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2658_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2658_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2658_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2659_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2659_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2659_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2659_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2659_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2659_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2659_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2659_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2659_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2659_1458_2659 = + {0x1458, 0x2659, pci_subsys_8086_2659_1458_2659, 0}; +#undef pci_ss_info_1458_2659 +#define pci_ss_info_1458_2659 pci_ss_info_8086_2659_1458_2659 +static const pciSubsystemInfo pci_ss_info_8086_2659_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2659_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2659_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2659_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2659_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2659_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265a_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265a_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265a_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265a_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265a_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265a_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265b_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265b_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265b_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265b_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265b_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265b_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265b_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265b_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265b_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265b_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265b_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265b_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265b_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265b_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265b_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265b_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265b_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265b_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265c_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265c_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265c_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265c_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265c_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265c_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265c_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265c_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_265c_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_265c_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_265c_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265c_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265c_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265c_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265c_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265c_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2660_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2660_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2660_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2668_1043_814e = + {0x1043, 0x814e, pci_subsys_8086_2668_1043_814e, 0}; +#undef pci_ss_info_1043_814e +#define pci_ss_info_1043_814e pci_ss_info_8086_2668_1043_814e +static const pciSubsystemInfo pci_ss_info_8086_266a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266a_1458_266a = + {0x1458, 0x266a, pci_subsys_8086_266a_1458_266a, 0}; +#undef pci_ss_info_1458_266a +#define pci_ss_info_1458_266a pci_ss_info_8086_266a_1458_266a +static const pciSubsystemInfo pci_ss_info_8086_266a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_266d_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266d_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266d_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266d_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266d_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266d_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266e_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266e_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266e_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266e_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_266e_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_266e_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0188 = + {0x1028, 0x0188, pci_subsys_8086_266e_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_8086_266e_1028_0188 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266e_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_266e_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_266e_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_266e_1734_105a = + {0x1734, 0x105a, pci_subsys_8086_266e_1734_105a, 0}; +#undef pci_ss_info_1734_105a +#define pci_ss_info_1734_105a pci_ss_info_8086_266e_1734_105a +static const pciSubsystemInfo pci_ss_info_8086_266f_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266f_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266f_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266f_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266f_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266f_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266f_1458_266f = + {0x1458, 0x266f, pci_subsys_8086_266f_1458_266f, 0}; +#undef pci_ss_info_1458_266f +#define pci_ss_info_1458_266f pci_ss_info_8086_266f_1458_266f +static const pciSubsystemInfo pci_ss_info_8086_266f_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266f_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266f_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266f_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266f_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266f_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2770_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2770_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2770_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2772_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2772_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2772_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2782_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2782_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2782_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2782_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2782_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2782_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2792_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2792_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2792_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2792_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2792_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2792_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_27b8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27b8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27b8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c0_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c0_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c0_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c9_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c9_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c9_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27ca_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27ca_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27ca_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cb_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cb_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cb_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cc_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cc_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cc_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27da_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27da_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27da_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27dc_8086_308d = + {0x8086, 0x308d, pci_subsys_8086_27dc_8086_308d, 0}; +#undef pci_ss_info_8086_308d +#define pci_ss_info_8086_308d pci_ss_info_8086_27dc_8086_308d +static const pciSubsystemInfo pci_ss_info_8086_27df_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27df_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27df_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_3340_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_3340_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_3340_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_3340_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_3340_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_3340_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_3340_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_3575_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_3575_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_3575_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3580_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3580_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3580_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3580_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3580_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3580_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3580_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3580_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3580_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3580_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3580_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3580_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3580_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3581_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3581_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3581_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3582_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3582_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3582_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3582_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3582_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3582_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3582_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3582_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3584_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3584_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3584_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3584_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3584_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3584_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3584_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3584_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3584_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3584_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3584_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3584_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3584_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3585_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3585_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3585_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3585_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3585_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3585_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3585_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3585_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3585_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3585_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3585_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3585_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3585_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3590_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_3590_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_3590_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_3590_1734_103e = + {0x1734, 0x103e, pci_subsys_8086_3590_1734_103e, 0}; +#undef pci_ss_info_1734_103e +#define pci_ss_info_1734_103e pci_ss_info_8086_3590_1734_103e +static const pciSubsystemInfo pci_ss_info_8086_3590_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3590_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3590_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3591_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_3591_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_3591_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_3591_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3591_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3591_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3594_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3594_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3594_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_359e_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_359e_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_359e_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7110_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7110_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7110_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7111_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7111_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7111_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7112_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7112_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7112_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7113_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7113_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7113_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7120_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7120_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7120_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7120_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7121_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7121_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7121_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7121_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_8086_4341 = + {0x8086, 0x4341, pci_subsys_8086_7121_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_8086_7121_8086_4341 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7190_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7190_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_7190_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_7190_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_7190_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_7190_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7192_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_7192_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_7192_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7194_1033_0000 = + {0x1033, 0x0000, pci_subsys_8086_7194_1033_0000, 0}; +#undef pci_ss_info_1033_0000 +#define pci_ss_info_1033_0000 pci_ss_info_8086_7194_1033_0000 +static const pciSubsystemInfo pci_ss_info_8086_7194_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_7194_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_7194_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_7195_1033_80cc = + {0x1033, 0x80cc, pci_subsys_8086_7195_1033_80cc, 0}; +#undef pci_ss_info_1033_80cc +#define pci_ss_info_1033_80cc pci_ss_info_8086_7195_1033_80cc +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_71a0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_71a0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_71a0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_71a0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_71a2_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_71a2_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_71a2_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0ded = + {0x1993, 0x0ded, pci_subsys_8086_8500_1993_0ded, 0}; +#undef pci_ss_info_1993_0ded +#define pci_ss_info_1993_0ded pci_ss_info_8086_8500_1993_0ded +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0dee = + {0x1993, 0x0dee, pci_subsys_8086_8500_1993_0dee, 0}; +#undef pci_ss_info_1993_0dee +#define pci_ss_info_1993_0dee pci_ss_info_8086_8500_1993_0dee +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0def = + {0x1993, 0x0def, pci_subsys_8086_8500_1993_0def, 0}; +#undef pci_ss_info_1993_0def +#define pci_ss_info_1993_0def pci_ss_info_8086_8500_1993_0def +static const pciSubsystemInfo pci_ss_info_8086_b555_12d9_000a = + {0x12d9, 0x000a, pci_subsys_8086_b555_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_8086_b555_12d9_000a +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_b555_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_b555_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_b555_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_b555_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +#endif +#define pci_ss_list_0095_0680 NULL +#define pci_ss_list_018a_0106 NULL +#define pci_ss_list_021b_8139 NULL +#define pci_ss_list_0291_8212 NULL +#define pci_ss_list_02ac_1012 NULL +#define pci_ss_list_0357_000a NULL +#define pci_ss_list_0432_0001 NULL +#define pci_ss_list_045e_006e NULL +#define pci_ss_list_045e_00c2 NULL +#define pci_ss_list_04cf_8818 NULL +#define pci_ss_list_050d_7050 NULL +#define pci_ss_list_05e3_0701 NULL +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_0675_1703 NULL +#define pci_ss_list_0675_1704 NULL +#define pci_ss_list_067b_3507 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0b49_064f NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_0046[] = { + &pci_ss_info_0e11_0046_0e11_409a, + &pci_ss_info_0e11_0046_0e11_409b, + &pci_ss_info_0e11_0046_0e11_409c, + &pci_ss_info_0e11_0046_0e11_409d, + NULL +}; +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_005a NULL +#define pci_ss_list_0e11_007c NULL +#define pci_ss_list_0e11_007d NULL +#define pci_ss_list_0e11_0085 NULL +#define pci_ss_list_0e11_00b1 NULL +#define pci_ss_list_0e11_00bb NULL +#define pci_ss_list_0e11_00ca NULL +#define pci_ss_list_0e11_00cb NULL +#define pci_ss_list_0e11_00cf NULL +#define pci_ss_list_0e11_00d0 NULL +#define pci_ss_list_0e11_00d1 NULL +#define pci_ss_list_0e11_00e3 NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_4030 NULL +#define pci_ss_list_0e11_4031 NULL +#define pci_ss_list_0e11_4032 NULL +#define pci_ss_list_0e11_4033 NULL +#define pci_ss_list_0e11_4034 NULL +#define pci_ss_list_0e11_4040 NULL +#define pci_ss_list_0e11_4048 NULL +#define pci_ss_list_0e11_4050 NULL +#define pci_ss_list_0e11_4051 NULL +#define pci_ss_list_0e11_4058 NULL +#define pci_ss_list_0e11_4070 NULL +#define pci_ss_list_0e11_4080 NULL +#define pci_ss_list_0e11_4082 NULL +#define pci_ss_list_0e11_4083 NULL +#define pci_ss_list_0e11_4091 NULL +#define pci_ss_list_0e11_409a NULL +#define pci_ss_list_0e11_409b NULL +#define pci_ss_list_0e11_409c NULL +#define pci_ss_list_0e11_409d NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_b178[] = { + &pci_ss_info_0e11_b178_0e11_4080, + &pci_ss_info_0e11_b178_0e11_4082, + &pci_ss_info_0e11_b178_0e11_4083, + NULL +}; +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_b200 NULL +#define pci_ss_list_0e11_b203 NULL +#define pci_ss_list_0e11_b204 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0003[] = { + &pci_ss_info_1000_0003_1000_1000, + NULL +}; +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0006[] = { + &pci_ss_info_1000_0006_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000a[] = { + &pci_ss_info_1000_000a_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000b[] = { + &pci_ss_info_1000_000b_0e11_6004, + &pci_ss_info_1000_000b_1000_1000, + &pci_ss_info_1000_000b_1000_1010, + &pci_ss_info_1000_000b_1000_1020, + &pci_ss_info_1000_000b_13e9_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1000_1010, + &pci_ss_info_1000_000c_1000_1020, + &pci_ss_info_1000_000c_1de1_3906, + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1000_1000, + &pci_ss_info_1000_000f_1000_1010, + &pci_ss_info_1000_000f_1000_1020, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1de1_3904, + &pci_ss_info_1000_000f_4c53_1000, + &pci_ss_info_1000_000f_4c53_1050, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + &pci_ss_info_1000_0010_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0012[] = { + &pci_ss_info_1000_0012_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0013[] = { + &pci_ss_info_1000_0013_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1000_1000, + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0021[] = { + &pci_ss_info_1000_0021_1000_1000, + &pci_ss_info_1000_0021_1000_1010, + &pci_ss_info_1000_0021_124b_1070, + &pci_ss_info_1000_0021_4c53_1080, + &pci_ss_info_1000_0021_4c53_1300, + &pci_ss_info_1000_0021_4c53_1310, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_0e11_00da, + &pci_ss_info_1000_0030_1028_0123, + &pci_ss_info_1000_0030_1028_014a, + &pci_ss_info_1000_0030_1028_016c, + &pci_ss_info_1000_0030_1028_0183, + &pci_ss_info_1000_0030_1028_1010, + &pci_ss_info_1000_0030_124b_1170, + &pci_ss_info_1000_0030_1734_1052, + NULL +}; +#define pci_ss_list_1000_0031 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0032[] = { + &pci_ss_info_1000_0032_1000_1000, + NULL +}; +#define pci_ss_list_1000_0033 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0040[] = { + &pci_ss_info_1000_0040_1000_0033, + &pci_ss_info_1000_0040_1000_0066, + NULL +}; +#define pci_ss_list_1000_0041 NULL +#define pci_ss_list_1000_0050 NULL +#define pci_ss_list_1000_0054 NULL +#define pci_ss_list_1000_0056 NULL +#define pci_ss_list_1000_0058 NULL +#define pci_ss_list_1000_005a NULL +#define pci_ss_list_1000_005c NULL +#define pci_ss_list_1000_005e NULL +#define pci_ss_list_1000_0060 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0062[] = { + &pci_ss_info_1000_0062_1000_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0407[] = { + &pci_ss_info_1000_0407_1000_0530, + &pci_ss_info_1000_0407_1000_0531, + &pci_ss_info_1000_0407_1000_0532, + &pci_ss_info_1000_0407_1028_0531, + &pci_ss_info_1000_0407_1028_0533, + &pci_ss_info_1000_0407_8086_0530, + &pci_ss_info_1000_0407_8086_0532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0408[] = { + &pci_ss_info_1000_0408_1000_0001, + &pci_ss_info_1000_0408_1000_0002, + &pci_ss_info_1000_0408_1025_004d, + &pci_ss_info_1000_0408_1028_0001, + &pci_ss_info_1000_0408_1028_0002, + &pci_ss_info_1000_0408_1734_1065, + &pci_ss_info_1000_0408_8086_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0409[] = { + &pci_ss_info_1000_0409_1000_3004, + &pci_ss_info_1000_0409_1000_3008, + &pci_ss_info_1000_0409_8086_3008, + &pci_ss_info_1000_0409_8086_3431, + &pci_ss_info_1000_0409_8086_3499, + NULL +}; +#define pci_ss_list_1000_0621 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0622[] = { + &pci_ss_info_1000_0622_1000_1020, + NULL +}; +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0626[] = { + &pci_ss_info_1000_0626_1000_1010, + NULL +}; +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0640 NULL +#define pci_ss_list_1000_0642 NULL +#define pci_ss_list_1000_0646 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0804 NULL +#define pci_ss_list_1000_0805 NULL +#define pci_ss_list_1000_0806 NULL +#define pci_ss_list_1000_0807 NULL +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1000_0518, + &pci_ss_info_1000_1960_1000_0520, + &pci_ss_info_1000_1960_1000_0522, + &pci_ss_info_1000_1960_1000_0523, + &pci_ss_info_1000_1960_1000_4523, + &pci_ss_info_1000_1960_1000_a520, + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + &pci_ss_info_1000_1960_1028_0533, + &pci_ss_info_1000_1960_8086_0520, + &pci_ss_info_1000_1960_8086_0523, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_3150 NULL +#define pci_ss_list_1002_3152 NULL +#define pci_ss_list_1002_3154 NULL +#define pci_ss_list_1002_3e50 NULL +#define pci_ss_list_1002_3e54 NULL +#define pci_ss_list_1002_3e70 NULL +#define pci_ss_list_1002_4136 NULL +#define pci_ss_list_1002_4137 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4148 NULL +#define pci_ss_list_1002_4149 NULL +#define pci_ss_list_1002_414a NULL +#define pci_ss_list_1002_414b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4150[] = { + &pci_ss_info_1002_4150_1002_0002, + &pci_ss_info_1002_4150_1002_0003, + &pci_ss_info_1002_4150_1002_4722, + &pci_ss_info_1002_4150_1458_4024, + &pci_ss_info_1002_4150_148c_2064, + &pci_ss_info_1002_4150_148c_2066, + &pci_ss_info_1002_4150_174b_7c19, + &pci_ss_info_1002_4150_174b_7c29, + &pci_ss_info_1002_4150_17ee_2002, + &pci_ss_info_1002_4150_18bc_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4151[] = { + &pci_ss_info_1002_4151_1043_c004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4152[] = { + &pci_ss_info_1002_4152_1002_0002, + &pci_ss_info_1002_4152_1002_4772, + &pci_ss_info_1002_4152_1043_c002, + &pci_ss_info_1002_4152_1043_c01a, + &pci_ss_info_1002_4152_174b_7c29, + &pci_ss_info_1002_4152_1787_4002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4153[] = { + &pci_ss_info_1002_4153_1462_932c, + NULL +}; +#define pci_ss_list_1002_4154 NULL +#define pci_ss_list_1002_4155 NULL +#define pci_ss_list_1002_4156 NULL +#define pci_ss_list_1002_4157 NULL +#define pci_ss_list_1002_4158 NULL +#define pci_ss_list_1002_4164 NULL +#define pci_ss_list_1002_4165 NULL +#define pci_ss_list_1002_4166 NULL +#define pci_ss_list_1002_4168 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4170[] = { + &pci_ss_info_1002_4170_1002_0003, + &pci_ss_info_1002_4170_1002_4723, + &pci_ss_info_1002_4170_1458_4025, + &pci_ss_info_1002_4170_148c_2067, + &pci_ss_info_1002_4170_174b_7c28, + &pci_ss_info_1002_4170_17ee_2003, + &pci_ss_info_1002_4170_18bc_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4171[] = { + &pci_ss_info_1002_4171_1043_c005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4172[] = { + &pci_ss_info_1002_4172_1002_0003, + &pci_ss_info_1002_4172_1002_4773, + &pci_ss_info_1002_4172_1043_c003, + &pci_ss_info_1002_4172_1043_c01b, + &pci_ss_info_1002_4172_174b_7c28, + &pci_ss_info_1002_4172_1787_4003, + NULL +}; +#define pci_ss_list_1002_4173 NULL +#define pci_ss_list_1002_4237 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4243 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4336[] = { + &pci_ss_info_1002_4336_1002_4336, + &pci_ss_info_1002_4336_103c_0024, + &pci_ss_info_1002_4336_161f_2029, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4337[] = { + &pci_ss_info_1002_4337_1014_053a, + &pci_ss_info_1002_4337_103c_0850, + NULL +}; +#define pci_ss_list_1002_4341 NULL +#define pci_ss_list_1002_4345 NULL +#define pci_ss_list_1002_4347 NULL +#define pci_ss_list_1002_4348 NULL +#define pci_ss_list_1002_4349 NULL +#define pci_ss_list_1002_434d NULL +#define pci_ss_list_1002_4353 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4363 NULL +#define pci_ss_list_1002_436e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4370[] = { + &pci_ss_info_1002_4370_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4371[] = { + &pci_ss_info_1002_4371_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4372[] = { + &pci_ss_info_1002_4372_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4373[] = { + &pci_ss_info_1002_4373_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4374[] = { + &pci_ss_info_1002_4374_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4375[] = { + &pci_ss_info_1002_4375_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4376[] = { + &pci_ss_info_1002_4376_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4377[] = { + &pci_ss_info_1002_4377_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4378[] = { + &pci_ss_info_1002_4378_103c_308b, + NULL +}; +#define pci_ss_list_1002_4379 NULL +#define pci_ss_list_1002_437a NULL +#define pci_ss_list_1002_4437 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00ce, + &pci_ss_info_1002_4752_1028_00d1, + &pci_ss_info_1002_4752_1028_00d9, + &pci_ss_info_1002_4752_1028_0134, + &pci_ss_info_1002_4752_1734_007a, + &pci_ss_info_1002_4752_8086_3411, + &pci_ss_info_1002_4752_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0084, + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +#define pci_ss_list_1002_4a48 NULL +#define pci_ss_list_1002_4a49 NULL +#define pci_ss_list_1002_4a4a NULL +#define pci_ss_list_1002_4a4b NULL +#define pci_ss_list_1002_4a4c NULL +#define pci_ss_list_1002_4a4d NULL +#define pci_ss_list_1002_4a4e NULL +#define pci_ss_list_1002_4a50 NULL +#define pci_ss_list_1002_4a70 NULL +#define pci_ss_list_1002_4b49 NULL +#define pci_ss_list_1002_4b4b NULL +#define pci_ss_list_1002_4b4c NULL +#define pci_ss_list_1002_4b69 NULL +#define pci_ss_list_1002_4b6b NULL +#define pci_ss_list_1002_4b6c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e7, + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c46[] = { + &pci_ss_info_1002_4c46_1028_00b1, + NULL +}; +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_0e11_b160, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + &pci_ss_info_1002_4c4d_1028_00aa, + &pci_ss_info_1002_4c4d_1028_00bb, + &pci_ss_info_1002_4c4d_10e1_10cf, + &pci_ss_info_1002_4c4d_1179_ff00, + &pci_ss_info_1002_4c4d_13bd_1019, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c52[] = { + &pci_ss_info_1002_4c52_1033_8112, + NULL +}; +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_1028_012a, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_0e11_b111, + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + &pci_ss_info_1002_4c59_1509_1930, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4c6e NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e44[] = { + &pci_ss_info_1002_4e44_1002_515e, + &pci_ss_info_1002_4e44_1002_5965, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4e45[] = { + &pci_ss_info_1002_4e45_1002_0002, + &pci_ss_info_1002_4e45_1681_0002, + NULL +}; +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e48 NULL +#define pci_ss_list_1002_4e49 NULL +#define pci_ss_list_1002_4e4a NULL +#define pci_ss_list_1002_4e4b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e50[] = { + &pci_ss_info_1002_4e50_1025_005a, + &pci_ss_info_1002_4e50_103c_088c, + &pci_ss_info_1002_4e50_103c_0890, + &pci_ss_info_1002_4e50_1734_1055, + NULL +}; +#define pci_ss_list_1002_4e51 NULL +#define pci_ss_list_1002_4e52 NULL +#define pci_ss_list_1002_4e53 NULL +#define pci_ss_list_1002_4e54 NULL +#define pci_ss_list_1002_4e56 NULL +#define pci_ss_list_1002_4e64 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e65[] = { + &pci_ss_info_1002_4e65_1002_0003, + &pci_ss_info_1002_4e65_1681_0003, + NULL +}; +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_4e68 NULL +#define pci_ss_list_1002_4e69 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e6a[] = { + &pci_ss_info_1002_4e6a_1002_4e71, + NULL +}; +#define pci_ss_list_1002_4e71 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_1681_0010, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +#define pci_ss_list_1002_5154 NULL +#define pci_ss_list_1002_5155 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1002_103a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7146, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1014_029a, + &pci_ss_info_1002_5159_1014_02c8, + &pci_ss_info_1002_5159_1028_019a, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_174b_7c28, + &pci_ss_info_1002_5159_1787_0202, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_515e NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5346[] = { + &pci_ss_info_1002_5346_1002_0048, + NULL +}; +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +#define pci_ss_list_1002_5460 NULL +#define pci_ss_list_1002_5462 NULL +#define pci_ss_list_1002_5464 NULL +#define pci_ss_list_1002_5548 NULL +#define pci_ss_list_1002_5549 NULL +#define pci_ss_list_1002_554a NULL +#define pci_ss_list_1002_554b NULL +#define pci_ss_list_1002_554d NULL +#define pci_ss_list_1002_554f NULL +#define pci_ss_list_1002_5550 NULL +#define pci_ss_list_1002_5551 NULL +#define pci_ss_list_1002_5552 NULL +#define pci_ss_list_1002_5554 NULL +#define pci_ss_list_1002_556b NULL +#define pci_ss_list_1002_556d NULL +#define pci_ss_list_1002_556f NULL +#define pci_ss_list_1002_564a NULL +#define pci_ss_list_1002_564b NULL +#define pci_ss_list_1002_5652 NULL +#define pci_ss_list_1002_5653 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_5830 NULL +#define pci_ss_list_1002_5831 NULL +#define pci_ss_list_1002_5832 NULL +#define pci_ss_list_1002_5833 NULL +#define pci_ss_list_1002_5834 NULL +#define pci_ss_list_1002_5835 NULL +#define pci_ss_list_1002_5838 NULL +#define pci_ss_list_1002_5940 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5941[] = { + &pci_ss_info_1002_5941_1458_4019, + &pci_ss_info_1002_5941_174b_7c12, + &pci_ss_info_1002_5941_17af_200d, + &pci_ss_info_1002_5941_18bc_0050, + NULL +}; +#define pci_ss_list_1002_5944 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5950[] = { + &pci_ss_info_1002_5950_103c_308b, + NULL +}; +#define pci_ss_list_1002_5951 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5954[] = { + &pci_ss_info_1002_5954_1002_5954, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5955[] = { + &pci_ss_info_1002_5955_1002_5955, + &pci_ss_info_1002_5955_103c_308b, + NULL +}; +#define pci_ss_list_1002_5960 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5961[] = { + &pci_ss_info_1002_5961_1002_2f72, + &pci_ss_info_1002_5961_1019_4c30, + &pci_ss_info_1002_5961_12ab_5961, + &pci_ss_info_1002_5961_1458_4018, + &pci_ss_info_1002_5961_174b_7c13, + &pci_ss_info_1002_5961_17af_200c, + &pci_ss_info_1002_5961_18bc_0050, + &pci_ss_info_1002_5961_18bc_0051, + &pci_ss_info_1002_5961_18bc_0053, + NULL +}; +#define pci_ss_list_1002_5962 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5964[] = { + &pci_ss_info_1002_5964_1043_c006, + &pci_ss_info_1002_5964_1458_4018, + &pci_ss_info_1002_5964_147b_6191, + &pci_ss_info_1002_5964_148c_2073, + &pci_ss_info_1002_5964_174b_7c13, + &pci_ss_info_1002_5964_1787_5964, + &pci_ss_info_1002_5964_17af_2012, + &pci_ss_info_1002_5964_18bc_0170, + &pci_ss_info_1002_5964_18bc_0173, + NULL +}; +#define pci_ss_list_1002_5969 NULL +#define pci_ss_list_1002_5974 NULL +#define pci_ss_list_1002_5975 NULL +#define pci_ss_list_1002_5a34 NULL +#define pci_ss_list_1002_5a38 NULL +#define pci_ss_list_1002_5a3f NULL +#define pci_ss_list_1002_5a41 NULL +#define pci_ss_list_1002_5a42 NULL +#define pci_ss_list_1002_5a61 NULL +#define pci_ss_list_1002_5a62 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b60[] = { + &pci_ss_info_1002_5b60_1043_002a, + &pci_ss_info_1002_5b60_1043_032e, + &pci_ss_info_1002_5b60_1462_0402, + NULL +}; +#define pci_ss_list_1002_5b62 NULL +#define pci_ss_list_1002_5b63 NULL +#define pci_ss_list_1002_5b64 NULL +#define pci_ss_list_1002_5b65 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b70[] = { + &pci_ss_info_1002_5b70_1462_0403, + NULL +}; +#define pci_ss_list_1002_5b72 NULL +#define pci_ss_list_1002_5b73 NULL +#define pci_ss_list_1002_5b74 NULL +#define pci_ss_list_1002_5c61 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5c63[] = { + &pci_ss_info_1002_5c63_1002_5c63, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5d44[] = { + &pci_ss_info_1002_5d44_1458_4019, + &pci_ss_info_1002_5d44_174b_7c12, + &pci_ss_info_1002_5d44_1787_5965, + &pci_ss_info_1002_5d44_17af_2013, + &pci_ss_info_1002_5d44_18bc_0171, + &pci_ss_info_1002_5d44_18bc_0172, + NULL +}; +#define pci_ss_list_1002_5d48 NULL +#define pci_ss_list_1002_5d49 NULL +#define pci_ss_list_1002_5d4a NULL +#define pci_ss_list_1002_5d4d NULL +#define pci_ss_list_1002_5d4f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5d52[] = { + &pci_ss_info_1002_5d52_1002_0b12, + &pci_ss_info_1002_5d52_1002_0b13, + NULL +}; +#define pci_ss_list_1002_5d57 NULL +#define pci_ss_list_1002_5d6d NULL +#define pci_ss_list_1002_5d6f NULL +#define pci_ss_list_1002_5d72 NULL +#define pci_ss_list_1002_5d77 NULL +#define pci_ss_list_1002_5e48 NULL +#define pci_ss_list_1002_5e49 NULL +#define pci_ss_list_1002_5e4a NULL +#define pci_ss_list_1002_5e4b NULL +#define pci_ss_list_1002_5e4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e4d[] = { + &pci_ss_info_1002_5e4d_148c_2116, + NULL +}; +#define pci_ss_list_1002_5e4f NULL +#define pci_ss_list_1002_5e6b NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e6d[] = { + &pci_ss_info_1002_5e6d_148c_2117, + NULL +}; +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1002_7010 NULL +#define pci_ss_list_1002_7100 NULL +#define pci_ss_list_1002_7105 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7109[] = { + &pci_ss_info_1002_7109_1002_0322, + &pci_ss_info_1002_7109_1002_0d02, + NULL +}; +#define pci_ss_list_1002_7120 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7129[] = { + &pci_ss_info_1002_7129_1002_0323, + &pci_ss_info_1002_7129_1002_0d03, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7142[] = { + &pci_ss_info_1002_7142_1002_0322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7146[] = { + &pci_ss_info_1002_7146_1002_0322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7162[] = { + &pci_ss_info_1002_7162_1002_0323, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7166[] = { + &pci_ss_info_1002_7166_1002_0323, + NULL +}; +#define pci_ss_list_1002_71c0 NULL +#define pci_ss_list_1002_71c2 NULL +#define pci_ss_list_1002_71e0 NULL +#define pci_ss_list_1002_71e2 NULL +#define pci_ss_list_1002_7833 NULL +#define pci_ss_list_1002_7834 NULL +#define pci_ss_list_1002_7835 NULL +#define pci_ss_list_1002_7838 NULL +#define pci_ss_list_1002_7c37 NULL +#define pci_ss_list_1002_cab0 NULL +#define pci_ss_list_1002_cab2 NULL +#define pci_ss_list_1002_cab3 NULL +#define pci_ss_list_1002_cbb2 NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +static const pciSubsystemInfo *pci_ss_list_100b_0020[] = { + &pci_ss_info_100b_0020_103c_0024, + &pci_ss_info_100b_0020_12d9_000c, + &pci_ss_info_100b_0020_1385_f311, + NULL +}; +#define pci_ss_list_100b_0021 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0028 NULL +#define pci_ss_list_100b_002a NULL +#define pci_ss_list_100b_002b NULL +#define pci_ss_list_100b_002d NULL +#define pci_ss_list_100b_002e NULL +#define pci_ss_list_100b_002f NULL +#define pci_ss_list_100b_0030 NULL +#define pci_ss_list_100b_0035 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_0510 NULL +#define pci_ss_list_100b_0511 NULL +#define pci_ss_list_100b_0515 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +#define pci_ss_list_1011_000f NULL +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +#define pci_ss_list_1011_0017 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1186_1112, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_14cb_0100, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_4c53_1050, + &pci_ss_info_1011_0046_4c53_1051, + &pci_ss_info_1011_0046_9005_0364, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4000 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_153b_1136, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0031[] = { + &pci_ss_info_1014_0031_1014_0031, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_0037 NULL +#define pci_ss_list_1014_003a NULL +#define pci_ss_list_1014_003c NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0054 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_005e NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +#define pci_ss_list_1014_008b NULL +#define pci_ss_list_1014_008e NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0091 NULL +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_009f NULL +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1014_00b7[] = { + &pci_ss_info_1014_00b7_1092_00b8, + NULL +}; +#define pci_ss_list_1014_00b8 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0104 NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_015e NULL +#define pci_ss_list_1014_0160 NULL +#define pci_ss_list_1014_016e NULL +#define pci_ss_list_1014_0170 NULL +#define pci_ss_list_1014_017d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0180[] = { + &pci_ss_info_1014_0180_1014_0241, + &pci_ss_info_1014_0180_1014_0264, + NULL +}; +#define pci_ss_list_1014_0188 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_01c1 NULL +#define pci_ss_list_1014_01e6 NULL +#define pci_ss_list_1014_01ff NULL +static const pciSubsystemInfo *pci_ss_list_1014_0219[] = { + &pci_ss_info_1014_0219_1014_021a, + &pci_ss_info_1014_0219_1014_0251, + &pci_ss_info_1014_0219_1014_0252, + NULL +}; +#define pci_ss_list_1014_021b NULL +#define pci_ss_list_1014_021c NULL +#define pci_ss_list_1014_0233 NULL +#define pci_ss_list_1014_0266 NULL +#define pci_ss_list_1014_0268 NULL +#define pci_ss_list_1014_0269 NULL +static const pciSubsystemInfo *pci_ss_list_1014_028c[] = { + &pci_ss_info_1014_028c_1014_028d, + &pci_ss_info_1014_028c_1014_02be, + &pci_ss_info_1014_028c_1014_02c0, + &pci_ss_info_1014_028c_1014_030d, + NULL +}; +#define pci_ss_list_1014_02a1 NULL +static const pciSubsystemInfo *pci_ss_list_1014_02bd[] = { + &pci_ss_info_1014_02bd_1014_02c1, + &pci_ss_info_1014_02bd_1014_02c2, + NULL +}; +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_0314 NULL +#define pci_ss_list_1014_3022 NULL +#define pci_ss_list_1014_4022 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#define pci_ss_list_101e_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0477, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_101e_0494, + &pci_ss_info_101e_1960_101e_0503, + &pci_ss_info_101e_1960_101e_0511, + &pci_ss_info_101e_1960_101e_0522, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + &pci_ss_info_101e_1960_103c_60e7, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_1022_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + &pci_ss_info_1022_2000_1259_2702, + &pci_ss_info_1022_2000_1259_2703, + &pci_ss_info_1022_2000_4c53_1000, + &pci_ss_info_1022_2000_4c53_1010, + &pci_ss_info_1022_2000_4c53_1020, + &pci_ss_info_1022_2000_4c53_1030, + &pci_ss_info_1022_2000_4c53_1040, + &pci_ss_info_1022_2000_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2003 NULL +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_2081 NULL +#define pci_ss_list_1022_2082 NULL +#define pci_ss_list_1022_208f NULL +#define pci_ss_list_1022_2090 NULL +#define pci_ss_list_1022_2091 NULL +#define pci_ss_list_1022_2093 NULL +#define pci_ss_list_1022_2094 NULL +#define pci_ss_list_1022_2095 NULL +#define pci_ss_list_1022_2096 NULL +#define pci_ss_list_1022_2097 NULL +#define pci_ss_list_1022_209a NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700a NULL +#define pci_ss_list_1022_700b NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7458 NULL +#define pci_ss_list_1022_7459 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7460[] = { + &pci_ss_info_1022_7460_161f_3017, + NULL +}; +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7464[] = { + &pci_ss_info_1022_7464_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7468[] = { + &pci_ss_info_1022_7468_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7469[] = { + &pci_ss_info_1022_7469_1022_2b80, + &pci_ss_info_1022_7469_161f_3017, + NULL +}; +#define pci_ss_list_1022_746a NULL +static const pciSubsystemInfo *pci_ss_list_1022_746b[] = { + &pci_ss_info_1022_746b_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_746d[] = { + &pci_ss_info_1022_746d_161f_3017, + NULL +}; +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1022_756b NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +static const pciSubsystemInfo *pci_ss_list_1023_2001[] = { + &pci_ss_info_1023_2001_122d_1400, + NULL +}; +#define pci_ss_list_1023_2100 NULL +#define pci_ss_list_1023_2200 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + &pci_ss_info_1023_8620_1014_1025, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_1671 NULL +#define pci_ss_list_1025_1672 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +#define pci_ss_list_1028_0009 NULL +#define pci_ss_list_1028_000a NULL +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000d NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_1028_0010 NULL +#define pci_ss_list_1028_0011 NULL +#define pci_ss_list_1028_0012 NULL +static const pciSubsystemInfo *pci_ss_list_1028_0013[] = { + &pci_ss_info_1028_0013_1028_016c, + &pci_ss_info_1028_0013_1028_016d, + &pci_ss_info_1028_0013_1028_016e, + &pci_ss_info_1028_0013_1028_016f, + &pci_ss_info_1028_0013_1028_0170, + NULL +}; +#define pci_ss_list_1028_0014 NULL +#define pci_ss_list_1028_0015 NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102a_001f[] = { + &pci_ss_info_102a_001f_9005_000f, + &pci_ss_info_102a_001f_9005_0106, + &pci_ss_info_102a_001f_9005_a180, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00c5[] = { + &pci_ss_info_102a_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00cf[] = { + &pci_ss_info_102a_00cf_1028_0106, + &pci_ss_info_102a_00cf_1028_0121, + NULL +}; +#endif +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0100 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0d43, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + &pci_ss_info_102b_0527_102b_0850, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0528[] = { + &pci_ss_info_102b_0528_102b_1020, + &pci_ss_info_102b_0528_102b_1030, + &pci_ss_info_102b_0528_102b_14e1, + &pci_ss_info_102b_0528_102b_2021, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2537[] = { + &pci_ss_info_102b_2537_102b_1820, + &pci_ss_info_102b_2537_102b_1830, + &pci_ss_info_102b_2537_102b_1c10, + &pci_ss_info_102b_2537_102b_2811, + &pci_ss_info_102b_2537_102b_2c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2538[] = { + &pci_ss_info_102b_2538_102b_08c7, + &pci_ss_info_102b_2538_102b_0907, + &pci_ss_info_102b_2538_102b_1047, + &pci_ss_info_102b_2538_102b_1087, + &pci_ss_info_102b_2538_102b_2538, + &pci_ss_info_102b_2538_102b_3007, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + &pci_ss_info_102c_00c0_4c53_1000, + &pci_ss_info_102c_00c0_4c53_1010, + &pci_ss_info_102c_00c0_4c53_1020, + &pci_ss_info_102c_00c0_4c53_1030, + &pci_ss_info_102c_00c0_4c53_1050, + &pci_ss_info_102c_00c0_4c53_1051, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + &pci_ss_info_102c_00e5_1179_0001, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_102c_0c30[] = { + &pci_ss_info_102c_0c30_4c53_1000, + &pci_ss_info_102c_0c30_4c53_1050, + &pci_ss_info_102c_0c30_4c53_1051, + &pci_ss_info_102c_0c30_4c53_1080, + NULL +}; +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#define pci_ss_list_102f_000a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#define pci_ss_list_102f_0030 NULL +#define pci_ss_list_102f_0031 NULL +#define pci_ss_list_102f_0105 NULL +#define pci_ss_list_102f_0106 NULL +#define pci_ss_list_102f_0107 NULL +#define pci_ss_list_102f_0108 NULL +#define pci_ss_list_102f_0180 NULL +#define pci_ss_list_102f_0181 NULL +#define pci_ss_list_102f_0182 NULL +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0000 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1033_0035, + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_14c2_0105, + &pci_ss_info_1033_0035_1799_0001, + &pci_ss_info_1033_0035_1931_000a, + &pci_ss_info_1033_0035_1931_000b, + &pci_ss_info_1033_0035_807d_0035, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +#define pci_ss_list_1033_0072 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a5 NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +#define pci_ss_list_1033_00ce NULL +#define pci_ss_list_1033_00df NULL +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_14c2_0205, + &pci_ss_info_1033_00e0_1799_0002, + &pci_ss_info_1033_00e0_807d_1043, + NULL +}; +#define pci_ss_list_1033_00e7 NULL +#define pci_ss_list_1033_00f2 NULL +#define pci_ss_list_1033_00f3 NULL +#define pci_ss_list_1033_010c NULL +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0003 NULL +#define pci_ss_list_1039_0004 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_000a NULL +#define pci_ss_list_1039_0016 NULL +#define pci_ss_list_1039_0018 NULL +#define pci_ss_list_1039_0180 NULL +#define pci_ss_list_1039_0181 NULL +#define pci_ss_list_1039_0182 NULL +#define pci_ss_list_1039_0190 NULL +#define pci_ss_list_1039_0191 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0550 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0648 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0655 NULL +#define pci_ss_list_1039_0660 NULL +#define pci_ss_list_1039_0661 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0741 NULL +#define pci_ss_list_1039_0745 NULL +#define pci_ss_list_1039_0746 NULL +#define pci_ss_list_1039_0755 NULL +#define pci_ss_list_1039_0760 NULL +#define pci_ss_list_1039_0761 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1019_0a14, + &pci_ss_info_1039_0900_1039_0900, + &pci_ss_info_1039_0900_1043_8035, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_0963 NULL +#define pci_ss_list_1039_0964 NULL +#define pci_ss_list_1039_0965 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + &pci_ss_info_1039_5513_1043_8035, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + &pci_ss_info_1039_6300_1043_8035, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6330[] = { + &pci_ss_info_1039_6330_1039_6330, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1019_0a14, + &pci_ss_info_1039_7001_1039_7000, + &pci_ss_info_1039_7001_1462_5470, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7012[] = { + &pci_ss_info_1039_7012_15bd_1001, + NULL +}; +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_1039_7019 NULL +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1006 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_100a NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + &pci_ss_info_103c_1048_103c_1301, + NULL +}; +#define pci_ss_list_103c_1054 NULL +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_10f0 NULL +#define pci_ss_list_103c_10f1 NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_127c NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_1291 NULL +#define pci_ss_list_103c_12b4 NULL +#define pci_ss_list_103c_12fa NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_103c_3080 NULL +#define pci_ss_list_103c_3220 NULL +#define pci_ss_list_103c_3230 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043_0675[] = { + &pci_ss_info_1043_0675_0675_1704, + &pci_ss_info_1043_0675_0675_1707, + &pci_ss_info_1043_0675_10cf_105e, + NULL +}; +#define pci_ss_list_1043_4015 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1043_4057 NULL +#define pci_ss_list_1043_8043 NULL +#define pci_ss_list_1043_807b NULL +#define pci_ss_list_1043_80bb NULL +#define pci_ss_list_1043_80c5 NULL +#define pci_ss_list_1043_80df NULL +#define pci_ss_list_1043_8187 NULL +#define pci_ss_list_1043_8188 NULL +#endif +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1044_a511[] = { + &pci_ss_info_1044_a511_1044_c032, + &pci_ss_info_1044_a511_1044_c035, + NULL +}; +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0c60 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048_8901[] = { + &pci_ss_info_1048_8901_1048_0935, + NULL +}; +#endif +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0209 NULL +#define pci_ss_list_104a_020a NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_021a NULL +#define pci_ss_list_104a_021b NULL +#define pci_ss_list_104a_0500 NULL +#define pci_ss_list_104a_0564 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104a_55cc NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a34, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_1048_0a36, + &pci_ss_info_104c_3d07_1048_0a43, + &pci_ss_info_104c_3d07_1048_0a44, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8020[] = { + &pci_ss_info_104c_8020_11bd_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8023[] = { + &pci_ss_info_104c_8023_103c_088c, + &pci_ss_info_104c_8023_1043_808b, + NULL +}; +#define pci_ss_list_104c_8024 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8025[] = { + &pci_ss_info_104c_8025_1458_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8026[] = { + &pci_ss_info_104c_8026_103c_006a, + &pci_ss_info_104c_8026_1043_808d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8029[] = { + &pci_ss_info_104c_8029_1028_0163, + &pci_ss_info_104c_8029_1028_0196, + &pci_ss_info_104c_8029_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_802b[] = { + &pci_ss_info_104c_802b_1028_0139, + &pci_ss_info_104c_802b_1028_014e, + NULL +}; +#define pci_ss_list_104c_802e NULL +static const pciSubsystemInfo *pci_ss_list_104c_8031[] = { + &pci_ss_info_104c_8031_103c_099c, + &pci_ss_info_104c_8031_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8032[] = { + &pci_ss_info_104c_8032_103c_099c, + &pci_ss_info_104c_8032_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8033[] = { + &pci_ss_info_104c_8033_103c_099c, + &pci_ss_info_104c_8033_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8034[] = { + &pci_ss_info_104c_8034_103c_099c, + &pci_ss_info_104c_8034_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8035[] = { + &pci_ss_info_104c_8035_103c_099c, + NULL +}; +#define pci_ss_list_104c_8036 NULL +#define pci_ss_list_104c_8038 NULL +#define pci_ss_list_104c_8201 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8204[] = { + &pci_ss_info_104c_8204_1028_0139, + &pci_ss_info_104c_8204_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8400[] = { + &pci_ss_info_104c_8400_1186_3b00, + &pci_ss_info_104c_8400_1186_3b01, + &pci_ss_info_104c_8400_16ab_8501, + NULL +}; +#define pci_ss_list_104c_8401 NULL +#define pci_ss_list_104c_9000 NULL +#define pci_ss_list_104c_9065 NULL +static const pciSubsystemInfo *pci_ss_list_104c_9066[] = { + &pci_ss_info_104c_9066_104c_9066, + &pci_ss_info_104c_9066_1186_3b04, + &pci_ss_info_104c_9066_1186_3b05, + &pci_ss_info_104c_9066_13d1_aba0, + NULL +}; +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +static const pciSubsystemInfo *pci_ss_list_104c_a106[] = { + &pci_ss_info_104c_a106_175c_5000, + &pci_ss_info_104c_a106_175c_6400, + &pci_ss_info_104c_a106_175c_8700, + NULL +}; +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac16[] = { + &pci_ss_info_104c_ac16_1014_0092, + NULL +}; +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + &pci_ss_info_104c_ac1b_1014_0130, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac1c[] = { + &pci_ss_info_104c_ac1c_0e11_b121, + &pci_ss_info_104c_ac1c_1028_0088, + NULL +}; +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac44[] = { + &pci_ss_info_104c_ac44_1028_0163, + &pci_ss_info_104c_ac44_1028_0196, + &pci_ss_info_104c_ac44_1071_8160, + NULL +}; +#define pci_ss_list_104c_ac46 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac47[] = { + &pci_ss_info_104c_ac47_1028_0139, + &pci_ss_info_104c_ac47_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac4a[] = { + &pci_ss_info_104c_ac4a_1028_0139, + &pci_ss_info_104c_ac4a_1028_014e, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_0e11_004e, + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_1028_00b1, + &pci_ss_info_104c_ac51_1028_012a, + &pci_ss_info_104c_ac51_1033_80cd, + &pci_ss_info_104c_ac51_1095_10cf, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +#define pci_ss_list_104c_ac54 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac56[] = { + &pci_ss_info_104c_ac56_1014_0528, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac60[] = { + &pci_ss_info_104c_ac60_175c_5100, + &pci_ss_info_104c_ac60_175c_6100, + &pci_ss_info_104c_ac60_175c_6200, + &pci_ss_info_104c_ac60_175c_8800, + NULL +}; +#define pci_ss_list_104c_ac8d NULL +#define pci_ss_list_104c_ac8e NULL +#define pci_ss_list_104c_ac8f NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8004 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +static const pciSubsystemInfo *pci_ss_list_1050_6692[] = { + &pci_ss_info_1050_6692_1043_1702, + &pci_ss_info_1050_6692_1043_1703, + &pci_ss_info_1050_6692_1043_1707, + &pci_ss_info_1050_6692_144f_1702, + &pci_ss_info_1050_6692_144f_1703, + &pci_ss_info_1050_6692_144f_1707, + NULL +}; +#define pci_ss_list_1050_9921 NULL +#define pci_ss_list_1050_9922 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0008 NULL +#define pci_ss_list_1057_0009 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_14fb_0101, + &pci_ss_info_1057_1801_14fb_0102, + &pci_ss_info_1057_1801_14fb_0202, + &pci_ss_info_1057_1801_14fb_0611, + &pci_ss_info_1057_1801_14fb_0612, + &pci_ss_info_1057_1801_14fb_0613, + &pci_ss_info_1057_1801_14fb_0614, + &pci_ss_info_1057_1801_14fb_0621, + &pci_ss_info_1057_1801_14fb_0622, + &pci_ss_info_1057_1801_14fb_0810, + &pci_ss_info_1057_1801_175c_4200, + &pci_ss_info_1057_1801_175c_4300, + &pci_ss_info_1057_1801_175c_4400, + &pci_ss_info_1057_1801_ecc0_0010, + &pci_ss_info_1057_1801_ecc0_0020, + &pci_ss_info_1057_1801_ecc0_0030, + &pci_ss_info_1057_1801_ecc0_0031, + &pci_ss_info_1057_1801_ecc0_0040, + &pci_ss_info_1057_1801_ecc0_0041, + &pci_ss_info_1057_1801_ecc0_0050, + &pci_ss_info_1057_1801_ecc0_0051, + &pci_ss_info_1057_1801_ecc0_0070, + &pci_ss_info_1057_1801_ecc0_0071, + &pci_ss_info_1057_1801_ecc0_0072, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_18c1 NULL +static const pciSubsystemInfo *pci_ss_list_1057_3410[] = { + &pci_ss_info_1057_3410_ecc0_0050, + &pci_ss_info_1057_3410_ecc0_0051, + &pci_ss_info_1057_3410_ecc0_0060, + &pci_ss_info_1057_3410_ecc0_0070, + &pci_ss_info_1057_3410_ecc0_0071, + &pci_ss_info_1057_3410_ecc0_0072, + &pci_ss_info_1057_3410_ecc0_0080, + &pci_ss_info_1057_3410_ecc0_0081, + &pci_ss_info_1057_3410_ecc0_0090, + &pci_ss_info_1057_3410_ecc0_00a0, + &pci_ss_info_1057_3410_ecc0_00b0, + &pci_ss_info_1057_3410_ecc0_0100, + NULL +}; +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_5608 NULL +#define pci_ss_list_1057_5803 NULL +#define pci_ss_list_1057_5806 NULL +#define pci_ss_list_1057_5808 NULL +#define pci_ss_list_1057_6400 NULL +#define pci_ss_list_1057_6405 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3318 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3319[] = { + &pci_ss_info_105a_3319_8086_3427, + NULL +}; +#define pci_ss_list_105a_3371 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3373[] = { + &pci_ss_info_105a_3373_1043_80f5, + &pci_ss_info_105a_3373_1462_702e, + NULL +}; +#define pci_ss_list_105a_3375 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3376[] = { + &pci_ss_info_105a_3376_1043_809e, + NULL +}; +#define pci_ss_list_105a_3515 NULL +#define pci_ss_list_105a_3519 NULL +#define pci_ss_list_105a_3570 NULL +#define pci_ss_list_105a_3571 NULL +#define pci_ss_list_105a_3574 NULL +#define pci_ss_list_105a_3577 NULL +#define pci_ss_list_105a_3d17 NULL +#define pci_ss_list_105a_3d18 NULL +#define pci_ss_list_105a_3d73 NULL +#define pci_ss_list_105a_3d75 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d69[] = { + &pci_ss_info_105a_4d69_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_1043_807e, + &pci_ss_info_105a_5275_105a_0275, + &pci_ss_info_105a_5275_105a_1275, + &pci_ss_info_105a_5275_1458_b001, + NULL +}; +#define pci_ss_list_105a_5300 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6268[] = { + &pci_ss_info_105a_6268_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_6622 NULL +#define pci_ss_list_105a_6624 NULL +#define pci_ss_list_105a_6626 NULL +#define pci_ss_list_105a_6629 NULL +#define pci_ss_list_105a_7275 NULL +#define pci_ss_list_105a_8002 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_5348[] = { + &pci_ss_info_105d_5348_105d_0037, + NULL +}; +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_0301 NULL +#define pci_ss_list_1067_0304 NULL +#define pci_ss_list_1067_0308 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069_0050[] = { + &pci_ss_info_1069_0050_1069_0050, + &pci_ss_info_1069_0050_1069_0052, + &pci_ss_info_1069_0050_1069_0054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_b166[] = { + &pci_ss_info_1069_b166_1014_0242, + &pci_ss_info_1069_b166_1014_0266, + &pci_ss_info_1069_b166_1014_0278, + &pci_ss_info_1069_b166_1014_02d3, + &pci_ss_info_1069_b166_1014_02d4, + &pci_ss_info_1069_b166_1069_0200, + &pci_ss_info_1069_b166_1069_0202, + &pci_ss_info_1069_b166_1069_0204, + &pci_ss_info_1069_b166_1069_0206, + NULL +}; +#define pci_ss_list_1069_ba55 NULL +static const pciSubsystemInfo *pci_ss_list_1069_ba56[] = { + &pci_ss_info_1069_ba56_1069_0030, + &pci_ss_info_1069_ba56_1069_0040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_ba57[] = { + &pci_ss_info_1069_ba57_1069_0072, + NULL +}; +#endif +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000c NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b_0031[] = { + &pci_ss_info_106b_0031_106b_5811, + NULL +}; +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_0035 NULL +#define pci_ss_list_106b_0036 NULL +#define pci_ss_list_106b_003b NULL +#define pci_ss_list_106b_003e NULL +#define pci_ss_list_106b_003f NULL +#define pci_ss_list_106b_0040 NULL +#define pci_ss_list_106b_0041 NULL +#define pci_ss_list_106b_0042 NULL +#define pci_ss_list_106b_0043 NULL +#define pci_ss_list_106b_0045 NULL +#define pci_ss_list_106b_0046 NULL +#define pci_ss_list_106b_0047 NULL +#define pci_ss_list_106b_0048 NULL +#define pci_ss_list_106b_0049 NULL +#define pci_ss_list_106b_004b NULL +#define pci_ss_list_106b_004c NULL +#define pci_ss_list_106b_004f NULL +#define pci_ss_list_106b_0050 NULL +#define pci_ss_list_106b_0051 NULL +#define pci_ss_list_106b_0052 NULL +#define pci_ss_list_106b_0053 NULL +#define pci_ss_list_106b_0054 NULL +#define pci_ss_list_106b_0055 NULL +#define pci_ss_list_106b_0058 NULL +#define pci_ss_list_106b_0059 NULL +#define pci_ss_list_106b_0066 NULL +#define pci_ss_list_106b_0067 NULL +#define pci_ss_list_106b_0068 NULL +#define pci_ss_list_106b_0069 NULL +#define pci_ss_list_106b_006a NULL +#define pci_ss_list_106b_006b NULL +#define pci_ss_list_106b_1645 NULL +#endif +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1071_8160 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1077_2200[] = { + &pci_ss_info_1077_2200_1077_0002, + NULL +}; +#define pci_ss_list_1077_2300 NULL +#define pci_ss_list_1077_2312 NULL +#define pci_ss_list_1077_2322 NULL +#define pci_ss_list_1077_2422 NULL +#define pci_ss_list_1077_2432 NULL +#define pci_ss_list_1077_3010 NULL +#define pci_ss_list_1077_3022 NULL +#define pci_ss_list_1077_4010 NULL +#define pci_ss_list_1077_4022 NULL +#define pci_ss_list_1077_6312 NULL +#define pci_ss_list_1077_6322 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107d_2134 NULL +#define pci_ss_list_107d_2971 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_1648 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_8002 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_108e_a801 NULL +#define pci_ss_list_108e_abba NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1091_07a0 NULL +#define pci_ss_list_1091_1091 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1310 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_14e0 NULL +#define pci_ss_list_1093_14f0 NULL +#define pci_ss_list_1093_17d0 NULL +#define pci_ss_list_1093_1870 NULL +#define pci_ss_list_1093_1880 NULL +#define pci_ss_list_1093_18b0 NULL +#define pci_ss_list_1093_2410 NULL +#define pci_ss_list_1093_2890 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_2a70 NULL +#define pci_ss_list_1093_2a80 NULL +#define pci_ss_list_1093_2c80 NULL +#define pci_ss_list_1093_2ca0 NULL +#define pci_ss_list_1093_70a9 NULL +#define pci_ss_list_1093_70b8 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0240 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0648[] = { + &pci_ss_info_1095_0648_1043_8025, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0680[] = { + &pci_ss_info_1095_0680_1095_3680, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3112[] = { + &pci_ss_info_1095_3112_1095_3112, + &pci_ss_info_1095_3112_1095_6112, + &pci_ss_info_1095_3112_9005_0250, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3114[] = { + &pci_ss_info_1095_3114_1095_3114, + &pci_ss_info_1095_3114_1095_6114, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3124[] = { + &pci_ss_info_1095_3124_1095_3124, + NULL +}; +#define pci_ss_list_1095_3132 NULL +static const pciSubsystemInfo *pci_ss_list_1095_3512[] = { + &pci_ss_info_1095_3512_1095_3512, + &pci_ss_info_1095_3512_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_032e NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_0071_0101, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0002, + &pci_ss_info_109e_036e_1461_0003, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_1461_0761, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1822_0001, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_18ac_d500, + &pci_ss_info_109e_036e_270f_fc00, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_0071_0101, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0002, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_1461_0761, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_1822_0001, + &pci_ss_info_109e_0878_18ac_d500, + &pci_ss_info_109e_0878_270f_fc00, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_3052 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9_0009[] = { + &pci_ss_info_10a9_0009_10a9_8002, + NULL +}; +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_100a NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_4001 NULL +#define pci_ss_list_10a9_4002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#define pci_ss_list_10a9_8010 NULL +#define pci_ss_list_10a9_8018 NULL +#endif +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1042 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2540 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_6540[] = { + &pci_ss_info_10b5_6540_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6541[] = { + &pci_ss_info_10b5_6541_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6542[] = { + &pci_ss_info_10b5_6542_4c53_10e0, + NULL +}; +#define pci_ss_list_10b5_8111 NULL +#define pci_ss_list_10b5_8114 NULL +#define pci_ss_list_10b5_8516 NULL +#define pci_ss_list_10b5_8532 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_10b5_2862, + &pci_ss_info_10b5_9030_10b5_2906, + &pci_ss_info_10b5_9030_10b5_2940, + &pci_ss_info_10b5_9030_10b5_2977, + &pci_ss_info_10b5_9030_10b5_2978, + &pci_ss_info_10b5_9030_10b5_3025, + &pci_ss_info_10b5_9030_10b5_3068, + &pci_ss_info_10b5_9030_1397_3136, + &pci_ss_info_10b5_9030_1397_3137, + &pci_ss_info_10b5_9030_1518_0200, + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_1067, + &pci_ss_info_10b5_9050_10b5_1172, + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2221, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_2431, + &pci_ss_info_10b5_9050_10b5_2905, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1498_0362, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_2036, + &pci_ss_info_10b5_9050_5654_3132, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + &pci_ss_info_10b5_9054_10b5_2696, + &pci_ss_info_10b5_9054_10b5_2717, + &pci_ss_info_10b5_9054_10b5_2844, + &pci_ss_info_10b5_9054_12c7_4001, + &pci_ss_info_10b5_9054_12d9_0002, + &pci_ss_info_10b5_9054_16df_0011, + &pci_ss_info_10b5_9054_16df_0012, + &pci_ss_info_10b5_9054_16df_0013, + &pci_ss_info_10b5_9054_16df_0014, + &pci_ss_info_10b5_9054_16df_0015, + &pci_ss_info_10b5_9054_16df_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9056[] = { + &pci_ss_info_10b5_9056_10b5_2979, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_103c_10eb, + &pci_ss_info_10b5_9080_103c_10ec, + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + &pci_ss_info_10b5_9080_12d9_0002, + &pci_ss_info_10b5_9080_12df_4422, + NULL +}; +#define pci_ss_list_10b5_bb04 NULL +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_0013[] = { + &pci_ss_info_10b7_0013_10b7_2031, + NULL +}; +#define pci_ss_list_10b7_0910 NULL +#define pci_ss_list_10b7_1006 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_1201 NULL +#define pci_ss_list_10b7_1202 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1700[] = { + &pci_ss_info_10b7_1700_1043_80eb, + &pci_ss_info_10b7_1700_10b7_0010, + &pci_ss_info_10b7_1700_10b7_0020, + &pci_ss_info_10b7_1700_147b_1407, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6000 NULL +#define pci_ss_list_10b7_6001 NULL +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7770 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_80eb NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_1028_0097, + &pci_ss_info_10b7_9200_1028_00fe, + &pci_ss_info_10b7_9200_1028_012a, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + &pci_ss_info_10b7_9200_10f1_2466, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9201[] = { + &pci_ss_info_10b7_9201_1043_80ab, + NULL +}; +#define pci_ss_list_10b7_9202 NULL +#define pci_ss_list_10b7_9210 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990a NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_2802 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +#define pci_ss_list_10b9_0101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_0780 NULL +#define pci_ss_list_10b9_0782 NULL +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_1014_053b, + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1573 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1672 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_1689 NULL +#define pci_ss_list_10b9_1695 NULL +#define pci_ss_list_10b9_1697 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_3323 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +#define pci_ss_list_10b9_5228 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1014_050f, + &pci_ss_info_10b9_5229_1014_053d, + &pci_ss_info_10b9_5229_103c_0024, + &pci_ss_info_10b9_5229_1043_8053, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5237[] = { + &pci_ss_info_10b9_5237_1014_0540, + &pci_ss_info_10b9_5237_103c_0024, + &pci_ss_info_10b9_5237_104d_810f, + NULL +}; +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5246 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_524b NULL +#define pci_ss_list_10b9_524c NULL +#define pci_ss_list_10b9_524d NULL +#define pci_ss_list_10b9_524e NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +#define pci_ss_list_10b9_5263 NULL +#define pci_ss_list_10b9_5281 NULL +#define pci_ss_list_10b9_5287 NULL +#define pci_ss_list_10b9_5288 NULL +#define pci_ss_list_10b9_5289 NULL +#define pci_ss_list_10b9_5450 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + &pci_ss_info_10b9_5451_1014_053e, + &pci_ss_info_10b9_5451_103c_0024, + &pci_ss_info_10b9_5451_10b9_5451, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5457[] = { + &pci_ss_info_10b9_5457_1014_0535, + &pci_ss_info_10b9_5457_103c_0024, + NULL +}; +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5461 NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_1014_0510, + &pci_ss_info_10b9_7101_1014_053c, + &pci_ss_info_10b9_7101_103c_0024, + NULL +}; +#endif +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10ba_0304 NULL +#define pci_ss_list_10ba_0308 NULL +#define pci_ss_list_10ba_1002 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + &pci_ss_info_10c8_0005_1028_0088, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_0088, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cc_0660 NULL +#define pci_ss_list_10cc_0661 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0431 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8626 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10dd_0100 NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c19, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1048_0c1c, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1048_0c21, + &pci_ss_info_10de_0028_1048_0c28, + &pci_ss_info_10de_0028_1048_0c29, + &pci_ss_info_10de_0028_1048_0c2a, + &pci_ss_info_10de_0028_1048_0c2b, + &pci_ss_info_10de_0028_1048_0c31, + &pci_ss_info_10de_0028_1048_0c32, + &pci_ss_info_10de_0028_1048_0c33, + &pci_ss_info_10de_0028_1048_0c34, + &pci_ss_info_10de_0028_107d_2134, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1048_0c2e, + &pci_ss_info_10de_0029_1048_0c2f, + &pci_ss_info_10de_0029_1048_0c30, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1048_0c20, + &pci_ss_info_10de_002c_1048_0c21, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_1048_0c3b, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + &pci_ss_info_10de_002d_1569_002d, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +#define pci_ss_list_10de_0034 NULL +#define pci_ss_list_10de_0035 NULL +#define pci_ss_list_10de_0036 NULL +#define pci_ss_list_10de_0037 NULL +#define pci_ss_list_10de_0038 NULL +#define pci_ss_list_10de_003a NULL +#define pci_ss_list_10de_003b NULL +#define pci_ss_list_10de_003c NULL +#define pci_ss_list_10de_003d NULL +#define pci_ss_list_10de_003e NULL +#define pci_ss_list_10de_0040 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0041[] = { + &pci_ss_info_10de_0041_1043_817b, + NULL +}; +#define pci_ss_list_10de_0042 NULL +#define pci_ss_list_10de_0043 NULL +#define pci_ss_list_10de_0045 NULL +#define pci_ss_list_10de_0046 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0047[] = { + &pci_ss_info_10de_0047_1682_2109, + NULL +}; +#define pci_ss_list_10de_0048 NULL +#define pci_ss_list_10de_0049 NULL +#define pci_ss_list_10de_004e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0050[] = { + &pci_ss_info_10de_0050_1043_815a, + &pci_ss_info_10de_0050_1458_0c11, + &pci_ss_info_10de_0050_1462_7100, + NULL +}; +#define pci_ss_list_10de_0051 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0052[] = { + &pci_ss_info_10de_0052_1043_815a, + &pci_ss_info_10de_0052_1458_0c11, + &pci_ss_info_10de_0052_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0053[] = { + &pci_ss_info_10de_0053_1043_815a, + &pci_ss_info_10de_0053_1458_5002, + &pci_ss_info_10de_0053_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0054[] = { + &pci_ss_info_10de_0054_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0055[] = { + &pci_ss_info_10de_0055_1043_815a, + NULL +}; +#define pci_ss_list_10de_0056 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0057[] = { + &pci_ss_info_10de_0057_1043_8141, + &pci_ss_info_10de_0057_1458_e000, + &pci_ss_info_10de_0057_1462_7100, + NULL +}; +#define pci_ss_list_10de_0058 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0059[] = { + &pci_ss_info_10de_0059_1043_812a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005a[] = { + &pci_ss_info_10de_005a_1043_815a, + &pci_ss_info_10de_005a_1458_5004, + &pci_ss_info_10de_005a_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005b[] = { + &pci_ss_info_10de_005b_1043_815a, + &pci_ss_info_10de_005b_1458_5004, + &pci_ss_info_10de_005b_1462_7100, + NULL +}; +#define pci_ss_list_10de_005c NULL +#define pci_ss_list_10de_005d NULL +static const pciSubsystemInfo *pci_ss_list_10de_005e[] = { + &pci_ss_info_10de_005e_1458_5000, + &pci_ss_info_10de_005e_1462_7100, + NULL +}; +#define pci_ss_list_10de_005f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + NULL +}; +#define pci_ss_list_10de_0064 NULL +#define pci_ss_list_10de_0065 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0066[] = { + &pci_ss_info_10de_0066_1043_80a7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + NULL +}; +#define pci_ss_list_10de_006a NULL +static const pciSubsystemInfo *pci_ss_list_10de_006b[] = { + &pci_ss_info_10de_006b_10de_006b, + NULL +}; +#define pci_ss_list_10de_006c NULL +#define pci_ss_list_10de_006d NULL +#define pci_ss_list_10de_006e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0080[] = { + &pci_ss_info_10de_0080_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0084[] = { + &pci_ss_info_10de_0084_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0085[] = { + &pci_ss_info_10de_0085_147b_1c09, + NULL +}; +#define pci_ss_list_10de_0086 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0087[] = { + &pci_ss_info_10de_0087_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0088[] = { + &pci_ss_info_10de_0088_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_008a[] = { + &pci_ss_info_10de_008a_147b_1c09, + NULL +}; +#define pci_ss_list_10de_008b NULL +#define pci_ss_list_10de_008c NULL +#define pci_ss_list_10de_008e NULL +#define pci_ss_list_10de_0091 NULL +#define pci_ss_list_10de_0092 NULL +#define pci_ss_list_10de_0099 NULL +#define pci_ss_list_10de_009d NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +#define pci_ss_list_10de_00c0 NULL +#define pci_ss_list_10de_00c1 NULL +#define pci_ss_list_10de_00c2 NULL +#define pci_ss_list_10de_00c3 NULL +#define pci_ss_list_10de_00c8 NULL +#define pci_ss_list_10de_00c9 NULL +#define pci_ss_list_10de_00cc NULL +#define pci_ss_list_10de_00cd NULL +#define pci_ss_list_10de_00ce NULL +#define pci_ss_list_10de_00d0 NULL +#define pci_ss_list_10de_00d1 NULL +#define pci_ss_list_10de_00d2 NULL +#define pci_ss_list_10de_00d3 NULL +#define pci_ss_list_10de_00d4 NULL +#define pci_ss_list_10de_00d5 NULL +#define pci_ss_list_10de_00d6 NULL +#define pci_ss_list_10de_00d7 NULL +#define pci_ss_list_10de_00d8 NULL +#define pci_ss_list_10de_00d9 NULL +#define pci_ss_list_10de_00da NULL +#define pci_ss_list_10de_00dd NULL +static const pciSubsystemInfo *pci_ss_list_10de_00df[] = { + &pci_ss_info_10de_00df_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e0[] = { + &pci_ss_info_10de_00e0_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e1[] = { + &pci_ss_info_10de_00e1_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e2 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e3[] = { + &pci_ss_info_10de_00e3_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e4[] = { + &pci_ss_info_10de_00e4_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e5[] = { + &pci_ss_info_10de_00e5_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e6 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e7[] = { + &pci_ss_info_10de_00e7_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e8[] = { + &pci_ss_info_10de_00e8_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00ea[] = { + &pci_ss_info_10de_00ea_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00ed NULL +#define pci_ss_list_10de_00ee NULL +#define pci_ss_list_10de_00f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f1[] = { + &pci_ss_info_10de_00f1_1043_81a6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00f2[] = { + &pci_ss_info_10de_00f2_1682_211c, + NULL +}; +#define pci_ss_list_10de_00f3 NULL +#define pci_ss_list_10de_00f8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f9[] = { + &pci_ss_info_10de_00f9_1682_2120, + NULL +}; +#define pci_ss_list_10de_00fa NULL +#define pci_ss_list_10de_00fb NULL +#define pci_ss_list_10de_00fc NULL +#define pci_ss_list_10de_00fd NULL +#define pci_ss_list_10de_00fe NULL +#define pci_ss_list_10de_00ff NULL +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1048_0c41, + &pci_ss_info_10de_0100_1048_0c43, + &pci_ss_info_10de_0100_1048_0c48, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1048_0c42, + &pci_ss_info_10de_0101_107d_2822, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0103[] = { + &pci_ss_info_10de_0103_1048_0c40, + &pci_ss_info_10de_0103_1048_0c44, + &pci_ss_info_10de_0103_1048_0c45, + &pci_ss_info_10de_0103_1048_0c4a, + &pci_ss_info_10de_0103_1048_0c4b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1048_0c60, + &pci_ss_info_10de_0110_1048_0c61, + &pci_ss_info_10de_0110_1048_0c63, + &pci_ss_info_10de_0110_1048_0c64, + &pci_ss_info_10de_0110_1048_0c65, + &pci_ss_info_10de_0110_1048_0c66, + &pci_ss_info_10de_0110_10de_0091, + &pci_ss_info_10de_0110_10de_00a1, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +#define pci_ss_list_10de_0140 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0141[] = { + &pci_ss_info_10de_0141_1458_3124, + NULL +}; +#define pci_ss_list_10de_0142 NULL +#define pci_ss_list_10de_0144 NULL +#define pci_ss_list_10de_0145 NULL +#define pci_ss_list_10de_0146 NULL +#define pci_ss_list_10de_0147 NULL +#define pci_ss_list_10de_0148 NULL +#define pci_ss_list_10de_0149 NULL +#define pci_ss_list_10de_014e NULL +#define pci_ss_list_10de_014f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_1048_0c50, + &pci_ss_info_10de_0150_1048_0c52, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_107d_2842, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + &pci_ss_info_10de_0151_1462_5506, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0160 NULL +#define pci_ss_list_10de_0161 NULL +#define pci_ss_list_10de_0162 NULL +#define pci_ss_list_10de_0163 NULL +#define pci_ss_list_10de_0164 NULL +#define pci_ss_list_10de_0165 NULL +#define pci_ss_list_10de_0166 NULL +#define pci_ss_list_10de_0167 NULL +#define pci_ss_list_10de_0168 NULL +#define pci_ss_list_10de_0169 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_10b0_0002, + &pci_ss_info_10de_0171_10de_0008, + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_1462_8852, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0176[] = { + &pci_ss_info_10de_0176_4c53_1090, + NULL +}; +#define pci_ss_list_10de_0177 NULL +#define pci_ss_list_10de_0178 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0179[] = { + &pci_ss_info_10de_0179_10de_0179, + NULL +}; +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_017d NULL +static const pciSubsystemInfo *pci_ss_list_10de_0181[] = { + &pci_ss_info_10de_0181_1043_806f, + &pci_ss_info_10de_0181_1462_8880, + &pci_ss_info_10de_0181_1462_8900, + &pci_ss_info_10de_0181_1462_9350, + &pci_ss_info_10de_0181_147b_8f0d, + NULL +}; +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0185 NULL +#define pci_ss_list_10de_0186 NULL +#define pci_ss_list_10de_0187 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_018c NULL +#define pci_ss_list_10de_018d NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b0 NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +static const pciSubsystemInfo *pci_ss_list_10de_01e0[] = { + &pci_ss_info_10de_01e0_147b_1c09, + NULL +}; +#define pci_ss_list_10de_01e8 NULL +#define pci_ss_list_10de_01ea NULL +#define pci_ss_list_10de_01eb NULL +#define pci_ss_list_10de_01ec NULL +#define pci_ss_list_10de_01ed NULL +#define pci_ss_list_10de_01ee NULL +#define pci_ss_list_10de_01ef NULL +#define pci_ss_list_10de_01f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + &pci_ss_info_10de_0200_1048_0c70, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0211 NULL +#define pci_ss_list_10de_0212 NULL +#define pci_ss_list_10de_0215 NULL +#define pci_ss_list_10de_0221 NULL +#define pci_ss_list_10de_0240 NULL +#define pci_ss_list_10de_0241 NULL +#define pci_ss_list_10de_0242 NULL +#define pci_ss_list_10de_0243 NULL +#define pci_ss_list_10de_0244 NULL +#define pci_ss_list_10de_0245 NULL +#define pci_ss_list_10de_0246 NULL +#define pci_ss_list_10de_0247 NULL +#define pci_ss_list_10de_0248 NULL +#define pci_ss_list_10de_0249 NULL +#define pci_ss_list_10de_024a NULL +#define pci_ss_list_10de_024b NULL +#define pci_ss_list_10de_024c NULL +#define pci_ss_list_10de_024d NULL +#define pci_ss_list_10de_024e NULL +#define pci_ss_list_10de_024f NULL +#define pci_ss_list_10de_0250 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0251[] = { + &pci_ss_info_10de_0251_1043_8023, + NULL +}; +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +#define pci_ss_list_10de_0260 NULL +#define pci_ss_list_10de_0261 NULL +#define pci_ss_list_10de_0262 NULL +#define pci_ss_list_10de_0263 NULL +#define pci_ss_list_10de_0264 NULL +#define pci_ss_list_10de_0265 NULL +#define pci_ss_list_10de_0266 NULL +#define pci_ss_list_10de_0267 NULL +#define pci_ss_list_10de_0268 NULL +#define pci_ss_list_10de_0269 NULL +#define pci_ss_list_10de_026a NULL +#define pci_ss_list_10de_026b NULL +#define pci_ss_list_10de_026c NULL +#define pci_ss_list_10de_026d NULL +#define pci_ss_list_10de_026e NULL +#define pci_ss_list_10de_026f NULL +#define pci_ss_list_10de_0270 NULL +#define pci_ss_list_10de_0271 NULL +#define pci_ss_list_10de_0272 NULL +#define pci_ss_list_10de_027e NULL +#define pci_ss_list_10de_027f NULL +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0286 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_028c NULL +#define pci_ss_list_10de_02a0 NULL +#define pci_ss_list_10de_02f0 NULL +#define pci_ss_list_10de_02f1 NULL +#define pci_ss_list_10de_02f2 NULL +#define pci_ss_list_10de_02f3 NULL +#define pci_ss_list_10de_02f4 NULL +#define pci_ss_list_10de_02f5 NULL +#define pci_ss_list_10de_02f6 NULL +#define pci_ss_list_10de_02f7 NULL +#define pci_ss_list_10de_02f8 NULL +#define pci_ss_list_10de_02f9 NULL +#define pci_ss_list_10de_02fa NULL +#define pci_ss_list_10de_02fb NULL +#define pci_ss_list_10de_02fc NULL +#define pci_ss_list_10de_02fd NULL +#define pci_ss_list_10de_02fe NULL +#define pci_ss_list_10de_02ff NULL +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10de_0311 NULL +#define pci_ss_list_10de_0312 NULL +#define pci_ss_list_10de_0313 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0314[] = { + &pci_ss_info_10de_0314_1043_814a, + NULL +}; +#define pci_ss_list_10de_0316 NULL +#define pci_ss_list_10de_0317 NULL +#define pci_ss_list_10de_031a NULL +#define pci_ss_list_10de_031b NULL +#define pci_ss_list_10de_031c NULL +#define pci_ss_list_10de_031d NULL +#define pci_ss_list_10de_031e NULL +#define pci_ss_list_10de_031f NULL +#define pci_ss_list_10de_0320 NULL +#define pci_ss_list_10de_0321 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0322[] = { + &pci_ss_info_10de_0322_1462_9171, + &pci_ss_info_10de_0322_1462_9360, + NULL +}; +#define pci_ss_list_10de_0323 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0324[] = { + &pci_ss_info_10de_0324_1028_0196, + &pci_ss_info_10de_0324_1071_8160, + NULL +}; +#define pci_ss_list_10de_0325 NULL +#define pci_ss_list_10de_0326 NULL +#define pci_ss_list_10de_0327 NULL +#define pci_ss_list_10de_0328 NULL +#define pci_ss_list_10de_0329 NULL +#define pci_ss_list_10de_032a NULL +#define pci_ss_list_10de_032b NULL +#define pci_ss_list_10de_032c NULL +#define pci_ss_list_10de_032d NULL +#define pci_ss_list_10de_032f NULL +#define pci_ss_list_10de_0330 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0331[] = { + &pci_ss_info_10de_0331_1043_8145, + NULL +}; +#define pci_ss_list_10de_0332 NULL +#define pci_ss_list_10de_0333 NULL +#define pci_ss_list_10de_0334 NULL +#define pci_ss_list_10de_0338 NULL +#define pci_ss_list_10de_033f NULL +#define pci_ss_list_10de_0341 NULL +#define pci_ss_list_10de_0342 NULL +#define pci_ss_list_10de_0343 NULL +#define pci_ss_list_10de_0344 NULL +#define pci_ss_list_10de_0345 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0347[] = { + &pci_ss_info_10de_0347_103c_006a, + NULL +}; +#define pci_ss_list_10de_0348 NULL +#define pci_ss_list_10de_0349 NULL +#define pci_ss_list_10de_034b NULL +#define pci_ss_list_10de_034c NULL +#define pci_ss_list_10de_034e NULL +#define pci_ss_list_10de_034f NULL +#define pci_ss_list_10de_0360 NULL +#define pci_ss_list_10de_0361 NULL +#define pci_ss_list_10de_0362 NULL +#define pci_ss_list_10de_0363 NULL +#define pci_ss_list_10de_0364 NULL +#define pci_ss_list_10de_0365 NULL +#define pci_ss_list_10de_0366 NULL +#define pci_ss_list_10de_0367 NULL +#define pci_ss_list_10de_0368 NULL +#define pci_ss_list_10de_0369 NULL +#define pci_ss_list_10de_036a NULL +#define pci_ss_list_10de_036c NULL +#define pci_ss_list_10de_036d NULL +#define pci_ss_list_10de_036e NULL +#define pci_ss_list_10de_0371 NULL +#define pci_ss_list_10de_0372 NULL +#define pci_ss_list_10de_0373 NULL +#define pci_ss_list_10de_037a NULL +#define pci_ss_list_10de_037e NULL +#define pci_ss_list_10de_037f NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f0a1 NULL +#define pci_ss_list_10df_f0a5 NULL +#define pci_ss_list_10df_f0b5 NULL +#define pci_ss_list_10df_f0d1 NULL +#define pci_ss_list_10df_f0d5 NULL +#define pci_ss_list_10df_f0e1 NULL +#define pci_ss_list_10df_f0e5 NULL +#define pci_ss_list_10df_f0f5 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f701 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f801 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f901 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10df_f981 NULL +#define pci_ss_list_10df_f982 NULL +#define pci_ss_list_10df_fa00 NULL +#define pci_ss_list_10df_fb00 NULL +#define pci_ss_list_10df_fc00 NULL +#define pci_ss_list_10df_fc10 NULL +#define pci_ss_list_10df_fc20 NULL +#define pci_ss_list_10df_fd00 NULL +#define pci_ss_list_10df_fe00 NULL +#define pci_ss_list_10df_ff00 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0148 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e3_8260 NULL +#define pci_ss_list_10e3_8261 NULL +#define pci_ss_list_10e4_8029 NULL +#define pci_ss_list_10e8_1072 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_814c NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_81e6 NULL +#define pci_ss_list_10e8_8291 NULL +#define pci_ss_list_10e8_82c4 NULL +#define pci_ss_list_10e8_82c5 NULL +#define pci_ss_list_10e8_82c6 NULL +#define pci_ss_list_10e8_82c7 NULL +#define pci_ss_list_10e8_82ca NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10e8_82e2 NULL +#define pci_ss_list_10e8_8851 NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10ea_5252 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#define pci_ss_list_10ec_0139 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_0357_000a, + &pci_ss_info_10ec_8139_1025_005a, + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_103c_006a, + &pci_ss_info_10ec_8139_1043_8109, + &pci_ss_info_10ec_8139_1071_8160, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1113_ec01, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_1458_e000, + &pci_ss_info_10ec_8139_1462_788c, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_14cb_0200, + &pci_ss_info_10ec_8139_1799_5000, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_9001_1695, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1259_c107, + &pci_ss_info_10ec_8169_1371_434e, + &pci_ss_info_10ec_8169_1458_e000, + &pci_ss_info_10ec_8169_1462_702c, + NULL +}; +#define pci_ss_list_10ec_8180 NULL +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_0205 NULL +#define pci_ss_list_10ee_0210 NULL +#define pci_ss_list_10ee_0314 NULL +#define pci_ss_list_10ee_0405 NULL +#define pci_ss_list_10ee_0410 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ee_3fc6 NULL +#define pci_ss_list_10ee_8381 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#define pci_ss_list_1101_9502 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_100a, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + &pci_ss_info_1102_0002_1102_8064, + &pci_ss_info_1102_0002_1102_8065, + &pci_ss_info_1102_0002_1102_8067, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + &pci_ss_info_1102_0004_1102_0058, + &pci_ss_info_1102_0004_1102_1007, + &pci_ss_info_1102_0004_1102_2002, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_0007[] = { + &pci_ss_info_1102_0007_1102_0007, + &pci_ss_info_1102_0007_1102_1001, + &pci_ss_info_1102_0007_1102_1002, + &pci_ss_info_1102_0007_1102_1006, + &pci_ss_info_1102_0007_1462_1009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0008[] = { + &pci_ss_info_1102_0008_1102_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +static const pciSubsystemInfo *pci_ss_list_1102_7005[] = { + &pci_ss_info_1102_7005_1102_1001, + &pci_ss_info_1102_7005_1102_1002, + NULL +}; +#define pci_ss_list_1102_8064 NULL +static const pciSubsystemInfo *pci_ss_list_1102_8938[] = { + &pci_ss_info_1102_8938_1033_80e5, + &pci_ss_info_1102_8938_1071_7150, + &pci_ss_info_1102_8938_110a_5938, + &pci_ss_info_1102_8938_13bd_100c, + &pci_ss_info_1102_8938_13bd_100d, + &pci_ss_info_1102_8938_13bd_100e, + &pci_ss_info_1102_8938_13bd_f6f1, + &pci_ss_info_1102_8938_14ff_0e70, + &pci_ss_info_1102_8938_14ff_c401, + &pci_ss_info_1102_8938_156d_b400, + &pci_ss_info_1102_8938_156d_b550, + &pci_ss_info_1102_8938_156d_b560, + &pci_ss_info_1102_8938_156d_b700, + &pci_ss_info_1102_8938_156d_b795, + &pci_ss_info_1102_8938_156d_b797, + NULL +}; +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0003, + &pci_ss_info_1103_0004_1103_0004, + &pci_ss_info_1103_0004_1103_0005, + &pci_ss_info_1103_0004_1103_0006, + &pci_ss_info_1103_0004_1103_0007, + &pci_ss_info_1103_0004_1103_0008, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#define pci_ss_list_1103_0009 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1105_8401 NULL +#define pci_ss_list_1105_8470 NULL +#define pci_ss_list_1105_8471 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105_8475[] = { + &pci_ss_info_1105_8475_1105_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1105_8476[] = { + &pci_ss_info_1105_8476_127d_0000, + NULL +}; +#define pci_ss_list_1105_8485 NULL +#define pci_ss_list_1105_8486 NULL +#endif +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +#define pci_ss_list_1106_0204 NULL +#define pci_ss_list_1106_0238 NULL +#define pci_ss_list_1106_0259 NULL +#define pci_ss_list_1106_0269 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106_0282[] = { + &pci_ss_info_1106_0282_1043_80a3, + NULL +}; +#define pci_ss_list_1106_0290 NULL +#define pci_ss_list_1106_0296 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1019_0987, + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0308 NULL +#define pci_ss_list_1106_0314 NULL +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1019_0985, + &pci_ss_info_1106_0571_1019_0a81, + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1043_808c, + &pci_ss_info_1106_0571_1043_80a1, + &pci_ss_info_1106_0571_1043_80ed, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1297_f641, + &pci_ss_info_1106_0571_1458_5002, + &pci_ss_info_1106_0571_1462_7020, + &pci_ss_info_1106_0571_147b_1407, + &pci_ss_info_1106_0571_1849_0571, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0591 NULL +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0605[] = { + &pci_ss_info_1106_0605_1043_802c, + NULL +}; +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1019_0985, + &pci_ss_info_1106_0686_1043_802c, + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1019_0985, + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1204 NULL +#define pci_ss_list_1106_1208 NULL +#define pci_ss_list_1106_1238 NULL +#define pci_ss_list_1106_1258 NULL +#define pci_ss_list_1106_1259 NULL +#define pci_ss_list_1106_1269 NULL +#define pci_ss_list_1106_1282 NULL +#define pci_ss_list_1106_1290 NULL +#define pci_ss_list_1106_1296 NULL +#define pci_ss_list_1106_1308 NULL +#define pci_ss_list_1106_1314 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +#define pci_ss_list_1106_2204 NULL +#define pci_ss_list_1106_2208 NULL +#define pci_ss_list_1106_2238 NULL +#define pci_ss_list_1106_2258 NULL +#define pci_ss_list_1106_2259 NULL +#define pci_ss_list_1106_2269 NULL +#define pci_ss_list_1106_2282 NULL +#define pci_ss_list_1106_2290 NULL +#define pci_ss_list_1106_2296 NULL +#define pci_ss_list_1106_2308 NULL +#define pci_ss_list_1106_2314 NULL +#define pci_ss_list_1106_287a NULL +#define pci_ss_list_1106_287b NULL +#define pci_ss_list_1106_287c NULL +#define pci_ss_list_1106_287d NULL +#define pci_ss_list_1106_287e NULL +#define pci_ss_list_1106_3022 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1019_0985, + &pci_ss_info_1106_3038_1019_0a81, + &pci_ss_info_1106_3038_1043_8080, + &pci_ss_info_1106_3038_1043_808c, + &pci_ss_info_1106_3038_1043_80a1, + &pci_ss_info_1106_3038_1043_80ed, + &pci_ss_info_1106_3038_1179_0001, + &pci_ss_info_1106_3038_1458_5004, + &pci_ss_info_1106_3038_1462_7020, + &pci_ss_info_1106_3038_147b_1407, + &pci_ss_info_1106_3038_182d_201d, + &pci_ss_info_1106_3038_1849_3038, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3044[] = { + &pci_ss_info_1106_3044_0574_086c, + &pci_ss_info_1106_3044_1025_005a, + &pci_ss_info_1106_3044_1043_808a, + &pci_ss_info_1106_3044_1458_1000, + &pci_ss_info_1106_3044_1462_702d, + &pci_ss_info_1106_3044_1462_971d, + NULL +}; +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +#define pci_ss_list_1106_3053 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1019_0985, + &pci_ss_info_1106_3057_1019_0987, + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_0097, + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1019_0985, + &pci_ss_info_1106_3058_1019_0987, + &pci_ss_info_1106_3058_1043_1106, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_1462_3300, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1019_0a81, + &pci_ss_info_1106_3059_1043_8095, + &pci_ss_info_1106_3059_1043_80a1, + &pci_ss_info_1106_3059_1043_80b0, + &pci_ss_info_1106_3059_1043_812a, + &pci_ss_info_1106_3059_1106_3059, + &pci_ss_info_1106_3059_1106_4161, + &pci_ss_info_1106_3059_1297_c160, + &pci_ss_info_1106_3059_1458_a002, + &pci_ss_info_1106_3059_1462_0080, + &pci_ss_info_1106_3059_1462_3800, + &pci_ss_info_1106_3059_147b_1407, + &pci_ss_info_1106_3059_1849_9761, + &pci_ss_info_1106_3059_4005_4710, + &pci_ss_info_1106_3059_4170_1106, + &pci_ss_info_1106_3059_4552_1106, + &pci_ss_info_1106_3059_a0a0_01b6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1043_80a1, + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + &pci_ss_info_1106_3065_13b9_1421, + &pci_ss_info_1106_3065_147b_1c09, + &pci_ss_info_1106_3065_1695_3005, + &pci_ss_info_1106_3065_1695_300c, + &pci_ss_info_1106_3065_1849_3065, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3068[] = { + &pci_ss_info_1106_3068_1462_309e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + &pci_ss_info_1106_3099_1849_3099, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1019_0a81, + &pci_ss_info_1106_3104_1043_808c, + &pci_ss_info_1106_3104_1043_80a1, + &pci_ss_info_1106_3104_1043_80ed, + &pci_ss_info_1106_3104_1297_f641, + &pci_ss_info_1106_3104_1458_5004, + &pci_ss_info_1106_3104_1462_7020, + &pci_ss_info_1106_3104_147b_1407, + &pci_ss_info_1106_3104_182d_201d, + &pci_ss_info_1106_3104_1849_3104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3106[] = { + &pci_ss_info_1106_3106_1186_1403, + NULL +}; +#define pci_ss_list_1106_3108 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3113 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3116[] = { + &pci_ss_info_1106_3116_1297_f641, + NULL +}; +#define pci_ss_list_1106_3118 NULL +#define pci_ss_list_1106_3119 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3147[] = { + &pci_ss_info_1106_3147_1043_808c, + NULL +}; +#define pci_ss_list_1106_3148 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3149[] = { + &pci_ss_info_1106_3149_1043_80ed, + &pci_ss_info_1106_3149_1458_b003, + &pci_ss_info_1106_3149_1462_7020, + &pci_ss_info_1106_3149_147b_1407, + &pci_ss_info_1106_3149_147b_1408, + &pci_ss_info_1106_3149_1849_3149, + NULL +}; +#define pci_ss_list_1106_3156 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3164[] = { + &pci_ss_info_1106_3164_1043_80f4, + &pci_ss_info_1106_3164_1462_7028, + NULL +}; +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1019_0a81, + &pci_ss_info_1106_3177_1043_808c, + &pci_ss_info_1106_3177_1043_80a1, + &pci_ss_info_1106_3177_1297_f641, + &pci_ss_info_1106_3177_1458_5001, + &pci_ss_info_1106_3177_1849_3177, + NULL +}; +#define pci_ss_list_1106_3178 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3188[] = { + &pci_ss_info_1106_3188_1043_80a3, + &pci_ss_info_1106_3188_147b_1407, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1043_807f, + &pci_ss_info_1106_3189_1458_5000, + &pci_ss_info_1106_3189_1849_3189, + NULL +}; +#define pci_ss_list_1106_3204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3205[] = { + &pci_ss_info_1106_3205_1458_5000, + NULL +}; +#define pci_ss_list_1106_3208 NULL +#define pci_ss_list_1106_3213 NULL +#define pci_ss_list_1106_3218 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3227[] = { + &pci_ss_info_1106_3227_1043_80ed, + &pci_ss_info_1106_3227_1106_3227, + &pci_ss_info_1106_3227_1458_5001, + &pci_ss_info_1106_3227_147b_1407, + &pci_ss_info_1106_3227_1849_3227, + NULL +}; +#define pci_ss_list_1106_3238 NULL +#define pci_ss_list_1106_3249 NULL +#define pci_ss_list_1106_3258 NULL +#define pci_ss_list_1106_3259 NULL +#define pci_ss_list_1106_3269 NULL +#define pci_ss_list_1106_3282 NULL +#define pci_ss_list_1106_3287 NULL +#define pci_ss_list_1106_3288 NULL +#define pci_ss_list_1106_3290 NULL +#define pci_ss_list_1106_3296 NULL +#define pci_ss_list_1106_3337 NULL +#define pci_ss_list_1106_3344 NULL +#define pci_ss_list_1106_3349 NULL +#define pci_ss_list_1106_337a NULL +#define pci_ss_list_1106_337b NULL +#define pci_ss_list_1106_4149 NULL +#define pci_ss_list_1106_4204 NULL +#define pci_ss_list_1106_4208 NULL +#define pci_ss_list_1106_4238 NULL +#define pci_ss_list_1106_4258 NULL +#define pci_ss_list_1106_4259 NULL +#define pci_ss_list_1106_4269 NULL +#define pci_ss_list_1106_4282 NULL +#define pci_ss_list_1106_4290 NULL +#define pci_ss_list_1106_4296 NULL +#define pci_ss_list_1106_4308 NULL +#define pci_ss_list_1106_4314 NULL +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_5208 NULL +#define pci_ss_list_1106_5238 NULL +#define pci_ss_list_1106_5290 NULL +#define pci_ss_list_1106_5308 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_7204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_7205[] = { + &pci_ss_info_1106_7205_1458_d000, + NULL +}; +#define pci_ss_list_1106_7208 NULL +#define pci_ss_list_1106_7238 NULL +#define pci_ss_list_1106_7258 NULL +#define pci_ss_list_1106_7259 NULL +#define pci_ss_list_1106_7269 NULL +#define pci_ss_list_1106_7282 NULL +#define pci_ss_list_1106_7290 NULL +#define pci_ss_list_1106_7296 NULL +#define pci_ss_list_1106_7308 NULL +#define pci_ss_list_1106_7314 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +static const pciSubsystemInfo *pci_ss_list_1106_8598[] = { + &pci_ss_info_1106_8598_1019_0985, + NULL +}; +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_a208 NULL +#define pci_ss_list_1106_a238 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b113 NULL +#define pci_ss_list_1106_b115 NULL +#define pci_ss_list_1106_b168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_b188[] = { + &pci_ss_info_1106_b188_147b_1407, + NULL +}; +#define pci_ss_list_1106_b198 NULL +#define pci_ss_list_1106_b213 NULL +#define pci_ss_list_1106_c208 NULL +#define pci_ss_list_1106_c238 NULL +#define pci_ss_list_1106_d104 NULL +#define pci_ss_list_1106_d208 NULL +#define pci_ss_list_1106_d213 NULL +#define pci_ss_list_1106_d238 NULL +#define pci_ss_list_1106_e208 NULL +#define pci_ss_list_1106_e238 NULL +#define pci_ss_list_1106_f208 NULL +#define pci_ss_list_1106_f238 NULL +#endif +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_0006 NULL +#define pci_ss_list_110a_0015 NULL +#define pci_ss_list_110a_001d NULL +#define pci_ss_list_110a_007b NULL +#define pci_ss_list_110a_007c NULL +#define pci_ss_list_110a_007d NULL +#define pci_ss_list_110a_2101 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_2104 NULL +#define pci_ss_list_110a_3142 NULL +#define pci_ss_list_110a_4021 NULL +#define pci_ss_list_110a_4029 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_1113_2242, + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#define pci_ss_list_1113_d301 NULL +#define pci_ss_list_1113_ec02 NULL +#endif +#define pci_ss_list_1114_0506 NULL +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0010 NULL +#define pci_ss_list_1119_0011 NULL +#define pci_ss_list_1119_0012 NULL +#define pci_ss_list_1119_0013 NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_02ff NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#define pci_ss_list_111a_1203 NULL +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111d_0004 NULL +#define pci_ss_list_111d_0005 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_112f_0008 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_5400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_5402[] = { + &pci_ss_info_1131_5402_1244_0f00, + NULL +}; +#define pci_ss_list_1131_5405 NULL +#define pci_ss_list_1131_5406 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7130[] = { + &pci_ss_info_1131_7130_102b_48d0, + &pci_ss_info_1131_7130_1048_226b, + &pci_ss_info_1131_7130_1131_2001, + &pci_ss_info_1131_7130_1131_2005, + &pci_ss_info_1131_7130_1461_050c, + &pci_ss_info_1131_7130_1461_10ff, + &pci_ss_info_1131_7130_1461_2108, + &pci_ss_info_1131_7130_1461_2115, + &pci_ss_info_1131_7130_153b_1152, + &pci_ss_info_1131_7130_185b_c100, + &pci_ss_info_1131_7130_185b_c901, + &pci_ss_info_1131_7130_5168_0138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7133[] = { + &pci_ss_info_1131_7133_0000_4091, + &pci_ss_info_1131_7133_002b_11bd, + &pci_ss_info_1131_7133_1019_4cb5, + &pci_ss_info_1131_7133_1043_0210, + &pci_ss_info_1131_7133_1043_4843, + &pci_ss_info_1131_7133_1043_4845, + &pci_ss_info_1131_7133_1043_4862, + &pci_ss_info_1131_7133_1131_2001, + &pci_ss_info_1131_7133_1131_2018, + &pci_ss_info_1131_7133_1131_4ee9, + &pci_ss_info_1131_7133_11bd_002e, + &pci_ss_info_1131_7133_12ab_0800, + &pci_ss_info_1131_7133_1421_1370, + &pci_ss_info_1131_7133_1435_7330, + &pci_ss_info_1131_7133_1435_7350, + &pci_ss_info_1131_7133_1461_1044, + &pci_ss_info_1131_7133_1461_f31f, + &pci_ss_info_1131_7133_1462_6231, + &pci_ss_info_1131_7133_1489_0214, + &pci_ss_info_1131_7133_14c0_1212, + &pci_ss_info_1131_7133_153b_1160, + &pci_ss_info_1131_7133_153b_1162, + &pci_ss_info_1131_7133_185b_c100, + &pci_ss_info_1131_7133_4e42_0212, + &pci_ss_info_1131_7133_4e42_0502, + &pci_ss_info_1131_7133_5168_0306, + &pci_ss_info_1131_7133_5168_0319, + &pci_ss_info_1131_7133_5456_7135, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7134[] = { + &pci_ss_info_1131_7134_1019_4cb4, + &pci_ss_info_1131_7134_1043_0210, + &pci_ss_info_1131_7134_1043_4840, + &pci_ss_info_1131_7134_1131_2004, + &pci_ss_info_1131_7134_1131_4e85, + &pci_ss_info_1131_7134_1131_6752, + &pci_ss_info_1131_7134_1131_7133, + &pci_ss_info_1131_7134_11bd_002b, + &pci_ss_info_1131_7134_11bd_002d, + &pci_ss_info_1131_7134_1461_9715, + &pci_ss_info_1131_7134_1461_a70a, + &pci_ss_info_1131_7134_1461_a70b, + &pci_ss_info_1131_7134_1461_d6ee, + &pci_ss_info_1131_7134_1471_b7e9, + &pci_ss_info_1131_7134_153b_1142, + &pci_ss_info_1131_7134_153b_1143, + &pci_ss_info_1131_7134_153b_1158, + &pci_ss_info_1131_7134_1540_9524, + &pci_ss_info_1131_7134_16be_0003, + &pci_ss_info_1131_7134_185b_c200, + &pci_ss_info_1131_7134_185b_c900, + &pci_ss_info_1131_7134_1894_a006, + &pci_ss_info_1131_7134_1894_fe01, + &pci_ss_info_1131_7134_4e42_0138, + NULL +}; +#define pci_ss_list_1131_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_110a_0000, + &pci_ss_info_1131_7146_110a_ffff, + &pci_ss_info_1131_7146_1131_4f56, + &pci_ss_info_1131_7146_1131_4f60, + &pci_ss_info_1131_7146_1131_4f61, + &pci_ss_info_1131_7146_1131_5f61, + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + &pci_ss_info_1131_7146_11bd_000f, + &pci_ss_info_1131_7146_13c2_0000, + &pci_ss_info_1131_7146_13c2_0001, + &pci_ss_info_1131_7146_13c2_0002, + &pci_ss_info_1131_7146_13c2_0003, + &pci_ss_info_1131_7146_13c2_0004, + &pci_ss_info_1131_7146_13c2_0006, + &pci_ss_info_1131_7146_13c2_0008, + &pci_ss_info_1131_7146_13c2_000a, + &pci_ss_info_1131_7146_13c2_1003, + &pci_ss_info_1131_7146_13c2_1004, + &pci_ss_info_1131_7146_13c2_1005, + &pci_ss_info_1131_7146_13c2_100c, + &pci_ss_info_1131_7146_13c2_100f, + &pci_ss_info_1131_7146_13c2_1011, + &pci_ss_info_1131_7146_13c2_1013, + &pci_ss_info_1131_7146_13c2_1016, + &pci_ss_info_1131_7146_13c2_1102, + NULL +}; +#define pci_ss_list_1131_9730 NULL +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#define pci_ss_list_1133_e001 NULL +#define pci_ss_list_1133_e002 NULL +#define pci_ss_list_1133_e003 NULL +#define pci_ss_list_1133_e004 NULL +#define pci_ss_list_1133_e005 NULL +#define pci_ss_list_1133_e006 NULL +#define pci_ss_list_1133_e007 NULL +#define pci_ss_list_1133_e008 NULL +#define pci_ss_list_1133_e009 NULL +#define pci_ss_list_1133_e00a NULL +#define pci_ss_list_1133_e00b NULL +#define pci_ss_list_1133_e00c NULL +#define pci_ss_list_1133_e00d NULL +#define pci_ss_list_1133_e00e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_110a_0021, + NULL +}; +#define pci_ss_list_1133_e011 NULL +#define pci_ss_list_1133_e012 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e013[] = { + &pci_ss_info_1133_e013_1133_1300, + &pci_ss_info_1133_e013_1133_e013, + NULL +}; +#define pci_ss_list_1133_e014 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e015[] = { + &pci_ss_info_1133_e015_1133_e015, + NULL +}; +#define pci_ss_list_1133_e016 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e017[] = { + &pci_ss_info_1133_e017_1133_e017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e018[] = { + &pci_ss_info_1133_e018_1133_1800, + &pci_ss_info_1133_e018_1133_e018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e019[] = { + &pci_ss_info_1133_e019_1133_e019, + NULL +}; +#define pci_ss_list_1133_e01a NULL +static const pciSubsystemInfo *pci_ss_list_1133_e01b[] = { + &pci_ss_info_1133_e01b_1133_e01b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e01c[] = { + &pci_ss_info_1133_e01c_1133_1c01, + &pci_ss_info_1133_e01c_1133_1c02, + &pci_ss_info_1133_e01c_1133_1c03, + &pci_ss_info_1133_e01c_1133_1c04, + &pci_ss_info_1133_e01c_1133_1c05, + &pci_ss_info_1133_e01c_1133_1c06, + &pci_ss_info_1133_e01c_1133_1c07, + &pci_ss_info_1133_e01c_1133_1c08, + &pci_ss_info_1133_e01c_1133_1c09, + &pci_ss_info_1133_e01c_1133_1c0a, + &pci_ss_info_1133_e01c_1133_1c0b, + &pci_ss_info_1133_e01c_1133_1c0c, + NULL +}; +#define pci_ss_list_1133_e01e NULL +#define pci_ss_list_1133_e020 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e024[] = { + &pci_ss_info_1133_e024_1133_2400, + &pci_ss_info_1133_e024_1133_e024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e028[] = { + &pci_ss_info_1133_e028_1133_2800, + &pci_ss_info_1133_e028_1133_e028, + NULL +}; +#define pci_ss_list_1133_e02a NULL +#define pci_ss_list_1133_e02c NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1134_0002 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#define pci_ss_list_1145_f020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2971, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2973, + &pci_ss_info_1148_4300_1259_2974, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2976, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_0121, + &pci_ss_info_1148_4320_1148_0221, + &pci_ss_info_1148_4320_1148_0321, + &pci_ss_info_1148_4320_1148_0421, + &pci_ss_info_1148_4320_1148_0621, + &pci_ss_info_1148_4320_1148_0721, + &pci_ss_info_1148_4320_1148_0821, + &pci_ss_info_1148_4320_1148_0921, + &pci_ss_info_1148_4320_1148_1121, + &pci_ss_info_1148_4320_1148_1221, + &pci_ss_info_1148_4320_1148_3221, + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#define pci_ss_list_1148_4500 NULL +#define pci_ss_list_1148_9000 NULL +#define pci_ss_list_1148_9843 NULL +static const pciSubsystemInfo *pci_ss_list_1148_9e00[] = { + &pci_ss_info_1148_9e00_1148_2100, + &pci_ss_info_1148_9e00_1148_21d0, + &pci_ss_info_1148_9e00_1148_2200, + &pci_ss_info_1148_9e00_1148_8100, + &pci_ss_info_1148_9e00_1148_8200, + &pci_ss_info_1148_9e00_1148_9100, + &pci_ss_info_1148_9e00_1148_9200, + NULL +}; +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0028 NULL +#define pci_ss_list_114f_0029 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0043 NULL +#define pci_ss_list_114f_0044 NULL +#define pci_ss_list_114f_0045 NULL +#define pci_ss_list_114f_004e NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_00b0 NULL +#define pci_ss_list_114f_00b1 NULL +#define pci_ss_list_114f_00c8 NULL +#define pci_ss_list_114f_00c9 NULL +#define pci_ss_list_114f_00ca NULL +#define pci_ss_list_114f_00cb NULL +#define pci_ss_list_114f_00d0 NULL +#define pci_ss_list_114f_00d1 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_0182, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +#define pci_ss_list_115d_00d4 NULL +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0000 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0006 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0036 NULL +#define pci_ss_list_1166_0101 NULL +#define pci_ss_list_1166_0104 NULL +#define pci_ss_list_1166_0110 NULL +#define pci_ss_list_1166_0130 NULL +#define pci_ss_list_1166_0132 NULL +#define pci_ss_list_1166_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166_0201[] = { + &pci_ss_info_1166_0201_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0203[] = { + &pci_ss_info_1166_0203_1734_1012, + NULL +}; +#define pci_ss_list_1166_0205 NULL +#define pci_ss_list_1166_0211 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0212[] = { + &pci_ss_info_1166_0212_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0213[] = { + &pci_ss_info_1166_0213_1028_c134, + &pci_ss_info_1166_0213_1734_1012, + NULL +}; +#define pci_ss_list_1166_0214 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0217[] = { + &pci_ss_info_1166_0217_1028_4134, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0220[] = { + &pci_ss_info_1166_0220_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0221[] = { + &pci_ss_info_1166_0221_1734_1012, + NULL +}; +#define pci_ss_list_1166_0223 NULL +#define pci_ss_list_1166_0225 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0227[] = { + &pci_ss_info_1166_0227_1734_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0230[] = { + &pci_ss_info_1166_0230_4c53_1080, + NULL +}; +#define pci_ss_list_1166_0234 NULL +#define pci_ss_list_1166_0240 NULL +#define pci_ss_list_1166_0241 NULL +#define pci_ss_list_1166_0242 NULL +#define pci_ss_list_1166_024a NULL +#endif +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0102 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0601[] = { + &pci_ss_info_1179_0601_1179_0001, + NULL +}; +#define pci_ss_list_1179_0603 NULL +static const pciSubsystemInfo *pci_ss_list_1179_060a[] = { + &pci_ss_info_1179_060a_1179_0001, + NULL +}; +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c_0030[] = { + &pci_ss_info_117c_0030_117c_8013, + &pci_ss_info_117c_0030_117c_8014, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_1028_0188, + &pci_ss_info_1180_0476_1043_1967, + &pci_ss_info_1180_0476_1043_1987, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + &pci_ss_info_1180_0476_14ef_0220, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +#define pci_ss_list_1180_0511 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + &pci_ss_info_1180_0522_1043_1967, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + &pci_ss_info_1180_0552_1028_0188, + NULL +}; +#define pci_ss_list_1180_0554 NULL +#define pci_ss_list_1180_0575 NULL +#define pci_ss_list_1180_0576 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0592[] = { + &pci_ss_info_1180_0592_1043_1967, + NULL +}; +#define pci_ss_list_1180_0811 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0822[] = { + &pci_ss_info_1180_0822_1014_0556, + &pci_ss_info_1180_0822_1028_0188, + &pci_ss_info_1180_0822_1028_01a2, + &pci_ss_info_1180_0822_1043_1967, + NULL +}; +#define pci_ss_list_1180_0841 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0852[] = { + &pci_ss_info_1180_0852_1043_1967, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +#define pci_ss_list_1186_1025 NULL +#define pci_ss_list_1186_1026 NULL +#define pci_ss_list_1186_1043 NULL +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + &pci_ss_info_1186_1300_1186_1303, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1541 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_2027 NULL +#define pci_ss_list_1186_3203 NULL +#define pci_ss_list_1186_3300 NULL +#define pci_ss_list_1186_3a03 NULL +#define pci_ss_list_1186_3a04 NULL +#define pci_ss_list_1186_3a05 NULL +#define pci_ss_list_1186_3a07 NULL +#define pci_ss_list_1186_3a08 NULL +#define pci_ss_list_1186_3a10 NULL +#define pci_ss_list_1186_3a11 NULL +#define pci_ss_list_1186_3a12 NULL +#define pci_ss_list_1186_3a13 NULL +#define pci_ss_list_1186_3a14 NULL +#define pci_ss_list_1186_3a63 NULL +#define pci_ss_list_1186_4000 NULL +#define pci_ss_list_1186_4300 NULL +static const pciSubsystemInfo *pci_ss_list_1186_4c00[] = { + &pci_ss_info_1186_4c00_1186_4c00, + NULL +}; +#define pci_ss_list_1186_8400 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1191_8060 NULL +#define pci_ss_list_1191_8080 NULL +#define pci_ss_list_1191_8081 NULL +#define pci_ss_list_1191_808a NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_1197_010c NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_138f NULL +#define pci_ss_list_11ab_1fa6 NULL +#define pci_ss_list_11ab_1fa7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab_1faa[] = { + &pci_ss_info_11ab_1faa_1385_4e00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4320[] = { + &pci_ss_info_11ab_4320_1019_0f38, + &pci_ss_info_11ab_4320_1019_8001, + &pci_ss_info_11ab_4320_1043_173c, + &pci_ss_info_11ab_4320_1043_811a, + &pci_ss_info_11ab_4320_105b_0c19, + &pci_ss_info_11ab_4320_10b8_b452, + &pci_ss_info_11ab_4320_11ab_0121, + &pci_ss_info_11ab_4320_11ab_0321, + &pci_ss_info_11ab_4320_11ab_1021, + &pci_ss_info_11ab_4320_11ab_5021, + &pci_ss_info_11ab_4320_11ab_9521, + &pci_ss_info_11ab_4320_1458_e000, + &pci_ss_info_11ab_4320_147b_1406, + &pci_ss_info_11ab_4320_15d4_0047, + &pci_ss_info_11ab_4320_1695_9025, + &pci_ss_info_11ab_4320_17f2_1c03, + &pci_ss_info_11ab_4320_270f_2803, + NULL +}; +#define pci_ss_list_11ab_4340 NULL +#define pci_ss_list_11ab_4341 NULL +#define pci_ss_list_11ab_4342 NULL +#define pci_ss_list_11ab_4343 NULL +#define pci_ss_list_11ab_4344 NULL +#define pci_ss_list_11ab_4345 NULL +#define pci_ss_list_11ab_4346 NULL +#define pci_ss_list_11ab_4347 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4350[] = { + &pci_ss_info_11ab_4350_1179_0001, + &pci_ss_info_11ab_4350_11ab_3521, + &pci_ss_info_11ab_4350_1854_000d, + &pci_ss_info_11ab_4350_1854_000e, + &pci_ss_info_11ab_4350_1854_000f, + &pci_ss_info_11ab_4350_1854_0011, + &pci_ss_info_11ab_4350_1854_0012, + &pci_ss_info_11ab_4350_1854_0016, + &pci_ss_info_11ab_4350_1854_0017, + &pci_ss_info_11ab_4350_1854_0018, + &pci_ss_info_11ab_4350_1854_0019, + &pci_ss_info_11ab_4350_1854_001c, + &pci_ss_info_11ab_4350_1854_001e, + &pci_ss_info_11ab_4350_1854_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4351[] = { + &pci_ss_info_11ab_4351_107b_4009, + &pci_ss_info_11ab_4351_10f7_8338, + &pci_ss_info_11ab_4351_1179_0001, + &pci_ss_info_11ab_4351_1179_ff00, + &pci_ss_info_11ab_4351_1179_ff10, + &pci_ss_info_11ab_4351_11ab_3621, + &pci_ss_info_11ab_4351_13d1_ac12, + &pci_ss_info_11ab_4351_161f_203d, + &pci_ss_info_11ab_4351_1854_000d, + &pci_ss_info_11ab_4351_1854_000e, + &pci_ss_info_11ab_4351_1854_000f, + &pci_ss_info_11ab_4351_1854_0011, + &pci_ss_info_11ab_4351_1854_0012, + &pci_ss_info_11ab_4351_1854_0016, + &pci_ss_info_11ab_4351_1854_0017, + &pci_ss_info_11ab_4351_1854_0018, + &pci_ss_info_11ab_4351_1854_0019, + &pci_ss_info_11ab_4351_1854_001c, + &pci_ss_info_11ab_4351_1854_001e, + &pci_ss_info_11ab_4351_1854_0020, + NULL +}; +#define pci_ss_list_11ab_4352 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4360[] = { + &pci_ss_info_11ab_4360_1043_8134, + &pci_ss_info_11ab_4360_107b_4009, + &pci_ss_info_11ab_4360_11ab_5221, + &pci_ss_info_11ab_4360_1458_e000, + &pci_ss_info_11ab_4360_1462_052c, + &pci_ss_info_11ab_4360_1849_8052, + &pci_ss_info_11ab_4360_a0a0_0509, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4361[] = { + &pci_ss_info_11ab_4361_107b_3015, + &pci_ss_info_11ab_4361_11ab_5021, + &pci_ss_info_11ab_4361_8086_3063, + &pci_ss_info_11ab_4361_8086_3439, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4362[] = { + &pci_ss_info_11ab_4362_103c_2a0d, + &pci_ss_info_11ab_4362_1043_8142, + &pci_ss_info_11ab_4362_109f_3197, + &pci_ss_info_11ab_4362_10f7_8338, + &pci_ss_info_11ab_4362_10fd_a430, + &pci_ss_info_11ab_4362_1179_0001, + &pci_ss_info_11ab_4362_1179_ff00, + &pci_ss_info_11ab_4362_1179_ff10, + &pci_ss_info_11ab_4362_11ab_5321, + &pci_ss_info_11ab_4362_1297_c240, + &pci_ss_info_11ab_4362_1297_c241, + &pci_ss_info_11ab_4362_1297_c242, + &pci_ss_info_11ab_4362_1297_c243, + &pci_ss_info_11ab_4362_1297_c244, + &pci_ss_info_11ab_4362_13d1_ac11, + &pci_ss_info_11ab_4362_1458_e000, + &pci_ss_info_11ab_4362_1462_058c, + &pci_ss_info_11ab_4362_14c0_0012, + &pci_ss_info_11ab_4362_1558_04a0, + &pci_ss_info_11ab_4362_15bd_1003, + &pci_ss_info_11ab_4362_161f_203c, + &pci_ss_info_11ab_4362_161f_203d, + &pci_ss_info_11ab_4362_1695_9029, + &pci_ss_info_11ab_4362_17f2_2c08, + &pci_ss_info_11ab_4362_17ff_0585, + &pci_ss_info_11ab_4362_1849_8053, + &pci_ss_info_11ab_4362_1854_000b, + &pci_ss_info_11ab_4362_1854_000c, + &pci_ss_info_11ab_4362_1854_0010, + &pci_ss_info_11ab_4362_1854_0013, + &pci_ss_info_11ab_4362_1854_0014, + &pci_ss_info_11ab_4362_1854_0015, + &pci_ss_info_11ab_4362_1854_001a, + &pci_ss_info_11ab_4362_1854_001b, + &pci_ss_info_11ab_4362_1854_001d, + &pci_ss_info_11ab_4362_1854_001f, + &pci_ss_info_11ab_4362_1854_0021, + &pci_ss_info_11ab_4362_1854_0022, + &pci_ss_info_11ab_4362_270f_2801, + &pci_ss_info_11ab_4362_a0a0_0506, + NULL +}; +#define pci_ss_list_11ab_4363 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_5005 NULL +#define pci_ss_list_11ab_5040 NULL +#define pci_ss_list_11ab_5041 NULL +#define pci_ss_list_11ab_5080 NULL +#define pci_ss_list_11ab_5081 NULL +#define pci_ss_list_11ab_6041 NULL +#define pci_ss_list_11ab_6081 NULL +#define pci_ss_list_11ab_6460 NULL +#define pci_ss_list_11ab_6480 NULL +#define pci_ss_list_11ab_f003 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11af_0001 NULL +#define pci_ss_list_11af_ee40 NULL +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#define pci_ss_list_11bd_002e NULL +#define pci_ss_list_11bd_bede NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0445[] = { + &pci_ss_info_11c1_0445_8086_2203, + &pci_ss_info_11c1_0445_8086_2204, + NULL +}; +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_1033_80a8, + &pci_ss_info_11c1_0450_144f_4005, + &pci_ss_info_11c1_0450_1468_0450, + &pci_ss_info_11c1_0450_4005_144f, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_048c NULL +#define pci_ss_list_11c1_048f NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_8086_524c, + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_8110[] = { + &pci_ss_info_11c1_8110_12d9_000c, + NULL +}; +#define pci_ss_list_11c1_ab10 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab11[] = { + &pci_ss_info_11c1_ab11_11c1_ab12, + &pci_ss_info_11c1_ab11_11c1_ab13, + &pci_ss_info_11c1_ab11_11c1_ab15, + &pci_ss_info_11c1_ab11_11c1_ab16, + NULL +}; +#define pci_ss_list_11c1_ab20 NULL +#define pci_ss_list_11c1_ab21 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab30[] = { + &pci_ss_info_11c1_ab30_14cd_2012, + NULL +}; +#define pci_ss_list_11c1_ed00 NULL +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1535 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d4_5340 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_12f8_8a02, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + &pci_ss_info_11de_6120_13c2_0000, + &pci_ss_info_11de_6120_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_11e3_0001 NULL +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_000d NULL +#define pci_ss_list_11fe_000e NULL +#define pci_ss_list_11fe_000f NULL +#define pci_ss_list_11fe_0801 NULL +#define pci_ss_list_11fe_0802 NULL +#define pci_ss_list_11fe_0803 NULL +#define pci_ss_list_11fe_0805 NULL +#define pci_ss_list_11fe_080c NULL +#define pci_ss_list_11fe_080d NULL +#define pci_ss_list_11fe_0812 NULL +#define pci_ss_list_11fe_0903 NULL +#define pci_ss_list_11fe_8015 NULL +#define pci_ss_list_11ff_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1014_020c, + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_7110[] = { + &pci_ss_info_1217_7110_103c_088c, + &pci_ss_info_1217_7110_103c_0890, + NULL +}; +#define pci_ss_list_1217_7112 NULL +#define pci_ss_list_1217_7113 NULL +#define pci_ss_list_1217_7114 NULL +#define pci_ss_list_1217_7134 NULL +#define pci_ss_list_1217_71e2 NULL +#define pci_ss_list_1217_7212 NULL +#define pci_ss_list_1217_7213 NULL +static const pciSubsystemInfo *pci_ss_list_1217_7223[] = { + &pci_ss_info_1217_7223_103c_088c, + &pci_ss_info_1217_7223_103c_0890, + NULL +}; +#define pci_ss_list_1217_7233 NULL +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0057, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0003, + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_1227_0006 NULL +#define pci_ss_list_1227_0023 NULL +#define pci_ss_list_122d_1206 NULL +#define pci_ss_list_122d_1400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + &pci_ss_info_123f_8120_11bd_000f, + &pci_ss_info_123f_8120_1809_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#define pci_ss_list_1242_6562 NULL +#define pci_ss_list_1242_656a NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#define pci_ss_list_1244_2700 NULL +#define pci_ss_list_1244_2900 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_1259_a117 NULL +#define pci_ss_list_1259_a120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125b_1400[] = { + &pci_ss_info_125b_1400_1186_1100, + NULL +}; +#endif +#define pci_ss_list_125c_0101 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + &pci_ss_info_125d_1969_153b_111b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_0e11_0098, + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00b1, + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3872[] = { + &pci_ss_info_1260_3872_1468_0202, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1186_3700, + &pci_ss_info_1260_3873_1385_4105, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_16a5_1601, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3886[] = { + &pci_ss_info_1260_3886_17cf_0037, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3890[] = { + &pci_ss_info_1260_3890_10b8_2802, + &pci_ss_info_1260_3890_10b8_2835, + &pci_ss_info_1260_3890_10b8_a835, + &pci_ss_info_1260_3890_1113_4203, + &pci_ss_info_1260_3890_1113_ee03, + &pci_ss_info_1260_3890_1113_ee08, + &pci_ss_info_1260_3890_1186_3202, + &pci_ss_info_1260_3890_1259_c104, + &pci_ss_info_1260_3890_1385_4800, + &pci_ss_info_1260_3890_16a5_1605, + &pci_ss_info_1260_3890_17cf_0014, + &pci_ss_info_1260_3890_17cf_0020, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +static const pciSubsystemInfo *pci_ss_list_1260_ffff[] = { + &pci_ss_info_1260_ffff_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126c_1211 NULL +#define pci_ss_list_126c_126c NULL +#define pci_ss_list_126f_0501 NULL +#define pci_ss_list_126f_0510 NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0730 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#define pci_ss_list_1274_1171 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1274_8001, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4541, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1274_8001, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1278_0710 NULL +#define pci_ss_list_1279_0060 NULL +#define pci_ss_list_1279_0061 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1005_127a, + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283_8211[] = { + &pci_ss_info_1283_8211_1043_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1283_8212[] = { + &pci_ss_info_1283_8212_1283_0001, + NULL +}; +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8872 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#endif +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12a3_8105 NULL +#define pci_ss_list_12ab_0002 NULL +#define pci_ss_list_12ab_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_1014_0104, + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_10a9_8002, + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#define pci_ss_list_12ae_00fa NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c4_0001 NULL +#define pci_ss_list_12c4_0002 NULL +#define pci_ss_list_12c4_0003 NULL +#define pci_ss_list_12c4_0004 NULL +#define pci_ss_list_12c4_0005 NULL +#define pci_ss_list_12c4_0006 NULL +#define pci_ss_list_12c4_0007 NULL +#define pci_ss_list_12c4_0008 NULL +#define pci_ss_list_12c4_0009 NULL +#define pci_ss_list_12c4_000a NULL +#define pci_ss_list_12c4_000b NULL +#define pci_ss_list_12c4_000c NULL +#define pci_ss_list_12c4_000d NULL +#define pci_ss_list_12c4_0100 NULL +#define pci_ss_list_12c4_0201 NULL +#define pci_ss_list_12c4_0202 NULL +#define pci_ss_list_12c4_0300 NULL +#define pci_ss_list_12c4_0301 NULL +#define pci_ss_list_12c4_0302 NULL +#define pci_ss_list_12c4_0310 NULL +#define pci_ss_list_12c4_0311 NULL +#define pci_ss_list_12c4_0312 NULL +#define pci_ss_list_12c4_0320 NULL +#define pci_ss_list_12c4_0321 NULL +#define pci_ss_list_12c4_0322 NULL +#define pci_ss_list_12c4_0330 NULL +#define pci_ss_list_12c4_0331 NULL +#define pci_ss_list_12c4_0332 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12d4_0200 NULL +#define pci_ss_list_12d5_0003 NULL +#define pci_ss_list_12d5_1000 NULL +#define pci_ss_list_12d8_8150 NULL +#define pci_ss_list_12d9_0002 NULL +#define pci_ss_list_12d9_0004 NULL +#define pci_ss_list_12d9_0005 NULL +#define pci_ss_list_12de_0200 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_12fb_0001 NULL +#define pci_ss_list_12fb_00f5 NULL +#define pci_ss_list_12fb_02ad NULL +#define pci_ss_list_12fb_2adc NULL +#define pci_ss_list_12fb_3100 NULL +#define pci_ss_list_12fb_3500 NULL +#define pci_ss_list_12fb_4d4f NULL +#define pci_ss_list_12fb_8120 NULL +#define pci_ss_list_12fb_da62 NULL +#define pci_ss_list_12fb_db62 NULL +#define pci_ss_list_12fb_dc62 NULL +#define pci_ss_list_12fb_dd62 NULL +#define pci_ss_list_12fb_eddc NULL +#define pci_ss_list_12fb_fa01 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#define pci_ss_list_1307_004d NULL +#define pci_ss_list_1307_0052 NULL +#define pci_ss_list_1307_0054 NULL +#define pci_ss_list_1307_005e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#define pci_ss_list_1317_0985 NULL +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1317_2850 NULL +#define pci_ss_list_1317_5120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317_8201[] = { + &pci_ss_info_1317_8201_10b8_2635, + &pci_ss_info_1317_8201_1317_8201, + NULL +}; +#define pci_ss_list_1317_8211 NULL +#define pci_ss_list_1317_9511 NULL +#endif +#define pci_ss_list_1318_0911 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319_0801[] = { + &pci_ss_info_1319_0801_1319_1319, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1319_0802[] = { + &pci_ss_info_1319_0802_1319_1319, + NULL +}; +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#endif +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#define pci_ss_list_131f_2081 NULL +#endif +#define pci_ss_list_1331_0030 NULL +#define pci_ss_list_1331_8200 NULL +#define pci_ss_list_1331_8201 NULL +#define pci_ss_list_1331_8202 NULL +#define pci_ss_list_1331_8210 NULL +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_1332_5425 NULL +#define pci_ss_list_1332_6140 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_2189 NULL +#define pci_ss_list_134d_2486 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7890[] = { + &pci_ss_info_134d_7890_134d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_5101 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1360_0101 NULL +#define pci_ss_list_1360_0102 NULL +#define pci_ss_list_1360_0103 NULL +#define pci_ss_list_1360_0201 NULL +#define pci_ss_list_1360_0202 NULL +#define pci_ss_list_1360_0203 NULL +#define pci_ss_list_1360_0301 NULL +#define pci_ss_list_1360_0302 NULL +#define pci_ss_list_136b_ff01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371_434e[] = { + &pci_ss_info_1371_434e_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1374_0024 NULL +#define pci_ss_list_1374_0025 NULL +#define pci_ss_list_1374_0026 NULL +#define pci_ss_list_1374_0027 NULL +#define pci_ss_list_1374_0029 NULL +#define pci_ss_list_1374_002a NULL +#define pci_ss_list_1374_002b NULL +#define pci_ss_list_1374_002c NULL +#define pci_ss_list_1374_002d NULL +#define pci_ss_list_1374_002e NULL +#define pci_ss_list_1374_002f NULL +#define pci_ss_list_1374_0030 NULL +#define pci_ss_list_1374_0031 NULL +#define pci_ss_list_1374_0032 NULL +#define pci_ss_list_1374_0034 NULL +#define pci_ss_list_1374_0035 NULL +#define pci_ss_list_1374_0036 NULL +#define pci_ss_list_1374_0037 NULL +#define pci_ss_list_1374_0038 NULL +#define pci_ss_list_1374_0039 NULL +#define pci_ss_list_1374_003a NULL +#define pci_ss_list_137a_0001 NULL +#define pci_ss_list_1382_0001 NULL +#define pci_ss_list_1382_2008 NULL +#define pci_ss_list_1382_2088 NULL +#define pci_ss_list_1382_20c8 NULL +#define pci_ss_list_1382_4008 NULL +#define pci_ss_list_1382_4010 NULL +#define pci_ss_list_1382_4048 NULL +#define pci_ss_list_1382_4088 NULL +#define pci_ss_list_1382_4248 NULL +#define pci_ss_list_1382_4424 NULL +#define pci_ss_list_1385_0013 NULL +#define pci_ss_list_1385_311a NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_4105 NULL +#define pci_ss_list_1385_4400 NULL +#define pci_ss_list_1385_4600 NULL +#define pci_ss_list_1385_4601 NULL +#define pci_ss_list_1385_4610 NULL +#define pci_ss_list_1385_4800 NULL +#define pci_ss_list_1385_4900 NULL +#define pci_ss_list_1385_4a00 NULL +#define pci_ss_list_1385_4b00 NULL +#define pci_ss_list_1385_4c00 NULL +#define pci_ss_list_1385_4d00 NULL +#define pci_ss_list_1385_4e00 NULL +#define pci_ss_list_1385_4f00 NULL +#define pci_ss_list_1385_5200 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_6b00 NULL +#define pci_ss_list_1385_6d00 NULL +#define pci_ss_list_1385_f004 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1141 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#define pci_ss_list_1397_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_0675_1704, + &pci_ss_info_1397_2bd0_0675_1708, + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a3_001d NULL +#define pci_ss_list_13a3_0020 NULL +#define pci_ss_list_13a3_0026 NULL +#define pci_ss_list_13a8_0152 NULL +#define pci_ss_list_13a8_0154 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c0_0020 NULL +#define pci_ss_list_13c0_0030 NULL +#define pci_ss_list_13c0_0210 NULL +#define pci_ss_list_13c1_1000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1_1001[] = { + &pci_ss_info_13c1_1001_13c1_1001, + NULL +}; +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13c1_1003 NULL +#endif +#define pci_ss_list_13c6_0520 NULL +#define pci_ss_list_13c6_0620 NULL +#define pci_ss_list_13c6_0820 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d0_2200 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab03 NULL +#define pci_ss_list_13d1_ab06 NULL +#define pci_ss_list_13d1_ab08 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13f0_0200 NULL +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f0_1023 NULL +#define pci_ss_list_13f4_1401 NULL +#define pci_ss_list_13f6_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8035, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + &pci_ss_info_13f6_0111_1681_a000, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1240 NULL +#define pci_ss_list_13fe_1600 NULL +#define pci_ss_list_13fe_1733 NULL +#define pci_ss_list_13fe_1752 NULL +#define pci_ss_list_13fe_1754 NULL +#define pci_ss_list_13fe_1756 NULL +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0110 NULL +#define pci_ss_list_1407_0111 NULL +#define pci_ss_list_1407_0120 NULL +#define pci_ss_list_1407_0121 NULL +#define pci_ss_list_1407_0180 NULL +#define pci_ss_list_1407_0181 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0220 NULL +#define pci_ss_list_1407_0221 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412_1712[] = { + &pci_ss_info_1412_1712_1412_1712, + &pci_ss_info_1412_1712_1412_d630, + &pci_ss_info_1412_1712_1412_d631, + &pci_ss_info_1412_1712_1412_d632, + &pci_ss_info_1412_1712_1412_d633, + &pci_ss_info_1412_1712_1412_d634, + &pci_ss_info_1412_1712_1412_d635, + &pci_ss_info_1412_1712_1412_d637, + &pci_ss_info_1412_1712_1412_d638, + &pci_ss_info_1412_1712_1412_d63b, + &pci_ss_info_1412_1712_1412_d63c, + &pci_ss_info_1412_1712_1416_1712, + &pci_ss_info_1412_1712_153b_1115, + &pci_ss_info_1412_1712_153b_1125, + &pci_ss_info_1412_1712_153b_112b, + &pci_ss_info_1412_1712_153b_112c, + &pci_ss_info_1412_1712_153b_1130, + &pci_ss_info_1412_1712_153b_1138, + &pci_ss_info_1412_1712_153b_1151, + &pci_ss_info_1412_1712_16ce_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1412_1724[] = { + &pci_ss_info_1412_1724_1412_1724, + &pci_ss_info_1412_1724_1412_3630, + &pci_ss_info_1412_1724_1412_3631, + &pci_ss_info_1412_1724_153b_1145, + &pci_ss_info_1412_1724_153b_1147, + &pci_ss_info_1412_1724_153b_1153, + &pci_ss_info_1412_1724_270f_f641, + &pci_ss_info_1412_1724_270f_f645, + NULL +}; +#endif +#define pci_ss_list_1415_8403 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_131f_2050, + &pci_ss_info_1415_9501_131f_2051, + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +#define pci_ss_list_1415_9510 NULL +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9521 NULL +#define pci_ss_list_1415_9523 NULL +#endif +#define pci_ss_list_1420_8002 NULL +#define pci_ss_list_1420_8003 NULL +#define pci_ss_list_1425_000b NULL +#define pci_ss_list_142e_4020 NULL +#define pci_ss_list_142e_4337 NULL +#define pci_ss_list_1432_9130 NULL +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8164 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_1458_0c11 NULL +#define pci_ss_list_1458_e911 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_1461_f436 NULL +#define pci_ss_list_1462_5501 NULL +#define pci_ss_list_1462_6819 NULL +#define pci_ss_list_1462_6825 NULL +#define pci_ss_list_1462_6834 NULL +#define pci_ss_list_1462_8725 NULL +#define pci_ss_list_1462_9000 NULL +#define pci_ss_list_1462_9110 NULL +#define pci_ss_list_1462_9119 NULL +#define pci_ss_list_1462_9591 NULL +#define pci_ss_list_146c_1430 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_1497_1497 NULL +#define pci_ss_list_1498_0330 NULL +#define pci_ss_list_1498_0385 NULL +#define pci_ss_list_1498_21cd NULL +#define pci_ss_list_1498_30c8 NULL +#define pci_ss_list_149d_0001 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14b9_a505 NULL +#define pci_ss_list_14b9_a506 NULL +#define pci_ss_list_14c1_8043 NULL +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14d9_0010 NULL +#define pci_ss_list_14d9_9000 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14db_2182 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#define pci_ss_list_14e4_0800 NULL +#define pci_ss_list_14e4_0804 NULL +#define pci_ss_list_14e4_0805 NULL +#define pci_ss_list_14e4_0806 NULL +#define pci_ss_list_14e4_080b NULL +#define pci_ss_list_14e4_080f NULL +#define pci_ss_list_14e4_0811 NULL +#define pci_ss_list_14e4_0816 NULL +#define pci_ss_list_14e4_1600 NULL +#define pci_ss_list_14e4_1601 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_103c_128a, + &pci_ss_info_14e4_1645_103c_128b, + &pci_ss_info_14e4_1645_103c_12a4, + &pci_ss_info_14e4_1645_103c_12c1, + &pci_ss_info_14e4_1645_103c_1300, + &pci_ss_info_14e4_1645_10a9_8010, + &pci_ss_info_14e4_1645_10a9_8011, + &pci_ss_info_14e4_1645_10a9_8012, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_10a9_8010, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + &pci_ss_info_14e4_1648_1734_100b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164a[] = { + &pci_ss_info_14e4_164a_103c_3101, + NULL +}; +#define pci_ss_list_14e4_164c NULL +#define pci_ss_list_14e4_164d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1653[] = { + &pci_ss_info_14e4_1653_0e11_00e3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1654[] = { + &pci_ss_info_14e4_1654_0e11_00e3, + &pci_ss_info_14e4_1654_103c_3100, + &pci_ss_info_14e4_1654_103c_3226, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1659[] = { + &pci_ss_info_14e4_1659_1014_02c6, + &pci_ss_info_14e4_1659_103c_7031, + &pci_ss_info_14e4_1659_103c_7032, + &pci_ss_info_14e4_1659_1734_1061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165d[] = { + &pci_ss_info_14e4_165d_1028_865d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165e[] = { + &pci_ss_info_14e4_165e_103c_088c, + &pci_ss_info_14e4_165e_103c_0890, + &pci_ss_info_14e4_165e_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1668[] = { + &pci_ss_info_14e4_1668_103c_7039, + NULL +}; +#define pci_ss_list_14e4_166a NULL +#define pci_ss_list_14e4_166b NULL +#define pci_ss_list_14e4_166e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1677[] = { + &pci_ss_info_14e4_1677_1028_0179, + &pci_ss_info_14e4_1677_1028_0182, + &pci_ss_info_14e4_1677_1028_01ad, + &pci_ss_info_14e4_1677_1734_105d, + NULL +}; +#define pci_ss_list_14e4_1678 NULL +#define pci_ss_list_14e4_167d NULL +#define pci_ss_list_14e4_167e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_103c_12bc, + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_169c[] = { + &pci_ss_info_14e4_169c_103c_308b, + NULL +}; +#define pci_ss_list_14e4_169d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16aa[] = { + &pci_ss_info_14e4_16aa_103c_3102, + NULL +}; +#define pci_ss_list_14e4_16ac NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_0e11_00ca, + &pci_ss_info_14e4_16c7_0e11_00cb, + &pci_ss_info_14e4_16c7_103c_12c3, + &pci_ss_info_14e4_16c7_103c_12ca, + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_16dd NULL +#define pci_ss_list_14e4_16f7 NULL +#define pci_ss_list_14e4_16fd NULL +#define pci_ss_list_14e4_16fe NULL +static const pciSubsystemInfo *pci_ss_list_14e4_170c[] = { + &pci_ss_info_14e4_170c_1028_0188, + &pci_ss_info_14e4_170c_1028_0196, + &pci_ss_info_14e4_170c_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_170d[] = { + &pci_ss_info_14e4_170d_1014_0545, + NULL +}; +#define pci_ss_list_14e4_170e NULL +#define pci_ss_list_14e4_3352 NULL +#define pci_ss_list_14e4_3360 NULL +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4301[] = { + &pci_ss_info_14e4_4301_1028_0407, + &pci_ss_info_14e4_4301_1043_0120, + NULL +}; +#define pci_ss_list_14e4_4305 NULL +#define pci_ss_list_14e4_4306 NULL +#define pci_ss_list_14e4_4307 NULL +#define pci_ss_list_14e4_4310 NULL +#define pci_ss_list_14e4_4312 NULL +#define pci_ss_list_14e4_4313 NULL +#define pci_ss_list_14e4_4315 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4318[] = { + &pci_ss_info_14e4_4318_103c_1356, + &pci_ss_info_14e4_4318_1468_0311, + &pci_ss_info_14e4_4318_1468_0312, + &pci_ss_info_14e4_4318_14e4_0449, + &pci_ss_info_14e4_4318_14e4_4318, + &pci_ss_info_14e4_4318_16ec_0119, + NULL +}; +#define pci_ss_list_14e4_4319 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4320[] = { + &pci_ss_info_14e4_4320_1028_0001, + &pci_ss_info_14e4_4320_1028_0003, + &pci_ss_info_14e4_4320_103c_12f4, + &pci_ss_info_14e4_4320_103c_12fa, + &pci_ss_info_14e4_4320_1043_100f, + &pci_ss_info_14e4_4320_1057_7025, + &pci_ss_info_14e4_4320_106b_004e, + &pci_ss_info_14e4_4320_144f_7050, + &pci_ss_info_14e4_4320_14e4_4320, + &pci_ss_info_14e4_4320_1737_4320, + &pci_ss_info_14e4_4320_1799_7001, + &pci_ss_info_14e4_4320_1799_7010, + &pci_ss_info_14e4_4320_185f_1220, + NULL +}; +#define pci_ss_list_14e4_4321 NULL +#define pci_ss_list_14e4_4322 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4324[] = { + &pci_ss_info_14e4_4324_1028_0001, + &pci_ss_info_14e4_4324_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_4325[] = { + &pci_ss_info_14e4_4325_1414_0003, + &pci_ss_info_14e4_4325_1414_0004, + NULL +}; +#define pci_ss_list_14e4_4326 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4401[] = { + &pci_ss_info_14e4_4401_1043_80a8, + NULL +}; +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4403 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_4430 NULL +#define pci_ss_list_14e4_4432 NULL +#define pci_ss_list_14e4_4610 NULL +#define pci_ss_list_14e4_4611 NULL +#define pci_ss_list_14e4_4612 NULL +#define pci_ss_list_14e4_4613 NULL +#define pci_ss_list_14e4_4614 NULL +#define pci_ss_list_14e4_4615 NULL +#define pci_ss_list_14e4_4704 NULL +#define pci_ss_list_14e4_4705 NULL +#define pci_ss_list_14e4_4706 NULL +#define pci_ss_list_14e4_4707 NULL +#define pci_ss_list_14e4_4708 NULL +#define pci_ss_list_14e4_4710 NULL +#define pci_ss_list_14e4_4711 NULL +#define pci_ss_list_14e4_4712 NULL +#define pci_ss_list_14e4_4713 NULL +#define pci_ss_list_14e4_4714 NULL +#define pci_ss_list_14e4_4715 NULL +#define pci_ss_list_14e4_4716 NULL +#define pci_ss_list_14e4_4717 NULL +#define pci_ss_list_14e4_4718 NULL +#define pci_ss_list_14e4_4719 NULL +#define pci_ss_list_14e4_4720 NULL +#define pci_ss_list_14e4_5365 NULL +#define pci_ss_list_14e4_5600 NULL +#define pci_ss_list_14e4_5605 NULL +#define pci_ss_list_14e4_5615 NULL +#define pci_ss_list_14e4_5625 NULL +#define pci_ss_list_14e4_5645 NULL +#define pci_ss_list_14e4_5670 NULL +#define pci_ss_list_14e4_5680 NULL +#define pci_ss_list_14e4_5690 NULL +#define pci_ss_list_14e4_5691 NULL +#define pci_ss_list_14e4_5692 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#define pci_ss_list_14e4_5822 NULL +#define pci_ss_list_14e4_5823 NULL +#define pci_ss_list_14e4_5824 NULL +#define pci_ss_list_14e4_5840 NULL +#define pci_ss_list_14e4_5841 NULL +#define pci_ss_list_14e4_5850 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14ea_ab07 NULL +#define pci_ss_list_14ea_ab08 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1085 NULL +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +#define pci_ss_list_14f1_1620 NULL +#define pci_ss_list_14f1_1621 NULL +#define pci_ss_list_14f1_1622 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +#define pci_ss_list_14f1_1811 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2045[] = { + &pci_ss_info_14f1_2045_14f1_2045, + NULL +}; +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_2f02 NULL +#define pci_ss_list_14f1_2f11 NULL +#define pci_ss_list_14f1_2f20 NULL +#define pci_ss_list_14f1_8234 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_8800[] = { + &pci_ss_info_14f1_8800_0070_2801, + &pci_ss_info_14f1_8800_0070_3401, + &pci_ss_info_14f1_8800_0070_9001, + &pci_ss_info_14f1_8800_0070_9200, + &pci_ss_info_14f1_8800_0070_9202, + &pci_ss_info_14f1_8800_0070_9402, + &pci_ss_info_14f1_8800_0070_9802, + &pci_ss_info_14f1_8800_1002_00f8, + &pci_ss_info_14f1_8800_1002_a101, + &pci_ss_info_14f1_8800_1043_4823, + &pci_ss_info_14f1_8800_107d_6613, + &pci_ss_info_14f1_8800_107d_6620, + &pci_ss_info_14f1_8800_107d_663c, + &pci_ss_info_14f1_8800_107d_665f, + &pci_ss_info_14f1_8800_10fc_d003, + &pci_ss_info_14f1_8800_10fc_d035, + &pci_ss_info_14f1_8800_1421_0334, + &pci_ss_info_14f1_8800_1461_000a, + &pci_ss_info_14f1_8800_1461_000b, + &pci_ss_info_14f1_8800_1461_8011, + &pci_ss_info_14f1_8800_1462_8606, + &pci_ss_info_14f1_8800_14c7_0107, + &pci_ss_info_14f1_8800_14f1_0187, + &pci_ss_info_14f1_8800_14f1_0342, + &pci_ss_info_14f1_8800_153b_1166, + &pci_ss_info_14f1_8800_1540_2580, + &pci_ss_info_14f1_8800_1554_4811, + &pci_ss_info_14f1_8800_1554_4813, + &pci_ss_info_14f1_8800_17de_08a1, + &pci_ss_info_14f1_8800_17de_08a6, + &pci_ss_info_14f1_8800_17de_08b2, + &pci_ss_info_14f1_8800_17de_a8a6, + &pci_ss_info_14f1_8800_1822_0025, + &pci_ss_info_14f1_8800_18ac_d500, + &pci_ss_info_14f1_8800_18ac_d810, + &pci_ss_info_14f1_8800_18ac_d820, + &pci_ss_info_14f1_8800_18ac_db00, + &pci_ss_info_14f1_8800_18ac_db11, + &pci_ss_info_14f1_8800_18ac_db50, + &pci_ss_info_14f1_8800_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8801[] = { + &pci_ss_info_14f1_8801_0070_2801, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8802[] = { + &pci_ss_info_14f1_8802_0070_2801, + &pci_ss_info_14f1_8802_0070_9002, + &pci_ss_info_14f1_8802_1043_4823, + &pci_ss_info_14f1_8802_107d_663c, + &pci_ss_info_14f1_8802_14f1_0187, + &pci_ss_info_14f1_8802_17de_08a1, + &pci_ss_info_14f1_8802_17de_08a6, + &pci_ss_info_14f1_8802_18ac_d500, + &pci_ss_info_14f1_8802_18ac_d810, + &pci_ss_info_14f1_8802_18ac_d820, + &pci_ss_info_14f1_8802_18ac_db00, + &pci_ss_info_14f1_8802_18ac_db10, + &pci_ss_info_14f1_8802_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8804[] = { + &pci_ss_info_14f1_8804_0070_9002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8811[] = { + &pci_ss_info_14f1_8811_0070_3401, + &pci_ss_info_14f1_8811_1462_8606, + &pci_ss_info_14f1_8811_18ac_d500, + &pci_ss_info_14f1_8811_18ac_d810, + &pci_ss_info_14f1_8811_18ac_d820, + &pci_ss_info_14f1_8811_18ac_db00, + NULL +}; +#endif +#define pci_ss_list_14f2_0120 NULL +#define pci_ss_list_14f2_0121 NULL +#define pci_ss_list_14f2_0122 NULL +#define pci_ss_list_14f2_0123 NULL +#define pci_ss_list_14f2_0124 NULL +#define pci_ss_list_14f3_2030 NULL +#define pci_ss_list_14f3_2050 NULL +#define pci_ss_list_14f3_2060 NULL +#define pci_ss_list_14f8_2077 NULL +#define pci_ss_list_14fc_0000 NULL +#define pci_ss_list_14fc_0001 NULL +#define pci_ss_list_1500_1360 NULL +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#define pci_ss_list_1516_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#define pci_ss_list_1516_0891 NULL +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151c_0003 NULL +#define pci_ss_list_151c_4000 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + &pci_ss_info_1522_0100_1522_0c00, + &pci_ss_info_1522_0100_1522_0d00, + &pci_ss_info_1522_0100_1522_1d00, + &pci_ss_info_1522_0100_1522_2000, + &pci_ss_info_1522_0100_1522_2100, + &pci_ss_info_1522_0100_1522_2200, + &pci_ss_info_1522_0100_1522_2300, + &pci_ss_info_1522_0100_1522_2400, + &pci_ss_info_1522_0100_1522_2500, + &pci_ss_info_1522_0100_1522_2600, + &pci_ss_info_1522_0100_1522_2700, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1524_0510[] = { + &pci_ss_info_1524_0510_103c_006a, + NULL +}; +#define pci_ss_list_1524_0520 NULL +#define pci_ss_list_1524_0530 NULL +#define pci_ss_list_1524_0550 NULL +#define pci_ss_list_1524_0610 NULL +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +static const pciSubsystemInfo *pci_ss_list_1524_1410[] = { + &pci_ss_info_1524_1410_1025_005a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1524_1411[] = { + &pci_ss_info_1524_1411_103c_006a, + NULL +}; +#define pci_ss_list_1524_1412 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1524_1421 NULL +#define pci_ss_list_1524_1422 NULL +#endif +#define pci_ss_list_1532_0020 NULL +#define pci_ss_list_1538_0303 NULL +#define pci_ss_list_153b_1144 NULL +#define pci_ss_list_153b_1147 NULL +#define pci_ss_list_153b_1158 NULL +#define pci_ss_list_153f_0001 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_1578_5615 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0405 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15ad_0720 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15b3_5a44 NULL +#define pci_ss_list_15b3_5a45 NULL +#define pci_ss_list_15b3_5a46 NULL +#define pci_ss_list_15b3_5e8d NULL +#define pci_ss_list_15b3_6274 NULL +#define pci_ss_list_15b3_6278 NULL +#define pci_ss_list_15b3_6279 NULL +#define pci_ss_list_15b3_6282 NULL +#define pci_ss_list_15bc_1100 NULL +#define pci_ss_list_15bc_2922 NULL +#define pci_ss_list_15bc_2928 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c5_8010 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_15e9_1841 NULL +#define pci_ss_list_15ec_3101 NULL +#define pci_ss_list_15ec_5102 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1619_0610 NULL +#define pci_ss_list_1619_0620 NULL +#define pci_ss_list_1619_0640 NULL +#define pci_ss_list_1619_1610 NULL +#define pci_ss_list_1619_2610 NULL +#define pci_ss_list_1626_8410 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1637_3874 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_3052 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_165f_1020 NULL +#define pci_ss_list_1668_0100 NULL +#define pci_ss_list_166d_0001 NULL +#define pci_ss_list_166d_0002 NULL +#define pci_ss_list_1677_104e NULL +#define pci_ss_list_1677_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_167b_2102[] = { + &pci_ss_info_167b_2102_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1681_0010 NULL +#define pci_ss_list_1688_1170 NULL +#define pci_ss_list_168c_0007 NULL +#define pci_ss_list_168c_0011 NULL +#define pci_ss_list_168c_0012 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c_0013[] = { + &pci_ss_info_168c_0013_1113_d301, + &pci_ss_info_168c_0013_1186_3202, + &pci_ss_info_168c_0013_1186_3203, + &pci_ss_info_168c_0013_1186_3a12, + &pci_ss_info_168c_0013_1186_3a13, + &pci_ss_info_168c_0013_1186_3a14, + &pci_ss_info_168c_0013_1186_3a17, + &pci_ss_info_168c_0013_1186_3a18, + &pci_ss_info_168c_0013_1186_3a63, + &pci_ss_info_168c_0013_1186_3a94, + &pci_ss_info_168c_0013_1385_4d00, + &pci_ss_info_168c_0013_1458_e911, + &pci_ss_info_168c_0013_14b7_0a60, + &pci_ss_info_168c_0013_168c_0013, + &pci_ss_info_168c_0013_168c_1025, + &pci_ss_info_168c_0013_168c_1027, + &pci_ss_info_168c_0013_168c_2026, + &pci_ss_info_168c_0013_168c_2041, + &pci_ss_info_168c_0013_168c_2042, + &pci_ss_info_168c_0013_16ab_7302, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001a[] = { + &pci_ss_info_168c_001a_1186_3a15, + &pci_ss_info_168c_001a_1186_3a16, + &pci_ss_info_168c_001a_1186_3a23, + &pci_ss_info_168c_001a_1186_3a24, + &pci_ss_info_168c_001a_168c_1052, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001b[] = { + &pci_ss_info_168c_001b_1186_3a19, + &pci_ss_info_168c_001b_1186_3a22, + NULL +}; +#define pci_ss_list_168c_0020 NULL +#define pci_ss_list_168c_1014 NULL +#endif +#define pci_ss_list_169c_0044 NULL +#define pci_ss_list_16ab_1100 NULL +#define pci_ss_list_16ab_1101 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ab_8501 NULL +#define pci_ss_list_16ae_1141 NULL +#define pci_ss_list_16ca_0001 NULL +#define pci_ss_list_16e3_1e0f NULL +#define pci_ss_list_16ec_00ff NULL +#define pci_ss_list_16ec_0116 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_16ed_1001 NULL +#define pci_ss_list_16f4_8000 NULL +#define pci_ss_list_170b_0100 NULL +#define pci_ss_list_1725_7174 NULL +#define pci_ss_list_172a_13c8 NULL +#define pci_ss_list_1737_0013 NULL +#define pci_ss_list_1737_0015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737_1032[] = { + &pci_ss_info_1737_1032_1737_0015, + &pci_ss_info_1737_1032_1737_0024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1737_1064[] = { + &pci_ss_info_1737_1064_1737_0016, + NULL +}; +#define pci_ss_list_1737_ab08 NULL +#define pci_ss_list_1737_ab09 NULL +#endif +#define pci_ss_list_173b_03e8 NULL +#define pci_ss_list_173b_03e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#define pci_ss_list_173b_03eb NULL +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_1799_6001 NULL +#define pci_ss_list_1799_6020 NULL +#define pci_ss_list_1799_6060 NULL +#define pci_ss_list_1799_7000 NULL +#define pci_ss_list_1799_7010 NULL +#define pci_ss_list_179c_0557 NULL +#define pci_ss_list_179c_0566 NULL +#define pci_ss_list_179c_5031 NULL +#define pci_ss_list_179c_5121 NULL +#define pci_ss_list_179c_5211 NULL +#define pci_ss_list_179c_5679 NULL +#define pci_ss_list_17a0_8033 NULL +#define pci_ss_list_17a0_8034 NULL +#define pci_ss_list_17b3_ab08 NULL +#define pci_ss_list_17b4_0011 NULL +#define pci_ss_list_17cc_2280 NULL +#define pci_ss_list_17d3_1110 NULL +#define pci_ss_list_17d3_1120 NULL +#define pci_ss_list_17d3_1130 NULL +#define pci_ss_list_17d3_1160 NULL +#define pci_ss_list_17d3_1210 NULL +#define pci_ss_list_17d3_1220 NULL +#define pci_ss_list_17d3_1230 NULL +#define pci_ss_list_17d3_1260 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17d5_5831[] = { + &pci_ss_info_17d5_5831_103c_12d5, + NULL +}; +#define pci_ss_list_17d5_5832 NULL +#endif +#define pci_ss_list_17fe_2120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe_2220[] = { + &pci_ss_info_17fe_2220_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1814_0101[] = { + &pci_ss_info_1814_0101_1043_0127, + &pci_ss_info_1814_0101_1462_6828, + NULL +}; +#define pci_ss_list_1814_0200 NULL +static const pciSubsystemInfo *pci_ss_list_1814_0201[] = { + &pci_ss_info_1814_0201_1043_130f, + &pci_ss_info_1814_0201_1371_001e, + &pci_ss_info_1814_0201_1371_001f, + &pci_ss_info_1814_0201_1371_0020, + &pci_ss_info_1814_0201_1458_e381, + &pci_ss_info_1814_0201_1458_e931, + &pci_ss_info_1814_0201_1462_6835, + &pci_ss_info_1814_0201_1737_0032, + &pci_ss_info_1814_0201_1799_700a, + &pci_ss_info_1814_0201_1799_701a, + &pci_ss_info_1814_0201_185f_22a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0301[] = { + &pci_ss_info_1814_0301_2561_1814, + NULL +}; +#define pci_ss_list_1814_0401 NULL +#endif +#define pci_ss_list_1822_4e35 NULL +#define pci_ss_list_182d_3069 NULL +#define pci_ss_list_182d_9790 NULL +#define pci_ss_list_183b_08a7 NULL +#define pci_ss_list_183b_08a8 NULL +#define pci_ss_list_183b_08a9 NULL +#define pci_ss_list_1864_2110 NULL +#define pci_ss_list_1867_5a44 NULL +#define pci_ss_list_1867_5a45 NULL +#define pci_ss_list_1867_5a46 NULL +#define pci_ss_list_1867_6278 NULL +#define pci_ss_list_1867_6282 NULL +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_18ac_d500 NULL +#define pci_ss_list_18ac_d810 NULL +#define pci_ss_list_18ac_d820 NULL +#define pci_ss_list_18b8_b001 NULL +#define pci_ss_list_18ca_0020 NULL +#define pci_ss_list_18ca_0040 NULL +#define pci_ss_list_18d2_3069 NULL +#define pci_ss_list_18dd_4c6f NULL +#define pci_ss_list_18e6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec_c006[] = { + &pci_ss_info_18ec_c006_18ec_d001, + &pci_ss_info_18ec_c006_18ec_d002, + &pci_ss_info_18ec_c006_18ec_d003, + &pci_ss_info_18ec_c006_18ec_d004, + NULL +}; +#define pci_ss_list_18ec_c045 NULL +#define pci_ss_list_18ec_c050 NULL +static const pciSubsystemInfo *pci_ss_list_18ec_c058[] = { + &pci_ss_info_18ec_c058_18ec_d001, + &pci_ss_info_18ec_c058_18ec_d002, + &pci_ss_info_18ec_c058_18ec_d003, + &pci_ss_info_18ec_c058_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7_0001 NULL +#define pci_ss_list_18f7_0002 NULL +#define pci_ss_list_18f7_0004 NULL +#define pci_ss_list_18f7_0005 NULL +#define pci_ss_list_18f7_000a NULL +#define pci_ss_list_1923_0100 NULL +#define pci_ss_list_1942_e511 NULL +#define pci_ss_list_1957_0080 NULL +#define pci_ss_list_1957_0081 NULL +#define pci_ss_list_1957_0082 NULL +#define pci_ss_list_1957_0083 NULL +#define pci_ss_list_1957_0084 NULL +#define pci_ss_list_1957_0085 NULL +#define pci_ss_list_1957_0086 NULL +#define pci_ss_list_1957_0087 NULL +#define pci_ss_list_1966_1975 NULL +#define pci_ss_list_196a_0101 NULL +#define pci_ss_list_196a_0102 NULL +#define pci_ss_list_197b_2360 NULL +#define pci_ss_list_197b_2363 NULL +#define pci_ss_list_1989_0001 NULL +#define pci_ss_list_1989_8001 NULL +#define pci_ss_list_19ae_0520 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_1fc0_0300 NULL +#define pci_ss_list_1fc1_000d NULL +#define pci_ss_list_1fce_0001 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_0021[] = { + &pci_ss_info_3388_0021_4c53_1050, + &pci_ss_info_3388_0021_4c53_1080, + &pci_ss_info_3388_0021_4c53_1090, + &pci_ss_info_3388_0021_4c53_10a0, + &pci_ss_info_3388_0021_4c53_3010, + &pci_ss_info_3388_0021_4c53_3011, + &pci_ss_info_3388_0021_4c53_4000, + NULL +}; +#define pci_ss_list_3388_0022 NULL +#define pci_ss_list_3388_0026 NULL +#define pci_ss_list_3388_101a NULL +#define pci_ss_list_3388_101b NULL +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3842_c370 NULL +#define pci_ss_list_3d3d_0001 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0002[] = { + &pci_ss_info_3d3d_0002_0000_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0003[] = { + &pci_ss_info_3d3d_0003_0000_0000, + NULL +}; +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0006[] = { + &pci_ss_info_3d3d_0006_0000_0000, + &pci_ss_info_3d3d_0006_1048_0a42, + NULL +}; +#define pci_ss_list_3d3d_0007 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0008[] = { + &pci_ss_info_3d3d_0008_1048_0a42, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_1048_0a42, + &pci_ss_info_3d3d_0009_13e9_1000, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_000d NULL +#define pci_ss_list_3d3d_0011 NULL +#define pci_ss_list_3d3d_0012 NULL +#define pci_ss_list_3d3d_0013 NULL +#define pci_ss_list_3d3d_0020 NULL +#define pci_ss_list_3d3d_0022 NULL +#define pci_ss_list_3d3d_0024 NULL +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_07a1 NULL +#define pci_ss_list_3d3d_07a2 NULL +#define pci_ss_list_3d3d_07a3 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_4144_0044 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4444_0016[] = { + &pci_ss_info_4444_0016_0070_0003, + &pci_ss_info_4444_0016_0070_0009, + &pci_ss_info_4444_0016_0070_0801, + &pci_ss_info_4444_0016_0070_0807, + &pci_ss_info_4444_0016_0070_4001, + &pci_ss_info_4444_0016_0070_4009, + &pci_ss_info_4444_0016_0070_4801, + &pci_ss_info_4444_0016_0070_4803, + &pci_ss_info_4444_0016_0070_8003, + &pci_ss_info_4444_0016_0070_8801, + &pci_ss_info_4444_0016_0070_c801, + &pci_ss_info_4444_0016_0070_e807, + &pci_ss_info_4444_0016_0070_e817, + &pci_ss_info_4444_0016_0270_0801, + &pci_ss_info_4444_0016_12ab_fff3, + &pci_ss_info_4444_0016_12ab_ffff, + &pci_ss_info_4444_0016_4070_8801, + &pci_ss_info_4444_0016_9005_0092, + &pci_ss_info_4444_0016_9005_0093, + &pci_ss_info_4444_0016_ff92_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4444_0803[] = { + &pci_ss_info_4444_0803_0070_4000, + &pci_ss_info_4444_0803_0070_4001, + &pci_ss_info_4444_0803_0070_4800, + &pci_ss_info_4444_0803_12ab_0000, + &pci_ss_info_4444_0803_1461_a3ce, + &pci_ss_info_4444_0803_1461_a3cf, + NULL +}; +#endif +#define pci_ss_list_4916_1960 NULL +#define pci_ss_list_494f_10e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53_0000[] = { + &pci_ss_info_4c53_0000_4c53_3000, + &pci_ss_info_4c53_0000_4c53_3001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4c53_0001[] = { + &pci_ss_info_4c53_0001_4c53_3002, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5168_0301 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_1033_8110, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + &pci_ss_info_5333_8c12_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_544c_0350 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_5654_3132 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_6666_0004 NULL +#define pci_ss_list_6666_0101 NULL +#define pci_ss_list_7063_2000 NULL +#define pci_ss_list_7063_3000 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0309 NULL +#define pci_ss_list_8086_030d NULL +#define pci_ss_list_8086_0326 NULL +#define pci_ss_list_8086_0327 NULL +#define pci_ss_list_8086_0329 NULL +#define pci_ss_list_8086_032a NULL +#define pci_ss_list_8086_032c NULL +#define pci_ss_list_8086_0330 NULL +#define pci_ss_list_8086_0331 NULL +#define pci_ss_list_8086_0332 NULL +#define pci_ss_list_8086_0333 NULL +#define pci_ss_list_8086_0334 NULL +#define pci_ss_list_8086_0335 NULL +#define pci_ss_list_8086_0336 NULL +#define pci_ss_list_8086_0340 NULL +#define pci_ss_list_8086_0341 NULL +#define pci_ss_list_8086_0370 NULL +#define pci_ss_list_8086_0371 NULL +#define pci_ss_list_8086_0372 NULL +#define pci_ss_list_8086_0373 NULL +#define pci_ss_list_8086_0374 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0500 NULL +#define pci_ss_list_8086_0501 NULL +#define pci_ss_list_8086_0502 NULL +#define pci_ss_list_8086_0503 NULL +#define pci_ss_list_8086_0510 NULL +#define pci_ss_list_8086_0511 NULL +#define pci_ss_list_8086_0512 NULL +#define pci_ss_list_8086_0513 NULL +#define pci_ss_list_8086_0514 NULL +#define pci_ss_list_8086_0515 NULL +#define pci_ss_list_8086_0516 NULL +#define pci_ss_list_8086_0530 NULL +#define pci_ss_list_8086_0531 NULL +#define pci_ss_list_8086_0532 NULL +#define pci_ss_list_8086_0533 NULL +#define pci_ss_list_8086_0534 NULL +#define pci_ss_list_8086_0535 NULL +#define pci_ss_list_8086_0536 NULL +#define pci_ss_list_8086_0537 NULL +static const pciSubsystemInfo *pci_ss_list_8086_0600[] = { + &pci_ss_info_8086_0600_8086_01af, + &pci_ss_info_8086_0600_8086_01c1, + &pci_ss_info_8086_0600_8086_01f7, + NULL +}; +#define pci_ss_list_8086_061f NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1002, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_1014_0269, + &pci_ss_info_8086_1008_1028_011c, + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + &pci_ss_info_8086_1008_8086_3108, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_1014_0268, + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +#define pci_ss_list_8086_100a NULL +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100d[] = { + &pci_ss_info_8086_100d_1028_0123, + &pci_ss_info_8086_100d_1079_891f, + &pci_ss_info_8086_100d_4c53_1080, + &pci_ss_info_8086_100d_8086_110d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_1014_0265, + &pci_ss_info_8086_100e_1014_0267, + &pci_ss_info_8086_100e_1014_026a, + &pci_ss_info_8086_100e_1024_0134, + &pci_ss_info_8086_100e_1028_002e, + &pci_ss_info_8086_100e_1028_0151, + &pci_ss_info_8086_100e_107b_8920, + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + &pci_ss_info_8086_100e_8086_1376, + &pci_ss_info_8086_100e_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_1014_0269, + &pci_ss_info_8086_100f_1014_028e, + &pci_ss_info_8086_100f_8086_1000, + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_0e11_00db, + &pci_ss_info_8086_1010_1014_027c, + &pci_ss_info_8086_1010_18fb_7872, + &pci_ss_info_8086_1010_1fc1_0026, + &pci_ss_info_8086_1010_4c53_1080, + &pci_ss_info_8086_1010_4c53_10a0, + &pci_ss_info_8086_1010_8086_1011, + &pci_ss_info_8086_1010_8086_1012, + &pci_ss_info_8086_1010_8086_101a, + &pci_ss_info_8086_1010_8086_3424, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_1014_0268, + &pci_ss_info_8086_1011_8086_1002, + &pci_ss_info_8086_1011_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_0e11_00dc, + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1013[] = { + &pci_ss_info_8086_1013_8086_0013, + &pci_ss_info_8086_1013_8086_1013, + &pci_ss_info_8086_1013_8086_1113, + NULL +}; +#define pci_ss_list_8086_1014 NULL +#define pci_ss_list_8086_1015 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1016[] = { + &pci_ss_info_8086_1016_1014_052c, + &pci_ss_info_8086_1016_1179_0001, + &pci_ss_info_8086_1016_8086_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1017[] = { + &pci_ss_info_8086_1017_8086_1017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1018[] = { + &pci_ss_info_8086_1018_8086_1018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1019[] = { + &pci_ss_info_8086_1019_1458_1019, + &pci_ss_info_8086_1019_1458_e000, + &pci_ss_info_8086_1019_8086_1019, + &pci_ss_info_8086_1019_8086_301f, + &pci_ss_info_8086_1019_8086_3427, + NULL +}; +#define pci_ss_list_8086_101a NULL +static const pciSubsystemInfo *pci_ss_list_8086_101d[] = { + &pci_ss_info_8086_101d_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101e[] = { + &pci_ss_info_8086_101e_1014_0549, + &pci_ss_info_8086_101e_1179_0001, + &pci_ss_info_8086_101e_8086_101e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1026[] = { + &pci_ss_info_8086_1026_1028_0169, + &pci_ss_info_8086_1026_8086_1000, + &pci_ss_info_8086_1026_8086_1001, + &pci_ss_info_8086_1026_8086_1002, + &pci_ss_info_8086_1026_8086_1026, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1027[] = { + &pci_ss_info_8086_1027_103c_3103, + &pci_ss_info_8086_1027_8086_1001, + &pci_ss_info_8086_1027_8086_1002, + &pci_ss_info_8086_1027_8086_1003, + &pci_ss_info_8086_1027_8086_1027, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1028[] = { + &pci_ss_info_8086_1028_8086_1028, + NULL +}; +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + &pci_ss_info_8086_1031_813c_104d, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1038[] = { + &pci_ss_info_8086_1038_0e11_0098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1039[] = { + &pci_ss_info_8086_1039_1014_0267, + NULL +}; +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +#define pci_ss_list_8086_103d NULL +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1043[] = { + &pci_ss_info_8086_1043_8086_2527, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1048[] = { + &pci_ss_info_8086_1048_8086_a01f, + &pci_ss_info_8086_1048_8086_a11f, + NULL +}; +#define pci_ss_list_8086_104b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1050[] = { + &pci_ss_info_8086_1050_1462_728c, + &pci_ss_info_8086_1050_1462_758c, + &pci_ss_info_8086_1050_8086_3020, + &pci_ss_info_8086_1050_8086_302f, + &pci_ss_info_8086_1050_8086_3427, + NULL +}; +#define pci_ss_list_8086_1051 NULL +#define pci_ss_list_8086_1052 NULL +#define pci_ss_list_8086_1053 NULL +#define pci_ss_list_8086_1059 NULL +#define pci_ss_list_8086_105e NULL +#define pci_ss_list_8086_105f NULL +#define pci_ss_list_8086_1060 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1064[] = { + &pci_ss_info_8086_1064_1043_80f8, + NULL +}; +#define pci_ss_list_8086_1065 NULL +#define pci_ss_list_8086_1066 NULL +#define pci_ss_list_8086_1067 NULL +#define pci_ss_list_8086_1068 NULL +#define pci_ss_list_8086_1069 NULL +#define pci_ss_list_8086_106a NULL +#define pci_ss_list_8086_106b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1075[] = { + &pci_ss_info_8086_1075_1028_0165, + &pci_ss_info_8086_1075_8086_0075, + &pci_ss_info_8086_1075_8086_1075, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1076[] = { + &pci_ss_info_8086_1076_1028_0165, + &pci_ss_info_8086_1076_1028_019a, + &pci_ss_info_8086_1076_8086_0076, + &pci_ss_info_8086_1076_8086_1076, + &pci_ss_info_8086_1076_8086_1176, + &pci_ss_info_8086_1076_8086_1276, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1077[] = { + &pci_ss_info_8086_1077_1179_0001, + &pci_ss_info_8086_1077_8086_0077, + &pci_ss_info_8086_1077_8086_1077, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1078[] = { + &pci_ss_info_8086_1078_8086_1078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1079[] = { + &pci_ss_info_8086_1079_103c_12a6, + &pci_ss_info_8086_1079_103c_12cf, + &pci_ss_info_8086_1079_1fc1_0027, + &pci_ss_info_8086_1079_4c53_1090, + &pci_ss_info_8086_1079_4c53_10b0, + &pci_ss_info_8086_1079_8086_0079, + &pci_ss_info_8086_1079_8086_1079, + &pci_ss_info_8086_1079_8086_1179, + &pci_ss_info_8086_1079_8086_117a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107a[] = { + &pci_ss_info_8086_107a_103c_12a8, + &pci_ss_info_8086_107a_8086_107a, + &pci_ss_info_8086_107a_8086_127a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107b[] = { + &pci_ss_info_8086_107b_8086_007b, + &pci_ss_info_8086_107b_8086_107b, + NULL +}; +#define pci_ss_list_8086_107c NULL +#define pci_ss_list_8086_107d NULL +#define pci_ss_list_8086_107e NULL +#define pci_ss_list_8086_107f NULL +#define pci_ss_list_8086_1080 NULL +#define pci_ss_list_8086_1081 NULL +#define pci_ss_list_8086_1082 NULL +#define pci_ss_list_8086_1083 NULL +#define pci_ss_list_8086_1084 NULL +#define pci_ss_list_8086_1085 NULL +#define pci_ss_list_8086_1086 NULL +#define pci_ss_list_8086_1087 NULL +#define pci_ss_list_8086_1089 NULL +#define pci_ss_list_8086_108a NULL +#define pci_ss_list_8086_108b NULL +#define pci_ss_list_8086_108c NULL +#define pci_ss_list_8086_1096 NULL +#define pci_ss_list_8086_1097 NULL +#define pci_ss_list_8086_1098 NULL +#define pci_ss_list_8086_1099 NULL +#define pci_ss_list_8086_109a NULL +#define pci_ss_list_8086_1107 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + &pci_ss_info_8086_1130_8086_4532, + &pci_ss_info_8086_1130_8086_4557, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + &pci_ss_info_8086_1132_8086_4532, + &pci_ss_info_8086_1132_8086_4541, + &pci_ss_info_8086_1132_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1209[] = { + &pci_ss_info_8086_1209_4c53_1050, + &pci_ss_info_8086_1209_4c53_1051, + &pci_ss_info_8086_1209_4c53_1070, + NULL +}; +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1028_00ce, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_108e_10cf, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_110a_008b, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_13e9_1000, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_4c53_1080, + &pci_ss_info_8086_1229_4c53_10e0, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + &pci_ss_info_8086_1229_8086_3411, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123e NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + &pci_ss_info_8086_1461_4c53_1090, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + &pci_ss_info_8086_1960_e4bf_1010, + &pci_ss_info_8086_1960_e4bf_1020, + &pci_ss_info_8086_1960_e4bf_1040, + &pci_ss_info_8086_1960_e4bf_3100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1a30[] = { + &pci_ss_info_8086_1a30_1028_010e, + NULL +}; +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_1a38 NULL +#define pci_ss_list_8086_1a48 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_110a_0051, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + &pci_ss_info_8086_2415_1734_1025, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_1028_010e, + &pci_ss_info_8086_2442_1043_8027, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + &pci_ss_info_8086_2442_8086_4532, + &pci_ss_info_8086_2442_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1028_010e, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + &pci_ss_info_8086_2443_8086_4532, + &pci_ss_info_8086_2443_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_1028_010e, + &pci_ss_info_8086_2444_1043_8027, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + &pci_ss_info_8086_2444_8086_4532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + &pci_ss_info_8086_2445_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2448[] = { + &pci_ss_info_8086_2448_103c_099c, + &pci_ss_info_8086_2448_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_1014_0265, + &pci_ss_info_8086_2449_1014_0267, + &pci_ss_info_8086_2449_1014_026a, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1179_ff01, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1028_010e, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + &pci_ss_info_8086_244b_8086_4532, + &pci_ss_info_8086_244b_8086_4557, + NULL +}; +#define pci_ss_list_8086_244c NULL +static const pciSubsystemInfo *pci_ss_list_8086_244e[] = { + &pci_ss_info_8086_244e_1014_0267, + NULL +}; +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_0e11_0030, + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + &pci_ss_info_8086_2482_8086_3424, + &pci_ss_info_8086_2482_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_0e11_0030, + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1013_5959, + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_101f_1025, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_1179_0001, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_0e11_0030, + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_0e11_0030, + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + &pci_ss_info_8086_248a_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1014_0267, + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1014_0267, + &pci_ss_info_8086_24c2_1025_005a, + &pci_ss_info_8086_24c2_1028_0126, + &pci_ss_info_8086_24c2_1028_0163, + &pci_ss_info_8086_24c2_1028_0196, + &pci_ss_info_8086_24c2_103c_088c, + &pci_ss_info_8086_24c2_103c_0890, + &pci_ss_info_8086_24c2_1071_8160, + &pci_ss_info_8086_24c2_1462_5800, + &pci_ss_info_8086_24c2_1509_2990, + &pci_ss_info_8086_24c2_1734_1055, + &pci_ss_info_8086_24c2_4c53_1090, + &pci_ss_info_8086_24c2_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1014_0267, + &pci_ss_info_8086_24c3_1025_005a, + &pci_ss_info_8086_24c3_1028_0126, + &pci_ss_info_8086_24c3_103c_088c, + &pci_ss_info_8086_24c3_103c_0890, + &pci_ss_info_8086_24c3_1071_8160, + &pci_ss_info_8086_24c3_1458_24c2, + &pci_ss_info_8086_24c3_1462_5800, + &pci_ss_info_8086_24c3_1734_1055, + &pci_ss_info_8086_24c3_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1014_0267, + &pci_ss_info_8086_24c4_1025_005a, + &pci_ss_info_8086_24c4_1028_0126, + &pci_ss_info_8086_24c4_1028_0163, + &pci_ss_info_8086_24c4_1028_0196, + &pci_ss_info_8086_24c4_103c_088c, + &pci_ss_info_8086_24c4_103c_0890, + &pci_ss_info_8086_24c4_1071_8160, + &pci_ss_info_8086_24c4_1462_5800, + &pci_ss_info_8086_24c4_1509_2990, + &pci_ss_info_8086_24c4_4c53_1090, + &pci_ss_info_8086_24c4_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_0e11_00b8, + &pci_ss_info_8086_24c5_1014_0267, + &pci_ss_info_8086_24c5_1025_005a, + &pci_ss_info_8086_24c5_1028_0139, + &pci_ss_info_8086_24c5_1028_0163, + &pci_ss_info_8086_24c5_1028_0196, + &pci_ss_info_8086_24c5_103c_088c, + &pci_ss_info_8086_24c5_103c_0890, + &pci_ss_info_8086_24c5_1071_8160, + &pci_ss_info_8086_24c5_1458_a002, + &pci_ss_info_8086_24c5_1462_5800, + &pci_ss_info_8086_24c5_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c6[] = { + &pci_ss_info_8086_24c6_1025_005a, + &pci_ss_info_8086_24c6_1028_0196, + &pci_ss_info_8086_24c6_103c_088c, + &pci_ss_info_8086_24c6_103c_0890, + &pci_ss_info_8086_24c6_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1014_0267, + &pci_ss_info_8086_24c7_1025_005a, + &pci_ss_info_8086_24c7_1028_0126, + &pci_ss_info_8086_24c7_1028_0163, + &pci_ss_info_8086_24c7_1028_0196, + &pci_ss_info_8086_24c7_103c_088c, + &pci_ss_info_8086_24c7_103c_0890, + &pci_ss_info_8086_24c7_1071_8160, + &pci_ss_info_8086_24c7_1462_5800, + &pci_ss_info_8086_24c7_1509_2990, + &pci_ss_info_8086_24c7_4c53_1090, + &pci_ss_info_8086_24c7_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24ca[] = { + &pci_ss_info_8086_24ca_1025_005a, + &pci_ss_info_8086_24ca_1028_0163, + &pci_ss_info_8086_24ca_1028_0196, + &pci_ss_info_8086_24ca_103c_088c, + &pci_ss_info_8086_24ca_103c_0890, + &pci_ss_info_8086_24ca_1071_8160, + &pci_ss_info_8086_24ca_1734_1055, + &pci_ss_info_8086_24ca_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1014_0267, + &pci_ss_info_8086_24cb_1028_0126, + &pci_ss_info_8086_24cb_1458_24c2, + &pci_ss_info_8086_24cb_1462_5800, + &pci_ss_info_8086_24cb_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cc[] = { + &pci_ss_info_8086_24cc_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1014_0267, + &pci_ss_info_8086_24cd_1025_005a, + &pci_ss_info_8086_24cd_1028_011d, + &pci_ss_info_8086_24cd_1028_0126, + &pci_ss_info_8086_24cd_1028_0139, + &pci_ss_info_8086_24cd_1028_0163, + &pci_ss_info_8086_24cd_1028_0196, + &pci_ss_info_8086_24cd_103c_088c, + &pci_ss_info_8086_24cd_103c_0890, + &pci_ss_info_8086_24cd_1071_8160, + &pci_ss_info_8086_24cd_1462_3981, + &pci_ss_info_8086_24cd_1509_1968, + &pci_ss_info_8086_24cd_1734_1055, + &pci_ss_info_8086_24cd_4c53_1090, + NULL +}; +#define pci_ss_list_8086_24d0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d1[] = { + &pci_ss_info_8086_24d1_1028_0169, + &pci_ss_info_8086_24d1_1028_019a, + &pci_ss_info_8086_24d1_103c_12bc, + &pci_ss_info_8086_24d1_1043_80a6, + &pci_ss_info_8086_24d1_1458_24d1, + &pci_ss_info_8086_24d1_1462_7280, + &pci_ss_info_8086_24d1_15d9_4580, + &pci_ss_info_8086_24d1_8086_3427, + &pci_ss_info_8086_24d1_8086_4246, + &pci_ss_info_8086_24d1_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d2[] = { + &pci_ss_info_8086_24d2_1014_02ed, + &pci_ss_info_8086_24d2_1028_0169, + &pci_ss_info_8086_24d2_1028_0183, + &pci_ss_info_8086_24d2_1028_019a, + &pci_ss_info_8086_24d2_103c_006a, + &pci_ss_info_8086_24d2_103c_12bc, + &pci_ss_info_8086_24d2_1043_80a6, + &pci_ss_info_8086_24d2_1458_24d2, + &pci_ss_info_8086_24d2_1462_7280, + &pci_ss_info_8086_24d2_15d9_4580, + &pci_ss_info_8086_24d2_1734_101c, + &pci_ss_info_8086_24d2_8086_3427, + &pci_ss_info_8086_24d2_8086_4246, + &pci_ss_info_8086_24d2_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d3[] = { + &pci_ss_info_8086_24d3_1014_02ed, + &pci_ss_info_8086_24d3_1028_0169, + &pci_ss_info_8086_24d3_1043_80a6, + &pci_ss_info_8086_24d3_1458_24d2, + &pci_ss_info_8086_24d3_1462_7280, + &pci_ss_info_8086_24d3_15d9_4580, + &pci_ss_info_8086_24d3_1734_101c, + &pci_ss_info_8086_24d3_8086_3427, + &pci_ss_info_8086_24d3_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d4[] = { + &pci_ss_info_8086_24d4_1014_02ed, + &pci_ss_info_8086_24d4_1028_0169, + &pci_ss_info_8086_24d4_1028_0183, + &pci_ss_info_8086_24d4_1028_019a, + &pci_ss_info_8086_24d4_103c_006a, + &pci_ss_info_8086_24d4_103c_12bc, + &pci_ss_info_8086_24d4_1043_80a6, + &pci_ss_info_8086_24d4_1458_24d2, + &pci_ss_info_8086_24d4_1462_7280, + &pci_ss_info_8086_24d4_15d9_4580, + &pci_ss_info_8086_24d4_1734_101c, + &pci_ss_info_8086_24d4_8086_3427, + &pci_ss_info_8086_24d4_8086_4246, + &pci_ss_info_8086_24d4_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d5[] = { + &pci_ss_info_8086_24d5_1028_0169, + &pci_ss_info_8086_24d5_103c_006a, + &pci_ss_info_8086_24d5_103c_12bc, + &pci_ss_info_8086_24d5_1043_80f3, + &pci_ss_info_8086_24d5_1043_810f, + &pci_ss_info_8086_24d5_1458_a002, + &pci_ss_info_8086_24d5_1462_0080, + &pci_ss_info_8086_24d5_1462_7280, + &pci_ss_info_8086_24d5_8086_a000, + &pci_ss_info_8086_24d5_8086_e000, + &pci_ss_info_8086_24d5_8086_e001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d6[] = { + &pci_ss_info_8086_24d6_103c_006a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d7[] = { + &pci_ss_info_8086_24d7_1014_02ed, + &pci_ss_info_8086_24d7_1028_0169, + &pci_ss_info_8086_24d7_1028_0183, + &pci_ss_info_8086_24d7_103c_006a, + &pci_ss_info_8086_24d7_103c_12bc, + &pci_ss_info_8086_24d7_1043_80a6, + &pci_ss_info_8086_24d7_1458_24d2, + &pci_ss_info_8086_24d7_1462_7280, + &pci_ss_info_8086_24d7_15d9_4580, + &pci_ss_info_8086_24d7_1734_101c, + &pci_ss_info_8086_24d7_8086_3427, + &pci_ss_info_8086_24d7_8086_4246, + &pci_ss_info_8086_24d7_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24db[] = { + &pci_ss_info_8086_24db_1014_02ed, + &pci_ss_info_8086_24db_1028_0169, + &pci_ss_info_8086_24db_1028_019a, + &pci_ss_info_8086_24db_103c_006a, + &pci_ss_info_8086_24db_103c_12bc, + &pci_ss_info_8086_24db_1043_80a6, + &pci_ss_info_8086_24db_1458_24d2, + &pci_ss_info_8086_24db_1462_7280, + &pci_ss_info_8086_24db_1462_7580, + &pci_ss_info_8086_24db_15d9_4580, + &pci_ss_info_8086_24db_1734_101c, + &pci_ss_info_8086_24db_8086_24db, + &pci_ss_info_8086_24db_8086_3427, + &pci_ss_info_8086_24db_8086_4246, + &pci_ss_info_8086_24db_8086_524c, + NULL +}; +#define pci_ss_list_8086_24dc NULL +static const pciSubsystemInfo *pci_ss_list_8086_24dd[] = { + &pci_ss_info_8086_24dd_1014_02ed, + &pci_ss_info_8086_24dd_1028_0169, + &pci_ss_info_8086_24dd_1028_0183, + &pci_ss_info_8086_24dd_1028_019a, + &pci_ss_info_8086_24dd_103c_006a, + &pci_ss_info_8086_24dd_103c_12bc, + &pci_ss_info_8086_24dd_1043_80a6, + &pci_ss_info_8086_24dd_1458_5006, + &pci_ss_info_8086_24dd_1462_7280, + &pci_ss_info_8086_24dd_8086_3427, + &pci_ss_info_8086_24dd_8086_4246, + &pci_ss_info_8086_24dd_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24de[] = { + &pci_ss_info_8086_24de_1014_02ed, + &pci_ss_info_8086_24de_1028_0169, + &pci_ss_info_8086_24de_1043_80a6, + &pci_ss_info_8086_24de_1458_24d2, + &pci_ss_info_8086_24de_1462_7280, + &pci_ss_info_8086_24de_15d9_4580, + &pci_ss_info_8086_24de_1734_101c, + &pci_ss_info_8086_24de_8086_3427, + &pci_ss_info_8086_24de_8086_4246, + &pci_ss_info_8086_24de_8086_524c, + NULL +}; +#define pci_ss_list_8086_24df NULL +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + &pci_ss_info_8086_2541_4c53_1090, + &pci_ss_info_8086_2541_8086_3424, + NULL +}; +#define pci_ss_list_8086_2543 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2544[] = { + &pci_ss_info_8086_2544_4c53_1090, + NULL +}; +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_254c[] = { + &pci_ss_info_8086_254c_4c53_1090, + &pci_ss_info_8086_254c_8086_3424, + NULL +}; +#define pci_ss_list_8086_2550 NULL +#define pci_ss_list_8086_2551 NULL +#define pci_ss_list_8086_2552 NULL +#define pci_ss_list_8086_2553 NULL +#define pci_ss_list_8086_2554 NULL +#define pci_ss_list_8086_255d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1028_0126, + &pci_ss_info_8086_2560_1458_2560, + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2562[] = { + &pci_ss_info_8086_2562_1014_0267, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2570[] = { + &pci_ss_info_8086_2570_103c_006a, + &pci_ss_info_8086_2570_1043_80f2, + &pci_ss_info_8086_2570_1458_2570, + NULL +}; +#define pci_ss_list_8086_2571 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2572[] = { + &pci_ss_info_8086_2572_1028_019d, + &pci_ss_info_8086_2572_1043_80a5, + NULL +}; +#define pci_ss_list_8086_2573 NULL +#define pci_ss_list_8086_2576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2578[] = { + &pci_ss_info_8086_2578_1458_2578, + &pci_ss_info_8086_2578_1462_7580, + &pci_ss_info_8086_2578_15d9_4580, + NULL +}; +#define pci_ss_list_8086_2579 NULL +#define pci_ss_list_8086_257b NULL +#define pci_ss_list_8086_257e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2580[] = { + &pci_ss_info_8086_2580_1458_2580, + &pci_ss_info_8086_2580_1462_7028, + &pci_ss_info_8086_2580_1734_105b, + NULL +}; +#define pci_ss_list_8086_2581 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2582[] = { + &pci_ss_info_8086_2582_1028_1079, + &pci_ss_info_8086_2582_1043_2582, + &pci_ss_info_8086_2582_1458_2582, + &pci_ss_info_8086_2582_1734_105b, + NULL +}; +#define pci_ss_list_8086_2584 NULL +#define pci_ss_list_8086_2585 NULL +#define pci_ss_list_8086_2588 NULL +#define pci_ss_list_8086_2589 NULL +#define pci_ss_list_8086_258a NULL +static const pciSubsystemInfo *pci_ss_list_8086_2590[] = { + &pci_ss_info_8086_2590_103c_099c, + &pci_ss_info_8086_2590_a304_81b7, + NULL +}; +#define pci_ss_list_8086_2591 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2592[] = { + &pci_ss_info_8086_2592_103c_099c, + &pci_ss_info_8086_2592_1043_1881, + NULL +}; +#define pci_ss_list_8086_25a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a2[] = { + &pci_ss_info_8086_25a2_4c53_10b0, + &pci_ss_info_8086_25a2_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a3[] = { + &pci_ss_info_8086_25a3_4c53_10b0, + &pci_ss_info_8086_25a3_4c53_10d0, + &pci_ss_info_8086_25a3_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a4[] = { + &pci_ss_info_8086_25a4_4c53_10b0, + &pci_ss_info_8086_25a4_4c53_10d0, + &pci_ss_info_8086_25a4_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a6[] = { + &pci_ss_info_8086_25a6_4c53_10b0, + NULL +}; +#define pci_ss_list_8086_25a7 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a9[] = { + &pci_ss_info_8086_25a9_4c53_10b0, + &pci_ss_info_8086_25a9_4c53_10d0, + &pci_ss_info_8086_25a9_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25aa[] = { + &pci_ss_info_8086_25aa_4c53_10b0, + &pci_ss_info_8086_25aa_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ab[] = { + &pci_ss_info_8086_25ab_4c53_10b0, + &pci_ss_info_8086_25ab_4c53_10d0, + &pci_ss_info_8086_25ab_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ac[] = { + &pci_ss_info_8086_25ac_4c53_10b0, + &pci_ss_info_8086_25ac_4c53_10d0, + &pci_ss_info_8086_25ac_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ad[] = { + &pci_ss_info_8086_25ad_4c53_10b0, + &pci_ss_info_8086_25ad_4c53_10d0, + &pci_ss_info_8086_25ad_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25ae NULL +static const pciSubsystemInfo *pci_ss_list_8086_25b0[] = { + &pci_ss_info_8086_25b0_4c53_10d0, + &pci_ss_info_8086_25b0_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25c0 NULL +#define pci_ss_list_8086_25d0 NULL +#define pci_ss_list_8086_25d4 NULL +#define pci_ss_list_8086_25d8 NULL +#define pci_ss_list_8086_25e2 NULL +#define pci_ss_list_8086_25e3 NULL +#define pci_ss_list_8086_25e4 NULL +#define pci_ss_list_8086_25e5 NULL +#define pci_ss_list_8086_25e6 NULL +#define pci_ss_list_8086_25e7 NULL +#define pci_ss_list_8086_25e8 NULL +#define pci_ss_list_8086_25f0 NULL +#define pci_ss_list_8086_25f1 NULL +#define pci_ss_list_8086_25f3 NULL +#define pci_ss_list_8086_25f5 NULL +#define pci_ss_list_8086_25f6 NULL +#define pci_ss_list_8086_25f7 NULL +#define pci_ss_list_8086_25f8 NULL +#define pci_ss_list_8086_25f9 NULL +#define pci_ss_list_8086_25fa NULL +#define pci_ss_list_8086_2600 NULL +#define pci_ss_list_8086_2601 NULL +#define pci_ss_list_8086_2602 NULL +#define pci_ss_list_8086_2603 NULL +#define pci_ss_list_8086_2604 NULL +#define pci_ss_list_8086_2605 NULL +#define pci_ss_list_8086_2606 NULL +#define pci_ss_list_8086_2607 NULL +#define pci_ss_list_8086_2608 NULL +#define pci_ss_list_8086_2609 NULL +#define pci_ss_list_8086_260a NULL +#define pci_ss_list_8086_260c NULL +#define pci_ss_list_8086_2610 NULL +#define pci_ss_list_8086_2611 NULL +#define pci_ss_list_8086_2612 NULL +#define pci_ss_list_8086_2613 NULL +#define pci_ss_list_8086_2614 NULL +#define pci_ss_list_8086_2615 NULL +#define pci_ss_list_8086_2617 NULL +#define pci_ss_list_8086_2618 NULL +#define pci_ss_list_8086_2619 NULL +#define pci_ss_list_8086_261a NULL +#define pci_ss_list_8086_261b NULL +#define pci_ss_list_8086_261c NULL +#define pci_ss_list_8086_261d NULL +#define pci_ss_list_8086_261e NULL +#define pci_ss_list_8086_2620 NULL +#define pci_ss_list_8086_2621 NULL +#define pci_ss_list_8086_2622 NULL +#define pci_ss_list_8086_2623 NULL +#define pci_ss_list_8086_2624 NULL +#define pci_ss_list_8086_2625 NULL +#define pci_ss_list_8086_2626 NULL +#define pci_ss_list_8086_2627 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2640[] = { + &pci_ss_info_8086_2640_1462_7028, + &pci_ss_info_8086_2640_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2641[] = { + &pci_ss_info_8086_2641_103c_099c, + NULL +}; +#define pci_ss_list_8086_2642 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2651[] = { + &pci_ss_info_8086_2651_1028_0179, + &pci_ss_info_8086_2651_1043_2601, + &pci_ss_info_8086_2651_1734_105c, + &pci_ss_info_8086_2651_8086_4147, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2652[] = { + &pci_ss_info_8086_2652_1462_7028, + NULL +}; +#define pci_ss_list_8086_2653 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2658[] = { + &pci_ss_info_8086_2658_1028_0179, + &pci_ss_info_8086_2658_103c_099c, + &pci_ss_info_8086_2658_1043_80a6, + &pci_ss_info_8086_2658_1458_2558, + &pci_ss_info_8086_2658_1462_7028, + &pci_ss_info_8086_2658_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2659[] = { + &pci_ss_info_8086_2659_1028_0179, + &pci_ss_info_8086_2659_103c_099c, + &pci_ss_info_8086_2659_1043_80a6, + &pci_ss_info_8086_2659_1458_2659, + &pci_ss_info_8086_2659_1462_7028, + &pci_ss_info_8086_2659_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265a[] = { + &pci_ss_info_8086_265a_1028_0179, + &pci_ss_info_8086_265a_103c_099c, + &pci_ss_info_8086_265a_1043_80a6, + &pci_ss_info_8086_265a_1458_265a, + &pci_ss_info_8086_265a_1462_7028, + &pci_ss_info_8086_265a_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265b[] = { + &pci_ss_info_8086_265b_1028_0179, + &pci_ss_info_8086_265b_103c_099c, + &pci_ss_info_8086_265b_1043_80a6, + &pci_ss_info_8086_265b_1458_265a, + &pci_ss_info_8086_265b_1462_7028, + &pci_ss_info_8086_265b_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265c[] = { + &pci_ss_info_8086_265c_1028_0179, + &pci_ss_info_8086_265c_103c_099c, + &pci_ss_info_8086_265c_1043_80a6, + &pci_ss_info_8086_265c_1458_5006, + &pci_ss_info_8086_265c_1462_7028, + &pci_ss_info_8086_265c_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2660[] = { + &pci_ss_info_8086_2660_103c_099c, + NULL +}; +#define pci_ss_list_8086_2662 NULL +#define pci_ss_list_8086_2664 NULL +#define pci_ss_list_8086_2666 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2668[] = { + &pci_ss_info_8086_2668_1043_814e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266a[] = { + &pci_ss_info_8086_266a_1028_0179, + &pci_ss_info_8086_266a_1043_80a6, + &pci_ss_info_8086_266a_1458_266a, + &pci_ss_info_8086_266a_1462_7028, + &pci_ss_info_8086_266a_1734_105c, + NULL +}; +#define pci_ss_list_8086_266c NULL +static const pciSubsystemInfo *pci_ss_list_8086_266d[] = { + &pci_ss_info_8086_266d_1025_006a, + &pci_ss_info_8086_266d_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266e[] = { + &pci_ss_info_8086_266e_1025_006a, + &pci_ss_info_8086_266e_1028_0179, + &pci_ss_info_8086_266e_1028_0182, + &pci_ss_info_8086_266e_1028_0188, + &pci_ss_info_8086_266e_103c_099c, + &pci_ss_info_8086_266e_1458_a002, + &pci_ss_info_8086_266e_1734_105a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266f[] = { + &pci_ss_info_8086_266f_103c_099c, + &pci_ss_info_8086_266f_1043_80a6, + &pci_ss_info_8086_266f_1458_266f, + &pci_ss_info_8086_266f_1462_7028, + &pci_ss_info_8086_266f_1734_105c, + NULL +}; +#define pci_ss_list_8086_2670 NULL +#define pci_ss_list_8086_2680 NULL +#define pci_ss_list_8086_2681 NULL +#define pci_ss_list_8086_2682 NULL +#define pci_ss_list_8086_2683 NULL +#define pci_ss_list_8086_2688 NULL +#define pci_ss_list_8086_2689 NULL +#define pci_ss_list_8086_268a NULL +#define pci_ss_list_8086_268b NULL +#define pci_ss_list_8086_268c NULL +#define pci_ss_list_8086_2690 NULL +#define pci_ss_list_8086_2692 NULL +#define pci_ss_list_8086_2694 NULL +#define pci_ss_list_8086_2696 NULL +#define pci_ss_list_8086_2698 NULL +#define pci_ss_list_8086_2699 NULL +#define pci_ss_list_8086_269a NULL +#define pci_ss_list_8086_269b NULL +#define pci_ss_list_8086_269e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2770[] = { + &pci_ss_info_8086_2770_8086_544e, + NULL +}; +#define pci_ss_list_8086_2771 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2772[] = { + &pci_ss_info_8086_2772_8086_544e, + NULL +}; +#define pci_ss_list_8086_2774 NULL +#define pci_ss_list_8086_2775 NULL +#define pci_ss_list_8086_2776 NULL +#define pci_ss_list_8086_2778 NULL +#define pci_ss_list_8086_2779 NULL +#define pci_ss_list_8086_277a NULL +#define pci_ss_list_8086_277c NULL +#define pci_ss_list_8086_277d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2782[] = { + &pci_ss_info_8086_2782_1043_2582, + &pci_ss_info_8086_2782_1734_105b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2792[] = { + &pci_ss_info_8086_2792_103c_099c, + &pci_ss_info_8086_2792_1043_1881, + NULL +}; +#define pci_ss_list_8086_27a0 NULL +#define pci_ss_list_8086_27a1 NULL +#define pci_ss_list_8086_27a2 NULL +#define pci_ss_list_8086_27a6 NULL +#define pci_ss_list_8086_27b0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27b8[] = { + &pci_ss_info_8086_27b8_8086_544e, + NULL +}; +#define pci_ss_list_8086_27b9 NULL +#define pci_ss_list_8086_27bd NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c0[] = { + &pci_ss_info_8086_27c0_8086_544e, + NULL +}; +#define pci_ss_list_8086_27c1 NULL +#define pci_ss_list_8086_27c3 NULL +#define pci_ss_list_8086_27c4 NULL +#define pci_ss_list_8086_27c5 NULL +#define pci_ss_list_8086_27c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c8[] = { + &pci_ss_info_8086_27c8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27c9[] = { + &pci_ss_info_8086_27c9_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27ca[] = { + &pci_ss_info_8086_27ca_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cb[] = { + &pci_ss_info_8086_27cb_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cc[] = { + &pci_ss_info_8086_27cc_8086_544e, + NULL +}; +#define pci_ss_list_8086_27d0 NULL +#define pci_ss_list_8086_27d2 NULL +#define pci_ss_list_8086_27d4 NULL +#define pci_ss_list_8086_27d6 NULL +#define pci_ss_list_8086_27d8 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27da[] = { + &pci_ss_info_8086_27da_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27dc[] = { + &pci_ss_info_8086_27dc_8086_308d, + NULL +}; +#define pci_ss_list_8086_27dd NULL +#define pci_ss_list_8086_27de NULL +static const pciSubsystemInfo *pci_ss_list_8086_27df[] = { + &pci_ss_info_8086_27df_8086_544e, + NULL +}; +#define pci_ss_list_8086_27e0 NULL +#define pci_ss_list_8086_27e2 NULL +#define pci_ss_list_8086_2810 NULL +#define pci_ss_list_8086_2811 NULL +#define pci_ss_list_8086_2812 NULL +#define pci_ss_list_8086_2814 NULL +#define pci_ss_list_8086_2815 NULL +#define pci_ss_list_8086_2820 NULL +#define pci_ss_list_8086_2821 NULL +#define pci_ss_list_8086_2822 NULL +#define pci_ss_list_8086_2824 NULL +#define pci_ss_list_8086_2825 NULL +#define pci_ss_list_8086_2828 NULL +#define pci_ss_list_8086_2829 NULL +#define pci_ss_list_8086_282a NULL +#define pci_ss_list_8086_2830 NULL +#define pci_ss_list_8086_2831 NULL +#define pci_ss_list_8086_2832 NULL +#define pci_ss_list_8086_2834 NULL +#define pci_ss_list_8086_2835 NULL +#define pci_ss_list_8086_2836 NULL +#define pci_ss_list_8086_283a NULL +#define pci_ss_list_8086_283e NULL +#define pci_ss_list_8086_283f NULL +#define pci_ss_list_8086_2841 NULL +#define pci_ss_list_8086_2843 NULL +#define pci_ss_list_8086_2844 NULL +#define pci_ss_list_8086_2847 NULL +#define pci_ss_list_8086_2849 NULL +#define pci_ss_list_8086_284b NULL +#define pci_ss_list_8086_284f NULL +#define pci_ss_list_8086_2850 NULL +#define pci_ss_list_8086_2970 NULL +#define pci_ss_list_8086_2971 NULL +#define pci_ss_list_8086_2972 NULL +#define pci_ss_list_8086_2973 NULL +#define pci_ss_list_8086_3092 NULL +#define pci_ss_list_8086_3200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3340[] = { + &pci_ss_info_8086_3340_1025_005a, + &pci_ss_info_8086_3340_103c_088c, + &pci_ss_info_8086_3340_103c_0890, + NULL +}; +#define pci_ss_list_8086_3341 NULL +#define pci_ss_list_8086_3500 NULL +#define pci_ss_list_8086_3501 NULL +#define pci_ss_list_8086_3504 NULL +#define pci_ss_list_8086_3505 NULL +#define pci_ss_list_8086_350c NULL +#define pci_ss_list_8086_350d NULL +#define pci_ss_list_8086_3510 NULL +#define pci_ss_list_8086_3511 NULL +#define pci_ss_list_8086_3514 NULL +#define pci_ss_list_8086_3515 NULL +#define pci_ss_list_8086_3518 NULL +#define pci_ss_list_8086_3519 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_0e11_0030, + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3580[] = { + &pci_ss_info_8086_3580_1028_0139, + &pci_ss_info_8086_3580_1028_0163, + &pci_ss_info_8086_3580_1028_0196, + &pci_ss_info_8086_3580_1734_1055, + &pci_ss_info_8086_3580_4c53_10b0, + &pci_ss_info_8086_3580_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3581[] = { + &pci_ss_info_8086_3581_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3582[] = { + &pci_ss_info_8086_3582_1028_0139, + &pci_ss_info_8086_3582_1028_0163, + &pci_ss_info_8086_3582_4c53_10b0, + &pci_ss_info_8086_3582_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3584[] = { + &pci_ss_info_8086_3584_1028_0139, + &pci_ss_info_8086_3584_1028_0163, + &pci_ss_info_8086_3584_1028_0196, + &pci_ss_info_8086_3584_1734_1055, + &pci_ss_info_8086_3584_4c53_10b0, + &pci_ss_info_8086_3584_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3585[] = { + &pci_ss_info_8086_3585_1028_0139, + &pci_ss_info_8086_3585_1028_0163, + &pci_ss_info_8086_3585_1028_0196, + &pci_ss_info_8086_3585_1734_1055, + &pci_ss_info_8086_3585_4c53_10b0, + &pci_ss_info_8086_3585_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3590[] = { + &pci_ss_info_8086_3590_1028_019a, + &pci_ss_info_8086_3590_1734_103e, + &pci_ss_info_8086_3590_4c53_10d0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3591[] = { + &pci_ss_info_8086_3591_1028_0169, + &pci_ss_info_8086_3591_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3592 NULL +#define pci_ss_list_8086_3593 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3594[] = { + &pci_ss_info_8086_3594_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3595 NULL +#define pci_ss_list_8086_3596 NULL +#define pci_ss_list_8086_3597 NULL +#define pci_ss_list_8086_3598 NULL +#define pci_ss_list_8086_3599 NULL +#define pci_ss_list_8086_359a NULL +#define pci_ss_list_8086_359b NULL +static const pciSubsystemInfo *pci_ss_list_8086_359e[] = { + &pci_ss_info_8086_359e_1028_0169, + NULL +}; +#define pci_ss_list_8086_4220 NULL +#define pci_ss_list_8086_4223 NULL +#define pci_ss_list_8086_4224 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7050 NULL +#define pci_ss_list_8086_7051 NULL +#define pci_ss_list_8086_7100 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7110[] = { + &pci_ss_info_8086_7110_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7111[] = { + &pci_ss_info_8086_7111_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7112[] = { + &pci_ss_info_8086_7112_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7113[] = { + &pci_ss_info_8086_7113_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7120[] = { + &pci_ss_info_8086_7120_4c53_1040, + &pci_ss_info_8086_7120_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7121[] = { + &pci_ss_info_8086_7121_4c53_1040, + &pci_ss_info_8086_7121_4c53_1060, + &pci_ss_info_8086_7121_8086_4341, + NULL +}; +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1179_0001, + &pci_ss_info_8086_7190_15ad_1976, + &pci_ss_info_8086_7190_4c53_1050, + &pci_ss_info_8086_7190_4c53_1051, + NULL +}; +#define pci_ss_list_8086_7191 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + &pci_ss_info_8086_7192_4c53_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7194[] = { + &pci_ss_info_8086_7194_1033_0000, + &pci_ss_info_8086_7194_4c53_10a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_1033_80cc, + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a0[] = { + &pci_ss_info_8086_71a0_4c53_1050, + &pci_ss_info_8086_71a0_4c53_1051, + NULL +}; +#define pci_ss_list_8086_71a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a2[] = { + &pci_ss_info_8086_71a2_4c53_1000, + NULL +}; +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +static const pciSubsystemInfo *pci_ss_list_8086_8500[] = { + &pci_ss_info_8086_8500_1993_0ded, + &pci_ss_info_8086_8500_1993_0dee, + &pci_ss_info_8086_8500_1993_0def, + NULL +}; +#define pci_ss_list_8086_9000 NULL +#define pci_ss_list_8086_9001 NULL +#define pci_ss_list_8086_9004 NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_12d9_000a, + &pci_ss_info_8086_b555_4c53_1050, + &pci_ss_info_8086_b555_4c53_1051, + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8c4a_1980 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_0078 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7710 NULL +#define pci_ss_list_9004_7711 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +#define pci_ss_list_9004_8178 NULL +#endif +#ifdef INIT_VENDOR_SUBSYS_INFO +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0000[] = { + &pci_ss_info_0000_0000, + &pci_ss_info_0000_4091, + NULL +}; +#endif +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#define pci_ss_list_0059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_0003, + &pci_ss_info_0070_0009, + &pci_ss_info_0070_0801, + &pci_ss_info_0070_0807, + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_2801, + &pci_ss_info_0070_3401, + &pci_ss_info_0070_4000, + &pci_ss_info_0070_4001, + &pci_ss_info_0070_4009, + &pci_ss_info_0070_4800, + &pci_ss_info_0070_4801, + &pci_ss_info_0070_4803, + &pci_ss_info_0070_8003, + &pci_ss_info_0070_8801, + &pci_ss_info_0070_9001, + &pci_ss_info_0070_9002, + &pci_ss_info_0070_9200, + &pci_ss_info_0070_9202, + &pci_ss_info_0070_9402, + &pci_ss_info_0070_9802, + &pci_ss_info_0070_c801, + &pci_ss_info_0070_e807, + &pci_ss_info_0070_e817, + &pci_ss_info_0070_ff01, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0071[] = { + &pci_ss_info_0071_0101, + NULL +}; +#endif +#define pci_ss_list_0095 NULL +#define pci_ss_list_00a7 NULL +#define pci_ss_list_0100 NULL +#define pci_ss_list_018a NULL +#define pci_ss_list_021b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0270[] = { + &pci_ss_info_0270_0801, + NULL +}; +#endif +#define pci_ss_list_0291 NULL +#define pci_ss_list_02ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0357[] = { + &pci_ss_info_0357_000a, + NULL +}; +#endif +#define pci_ss_list_0432 NULL +#define pci_ss_list_045e NULL +#define pci_ss_list_04cf NULL +#define pci_ss_list_050d NULL +#define pci_ss_list_05e3 NULL +#define pci_ss_list_066f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0675[] = { + &pci_ss_info_0675_1704, + &pci_ss_info_0675_1707, + &pci_ss_info_0675_1708, + NULL +}; +#endif +#define pci_ss_list_067b NULL +#define pci_ss_list_0721 NULL +#define pci_ss_list_07e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +#define pci_ss_list_0b49 NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0030, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_004e, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0097, + &pci_ss_info_0e11_0098, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00b8, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_00da, + &pci_ss_info_0e11_00db, + &pci_ss_info_0e11_00dc, + &pci_ss_info_0e11_00e3, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_4080, + &pci_ss_info_0e11_4082, + &pci_ss_info_0e11_4083, + &pci_ss_info_0e11_409a, + &pci_ss_info_0e11_409b, + &pci_ss_info_0e11_409c, + &pci_ss_info_0e11_409d, + &pci_ss_info_0e11_6004, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e7, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b121, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b160, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + NULL +}; +#define pci_ss_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_0001, + &pci_ss_info_1000_0002, + &pci_ss_info_1000_0033, + &pci_ss_info_1000_0062, + &pci_ss_info_1000_0066, + &pci_ss_info_1000_0518, + &pci_ss_info_1000_0520, + &pci_ss_info_1000_0522, + &pci_ss_info_1000_0523, + &pci_ss_info_1000_0530, + &pci_ss_info_1000_0531, + &pci_ss_info_1000_0532, + &pci_ss_info_1000_1000, + &pci_ss_info_1000_1010, + &pci_ss_info_1000_1020, + &pci_ss_info_1000_3004, + &pci_ss_info_1000_3008, + &pci_ss_info_1000_4523, + &pci_ss_info_1000_a520, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_00f8, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0322, + &pci_ss_info_1002_0323, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_0b12, + &pci_ss_info_1002_0b13, + &pci_ss_info_1002_0d02, + &pci_ss_info_1002_0d03, + &pci_ss_info_1002_103a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_2f72, + &pci_ss_info_1002_4336, + &pci_ss_info_1002_4722, + &pci_ss_info_1002_4723, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4772, + &pci_ss_info_1002_4773, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_4e71, + &pci_ss_info_1002_515e, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_5954, + &pci_ss_info_1002_5955, + &pci_ss_info_1002_5965, + &pci_ss_info_1002_5c63, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + &pci_ss_info_1002_a101, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1005[] = { + &pci_ss_info_1005_127a, + NULL +}; +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + &pci_ss_info_1013_5959, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_0031, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0092, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0104, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0130, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020c, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021a, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0241, + &pci_ss_info_1014_0242, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0251, + &pci_ss_info_1014_0252, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0264, + &pci_ss_info_1014_0265, + &pci_ss_info_1014_0266, + &pci_ss_info_1014_0267, + &pci_ss_info_1014_0268, + &pci_ss_info_1014_0269, + &pci_ss_info_1014_026a, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0278, + &pci_ss_info_1014_027c, + &pci_ss_info_1014_028d, + &pci_ss_info_1014_028e, + &pci_ss_info_1014_029a, + &pci_ss_info_1014_02be, + &pci_ss_info_1014_02c0, + &pci_ss_info_1014_02c1, + &pci_ss_info_1014_02c2, + &pci_ss_info_1014_02c6, + &pci_ss_info_1014_02c8, + &pci_ss_info_1014_02d3, + &pci_ss_info_1014_02d4, + &pci_ss_info_1014_02ed, + &pci_ss_info_1014_030d, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_050f, + &pci_ss_info_1014_0510, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_0528, + &pci_ss_info_1014_052c, + &pci_ss_info_1014_0535, + &pci_ss_info_1014_053a, + &pci_ss_info_1014_053b, + &pci_ss_info_1014_053c, + &pci_ss_info_1014_053d, + &pci_ss_info_1014_053e, + &pci_ss_info_1014_0540, + &pci_ss_info_1014_0545, + &pci_ss_info_1014_0549, + &pci_ss_info_1014_0556, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_1025, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_0985, + &pci_ss_info_1019_0987, + &pci_ss_info_1019_0a14, + &pci_ss_info_1019_0a81, + &pci_ss_info_1019_0f38, + &pci_ss_info_1019_4c30, + &pci_ss_info_1019_4cb4, + &pci_ss_info_1019_4cb5, + &pci_ss_info_1019_7018, + &pci_ss_info_1019_8001, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0477, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0494, + &pci_ss_info_101e_0503, + &pci_ss_info_101e_0511, + &pci_ss_info_101e_0522, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101f[] = { + &pci_ss_info_101f_1025, + NULL +}; +#endif +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +static const pciSubsystemInfo *pci_ss_list_1022[] = { + &pci_ss_info_1022_2000, + &pci_ss_info_1022_2b80, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1024[] = { + &pci_ss_info_1024_0134, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_004d, + &pci_ss_info_1025_005a, + &pci_ss_info_1025_006a, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_002e, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00aa, + &pci_ss_info_1028_00b1, + &pci_ss_info_1028_00bb, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00ce, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_00fe, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_010e, + &pci_ss_info_1028_011c, + &pci_ss_info_1028_011d, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0123, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_012a, + &pci_ss_info_1028_0134, + &pci_ss_info_1028_0139, + &pci_ss_info_1028_014a, + &pci_ss_info_1028_014e, + &pci_ss_info_1028_0151, + &pci_ss_info_1028_0163, + &pci_ss_info_1028_0165, + &pci_ss_info_1028_0169, + &pci_ss_info_1028_016c, + &pci_ss_info_1028_016d, + &pci_ss_info_1028_016e, + &pci_ss_info_1028_016f, + &pci_ss_info_1028_0170, + &pci_ss_info_1028_0179, + &pci_ss_info_1028_0182, + &pci_ss_info_1028_0183, + &pci_ss_info_1028_0188, + &pci_ss_info_1028_0196, + &pci_ss_info_1028_019a, + &pci_ss_info_1028_019d, + &pci_ss_info_1028_01a2, + &pci_ss_info_1028_01ad, + &pci_ss_info_1028_0407, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_0533, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1079, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_4134, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_865d, + &pci_ss_info_1028_c082, + &pci_ss_info_1028_c134, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0850, + &pci_ss_info_102b_08c7, + &pci_ss_info_102b_0907, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0d43, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1020, + &pci_ss_info_102b_1030, + &pci_ss_info_102b_1047, + &pci_ss_info_102b_1087, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_14e1, + &pci_ss_info_102b_1820, + &pci_ss_info_102b_1830, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1c10, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2021, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2538, + &pci_ss_info_102b_2811, + &pci_ss_info_102b_2c11, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3007, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48d0, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_0000, + &pci_ss_info_1033_0035, + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80a8, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + &pci_ss_info_1033_80cc, + &pci_ss_info_1033_80cd, + &pci_ss_info_1033_80e5, + &pci_ss_info_1033_8110, + &pci_ss_info_1033_8112, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_6330, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_0024, + &pci_ss_info_103c_006a, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_0850, + &pci_ss_info_103c_088c, + &pci_ss_info_103c_0890, + &pci_ss_info_103c_099c, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_10eb, + &pci_ss_info_103c_10ec, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + &pci_ss_info_103c_128a, + &pci_ss_info_103c_128b, + &pci_ss_info_103c_12a4, + &pci_ss_info_103c_12a6, + &pci_ss_info_103c_12a8, + &pci_ss_info_103c_12bc, + &pci_ss_info_103c_12c1, + &pci_ss_info_103c_12c3, + &pci_ss_info_103c_12ca, + &pci_ss_info_103c_12cf, + &pci_ss_info_103c_12d5, + &pci_ss_info_103c_12f4, + &pci_ss_info_103c_12fa, + &pci_ss_info_103c_1300, + &pci_ss_info_103c_1301, + &pci_ss_info_103c_1356, + &pci_ss_info_103c_2a0d, + &pci_ss_info_103c_308b, + &pci_ss_info_103c_3100, + &pci_ss_info_103c_3101, + &pci_ss_info_103c_3102, + &pci_ss_info_103c_3103, + &pci_ss_info_103c_3226, + &pci_ss_info_103c_60e7, + &pci_ss_info_103c_7031, + &pci_ss_info_103c_7032, + &pci_ss_info_103c_7039, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_002a, + &pci_ss_info_1043_0120, + &pci_ss_info_1043_0127, + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0210, + &pci_ss_info_1043_032e, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_100f, + &pci_ss_info_1043_1106, + &pci_ss_info_1043_130f, + &pci_ss_info_1043_1702, + &pci_ss_info_1043_1703, + &pci_ss_info_1043_1707, + &pci_ss_info_1043_173c, + &pci_ss_info_1043_1881, + &pci_ss_info_1043_1967, + &pci_ss_info_1043_1987, + &pci_ss_info_1043_2582, + &pci_ss_info_1043_2601, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_4823, + &pci_ss_info_1043_4840, + &pci_ss_info_1043_4843, + &pci_ss_info_1043_4845, + &pci_ss_info_1043_4862, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8023, + &pci_ss_info_1043_8025, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_802c, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_8035, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_806f, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807e, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_8080, + &pci_ss_info_1043_808a, + &pci_ss_info_1043_808b, + &pci_ss_info_1043_808c, + &pci_ss_info_1043_808d, + &pci_ss_info_1043_8095, + &pci_ss_info_1043_809e, + &pci_ss_info_1043_80a1, + &pci_ss_info_1043_80a3, + &pci_ss_info_1043_80a5, + &pci_ss_info_1043_80a6, + &pci_ss_info_1043_80a7, + &pci_ss_info_1043_80a8, + &pci_ss_info_1043_80ab, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80b0, + &pci_ss_info_1043_80e2, + &pci_ss_info_1043_80eb, + &pci_ss_info_1043_80ed, + &pci_ss_info_1043_80f2, + &pci_ss_info_1043_80f3, + &pci_ss_info_1043_80f4, + &pci_ss_info_1043_80f5, + &pci_ss_info_1043_80f8, + &pci_ss_info_1043_8109, + &pci_ss_info_1043_810f, + &pci_ss_info_1043_811a, + &pci_ss_info_1043_812a, + &pci_ss_info_1043_8134, + &pci_ss_info_1043_8138, + &pci_ss_info_1043_8141, + &pci_ss_info_1043_8142, + &pci_ss_info_1043_8145, + &pci_ss_info_1043_814a, + &pci_ss_info_1043_814e, + &pci_ss_info_1043_815a, + &pci_ss_info_1043_817b, + &pci_ss_info_1043_81a6, + &pci_ss_info_1043_c002, + &pci_ss_info_1043_c003, + &pci_ss_info_1043_c004, + &pci_ss_info_1043_c005, + &pci_ss_info_1043_c006, + &pci_ss_info_1043_c01a, + &pci_ss_info_1043_c01b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c032, + &pci_ss_info_1044_c035, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0935, + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a34, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0a36, + &pci_ss_info_1048_0a42, + &pci_ss_info_1048_0a43, + &pci_ss_info_1048_0a44, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c19, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c1c, + &pci_ss_info_1048_0c20, + &pci_ss_info_1048_0c21, + &pci_ss_info_1048_0c28, + &pci_ss_info_1048_0c29, + &pci_ss_info_1048_0c2a, + &pci_ss_info_1048_0c2b, + &pci_ss_info_1048_0c2e, + &pci_ss_info_1048_0c2f, + &pci_ss_info_1048_0c30, + &pci_ss_info_1048_0c31, + &pci_ss_info_1048_0c32, + &pci_ss_info_1048_0c33, + &pci_ss_info_1048_0c34, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c3b, + &pci_ss_info_1048_0c40, + &pci_ss_info_1048_0c41, + &pci_ss_info_1048_0c42, + &pci_ss_info_1048_0c43, + &pci_ss_info_1048_0c44, + &pci_ss_info_1048_0c45, + &pci_ss_info_1048_0c48, + &pci_ss_info_1048_0c4a, + &pci_ss_info_1048_0c4b, + &pci_ss_info_1048_0c50, + &pci_ss_info_1048_0c52, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_0c60, + &pci_ss_info_1048_0c61, + &pci_ss_info_1048_0c63, + &pci_ss_info_1048_0c64, + &pci_ss_info_1048_0c65, + &pci_ss_info_1048_0c66, + &pci_ss_info_1048_0c70, + &pci_ss_info_1048_1500, + &pci_ss_info_1048_226b, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +#define pci_ss_list_104a NULL +#define pci_ss_list_104b NULL +static const pciSubsystemInfo *pci_ss_list_104c[] = { + &pci_ss_info_104c_9066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_810f, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + &pci_ss_info_1057_7025, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_1275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105b[] = { + &pci_ss_info_105b_0c19, + NULL +}; +#endif +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_0037, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + &pci_ss_info_1069_0030, + &pci_ss_info_1069_0040, + &pci_ss_info_1069_0050, + &pci_ss_info_1069_0052, + &pci_ss_info_1069_0054, + &pci_ss_info_1069_0072, + &pci_ss_info_1069_0200, + &pci_ss_info_1069_0202, + &pci_ss_info_1069_0204, + &pci_ss_info_1069_0206, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b[] = { + &pci_ss_info_106b_004e, + &pci_ss_info_106b_5811, + NULL +}; +#endif +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1071[] = { + &pci_ss_info_1071_7150, + &pci_ss_info_1071_8160, + NULL +}; +#endif +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + &pci_ss_info_1077_0002, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1079[] = { + &pci_ss_info_1079_891f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_3015, + &pci_ss_info_107b_4009, + &pci_ss_info_107b_5350, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + &pci_ss_info_107b_8920, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2134, + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2822, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2842, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + &pci_ss_info_107d_6613, + &pci_ss_info_107d_6620, + &pci_ss_info_107d_663c, + &pci_ss_info_107d_665f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_108e[] = { + &pci_ss_info_108e_10cf, + NULL +}; +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_00b8, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + &pci_ss_info_1095_10cf, + &pci_ss_info_1095_3112, + &pci_ss_info_1095_3114, + &pci_ss_info_1095_3124, + &pci_ss_info_1095_3512, + &pci_ss_info_1095_3680, + &pci_ss_info_1095_6112, + &pci_ss_info_1095_6114, + &pci_ss_info_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + &pci_ss_info_109f_3197, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9[] = { + &pci_ss_info_10a9_8002, + &pci_ss_info_10a9_8010, + &pci_ss_info_10a9_8011, + &pci_ss_info_10a9_8012, + NULL +}; +#endif +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + &pci_ss_info_10b0_0002, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_1067, + &pci_ss_info_10b5_1172, + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2221, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2431, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_2696, + &pci_ss_info_10b5_2717, + &pci_ss_info_10b5_2844, + &pci_ss_info_10b5_2862, + &pci_ss_info_10b5_2905, + &pci_ss_info_10b5_2906, + &pci_ss_info_10b5_2940, + &pci_ss_info_10b5_2977, + &pci_ss_info_10b5_2978, + &pci_ss_info_10b5_2979, + &pci_ss_info_10b5_3025, + &pci_ss_info_10b5_3068, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_0010, + &pci_ss_info_10b7_0020, + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2031, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_2635, + &pci_ss_info_10b8_2802, + &pci_ss_info_10b8_2835, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + &pci_ss_info_10b8_a835, + &pci_ss_info_10b8_b452, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_5451, + &pci_ss_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105e, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_0008, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + &pci_ss_info_10de_006b, + &pci_ss_info_10de_0091, + &pci_ss_info_10de_00a1, + &pci_ss_info_10de_0179, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + &pci_ss_info_10e1_10cf, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + &pci_ss_info_10f1_2466, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + &pci_ss_info_10f7_8338, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fc[] = { + &pci_ss_info_10fc_d003, + &pci_ss_info_10fc_d035, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fd[] = { + &pci_ss_info_10fd_a430, + NULL +}; +#endif +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0007, + &pci_ss_info_1102_0008, + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_0058, + &pci_ss_info_1102_1001, + &pci_ss_info_1102_1002, + &pci_ss_info_1102_1006, + &pci_ss_info_1102_1007, + &pci_ss_info_1102_100a, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_2002, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + &pci_ss_info_1102_8064, + &pci_ss_info_1102_8065, + &pci_ss_info_1102_8067, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0003, + &pci_ss_info_1103_0004, + &pci_ss_info_1103_0005, + &pci_ss_info_1103_0006, + &pci_ss_info_1103_0007, + &pci_ss_info_1103_0008, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105[] = { + &pci_ss_info_1105_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_3059, + &pci_ss_info_1106_3227, + &pci_ss_info_1106_4161, + &pci_ss_info_1106_4511, + NULL +}; +#endif +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0000, + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0021, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_0051, + &pci_ss_info_110a_008b, + &pci_ss_info_110a_5938, + &pci_ss_info_110a_8005, + &pci_ss_info_110a_ffff, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_2242, + &pci_ss_info_1113_4203, + &pci_ss_info_1113_9211, + &pci_ss_info_1113_d301, + &pci_ss_info_1113_ec01, + &pci_ss_info_1113_ee03, + &pci_ss_info_1113_ee08, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131[] = { + &pci_ss_info_1131_2001, + &pci_ss_info_1131_2004, + &pci_ss_info_1131_2005, + &pci_ss_info_1131_2018, + &pci_ss_info_1131_4e85, + &pci_ss_info_1131_4ee9, + &pci_ss_info_1131_4f56, + &pci_ss_info_1131_4f60, + &pci_ss_info_1131_4f61, + &pci_ss_info_1131_5f61, + &pci_ss_info_1131_6752, + &pci_ss_info_1131_7133, + NULL +}; +#endif +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_1300, + &pci_ss_info_1133_1800, + &pci_ss_info_1133_1c01, + &pci_ss_info_1133_1c02, + &pci_ss_info_1133_1c03, + &pci_ss_info_1133_1c04, + &pci_ss_info_1133_1c05, + &pci_ss_info_1133_1c06, + &pci_ss_info_1133_1c07, + &pci_ss_info_1133_1c08, + &pci_ss_info_1133_1c09, + &pci_ss_info_1133_1c0a, + &pci_ss_info_1133_1c0b, + &pci_ss_info_1133_1c0c, + &pci_ss_info_1133_2400, + &pci_ss_info_1133_2800, + &pci_ss_info_1133_e013, + &pci_ss_info_1133_e015, + &pci_ss_info_1133_e017, + &pci_ss_info_1133_e018, + &pci_ss_info_1133_e019, + &pci_ss_info_1133_e01b, + &pci_ss_info_1133_e024, + &pci_ss_info_1133_e028, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_0121, + &pci_ss_info_1148_0221, + &pci_ss_info_1148_0321, + &pci_ss_info_1148_0421, + &pci_ss_info_1148_0621, + &pci_ss_info_1148_0721, + &pci_ss_info_1148_0821, + &pci_ss_info_1148_0921, + &pci_ss_info_1148_1121, + &pci_ss_info_1148_1221, + &pci_ss_info_1148_2100, + &pci_ss_info_1148_21d0, + &pci_ss_info_1148_2200, + &pci_ss_info_1148_3221, + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_8100, + &pci_ss_info_1148_8200, + &pci_ss_info_1148_9100, + &pci_ss_info_1148_9200, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#define pci_ss_list_1154 NULL +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + &pci_ss_info_1179_ff01, + &pci_ss_info_1179_ff10, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c[] = { + &pci_ss_info_117c_8013, + &pci_ss_info_117c_8014, + NULL +}; +#endif +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1303, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_1403, + &pci_ss_info_1186_3202, + &pci_ss_info_1186_3203, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_3700, + &pci_ss_info_1186_3a12, + &pci_ss_info_1186_3a13, + &pci_ss_info_1186_3a14, + &pci_ss_info_1186_3a15, + &pci_ss_info_1186_3a16, + &pci_ss_info_1186_3a17, + &pci_ss_info_1186_3a18, + &pci_ss_info_1186_3a19, + &pci_ss_info_1186_3a22, + &pci_ss_info_1186_3a23, + &pci_ss_info_1186_3a24, + &pci_ss_info_1186_3a63, + &pci_ss_info_1186_3a94, + &pci_ss_info_1186_3b00, + &pci_ss_info_1186_3b01, + &pci_ss_info_1186_3b04, + &pci_ss_info_1186_3b05, + &pci_ss_info_1186_4c00, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#define pci_ss_list_1195 NULL +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab[] = { + &pci_ss_info_11ab_0121, + &pci_ss_info_11ab_0321, + &pci_ss_info_11ab_1021, + &pci_ss_info_11ab_3521, + &pci_ss_info_11ab_3621, + &pci_ss_info_11ab_5021, + &pci_ss_info_11ab_5221, + &pci_ss_info_11ab_5321, + &pci_ss_info_11ab_9521, + NULL +}; +#endif +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_000f, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + &pci_ss_info_11bd_002b, + &pci_ss_info_11bd_002d, + &pci_ss_info_11bd_002e, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + &pci_ss_info_11c1_ab12, + &pci_ss_info_11c1_ab13, + &pci_ss_info_11c1_ab15, + &pci_ss_info_11c1_ab16, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0057, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_1400, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + &pci_ss_info_1244_0f00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_1070, + &pci_ss_info_124b_1170, + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2702, + &pci_ss_info_1259_2703, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2971, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2973, + &pci_ss_info_1259_2974, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2976, + &pci_ss_info_1259_2977, + &pci_ss_info_1259_c104, + &pci_ss_info_1259_c107, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260[] = { + &pci_ss_info_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + &pci_ss_info_1274_8001, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127d[] = { + &pci_ss_info_127d_0000, + NULL +}; +#endif +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283[] = { + &pci_ss_info_1283_0001, + NULL +}; +#endif +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1297[] = { + &pci_ss_info_1297_c160, + &pci_ss_info_1297_c240, + &pci_ss_info_1297_c241, + &pci_ss_info_1297_c242, + &pci_ss_info_1297_c243, + &pci_ss_info_1297_c244, + &pci_ss_info_1297_f641, + NULL +}; +#endif +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ab[] = { + &pci_ss_info_12ab_0000, + &pci_ss_info_12ab_0800, + &pci_ss_info_12ab_5961, + &pci_ss_info_12ab_fff3, + &pci_ss_info_12ab_ffff, + NULL +}; +#endif +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#define pci_ss_list_12c4 NULL +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c7[] = { + &pci_ss_info_12c7_4001, + NULL +}; +#endif +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_0002, + &pci_ss_info_12d9_000a, + &pci_ss_info_12d9_000c, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12df[] = { + &pci_ss_info_12df_4422, + NULL +}; +#endif +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12f8[] = { + &pci_ss_info_12f8_8a02, + NULL +}; +#endif +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317[] = { + &pci_ss_info_1317_8201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319[] = { + &pci_ss_info_1319_1319, + NULL +}; +#endif +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + &pci_ss_info_131f_2050, + &pci_ss_info_131f_2051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#define pci_ss_list_1351 NULL +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_001e, + &pci_ss_info_1371_001f, + &pci_ss_info_1371_0020, + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_4105, + &pci_ss_info_1385_4800, + &pci_ss_info_1385_4d00, + &pci_ss_info_1385_4e00, + &pci_ss_info_1385_f004, + &pci_ss_info_1385_f311, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + &pci_ss_info_1397_3136, + &pci_ss_info_1397_3137, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13b9[] = { + &pci_ss_info_13b9_1421, + NULL +}; +#endif +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13bd[] = { + &pci_ss_info_13bd_100c, + &pci_ss_info_13bd_100d, + &pci_ss_info_13bd_100e, + &pci_ss_info_13bd_1019, + &pci_ss_info_13bd_f6f1, + NULL +}; +#endif +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1[] = { + &pci_ss_info_13c1_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c2[] = { + &pci_ss_info_13c2_0000, + &pci_ss_info_13c2_0001, + &pci_ss_info_13c2_0002, + &pci_ss_info_13c2_0003, + &pci_ss_info_13c2_0004, + &pci_ss_info_13c2_0006, + &pci_ss_info_13c2_0008, + &pci_ss_info_13c2_000a, + &pci_ss_info_13c2_1003, + &pci_ss_info_13c2_1004, + &pci_ss_info_13c2_1005, + &pci_ss_info_13c2_100c, + &pci_ss_info_13c2_100f, + &pci_ss_info_13c2_1011, + &pci_ss_info_13c2_1013, + &pci_ss_info_13c2_1016, + &pci_ss_info_13c2_1102, + NULL +}; +#endif +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + &pci_ss_info_13d1_aba0, + &pci_ss_info_13d1_ac11, + &pci_ss_info_13d1_ac12, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + &pci_ss_info_13e9_1000, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412[] = { + &pci_ss_info_1412_1712, + &pci_ss_info_1412_1724, + &pci_ss_info_1412_3630, + &pci_ss_info_1412_3631, + &pci_ss_info_1412_d630, + &pci_ss_info_1412_d631, + &pci_ss_info_1412_d632, + &pci_ss_info_1412_d633, + &pci_ss_info_1412_d634, + &pci_ss_info_1412_d635, + &pci_ss_info_1412_d637, + &pci_ss_info_1412_d638, + &pci_ss_info_1412_d63b, + &pci_ss_info_1412_d63c, + NULL +}; +#endif +#define pci_ss_list_1413 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1414[] = { + &pci_ss_info_1414_0003, + &pci_ss_info_1414_0004, + NULL +}; +#endif +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_1712, + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1421[] = { + &pci_ss_info_1421_0334, + &pci_ss_info_1421_1370, + NULL +}; +#endif +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1435[] = { + &pci_ss_info_1435_7330, + &pci_ss_info_1435_7350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_1702, + &pci_ss_info_144f_1703, + &pci_ss_info_144f_1707, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + &pci_ss_info_144f_7050, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_0c11, + &pci_ss_info_1458_1000, + &pci_ss_info_1458_1019, + &pci_ss_info_1458_24c2, + &pci_ss_info_1458_24d1, + &pci_ss_info_1458_24d2, + &pci_ss_info_1458_2558, + &pci_ss_info_1458_2560, + &pci_ss_info_1458_2570, + &pci_ss_info_1458_2578, + &pci_ss_info_1458_2580, + &pci_ss_info_1458_2582, + &pci_ss_info_1458_2659, + &pci_ss_info_1458_265a, + &pci_ss_info_1458_266a, + &pci_ss_info_1458_266f, + &pci_ss_info_1458_3124, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_4018, + &pci_ss_info_1458_4019, + &pci_ss_info_1458_4024, + &pci_ss_info_1458_4025, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_5006, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + &pci_ss_info_1458_b001, + &pci_ss_info_1458_b003, + &pci_ss_info_1458_d000, + &pci_ss_info_1458_e000, + &pci_ss_info_1458_e381, + &pci_ss_info_1458_e911, + &pci_ss_info_1458_e931, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0002, + &pci_ss_info_1461_0003, + &pci_ss_info_1461_0004, + &pci_ss_info_1461_000a, + &pci_ss_info_1461_000b, + &pci_ss_info_1461_050c, + &pci_ss_info_1461_0761, + &pci_ss_info_1461_1044, + &pci_ss_info_1461_10ff, + &pci_ss_info_1461_2108, + &pci_ss_info_1461_2115, + &pci_ss_info_1461_8011, + &pci_ss_info_1461_9715, + &pci_ss_info_1461_a3ce, + &pci_ss_info_1461_a3cf, + &pci_ss_info_1461_a70a, + &pci_ss_info_1461_a70b, + &pci_ss_info_1461_d6ee, + &pci_ss_info_1461_f31f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_0080, + &pci_ss_info_1462_0402, + &pci_ss_info_1462_0403, + &pci_ss_info_1462_052c, + &pci_ss_info_1462_058c, + &pci_ss_info_1462_1009, + &pci_ss_info_1462_3091, + &pci_ss_info_1462_309e, + &pci_ss_info_1462_3300, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3800, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5470, + &pci_ss_info_1462_5506, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6231, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6828, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6835, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_7020, + &pci_ss_info_1462_7028, + &pci_ss_info_1462_702c, + &pci_ss_info_1462_702d, + &pci_ss_info_1462_702e, + &pci_ss_info_1462_7100, + &pci_ss_info_1462_7280, + &pci_ss_info_1462_728c, + &pci_ss_info_1462_7580, + &pci_ss_info_1462_758c, + &pci_ss_info_1462_788c, + &pci_ss_info_1462_8606, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + &pci_ss_info_1462_8852, + &pci_ss_info_1462_8880, + &pci_ss_info_1462_8900, + &pci_ss_info_1462_9171, + &pci_ss_info_1462_932c, + &pci_ss_info_1462_9350, + &pci_ss_info_1462_9360, + &pci_ss_info_1462_971d, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0202, + &pci_ss_info_1468_0311, + &pci_ss_info_1468_0312, + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_0450, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1471[] = { + &pci_ss_info_1471_b7e9, + NULL +}; +#endif +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_1406, + &pci_ss_info_147b_1407, + &pci_ss_info_147b_1408, + &pci_ss_info_147b_1c09, + &pci_ss_info_147b_1c0b, + &pci_ss_info_147b_6191, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_8f0d, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_0214, + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + &pci_ss_info_148c_2064, + &pci_ss_info_148c_2066, + &pci_ss_info_148c_2067, + &pci_ss_info_148c_2073, + &pci_ss_info_148c_2116, + &pci_ss_info_148c_2117, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1498[] = { + &pci_ss_info_1498_0362, + NULL +}; +#endif +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14b7[] = { + &pci_ss_info_14b7_0a60, + NULL +}; +#endif +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + &pci_ss_info_14c0_0012, + &pci_ss_info_14c0_1212, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c2[] = { + &pci_ss_info_14c2_0105, + &pci_ss_info_14c2_0205, + NULL +}; +#endif +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c7[] = { + &pci_ss_info_14c7_0107, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cb[] = { + &pci_ss_info_14cb_0100, + &pci_ss_info_14cb_0200, + NULL +}; +#endif +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2012, + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_0449, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_4318, + &pci_ss_info_14e4_4320, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ef[] = { + &pci_ss_info_14ef_0220, + NULL +}; +#endif +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0187, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0342, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_2045, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fb[] = { + &pci_ss_info_14fb_0101, + &pci_ss_info_14fb_0102, + &pci_ss_info_14fb_0202, + &pci_ss_info_14fb_0611, + &pci_ss_info_14fb_0612, + &pci_ss_info_14fb_0613, + &pci_ss_info_14fb_0614, + &pci_ss_info_14fb_0621, + &pci_ss_info_14fb_0622, + &pci_ss_info_14fb_0810, + NULL +}; +#endif +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_0e70, + &pci_ss_info_14ff_1100, + &pci_ss_info_14ff_c401, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_1930, + &pci_ss_info_1509_1968, + &pci_ss_info_1509_2990, + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#define pci_ss_list_1517 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1518[] = { + &pci_ss_info_1518_0200, + NULL +}; +#endif +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + &pci_ss_info_1522_0c00, + &pci_ss_info_1522_0d00, + &pci_ss_info_1522_1d00, + &pci_ss_info_1522_2000, + &pci_ss_info_1522_2100, + &pci_ss_info_1522_2200, + &pci_ss_info_1522_2300, + &pci_ss_info_1522_2400, + &pci_ss_info_1522_2500, + &pci_ss_info_1522_2600, + &pci_ss_info_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_153b[] = { + &pci_ss_info_153b_1115, + &pci_ss_info_153b_111b, + &pci_ss_info_153b_1125, + &pci_ss_info_153b_112b, + &pci_ss_info_153b_112c, + &pci_ss_info_153b_1130, + &pci_ss_info_153b_1136, + &pci_ss_info_153b_1138, + &pci_ss_info_153b_1142, + &pci_ss_info_153b_1143, + &pci_ss_info_153b_1145, + &pci_ss_info_153b_1147, + &pci_ss_info_153b_1151, + &pci_ss_info_153b_1152, + &pci_ss_info_153b_1153, + &pci_ss_info_153b_1158, + &pci_ss_info_153b_1160, + &pci_ss_info_153b_1162, + &pci_ss_info_153b_1166, + NULL +}; +#endif +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1540[] = { + &pci_ss_info_1540_2580, + &pci_ss_info_1540_9524, + NULL +}; +#endif +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + &pci_ss_info_1554_4811, + &pci_ss_info_1554_4813, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_04a0, + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_002d, + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_156d[] = { + &pci_ss_info_156d_b400, + &pci_ss_info_156d_b550, + &pci_ss_info_156d_b560, + &pci_ss_info_156d_b700, + &pci_ss_info_156d_b795, + &pci_ss_info_156d_b797, + NULL +}; +#endif +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +static const pciSubsystemInfo *pci_ss_list_15ad[] = { + &pci_ss_info_15ad_1976, + NULL +}; +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15bd[] = { + &pci_ss_info_15bd_1001, + &pci_ss_info_15bd_1003, + NULL +}; +#endif +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d4[] = { + &pci_ss_info_15d4_0047, + NULL +}; +#endif +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_4580, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#define pci_ss_list_1601 NULL +#define pci_ss_list_1602 NULL +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#define pci_ss_list_1612 NULL +#define pci_ss_list_1619 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_161f[] = { + &pci_ss_info_161f_2029, + &pci_ss_info_161f_203c, + &pci_ss_info_161f_203d, + &pci_ss_info_161f_3017, + NULL +}; +#endif +#define pci_ss_list_1626 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1637 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_165f NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#define pci_ss_list_166d NULL +#define pci_ss_list_1677 NULL +#define pci_ss_list_167b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0002, + &pci_ss_info_1681_0003, + &pci_ss_info_1681_0010, + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a000, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1682[] = { + &pci_ss_info_1682_2109, + &pci_ss_info_1682_211c, + &pci_ss_info_1682_2120, + NULL +}; +#endif +#define pci_ss_list_1688 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c[] = { + &pci_ss_info_168c_0013, + &pci_ss_info_168c_1025, + &pci_ss_info_168c_1027, + &pci_ss_info_168c_1052, + &pci_ss_info_168c_2026, + &pci_ss_info_168c_2041, + &pci_ss_info_168c_2042, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1695[] = { + &pci_ss_info_1695_3005, + &pci_ss_info_1695_300c, + &pci_ss_info_1695_9025, + &pci_ss_info_1695_9029, + NULL +}; +#endif +#define pci_ss_list_169c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16a5[] = { + &pci_ss_info_16a5_1601, + &pci_ss_info_16a5_1605, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ab[] = { + &pci_ss_info_16ab_7302, + &pci_ss_info_16ab_8501, + NULL +}; +#endif +#define pci_ss_list_16ae NULL +#define pci_ss_list_16af NULL +#define pci_ss_list_16b4 NULL +#define pci_ss_list_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_0003, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16c8 NULL +#define pci_ss_list_16c9 NULL +#define pci_ss_list_16ca NULL +#define pci_ss_list_16cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ce[] = { + &pci_ss_info_16ce_1040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16df[] = { + &pci_ss_info_16df_0011, + &pci_ss_info_16df_0012, + &pci_ss_info_16df_0013, + &pci_ss_info_16df_0014, + &pci_ss_info_16df_0015, + &pci_ss_info_16df_0016, + NULL +}; +#endif +#define pci_ss_list_16e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ec[] = { + &pci_ss_info_16ec_0119, + NULL +}; +#endif +#define pci_ss_list_16ed NULL +#define pci_ss_list_16f3 NULL +#define pci_ss_list_16f4 NULL +#define pci_ss_list_16f6 NULL +#define pci_ss_list_1702 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#define pci_ss_list_1725 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1734[] = { + &pci_ss_info_1734_007a, + &pci_ss_info_1734_100b, + &pci_ss_info_1734_1012, + &pci_ss_info_1734_101c, + &pci_ss_info_1734_1025, + &pci_ss_info_1734_103e, + &pci_ss_info_1734_1052, + &pci_ss_info_1734_1055, + &pci_ss_info_1734_105a, + &pci_ss_info_1734_105b, + &pci_ss_info_1734_105c, + &pci_ss_info_1734_105d, + &pci_ss_info_1734_1061, + &pci_ss_info_1734_1065, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_0015, + &pci_ss_info_1737_0016, + &pci_ss_info_1737_0024, + &pci_ss_info_1737_0032, + &pci_ss_info_1737_3874, + &pci_ss_info_1737_4320, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#define pci_ss_list_1749 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7146, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + &pci_ss_info_174b_7c12, + &pci_ss_info_174b_7c13, + &pci_ss_info_174b_7c19, + &pci_ss_info_174b_7c28, + &pci_ss_info_174b_7c29, + NULL +}; +#endif +#define pci_ss_list_174d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_175c[] = { + &pci_ss_info_175c_4200, + &pci_ss_info_175c_4300, + &pci_ss_info_175c_4400, + &pci_ss_info_175c_5000, + &pci_ss_info_175c_5100, + &pci_ss_info_175c_6100, + &pci_ss_info_175c_6200, + &pci_ss_info_175c_6400, + &pci_ss_info_175c_8700, + &pci_ss_info_175c_8800, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#define pci_ss_list_1775 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + &pci_ss_info_1787_4002, + &pci_ss_info_1787_4003, + &pci_ss_info_1787_5964, + &pci_ss_info_1787_5965, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#define pci_ss_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + &pci_ss_info_1799_5000, + &pci_ss_info_1799_7001, + &pci_ss_info_1799_700a, + &pci_ss_info_1799_7010, + &pci_ss_info_1799_701a, + NULL +}; +#endif +#define pci_ss_list_179c NULL +#define pci_ss_list_17a0 NULL +#define pci_ss_list_17aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + &pci_ss_info_17af_200c, + &pci_ss_info_17af_200d, + &pci_ss_info_17af_2012, + &pci_ss_info_17af_2013, + NULL +}; +#endif +#define pci_ss_list_17b3 NULL +#define pci_ss_list_17b4 NULL +#define pci_ss_list_17c0 NULL +#define pci_ss_list_17c2 NULL +#define pci_ss_list_17cb NULL +#define pci_ss_list_17cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17cf[] = { + &pci_ss_info_17cf_0014, + &pci_ss_info_17cf_0020, + &pci_ss_info_17cf_0037, + NULL +}; +#endif +#define pci_ss_list_17d3 NULL +#define pci_ss_list_17d5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17de[] = { + &pci_ss_info_17de_08a1, + &pci_ss_info_17de_08a6, + &pci_ss_info_17de_08b2, + &pci_ss_info_17de_a8a6, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ee[] = { + &pci_ss_info_17ee_2002, + &pci_ss_info_17ee_2003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17f2[] = { + &pci_ss_info_17f2_1c03, + &pci_ss_info_17f2_2c08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe[] = { + &pci_ss_info_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ff[] = { + &pci_ss_info_17ff_0585, + NULL +}; +#endif +#define pci_ss_list_1813 NULL +#define pci_ss_list_1814 NULL +#define pci_ss_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1822[] = { + &pci_ss_info_1822_0001, + &pci_ss_info_1822_0025, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_182d[] = { + &pci_ss_info_182d_201d, + NULL +}; +#endif +#define pci_ss_list_1830 NULL +#define pci_ss_list_183b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1849[] = { + &pci_ss_info_1849_0571, + &pci_ss_info_1849_3038, + &pci_ss_info_1849_3065, + &pci_ss_info_1849_3099, + &pci_ss_info_1849_3104, + &pci_ss_info_1849_3149, + &pci_ss_info_1849_3177, + &pci_ss_info_1849_3189, + &pci_ss_info_1849_3227, + &pci_ss_info_1849_8052, + &pci_ss_info_1849_8053, + &pci_ss_info_1849_9761, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1854[] = { + &pci_ss_info_1854_000b, + &pci_ss_info_1854_000c, + &pci_ss_info_1854_000d, + &pci_ss_info_1854_000e, + &pci_ss_info_1854_000f, + &pci_ss_info_1854_0010, + &pci_ss_info_1854_0011, + &pci_ss_info_1854_0012, + &pci_ss_info_1854_0013, + &pci_ss_info_1854_0014, + &pci_ss_info_1854_0015, + &pci_ss_info_1854_0016, + &pci_ss_info_1854_0017, + &pci_ss_info_1854_0018, + &pci_ss_info_1854_0019, + &pci_ss_info_1854_001a, + &pci_ss_info_1854_001b, + &pci_ss_info_1854_001c, + &pci_ss_info_1854_001d, + &pci_ss_info_1854_001e, + &pci_ss_info_1854_001f, + &pci_ss_info_1854_0020, + &pci_ss_info_1854_0021, + &pci_ss_info_1854_0022, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185b[] = { + &pci_ss_info_185b_c100, + &pci_ss_info_185b_c200, + &pci_ss_info_185b_c900, + &pci_ss_info_185b_c901, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185f[] = { + &pci_ss_info_185f_1220, + &pci_ss_info_185f_22a0, + NULL +}; +#endif +#define pci_ss_list_1864 NULL +#define pci_ss_list_1867 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_187e[] = { + &pci_ss_info_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#define pci_ss_list_1890 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1894[] = { + &pci_ss_info_1894_a006, + &pci_ss_info_1894_fe01, + NULL +}; +#endif +#define pci_ss_list_1896 NULL +#define pci_ss_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ac[] = { + &pci_ss_info_18ac_d500, + &pci_ss_info_18ac_d810, + &pci_ss_info_18ac_d820, + &pci_ss_info_18ac_db00, + &pci_ss_info_18ac_db10, + &pci_ss_info_18ac_db11, + &pci_ss_info_18ac_db50, + NULL +}; +#endif +#define pci_ss_list_18b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18bc[] = { + &pci_ss_info_18bc_0050, + &pci_ss_info_18bc_0051, + &pci_ss_info_18bc_0053, + &pci_ss_info_18bc_0100, + &pci_ss_info_18bc_0101, + &pci_ss_info_18bc_0170, + &pci_ss_info_18bc_0171, + &pci_ss_info_18bc_0172, + &pci_ss_info_18bc_0173, + NULL +}; +#endif +#define pci_ss_list_18c8 NULL +#define pci_ss_list_18c9 NULL +#define pci_ss_list_18ca NULL +#define pci_ss_list_18d2 NULL +#define pci_ss_list_18dd NULL +#define pci_ss_list_18e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec[] = { + &pci_ss_info_18ec_d001, + &pci_ss_info_18ec_d002, + &pci_ss_info_18ec_d003, + &pci_ss_info_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18fb[] = { + &pci_ss_info_18fb_7872, + NULL +}; +#endif +#define pci_ss_list_1923 NULL +#define pci_ss_list_1924 NULL +#define pci_ss_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1931[] = { + &pci_ss_info_1931_000a, + &pci_ss_info_1931_000b, + NULL +}; +#endif +#define pci_ss_list_1942 NULL +#define pci_ss_list_1957 NULL +#define pci_ss_list_1958 NULL +#define pci_ss_list_1966 NULL +#define pci_ss_list_196a NULL +#define pci_ss_list_197b NULL +#define pci_ss_list_1989 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1993[] = { + &pci_ss_info_1993_0ded, + &pci_ss_info_1993_0dee, + &pci_ss_info_1993_0def, + NULL +}; +#endif +#define pci_ss_list_19a8 NULL +#define pci_ss_list_19ac NULL +#define pci_ss_list_19ae NULL +#define pci_ss_list_19d4 NULL +#define pci_ss_list_19e2 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3906, + &pci_ss_info_1de1_3907, + &pci_ss_info_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_1fc0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1fc1[] = { + &pci_ss_info_1fc1_0026, + &pci_ss_info_1fc1_0027, + NULL +}; +#endif +#define pci_ss_list_1fce NULL +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_2801, + &pci_ss_info_270f_2803, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + &pci_ss_info_270f_f641, + &pci_ss_info_270f_f645, + &pci_ss_info_270f_fc00, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_3842 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_144f, + &pci_ss_info_4005_4000, + &pci_ss_info_4005_4710, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_4144 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4321 NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_494f NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53[] = { + &pci_ss_info_4c53_1000, + &pci_ss_info_4c53_1010, + &pci_ss_info_4c53_1020, + &pci_ss_info_4c53_1030, + &pci_ss_info_4c53_1040, + &pci_ss_info_4c53_1050, + &pci_ss_info_4c53_1051, + &pci_ss_info_4c53_1060, + &pci_ss_info_4c53_1070, + &pci_ss_info_4c53_1080, + &pci_ss_info_4c53_1090, + &pci_ss_info_4c53_10a0, + &pci_ss_info_4c53_10b0, + &pci_ss_info_4c53_10d0, + &pci_ss_info_4c53_10e0, + &pci_ss_info_4c53_1300, + &pci_ss_info_4c53_1310, + &pci_ss_info_4c53_3000, + &pci_ss_info_4c53_3001, + &pci_ss_info_4c53_3002, + &pci_ss_info_4c53_3010, + &pci_ss_info_4c53_3011, + &pci_ss_info_4c53_4000, + NULL +}; +#endif +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5168[] = { + &pci_ss_info_5168_0138, + &pci_ss_info_5168_0306, + &pci_ss_info_5168_0319, + NULL +}; +#endif +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_2036, + &pci_ss_info_5654_3132, + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_5851 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_7063[] = { + &pci_ss_info_7063_3000, + NULL +}; +#endif +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_807d[] = { + &pci_ss_info_807d_0035, + &pci_ss_info_807d_1043, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_0075, + &pci_ss_info_8086_0076, + &pci_ss_info_8086_0077, + &pci_ss_info_8086_0079, + &pci_ss_info_8086_007b, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_01af, + &pci_ss_info_8086_01c1, + &pci_ss_info_8086_01f7, + &pci_ss_info_8086_0520, + &pci_ss_info_8086_0523, + &pci_ss_info_8086_0530, + &pci_ss_info_8086_0532, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1016, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1018, + &pci_ss_info_8086_1019, + &pci_ss_info_8086_101a, + &pci_ss_info_8086_101e, + &pci_ss_info_8086_1026, + &pci_ss_info_8086_1027, + &pci_ss_info_8086_1028, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_1075, + &pci_ss_info_8086_1076, + &pci_ss_info_8086_1077, + &pci_ss_info_8086_1078, + &pci_ss_info_8086_1079, + &pci_ss_info_8086_107a, + &pci_ss_info_8086_107b, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_110d, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1113, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_1176, + &pci_ss_info_8086_1179, + &pci_ss_info_8086_117a, + &pci_ss_info_8086_1276, + &pci_ss_info_8086_127a, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1376, + &pci_ss_info_8086_1476, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_24db, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_2527, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_301f, + &pci_ss_info_8086_3020, + &pci_ss_info_8086_302f, + &pci_ss_info_8086_3063, + &pci_ss_info_8086_308d, + &pci_ss_info_8086_3108, + &pci_ss_info_8086_3411, + &pci_ss_info_8086_3424, + &pci_ss_info_8086_3427, + &pci_ss_info_8086_3431, + &pci_ss_info_8086_3439, + &pci_ss_info_8086_3499, + &pci_ss_info_8086_4147, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4246, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4532, + &pci_ss_info_8086_4541, + &pci_ss_info_8086_4557, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_524c, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_544e, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + &pci_ss_info_8086_a000, + &pci_ss_info_8086_a01f, + &pci_ss_info_8086_a11f, + &pci_ss_info_8086_e000, + &pci_ss_info_8086_e001, + NULL +}; +#define pci_ss_list_8401 NULL +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8912 NULL +#define pci_ss_list_8c4a NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0095_0680 = { + 0x0680, pci_device_0095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0095_0680, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_018a_0106 = { + 0x0106, pci_device_018a_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_018a_0106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_021b_8139 = { + 0x8139, pci_device_021b_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_021b_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0291_8212 = { + 0x8212, pci_device_0291_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0291_8212, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_02ac_1012 = { + 0x1012, pci_device_02ac_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_02ac_1012, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0357_000a = { + 0x000a, pci_device_0357_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0357_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0432_0001 = { + 0x0001, pci_device_0432_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0432_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_045e_006e = { + 0x006e, pci_device_045e_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_045e_00c2 = { + 0x00c2, pci_device_045e_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_00c2, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_04cf_8818 = { + 0x8818, pci_device_04cf_8818, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_04cf_8818, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_050d_7050 = { + 0x7050, pci_device_050d_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_050d_7050, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05e3_0701 = { + 0x0701, pci_device_05e3_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05e3_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1703 = { + 0x1703, pci_device_0675_1703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1703, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1704 = { + 0x1704, pci_device_0675_1704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_067b_3507 = { + 0x3507, pci_device_067b_3507, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_3507, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b49_064f = { + 0x064f, pci_device_0b49_064f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b49_064f, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0046 = { + 0x0046, pci_device_0e11_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_005a = { + 0x005a, pci_device_0e11_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007c = { + 0x007c, pci_device_0e11_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007d = { + 0x007d, pci_device_0e11_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0085 = { + 0x0085, pci_device_0e11_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00b1 = { + 0x00b1, pci_device_0e11_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00bb = { + 0x00bb, pci_device_0e11_00bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00ca = { + 0x00ca, pci_device_0e11_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cb = { + 0x00cb, pci_device_0e11_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cf = { + 0x00cf, pci_device_0e11_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d0 = { + 0x00d0, pci_device_0e11_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d1 = { + 0x00d1, pci_device_0e11_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00e3 = { + 0x00e3, pci_device_0e11_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4030 = { + 0x4030, pci_device_0e11_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4031 = { + 0x4031, pci_device_0e11_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4032 = { + 0x4032, pci_device_0e11_4032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4033 = { + 0x4033, pci_device_0e11_4033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4034 = { + 0x4034, pci_device_0e11_4034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4040 = { + 0x4040, pci_device_0e11_4040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4048 = { + 0x4048, pci_device_0e11_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4050 = { + 0x4050, pci_device_0e11_4050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4051 = { + 0x4051, pci_device_0e11_4051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4058 = { + 0x4058, pci_device_0e11_4058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4070 = { + 0x4070, pci_device_0e11_4070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4080 = { + 0x4080, pci_device_0e11_4080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4082 = { + 0x4082, pci_device_0e11_4082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4083 = { + 0x4083, pci_device_0e11_4083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4091 = { + 0x4091, pci_device_0e11_4091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409a = { + 0x409a, pci_device_0e11_409a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409b = { + 0x409b, pci_device_0e11_409b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409c = { + 0x409c, pci_device_0e11_409c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409d = { + 0x409d, pci_device_0e11_409d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b200 = { + 0xb200, pci_device_0e11_b200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b203 = { + 0xb203, pci_device_0e11_b203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b204 = { + 0xb204, pci_device_0e11_b204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0031 = { + 0x0031, pci_device_1000_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0032 = { + 0x0032, pci_device_1000_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0033 = { + 0x0033, pci_device_1000_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0041 = { + 0x0041, pci_device_1000_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0050 = { + 0x0050, pci_device_1000_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0054 = { + 0x0054, pci_device_1000_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0056 = { + 0x0056, pci_device_1000_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0058 = { + 0x0058, pci_device_1000_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005a = { + 0x005a, pci_device_1000_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005c = { + 0x005c, pci_device_1000_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005e = { + 0x005e, pci_device_1000_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0060 = { + 0x0060, pci_device_1000_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0062 = { + 0x0062, pci_device_1000_0062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0407 = { + 0x0407, pci_device_1000_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0408 = { + 0x0408, pci_device_1000_0408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0409 = { + 0x0409, pci_device_1000_0409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0640 = { + 0x0640, pci_device_1000_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0642 = { + 0x0642, pci_device_1000_0642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0646 = { + 0x0646, pci_device_1000_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0804 = { + 0x0804, pci_device_1000_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0805 = { + 0x0805, pci_device_1000_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0806 = { + 0x0806, pci_device_1000_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0807 = { + 0x0807, pci_device_1000_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_3150 = { + 0x3150, pci_device_1002_3150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3152 = { + 0x3152, pci_device_1002_3152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3154 = { + 0x3154, pci_device_1002_3154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e50 = { + 0x3e50, pci_device_1002_3e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e54 = { + 0x3e54, pci_device_1002_3e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e70 = { + 0x3e70, pci_device_1002_3e70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4136 = { + 0x4136, pci_device_1002_4136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4137 = { + 0x4137, pci_device_1002_4137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4148 = { + 0x4148, pci_device_1002_4148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4149 = { + 0x4149, pci_device_1002_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414a = { + 0x414a, pci_device_1002_414a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414b = { + 0x414b, pci_device_1002_414b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4150 = { + 0x4150, pci_device_1002_4150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4151 = { + 0x4151, pci_device_1002_4151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4152 = { + 0x4152, pci_device_1002_4152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4153 = { + 0x4153, pci_device_1002_4153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4154 = { + 0x4154, pci_device_1002_4154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4155 = { + 0x4155, pci_device_1002_4155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4156 = { + 0x4156, pci_device_1002_4156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4157 = { + 0x4157, pci_device_1002_4157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4164 = { + 0x4164, pci_device_1002_4164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4165 = { + 0x4165, pci_device_1002_4165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4166 = { + 0x4166, pci_device_1002_4166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4168 = { + 0x4168, pci_device_1002_4168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4170 = { + 0x4170, pci_device_1002_4170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4171 = { + 0x4171, pci_device_1002_4171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4172 = { + 0x4172, pci_device_1002_4172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4173 = { + 0x4173, pci_device_1002_4173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4237 = { + 0x4237, pci_device_1002_4237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4243 = { + 0x4243, pci_device_1002_4243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4341 = { + 0x4341, pci_device_1002_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4345 = { + 0x4345, pci_device_1002_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4347 = { + 0x4347, pci_device_1002_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4348 = { + 0x4348, pci_device_1002_4348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4349 = { + 0x4349, pci_device_1002_4349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_434d = { + 0x434d, pci_device_1002_434d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_434d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4353 = { + 0x4353, pci_device_1002_4353, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4353, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4363 = { + 0x4363, pci_device_1002_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_436e = { + 0x436e, pci_device_1002_436e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_436e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4370 = { + 0x4370, pci_device_1002_4370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4371 = { + 0x4371, pci_device_1002_4371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4372 = { + 0x4372, pci_device_1002_4372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4373 = { + 0x4373, pci_device_1002_4373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4374 = { + 0x4374, pci_device_1002_4374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4375 = { + 0x4375, pci_device_1002_4375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4376 = { + 0x4376, pci_device_1002_4376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4377 = { + 0x4377, pci_device_1002_4377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4378 = { + 0x4378, pci_device_1002_4378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4379 = { + 0x4379, pci_device_1002_4379, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4379, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437a = { + 0x437a, pci_device_1002_437a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4437 = { + 0x4437, pci_device_1002_4437, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4437, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a48 = { + 0x4a48, pci_device_1002_4a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a49 = { + 0x4a49, pci_device_1002_4a49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4a = { + 0x4a4a, pci_device_1002_4a4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4b = { + 0x4a4b, pci_device_1002_4a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4c = { + 0x4a4c, pci_device_1002_4a4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4d = { + 0x4a4d, pci_device_1002_4a4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4e = { + 0x4a4e, pci_device_1002_4a4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a50 = { + 0x4a50, pci_device_1002_4a50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a70 = { + 0x4a70, pci_device_1002_4a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b49 = { + 0x4b49, pci_device_1002_4b49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4b = { + 0x4b4b, pci_device_1002_4b4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4c = { + 0x4b4c, pci_device_1002_4b4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b69 = { + 0x4b69, pci_device_1002_4b69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6b = { + 0x4b6b, pci_device_1002_4b6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6c = { + 0x4b6c, pci_device_1002_4b6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c6e = { + 0x4c6e, pci_device_1002_4c6e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c6e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e48 = { + 0x4e48, pci_device_1002_4e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e49 = { + 0x4e49, pci_device_1002_4e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4a = { + 0x4e4a, pci_device_1002_4e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4b = { + 0x4e4b, pci_device_1002_4e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e50 = { + 0x4e50, pci_device_1002_4e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e51 = { + 0x4e51, pci_device_1002_4e51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e52 = { + 0x4e52, pci_device_1002_4e52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e53 = { + 0x4e53, pci_device_1002_4e53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e54 = { + 0x4e54, pci_device_1002_4e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e56 = { + 0x4e56, pci_device_1002_4e56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e68 = { + 0x4e68, pci_device_1002_4e68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e69 = { + 0x4e69, pci_device_1002_4e69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e6a = { + 0x4e6a, pci_device_1002_4e6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e71 = { + 0x4e71, pci_device_1002_4e71, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e71, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5154 = { + 0x5154, pci_device_1002_5154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5155 = { + 0x5155, pci_device_1002_5155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515e = { + 0x515e, pci_device_1002_515e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5460 = { + 0x5460, pci_device_1002_5460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5462 = { + 0x5462, pci_device_1002_5462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5464 = { + 0x5464, pci_device_1002_5464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5548 = { + 0x5548, pci_device_1002_5548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5549 = { + 0x5549, pci_device_1002_5549, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5549, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554a = { + 0x554a, pci_device_1002_554a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554b = { + 0x554b, pci_device_1002_554b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554d = { + 0x554d, pci_device_1002_554d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554f = { + 0x554f, pci_device_1002_554f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5550 = { + 0x5550, pci_device_1002_5550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5551 = { + 0x5551, pci_device_1002_5551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5552 = { + 0x5552, pci_device_1002_5552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5554 = { + 0x5554, pci_device_1002_5554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556b = { + 0x556b, pci_device_1002_556b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556d = { + 0x556d, pci_device_1002_556d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556f = { + 0x556f, pci_device_1002_556f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564a = { + 0x564a, pci_device_1002_564a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564b = { + 0x564b, pci_device_1002_564b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5652 = { + 0x5652, pci_device_1002_5652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5653 = { + 0x5653, pci_device_1002_5653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5830 = { + 0x5830, pci_device_1002_5830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5831 = { + 0x5831, pci_device_1002_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5832 = { + 0x5832, pci_device_1002_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5833 = { + 0x5833, pci_device_1002_5833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5834 = { + 0x5834, pci_device_1002_5834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5835 = { + 0x5835, pci_device_1002_5835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5838 = { + 0x5838, pci_device_1002_5838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5940 = { + 0x5940, pci_device_1002_5940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5941 = { + 0x5941, pci_device_1002_5941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5944 = { + 0x5944, pci_device_1002_5944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5950 = { + 0x5950, pci_device_1002_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5951 = { + 0x5951, pci_device_1002_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5954 = { + 0x5954, pci_device_1002_5954, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5954, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5955 = { + 0x5955, pci_device_1002_5955, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5955, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5960 = { + 0x5960, pci_device_1002_5960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5961 = { + 0x5961, pci_device_1002_5961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5962 = { + 0x5962, pci_device_1002_5962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5964 = { + 0x5964, pci_device_1002_5964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5969 = { + 0x5969, pci_device_1002_5969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5974 = { + 0x5974, pci_device_1002_5974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5975 = { + 0x5975, pci_device_1002_5975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a34 = { + 0x5a34, pci_device_1002_5a34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a38 = { + 0x5a38, pci_device_1002_5a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a3f = { + 0x5a3f, pci_device_1002_5a3f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a3f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a41 = { + 0x5a41, pci_device_1002_5a41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a42 = { + 0x5a42, pci_device_1002_5a42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a61 = { + 0x5a61, pci_device_1002_5a61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a62 = { + 0x5a62, pci_device_1002_5a62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b60 = { + 0x5b60, pci_device_1002_5b60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b62 = { + 0x5b62, pci_device_1002_5b62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b63 = { + 0x5b63, pci_device_1002_5b63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b64 = { + 0x5b64, pci_device_1002_5b64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b65 = { + 0x5b65, pci_device_1002_5b65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b70 = { + 0x5b70, pci_device_1002_5b70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b72 = { + 0x5b72, pci_device_1002_5b72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b73 = { + 0x5b73, pci_device_1002_5b73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b74 = { + 0x5b74, pci_device_1002_5b74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c61 = { + 0x5c61, pci_device_1002_5c61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c63 = { + 0x5c63, pci_device_1002_5c63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d44 = { + 0x5d44, pci_device_1002_5d44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d48 = { + 0x5d48, pci_device_1002_5d48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d49 = { + 0x5d49, pci_device_1002_5d49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4a = { + 0x5d4a, pci_device_1002_5d4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4d = { + 0x5d4d, pci_device_1002_5d4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4f = { + 0x5d4f, pci_device_1002_5d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d52 = { + 0x5d52, pci_device_1002_5d52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d57 = { + 0x5d57, pci_device_1002_5d57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6d = { + 0x5d6d, pci_device_1002_5d6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6f = { + 0x5d6f, pci_device_1002_5d6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d72 = { + 0x5d72, pci_device_1002_5d72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d77 = { + 0x5d77, pci_device_1002_5d77, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d77, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e48 = { + 0x5e48, pci_device_1002_5e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e49 = { + 0x5e49, pci_device_1002_5e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4a = { + 0x5e4a, pci_device_1002_5e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4b = { + 0x5e4b, pci_device_1002_5e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4c = { + 0x5e4c, pci_device_1002_5e4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4d = { + 0x5e4d, pci_device_1002_5e4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4f = { + 0x5e4f, pci_device_1002_5e4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6b = { + 0x5e6b, pci_device_1002_5e6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6d = { + 0x5e6d, pci_device_1002_5e6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7010 = { + 0x7010, pci_device_1002_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7100 = { + 0x7100, pci_device_1002_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7105 = { + 0x7105, pci_device_1002_7105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7109 = { + 0x7109, pci_device_1002_7109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7120 = { + 0x7120, pci_device_1002_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7129 = { + 0x7129, pci_device_1002_7129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7142 = { + 0x7142, pci_device_1002_7142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7146 = { + 0x7146, pci_device_1002_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7162 = { + 0x7162, pci_device_1002_7162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7166 = { + 0x7166, pci_device_1002_7166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c0 = { + 0x71c0, pci_device_1002_71c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c2 = { + 0x71c2, pci_device_1002_71c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e0 = { + 0x71e0, pci_device_1002_71e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e2 = { + 0x71e2, pci_device_1002_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7833 = { + 0x7833, pci_device_1002_7833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7834 = { + 0x7834, pci_device_1002_7834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7835 = { + 0x7835, pci_device_1002_7835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7838 = { + 0x7838, pci_device_1002_7838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7c37 = { + 0x7c37, pci_device_1002_7c37, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7c37, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab0 = { + 0xcab0, pci_device_1002_cab0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab2 = { + 0xcab2, pci_device_1002_cab2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab3 = { + 0xcab3, pci_device_1002_cab3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cbb2 = { + 0xcbb2, pci_device_1002_cbb2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cbb2, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0021 = { + 0x0021, pci_device_100b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0028 = { + 0x0028, pci_device_100b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002a = { + 0x002a, pci_device_100b_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002b = { + 0x002b, pci_device_100b_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002d = { + 0x002d, pci_device_100b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002e = { + 0x002e, pci_device_100b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002f = { + 0x002f, pci_device_100b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0030 = { + 0x0030, pci_device_100b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0035 = { + 0x0035, pci_device_100b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0510 = { + 0x0510, pci_device_100b_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0511 = { + 0x0511, pci_device_100b_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0515 = { + 0x0515, pci_device_100b_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0017 = { + 0x0017, pci_device_1011_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4000 = { + 0x4000, pci_device_1013_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0031 = { + 0x0031, pci_device_1014_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0037 = { + 0x0037, pci_device_1014_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003c = { + 0x003c, pci_device_1014_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0054 = { + 0x0054, pci_device_1014_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005e = { + 0x005e, pci_device_1014_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008b = { + 0x008b, pci_device_1014_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008e = { + 0x008e, pci_device_1014_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0091 = { + 0x0091, pci_device_1014_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_009f = { + 0x009f, pci_device_1014_009f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_009f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b8 = { + 0x00b8, pci_device_1014_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0104 = { + 0x0104, pci_device_1014_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_015e = { + 0x015e, pci_device_1014_015e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_015e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0160 = { + 0x0160, pci_device_1014_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_016e = { + 0x016e, pci_device_1014_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0170 = { + 0x0170, pci_device_1014_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_017d = { + 0x017d, pci_device_1014_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0180 = { + 0x0180, pci_device_1014_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0188 = { + 0x0188, pci_device_1014_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01c1 = { + 0x01c1, pci_device_1014_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01e6 = { + 0x01e6, pci_device_1014_01e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01ff = { + 0x01ff, pci_device_1014_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0219 = { + 0x0219, pci_device_1014_0219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021b = { + 0x021b, pci_device_1014_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021c = { + 0x021c, pci_device_1014_021c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0233 = { + 0x0233, pci_device_1014_0233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0266 = { + 0x0266, pci_device_1014_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0268 = { + 0x0268, pci_device_1014_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0269 = { + 0x0269, pci_device_1014_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_028c = { + 0x028c, pci_device_1014_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02a1 = { + 0x02a1, pci_device_1014_02a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02bd = { + 0x02bd, pci_device_1014_02bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0314 = { + 0x0314, pci_device_1014_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_3022 = { + 0x3022, pci_device_1014_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_4022 = { + 0x4022, pci_device_1014_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_0009 = { + 0x0009, pci_device_101e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2003 = { + 0x2003, pci_device_1022_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2081 = { + 0x2081, pci_device_1022_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2082 = { + 0x2082, pci_device_1022_2082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_208f = { + 0x208f, pci_device_1022_208f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_208f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2090 = { + 0x2090, pci_device_1022_2090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2091 = { + 0x2091, pci_device_1022_2091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2093 = { + 0x2093, pci_device_1022_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2094 = { + 0x2094, pci_device_1022_2094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2095 = { + 0x2095, pci_device_1022_2095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2096 = { + 0x2096, pci_device_1022_2096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2097 = { + 0x2097, pci_device_1022_2097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_209a = { + 0x209a, pci_device_1022_209a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_209a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700a = { + 0x700a, pci_device_1022_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700b = { + 0x700b, pci_device_1022_700b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7458 = { + 0x7458, pci_device_1022_7458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7459 = { + 0x7459, pci_device_1022_7459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_756b = { + 0x756b, pci_device_1022_756b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_756b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2100 = { + 0x2100, pci_device_1023_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2200 = { + 0x2200, pci_device_1023_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1671 = { + 0x1671, pci_device_1025_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1672 = { + 0x1672, pci_device_1025_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0009 = { + 0x0009, pci_device_1028_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000d = { + 0x000d, pci_device_1028_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0010 = { + 0x0010, pci_device_1028_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0011 = { + 0x0011, pci_device_1028_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0012 = { + 0x0012, pci_device_1028_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0013 = { + 0x0013, pci_device_1028_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0014 = { + 0x0014, pci_device_1028_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0015 = { + 0x0015, pci_device_1028_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0015, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_001f = { + 0x001f, pci_device_102a_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00c5 = { + 0x00c5, pci_device_102a_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00cf = { + 0x00cf, pci_device_102a_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00cf, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0100 = { + 0x0100, pci_device_102b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0528 = { + 0x0528, pci_device_102b_0528, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0528, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2537 = { + 0x2537, pci_device_102b_2537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2538 = { + 0x2538, pci_device_102b_2538, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2538, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_000a = { + 0x000a, pci_device_102f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0030 = { + 0x0030, pci_device_102f_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0031 = { + 0x0031, pci_device_102f_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0105 = { + 0x0105, pci_device_102f_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0106 = { + 0x0106, pci_device_102f_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0107 = { + 0x0107, pci_device_102f_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0108 = { + 0x0108, pci_device_102f_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0180 = { + 0x0180, pci_device_102f_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0181 = { + 0x0181, pci_device_102f_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0182 = { + 0x0182, pci_device_102f_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0182, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0000 = { + 0x0000, pci_device_1033_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0072 = { + 0x0072, pci_device_1033_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a5 = { + 0x00a5, pci_device_1033_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00ce = { + 0x00ce, pci_device_1033_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00df = { + 0x00df, pci_device_1033_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e7 = { + 0x00e7, pci_device_1033_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f2 = { + 0x00f2, pci_device_1033_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f3 = { + 0x00f3, pci_device_1033_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_010c = { + 0x010c, pci_device_1033_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_010c, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0003 = { + 0x0003, pci_device_1039_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0004 = { + 0x0004, pci_device_1039_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_000a = { + 0x000a, pci_device_1039_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0016 = { + 0x0016, pci_device_1039_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0180 = { + 0x0180, pci_device_1039_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0181 = { + 0x0181, pci_device_1039_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0182 = { + 0x0182, pci_device_1039_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0190 = { + 0x0190, pci_device_1039_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0191 = { + 0x0191, pci_device_1039_0191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0550 = { + 0x0550, pci_device_1039_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0648 = { + 0x0648, pci_device_1039_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0655 = { + 0x0655, pci_device_1039_0655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0660 = { + 0x0660, pci_device_1039_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0661 = { + 0x0661, pci_device_1039_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0661, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0741 = { + 0x0741, pci_device_1039_0741, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0741, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0746 = { + 0x0746, pci_device_1039_0746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0755 = { + 0x0755, pci_device_1039_0755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0760 = { + 0x0760, pci_device_1039_0760, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0760, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0761 = { + 0x0761, pci_device_1039_0761, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0761, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0963 = { + 0x0963, pci_device_1039_0963, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0963, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0964 = { + 0x0964, pci_device_1039_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0965 = { + 0x0965, pci_device_1039_0965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6330 = { + 0x6330, pci_device_1039_6330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7019 = { + 0x7019, pci_device_1039_7019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1006 = { + 0x1006, pci_device_103c_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_100a = { + 0x100a, pci_device_103c_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1054 = { + 0x1054, pci_device_103c_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f0 = { + 0x10f0, pci_device_103c_10f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f1 = { + 0x10f1, pci_device_103c_10f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127c = { + 0x127c, pci_device_103c_127c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1291 = { + 0x1291, pci_device_103c_1291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12b4 = { + 0x12b4, pci_device_103c_12b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12fa = { + 0x12fa, pci_device_103c_12fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3080 = { + 0x3080, pci_device_103c_3080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3220 = { + 0x3220, pci_device_103c_3220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3230 = { + 0x3230, pci_device_103c_3230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3230, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4015 = { + 0x4015, pci_device_1043_4015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4057 = { + 0x4057, pci_device_1043_4057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8043 = { + 0x8043, pci_device_1043_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_807b = { + 0x807b, pci_device_1043_807b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_807b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80bb = { + 0x80bb, pci_device_1043_80bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80c5 = { + 0x80c5, pci_device_1043_80c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80df = { + 0x80df, pci_device_1043_80df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8187 = { + 0x8187, pci_device_1043_8187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8188 = { + 0x8188, pci_device_1043_8188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8188, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0c60 = { + 0x0c60, pci_device_1048_0c60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0c60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_8901 = { + 0x8901, pci_device_1048_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_8901, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0209 = { + 0x0209, pci_device_104a_0209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_020a = { + 0x020a, pci_device_104a_020a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_020a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021a = { + 0x021a, pci_device_104a_021a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021b = { + 0x021b, pci_device_104a_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0500 = { + 0x0500, pci_device_104a_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0564 = { + 0x0564, pci_device_104a_0564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_55cc = { + 0x55cc, pci_device_104a_55cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_55cc, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8025 = { + 0x8025, pci_device_104c_8025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8029 = { + 0x8029, pci_device_104c_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802b = { + 0x802b, pci_device_104c_802b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802e = { + 0x802e, pci_device_104c_802e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8031 = { + 0x8031, pci_device_104c_8031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8032 = { + 0x8032, pci_device_104c_8032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8033 = { + 0x8033, pci_device_104c_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8034 = { + 0x8034, pci_device_104c_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8035 = { + 0x8035, pci_device_104c_8035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8036 = { + 0x8036, pci_device_104c_8036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8038 = { + 0x8038, pci_device_104c_8038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8201 = { + 0x8201, pci_device_104c_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8204 = { + 0x8204, pci_device_104c_8204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8401 = { + 0x8401, pci_device_104c_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9000 = { + 0x9000, pci_device_104c_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9065 = { + 0x9065, pci_device_104c_9065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9066 = { + 0x9066, pci_device_104c_9066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac44 = { + 0xac44, pci_device_104c_ac44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac46 = { + 0xac46, pci_device_104c_ac46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac47 = { + 0xac47, pci_device_104c_ac47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac4a = { + 0xac4a, pci_device_104c_ac4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac54 = { + 0xac54, pci_device_104c_ac54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8d = { + 0xac8d, pci_device_104c_ac8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8e = { + 0xac8e, pci_device_104c_ac8e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8f = { + 0xac8f, pci_device_104c_ac8f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8004 = { + 0x8004, pci_device_104d_8004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9921 = { + 0x9921, pci_device_1050_9921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9922 = { + 0x9922, pci_device_1050_9922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0008 = { + 0x0008, pci_device_1057_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0009 = { + 0x0009, pci_device_1057_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c1 = { + 0x18c1, pci_device_1057_18c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3410 = { + 0x3410, pci_device_1057_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5608 = { + 0x5608, pci_device_1057_5608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5803 = { + 0x5803, pci_device_1057_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5806 = { + 0x5806, pci_device_1057_5806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5808 = { + 0x5808, pci_device_1057_5808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6405 = { + 0x6405, pci_device_1057_6405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6405, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3318 = { + 0x3318, pci_device_105a_3318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3319 = { + 0x3319, pci_device_105a_3319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3371 = { + 0x3371, pci_device_105a_3371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3373 = { + 0x3373, pci_device_105a_3373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3375 = { + 0x3375, pci_device_105a_3375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3515 = { + 0x3515, pci_device_105a_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3519 = { + 0x3519, pci_device_105a_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3570 = { + 0x3570, pci_device_105a_3570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3571 = { + 0x3571, pci_device_105a_3571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3574 = { + 0x3574, pci_device_105a_3574, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3574, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3577 = { + 0x3577, pci_device_105a_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d17 = { + 0x3d17, pci_device_105a_3d17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d18 = { + 0x3d18, pci_device_105a_3d18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d73 = { + 0x3d73, pci_device_105a_3d73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d75 = { + 0x3d75, pci_device_105a_3d75, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d75, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6622 = { + 0x6622, pci_device_105a_6622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6624 = { + 0x6624, pci_device_105a_6624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6626 = { + 0x6626, pci_device_105a_6626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6629 = { + 0x6629, pci_device_105a_6629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8002 = { + 0x8002, pci_device_105a_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_0301 = { + 0x0301, pci_device_1067_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0304 = { + 0x0304, pci_device_1067_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0308 = { + 0x0308, pci_device_1067_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0020 = { + 0x0020, pci_device_1069_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_b166 = { + 0xb166, pci_device_1069_b166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_b166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba57 = { + 0xba57, pci_device_1069_ba57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba57, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000c = { + 0x000c, pci_device_106b_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0035 = { + 0x0035, pci_device_106b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0036 = { + 0x0036, pci_device_106b_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003b = { + 0x003b, pci_device_106b_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003e = { + 0x003e, pci_device_106b_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003f = { + 0x003f, pci_device_106b_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0040 = { + 0x0040, pci_device_106b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0041 = { + 0x0041, pci_device_106b_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0042 = { + 0x0042, pci_device_106b_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0043 = { + 0x0043, pci_device_106b_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0045 = { + 0x0045, pci_device_106b_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0046 = { + 0x0046, pci_device_106b_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0047 = { + 0x0047, pci_device_106b_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0048 = { + 0x0048, pci_device_106b_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0049 = { + 0x0049, pci_device_106b_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004b = { + 0x004b, pci_device_106b_004b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004c = { + 0x004c, pci_device_106b_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004f = { + 0x004f, pci_device_106b_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0050 = { + 0x0050, pci_device_106b_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0051 = { + 0x0051, pci_device_106b_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0052 = { + 0x0052, pci_device_106b_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0053 = { + 0x0053, pci_device_106b_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0054 = { + 0x0054, pci_device_106b_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0055 = { + 0x0055, pci_device_106b_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0058 = { + 0x0058, pci_device_106b_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0059 = { + 0x0059, pci_device_106b_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0066 = { + 0x0066, pci_device_106b_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0067 = { + 0x0067, pci_device_106b_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0068 = { + 0x0068, pci_device_106b_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0069 = { + 0x0069, pci_device_106b_0069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006a = { + 0x006a, pci_device_106b_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006b = { + 0x006b, pci_device_106b_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1071_8160 = { + 0x8160, pci_device_1071_8160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1071_8160, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2322 = { + 0x2322, pci_device_1077_2322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2422 = { + 0x2422, pci_device_1077_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2432 = { + 0x2432, pci_device_1077_2432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3010 = { + 0x3010, pci_device_1077_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3022 = { + 0x3022, pci_device_1077_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4010 = { + 0x4010, pci_device_1077_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4022 = { + 0x4022, pci_device_1077_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6312 = { + 0x6312, pci_device_1077_6312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6322 = { + 0x6322, pci_device_1077_6322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6322, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2134 = { + 0x2134, pci_device_107d_2134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2971 = { + 0x2971, pci_device_107d_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2971, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1648 = { + 0x1648, pci_device_108e_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8002 = { + 0x8002, pci_device_108e_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a801 = { + 0xa801, pci_device_108e_a801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_abba = { + 0xabba, pci_device_108e_abba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_abba, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_07a0 = { + 0x07a0, pci_device_1091_07a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_07a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_1091 = { + 0x1091, pci_device_1091_1091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_1091, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1310 = { + 0x1310, pci_device_1093_1310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14e0 = { + 0x14e0, pci_device_1093_14e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14f0 = { + 0x14f0, pci_device_1093_14f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_17d0 = { + 0x17d0, pci_device_1093_17d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_17d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1870 = { + 0x1870, pci_device_1093_1870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1880 = { + 0x1880, pci_device_1093_1880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_18b0 = { + 0x18b0, pci_device_1093_18b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_18b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2410 = { + 0x2410, pci_device_1093_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2890 = { + 0x2890, pci_device_1093_2890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a70 = { + 0x2a70, pci_device_1093_2a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a80 = { + 0x2a80, pci_device_1093_2a80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2c80 = { + 0x2c80, pci_device_1093_2c80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2c80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2ca0 = { + 0x2ca0, pci_device_1093_2ca0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2ca0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70a9 = { + 0x70a9, pci_device_1093_70a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70b8 = { + 0x70b8, pci_device_1093_70b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0240 = { + 0x0240, pci_device_1095_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3114 = { + 0x3114, pci_device_1095_3114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3124 = { + 0x3124, pci_device_1095_3124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3132 = { + 0x3132, pci_device_1095_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3512 = { + 0x3512, pci_device_1095_3512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3512, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_032e = { + 0x032e, pci_device_109e_032e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_032e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_3052 = { + 0x3052, pci_device_10a5_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_100a = { + 0x100a, pci_device_10a9_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4001 = { + 0x4001, pci_device_10a9_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4002 = { + 0x4002, pci_device_10a9_4002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8010 = { + 0x8010, pci_device_10a9_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8018 = { + 0x8018, pci_device_10a9_8018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1042 = { + 0x1042, pci_device_10b5_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2540 = { + 0x2540, pci_device_10b5_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6540 = { + 0x6540, pci_device_10b5_6540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6541 = { + 0x6541, pci_device_10b5_6541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6542 = { + 0x6542, pci_device_10b5_6542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8111 = { + 0x8111, pci_device_10b5_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8114 = { + 0x8114, pci_device_10b5_8114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8516 = { + 0x8516, pci_device_10b5_8516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8532 = { + 0x8532, pci_device_10b5_8532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9056 = { + 0x9056, pci_device_10b5_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_bb04 = { + 0xbb04, pci_device_10b5_bb04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_bb04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0013 = { + 0x0013, pci_device_10b7_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0910 = { + 0x0910, pci_device_10b7_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1201 = { + 0x1201, pci_device_10b7_1201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1202 = { + 0x1202, pci_device_10b7_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1700 = { + 0x1700, pci_device_10b7_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6000 = { + 0x6000, pci_device_10b7_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6001 = { + 0x6001, pci_device_10b7_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7770 = { + 0x7770, pci_device_10b7_7770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_80eb = { + 0x80eb, pci_device_10b7_80eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_80eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9202 = { + 0x9202, pci_device_10b7_9202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9210 = { + 0x9210, pci_device_10b7_9210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990a = { + 0x990a, pci_device_10b7_990a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_2802 = { + 0x2802, pci_device_10b8_2802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_2802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b9_0101 = { + 0x0101, pci_device_10b9_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0780 = { + 0x0780, pci_device_10b9_0780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0782 = { + 0x0782, pci_device_10b9_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1573 = { + 0x1573, pci_device_10b9_1573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1672 = { + 0x1672, pci_device_10b9_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1689 = { + 0x1689, pci_device_10b9_1689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1695 = { + 0x1695, pci_device_10b9_1695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1695, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1697 = { + 0x1697, pci_device_10b9_1697, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1697, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3323 = { + 0x3323, pci_device_10b9_3323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5228 = { + 0x5228, pci_device_10b9_5228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5246 = { + 0x5246, pci_device_10b9_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524b = { + 0x524b, pci_device_10b9_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524c = { + 0x524c, pci_device_10b9_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524d = { + 0x524d, pci_device_10b9_524d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524e = { + 0x524e, pci_device_10b9_524e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5263 = { + 0x5263, pci_device_10b9_5263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5281 = { + 0x5281, pci_device_10b9_5281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5287 = { + 0x5287, pci_device_10b9_5287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5288 = { + 0x5288, pci_device_10b9_5288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5289 = { + 0x5289, pci_device_10b9_5289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5450 = { + 0x5450, pci_device_10b9_5450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5461 = { + 0x5461, pci_device_10b9_5461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0304 = { + 0x0304, pci_device_10ba_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0308 = { + 0x0308, pci_device_10ba_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_1002 = { + 0x1002, pci_device_10ba_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cc_0660 = { + 0x0660, pci_device_10cc_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cc_0661 = { + 0x0661, pci_device_10cc_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0661, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0431 = { + 0x0431, pci_device_10d9_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8626 = { + 0x8626, pci_device_10d9_8626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dd_0100 = { + 0x0100, pci_device_10dd_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dd_0100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0034 = { + 0x0034, pci_device_10de_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0035 = { + 0x0035, pci_device_10de_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0036 = { + 0x0036, pci_device_10de_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0037 = { + 0x0037, pci_device_10de_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0038 = { + 0x0038, pci_device_10de_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003a = { + 0x003a, pci_device_10de_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003b = { + 0x003b, pci_device_10de_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003c = { + 0x003c, pci_device_10de_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003d = { + 0x003d, pci_device_10de_003d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003e = { + 0x003e, pci_device_10de_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0040 = { + 0x0040, pci_device_10de_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0041 = { + 0x0041, pci_device_10de_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0042 = { + 0x0042, pci_device_10de_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0043 = { + 0x0043, pci_device_10de_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0045 = { + 0x0045, pci_device_10de_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0046 = { + 0x0046, pci_device_10de_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0047 = { + 0x0047, pci_device_10de_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0048 = { + 0x0048, pci_device_10de_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0049 = { + 0x0049, pci_device_10de_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004e = { + 0x004e, pci_device_10de_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0050 = { + 0x0050, pci_device_10de_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0051 = { + 0x0051, pci_device_10de_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0052 = { + 0x0052, pci_device_10de_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0053 = { + 0x0053, pci_device_10de_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0054 = { + 0x0054, pci_device_10de_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0055 = { + 0x0055, pci_device_10de_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0056 = { + 0x0056, pci_device_10de_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0057 = { + 0x0057, pci_device_10de_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0058 = { + 0x0058, pci_device_10de_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0059 = { + 0x0059, pci_device_10de_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005a = { + 0x005a, pci_device_10de_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005b = { + 0x005b, pci_device_10de_005b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005c = { + 0x005c, pci_device_10de_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005d = { + 0x005d, pci_device_10de_005d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005e = { + 0x005e, pci_device_10de_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005f = { + 0x005f, pci_device_10de_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006c = { + 0x006c, pci_device_10de_006c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006d = { + 0x006d, pci_device_10de_006d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0080 = { + 0x0080, pci_device_10de_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0084 = { + 0x0084, pci_device_10de_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0085 = { + 0x0085, pci_device_10de_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0086 = { + 0x0086, pci_device_10de_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0087 = { + 0x0087, pci_device_10de_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0088 = { + 0x0088, pci_device_10de_0088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008a = { + 0x008a, pci_device_10de_008a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008b = { + 0x008b, pci_device_10de_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008c = { + 0x008c, pci_device_10de_008c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008e = { + 0x008e, pci_device_10de_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0091 = { + 0x0091, pci_device_10de_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0092 = { + 0x0092, pci_device_10de_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0099 = { + 0x0099, pci_device_10de_0099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_009d = { + 0x009d, pci_device_10de_009d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_009d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c0 = { + 0x00c0, pci_device_10de_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c1 = { + 0x00c1, pci_device_10de_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c2 = { + 0x00c2, pci_device_10de_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c3 = { + 0x00c3, pci_device_10de_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c8 = { + 0x00c8, pci_device_10de_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c9 = { + 0x00c9, pci_device_10de_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cc = { + 0x00cc, pci_device_10de_00cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cd = { + 0x00cd, pci_device_10de_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ce = { + 0x00ce, pci_device_10de_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d0 = { + 0x00d0, pci_device_10de_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d1 = { + 0x00d1, pci_device_10de_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d2 = { + 0x00d2, pci_device_10de_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d3 = { + 0x00d3, pci_device_10de_00d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d4 = { + 0x00d4, pci_device_10de_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d5 = { + 0x00d5, pci_device_10de_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d6 = { + 0x00d6, pci_device_10de_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d7 = { + 0x00d7, pci_device_10de_00d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d8 = { + 0x00d8, pci_device_10de_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d9 = { + 0x00d9, pci_device_10de_00d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00da = { + 0x00da, pci_device_10de_00da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00dd = { + 0x00dd, pci_device_10de_00dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00df = { + 0x00df, pci_device_10de_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e0 = { + 0x00e0, pci_device_10de_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e1 = { + 0x00e1, pci_device_10de_00e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e2 = { + 0x00e2, pci_device_10de_00e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e3 = { + 0x00e3, pci_device_10de_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e4 = { + 0x00e4, pci_device_10de_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e5 = { + 0x00e5, pci_device_10de_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e6 = { + 0x00e6, pci_device_10de_00e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e7 = { + 0x00e7, pci_device_10de_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e8 = { + 0x00e8, pci_device_10de_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ea = { + 0x00ea, pci_device_10de_00ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ed = { + 0x00ed, pci_device_10de_00ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ee = { + 0x00ee, pci_device_10de_00ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f0 = { + 0x00f0, pci_device_10de_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f1 = { + 0x00f1, pci_device_10de_00f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f2 = { + 0x00f2, pci_device_10de_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f3 = { + 0x00f3, pci_device_10de_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f8 = { + 0x00f8, pci_device_10de_00f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f9 = { + 0x00f9, pci_device_10de_00f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fa = { + 0x00fa, pci_device_10de_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fb = { + 0x00fb, pci_device_10de_00fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fc = { + 0x00fc, pci_device_10de_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fd = { + 0x00fd, pci_device_10de_00fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fe = { + 0x00fe, pci_device_10de_00fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ff = { + 0x00ff, pci_device_10de_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0140 = { + 0x0140, pci_device_10de_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0141 = { + 0x0141, pci_device_10de_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0142 = { + 0x0142, pci_device_10de_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0144 = { + 0x0144, pci_device_10de_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0145 = { + 0x0145, pci_device_10de_0145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0146 = { + 0x0146, pci_device_10de_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0147 = { + 0x0147, pci_device_10de_0147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0148 = { + 0x0148, pci_device_10de_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0149 = { + 0x0149, pci_device_10de_0149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014e = { + 0x014e, pci_device_10de_014e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014f = { + 0x014f, pci_device_10de_014f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0160 = { + 0x0160, pci_device_10de_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0161 = { + 0x0161, pci_device_10de_0161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0162 = { + 0x0162, pci_device_10de_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0163 = { + 0x0163, pci_device_10de_0163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0164 = { + 0x0164, pci_device_10de_0164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0165 = { + 0x0165, pci_device_10de_0165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0166 = { + 0x0166, pci_device_10de_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0167 = { + 0x0167, pci_device_10de_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0168 = { + 0x0168, pci_device_10de_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0169 = { + 0x0169, pci_device_10de_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0177 = { + 0x0177, pci_device_10de_0177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017d = { + 0x017d, pci_device_10de_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0185 = { + 0x0185, pci_device_10de_0185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0186 = { + 0x0186, pci_device_10de_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0187 = { + 0x0187, pci_device_10de_0187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018c = { + 0x018c, pci_device_10de_018c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018d = { + 0x018d, pci_device_10de_018d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b0 = { + 0x01b0, pci_device_10de_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e0 = { + 0x01e0, pci_device_10de_01e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ea = { + 0x01ea, pci_device_10de_01ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01eb = { + 0x01eb, pci_device_10de_01eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ec = { + 0x01ec, pci_device_10de_01ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ed = { + 0x01ed, pci_device_10de_01ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ee = { + 0x01ee, pci_device_10de_01ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ef = { + 0x01ef, pci_device_10de_01ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0211 = { + 0x0211, pci_device_10de_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0212 = { + 0x0212, pci_device_10de_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0215 = { + 0x0215, pci_device_10de_0215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0221 = { + 0x0221, pci_device_10de_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0240 = { + 0x0240, pci_device_10de_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0241 = { + 0x0241, pci_device_10de_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0242 = { + 0x0242, pci_device_10de_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0243 = { + 0x0243, pci_device_10de_0243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0244 = { + 0x0244, pci_device_10de_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0245 = { + 0x0245, pci_device_10de_0245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0246 = { + 0x0246, pci_device_10de_0246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0247 = { + 0x0247, pci_device_10de_0247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0248 = { + 0x0248, pci_device_10de_0248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0249 = { + 0x0249, pci_device_10de_0249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024a = { + 0x024a, pci_device_10de_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024b = { + 0x024b, pci_device_10de_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024c = { + 0x024c, pci_device_10de_024c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024d = { + 0x024d, pci_device_10de_024d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024e = { + 0x024e, pci_device_10de_024e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024f = { + 0x024f, pci_device_10de_024f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0260 = { + 0x0260, pci_device_10de_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0261 = { + 0x0261, pci_device_10de_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0262 = { + 0x0262, pci_device_10de_0262, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0262, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0263 = { + 0x0263, pci_device_10de_0263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0264 = { + 0x0264, pci_device_10de_0264, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0264, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0265 = { + 0x0265, pci_device_10de_0265, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0265, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0266 = { + 0x0266, pci_device_10de_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0267 = { + 0x0267, pci_device_10de_0267, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0267, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0268 = { + 0x0268, pci_device_10de_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0269 = { + 0x0269, pci_device_10de_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026a = { + 0x026a, pci_device_10de_026a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026b = { + 0x026b, pci_device_10de_026b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026c = { + 0x026c, pci_device_10de_026c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026d = { + 0x026d, pci_device_10de_026d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026e = { + 0x026e, pci_device_10de_026e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026f = { + 0x026f, pci_device_10de_026f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0270 = { + 0x0270, pci_device_10de_0270, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0270, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0271 = { + 0x0271, pci_device_10de_0271, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0271, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0272 = { + 0x0272, pci_device_10de_0272, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0272, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027e = { + 0x027e, pci_device_10de_027e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027f = { + 0x027f, pci_device_10de_027f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0286 = { + 0x0286, pci_device_10de_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_028c = { + 0x028c, pci_device_10de_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02a0 = { + 0x02a0, pci_device_10de_02a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f0 = { + 0x02f0, pci_device_10de_02f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f1 = { + 0x02f1, pci_device_10de_02f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f2 = { + 0x02f2, pci_device_10de_02f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f3 = { + 0x02f3, pci_device_10de_02f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f4 = { + 0x02f4, pci_device_10de_02f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f5 = { + 0x02f5, pci_device_10de_02f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f6 = { + 0x02f6, pci_device_10de_02f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f7 = { + 0x02f7, pci_device_10de_02f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f8 = { + 0x02f8, pci_device_10de_02f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f9 = { + 0x02f9, pci_device_10de_02f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fa = { + 0x02fa, pci_device_10de_02fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fb = { + 0x02fb, pci_device_10de_02fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fc = { + 0x02fc, pci_device_10de_02fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fd = { + 0x02fd, pci_device_10de_02fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fe = { + 0x02fe, pci_device_10de_02fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02ff = { + 0x02ff, pci_device_10de_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0311 = { + 0x0311, pci_device_10de_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0312 = { + 0x0312, pci_device_10de_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0313 = { + 0x0313, pci_device_10de_0313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0314 = { + 0x0314, pci_device_10de_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0316 = { + 0x0316, pci_device_10de_0316, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0316, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0317 = { + 0x0317, pci_device_10de_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0317, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031a = { + 0x031a, pci_device_10de_031a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031b = { + 0x031b, pci_device_10de_031b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031c = { + 0x031c, pci_device_10de_031c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031d = { + 0x031d, pci_device_10de_031d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031e = { + 0x031e, pci_device_10de_031e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031f = { + 0x031f, pci_device_10de_031f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0320 = { + 0x0320, pci_device_10de_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0321 = { + 0x0321, pci_device_10de_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0322 = { + 0x0322, pci_device_10de_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0323 = { + 0x0323, pci_device_10de_0323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0324 = { + 0x0324, pci_device_10de_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0325 = { + 0x0325, pci_device_10de_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0326 = { + 0x0326, pci_device_10de_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0327 = { + 0x0327, pci_device_10de_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0328 = { + 0x0328, pci_device_10de_0328, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0328, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0329 = { + 0x0329, pci_device_10de_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032a = { + 0x032a, pci_device_10de_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032b = { + 0x032b, pci_device_10de_032b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032c = { + 0x032c, pci_device_10de_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032d = { + 0x032d, pci_device_10de_032d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032f = { + 0x032f, pci_device_10de_032f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0330 = { + 0x0330, pci_device_10de_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0331 = { + 0x0331, pci_device_10de_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0332 = { + 0x0332, pci_device_10de_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0333 = { + 0x0333, pci_device_10de_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0334 = { + 0x0334, pci_device_10de_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0338 = { + 0x0338, pci_device_10de_0338, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0338, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_033f = { + 0x033f, pci_device_10de_033f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_033f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0341 = { + 0x0341, pci_device_10de_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0342 = { + 0x0342, pci_device_10de_0342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0343 = { + 0x0343, pci_device_10de_0343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0344 = { + 0x0344, pci_device_10de_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0345 = { + 0x0345, pci_device_10de_0345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0347 = { + 0x0347, pci_device_10de_0347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0348 = { + 0x0348, pci_device_10de_0348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0349 = { + 0x0349, pci_device_10de_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034b = { + 0x034b, pci_device_10de_034b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034c = { + 0x034c, pci_device_10de_034c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034e = { + 0x034e, pci_device_10de_034e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034f = { + 0x034f, pci_device_10de_034f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0360 = { + 0x0360, pci_device_10de_0360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0361 = { + 0x0361, pci_device_10de_0361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0362 = { + 0x0362, pci_device_10de_0362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0363 = { + 0x0363, pci_device_10de_0363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0364 = { + 0x0364, pci_device_10de_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0365 = { + 0x0365, pci_device_10de_0365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0366 = { + 0x0366, pci_device_10de_0366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0367 = { + 0x0367, pci_device_10de_0367, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0367, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0368 = { + 0x0368, pci_device_10de_0368, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0368, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0369 = { + 0x0369, pci_device_10de_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036a = { + 0x036a, pci_device_10de_036a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036c = { + 0x036c, pci_device_10de_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036d = { + 0x036d, pci_device_10de_036d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036e = { + 0x036e, pci_device_10de_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0371 = { + 0x0371, pci_device_10de_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0372 = { + 0x0372, pci_device_10de_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0373 = { + 0x0373, pci_device_10de_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037a = { + 0x037a, pci_device_10de_037a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037e = { + 0x037e, pci_device_10de_037e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037f = { + 0x037f, pci_device_10de_037f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a1 = { + 0xf0a1, pci_device_10df_f0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a5 = { + 0xf0a5, pci_device_10df_f0a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0b5 = { + 0xf0b5, pci_device_10df_f0b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d1 = { + 0xf0d1, pci_device_10df_f0d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d5 = { + 0xf0d5, pci_device_10df_f0d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e1 = { + 0xf0e1, pci_device_10df_f0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e5 = { + 0xf0e5, pci_device_10df_f0e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0f5 = { + 0xf0f5, pci_device_10df_f0f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f701 = { + 0xf701, pci_device_10df_f701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f801 = { + 0xf801, pci_device_10df_f801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f901 = { + 0xf901, pci_device_10df_f901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f981 = { + 0xf981, pci_device_10df_f981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f982 = { + 0xf982, pci_device_10df_f982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fa00 = { + 0xfa00, pci_device_10df_fa00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fa00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fb00 = { + 0xfb00, pci_device_10df_fb00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fb00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc00 = { + 0xfc00, pci_device_10df_fc00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc10 = { + 0xfc10, pci_device_10df_fc10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc20 = { + 0xfc20, pci_device_10df_fc20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fd00 = { + 0xfd00, pci_device_10df_fd00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fd00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fe00 = { + 0xfe00, pci_device_10df_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_ff00 = { + 0xff00, pci_device_10df_ff00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_ff00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0148 = { + 0x0148, pci_device_10e3_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8260 = { + 0x8260, pci_device_10e3_8260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8261 = { + 0x8261, pci_device_10e3_8261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8261, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e4_8029 = { + 0x8029, pci_device_10e4_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e4_8029, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_1072 = { + 0x1072, pci_device_10e8_1072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_1072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_814c = { + 0x814c, pci_device_10e8_814c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_814c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_81e6 = { + 0x81e6, pci_device_10e8_81e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_81e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8291 = { + 0x8291, pci_device_10e8_8291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c4 = { + 0x82c4, pci_device_10e8_82c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c5 = { + 0x82c5, pci_device_10e8_82c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c6 = { + 0x82c6, pci_device_10e8_82c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c7 = { + 0x82c7, pci_device_10e8_82c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82ca = { + 0x82ca, pci_device_10e8_82ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82e2 = { + 0x82e2, pci_device_10e8_82e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8851 = { + 0x8851, pci_device_10e8_8851, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8851, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5252 = { + 0x5252, pci_device_10ea_5252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5252, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_0139 = { + 0x0139, pci_device_10ec_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8180 = { + 0x8180, pci_device_10ec_8180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_0205 = { + 0x0205, pci_device_10ee_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0210 = { + 0x0210, pci_device_10ee_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0314 = { + 0x0314, pci_device_10ee_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0405 = { + 0x0405, pci_device_10ee_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0410 = { + 0x0410, pci_device_10ee_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc6 = { + 0x3fc6, pci_device_10ee_3fc6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_8381 = { + 0x8381, pci_device_10ee_8381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_8381, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9502 = { + 0x9502, pci_device_1101_9502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9502, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0x0401 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0007 = { + 0x0007, pci_device_1102_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0008 = { + 0x0008, pci_device_1102_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7005 = { + 0x7005, pci_device_1102_7005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0009 = { + 0x0009, pci_device_1103_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0009, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8401 = { + 0x8401, pci_device_1105_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8470 = { + 0x8470, pci_device_1105_8470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8471 = { + 0x8471, pci_device_1105_8471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8475 = { + 0x8475, pci_device_1105_8475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8476 = { + 0x8476, pci_device_1105_8476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8485 = { + 0x8485, pci_device_1105_8485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8486 = { + 0x8486, pci_device_1105_8486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8486, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0204 = { + 0x0204, pci_device_1106_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0238 = { + 0x0238, pci_device_1106_0238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0259 = { + 0x0259, pci_device_1106_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0269 = { + 0x0269, pci_device_1106_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0282 = { + 0x0282, pci_device_1106_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0290 = { + 0x0290, pci_device_1106_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0296 = { + 0x0296, pci_device_1106_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0308 = { + 0x0308, pci_device_1106_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0314 = { + 0x0314, pci_device_1106_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0591 = { + 0x0591, pci_device_1106_0591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1204 = { + 0x1204, pci_device_1106_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1208 = { + 0x1208, pci_device_1106_1208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1238 = { + 0x1238, pci_device_1106_1238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1258 = { + 0x1258, pci_device_1106_1258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1259 = { + 0x1259, pci_device_1106_1259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1269 = { + 0x1269, pci_device_1106_1269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1282 = { + 0x1282, pci_device_1106_1282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1290 = { + 0x1290, pci_device_1106_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1296 = { + 0x1296, pci_device_1106_1296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1308 = { + 0x1308, pci_device_1106_1308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1314 = { + 0x1314, pci_device_1106_1314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2204 = { + 0x2204, pci_device_1106_2204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2208 = { + 0x2208, pci_device_1106_2208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2238 = { + 0x2238, pci_device_1106_2238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2258 = { + 0x2258, pci_device_1106_2258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2259 = { + 0x2259, pci_device_1106_2259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2269 = { + 0x2269, pci_device_1106_2269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2282 = { + 0x2282, pci_device_1106_2282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2290 = { + 0x2290, pci_device_1106_2290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2296 = { + 0x2296, pci_device_1106_2296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2308 = { + 0x2308, pci_device_1106_2308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2314 = { + 0x2314, pci_device_1106_2314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287a = { + 0x287a, pci_device_1106_287a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287b = { + 0x287b, pci_device_1106_287b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287c = { + 0x287c, pci_device_1106_287c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287d = { + 0x287d, pci_device_1106_287d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287e = { + 0x287e, pci_device_1106_287e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3022 = { + 0x3022, pci_device_1106_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3053 = { + 0x3053, pci_device_1106_3053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3108 = { + 0x3108, pci_device_1106_3108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3113 = { + 0x3113, pci_device_1106_3113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3118 = { + 0x3118, pci_device_1106_3118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3119 = { + 0x3119, pci_device_1106_3119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3149 = { + 0x3149, pci_device_1106_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3164 = { + 0x3164, pci_device_1106_3164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3178 = { + 0x3178, pci_device_1106_3178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3188 = { + 0x3188, pci_device_1106_3188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3204 = { + 0x3204, pci_device_1106_3204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3205 = { + 0x3205, pci_device_1106_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3208 = { + 0x3208, pci_device_1106_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3213 = { + 0x3213, pci_device_1106_3213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3218 = { + 0x3218, pci_device_1106_3218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3227 = { + 0x3227, pci_device_1106_3227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3238 = { + 0x3238, pci_device_1106_3238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3249 = { + 0x3249, pci_device_1106_3249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3258 = { + 0x3258, pci_device_1106_3258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3259 = { + 0x3259, pci_device_1106_3259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3269 = { + 0x3269, pci_device_1106_3269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3282 = { + 0x3282, pci_device_1106_3282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3287 = { + 0x3287, pci_device_1106_3287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3288 = { + 0x3288, pci_device_1106_3288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3290 = { + 0x3290, pci_device_1106_3290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3296 = { + 0x3296, pci_device_1106_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3337 = { + 0x3337, pci_device_1106_3337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3344 = { + 0x3344, pci_device_1106_3344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3349 = { + 0x3349, pci_device_1106_3349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337a = { + 0x337a, pci_device_1106_337a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337b = { + 0x337b, pci_device_1106_337b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4149 = { + 0x4149, pci_device_1106_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4204 = { + 0x4204, pci_device_1106_4204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4208 = { + 0x4208, pci_device_1106_4208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4238 = { + 0x4238, pci_device_1106_4238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4258 = { + 0x4258, pci_device_1106_4258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4259 = { + 0x4259, pci_device_1106_4259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4269 = { + 0x4269, pci_device_1106_4269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4282 = { + 0x4282, pci_device_1106_4282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4290 = { + 0x4290, pci_device_1106_4290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4296 = { + 0x4296, pci_device_1106_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4308 = { + 0x4308, pci_device_1106_4308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4314 = { + 0x4314, pci_device_1106_4314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5208 = { + 0x5208, pci_device_1106_5208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5238 = { + 0x5238, pci_device_1106_5238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5290 = { + 0x5290, pci_device_1106_5290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5308 = { + 0x5308, pci_device_1106_5308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7204 = { + 0x7204, pci_device_1106_7204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7205 = { + 0x7205, pci_device_1106_7205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7208 = { + 0x7208, pci_device_1106_7208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7238 = { + 0x7238, pci_device_1106_7238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7258 = { + 0x7258, pci_device_1106_7258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7259 = { + 0x7259, pci_device_1106_7259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7269 = { + 0x7269, pci_device_1106_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7282 = { + 0x7282, pci_device_1106_7282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7290 = { + 0x7290, pci_device_1106_7290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7296 = { + 0x7296, pci_device_1106_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7308 = { + 0x7308, pci_device_1106_7308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7314 = { + 0x7314, pci_device_1106_7314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a208 = { + 0xa208, pci_device_1106_a208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a238 = { + 0xa238, pci_device_1106_a238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b113 = { + 0xb113, pci_device_1106_b113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b115 = { + 0xb115, pci_device_1106_b115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b188 = { + 0xb188, pci_device_1106_b188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b198 = { + 0xb198, pci_device_1106_b198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b213 = { + 0xb213, pci_device_1106_b213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c208 = { + 0xc208, pci_device_1106_c208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c238 = { + 0xc238, pci_device_1106_c238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d104 = { + 0xd104, pci_device_1106_d104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d208 = { + 0xd208, pci_device_1106_d208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d213 = { + 0xd213, pci_device_1106_d213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d238 = { + 0xd238, pci_device_1106_d238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e208 = { + 0xe208, pci_device_1106_e208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e238 = { + 0xe238, pci_device_1106_e238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f208 = { + 0xf208, pci_device_1106_f208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f238 = { + 0xf238, pci_device_1106_f238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f238, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0006 = { + 0x0006, pci_device_110a_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0015 = { + 0x0015, pci_device_110a_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_001d = { + 0x001d, pci_device_110a_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007b = { + 0x007b, pci_device_110a_007b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007c = { + 0x007c, pci_device_110a_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007d = { + 0x007d, pci_device_110a_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2101 = { + 0x2101, pci_device_110a_2101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2104 = { + 0x2104, pci_device_110a_2104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_3142 = { + 0x3142, pci_device_110a_3142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_3142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4021 = { + 0x4021, pci_device_110a_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4029 = { + 0x4029, pci_device_110a_4029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_d301 = { + 0xd301, pci_device_1113_d301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_d301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_ec02 = { + 0xec02, pci_device_1113_ec02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_ec02, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1114_0506 = { + 0x0506, pci_device_1114_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1114_0506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0010 = { + 0x0010, pci_device_1119_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0011 = { + 0x0011, pci_device_1119_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0012 = { + 0x0012, pci_device_1119_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0013 = { + 0x0013, pci_device_1119_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_02ff = { + 0x02ff, pci_device_1119_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_1203 = { + 0x1203, pci_device_111a_1203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_1203, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0004 = { + 0x0004, pci_device_111d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0005 = { + 0x0005, pci_device_111d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0008 = { + 0x0008, pci_device_112f_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5400 = { + 0x5400, pci_device_1131_5400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5402 = { + 0x5402, pci_device_1131_5402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5405 = { + 0x5405, pci_device_1131_5405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5406 = { + 0x5406, pci_device_1131_5406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_9730 = { + 0x9730, pci_device_1131_9730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_9730, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e006 = { + 0xe006, pci_device_1133_e006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e007 = { + 0xe007, pci_device_1133_e007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e008 = { + 0xe008, pci_device_1133_e008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e009 = { + 0xe009, pci_device_1133_e009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00a = { + 0xe00a, pci_device_1133_e00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00c = { + 0xe00c, pci_device_1133_e00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00d = { + 0xe00d, pci_device_1133_e00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00e = { + 0xe00e, pci_device_1133_e00e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e011 = { + 0xe011, pci_device_1133_e011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e013 = { + 0xe013, pci_device_1133_e013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e015 = { + 0xe015, pci_device_1133_e015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e016 = { + 0xe016, pci_device_1133_e016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e017 = { + 0xe017, pci_device_1133_e017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e019 = { + 0xe019, pci_device_1133_e019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01a = { + 0xe01a, pci_device_1133_e01a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01b = { + 0xe01b, pci_device_1133_e01b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01c = { + 0xe01c, pci_device_1133_e01c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01e = { + 0xe01e, pci_device_1133_e01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e020 = { + 0xe020, pci_device_1133_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e024 = { + 0xe024, pci_device_1133_e024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e028 = { + 0xe028, pci_device_1133_e028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02a = { + 0xe02a, pci_device_1133_e02a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02c = { + 0xe02c, pci_device_1133_e02c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1134_0002 = { + 0x0002, pci_device_1134_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f020 = { + 0xf020, pci_device_1145_f020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4500 = { + 0x4500, pci_device_1148_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9000 = { + 0x9000, pci_device_1148_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9843 = { + 0x9843, pci_device_1148_9843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9e00 = { + 0x9e00, pci_device_1148_9e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9e00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0028 = { + 0x0028, pci_device_114f_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0029 = { + 0x0029, pci_device_114f_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0043 = { + 0x0043, pci_device_114f_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0044 = { + 0x0044, pci_device_114f_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0045 = { + 0x0045, pci_device_114f_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_004e = { + 0x004e, pci_device_114f_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b0 = { + 0x00b0, pci_device_114f_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b1 = { + 0x00b1, pci_device_114f_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c8 = { + 0x00c8, pci_device_114f_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c9 = { + 0x00c9, pci_device_114f_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00ca = { + 0x00ca, pci_device_114f_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00cb = { + 0x00cb, pci_device_114f_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d0 = { + 0x00d0, pci_device_114f_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d1 = { + 0x00d1, pci_device_114f_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_00d4 = { + 0x00d4, pci_device_115d_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0000 = { + 0x0000, pci_device_1166_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0006 = { + 0x0006, pci_device_1166_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0036 = { + 0x0036, pci_device_1166_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0101 = { + 0x0101, pci_device_1166_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0104 = { + 0x0104, pci_device_1166_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0110 = { + 0x0110, pci_device_1166_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0130 = { + 0x0130, pci_device_1166_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0132 = { + 0x0132, pci_device_1166_0132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0205 = { + 0x0205, pci_device_1166_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0214 = { + 0x0214, pci_device_1166_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0217 = { + 0x0217, pci_device_1166_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0223 = { + 0x0223, pci_device_1166_0223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0230 = { + 0x0230, pci_device_1166_0230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0234 = { + 0x0234, pci_device_1166_0234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0240 = { + 0x0240, pci_device_1166_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0241 = { + 0x0241, pci_device_1166_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0242 = { + 0x0242, pci_device_1166_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024a = { + 0x024a, pci_device_1166_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0102 = { + 0x0102, pci_device_1179_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_117c_0030 = { + 0x0030, pci_device_117c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_117c_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0511 = { + 0x0511, pci_device_1180_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0554 = { + 0x0554, pci_device_1180_0554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0575 = { + 0x0575, pci_device_1180_0575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0576 = { + 0x0576, pci_device_1180_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0592 = { + 0x0592, pci_device_1180_0592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0811 = { + 0x0811, pci_device_1180_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0822 = { + 0x0822, pci_device_1180_0822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0841 = { + 0x0841, pci_device_1180_0841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0852 = { + 0x0852, pci_device_1180_0852, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0852, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1025 = { + 0x1025, pci_device_1186_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1026 = { + 0x1026, pci_device_1186_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1043 = { + 0x1043, pci_device_1186_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1541 = { + 0x1541, pci_device_1186_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_2027 = { + 0x2027, pci_device_1186_2027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_2027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3203 = { + 0x3203, pci_device_1186_3203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3300 = { + 0x3300, pci_device_1186_3300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a03 = { + 0x3a03, pci_device_1186_3a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a04 = { + 0x3a04, pci_device_1186_3a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a05 = { + 0x3a05, pci_device_1186_3a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a07 = { + 0x3a07, pci_device_1186_3a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a08 = { + 0x3a08, pci_device_1186_3a08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a10 = { + 0x3a10, pci_device_1186_3a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a11 = { + 0x3a11, pci_device_1186_3a11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a12 = { + 0x3a12, pci_device_1186_3a12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a13 = { + 0x3a13, pci_device_1186_3a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a14 = { + 0x3a14, pci_device_1186_3a14, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a14, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a63 = { + 0x3a63, pci_device_1186_3a63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4300 = { + 0x4300, pci_device_1186_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4c00 = { + 0x4c00, pci_device_1186_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_8400 = { + 0x8400, pci_device_1186_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_8400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8060 = { + 0x8060, pci_device_1191_8060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8080 = { + 0x8080, pci_device_1191_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8081 = { + 0x8081, pci_device_1191_8081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_808a = { + 0x808a, pci_device_1191_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_808a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1197_010c = { + 0x010c, pci_device_1197_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1197_010c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_138f = { + 0x138f, pci_device_11ab_138f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_138f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa6 = { + 0x1fa6, pci_device_11ab_1fa6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa7 = { + 0x1fa7, pci_device_11ab_1fa7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1faa = { + 0x1faa, pci_device_11ab_1faa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1faa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4320 = { + 0x4320, pci_device_11ab_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4340 = { + 0x4340, pci_device_11ab_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4341 = { + 0x4341, pci_device_11ab_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4342 = { + 0x4342, pci_device_11ab_4342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4343 = { + 0x4343, pci_device_11ab_4343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4344 = { + 0x4344, pci_device_11ab_4344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4345 = { + 0x4345, pci_device_11ab_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4346 = { + 0x4346, pci_device_11ab_4346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4347 = { + 0x4347, pci_device_11ab_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4350 = { + 0x4350, pci_device_11ab_4350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4351 = { + 0x4351, pci_device_11ab_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4352 = { + 0x4352, pci_device_11ab_4352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4360 = { + 0x4360, pci_device_11ab_4360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4361 = { + 0x4361, pci_device_11ab_4361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4362 = { + 0x4362, pci_device_11ab_4362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4363 = { + 0x4363, pci_device_11ab_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5005 = { + 0x5005, pci_device_11ab_5005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5040 = { + 0x5040, pci_device_11ab_5040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5041 = { + 0x5041, pci_device_11ab_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5080 = { + 0x5080, pci_device_11ab_5080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5081 = { + 0x5081, pci_device_11ab_5081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6041 = { + 0x6041, pci_device_11ab_6041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6081 = { + 0x6081, pci_device_11ab_6081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6460 = { + 0x6460, pci_device_11ab_6460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6480 = { + 0x6480, pci_device_11ab_6480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11af_0001 = { + 0x0001, pci_device_11af_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11af_ee40 = { + 0xee40, pci_device_11af_ee40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_ee40, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bd_002e = { + 0x002e, pci_device_11bd_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11bd_bede = { + 0xbede, pci_device_11bd_bede, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_bede, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048c = { + 0x048c, pci_device_11c1_048c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048f = { + 0x048f, pci_device_11c1_048f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_8110 = { + 0x8110, pci_device_11c1_8110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_8110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab10 = { + 0xab10, pci_device_11c1_ab10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab11 = { + 0xab11, pci_device_11c1_ab11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab20 = { + 0xab20, pci_device_11c1_ab20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab21 = { + 0xab21, pci_device_11c1_ab21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab30 = { + 0xab30, pci_device_11c1_ab30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ed00 = { + 0xed00, pci_device_11c1_ed00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ed00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1535 = { + 0x1535, pci_device_11d4_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_5340 = { + 0x5340, pci_device_11d4_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_5340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_0001 = { + 0x0001, pci_device_11e3_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000d = { + 0x000d, pci_device_11fe_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000e = { + 0x000e, pci_device_11fe_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000f = { + 0x000f, pci_device_11fe_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0801 = { + 0x0801, pci_device_11fe_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0802 = { + 0x0802, pci_device_11fe_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0803 = { + 0x0803, pci_device_11fe_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0805 = { + 0x0805, pci_device_11fe_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080c = { + 0x080c, pci_device_11fe_080c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080d = { + 0x080d, pci_device_11fe_080d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0812 = { + 0x0812, pci_device_11fe_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0903 = { + 0x0903, pci_device_11fe_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ff_0003 = { + 0x0003, pci_device_11ff_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ff_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7110 = { + 0x7110, pci_device_1217_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7112 = { + 0x7112, pci_device_1217_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7113 = { + 0x7113, pci_device_1217_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7114 = { + 0x7114, pci_device_1217_7114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7134 = { + 0x7134, pci_device_1217_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_71e2 = { + 0x71e2, pci_device_1217_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7212 = { + 0x7212, pci_device_1217_7212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7213 = { + 0x7213, pci_device_1217_7213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7223 = { + 0x7223, pci_device_1217_7223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7233 = { + 0x7233, pci_device_1217_7233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7233, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1227_0006 = { + 0x0006, pci_device_1227_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1227_0023 = { + 0x0023, pci_device_1227_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_1400 = { + 0x1400, pci_device_122d_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_6562 = { + 0x6562, pci_device_1242_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_656a = { + 0x656a, pci_device_1242_656a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_656a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2700 = { + 0x2700, pci_device_1244_2700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2900 = { + 0x2900, pci_device_1244_2900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2900, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a117 = { + 0xa117, pci_device_1259_a117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a117, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a120 = { + 0xa120, pci_device_1259_a120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0101 = { + 0x0101, pci_device_125c_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3872 = { + 0x3872, pci_device_1260_3872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3886 = { + 0x3886, pci_device_1260_3886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3890 = { + 0x3890, pci_device_1260_3890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_ffff = { + 0xffff, pci_device_1260_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_126c_1211 = { + 0x1211, pci_device_126c_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126c_126c = { + 0x126c, pci_device_126c_126c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_126c, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0501 = { + 0x0501, pci_device_126f_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0510 = { + 0x0510, pci_device_126f_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0730 = { + 0x0730, pci_device_126f_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1171 = { + 0x1171, pci_device_1274_1171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1278_0710 = { + 0x0710, pci_device_1278_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0710, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0060 = { + 0x0060, pci_device_1279_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0061 = { + 0x0061, pci_device_1279_0061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8211 = { + 0x8211, pci_device_1283_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8212 = { + 0x8212, pci_device_1283_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8872 = { + 0x8872, pci_device_1283_8872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12a3_8105 = { + 0x8105, pci_device_12a3_8105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12a3_8105, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_0002 = { + 0x0002, pci_device_12ab_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_00fa = { + 0x00fa, pci_device_12ae_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_00fa, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c4_0001 = { + 0x0001, pci_device_12c4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0002 = { + 0x0002, pci_device_12c4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0003 = { + 0x0003, pci_device_12c4_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0004 = { + 0x0004, pci_device_12c4_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0005 = { + 0x0005, pci_device_12c4_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0006 = { + 0x0006, pci_device_12c4_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0007 = { + 0x0007, pci_device_12c4_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0008 = { + 0x0008, pci_device_12c4_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0009 = { + 0x0009, pci_device_12c4_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000a = { + 0x000a, pci_device_12c4_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000b = { + 0x000b, pci_device_12c4_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000c = { + 0x000c, pci_device_12c4_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000d = { + 0x000d, pci_device_12c4_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0100 = { + 0x0100, pci_device_12c4_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0201 = { + 0x0201, pci_device_12c4_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0202 = { + 0x0202, pci_device_12c4_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0300 = { + 0x0300, pci_device_12c4_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0301 = { + 0x0301, pci_device_12c4_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0302 = { + 0x0302, pci_device_12c4_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0310 = { + 0x0310, pci_device_12c4_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0311 = { + 0x0311, pci_device_12c4_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0312 = { + 0x0312, pci_device_12c4_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0320 = { + 0x0320, pci_device_12c4_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0321 = { + 0x0321, pci_device_12c4_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0322 = { + 0x0322, pci_device_12c4_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0330 = { + 0x0330, pci_device_12c4_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0331 = { + 0x0331, pci_device_12c4_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0332 = { + 0x0332, pci_device_12c4_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0332, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d4_0200 = { + 0x0200, pci_device_12d4_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d4_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d5_0003 = { + 0x0003, pci_device_12d5_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d5_1000 = { + 0x1000, pci_device_12d5_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_1000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d8_8150 = { + 0x8150, pci_device_12d8_8150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d8_8150, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d9_0002 = { + 0x0002, pci_device_12d9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0004 = { + 0x0004, pci_device_12d9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0005 = { + 0x0005, pci_device_12d9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12de_0200 = { + 0x0200, pci_device_12de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12de_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12fb_0001 = { + 0x0001, pci_device_12fb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_00f5 = { + 0x00f5, pci_device_12fb_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_02ad = { + 0x02ad, pci_device_12fb_02ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_02ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_2adc = { + 0x2adc, pci_device_12fb_2adc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_2adc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3100 = { + 0x3100, pci_device_12fb_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3500 = { + 0x3500, pci_device_12fb_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_4d4f = { + 0x4d4f, pci_device_12fb_4d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_4d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_8120 = { + 0x8120, pci_device_12fb_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_da62 = { + 0xda62, pci_device_12fb_da62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_da62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_db62 = { + 0xdb62, pci_device_12fb_db62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_db62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dc62 = { + 0xdc62, pci_device_12fb_dc62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dc62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dd62 = { + 0xdd62, pci_device_12fb_dd62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dd62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_eddc = { + 0xeddc, pci_device_12fb_eddc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_eddc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_fa01 = { + 0xfa01, pci_device_12fb_fa01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_fa01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004d = { + 0x004d, pci_device_1307_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0052 = { + 0x0052, pci_device_1307_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0054 = { + 0x0054, pci_device_1307_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_005e = { + 0x005e, pci_device_1307_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_005e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_2850 = { + 0x2850, pci_device_1317_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_5120 = { + 0x5120, pci_device_1317_5120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_5120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8201 = { + 0x8201, pci_device_1317_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8211 = { + 0x8211, pci_device_1317_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_9511 = { + 0x9511, pci_device_1317_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2081 = { + 0x2081, pci_device_131f_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2081, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1331_0030 = { + 0x0030, pci_device_1331_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8200 = { + 0x8200, pci_device_1331_8200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8201 = { + 0x8201, pci_device_1331_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8202 = { + 0x8202, pci_device_1331_8202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8210 = { + 0x8210, pci_device_1331_8210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_5425 = { + 0x5425, pci_device_1332_5425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_6140 = { + 0x6140, pci_device_1332_6140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_6140, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_2189 = { + 0x2189, pci_device_134d_2189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_2486 = { + 0x2486, pci_device_134d_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_5101 = { + 0x5101, pci_device_135e_5101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_5101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1360_0101 = { + 0x0101, pci_device_1360_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0102 = { + 0x0102, pci_device_1360_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0103 = { + 0x0103, pci_device_1360_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0201 = { + 0x0201, pci_device_1360_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0202 = { + 0x0202, pci_device_1360_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0203 = { + 0x0203, pci_device_1360_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0301 = { + 0x0301, pci_device_1360_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0302 = { + 0x0302, pci_device_1360_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0302, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136b_ff01 = { + 0xff01, pci_device_136b_ff01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136b_ff01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1371_434e = { + 0x434e, pci_device_1371_434e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1371_434e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1374_0024 = { + 0x0024, pci_device_1374_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0025 = { + 0x0025, pci_device_1374_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0026 = { + 0x0026, pci_device_1374_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0027 = { + 0x0027, pci_device_1374_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0029 = { + 0x0029, pci_device_1374_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002a = { + 0x002a, pci_device_1374_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002b = { + 0x002b, pci_device_1374_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002c = { + 0x002c, pci_device_1374_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002d = { + 0x002d, pci_device_1374_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002e = { + 0x002e, pci_device_1374_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002f = { + 0x002f, pci_device_1374_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0030 = { + 0x0030, pci_device_1374_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0031 = { + 0x0031, pci_device_1374_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0032 = { + 0x0032, pci_device_1374_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0034 = { + 0x0034, pci_device_1374_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0035 = { + 0x0035, pci_device_1374_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0036 = { + 0x0036, pci_device_1374_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0037 = { + 0x0037, pci_device_1374_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0038 = { + 0x0038, pci_device_1374_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0039 = { + 0x0039, pci_device_1374_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_003a = { + 0x003a, pci_device_1374_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_003a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_137a_0001 = { + 0x0001, pci_device_137a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_137a_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1382_0001 = { + 0x0001, pci_device_1382_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2008 = { + 0x2008, pci_device_1382_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2088 = { + 0x2088, pci_device_1382_2088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_20c8 = { + 0x20c8, pci_device_1382_20c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_20c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4008 = { + 0x4008, pci_device_1382_4008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4010 = { + 0x4010, pci_device_1382_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4048 = { + 0x4048, pci_device_1382_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4088 = { + 0x4088, pci_device_1382_4088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4248 = { + 0x4248, pci_device_1382_4248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4424 = { + 0x4424, pci_device_1382_4424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4424, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_0013 = { + 0x0013, pci_device_1385_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_311a = { + 0x311a, pci_device_1385_311a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_311a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4105 = { + 0x4105, pci_device_1385_4105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4400 = { + 0x4400, pci_device_1385_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4600 = { + 0x4600, pci_device_1385_4600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4601 = { + 0x4601, pci_device_1385_4601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4610 = { + 0x4610, pci_device_1385_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4800 = { + 0x4800, pci_device_1385_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4900 = { + 0x4900, pci_device_1385_4900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4a00 = { + 0x4a00, pci_device_1385_4a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4b00 = { + 0x4b00, pci_device_1385_4b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4c00 = { + 0x4c00, pci_device_1385_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4d00 = { + 0x4d00, pci_device_1385_4d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4e00 = { + 0x4e00, pci_device_1385_4e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4f00 = { + 0x4f00, pci_device_1385_4f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_5200 = { + 0x5200, pci_device_1385_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6b00 = { + 0x6b00, pci_device_1385_6b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6d00 = { + 0x6d00, pci_device_1385_6d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f004 = { + 0xf004, pci_device_1385_f004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1141 = { + 0x1141, pci_device_1393_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_16b8 = { + 0x16b8, pci_device_1397_16b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_16b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_001d = { + 0x001d, pci_device_13a3_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0020 = { + 0x0020, pci_device_13a3_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0026 = { + 0x0026, pci_device_13a3_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0026, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0152 = { + 0x0152, pci_device_13a8_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0154 = { + 0x0154, pci_device_13a8_0154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0020 = { + 0x0020, pci_device_13c0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0030 = { + 0x0030, pci_device_13c0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0210 = { + 0x0210, pci_device_13c0_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1003 = { + 0x1003, pci_device_13c1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c6_0520 = { + 0x0520, pci_device_13c6_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0620 = { + 0x0620, pci_device_13c6_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0820 = { + 0x0820, pci_device_13c6_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d0_2200 = { + 0x2200, pci_device_13d0_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab03 = { + 0xab03, pci_device_13d1_ab03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab08 = { + 0xab08, pci_device_13d1_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0200 = { + 0x0200, pci_device_13f0_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_1023 = { + 0x1023, pci_device_13f0_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_1023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0011 = { + 0x0011, pci_device_13f6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1240 = { + 0x1240, pci_device_13fe_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1600 = { + 0x1600, pci_device_13fe_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1733 = { + 0x1733, pci_device_13fe_1733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1752 = { + 0x1752, pci_device_13fe_1752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1754 = { + 0x1754, pci_device_13fe_1754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0110 = { + 0x0110, pci_device_1407_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0111 = { + 0x0111, pci_device_1407_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0120 = { + 0x0120, pci_device_1407_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0121 = { + 0x0121, pci_device_1407_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0180 = { + 0x0180, pci_device_1407_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0181 = { + 0x0181, pci_device_1407_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0220 = { + 0x0220, pci_device_1407_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0221 = { + 0x0221, pci_device_1407_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9510 = { + 0x9510, pci_device_1415_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9523 = { + 0x9523, pci_device_1415_9523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9523, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1420_8002 = { + 0x8002, pci_device_1420_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1420_8003 = { + 0x8003, pci_device_1420_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1425_000b = { + 0x000b, pci_device_1425_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1425_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_142e_4020 = { + 0x4020, pci_device_142e_4020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_142e_4337 = { + 0x4337, pci_device_142e_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4337, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1432_9130 = { + 0x9130, pci_device_1432_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1432_9130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8164 = { + 0x8164, pci_device_144a_8164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1458_0c11 = { + 0x0c11, pci_device_1458_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1458_e911 = { + 0xe911, pci_device_1458_e911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_e911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1461_f436 = { + 0xf436, pci_device_1461_f436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_f436, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1462_5501 = { + 0x5501, pci_device_1462_5501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_5501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6819 = { + 0x6819, pci_device_1462_6819, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6819, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6825 = { + 0x6825, pci_device_1462_6825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6834 = { + 0x6834, pci_device_1462_6834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_8725 = { + 0x8725, pci_device_1462_8725, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_8725, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9000 = { + 0x9000, pci_device_1462_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9110 = { + 0x9110, pci_device_1462_9110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9119 = { + 0x9119, pci_device_1462_9119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9591 = { + 0x9591, pci_device_1462_9591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9591, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_146c_1430 = { + 0x1430, pci_device_146c_1430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_146c_1430, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1497_1497 = { + 0x1497, pci_device_1497_1497, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1497_1497, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1498_0330 = { + 0x0330, pci_device_1498_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_0385 = { + 0x0385, pci_device_1498_0385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_21cd = { + 0x21cd, pci_device_1498_21cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_30c8 = { + 0x30c8, pci_device_1498_30c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_30c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_149d_0001 = { + 0x0001, pci_device_149d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_149d_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a505 = { + 0xa505, pci_device_14b9_a505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a506 = { + 0xa506, pci_device_14b9_a506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14c1_8043 = { + 0x8043, pci_device_14c1_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_8043, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d9_0010 = { + 0x0010, pci_device_14d9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d9_9000 = { + 0x9000, pci_device_14d9_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_9000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14db_2182 = { + 0x2182, pci_device_14db_2182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2182, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_0800 = { + 0x0800, pci_device_14e4_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0804 = { + 0x0804, pci_device_14e4_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0805 = { + 0x0805, pci_device_14e4_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0806 = { + 0x0806, pci_device_14e4_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080b = { + 0x080b, pci_device_14e4_080b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080f = { + 0x080f, pci_device_14e4_080f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0811 = { + 0x0811, pci_device_14e4_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0816 = { + 0x0816, pci_device_14e4_0816, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0816, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1600 = { + 0x1600, pci_device_14e4_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1601 = { + 0x1601, pci_device_14e4_1601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164a = { + 0x164a, pci_device_14e4_164a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164c = { + 0x164c, pci_device_14e4_164c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1654 = { + 0x1654, pci_device_14e4_1654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1659 = { + 0x1659, pci_device_14e4_1659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165e = { + 0x165e, pci_device_14e4_165e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1668 = { + 0x1668, pci_device_14e4_1668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166a = { + 0x166a, pci_device_14e4_166a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166b = { + 0x166b, pci_device_14e4_166b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166e = { + 0x166e, pci_device_14e4_166e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1677 = { + 0x1677, pci_device_14e4_1677, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1677, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1678 = { + 0x1678, pci_device_14e4_1678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167d = { + 0x167d, pci_device_14e4_167d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167e = { + 0x167e, pci_device_14e4_167e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169c = { + 0x169c, pci_device_14e4_169c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169d = { + 0x169d, pci_device_14e4_169d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16aa = { + 0x16aa, pci_device_14e4_16aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16ac = { + 0x16ac, pci_device_14e4_16ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16dd = { + 0x16dd, pci_device_14e4_16dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16f7 = { + 0x16f7, pci_device_14e4_16f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fd = { + 0x16fd, pci_device_14e4_16fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fe = { + 0x16fe, pci_device_14e4_16fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170c = { + 0x170c, pci_device_14e4_170c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170d = { + 0x170d, pci_device_14e4_170d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170e = { + 0x170e, pci_device_14e4_170e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3352 = { + 0x3352, pci_device_14e4_3352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3360 = { + 0x3360, pci_device_14e4_3360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4305 = { + 0x4305, pci_device_14e4_4305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4306 = { + 0x4306, pci_device_14e4_4306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4307 = { + 0x4307, pci_device_14e4_4307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4310 = { + 0x4310, pci_device_14e4_4310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4312 = { + 0x4312, pci_device_14e4_4312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4313 = { + 0x4313, pci_device_14e4_4313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4315 = { + 0x4315, pci_device_14e4_4315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4318 = { + 0x4318, pci_device_14e4_4318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4319 = { + 0x4319, pci_device_14e4_4319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4320 = { + 0x4320, pci_device_14e4_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4321 = { + 0x4321, pci_device_14e4_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4322 = { + 0x4322, pci_device_14e4_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4324 = { + 0x4324, pci_device_14e4_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4325 = { + 0x4325, pci_device_14e4_4325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4326 = { + 0x4326, pci_device_14e4_4326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4403 = { + 0x4403, pci_device_14e4_4403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4430 = { + 0x4430, pci_device_14e4_4430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4432 = { + 0x4432, pci_device_14e4_4432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4610 = { + 0x4610, pci_device_14e4_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4611 = { + 0x4611, pci_device_14e4_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4612 = { + 0x4612, pci_device_14e4_4612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4613 = { + 0x4613, pci_device_14e4_4613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4614 = { + 0x4614, pci_device_14e4_4614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4615 = { + 0x4615, pci_device_14e4_4615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4704 = { + 0x4704, pci_device_14e4_4704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4704, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4705 = { + 0x4705, pci_device_14e4_4705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4705, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4706 = { + 0x4706, pci_device_14e4_4706, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4706, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4707 = { + 0x4707, pci_device_14e4_4707, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4707, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4708 = { + 0x4708, pci_device_14e4_4708, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4708, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4710 = { + 0x4710, pci_device_14e4_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4711 = { + 0x4711, pci_device_14e4_4711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4712 = { + 0x4712, pci_device_14e4_4712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4713 = { + 0x4713, pci_device_14e4_4713, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4713, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4714 = { + 0x4714, pci_device_14e4_4714, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4714, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4715 = { + 0x4715, pci_device_14e4_4715, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4715, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4716 = { + 0x4716, pci_device_14e4_4716, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4716, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4717 = { + 0x4717, pci_device_14e4_4717, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4717, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4718 = { + 0x4718, pci_device_14e4_4718, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4718, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4719 = { + 0x4719, pci_device_14e4_4719, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4719, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4720 = { + 0x4720, pci_device_14e4_4720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5365 = { + 0x5365, pci_device_14e4_5365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5600 = { + 0x5600, pci_device_14e4_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5605 = { + 0x5605, pci_device_14e4_5605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5615 = { + 0x5615, pci_device_14e4_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5625 = { + 0x5625, pci_device_14e4_5625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5645 = { + 0x5645, pci_device_14e4_5645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5670 = { + 0x5670, pci_device_14e4_5670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5680 = { + 0x5680, pci_device_14e4_5680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5690 = { + 0x5690, pci_device_14e4_5690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5691 = { + 0x5691, pci_device_14e4_5691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5692 = { + 0x5692, pci_device_14e4_5692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5822 = { + 0x5822, pci_device_14e4_5822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5823 = { + 0x5823, pci_device_14e4_5823, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5823, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5824 = { + 0x5824, pci_device_14e4_5824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5840 = { + 0x5840, pci_device_14e4_5840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5841 = { + 0x5841, pci_device_14e4_5841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5850 = { + 0x5850, pci_device_14e4_5850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5850, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab07 = { + 0xab07, pci_device_14ea_ab07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab08 = { + 0xab08, pci_device_14ea_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1085 = { + 0x1085, pci_device_14f1_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1620 = { + 0x1620, pci_device_14f1_1620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1621 = { + 0x1621, pci_device_14f1_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1622 = { + 0x1622, pci_device_14f1_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1811 = { + 0x1811, pci_device_14f1_1811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f02 = { + 0x2f02, pci_device_14f1_2f02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f11 = { + 0x2f11, pci_device_14f1_2f11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f20 = { + 0x2f20, pci_device_14f1_2f20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8800 = { + 0x8800, pci_device_14f1_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8801 = { + 0x8801, pci_device_14f1_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8802 = { + 0x8802, pci_device_14f1_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8804 = { + 0x8804, pci_device_14f1_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8811 = { + 0x8811, pci_device_14f1_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f2_0120 = { + 0x0120, pci_device_14f2_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0121 = { + 0x0121, pci_device_14f2_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0122 = { + 0x0122, pci_device_14f2_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0123 = { + 0x0123, pci_device_14f2_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0124 = { + 0x0124, pci_device_14f2_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0124, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f3_2030 = { + 0x2030, pci_device_14f3_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2050 = { + 0x2050, pci_device_14f3_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2060 = { + 0x2060, pci_device_14f3_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2060, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f8_2077 = { + 0x2077, pci_device_14f8_2077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f8_2077, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14fc_0000 = { + 0x0000, pci_device_14fc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0001 = { + 0x0001, pci_device_14fc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1500_1360 = { + 0x1360, pci_device_1500_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1500_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0800 = { + 0x0800, pci_device_1516_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0891 = { + 0x0891, pci_device_1516_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151c_0003 = { + 0x0003, pci_device_151c_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151c_4000 = { + 0x4000, pci_device_151c_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_0510 = { + 0x0510, pci_device_1524_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0520 = { + 0x0520, pci_device_1524_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0530 = { + 0x0530, pci_device_1524_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0550 = { + 0x0550, pci_device_1524_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0610 = { + 0x0610, pci_device_1524_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1411 = { + 0x1411, pci_device_1524_1411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1412 = { + 0x1412, pci_device_1524_1412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1421 = { + 0x1421, pci_device_1524_1421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1422 = { + 0x1422, pci_device_1524_1422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1422, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1532_0020 = { + 0x0020, pci_device_1532_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1532_0020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1538_0303 = { + 0x0303, pci_device_1538_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1538_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153b_1144 = { + 0x1144, pci_device_153b_1144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1147 = { + 0x1147, pci_device_153b_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1158 = { + 0x1158, pci_device_153b_1158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153f_0001 = { + 0x0001, pci_device_153f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1578_5615 = { + 0x5615, pci_device_1578_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1578_5615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0405 = { + 0x0405, pci_device_15ad_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0720 = { + 0x0720, pci_device_15ad_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0720, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a44 = { + 0x5a44, pci_device_15b3_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a45 = { + 0x5a45, pci_device_15b3_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a46 = { + 0x5a46, pci_device_15b3_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5e8d = { + 0x5e8d, pci_device_15b3_5e8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5e8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6274 = { + 0x6274, pci_device_15b3_6274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6278 = { + 0x6278, pci_device_15b3_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6279 = { + 0x6279, pci_device_15b3_6279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6282 = { + 0x6282, pci_device_15b3_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_1100 = { + 0x1100, pci_device_15bc_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2922 = { + 0x2922, pci_device_15bc_2922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2928 = { + 0x2928, pci_device_15bc_2928, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2928, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c5_8010 = { + 0x8010, pci_device_15c5_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c5_8010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e9_1841 = { + 0x1841, pci_device_15e9_1841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e9_1841, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15ec_3101 = { + 0x3101, pci_device_15ec_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ec_5102 = { + 0x5102, pci_device_15ec_5102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_5102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0610 = { + 0x0610, pci_device_1619_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0620 = { + 0x0620, pci_device_1619_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0640 = { + 0x0640, pci_device_1619_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_1610 = { + 0x1610, pci_device_1619_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_2610 = { + 0x2610, pci_device_1619_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_2610, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1626_8410 = { + 0x8410, pci_device_1626_8410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1626_8410, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1637_3874 = { + 0x3874, pci_device_1637_3874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1637_3874, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_3052 = { + 0x3052, pci_device_163c_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165f_1020 = { + 0x1020, pci_device_165f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165f_1020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1668_0100 = { + 0x0100, pci_device_1668_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1668_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_166d_0001 = { + 0x0001, pci_device_166d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_166d_0002 = { + 0x0002, pci_device_166d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1677_104e = { + 0x104e, pci_device_1677_104e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_104e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_12d7 = { + 0x12d7, pci_device_1677_12d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_12d7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167b_2102 = { + 0x2102, pci_device_167b_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167b_2102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1681_0010 = { + 0x0010, pci_device_1681_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1681_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1688_1170 = { + 0x1170, pci_device_1688_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1688_1170, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_168c_0007 = { + 0x0007, pci_device_168c_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0011 = { + 0x0011, pci_device_168c_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0012 = { + 0x0012, pci_device_168c_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0013 = { + 0x0013, pci_device_168c_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001a = { + 0x001a, pci_device_168c_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001b = { + 0x001b, pci_device_168c_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0020 = { + 0x0020, pci_device_168c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_1014 = { + 0x1014, pci_device_168c_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_1014, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_169c_0044 = { + 0x0044, pci_device_169c_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_169c_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1100 = { + 0x1100, pci_device_16ab_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1101 = { + 0x1101, pci_device_16ab_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_8501 = { + 0x8501, pci_device_16ab_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_8501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ae_1141 = { + 0x1141, pci_device_16ae_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ae_1141, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ca_0001 = { + 0x0001, pci_device_16ca_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ca_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e3_1e0f = { + 0x1e0f, pci_device_16e3_1e0f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e3_1e0f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_00ff = { + 0x00ff, pci_device_16ec_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_0116 = { + 0x0116, pci_device_16ec_0116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_0116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ed_1001 = { + 0x1001, pci_device_16ed_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ed_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16f4_8000 = { + 0x8000, pci_device_16f4_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16f4_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_170b_0100 = { + 0x0100, pci_device_170b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_170b_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1725_7174 = { + 0x7174, pci_device_1725_7174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1725_7174, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_172a_13c8 = { + 0x13c8, pci_device_172a_13c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_172a_13c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1737_0013 = { + 0x0013, pci_device_1737_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_0015 = { + 0x0015, pci_device_1737_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1032 = { + 0x1032, pci_device_1737_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1064 = { + 0x1064, pci_device_1737_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab08 = { + 0xab08, pci_device_1737_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab09 = { + 0xab09, pci_device_1737_ab09, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab09, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03e9 = { + 0x03e9, pci_device_173b_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03eb = { + 0x03eb, pci_device_173b_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03eb, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1799_6001 = { + 0x6001, pci_device_1799_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6020 = { + 0x6020, pci_device_1799_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6060 = { + 0x6060, pci_device_1799_6060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7000 = { + 0x7000, pci_device_1799_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7010 = { + 0x7010, pci_device_1799_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_179c_0557 = { + 0x0557, pci_device_179c_0557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_0566 = { + 0x0566, pci_device_179c_0566, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0566, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5031 = { + 0x5031, pci_device_179c_5031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5121 = { + 0x5121, pci_device_179c_5121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5211 = { + 0x5211, pci_device_179c_5211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5679 = { + 0x5679, pci_device_179c_5679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5679, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17a0_8033 = { + 0x8033, pci_device_17a0_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17a0_8034 = { + 0x8034, pci_device_17a0_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8034, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b3_ab08 = { + 0xab08, pci_device_17b3_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b3_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b4_0011 = { + 0x0011, pci_device_17b4_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b4_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d3_1110 = { + 0x1110, pci_device_17d3_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1120 = { + 0x1120, pci_device_17d3_1120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1130 = { + 0x1130, pci_device_17d3_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1160 = { + 0x1160, pci_device_17d3_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1210 = { + 0x1210, pci_device_17d3_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1220 = { + 0x1220, pci_device_17d3_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1230 = { + 0x1230, pci_device_17d3_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1260 = { + 0x1260, pci_device_17d3_1260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1260, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d5_5831 = { + 0x5831, pci_device_17d5_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d5_5832 = { + 0x5832, pci_device_17d5_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5832, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17fe_2120 = { + 0x2120, pci_device_17fe_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17fe_2220 = { + 0x2220, pci_device_17fe_2220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1814_0101 = { + 0x0101, pci_device_1814_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0200 = { + 0x0200, pci_device_1814_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0201 = { + 0x0201, pci_device_1814_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0301 = { + 0x0301, pci_device_1814_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0401 = { + 0x0401, pci_device_1814_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1822_4e35 = { + 0x4e35, pci_device_1822_4e35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1822_4e35, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182d_3069 = { + 0x3069, pci_device_182d_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_3069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_182d_9790 = { + 0x9790, pci_device_182d_9790, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_9790, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_183b_08a7 = { + 0x08a7, pci_device_183b_08a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a8 = { + 0x08a8, pci_device_183b_08a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a9 = { + 0x08a9, pci_device_183b_08a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a9, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1864_2110 = { + 0x2110, pci_device_1864_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1864_2110, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1867_5a44 = { + 0x5a44, pci_device_1867_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a45 = { + 0x5a45, pci_device_1867_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a46 = { + 0x5a46, pci_device_1867_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6278 = { + 0x6278, pci_device_1867_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6282 = { + 0x6282, pci_device_1867_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ac_d500 = { + 0xd500, pci_device_18ac_d500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d810 = { + 0xd810, pci_device_18ac_d810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d820 = { + 0xd820, pci_device_18ac_d820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18b8_b001 = { + 0xb001, pci_device_18b8_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18b8_b001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ca_0020 = { + 0x0020, pci_device_18ca_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ca_0040 = { + 0x0040, pci_device_18ca_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18d2_3069 = { + 0x3069, pci_device_18d2_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18d2_3069, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18dd_4c6f = { + 0x4c6f, pci_device_18dd_4c6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18dd_4c6f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18e6_0001 = { + 0x0001, pci_device_18e6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18e6_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ec_c006 = { + 0xc006, pci_device_18ec_c006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c045 = { + 0xc045, pci_device_18ec_c045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c050 = { + 0xc050, pci_device_18ec_c050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c058 = { + 0xc058, pci_device_18ec_c058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c058, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f7_0001 = { + 0x0001, pci_device_18f7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0002 = { + 0x0002, pci_device_18f7_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0004 = { + 0x0004, pci_device_18f7_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0005 = { + 0x0005, pci_device_18f7_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_000a = { + 0x000a, pci_device_18f7_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1923_0100 = { + 0x0100, pci_device_1923_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1942_e511 = { + 0xe511, pci_device_1942_e511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1942_e511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1957_0080 = { + 0x0080, pci_device_1957_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0081 = { + 0x0081, pci_device_1957_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0082 = { + 0x0082, pci_device_1957_0082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0083 = { + 0x0083, pci_device_1957_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0084 = { + 0x0084, pci_device_1957_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0085 = { + 0x0085, pci_device_1957_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0086 = { + 0x0086, pci_device_1957_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0087 = { + 0x0087, pci_device_1957_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0087, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1966_1975 = { + 0x1975, pci_device_1966_1975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1966_1975, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_196a_0101 = { + 0x0101, pci_device_196a_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_196a_0102 = { + 0x0102, pci_device_196a_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_197b_2360 = { + 0x2360, pci_device_197b_2360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2363 = { + 0x2363, pci_device_197b_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2363, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1989_0001 = { + 0x0001, pci_device_1989_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1989_8001 = { + 0x8001, pci_device_1989_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ae_0520 = { + 0x0520, pci_device_19ae_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ae_0520, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc0_0300 = { + 0x0300, pci_device_1fc0_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc0_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc1_000d = { + 0x000d, pci_device_1fc1_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_000d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fce_0001 = { + 0x0001, pci_device_1fce_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fce_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0020 = { + 0x0020, pci_device_3388_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0022 = { + 0x0022, pci_device_3388_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0026 = { + 0x0026, pci_device_3388_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101a = { + 0x101a, pci_device_3388_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101b = { + 0x101b, pci_device_3388_101b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3842_c370 = { + 0xc370, pci_device_3842_c370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3842_c370, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000d = { + 0x000d, pci_device_3d3d_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0011 = { + 0x0011, pci_device_3d3d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0012 = { + 0x0012, pci_device_3d3d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0013 = { + 0x0013, pci_device_3d3d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0020 = { + 0x0020, pci_device_3d3d_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0022 = { + 0x0022, pci_device_3d3d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0024 = { + 0x0024, pci_device_3d3d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a1 = { + 0x07a1, pci_device_3d3d_07a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a2 = { + 0x07a2, pci_device_3d3d_07a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a3 = { + 0x07a3, pci_device_3d3d_07a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4144_0044 = { + 0x0044, pci_device_4144_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4144_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0016 = { + 0x0016, pci_device_4444_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_494f_10e8 = { + 0x10e8, pci_device_494f_10e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_494f_10e8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4c53_0000 = { + 0x0000, pci_device_4c53_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4c53_0001 = { + 0x0001, pci_device_4c53_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5168_0301 = { + 0x0301, pci_device_5168_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_544c_0350 = { + 0x0350, pci_device_544c_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_544c_0350, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5654_3132 = { + 0x3132, pci_device_5654_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5654_3132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0004 = { + 0x0004, pci_device_6666_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0101 = { + 0x0101, pci_device_6666_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_7063_2000 = { + 0x2000, pci_device_7063_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_3000 = { + 0x3000, pci_device_7063_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0309 = { + 0x0309, pci_device_8086_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_030d = { + 0x030d, pci_device_8086_030d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_030d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0326 = { + 0x0326, pci_device_8086_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0327 = { + 0x0327, pci_device_8086_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0329 = { + 0x0329, pci_device_8086_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032a = { + 0x032a, pci_device_8086_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032c = { + 0x032c, pci_device_8086_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0330 = { + 0x0330, pci_device_8086_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0331 = { + 0x0331, pci_device_8086_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0332 = { + 0x0332, pci_device_8086_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0333 = { + 0x0333, pci_device_8086_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0334 = { + 0x0334, pci_device_8086_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0335 = { + 0x0335, pci_device_8086_0335, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0335, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0336 = { + 0x0336, pci_device_8086_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0340 = { + 0x0340, pci_device_8086_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0341 = { + 0x0341, pci_device_8086_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0370 = { + 0x0370, pci_device_8086_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0371 = { + 0x0371, pci_device_8086_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0372 = { + 0x0372, pci_device_8086_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0373 = { + 0x0373, pci_device_8086_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0374 = { + 0x0374, pci_device_8086_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0500 = { + 0x0500, pci_device_8086_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0501 = { + 0x0501, pci_device_8086_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0502 = { + 0x0502, pci_device_8086_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0503 = { + 0x0503, pci_device_8086_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0510 = { + 0x0510, pci_device_8086_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0511 = { + 0x0511, pci_device_8086_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0512 = { + 0x0512, pci_device_8086_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0513 = { + 0x0513, pci_device_8086_0513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0514 = { + 0x0514, pci_device_8086_0514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0515 = { + 0x0515, pci_device_8086_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0516 = { + 0x0516, pci_device_8086_0516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0530 = { + 0x0530, pci_device_8086_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0531 = { + 0x0531, pci_device_8086_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0532 = { + 0x0532, pci_device_8086_0532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0533 = { + 0x0533, pci_device_8086_0533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0534 = { + 0x0534, pci_device_8086_0534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0535 = { + 0x0535, pci_device_8086_0535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0536 = { + 0x0536, pci_device_8086_0536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0537 = { + 0x0537, pci_device_8086_0537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_061f = { + 0x061f, pci_device_8086_061f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_061f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100a = { + 0x100a, pci_device_8086_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1013 = { + 0x1013, pci_device_8086_1013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1014 = { + 0x1014, pci_device_8086_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1016 = { + 0x1016, pci_device_8086_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1017 = { + 0x1017, pci_device_8086_1017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1018 = { + 0x1018, pci_device_8086_1018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1019 = { + 0x1019, pci_device_8086_1019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101a = { + 0x101a, pci_device_8086_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101d = { + 0x101d, pci_device_8086_101d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101e = { + 0x101e, pci_device_8086_101e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1026 = { + 0x1026, pci_device_8086_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1027 = { + 0x1027, pci_device_8086_1027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1028 = { + 0x1028, pci_device_8086_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1043 = { + 0x1043, pci_device_8086_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1048 = { + 0x1048, pci_device_8086_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104b = { + 0x104b, pci_device_8086_104b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1050 = { + 0x1050, pci_device_8086_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1051 = { + 0x1051, pci_device_8086_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1052 = { + 0x1052, pci_device_8086_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1053 = { + 0x1053, pci_device_8086_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105e = { + 0x105e, pci_device_8086_105e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105f = { + 0x105f, pci_device_8086_105f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1060 = { + 0x1060, pci_device_8086_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1064 = { + 0x1064, pci_device_8086_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1065 = { + 0x1065, pci_device_8086_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1066 = { + 0x1066, pci_device_8086_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1067 = { + 0x1067, pci_device_8086_1067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1068 = { + 0x1068, pci_device_8086_1068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1069 = { + 0x1069, pci_device_8086_1069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106a = { + 0x106a, pci_device_8086_106a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106b = { + 0x106b, pci_device_8086_106b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1075 = { + 0x1075, pci_device_8086_1075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1076 = { + 0x1076, pci_device_8086_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1077 = { + 0x1077, pci_device_8086_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1078 = { + 0x1078, pci_device_8086_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1079 = { + 0x1079, pci_device_8086_1079, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1079, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107a = { + 0x107a, pci_device_8086_107a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107b = { + 0x107b, pci_device_8086_107b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107c = { + 0x107c, pci_device_8086_107c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107d = { + 0x107d, pci_device_8086_107d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107e = { + 0x107e, pci_device_8086_107e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107f = { + 0x107f, pci_device_8086_107f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1080 = { + 0x1080, pci_device_8086_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1081 = { + 0x1081, pci_device_8086_1081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1082 = { + 0x1082, pci_device_8086_1082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1083 = { + 0x1083, pci_device_8086_1083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1084 = { + 0x1084, pci_device_8086_1084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1085 = { + 0x1085, pci_device_8086_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1086 = { + 0x1086, pci_device_8086_1086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1087 = { + 0x1087, pci_device_8086_1087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1089 = { + 0x1089, pci_device_8086_1089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108a = { + 0x108a, pci_device_8086_108a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108b = { + 0x108b, pci_device_8086_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108c = { + 0x108c, pci_device_8086_108c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1096 = { + 0x1096, pci_device_8086_1096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1097 = { + 0x1097, pci_device_8086_1097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1098 = { + 0x1098, pci_device_8086_1098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1099 = { + 0x1099, pci_device_8086_1099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109a = { + 0x109a, pci_device_8086_109a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1107 = { + 0x1107, pci_device_8086_1107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123e = { + 0x123e, pci_device_8086_123e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a38 = { + 0x1a38, pci_device_8086_1a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a48 = { + 0x1a48, pci_device_8086_1a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c1 = { + 0x24c1, pci_device_8086_24c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24ca = { + 0x24ca, pci_device_8086_24ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cc = { + 0x24cc, pci_device_8086_24cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d0 = { + 0x24d0, pci_device_8086_24d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d1 = { + 0x24d1, pci_device_8086_24d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d2 = { + 0x24d2, pci_device_8086_24d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d3 = { + 0x24d3, pci_device_8086_24d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d4 = { + 0x24d4, pci_device_8086_24d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d5 = { + 0x24d5, pci_device_8086_24d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d6 = { + 0x24d6, pci_device_8086_24d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d7 = { + 0x24d7, pci_device_8086_24d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24db = { + 0x24db, pci_device_8086_24db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dc = { + 0x24dc, pci_device_8086_24dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dd = { + 0x24dd, pci_device_8086_24dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24de = { + 0x24de, pci_device_8086_24de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24df = { + 0x24df, pci_device_8086_24df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_254c = { + 0x254c, pci_device_8086_254c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_254c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2550 = { + 0x2550, pci_device_8086_2550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2551 = { + 0x2551, pci_device_8086_2551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2552 = { + 0x2552, pci_device_8086_2552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2553 = { + 0x2553, pci_device_8086_2553, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2553, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2554 = { + 0x2554, pci_device_8086_2554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_255d = { + 0x255d, pci_device_8086_255d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_255d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2571 = { + 0x2571, pci_device_8086_2571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2573 = { + 0x2573, pci_device_8086_2573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2576 = { + 0x2576, pci_device_8086_2576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2578 = { + 0x2578, pci_device_8086_2578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2579 = { + 0x2579, pci_device_8086_2579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257b = { + 0x257b, pci_device_8086_257b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257e = { + 0x257e, pci_device_8086_257e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2580 = { + 0x2580, pci_device_8086_2580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2581 = { + 0x2581, pci_device_8086_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2582 = { + 0x2582, pci_device_8086_2582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2584 = { + 0x2584, pci_device_8086_2584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2585 = { + 0x2585, pci_device_8086_2585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2588 = { + 0x2588, pci_device_8086_2588, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2588, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2589 = { + 0x2589, pci_device_8086_2589, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2589, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_258a = { + 0x258a, pci_device_8086_258a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_258a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2590 = { + 0x2590, pci_device_8086_2590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2591 = { + 0x2591, pci_device_8086_2591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2592 = { + 0x2592, pci_device_8086_2592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a1 = { + 0x25a1, pci_device_8086_25a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a2 = { + 0x25a2, pci_device_8086_25a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a3 = { + 0x25a3, pci_device_8086_25a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a4 = { + 0x25a4, pci_device_8086_25a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a6 = { + 0x25a6, pci_device_8086_25a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a7 = { + 0x25a7, pci_device_8086_25a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a9 = { + 0x25a9, pci_device_8086_25a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25aa = { + 0x25aa, pci_device_8086_25aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ab = { + 0x25ab, pci_device_8086_25ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ac = { + 0x25ac, pci_device_8086_25ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ad = { + 0x25ad, pci_device_8086_25ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ae = { + 0x25ae, pci_device_8086_25ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25b0 = { + 0x25b0, pci_device_8086_25b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25c0 = { + 0x25c0, pci_device_8086_25c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d0 = { + 0x25d0, pci_device_8086_25d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d4 = { + 0x25d4, pci_device_8086_25d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d8 = { + 0x25d8, pci_device_8086_25d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e2 = { + 0x25e2, pci_device_8086_25e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e3 = { + 0x25e3, pci_device_8086_25e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e4 = { + 0x25e4, pci_device_8086_25e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e5 = { + 0x25e5, pci_device_8086_25e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e6 = { + 0x25e6, pci_device_8086_25e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e7 = { + 0x25e7, pci_device_8086_25e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e8 = { + 0x25e8, pci_device_8086_25e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f0 = { + 0x25f0, pci_device_8086_25f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f1 = { + 0x25f1, pci_device_8086_25f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f3 = { + 0x25f3, pci_device_8086_25f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f5 = { + 0x25f5, pci_device_8086_25f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f6 = { + 0x25f6, pci_device_8086_25f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f7 = { + 0x25f7, pci_device_8086_25f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f8 = { + 0x25f8, pci_device_8086_25f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f9 = { + 0x25f9, pci_device_8086_25f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25fa = { + 0x25fa, pci_device_8086_25fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2600 = { + 0x2600, pci_device_8086_2600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2601 = { + 0x2601, pci_device_8086_2601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2602 = { + 0x2602, pci_device_8086_2602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2603 = { + 0x2603, pci_device_8086_2603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2604 = { + 0x2604, pci_device_8086_2604, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2604, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2605 = { + 0x2605, pci_device_8086_2605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2606 = { + 0x2606, pci_device_8086_2606, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2606, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2607 = { + 0x2607, pci_device_8086_2607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2608 = { + 0x2608, pci_device_8086_2608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2609 = { + 0x2609, pci_device_8086_2609, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2609, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260a = { + 0x260a, pci_device_8086_260a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260c = { + 0x260c, pci_device_8086_260c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2610 = { + 0x2610, pci_device_8086_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2611 = { + 0x2611, pci_device_8086_2611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2612 = { + 0x2612, pci_device_8086_2612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2613 = { + 0x2613, pci_device_8086_2613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2614 = { + 0x2614, pci_device_8086_2614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2615 = { + 0x2615, pci_device_8086_2615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2617 = { + 0x2617, pci_device_8086_2617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2618 = { + 0x2618, pci_device_8086_2618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2619 = { + 0x2619, pci_device_8086_2619, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2619, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261a = { + 0x261a, pci_device_8086_261a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261b = { + 0x261b, pci_device_8086_261b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261c = { + 0x261c, pci_device_8086_261c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261d = { + 0x261d, pci_device_8086_261d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261e = { + 0x261e, pci_device_8086_261e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2620 = { + 0x2620, pci_device_8086_2620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2621 = { + 0x2621, pci_device_8086_2621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2622 = { + 0x2622, pci_device_8086_2622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2623 = { + 0x2623, pci_device_8086_2623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2624 = { + 0x2624, pci_device_8086_2624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2625 = { + 0x2625, pci_device_8086_2625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2626 = { + 0x2626, pci_device_8086_2626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2627 = { + 0x2627, pci_device_8086_2627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2640 = { + 0x2640, pci_device_8086_2640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2641 = { + 0x2641, pci_device_8086_2641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2642 = { + 0x2642, pci_device_8086_2642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2651 = { + 0x2651, pci_device_8086_2651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2652 = { + 0x2652, pci_device_8086_2652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2653 = { + 0x2653, pci_device_8086_2653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2658 = { + 0x2658, pci_device_8086_2658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2659 = { + 0x2659, pci_device_8086_2659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265a = { + 0x265a, pci_device_8086_265a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265b = { + 0x265b, pci_device_8086_265b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265c = { + 0x265c, pci_device_8086_265c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2660 = { + 0x2660, pci_device_8086_2660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2662 = { + 0x2662, pci_device_8086_2662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2664 = { + 0x2664, pci_device_8086_2664, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2664, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2666 = { + 0x2666, pci_device_8086_2666, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2666, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2668 = { + 0x2668, pci_device_8086_2668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266a = { + 0x266a, pci_device_8086_266a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266c = { + 0x266c, pci_device_8086_266c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266d = { + 0x266d, pci_device_8086_266d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266e = { + 0x266e, pci_device_8086_266e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266f = { + 0x266f, pci_device_8086_266f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2670 = { + 0x2670, pci_device_8086_2670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2680 = { + 0x2680, pci_device_8086_2680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2681 = { + 0x2681, pci_device_8086_2681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2682 = { + 0x2682, pci_device_8086_2682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2683 = { + 0x2683, pci_device_8086_2683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2688 = { + 0x2688, pci_device_8086_2688, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2688, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2689 = { + 0x2689, pci_device_8086_2689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268a = { + 0x268a, pci_device_8086_268a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268b = { + 0x268b, pci_device_8086_268b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268c = { + 0x268c, pci_device_8086_268c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2690 = { + 0x2690, pci_device_8086_2690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2692 = { + 0x2692, pci_device_8086_2692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2694 = { + 0x2694, pci_device_8086_2694, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2694, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2696 = { + 0x2696, pci_device_8086_2696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2698 = { + 0x2698, pci_device_8086_2698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2699 = { + 0x2699, pci_device_8086_2699, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2699, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269a = { + 0x269a, pci_device_8086_269a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269b = { + 0x269b, pci_device_8086_269b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269e = { + 0x269e, pci_device_8086_269e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2770 = { + 0x2770, pci_device_8086_2770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2771 = { + 0x2771, pci_device_8086_2771, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2771, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2772 = { + 0x2772, pci_device_8086_2772, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2772, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2774 = { + 0x2774, pci_device_8086_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2775 = { + 0x2775, pci_device_8086_2775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2776 = { + 0x2776, pci_device_8086_2776, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2776, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2778 = { + 0x2778, pci_device_8086_2778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2779 = { + 0x2779, pci_device_8086_2779, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2779, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277a = { + 0x277a, pci_device_8086_277a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277c = { + 0x277c, pci_device_8086_277c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277d = { + 0x277d, pci_device_8086_277d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2782 = { + 0x2782, pci_device_8086_2782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2792 = { + 0x2792, pci_device_8086_2792, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2792, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a0 = { + 0x27a0, pci_device_8086_27a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a1 = { + 0x27a1, pci_device_8086_27a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a2 = { + 0x27a2, pci_device_8086_27a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a6 = { + 0x27a6, pci_device_8086_27a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b0 = { + 0x27b0, pci_device_8086_27b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b8 = { + 0x27b8, pci_device_8086_27b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b9 = { + 0x27b9, pci_device_8086_27b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27bd = { + 0x27bd, pci_device_8086_27bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c0 = { + 0x27c0, pci_device_8086_27c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c1 = { + 0x27c1, pci_device_8086_27c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c3 = { + 0x27c3, pci_device_8086_27c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c4 = { + 0x27c4, pci_device_8086_27c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c5 = { + 0x27c5, pci_device_8086_27c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c6 = { + 0x27c6, pci_device_8086_27c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c8 = { + 0x27c8, pci_device_8086_27c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c9 = { + 0x27c9, pci_device_8086_27c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27ca = { + 0x27ca, pci_device_8086_27ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cb = { + 0x27cb, pci_device_8086_27cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cc = { + 0x27cc, pci_device_8086_27cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d0 = { + 0x27d0, pci_device_8086_27d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d2 = { + 0x27d2, pci_device_8086_27d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d4 = { + 0x27d4, pci_device_8086_27d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d6 = { + 0x27d6, pci_device_8086_27d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d8 = { + 0x27d8, pci_device_8086_27d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27da = { + 0x27da, pci_device_8086_27da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dc = { + 0x27dc, pci_device_8086_27dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dd = { + 0x27dd, pci_device_8086_27dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27de = { + 0x27de, pci_device_8086_27de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27df = { + 0x27df, pci_device_8086_27df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e0 = { + 0x27e0, pci_device_8086_27e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e2 = { + 0x27e2, pci_device_8086_27e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2810 = { + 0x2810, pci_device_8086_2810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2811 = { + 0x2811, pci_device_8086_2811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2812 = { + 0x2812, pci_device_8086_2812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2814 = { + 0x2814, pci_device_8086_2814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2815 = { + 0x2815, pci_device_8086_2815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2820 = { + 0x2820, pci_device_8086_2820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2821 = { + 0x2821, pci_device_8086_2821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2822 = { + 0x2822, pci_device_8086_2822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2824 = { + 0x2824, pci_device_8086_2824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2825 = { + 0x2825, pci_device_8086_2825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2828 = { + 0x2828, pci_device_8086_2828, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2828, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2829 = { + 0x2829, pci_device_8086_2829, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2829, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_282a = { + 0x282a, pci_device_8086_282a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_282a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2830 = { + 0x2830, pci_device_8086_2830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2831 = { + 0x2831, pci_device_8086_2831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2832 = { + 0x2832, pci_device_8086_2832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2834 = { + 0x2834, pci_device_8086_2834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2835 = { + 0x2835, pci_device_8086_2835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2836 = { + 0x2836, pci_device_8086_2836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283a = { + 0x283a, pci_device_8086_283a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283e = { + 0x283e, pci_device_8086_283e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283f = { + 0x283f, pci_device_8086_283f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2841 = { + 0x2841, pci_device_8086_2841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2843 = { + 0x2843, pci_device_8086_2843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2844 = { + 0x2844, pci_device_8086_2844, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2844, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2847 = { + 0x2847, pci_device_8086_2847, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2847, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2849 = { + 0x2849, pci_device_8086_2849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284b = { + 0x284b, pci_device_8086_284b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284f = { + 0x284f, pci_device_8086_284f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2850 = { + 0x2850, pci_device_8086_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2970 = { + 0x2970, pci_device_8086_2970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2971 = { + 0x2971, pci_device_8086_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2971, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2972 = { + 0x2972, pci_device_8086_2972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2973 = { + 0x2973, pci_device_8086_2973, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2973, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3200 = { + 0x3200, pci_device_8086_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3340 = { + 0x3340, pci_device_8086_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3341 = { + 0x3341, pci_device_8086_3341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3500 = { + 0x3500, pci_device_8086_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3501 = { + 0x3501, pci_device_8086_3501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3504 = { + 0x3504, pci_device_8086_3504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3505 = { + 0x3505, pci_device_8086_3505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350c = { + 0x350c, pci_device_8086_350c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350d = { + 0x350d, pci_device_8086_350d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3510 = { + 0x3510, pci_device_8086_3510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3511 = { + 0x3511, pci_device_8086_3511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3514 = { + 0x3514, pci_device_8086_3514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3515 = { + 0x3515, pci_device_8086_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3518 = { + 0x3518, pci_device_8086_3518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3519 = { + 0x3519, pci_device_8086_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3581 = { + 0x3581, pci_device_8086_3581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3584 = { + 0x3584, pci_device_8086_3584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3585 = { + 0x3585, pci_device_8086_3585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3590 = { + 0x3590, pci_device_8086_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3591 = { + 0x3591, pci_device_8086_3591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3592 = { + 0x3592, pci_device_8086_3592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3593 = { + 0x3593, pci_device_8086_3593, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3593, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3594 = { + 0x3594, pci_device_8086_3594, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3594, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3595 = { + 0x3595, pci_device_8086_3595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3596 = { + 0x3596, pci_device_8086_3596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3597 = { + 0x3597, pci_device_8086_3597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3598 = { + 0x3598, pci_device_8086_3598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3599 = { + 0x3599, pci_device_8086_3599, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3599, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359a = { + 0x359a, pci_device_8086_359a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359b = { + 0x359b, pci_device_8086_359b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359e = { + 0x359e, pci_device_8086_359e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4220 = { + 0x4220, pci_device_8086_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4223 = { + 0x4223, pci_device_8086_4223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4224 = { + 0x4224, pci_device_8086_4224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7050 = { + 0x7050, pci_device_8086_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7051 = { + 0x7051, pci_device_8086_7051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_8500 = { + 0x8500, pci_device_8086_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9000 = { + 0x9000, pci_device_8086_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9001 = { + 0x9001, pci_device_8086_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9004 = { + 0x9004, pci_device_8086_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8c4a_1980 = { + 0x1980, pci_device_8c4a_1980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8c4a_1980, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_0078 = { + 0x0078, pci_device_9004_0078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_0078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7710 = { + 0x7710, pci_device_9004_7710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7711 = { + 0x7711, pci_device_9004_7711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#define pci_dev_list_0070 NULL +#define pci_dev_list_0071 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0095[] = { + &pci_dev_info_0095_0680, + NULL +}; +#endif +#define pci_dev_list_00a7 NULL +#define pci_dev_list_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_018a[] = { + &pci_dev_info_018a_0106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_021b[] = { + &pci_dev_info_021b_8139, + NULL +}; +#endif +#define pci_dev_list_0270 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0291[] = { + &pci_dev_info_0291_8212, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_02ac[] = { + &pci_dev_info_02ac_1012, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0357[] = { + &pci_dev_info_0357_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0432[] = { + &pci_dev_info_0432_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_045e[] = { + &pci_dev_info_045e_006e, + &pci_dev_info_045e_00c2, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_04cf[] = { + &pci_dev_info_04cf_8818, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_050d[] = { + &pci_dev_info_050d_7050, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05e3[] = { + &pci_dev_info_05e3_0701, + NULL +}; +#endif +#define pci_dev_list_066f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + &pci_dev_info_0675_1703, + &pci_dev_info_0675_1704, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_067b[] = { + &pci_dev_info_067b_3507, + NULL +}; +#endif +#define pci_dev_list_0721 NULL +#define pci_dev_list_07e2 NULL +#define pci_dev_list_0925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b49[] = { + &pci_dev_info_0b49_064f, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0046, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_005a, + &pci_dev_info_0e11_007c, + &pci_dev_info_0e11_007d, + &pci_dev_info_0e11_0085, + &pci_dev_info_0e11_00b1, + &pci_dev_info_0e11_00bb, + &pci_dev_info_0e11_00ca, + &pci_dev_info_0e11_00cb, + &pci_dev_info_0e11_00cf, + &pci_dev_info_0e11_00d0, + &pci_dev_info_0e11_00d1, + &pci_dev_info_0e11_00e3, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_4030, + &pci_dev_info_0e11_4031, + &pci_dev_info_0e11_4032, + &pci_dev_info_0e11_4033, + &pci_dev_info_0e11_4034, + &pci_dev_info_0e11_4040, + &pci_dev_info_0e11_4048, + &pci_dev_info_0e11_4050, + &pci_dev_info_0e11_4051, + &pci_dev_info_0e11_4058, + &pci_dev_info_0e11_4070, + &pci_dev_info_0e11_4080, + &pci_dev_info_0e11_4082, + &pci_dev_info_0e11_4083, + &pci_dev_info_0e11_4091, + &pci_dev_info_0e11_409a, + &pci_dev_info_0e11_409b, + &pci_dev_info_0e11_409c, + &pci_dev_info_0e11_409d, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_b200, + &pci_dev_info_0e11_b203, + &pci_dev_info_0e11_b204, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0031, + &pci_dev_info_1000_0032, + &pci_dev_info_1000_0033, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_0041, + &pci_dev_info_1000_0050, + &pci_dev_info_1000_0054, + &pci_dev_info_1000_0056, + &pci_dev_info_1000_0058, + &pci_dev_info_1000_005a, + &pci_dev_info_1000_005c, + &pci_dev_info_1000_005e, + &pci_dev_info_1000_0060, + &pci_dev_info_1000_0062, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0407, + &pci_dev_info_1000_0408, + &pci_dev_info_1000_0409, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0640, + &pci_dev_info_1000_0642, + &pci_dev_info_1000_0646, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0804, + &pci_dev_info_1000_0805, + &pci_dev_info_1000_0806, + &pci_dev_info_1000_0807, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_3150, + &pci_dev_info_1002_3152, + &pci_dev_info_1002_3154, + &pci_dev_info_1002_3e50, + &pci_dev_info_1002_3e54, + &pci_dev_info_1002_3e70, + &pci_dev_info_1002_4136, + &pci_dev_info_1002_4137, + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4148, + &pci_dev_info_1002_4149, + &pci_dev_info_1002_414a, + &pci_dev_info_1002_414b, + &pci_dev_info_1002_4150, + &pci_dev_info_1002_4151, + &pci_dev_info_1002_4152, + &pci_dev_info_1002_4153, + &pci_dev_info_1002_4154, + &pci_dev_info_1002_4155, + &pci_dev_info_1002_4156, + &pci_dev_info_1002_4157, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4164, + &pci_dev_info_1002_4165, + &pci_dev_info_1002_4166, + &pci_dev_info_1002_4168, + &pci_dev_info_1002_4170, + &pci_dev_info_1002_4171, + &pci_dev_info_1002_4172, + &pci_dev_info_1002_4173, + &pci_dev_info_1002_4237, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4243, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4341, + &pci_dev_info_1002_4345, + &pci_dev_info_1002_4347, + &pci_dev_info_1002_4348, + &pci_dev_info_1002_4349, + &pci_dev_info_1002_434d, + &pci_dev_info_1002_4353, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4363, + &pci_dev_info_1002_436e, + &pci_dev_info_1002_4370, + &pci_dev_info_1002_4371, + &pci_dev_info_1002_4372, + &pci_dev_info_1002_4373, + &pci_dev_info_1002_4374, + &pci_dev_info_1002_4375, + &pci_dev_info_1002_4376, + &pci_dev_info_1002_4377, + &pci_dev_info_1002_4378, + &pci_dev_info_1002_4379, + &pci_dev_info_1002_437a, + &pci_dev_info_1002_4437, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4a48, + &pci_dev_info_1002_4a49, + &pci_dev_info_1002_4a4a, + &pci_dev_info_1002_4a4b, + &pci_dev_info_1002_4a4c, + &pci_dev_info_1002_4a4d, + &pci_dev_info_1002_4a4e, + &pci_dev_info_1002_4a50, + &pci_dev_info_1002_4a70, + &pci_dev_info_1002_4b49, + &pci_dev_info_1002_4b4b, + &pci_dev_info_1002_4b4c, + &pci_dev_info_1002_4b69, + &pci_dev_info_1002_4b6b, + &pci_dev_info_1002_4b6c, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4c6e, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e48, + &pci_dev_info_1002_4e49, + &pci_dev_info_1002_4e4a, + &pci_dev_info_1002_4e4b, + &pci_dev_info_1002_4e50, + &pci_dev_info_1002_4e51, + &pci_dev_info_1002_4e52, + &pci_dev_info_1002_4e53, + &pci_dev_info_1002_4e54, + &pci_dev_info_1002_4e56, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_4e68, + &pci_dev_info_1002_4e69, + &pci_dev_info_1002_4e6a, + &pci_dev_info_1002_4e71, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5154, + &pci_dev_info_1002_5155, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_515e, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5460, + &pci_dev_info_1002_5462, + &pci_dev_info_1002_5464, + &pci_dev_info_1002_5548, + &pci_dev_info_1002_5549, + &pci_dev_info_1002_554a, + &pci_dev_info_1002_554b, + &pci_dev_info_1002_554d, + &pci_dev_info_1002_554f, + &pci_dev_info_1002_5550, + &pci_dev_info_1002_5551, + &pci_dev_info_1002_5552, + &pci_dev_info_1002_5554, + &pci_dev_info_1002_556b, + &pci_dev_info_1002_556d, + &pci_dev_info_1002_556f, + &pci_dev_info_1002_564a, + &pci_dev_info_1002_564b, + &pci_dev_info_1002_5652, + &pci_dev_info_1002_5653, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_5830, + &pci_dev_info_1002_5831, + &pci_dev_info_1002_5832, + &pci_dev_info_1002_5833, + &pci_dev_info_1002_5834, + &pci_dev_info_1002_5835, + &pci_dev_info_1002_5838, + &pci_dev_info_1002_5940, + &pci_dev_info_1002_5941, + &pci_dev_info_1002_5944, + &pci_dev_info_1002_5950, + &pci_dev_info_1002_5951, + &pci_dev_info_1002_5954, + &pci_dev_info_1002_5955, + &pci_dev_info_1002_5960, + &pci_dev_info_1002_5961, + &pci_dev_info_1002_5962, + &pci_dev_info_1002_5964, + &pci_dev_info_1002_5969, + &pci_dev_info_1002_5974, + &pci_dev_info_1002_5975, + &pci_dev_info_1002_5a34, + &pci_dev_info_1002_5a38, + &pci_dev_info_1002_5a3f, + &pci_dev_info_1002_5a41, + &pci_dev_info_1002_5a42, + &pci_dev_info_1002_5a61, + &pci_dev_info_1002_5a62, + &pci_dev_info_1002_5b60, + &pci_dev_info_1002_5b62, + &pci_dev_info_1002_5b63, + &pci_dev_info_1002_5b64, + &pci_dev_info_1002_5b65, + &pci_dev_info_1002_5b70, + &pci_dev_info_1002_5b72, + &pci_dev_info_1002_5b73, + &pci_dev_info_1002_5b74, + &pci_dev_info_1002_5c61, + &pci_dev_info_1002_5c63, + &pci_dev_info_1002_5d44, + &pci_dev_info_1002_5d48, + &pci_dev_info_1002_5d49, + &pci_dev_info_1002_5d4a, + &pci_dev_info_1002_5d4d, + &pci_dev_info_1002_5d4f, + &pci_dev_info_1002_5d52, + &pci_dev_info_1002_5d57, + &pci_dev_info_1002_5d6d, + &pci_dev_info_1002_5d6f, + &pci_dev_info_1002_5d72, + &pci_dev_info_1002_5d77, + &pci_dev_info_1002_5e48, + &pci_dev_info_1002_5e49, + &pci_dev_info_1002_5e4a, + &pci_dev_info_1002_5e4b, + &pci_dev_info_1002_5e4c, + &pci_dev_info_1002_5e4d, + &pci_dev_info_1002_5e4f, + &pci_dev_info_1002_5e6b, + &pci_dev_info_1002_5e6d, + &pci_dev_info_1002_700f, + &pci_dev_info_1002_7010, + &pci_dev_info_1002_7100, + &pci_dev_info_1002_7105, + &pci_dev_info_1002_7109, + &pci_dev_info_1002_7120, + &pci_dev_info_1002_7129, + &pci_dev_info_1002_7142, + &pci_dev_info_1002_7146, + &pci_dev_info_1002_7162, + &pci_dev_info_1002_7166, + &pci_dev_info_1002_71c0, + &pci_dev_info_1002_71c2, + &pci_dev_info_1002_71e0, + &pci_dev_info_1002_71e2, + &pci_dev_info_1002_7833, + &pci_dev_info_1002_7834, + &pci_dev_info_1002_7835, + &pci_dev_info_1002_7838, + &pci_dev_info_1002_7c37, + &pci_dev_info_1002_cab0, + &pci_dev_info_1002_cab2, + &pci_dev_info_1002_cab3, + &pci_dev_info_1002_cbb2, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0021, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0028, + &pci_dev_info_100b_002a, + &pci_dev_info_100b_002b, + &pci_dev_info_100b_002d, + &pci_dev_info_100b_002e, + &pci_dev_info_100b_002f, + &pci_dev_info_100b_0030, + &pci_dev_info_100b_0035, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_0510, + &pci_dev_info_100b_0511, + &pci_dev_info_100b_0515, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0017, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4000, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0031, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_0037, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003c, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0054, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_005e, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_008b, + &pci_dev_info_1014_008e, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0091, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_009f, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00b8, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0104, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_015e, + &pci_dev_info_1014_0160, + &pci_dev_info_1014_016e, + &pci_dev_info_1014_0170, + &pci_dev_info_1014_017d, + &pci_dev_info_1014_0180, + &pci_dev_info_1014_0188, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_01c1, + &pci_dev_info_1014_01e6, + &pci_dev_info_1014_01ff, + &pci_dev_info_1014_0219, + &pci_dev_info_1014_021b, + &pci_dev_info_1014_021c, + &pci_dev_info_1014_0233, + &pci_dev_info_1014_0266, + &pci_dev_info_1014_0268, + &pci_dev_info_1014_0269, + &pci_dev_info_1014_028c, + &pci_dev_info_1014_02a1, + &pci_dev_info_1014_02bd, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_0314, + &pci_dev_info_1014_3022, + &pci_dev_info_1014_4022, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_0009, + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2003, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_2081, + &pci_dev_info_1022_2082, + &pci_dev_info_1022_208f, + &pci_dev_info_1022_2090, + &pci_dev_info_1022_2091, + &pci_dev_info_1022_2093, + &pci_dev_info_1022_2094, + &pci_dev_info_1022_2095, + &pci_dev_info_1022_2096, + &pci_dev_info_1022_2097, + &pci_dev_info_1022_209a, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700a, + &pci_dev_info_1022_700b, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7458, + &pci_dev_info_1022_7459, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + &pci_dev_info_1022_756b, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_2100, + &pci_dev_info_1023_2200, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_1671, + &pci_dev_info_1025_1672, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_0009, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000d, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + &pci_dev_info_1028_0010, + &pci_dev_info_1028_0011, + &pci_dev_info_1028_0012, + &pci_dev_info_1028_0013, + &pci_dev_info_1028_0014, + &pci_dev_info_1028_0015, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + &pci_dev_info_102a_001f, + &pci_dev_info_102a_00c5, + &pci_dev_info_102a_00cf, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0100, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0528, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_2537, + &pci_dev_info_102b_2538, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_000a, + &pci_dev_info_102f_0020, + &pci_dev_info_102f_0030, + &pci_dev_info_102f_0031, + &pci_dev_info_102f_0105, + &pci_dev_info_102f_0106, + &pci_dev_info_102f_0107, + &pci_dev_info_102f_0108, + &pci_dev_info_102f_0180, + &pci_dev_info_102f_0181, + &pci_dev_info_102f_0182, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0000, + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0072, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a5, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00ce, + &pci_dev_info_1033_00df, + &pci_dev_info_1033_00e0, + &pci_dev_info_1033_00e7, + &pci_dev_info_1033_00f2, + &pci_dev_info_1033_00f3, + &pci_dev_info_1033_010c, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0003, + &pci_dev_info_1039_0004, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_000a, + &pci_dev_info_1039_0016, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0180, + &pci_dev_info_1039_0181, + &pci_dev_info_1039_0182, + &pci_dev_info_1039_0190, + &pci_dev_info_1039_0191, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0550, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0648, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0655, + &pci_dev_info_1039_0660, + &pci_dev_info_1039_0661, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0741, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0746, + &pci_dev_info_1039_0755, + &pci_dev_info_1039_0760, + &pci_dev_info_1039_0761, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_0963, + &pci_dev_info_1039_0964, + &pci_dev_info_1039_0965, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_6330, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + &pci_dev_info_1039_7019, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1006, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_100a, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1054, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_10f0, + &pci_dev_info_103c_10f1, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_127c, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_1291, + &pci_dev_info_103c_12b4, + &pci_dev_info_103c_12fa, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + &pci_dev_info_103c_3080, + &pci_dev_info_103c_3220, + &pci_dev_info_103c_3230, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_4015, + &pci_dev_info_1043_4021, + &pci_dev_info_1043_4057, + &pci_dev_info_1043_8043, + &pci_dev_info_1043_807b, + &pci_dev_info_1043_80bb, + &pci_dev_info_1043_80c5, + &pci_dev_info_1043_80df, + &pci_dev_info_1043_8187, + &pci_dev_info_1043_8188, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0c60, + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + &pci_dev_info_1048_8901, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0209, + &pci_dev_info_104a_020a, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_021a, + &pci_dev_info_104a_021b, + &pci_dev_info_104a_0500, + &pci_dev_info_104a_0564, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + &pci_dev_info_104a_55cc, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8025, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8029, + &pci_dev_info_104c_802b, + &pci_dev_info_104c_802e, + &pci_dev_info_104c_8031, + &pci_dev_info_104c_8032, + &pci_dev_info_104c_8033, + &pci_dev_info_104c_8034, + &pci_dev_info_104c_8035, + &pci_dev_info_104c_8036, + &pci_dev_info_104c_8038, + &pci_dev_info_104c_8201, + &pci_dev_info_104c_8204, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_8401, + &pci_dev_info_104c_9000, + &pci_dev_info_104c_9065, + &pci_dev_info_104c_9066, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac44, + &pci_dev_info_104c_ac46, + &pci_dev_info_104c_ac47, + &pci_dev_info_104c_ac4a, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac54, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_ac8d, + &pci_dev_info_104c_ac8e, + &pci_dev_info_104c_ac8f, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8004, + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9921, + &pci_dev_info_1050_9922, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0008, + &pci_dev_info_1057_0009, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_18c1, + &pci_dev_info_1057_3410, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_5608, + &pci_dev_info_1057_5803, + &pci_dev_info_1057_5806, + &pci_dev_info_1057_5808, + &pci_dev_info_1057_6400, + &pci_dev_info_1057_6405, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3318, + &pci_dev_info_105a_3319, + &pci_dev_info_105a_3371, + &pci_dev_info_105a_3373, + &pci_dev_info_105a_3375, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_3515, + &pci_dev_info_105a_3519, + &pci_dev_info_105a_3570, + &pci_dev_info_105a_3571, + &pci_dev_info_105a_3574, + &pci_dev_info_105a_3577, + &pci_dev_info_105a_3d17, + &pci_dev_info_105a_3d18, + &pci_dev_info_105a_3d73, + &pci_dev_info_105a_3d75, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_6622, + &pci_dev_info_105a_6624, + &pci_dev_info_105a_6626, + &pci_dev_info_105a_6629, + &pci_dev_info_105a_7275, + &pci_dev_info_105a_8002, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_0301, + &pci_dev_info_1067_0304, + &pci_dev_info_1067_0308, + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0020, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_b166, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + &pci_dev_info_1069_ba57, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000c, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_0035, + &pci_dev_info_106b_0036, + &pci_dev_info_106b_003b, + &pci_dev_info_106b_003e, + &pci_dev_info_106b_003f, + &pci_dev_info_106b_0040, + &pci_dev_info_106b_0041, + &pci_dev_info_106b_0042, + &pci_dev_info_106b_0043, + &pci_dev_info_106b_0045, + &pci_dev_info_106b_0046, + &pci_dev_info_106b_0047, + &pci_dev_info_106b_0048, + &pci_dev_info_106b_0049, + &pci_dev_info_106b_004b, + &pci_dev_info_106b_004c, + &pci_dev_info_106b_004f, + &pci_dev_info_106b_0050, + &pci_dev_info_106b_0051, + &pci_dev_info_106b_0052, + &pci_dev_info_106b_0053, + &pci_dev_info_106b_0054, + &pci_dev_info_106b_0055, + &pci_dev_info_106b_0058, + &pci_dev_info_106b_0059, + &pci_dev_info_106b_0066, + &pci_dev_info_106b_0067, + &pci_dev_info_106b_0068, + &pci_dev_info_106b_0069, + &pci_dev_info_106b_006a, + &pci_dev_info_106b_006b, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1071[] = { + &pci_dev_info_1071_8160, + NULL +}; +#endif +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + &pci_dev_info_1077_2322, + &pci_dev_info_1077_2422, + &pci_dev_info_1077_2432, + &pci_dev_info_1077_3010, + &pci_dev_info_1077_3022, + &pci_dev_info_1077_4010, + &pci_dev_info_1077_4022, + &pci_dev_info_1077_6312, + &pci_dev_info_1077_6322, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + &pci_dev_info_107d_2134, + &pci_dev_info_107d_2971, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_1648, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_8002, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + &pci_dev_info_108e_a801, + &pci_dev_info_108e_abba, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + &pci_dev_info_1091_07a0, + &pci_dev_info_1091_1091, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1310, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_14e0, + &pci_dev_info_1093_14f0, + &pci_dev_info_1093_17d0, + &pci_dev_info_1093_1870, + &pci_dev_info_1093_1880, + &pci_dev_info_1093_18b0, + &pci_dev_info_1093_2410, + &pci_dev_info_1093_2890, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_2a70, + &pci_dev_info_1093_2a80, + &pci_dev_info_1093_2c80, + &pci_dev_info_1093_2ca0, + &pci_dev_info_1093_70a9, + &pci_dev_info_1093_70b8, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0240, + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + &pci_dev_info_1095_3114, + &pci_dev_info_1095_3124, + &pci_dev_info_1095_3132, + &pci_dev_info_1095_3512, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_032e, + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_3052, + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_100a, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_4001, + &pci_dev_info_10a9_4002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + &pci_dev_info_10a9_8010, + &pci_dev_info_10a9_8018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1042, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2540, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_6540, + &pci_dev_info_10b5_6541, + &pci_dev_info_10b5_6542, + &pci_dev_info_10b5_8111, + &pci_dev_info_10b5_8114, + &pci_dev_info_10b5_8516, + &pci_dev_info_10b5_8532, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9056, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + &pci_dev_info_10b5_bb04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_0013, + &pci_dev_info_10b7_0910, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_1201, + &pci_dev_info_10b7_1202, + &pci_dev_info_10b7_1700, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6000, + &pci_dev_info_10b7_6001, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7770, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_80eb, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9202, + &pci_dev_info_10b7_9210, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990a, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_2802, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0101, + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_0780, + &pci_dev_info_10b9_0782, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1573, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1672, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_1689, + &pci_dev_info_10b9_1695, + &pci_dev_info_10b9_1697, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_3323, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5228, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5246, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_524b, + &pci_dev_info_10b9_524c, + &pci_dev_info_10b9_524d, + &pci_dev_info_10b9_524e, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5263, + &pci_dev_info_10b9_5281, + &pci_dev_info_10b9_5287, + &pci_dev_info_10b9_5288, + &pci_dev_info_10b9_5289, + &pci_dev_info_10b9_5450, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5461, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + &pci_dev_info_10ba_0304, + &pci_dev_info_10ba_0308, + &pci_dev_info_10ba_1002, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cc[] = { + &pci_dev_info_10cc_0660, + &pci_dev_info_10cc_0661, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0431, + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8626, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dd[] = { + &pci_dev_info_10dd_0100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0034, + &pci_dev_info_10de_0035, + &pci_dev_info_10de_0036, + &pci_dev_info_10de_0037, + &pci_dev_info_10de_0038, + &pci_dev_info_10de_003a, + &pci_dev_info_10de_003b, + &pci_dev_info_10de_003c, + &pci_dev_info_10de_003d, + &pci_dev_info_10de_003e, + &pci_dev_info_10de_0040, + &pci_dev_info_10de_0041, + &pci_dev_info_10de_0042, + &pci_dev_info_10de_0043, + &pci_dev_info_10de_0045, + &pci_dev_info_10de_0046, + &pci_dev_info_10de_0047, + &pci_dev_info_10de_0048, + &pci_dev_info_10de_0049, + &pci_dev_info_10de_004e, + &pci_dev_info_10de_0050, + &pci_dev_info_10de_0051, + &pci_dev_info_10de_0052, + &pci_dev_info_10de_0053, + &pci_dev_info_10de_0054, + &pci_dev_info_10de_0055, + &pci_dev_info_10de_0056, + &pci_dev_info_10de_0057, + &pci_dev_info_10de_0058, + &pci_dev_info_10de_0059, + &pci_dev_info_10de_005a, + &pci_dev_info_10de_005b, + &pci_dev_info_10de_005c, + &pci_dev_info_10de_005d, + &pci_dev_info_10de_005e, + &pci_dev_info_10de_005f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006c, + &pci_dev_info_10de_006d, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_0080, + &pci_dev_info_10de_0084, + &pci_dev_info_10de_0085, + &pci_dev_info_10de_0086, + &pci_dev_info_10de_0087, + &pci_dev_info_10de_0088, + &pci_dev_info_10de_008a, + &pci_dev_info_10de_008b, + &pci_dev_info_10de_008c, + &pci_dev_info_10de_008e, + &pci_dev_info_10de_0091, + &pci_dev_info_10de_0092, + &pci_dev_info_10de_0099, + &pci_dev_info_10de_009d, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_00c0, + &pci_dev_info_10de_00c1, + &pci_dev_info_10de_00c2, + &pci_dev_info_10de_00c3, + &pci_dev_info_10de_00c8, + &pci_dev_info_10de_00c9, + &pci_dev_info_10de_00cc, + &pci_dev_info_10de_00cd, + &pci_dev_info_10de_00ce, + &pci_dev_info_10de_00d0, + &pci_dev_info_10de_00d1, + &pci_dev_info_10de_00d2, + &pci_dev_info_10de_00d3, + &pci_dev_info_10de_00d4, + &pci_dev_info_10de_00d5, + &pci_dev_info_10de_00d6, + &pci_dev_info_10de_00d7, + &pci_dev_info_10de_00d8, + &pci_dev_info_10de_00d9, + &pci_dev_info_10de_00da, + &pci_dev_info_10de_00dd, + &pci_dev_info_10de_00df, + &pci_dev_info_10de_00e0, + &pci_dev_info_10de_00e1, + &pci_dev_info_10de_00e2, + &pci_dev_info_10de_00e3, + &pci_dev_info_10de_00e4, + &pci_dev_info_10de_00e5, + &pci_dev_info_10de_00e6, + &pci_dev_info_10de_00e7, + &pci_dev_info_10de_00e8, + &pci_dev_info_10de_00ea, + &pci_dev_info_10de_00ed, + &pci_dev_info_10de_00ee, + &pci_dev_info_10de_00f0, + &pci_dev_info_10de_00f1, + &pci_dev_info_10de_00f2, + &pci_dev_info_10de_00f3, + &pci_dev_info_10de_00f8, + &pci_dev_info_10de_00f9, + &pci_dev_info_10de_00fa, + &pci_dev_info_10de_00fb, + &pci_dev_info_10de_00fc, + &pci_dev_info_10de_00fd, + &pci_dev_info_10de_00fe, + &pci_dev_info_10de_00ff, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0140, + &pci_dev_info_10de_0141, + &pci_dev_info_10de_0142, + &pci_dev_info_10de_0144, + &pci_dev_info_10de_0145, + &pci_dev_info_10de_0146, + &pci_dev_info_10de_0147, + &pci_dev_info_10de_0148, + &pci_dev_info_10de_0149, + &pci_dev_info_10de_014e, + &pci_dev_info_10de_014f, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0160, + &pci_dev_info_10de_0161, + &pci_dev_info_10de_0162, + &pci_dev_info_10de_0163, + &pci_dev_info_10de_0164, + &pci_dev_info_10de_0165, + &pci_dev_info_10de_0166, + &pci_dev_info_10de_0167, + &pci_dev_info_10de_0168, + &pci_dev_info_10de_0169, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0177, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_017d, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0185, + &pci_dev_info_10de_0186, + &pci_dev_info_10de_0187, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_018c, + &pci_dev_info_10de_018d, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b0, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01e0, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01ea, + &pci_dev_info_10de_01eb, + &pci_dev_info_10de_01ec, + &pci_dev_info_10de_01ed, + &pci_dev_info_10de_01ee, + &pci_dev_info_10de_01ef, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0211, + &pci_dev_info_10de_0212, + &pci_dev_info_10de_0215, + &pci_dev_info_10de_0221, + &pci_dev_info_10de_0240, + &pci_dev_info_10de_0241, + &pci_dev_info_10de_0242, + &pci_dev_info_10de_0243, + &pci_dev_info_10de_0244, + &pci_dev_info_10de_0245, + &pci_dev_info_10de_0246, + &pci_dev_info_10de_0247, + &pci_dev_info_10de_0248, + &pci_dev_info_10de_0249, + &pci_dev_info_10de_024a, + &pci_dev_info_10de_024b, + &pci_dev_info_10de_024c, + &pci_dev_info_10de_024d, + &pci_dev_info_10de_024e, + &pci_dev_info_10de_024f, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0260, + &pci_dev_info_10de_0261, + &pci_dev_info_10de_0262, + &pci_dev_info_10de_0263, + &pci_dev_info_10de_0264, + &pci_dev_info_10de_0265, + &pci_dev_info_10de_0266, + &pci_dev_info_10de_0267, + &pci_dev_info_10de_0268, + &pci_dev_info_10de_0269, + &pci_dev_info_10de_026a, + &pci_dev_info_10de_026b, + &pci_dev_info_10de_026c, + &pci_dev_info_10de_026d, + &pci_dev_info_10de_026e, + &pci_dev_info_10de_026f, + &pci_dev_info_10de_0270, + &pci_dev_info_10de_0271, + &pci_dev_info_10de_0272, + &pci_dev_info_10de_027e, + &pci_dev_info_10de_027f, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0286, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_028c, + &pci_dev_info_10de_02a0, + &pci_dev_info_10de_02f0, + &pci_dev_info_10de_02f1, + &pci_dev_info_10de_02f2, + &pci_dev_info_10de_02f3, + &pci_dev_info_10de_02f4, + &pci_dev_info_10de_02f5, + &pci_dev_info_10de_02f6, + &pci_dev_info_10de_02f7, + &pci_dev_info_10de_02f8, + &pci_dev_info_10de_02f9, + &pci_dev_info_10de_02fa, + &pci_dev_info_10de_02fb, + &pci_dev_info_10de_02fc, + &pci_dev_info_10de_02fd, + &pci_dev_info_10de_02fe, + &pci_dev_info_10de_02ff, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + &pci_dev_info_10de_0311, + &pci_dev_info_10de_0312, + &pci_dev_info_10de_0313, + &pci_dev_info_10de_0314, + &pci_dev_info_10de_0316, + &pci_dev_info_10de_0317, + &pci_dev_info_10de_031a, + &pci_dev_info_10de_031b, + &pci_dev_info_10de_031c, + &pci_dev_info_10de_031d, + &pci_dev_info_10de_031e, + &pci_dev_info_10de_031f, + &pci_dev_info_10de_0320, + &pci_dev_info_10de_0321, + &pci_dev_info_10de_0322, + &pci_dev_info_10de_0323, + &pci_dev_info_10de_0324, + &pci_dev_info_10de_0325, + &pci_dev_info_10de_0326, + &pci_dev_info_10de_0327, + &pci_dev_info_10de_0328, + &pci_dev_info_10de_0329, + &pci_dev_info_10de_032a, + &pci_dev_info_10de_032b, + &pci_dev_info_10de_032c, + &pci_dev_info_10de_032d, + &pci_dev_info_10de_032f, + &pci_dev_info_10de_0330, + &pci_dev_info_10de_0331, + &pci_dev_info_10de_0332, + &pci_dev_info_10de_0333, + &pci_dev_info_10de_0334, + &pci_dev_info_10de_0338, + &pci_dev_info_10de_033f, + &pci_dev_info_10de_0341, + &pci_dev_info_10de_0342, + &pci_dev_info_10de_0343, + &pci_dev_info_10de_0344, + &pci_dev_info_10de_0345, + &pci_dev_info_10de_0347, + &pci_dev_info_10de_0348, + &pci_dev_info_10de_0349, + &pci_dev_info_10de_034b, + &pci_dev_info_10de_034c, + &pci_dev_info_10de_034e, + &pci_dev_info_10de_034f, + &pci_dev_info_10de_0360, + &pci_dev_info_10de_0361, + &pci_dev_info_10de_0362, + &pci_dev_info_10de_0363, + &pci_dev_info_10de_0364, + &pci_dev_info_10de_0365, + &pci_dev_info_10de_0366, + &pci_dev_info_10de_0367, + &pci_dev_info_10de_0368, + &pci_dev_info_10de_0369, + &pci_dev_info_10de_036a, + &pci_dev_info_10de_036c, + &pci_dev_info_10de_036d, + &pci_dev_info_10de_036e, + &pci_dev_info_10de_0371, + &pci_dev_info_10de_0372, + &pci_dev_info_10de_0373, + &pci_dev_info_10de_037a, + &pci_dev_info_10de_037e, + &pci_dev_info_10de_037f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f0a1, + &pci_dev_info_10df_f0a5, + &pci_dev_info_10df_f0b5, + &pci_dev_info_10df_f0d1, + &pci_dev_info_10df_f0d5, + &pci_dev_info_10df_f0e1, + &pci_dev_info_10df_f0e5, + &pci_dev_info_10df_f0f5, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f701, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f801, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f901, + &pci_dev_info_10df_f980, + &pci_dev_info_10df_f981, + &pci_dev_info_10df_f982, + &pci_dev_info_10df_fa00, + &pci_dev_info_10df_fb00, + &pci_dev_info_10df_fc00, + &pci_dev_info_10df_fc10, + &pci_dev_info_10df_fc20, + &pci_dev_info_10df_fd00, + &pci_dev_info_10df_fe00, + &pci_dev_info_10df_ff00, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0148, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + &pci_dev_info_10e3_8260, + &pci_dev_info_10e3_8261, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e4[] = { + &pci_dev_info_10e4_8029, + NULL +}; +#endif +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_1072, + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_814c, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_81e6, + &pci_dev_info_10e8_8291, + &pci_dev_info_10e8_82c4, + &pci_dev_info_10e8_82c5, + &pci_dev_info_10e8_82c6, + &pci_dev_info_10e8_82c7, + &pci_dev_info_10e8_82ca, + &pci_dev_info_10e8_82db, + &pci_dev_info_10e8_82e2, + &pci_dev_info_10e8_8851, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + &pci_dev_info_10ea_5252, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_0139, + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8180, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_0205, + &pci_dev_info_10ee_0210, + &pci_dev_info_10ee_0314, + &pci_dev_info_10ee_0405, + &pci_dev_info_10ee_0410, + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + &pci_dev_info_10ee_3fc6, + &pci_dev_info_10ee_8381, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#define pci_dev_list_10f1 NULL +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + &pci_dev_info_1101_9502, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_0007, + &pci_dev_info_1102_0008, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_7005, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + &pci_dev_info_1103_0009, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + &pci_dev_info_1105_8401, + &pci_dev_info_1105_8470, + &pci_dev_info_1105_8471, + &pci_dev_info_1105_8475, + &pci_dev_info_1105_8476, + &pci_dev_info_1105_8485, + &pci_dev_info_1105_8486, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0204, + &pci_dev_info_1106_0238, + &pci_dev_info_1106_0259, + &pci_dev_info_1106_0269, + &pci_dev_info_1106_0282, + &pci_dev_info_1106_0290, + &pci_dev_info_1106_0296, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0308, + &pci_dev_info_1106_0314, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0591, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1204, + &pci_dev_info_1106_1208, + &pci_dev_info_1106_1238, + &pci_dev_info_1106_1258, + &pci_dev_info_1106_1259, + &pci_dev_info_1106_1269, + &pci_dev_info_1106_1282, + &pci_dev_info_1106_1290, + &pci_dev_info_1106_1296, + &pci_dev_info_1106_1308, + &pci_dev_info_1106_1314, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_2204, + &pci_dev_info_1106_2208, + &pci_dev_info_1106_2238, + &pci_dev_info_1106_2258, + &pci_dev_info_1106_2259, + &pci_dev_info_1106_2269, + &pci_dev_info_1106_2282, + &pci_dev_info_1106_2290, + &pci_dev_info_1106_2296, + &pci_dev_info_1106_2308, + &pci_dev_info_1106_2314, + &pci_dev_info_1106_287a, + &pci_dev_info_1106_287b, + &pci_dev_info_1106_287c, + &pci_dev_info_1106_287d, + &pci_dev_info_1106_287e, + &pci_dev_info_1106_3022, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3053, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3108, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3113, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3118, + &pci_dev_info_1106_3119, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3149, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3164, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3178, + &pci_dev_info_1106_3188, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_3204, + &pci_dev_info_1106_3205, + &pci_dev_info_1106_3208, + &pci_dev_info_1106_3213, + &pci_dev_info_1106_3218, + &pci_dev_info_1106_3227, + &pci_dev_info_1106_3238, + &pci_dev_info_1106_3249, + &pci_dev_info_1106_3258, + &pci_dev_info_1106_3259, + &pci_dev_info_1106_3269, + &pci_dev_info_1106_3282, + &pci_dev_info_1106_3287, + &pci_dev_info_1106_3288, + &pci_dev_info_1106_3290, + &pci_dev_info_1106_3296, + &pci_dev_info_1106_3337, + &pci_dev_info_1106_3344, + &pci_dev_info_1106_3349, + &pci_dev_info_1106_337a, + &pci_dev_info_1106_337b, + &pci_dev_info_1106_4149, + &pci_dev_info_1106_4204, + &pci_dev_info_1106_4208, + &pci_dev_info_1106_4238, + &pci_dev_info_1106_4258, + &pci_dev_info_1106_4259, + &pci_dev_info_1106_4269, + &pci_dev_info_1106_4282, + &pci_dev_info_1106_4290, + &pci_dev_info_1106_4296, + &pci_dev_info_1106_4308, + &pci_dev_info_1106_4314, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_5208, + &pci_dev_info_1106_5238, + &pci_dev_info_1106_5290, + &pci_dev_info_1106_5308, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_7204, + &pci_dev_info_1106_7205, + &pci_dev_info_1106_7208, + &pci_dev_info_1106_7238, + &pci_dev_info_1106_7258, + &pci_dev_info_1106_7259, + &pci_dev_info_1106_7269, + &pci_dev_info_1106_7282, + &pci_dev_info_1106_7290, + &pci_dev_info_1106_7296, + &pci_dev_info_1106_7308, + &pci_dev_info_1106_7314, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_a208, + &pci_dev_info_1106_a238, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b113, + &pci_dev_info_1106_b115, + &pci_dev_info_1106_b168, + &pci_dev_info_1106_b188, + &pci_dev_info_1106_b198, + &pci_dev_info_1106_b213, + &pci_dev_info_1106_c208, + &pci_dev_info_1106_c238, + &pci_dev_info_1106_d104, + &pci_dev_info_1106_d208, + &pci_dev_info_1106_d213, + &pci_dev_info_1106_d238, + &pci_dev_info_1106_e208, + &pci_dev_info_1106_e238, + &pci_dev_info_1106_f208, + &pci_dev_info_1106_f238, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_0006, + &pci_dev_info_110a_0015, + &pci_dev_info_110a_001d, + &pci_dev_info_110a_007b, + &pci_dev_info_110a_007c, + &pci_dev_info_110a_007d, + &pci_dev_info_110a_2101, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_2104, + &pci_dev_info_110a_3142, + &pci_dev_info_110a_4021, + &pci_dev_info_110a_4029, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + &pci_dev_info_1113_d301, + &pci_dev_info_1113_ec02, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1114[] = { + &pci_dev_info_1114_0506, + NULL +}; +#endif +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0010, + &pci_dev_info_1119_0011, + &pci_dev_info_1119_0012, + &pci_dev_info_1119_0013, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_02ff, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + &pci_dev_info_111a_1203, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + &pci_dev_info_111d_0004, + &pci_dev_info_111d_0005, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#define pci_dev_list_1124 NULL +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + &pci_dev_info_112f_0008, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_5400, + &pci_dev_info_1131_5402, + &pci_dev_info_1131_5405, + &pci_dev_info_1131_5406, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + &pci_dev_info_1131_9730, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e006, + &pci_dev_info_1133_e007, + &pci_dev_info_1133_e008, + &pci_dev_info_1133_e009, + &pci_dev_info_1133_e00a, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e00c, + &pci_dev_info_1133_e00d, + &pci_dev_info_1133_e00e, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e011, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e013, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e015, + &pci_dev_info_1133_e016, + &pci_dev_info_1133_e017, + &pci_dev_info_1133_e018, + &pci_dev_info_1133_e019, + &pci_dev_info_1133_e01a, + &pci_dev_info_1133_e01b, + &pci_dev_info_1133_e01c, + &pci_dev_info_1133_e01e, + &pci_dev_info_1133_e020, + &pci_dev_info_1133_e024, + &pci_dev_info_1133_e028, + &pci_dev_info_1133_e02a, + &pci_dev_info_1133_e02c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + &pci_dev_info_1134_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + &pci_dev_info_1145_f020, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + &pci_dev_info_1148_4500, + &pci_dev_info_1148_9000, + &pci_dev_info_1148_9843, + &pci_dev_info_1148_9e00, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0028, + &pci_dev_info_114f_0029, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0043, + &pci_dev_info_114f_0044, + &pci_dev_info_114f_0045, + &pci_dev_info_114f_004e, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_00b0, + &pci_dev_info_114f_00b1, + &pci_dev_info_114f_00c8, + &pci_dev_info_114f_00c9, + &pci_dev_info_114f_00ca, + &pci_dev_info_114f_00cb, + &pci_dev_info_114f_00d0, + &pci_dev_info_114f_00d1, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_00d4, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0000, + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0006, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0036, + &pci_dev_info_1166_0101, + &pci_dev_info_1166_0104, + &pci_dev_info_1166_0110, + &pci_dev_info_1166_0130, + &pci_dev_info_1166_0132, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0205, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0214, + &pci_dev_info_1166_0217, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0223, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + &pci_dev_info_1166_0230, + &pci_dev_info_1166_0234, + &pci_dev_info_1166_0240, + &pci_dev_info_1166_0241, + &pci_dev_info_1166_0242, + &pci_dev_info_1166_024a, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0102, + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_117c[] = { + &pci_dev_info_117c_0030, + NULL +}; +#endif +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0511, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + &pci_dev_info_1180_0554, + &pci_dev_info_1180_0575, + &pci_dev_info_1180_0576, + &pci_dev_info_1180_0592, + &pci_dev_info_1180_0811, + &pci_dev_info_1180_0822, + &pci_dev_info_1180_0841, + &pci_dev_info_1180_0852, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1025, + &pci_dev_info_1186_1026, + &pci_dev_info_1186_1043, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1541, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_2027, + &pci_dev_info_1186_3203, + &pci_dev_info_1186_3300, + &pci_dev_info_1186_3a03, + &pci_dev_info_1186_3a04, + &pci_dev_info_1186_3a05, + &pci_dev_info_1186_3a07, + &pci_dev_info_1186_3a08, + &pci_dev_info_1186_3a10, + &pci_dev_info_1186_3a11, + &pci_dev_info_1186_3a12, + &pci_dev_info_1186_3a13, + &pci_dev_info_1186_3a14, + &pci_dev_info_1186_3a63, + &pci_dev_info_1186_4000, + &pci_dev_info_1186_4300, + &pci_dev_info_1186_4c00, + &pci_dev_info_1186_8400, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + &pci_dev_info_1191_8060, + &pci_dev_info_1191_8080, + &pci_dev_info_1191_8081, + &pci_dev_info_1191_808a, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1197[] = { + &pci_dev_info_1197_010c, + NULL +}; +#endif +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_138f, + &pci_dev_info_11ab_1fa6, + &pci_dev_info_11ab_1fa7, + &pci_dev_info_11ab_1faa, + &pci_dev_info_11ab_4320, + &pci_dev_info_11ab_4340, + &pci_dev_info_11ab_4341, + &pci_dev_info_11ab_4342, + &pci_dev_info_11ab_4343, + &pci_dev_info_11ab_4344, + &pci_dev_info_11ab_4345, + &pci_dev_info_11ab_4346, + &pci_dev_info_11ab_4347, + &pci_dev_info_11ab_4350, + &pci_dev_info_11ab_4351, + &pci_dev_info_11ab_4352, + &pci_dev_info_11ab_4360, + &pci_dev_info_11ab_4361, + &pci_dev_info_11ab_4362, + &pci_dev_info_11ab_4363, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_5005, + &pci_dev_info_11ab_5040, + &pci_dev_info_11ab_5041, + &pci_dev_info_11ab_5080, + &pci_dev_info_11ab_5081, + &pci_dev_info_11ab_6041, + &pci_dev_info_11ab_6081, + &pci_dev_info_11ab_6460, + &pci_dev_info_11ab_6480, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11af[] = { + &pci_dev_info_11af_0001, + &pci_dev_info_11af_ee40, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bd[] = { + &pci_dev_info_11bd_002e, + &pci_dev_info_11bd_bede, + NULL +}; +#endif +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_048c, + &pci_dev_info_11c1_048f, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + &pci_dev_info_11c1_8110, + &pci_dev_info_11c1_ab10, + &pci_dev_info_11c1_ab11, + &pci_dev_info_11c1_ab20, + &pci_dev_info_11c1_ab21, + &pci_dev_info_11c1_ab30, + &pci_dev_info_11c1_ed00, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1535, + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + &pci_dev_info_11d4_5340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_0001, + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_000d, + &pci_dev_info_11fe_000e, + &pci_dev_info_11fe_000f, + &pci_dev_info_11fe_0801, + &pci_dev_info_11fe_0802, + &pci_dev_info_11fe_0803, + &pci_dev_info_11fe_0805, + &pci_dev_info_11fe_080c, + &pci_dev_info_11fe_080d, + &pci_dev_info_11fe_0812, + &pci_dev_info_11fe_0903, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ff[] = { + &pci_dev_info_11ff_0003, + NULL +}; +#endif +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + &pci_dev_info_1217_7110, + &pci_dev_info_1217_7112, + &pci_dev_info_1217_7113, + &pci_dev_info_1217_7114, + &pci_dev_info_1217_7134, + &pci_dev_info_1217_71e2, + &pci_dev_info_1217_7212, + &pci_dev_info_1217_7213, + &pci_dev_info_1217_7223, + &pci_dev_info_1217_7233, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#define pci_dev_list_121e NULL +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1227[] = { + &pci_dev_info_1227_0006, + &pci_dev_info_1227_0023, + NULL +}; +#endif +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_1400, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + &pci_dev_info_1242_6562, + &pci_dev_info_1242_656a, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + &pci_dev_info_1244_2700, + &pci_dev_info_1244_2900, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + &pci_dev_info_1259_a117, + &pci_dev_info_1259_a120, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0101, + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3872, + &pci_dev_info_1260_3873, + &pci_dev_info_1260_3886, + &pci_dev_info_1260_3890, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + &pci_dev_info_1260_ffff, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_126c[] = { + &pci_dev_info_126c_1211, + &pci_dev_info_126c_126c, + NULL +}; +#endif +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0501, + &pci_dev_info_126f_0510, + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0730, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1171, + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + &pci_dev_info_1278_0710, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0060, + &pci_dev_info_1279_0061, + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8211, + &pci_dev_info_1283_8212, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8872, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12a3[] = { + &pci_dev_info_12a3_8105, + NULL +}; +#endif +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_0002, + &pci_dev_info_12ab_3000, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + &pci_dev_info_12ae_00fa, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c4[] = { + &pci_dev_info_12c4_0001, + &pci_dev_info_12c4_0002, + &pci_dev_info_12c4_0003, + &pci_dev_info_12c4_0004, + &pci_dev_info_12c4_0005, + &pci_dev_info_12c4_0006, + &pci_dev_info_12c4_0007, + &pci_dev_info_12c4_0008, + &pci_dev_info_12c4_0009, + &pci_dev_info_12c4_000a, + &pci_dev_info_12c4_000b, + &pci_dev_info_12c4_000c, + &pci_dev_info_12c4_000d, + &pci_dev_info_12c4_0100, + &pci_dev_info_12c4_0201, + &pci_dev_info_12c4_0202, + &pci_dev_info_12c4_0300, + &pci_dev_info_12c4_0301, + &pci_dev_info_12c4_0302, + &pci_dev_info_12c4_0310, + &pci_dev_info_12c4_0311, + &pci_dev_info_12c4_0312, + &pci_dev_info_12c4_0320, + &pci_dev_info_12c4_0321, + &pci_dev_info_12c4_0322, + &pci_dev_info_12c4_0330, + &pci_dev_info_12c4_0331, + &pci_dev_info_12c4_0332, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d4[] = { + &pci_dev_info_12d4_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d5[] = { + &pci_dev_info_12d5_0003, + &pci_dev_info_12d5_1000, + NULL +}; +#endif +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d8[] = { + &pci_dev_info_12d8_8150, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d9[] = { + &pci_dev_info_12d9_0002, + &pci_dev_info_12d9_0004, + &pci_dev_info_12d9_0005, + NULL +}; +#endif +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12de[] = { + &pci_dev_info_12de_0200, + NULL +}; +#endif +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12fb[] = { + &pci_dev_info_12fb_0001, + &pci_dev_info_12fb_00f5, + &pci_dev_info_12fb_02ad, + &pci_dev_info_12fb_2adc, + &pci_dev_info_12fb_3100, + &pci_dev_info_12fb_3500, + &pci_dev_info_12fb_4d4f, + &pci_dev_info_12fb_8120, + &pci_dev_info_12fb_da62, + &pci_dev_info_12fb_db62, + &pci_dev_info_12fb_dc62, + &pci_dev_info_12fb_dd62, + &pci_dev_info_12fb_eddc, + &pci_dev_info_12fb_fa01, + NULL +}; +#endif +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + &pci_dev_info_1307_004d, + &pci_dev_info_1307_0052, + &pci_dev_info_1307_0054, + &pci_dev_info_1307_005e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + &pci_dev_info_1317_2850, + &pci_dev_info_1317_5120, + &pci_dev_info_1317_8201, + &pci_dev_info_1317_8211, + &pci_dev_info_1317_9511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + &pci_dev_info_131f_2081, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1331[] = { + &pci_dev_info_1331_0030, + &pci_dev_info_1331_8200, + &pci_dev_info_1331_8201, + &pci_dev_info_1331_8202, + &pci_dev_info_1331_8210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + &pci_dev_info_1332_5425, + &pci_dev_info_1332_6140, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_2189, + &pci_dev_info_134d_2486, + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_5101, + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1360[] = { + &pci_dev_info_1360_0101, + &pci_dev_info_1360_0102, + &pci_dev_info_1360_0103, + &pci_dev_info_1360_0201, + &pci_dev_info_1360_0202, + &pci_dev_info_1360_0203, + &pci_dev_info_1360_0301, + &pci_dev_info_1360_0302, + NULL +}; +#endif +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#define pci_dev_list_136a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136b[] = { + &pci_dev_info_136b_ff01, + NULL +}; +#endif +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1371[] = { + &pci_dev_info_1371_434e, + NULL +}; +#endif +#define pci_dev_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1374[] = { + &pci_dev_info_1374_0024, + &pci_dev_info_1374_0025, + &pci_dev_info_1374_0026, + &pci_dev_info_1374_0027, + &pci_dev_info_1374_0029, + &pci_dev_info_1374_002a, + &pci_dev_info_1374_002b, + &pci_dev_info_1374_002c, + &pci_dev_info_1374_002d, + &pci_dev_info_1374_002e, + &pci_dev_info_1374_002f, + &pci_dev_info_1374_0030, + &pci_dev_info_1374_0031, + &pci_dev_info_1374_0032, + &pci_dev_info_1374_0034, + &pci_dev_info_1374_0035, + &pci_dev_info_1374_0036, + &pci_dev_info_1374_0037, + &pci_dev_info_1374_0038, + &pci_dev_info_1374_0039, + &pci_dev_info_1374_003a, + NULL +}; +#endif +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_137a[] = { + &pci_dev_info_137a_0001, + NULL +}; +#endif +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1382[] = { + &pci_dev_info_1382_0001, + &pci_dev_info_1382_2008, + &pci_dev_info_1382_2088, + &pci_dev_info_1382_20c8, + &pci_dev_info_1382_4008, + &pci_dev_info_1382_4010, + &pci_dev_info_1382_4048, + &pci_dev_info_1382_4088, + &pci_dev_info_1382_4248, + &pci_dev_info_1382_4424, + NULL +}; +#endif +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_0013, + &pci_dev_info_1385_311a, + &pci_dev_info_1385_4100, + &pci_dev_info_1385_4105, + &pci_dev_info_1385_4400, + &pci_dev_info_1385_4600, + &pci_dev_info_1385_4601, + &pci_dev_info_1385_4610, + &pci_dev_info_1385_4800, + &pci_dev_info_1385_4900, + &pci_dev_info_1385_4a00, + &pci_dev_info_1385_4b00, + &pci_dev_info_1385_4c00, + &pci_dev_info_1385_4d00, + &pci_dev_info_1385_4e00, + &pci_dev_info_1385_4f00, + &pci_dev_info_1385_5200, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_6b00, + &pci_dev_info_1385_6d00, + &pci_dev_info_1385_f004, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1141, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_16b8, + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + &pci_dev_info_13a3_001d, + &pci_dev_info_13a3_0020, + &pci_dev_info_13a3_0026, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0152, + &pci_dev_info_13a8_0154, + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + &pci_dev_info_13c0_0020, + &pci_dev_info_13c0_0030, + &pci_dev_info_13c0_0210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + &pci_dev_info_13c1_1003, + NULL +}; +#endif +#define pci_dev_list_13c2 NULL +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c6[] = { + &pci_dev_info_13c6_0520, + &pci_dev_info_13c6_0620, + &pci_dev_info_13c6_0820, + NULL +}; +#endif +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + &pci_dev_info_13d0_2200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab03, + &pci_dev_info_13d1_ab06, + &pci_dev_info_13d1_ab08, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#define pci_dev_list_13ec NULL +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0200, + &pci_dev_info_13f0_0201, + &pci_dev_info_13f0_1023, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0011, + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1240, + &pci_dev_info_13fe_1600, + &pci_dev_info_13fe_1733, + &pci_dev_info_13fe_1752, + &pci_dev_info_13fe_1754, + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0110, + &pci_dev_info_1407_0111, + &pci_dev_info_1407_0120, + &pci_dev_info_1407_0121, + &pci_dev_info_1407_0180, + &pci_dev_info_1407_0181, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0220, + &pci_dev_info_1407_0221, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9510, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9521, + &pci_dev_info_1415_9523, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1420[] = { + &pci_dev_info_1420_8002, + &pci_dev_info_1420_8003, + NULL +}; +#endif +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1425[] = { + &pci_dev_info_1425_000b, + NULL +}; +#endif +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_142e[] = { + &pci_dev_info_142e_4020, + &pci_dev_info_142e_4337, + NULL +}; +#endif +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1432[] = { + &pci_dev_info_1432_9130, + NULL +}; +#endif +#define pci_dev_list_1433 NULL +#define pci_dev_list_1435 NULL +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8164, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#define pci_dev_list_144d NULL +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1458[] = { + &pci_dev_info_1458_0c11, + &pci_dev_info_1458_e911, + NULL +}; +#endif +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1461[] = { + &pci_dev_info_1461_f436, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1462[] = { + &pci_dev_info_1462_5501, + &pci_dev_info_1462_6819, + &pci_dev_info_1462_6825, + &pci_dev_info_1462_6834, + &pci_dev_info_1462_8725, + &pci_dev_info_1462_9000, + &pci_dev_info_1462_9110, + &pci_dev_info_1462_9119, + &pci_dev_info_1462_9591, + NULL +}; +#endif +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_146c[] = { + &pci_dev_info_146c_1430, + NULL +}; +#endif +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1497[] = { + &pci_dev_info_1497_1497, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1498[] = { + &pci_dev_info_1498_0330, + &pci_dev_info_1498_0385, + &pci_dev_info_1498_21cd, + &pci_dev_info_1498_30c8, + NULL +}; +#endif +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_149d[] = { + &pci_dev_info_149d_0001, + NULL +}; +#endif +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + &pci_dev_info_14b9_a505, + &pci_dev_info_14b9_a506, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#define pci_dev_list_14bc NULL +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14c1[] = { + &pci_dev_info_14c1_8043, + NULL +}; +#endif +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d9[] = { + &pci_dev_info_14d9_0010, + &pci_dev_info_14d9_9000, + NULL +}; +#endif +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + &pci_dev_info_14db_2182, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_0800, + &pci_dev_info_14e4_0804, + &pci_dev_info_14e4_0805, + &pci_dev_info_14e4_0806, + &pci_dev_info_14e4_080b, + &pci_dev_info_14e4_080f, + &pci_dev_info_14e4_0811, + &pci_dev_info_14e4_0816, + &pci_dev_info_14e4_1600, + &pci_dev_info_14e4_1601, + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164a, + &pci_dev_info_14e4_164c, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_1654, + &pci_dev_info_14e4_1659, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_165e, + &pci_dev_info_14e4_1668, + &pci_dev_info_14e4_166a, + &pci_dev_info_14e4_166b, + &pci_dev_info_14e4_166e, + &pci_dev_info_14e4_1677, + &pci_dev_info_14e4_1678, + &pci_dev_info_14e4_167d, + &pci_dev_info_14e4_167e, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_169c, + &pci_dev_info_14e4_169d, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16aa, + &pci_dev_info_14e4_16ac, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_16dd, + &pci_dev_info_14e4_16f7, + &pci_dev_info_14e4_16fd, + &pci_dev_info_14e4_16fe, + &pci_dev_info_14e4_170c, + &pci_dev_info_14e4_170d, + &pci_dev_info_14e4_170e, + &pci_dev_info_14e4_3352, + &pci_dev_info_14e4_3360, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4305, + &pci_dev_info_14e4_4306, + &pci_dev_info_14e4_4307, + &pci_dev_info_14e4_4310, + &pci_dev_info_14e4_4312, + &pci_dev_info_14e4_4313, + &pci_dev_info_14e4_4315, + &pci_dev_info_14e4_4318, + &pci_dev_info_14e4_4319, + &pci_dev_info_14e4_4320, + &pci_dev_info_14e4_4321, + &pci_dev_info_14e4_4322, + &pci_dev_info_14e4_4324, + &pci_dev_info_14e4_4325, + &pci_dev_info_14e4_4326, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4403, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_4430, + &pci_dev_info_14e4_4432, + &pci_dev_info_14e4_4610, + &pci_dev_info_14e4_4611, + &pci_dev_info_14e4_4612, + &pci_dev_info_14e4_4613, + &pci_dev_info_14e4_4614, + &pci_dev_info_14e4_4615, + &pci_dev_info_14e4_4704, + &pci_dev_info_14e4_4705, + &pci_dev_info_14e4_4706, + &pci_dev_info_14e4_4707, + &pci_dev_info_14e4_4708, + &pci_dev_info_14e4_4710, + &pci_dev_info_14e4_4711, + &pci_dev_info_14e4_4712, + &pci_dev_info_14e4_4713, + &pci_dev_info_14e4_4714, + &pci_dev_info_14e4_4715, + &pci_dev_info_14e4_4716, + &pci_dev_info_14e4_4717, + &pci_dev_info_14e4_4718, + &pci_dev_info_14e4_4719, + &pci_dev_info_14e4_4720, + &pci_dev_info_14e4_5365, + &pci_dev_info_14e4_5600, + &pci_dev_info_14e4_5605, + &pci_dev_info_14e4_5615, + &pci_dev_info_14e4_5625, + &pci_dev_info_14e4_5645, + &pci_dev_info_14e4_5670, + &pci_dev_info_14e4_5680, + &pci_dev_info_14e4_5690, + &pci_dev_info_14e4_5691, + &pci_dev_info_14e4_5692, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + &pci_dev_info_14e4_5822, + &pci_dev_info_14e4_5823, + &pci_dev_info_14e4_5824, + &pci_dev_info_14e4_5840, + &pci_dev_info_14e4_5841, + &pci_dev_info_14e4_5850, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + &pci_dev_info_14ea_ab07, + &pci_dev_info_14ea_ab08, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1085, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1620, + &pci_dev_info_14f1_1621, + &pci_dev_info_14f1_1622, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1811, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_2f02, + &pci_dev_info_14f1_2f11, + &pci_dev_info_14f1_2f20, + &pci_dev_info_14f1_8234, + &pci_dev_info_14f1_8800, + &pci_dev_info_14f1_8801, + &pci_dev_info_14f1_8802, + &pci_dev_info_14f1_8804, + &pci_dev_info_14f1_8811, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f2[] = { + &pci_dev_info_14f2_0120, + &pci_dev_info_14f2_0121, + &pci_dev_info_14f2_0122, + &pci_dev_info_14f2_0123, + &pci_dev_info_14f2_0124, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f3[] = { + &pci_dev_info_14f3_2030, + &pci_dev_info_14f3_2050, + &pci_dev_info_14f3_2060, + NULL +}; +#endif +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f8[] = { + &pci_dev_info_14f8_2077, + NULL +}; +#endif +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14fc[] = { + &pci_dev_info_14fc_0000, + &pci_dev_info_14fc_0001, + NULL +}; +#endif +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1500[] = { + &pci_dev_info_1500_1360, + NULL +}; +#endif +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0800, + &pci_dev_info_1516_0803, + &pci_dev_info_1516_0891, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151c[] = { + &pci_dev_info_151c_0003, + &pci_dev_info_151c_4000, + NULL +}; +#endif +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_0510, + &pci_dev_info_1524_0520, + &pci_dev_info_1524_0530, + &pci_dev_info_1524_0550, + &pci_dev_info_1524_0610, + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1411, + &pci_dev_info_1524_1412, + &pci_dev_info_1524_1420, + &pci_dev_info_1524_1421, + &pci_dev_info_1524_1422, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1532[] = { + &pci_dev_info_1532_0020, + NULL +}; +#endif +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1538[] = { + &pci_dev_info_1538_0303, + NULL +}; +#endif +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153b[] = { + &pci_dev_info_153b_1144, + &pci_dev_info_153b_1147, + &pci_dev_info_153b_1158, + NULL +}; +#endif +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153f[] = { + &pci_dev_info_153f_0001, + NULL +}; +#endif +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#define pci_dev_list_1542 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1578[] = { + &pci_dev_info_1578_5615, + NULL +}; +#endif +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0405, + &pci_dev_info_15ad_0710, + &pci_dev_info_15ad_0720, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + &pci_dev_info_15b3_5a44, + &pci_dev_info_15b3_5a45, + &pci_dev_info_15b3_5a46, + &pci_dev_info_15b3_5e8d, + &pci_dev_info_15b3_6274, + &pci_dev_info_15b3_6278, + &pci_dev_info_15b3_6279, + &pci_dev_info_15b3_6282, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_1100, + &pci_dev_info_15bc_2922, + &pci_dev_info_15bc_2928, + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c5[] = { + &pci_dev_info_15c5_8010, + NULL +}; +#endif +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e9[] = { + &pci_dev_info_15e9_1841, + NULL +}; +#endif +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15ec[] = { + &pci_dev_info_15ec_3101, + &pci_dev_info_15ec_5102, + NULL +}; +#endif +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + &pci_dev_info_1619_0610, + &pci_dev_info_1619_0620, + &pci_dev_info_1619_0640, + &pci_dev_info_1619_1610, + &pci_dev_info_1619_2610, + NULL +}; +#endif +#define pci_dev_list_161f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1626[] = { + &pci_dev_info_1626_8410, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1637[] = { + &pci_dev_info_1637_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_3052, + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165f[] = { + &pci_dev_info_165f_1020, + NULL +}; +#endif +#define pci_dev_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1668[] = { + &pci_dev_info_1668_0100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_166d[] = { + &pci_dev_info_166d_0001, + &pci_dev_info_166d_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1677[] = { + &pci_dev_info_1677_104e, + &pci_dev_info_1677_12d7, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167b[] = { + &pci_dev_info_167b_2102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1681[] = { + &pci_dev_info_1681_0010, + NULL +}; +#endif +#define pci_dev_list_1682 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1688[] = { + &pci_dev_info_1688_1170, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_168c[] = { + &pci_dev_info_168c_0007, + &pci_dev_info_168c_0011, + &pci_dev_info_168c_0012, + &pci_dev_info_168c_0013, + &pci_dev_info_168c_001a, + &pci_dev_info_168c_001b, + &pci_dev_info_168c_0020, + &pci_dev_info_168c_1014, + NULL +}; +#endif +#define pci_dev_list_1695 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_169c[] = { + &pci_dev_info_169c_0044, + NULL +}; +#endif +#define pci_dev_list_16a5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1100, + &pci_dev_info_16ab_1101, + &pci_dev_info_16ab_1102, + &pci_dev_info_16ab_8501, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ae[] = { + &pci_dev_info_16ae_1141, + NULL +}; +#endif +#define pci_dev_list_16af NULL +#define pci_dev_list_16b4 NULL +#define pci_dev_list_16b8 NULL +#define pci_dev_list_16be NULL +#define pci_dev_list_16c8 NULL +#define pci_dev_list_16c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ca[] = { + &pci_dev_info_16ca_0001, + NULL +}; +#endif +#define pci_dev_list_16cd NULL +#define pci_dev_list_16ce NULL +#define pci_dev_list_16df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e3[] = { + &pci_dev_info_16e3_1e0f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_00ff, + &pci_dev_info_16ec_0116, + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ed[] = { + &pci_dev_info_16ed_1001, + NULL +}; +#endif +#define pci_dev_list_16f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16f4[] = { + &pci_dev_info_16f4_8000, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1702 NULL +#define pci_dev_list_1705 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_170b[] = { + &pci_dev_info_170b_0100, + NULL +}; +#endif +#define pci_dev_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1725[] = { + &pci_dev_info_1725_7174, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_172a[] = { + &pci_dev_info_172a_13c8, + NULL +}; +#endif +#define pci_dev_list_1734 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1737[] = { + &pci_dev_info_1737_0013, + &pci_dev_info_1737_0015, + &pci_dev_info_1737_1032, + &pci_dev_info_1737_1064, + &pci_dev_info_1737_ab08, + &pci_dev_info_1737_ab09, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03e9, + &pci_dev_info_173b_03ea, + &pci_dev_info_173b_03eb, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_1749 NULL +#define pci_dev_list_174b NULL +#define pci_dev_list_174d NULL +#define pci_dev_list_175c NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1775 NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1799[] = { + &pci_dev_info_1799_6001, + &pci_dev_info_1799_6020, + &pci_dev_info_1799_6060, + &pci_dev_info_1799_7000, + &pci_dev_info_1799_7010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_179c[] = { + &pci_dev_info_179c_0557, + &pci_dev_info_179c_0566, + &pci_dev_info_179c_5031, + &pci_dev_info_179c_5121, + &pci_dev_info_179c_5211, + &pci_dev_info_179c_5679, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17a0[] = { + &pci_dev_info_17a0_8033, + &pci_dev_info_17a0_8034, + NULL +}; +#endif +#define pci_dev_list_17aa NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b3[] = { + &pci_dev_info_17b3_ab08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b4[] = { + &pci_dev_info_17b4_0011, + NULL +}; +#endif +#define pci_dev_list_17c0 NULL +#define pci_dev_list_17c2 NULL +#define pci_dev_list_17cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#define pci_dev_list_17cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d3[] = { + &pci_dev_info_17d3_1110, + &pci_dev_info_17d3_1120, + &pci_dev_info_17d3_1130, + &pci_dev_info_17d3_1160, + &pci_dev_info_17d3_1210, + &pci_dev_info_17d3_1220, + &pci_dev_info_17d3_1230, + &pci_dev_info_17d3_1260, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d5[] = { + &pci_dev_info_17d5_5831, + &pci_dev_info_17d5_5832, + NULL +}; +#endif +#define pci_dev_list_17de NULL +#define pci_dev_list_17ee NULL +#define pci_dev_list_17f2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17fe[] = { + &pci_dev_info_17fe_2120, + &pci_dev_info_17fe_2220, + NULL +}; +#endif +#define pci_dev_list_17ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1814[] = { + &pci_dev_info_1814_0101, + &pci_dev_info_1814_0200, + &pci_dev_info_1814_0201, + &pci_dev_info_1814_0301, + &pci_dev_info_1814_0401, + NULL +}; +#endif +#define pci_dev_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1822[] = { + &pci_dev_info_1822_4e35, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182d[] = { + &pci_dev_info_182d_3069, + &pci_dev_info_182d_9790, + NULL +}; +#endif +#define pci_dev_list_1830 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_183b[] = { + &pci_dev_info_183b_08a7, + &pci_dev_info_183b_08a8, + &pci_dev_info_183b_08a9, + NULL +}; +#endif +#define pci_dev_list_1849 NULL +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#define pci_dev_list_1854 NULL +#define pci_dev_list_185b NULL +#define pci_dev_list_185f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1864[] = { + &pci_dev_info_1864_2110, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1867[] = { + &pci_dev_info_1867_5a44, + &pci_dev_info_1867_5a45, + &pci_dev_info_1867_5a46, + &pci_dev_info_1867_6278, + &pci_dev_info_1867_6282, + NULL +}; +#endif +#define pci_dev_list_187e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#define pci_dev_list_1890 NULL +#define pci_dev_list_1894 NULL +#define pci_dev_list_1896 NULL +#define pci_dev_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ac[] = { + &pci_dev_info_18ac_d500, + &pci_dev_info_18ac_d810, + &pci_dev_info_18ac_d820, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18b8[] = { + &pci_dev_info_18b8_b001, + NULL +}; +#endif +#define pci_dev_list_18bc NULL +#define pci_dev_list_18c8 NULL +#define pci_dev_list_18c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ca[] = { + &pci_dev_info_18ca_0020, + &pci_dev_info_18ca_0040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18d2[] = { + &pci_dev_info_18d2_3069, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18dd[] = { + &pci_dev_info_18dd_4c6f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18e6[] = { + &pci_dev_info_18e6_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ec[] = { + &pci_dev_info_18ec_c006, + &pci_dev_info_18ec_c045, + &pci_dev_info_18ec_c050, + &pci_dev_info_18ec_c058, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f7[] = { + &pci_dev_info_18f7_0001, + &pci_dev_info_18f7_0002, + &pci_dev_info_18f7_0004, + &pci_dev_info_18f7_0005, + &pci_dev_info_18f7_000a, + NULL +}; +#endif +#define pci_dev_list_18fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1923[] = { + &pci_dev_info_1923_0100, + NULL +}; +#endif +#define pci_dev_list_1924 NULL +#define pci_dev_list_192e NULL +#define pci_dev_list_1931 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1942[] = { + &pci_dev_info_1942_e511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1957[] = { + &pci_dev_info_1957_0080, + &pci_dev_info_1957_0081, + &pci_dev_info_1957_0082, + &pci_dev_info_1957_0083, + &pci_dev_info_1957_0084, + &pci_dev_info_1957_0085, + &pci_dev_info_1957_0086, + &pci_dev_info_1957_0087, + NULL +}; +#endif +#define pci_dev_list_1958 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1966[] = { + &pci_dev_info_1966_1975, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_196a[] = { + &pci_dev_info_196a_0101, + &pci_dev_info_196a_0102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_197b[] = { + &pci_dev_info_197b_2360, + &pci_dev_info_197b_2363, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1989[] = { + &pci_dev_info_1989_0001, + &pci_dev_info_1989_8001, + NULL +}; +#endif +#define pci_dev_list_1993 NULL +#define pci_dev_list_19a8 NULL +#define pci_dev_list_19ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ae[] = { + &pci_dev_info_19ae_0520, + NULL +}; +#endif +#define pci_dev_list_19d4 NULL +#define pci_dev_list_19e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc0[] = { + &pci_dev_info_1fc0_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc1[] = { + &pci_dev_info_1fc1_000d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fce[] = { + &pci_dev_info_1fce_0001, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0020, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_0022, + &pci_dev_info_3388_0026, + &pci_dev_info_3388_101a, + &pci_dev_info_3388_101b, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3842[] = { + &pci_dev_info_3842_c370, + NULL +}; +#endif +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_000d, + &pci_dev_info_3d3d_0011, + &pci_dev_info_3d3d_0012, + &pci_dev_info_3d3d_0013, + &pci_dev_info_3d3d_0020, + &pci_dev_info_3d3d_0022, + &pci_dev_info_3d3d_0024, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_07a1, + &pci_dev_info_3d3d_07a2, + &pci_dev_info_3d3d_07a3, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4144[] = { + &pci_dev_info_4144_0044, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#define pci_dev_list_4321 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0016, + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_494f[] = { + &pci_dev_info_494f_10e8, + NULL +}; +#endif +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4c53[] = { + &pci_dev_info_4c53_0000, + &pci_dev_info_4c53_0001, + NULL +}; +#endif +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5168[] = { + &pci_dev_info_5168_0301, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_544c[] = { + &pci_dev_info_544c_0350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5654[] = { + &pci_dev_info_5654_3132, + NULL +}; +#endif +#define pci_dev_list_5700 NULL +#define pci_dev_list_5851 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + &pci_dev_info_6666_0004, + &pci_dev_info_6666_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_7063[] = { + &pci_dev_info_7063_2000, + &pci_dev_info_7063_3000, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +#define pci_dev_list_807d NULL +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0309, + &pci_dev_info_8086_030d, + &pci_dev_info_8086_0326, + &pci_dev_info_8086_0327, + &pci_dev_info_8086_0329, + &pci_dev_info_8086_032a, + &pci_dev_info_8086_032c, + &pci_dev_info_8086_0330, + &pci_dev_info_8086_0331, + &pci_dev_info_8086_0332, + &pci_dev_info_8086_0333, + &pci_dev_info_8086_0334, + &pci_dev_info_8086_0335, + &pci_dev_info_8086_0336, + &pci_dev_info_8086_0340, + &pci_dev_info_8086_0341, + &pci_dev_info_8086_0370, + &pci_dev_info_8086_0371, + &pci_dev_info_8086_0372, + &pci_dev_info_8086_0373, + &pci_dev_info_8086_0374, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0500, + &pci_dev_info_8086_0501, + &pci_dev_info_8086_0502, + &pci_dev_info_8086_0503, + &pci_dev_info_8086_0510, + &pci_dev_info_8086_0511, + &pci_dev_info_8086_0512, + &pci_dev_info_8086_0513, + &pci_dev_info_8086_0514, + &pci_dev_info_8086_0515, + &pci_dev_info_8086_0516, + &pci_dev_info_8086_0530, + &pci_dev_info_8086_0531, + &pci_dev_info_8086_0532, + &pci_dev_info_8086_0533, + &pci_dev_info_8086_0534, + &pci_dev_info_8086_0535, + &pci_dev_info_8086_0536, + &pci_dev_info_8086_0537, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_061f, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100a, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1013, + &pci_dev_info_8086_1014, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1016, + &pci_dev_info_8086_1017, + &pci_dev_info_8086_1018, + &pci_dev_info_8086_1019, + &pci_dev_info_8086_101a, + &pci_dev_info_8086_101d, + &pci_dev_info_8086_101e, + &pci_dev_info_8086_1026, + &pci_dev_info_8086_1027, + &pci_dev_info_8086_1028, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1043, + &pci_dev_info_8086_1048, + &pci_dev_info_8086_104b, + &pci_dev_info_8086_1050, + &pci_dev_info_8086_1051, + &pci_dev_info_8086_1052, + &pci_dev_info_8086_1053, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_105e, + &pci_dev_info_8086_105f, + &pci_dev_info_8086_1060, + &pci_dev_info_8086_1064, + &pci_dev_info_8086_1065, + &pci_dev_info_8086_1066, + &pci_dev_info_8086_1067, + &pci_dev_info_8086_1068, + &pci_dev_info_8086_1069, + &pci_dev_info_8086_106a, + &pci_dev_info_8086_106b, + &pci_dev_info_8086_1075, + &pci_dev_info_8086_1076, + &pci_dev_info_8086_1077, + &pci_dev_info_8086_1078, + &pci_dev_info_8086_1079, + &pci_dev_info_8086_107a, + &pci_dev_info_8086_107b, + &pci_dev_info_8086_107c, + &pci_dev_info_8086_107d, + &pci_dev_info_8086_107e, + &pci_dev_info_8086_107f, + &pci_dev_info_8086_1080, + &pci_dev_info_8086_1081, + &pci_dev_info_8086_1082, + &pci_dev_info_8086_1083, + &pci_dev_info_8086_1084, + &pci_dev_info_8086_1085, + &pci_dev_info_8086_1086, + &pci_dev_info_8086_1087, + &pci_dev_info_8086_1089, + &pci_dev_info_8086_108a, + &pci_dev_info_8086_108b, + &pci_dev_info_8086_108c, + &pci_dev_info_8086_1096, + &pci_dev_info_8086_1097, + &pci_dev_info_8086_1098, + &pci_dev_info_8086_1099, + &pci_dev_info_8086_109a, + &pci_dev_info_8086_1107, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123e, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_1a38, + &pci_dev_info_8086_1a48, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c1, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24ca, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cc, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_24d0, + &pci_dev_info_8086_24d1, + &pci_dev_info_8086_24d2, + &pci_dev_info_8086_24d3, + &pci_dev_info_8086_24d4, + &pci_dev_info_8086_24d5, + &pci_dev_info_8086_24d6, + &pci_dev_info_8086_24d7, + &pci_dev_info_8086_24db, + &pci_dev_info_8086_24dc, + &pci_dev_info_8086_24dd, + &pci_dev_info_8086_24de, + &pci_dev_info_8086_24df, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_254c, + &pci_dev_info_8086_2550, + &pci_dev_info_8086_2551, + &pci_dev_info_8086_2552, + &pci_dev_info_8086_2553, + &pci_dev_info_8086_2554, + &pci_dev_info_8086_255d, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2571, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_2573, + &pci_dev_info_8086_2576, + &pci_dev_info_8086_2578, + &pci_dev_info_8086_2579, + &pci_dev_info_8086_257b, + &pci_dev_info_8086_257e, + &pci_dev_info_8086_2580, + &pci_dev_info_8086_2581, + &pci_dev_info_8086_2582, + &pci_dev_info_8086_2584, + &pci_dev_info_8086_2585, + &pci_dev_info_8086_2588, + &pci_dev_info_8086_2589, + &pci_dev_info_8086_258a, + &pci_dev_info_8086_2590, + &pci_dev_info_8086_2591, + &pci_dev_info_8086_2592, + &pci_dev_info_8086_25a1, + &pci_dev_info_8086_25a2, + &pci_dev_info_8086_25a3, + &pci_dev_info_8086_25a4, + &pci_dev_info_8086_25a6, + &pci_dev_info_8086_25a7, + &pci_dev_info_8086_25a9, + &pci_dev_info_8086_25aa, + &pci_dev_info_8086_25ab, + &pci_dev_info_8086_25ac, + &pci_dev_info_8086_25ad, + &pci_dev_info_8086_25ae, + &pci_dev_info_8086_25b0, + &pci_dev_info_8086_25c0, + &pci_dev_info_8086_25d0, + &pci_dev_info_8086_25d4, + &pci_dev_info_8086_25d8, + &pci_dev_info_8086_25e2, + &pci_dev_info_8086_25e3, + &pci_dev_info_8086_25e4, + &pci_dev_info_8086_25e5, + &pci_dev_info_8086_25e6, + &pci_dev_info_8086_25e7, + &pci_dev_info_8086_25e8, + &pci_dev_info_8086_25f0, + &pci_dev_info_8086_25f1, + &pci_dev_info_8086_25f3, + &pci_dev_info_8086_25f5, + &pci_dev_info_8086_25f6, + &pci_dev_info_8086_25f7, + &pci_dev_info_8086_25f8, + &pci_dev_info_8086_25f9, + &pci_dev_info_8086_25fa, + &pci_dev_info_8086_2600, + &pci_dev_info_8086_2601, + &pci_dev_info_8086_2602, + &pci_dev_info_8086_2603, + &pci_dev_info_8086_2604, + &pci_dev_info_8086_2605, + &pci_dev_info_8086_2606, + &pci_dev_info_8086_2607, + &pci_dev_info_8086_2608, + &pci_dev_info_8086_2609, + &pci_dev_info_8086_260a, + &pci_dev_info_8086_260c, + &pci_dev_info_8086_2610, + &pci_dev_info_8086_2611, + &pci_dev_info_8086_2612, + &pci_dev_info_8086_2613, + &pci_dev_info_8086_2614, + &pci_dev_info_8086_2615, + &pci_dev_info_8086_2617, + &pci_dev_info_8086_2618, + &pci_dev_info_8086_2619, + &pci_dev_info_8086_261a, + &pci_dev_info_8086_261b, + &pci_dev_info_8086_261c, + &pci_dev_info_8086_261d, + &pci_dev_info_8086_261e, + &pci_dev_info_8086_2620, + &pci_dev_info_8086_2621, + &pci_dev_info_8086_2622, + &pci_dev_info_8086_2623, + &pci_dev_info_8086_2624, + &pci_dev_info_8086_2625, + &pci_dev_info_8086_2626, + &pci_dev_info_8086_2627, + &pci_dev_info_8086_2640, + &pci_dev_info_8086_2641, + &pci_dev_info_8086_2642, + &pci_dev_info_8086_2651, + &pci_dev_info_8086_2652, + &pci_dev_info_8086_2653, + &pci_dev_info_8086_2658, + &pci_dev_info_8086_2659, + &pci_dev_info_8086_265a, + &pci_dev_info_8086_265b, + &pci_dev_info_8086_265c, + &pci_dev_info_8086_2660, + &pci_dev_info_8086_2662, + &pci_dev_info_8086_2664, + &pci_dev_info_8086_2666, + &pci_dev_info_8086_2668, + &pci_dev_info_8086_266a, + &pci_dev_info_8086_266c, + &pci_dev_info_8086_266d, + &pci_dev_info_8086_266e, + &pci_dev_info_8086_266f, + &pci_dev_info_8086_2670, + &pci_dev_info_8086_2680, + &pci_dev_info_8086_2681, + &pci_dev_info_8086_2682, + &pci_dev_info_8086_2683, + &pci_dev_info_8086_2688, + &pci_dev_info_8086_2689, + &pci_dev_info_8086_268a, + &pci_dev_info_8086_268b, + &pci_dev_info_8086_268c, + &pci_dev_info_8086_2690, + &pci_dev_info_8086_2692, + &pci_dev_info_8086_2694, + &pci_dev_info_8086_2696, + &pci_dev_info_8086_2698, + &pci_dev_info_8086_2699, + &pci_dev_info_8086_269a, + &pci_dev_info_8086_269b, + &pci_dev_info_8086_269e, + &pci_dev_info_8086_2770, + &pci_dev_info_8086_2771, + &pci_dev_info_8086_2772, + &pci_dev_info_8086_2774, + &pci_dev_info_8086_2775, + &pci_dev_info_8086_2776, + &pci_dev_info_8086_2778, + &pci_dev_info_8086_2779, + &pci_dev_info_8086_277a, + &pci_dev_info_8086_277c, + &pci_dev_info_8086_277d, + &pci_dev_info_8086_2782, + &pci_dev_info_8086_2792, + &pci_dev_info_8086_27a0, + &pci_dev_info_8086_27a1, + &pci_dev_info_8086_27a2, + &pci_dev_info_8086_27a6, + &pci_dev_info_8086_27b0, + &pci_dev_info_8086_27b8, + &pci_dev_info_8086_27b9, + &pci_dev_info_8086_27bd, + &pci_dev_info_8086_27c0, + &pci_dev_info_8086_27c1, + &pci_dev_info_8086_27c3, + &pci_dev_info_8086_27c4, + &pci_dev_info_8086_27c5, + &pci_dev_info_8086_27c6, + &pci_dev_info_8086_27c8, + &pci_dev_info_8086_27c9, + &pci_dev_info_8086_27ca, + &pci_dev_info_8086_27cb, + &pci_dev_info_8086_27cc, + &pci_dev_info_8086_27d0, + &pci_dev_info_8086_27d2, + &pci_dev_info_8086_27d4, + &pci_dev_info_8086_27d6, + &pci_dev_info_8086_27d8, + &pci_dev_info_8086_27da, + &pci_dev_info_8086_27dc, + &pci_dev_info_8086_27dd, + &pci_dev_info_8086_27de, + &pci_dev_info_8086_27df, + &pci_dev_info_8086_27e0, + &pci_dev_info_8086_27e2, + &pci_dev_info_8086_2810, + &pci_dev_info_8086_2811, + &pci_dev_info_8086_2812, + &pci_dev_info_8086_2814, + &pci_dev_info_8086_2815, + &pci_dev_info_8086_2820, + &pci_dev_info_8086_2821, + &pci_dev_info_8086_2822, + &pci_dev_info_8086_2824, + &pci_dev_info_8086_2825, + &pci_dev_info_8086_2828, + &pci_dev_info_8086_2829, + &pci_dev_info_8086_282a, + &pci_dev_info_8086_2830, + &pci_dev_info_8086_2831, + &pci_dev_info_8086_2832, + &pci_dev_info_8086_2834, + &pci_dev_info_8086_2835, + &pci_dev_info_8086_2836, + &pci_dev_info_8086_283a, + &pci_dev_info_8086_283e, + &pci_dev_info_8086_283f, + &pci_dev_info_8086_2841, + &pci_dev_info_8086_2843, + &pci_dev_info_8086_2844, + &pci_dev_info_8086_2847, + &pci_dev_info_8086_2849, + &pci_dev_info_8086_284b, + &pci_dev_info_8086_284f, + &pci_dev_info_8086_2850, + &pci_dev_info_8086_2970, + &pci_dev_info_8086_2971, + &pci_dev_info_8086_2972, + &pci_dev_info_8086_2973, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3200, + &pci_dev_info_8086_3340, + &pci_dev_info_8086_3341, + &pci_dev_info_8086_3500, + &pci_dev_info_8086_3501, + &pci_dev_info_8086_3504, + &pci_dev_info_8086_3505, + &pci_dev_info_8086_350c, + &pci_dev_info_8086_350d, + &pci_dev_info_8086_3510, + &pci_dev_info_8086_3511, + &pci_dev_info_8086_3514, + &pci_dev_info_8086_3515, + &pci_dev_info_8086_3518, + &pci_dev_info_8086_3519, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3581, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_3584, + &pci_dev_info_8086_3585, + &pci_dev_info_8086_3590, + &pci_dev_info_8086_3591, + &pci_dev_info_8086_3592, + &pci_dev_info_8086_3593, + &pci_dev_info_8086_3594, + &pci_dev_info_8086_3595, + &pci_dev_info_8086_3596, + &pci_dev_info_8086_3597, + &pci_dev_info_8086_3598, + &pci_dev_info_8086_3599, + &pci_dev_info_8086_359a, + &pci_dev_info_8086_359b, + &pci_dev_info_8086_359e, + &pci_dev_info_8086_4220, + &pci_dev_info_8086_4223, + &pci_dev_info_8086_4224, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7050, + &pci_dev_info_8086_7051, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_8500, + &pci_dev_info_8086_9000, + &pci_dev_info_8086_9001, + &pci_dev_info_8086_9004, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + NULL +}; +#define pci_dev_list_8401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8912 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8c4a[] = { + &pci_dev_info_8c4a_1980, + NULL +}; +#endif +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_0078, + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7710, + &pci_dev_info_9004_7711, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + NULL +}; +#endif + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_dev_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_dev_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_dev_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_dev_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_dev_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_dev_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_dev_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_dev_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_dev_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_dev_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_dev_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_dev_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_dev_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_dev_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_dev_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_dev_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_dev_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_dev_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_dev_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_dev_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_dev_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_dev_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_dev_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_dev_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_dev_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_dev_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_dev_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_dev_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_dev_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_dev_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_dev_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_dev_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_dev_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_dev_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_dev_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_dev_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_dev_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_dev_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_dev_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_dev_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_dev_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_dev_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_dev_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_dev_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_dev_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_dev_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_dev_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_dev_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_dev_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_dev_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_dev_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_dev_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_dev_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_dev_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_dev_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_dev_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_dev_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_dev_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_dev_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_dev_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_dev_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_dev_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_dev_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_dev_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_dev_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_dev_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_dev_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_dev_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_dev_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_dev_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_dev_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_dev_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_dev_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_dev_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_dev_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_dev_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_dev_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_dev_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_dev_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_dev_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_dev_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_dev_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_dev_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_dev_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_dev_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_dev_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_dev_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_dev_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_dev_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_dev_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_dev_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_dev_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_dev_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_dev_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_dev_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_dev_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_dev_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_dev_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_dev_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_dev_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_dev_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_dev_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_dev_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_dev_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_dev_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_dev_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_dev_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_dev_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_dev_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_dev_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_dev_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_dev_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_dev_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_dev_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_dev_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_dev_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_dev_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_dev_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_dev_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_dev_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_dev_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_dev_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_dev_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_dev_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_dev_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_dev_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_dev_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_dev_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_dev_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_ss_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_ss_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_ss_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_ss_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_ss_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_ss_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_ss_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_ss_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_ss_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_ss_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_ss_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_ss_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_ss_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_ss_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_ss_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_ss_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_ss_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_ss_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_ss_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_ss_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_ss_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_ss_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_ss_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_ss_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_ss_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_ss_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_ss_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_ss_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_ss_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_ss_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_ss_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_ss_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_ss_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_ss_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_ss_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_ss_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_ss_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_ss_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_ss_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_ss_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_ss_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_ss_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_ss_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_ss_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_ss_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_ss_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_ss_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_ss_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_ss_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_ss_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_ss_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_ss_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_ss_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_ss_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_ss_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_ss_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_ss_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_ss_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_ss_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_ss_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_ss_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_ss_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_ss_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_ss_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_ss_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_ss_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_ss_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_ss_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_ss_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_ss_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_ss_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_ss_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_ss_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_ss_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_ss_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_ss_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_ss_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_ss_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_ss_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_ss_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_ss_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_ss_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_ss_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_ss_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_ss_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_ss_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_ss_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_ss_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_ss_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_ss_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_ss_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_ss_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_ss_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_ss_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_ss_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_ss_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_ss_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_ss_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_ss_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_ss_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_ss_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_ss_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_ss_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_ss_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_ss_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_ss_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_ss_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_ss_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_ss_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_ss_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_ss_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_ss_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_ss_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_ss_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_ss_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_ss_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_ss_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_ss_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_ss_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_ss_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_ss_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_ss_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_ss_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_ss_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_ss_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_ss_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_ss_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_ss_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_ss_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif + {0x0000, NULL, NULL} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciInfo.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciInfo.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciInfo.h (revision 51223) @@ -0,0 +1,729 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.156 2003/10/30 15:26:33 tsi Exp $ */ + +/* + * Copyright (c) 1995-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains macros for the PCI Vendor and Device IDs for video + * cards plus a few other things that are needed in drivers or elsewhere. + * This information is used in several ways: + * 1. It is used by drivers and/or other code. + * 2. It is used by the pciid2c.pl script to determine what vendor data to + * include in the pcidata module that the X server loads. + * 3. A side-effect of 2. affects how config-generation works for + * otherwise "unknown" cards. + * + * Don't add entries here for vendors that don't make video cards, + * or for non-video devices unless they're needed by a driver or elsewhere. + * A comprehensive set of PCI vendor, device and subsystem data is + * auto-generated from the ../etc/pci.ids file using the pciids2c.pl script, + * and is used in both the scanpci module and the scanpci utility. Don't + * modify the pci.ids file. If new/corrected entries are required, add them + * to ../etc/extrapci.ids. + */ + +#ifndef _XF86_PCIINFO_H +#define _XF86_PCIINFO_H + +/* PCI Pseudo Vendor */ +#define PCI_VENDOR_GENERIC 0x00FF + +#define PCI_VENDOR_REAL3D 0x003D +#define PCI_VENDOR_COMPAQ 0x0E11 +#define PCI_VENDOR_ATI 0x1002 +#define PCI_VENDOR_AVANCE 0x1005 +#define PCI_VENDOR_TSENG 0x100C +#define PCI_VENDOR_NS 0x100B +#define PCI_VENDOR_WEITEK 0x100E +#define PCI_VENDOR_VIDEOLOGIC 0x1010 +#define PCI_VENDOR_DIGITAL 0x1011 +#define PCI_VENDOR_CIRRUS 0x1013 +#define PCI_VENDOR_AMD 0x1022 +#define PCI_VENDOR_TRIDENT 0x1023 +#define PCI_VENDOR_ALI 0x1025 +#define PCI_VENDOR_DELL 0x1028 +#define PCI_VENDOR_MATROX 0x102B +#define PCI_VENDOR_CHIPSTECH 0x102C +#define PCI_VENDOR_MIRO 0x1031 +#define PCI_VENDOR_NEC 0x1033 +#define PCI_VENDOR_SIS 0x1039 +#define PCI_VENDOR_HP 0x103C +#define PCI_VENDOR_SGS 0x104A +#define PCI_VENDOR_TI 0x104C +#define PCI_VENDOR_SONY 0x104D +#define PCI_VENDOR_OAK 0x104E +#define PCI_VENDOR_MOTOROLA 0x1057 +#define PCI_VENDOR_NUMNINE 0x105D +#define PCI_VENDOR_CYRIX 0x1078 +#define PCI_VENDOR_SUN 0x108E +#define PCI_VENDOR_DIAMOND 0x1092 +#define PCI_VENDOR_BROOKTREE 0x109E +#define PCI_VENDOR_NEOMAGIC 0x10C8 +#define PCI_VENDOR_NVIDIA 0x10DE +#define PCI_VENDOR_IMS 0x10E0 +#define PCI_VENDOR_INTEGRAPHICS 0x10EA +#define PCI_VENDOR_ALLIANCE 0x1142 +#define PCI_VENDOR_RENDITION 0x1163 +#define PCI_VENDOR_3DFX 0x121A +#define PCI_VENDOR_SMI 0x126F +#define PCI_VENDOR_TRITECH 0x1292 +#define PCI_VENDOR_NVIDIA_SGS 0x12D2 +#define PCI_VENDOR_VMWARE 0x15AD +#define PCI_VENDOR_3DLABS 0x3D3D +#define PCI_VENDOR_AVANCE_2 0x4005 +#define PCI_VENDOR_HERCULES 0x4843 +#define PCI_VENDOR_S3 0x5333 +#define PCI_VENDOR_INTEL 0x8086 +#define PCI_VENDOR_ARK 0xEDD8 + + +/* Generic */ +#define PCI_CHIP_VGA 0x0000 +#define PCI_CHIP_8514 0x0001 + +/* Real 3D */ +#define PCI_CHIP_I740_PCI 0x00D1 + +/* Compaq */ +#define PCI_CHIP_QV1280 0x3033 + +/* ATI */ +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_4155 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_4A4F 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_R420_4A54 0x4A54 +#define PCI_CHIP_R481_4B49 0x4B49 +#define PCI_CHIP_R481_4B4A 0x4B4A +#define PCI_CHIP_R481_4B4B 0x4B4B +#define PCI_CHIP_R481_4B4C 0x4B4C +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R430_554C 0x554C +#define PCI_CHIP_R430_554D 0x554D +#define PCI_CHIP_R430_554E 0x554E +#define PCI_CHIP_R430_554F 0x554F +#define PCI_CHIP_R423_5550 0x5550 +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_RV410_564A 0x564A +#define PCI_CHIP_RV410_564B 0x564B +#define PCI_CHIP_RV410_564F 0x564F +#define PCI_CHIP_RV410_5652 0x5652 +#define PCI_CHIP_RV410_5653 0x5653 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RS480_5954 0x5954 +#define PCI_CHIP_RS480_5955 0x5955 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RS482_5974 0x5974 +#define PCI_CHIP_RS482_5975 0x5975 +#define PCI_CHIP_RS400_5A41 0x5A41 +#define PCI_CHIP_RS400_5A42 0x5A42 +#define PCI_CHIP_RC410_5A61 0x5A61 +#define PCI_CHIP_RC410_5A62 0x5A62 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R430_5D48 0x5D48 +#define PCI_CHIP_R430_5D49 0x5D49 +#define PCI_CHIP_R430_5D4A 0x5D4A +#define PCI_CHIP_R480_5D4C 0x5D4C +#define PCI_CHIP_R480_5D4D 0x5D4D +#define PCI_CHIP_R480_5D4E 0x5D4E +#define PCI_CHIP_R480_5D4F 0x5D4F +#define PCI_CHIP_R480_5D50 0x5D50 +#define PCI_CHIP_R480_5D52 0x5D52 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RV410_5E48 0x5E48 +#define PCI_CHIP_RV410_5E4A 0x5E4A +#define PCI_CHIP_RV410_5E4B 0x5E4B +#define PCI_CHIP_RV410_5E4C 0x5E4C +#define PCI_CHIP_RV410_5E4D 0x5E4D +#define PCI_CHIP_RV410_5E4F 0x5E4F +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + +/* Avance Logic */ +#define PCI_CHIP_ALG2064 0x2064 +#define PCI_CHIP_ALG2301 0x2301 +#define PCI_CHIP_ALG2501 0x2501 + +/* Tseng */ +#define PCI_CHIP_ET4000_W32P_A 0x3202 +#define PCI_CHIP_ET4000_W32P_B 0x3205 +#define PCI_CHIP_ET4000_W32P_D 0x3206 +#define PCI_CHIP_ET4000_W32P_C 0x3207 +#define PCI_CHIP_ET6000 0x3208 +#define PCI_CHIP_ET6300 0x4702 + +/* Weitek */ +#define PCI_CHIP_P9000 0x9001 +#define PCI_CHIP_P9100 0x9100 + +/* Digital */ +#define PCI_CHIP_DC21050 0x0001 +#define PCI_CHIP_DEC21030 0x0004 +#define PCI_CHIP_TGA2 0x000D + +/* Cirrus Logic */ +#define PCI_CHIP_GD7548 0x0038 +#define PCI_CHIP_GD7555 0x0040 +#define PCI_CHIP_GD5430 0x00A0 +#define PCI_CHIP_GD5434_4 0x00A4 +#define PCI_CHIP_GD5434_8 0x00A8 +#define PCI_CHIP_GD5436 0x00AC +#define PCI_CHIP_GD5446 0x00B8 +#define PCI_CHIP_GD5480 0x00BC +#define PCI_CHIP_GD5462 0x00D0 +#define PCI_CHIP_GD5464 0x00D4 +#define PCI_CHIP_GD5464BD 0x00D5 +#define PCI_CHIP_GD5465 0x00D6 +#define PCI_CHIP_6729 0x1100 +#define PCI_CHIP_6832 0x1110 +#define PCI_CHIP_GD7542 0x1200 +#define PCI_CHIP_GD7543 0x1202 +#define PCI_CHIP_GD7541 0x1204 + +/* AMD */ +#define PCI_CHIP_AMD761 0x700E + +/* Trident */ +#define PCI_CHIP_2100 0x2100 +#define PCI_CHIP_8400 0x8400 +#define PCI_CHIP_8420 0x8420 +#define PCI_CHIP_8500 0x8500 +#define PCI_CHIP_8520 0x8520 +#define PCI_CHIP_8600 0x8600 +#define PCI_CHIP_8620 0x8620 +#define PCI_CHIP_8820 0x8820 +#define PCI_CHIP_9320 0x9320 +#define PCI_CHIP_9388 0x9388 +#define PCI_CHIP_9397 0x9397 +#define PCI_CHIP_939A 0x939A +#define PCI_CHIP_9420 0x9420 +#define PCI_CHIP_9440 0x9440 +#define PCI_CHIP_9520 0x9520 +#define PCI_CHIP_9525 0x9525 +#define PCI_CHIP_9540 0x9540 +#define PCI_CHIP_9660 0x9660 +#define PCI_CHIP_9750 0x9750 +#define PCI_CHIP_9850 0x9850 +#define PCI_CHIP_9880 0x9880 +#define PCI_CHIP_9910 0x9910 + +/* ALI */ +#define PCI_CHIP_M1435 0x1435 + +/* Matrox */ +#define PCI_CHIP_MGA2085 0x0518 +#define PCI_CHIP_MGA2064 0x0519 +#define PCI_CHIP_MGA1064 0x051A +#define PCI_CHIP_MGA2164 0x051B +#define PCI_CHIP_MGA2164_AGP 0x051F +#define PCI_CHIP_MGAG200_PCI 0x0520 +#define PCI_CHIP_MGAG200 0x0521 +#define PCI_CHIP_MGAG400 0x0525 +#define PCI_CHIP_MGAG550 0x2527 +#define PCI_CHIP_IMPRESSION 0x0D10 +#define PCI_CHIP_MGAG100_PCI 0x1000 +#define PCI_CHIP_MGAG100 0x1001 + +#define PCI_CARD_G400_TH 0x2179 +#define PCI_CARD_MILL_G200_SD 0xFF00 +#define PCI_CARD_PROD_G100_SD 0xFF01 +#define PCI_CARD_MYST_G200_SD 0xFF02 +#define PCI_CARD_MILL_G200_SG 0xFF03 +#define PCI_CARD_MARV_G200_SD 0xFF04 + +/* Chips & Tech */ +#define PCI_CHIP_65545 0x00D8 +#define PCI_CHIP_65548 0x00DC +#define PCI_CHIP_65550 0x00E0 +#define PCI_CHIP_65554 0x00E4 +#define PCI_CHIP_65555 0x00E5 +#define PCI_CHIP_68554 0x00F4 +#define PCI_CHIP_69000 0x00C0 +#define PCI_CHIP_69030 0x0C30 + +/* Miro */ +#define PCI_CHIP_ZR36050 0x5601 + +/* NEC */ +#define PCI_CHIP_POWER_VR 0x0046 + +/* SiS */ +#define PCI_CHIP_SG86C201 0x0001 +#define PCI_CHIP_SG86C202 0x0002 +#define PCI_CHIP_SG85C503 0x0008 +#define PCI_CHIP_SIS5597 0x0200 +/* Agregado por Carlos Duclos & Manuel Jander */ +#define PCI_CHIP_SIS82C204 0x0204 +#define PCI_CHIP_SG86C205 0x0205 +#define PCI_CHIP_SG86C215 0x0215 +#define PCI_CHIP_SG86C225 0x0225 +#define PCI_CHIP_85C501 0x0406 +#define PCI_CHIP_85C496 0x0496 +#define PCI_CHIP_85C601 0x0601 +#define PCI_CHIP_85C5107 0x5107 +#define PCI_CHIP_85C5511 0x5511 +#define PCI_CHIP_85C5513 0x5513 +#define PCI_CHIP_SIS5571 0x5571 +#define PCI_CHIP_SIS5597_2 0x5597 +#define PCI_CHIP_SIS530 0x6306 +#define PCI_CHIP_SIS6326 0x6326 +#define PCI_CHIP_SIS7001 0x7001 +#define PCI_CHIP_SIS300 0x0300 +#define PCI_CHIP_SIS315H 0x0310 +#define PCI_CHIP_SIS315PRO 0x0325 +#define PCI_CHIP_SIS330 0x0330 +#define PCI_CHIP_SIS630 0x6300 +#define PCI_CHIP_SIS540 0x5300 +#define PCI_CHIP_SIS550 0x5315 +#define PCI_CHIP_SIS650 0x6325 +#define PCI_CHIP_SIS730 0x7300 + +/* Hewlett-Packard */ +#define PCI_CHIP_ELROY 0x1054 +#define PCI_CHIP_ZX1_SBA 0x1229 +#define PCI_CHIP_ZX1_IOC 0x122A +#define PCI_CHIP_ZX1_LBA 0x122E /* a.k.a. Mercury */ +#define PCI_CHIP_ZX1_AGP8 0x12B4 /* a.k.a. QuickSilver */ +#define PCI_CHIP_ZX2_LBA 0x12EE +#define PCI_CHIP_ZX2_SBA 0x4030 +#define PCI_CHIP_ZX2_IOC 0x4031 +#define PCI_CHIP_ZX2_PCIE 0x4037 + +/* SGS */ +#define PCI_CHIP_STG2000 0x0008 +#define PCI_CHIP_STG1764 0x0009 +#define PCI_CHIP_KYROII 0x0010 + +/* Texas Instruments */ +#define PCI_CHIP_TI_PERMEDIA 0x3D04 +#define PCI_CHIP_TI_PERMEDIA2 0x3D07 + +/* Oak */ +#define PCI_CHIP_OTI107 0x0107 + +/* Number Nine */ +#define PCI_CHIP_I128 0x2309 +#define PCI_CHIP_I128_2 0x2339 +#define PCI_CHIP_I128_T2R 0x493D +#define PCI_CHIP_I128_T2R4 0x5348 + +/* Sun */ +#define PCI_CHIP_EBUS 0x1000 +#define PCI_CHIP_HAPPY_MEAL 0x1001 +#define PCI_CHIP_SIMBA 0x5000 +#define PCI_CHIP_PSYCHO 0x8000 +#define PCI_CHIP_SCHIZO 0x8001 +#define PCI_CHIP_SABRE 0xA000 +#define PCI_CHIP_HUMMINGBIRD 0xA001 + +/* BrookTree */ +#define PCI_CHIP_BT848 0x0350 +#define PCI_CHIP_BT849 0x0351 + +/* NVIDIA */ +#define PCI_CHIP_NV1 0x0008 +#define PCI_CHIP_DAC64 0x0009 +#define PCI_CHIP_TNT 0x0020 +#define PCI_CHIP_TNT2 0x0028 +#define PCI_CHIP_UTNT2 0x0029 +#define PCI_CHIP_VTNT2 0x002C +#define PCI_CHIP_UVTNT2 0x002D +#define PCI_CHIP_ITNT2 0x00A0 +#define PCI_CHIP_GEFORCE_256 0x0100 +#define PCI_CHIP_GEFORCE_DDR 0x0101 +#define PCI_CHIP_QUADRO 0x0103 +#define PCI_CHIP_GEFORCE2_MX 0x0110 +#define PCI_CHIP_GEFORCE2_MX_100 0x0111 +#define PCI_CHIP_GEFORCE2_GO 0x0112 +#define PCI_CHIP_QUADRO2_MXR 0x0113 +#define PCI_CHIP_GEFORCE2_GTS 0x0150 +#define PCI_CHIP_GEFORCE2_TI 0x0151 +#define PCI_CHIP_GEFORCE2_ULTRA 0x0152 +#define PCI_CHIP_QUADRO2_PRO 0x0153 +#define PCI_CHIP_GEFORCE4_MX_460 0x0170 +#define PCI_CHIP_GEFORCE4_MX_440 0x0171 +#define PCI_CHIP_GEFORCE4_MX_420 0x0172 +#define PCI_CHIP_GEFORCE4_440_GO 0x0174 +#define PCI_CHIP_GEFORCE4_420_GO 0x0175 +#define PCI_CHIP_GEFORCE4_420_GO_M32 0x0176 +#define PCI_CHIP_QUADRO4_500XGL 0x0178 +#define PCI_CHIP_GEFORCE4_440_GO_M64 0x0179 +#define PCI_CHIP_QUADRO4_200 0x017A +#define PCI_CHIP_QUADRO4_550XGL 0x017B +#define PCI_CHIP_QUADRO4_500_GOGL 0x017C +#define PCI_CHIP_IGEFORCE2 0x01A0 +#define PCI_CHIP_GEFORCE3 0x0200 +#define PCI_CHIP_GEFORCE3_TI_200 0x0201 +#define PCI_CHIP_GEFORCE3_TI_500 0x0202 +#define PCI_CHIP_QUADRO_DCC 0x0203 +#define PCI_CHIP_GEFORCE4_TI_4600 0x0250 +#define PCI_CHIP_GEFORCE4_TI_4400 0x0251 +#define PCI_CHIP_GEFORCE4_TI_4200 0x0253 +#define PCI_CHIP_QUADRO4_900XGL 0x0258 +#define PCI_CHIP_QUADRO4_750XGL 0x0259 +#define PCI_CHIP_QUADRO4_700XGL 0x025B + +/* NVIDIA & SGS */ +#define PCI_CHIP_RIVA128 0x0018 + +/* IMS */ +#define PCI_CHIP_IMSTT128 0x9128 +#define PCI_CHIP_IMSTT3D 0x9135 + +/* Alliance Semiconductor */ +#define PCI_CHIP_AP6410 0x3210 +#define PCI_CHIP_AP6422 0x6422 +#define PCI_CHIP_AT24 0x6424 +#define PCI_CHIP_AT3D 0x643D + +/* 3dfx Interactive */ +#define PCI_CHIP_VOODOO_GRAPHICS 0x0001 +#define PCI_CHIP_VOODOO2 0x0002 +#define PCI_CHIP_BANSHEE 0x0003 +#define PCI_CHIP_VOODOO3 0x0005 +#define PCI_CHIP_VOODOO5 0x0009 + +#define PCI_CARD_VOODOO3_2000 0x0036 +#define PCI_CARD_VOODOO3_3000 0x003A + +/* Rendition */ +#define PCI_CHIP_V1000 0x0001 +#define PCI_CHIP_V2x00 0x2000 + +/* 3Dlabs */ +#define PCI_CHIP_300SX 0x0001 +#define PCI_CHIP_500TX 0x0002 +#define PCI_CHIP_DELTA 0x0003 +#define PCI_CHIP_PERMEDIA 0x0004 +#define PCI_CHIP_MX 0x0006 +#define PCI_CHIP_PERMEDIA2 0x0007 +#define PCI_CHIP_GAMMA 0x0008 +#define PCI_CHIP_PERMEDIA2V 0x0009 +#define PCI_CHIP_PERMEDIA3 0x000A +#define PCI_CHIP_PERMEDIA4 0x000C +#define PCI_CHIP_R4 0x000D +#define PCI_CHIP_GAMMA2 0x000E +#define PCI_CHIP_R4ALT 0x0011 + +/* S3 */ +#define PCI_CHIP_PLATO 0x0551 +#define PCI_CHIP_VIRGE 0x5631 +#define PCI_CHIP_TRIO 0x8811 +#define PCI_CHIP_AURORA64VP 0x8812 +#define PCI_CHIP_TRIO64UVP 0x8814 +#define PCI_CHIP_VIRGE_VX 0x883D +#define PCI_CHIP_868 0x8880 +#define PCI_CHIP_928 0x88B0 +#define PCI_CHIP_864_0 0x88C0 +#define PCI_CHIP_864_1 0x88C1 +#define PCI_CHIP_964_0 0x88D0 +#define PCI_CHIP_964_1 0x88D1 +#define PCI_CHIP_968 0x88F0 +#define PCI_CHIP_TRIO64V2_DXGX 0x8901 +#define PCI_CHIP_PLATO_PX 0x8902 +#define PCI_CHIP_Trio3D 0x8904 +#define PCI_CHIP_VIRGE_DXGX 0x8A01 +#define PCI_CHIP_VIRGE_GX2 0x8A10 +#define PCI_CHIP_Trio3D_2X 0x8A13 +#define PCI_CHIP_SAVAGE3D 0x8A20 +#define PCI_CHIP_SAVAGE3D_MV 0x8A21 +#define PCI_CHIP_SAVAGE4 0x8A22 +#define PCI_CHIP_PROSAVAGE_PM 0x8A25 +#define PCI_CHIP_PROSAVAGE_KM 0x8A26 +#define PCI_CHIP_VIRGE_MX 0x8C01 +#define PCI_CHIP_VIRGE_MXPLUS 0x8C02 +#define PCI_CHIP_VIRGE_MXP 0x8C03 +#define PCI_CHIP_SAVAGE_MX_MV 0x8C10 +#define PCI_CHIP_SAVAGE_MX 0x8C11 +#define PCI_CHIP_SAVAGE_IX_MV 0x8C12 +#define PCI_CHIP_SAVAGE_IX 0x8C13 +#define PCI_CHIP_SUPSAV_MX128 0x8C22 +#define PCI_CHIP_SUPSAV_MX64 0x8C24 +#define PCI_CHIP_SUPSAV_MX64C 0x8C26 +#define PCI_CHIP_SUPSAV_IX128SDR 0x8C2A +#define PCI_CHIP_SUPSAV_IX128DDR 0x8C2B +#define PCI_CHIP_SUPSAV_IX64SDR 0x8C2C +#define PCI_CHIP_SUPSAV_IX64DDR 0x8C2D +#define PCI_CHIP_SUPSAV_IXCSDR 0x8C2E +#define PCI_CHIP_SUPSAV_IXCDDR 0x8C2F +#define PCI_CHIP_S3TWISTER_P 0x8D01 +#define PCI_CHIP_S3TWISTER_K 0x8D02 +#define PCI_CHIP_PROSAVAGE_DDR 0x8D03 +#define PCI_CHIP_PROSAVAGE_DDRK 0x8D04 +#define PCI_CHIP_SAVAGE2000 0x9102 + +/* ARK Logic */ +#define PCI_CHIP_1000PV 0xA091 +#define PCI_CHIP_2000PV 0xA099 +#define PCI_CHIP_2000MT 0xA0A1 +#define PCI_CHIP_2000MI 0xA0A9 + +/* Tritech Microelectronics */ +#define PCI_CHIP_TR25202 0xFC02 + +/* Neomagic */ +#define PCI_CHIP_NM2070 0x0001 +#define PCI_CHIP_NM2090 0x0002 +#define PCI_CHIP_NM2093 0x0003 +#define PCI_CHIP_NM2097 0x0083 +#define PCI_CHIP_NM2160 0x0004 +#define PCI_CHIP_NM2200 0x0005 +#define PCI_CHIP_NM2230 0x0025 +#define PCI_CHIP_NM2360 0x0006 +#define PCI_CHIP_NM2380 0x0016 + +/* Intel */ +#define PCI_CHIP_I815_BRIDGE 0x1130 +#define PCI_CHIP_I815 0x1132 +#define PCI_CHIP_82801_P2P 0x244E +#define PCI_CHIP_845_G_BRIDGE 0x2560 +#define PCI_CHIP_845_G 0x2562 +#define PCI_CHIP_I830_M_BRIDGE 0x3575 +#define PCI_CHIP_I830_M 0x3577 +#define PCI_CHIP_I810_BRIDGE 0x7120 +#define PCI_CHIP_I810 0x7121 +#define PCI_CHIP_I810_DC100_BRIDGE 0x7122 +#define PCI_CHIP_I810_DC100 0x7123 +#define PCI_CHIP_I810_E_BRIDGE 0x7124 +#define PCI_CHIP_I810_E 0x7125 +#define PCI_CHIP_I740_AGP 0x7800 +#define PCI_CHIP_460GX_PXB 0x84CB +#define PCI_CHIP_460GX_SAC 0x84E0 +#define PCI_CHIP_460GX_GXB_2 0x84E2 /* PCI function 2 */ +#define PCI_CHIP_460GX_WXB 0x84E6 +#define PCI_CHIP_460GX_GXB_1 0x84EA /* PCI function 1 */ + +/* Silicon Motion Inc. */ +#define PCI_CHIP_SMI910 0x0910 +#define PCI_CHIP_SMI810 0x0810 +#define PCI_CHIP_SMI820 0x0820 +#define PCI_CHIP_SMI710 0x0710 +#define PCI_CHIP_SMI712 0x0712 +#define PCI_CHIP_SMI720 0x0720 +#define PCI_CHIP_SMI731 0x0730 + +/* VMware */ +#define PCI_CHIP_VMWARE0405 0x0405 +#define PCI_CHIP_VMWARE0710 0x0710 + +#endif /* _XF86_PCIINFO_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStdIds.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStdIds.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStdIds.h (revision 51223) @@ -0,0 +1,124639 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/scanpci/xf86PciStdIds.h,v 1.10 2006/01/27 12:27:34 alanh Exp $ */ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0071[] = "Nebula Electronics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0095[] = "Silicon Image, Inc. (Wrong ID)"; +static const char pci_device_0095_0680[] = "Ultra ATA/133 IDE RAID CONTROLLER CARD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00a7[] = "Teles AG (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_018a[] = "LevelOne"; +static const char pci_device_018a_0106[] = "FPC-0106TX misprogrammed [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_021b[] = "Compaq Computer Corporation"; +static const char pci_device_021b_8139[] = "HNE-300 (RealTek RTL8139c) [iPaq Networking]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0270[] = "Hauppauge computer works Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0291[] = "Davicom Semiconductor, Inc."; +static const char pci_device_0291_8212[] = "DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_02ac[] = "SpeedStream"; +static const char pci_device_02ac_1012[] = "1012 PCMCIA 10/100 Ethernet Card [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0357[] = "TTTech AG"; +static const char pci_device_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0432[] = "SCM Microsystems, Inc."; +static const char pci_device_0432_0001[] = "Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_045e[] = "Microsoft"; +static const char pci_device_045e_006e[] = "MN-510 802.11b wireless USB paddle"; +static const char pci_device_045e_00c2[] = "MN-710 wireless USB paddle"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_04cf[] = "Myson Century, Inc"; +static const char pci_device_04cf_8818[] = "CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_050d[] = "Belkin"; +static const char pci_device_050d_7050[] = "F5D7050 802.11g Wireless USB Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05e3[] = "CyberDoor"; +static const char pci_device_05e3_0701[] = "CBD516"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_066f[] = "Sigmatel Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +static const char pci_device_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_067b[] = "Prolific Technology, Inc."; +static const char pci_device_067b_3507[] = "PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0721[] = "Sapphire, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_07e2[] = "ELMEG Communication Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b49[] = "ASCII Corporation"; +static const char pci_device_0b49_064f[] = "Trance Vibrator"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0046[] = "Smart Array 64xx"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409a[] = "Smart Array 641"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409b[] = "Smart Array 642"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409c[] = "Smart Array 6400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409d[] = "Smart Array 6400 EM"; +#endif +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_005a[] = "Remote Insight II board - Lights-Out"; +static const char pci_device_0e11_007c[] = "NC7770 1000BaseTX"; +static const char pci_device_0e11_007d[] = "NC6770 1000BaseTX"; +static const char pci_device_0e11_0085[] = "NC7780 1000BaseTX"; +static const char pci_device_0e11_00b1[] = "Remote Insight II board - PCI device"; +static const char pci_device_0e11_00bb[] = "NC7760"; +static const char pci_device_0e11_00ca[] = "NC7771"; +static const char pci_device_0e11_00cb[] = "NC7781"; +static const char pci_device_0e11_00cf[] = "NC7772"; +static const char pci_device_0e11_00d0[] = "NC7782"; +static const char pci_device_0e11_00d1[] = "NC7783"; +static const char pci_device_0e11_00e3[] = "NC7761"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_4030[] = "SMART-2/P"; +static const char pci_device_0e11_4031[] = "SMART-2SL"; +static const char pci_device_0e11_4032[] = "Smart Array 3200"; +static const char pci_device_0e11_4033[] = "Smart Array 3100ES"; +static const char pci_device_0e11_4034[] = "Smart Array 221"; +static const char pci_device_0e11_4040[] = "Integrated Array"; +static const char pci_device_0e11_4048[] = "Compaq Raid LC2"; +static const char pci_device_0e11_4050[] = "Smart Array 4200"; +static const char pci_device_0e11_4051[] = "Smart Array 4250ES"; +static const char pci_device_0e11_4058[] = "Smart Array 431"; +static const char pci_device_0e11_4070[] = "Smart Array 5300"; +static const char pci_device_0e11_4080[] = "Smart Array 5i"; +static const char pci_device_0e11_4082[] = "Smart Array 532"; +static const char pci_device_0e11_4083[] = "Smart Array 5312"; +static const char pci_device_0e11_4091[] = "Smart Array 6i"; +static const char pci_device_0e11_409a[] = "Smart Array 641"; +static const char pci_device_0e11_409b[] = "Smart Array 642"; +static const char pci_device_0e11_409c[] = "Smart Array 6400"; +static const char pci_device_0e11_409d[] = "Smart Array 6400 EM"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "FibreChannel HBA Tachyon"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10 T PCI UTP"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent Dual 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae43[] = "Netelligent Integrated 10/100 TX UTP"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Netelligent 10/100 TX Embedded UTP"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2 PCI UTP/Coax"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent 10/100 TX UTP"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4080[] = "Smart Array 5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4082[] = "Smart Array 532"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4083[] = "Smart Array 5312"; +#endif +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_b200[] = "Memory Hot-Plug Controller"; +static const char pci_device_0e11_b203[] = "Integrated Lights Out Controller"; +static const char pci_device_0e11_b204[] = "Integrated Lights Out Processor"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "LSI53C810AE PCI to SCSI I/O Processor"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0003_1000_1000[] = "LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide)"; +#endif +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0006_1000_1000[] = "LSI53C860E PCI to Ultra SCSI I/O Processor"; +#endif +static const char pci_device_1000_000a[] = "53c1510"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_1000_1000[] = "LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode)"; +#endif +static const char pci_device_1000_000b[] = "53C896/897"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_0e11_6004[] = "EOB003 Series SCSI host adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1000[] = "LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1010[] = "LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1020[] = "LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_13e9_1000[] = "6221L-4U"; +#endif +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1010[] = "LSI8951U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1020[] = "LSI8952U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3906[] = "DC-390U2B SCSI adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1000[] = "LSI53C876/E PCI to Dual Channel SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1010[] = "LSI22801 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1020[] = "LSI22802 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F/U Ultra Wide SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1050[] = "CT7 mainboard"; +#endif +static const char pci_device_1000_0010[] = "53C1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "RAID LC2 Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_1000_1000[] = "53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode)"; +#endif +static const char pci_device_1000_0012[] = "53c895a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0012_1000_1000[] = "LSI53C895A PCI to Ultra2 SCSI Controller"; +#endif +static const char pci_device_1000_0013[] = "53c875a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0013_1000_1000[] = "LSI53C875A PCI to Ultra SCSI Controller"; +#endif +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1000_1000[] = "LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1000[] = "LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1010[] = "Asus TR-DLS onboard 53C1010-66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_124b_1070[] = "PMC-USCSI3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1300[] = "P017 mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1310[] = "P017 mezzanine (64-bit PMC)"; +#endif +static const char pci_device_1000_0030[] = "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_0e11_00da[] = "ProLiant ML 350"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0123[] = "PowerEdge 2600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_014a[] = "PowerEdge 1750"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_016c[] = "PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_124b_1170[] = "PMC-USCSI320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1734_1052[] = "Primergy RX300 S2"; +#endif +static const char pci_device_1000_0031[] = "53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0032[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0032_1000_1000[] = "LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller"; +#endif +static const char pci_device_1000_0033[] = "1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0040[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0033[] = "MegaRAID SCSI 320-2XR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0066[] = "MegaRAID SCSI 320-2XRWS"; +#endif +static const char pci_device_1000_0041[] = "53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0050[] = "SAS1064 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0054[] = "SAS1068 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0056[] = "SAS1064E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_0058[] = "SAS1068E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005a[] = "SAS1066E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005c[] = "SAS1064A PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_005e[] = "SAS1066 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0060[] = "SAS1078 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0062_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#endif +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0407[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0530[] = "MegaRAID 530 SCSI 320-0X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0531[] = "MegaRAID 531 SCSI 320-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0532[] = "MegaRAID 532 SCSI 320-2X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0530[] = "MegaRAID Intel RAID Controller SRCZCRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0532[] = "MegaRAID Intel RAID Controller SRCU42X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0408[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0001[] = "MegaRAID SCSI 320-1E RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0002[] = "MegaRAID SCSI 320-2E RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1025_004d[] = "MegaRAID ACER ROMB-2E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0001[] = "PowerEdge RAID Controller PERC4e/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0002[] = "PowerEdge RAID Controller PERC4e/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1734_1065[] = "FSC MegaRAID PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_8086_0002[] = "MegaRAID Intel RAID Controller SRCU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0409[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3004[] = "MegaRAID SATA 300-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3008[] = "MegaRAID SATA 300-8X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3008[] = "MegaRAID RAID Controller SRCS28X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3431[] = "MegaRAID RAID Controller Alief SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3499[] = "MegaRAID RAID Controller Harwich SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0621[] = "FC909 Fibre Channel Adapter"; +static const char pci_device_1000_0622[] = "FC929 Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0622_1000_1020[] = "44929 O Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919 Fibre Channel Adapter"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0626_1000_1010[] = "7202-XP-LC Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X Fibre Channel Adapter"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0640[] = "FC949X Fibre Channel Adapter"; +static const char pci_device_1000_0642[] = "FC939X Fibre Channel Adapter"; +static const char pci_device_1000_0646[] = "FC949ES Fibre Channel Adapter"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0804[] = "SA2010"; +static const char pci_device_1000_0805[] = "SA2010ZC"; +static const char pci_device_1000_0806[] = "SA2020"; +static const char pci_device_1000_0807[] = "SA2020ZC"; +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0518[] = "MegaRAID 518 SCSI 320-2 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0520[] = "MegaRAID 520 SCSI 320-1 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0522[] = "MegaRAID 522 i4 133 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0523[] = "MegaRAID SATA 150-6 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_4523[] = "MegaRAID SATA 150-4 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_a520[] = "MegaRAID ZCR SCSI 320-0 Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "MegaRAID 518 DELL PERC 4/DC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "MegaRAID 520 DELL PERC 4/SC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0520[] = "MegaRAIDRAID Controller SRCU41L"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0523[] = "MegaRAID RAID Controller SRCS16"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_3150[] = "M24 1P [Radeon Mobility X600]"; +static const char pci_device_1002_3152[] = "M22 [Radeon Mobility X300]"; +static const char pci_device_1002_3154[] = "M24 1T [FireGL M24 GL]"; +static const char pci_device_1002_3e50[] = "RV380 0x3e50 [Radeon X600]"; +static const char pci_device_1002_3e54[] = "RV380 0x3e54 [FireGL V3200]"; +static const char pci_device_1002_3e70[] = "RV380 [Radeon X600] Secondary"; +static const char pci_device_1002_4136[] = "Radeon IGP 320 M"; +static const char pci_device_1002_4137[] = "Radeon IGP330/340/350"; +static const char pci_device_1002_4144[] = "R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "R300 AE [Radeon 9700 Pro]"; +static const char pci_device_1002_4146[] = "R300 AF [Radeon 9700 Pro]"; +static const char pci_device_1002_4147[] = "R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4148[] = "R350 AH [Radeon 9800]"; +static const char pci_device_1002_4149[] = "R350 AI [Radeon 9800]"; +static const char pci_device_1002_414a[] = "R350 AJ [Radeon 9800]"; +static const char pci_device_1002_414b[] = "R350 AK [Fire GL X2]"; +static const char pci_device_1002_4150[] = "RV350 AP [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0002[] = "R9600 Pro primary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_4722[] = "All-in-Wonder 2006 AGP Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1458_4024[] = "Giga-Byte GV-R96128D Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2064[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2066[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c19[] = "Sapphire Atlantis Radeon 9600 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c29[] = "GC-R9600PRO Primary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_17ee_2002[] = "Radeon 9600 256Mb Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_18bc_0101[] = "GC-R9600PRO Primary"; +#endif +static const char pci_device_1002_4151[] = "RV350 AQ [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4151_1043_c004[] = "A9600SE"; +#endif +static const char pci_device_1002_4152[] = "RV350 AR [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_0002[] = "Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_4772[] = "All-in-Wonder 9600 XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c002[] = "Radeon 9600 XT TVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c01a[] = "A9600XT/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_174b_7c29[] = "Sapphire Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1787_4002[] = "Radeon 9600 XT"; +#endif +static const char pci_device_1002_4153[] = "RV350 AS [Radeon 9550]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4153_1462_932c[] = "865PE Neo2-V (MS-6788) mainboard"; +#endif +static const char pci_device_1002_4154[] = "RV350 AT [Fire GL T2]"; +static const char pci_device_1002_4155[] = "RV350 AU [Fire GL T2]"; +static const char pci_device_1002_4156[] = "RV350 AV [Fire GL T2]"; +static const char pci_device_1002_4157[] = "RV350 AW [Fire GL T2]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4164[] = "R300 AD [Radeon 9500 Pro] (Secondary)"; +static const char pci_device_1002_4165[] = "R300 AE [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4166[] = "R300 AF [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4168[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4170[] = "RV350 AP [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_4723[] = "All-in-Wonder 2006 AGP Edition (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1458_4025[] = "Giga-Byte GV-R96128D Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_148c_2067[] = "PowerColor R96A-C3N (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_174b_7c28[] = "GC-R9600PRO Secondary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_17ee_2003[] = "Radeon 9600 256Mb Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_18bc_0100[] = "GC-R9600PRO Secondary"; +#endif +static const char pci_device_1002_4171[] = "RV350 AQ [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4171_1043_c005[] = "A9600SE (Secondary)"; +#endif +static const char pci_device_1002_4172[] = "RV350 AR [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_0003[] = "Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_4773[] = "All-in-Wonder 9600 XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c003[] = "A9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c01b[] = "A9600XT/TD (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_174b_7c28[] = "Sapphire Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1787_4003[] = "Radeon 9600 XT (Secondary)"; +#endif +static const char pci_device_1002_4173[] = "RV350 ? [Radeon 9550] (Secondary)"; +static const char pci_device_1002_4237[] = "Radeon 7000 IGP"; +static const char pci_device_1002_4242[] = "R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4243[] = "R200 BC [Radeon All in Wonder 8500]"; +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_1002_4336[] = "Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_103c_0024[] = "Pavilion ze4400 builtin Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_161f_2029[] = "eMachines M5312 builtin Video"; +#endif +static const char pci_device_1002_4337[] = "Radeon IGP 330M/340M/350M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_1014_053a[] = "ThinkPad R40e (2684-HVG) builtin VGA controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_103c_0850[] = "Radeon IGP 345M"; +#endif +static const char pci_device_1002_4341[] = "IXP150 AC'97 Audio Controller"; +static const char pci_device_1002_4345[] = "EHCI USB Controller"; +static const char pci_device_1002_4347[] = "OHCI USB Controller #1"; +static const char pci_device_1002_4348[] = "OHCI USB Controller #2"; +static const char pci_device_1002_4349[] = "ATI Dual Channel Bus Master PCI IDE Controller"; +static const char pci_device_1002_434d[] = "IXP AC'97 Modem"; +static const char pci_device_1002_4353[] = "ATI SMBus"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4363[] = "ATI SMBus"; +static const char pci_device_1002_436e[] = "ATI 436E Serial ATA Controller"; +static const char pci_device_1002_4370[] = "IXP SB400 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4371[] = "IXP SB400 PCI-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4371_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4372[] = "IXP SB400 SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4373[] = "IXP SB400 USB2 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4374[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4374_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4375[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4376[] = "Standard Dual Channel PCI IDE Controller ATI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4377[] = "IXP SB400 PCI-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4378[] = "ATI SB400 - AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_4379[] = "ATI 4379 Serial ATA Controller"; +static const char pci_device_1002_437a[] = "ATI 437A Serial ATA Controller"; +static const char pci_device_1002_4437[] = "Radeon Mobility 7000 IGP"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1734_007a[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0084[] = "Rage 3D Pro AGP 2x XPERT 98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon RV250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon RV250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon RV250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "RV250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "RV250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "RV250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "RV250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "RV250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "RV250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "RV250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "RV250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon RV250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon RV250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4a48[] = "R420 JH [Radeon X800]"; +static const char pci_device_1002_4a49[] = "R420 JI [Radeon X800PRO]"; +static const char pci_device_1002_4a4a[] = "R420 JJ [Radeon X800SE]"; +static const char pci_device_1002_4a4b[] = "R420 JK [Radeon X800]"; +static const char pci_device_1002_4a4c[] = "R420 JL [Radeon X800]"; +static const char pci_device_1002_4a4d[] = "R420 JM [FireGL X3]"; +static const char pci_device_1002_4a4e[] = "M18 JN [Radeon Mobility 9800]"; +static const char pci_device_1002_4a50[] = "R420 JP [Radeon X800XT]"; +static const char pci_device_1002_4a70[] = "R420 [X800XT-PE] (Secondary)"; +static const char pci_device_1002_4b49[] = "R480 [Radeon X850XT]"; +static const char pci_device_1002_4b4b[] = "R480 [Radeon X850Pro]"; +static const char pci_device_1002_4b4c[] = "R481 [Radeon X850XT-PE]"; +static const char pci_device_1002_4b69[] = "R480 [Radeon X850XT secondary]"; +static const char pci_device_1002_4b6b[] = "R480 [Radeon X850Pro] (Secondary)"; +static const char pci_device_1002_4b6c[] = "R481 [Radeon X850XT-PE] Secondary"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e7[] = "Rage LT Pro (Compaq Presario 5240)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c46_1028_00b1[] = "Latitude C600"; +#endif +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b160[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m/A21m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00aa[] = "Latitude CPt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00bb[] = "Latitude CPx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_10e1_10cf[] = "Fujitsu Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1179_ff00[] = "Satellite 1715XCDS laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_13bd_1019[] = "PC-AR10"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c52_1033_8112[] = "Versa Note VXi"; +#endif +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_0e11_b111[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1509_1930[] = "Medion MD9703"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 Lf [FireGL 9000]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c6e[] = "Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_515e[] = "Radeon ES1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_5965[] = "Radeon ES1000"; +#endif +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1002_0002[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1681_0002[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro]"; +#endif +static const char pci_device_1002_4e46[] = "RV350 NF [Radeon 9600]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e48[] = "Radeon R350 [Radeon 9800 Pro]"; +static const char pci_device_1002_4e49[] = "Radeon R350 [Radeon 9800]"; +static const char pci_device_1002_4e4a[] = "RV350 NJ [Radeon 9800 XT]"; +static const char pci_device_1002_4e4b[] = "R350 NK [Fire GL X2]"; +static const char pci_device_1002_4e50[] = "RV350 [Mobility Radeon 9600 M10]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1734_1055[] = "Amilo M1420W"; +#endif +static const char pci_device_1002_4e51[] = "M10 NQ [Radeon Mobility 9600]"; +static const char pci_device_1002_4e52[] = "RV350 [Mobility Radeon 9600 M10]"; +static const char pci_device_1002_4e53[] = "M10 NS [Radeon Mobility 9600]"; +static const char pci_device_1002_4e54[] = "M10 NT [FireGL Mobility T2]"; +static const char pci_device_1002_4e56[] = "M11 NV [FireGL Mobility T2e]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9500 Pro] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1002_0003[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1681_0003[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary)"; +#endif +static const char pci_device_1002_4e66[] = "RV350 NF [Radeon 9600] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_4e68[] = "Radeon R350 [Radeon 9800 Pro] (Secondary)"; +static const char pci_device_1002_4e69[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4e6a[] = "RV350 NJ [Radeon 9800 XT] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e6a_1002_4e71[] = "ATI Technologies Inc M10 NQ [Radeon Mobility 9600]"; +#endif +static const char pci_device_1002_4e71[] = "M10 NQ [Radeon Mobility 9600] (secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1681_0010[] = "Radeon 8500 [3D Prophet 8500 128Mb]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5154[] = "R200 QT [Radeon 8500]"; +static const char pci_device_1002_5155[] = "R200 QU [Radeon 9100]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_103a[] = "Dell Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7146[] = "RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_029a[] = "Remote Supervisor Adapter II (RSA2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_02c8[] = "IBM eServer xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7c28[] = "Sapphire Radeon VE 7000 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_515e[] = "ES1000"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5346_1002_0048[] = "RAGE 128 16MB VGA TVOUT AMC PAL"; +#endif +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5460[] = "M22 [Radeon Mobility M300]"; +static const char pci_device_1002_5462[] = "M24 [Radeon Mobility X600]"; +static const char pci_device_1002_5464[] = "M22 [FireGL GL]"; +static const char pci_device_1002_5548[] = "R423 UH [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5549[] = "R423 UI [Radeon X800PRO (PCIE)]"; +static const char pci_device_1002_554a[] = "R423 UJ [Radeon X800LE (PCIE)]"; +static const char pci_device_1002_554b[] = "R423 UK [Radeon X800SE (PCIE)]"; +static const char pci_device_1002_554d[] = "R430 [Radeon X800 XL] (PCIe)"; +static const char pci_device_1002_554f[] = "R430 [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5550[] = "R423 [Fire GL V7100]"; +static const char pci_device_1002_5551[] = "R423 UQ [FireGL V7200 (PCIE)]"; +static const char pci_device_1002_5552[] = "R423 UR [FireGL V5100 (PCIE)]"; +static const char pci_device_1002_5554[] = "R423 UT [FireGL V7100 (PCIE)]"; +static const char pci_device_1002_556b[] = "Radeon R423 UK (PCIE) [X800 SE] (Secondary)"; +static const char pci_device_1002_556d[] = "R430 [Radeon X800 XL] (PCIe) Secondary"; +static const char pci_device_1002_556f[] = "R430 [Radeon X800 (PCIE) Secondary]"; +static const char pci_device_1002_564a[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564b[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_5652[] = "M26 [Radeon Mobility X700]"; +static const char pci_device_1002_5653[] = "Radeon Mobility X700 (PCIE)"; +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_5830[] = "RS300 Host Bridge"; +static const char pci_device_1002_5831[] = "RS300 Host Bridge"; +static const char pci_device_1002_5832[] = "RS300 Host Bridge"; +static const char pci_device_1002_5833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_5834[] = "Radeon 9100 IGP"; +static const char pci_device_1002_5835[] = "RS300M AGP [Radeon Mobility 9100IGP]"; +static const char pci_device_1002_5838[] = "Radeon 9100 IGP AGP Bridge"; +static const char pci_device_1002_5940[] = "RV280 [Radeon 9200 PRO] (Secondary)"; +static const char pci_device_1002_5941[] = "RV280 [Radeon 9200] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_1458_4019[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_174b_7c12[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_17af_200d[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_18bc_0050[] = "GeXcube GC-R9200-C3 (Secondary)"; +#endif +static const char pci_device_1002_5944[] = "RV280 [Radeon 9200 SE (PCI)]"; +static const char pci_device_1002_5950[] = "RS480 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5951[] = "ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge"; +static const char pci_device_1002_5954[] = "RS480 [Radeon Xpress 200G Series]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5954_1002_5954[] = "RV370 [Radeon Xpress 200G Series]"; +#endif +static const char pci_device_1002_5955[] = "ATI Radeon XPRESS 200M 5955 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_1002_5955[] = "RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_103c_308b[] = "nx6125"; +#endif +static const char pci_device_1002_5960[] = "RV280 [Radeon 9200 PRO]"; +static const char pci_device_1002_5961[] = "RV280 [Radeon 9200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1002_2f72[] = "All-in-Wonder 9200 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1019_4c30[] = "Radeon 9200 VIVO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_12ab_5961[] = "YUAN SMARTVGA Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1458_4018[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_174b_7c13[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_17af_200c[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0050[] = "Radeon 9200 Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0051[] = "GeXcube GC-R9200-C3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0053[] = "Radeon 9200 Game Buster VIVO"; +#endif +static const char pci_device_1002_5962[] = "RV280 [Radeon 9200]"; +static const char pci_device_1002_5964[] = "RV280 [Radeon 9200 SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1043_c006[] = "ASUS Radeon 9200 SE / TD / 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4018[] = "Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_147b_6191[] = "R9200SE-DT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_148c_2073[] = "CN-AG92E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_174b_7c13[] = "Sapphire Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1787_5964[] = "Excalibur 9200SE VIVO 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_17af_2012[] = "Radeon 9200 SE Excalibur"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0170[] = "Sapphire Radeon 9200 SE 128MB Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0173[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5969[] = "ES1000"; +static const char pci_device_1002_5974[] = "RS482 [Radeon Xpress 200]"; +static const char pci_device_1002_5975[] = "RS482 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a34[] = "RS480 PCI-X Root Port"; +static const char pci_device_1002_5a38[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a3f[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a41[] = "RS400 [Radeon Xpress 200]"; +static const char pci_device_1002_5a42[] = "RS400 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a61[] = "RC410 [Radeon Xpress 200]"; +static const char pci_device_1002_5a62[] = "RC410 [Radeon Xpress 200M]"; +static const char pci_device_1002_5b60[] = "RV370 5B60 [Radeon X300 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_002a[] = "Extreme AX300SE-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_032e[] = "Extreme AX300/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1462_0402[] = "RX300SE-TD128E (MS-8940)"; +#endif +static const char pci_device_1002_5b62[] = "RV370 5B62 [Radeon X600 (PCIE)]"; +static const char pci_device_1002_5b63[] = "RV370 [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b64[] = "RV370 5B64 [FireGL V3100 (PCIE)]"; +static const char pci_device_1002_5b65[] = "RV370 5B65 [FireGL D1100 (PCIE)]"; +static const char pci_device_1002_5b70[] = "RV370 [Radeon X300SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b70_1462_0403[] = "RX300SE-TD128E (MS-8940) (secondary display)"; +#endif +static const char pci_device_1002_5b72[] = "Radeon X600(RV380)"; +static const char pci_device_1002_5b73[] = "RV370 secondary [ATI Sapphire X550 Silent]"; +static const char pci_device_1002_5b74[] = "RV370 5B64 [FireGL V3100 (PCIE)] (Secondary)"; +static const char pci_device_1002_5c61[] = "M9+ 5C61 [Radeon Mobility 9200 (AGP)]"; +static const char pci_device_1002_5c63[] = "M9+ 5C63 [Radeon Mobility 9200 (AGP)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5c63_1002_5c63[] = "Apple iBook G4 2004"; +#endif +static const char pci_device_1002_5d44[] = "RV280 [Radeon 9200 SE] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4019[] = "Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_174b_7c12[] = "Sapphire Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1787_5965[] = "Excalibur 9200SE VIVO 128M (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_17af_2013[] = "Radeon 9200 SE Excalibur (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0171[] = "Radeon 9200 SE 128MB Game Buster (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0172[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5d48[] = "M28 [Radeon Mobility X800XT]"; +static const char pci_device_1002_5d49[] = "M28 [Mobility FireGL V5100]"; +static const char pci_device_1002_5d4a[] = "Mobility Radeon X800"; +static const char pci_device_1002_5d4d[] = "R480 [Radeon X850XT Platinum (PCIE)]"; +static const char pci_device_1002_5d4f[] = "R480 [Radeon X800 GTO (PCIE)]"; +static const char pci_device_1002_5d52[] = "R480 [Radeon X850XT (PCIE)] (Primary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b12[] = "PowerColor X850XT PCIe Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b13[] = "PowerColor X850XT PCIe Secondary"; +#endif +static const char pci_device_1002_5d57[] = "R423 5F57 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_5d6d[] = "R480 [Radeon X850XT Platinum (PCIE)] (Secondary)"; +static const char pci_device_1002_5d6f[] = "R480 [Radeon X800 GTO (PCIE)] (Secondary)"; +static const char pci_device_1002_5d72[] = "R480 [Radeon X850XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5d77[] = "R423 5F57 [Radeon X800XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5e48[] = "RV410 [FireGL V5000]"; +static const char pci_device_1002_5e49[] = "RV410 [FireGL V3300]"; +static const char pci_device_1002_5e4a[] = "RV410 [Radeon X700XT]"; +static const char pci_device_1002_5e4b[] = "RV410 [Radeon X700 Pro (PCIE)]"; +static const char pci_device_1002_5e4c[] = "RV410 [Radeon X700SE]"; +static const char pci_device_1002_5e4d[] = "RV410 [Radeon X700 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e4d_148c_2116[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5e4f[] = "RV410 [Radeon X700]"; +static const char pci_device_1002_5e6b[] = "RV410 [Radeon X700 Pro (PCIE)] Secondary"; +static const char pci_device_1002_5e6d[] = "RV410 [Radeon X700 (PCIE)] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e6d_148c_2117[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_700f[] = "PCI Bridge [IGP 320M]"; +static const char pci_device_1002_7010[] = "PCI Bridge [IGP 340M]"; +static const char pci_device_1002_7100[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_7105[] = "R520 [FireGL]"; +static const char pci_device_1002_7109[] = "R520 [Radeon X1800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0322[] = "All-in-Wonder X1800XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0d02[] = "Radeon X1800 CrossFire Edition"; +#endif +static const char pci_device_1002_7120[] = "R520 [Radeon X1800] (Secondary)"; +static const char pci_device_1002_7129[] = "R520 [Radeon X1800] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0323[] = "All-in-Wonder X1800XL (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0d03[] = "Radeon X1800 CrossFire Edition (Secondary)"; +#endif +static const char pci_device_1002_7142[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7142_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7146[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7146_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7162[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7162_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_7166[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7166_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_71c0[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71c2[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71e0[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_71e2[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_7833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_7834[] = "Radeon 9100 PRO IGP"; +static const char pci_device_1002_7835[] = "Radeon Mobility 9200 IGP"; +static const char pci_device_1002_7838[] = "Radeon 9100 IGP PCI/AGP Bridge"; +static const char pci_device_1002_7c37[] = "RV350 AQ [Radeon 9600 SE]"; +static const char pci_device_1002_cab0[] = "AGP Bridge [IGP 320M]"; +static const char pci_device_1002_cab2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +static const char pci_device_1002_cab3[] = "R200 AGP Bridge [Mobility Radeon 7000 IGP]"; +static const char pci_device_1002_cbb2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_103c_0024[] = "Pavilion ze4400 builtin Network"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_12d9_000c[] = "Aculab E1/T1 PMXc cPCI carrier card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_1385_f311[] = "FA311 / FA312 (FA311 with WoL HW)"; +#endif +static const char pci_device_100b_0021[] = "PC87200 PCI to ISA Bridge"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0028[] = "Geode GX2 Host Bridge"; +static const char pci_device_100b_002a[] = "CS5535 South Bridge"; +static const char pci_device_100b_002b[] = "CS5535 ISA bridge"; +static const char pci_device_100b_002d[] = "CS5535 IDE"; +static const char pci_device_100b_002e[] = "CS5535 Audio"; +static const char pci_device_100b_002f[] = "CS5535 USB"; +static const char pci_device_100b_0030[] = "Geode GX2 Graphics Processor"; +static const char pci_device_100b_0035[] = "DP83065 [Saturn] 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_0510[] = "SC1100 Bridge"; +static const char pci_device_100b_0511[] = "SC1100 SMI"; +static const char pci_device_100b_0515[] = "SC1100 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "DEFPA"; +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0017[] = "PV-PCI Graphics Controller (ZLXp-L)"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1112[] = "DFE-570TX Quad Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_14cb_0100[] = "LNDL-100N 100Base-TX Ethernet PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX Gigabit Ethernet"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "Hewlett-Packard NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "IP Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0364[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4000[] = "MD 5620 [CLM Data Fax Voice]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_1136[] = "SiXPack 5.1+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "GXT1000 Graphics Adapter"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "SCSI RAID Adapter [ServeRAID]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0031[] = "2 Port Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0031_1014_0031[] = "2721 WAN IOA - 2 Port Sync Serial Adapter"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_0037[] = "82660 CPU to PCI Bridge"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003c[] = "GXT250P/GXT255P Graphics Adapter"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0054[] = "GXT500P/GXT550P Graphics Adapter"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_005e[] = "GXT800P Graphics Adapter"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_008b[] = "EADS PCI to PCI Bridge"; +static const char pci_device_1014_008e[] = "GXT3000P Graphics Adapter"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0091[] = "SSA Adapter"; +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_009f[] = "PCI 4758 Cryptographic Accelerator"; +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_00b7_1092_00b8[] = "FireGL1 AGP 32Mb"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1014_00b8[] = "GXT2000P Graphics Adapter"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0104[] = "Gigabit Ethernet-SX Adapter"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_015e[] = "622Mbps ATM PCI Adapter"; +static const char pci_device_1014_0160[] = "64bit/66MHz PCI ATM 155 MMF"; +static const char pci_device_1014_016e[] = "GXT4000P Graphics Adapter"; +static const char pci_device_1014_0170[] = "GXT6000P Graphics Adapter"; +static const char pci_device_1014_017d[] = "GXT300P Graphics Adapter"; +static const char pci_device_1014_0180[] = "Snipe chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0241[] = "iSeries 2757 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0264[] = "Quad Channel PCI-X U320 SCSI RAID Adapter (2780)"; +#endif +static const char pci_device_1014_0188[] = "EADS-X PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_01c1[] = "64bit/66MHz PCI ATM 155 UTP"; +static const char pci_device_1014_01e6[] = "Cryptographic Accelerator"; +static const char pci_device_1014_01ff[] = "10/100 Mbps Ethernet"; +static const char pci_device_1014_0219[] = "Multiport Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_021a[] = "Dual RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0251[] = "Internal Modem/RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0252[] = "Quad Internal Modem"; +#endif +static const char pci_device_1014_021b[] = "GXT6500P Graphics Adapter"; +static const char pci_device_1014_021c[] = "GXT4500P Graphics Adapter"; +static const char pci_device_1014_0233[] = "GXT135P Graphics Adapter"; +static const char pci_device_1014_0266[] = "PCI-X Dual Channel SCSI"; +static const char pci_device_1014_0268[] = "Gigabit Ethernet-SX Adapter (PCI-X)"; +static const char pci_device_1014_0269[] = "10/100/1000 Base-TX Ethernet Adapter (PCI-X)"; +static const char pci_device_1014_028c[] = "Citrine chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_028d[] = "Dual Channel PCI-X DDR SAS RAID Adapter (572E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02be[] = "Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02c0[] = "Dual Channel PCI-X DDR U320 SCSI Adapter (571A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_030d[] = "PCI-X DDR Auxiliary Cache Adapter (575B)"; +#endif +static const char pci_device_1014_02a1[] = "Calgary PCI-X Host Bridge"; +static const char pci_device_1014_02bd[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/571D)"; +#endif +static const char pci_device_1014_0302[] = "Winnipeg PCI-X Host Bridge"; +static const char pci_device_1014_0314[] = "ZISC 036 Neural accelerator card"; +static const char pci_device_1014_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_4022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_0009[] = "MegaRAID 428 Ultra RAID Controller (rev 03)"; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500/500LC RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0477[] = "MegaRAID 477 Elite 3100 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0494[] = "MegaRAID 494 Elite 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0503[] = "MegaRAID 503 Enterprise 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0511[] = "MegaRAID 511 i4 IDE RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0522[] = "MegaRAID 522 i4133 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_103c_60e7[] = "NetRAID-1M"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 [Athlon64/Opteron] HyperTransport Technology Configuration"; +static const char pci_device_1022_1101[] = "K8 [Athlon64/Opteron] Address Map"; +static const char pci_device_1022_1102[] = "K8 [Athlon64/Opteron] DRAM Controller"; +static const char pci_device_1022_1103[] = "K8 [Athlon64/Opteron] Miscellaneous Control"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1022_2000[] = "PCnet - Fast 79C971"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2702[] = "AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2703[] = "AT-2701FX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2003[] = "Am 1771 MBW [Alchemy]"; +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_2081[] = "Geode LX Video"; +static const char pci_device_1022_2082[] = "Geode LX AES Security Block"; +static const char pci_device_1022_208f[] = "CS5536 GeodeLink PCI South Bridge"; +static const char pci_device_1022_2090[] = "CS5536 [Geode companion] ISA"; +static const char pci_device_1022_2091[] = "CS5536 [Geode companion] FLASH"; +static const char pci_device_1022_2093[] = "CS5536 [Geode companion] Audio"; +static const char pci_device_1022_2094[] = "CS5536 [Geode companion] OHC"; +static const char pci_device_1022_2095[] = "CS5536 [Geode companion] EHC"; +static const char pci_device_1022_2096[] = "CS5536 [Geode companion] UDC"; +static const char pci_device_1022_2097[] = "CS5536 [Geode companion] UOC"; +static const char pci_device_1022_209a[] = "CS5536 [Geode companion] IDE"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700a[] = "AMD-IGR4 AGP Host to PCI Bridge"; +static const char pci_device_1022_700b[] = "AMD-IGR4 PCI to PCI Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X IOAPIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7458[] = "AMD-8132 PCI-X Bridge"; +static const char pci_device_1022_7459[] = "AMD-8132 PCI-X IOAPIC"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7460_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7464_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7468_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_1022_2b80[] = "AMD-8111 IDE [Quartet]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746b_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746d_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_device_1022_756b[] = "AMD-8111 ACPI"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_2001_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +#endif +static const char pci_device_1023_2100[] = "CyberBlade XP4m32"; +static const char pci_device_1023_2200[] = "XGI Volari XP5"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad R30/T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_1025[] = "Travelmate 352TE"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_1671[] = "M1671 Northbridge [ALADDiN-P4]"; +static const char pci_device_1025_1672[] = "Northbridge [CyberALADDiN-P4]"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge 2400"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge 4400"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge 2450"; +#endif +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Access Card III"; +static const char pci_device_1028_0008[] = "Remote Access Card III"; +static const char pci_device_1028_0009[] = "Remote Access Card III: BMC/SMIC device not present"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000c[] = "Embedded Remote Access or ERA/O"; +static const char pci_device_1028_000d[] = "Embedded Remote Access: BMC/SMIC device"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_0010[] = "Remote Access Card 4"; +static const char pci_device_1028_0011[] = "Remote Access Card 4 Daughter Card"; +static const char pci_device_1028_0012[] = "Remote Access Card 4 Daughter Card Virtual UART"; +static const char pci_device_1028_0013[] = "PowerEdge Expandable RAID controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016c[] = "PowerEdge Expandable RAID Controller 4e/Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016d[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016e[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016f[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_0170[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +static const char pci_device_1028_0014[] = "Remote Access Card 4 Daughter Card SMIC interface"; +static const char pci_device_1028_0015[] = "PowerEdge Expandable RAID controller 5"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +static const char pci_device_102a_001f[] = "AHA-2940U2/U2W /7890/7891 SCSI Controllers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_0106[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_102a_00c5[] = "AIC-7899 U160/m SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00c5_1028_00c5[] = "PowerEdge 2550/2650/4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_102a_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0106[] = "PowerEdge 4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0121[] = "PowerEdge 2650"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0100[] = "MGA 1064SG [Mystique]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0525[] = "G400/G450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d43[] = "Millennium G450 32Mb Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0850[] = "Parhelia 256MB AGP 4X"; +#endif +static const char pci_device_102b_0528[] = "Parhelia 8X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1020[] = "Parhelia 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1030[] = "Parhelia 256 MB Dual DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_14e1[] = "Parhelia PCI 256MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_2021[] = "QID Pro"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_2537[] = "Millenium P650/P750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1820[] = "Millennium P750 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1830[] = "Millennium P650 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1c10[] = "QID 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2811[] = "Millennium P650 Low-profile PCI 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2c11[] = "QID Low-profile PCI"; +#endif +static const char pci_device_102b_2538[] = "Millenium P650 PCIe"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_08c7[] = "Millennium P650 PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_0907[] = "Millennium P650 PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1047[] = "Millennium P650 LP PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1087[] = "Millennium P650 LP PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_2538[] = "Parhelia APVe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_3007[] = "QID Low-profile PCIe"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_000a[] = "TX3927 MIPS RISC PCI Controller"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +static const char pci_device_102f_0030[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller"; +static const char pci_device_102f_0031[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL"; +static const char pci_device_102f_0105[] = "TC86C001 [goku-s] IDE"; +static const char pci_device_102f_0106[] = "TC86C001 [goku-s] USB 1.1 Host"; +static const char pci_device_102f_0107[] = "TC86C001 [goku-s] USB Device Controller"; +static const char pci_device_102f_0108[] = "TC86C001 [goku-s] I2C/SIO/GPIO Controller"; +static const char pci_device_102f_0180[] = "TX4927/38 MIPS RISC PCI Controller"; +static const char pci_device_102f_0181[] = "TX4925 MIPS RISC PCI Controller"; +static const char pci_device_102f_0182[] = "TX4937 MIPS RISC PCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0000[] = "Vr4181A USB Host or Function Control Unit"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1033_0035[] = "Hama USB 2.0 CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_14c2_0105[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000a[] = "GlobeTrotter Fusion Quad Lite (PPP data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000b[] = "GlobeTrotter Fusion Quad Lite (GSM data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_807d_0035[] = "PCI-USB2 (OHCI subsystem)"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0072[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a5[] = "VRC4173"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00ce[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00df[] = "Vr4131"; +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_14c2_0205[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_807d_1043[] = "PCI-USB2 (EHCI subsystem)"; +#endif +static const char pci_device_1033_00e7[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00f2[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_00f3[] = "uPD6113x Multimedia Decoder/Processor [EMMA2]"; +static const char pci_device_1033_010c[] = "VR7701"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0003[] = "SiS AGP Port (virtual PCI-to-PCI bridge)"; +static const char pci_device_1039_0004[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_000a[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0016[] = "SiS961/2 SMBus Controller"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0180[] = "RAID bus controller 180 SATA/PATA [SiS]"; +static const char pci_device_1039_0181[] = "SATA"; +static const char pci_device_1039_0182[] = "182 SATA/RAID Controller"; +static const char pci_device_1039_0190[] = "190 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0191[] = "191 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0550[] = "550 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0648[] = "645xx"; +static const char pci_device_1039_0650[] = "650/M650 Host"; +static const char pci_device_1039_0651[] = "651 Host"; +static const char pci_device_1039_0655[] = "655 Host"; +static const char pci_device_1039_0660[] = "660 Host"; +static const char pci_device_1039_0661[] = "661FX/M661FX/M661MX Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0741[] = "741/741GX/M741 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0746[] = "746 Host"; +static const char pci_device_1039_0755[] = "755 Host"; +static const char pci_device_1039_0760[] = "760/M760 Host"; +static const char pci_device_1039_0761[] = "761/M761 Host"; +static const char pci_device_1039_0900[] = "SiS900 PCI Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_0963[] = "SiS963 [MuTIOL Media IO]"; +static const char pci_device_1039_0964[] = "SiS964 [MuTIOL Media IO]"; +static const char pci_device_1039_0965[] = "SiS965 [MuTIOL Media IO]"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "550 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "630/730 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_6306[] = "530/620 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "65x/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_6330[] = "661/741/760/761 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6330_1039_6330[] = "[M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter"; +#endif +static const char pci_device_1039_7001[] = "USB 1.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1462_5470[] = "K7SOM+ 5.2C Motherboard"; +#endif +static const char pci_device_1039_7002[] = "USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "AC'97 Sound Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7012_15bd_1001[] = "DFI 661FX motherboard"; +#endif +static const char pci_device_1039_7013[] = "AC'97 Modem Controller"; +static const char pci_device_1039_7016[] = "SiS7016 PCI Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +static const char pci_device_1039_7019[] = "SiS7019 Audio Accelerator"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1006[] = "Visualize FX6"; +static const char pci_device_103c_1008[] = "Visualize FX4"; +static const char pci_device_103c_100a[] = "Visualize FX2"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Superdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1301[] = "Diva RMP3"; +#endif +static const char pci_device_103c_1054[] = "PCI Local Bus Adapter"; +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_10f0[] = "rio System Bus Adapter"; +static const char pci_device_103c_10f1[] = "rio I/O Controller"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "zx1 Local Bus Adapter"; +static const char pci_device_103c_127c[] = "sx1000 I/O Controller"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_1291[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_12b4[] = "zx1 QuickSilver AGP8x Local Bus Adapter"; +static const char pci_device_103c_12fa[] = "BCM4306 802.11b/g Wireless LAN Controller"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +static const char pci_device_103c_3080[] = "Pavilion ze2028ea"; +static const char pci_device_103c_3220[] = "Hewlett-Packard Smart Array P600"; +static const char pci_device_103c_3230[] = "Hewlett-Packard Smart Array Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "PC Tech RZ1000"; +static const char pci_device_1042_1001[] = "PC Tech RZ1001"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "ASUSTeK Computer Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_10cf_105e[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1043_4015[] = "v7100 SDRAM [GeForce2 MX]"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +static const char pci_device_1043_4057[] = "v8200 GeForce 3"; +static const char pci_device_1043_8043[] = "v8240 PAL 128M [P4T] Motherboard"; +static const char pci_device_1043_807b[] = "v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI]"; +static const char pci_device_1043_80bb[] = "v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out]"; +static const char pci_device_1043_80c5[] = "nForce3 chipset motherboard [SK8N]"; +static const char pci_device_1043_80df[] = "v9520 Magic/T"; +static const char pci_device_1043_8187[] = "802.11a/b/g Wireless LAN Card"; +static const char pci_device_1043_8188[] = "Tiger Hybrid TV Capture Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Adaptec (formerly DPT)"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3410S Ultra160 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c032[] = "ASR-2005S I2O Zero Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c035[] = "ASR-2010S I2O Zero Channel"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCIAudio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0c60[] = "Gladiac MX"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +static const char pci_device_1048_8901[] = "Gloria XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1048_8901_1048_0935[] = "GLoria XL (Virge)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "STMicroelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0209[] = "STPC Consumer/Industrial North- and Southbridge"; +static const char pci_device_104a_020a[] = "STPC Atlas/ConsumerS/Consumer IIA Northbridge"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_021a[] = "STPC Consumer S Southbridge"; +static const char pci_device_104a_021b[] = "STPC Consumer IIA Southbridge"; +static const char pci_device_104a_0500[] = "ST70137 [Unicorn] ADSL DMT Transceiver"; +static const char pci_device_104a_0564[] = "STPC Client Northbridge"; +static const char pci_device_104a_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +static const char pci_device_104a_55cc[] = "STPC Client Southbridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a34[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a36[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a43[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a44[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_000f[] = "Studio DV500-1394"; +#endif +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_1043_808b[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8025[] = "TSB82AA2 IEEE-1394b Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8025_1458_1000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1043_808d[] = "A7V333 mainboard."; +#endif +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8029[] = "PCI4510 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1071_8160[] = "MIM2900"; +#endif +static const char pci_device_104c_802b[] = "PCI7410,7510,7610 OHCI-Lynx Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_014e[] = "PCI7410,7510,7610 OHCI-Lynx Controller (Dell Latitude D800)"; +#endif +static const char pci_device_104c_802e[] = "PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller"; +static const char pci_device_104c_8031[] = "PCIxx21/x515 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8032[] = "OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8033[] = "PCIxx21 Integrated FlashMedia Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8034[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_308b[] = "nx6125"; +#endif +static const char pci_device_104c_8035[] = "PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Smart Card Controller (SMC)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8035_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_104c_8036[] = "PCI6515 Cardbus Controller"; +static const char pci_device_104c_8038[] = "PCI6515 SmartCard Controller"; +static const char pci_device_104c_8201[] = "PCI1620 Firmware Loading Function"; +static const char pci_device_104c_8204[] = "PCI7410,7510,7610 PCI Firmware Loading Function"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b00[] = "DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b01[] = "DWL-520+ 22Mbps PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_16ab_8501[] = "WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter"; +#endif +static const char pci_device_104c_8401[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_9000[] = "Wireless Interface (of unknown type)"; +static const char pci_device_104c_9065[] = "TMS320DM642"; +static const char pci_device_104c_9066[] = "ACX 111 54Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_104c_9066[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b04[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b05[] = "DWL-G650+ AirPlusG+ CardBus Wireless LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_13d1_aba0[] = "SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+"; +#endif +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6414 TMS320C6415 TMS320C6416"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_5000[] = "ASI50xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_6400[] = "ASI6400 Cobranet series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_8700[] = "ASI87xx Radio Tuner card"; +#endif +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac16_1014_0092[] = "ThinkPad 600"; +#endif +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_1014_0130[] = "Thinkpad T20/T22/A21m"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_0e11_b121[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_1028_0088[] = "Latitude CPi A400XT"; +#endif +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_ac44[] = "PCI4510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_104c_ac46[] = "PCI4520 PC card Cardbus Controller"; +static const char pci_device_104c_ac47[] = "PCI7510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac4a[] = "PCI7510,7610 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_0e11_004e[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_00b1[] = "Latitude C600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1033_80cd[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1095_10cf[] = "Fujitsu-Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook S-4510/C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac54[] = "PCI1620 PC Card Controller"; +static const char pci_device_104c_ac55[] = "PCI1520 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30/T40"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0528[] = "ThinkPad R40e (2684-HVG) Cardbus Controller"; +#endif +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_5100[] = "ASI51xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6100[] = "ASI61xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6200[] = "ASI62xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_8800[] = "ASI88xx Audio Adapter"; +#endif +static const char pci_device_104c_ac8d[] = "PCI 7620"; +static const char pci_device_104c_ac8e[] = "PCI7420 CardBus Controller"; +static const char pci_device_104c_ac8f[] = "PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8004[] = "DTL-H2500 [Playstation development board]"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1050_9921[] = "W99200F MPEG-1 Video Encoder"; +static const char pci_device_1050_9922[] = "W99200F/W9922PF MPEG-1/2 Video Encoder"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0008[] = "MPC8540"; +static const char pci_device_1057_0009[] = "MPC8560"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "DSP56301 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0101[] = "Transas Radar Imitator Board [RIM]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0102[] = "Transas Radar Imitator Board [RIM-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0202[] = "Transas Radar Integrator Board [RIB-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0611[] = "1 channel CAN bus Controller [CanPci-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0612[] = "2 channels CAN bus Controller [CanPci-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0613[] = "3 channels CAN bus Controller [CanPci-3]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0614[] = "4 channels CAN bus Controller [CanPci-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0621[] = "1 channel CAN bus Controller [CanPci2-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0622[] = "2 channels CAN bus Controller [CanPci2-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0810[] = "Transas VTS Radar Integrator Board [RIB-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4200[] = "ASI4215 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4300[] = "ASI43xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4400[] = "ASI4401 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0010[] = "Darla"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0020[] = "Gina"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0031[] = "Layla rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0040[] = "Darla24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0041[] = "Darla24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0072[] = "Mona rev.2"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/8266/8272"; +static const char pci_device_1057_18c1[] = "MPC8271/MPC8272"; +static const char pci_device_1057_3410[] = "DSP56361 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0060[] = "Layla24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0072[] = "Mona rev.2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0080[] = "Mia rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0081[] = "Mia rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0090[] = "Indigo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00a0[] = "Indigo IO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00b0[] = "Indigo DJ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0100[] = "3G"; +#endif +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_5608[] = "Wildcard X100P"; +static const char pci_device_1057_5803[] = "MPC5200"; +static const char pci_device_1057_5806[] = "MCF54 Coldfire"; +static const char pci_device_1057_5808[] = "MPC8220"; +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +static const char pci_device_1057_6405[] = "MPC184 Security Processor (S1 family)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "PDC20265 (FastTrak100 Lite/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3318[] = "PDC20318 (SATA150 TX4)"; +static const char pci_device_105a_3319[] = "PDC20319 (FastTrak S150 TX4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3319_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_105a_3371[] = "PDC20371 (FastTrak S150 TX2plus)"; +static const char pci_device_105a_3373[] = "PDC20378 (FastTrak 378/SATA 378)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1043_80f5[] = "K8V Deluxe/PC-DL Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1462_702e[] = "K8T NEO FIS2R motherboard"; +#endif +static const char pci_device_105a_3375[] = "PDC20375 (SATA150 TX2plus)"; +static const char pci_device_105a_3376[] = "PDC20376 (FastTrak 376)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3376_1043_809e[] = "A7V8X motherboard"; +#endif +static const char pci_device_105a_3515[] = "PDC40719"; +static const char pci_device_105a_3519[] = "PDC40519 (FastTrak TX4200)"; +static const char pci_device_105a_3570[] = "20771 (FastTrak TX2300)"; +static const char pci_device_105a_3571[] = "PDC20571 (FastTrak TX2200)"; +static const char pci_device_105a_3574[] = "PDC20579 SATAII 150 IDE Controller"; +static const char pci_device_105a_3577[] = "PDC40779 (SATA 300 779)"; +static const char pci_device_105a_3d17[] = "PDC20718 (SATA 300 TX4)"; +static const char pci_device_105a_3d18[] = "PDC20518/PDC40518 (SATAII 150 TX4)"; +static const char pci_device_105a_3d73[] = "PDC40775 (SATA 300 TX2plus)"; +static const char pci_device_105a_3d75[] = "PDC20575 (SATAII150 TX2plus)"; +static const char pci_device_105a_4d30[] = "PDC20267 (FastTrak100/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "FastTrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "PDC20262 (FastTrak66/Ultra66)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "FastTrak66"; +#endif +static const char pci_device_105a_4d68[] = "PDC20268 (Ultra100 TX2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d69_105a_4d68[] = "Ultra133TX2"; +#endif +static const char pci_device_105a_5275[] = "PDC20276 (MBFastTrak133 Lite)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1043_807e[] = "A7V333 motherboard."; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_1275[] = "MBFastTrak133 Lite (tm) Controller (RAID mode)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1458_b001[] = "MBUltra 133"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "PDC20270 (FastTrak100 LP/TX2/TX4)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6268_105a_4d68[] = "FastTrak100 TX2"; +#endif +static const char pci_device_105a_6269[] = "PDC20271 (FastTrak TX2000)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite)"; +static const char pci_device_105a_6622[] = "PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_6624[] = "PDC20621 [FastTrak SX4100]"; +static const char pci_device_105a_6626[] = "PDC20618 (Ultra 618)"; +static const char pci_device_105a_6629[] = "PDC20619 (FastTrak TX4000)"; +static const char pci_device_105a_7275[] = "PDC20277 (SBFastTrak133 Lite)"; +static const char pci_device_105a_8002[] = "SATAII150 SX8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_105d_0037[] = "Revolution IV-FP AGP (For SGI 1600SW)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_1067_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_1067_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PG"; +static const char pci_device_1069_0020[] = "DAC960LA"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0050[] = "AcceleRAID 352 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0052[] = "AcceleRAID 170 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0054[] = "AcceleRAID 160 support Device"; +#endif +static const char pci_device_1069_b166[] = "AcceleRAID 600/500/400/Sapphire support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0242[] = "iSeries 2872 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0266[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0278[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d3[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d4[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0200[] = "AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0202[] = "AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0204[] = "AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0206[] = "AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0030[] = "eXtremeRAID 3000 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0040[] = "eXtremeRAID 2000 support Device"; +#endif +static const char pci_device_1069_ba57[] = "eXtremeRAID 4000/5000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba57_1069_0072[] = "eXtremeRAID 5000 support Device"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000c[] = "DOS on Mac"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_106b_0031_106b_5811[] = "iBook G4 2004"; +#endif +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_0035[] = "UniNorth 2 PCI"; +static const char pci_device_106b_0036[] = "UniNorth 2 Internal PCI"; +static const char pci_device_106b_003b[] = "UniNorth/Intrepid ATA/100"; +static const char pci_device_106b_003e[] = "KeyLargo/Intrepid Mac I/O"; +static const char pci_device_106b_003f[] = "KeyLargo/Intrepid USB"; +static const char pci_device_106b_0040[] = "K2 KeyLargo USB"; +static const char pci_device_106b_0041[] = "K2 KeyLargo Mac/IO"; +static const char pci_device_106b_0042[] = "K2 FireWire"; +static const char pci_device_106b_0043[] = "K2 ATA/100"; +static const char pci_device_106b_0045[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0046[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0047[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0048[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0049[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_004b[] = "U3 AGP"; +static const char pci_device_106b_004c[] = "K2 GMAC (Sun GEM)"; +static const char pci_device_106b_004f[] = "Shasta Mac I/O"; +static const char pci_device_106b_0050[] = "Shasta IDE"; +static const char pci_device_106b_0051[] = "Shasta (Sun GEM)"; +static const char pci_device_106b_0052[] = "Shasta Firewire"; +static const char pci_device_106b_0053[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0054[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0055[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0058[] = "U3L AGP Bridge"; +static const char pci_device_106b_0059[] = "U3H AGP Bridge"; +static const char pci_device_106b_0066[] = "Intrepid2 AGP Bridge"; +static const char pci_device_106b_0067[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0068[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0069[] = "Intrepid2 ATA/100"; +static const char pci_device_106b_006a[] = "Intrepid2 Firewire"; +static const char pci_device_106b_006b[] = "Intrepid2 GMAC (Sun GEM)"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hynix Semiconductor"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +static const char pci_device_1071_8160[] = "Mitac 8060B Mobile Platform"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280 SCSI Host Adapter"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2200_1077_0002[] = "QLA2200"; +#endif +static const char pci_device_1077_2300[] = "QLA2300 64-bit Fibre Channel Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +static const char pci_device_1077_2322[] = "QLA2322 Fibre Channel Adapter"; +static const char pci_device_1077_2422[] = "QLA2422 Fibre Channel Adapter"; +static const char pci_device_1077_2432[] = "QLA2432 Fibre Channel Adapter"; +static const char pci_device_1077_3010[] = "QLA3010 Network Adapter"; +static const char pci_device_1077_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1077_4010[] = "QLA4010 iSCSI TOE Adapter"; +static const char pci_device_1077_4022[] = "QLA4022 iSCSI TOE Adapter"; +static const char pci_device_1077_6312[] = "QLA6312 Fibre Channel Adapter"; +static const char pci_device_1077_6322[] = "QLA6322 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +static const char pci_device_107d_2134[] = "WinFast 3D S320 II"; +static const char pci_device_107d_2971[] = "[GeForce FX 5900] WinFast A350 TDH MyViVo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_1648[] = "[bge] Gigabit Ethernet"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_8002[] = "Schizo+ PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +static const char pci_device_108e_a801[] = "Tomatillo PCI Bus Module"; +static const char pci_device_108e_abba[] = "Cassini 10/100/1000"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Compro Computer Services, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +static const char pci_device_1091_07a0[] = "Sun Expert3D-Lite Graphics Accelerator"; +static const char pci_device_1091_1091[] = "Sun Expert3D Graphics Accelerator"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1310[] = "PCI-6602"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_14e0[] = "PCI-6110"; +static const char pci_device_1093_14f0[] = "PCI-6111"; +static const char pci_device_1093_17d0[] = "PCI-6503"; +static const char pci_device_1093_1870[] = "PCI-6713"; +static const char pci_device_1093_1880[] = "PCI-6711"; +static const char pci_device_1093_18b0[] = "PCI-6052E"; +static const char pci_device_1093_2410[] = "PCI-6733"; +static const char pci_device_1093_2890[] = "PCI-6036E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_2a70[] = "PCI-6024E"; +static const char pci_device_1093_2a80[] = "PCI-6025E"; +static const char pci_device_1093_2c80[] = "PCI-6035E"; +static const char pci_device_1093_2ca0[] = "PCI-6034E"; +static const char pci_device_1093_70a9[] = "PCI-6528"; +static const char pci_device_1093_70b8[] = "PCI-6251 [M Series - High Speed Multifunction DAQ]"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "Silicon Image, Inc."; +static const char pci_device_1095_0240[] = "Adaptec AAR-1210SA SATA HostRAID Controller"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0648_1043_8025[] = "CUBX motherboard"; +#endif +static const char pci_device_1095_0649[] = "SiI 0649 Ultra ATA/100 PCI to ATA Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680 Ultra ATA-133 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0680_1095_3680[] = "Winic W-680 (Silicon Image 680 based)"; +#endif +static const char pci_device_1095_3112[] = "SiI 3112 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_3112[] = "SiI 3112 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_6112[] = "SiI 3112 SATARaid Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_9005_0250[] = "SATAConnect 1205SA Host Controller"; +#endif +static const char pci_device_1095_3114[] = "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_3114[] = "SiI 3114 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_6114[] = "SiI 3114 SATARaid Controller"; +#endif +static const char pci_device_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3124_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#endif +static const char pci_device_1095_3132[] = "SiI 3132 Serial ATA Raid II Controller"; +static const char pci_device_1095_3512[] = "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_3512[] = "SiI 3512 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_6512[] = "SiI 3512 SATARaid Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_032e[] = "Bt878 Video Capture"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0002[] = "TV98 Series (TV/No FM/Remote)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0003[] = "AverMedia UltraTV PCI 350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0761[] = "AverTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1822_0001[] = "VisionPlus DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0002[] = "Avermedia PCTV98 Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0761[] = "AVerTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1822_0001[] = "VisionPlus DVB Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_3052[] = "SmartPCI562 56K Modem"; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10a9_0009_10a9_8002[] = "AceNIC Gigabit Ethernet"; +#endif +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_100a[] = "IOC4 I/O controller"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_4001[] = "TIO-CE PCI Express Bridge"; +static const char pci_device_10a9_4002[] = "TIO-CE PCI Express Port"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +static const char pci_device_10a9_8010[] = "Broadcom e-net [SGI IO9/IO10 BaseIO]"; +static const char pci_device_10a9_8018[] = "Broadcom e-net [SGI A330 Server BaseIO]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1042[] = "Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2540[] = "IXXAT CAN-Interface PC-I 04/PCI"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_6540[] = "PCI6540/6466 PCI-PCI bridge (transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6540_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6541[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6541_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6542[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6542_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_8111[] = "PEX 8111 PCI Express-to-PCI Bridge"; +static const char pci_device_10b5_8114[] = "PEX 8114 PCI Express-to-PCI/PCI-X Bridge"; +static const char pci_device_10b5_8516[] = "PEX 8516 Versatile PCI Express Switch"; +static const char pci_device_10b5_8532[] = "PEX 8532 Versatile PCI Express Switch"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2862[] = "Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2906[] = "Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2940[] = "Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2977[] = "IXXAT iPC-I XC16/PCI CAN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2978[] = "SH ARC-PCIu SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3025[] = "Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3068[] = "Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3136[] = "4xS0-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3137[] = "S2M-E1-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1518_0200[] = "Kontron ThinkIO-C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1067[] = "IXXAT CAN i165"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1172[] = "IK220 (Heidenhain)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2221[] = "Alpermann+Velte PCL PCI LV: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH ARC-PCI SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2431[] = "Alpermann+Velte PCL PCI D: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2905[] = "Alpermann+Velte PCI TS: Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "MP9050"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1498_0362[] = "TPMC866 8 Channel Serial Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_2036[] = "OpenSwitch 6 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_3132[] = "OpenSwitch 12 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2696[] = "Innes Corp AM Radcap card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2717[] = "Innes Corp Auricon card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2844[] = "Innes Corp TVS Encoder card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12c7_4001[] = "Intel Dialogic DM/V960-4T1 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12d9_0002[] = "PCI Prosody Card rev 1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0011[] = "PIKA PrimeNet MM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0012[] = "PIKA PrimeNet MM cPCI 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0013[] = "PIKA PrimeNet MM cPCI 8 (without CAS Signaling)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0014[] = "PIKA PrimeNet MM cPCI 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0015[] = "PIKA Daytona MM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0016[] = "PIKA InLine MM"; +#endif +static const char pci_device_10b5_9056[] = "Francois"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9056_10b5_2979[] = "CellinkBlade 11 - CPCI board VoATM AAL1"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10eb[] = "(Agilent) E2777B 83K Series Optical Communication Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10ec[] = "(Agilent) E6978-66442 PCI CIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12d9_0002[] = "PCI Prosody Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12df_4422[] = "4422PCI [Do-All Telemetry Data Aquisition System]"; +#endif +static const char pci_device_10b5_bb04[] = "B&B 3PCIOSD1A Isolated PCI Serial"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_0013[] = "AR5212 802.11abg NIC (3CRDAG675)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_0013_10b7_2031[] = "3CRDAG675 11a/b/g Wireless PCI Adapter"; +#endif +static const char pci_device_10b7_0910[] = "3C910-A01"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +static const char pci_device_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +static const char pci_device_10b7_1700[] = "3c940 10/100/1000Base-T [Marvell]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_1043_80eb[] = "A7V600/P4P800/K8V motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0010[] = "3C940 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0020[] = "3C941 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 HomePNA [Tornado]"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3cCFE575CT CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6000[] = "3CRSHPW796 [OfficeConnect Wireless CardBus]"; +static const char pci_device_10b7_6001[] = "3com 3CRWE154G72 [Office Connect Wireless LAN Adapter]"; +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus [Cyclone]"; +static const char pci_device_10b7_6056[] = "3c556B CardBus [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3cCFE656 CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3cCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3cCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado]"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7770[] = "3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect]"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_80eb[] = "3c940B 10/100/1000Base-T"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 10Mbps Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC Etherlink XL [Cyclone]"; +static const char pci_device_10b7_900a[] = "3c900B-FL 10base-FL [Cyclone]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 Fast EtherLink XL [Cyclone]"; +static const char pci_device_10b7_9058[] = "3c905B Deluxe Etherlink 10/100/BNC [Cyclone]"; +static const char pci_device_10b7_905a[] = "3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0097[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_00fe[] = "Optiplex GX240"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_012a[] = "3C920 Integrated Fast Ethernet Controller [Latitude C640]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10f1_2466[] = "Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller)"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9201_1043_80ab[] = "A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller"; +#endif +static const char pci_device_10b7_9202[] = "3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9210[] = "3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX 910-A01 [tulip]"; +static const char pci_device_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-C 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "EtherLink Server 10/100 Dual Port A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "EtherLink Server 10/100 Dual Port B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990a[] = "3C990SVR [Typhoon Server]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83c170 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "83c175 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_2802[] = "SMC2802W [EZ Connect g]"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0101[] = "CMI8338/C3DX PCI Audio Device"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_0780[] = "Multi-IO Card"; +static const char pci_device_10b9_0782[] = "Multi-IO Card"; +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_1014_053b[] = "ThinkPad R40e (2684-HVG) PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALi M1533 Aladdin IV/V ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1573[] = "PCI to LPC Controller"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1672[] = "M1672 Northbridge [CyberALADDiN-P4]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_1689[] = "M1689 K8 Northbridge [Super K8 Single Chip]"; +static const char pci_device_10b9_1695[] = "M1695 K8 Northbridge [PCI Express and HyperTransport]"; +static const char pci_device_10b9_1697[] = "M1697 HTT Host Bridge"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_3323[] = "M3325 Video/Audio Decoder"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5228[] = "M5228 ALi ATA/RAID Controller"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_050f[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_053d[] = "ThinkPad R40e (2684-HVG) builtin IDE"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_103c_0024[] = "Pavilion ze4400 builtin IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_1014_0540[] = "ThinkPad R40e (2684-HVG) builtin USB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_103c_0024[] = "Pavilion ze4400 builtin USB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_104d_810f[] = "VAIO PCG-U1 USB/OHCI Revision 1.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5246[] = "AGP8X Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_524b[] = "PCI Express Root Port"; +static const char pci_device_10b9_524c[] = "PCI Express Root Port"; +static const char pci_device_10b9_524d[] = "PCI Express Root Port"; +static const char pci_device_10b9_524e[] = "PCI Express Root Port"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5263[] = "M5263 Ethernet Controller"; +static const char pci_device_10b9_5281[] = "ALi M5281 Serial ATA / RAID Host Controller"; +static const char pci_device_10b9_5287[] = "ULi 5287 SATA"; +static const char pci_device_10b9_5288[] = "ULi M5288 SATA"; +static const char pci_device_10b9_5289[] = "ULi 5289 SATA"; +static const char pci_device_10b9_5450[] = "Lucent Technologies Soft Modem AMR"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_053e[] = "ThinkPad R40e (2684-HVG) builtin Audio"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_103c_0024[] = "Pavilion ze4400 builtin Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_10b9_5451[] = "HP Compaq nc4010 (DY885AA#ABN)"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "M5457 AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_1014_0535[] = "ThinkPad R40e (2684-HVG) builtin modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_103c_0024[] = "Pavilion ze4400 builtin Modem Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5461[] = "High Definition Audio/AC'97 Host Controller"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 Power Management Controller [PMU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_0510[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_053c[] = "ThinkPad R40e (2684-HVG) Power Management Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_103c_0024[] = "Pavilion ze4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_10ba_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1028_0088[] = "Latitude CPi A"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_0088[] = "Latitude CPi A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mai Logic Incorporated"; +static const char pci_device_10cc_0660[] = "Articia S Host Bridge"; +static const char pci_device_10cc_0661[] = "Articia S PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Fujitsu Limited."; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0431[] = "MX98715"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8626[] = "Macronix MX86251 + 3Dfx Voodoo Rush"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +static const char pci_device_10dd_0100[] = "Lightning 1200"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c19[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1c[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c21[] = "Synergy II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c28[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c29[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2a[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2b[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c31[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c32[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c33[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c34[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_107d_2134[] = "WinFast 3D S320 II + TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2e[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2f[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c30[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c20[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c21[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3b[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "Pixelview RIVA TNT2 M64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1569_002d[] = "Palit Microsystems Daytona TNT2 M64"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0034[] = "MCP04 SMBus"; +static const char pci_device_10de_0035[] = "MCP04 IDE"; +static const char pci_device_10de_0036[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0037[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_0038[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_003a[] = "MCP04 AC'97 Audio Controller"; +static const char pci_device_10de_003b[] = "MCP04 USB Controller"; +static const char pci_device_10de_003c[] = "MCP04 USB Controller"; +static const char pci_device_10de_003d[] = "MCP04 PCI Bridge"; +static const char pci_device_10de_003e[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0040[] = "NV40 [GeForce 6800 Ultra]"; +static const char pci_device_10de_0041[] = "NV40 [GeForce 6800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0041_1043_817b[] = "V9999 Gamer Edition"; +#endif +static const char pci_device_10de_0042[] = "NV40.2 [GeForce 6800 LE]"; +static const char pci_device_10de_0043[] = "NV40.3"; +static const char pci_device_10de_0045[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0047[] = "NV40 [GeForce 6800 GS]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0047_1682_2109[] = "GeForce 6800 GS"; +#endif +static const char pci_device_10de_0049[] = "NV40GL"; +static const char pci_device_10de_004e[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_0050[] = "CK804 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0051[] = "CK804 ISA Bridge"; +static const char pci_device_10de_0052[] = "CK804 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0053[] = "CK804 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1458_5002[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0054[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0055[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1043_815a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_0056[] = "CK804 Ethernet Controller"; +static const char pci_device_10de_0057[] = "CK804 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1043_8141[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1458_e000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_0058[] = "CK804 AC'97 Modem"; +static const char pci_device_10de_0059[] = "CK804 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_1043_812a[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_10de_005a[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005b[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005c[] = "CK804 PCI Bridge"; +static const char pci_device_10de_005d[] = "CK804 PCIE Bridge"; +static const char pci_device_10de_005e[] = "CK804 Memory Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1458_5000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1462_7100[] = "MSI K8N Diamond"; +#endif +static const char pci_device_10de_005f[] = "CK804 Memory Controller"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +static const char pci_device_10de_0065[] = "nForce2 IDE"; +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0066_1043_80a7[] = "A7N8X Mainboard onboard nForce2 Ethernet"; +#endif +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +static const char pci_device_10de_006b[] = "nForce Audio Processing Unit"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006b_10de_006b[] = "nForce2 MCP Audio Processing Unit"; +#endif +static const char pci_device_10de_006c[] = "nForce2 External PCI Bridge"; +static const char pci_device_10de_006d[] = "nForce2 PCI Bridge"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +static const char pci_device_10de_0080[] = "MCP2A ISA bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0080_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0084[] = "MCP2A SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0084_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0085[] = "MCP2A IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0085_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0086[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_0087[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0087_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0088[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0088_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008a[] = "MCP2S AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_008a_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008b[] = "MCP2A PCI Bridge"; +static const char pci_device_10de_008c[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_008e[] = "nForce2 Serial ATA Controller"; +static const char pci_device_10de_0091[] = "GeForce 7800 GTX"; +static const char pci_device_10de_0092[] = "GeForce 7800 GT"; +static const char pci_device_10de_0099[] = "GE Force Go 7800 GTX"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_00c0[] = "NV41.0"; +static const char pci_device_10de_00c1[] = "NV41.1 [GeForce 6800]"; +static const char pci_device_10de_00c2[] = "NV41.2 [GeForce 6800 LE]"; +static const char pci_device_10de_00c8[] = "NV41.8 [GeForce Go 6800]"; +static const char pci_device_10de_00c9[] = "NV41.9 [GeForce Go 6800 Ultra]"; +static const char pci_device_10de_00cc[] = "NV41 [Quadro FX Go1400]"; +static const char pci_device_10de_00cd[] = "NV41 [Quadro FX 3450/4000 SDI]"; +static const char pci_device_10de_00ce[] = "NV41GL [Quadro FX 1400]"; +static const char pci_device_10de_00d0[] = "nForce3 LPC Bridge"; +static const char pci_device_10de_00d1[] = "nForce3 Host Bridge"; +static const char pci_device_10de_00d2[] = "nForce3 AGP Bridge"; +static const char pci_device_10de_00d3[] = "CK804 Memory Controller"; +static const char pci_device_10de_00d4[] = "nForce3 SMBus"; +static const char pci_device_10de_00d5[] = "nForce3 IDE"; +static const char pci_device_10de_00d6[] = "nForce3 Ethernet"; +static const char pci_device_10de_00d7[] = "nForce3 USB 1.1"; +static const char pci_device_10de_00d8[] = "nForce3 USB 2.0"; +static const char pci_device_10de_00d9[] = "nForce3 Audio"; +static const char pci_device_10de_00da[] = "nForce3 Audio"; +static const char pci_device_10de_00dd[] = "nForce3 PCI Bridge"; +static const char pci_device_10de_00df[] = "CK8S Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e0[] = "nForce3 250Gb LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e1[] = "nForce3 250Gb Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e2[] = "nForce3 250Gb AGP Host to PCI Bridge"; +static const char pci_device_10de_00e3[] = "CK8S Serial ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e4[] = "nForce 250Gb PCI System Management"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e5[] = "CK8S Parallel ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e6[] = "CK8S Ethernet Controller"; +static const char pci_device_10de_00e7[] = "CK8S USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e8[] = "nForce3 EHCI USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ea[] = "nForce3 250Gb AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ed[] = "nForce3 250Gb PCI-to-PCI Bridge"; +static const char pci_device_10de_00ee[] = "CK8S Serial ATA Controller (v2.5)"; +static const char pci_device_10de_00f0[] = "NV40 [GeForce 6800/GeForce 6800 Ultra]"; +static const char pci_device_10de_00f1[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1043_81a6[] = "N6600GT TD 128M AGP"; +#endif +static const char pci_device_10de_00f2[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f2_1682_211c[] = "GeForce 6600 256MB DDR DUAL DVI TV"; +#endif +static const char pci_device_10de_00f3[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_00f8[] = "NV45GL [Quadro FX 3400/4400]"; +static const char pci_device_10de_00f9[] = "NV40 [GeForce 6800 Ultra/GeForce 6800 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f9_1682_2120[] = "GEFORCE 6800 GT PCI-E"; +#endif +static const char pci_device_10de_00fa[] = "NV36 [GeForce PCX 5750]"; +static const char pci_device_10de_00fb[] = "NV35 [GeForce PCX 5900]"; +static const char pci_device_10de_00fc[] = "NV37GL [Quadro FX 330/GeForce PCX 5300]"; +static const char pci_device_10de_00fd[] = "NV37GL [Quadro FX 330/Quadro NVS280]"; +static const char pci_device_10de_00fe[] = "NV38GL [Quadro FX 1300]"; +static const char pci_device_10de_00ff[] = "NV18 [GeForce PCX 4300]"; +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c41[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c43[] = "ERAZOR X PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c48[] = "Synergy Force"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1048_0c42[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_107d_2822[] = "WinFast GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c40[] = "GLoria II-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c44[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c45[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4a[] = "GLoria II-64 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4b[] = "GLoria II-64 Pro DVII"; +#endif +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c60[] = "Gladiac MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c61[] = "Gladiac 511PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c63[] = "Gladiac 511TV-OUT 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c64[] = "Gladiac 511TV-OUT 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c65[] = "Gladiac 511TWIN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c66[] = "Gladiac 311"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_0091[] = "Dell OEM GeForce 2 MX 400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_00a1[] = "Apple OEM GeForce2 MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX/Go]"; +static const char pci_device_10de_0140[] = "NV43 [GeForce 6600 GT]"; +static const char pci_device_10de_0141[] = "NV43 [GeForce 6600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0141_1458_3124[] = "GV-NX66128DP Turbo Force Edition"; +#endif +static const char pci_device_10de_0142[] = "NV43 [GeForce 6600 PCIe]"; +static const char pci_device_10de_0144[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0145[] = "NV43 [GeForce 6610 XL]"; +static const char pci_device_10de_0146[] = "NV43 [Geforce Go 6600TE/6200TE]"; +static const char pci_device_10de_0148[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_014e[] = "NV43GL [Quadro FX 540]"; +static const char pci_device_10de_014f[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c50[] = "Gladiac"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c52[] = "Gladiac-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2842[] = "WinFast GeForce 2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1462_5506[] = "Creative 3D Blaster Geforce2 Titanium"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0161[] = "GeForce 6200 TurboCache(TM)"; +static const char pci_device_10de_0164[] = "NV44 [GeForce Go 6200]"; +static const char pci_device_10de_0165[] = "NV44 [Quadro NVS 285]"; +static const char pci_device_10de_0167[] = "GeForce Go 6200 TurboCache"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10b0_0002[] = "Gainward Pro/600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10de_0008[] = "Apple OEM GeForce4 MX 440"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8852[] = "GeForce4 MX440 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_10de_0177[] = "NV17 [GeForce4 460 Go]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0179_10de_0179[] = "GeForce4 MX (Mac)"; +#endif +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 500 GoGL]"; +static const char pci_device_10de_017d[] = "NV17 [GeForce4 410 Go 16M]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_806f[] = "V9180 Magic"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8880[] = "MS-StarForce GeForce4 MX 440 with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8900[] = "MS-8890 GeForce 4 MX440 AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_9350[] = "MSI Geforce4 MX T8X with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_147b_8f0d[] = "Siluro GF4 MX-8X"; +#endif +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0185[] = "NV18 [GeForce4 MX 4000 AGP 8x]"; +static const char pci_device_10de_0186[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_0187[] = "NV18M [GeForce4 488 Go]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS AGP 8x]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_018d[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_01a0[] = "NVCrush11 [GeForce2 MX Integrated Graphics]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b0[] = "nForce Audio"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "nForce AC'97 Modem Controller"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01e0[] = "nForce2 AGP (different version?)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01e0_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01ea[] = "nForce2 Memory Controller 0"; +static const char pci_device_10de_01eb[] = "nForce2 Memory Controller 1"; +static const char pci_device_10de_01ec[] = "nForce2 Memory Controller 2"; +static const char pci_device_10de_01ed[] = "nForce2 Memory Controller 3"; +static const char pci_device_10de_01ee[] = "nForce2 Memory Controller 4"; +static const char pci_device_10de_01ef[] = "nForce2 Memory Controller 5"; +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1048_0c70[] = "GLADIAC 920"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0221[] = "GeForce 6200"; +static const char pci_device_10de_0240[] = "C51PV [GeForce 6150]"; +static const char pci_device_10de_0241[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0242[] = "C51G [GeForce 6100]"; +static const char pci_device_10de_0243[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0244[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0245[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0246[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0247[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0248[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0249[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024a[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024b[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024c[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024d[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024e[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024f[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0251_1043_8023[] = "v8440 GeForce 4 Ti4400"; +#endif +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0260[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0261[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0262[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0263[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0264[] = "MCP51 SMBus"; +static const char pci_device_10de_0265[] = "MCP51 IDE"; +static const char pci_device_10de_0266[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0267[] = "MCP51 Serial ATA Controller"; +static const char pci_device_10de_0268[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_0269[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_026a[] = "MCP51 MCI"; +static const char pci_device_10de_026b[] = "MCP51 AC97 Audio Controller"; +static const char pci_device_10de_026c[] = "MCP51 High Definition Audio"; +static const char pci_device_10de_026d[] = "MCP51 USB Controller"; +static const char pci_device_10de_026e[] = "MCP51 USB Controller"; +static const char pci_device_10de_026f[] = "MCP51 PCI Bridge"; +static const char pci_device_10de_0270[] = "MCP51 Host Bridge"; +static const char pci_device_10de_0271[] = "MCP51 PMU"; +static const char pci_device_10de_0272[] = "MCP51 Memory Controller 0"; +static const char pci_device_10de_027e[] = "C51 Memory Controller 2"; +static const char pci_device_10de_027f[] = "C51 Memory Controller 3"; +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0286[] = "NV28 [GeForce4 Ti 4200 Go AGP 8x]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_028c[] = "NV28GLM [Quadro4 700 GoGL]"; +static const char pci_device_10de_02a0[] = "NV2A [XGPU]"; +static const char pci_device_10de_02f0[] = "C51 Host Bridge"; +static const char pci_device_10de_02f1[] = "C51 Host Bridge"; +static const char pci_device_10de_02f2[] = "C51 Host Bridge"; +static const char pci_device_10de_02f3[] = "C51 Host Bridge"; +static const char pci_device_10de_02f4[] = "C51 Host Bridge"; +static const char pci_device_10de_02f5[] = "C51 Host Bridge"; +static const char pci_device_10de_02f6[] = "C51 Host Bridge"; +static const char pci_device_10de_02f7[] = "C51 Host Bridge"; +static const char pci_device_10de_02f8[] = "C51 Memory Controller 5"; +static const char pci_device_10de_02f9[] = "C51 Memory Controller 4"; +static const char pci_device_10de_02fa[] = "C51 Memory Controller 0"; +static const char pci_device_10de_02fb[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fc[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fd[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fe[] = "C51 Memory Controller 1"; +static const char pci_device_10de_02ff[] = "C51 Host Bridge"; +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +static const char pci_device_10de_0311[] = "NV31 [GeForce FX 5600 Ultra]"; +static const char pci_device_10de_0312[] = "NV31 [GeForce FX 5600]"; +static const char pci_device_10de_0313[] = "NV31"; +static const char pci_device_10de_0314[] = "NV31 [GeForce FX 5600XT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0314_1043_814a[] = "V9560XT/TD"; +#endif +static const char pci_device_10de_0316[] = "NV31M"; +static const char pci_device_10de_0317[] = "NV31M Pro"; +static const char pci_device_10de_031a[] = "NV31M [GeForce FX Go5600]"; +static const char pci_device_10de_031b[] = "NV31M [GeForce FX Go5650]"; +static const char pci_device_10de_031c[] = "NVIDIA Quadro FX Go700"; +static const char pci_device_10de_031d[] = "NV31GLM"; +static const char pci_device_10de_031e[] = "NV31GLM Pro"; +static const char pci_device_10de_031f[] = "NV31GLM Pro"; +static const char pci_device_10de_0320[] = "NV34 [GeForce FX 5200]"; +static const char pci_device_10de_0321[] = "NV34 [GeForce FX 5200 Ultra]"; +static const char pci_device_10de_0322[] = "NV34 [GeForce FX 5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9171[] = "MS-8917 (FX5200-T128)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9360[] = "MS-8936 (FX5200-T128)"; +#endif +static const char pci_device_10de_0323[] = "NV34 [GeForce FX 5200LE]"; +static const char pci_device_10de_0324[] = "NV34M [GeForce FX Go5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_10de_0325[] = "NV34M [GeForce FX Go5250]"; +static const char pci_device_10de_0326[] = "NV34 [GeForce FX 5500]"; +static const char pci_device_10de_0327[] = "NV34 [GeForce FX 5100]"; +static const char pci_device_10de_0328[] = "NV34M [GeForce FX Go5200 32M/64M]"; +static const char pci_device_10de_0329[] = "NV34M [GeForce FX Go5200]"; +static const char pci_device_10de_032a[] = "NV34GL [Quadro NVS 280 PCI]"; +static const char pci_device_10de_032b[] = "NV34GL [Quadro FX 500/600 PCI]"; +static const char pci_device_10de_032c[] = "NV34GLM [GeForce FX Go 5300]"; +static const char pci_device_10de_032d[] = "NV34 [GeForce FX Go5100]"; +static const char pci_device_10de_032f[] = "NV34GL"; +static const char pci_device_10de_0330[] = "NV35 [GeForce FX 5900 Ultra]"; +static const char pci_device_10de_0331[] = "NV35 [GeForce FX 5900]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0331_1043_8145[] = "V9950GE"; +#endif +static const char pci_device_10de_0332[] = "NV35 [GeForce FX 5900XT]"; +static const char pci_device_10de_0333[] = "NV38 [GeForce FX 5950 Ultra]"; +static const char pci_device_10de_0334[] = "NV35 [GeForce FX 5900ZT]"; +static const char pci_device_10de_0338[] = "NV35GL [Quadro FX 3000]"; +static const char pci_device_10de_033f[] = "NV35GL [Quadro FX 700]"; +static const char pci_device_10de_0341[] = "NV36.1 [GeForce FX 5700 Ultra]"; +static const char pci_device_10de_0342[] = "NV36.2 [GeForce FX 5700]"; +static const char pci_device_10de_0343[] = "NV36 [GeForce FX 5700LE]"; +static const char pci_device_10de_0344[] = "NV36.4 [GeForce FX 5700VE]"; +static const char pci_device_10de_0345[] = "NV36.5"; +static const char pci_device_10de_0347[] = "NV36 [GeForce FX Go5700]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0347_103c_006a[] = "nx9500"; +#endif +static const char pci_device_10de_0348[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0349[] = "NV36M Pro"; +static const char pci_device_10de_034b[] = "NV36MAP"; +static const char pci_device_10de_034c[] = "NV36 [Quadro FX Go1000]"; +static const char pci_device_10de_034e[] = "NV36GL [Quadro FX 1100]"; +static const char pci_device_10de_034f[] = "NV36GL"; +static const char pci_device_10de_0360[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0361[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0362[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0363[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0364[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0365[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0366[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0367[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0368[] = "MCP55 SMBus"; +static const char pci_device_10de_0369[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036c[] = "MCP55 USB Controller"; +static const char pci_device_10de_036d[] = "MCP55 USB Controller"; +static const char pci_device_10de_036e[] = "MCP55 IDE"; +static const char pci_device_10de_0371[] = "MCP55 High Definition Audio"; +static const char pci_device_10de_0372[] = "MCP55 Ethernet"; +static const char pci_device_10de_0373[] = "MCP55 Ethernet"; +static const char pci_device_10de_037a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_037e[] = "MCP55 SATA Controller"; +static const char pci_device_10de_037f[] = "MCP55 SATA Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Host Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Host Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a1[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a5[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0b5[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d1[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d5[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e1[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e5[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0f5[] = "Neptune LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f701[] = "LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f801[] = "LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f901[] = "LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Host Adapter"; +static const char pci_device_10df_f981[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_f982[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_fa00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fb00[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc10[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc20[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fd00[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fe00[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_ff00[] = "Neptune LightPulse Fibre Channel Host Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0148[] = "Tsi148 [Tempe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +static const char pci_device_10e3_8260[] = "CA91L8200B [Dual PCI PowerSpan II]"; +static const char pci_device_10e3_8261[] = "CA91L8260B [Single PCI PowerSpan II]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +static const char pci_device_10e4_8029[] = "Realtek 8029 Network Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_1072[] = "INES GPIB-PCI (AMCC5920 based)"; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_814c[] = "Fastcom ESCC-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_81e6[] = "Multimedia video controller"; +static const char pci_device_10e8_8291[] = "Fastcom 232/8-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c4[] = "Fastcom 422/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c5[] = "Fastcom 422/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c6[] = "Fastcom IG422/1-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c7[] = "Fastcom IG232/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82ca[] = "Fastcom 232/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +static const char pci_device_10e8_82e2[] = "Fastcom DIO24H-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8851[] = "S5933 on Innes Corp FM Radio Capture card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +static const char pci_device_10ea_5252[] = "CyberPro5252"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_0139[] = "Zonet Zen3200"; +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1043_8109[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1113_ec01[] = "FNC-0107TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1458_e000[] = "GA-7VM400M/7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1462_788c[] = "865PE Neo2-V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_14cb_0200[] = "LNR-100 Family 10/100 Base-TX Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1799_5000[] = "F5D5000 PCI Card/Desktop Network PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_9001_1695[] = "Onboard RTL8101L 10/100 MBit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8169[] = "RTL-8169 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1259_c107[] = "CG-LAPCIGT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1458_e000[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1462_702c[] = "K8T NEO 2 motherboard"; +#endif +static const char pci_device_10ec_8180[] = "RTL8180L 802.11b MAC"; +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_0205[] = "Wildcard TE205P"; +static const char pci_device_10ee_0210[] = "Wildcard TE210P"; +static const char pci_device_10ee_0314[] = "Wildcard TE405P/TE410P (1st Gen)"; +static const char pci_device_10ee_0405[] = "Wildcard TE405P (2nd Gen)"; +static const char pci_device_10ee_0410[] = "Wildcard TE410P (2nd Gen)"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +static const char pci_device_10ee_3fc6[] = "RME Hammerfall DSP MADI"; +static const char pci_device_10ee_8381[] = "Ellips Santos Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft fuer Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +static const char pci_device_1101_9502[] = "Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_100a[] = "SB Live! 5.1 Digital OEM [SB0220]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8064[] = "SBLive! 5.1 Model SB0100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8065[] = "SBLive! 5.1 Digital Model SB0220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8067[] = "SBLive! 5.1 eMicro 28028"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0058[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_1007[] = "SB0240 Audigy 2 Platinum 6.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_2002[] = "SB Audigy 2 ZS (SB0350)"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_0007[] = "SB Audigy LS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_0007[] = "SBLive! 24bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1001[] = "SB0310 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1002[] = "SB0312 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1006[] = "SB0410 SBLive! 24-bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1462_1009[] = "K8N Diamond"; +#endif +static const char pci_device_1102_0008[] = "SB0400 Audigy2 Value"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0008_1102_0008[] = "EMU0404 Digital Audio System"; +#endif +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! MIDI/Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_7005[] = "SB Audigy LS MIDI/Game port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1001[] = "SB0310 Audigy LS MIDI/Game port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1002[] = "SB0312 Audigy LS MIDI/Game port"; +#endif +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "Ectiva EV1938"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1033_80e5[] = "SlimTower-Jim (NEC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1071_7150[] = "Mitac 7150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_110a_5938[] = "Siemens Scenic Mobile 510PIII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100c[] = "Ceres-C (Sharp, Intel BX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100d[] = "Sharp, Intel Banister"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100e[] = "TwinHead P09S/P09S3 (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_f6f1[] = "Marlin (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_0e70[] = "P88TE (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_c401[] = "Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b400[] = "G400 - Geo (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b550[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b560[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b700[] = "G700/U700 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b795[] = "G795 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b797[] = "G797 (AlphaTop (Taiwan))"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372/372N"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0003[] = "HPT343 / HPT345 / HPT363 UDMA33"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0004[] = "HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0006[] = "HPT302"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0007[] = "HPT371 UDMA133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0008[] = "HPT374 UDMA/ATA133 RAID Controller"; +#endif +static const char pci_device_1103_0005[] = "HPT372A/372N"; +static const char pci_device_1103_0006[] = "HPT302"; +static const char pci_device_1103_0007[] = "HPT371/371N"; +static const char pci_device_1103_0008[] = "HPT374"; +static const char pci_device_1103_0009[] = "HPT372N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +static const char pci_device_1105_8401[] = "EM8401 REALmagic DVD/MPEG-2 A/V Decoder"; +static const char pci_device_1105_8470[] = "EM8470 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8471[] = "EM8471 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8475[] = "EM8475 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8475_1105_0001[] = "REALmagic X-Card"; +#endif +static const char pci_device_1105_8476[] = "EM8476 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8476_127d_0000[] = "CineView II"; +#endif +static const char pci_device_1105_8485[] = "EM8485 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8486[] = "EM8486 REALmagic DVD/MPEG-4 A/V Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_0238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_0259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_0269[] = "KT880 Host Bridge"; +static const char pci_device_1106_0282[] = "K8T800Pro Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0282_1043_80a3[] = "A8V Deluxe"; +#endif +static const char pci_device_1106_0290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_0296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1019_0987[] = "K7VZA (Rev. 1.0) Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0308[] = "PT894 Host Bridge"; +static const char pci_device_1106_0314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C576MV"; +static const char pci_device_1106_0571[] = "VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_808c[] = "A7V8X / A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80a1[] = "A7V8X-X motherboard rev. 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1849_0571[] = "K7VT2 / K7VT6 motherboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0591[] = "VT8237A SATA 2-Port Controller"; +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0605_1043_802c[] = "CUV4X mainboard"; +#endif +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_802c[] = "CUV4X mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_1208[] = "PT890 Host Bridge"; +static const char pci_device_1106_1238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_1258[] = "PT880 Host Bridge"; +static const char pci_device_1106_1259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_1269[] = "KT880 Host Bridge"; +static const char pci_device_1106_1282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_1290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_1296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_1308[] = "PT894 Host Bridge"; +static const char pci_device_1106_1314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_1571[] = "VT82C576M/VT82C586"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_2204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_2208[] = "PT890 Host Bridge"; +static const char pci_device_1106_2238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_2258[] = "PT880 Host Bridge"; +static const char pci_device_1106_2259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_2269[] = "KT880 Host Bridge"; +static const char pci_device_1106_2282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_2290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_2296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_2308[] = "PT894 Host Bridge"; +static const char pci_device_1106_2314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_287a[] = "VT8251 PCI to PCI Bridge"; +static const char pci_device_1106_287b[] = "VT8251 PCI to PCIE Bridge"; +static const char pci_device_1106_287c[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287d[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287e[] = "VT8251 Ultra VLINK Controller"; +static const char pci_device_1106_3022[] = "CLE266"; +static const char pci_device_1106_3038[] = "VT82xxxxx UHCI USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_8080[] = "A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_808c[] = "VT6202 USB2.0 4 port controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_182d_201d[] = "CN-029 USB2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1849_3038[] = "K7VT6"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_0574_086c[] = "K8N Diamond"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1043_808a[] = "A8V Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1458_1000[] = "GA-7VT600-1394 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_702d[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_971d[] = "MS-6917"; +#endif +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3053[] = "VT6105M [Rhine-III]"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_0097[] = "SoundMax Digital Integrated Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0987[] = "K7VZA (Rev. 1.0) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1043_1106[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3300[] = "MS-6330 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233/A/8235/8237 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_8095[] = "A7V8X Motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80b0[] = "A7V600/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX])"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_812a[] = "A8V Deluxe motherboard (Realtek ALC850 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_3059[] = "L7VMM2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4161[] = "K7VT2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1297_c160[] = "FX41 motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_0080[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_3800[] = "KT266 onboard audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1849_9761[] = "K7VT6 motherboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4005_4710[] = "MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4170_1106[] = "PCPartner P4M800-8237R Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4552_1106[] = "Soyo KT-600 Dragon Plus (Realtek ALC 650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_a0a0_01b6[] = "AK77-8XN onboard audio"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_13b9_1421[] = "LD-10/100AL PCI Fast Ethernet Adapter (rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_147b_1c09[] = "NV7 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_3005[] = "VT6103"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_300c[] = "Realtek ALC655 sound chip"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1849_3065[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3068[] = "AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3068_1462_309e[] = "MS-6309 Saturn Motherboard"; +#endif +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1849_3099[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80a1[] = "A7V8X-X motherboard rev 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_182d_201d[] = "CN-029 USB 2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1849_3104[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3106_1186_1403[] = "DFE-530TX rev C"; +#endif +static const char pci_device_1106_3108[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3113[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3116[] = "VT8375 [KM266/KL266] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3116_1297_f641[] = "FX41 motherboard"; +#endif +static const char pci_device_1106_3118[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3119[] = "VT6120/VT6121/VT6122 Gigabit Ethernet Adapter"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3147_1043_808c[] = "A7V333 motherboard"; +#endif +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3149[] = "VIA VT6420 SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1043_80ed[] = "A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1458_b003[] = "GA-7VM400AM(F) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1462_7020[] = "K8T Neo 2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1408[] = "KV7"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1849_3149[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3164[] = "VT6410 ATA133 RAID controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1043_80f4[] = "P4P800 Mainboard Deluxe ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1849_3177[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3178[] = "ProSavageDDR P4N333 Host Bridge"; +static const char pci_device_1106_3188[] = "VT8385 [K8T800 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_1043_80a3[] = "K8V Deluxe/K8V-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400/KT600 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1043_807f[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1849_3189[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_3205[] = "VT8378 [KM400/A] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3205_1458_5000[] = "GA-7VM400M Motherboard"; +#endif +static const char pci_device_1106_3208[] = "PT890 Host Bridge"; +static const char pci_device_1106_3213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3218[] = "K8T800M Host Bridge"; +static const char pci_device_1106_3227[] = "VT8237 ISA bridge [KT600/K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1106_3227[] = "DFI KT600-AL Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1458_5001[] = "GA-7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1849_3227[] = "K7VT4 motherboard"; +#endif +static const char pci_device_1106_3238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_3249[] = "VT6421 IDE RAID Controller"; +static const char pci_device_1106_3258[] = "PT880 Host Bridge"; +static const char pci_device_1106_3259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_3269[] = "KT880 Host Bridge"; +static const char pci_device_1106_3282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_3287[] = "VT8251 PCI to ISA Bridge"; +static const char pci_device_1106_3288[] = "VIA High Definition Audio Controller"; +static const char pci_device_1106_3290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_3296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_3337[] = "VT8237A PCI to ISA Bridge"; +static const char pci_device_1106_3344[] = "UniChrome Pro IGP"; +static const char pci_device_1106_3349[] = "VT8251 AHCI/SATA 4-Port Controller"; +static const char pci_device_1106_337a[] = "VT8237A PCI to PCI Bridge"; +static const char pci_device_1106_337b[] = "VT8237A PCI to PCIE Bridge"; +static const char pci_device_1106_4149[] = "VIA VT6420 (ATA133) Controller"; +static const char pci_device_1106_4204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_4208[] = "PT890 Host Bridge"; +static const char pci_device_1106_4238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_4258[] = "PT880 Host Bridge"; +static const char pci_device_1106_4259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_4269[] = "KT880 Host Bridge"; +static const char pci_device_1106_4282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_4290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_4296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_4308[] = "PT894 Host Bridge"; +static const char pci_device_1106_4314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_5208[] = "PT890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5238[] = "K8T890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5290[] = "K8M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5308[] = "PT894 I/O APIC Interrupt Controller"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_7204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_7205[] = "VT8378 [S3 UniChrome] Integrated Video"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_7205_1458_d000[] = "Gigabyte GA-7VM400(A)M(F) Motherboard"; +#endif +static const char pci_device_1106_7208[] = "PT890 Host Bridge"; +static const char pci_device_1106_7238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_7258[] = "PT880 Host Bridge"; +static const char pci_device_1106_7259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_7269[] = "KT880 Host Bridge"; +static const char pci_device_1106_7282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_7290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_7296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_7308[] = "PT894 Host Bridge"; +static const char pci_device_1106_7314[] = "P4M800CE Host Bridge"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_8598_1019_0985[] = "P6VXA Motherboard"; +#endif +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_a208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b113[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b115[] = "VT8363/8365 [KT133/KM133] PCI Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +static const char pci_device_1106_b188[] = "VT8237 PCI bridge [K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_b188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_b198[] = "VT8237 PCI Bridge"; +static const char pci_device_1106_b213[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_c208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d104[] = "VT8237 Integrated Fast Ethernet Controller"; +static const char pci_device_1106_d208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f238[] = "K8T890 PCI to PCI Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_0006[] = "FSC PINC (I/O-APIC)"; +static const char pci_device_110a_0015[] = "FSC Multiprocessor Interrupt Controller"; +static const char pci_device_110a_001d[] = "FSC Copernicus Management Controller"; +static const char pci_device_110a_007b[] = "FSC Remote Service Controller, mailbox device"; +static const char pci_device_110a_007c[] = "FSC Remote Service Controller, shared memory device"; +static const char pci_device_110a_007d[] = "FSC Remote Service Controller, SMIC device"; +static const char pci_device_110a_2101[] = "HST SAPHIR V Primary PCI (ISDN/PMx)"; +static const char pci_device_110a_2102[] = "DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels"; +static const char pci_device_110a_2104[] = "Eicon Diva 2.02 compatible passive ISDN card"; +static const char pci_device_110a_3142[] = "SIMATIC NET CP 5613A1 (Profibus Adapter)"; +static const char pci_device_110a_4021[] = "SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter)"; +static const char pci_device_110a_4029[] = "SIMATIC NET CP 5613A2 (Profibus Adapter)"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_1113_2242[] = "EN2242 10/100 Ethernet Mini-PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "21x4x DEC-Tulip compatible Fast Ethernet"; +static const char pci_device_1113_d301[] = "CPWNA100 (Philips wireless PCMCIA)"; +static const char pci_device_1113_ec02[] = "SMC 1244TX v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +static const char pci_device_1114_0506[] = "at76c506 802.11b Wireless Network Adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6117/6517"; +static const char pci_device_1119_0007[] = "GDT 6127/6527"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557/6557-ECC"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0010[] = "GDT 6115/6515"; +static const char pci_device_1119_0011[] = "GDT 6125/6525"; +static const char pci_device_1119_0012[] = "GDT 6535"; +static const char pci_device_1119_0013[] = "GDT 6555/6555-ECC"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_02ff[] = "GDT MAXRP"; +static const char pci_device_1119_0300[] = "GDT NEWRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +static const char pci_device_111a_1203[] = "SpeedStream 1023 Wireless PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Technology, Inc."; +static const char pci_device_111d_0001[] = "IDT77201/77211 155Mbps ATM SAR Controller [NICStAR]"; +static const char pci_device_111d_0003[] = "IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0004[] = "IDT77V252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0005[] = "IDT77V222 155Mbps ATM MICRO ABR SAR Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +static const char pci_device_112f_0008[] = "PC-CamLink PCI framegrabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_5400[] = "TriMedia TM1000/1100"; +static const char pci_device_1131_5402[] = "TriMedia TM-1300"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_5402_1244_0f00[] = "Fritz!Card DSL"; +#endif +static const char pci_device_1131_5405[] = "TriMedia TM1500"; +static const char pci_device_1131_5406[] = "TriMedia TM1700"; +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_102b_48d0[] = "Matrox CronosPlus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1048_226b[] = "ELSA EX-VISION 300TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2001[] = "10MOONS PCI TV CAPTURE CARD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2005[] = "Techcom (India) TV Tuner Card (SSD-TV-670)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_050c[] = "Nagase Sangyo TransGear 3000TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_10ff[] = "AVerMedia DVD EZMaker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2108[] = "AverMedia AverTV/305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2115[] = "AverMedia AverTV Studio 305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_153b_1152[] = "Terratec Cinergy 200 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c100[] = "Compro VideoMate TV PVR/FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c901[] = "Videomate DVB-T200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_5168_0138[] = "LifeView FlyVIDEO2000"; +#endif +static const char pci_device_1131_7133[] = "SAA7133/SAA7135 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_0000_4091[] = "Beholder BeholdTV 409 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_002b_11bd[] = "Pinnacle PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1019_4cb5[] = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_0210[] = "FlyTV mini Asus Digimatrix"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4843[] = "ASUS TV-FM 7133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4845[] = "TV-FM 7135"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4862[] = "P7131 Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2001[] = "Proteus Pro [philips reference design]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2018[] = "Tiger reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_4ee9[] = "MonsterTV Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_11bd_002e[] = "PCTV 110i (saa7133)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_12ab_0800[] = "PURPLE TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1421_1370[] = "Instant TV (saa7135)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7330[] = "VFG7330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7350[] = "VFG7350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_1044[] = "AVerTVHD MCE A180"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_f31f[] = "Avermedia AVerTV GO 007 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1462_6231[] = "TV@Anywhere plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1489_0214[] = "LifeView FlyTV Platinum FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_14c0_1212[] = "LifeView FlyTV Platinum Mini2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1160[] = "Cinergy 250 PCI TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1162[] = "Terratec Cinergy 400 mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_185b_c100[] = "VideoMate TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_4e42_0212[] = "LifeView FlyTV Platinum Mini"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_4e42_0502[] = "Typhoon DVB-T Duo Digital/Analog Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0306[] = "LifeView FlyDVB-T DUO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0319[] = "LifeView FlyDVB Trio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5456_7135[] = "GoTView 7135 PCI"; +#endif +static const char pci_device_1131_7134[] = "SAA7134 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1019_4cb4[] = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_0210[] = "Digimatrix TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4840[] = "ASUS TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_2004[] = "EUROPA V3 reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_4e85[] = "SKNet Monster TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_6752[] = "EMPRESS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_7133[] = "AOPEN VA1000 POWER"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002b[] = "Pinnacle PCTV Stereo (saa7134)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002d[] = "Pinnacle PCTV 300i DVB-T + PAL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_9715[] = "AVerTV Studio 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70a[] = "Avermedia AVerTV 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70b[] = "AverMedia M156 / Medion 2819"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_d6ee[] = "Cardbus TV/Radio (E500)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1471_b7e9[] = "AVerTV Cardbus plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1142[] = "Terratec Cinergy 400 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1143[] = "Terratec Cinergy 600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1158[] = "Terratec Cinergy 600 TV MK3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1540_9524[] = "ProVideo PV952"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_16be_0003[] = "Medion 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c200[] = "Compro VideoMate Gold+ Pal"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c900[] = "Videomate DVB-T300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_a006[] = "KNC One TV-Station DVR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_fe01[] = "KNC One TV-Station RDS / Typhoon TV Tuner RDS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_4e42_0138[] = "LifeView FlyVIDEO3000"; +#endif +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_0000[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_ffff[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f56[] = "KNC1 DVB-S Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f60[] = "Fujitsu-Siemens Activy DVB-S Budget Rev AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f61[] = "Activy DVB-S Budget Rev GR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_5f61[] = "Activy DVB-T Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000f[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0000[] = "Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0001[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0002[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0003[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0004[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0006[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0008[] = "Technotrend/Hauppauge DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_000a[] = "Octal/Technotrend DVB-C for iTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1003[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-S DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1004[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-C DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1005[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100c[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100f[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1011[] = "Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1013[] = "SATELCO Multimedia DVB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1016[] = "WinTV-NOVA-SE DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1102[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +static const char pci_device_1131_9730[] = "SAA9730 Integrated Multimedia and Peripheral Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Networks Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "Diva Pro 2.0 S/T"; +static const char pci_device_1133_e002[] = "Diva 2.0 S/T PCI"; +static const char pci_device_1133_e003[] = "Diva Pro 2.0 U"; +static const char pci_device_1133_e004[] = "Diva 2.0 U PCI"; +static const char pci_device_1133_e005[] = "Diva 2.01 S/T PCI"; +static const char pci_device_1133_e006[] = "Diva CT S/T PCI"; +static const char pci_device_1133_e007[] = "Diva CT U PCI"; +static const char pci_device_1133_e008[] = "Diva CT Lite S/T PCI"; +static const char pci_device_1133_e009[] = "Diva CT Lite U PCI"; +static const char pci_device_1133_e00a[] = "Diva ISDN+V.90 PCI"; +static const char pci_device_1133_e00b[] = "Diva 2.02 PCI S/T"; +static const char pci_device_1133_e00c[] = "Diva 2.02 PCI U"; +static const char pci_device_1133_e00d[] = "Diva ISDN Pro 3.0 PCI"; +static const char pci_device_1133_e00e[] = "Diva ISDN+CT S/T PCI Rev 2"; +static const char pci_device_1133_e010[] = "Diva Server BRI-2M PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_110a_0021[] = "Fujitsu Siemens ISDN S0"; +#endif +static const char pci_device_1133_e011[] = "Diva Server BRI S/T Rev 2"; +static const char pci_device_1133_e012[] = "Diva Server 4BRI-8M PCI"; +static const char pci_device_1133_e013[] = "Diva Server 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_1300[] = "Diva Server V-4BRI-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_e013[] = "Diva Server 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e014[] = "Diva Server PRI-30M PCI"; +static const char pci_device_1133_e015[] = "DIVA Server PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e015_1133_e015[] = "Diva Server PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e016[] = "Diva Server Voice 4BRI PCI"; +static const char pci_device_1133_e017[] = "Diva Server Voice 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e017_1133_e017[] = "Diva Server Voice 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_1800[] = "Diva Server V-BRI-2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e019[] = "Diva Server Voice PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e019_1133_e019[] = "Diva Server Voice PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e01a[] = "Diva Server 2FX"; +static const char pci_device_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01b_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e01c[] = "Diva Server PRI Rev 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c01[] = "Diva Server PRI/E1/T1-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c02[] = "Diva Server PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c03[] = "Diva Server PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c04[] = "Diva Server PRI/E1/T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c05[] = "Diva Server V-PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c06[] = "Diva Server V-PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c07[] = "Diva Server PRI/E1/T1-8 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c08[] = "Diva Server PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c09[] = "Diva Server PRI/E1-30 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0a[] = "Diva Server PRI/E1/T1 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0b[] = "Diva Server V-PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0c[] = "Diva Server V-PRI/E1-30 Cornet NQ"; +#endif +static const char pci_device_1133_e01e[] = "Diva Server 2PRI"; +static const char pci_device_1133_e020[] = "Diva Server 4PRI"; +static const char pci_device_1133_e024[] = "Diva Server Analog-4P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_2400[] = "Diva Server V-Analog-4P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_e024[] = "Diva Server Analog-4P"; +#endif +static const char pci_device_1133_e028[] = "Diva Server Analog-8P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_2800[] = "Diva Server V-Analog-8P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_e028[] = "Diva Server Analog-8P"; +#endif +static const char pci_device_1133_e02a[] = "Diva Server IPM-300"; +static const char pci_device_1133_e02c[] = "Diva Server IPM-600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +static const char pci_device_1134_0002[] = "Dual PCI to RapidIO Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +static const char pci_device_1145_f020[] = "NinjaSCSI-32 Sony PCGA-DVD51"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "SysKonnect"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2971[] = "AT-2970LX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970TX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2973[] = "AT-2971SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2974[] = "AT-2971T Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2976[] = "AT-2970LX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970TX/2TX Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1148_4320[] = "SysKonnect SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0121[] = "Marvell RDK-8001 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0221[] = "Marvell RDK-8002 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0321[] = "Marvell RDK-8003 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0421[] = "Marvell RDK-8004 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0621[] = "Marvell RDK-8006 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0721[] = "Marvell RDK-8007 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0821[] = "Marvell RDK-8008 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0921[] = "Marvell RDK-8009 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1121[] = "Marvell RDK-8011 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1221[] = "Marvell RDK-8012 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_3221[] = "SK-9521 V2.0 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "SK-9Dxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_4500[] = "SK-9Mxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_9000[] = "SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45"; +static const char pci_device_1148_9843[] = "[Fujitsu] Gigabit Ethernet"; +static const char pci_device_1148_9e00[] = "SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2100[] = "SK-9E21 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_21d0[] = "SK-9E21D 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2200[] = "SK-9E22 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8100[] = "SK-9E81 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8200[] = "SK-9E82 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9100[] = "SK-9E91 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9200[] = "SK-9E92 Server Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0028[] = "ClassicBoard 4"; +static const char pci_device_114f_0029[] = "ClassicBoard 8"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p"; +static const char pci_device_114f_0043[] = "AccelePort 4p"; +static const char pci_device_114f_0044[] = "AccelePort 8p"; +static const char pci_device_114f_0045[] = "AccelePort 16p"; +static const char pci_device_114f_004e[] = "AccelePort 32p"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_00b0[] = "Digi Neo 4"; +static const char pci_device_114f_00b1[] = "Digi Neo 8"; +static const char pci_device_114f_00c8[] = "Digi Neo 2 DB9"; +static const char pci_device_114f_00c9[] = "Digi Neo 2 DB9 PRI"; +static const char pci_device_114f_00ca[] = "Digi Neo 2 RJ45"; +static const char pci_device_114f_00cb[] = "Digi Neo 2 RJ45 PRI"; +static const char pci_device_114f_00d0[] = "ClassicBoard 4 422"; +static const char pci_device_114f_00d1[] = "ClassicBoard 8 422"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0182[] = "RealPort2 CardBus Ethernet 10/100 (R2BE-100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_00d4[] = "Mini-PCI K56Flex Modem"; +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "Broadcom"; +static const char pci_device_1166_0000[] = "CMIC-LE"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0006[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-WS Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CMIC-LE Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0036[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0101[] = "CIOB-X2 PCI-X I/O Bridge"; +static const char pci_device_1166_0104[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0110[] = "CIOB-E I/O Bridge with Gigabit Ethernet"; +static const char pci_device_1166_0130[] = "HT1000 PCI-X bridge"; +static const char pci_device_1166_0132[] = "HT1000 PCI-Express bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0201_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0203_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0205[] = "HT1000 Legacy South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0212_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_c134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0214[] = "HT1000 Legacy IDE controller"; +static const char pci_device_1166_0217[] = "CSB6 IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0217_1028_4134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0220_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0221_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0223[] = "HT1000 USB Controller"; +static const char pci_device_1166_0225[] = "CSB5 LPC bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0227_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0230[] = "CSB5 LPC bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0230_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0234[] = "HT1000 LPC Bridge"; +static const char pci_device_1166_0240[] = "K2 SATA"; +static const char pci_device_1166_0241[] = "RAIDCore RC4000"; +static const char pci_device_1166_0242[] = "RAIDCore BC4000"; +static const char pci_device_1166_024a[] = "BCM5785 (HT1000) SATA Native SATA Mode"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0102[] = "Extended IDE Controller"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "CPU to PCI bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0601_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_060a_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC100 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +static const char pci_device_117c_0030[] = "Ultra320 SCSI Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8013[] = "ExpressPCI UL4D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8014[] = "ExpressPCI UL4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1987[] = "Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines )"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_14ef_0220[] = "PCD-RP-220S"; +#endif +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0511[] = "R5C511"; +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1180_0554[] = "R5C554"; +static const char pci_device_1180_0575[] = "R5C575 SD Bus Host Adapter"; +static const char pci_device_1180_0576[] = "R5C576 SD Bus Host Adapter"; +static const char pci_device_1180_0592[] = "R5C592 Memory Stick Bus Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0811[] = "R5C811"; +static const char pci_device_1180_0822[] = "R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0556[] = "Thinkpad X40"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_01a2[] = "Inspiron 9200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1043_1967[] = "ASUS V6800V"; +#endif +static const char pci_device_1180_0841[] = "R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394"; +static const char pci_device_1180_0852[] = "xD-Picture Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0852_1043_1967[] = "V6800V"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1025[] = "AirPlus Xtreme G DWL-G650 Adapter"; +static const char pci_device_1186_1026[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1043[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1303[] = "DFE-528TX 10/100 Fast Ethernet PCI Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1541[] = "DFE-680TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_2027[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3203[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3300[] = "DWL-510 2.4GHz Wireless PCI Adapter"; +static const char pci_device_1186_3a03[] = "AirPro DWL-A650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a04[] = "AirPro DWL-AB650 Multimode Wireless Cardbus Adapter"; +static const char pci_device_1186_3a05[] = "AirPro DWL-AB520 Multimode Wireless PCI Adapter"; +static const char pci_device_1186_3a07[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_3a08[] = "AirXpert DWL-AG520 Wireless PCI Adapter"; +static const char pci_device_1186_3a10[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a11[] = "AirXpert DWL-AG520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a12[] = "AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +static const char pci_device_1186_3a13[] = "AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a14[] = "AirPremier DWL-AG530 Wireless PCI Adapter"; +static const char pci_device_1186_3a63[] = "AirXpert DWL-AG660 Wireless Cardbus Adapter"; +static const char pci_device_1186_4000[] = "DL2000-based Gigabit Ethernet"; +static const char pci_device_1186_4300[] = "DGE-528T Gigabit Ethernet Adapter"; +static const char pci_device_1186_4c00[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_4c00_1186_4c00[] = "DGE-530T Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1186_8400[] = "D-Link DWL-650+ CardBus PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +static const char pci_device_1191_8060[] = "AEC6712 SCSI"; +static const char pci_device_1191_8080[] = "AEC67160 SCSI"; +static const char pci_device_1191_8081[] = "AEC67160S SCSI"; +static const char pci_device_1191_808a[] = "AEC67162 2-ch. LVD SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +static const char pci_device_1197_010c[] = "CompuScope 82G 8bit 2GS/s Analog Input Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Marvell Technology Group Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_138f[] = "W8300 802.11 Adapter (rev 07)"; +static const char pci_device_11ab_1fa6[] = "Marvell W8300 802.11 Adapter"; +static const char pci_device_11ab_1fa7[] = "88W8310 and 88W8000G [Libertas] 802.11g client chipset"; +static const char pci_device_11ab_1faa[] = "88w8335 [Libertas] 802.11b/g Wireless"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_1faa_1385_4e00[] = "WG511 v2 54MBit/ Wireless PC-Card"; +#endif +static const char pci_device_11ab_4320[] = "88E8001 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_0f38[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_8001[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_173c[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_811a[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_105b_0c19[] = "Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_10b8_b452[] = "EZ Card 1000 (SMC9452TXV.2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0121[] = "Marvell RDK-8001"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0321[] = "Marvell RDK-8003"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_1021[] = "Marvell RDK-8010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_5021[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_9521[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1458_e000[] = "Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_147b_1406[] = "Marvell 88E8001 Gigabit Ethernet Controller (Abit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_15d4_0047[] = "Marvell 88E8001 Gigabit Ethernet Controller (Iwill)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1695_9025[] = "Marvell 88E8001 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_17f2_1c03[] = "Marvell 88E8001 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_270f_2803[] = "Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)"; +#endif +static const char pci_device_11ab_4340[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4341[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4342[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4343[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4344[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4345[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4346[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4347[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4350[] = "88E8035 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1179_0001[] = "Marvell 88E8035 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_11ab_3521[] = "Marvell RDK-8035"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000d[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000f[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0011[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0012[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0016[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0017[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0018[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0019[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001c[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0020[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4351[] = "88E8036 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_107b_4009[] = "Marvell 88E8036 Fast Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_10f7_8338[] = "Marvell 88E8036 Fast Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_0001[] = "Marvell 88E8036 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff00[] = "Marvell 88E8036 Fast Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff10[] = "Marvell 88E8036 Fast Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_11ab_3621[] = "Marvell RDK-8036"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_13d1_ac12[] = "Abocom EFE3K - 10/100 Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_161f_203d[] = "Marvell 88E8036 Fast Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000d[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000f[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0011[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0012[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0016[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0017[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0018[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0019[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001c[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0020[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4352[] = "88E8038 PCI-E Fast Ethernet Controller"; +static const char pci_device_11ab_4360[] = "88E8052 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1043_8134[] = "Marvell 88E8052 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_107b_4009[] = "Marvell 88E8052 Gigabit Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_11ab_5221[] = "Marvell RDK-8052"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1458_e000[] = "Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1462_052c[] = "Marvell 88E8052 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1849_8052[] = "Marvell 88E8052 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_a0a0_0509[] = "Marvell 88E8052 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4361[] = "88E8050 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_107b_3015[] = "Marvell 88E8050 Gigabit Ethernet Controller (Gateway)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_11ab_5021[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3063[] = "D925XCVLK mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3439[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11ab_4362[] = "88E8053 PCI-E Gigabit Ethernet Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_103c_2a0d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1043_8142[] = "Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_109f_3197[] = "Marvell 88E8053 Gigabit Ethernet Controller (Trigem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10f7_8338[] = "Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10fd_a430[] = "Marvell 88E8053 Gigabit Ethernet Controller (SOYO)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_0001[] = "Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff00[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff10[] = "Marvell 88E8053 Gigabit Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_11ab_5321[] = "Marvell RDK-8053"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c240[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c241[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c242[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c243[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c244[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_13d1_ac11[] = "EGE5K - Giga Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1458_e000[] = "Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1462_058c[] = "Marvell 88E8053 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_14c0_0012[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1558_04a0[] = "Marvell 88E8053 Gigabit Ethernet Controller (Clevo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_15bd_1003[] = "Marvell 88E8053 Gigabit Ethernet Controller (DFI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203c[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1695_9029[] = "Marvell 88E8053 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17f2_2c08[] = "Marvell 88E8053 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17ff_0585[] = "Marvell 88E8053 Gigabit Ethernet Controller (Quanta)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1849_8053[] = "Marvell 88E8053 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000c[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0010[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0013[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0014[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0015[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001a[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001d[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001f[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0021[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0022[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_270f_2801[] = "Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_a0a0_0506[] = "Marvell 88E8053 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4363[] = "88E8055 PCI-E Gigabit Ethernet Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_5005[] = "Belkin F5D5005 Gigabit Desktop Network PCI Card"; +static const char pci_device_11ab_5040[] = "MV88SX5040 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5041[] = "MV88SX5041 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5080[] = "MV88SX5080 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5081[] = "MV88SX5081 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_6041[] = "MV88SX6041 4-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6081[] = "MV88SX6081 8-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6460[] = "MV64360/64361/64362 System Controller"; +static const char pci_device_11ab_6480[] = "MV64460/64461/64462 System Controller"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +static const char pci_device_11af_0001[] = "Cinema"; +static const char pci_device_11af_ee40[] = "Digidesign Audiomedia III"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +static const char pci_device_11bd_002e[] = "PCTV 40i"; +static const char pci_device_11bd_bede[] = "Pinnacle AV/DV Studio Capture Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Agere Systems"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2203[] = "PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2204[] = "PRO/100+ MiniPCI on Armada E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1033_80a8[] = "Versa Note Vxi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1468_0450[] = "Evo N600c"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_4005_144f[] = "LifeBook C Series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_048c[] = "V.92 56K WinModem"; +static const char pci_device_11c1_048f[] = "V.92 56k WinModem"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_8086_524c[] = "D865PERL mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +static const char pci_device_11c1_8110[] = "T8110 H.100/H.110 TDM switch"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_8110_12d9_000c[] = "E1/T1 PMXc cPCI carrier card"; +#endif +static const char pci_device_11c1_ab10[] = "WL60010 Wireless LAN MAC"; +static const char pci_device_11c1_ab11[] = "WL60040 Multimode Wireles LAN MAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab12[] = "WaveLAN 11abg Cardbus card (Model 1102)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab13[] = "WaveLAN 11abg MiniPCI card (Model 0512)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab15[] = "WaveLAN 11abg Cardbus card (Model 1106)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab16[] = "WaveLAN 11abg MiniPCI card (Model 0516)"; +#endif +static const char pci_device_11c1_ab20[] = "ORiNOCO PCI Adapter"; +static const char pci_device_11c1_ab21[] = "Agere Wireless PCI Adapter"; +static const char pci_device_11c1_ab30[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab30_14cd_2012[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#endif +static const char pci_device_11c1_ed00[] = "ET-131x PCI-E Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1535[] = "Blackfin BF535 processor"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +static const char pci_device_11d4_5340[] = "AD1881 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_12f8_8a02[] = "Tekram Video Kit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_13c2_0000[] = "MediaFocus Satellite TV Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1de1_9fff[] = "Video Kit C210"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_0001[] = "COM-ON-AIR Dosch&Amand DECT"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 32 port w/external I/F"; +static const char pci_device_11fe_0002[] = "RocketPort 8 port w/external I/F"; +static const char pci_device_11fe_0003[] = "RocketPort 16 port w/external I/F"; +static const char pci_device_11fe_0004[] = "RocketPort 4 port w/quad cable"; +static const char pci_device_11fe_0005[] = "RocketPort 8 port w/octa cable"; +static const char pci_device_11fe_0006[] = "RocketPort 8 port w/RJ11 connectors"; +static const char pci_device_11fe_0007[] = "RocketPort 4 port w/RJ11 connectors"; +static const char pci_device_11fe_0008[] = "RocketPort 8 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_0009[] = "RocketPort 16 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_000a[] = "RocketPort Plus 4 port"; +static const char pci_device_11fe_000b[] = "RocketPort Plus 8 port"; +static const char pci_device_11fe_000c[] = "RocketModem 6 port"; +static const char pci_device_11fe_000d[] = "RocketModem 4-port"; +static const char pci_device_11fe_000e[] = "RocketPort Plus 2 port RS232"; +static const char pci_device_11fe_000f[] = "RocketPort Plus 2 port RS422"; +static const char pci_device_11fe_0801[] = "RocketPort UPCI 32 port w/external I/F"; +static const char pci_device_11fe_0802[] = "RocketPort UPCI 8 port w/external I/F"; +static const char pci_device_11fe_0803[] = "RocketPort UPCI 16 port w/external I/F"; +static const char pci_device_11fe_0805[] = "RocketPort UPCI 8 port w/octa cable"; +static const char pci_device_11fe_080c[] = "RocketModem III 8 port"; +static const char pci_device_11fe_080d[] = "RocketModem III 4 port"; +static const char pci_device_11fe_0812[] = "RocketPort UPCI Plus 8 port RS422"; +static const char pci_device_11fe_0903[] = "RocketPort Compact PCI 16 port w/external I/F"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +static const char pci_device_11ff_0003[] = "AG-5"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 CardBus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 CardBus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 CardBus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 CardBus Controller"; +static const char pci_device_1217_6933[] = "OZ6933/711E1 CardBus/SmartCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ601/6912/711E0 CardBus/SmartCardBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1014_020c[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1217_7110[] = "OZ711Mx 4-in-1 MemoryCardBus Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7112[] = "OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller"; +static const char pci_device_1217_7113[] = "OZ711EC1 SmartCardBus Controller"; +static const char pci_device_1217_7114[] = "OZ711M1/MC1 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7134[] = "OZ711MP1/MS1 MemoryCardBus Controller"; +static const char pci_device_1217_71e2[] = "OZ711E2 SmartCardBus Controller"; +static const char pci_device_1217_7212[] = "OZ711M2 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7213[] = "OZ6933E CardBus Controller"; +static const char pci_device_1217_7223[] = "OZ711M3/MC3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7233[] = "OZ711MP3/MS3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3 2000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0057[] = "Voodoo3 3000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0003[] = "Voodoo5 PCI 5500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +static const char pci_device_1227_0006[] = "Raptor GFX 8P"; +static const char pci_device_1227_0023[] = "Raptor GFX [1100T]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000f[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_1809_0016[] = "Emuzed MAUI-III PCI PVR FM TV"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +static const char pci_device_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +static const char pci_device_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +static const char pci_device_1244_2700[] = "Fritz!Card DSL SL"; +static const char pci_device_1244_2900[] = "Fritz!Card DSL v2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infortrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +static const char pci_device_1259_a117[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a120[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204 Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125b_1400_1186_1100[] = "AX8814X Based PCI Fast Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0101[] = "Saturn 4520P"; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_153b_111b[] = "Terratec 128i PCI"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700/E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_0e11_0098[] = "Evo N600c"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00b1[] = "Latitude C600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Intersil Corporation"; +static const char pci_device_1260_3872[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3872_1468_0202[] = "LAN-Express IEEE 802.11b Wireless LAN"; +#endif +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3700[] = "DWL-520 Wireless PCI Adapter, Rev E1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1385_4105[] = "MA311 802.11b wireless adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_16a5_1601[] = "AIR.mate PC-400 PCI Wireless LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_3886[] = "ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3886_17cf_0037[] = "XG-901 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_3890[] = "ISL3890 [Prism GT/Prism Duette]/ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2802[] = "SMC2802W Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2835[] = "SMC2835W Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_a835[] = "SMC2835W V2 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_4203[] = "WN4201B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee03[] = "SMC2802W V2 Wireless PCI Adapter [ISL3886]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee08[] = "SMC2835W V3 EU Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1186_3202[] = "DWL-G650 A1 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1259_c104[] = "CG-WLCB54GT Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1385_4800[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_16a5_1605[] = "ALLNET ALL0271 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0014[] = "XG-600 and clones Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0020[] = "XG-900 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +static const char pci_device_1260_ffff[] = "ISL3886IK"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_ffff_1260_0000[] = "Senao 3054MP+ (J) mini-PCI WLAN 802.11g adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +static const char pci_device_126c_1211[] = "10/100BaseTX [RTL81xx]"; +static const char pci_device_126c_126c[] = "802.11b Wireless Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0501[] = "SM501 VoyagerGX Rev. AA"; +static const char pci_device_126f_0510[] = "SM501 VoyagerGX Rev. B"; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0730[] = "SM731 Cougar3DR"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1171[] = "ES1373 [AudioPCI] (also Creative Labs CT5803)"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_8001[] = "CT4751 board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_8001[] = "Sound Blaster 16PCI 4.1ch"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +static const char pci_device_1278_0710[] = "TPE5 PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0060[] = "TM8000 Northbridge"; +static const char pci_device_1279_0061[] = "TM8000 AGP bridge"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1005_127a[] = "AOpen FM56-P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9102[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8211[] = "ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller))"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8211_1043_8138[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_1283_8212[] = "IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8212_1283_0001[] = "IT/ITE8212 Dual channel ATA RAID controller"; +#endif +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8872[] = "IT8874F PCI Dual Serial Port Controller"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +static const char pci_device_12a3_8105[] = "T8105 H100 Digital Switch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_0002[] = "AU8830 [Vortex2] Based Sound Card With A3D Support"; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1014_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_10a9_8002[] = "Acenic Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +static const char pci_device_12ae_00fa[] = "Farallon PN9100-T Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "3Com Corp, Modem Division"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +static const char pci_device_12c4_0001[] = "Blue HEAT/PCI 8 (RS232/CL/RJ11)"; +static const char pci_device_12c4_0002[] = "Blue HEAT/PCI 4 (RS232)"; +static const char pci_device_12c4_0003[] = "Blue HEAT/PCI 2 (RS232)"; +static const char pci_device_12c4_0004[] = "Blue HEAT/PCI 8 (UNIV, RS485)"; +static const char pci_device_12c4_0005[] = "Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485)"; +static const char pci_device_12c4_0006[] = "Blue HEAT/PCI 4 (OPTO, RS485)"; +static const char pci_device_12c4_0007[] = "Blue HEAT/PCI 2+2 (RS232/485)"; +static const char pci_device_12c4_0008[] = "Blue HEAT/PCI 2 (OPTO, Tx, RS485)"; +static const char pci_device_12c4_0009[] = "Blue HEAT/PCI 2+6 (RS232/485)"; +static const char pci_device_12c4_000a[] = "Blue HEAT/PCI 8 (Tx, RS485)"; +static const char pci_device_12c4_000b[] = "Blue HEAT/PCI 4 (Tx, RS485)"; +static const char pci_device_12c4_000c[] = "Blue HEAT/PCI 2 (20 MHz, RS485)"; +static const char pci_device_12c4_000d[] = "Blue HEAT/PCI 2 PTM"; +static const char pci_device_12c4_0100[] = "NT960/PCI"; +static const char pci_device_12c4_0201[] = "cPCI Titan - 2 Port"; +static const char pci_device_12c4_0202[] = "cPCI Titan - 4 Port"; +static const char pci_device_12c4_0300[] = "CTI PCI UART 2 (RS232)"; +static const char pci_device_12c4_0301[] = "CTI PCI UART 4 (RS232)"; +static const char pci_device_12c4_0302[] = "CTI PCI UART 8 (RS232)"; +static const char pci_device_12c4_0310[] = "CTI PCI UART 1+1 (RS232/485)"; +static const char pci_device_12c4_0311[] = "CTI PCI UART 2+2 (RS232/485)"; +static const char pci_device_12c4_0312[] = "CTI PCI UART 4+4 (RS232/485)"; +static const char pci_device_12c4_0320[] = "CTI PCI UART 2"; +static const char pci_device_12c4_0321[] = "CTI PCI UART 4"; +static const char pci_device_12c4_0322[] = "CTI PCI UART 8"; +static const char pci_device_12c4_0330[] = "CTI PCI UART 2 (RS485)"; +static const char pci_device_12c4_0331[] = "CTI PCI UART 4 (RS485)"; +static const char pci_device_12c4_0332[] = "CTI PCI UART 8 (RS485)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +static const char pci_device_12d4_0200[] = "T1 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies Inc"; +static const char pci_device_12d5_0003[] = "BSP16"; +static const char pci_device_12d5_1000[] = "BSP15"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +static const char pci_device_12d8_8150[] = "PCI to PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +static const char pci_device_12d9_0002[] = "PCI Prosody"; +static const char pci_device_12d9_0004[] = "cPCI Prosody"; +static const char pci_device_12d9_0005[] = "Aculab E1/T1 PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +static const char pci_device_12de_0200[] = "CryptoSwift CS200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +static const char pci_device_12fb_0001[] = "PMC-MAI"; +static const char pci_device_12fb_00f5[] = "F5 Dakar"; +static const char pci_device_12fb_02ad[] = "PMC-2MAI"; +static const char pci_device_12fb_2adc[] = "ePMC-2ADC"; +static const char pci_device_12fb_3100[] = "PRO-3100"; +static const char pci_device_12fb_3500[] = "PRO-3500"; +static const char pci_device_12fb_4d4f[] = "Modena"; +static const char pci_device_12fb_8120[] = "ePMC-8120"; +static const char pci_device_12fb_da62[] = "Daytona C6201 PCI (Hurricane)"; +static const char pci_device_12fb_db62[] = "Ingliston XBIF"; +static const char pci_device_12fb_dc62[] = "Ingliston PLX9054"; +static const char pci_device_12fb_dd62[] = "Ingliston JTAG/ISP"; +static const char pci_device_12fb_eddc[] = "ePMC-MSDDC"; +static const char pci_device_12fb_fa01[] = "ePMC-FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Measurement Computing"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +static const char pci_device_1307_004d[] = "PCI-QUAD04"; +static const char pci_device_1307_0052[] = "PCI-DAS4020/12"; +static const char pci_device_1307_0054[] = "PCI-DIO96"; +static const char pci_device_1307_005e[] = "PCI-DAS6025"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "Linksys"; +static const char pci_device_1317_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_0985[] = "NC100 Network Everywhere Fast Ethernet 10/100"; +static const char pci_device_1317_1985[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_2850[] = "HSP MicroModem 56"; +static const char pci_device_1317_5120[] = "ADMtek ADM5120 OpenGate System-on-Chip"; +static const char pci_device_1317_8201[] = "ADMtek ADM8211 802.11b Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_10b8_2635[] = "SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_1317_8201[] = "SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card"; +#endif +static const char pci_device_1317_8211[] = "ADMtek ADM8211 802.11b Wireless Interface"; +static const char pci_device_1317_9511[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "GNIC-II PCI Gigabit Ethernet [Hamachi]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0801_1319_1319[] = "FM801 PCI Audio"; +#endif +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0802_1319_1319[] = "FM801 PCI Joystick"; +#endif +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_2081[] = "CyberSerial (8-port) ST16654"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +static const char pci_device_1331_0030[] = "ENP-2611"; +static const char pci_device_1331_8200[] = "82600 Host Bridge"; +static const char pci_device_1331_8201[] = "82600 IDE"; +static const char pci_device_1331_8202[] = "82600 USB"; +static const char pci_device_1331_8210[] = "82600 PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +static const char pci_device_1332_5425[] = "MM-5425CN PCI 64/66 Memory Module with Battery Backup"; +static const char pci_device_1332_6140[] = "MM-6140D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_2189[] = "HSP56 MicroModem"; +static const char pci_device_134d_2486[] = "2304WT V.92 MDC Modem"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7890_134d_0001[] = "PCT789 adapter"; +#endif +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_5101[] = "Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32)"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +static const char pci_device_1360_0101[] = "PCI32 DCF77 Radio Clock"; +static const char pci_device_1360_0102[] = "PCI509 DCF77 Radio Clock"; +static const char pci_device_1360_0103[] = "PCI510 DCF77 Radio Clock"; +static const char pci_device_1360_0201[] = "GPS167PCI GPS Receiver"; +static const char pci_device_1360_0202[] = "GPS168PCI GPS Receiver"; +static const char pci_device_1360_0203[] = "GPS169PCI GPS Receiver"; +static const char pci_device_1360_0301[] = "TCR510PCI IRIG Timecode Reader"; +static const char pci_device_1360_0302[] = "TCR167PCI IRIG Timecode Reader"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +static const char pci_device_136b_ff01[] = "KL5A72002 Motion JPEG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +static const char pci_device_1371_434e[] = "GigaCard Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1371_434e_1371_434e[] = "N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd."; +static const char pci_device_1374_0024[] = "Silicom Dual port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0025[] = "Silicom Quad port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0026[] = "Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0027[] = "Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0029[] = "Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002a[] = "Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002b[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002c[] = "Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002d[] = "Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002e[] = "Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002f[] = "Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0030[] = "Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0031[] = "Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter"; +static const char pci_device_1374_0032[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_0034[] = "Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0035[] = "Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0036[] = "Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0037[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0038[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0039[] = "Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_003a[] = "Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +static const char pci_device_137a_0001[] = "PCI-324 Audiowire Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +static const char pci_device_1382_0001[] = "ARC88 audio recording card"; +static const char pci_device_1382_2008[] = "Prodif 96 Pro sound system"; +static const char pci_device_1382_2088[] = "Marc 8 Midi sound system"; +static const char pci_device_1382_20c8[] = "Marc A sound system"; +static const char pci_device_1382_4008[] = "Marc 2 sound system"; +static const char pci_device_1382_4010[] = "Marc 2 Pro sound system"; +static const char pci_device_1382_4048[] = "Marc 4 MIDI sound system"; +static const char pci_device_1382_4088[] = "Marc 4 Digi sound system"; +static const char pci_device_1382_4248[] = "Marc X sound system"; +static const char pci_device_1382_4424[] = "TRACE D4 Sound System"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_0013[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_311a[] = "GA511 Gigabit Ethernet"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_4105[] = "MA311 802.11b wireless adapter"; +static const char pci_device_1385_4400[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4600[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4601[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4610[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4800[] = "WG511(v1) 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4900[] = "WG311v1 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4a00[] = "WAG311 802.11a/g Wireless PCI Adapter"; +static const char pci_device_1385_4b00[] = "WG511T 108 Mbps Wireless PC Card"; +static const char pci_device_1385_4c00[] = "WG311v2 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4d00[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4e00[] = "WG511v2 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4f00[] = "WG511U Double 108 Mbps Wireless PC Card"; +static const char pci_device_1385_5200[] = "GA511 Gigabit PC Card"; +static const char pci_device_1385_620a[] = "GA620 Gigabit Ethernet"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630 Gigabit Ethernet"; +static const char pci_device_1385_6b00[] = "WG311v3 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_6d00[] = "WPNT511 RangeMax™ 240 Mbps Wireless PC Card"; +static const char pci_device_1385_f004[] = "FA310TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1141[] = "Industrio CP-114"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_16b8[] = "ISDN network Controller [HFC-8S]"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1708[] = "ISDN Adapter (PCI Bus, D, C, ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +static const char pci_device_13a3_001d[] = "7956 Security Processor"; +static const char pci_device_13a3_0020[] = "7955 Security Processor"; +static const char pci_device_13a3_0026[] = "8155 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0152[] = "XR17C/D152 Dual PCI UART"; +static const char pci_device_13a8_0154[] = "XR17C154 Quad UART"; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink Adapter v1"; +static const char pci_device_13c0_0020[] = "SyncLink SCC Adapter"; +static const char pci_device_13c0_0030[] = "SyncLink Multiport Adapter"; +static const char pci_device_13c0_0210[] = "SyncLink Adapter v2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "5xxx/6xxx-series PATA-RAID"; +static const char pci_device_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13c1_1001_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#endif +static const char pci_device_13c1_1002[] = "9xxx-series SATA-RAID"; +static const char pci_device_13c1_1003[] = "9550SX SATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +static const char pci_device_13c6_0520[] = "CEI-520 A429 Card"; +static const char pci_device_13c6_0620[] = "CEI-620 A429 Card"; +static const char pci_device_13c6_0820[] = "CEI-820 A429 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card"; +static const char pci_device_13d0_2200[] = "B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab03[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +static const char pci_device_13d1_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Intraserver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc / IC Plus Corp"; +static const char pci_device_13f0_0200[] = "IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +static const char pci_device_13f0_1023[] = "IC Plus IP1000 Family Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0011[] = "CMI8738"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8035[] = "CUSI-FX motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1681_a000[] = "Gamesurround MUSE XL"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1240[] = "PCI-1240 4-channel stepper motor controller card"; +static const char pci_device_13fe_1600[] = "PCI-1612 4-port RS-232/422/485 PCI communication card"; +static const char pci_device_13fe_1733[] = "PCI-1733 32-channel isolated digital input card"; +static const char pci_device_13fe_1752[] = "PCI-1752"; +static const char pci_device_13fe_1754[] = "PCI-1754"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0110[] = "Lava DSerial-PCI Port A"; +static const char pci_device_1407_0111[] = "Lava DSerial-PCI Port B"; +static const char pci_device_1407_0120[] = "Quattro-PCI A"; +static const char pci_device_1407_0121[] = "Quattro-PCI B"; +static const char pci_device_1407_0180[] = "Lava Octo A"; +static const char pci_device_1407_0181[] = "Lava Octo B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0220[] = "Lava Quattro PCI Ports A/B"; +static const char pci_device_1407_0221[] = "Lava Quattro PCI Ports C/D"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "VIA Technologies Inc."; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24] PCI Multi-Channel I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_1712[] = "Hoontech ST Audio DSP 24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d630[] = "M-Audio Delta 1010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d631[] = "M-Audio Delta DiO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d632[] = "M-Audio Delta 66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d633[] = "M-Audio Delta 44"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d634[] = "M-Audio Delta Audiophile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d635[] = "M-Audio Delta TDIF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d637[] = "M-Audio Delta RBUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d638[] = "M-Audio Delta 410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63b[] = "M-Audio Delta 1010LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63c[] = "Digigram VX442"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1416_1712[] = "Hoontech ST Audio DSP 24 Media 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1115[] = "EWS88 MT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1125[] = "EWS88 MT (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112b[] = "EWS88 D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112c[] = "EWS88 D (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1130[] = "EWX 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1138[] = "DMX 6fire 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1151[] = "PHASE88"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_16ce_1040[] = "Edirol DA-2496"; +#endif +static const char pci_device_1412_1724[] = "VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_1724[] = "AMP Ltd AUDIO2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3630[] = "M-Audio Revolution 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3631[] = "M-Audio Revolution 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1145[] = "Aureon 7.1 Space"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1147[] = "Aureon 5.1 Sky"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1153[] = "Aureon 7.1 Universe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f641[] = "ZNF3-150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f645[] = "ZNF3-250"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2050[] = "CyberPro (4-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2051[] = "CyberSerial 4S Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9510[] = "OX16PCI954 (Quad 16950 UART) function 1 (Disabled)"; +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +static const char pci_device_1415_9523[] = "OX16PCI952 Integrated Parallel Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +static const char pci_device_1420_8002[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part)"; +static const char pci_device_1420_8003[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "Chelsio Communications Inc"; +static const char pci_device_1425_000b[] = "T210 Protocol Engine"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +static const char pci_device_142e_4020[] = "VM2-2 [Video Maker 2] MPEG1/2 Encoder"; +static const char pci_device_142e_4337[] = "VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +static const char pci_device_1432_9130[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "RTD Embedded Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8164[] = "PCI-8164"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +static const char pci_device_1458_0c11[] = "K8NS Pro Mainboard"; +static const char pci_device_1458_e911[] = "GN-WIAG02"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +static const char pci_device_1461_f436[] = "AVerTV Hybrid+FM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +static const char pci_device_1462_5501[] = "nVidia NV15DDR [GeForce2 Ti]"; +static const char pci_device_1462_6819[] = "Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G]"; +static const char pci_device_1462_6825[] = "PCI Card wireless 11g [PC54G]"; +static const char pci_device_1462_6834[] = "RaLink RT2500 802.11g [PC54G2]"; +static const char pci_device_1462_8725[] = "NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter"; +static const char pci_device_1462_9000[] = "NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter"; +static const char pci_device_1462_9110[] = "GeFORCE FX5200"; +static const char pci_device_1462_9119[] = "NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter"; +static const char pci_device_1462_9591[] = "nVidia Corporation NV36 [GeForce FX 5700LE]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +static const char pci_device_146c_1430[] = "FE-1430TX Fast Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +static const char pci_device_1497_1497[] = "SMA Technologie AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +static const char pci_device_1498_0330[] = "TPMC816 2 Channel CAN bus controller."; +static const char pci_device_1498_0385[] = "TPMC901 Extended CAN bus with 2/4/6 CAN controller"; +static const char pci_device_1498_21cd[] = "TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_30c8[] = "TPCI200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +static const char pci_device_149d_0001[] = "Video Toaster for PC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "PulsarSRB"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +static const char pci_device_14b9_a505[] = "Cisco Aironet CB20a 802.11a Wireless LAN Adapter"; +static const char pci_device_14b9_a506[] = "Cisco Aironet Mini PCI b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +static const char pci_device_14c1_8043[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alliance Semiconductor Corporation"; +static const char pci_device_14d9_0010[] = "AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon]"; +static const char pci_device_14d9_9000[] = "AS90L10204/10208 HyperTransport to PCI-X Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +static const char pci_device_14db_2182[] = "AFAVLAB Technology Inc. 8-port serial card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_0800[] = "Sentry5 Chipcommon I/O Controller"; +static const char pci_device_14e4_0804[] = "Sentry5 PCI Bridge"; +static const char pci_device_14e4_0805[] = "Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_0806[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_080b[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_080f[] = "Sentry5 DDR/SDR RAM Controller"; +static const char pci_device_14e4_0811[] = "Sentry5 External Interface Core"; +static const char pci_device_14e4_0816[] = "BCM3302 Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_1600[] = "NetXtreme BCM5752 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1601[] = "NetXtreme BCM5752M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128a[] = "1000Base-T (PCI) [A7061A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128b[] = "1000Base-SX (PCI) [A7073A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12a4[] = "Core Lan 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12c1[] = "IOX Core Lan 1000Base-T [A7109AX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_1300[] = "Core LAN/SCSI Combo [A6794A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8010[] = "IO9/IO10 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8011[] = "Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8012[] = "Gigabit Ethernet (Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_10a9_8010[] = "SGI IO9 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1734_100b[] = "Primergy RX300"; +#endif +static const char pci_device_14e4_164a[] = "NetXtreme II BCM5706 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3101[] = "NC370T Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164c[] = "NetXtreme II BCM5708 Gigabit Ethernet"; +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1653_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1654[] = "NetXtreme BCM5705_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3100[] = "NC1020 HP ProLiant Gigabit Server Adapter 32 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3226[] = "NC150T 4-port Gigabit Combo Switch & Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1659[] = "NetXtreme BCM5721 Gigabit Ethernet PCI Express"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1014_02c6[] = "eServer xSeries server mainboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7031[] = "NC320T PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7032[] = "NC320i PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1734_1061[] = "Primergy RX300 S2"; +#endif +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165d_1028_865d[] = "Latitude D400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_165e[] = "NetXtreme BCM5705M_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1668[] = "NetXtreme BCM5714 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1668_103c_7039[] = "NC324i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_166a[] = "NetXtreme BCM5780 Gigabit Ethernet"; +static const char pci_device_14e4_166b[] = "NetXtreme BCM5780S Gigabit Ethernet"; +static const char pci_device_14e4_166e[] = "570x 10/100 Integrated Controller"; +static const char pci_device_14e4_1677[] = "NetXtreme BCM5751 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0182[] = "Latitude D610"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_01ad[] = "Optiplex GX620"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1734_105d[] = "Scenic W620"; +#endif +static const char pci_device_14e4_1678[] = "NetXtreme BCM5715 Gigabit Ethernet"; +static const char pci_device_14e4_167d[] = "NetXtreme BCM5751M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167e[] = "NetXtreme BCM5751F Fast Ethernet PCI Express"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_103c_12bc[] = "HP d530 CMT (DG746A)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_169c[] = "NetXtreme BCM5788 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_169c_103c_308b[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_169d[] = "NetLink BCM5789 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16aa[] = "NetXtreme II BCM5706S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16aa_103c_3102[] = "NC370F Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16ac[] = "NetXtreme II BCM5708S Gigabit Ethernet"; +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702A3 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12c3[] = "Combo FC/GigE-SX [A9782A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12ca[] = "Combo FC/GigE-T [A9784A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_16dd[] = "NetLink BCM5781 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16f7[] = "NetXtreme BCM5753 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fd[] = "NetXtreme BCM5753M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fe[] = "NetXtreme BCM5753F Fast Ethernet PCI Express"; +static const char pci_device_14e4_170c[] = "BCM4401-B0 100Base-TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_170d[] = "NetXtreme BCM5901 100Base-TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170d_1014_0545[] = "ThinkPad R40e (2684-HVG) builtin ethernet controller"; +#endif +static const char pci_device_14e4_170e[] = "NetXtreme BCM5901 100Base-TX"; +static const char pci_device_14e4_3352[] = "BCM3352"; +static const char pci_device_14e4_3360[] = "BCM3360"; +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4303 802.11b Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1028_0407[] = "TrueMobile 1180 Onboard WLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1043_0120[] = "WL-103b Wireless LAN PC Card"; +#endif +static const char pci_device_14e4_4305[] = "BCM4307 V.90 56k Modem"; +static const char pci_device_14e4_4306[] = "BCM4307 Ethernet Controller"; +static const char pci_device_14e4_4307[] = "BCM4307 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4310[] = "BCM4310 Chipcommon I/OController"; +static const char pci_device_14e4_4312[] = "BCM4310 UART"; +static const char pci_device_14e4_4313[] = "BCM4310 Ethernet Controller"; +static const char pci_device_14e4_4315[] = "BCM4310 USB Controller"; +static const char pci_device_14e4_4318[] = "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_103c_1356[] = "nx6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0311[] = "Aspire 3022WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0312[] = "TravelMate 2410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_0449[] = "Gateway 7510GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_4318[] = "WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_16ec_0119[] = "U.S.Robotics Wireless MAXg PC Card"; +#endif +static const char pci_device_14e4_4319[] = "Dell Wireless 1470 DualBand WLAN"; +static const char pci_device_14e4_4320[] = "BCM4306 802.11b/g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0001[] = "TrueMobile 1300 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0003[] = "Wireless 1350 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12f4[] = "nx9500 Built-in Wireless"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12fa[] = "Presario R3000 802.11b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1043_100f[] = "WL-100G"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1057_7025[] = "WN825G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_106b_004e[] = "AirPort Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_144f_7050[] = "eMachines M6805 802.11g Built-in Wireless"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_14e4_4320[] = "Linksys WMP54G PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1737_4320[] = "WPC54G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7001[] = "Belkin F5D7001 High-Speed Mode Wireless G Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7010[] = "Belkin F5D7010 54g Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_185f_1220[] = "Acer TravelMate 290E WLAN Mini-PCI Card"; +#endif +static const char pci_device_14e4_4321[] = "BCM4306 802.11a Wireless LAN Controller"; +static const char pci_device_14e4_4322[] = "BCM4306 UART"; +static const char pci_device_14e4_4324[] = "BCM4309 802.11a/b/g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0001[] = "Truemobile 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0003[] = "Truemobile 1450 MiniPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_4325[] = "BCM43xG 802.11b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0003[] = "Wireless Notebook Adapter MN-720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0004[] = "Wireless PCI Adapter MN-730"; +#endif +static const char pci_device_14e4_4326[] = "BCM4307 Chipcommon I/O Controller?"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_1043_80a8[] = "A7V8X motherboard"; +#endif +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4403[] = "BCM4402 V.90 56k Modem"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4412 10/100BaseT"; +static const char pci_device_14e4_4430[] = "BCM44xx CardBus iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4432[] = "BCM4432 CardBus 10/100BaseT"; +static const char pci_device_14e4_4610[] = "BCM4610 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4611[] = "BCM4610 Sentry5 iLine32 HomePNA 1.0"; +static const char pci_device_14e4_4612[] = "BCM4610 Sentry5 V.90 56k Modem"; +static const char pci_device_14e4_4613[] = "BCM4610 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4614[] = "BCM4610 Sentry5 External Interface"; +static const char pci_device_14e4_4615[] = "BCM4610 Sentry5 USB Controller"; +static const char pci_device_14e4_4704[] = "BCM4704 PCI to SB Bridge"; +static const char pci_device_14e4_4705[] = "BCM4704 Sentry5 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4706[] = "BCM4704 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4707[] = "BCM4704 Sentry5 USB Controller"; +static const char pci_device_14e4_4708[] = "BCM4704 Crypto Accelerator"; +static const char pci_device_14e4_4710[] = "BCM4710 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4711[] = "BCM47xx Sentry5 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4712[] = "BCM47xx V.92 56k modem"; +static const char pci_device_14e4_4713[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4714[] = "BCM47xx Sentry5 External Interface"; +static const char pci_device_14e4_4715[] = "Sentry5 USB Controller"; +static const char pci_device_14e4_4716[] = "BCM47xx Sentry5 USB Host Controller"; +static const char pci_device_14e4_4717[] = "BCM47xx Sentry5 USB Device Controller"; +static const char pci_device_14e4_4718[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_4719[] = "BCM47xx/53xx RoboSwitch Core"; +static const char pci_device_14e4_4720[] = "BCM4712 MIPS CPU"; +static const char pci_device_14e4_5365[] = "BCM5365P Sentry5 Host Bridge"; +static const char pci_device_14e4_5600[] = "BCM5600 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5605[] = "BCM5605 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5615[] = "BCM5615 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5625[] = "BCM5625 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5645[] = "BCM5645 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5670[] = "BCM5670 8-Port 10GE Ethernet Switch Fabric"; +static const char pci_device_14e4_5680[] = "BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5690[] = "BCM5690 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5691[] = "BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5692[] = "BCM5692 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +static const char pci_device_14e4_5822[] = "BCM5822 Crypto Accelerator"; +static const char pci_device_14e4_5823[] = "BCM5823 Crypto Accelerator"; +static const char pci_device_14e4_5824[] = "BCM5824 Crypto Accelerator"; +static const char pci_device_14e4_5840[] = "BCM5840 Crypto Accelerator"; +static const char pci_device_14e4_5841[] = "BCM5841 Crypto Accelerator"; +static const char pci_device_14e4_5850[] = "BCM5850 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +static const char pci_device_14ea_ab07[] = "RTL81xx RealTek Ethernet"; +static const char pci_device_14ea_ab08[] = "FNW-3602-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1085[] = "HCF V90 56k Data/Fax/Voice/Spkp PCI Modem"; +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1620[] = "AccessRunner V2 PCI ADSL Arbitration Device"; +static const char pci_device_14f1_1621[] = "AccessRunner V2 PCI ADSL Interface Device"; +static const char pci_device_14f1_1622[] = "AccessRunner V2 PCI ADSL Yukon WAN Adapter"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1811[] = "Conextant MiniPCI Network Adapter"; +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2045_14f1_2045[] = "Generic SoftK56"; +#endif +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_2f02[] = "HSF 56k HSFi Data/Fax"; +static const char pci_device_14f1_2f11[] = "HSF 56k HSFi Modem"; +static const char pci_device_14f1_2f20[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +static const char pci_device_14f1_8800[] = "CX23880/1/2/3 PCI Video and Audio Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9001[] = "Nova-T DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9200[] = "Nova-SE2 DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9202[] = "Nova-S-Plus DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9402[] = "WinTV-HVR1100 DVB-T/Hybrid"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9802[] = "WinTV-HVR1100 DVB-T/Hybrid (Low Profile)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_00f8[] = "ATI TV Wonder Pro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_a101[] = "HDTV Wonder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6613[] = "Leadtek Winfast 2000XP Expert"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6620[] = "Leadtek Winfast DV2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_665f[] = "WinFast DTV1000-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d003[] = "IODATA GV-VCP3/PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d035[] = "IODATA GV/BCTV7E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1421_0334[] = "Instant TV DVB-T PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000a[] = "AVerTV 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000b[] = "AverTV Studio 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_8011[] = "UltraTV Media Center PCI 550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14c7_0107[] = "GDI Black Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0342[] = "Digital-Logic MICROSPACE Entertainment Center (MEC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_153b_1166[] = "Cinergy 1400 DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1540_2580[] = "Provideo PV259"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4811[] = "PixelView"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4813[] = "Club 3D ZAP1000 MCE Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a1[] = "KWorld/VStream XPert DVB-T with cx22702"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08b2[] = "KWorld DVB-S 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_a8a6[] = "digitalnow DNTV Live! DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1822_0025[] = "digitalnow DNTV Live! DVB-T Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d500[] = "FusionHDTV 5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d810[] = "FusionHDTV 3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db00[] = "FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db11[] = "FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db50[] = "FusionHDTV DVB-T Dual Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8801[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8801_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +static const char pci_device_14f1_8802[] = "CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8804[] = "CX23880/1/2/3 PCI Video and Audio Decoder [IR Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8804_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +static const char pci_device_14f1_8811[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +static const char pci_device_14f2_0120[] = "EV1000 bridge"; +static const char pci_device_14f2_0121[] = "EV1000 Parallel port"; +static const char pci_device_14f2_0122[] = "EV1000 Serial port"; +static const char pci_device_14f2_0123[] = "EV1000 Keyboard controller"; +static const char pci_device_14f2_0124[] = "EV1000 Mouse controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BroadLogic"; +static const char pci_device_14f3_2030[] = "2030 DVB-S Satellite Reciever"; +static const char pci_device_14f3_2050[] = "2050 DVB-T Terrestrial (Cable) Reciever"; +static const char pci_device_14f3_2060[] = "2060 ATSC Terrestrial (Cable) Reciever"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +static const char pci_device_14f8_2077[] = "TP-240 dual span E1 VoIP PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOLTERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "Quadrics Ltd"; +static const char pci_device_14fc_0000[] = "QsNet Elan3 Network Adapter"; +static const char pci_device_14fc_0001[] = "QsNetII Elan4 Network Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +static const char pci_device_1500_1360[] = "RTL81xx RealTek Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0800[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +static const char pci_device_1516_0891[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +static const char pci_device_151c_0003[] = "Prodif T 2496"; +static const char pci_device_151c_4000[] = "Prodif 88"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0c00[] = "RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0d00[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_1d00[] = "RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2000[] = "RockForceD1 1 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2100[] = "RockForceF1 1 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2200[] = "RockForceD2 2 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2300[] = "RockForceF2 2 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2400[] = "RockForceD4 4 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2500[] = "RockForceF4 4 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2600[] = "RockForceD8 8 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2700[] = "RockForceF8 8 Port V.34 Super-G3 Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_0510[] = "CB710 Memory Card Reader Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_0510_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_0520[] = "FLASH memory: ENE Technology Inc:"; +static const char pci_device_1524_0530[] = "ENE PCI Memory Stick Card Reader Controller"; +static const char pci_device_1524_0550[] = "ENE PCI Secure Digital Card Reader Controller"; +static const char pci_device_1524_0610[] = "PCI Smart Card Reader Controller"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1411[] = "CB-710/2/4 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1411_103c_006a[] = "nx9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1412[] = "CB-712/4 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +static const char pci_device_1524_1421[] = "CB-720/2/4 Cardbus Controller"; +static const char pci_device_1524_1422[] = "CB-722/4 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +static const char pci_device_1532_0020[] = "LonWorks PCLTA-20 PCI LonTalk Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +static const char pci_device_1538_0303[] = "ARS106S Ultra ATA 133/100/66 Host Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +static const char pci_device_153b_1144[] = "Aureon 5.1"; +static const char pci_device_153b_1147[] = "Aureon 5.1 Sky"; +static const char pci_device_153b_1158[] = "Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS Technologies, Inc."; +static const char pci_device_153f_0001[] = "SOC-it 101 System Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "Concurrent Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +static const char pci_device_1578_5615[] = "VPMK3 [Video Processor Mk III]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMware Inc"; +static const char pci_device_15ad_0405[] = "[VMware SVGA II] PCI Display Adapter"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +static const char pci_device_15ad_0720[] = "VMware High-Speed Virtual NIC [vmxnet]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technologies"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +static const char pci_device_15b3_5a44[] = "MT23108 InfiniHost"; +static const char pci_device_15b3_5a45[] = "MT23108 [Infinihost HCA Flash Recovery]"; +static const char pci_device_15b3_5a46[] = "MT23108 PCI Bridge"; +static const char pci_device_15b3_5e8d[] = "MT25204 [InfiniHost III Lx HCA Flash Recovery]"; +static const char pci_device_15b3_6274[] = "MT25204 [InfiniHost III Lx HCA]"; +static const char pci_device_15b3_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_15b3_6279[] = "MT25208 [InfiniHost III Ex HCA Flash Recovery]"; +static const char pci_device_15b3_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_1100[] = "E8001-66442 PCI Express CIC"; +static const char pci_device_15bc_2922[] = "64 Bit, 133MHz PCI-X Exerciser & Protocol Checker"; +static const char pci_device_15bc_2928[] = "64 Bit, 66MHz PCI Exerciser & Analyzer"; +static const char pci_device_15bc_2929[] = "64 Bit, 133MHz PCI-X Analyzer & Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +static const char pci_device_15c5_8010[] = "1394b - 1394 Firewire 3-Port Host Adapter Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +static const char pci_device_15e9_1841[] = "ADMA-100 DiscStaQ ATA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +static const char pci_device_15ec_3101[] = "FC3101 Profibus DP 1 Channel PCI"; +static const char pci_device_15ec_5102[] = "FC5102"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_0610[] = "FarSync T1U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0620[] = "FarSync T2U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0640[] = "FarSync T4U (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_1610[] = "FarSync TE1 (T1,E1)"; +static const char pci_device_1619_2610[] = "FarSync DSL-S1 (SHDSL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_161f[] = "Rioworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1626[] = "TDK Semiconductor Corp."; +static const char pci_device_1626_8410[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1637[] = "Linksys"; +static const char pci_device_1637_3874[] = "Linksys 802.11b WMP11 PCI Wireless card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_3052[] = "SmartLink SmartPCI562 56K Modem"; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165f[] = "Linux Media Labs, LLC"; +static const char pci_device_165f_1020[] = "LMLM4 MPEG-4 encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +static const char pci_device_1668_0100[] = "Mini-PCI bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_166d[] = "Broadcom Corporation"; +static const char pci_device_166d_0001[] = "SiByte BCM1125/1125H/1250 System-on-a-Chip PCI"; +static const char pci_device_166d_0002[] = "SiByte BCM1125H/1250 System-on-a-Chip HyperTransport"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1677[] = "Bernecker + Rainer"; +static const char pci_device_1677_104e[] = "5LS172.6 B&R Dual CAN Interface Card"; +static const char pci_device_1677_12d7[] = "5LS172.61 B&R Dual CAN Interface Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167b[] = "ZyDAS Technology Corp."; +static const char pci_device_167b_2102[] = "ZyDAS ZD1202"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_167b_2102_187e_3406[] = "ZyAIR B-122 CardBus 11Mbs Wireless LAN Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +static const char pci_device_1681_0010[] = "Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1682[] = "XFX Pine Group Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1688[] = "CastleNet Technology Inc."; +static const char pci_device_1688_1170[] = "WLAN 802.11b card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_168c[] = "Atheros Communications, Inc."; +static const char pci_device_168c_0007[] = "AR5000 802.11a Wireless Adapter"; +static const char pci_device_168c_0011[] = "AR5210 802.11a NIC"; +static const char pci_device_168c_0012[] = "AR5211 802.11ab NIC"; +static const char pci_device_168c_0013[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1113_d301[] = "Philips CPWNA100 Wireless CardBus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3202[] = "D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3203[] = "DWL-G520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a12[] = "D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a13[] = "D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a14[] = "D-Link AirPremier DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a17[] = "D-Link AirPremier DWL-G680 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a18[] = "D-Link AirPremier DWL-G550 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a63[] = "D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a94[] = "C54C Wireless 801.11g cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1385_4d00[] = "Netgear WG311T Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1458_e911[] = "Gigabyte GN-WIAG02"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_14b7_0a60[] = "8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_0013[] = "AirPlus XtremeG DWL-G650 Wireless PCMCIA Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1025[] = "DWL-G650B2 Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1027[] = "Netgate NL-3054CB ARIES b/g CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2026[] = "Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2041[] = "Netgate 5354MP Plus ARIES2 b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2042[] = "Netgate 5354MP Plus ARIES2 a/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_16ab_7302[] = "Trust Speedshare Turbo Pro Wireless PCI Adapter"; +#endif +static const char pci_device_168c_001a[] = "AR5005G 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a15[] = "D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a16[] = "D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a23[] = "D-Link AirPlus G DWL-G520+A Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a24[] = "D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_1052[] = "TP-Link TL-WN510G Wireless CardBus Adapter"; +#endif +static const char pci_device_168c_001b[] = "AR5006X 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a19[] = "D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a22[] = "D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter"; +#endif +static const char pci_device_168c_0020[] = "AR5005VL 802.11bg Wireless NIC"; +static const char pci_device_168c_1014[] = "AR5212 802.11abg NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1695[] = "EPoX Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_169c[] = "Netcell Corporation"; +static const char pci_device_169c_0044[] = "Revolution Storage Processing Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16a5[] = "Tekram Technology Co.,Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1100[] = "GL24110P"; +static const char pci_device_16ab_1101[] = "PLX9052 PCMCIA-to-PCI Wireless LAN"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +static const char pci_device_16ab_8501[] = "WL-8305 Wireless LAN PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ae[] = "Safenet Inc"; +static const char pci_device_16ae_1141[] = "SafeXcel-1141"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16af[] = "SparkLAN Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b4[] = "Aspex Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b8[] = "Sonnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c8[] = "Octasic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c9[] = "EONIC B.V. The Netherlands"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ca[] = "CENATEK Inc"; +static const char pci_device_16ca_0001[] = "Rocket Drive DL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16cd[] = "Densitron Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ce[] = "Roland Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16df[] = "PIKA Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e3[] = "European Space Agency"; +static const char pci_device_16e3_1e0f[] = "LEON2FT Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_00ff[] = "USR997900 10/100 Mbps PCI Network Card"; +static const char pci_device_16ec_0116[] = "USR997902 10/100/1000 Mbps PCI Network Card"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ed[] = "Sycron N. V."; +static const char pci_device_16ed_1001[] = "UMIO communication card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f3[] = "Jetway Information Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f4[] = "Vweb Corp"; +static const char pci_device_16f4_8000[] = "VW2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1702[] = "Internet Machines Corporation (IMC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave"; +static const char pci_device_170b_0100[] = "NSP2000-SSL crypto accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1725[] = "Vitesse Semiconductor"; +static const char pci_device_1725_7174[] = "VSC7174 PCI/PCI-X Serial ATA Host Bus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +static const char pci_device_172a_13c8[] = "AEP SureWare Runner 1000V3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1734[] = "Fujitsu Siemens Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +static const char pci_device_1737_0013[] = "WMP54G Wireless Pci Card"; +static const char pci_device_1737_0015[] = "WMP54GS Wireless Pci Card"; +static const char pci_device_1737_1032[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0015[] = "EG1032 v2 Instant Gigabit Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0024[] = "EG1032 v3 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_1064[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1064_1737_0016[] = "EG1064 v2 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1737_ab09[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03e9[] = "AC1001 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +static const char pci_device_173b_03eb[] = "AC1003 Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1749[] = "RLX Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174d[] = "WellX Telecom SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175c[] = "AudioScience Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1775[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1797[] = "JumpTec h, GMBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +static const char pci_device_1799_6001[] = "Wireless PCI Card - F5D6001"; +static const char pci_device_1799_6020[] = "Wireless PCMCIA Card - F5D6020"; +static const char pci_device_1799_6060[] = "Wireless PDA Card - F5D6060"; +static const char pci_device_1799_7000[] = "Wireless PCI Card - F5D7000"; +static const char pci_device_1799_7010[] = "BCM4306 802.11b/g Wireless Lan Controller F5D7010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_179c[] = "Data Patterns"; +static const char pci_device_179c_0557[] = "DP-PCI-557 [PCI 1553B]"; +static const char pci_device_179c_0566[] = "DP-PCI-566 [Intelligent PCI 1553B]"; +static const char pci_device_179c_5031[] = "DP-CPCI-5031-Synchro Module"; +static const char pci_device_179c_5121[] = "DP-CPCI-5121-IP Carrier"; +static const char pci_device_179c_5211[] = "DP-CPCI-5211-IP Carrier"; +static const char pci_device_179c_5679[] = "AGE Display Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17a0[] = "Genesys Logic, Inc"; +static const char pci_device_17a0_8033[] = "GL880S USB 1.1 controller"; +static const char pci_device_17a0_8034[] = "GL880S USB 2.0 controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17aa[] = "Lenovo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b3[] = "Hawking Technologies"; +static const char pci_device_17b3_ab08[] = "PN672TX 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b4[] = "Indra Networks, Inc."; +static const char pci_device_17b4_0011[] = "WebEnhance 100 GZIP Compression Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c0[] = "Wistron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c2[] = "Newisys, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cb[] = "Airgo Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cf[] = "Z-Com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d3[] = "Areca Technology Corp."; +static const char pci_device_17d3_1110[] = "ARC-1110 4-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1120[] = "ARC-1120 8-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1130[] = "ARC-1130 12-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1160[] = "ARC-1160 16-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1210[] = "ARC-1210 4-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1220[] = "ARC-1220 8-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1230[] = "ARC-1230 12-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1260[] = "ARC-1260 16-Port PCI-Express to SATA RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d5[] = "S2io Inc."; +static const char pci_device_17d5_5831[] = "Xframe 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5831_103c_12d5[] = "HP PCI-X 133MHz 10GbE SR Fiber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_17d5_5832[] = "Xframe II 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17de[] = "KWorld Computer Co. Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ee[] = "Connect Components Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17f2[] = "Albatron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17fe[] = "Linksys, A Division of Cisco Systems"; +static const char pci_device_17fe_2120[] = "WMP11v4 802.11b PCI card"; +static const char pci_device_17fe_2220[] = "[AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17fe_2220_17fe_2220[] = "WPC54G ver. 4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ff[] = "Benq Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1814[] = "RaLink"; +static const char pci_device_1814_0101[] = "Wireless PCI Adapter RT2400 / RT2460"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1043_0127[] = "WiFi-b add-on Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1462_6828[] = "PC11B2 (MS-6828) Wireless 11b PCI Card"; +#endif +static const char pci_device_1814_0200[] = "RT2500 802.11g PCI [PC54G2]"; +static const char pci_device_1814_0201[] = "RT2500 802.11g Cardbus/mini-PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1043_130f[] = "WL-130g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001e[] = "CWC-854 Wireless-G CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001f[] = "CWM-854 Wireless-G Mini PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_0020[] = "CWP-854 Wireless-G PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e381[] = "GN-WMKG 802.11b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e931[] = "GN-WIKG 802.11b/g mini-PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1462_6835[] = "Wireless 11G CardBus CB54G2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1737_0032[] = "WMP54G 2.0 PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_700a[] = "F5D7000 Wireless G Desktop Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_701a[] = "F5D7010 Wireless G Notebook Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_185f_22a0[] = "CN-WF513 Wireless Cardbus Adapter"; +#endif +static const char pci_device_1814_0301[] = "RT2561/RT61 802.11g PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0301_2561_1814[] = "Intellinet Wireless G PCI Adapter"; +#endif +static const char pci_device_1814_0401[] = "Ralink RT2600 802.11 MIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1820[] = "InfiniCon Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1822[] = "Twinhan Technology Co. Ltd"; +static const char pci_device_1822_4e35[] = "Mantis DTV PCI Bridge Controller [Ver 1.0]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182d[] = "SiteCom Europe BV"; +static const char pci_device_182d_3069[] = "ISDN PCI DC-105V2"; +static const char pci_device_182d_9790[] = "WL-121 Wireless Network Adapter 100g+ [Ver.3]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1830[] = "Credence Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_183b[] = "MikroM GmbH"; +static const char pci_device_183b_08a7[] = "MVC100 DVI"; +static const char pci_device_183b_08a8[] = "MVC101 SDI"; +static const char pci_device_183b_08a9[] = "MVC102 DVI+Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1849[] = "ASRock Incorporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1854[] = "LG Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185b[] = "Compro Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185f[] = "Wistron NeWeb Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1864[] = "SilverBack"; +static const char pci_device_1864_2110[] = "ISNAP 2110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1867[] = "Topspin Communications"; +static const char pci_device_1867_5a44[] = "MT23108 InfiniHost HCA"; +static const char pci_device_1867_5a45[] = "MT23108 InfiniHost HCA flash recovery"; +static const char pci_device_1867_5a46[] = "MT23108 InfiniHost HCA bridge"; +static const char pci_device_1867_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_1867_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_187e[] = "ZyXEL Communication Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1890[] = "Egenera, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1894[] = "KNC One"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1896[] = "B&B Electronics Manufacturing Company, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18a1[] = "Astute Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ac[] = "DViCO Corporation"; +static const char pci_device_18ac_d500[] = "FusionHDTV 5"; +static const char pci_device_18ac_d810[] = "FusionHDTV 3 Gold"; +static const char pci_device_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18b8[] = "Ammasso"; +static const char pci_device_18b8_b001[] = "AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18bc[] = "Info-Tek Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c8[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c9[] = "ARVOO Engineering BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ca[] = "XGI - Xabre Graphics Inc"; +static const char pci_device_18ca_0020[] = "Volari Z7"; +static const char pci_device_18ca_0040[] = "Volari V3XT/V5/V8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18d2[] = "Sitecom"; +static const char pci_device_18d2_3069[] = "DC-105v2 ISDN controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18dd[] = "Artimi Inc"; +static const char pci_device_18dd_4c6f[] = "Artimi RTMI-100 UWB adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18e6[] = "MPL AG"; +static const char pci_device_18e6_0001[] = "OSCI [Octal Serial Communication Interface]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ec[] = "Cesnet, z.s.p.o."; +static const char pci_device_18ec_c006[] = "COMBO6"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d004[] = "COMBO-2XFP"; +#endif +static const char pci_device_18ec_c045[] = "COMBO6E"; +static const char pci_device_18ec_c050[] = "COMBO-PTM"; +static const char pci_device_18ec_c058[] = "COMBO6X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d004[] = "COMBO-2XFP"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f7[] = "Commtech, Inc."; +static const char pci_device_18f7_0001[] = "Fastcom ESCC-PCI-335"; +static const char pci_device_18f7_0002[] = "Fastcom 422/4-PCI-335"; +static const char pci_device_18f7_0004[] = "Fastcom 422/2-PCI-335"; +static const char pci_device_18f7_0005[] = "Fastcom IGESCC-PCI-ISO/1"; +static const char pci_device_18f7_000a[] = "Fastcom 232/4-PCI-335"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18fb[] = "Resilience Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1923[] = "Sangoma Technologies Corp."; +static const char pci_device_1923_0100[] = "A104d QUAD T1/E1 AFT card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1924[] = "Level 5 Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_192e[] = "TransDimension"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1931[] = "Option N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1942[] = "ClearSpeed Technology plc"; +static const char pci_device_1942_e511[] = "CSX600 Advance Accelerator Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1957[] = "Freescale Semiconductor Inc"; +static const char pci_device_1957_0080[] = "MPC8349E"; +static const char pci_device_1957_0081[] = "MPC8349"; +static const char pci_device_1957_0082[] = "MPC8347E TBGA"; +static const char pci_device_1957_0083[] = "MPC8347 TBGA"; +static const char pci_device_1957_0084[] = "MPC8347E PBGA"; +static const char pci_device_1957_0085[] = "MPC8347 PBGA"; +static const char pci_device_1957_0086[] = "MPC8343E"; +static const char pci_device_1957_0087[] = "MPC8343"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1958[] = "Faster Technology, LLC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1966[] = "Orad Hi-Tec Systems"; +static const char pci_device_1966_1975[] = "DVG64 family"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196a[] = "Sensory Networks Inc."; +static const char pci_device_196a_0101[] = "NodalCore C-1000 Content Classification Accelerator"; +static const char pci_device_196a_0102[] = "NodalCore C-2000 Content Classification Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_197b[] = "JMicron Technologies, Inc."; +static const char pci_device_197b_2360[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2363[] = "JMicron 20360/20363 AHCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1989[] = "Montilio Inc."; +static const char pci_device_1989_0001[] = "RapidFile Bridge"; +static const char pci_device_1989_8001[] = "RapidFile"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1993[] = "Innominate Security Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19a8[] = "DAQDATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ac[] = "Kasten Chase Applied Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ae[] = "Progeny Systems Corporation"; +static const char pci_device_19ae_0520[] = "4135 HFT Interface Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19d4[] = "Quixant Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19e2[] = "Vector Informatik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc0[] = "Tumsan Oy"; +static const char pci_device_1fc0_0300[] = "E2200 Dual E1/Rawpipe Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc1[] = "PathScale, Inc"; +static const char pci_device_1fc1_000d[] = "InfiniPath HT-400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fce[] = "Cognio Inc."; +static const char pci_device_1fce_0001[] = "Spectrum Analyzer PC Card (SAgE)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0020[] = "HB6 Universal PCI-PCI bridge (transparent mode)"; +static const char pci_device_3388_0021[] = "HB6 Universal PCI-PCI bridge (non-transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1090[] = "Cx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3010[] = "PPCI mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3011[] = "PPCI mezzanine (64-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_4000[] = "PMCCARR1 carrier board"; +#endif +static const char pci_device_3388_0022[] = "HiNT HB4 PCI-PCI Bridge (PCI6150)"; +static const char pci_device_3388_0026[] = "HB2 PCI-PCI Bridge"; +static const char pci_device_3388_101a[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_101b[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3842[] = "eVga.com. Corp."; +static const char pci_device_3842_c370[] = "e-GeFORCE 6600 256 DDR PCI-e"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0002_0000_0000[] = "GLoria L"; +#endif +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0003_0000_0000[] = "GLoria XL"; +#endif +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_0000_0000[] = "GLoria XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0008_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1048_0a42[] = "GLoria XXL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_000d[] = "GLint R4 rev A"; +static const char pci_device_3d3d_0011[] = "GLint R4 rev B"; +static const char pci_device_3d3d_0012[] = "GLint R5 rev A"; +static const char pci_device_3d3d_0013[] = "GLint R5 rev B"; +static const char pci_device_3d3d_0020[] = "VP10 visual processor"; +static const char pci_device_3d3d_0022[] = "VP10 visual processor"; +static const char pci_device_3d3d_0024[] = "VP9 visual processor"; +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_07a1[] = "Wildcat III 6210"; +static const char pci_device_3d3d_07a2[] = "Sun XVR-500 Graphics Accelerator"; +static const char pci_device_3d3d_07a3[] = "Wildcat IV 7210"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4144[] = "Alpha Data"; +static const char pci_device_4144_0044[] = "ADM-XRCIIPro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4321[] = "Tata Power Strategic Electronics Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0016[] = "iTVC16 (CX23416) MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0003[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0009[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0807[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4001[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4009[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4801[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4803[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8003[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_c801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e807[] = "WinTV PVR 500 (1st unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e817[] = "WinTV PVR 500 (2nd unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0270_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_fff3[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_ffff[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_4070_8801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0092[] = "VideOh! AVC-2010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0093[] = "VideOh! AVC-2410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_ff92_0070[] = "PVR-550"; +#endif +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4000[] = "WinTV PVR-350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4001[] = "WinTV PVR-250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4800[] = "WinTV PVR-350 (V1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_12ab_0000[] = "MPG160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3ce[] = "M179"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3cf[] = "M179"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_494f[] = "ACCES I/O Products, Inc."; +static const char pci_device_494f_10e8[] = "LPCI-COM-8SM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +static const char pci_device_4c53_0000[] = "PLUSTEST device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3000[] = "PLUSTEST card (PC104+)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3001[] = "PLUSTEST card (PMC)"; +#endif +static const char pci_device_4c53_0001[] = "PLUSTEST-MM device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0001_4c53_3002[] = "PLUSTEST-MM card (PMC)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +static const char pci_device_5168_0301[] = "FlyDVB-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8110[] = "Savage 4 LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "Thinkpad T20/T22"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1179_0001[] = "86C584 SuperSavage/IXC Toshiba"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "VT8375 [ProSavage8 KM266/KL266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +static const char pci_device_544c_0350[] = "TL880-based HDTV/ATSC tuner"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +static const char pci_device_5654_3132[] = "OpenSwitch12"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5851[] = "Exacq Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin fuer Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +static const char pci_device_6666_0004[] = "PCCOM2"; +static const char pci_device_6666_0101[] = "PCI 8255/8254 I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7063[] = "pcHDTV"; +static const char pci_device_7063_2000[] = "HD-2000"; +static const char pci_device_7063_3000[] = "HD-3000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_807d[] = "Asustek Computer, Inc."; +#endif +static const char pci_vendor_8086[] = "Intel Corporation"; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145 Fast Ethernet"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0309[] = "80303 I/O Processor PCI-to-PCI Bridge"; +static const char pci_device_8086_030d[] = "80312 I/O Companion Chip PCI-to-PCI Bridge"; +static const char pci_device_8086_0326[] = "6700/6702PXH I/OxAPIC Interrupt Controller A"; +static const char pci_device_8086_0327[] = "6700PXH I/OxAPIC Interrupt Controller B"; +static const char pci_device_8086_0329[] = "6700PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_032a[] = "6700PXH PCI Express-to-PCI Bridge B"; +static const char pci_device_8086_032c[] = "6702PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_0330[] = "80332 [Dobson] I/O processor (A-Segment Bridge)"; +static const char pci_device_8086_0331[] = "80332 [Dobson] I/O processor (A-Segment IOAPIC)"; +static const char pci_device_8086_0332[] = "80332 [Dobson] I/O processor (B-Segment Bridge)"; +static const char pci_device_8086_0333[] = "80332 [Dobson] I/O processor (B-Segment IOAPIC)"; +static const char pci_device_8086_0334[] = "80332 [Dobson] I/O processor (ATU)"; +static const char pci_device_8086_0335[] = "80331 [Lindsay] I/O processor (PCI-X Bridge)"; +static const char pci_device_8086_0336[] = "80331 [Lindsay] I/O processor (ATU)"; +static const char pci_device_8086_0340[] = "41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge)"; +static const char pci_device_8086_0341[] = "41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge)"; +static const char pci_device_8086_0370[] = "80333 Segment-A PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0371[] = "80333 A-Bus IOAPIC"; +static const char pci_device_8086_0372[] = "80333 Segment-B PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0373[] = "80333 B-Bus IOAPIC"; +static const char pci_device_8086_0374[] = "80333 Address Translation Unit"; +static const char pci_device_8086_0482[] = "82375EB/SB PCI to EISA Bridge"; +static const char pci_device_8086_0483[] = "82424TX/ZX [Saturn] CPU to PCI bridge"; +static const char pci_device_8086_0484[] = "82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge"; +static const char pci_device_8086_0486[] = "82425EX/ZX [Aries] PCIset with ISA bridge"; +static const char pci_device_8086_04a3[] = "82434LX/NX [Mercury/Neptune] Processor to PCI bridge"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0500[] = "E8870 Processor bus control"; +static const char pci_device_8086_0501[] = "E8870 Memory controller"; +static const char pci_device_8086_0502[] = "E8870 Scalability Port 0"; +static const char pci_device_8086_0503[] = "E8870 Scalability Port 1"; +static const char pci_device_8086_0510[] = "E8870IO Hub Interface Port 0 registers (8-bit compatibility port)"; +static const char pci_device_8086_0511[] = "E8870IO Hub Interface Port 1 registers"; +static const char pci_device_8086_0512[] = "E8870IO Hub Interface Port 2 registers"; +static const char pci_device_8086_0513[] = "E8870IO Hub Interface Port 3 registers"; +static const char pci_device_8086_0514[] = "E8870IO Hub Interface Port 4 registers"; +static const char pci_device_8086_0515[] = "E8870IO General SIOH registers"; +static const char pci_device_8086_0516[] = "E8870IO RAS registers"; +static const char pci_device_8086_0530[] = "E8870SP Scalability Port 0 registers"; +static const char pci_device_8086_0531[] = "E8870SP Scalability Port 1 registers"; +static const char pci_device_8086_0532[] = "E8870SP Scalability Port 2 registers"; +static const char pci_device_8086_0533[] = "E8870SP Scalability Port 3 registers"; +static const char pci_device_8086_0534[] = "E8870SP Scalability Port 4 registers"; +static const char pci_device_8086_0535[] = "E8870SP Scalability Port 5 registers"; +static const char pci_device_8086_0536[] = "E8870SP Interleave registers 0 and 1"; +static const char pci_device_8086_0537[] = "E8870SP Interleave registers 2 and 3"; +static const char pci_device_8086_0600[] = "RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01af[] = "SRCZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01c1[] = "ICP Vortex GDT8546RZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01f7[] = "SCRU32"; +#endif +static const char pci_device_8086_061f[] = "80303 I/O Processor"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1002[] = "PRO/1000 F Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1028_011c[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_3108[] = "PRO/1000 XT Network Connection"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100a[] = "82540EM Gigabit Ethernet Controller"; +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1028_0123[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1079_891f[] = "82544GC Based Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_8086_110d[] = "82544GC Based Network Connection"; +#endif +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0265[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0267[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_026a[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1024_0134[] = "Poweredge SC600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_002e[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0151[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_107b_8920[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_028e[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1000[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_0e11_00db[] = "NC7170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1014_027c[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_18fb_7872[] = "RESlink-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1fc1_0026[] = "Niagara 2260 Bypass Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1012[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_101a[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1003[] = "PRO/1000 MF Server Adapter (LX)"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_0e11_00dc[] = "NC6170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1013[] = "82541EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_0013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1013[] = "IBM ThinkCentre Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1113[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1014[] = "82541ER Gigabit Ethernet Controller"; +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +static const char pci_device_8086_1016[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1014_052c[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_8086_1016[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1017[] = "82540EP Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1017_8086_1017[] = "PR0/1000 MT Desktop Connection"; +#endif +static const char pci_device_8086_1018[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1018_8086_1018[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1019[] = "82547EI Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_1019[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_e000[] = "Intel Gigabit Ethernet (Kenai II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_1019[] = "PRO/1000 CT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_301f[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_101a[] = "82547EI Gigabit Ethernet Controller (Mobile)"; +static const char pci_device_8086_101d[] = "82546EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101d_8086_1000[] = "PRO/1000 MT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_101e[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1014_0549[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_8086_101e[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1026[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1000[] = "PRO/1000 MT Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1002[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1026[] = "PRO/1000 MT Server Connection"; +#endif +static const char pci_device_8086_1027[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_103c_3103[] = "NC310F PCI-X Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1001[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1002[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1003[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1027[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1028[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1028_8086_1028[] = "PRO/1000 MB Server Adapter"; +#endif +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_813c_104d[] = "Vaio PCG-GRV616G"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1038_0e11_0098[] = "Evo N600c"; +#endif +static const char pci_device_8086_1039[] = "82801DB PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1039_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_103a[] = "82801DB PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801DB PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801DB PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801DB PRO/100 VE (MOB) Ethernet Controller"; +static const char pci_device_8086_103e[] = "82801DB PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1043[] = "PRO/Wireless LAN 2100 3B Mini PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_8086_2527[] = "MIM2000/Centrino"; +#endif +static const char pci_device_8086_1048[] = "PRO/10GbE LR Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a01f[] = "PRO/10GbE LR Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a11f[] = "PRO/10GbE LR Server Adapter"; +#endif +static const char pci_device_8086_104b[] = "Ethernet Controller"; +static const char pci_device_8086_1050[] = "82562EZ 10/100 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_728c[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_758c[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3020[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_302f[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_1051[] = "82801EB/ER (ICH5/ICH5R) integrated LAN Controller"; +static const char pci_device_8086_1052[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1053[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_105e[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_105f[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1060[] = "82571EB Gigabit Ethernet Controller"; +static const char pci_device_8086_1064[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1064_1043_80f8[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_1065[] = "82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1066[] = "82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1067[] = "82562 EM/EX/GX - PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1068[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_1069[] = "82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_106a[] = "82562G - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_106b[] = "82562G - PRO/100 VE Ethernet Controller Mobile"; +static const char pci_device_8086_1075[] = "82547GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_0075[] = "PRO/1000 CT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_1075[] = "PRO/1000 CT Network Connection"; +#endif +static const char pci_device_8086_1076[] = "82541GI/PI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_0076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1176[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1276[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1077[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_0077[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_1077[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1078[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1078_8086_1078[] = "PRO/1000 MT Network Connection"; +#endif +static const char pci_device_8086_1079[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12a6[] = "HP Dual Port 1000Base-T [A9900A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12cf[] = "HP Core Dual Port 1000Base-T [AB352A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1fc1_0027[] = "Niagara 2261 Failover NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_0079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1179[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_117a[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_103c_12a8[] = "HP Dual Port 1000base-SX [A9899A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_107a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_127a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107b[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_007b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_107b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +static const char pci_device_8086_107c[] = "82541PI Gigabit Ethernet Controller"; +static const char pci_device_8086_107d[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107e[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_107f[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_1080[] = "FA82537EP 56K V.92 Data/Fax Modem PCI"; +static const char pci_device_8086_1081[] = "Enterprise Southbridge LAN Copper"; +static const char pci_device_8086_1082[] = "Enterprise Southbridge LAN fiber"; +static const char pci_device_8086_1083[] = "Enterprise Southbridge LAN SERDES"; +static const char pci_device_8086_1084[] = "Enterprise Southbridge IDE Redirection"; +static const char pci_device_8086_1085[] = "Enterprise Southbridge Serial Port Redirection"; +static const char pci_device_8086_1086[] = "Enterprise Southbridge IPMI/KCS0"; +static const char pci_device_8086_1087[] = "Enterprise Southbridge UHCI Redirection"; +static const char pci_device_8086_1089[] = "Enterprise Southbridge BT"; +static const char pci_device_8086_108a[] = "82546EB Gigabit Ethernet Controller"; +static const char pci_device_8086_108b[] = "82573V Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108c[] = "82573E Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_1096[] = "Enterprise Southbridge DPT LAN Copper"; +static const char pci_device_8086_1097[] = "Enterprise Southbridge DPT LAN fiber"; +static const char pci_device_8086_1098[] = "Enterprise Southbridge DPT LAN SERDES"; +static const char pci_device_8086_1099[] = "82546GB Quad Port Server Adapter"; +static const char pci_device_8086_109a[] = "82573L Gigabit Ethernet Controller"; +static const char pci_device_8086_1107[] = "PRO/1000 MF Server Adapter (LX)"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4532[] = "D815EEA2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "Intel IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "8255xER/82551IT Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1070[] = "PC6 mainboard"; +#endif +static const char pci_device_8086_1221[] = "82092AA PCI to PCMCIA Bridge"; +static const char pci_device_8086_1222[] = "82092AA IDE Controller"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2500/2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_108e_10cf[] = "EtherExpress PRO/100(B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_110a_008b[] = "82551QM Fast Ethernet Multifuction PCI/CardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_10e0[] = "PSL09 PrPMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3411[] = "SDS2 Mainboard"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB PIIX IDE Interface"; +static const char pci_device_8086_123b[] = "82380PB PCI to PCI Docking Bridge"; +static const char pci_device_8086_123c[] = "82380AB (MISA) Mobile PCI-to-ISA Bridge"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123e[] = "82466GX (IHPC) Integrated Hot-Plug Controller"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "82752 (752) AGP Graphics Accelerator"; +static const char pci_device_8086_124b[] = "82380FB (MPCI2) Mobile Docking Controller"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_4c53_1090[] = "Cx9/Vx9 mainboard"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, HP NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated HP NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "HP NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1010[] = "CG1-RADIO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1020[] = "CU2-QUARTET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1040[] = "CU1-CHORUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_3100[] = "CX1-BAND"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1a30_1028_010e[] = "Optiplex GX240"; +#endif +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_1a38[] = "Server DMA Controller"; +static const char pci_device_8086_1a48[] = "PRO/10GbE SR Server Adapter"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_110a_0051[] = "Activy 2xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1734_1025[] = "Activy 3xx"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_8086_4532[] = "D815EEA2 mainboard"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2446[] = "82801BA/BAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801 Mobile PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0265[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0267[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_026a[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1179_ff01[] = "PRO/100 VE Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801 PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244e_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA LPC Interface Controller"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1013_5959[] = "Crystal WMD Audio Codec"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_101f_1025[] = "Acer 620 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1179_0001[] = "Toshiba Satellite 1110 Z15 internal Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_248b[] = "82801CA Ultra ATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c1[] = "82801DBL (ICH4-L) IDE Controller"; +static const char pci_device_8086_24c2[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1509_2990[] = "Averatec 5110H laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c3[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24c4[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c5[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_0e11_00b8[] = "Analog Devices Inc. codec [SoundMAX]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1458_a002[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24c6[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_8086_24c7[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24ca[] = "82801DBM (ICH4-M) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24cb[] = "82801DB (ICH4) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24cc[] = "82801DBM (ICH4-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cc_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24cd[] = "82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_011d[] = "Latitude D600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_0890[] = "nc6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1509_1968[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24d0[] = "82801EB/ER (ICH5/ICH5R) LPC Interface Bridge"; +static const char pci_device_8086_24d1[] = "82801EB (ICH5) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1043_80a6[] = "P4P800 SE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1458_24d1[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d2[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1458_24d2[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d3[] = "82801EB/ER (ICH5/ICH5R) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1043_80a6[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d4[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d5[] = "82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_12bc[] = "Analog Devices codec [SoundMAX Integrated Digital Audio]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_80f3[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_810f[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1458_a002[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_0080[] = "65PE Neo2-V (MS-6788) mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_a000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e001[] = "Desktop Board D865GBF"; +#endif +static const char pci_device_8086_24d6[] = "82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d6_103c_006a[] = "nx9500"; +#endif +static const char pci_device_8086_24d7[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24db[] = "82801EB/ER (ICH5/ICH5R) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7580[] = "MSI 875P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_24db[] = "P4C800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24dc[] = "82801EB (ICH5) LPC Interface Bridge"; +static const char pci_device_8086_24dd[] = "82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1458_5006[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24de[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24df[] = "82801ER (ICH5R) SATA Controller"; +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "E7500 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "E7500/E7501 Host RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2543[] = "E7500/E7501 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2544[] = "E7500/E7501 Hub Interface B RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2544_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_2545[] = "E7500/E7501 Hub Interface C PCI-to-PCI Bridge"; +static const char pci_device_8086_2546[] = "E7500/E7501 Hub Interface C RASUM Controller"; +static const char pci_device_8086_2547[] = "E7500/E7501 Hub Interface D PCI-to-PCI Bridge"; +static const char pci_device_8086_2548[] = "E7500/E7501 Hub Interface D RASUM Controller"; +static const char pci_device_8086_254c[] = "E7501 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2550[] = "E7505 Memory Controller Hub"; +static const char pci_device_8086_2551[] = "E7505/E7205 Series RAS Controller"; +static const char pci_device_8086_2552[] = "E7505/E7205 PCI-to-AGP Bridge"; +static const char pci_device_8086_2553[] = "E7505 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2554[] = "E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller"; +static const char pci_device_8086_255d[] = "E7205 Memory Controller Hub"; +static const char pci_device_8086_2560[] = "82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1458_2560[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2570[] = "82865G/PE/P DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_103c_006a[] = "nx9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1043_80f2[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1458_2570[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +static const char pci_device_8086_2571[] = "82865G/PE/P PCI to AGP Controller"; +static const char pci_device_8086_2572[] = "82865G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1028_019d[] = "Dimension 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1043_80a5[] = "P5P800-MX Mainboard"; +#endif +static const char pci_device_8086_2573[] = "82865G/PE/P PCI to CSA Bridge"; +static const char pci_device_8086_2576[] = "82865G/PE/P Processor to I/O Memory Interface"; +static const char pci_device_8086_2578[] = "82875P/E7210 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1458_2578[] = "GA-8KNXP motherboard (875P)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1462_7580[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_15d9_4580[] = "P4SCE Motherboard"; +#endif +static const char pci_device_8086_2579[] = "82875P Processor to AGP Controller"; +static const char pci_device_8086_257b[] = "82875P/E7210 Processor to PCI to CSA Bridge"; +static const char pci_device_8086_257e[] = "82875P/E7210 Processor to I/O Memory Interface"; +static const char pci_device_8086_2580[] = "915G/P/GV/GL/PL/910GL Express Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1458_2580[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2581[] = "915G/P/GV/GL/PL/910GL Express PCI Express Root Port"; +static const char pci_device_8086_2582[] = "82915G/GV/910GL Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1028_1079[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1458_2582[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2584[] = "925X/XE Express Memory Controller Hub"; +static const char pci_device_8086_2585[] = "925X/XE Express PCI Express Root Port"; +static const char pci_device_8086_2588[] = "E7220/E7221 Memory Controller Hub"; +static const char pci_device_8086_2589[] = "E7220/E7221 PCI Express Root Port"; +static const char pci_device_8086_258a[] = "E7221 Integrated Graphics Controller"; +static const char pci_device_8086_2590[] = "Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_a304_81b7[] = "Vaio VGN-S3XP"; +#endif +static const char pci_device_8086_2591[] = "Mobile 915GM/PM Express PCI Express Root Port"; +static const char pci_device_8086_2592[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_25a1[] = "6300ESB LPC Interface Controller"; +static const char pci_device_8086_25a2[] = "6300ESB PATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a3[] = "6300ESB SATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a4[] = "6300ESB SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a6[] = "6300ESB AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_4c53_10b0[] = "CL9 mainboard"; +#endif +static const char pci_device_8086_25a7[] = "6300ESB AC'97 Modem Controller"; +static const char pci_device_8086_25a9[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25aa[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ab[] = "6300ESB Watchdog Timer"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ac[] = "6300ESB I/O Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ad[] = "6300ESB USB2 Enhanced Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ae[] = "6300ESB 64-bit PCI-X Bridge"; +static const char pci_device_8086_25b0[] = "6300ESB SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25c0[] = "Workstation Memory Controller Hub"; +static const char pci_device_8086_25d0[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25d4[] = "Server Memory Contoller Hub"; +static const char pci_device_8086_25d8[] = "Server Memory Controller Hub"; +static const char pci_device_8086_25e2[] = "Server PCI Express x4 Port 2"; +static const char pci_device_8086_25e3[] = "Server PCI Express x4 Port 3"; +static const char pci_device_8086_25e4[] = "Server PCI Express x4 Port 4"; +static const char pci_device_8086_25e5[] = "Server PCI Express x4 Port 5"; +static const char pci_device_8086_25e6[] = "Server PCI Express x4 Port 6"; +static const char pci_device_8086_25e7[] = "Server PCI Express x4 Port 7"; +static const char pci_device_8086_25e8[] = "Server AMB Memory Mapped Registers"; +static const char pci_device_8086_25f0[] = "Server Error Reporting Registers"; +static const char pci_device_8086_25f1[] = "Reserved Registers"; +static const char pci_device_8086_25f3[] = "Reserved Registers"; +static const char pci_device_8086_25f5[] = "Server FBD Registers"; +static const char pci_device_8086_25f6[] = "Server FBD Registers"; +static const char pci_device_8086_25f7[] = "Server PCI Express x8 Port 2-3"; +static const char pci_device_8086_25f8[] = "Server PCI Express x8 Port 4-5"; +static const char pci_device_8086_25f9[] = "Server PCI Express x8 Port 6-7"; +static const char pci_device_8086_25fa[] = "Server PCI Express x16 Port 4-7"; +static const char pci_device_8086_2600[] = "E8500/E8501 Hub Interface 1.5"; +static const char pci_device_8086_2601[] = "E8500/E8501 PCI Express x4 Port D"; +static const char pci_device_8086_2602[] = "E8500/E8501 PCI Express x4 Port C0"; +static const char pci_device_8086_2603[] = "E8500/E8501 PCI Express x4 Port C1"; +static const char pci_device_8086_2604[] = "E8500/E8501 PCI Express x4 Port B0"; +static const char pci_device_8086_2605[] = "E8500/E8501 PCI Express x4 Port B1"; +static const char pci_device_8086_2606[] = "E8500/E8501 PCI Express x4 Port A0"; +static const char pci_device_8086_2607[] = "E8500/E8501 PCI Express x4 Port A1"; +static const char pci_device_8086_2608[] = "E8500/E8501 PCI Express x8 Port C"; +static const char pci_device_8086_2609[] = "E8500/E8501 PCI Express x8 Port B"; +static const char pci_device_8086_260a[] = "E8500/E8501 PCI Express x8 Port A"; +static const char pci_device_8086_260c[] = "E8500/E8501 IMI Registers"; +static const char pci_device_8086_2610[] = "E8500/E8501 Front Side Bus, Boot, and Interrupt Registers"; +static const char pci_device_8086_2611[] = "E8500/E8501 Address Mapping Registers"; +static const char pci_device_8086_2612[] = "E8500/E8501 RAS Registers"; +static const char pci_device_8086_2613[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2614[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2615[] = "E8500/E8501 Miscellaneous Registers"; +static const char pci_device_8086_2617[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2618[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2619[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261a[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261b[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261c[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261d[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261e[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2620[] = "E8500/E8501 eXternal Memory Bridge"; +static const char pci_device_8086_2621[] = "E8500/E8501 XMB Miscellaneous Registers"; +static const char pci_device_8086_2622[] = "E8500/E8501 XMB Memory Interleaving Registers"; +static const char pci_device_8086_2623[] = "E8500/E8501 XMB DDR Initialization and Calibration"; +static const char pci_device_8086_2624[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2625[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2626[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2627[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2640[] = "82801FB/FR (ICH6/ICH6R) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2641[] = "82801FBM (ICH6M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2641_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2642[] = "82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge"; +static const char pci_device_8086_2651[] = "82801FB/FW (ICH6/ICH6W) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1043_2601[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_8086_4147[] = "D915GAG Motherboard"; +#endif +static const char pci_device_8086_2652[] = "82801FR/FRW (ICH6R/ICH6RW) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2652_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_8086_2653[] = "82801FBM (ICH6M) SATA Controller"; +static const char pci_device_8086_2658[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1458_2558[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2659[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1458_2659[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265b[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1458_5006[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2660[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2660_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_2662[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2"; +static const char pci_device_8086_2664[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3"; +static const char pci_device_8086_2666[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4"; +static const char pci_device_8086_2668[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2668_1043_814e[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_266a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1458_266a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_266c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller"; +static const char pci_device_8086_266d[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_1025_006a[] = "Conexant AC'97 CoDec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_103c_099c[] = "nx6110/nc6120"; +#endif +static const char pci_device_8086_266e[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1025_006a[] = "Realtek ALC 655 codec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0182[] = "Latitude D610 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1458_a002[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1734_105a[] = "Scenic W620"; +#endif +static const char pci_device_8086_266f[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1458_266f[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2670[] = "Enterprise Southbridge LPC"; +static const char pci_device_8086_2680[] = "Enterprise Southbridge SATA IDE"; +static const char pci_device_8086_2681[] = "Enterprise Southbridge SATA AHCI"; +static const char pci_device_8086_2682[] = "Enterprise Southbridge SATA RAID"; +static const char pci_device_8086_2683[] = "Enterprise Southbridge SATA RAID"; +static const char pci_device_8086_2688[] = "Enterprise Southbridge UHCI USB #1"; +static const char pci_device_8086_2689[] = "Enterprise Southbridge UHCI USB #2"; +static const char pci_device_8086_268a[] = "Enterprise Southbridge UHCI USB #3"; +static const char pci_device_8086_268b[] = "Enterprise Southbridge UHCI USB #4"; +static const char pci_device_8086_268c[] = "Enterprise Southbridge EHCI USB"; +static const char pci_device_8086_2690[] = "Enterprise Southbridge PCI Express Root Port 1"; +static const char pci_device_8086_2692[] = "Enterprise Southbridge PCI Express Root Port 2"; +static const char pci_device_8086_2694[] = "Enterprise Southbridge PCI Express Root Port 3"; +static const char pci_device_8086_2696[] = "Enterprise Southbridge PCI Express Root Port 4"; +static const char pci_device_8086_2698[] = "Enterprise Southbridge AC '97 Audio"; +static const char pci_device_8086_2699[] = "Enterprise Southbridge AC '97 Modem"; +static const char pci_device_8086_269a[] = "Enterprise Southbridge High Definition Audio"; +static const char pci_device_8086_269b[] = "Enterprise Southbridge SMBus"; +static const char pci_device_8086_269e[] = "Enterprise Southbridge PATA"; +static const char pci_device_8086_2770[] = "945G/GZ/P/PL Express Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2771[] = "945G/GZ/P/PL Express PCI Express Root Port"; +static const char pci_device_8086_2772[] = "945G/GZ Express Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2772_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2774[] = "955X Express Memory Controller Hub"; +static const char pci_device_8086_2775[] = "955X Express PCI Express Root Port"; +static const char pci_device_8086_2776[] = "945G/GZ Express Integrated Graphics Controller"; +static const char pci_device_8086_2778[] = "E7230 Memory Controller Hub"; +static const char pci_device_8086_2779[] = "E7230 PCI Express Root Port"; +static const char pci_device_8086_277a[] = "975X Express PCI Express Root Port"; +static const char pci_device_8086_277c[] = "975X Express Memory Controller Hub"; +static const char pci_device_8086_277d[] = "975X Express PCI Express Root Port"; +static const char pci_device_8086_2782[] = "82915G Express Chipset Family Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2792[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_103c_099c[] = "nx6110/nc6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_27a0[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express Memory Controller Hub"; +static const char pci_device_8086_27a1[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express PCI Express Root Port"; +static const char pci_device_8086_27a2[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +static const char pci_device_8086_27a6[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +static const char pci_device_8086_27b0[] = "82801GH (ICH7DH) LPC Interface Bridge"; +static const char pci_device_8086_27b8[] = "82801GB/GR (ICH7 Family) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27b9[] = "82801GBM (ICH7-M) LPC Interface Bridge"; +static const char pci_device_8086_27bd[] = "82801GHM (ICH7-M DH) LPC Interface Bridge"; +static const char pci_device_8086_27c0[] = "82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controller IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c1[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller AHCI"; +static const char pci_device_8086_27c3[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c4[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller IDE"; +static const char pci_device_8086_27c5[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller AHCI"; +static const char pci_device_8086_27c6[] = "82801GHM (ICH7-M DH) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c8[] = "82801G (ICH7 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c9[] = "82801G (ICH7 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27ca[] = "82801G (ICH7 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cb[] = "82801G (ICH7 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cc[] = "82801G (ICH7 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27d0[] = "82801G (ICH7 Family) PCI Express Port 1"; +static const char pci_device_8086_27d2[] = "82801G (ICH7 Family) PCI Express Port 2"; +static const char pci_device_8086_27d4[] = "82801G (ICH7 Family) PCI Express Port 3"; +static const char pci_device_8086_27d6[] = "82801G (ICH7 Family) PCI Express Port 4"; +static const char pci_device_8086_27d8[] = "82801G (ICH7 Family) High Definition Audio Controller"; +static const char pci_device_8086_27da[] = "82801G (ICH7 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dc[] = "82801G (ICH7 Family) LAN Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27dc_8086_308d[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dd[] = "82801G (ICH7 Family) AC'97 Modem Controller"; +static const char pci_device_8086_27de[] = "82801G (ICH7 Family) AC'97 Audio Controller"; +static const char pci_device_8086_27df[] = "82801G (ICH7 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27e0[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 5"; +static const char pci_device_8086_27e2[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 6"; +static const char pci_device_8086_2810[] = "LPC Interface Controller"; +static const char pci_device_8086_2811[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2812[] = "LPC Interface Controller"; +static const char pci_device_8086_2814[] = "LPC Interface Controller"; +static const char pci_device_8086_2815[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2820[] = "SATA Controller 1 IDE"; +static const char pci_device_8086_2821[] = "SATA Controller AHCI"; +static const char pci_device_8086_2822[] = "SATA Controller RAID"; +static const char pci_device_8086_2824[] = "SATA Controller AHCI"; +static const char pci_device_8086_2825[] = "SATA Controller 2 IDE"; +static const char pci_device_8086_2828[] = "Mobile SATA Controller IDE"; +static const char pci_device_8086_2829[] = "Mobile SATA Controller AHCI"; +static const char pci_device_8086_282a[] = "Mobile SATA Controller RAID"; +static const char pci_device_8086_2830[] = "USB UHCI Controller #1"; +static const char pci_device_8086_2831[] = "USB UHCI Controller #2"; +static const char pci_device_8086_2832[] = "USB UHCI Controller #3"; +static const char pci_device_8086_2834[] = "USB UHCI Controller #4"; +static const char pci_device_8086_2835[] = "USB UHCI Controller #5"; +static const char pci_device_8086_2836[] = "USB2 EHCI Controller #1"; +static const char pci_device_8086_283a[] = "USB2 EHCI Controller #2"; +static const char pci_device_8086_283e[] = "SMBus Controller"; +static const char pci_device_8086_283f[] = "PCI Express Port 1"; +static const char pci_device_8086_2841[] = "PCI Express Port 2"; +static const char pci_device_8086_2843[] = "PCI Express Port 3"; +static const char pci_device_8086_2844[] = "PCI Express Port 4"; +static const char pci_device_8086_2847[] = "PCI Express Port 5"; +static const char pci_device_8086_2849[] = "PCI Express Port 6"; +static const char pci_device_8086_284b[] = "HD Audio Controller"; +static const char pci_device_8086_284f[] = "Thermal Subsystem"; +static const char pci_device_8086_2850[] = "Mobile IDE Controller"; +static const char pci_device_8086_2970[] = "Memory Controller Hub"; +static const char pci_device_8086_2971[] = "PCI Express Root Port"; +static const char pci_device_8086_2972[] = "Integrated Graphics Controller"; +static const char pci_device_8086_2973[] = "Integrated Graphics Controller"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3200[] = "GD31244 PCI-X SATA HBA"; +static const char pci_device_8086_3340[] = "82855PM Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_088c[] = "nc8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_0890[] = "nc6000 laptop"; +#endif +static const char pci_device_8086_3341[] = "82855PM Processor to AGP Controller"; +static const char pci_device_8086_3500[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3501[] = "Enterprise Southbridge PCI Express Upstream Port"; +static const char pci_device_8086_3504[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_3505[] = "Enterprise Southbridge IOxAPIC"; +static const char pci_device_8086_350c[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_350d[] = "Enterprise Southbridge PCI Express to PCI-X Bridge"; +static const char pci_device_8086_3510[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3511[] = "Enterprise Southbridge PCI Express Downstream Port E1"; +static const char pci_device_8086_3514[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3515[] = "Enterprise Southbridge PCI Express Downstream Port E2"; +static const char pci_device_8086_3518[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3519[] = "Enterprise Southbridge PCI Express Downstream Port E3"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3581[] = "82852/82855 GM/GME/PM/GMV Processor to AGP Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3581_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_3582[] = "82852/855GM Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3584[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3585[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3590[] = "E7520 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1734_103e[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3591[] = "E7525/E7520 Error Reporting Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3592[] = "E7320 Memory Controller Hub"; +static const char pci_device_8086_3593[] = "E7320 Error Reporting Registers"; +static const char pci_device_8086_3594[] = "E7520 DMA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3594_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3595[] = "E7525/E7520/E7320 PCI Express Port A"; +static const char pci_device_8086_3596[] = "E7525/E7520/E7320 PCI Express Port A1"; +static const char pci_device_8086_3597[] = "E7525/E7520 PCI Express Port B"; +static const char pci_device_8086_3598[] = "E7520 PCI Express Port B1"; +static const char pci_device_8086_3599[] = "E7520 PCI Express Port C"; +static const char pci_device_8086_359a[] = "E7520 PCI Express Port C1"; +static const char pci_device_8086_359b[] = "E7525/E7520/E7320 Extended Configuration Registers"; +static const char pci_device_8086_359e[] = "E7525 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_359e_1028_0169[] = "Precision 470"; +#endif +static const char pci_device_8086_4220[] = "PRO/Wireless 2200BG"; +static const char pci_device_8086_4223[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_4224[] = "PRO/Wireless 2915ABG MiniPCI Adapter"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7050[] = "Intercast Video Capture Card"; +static const char pci_device_8086_7051[] = "PB 642365-003 (Business Video Conferencing Card)"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7110_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7111_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7112_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7113_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1060[] = "PC7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_8086_4341[] = "Cayman (CA810) Mainboard"; +#endif +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700/E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_15ad_1976[] = "virtualHW v3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_1033_0000[] = "Versa Note Vxi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_1033_80cc[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a2_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "82740 (i740) AGP Graphics Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_8500[] = "IXP4XX Intel Network Processor (IXP420/421/422/425/IXC1100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0ded[] = "mGuard-PCI AV#2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0dee[] = "mGuard-PCI AV#1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0def[] = "mGuard-PCI AV#0"; +#endif +static const char pci_device_8086_9000[] = "IXP2000 Family Network Processor"; +static const char pci_device_8086_9001[] = "IXP2400 Network Processor"; +static const char pci_device_8086_9004[] = "IXP2800 Network Processor"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12d9_000a[] = "PCI VoIP Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8401[] = "TRENDware International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8912[] = "TRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8c4a[] = "Winbond"; +static const char pci_device_8c4a_1980[] = "W89C940 misprogrammed [ne2k]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_0078[] = "AHA-2940U_CN"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7710[] = "ANA-7711F Network Accelerator Card (NAC) - Optical"; +static const char pci_device_9004_7711[] = "ANA-7711C Network Accelerator Card (NAC) - Copper"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409a = + {0x0e11, 0x409a, pci_subsys_0e11_0046_0e11_409a, 0}; +#undef pci_ss_info_0e11_409a +#define pci_ss_info_0e11_409a pci_ss_info_0e11_0046_0e11_409a +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409b = + {0x0e11, 0x409b, pci_subsys_0e11_0046_0e11_409b, 0}; +#undef pci_ss_info_0e11_409b +#define pci_ss_info_0e11_409b pci_ss_info_0e11_0046_0e11_409b +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409c = + {0x0e11, 0x409c, pci_subsys_0e11_0046_0e11_409c, 0}; +#undef pci_ss_info_0e11_409c +#define pci_ss_info_0e11_409c pci_ss_info_0e11_0046_0e11_409c +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409d = + {0x0e11, 0x409d, pci_subsys_0e11_0046_0e11_409d, 0}; +#undef pci_ss_info_0e11_409d +#define pci_ss_info_0e11_409d pci_ss_info_0e11_0046_0e11_409d +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4080 = + {0x0e11, 0x4080, pci_subsys_0e11_b178_0e11_4080, 0}; +#undef pci_ss_info_0e11_4080 +#define pci_ss_info_0e11_4080 pci_ss_info_0e11_b178_0e11_4080 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4082 = + {0x0e11, 0x4082, pci_subsys_0e11_b178_0e11_4082, 0}; +#undef pci_ss_info_0e11_4082 +#define pci_ss_info_0e11_4082 pci_ss_info_0e11_b178_0e11_4082 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4083 = + {0x0e11, 0x4083, pci_subsys_0e11_b178_0e11_4083, 0}; +#undef pci_ss_info_0e11_4083 +#define pci_ss_info_0e11_4083 pci_ss_info_0e11_b178_0e11_4083 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0003_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0003_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0003_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0006_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0006_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0006_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000a_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000a_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000a_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000b_0e11_6004 = + {0x0e11, 0x6004, pci_subsys_1000_000b_0e11_6004, 0}; +#undef pci_ss_info_0e11_6004 +#define pci_ss_info_0e11_6004 pci_ss_info_1000_000b_0e11_6004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000b_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000b_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000b_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000b_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000b_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000b_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000b_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_1000_000b_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_1000_000b_13e9_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000c_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000c_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000c_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000c_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3906 = + {0x1de1, 0x3906, pci_subsys_1000_000c_1de1_3906, 0}; +#undef pci_ss_info_1de1_3906 +#define pci_ss_info_1de1_3906 pci_ss_info_1000_000c_1de1_3906 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000f_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000f_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000f_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000f_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000f_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000f_1000_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1000_000f_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1000_000f_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1000_000f_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1000_000f_4c53_1050 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0010_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0010_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0010_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0012_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0012_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0012_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0013_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0013_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0013_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0020_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0020_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0021_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0021_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0021_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0021_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0021_124b_1070 = + {0x124b, 0x1070, pci_subsys_1000_0021_124b_1070, 0}; +#undef pci_ss_info_124b_1070 +#define pci_ss_info_124b_1070 pci_ss_info_1000_0021_124b_1070 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1000_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1000_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1300 = + {0x4c53, 0x1300, pci_subsys_1000_0021_4c53_1300, 0}; +#undef pci_ss_info_4c53_1300 +#define pci_ss_info_4c53_1300 pci_ss_info_1000_0021_4c53_1300 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1310 = + {0x4c53, 0x1310, pci_subsys_1000_0021_4c53_1310, 0}; +#undef pci_ss_info_4c53_1310 +#define pci_ss_info_4c53_1310 pci_ss_info_1000_0021_4c53_1310 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_0e11_00da = + {0x0e11, 0x00da, pci_subsys_1000_0030_0e11_00da, 0}; +#undef pci_ss_info_0e11_00da +#define pci_ss_info_0e11_00da pci_ss_info_1000_0030_0e11_00da +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0123 = + {0x1028, 0x0123, pci_subsys_1000_0030_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_1000_0030_1028_0123 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_014a = + {0x1028, 0x014a, pci_subsys_1000_0030_1028_014a, 0}; +#undef pci_ss_info_1028_014a +#define pci_ss_info_1028_014a pci_ss_info_1000_0030_1028_014a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_016c = + {0x1028, 0x016c, pci_subsys_1000_0030_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1000_0030_1028_016c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0183 = + {0x1028, 0x0183, pci_subsys_1000_0030_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_1000_0030_1028_0183 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0030_124b_1170 = + {0x124b, 0x1170, pci_subsys_1000_0030_124b_1170, 0}; +#undef pci_ss_info_124b_1170 +#define pci_ss_info_124b_1170 pci_ss_info_1000_0030_124b_1170 +static const pciSubsystemInfo pci_ss_info_1000_0030_1734_1052 = + {0x1734, 0x1052, pci_subsys_1000_0030_1734_1052, 0}; +#undef pci_ss_info_1734_1052 +#define pci_ss_info_1734_1052 pci_ss_info_1000_0030_1734_1052 +static const pciSubsystemInfo pci_ss_info_1000_0032_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0032_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0032_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0033 = + {0x1000, 0x0033, pci_subsys_1000_0040_1000_0033, 0}; +#undef pci_ss_info_1000_0033 +#define pci_ss_info_1000_0033 pci_ss_info_1000_0040_1000_0033 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0066 = + {0x1000, 0x0066, pci_subsys_1000_0040_1000_0066, 0}; +#undef pci_ss_info_1000_0066 +#define pci_ss_info_1000_0066 pci_ss_info_1000_0040_1000_0066 +static const pciSubsystemInfo pci_ss_info_1000_0062_1000_0062 = + {0x1000, 0x0062, pci_subsys_1000_0062_1000_0062, 0}; +#undef pci_ss_info_1000_0062 +#define pci_ss_info_1000_0062 pci_ss_info_1000_0062_1000_0062 +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0530 = + {0x1000, 0x0530, pci_subsys_1000_0407_1000_0530, 0}; +#undef pci_ss_info_1000_0530 +#define pci_ss_info_1000_0530 pci_ss_info_1000_0407_1000_0530 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0531 = + {0x1000, 0x0531, pci_subsys_1000_0407_1000_0531, 0}; +#undef pci_ss_info_1000_0531 +#define pci_ss_info_1000_0531 pci_ss_info_1000_0407_1000_0531 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0532 = + {0x1000, 0x0532, pci_subsys_1000_0407_1000_0532, 0}; +#undef pci_ss_info_1000_0532 +#define pci_ss_info_1000_0532 pci_ss_info_1000_0407_1000_0532 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_0407_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_0407_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_0407_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_0407_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0530 = + {0x8086, 0x0530, pci_subsys_1000_0407_8086_0530, 0}; +#undef pci_ss_info_8086_0530 +#define pci_ss_info_8086_0530 pci_ss_info_1000_0407_8086_0530 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0532 = + {0x8086, 0x0532, pci_subsys_1000_0407_8086_0532, 0}; +#undef pci_ss_info_8086_0532 +#define pci_ss_info_8086_0532 pci_ss_info_1000_0407_8086_0532 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0001 = + {0x1000, 0x0001, pci_subsys_1000_0408_1000_0001, 0}; +#undef pci_ss_info_1000_0001 +#define pci_ss_info_1000_0001 pci_ss_info_1000_0408_1000_0001 +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0002 = + {0x1000, 0x0002, pci_subsys_1000_0408_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_1000_0408_1000_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1025_004d = + {0x1025, 0x004d, pci_subsys_1000_0408_1025_004d, 0}; +#undef pci_ss_info_1025_004d +#define pci_ss_info_1025_004d pci_ss_info_1000_0408_1025_004d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0001 = + {0x1028, 0x0001, pci_subsys_1000_0408_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1000_0408_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0002 = + {0x1028, 0x0002, pci_subsys_1000_0408_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1000_0408_1028_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1734_1065 = + {0x1734, 0x1065, pci_subsys_1000_0408_1734_1065, 0}; +#undef pci_ss_info_1734_1065 +#define pci_ss_info_1734_1065 pci_ss_info_1000_0408_1734_1065 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_8086_0002 = + {0x8086, 0x0002, pci_subsys_1000_0408_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_1000_0408_8086_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3004 = + {0x1000, 0x3004, pci_subsys_1000_0409_1000_3004, 0}; +#undef pci_ss_info_1000_3004 +#define pci_ss_info_1000_3004 pci_ss_info_1000_0409_1000_3004 +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3008 = + {0x1000, 0x3008, pci_subsys_1000_0409_1000_3008, 0}; +#undef pci_ss_info_1000_3008 +#define pci_ss_info_1000_3008 pci_ss_info_1000_0409_1000_3008 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3008 = + {0x8086, 0x3008, pci_subsys_1000_0409_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_1000_0409_8086_3008 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3431 = + {0x8086, 0x3431, pci_subsys_1000_0409_8086_3431, 0}; +#undef pci_ss_info_8086_3431 +#define pci_ss_info_8086_3431 pci_ss_info_1000_0409_8086_3431 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3499 = + {0x8086, 0x3499, pci_subsys_1000_0409_8086_3499, 0}; +#undef pci_ss_info_8086_3499 +#define pci_ss_info_8086_3499 pci_ss_info_1000_0409_8086_3499 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0622_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_0622_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_0622_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_0626_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0626_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0626_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0518 = + {0x1000, 0x0518, pci_subsys_1000_1960_1000_0518, 0}; +#undef pci_ss_info_1000_0518 +#define pci_ss_info_1000_0518 pci_ss_info_1000_1960_1000_0518 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0520 = + {0x1000, 0x0520, pci_subsys_1000_1960_1000_0520, 0}; +#undef pci_ss_info_1000_0520 +#define pci_ss_info_1000_0520 pci_ss_info_1000_1960_1000_0520 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0522 = + {0x1000, 0x0522, pci_subsys_1000_1960_1000_0522, 0}; +#undef pci_ss_info_1000_0522 +#define pci_ss_info_1000_0522 pci_ss_info_1000_1960_1000_0522 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0523 = + {0x1000, 0x0523, pci_subsys_1000_1960_1000_0523, 0}; +#undef pci_ss_info_1000_0523 +#define pci_ss_info_1000_0523 pci_ss_info_1000_1960_1000_0523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_4523 = + {0x1000, 0x4523, pci_subsys_1000_1960_1000_4523, 0}; +#undef pci_ss_info_1000_4523 +#define pci_ss_info_1000_4523 pci_ss_info_1000_1960_1000_4523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_a520 = + {0x1000, 0xa520, pci_subsys_1000_1960_1000_a520, 0}; +#undef pci_ss_info_1000_a520 +#define pci_ss_info_1000_a520 pci_ss_info_1000_1960_1000_a520 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_1960_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_1960_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0520 = + {0x8086, 0x0520, pci_subsys_1000_1960_8086_0520, 0}; +#undef pci_ss_info_8086_0520 +#define pci_ss_info_8086_0520 pci_ss_info_1000_1960_8086_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0523 = + {0x8086, 0x0523, pci_subsys_1000_1960_8086_0523, 0}; +#undef pci_ss_info_8086_0523 +#define pci_ss_info_8086_0523 pci_ss_info_1000_1960_8086_0523 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4150_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4150_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4150_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4150_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_4722 = + {0x1002, 0x4722, pci_subsys_1002_4150_1002_4722, 0}; +#undef pci_ss_info_1002_4722 +#define pci_ss_info_1002_4722 pci_ss_info_1002_4150_1002_4722 +static const pciSubsystemInfo pci_ss_info_1002_4150_1458_4024 = + {0x1458, 0x4024, pci_subsys_1002_4150_1458_4024, 0}; +#undef pci_ss_info_1458_4024 +#define pci_ss_info_1458_4024 pci_ss_info_1002_4150_1458_4024 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2064 = + {0x148c, 0x2064, pci_subsys_1002_4150_148c_2064, 0}; +#undef pci_ss_info_148c_2064 +#define pci_ss_info_148c_2064 pci_ss_info_1002_4150_148c_2064 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2066 = + {0x148c, 0x2066, pci_subsys_1002_4150_148c_2066, 0}; +#undef pci_ss_info_148c_2066 +#define pci_ss_info_148c_2066 pci_ss_info_1002_4150_148c_2066 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c19 = + {0x174b, 0x7c19, pci_subsys_1002_4150_174b_7c19, 0}; +#undef pci_ss_info_174b_7c19 +#define pci_ss_info_174b_7c19 pci_ss_info_1002_4150_174b_7c19 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4150_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4150_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4150_17ee_2002 = + {0x17ee, 0x2002, pci_subsys_1002_4150_17ee_2002, 0}; +#undef pci_ss_info_17ee_2002 +#define pci_ss_info_17ee_2002 pci_ss_info_1002_4150_17ee_2002 +static const pciSubsystemInfo pci_ss_info_1002_4150_18bc_0101 = + {0x18bc, 0x0101, pci_subsys_1002_4150_18bc_0101, 0}; +#undef pci_ss_info_18bc_0101 +#define pci_ss_info_18bc_0101 pci_ss_info_1002_4150_18bc_0101 +static const pciSubsystemInfo pci_ss_info_1002_4151_1043_c004 = + {0x1043, 0xc004, pci_subsys_1002_4151_1043_c004, 0}; +#undef pci_ss_info_1043_c004 +#define pci_ss_info_1043_c004 pci_ss_info_1002_4151_1043_c004 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4152_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4152_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_4772 = + {0x1002, 0x4772, pci_subsys_1002_4152_1002_4772, 0}; +#undef pci_ss_info_1002_4772 +#define pci_ss_info_1002_4772 pci_ss_info_1002_4152_1002_4772 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c002 = + {0x1043, 0xc002, pci_subsys_1002_4152_1043_c002, 0}; +#undef pci_ss_info_1043_c002 +#define pci_ss_info_1043_c002 pci_ss_info_1002_4152_1043_c002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c01a = + {0x1043, 0xc01a, pci_subsys_1002_4152_1043_c01a, 0}; +#undef pci_ss_info_1043_c01a +#define pci_ss_info_1043_c01a pci_ss_info_1002_4152_1043_c01a +static const pciSubsystemInfo pci_ss_info_1002_4152_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4152_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4152_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4152_1787_4002 = + {0x1787, 0x4002, pci_subsys_1002_4152_1787_4002, 0}; +#undef pci_ss_info_1787_4002 +#define pci_ss_info_1787_4002 pci_ss_info_1002_4152_1787_4002 +static const pciSubsystemInfo pci_ss_info_1002_4153_1462_932c = + {0x1462, 0x932c, pci_subsys_1002_4153_1462_932c, 0}; +#undef pci_ss_info_1462_932c +#define pci_ss_info_1462_932c pci_ss_info_1002_4153_1462_932c +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4170_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4170_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_4723 = + {0x1002, 0x4723, pci_subsys_1002_4170_1002_4723, 0}; +#undef pci_ss_info_1002_4723 +#define pci_ss_info_1002_4723 pci_ss_info_1002_4170_1002_4723 +static const pciSubsystemInfo pci_ss_info_1002_4170_1458_4025 = + {0x1458, 0x4025, pci_subsys_1002_4170_1458_4025, 0}; +#undef pci_ss_info_1458_4025 +#define pci_ss_info_1458_4025 pci_ss_info_1002_4170_1458_4025 +static const pciSubsystemInfo pci_ss_info_1002_4170_148c_2067 = + {0x148c, 0x2067, pci_subsys_1002_4170_148c_2067, 0}; +#undef pci_ss_info_148c_2067 +#define pci_ss_info_148c_2067 pci_ss_info_1002_4170_148c_2067 +static const pciSubsystemInfo pci_ss_info_1002_4170_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4170_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4170_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4170_17ee_2003 = + {0x17ee, 0x2003, pci_subsys_1002_4170_17ee_2003, 0}; +#undef pci_ss_info_17ee_2003 +#define pci_ss_info_17ee_2003 pci_ss_info_1002_4170_17ee_2003 +static const pciSubsystemInfo pci_ss_info_1002_4170_18bc_0100 = + {0x18bc, 0x0100, pci_subsys_1002_4170_18bc_0100, 0}; +#undef pci_ss_info_18bc_0100 +#define pci_ss_info_18bc_0100 pci_ss_info_1002_4170_18bc_0100 +static const pciSubsystemInfo pci_ss_info_1002_4171_1043_c005 = + {0x1043, 0xc005, pci_subsys_1002_4171_1043_c005, 0}; +#undef pci_ss_info_1043_c005 +#define pci_ss_info_1043_c005 pci_ss_info_1002_4171_1043_c005 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4172_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4172_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_4773 = + {0x1002, 0x4773, pci_subsys_1002_4172_1002_4773, 0}; +#undef pci_ss_info_1002_4773 +#define pci_ss_info_1002_4773 pci_ss_info_1002_4172_1002_4773 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c003 = + {0x1043, 0xc003, pci_subsys_1002_4172_1043_c003, 0}; +#undef pci_ss_info_1043_c003 +#define pci_ss_info_1043_c003 pci_ss_info_1002_4172_1043_c003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c01b = + {0x1043, 0xc01b, pci_subsys_1002_4172_1043_c01b, 0}; +#undef pci_ss_info_1043_c01b +#define pci_ss_info_1043_c01b pci_ss_info_1002_4172_1043_c01b +static const pciSubsystemInfo pci_ss_info_1002_4172_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4172_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4172_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4172_1787_4003 = + {0x1787, 0x4003, pci_subsys_1002_4172_1787_4003, 0}; +#undef pci_ss_info_1787_4003 +#define pci_ss_info_1787_4003 pci_ss_info_1002_4172_1787_4003 +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4336_1002_4336 = + {0x1002, 0x4336, pci_subsys_1002_4336_1002_4336, 0}; +#undef pci_ss_info_1002_4336 +#define pci_ss_info_1002_4336 pci_ss_info_1002_4336_1002_4336 +static const pciSubsystemInfo pci_ss_info_1002_4336_103c_0024 = + {0x103c, 0x0024, pci_subsys_1002_4336_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_1002_4336_103c_0024 +static const pciSubsystemInfo pci_ss_info_1002_4336_161f_2029 = + {0x161f, 0x2029, pci_subsys_1002_4336_161f_2029, 0}; +#undef pci_ss_info_161f_2029 +#define pci_ss_info_161f_2029 pci_ss_info_1002_4336_161f_2029 +static const pciSubsystemInfo pci_ss_info_1002_4337_1014_053a = + {0x1014, 0x053a, pci_subsys_1002_4337_1014_053a, 0}; +#undef pci_ss_info_1014_053a +#define pci_ss_info_1014_053a pci_ss_info_1002_4337_1014_053a +static const pciSubsystemInfo pci_ss_info_1002_4337_103c_0850 = + {0x103c, 0x0850, pci_subsys_1002_4337_103c_0850, 0}; +#undef pci_ss_info_103c_0850 +#define pci_ss_info_103c_0850 pci_ss_info_1002_4337_103c_0850 +static const pciSubsystemInfo pci_ss_info_1002_4370_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4370_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4370_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4371_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4371_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4371_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4372_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4372_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4372_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4373_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4373_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4373_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4374_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4374_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4374_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4375_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4375_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4375_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4376_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4376_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4376_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4377_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4377_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4377_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4378_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4378_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4378_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00ce = + {0x1028, 0x00ce, pci_subsys_1002_4752_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_1002_4752_1028_00ce +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1002_4752_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1002_4752_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_0134 = + {0x1028, 0x0134, pci_subsys_1002_4752_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_1002_4752_1028_0134 +static const pciSubsystemInfo pci_ss_info_1002_4752_1734_007a = + {0x1734, 0x007a, pci_subsys_1002_4752_1734_007a, 0}; +#undef pci_ss_info_1734_007a +#define pci_ss_info_1734_007a pci_ss_info_1002_4752_1734_007a +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3411 = + {0x8086, 0x3411, pci_subsys_1002_4752_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_1002_4752_8086_3411 +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3427 = + {0x8086, 0x3427, pci_subsys_1002_4752_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_1002_4752_8086_3427 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_475a_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_475a_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e7 = + {0x0e11, 0xb0e7, pci_subsys_1002_4c42_0e11_b0e7, 0}; +#undef pci_ss_info_0e11_b0e7 +#define pci_ss_info_0e11_b0e7 pci_ss_info_1002_4c42_0e11_b0e7 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c46_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_1002_4c46_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_1002_4c46_1028_00b1 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b160 = + {0x0e11, 0xb160, pci_subsys_1002_4c4d_0e11_b160, 0}; +#undef pci_ss_info_0e11_b160 +#define pci_ss_info_0e11_b160 pci_ss_info_1002_4c4d_0e11_b160 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00aa = + {0x1028, 0x00aa, pci_subsys_1002_4c4d_1028_00aa, 0}; +#undef pci_ss_info_1028_00aa +#define pci_ss_info_1028_00aa pci_ss_info_1002_4c4d_1028_00aa +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00bb = + {0x1028, 0x00bb, pci_subsys_1002_4c4d_1028_00bb, 0}; +#undef pci_ss_info_1028_00bb +#define pci_ss_info_1028_00bb pci_ss_info_1002_4c4d_1028_00bb +static const pciSubsystemInfo pci_ss_info_1002_4c4d_10e1_10cf = + {0x10e1, 0x10cf, pci_subsys_1002_4c4d_10e1_10cf, 0}; +#undef pci_ss_info_10e1_10cf +#define pci_ss_info_10e1_10cf pci_ss_info_1002_4c4d_10e1_10cf +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1179_ff00 = + {0x1179, 0xff00, pci_subsys_1002_4c4d_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_1002_4c4d_1179_ff00 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_13bd_1019 = + {0x13bd, 0x1019, pci_subsys_1002_4c4d_13bd_1019, 0}; +#undef pci_ss_info_13bd_1019 +#define pci_ss_info_13bd_1019 pci_ss_info_1002_4c4d_13bd_1019 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c52_1033_8112 = + {0x1033, 0x8112, pci_subsys_1002_4c52_1033_8112, 0}; +#undef pci_ss_info_1033_8112 +#define pci_ss_info_1033_8112 pci_ss_info_1002_4c52_1033_8112 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_012a = + {0x1028, 0x012a, pci_subsys_1002_4c57_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_1002_4c57_1028_012a +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c59_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c59_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1509_1930 = + {0x1509, 0x1930, pci_subsys_1002_4c59_1509_1930, 0}; +#undef pci_ss_info_1509_1930 +#define pci_ss_info_1509_1930 pci_ss_info_1002_4c59_1509_1930 +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_515e = + {0x1002, 0x515e, pci_subsys_1002_4e44_1002_515e, 0}; +#undef pci_ss_info_1002_515e +#define pci_ss_info_1002_515e pci_ss_info_1002_4e44_1002_515e +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_5965 = + {0x1002, 0x5965, pci_subsys_1002_4e44_1002_5965, 0}; +#undef pci_ss_info_1002_5965 +#define pci_ss_info_1002_5965 pci_ss_info_1002_4e44_1002_5965 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4e45_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4e45_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1681_0002 = + {0x1681, 0x0002, pci_subsys_1002_4e45_1681_0002, 0}; +#undef pci_ss_info_1681_0002 +#define pci_ss_info_1681_0002 pci_ss_info_1002_4e45_1681_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1025_005a = + {0x1025, 0x005a, pci_subsys_1002_4e50_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1002_4e50_1025_005a +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_088c = + {0x103c, 0x088c, pci_subsys_1002_4e50_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1002_4e50_103c_088c +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_0890 = + {0x103c, 0x0890, pci_subsys_1002_4e50_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1002_4e50_103c_0890 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1734_1055 = + {0x1734, 0x1055, pci_subsys_1002_4e50_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_1002_4e50_1734_1055 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4e65_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4e65_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1681_0003 = + {0x1681, 0x0003, pci_subsys_1002_4e65_1681_0003, 0}; +#undef pci_ss_info_1681_0003 +#define pci_ss_info_1681_0003 pci_ss_info_1002_4e65_1681_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e6a_1002_4e71 = + {0x1002, 0x4e71, pci_subsys_1002_4e6a_1002_4e71, 0}; +#undef pci_ss_info_1002_4e71 +#define pci_ss_info_1002_4e71 pci_ss_info_1002_4e6a_1002_4e71 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_1681_0010 = + {0x1681, 0x0010, pci_subsys_1002_514c_1681_0010, 0}; +#undef pci_ss_info_1681_0010 +#define pci_ss_info_1681_0010 pci_ss_info_1002_514c_1681_0010 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_103a = + {0x1002, 0x103a, pci_subsys_1002_5157_1002_103a, 0}; +#undef pci_ss_info_1002_103a +#define pci_ss_info_1002_103a pci_ss_info_1002_5157_1002_103a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7146 = + {0x174b, 0x7146, pci_subsys_1002_5157_174b_7146, 0}; +#undef pci_ss_info_174b_7146 +#define pci_ss_info_174b_7146 pci_ss_info_1002_5157_174b_7146 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_029a = + {0x1014, 0x029a, pci_subsys_1002_5159_1014_029a, 0}; +#undef pci_ss_info_1014_029a +#define pci_ss_info_1014_029a pci_ss_info_1002_5159_1014_029a +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_02c8 = + {0x1014, 0x02c8, pci_subsys_1002_5159_1014_02c8, 0}; +#undef pci_ss_info_1014_02c8 +#define pci_ss_info_1014_02c8 pci_ss_info_1002_5159_1014_02c8 +static const pciSubsystemInfo pci_ss_info_1002_5159_1028_019a = + {0x1028, 0x019a, pci_subsys_1002_5159_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_1002_5159_1028_019a +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_5159_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_5159_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_5346_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5346_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5346_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5941_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5941_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5941_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5941_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5941_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5941_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5941_17af_200d = + {0x17af, 0x200d, pci_subsys_1002_5941_17af_200d, 0}; +#undef pci_ss_info_17af_200d +#define pci_ss_info_17af_200d pci_ss_info_1002_5941_17af_200d +static const pciSubsystemInfo pci_ss_info_1002_5941_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5941_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5941_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5950_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5950_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5950_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5954_1002_5954 = + {0x1002, 0x5954, pci_subsys_1002_5954_1002_5954, 0}; +#undef pci_ss_info_1002_5954 +#define pci_ss_info_1002_5954 pci_ss_info_1002_5954_1002_5954 +static const pciSubsystemInfo pci_ss_info_1002_5955_1002_5955 = + {0x1002, 0x5955, pci_subsys_1002_5955_1002_5955, 0}; +#undef pci_ss_info_1002_5955 +#define pci_ss_info_1002_5955 pci_ss_info_1002_5955_1002_5955 +static const pciSubsystemInfo pci_ss_info_1002_5955_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5955_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5955_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5961_1002_2f72 = + {0x1002, 0x2f72, pci_subsys_1002_5961_1002_2f72, 0}; +#undef pci_ss_info_1002_2f72 +#define pci_ss_info_1002_2f72 pci_ss_info_1002_5961_1002_2f72 +static const pciSubsystemInfo pci_ss_info_1002_5961_1019_4c30 = + {0x1019, 0x4c30, pci_subsys_1002_5961_1019_4c30, 0}; +#undef pci_ss_info_1019_4c30 +#define pci_ss_info_1019_4c30 pci_ss_info_1002_5961_1019_4c30 +static const pciSubsystemInfo pci_ss_info_1002_5961_12ab_5961 = + {0x12ab, 0x5961, pci_subsys_1002_5961_12ab_5961, 0}; +#undef pci_ss_info_12ab_5961 +#define pci_ss_info_12ab_5961 pci_ss_info_1002_5961_12ab_5961 +static const pciSubsystemInfo pci_ss_info_1002_5961_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5961_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5961_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5961_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5961_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5961_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5961_17af_200c = + {0x17af, 0x200c, pci_subsys_1002_5961_17af_200c, 0}; +#undef pci_ss_info_17af_200c +#define pci_ss_info_17af_200c pci_ss_info_1002_5961_17af_200c +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5961_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5961_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0051 = + {0x18bc, 0x0051, pci_subsys_1002_5961_18bc_0051, 0}; +#undef pci_ss_info_18bc_0051 +#define pci_ss_info_18bc_0051 pci_ss_info_1002_5961_18bc_0051 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0053 = + {0x18bc, 0x0053, pci_subsys_1002_5961_18bc_0053, 0}; +#undef pci_ss_info_18bc_0053 +#define pci_ss_info_18bc_0053 pci_ss_info_1002_5961_18bc_0053 +static const pciSubsystemInfo pci_ss_info_1002_5964_1043_c006 = + {0x1043, 0xc006, pci_subsys_1002_5964_1043_c006, 0}; +#undef pci_ss_info_1043_c006 +#define pci_ss_info_1043_c006 pci_ss_info_1002_5964_1043_c006 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5964_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5964_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5964_147b_6191 = + {0x147b, 0x6191, pci_subsys_1002_5964_147b_6191, 0}; +#undef pci_ss_info_147b_6191 +#define pci_ss_info_147b_6191 pci_ss_info_1002_5964_147b_6191 +static const pciSubsystemInfo pci_ss_info_1002_5964_148c_2073 = + {0x148c, 0x2073, pci_subsys_1002_5964_148c_2073, 0}; +#undef pci_ss_info_148c_2073 +#define pci_ss_info_148c_2073 pci_ss_info_1002_5964_148c_2073 +static const pciSubsystemInfo pci_ss_info_1002_5964_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5964_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5964_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5964_1787_5964 = + {0x1787, 0x5964, pci_subsys_1002_5964_1787_5964, 0}; +#undef pci_ss_info_1787_5964 +#define pci_ss_info_1787_5964 pci_ss_info_1002_5964_1787_5964 +static const pciSubsystemInfo pci_ss_info_1002_5964_17af_2012 = + {0x17af, 0x2012, pci_subsys_1002_5964_17af_2012, 0}; +#undef pci_ss_info_17af_2012 +#define pci_ss_info_17af_2012 pci_ss_info_1002_5964_17af_2012 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0170 = + {0x18bc, 0x0170, pci_subsys_1002_5964_18bc_0170, 0}; +#undef pci_ss_info_18bc_0170 +#define pci_ss_info_18bc_0170 pci_ss_info_1002_5964_18bc_0170 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0173 = + {0x18bc, 0x0173, pci_subsys_1002_5964_18bc_0173, 0}; +#undef pci_ss_info_18bc_0173 +#define pci_ss_info_18bc_0173 pci_ss_info_1002_5964_18bc_0173 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_002a = + {0x1043, 0x002a, pci_subsys_1002_5b60_1043_002a, 0}; +#undef pci_ss_info_1043_002a +#define pci_ss_info_1043_002a pci_ss_info_1002_5b60_1043_002a +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_032e = + {0x1043, 0x032e, pci_subsys_1002_5b60_1043_032e, 0}; +#undef pci_ss_info_1043_032e +#define pci_ss_info_1043_032e pci_ss_info_1002_5b60_1043_032e +static const pciSubsystemInfo pci_ss_info_1002_5b60_1462_0402 = + {0x1462, 0x0402, pci_subsys_1002_5b60_1462_0402, 0}; +#undef pci_ss_info_1462_0402 +#define pci_ss_info_1462_0402 pci_ss_info_1002_5b60_1462_0402 +static const pciSubsystemInfo pci_ss_info_1002_5b70_1462_0403 = + {0x1462, 0x0403, pci_subsys_1002_5b70_1462_0403, 0}; +#undef pci_ss_info_1462_0403 +#define pci_ss_info_1462_0403 pci_ss_info_1002_5b70_1462_0403 +static const pciSubsystemInfo pci_ss_info_1002_5c63_1002_5c63 = + {0x1002, 0x5c63, pci_subsys_1002_5c63_1002_5c63, 0}; +#undef pci_ss_info_1002_5c63 +#define pci_ss_info_1002_5c63 pci_ss_info_1002_5c63_1002_5c63 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5d44_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5d44_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5d44_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5d44_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5d44_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1787_5965 = + {0x1787, 0x5965, pci_subsys_1002_5d44_1787_5965, 0}; +#undef pci_ss_info_1787_5965 +#define pci_ss_info_1787_5965 pci_ss_info_1002_5d44_1787_5965 +static const pciSubsystemInfo pci_ss_info_1002_5d44_17af_2013 = + {0x17af, 0x2013, pci_subsys_1002_5d44_17af_2013, 0}; +#undef pci_ss_info_17af_2013 +#define pci_ss_info_17af_2013 pci_ss_info_1002_5d44_17af_2013 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0171 = + {0x18bc, 0x0171, pci_subsys_1002_5d44_18bc_0171, 0}; +#undef pci_ss_info_18bc_0171 +#define pci_ss_info_18bc_0171 pci_ss_info_1002_5d44_18bc_0171 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0172 = + {0x18bc, 0x0172, pci_subsys_1002_5d44_18bc_0172, 0}; +#undef pci_ss_info_18bc_0172 +#define pci_ss_info_18bc_0172 pci_ss_info_1002_5d44_18bc_0172 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b12 = + {0x1002, 0x0b12, pci_subsys_1002_5d52_1002_0b12, 0}; +#undef pci_ss_info_1002_0b12 +#define pci_ss_info_1002_0b12 pci_ss_info_1002_5d52_1002_0b12 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b13 = + {0x1002, 0x0b13, pci_subsys_1002_5d52_1002_0b13, 0}; +#undef pci_ss_info_1002_0b13 +#define pci_ss_info_1002_0b13 pci_ss_info_1002_5d52_1002_0b13 +static const pciSubsystemInfo pci_ss_info_1002_5e4d_148c_2116 = + {0x148c, 0x2116, pci_subsys_1002_5e4d_148c_2116, 0}; +#undef pci_ss_info_148c_2116 +#define pci_ss_info_148c_2116 pci_ss_info_1002_5e4d_148c_2116 +static const pciSubsystemInfo pci_ss_info_1002_5e6d_148c_2117 = + {0x148c, 0x2117, pci_subsys_1002_5e6d_148c_2117, 0}; +#undef pci_ss_info_148c_2117 +#define pci_ss_info_148c_2117 pci_ss_info_1002_5e6d_148c_2117 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7109_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7109_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0d02 = + {0x1002, 0x0d02, pci_subsys_1002_7109_1002_0d02, 0}; +#undef pci_ss_info_1002_0d02 +#define pci_ss_info_1002_0d02 pci_ss_info_1002_7109_1002_0d02 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7129_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7129_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0d03 = + {0x1002, 0x0d03, pci_subsys_1002_7129_1002_0d03, 0}; +#undef pci_ss_info_1002_0d03 +#define pci_ss_info_1002_0d03 pci_ss_info_1002_7129_1002_0d03 +static const pciSubsystemInfo pci_ss_info_1002_7142_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7142_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7142_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7146_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7146_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7146_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7162_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7162_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7162_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7166_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7166_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7166_1002_0323 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_100b_0020_103c_0024 = + {0x103c, 0x0024, pci_subsys_100b_0020_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_100b_0020_103c_0024 +static const pciSubsystemInfo pci_ss_info_100b_0020_12d9_000c = + {0x12d9, 0x000c, pci_subsys_100b_0020_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_100b_0020_12d9_000c +static const pciSubsystemInfo pci_ss_info_100b_0020_1385_f311 = + {0x1385, 0xf311, pci_subsys_100b_0020_1385_f311, 0}; +#undef pci_ss_info_1385_f311 +#define pci_ss_info_1385_f311 pci_ss_info_100b_0020_1385_f311 +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0019_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0019_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_14cb_0100 = + {0x14cb, 0x0100, pci_subsys_1011_0019_14cb_0100, 0}; +#undef pci_ss_info_14cb_0100 +#define pci_ss_info_14cb_0100 pci_ss_info_1011_0019_14cb_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1011_0046_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1011_0046_4c53_1050 +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_1011_0046_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_1011_0046_4c53_1051 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0364 = + {0x9005, 0x0364, pci_subsys_1011_0046_9005_0364, 0}; +#undef pci_ss_info_9005_0364 +#define pci_ss_info_9005_0364 pci_ss_info_1011_0046_9005_0364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_1136 = + {0x153b, 0x1136, pci_subsys_1013_6003_153b_1136, 0}; +#undef pci_ss_info_153b_1136 +#define pci_ss_info_153b_1136 pci_ss_info_1013_6003_153b_1136 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_0031_1014_0031 = + {0x1014, 0x0031, pci_subsys_1014_0031_1014_0031, 0}; +#undef pci_ss_info_1014_0031 +#define pci_ss_info_1014_0031 pci_ss_info_1014_0031_1014_0031 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +#endif +static const pciSubsystemInfo pci_ss_info_1014_00b7_1092_00b8 = + {0x1092, 0x00b8, pci_subsys_1014_00b7_1092_00b8, 0}; +#undef pci_ss_info_1092_00b8 +#define pci_ss_info_1092_00b8 pci_ss_info_1014_00b7_1092_00b8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0241 = + {0x1014, 0x0241, pci_subsys_1014_0180_1014_0241, 0}; +#undef pci_ss_info_1014_0241 +#define pci_ss_info_1014_0241 pci_ss_info_1014_0180_1014_0241 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0264 = + {0x1014, 0x0264, pci_subsys_1014_0180_1014_0264, 0}; +#undef pci_ss_info_1014_0264 +#define pci_ss_info_1014_0264 pci_ss_info_1014_0180_1014_0264 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_021a = + {0x1014, 0x021a, pci_subsys_1014_0219_1014_021a, 0}; +#undef pci_ss_info_1014_021a +#define pci_ss_info_1014_021a pci_ss_info_1014_0219_1014_021a +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0251 = + {0x1014, 0x0251, pci_subsys_1014_0219_1014_0251, 0}; +#undef pci_ss_info_1014_0251 +#define pci_ss_info_1014_0251 pci_ss_info_1014_0219_1014_0251 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0252 = + {0x1014, 0x0252, pci_subsys_1014_0219_1014_0252, 0}; +#undef pci_ss_info_1014_0252 +#define pci_ss_info_1014_0252 pci_ss_info_1014_0219_1014_0252 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_028d = + {0x1014, 0x028d, pci_subsys_1014_028c_1014_028d, 0}; +#undef pci_ss_info_1014_028d +#define pci_ss_info_1014_028d pci_ss_info_1014_028c_1014_028d +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02be = + {0x1014, 0x02be, pci_subsys_1014_028c_1014_02be, 0}; +#undef pci_ss_info_1014_02be +#define pci_ss_info_1014_02be pci_ss_info_1014_028c_1014_02be +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02c0 = + {0x1014, 0x02c0, pci_subsys_1014_028c_1014_02c0, 0}; +#undef pci_ss_info_1014_02c0 +#define pci_ss_info_1014_02c0 pci_ss_info_1014_028c_1014_02c0 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_030d = + {0x1014, 0x030d, pci_subsys_1014_028c_1014_030d, 0}; +#undef pci_ss_info_1014_030d +#define pci_ss_info_1014_030d pci_ss_info_1014_028c_1014_030d +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_1014_02bd_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_1014_02bd_1014_02c1 +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_1014_02bd_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_1014_02bd_1014_02c2 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0477 = + {0x101e, 0x0477, pci_subsys_101e_1960_101e_0477, 0}; +#undef pci_ss_info_101e_0477 +#define pci_ss_info_101e_0477 pci_ss_info_101e_1960_101e_0477 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0494 = + {0x101e, 0x0494, pci_subsys_101e_1960_101e_0494, 0}; +#undef pci_ss_info_101e_0494 +#define pci_ss_info_101e_0494 pci_ss_info_101e_1960_101e_0494 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0503 = + {0x101e, 0x0503, pci_subsys_101e_1960_101e_0503, 0}; +#undef pci_ss_info_101e_0503 +#define pci_ss_info_101e_0503 pci_ss_info_101e_1960_101e_0503 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0511 = + {0x101e, 0x0511, pci_subsys_101e_1960_101e_0511, 0}; +#undef pci_ss_info_101e_0511 +#define pci_ss_info_101e_0511 pci_ss_info_101e_1960_101e_0511 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0522 = + {0x101e, 0x0522, pci_subsys_101e_1960_101e_0522, 0}; +#undef pci_ss_info_101e_0522 +#define pci_ss_info_101e_0522 pci_ss_info_101e_1960_101e_0522 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_103c_60e7 = + {0x103c, 0x60e7, pci_subsys_101e_1960_103c_60e7, 0}; +#undef pci_ss_info_103c_60e7 +#define pci_ss_info_103c_60e7 pci_ss_info_101e_1960_103c_60e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_1022_2000 = + {0x1022, 0x2000, pci_subsys_1022_2000_1022_2000, 0}; +#undef pci_ss_info_1022_2000 +#define pci_ss_info_1022_2000 pci_ss_info_1022_2000_1022_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2702 = + {0x1259, 0x2702, pci_subsys_1022_2000_1259_2702, 0}; +#undef pci_ss_info_1259_2702 +#define pci_ss_info_1259_2702 pci_ss_info_1022_2000_1259_2702 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2703 = + {0x1259, 0x2703, pci_subsys_1022_2000_1259_2703, 0}; +#undef pci_ss_info_1259_2703 +#define pci_ss_info_1259_2703 pci_ss_info_1022_2000_1259_2703 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1022_2000_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1022_2000_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_1022_2000_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_1022_2000_4c53_1010 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_1022_2000_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_1022_2000_4c53_1020 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_1022_2000_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_1022_2000_4c53_1030 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_1022_2000_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_1022_2000_4c53_1040 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_1022_2000_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_1022_2000_4c53_1060 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7460_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7460_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7460_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7464_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7464_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7464_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7468_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7468_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7468_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7469_1022_2b80 = + {0x1022, 0x2b80, pci_subsys_1022_7469_1022_2b80, 0}; +#undef pci_ss_info_1022_2b80 +#define pci_ss_info_1022_2b80 pci_ss_info_1022_7469_1022_2b80 +static const pciSubsystemInfo pci_ss_info_1022_7469_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7469_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7469_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746b_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746b_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746b_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746d_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746d_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746d_161f_3017 +static const pciSubsystemInfo pci_ss_info_1023_2001_122d_1400 = + {0x122d, 0x1400, pci_subsys_1023_2001_122d_1400, 0}; +#undef pci_ss_info_122d_1400 +#define pci_ss_info_122d_1400 pci_ss_info_1023_2001_122d_1400 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_1025 = + {0x1014, 0x1025, pci_subsys_1023_8620_1014_1025, 0}; +#undef pci_ss_info_1014_1025 +#define pci_ss_info_1014_1025 pci_ss_info_1023_8620_1014_1025 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016c = + {0x1028, 0x016c, pci_subsys_1028_0013_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1028_0013_1028_016c +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016d = + {0x1028, 0x016d, pci_subsys_1028_0013_1028_016d, 0}; +#undef pci_ss_info_1028_016d +#define pci_ss_info_1028_016d pci_ss_info_1028_0013_1028_016d +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016e = + {0x1028, 0x016e, pci_subsys_1028_0013_1028_016e, 0}; +#undef pci_ss_info_1028_016e +#define pci_ss_info_1028_016e pci_ss_info_1028_0013_1028_016e +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016f = + {0x1028, 0x016f, pci_subsys_1028_0013_1028_016f, 0}; +#undef pci_ss_info_1028_016f +#define pci_ss_info_1028_016f pci_ss_info_1028_0013_1028_016f +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_0170 = + {0x1028, 0x0170, pci_subsys_1028_0013_1028_0170, 0}; +#undef pci_ss_info_1028_0170 +#define pci_ss_info_1028_0170 pci_ss_info_1028_0013_1028_0170 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_102a_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_102a_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_0106 = + {0x9005, 0x0106, pci_subsys_102a_001f_9005_0106, 0}; +#undef pci_ss_info_9005_0106 +#define pci_ss_info_9005_0106 pci_ss_info_102a_001f_9005_0106 +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_102a_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_102a_001f_9005_a180 +#endif +static const pciSubsystemInfo pci_ss_info_102a_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_102a_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_102a_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0106 = + {0x1028, 0x0106, pci_subsys_102a_00cf_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_102a_00cf_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0121 = + {0x1028, 0x0121, pci_subsys_102a_00cf_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_102a_00cf_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d43 = + {0x102b, 0x0d43, pci_subsys_102b_0525_102b_0d43, 0}; +#undef pci_ss_info_102b_0d43 +#define pci_ss_info_102b_0d43 pci_ss_info_102b_0525_102b_0d43 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0850 = + {0x102b, 0x0850, pci_subsys_102b_0527_102b_0850, 0}; +#undef pci_ss_info_102b_0850 +#define pci_ss_info_102b_0850 pci_ss_info_102b_0527_102b_0850 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1020 = + {0x102b, 0x1020, pci_subsys_102b_0528_102b_1020, 0}; +#undef pci_ss_info_102b_1020 +#define pci_ss_info_102b_1020 pci_ss_info_102b_0528_102b_1020 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1030 = + {0x102b, 0x1030, pci_subsys_102b_0528_102b_1030, 0}; +#undef pci_ss_info_102b_1030 +#define pci_ss_info_102b_1030 pci_ss_info_102b_0528_102b_1030 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_14e1 = + {0x102b, 0x14e1, pci_subsys_102b_0528_102b_14e1, 0}; +#undef pci_ss_info_102b_14e1 +#define pci_ss_info_102b_14e1 pci_ss_info_102b_0528_102b_14e1 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_2021 = + {0x102b, 0x2021, pci_subsys_102b_0528_102b_2021, 0}; +#undef pci_ss_info_102b_2021 +#define pci_ss_info_102b_2021 pci_ss_info_102b_0528_102b_2021 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1820 = + {0x102b, 0x1820, pci_subsys_102b_2537_102b_1820, 0}; +#undef pci_ss_info_102b_1820 +#define pci_ss_info_102b_1820 pci_ss_info_102b_2537_102b_1820 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1830 = + {0x102b, 0x1830, pci_subsys_102b_2537_102b_1830, 0}; +#undef pci_ss_info_102b_1830 +#define pci_ss_info_102b_1830 pci_ss_info_102b_2537_102b_1830 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1c10 = + {0x102b, 0x1c10, pci_subsys_102b_2537_102b_1c10, 0}; +#undef pci_ss_info_102b_1c10 +#define pci_ss_info_102b_1c10 pci_ss_info_102b_2537_102b_1c10 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2811 = + {0x102b, 0x2811, pci_subsys_102b_2537_102b_2811, 0}; +#undef pci_ss_info_102b_2811 +#define pci_ss_info_102b_2811 pci_ss_info_102b_2537_102b_2811 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2c11 = + {0x102b, 0x2c11, pci_subsys_102b_2537_102b_2c11, 0}; +#undef pci_ss_info_102b_2c11 +#define pci_ss_info_102b_2c11 pci_ss_info_102b_2537_102b_2c11 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_08c7 = + {0x102b, 0x08c7, pci_subsys_102b_2538_102b_08c7, 0}; +#undef pci_ss_info_102b_08c7 +#define pci_ss_info_102b_08c7 pci_ss_info_102b_2538_102b_08c7 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_0907 = + {0x102b, 0x0907, pci_subsys_102b_2538_102b_0907, 0}; +#undef pci_ss_info_102b_0907 +#define pci_ss_info_102b_0907 pci_ss_info_102b_2538_102b_0907 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1047 = + {0x102b, 0x1047, pci_subsys_102b_2538_102b_1047, 0}; +#undef pci_ss_info_102b_1047 +#define pci_ss_info_102b_1047 pci_ss_info_102b_2538_102b_1047 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1087 = + {0x102b, 0x1087, pci_subsys_102b_2538_102b_1087, 0}; +#undef pci_ss_info_102b_1087 +#define pci_ss_info_102b_1087 pci_ss_info_102b_2538_102b_1087 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_2538 = + {0x102b, 0x2538, pci_subsys_102b_2538_102b_2538, 0}; +#undef pci_ss_info_102b_2538 +#define pci_ss_info_102b_2538 pci_ss_info_102b_2538_102b_2538 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_3007 = + {0x102b, 0x3007, pci_subsys_102b_2538_102b_3007, 0}; +#undef pci_ss_info_102b_3007 +#define pci_ss_info_102b_3007 pci_ss_info_102b_2538_102b_3007 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_00c0_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_00c0_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_102c_00c0_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_102c_00c0_4c53_1010 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_102c_00c0_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_102c_00c0_4c53_1020 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_102c_00c0_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_102c_00c0_4c53_1030 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_00c0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_00c0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_00c0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_00c0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +static const pciSubsystemInfo pci_ss_info_102c_00e5_1179_0001 = + {0x1179, 0x0001, pci_subsys_102c_00e5_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_102c_00e5_1179_0001 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_0c30_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_0c30_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_0c30_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_0c30_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_0c30_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_0c30_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_102c_0c30_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_102c_0c30_4c53_1080 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1033_0035 = + {0x1033, 0x0035, pci_subsys_1033_0035_1033_0035, 0}; +#undef pci_ss_info_1033_0035 +#define pci_ss_info_1033_0035 pci_ss_info_1033_0035_1033_0035 +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_14c2_0105 = + {0x14c2, 0x0105, pci_subsys_1033_0035_14c2_0105, 0}; +#undef pci_ss_info_14c2_0105 +#define pci_ss_info_14c2_0105 pci_ss_info_1033_0035_14c2_0105 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000a = + {0x1931, 0x000a, pci_subsys_1033_0035_1931_000a, 0}; +#undef pci_ss_info_1931_000a +#define pci_ss_info_1931_000a pci_ss_info_1033_0035_1931_000a +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000b = + {0x1931, 0x000b, pci_subsys_1033_0035_1931_000b, 0}; +#undef pci_ss_info_1931_000b +#define pci_ss_info_1931_000b pci_ss_info_1033_0035_1931_000b +static const pciSubsystemInfo pci_ss_info_1033_0035_807d_0035 = + {0x807d, 0x0035, pci_subsys_1033_0035_807d_0035, 0}; +#undef pci_ss_info_807d_0035 +#define pci_ss_info_807d_0035 pci_ss_info_1033_0035_807d_0035 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_14c2_0205 = + {0x14c2, 0x0205, pci_subsys_1033_00e0_14c2_0205, 0}; +#undef pci_ss_info_14c2_0205 +#define pci_ss_info_14c2_0205 pci_ss_info_1033_00e0_14c2_0205 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1033_00e0_807d_1043 = + {0x807d, 0x1043, pci_subsys_1033_00e0_807d_1043, 0}; +#undef pci_ss_info_807d_1043 +#define pci_ss_info_807d_1043 pci_ss_info_1033_00e0_807d_1043 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_0900_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_0900_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_0900_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_0900_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_0900_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_5513_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_5513_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_5513_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6300_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_6300_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_6300_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_6330_1039_6330 = + {0x1039, 0x6330, pci_subsys_1039_6330_1039_6330, 0}; +#undef pci_ss_info_1039_6330 +#define pci_ss_info_1039_6330 pci_ss_info_1039_6330_1039_6330 +static const pciSubsystemInfo pci_ss_info_1039_7001_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_7001_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_7001_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7001_1462_5470 = + {0x1462, 0x5470, pci_subsys_1039_7001_1462_5470, 0}; +#undef pci_ss_info_1462_5470 +#define pci_ss_info_1462_5470 pci_ss_info_1039_7001_1462_5470 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7012_15bd_1001 = + {0x15bd, 0x1001, pci_subsys_1039_7012_15bd_1001, 0}; +#undef pci_ss_info_15bd_1001 +#define pci_ss_info_15bd_1001 pci_ss_info_1039_7012_15bd_1001 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1301 = + {0x103c, 0x1301, pci_subsys_103c_1048_103c_1301, 0}; +#undef pci_ss_info_103c_1301 +#define pci_ss_info_103c_1301 pci_ss_info_103c_1048_103c_1301 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1704 = + {0x0675, 0x1704, pci_subsys_1043_0675_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1043_0675_0675_1704 +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1707 = + {0x0675, 0x1707, pci_subsys_1043_0675_0675_1707, 0}; +#undef pci_ss_info_0675_1707 +#define pci_ss_info_0675_1707 pci_ss_info_1043_0675_0675_1707 +static const pciSubsystemInfo pci_ss_info_1043_0675_10cf_105e = + {0x10cf, 0x105e, pci_subsys_1043_0675_10cf_105e, 0}; +#undef pci_ss_info_10cf_105e +#define pci_ss_info_10cf_105e pci_ss_info_1043_0675_10cf_105e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c032 = + {0x1044, 0xc032, pci_subsys_1044_a511_1044_c032, 0}; +#undef pci_ss_info_1044_c032 +#define pci_ss_info_1044_c032 pci_ss_info_1044_a511_1044_c032 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c035 = + {0x1044, 0xc035, pci_subsys_1044_a511_1044_c035, 0}; +#undef pci_ss_info_1044_c035 +#define pci_ss_info_1044_c035 pci_ss_info_1044_a511_1044_c035 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1048_8901_1048_0935 = + {0x1048, 0x0935, pci_subsys_1048_8901_1048_0935, 0}; +#undef pci_ss_info_1048_0935 +#define pci_ss_info_1048_0935 pci_ss_info_1048_8901_1048_0935 +#endif +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a34 = + {0x1048, 0x0a34, pci_subsys_104c_3d07_1048_0a34, 0}; +#undef pci_ss_info_1048_0a34 +#define pci_ss_info_1048_0a34 pci_ss_info_104c_3d07_1048_0a34 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a36 = + {0x1048, 0x0a36, pci_subsys_104c_3d07_1048_0a36, 0}; +#undef pci_ss_info_1048_0a36 +#define pci_ss_info_1048_0a36 pci_ss_info_104c_3d07_1048_0a36 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a43 = + {0x1048, 0x0a43, pci_subsys_104c_3d07_1048_0a43, 0}; +#undef pci_ss_info_1048_0a43 +#define pci_ss_info_1048_0a43 pci_ss_info_104c_3d07_1048_0a43 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a44 = + {0x1048, 0x0a44, pci_subsys_104c_3d07_1048_0a44, 0}; +#undef pci_ss_info_1048_0a44 +#define pci_ss_info_1048_0a44 pci_ss_info_104c_3d07_1048_0a44 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_000f = + {0x11bd, 0x000f, pci_subsys_104c_8020_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_104c_8020_11bd_000f +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8023_103c_088c = + {0x103c, 0x088c, pci_subsys_104c_8023_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_104c_8023_103c_088c +static const pciSubsystemInfo pci_ss_info_104c_8023_1043_808b = + {0x1043, 0x808b, pci_subsys_104c_8023_1043_808b, 0}; +#undef pci_ss_info_1043_808b +#define pci_ss_info_1043_808b pci_ss_info_104c_8023_1043_808b +static const pciSubsystemInfo pci_ss_info_104c_8025_1458_1000 = + {0x1458, 0x1000, pci_subsys_104c_8025_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_104c_8025_1458_1000 +static const pciSubsystemInfo pci_ss_info_104c_8026_103c_006a = + {0x103c, 0x006a, pci_subsys_104c_8026_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_104c_8026_103c_006a +static const pciSubsystemInfo pci_ss_info_104c_8026_1043_808d = + {0x1043, 0x808d, pci_subsys_104c_8026_1043_808d, 0}; +#undef pci_ss_info_1043_808d +#define pci_ss_info_1043_808d pci_ss_info_104c_8026_1043_808d +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_8029_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_8029_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_8029_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_8029_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_8029_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_8029_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_8029_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_802b_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_802b_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_802b_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_802b_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8031_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8031_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8031_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8031_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8032_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8032_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8032_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8032_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8033_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8033_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8033_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8033_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8034_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8034_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8034_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8034_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8035_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8035_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8035_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_8204_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_8204_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_8204_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_8204_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b00 = + {0x1186, 0x3b00, pci_subsys_104c_8400_1186_3b00, 0}; +#undef pci_ss_info_1186_3b00 +#define pci_ss_info_1186_3b00 pci_ss_info_104c_8400_1186_3b00 +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b01 = + {0x1186, 0x3b01, pci_subsys_104c_8400_1186_3b01, 0}; +#undef pci_ss_info_1186_3b01 +#define pci_ss_info_1186_3b01 pci_ss_info_104c_8400_1186_3b01 +static const pciSubsystemInfo pci_ss_info_104c_8400_16ab_8501 = + {0x16ab, 0x8501, pci_subsys_104c_8400_16ab_8501, 0}; +#undef pci_ss_info_16ab_8501 +#define pci_ss_info_16ab_8501 pci_ss_info_104c_8400_16ab_8501 +static const pciSubsystemInfo pci_ss_info_104c_9066_104c_9066 = + {0x104c, 0x9066, pci_subsys_104c_9066_104c_9066, 0}; +#undef pci_ss_info_104c_9066 +#define pci_ss_info_104c_9066 pci_ss_info_104c_9066_104c_9066 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b04 = + {0x1186, 0x3b04, pci_subsys_104c_9066_1186_3b04, 0}; +#undef pci_ss_info_1186_3b04 +#define pci_ss_info_1186_3b04 pci_ss_info_104c_9066_1186_3b04 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b05 = + {0x1186, 0x3b05, pci_subsys_104c_9066_1186_3b05, 0}; +#undef pci_ss_info_1186_3b05 +#define pci_ss_info_1186_3b05 pci_ss_info_104c_9066_1186_3b05 +static const pciSubsystemInfo pci_ss_info_104c_9066_13d1_aba0 = + {0x13d1, 0xaba0, pci_subsys_104c_9066_13d1_aba0, 0}; +#undef pci_ss_info_13d1_aba0 +#define pci_ss_info_13d1_aba0 pci_ss_info_104c_9066_13d1_aba0 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_5000 = + {0x175c, 0x5000, pci_subsys_104c_a106_175c_5000, 0}; +#undef pci_ss_info_175c_5000 +#define pci_ss_info_175c_5000 pci_ss_info_104c_a106_175c_5000 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_6400 = + {0x175c, 0x6400, pci_subsys_104c_a106_175c_6400, 0}; +#undef pci_ss_info_175c_6400 +#define pci_ss_info_175c_6400 pci_ss_info_104c_a106_175c_6400 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_8700 = + {0x175c, 0x8700, pci_subsys_104c_a106_175c_8700, 0}; +#undef pci_ss_info_175c_8700 +#define pci_ss_info_175c_8700 pci_ss_info_104c_a106_175c_8700 +static const pciSubsystemInfo pci_ss_info_104c_ac16_1014_0092 = + {0x1014, 0x0092, pci_subsys_104c_ac16_1014_0092, 0}; +#undef pci_ss_info_1014_0092 +#define pci_ss_info_1014_0092 pci_ss_info_104c_ac16_1014_0092 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_1014_0130 = + {0x1014, 0x0130, pci_subsys_104c_ac1b_1014_0130, 0}; +#undef pci_ss_info_1014_0130 +#define pci_ss_info_1014_0130 pci_ss_info_104c_ac1b_1014_0130 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_0e11_b121 = + {0x0e11, 0xb121, pci_subsys_104c_ac1c_0e11_b121, 0}; +#undef pci_ss_info_0e11_b121 +#define pci_ss_info_0e11_b121 pci_ss_info_104c_ac1c_0e11_b121 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_1028_0088 = + {0x1028, 0x0088, pci_subsys_104c_ac1c_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_104c_ac1c_1028_0088 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_ac44_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_ac44_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_ac44_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_ac44_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_ac44_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_ac44_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac47_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac47_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac47_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac47_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac4a_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac4a_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac4a_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac4a_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac51_0e11_004e = + {0x0e11, 0x004e, pci_subsys_104c_ac51_0e11_004e, 0}; +#undef pci_ss_info_0e11_004e +#define pci_ss_info_0e11_004e pci_ss_info_104c_ac51_0e11_004e +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_104c_ac51_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_104c_ac51_1028_00b1 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_012a = + {0x1028, 0x012a, pci_subsys_104c_ac51_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_104c_ac51_1028_012a +static const pciSubsystemInfo pci_ss_info_104c_ac51_1033_80cd = + {0x1033, 0x80cd, pci_subsys_104c_ac51_1033_80cd, 0}; +#undef pci_ss_info_1033_80cd +#define pci_ss_info_1033_80cd pci_ss_info_104c_ac51_1033_80cd +static const pciSubsystemInfo pci_ss_info_104c_ac51_1095_10cf = + {0x1095, 0x10cf, pci_subsys_104c_ac51_1095_10cf, 0}; +#undef pci_ss_info_1095_10cf +#define pci_ss_info_1095_10cf pci_ss_info_104c_ac51_1095_10cf +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0528 = + {0x1014, 0x0528, pci_subsys_104c_ac56_1014_0528, 0}; +#undef pci_ss_info_1014_0528 +#define pci_ss_info_1014_0528 pci_ss_info_104c_ac56_1014_0528 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_5100 = + {0x175c, 0x5100, pci_subsys_104c_ac60_175c_5100, 0}; +#undef pci_ss_info_175c_5100 +#define pci_ss_info_175c_5100 pci_ss_info_104c_ac60_175c_5100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6100 = + {0x175c, 0x6100, pci_subsys_104c_ac60_175c_6100, 0}; +#undef pci_ss_info_175c_6100 +#define pci_ss_info_175c_6100 pci_ss_info_104c_ac60_175c_6100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6200 = + {0x175c, 0x6200, pci_subsys_104c_ac60_175c_6200, 0}; +#undef pci_ss_info_175c_6200 +#define pci_ss_info_175c_6200 pci_ss_info_104c_ac60_175c_6200 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_8800 = + {0x175c, 0x8800, pci_subsys_104c_ac60_175c_8800, 0}; +#undef pci_ss_info_175c_8800 +#define pci_ss_info_175c_8800 pci_ss_info_104c_ac60_175c_8800 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1702 = + {0x1043, 0x1702, pci_subsys_1050_6692_1043_1702, 0}; +#undef pci_ss_info_1043_1702 +#define pci_ss_info_1043_1702 pci_ss_info_1050_6692_1043_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1703 = + {0x1043, 0x1703, pci_subsys_1050_6692_1043_1703, 0}; +#undef pci_ss_info_1043_1703 +#define pci_ss_info_1043_1703 pci_ss_info_1050_6692_1043_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1707 = + {0x1043, 0x1707, pci_subsys_1050_6692_1043_1707, 0}; +#undef pci_ss_info_1043_1707 +#define pci_ss_info_1043_1707 pci_ss_info_1050_6692_1043_1707 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1702 = + {0x144f, 0x1702, pci_subsys_1050_6692_144f_1702, 0}; +#undef pci_ss_info_144f_1702 +#define pci_ss_info_144f_1702 pci_ss_info_1050_6692_144f_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1703 = + {0x144f, 0x1703, pci_subsys_1050_6692_144f_1703, 0}; +#undef pci_ss_info_144f_1703 +#define pci_ss_info_144f_1703 pci_ss_info_1050_6692_144f_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1707 = + {0x144f, 0x1707, pci_subsys_1050_6692_144f_1707, 0}; +#undef pci_ss_info_144f_1707 +#define pci_ss_info_144f_1707 pci_ss_info_1050_6692_144f_1707 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0101 = + {0x14fb, 0x0101, pci_subsys_1057_1801_14fb_0101, 0}; +#undef pci_ss_info_14fb_0101 +#define pci_ss_info_14fb_0101 pci_ss_info_1057_1801_14fb_0101 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0102 = + {0x14fb, 0x0102, pci_subsys_1057_1801_14fb_0102, 0}; +#undef pci_ss_info_14fb_0102 +#define pci_ss_info_14fb_0102 pci_ss_info_1057_1801_14fb_0102 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0202 = + {0x14fb, 0x0202, pci_subsys_1057_1801_14fb_0202, 0}; +#undef pci_ss_info_14fb_0202 +#define pci_ss_info_14fb_0202 pci_ss_info_1057_1801_14fb_0202 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0611 = + {0x14fb, 0x0611, pci_subsys_1057_1801_14fb_0611, 0}; +#undef pci_ss_info_14fb_0611 +#define pci_ss_info_14fb_0611 pci_ss_info_1057_1801_14fb_0611 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0612 = + {0x14fb, 0x0612, pci_subsys_1057_1801_14fb_0612, 0}; +#undef pci_ss_info_14fb_0612 +#define pci_ss_info_14fb_0612 pci_ss_info_1057_1801_14fb_0612 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0613 = + {0x14fb, 0x0613, pci_subsys_1057_1801_14fb_0613, 0}; +#undef pci_ss_info_14fb_0613 +#define pci_ss_info_14fb_0613 pci_ss_info_1057_1801_14fb_0613 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0614 = + {0x14fb, 0x0614, pci_subsys_1057_1801_14fb_0614, 0}; +#undef pci_ss_info_14fb_0614 +#define pci_ss_info_14fb_0614 pci_ss_info_1057_1801_14fb_0614 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0621 = + {0x14fb, 0x0621, pci_subsys_1057_1801_14fb_0621, 0}; +#undef pci_ss_info_14fb_0621 +#define pci_ss_info_14fb_0621 pci_ss_info_1057_1801_14fb_0621 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0622 = + {0x14fb, 0x0622, pci_subsys_1057_1801_14fb_0622, 0}; +#undef pci_ss_info_14fb_0622 +#define pci_ss_info_14fb_0622 pci_ss_info_1057_1801_14fb_0622 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0810 = + {0x14fb, 0x0810, pci_subsys_1057_1801_14fb_0810, 0}; +#undef pci_ss_info_14fb_0810 +#define pci_ss_info_14fb_0810 pci_ss_info_1057_1801_14fb_0810 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4200 = + {0x175c, 0x4200, pci_subsys_1057_1801_175c_4200, 0}; +#undef pci_ss_info_175c_4200 +#define pci_ss_info_175c_4200 pci_ss_info_1057_1801_175c_4200 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4300 = + {0x175c, 0x4300, pci_subsys_1057_1801_175c_4300, 0}; +#undef pci_ss_info_175c_4300 +#define pci_ss_info_175c_4300 pci_ss_info_1057_1801_175c_4300 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4400 = + {0x175c, 0x4400, pci_subsys_1057_1801_175c_4400, 0}; +#undef pci_ss_info_175c_4400 +#define pci_ss_info_175c_4400 pci_ss_info_1057_1801_175c_4400 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0010 = + {0xecc0, 0x0010, pci_subsys_1057_1801_ecc0_0010, 0}; +#undef pci_ss_info_ecc0_0010 +#define pci_ss_info_ecc0_0010 pci_ss_info_1057_1801_ecc0_0010 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0020 = + {0xecc0, 0x0020, pci_subsys_1057_1801_ecc0_0020, 0}; +#undef pci_ss_info_ecc0_0020 +#define pci_ss_info_ecc0_0020 pci_ss_info_1057_1801_ecc0_0020 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0031 = + {0xecc0, 0x0031, pci_subsys_1057_1801_ecc0_0031, 0}; +#undef pci_ss_info_ecc0_0031 +#define pci_ss_info_ecc0_0031 pci_ss_info_1057_1801_ecc0_0031 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0040 = + {0xecc0, 0x0040, pci_subsys_1057_1801_ecc0_0040, 0}; +#undef pci_ss_info_ecc0_0040 +#define pci_ss_info_ecc0_0040 pci_ss_info_1057_1801_ecc0_0040 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0041 = + {0xecc0, 0x0041, pci_subsys_1057_1801_ecc0_0041, 0}; +#undef pci_ss_info_ecc0_0041 +#define pci_ss_info_ecc0_0041 pci_ss_info_1057_1801_ecc0_0041 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_1801_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_1801_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_1801_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_1801_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_1801_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_1801_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_1801_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_1801_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_1801_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_1801_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_3410_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_3410_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_3410_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_3410_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0060 = + {0xecc0, 0x0060, pci_subsys_1057_3410_ecc0_0060, 0}; +#undef pci_ss_info_ecc0_0060 +#define pci_ss_info_ecc0_0060 pci_ss_info_1057_3410_ecc0_0060 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_3410_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_3410_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_3410_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_3410_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_3410_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_3410_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0080 = + {0xecc0, 0x0080, pci_subsys_1057_3410_ecc0_0080, 0}; +#undef pci_ss_info_ecc0_0080 +#define pci_ss_info_ecc0_0080 pci_ss_info_1057_3410_ecc0_0080 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0081 = + {0xecc0, 0x0081, pci_subsys_1057_3410_ecc0_0081, 0}; +#undef pci_ss_info_ecc0_0081 +#define pci_ss_info_ecc0_0081 pci_ss_info_1057_3410_ecc0_0081 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0090 = + {0xecc0, 0x0090, pci_subsys_1057_3410_ecc0_0090, 0}; +#undef pci_ss_info_ecc0_0090 +#define pci_ss_info_ecc0_0090 pci_ss_info_1057_3410_ecc0_0090 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00a0 = + {0xecc0, 0x00a0, pci_subsys_1057_3410_ecc0_00a0, 0}; +#undef pci_ss_info_ecc0_00a0 +#define pci_ss_info_ecc0_00a0 pci_ss_info_1057_3410_ecc0_00a0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00b0 = + {0xecc0, 0x00b0, pci_subsys_1057_3410_ecc0_00b0, 0}; +#undef pci_ss_info_ecc0_00b0 +#define pci_ss_info_ecc0_00b0 pci_ss_info_1057_3410_ecc0_00b0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0100 = + {0xecc0, 0x0100, pci_subsys_1057_3410_ecc0_0100, 0}; +#undef pci_ss_info_ecc0_0100 +#define pci_ss_info_ecc0_0100 pci_ss_info_1057_3410_ecc0_0100 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +#endif +static const pciSubsystemInfo pci_ss_info_105a_3319_8086_3427 = + {0x8086, 0x3427, pci_subsys_105a_3319_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_105a_3319_8086_3427 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_3373_1043_80f5 = + {0x1043, 0x80f5, pci_subsys_105a_3373_1043_80f5, 0}; +#undef pci_ss_info_1043_80f5 +#define pci_ss_info_1043_80f5 pci_ss_info_105a_3373_1043_80f5 +static const pciSubsystemInfo pci_ss_info_105a_3373_1462_702e = + {0x1462, 0x702e, pci_subsys_105a_3373_1462_702e, 0}; +#undef pci_ss_info_1462_702e +#define pci_ss_info_1462_702e pci_ss_info_105a_3373_1462_702e +static const pciSubsystemInfo pci_ss_info_105a_3376_1043_809e = + {0x1043, 0x809e, pci_subsys_105a_3376_1043_809e, 0}; +#undef pci_ss_info_1043_809e +#define pci_ss_info_1043_809e pci_ss_info_105a_3376_1043_809e +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_4d69_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d69_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d69_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_1043_807e = + {0x1043, 0x807e, pci_subsys_105a_5275_1043_807e, 0}; +#undef pci_ss_info_1043_807e +#define pci_ss_info_1043_807e pci_ss_info_105a_5275_1043_807e +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_1275 = + {0x105a, 0x1275, pci_subsys_105a_5275_105a_1275, 0}; +#undef pci_ss_info_105a_1275 +#define pci_ss_info_105a_1275 pci_ss_info_105a_5275_105a_1275 +static const pciSubsystemInfo pci_ss_info_105a_5275_1458_b001 = + {0x1458, 0xb001, pci_subsys_105a_5275_1458_b001, 0}; +#undef pci_ss_info_1458_b001 +#define pci_ss_info_1458_b001 pci_ss_info_105a_5275_1458_b001 +static const pciSubsystemInfo pci_ss_info_105a_6268_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_6268_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_6268_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_5348_105d_0037 = + {0x105d, 0x0037, pci_subsys_105d_5348_105d_0037, 0}; +#undef pci_ss_info_105d_0037 +#define pci_ss_info_105d_0037 pci_ss_info_105d_5348_105d_0037 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0050 = + {0x1069, 0x0050, pci_subsys_1069_0050_1069_0050, 0}; +#undef pci_ss_info_1069_0050 +#define pci_ss_info_1069_0050 pci_ss_info_1069_0050_1069_0050 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0052 = + {0x1069, 0x0052, pci_subsys_1069_0050_1069_0052, 0}; +#undef pci_ss_info_1069_0052 +#define pci_ss_info_1069_0052 pci_ss_info_1069_0050_1069_0052 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0054 = + {0x1069, 0x0054, pci_subsys_1069_0050_1069_0054, 0}; +#undef pci_ss_info_1069_0054 +#define pci_ss_info_1069_0054 pci_ss_info_1069_0050_1069_0054 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0242 = + {0x1014, 0x0242, pci_subsys_1069_b166_1014_0242, 0}; +#undef pci_ss_info_1014_0242 +#define pci_ss_info_1014_0242 pci_ss_info_1069_b166_1014_0242 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0266 = + {0x1014, 0x0266, pci_subsys_1069_b166_1014_0266, 0}; +#undef pci_ss_info_1014_0266 +#define pci_ss_info_1014_0266 pci_ss_info_1069_b166_1014_0266 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0278 = + {0x1014, 0x0278, pci_subsys_1069_b166_1014_0278, 0}; +#undef pci_ss_info_1014_0278 +#define pci_ss_info_1014_0278 pci_ss_info_1069_b166_1014_0278 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d3 = + {0x1014, 0x02d3, pci_subsys_1069_b166_1014_02d3, 0}; +#undef pci_ss_info_1014_02d3 +#define pci_ss_info_1014_02d3 pci_ss_info_1069_b166_1014_02d3 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d4 = + {0x1014, 0x02d4, pci_subsys_1069_b166_1014_02d4, 0}; +#undef pci_ss_info_1014_02d4 +#define pci_ss_info_1014_02d4 pci_ss_info_1069_b166_1014_02d4 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0200 = + {0x1069, 0x0200, pci_subsys_1069_b166_1069_0200, 0}; +#undef pci_ss_info_1069_0200 +#define pci_ss_info_1069_0200 pci_ss_info_1069_b166_1069_0200 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0202 = + {0x1069, 0x0202, pci_subsys_1069_b166_1069_0202, 0}; +#undef pci_ss_info_1069_0202 +#define pci_ss_info_1069_0202 pci_ss_info_1069_b166_1069_0202 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0204 = + {0x1069, 0x0204, pci_subsys_1069_b166_1069_0204, 0}; +#undef pci_ss_info_1069_0204 +#define pci_ss_info_1069_0204 pci_ss_info_1069_b166_1069_0204 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0206 = + {0x1069, 0x0206, pci_subsys_1069_b166_1069_0206, 0}; +#undef pci_ss_info_1069_0206 +#define pci_ss_info_1069_0206 pci_ss_info_1069_b166_1069_0206 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0030 = + {0x1069, 0x0030, pci_subsys_1069_ba56_1069_0030, 0}; +#undef pci_ss_info_1069_0030 +#define pci_ss_info_1069_0030 pci_ss_info_1069_ba56_1069_0030 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0040 = + {0x1069, 0x0040, pci_subsys_1069_ba56_1069_0040, 0}; +#undef pci_ss_info_1069_0040 +#define pci_ss_info_1069_0040 pci_ss_info_1069_ba56_1069_0040 +static const pciSubsystemInfo pci_ss_info_1069_ba57_1069_0072 = + {0x1069, 0x0072, pci_subsys_1069_ba57_1069_0072, 0}; +#undef pci_ss_info_1069_0072 +#define pci_ss_info_1069_0072 pci_ss_info_1069_ba57_1069_0072 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_106b_0031_106b_5811 = + {0x106b, 0x5811, pci_subsys_106b_0031_106b_5811, 0}; +#undef pci_ss_info_106b_5811 +#define pci_ss_info_106b_5811 pci_ss_info_106b_0031_106b_5811 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +static const pciSubsystemInfo pci_ss_info_1077_2200_1077_0002 = + {0x1077, 0x0002, pci_subsys_1077_2200_1077_0002, 0}; +#undef pci_ss_info_1077_0002 +#define pci_ss_info_1077_0002 pci_ss_info_1077_2200_1077_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0648_1043_8025 = + {0x1043, 0x8025, pci_subsys_1095_0648_1043_8025, 0}; +#undef pci_ss_info_1043_8025 +#define pci_ss_info_1043_8025 pci_ss_info_1095_0648_1043_8025 +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +static const pciSubsystemInfo pci_ss_info_1095_0680_1095_3680 = + {0x1095, 0x3680, pci_subsys_1095_0680_1095_3680, 0}; +#undef pci_ss_info_1095_3680 +#define pci_ss_info_1095_3680 pci_ss_info_1095_0680_1095_3680 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_3112 = + {0x1095, 0x3112, pci_subsys_1095_3112_1095_3112, 0}; +#undef pci_ss_info_1095_3112 +#define pci_ss_info_1095_3112 pci_ss_info_1095_3112_1095_3112 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_6112 = + {0x1095, 0x6112, pci_subsys_1095_3112_1095_6112, 0}; +#undef pci_ss_info_1095_6112 +#define pci_ss_info_1095_6112 pci_ss_info_1095_3112_1095_6112 +static const pciSubsystemInfo pci_ss_info_1095_3112_9005_0250 = + {0x9005, 0x0250, pci_subsys_1095_3112_9005_0250, 0}; +#undef pci_ss_info_9005_0250 +#define pci_ss_info_9005_0250 pci_ss_info_1095_3112_9005_0250 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_3114 = + {0x1095, 0x3114, pci_subsys_1095_3114_1095_3114, 0}; +#undef pci_ss_info_1095_3114 +#define pci_ss_info_1095_3114 pci_ss_info_1095_3114_1095_3114 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_6114 = + {0x1095, 0x6114, pci_subsys_1095_3114_1095_6114, 0}; +#undef pci_ss_info_1095_6114 +#define pci_ss_info_1095_6114 pci_ss_info_1095_3114_1095_6114 +static const pciSubsystemInfo pci_ss_info_1095_3124_1095_3124 = + {0x1095, 0x3124, pci_subsys_1095_3124_1095_3124, 0}; +#undef pci_ss_info_1095_3124 +#define pci_ss_info_1095_3124 pci_ss_info_1095_3124_1095_3124 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_3512 = + {0x1095, 0x3512, pci_subsys_1095_3512_1095_3512, 0}; +#undef pci_ss_info_1095_3512 +#define pci_ss_info_1095_3512 pci_ss_info_1095_3512_1095_3512 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_6512 = + {0x1095, 0x6512, pci_subsys_1095_3512_1095_6512, 0}; +#undef pci_ss_info_1095_6512 +#define pci_ss_info_1095_6512 pci_ss_info_1095_3512_1095_6512 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_036e_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_036e_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_036e_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_036e_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0003 = + {0x1461, 0x0003, pci_subsys_109e_036e_1461_0003, 0}; +#undef pci_ss_info_1461_0003 +#define pci_ss_info_1461_0003 pci_ss_info_109e_036e_1461_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_036e_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_036e_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_036e_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_036e_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_036e_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_036e_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_036e_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_036e_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_036e_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_0878_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_0878_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_0878_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_0878_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_0878_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_0878_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_0878_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_0878_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_0878_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_0878_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_0878_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_0878_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_0878_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10a9_0009_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_10a9_0009_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_10a9_0009_10a9_8002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_6540_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6540_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6540_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6541_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6541_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6541_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6542_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6542_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6542_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2862 = + {0x10b5, 0x2862, pci_subsys_10b5_9030_10b5_2862, 0}; +#undef pci_ss_info_10b5_2862 +#define pci_ss_info_10b5_2862 pci_ss_info_10b5_9030_10b5_2862 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2906 = + {0x10b5, 0x2906, pci_subsys_10b5_9030_10b5_2906, 0}; +#undef pci_ss_info_10b5_2906 +#define pci_ss_info_10b5_2906 pci_ss_info_10b5_9030_10b5_2906 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2940 = + {0x10b5, 0x2940, pci_subsys_10b5_9030_10b5_2940, 0}; +#undef pci_ss_info_10b5_2940 +#define pci_ss_info_10b5_2940 pci_ss_info_10b5_9030_10b5_2940 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2977 = + {0x10b5, 0x2977, pci_subsys_10b5_9030_10b5_2977, 0}; +#undef pci_ss_info_10b5_2977 +#define pci_ss_info_10b5_2977 pci_ss_info_10b5_9030_10b5_2977 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2978 = + {0x10b5, 0x2978, pci_subsys_10b5_9030_10b5_2978, 0}; +#undef pci_ss_info_10b5_2978 +#define pci_ss_info_10b5_2978 pci_ss_info_10b5_9030_10b5_2978 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3025 = + {0x10b5, 0x3025, pci_subsys_10b5_9030_10b5_3025, 0}; +#undef pci_ss_info_10b5_3025 +#define pci_ss_info_10b5_3025 pci_ss_info_10b5_9030_10b5_3025 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3068 = + {0x10b5, 0x3068, pci_subsys_10b5_9030_10b5_3068, 0}; +#undef pci_ss_info_10b5_3068 +#define pci_ss_info_10b5_3068 pci_ss_info_10b5_9030_10b5_3068 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3136 = + {0x1397, 0x3136, pci_subsys_10b5_9030_1397_3136, 0}; +#undef pci_ss_info_1397_3136 +#define pci_ss_info_1397_3136 pci_ss_info_10b5_9030_1397_3136 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3137 = + {0x1397, 0x3137, pci_subsys_10b5_9030_1397_3137, 0}; +#undef pci_ss_info_1397_3137 +#define pci_ss_info_1397_3137 pci_ss_info_10b5_9030_1397_3137 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1518_0200 = + {0x1518, 0x0200, pci_subsys_10b5_9030_1518_0200, 0}; +#undef pci_ss_info_1518_0200 +#define pci_ss_info_1518_0200 pci_ss_info_10b5_9030_1518_0200 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1067 = + {0x10b5, 0x1067, pci_subsys_10b5_9050_10b5_1067, 0}; +#undef pci_ss_info_10b5_1067 +#define pci_ss_info_10b5_1067 pci_ss_info_10b5_9050_10b5_1067 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1172 = + {0x10b5, 0x1172, pci_subsys_10b5_9050_10b5_1172, 0}; +#undef pci_ss_info_10b5_1172 +#define pci_ss_info_10b5_1172 pci_ss_info_10b5_9050_10b5_1172 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2221 = + {0x10b5, 0x2221, pci_subsys_10b5_9050_10b5_2221, 0}; +#undef pci_ss_info_10b5_2221 +#define pci_ss_info_10b5_2221 pci_ss_info_10b5_9050_10b5_2221 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2431 = + {0x10b5, 0x2431, pci_subsys_10b5_9050_10b5_2431, 0}; +#undef pci_ss_info_10b5_2431 +#define pci_ss_info_10b5_2431 pci_ss_info_10b5_9050_10b5_2431 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2905 = + {0x10b5, 0x2905, pci_subsys_10b5_9050_10b5_2905, 0}; +#undef pci_ss_info_10b5_2905 +#define pci_ss_info_10b5_2905 pci_ss_info_10b5_9050_10b5_2905 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1498_0362 = + {0x1498, 0x0362, pci_subsys_10b5_9050_1498_0362, 0}; +#undef pci_ss_info_1498_0362 +#define pci_ss_info_1498_0362 pci_ss_info_10b5_9050_1498_0362 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_2036 = + {0x5654, 0x2036, pci_subsys_10b5_9050_5654_2036, 0}; +#undef pci_ss_info_5654_2036 +#define pci_ss_info_5654_2036 pci_ss_info_10b5_9050_5654_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_3132 = + {0x5654, 0x3132, pci_subsys_10b5_9050_5654_3132, 0}; +#undef pci_ss_info_5654_3132 +#define pci_ss_info_5654_3132 pci_ss_info_10b5_9050_5654_3132 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2696 = + {0x10b5, 0x2696, pci_subsys_10b5_9054_10b5_2696, 0}; +#undef pci_ss_info_10b5_2696 +#define pci_ss_info_10b5_2696 pci_ss_info_10b5_9054_10b5_2696 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2717 = + {0x10b5, 0x2717, pci_subsys_10b5_9054_10b5_2717, 0}; +#undef pci_ss_info_10b5_2717 +#define pci_ss_info_10b5_2717 pci_ss_info_10b5_9054_10b5_2717 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2844 = + {0x10b5, 0x2844, pci_subsys_10b5_9054_10b5_2844, 0}; +#undef pci_ss_info_10b5_2844 +#define pci_ss_info_10b5_2844 pci_ss_info_10b5_9054_10b5_2844 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12c7_4001 = + {0x12c7, 0x4001, pci_subsys_10b5_9054_12c7_4001, 0}; +#undef pci_ss_info_12c7_4001 +#define pci_ss_info_12c7_4001 pci_ss_info_10b5_9054_12c7_4001 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9054_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9054_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0011 = + {0x16df, 0x0011, pci_subsys_10b5_9054_16df_0011, 0}; +#undef pci_ss_info_16df_0011 +#define pci_ss_info_16df_0011 pci_ss_info_10b5_9054_16df_0011 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0012 = + {0x16df, 0x0012, pci_subsys_10b5_9054_16df_0012, 0}; +#undef pci_ss_info_16df_0012 +#define pci_ss_info_16df_0012 pci_ss_info_10b5_9054_16df_0012 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0013 = + {0x16df, 0x0013, pci_subsys_10b5_9054_16df_0013, 0}; +#undef pci_ss_info_16df_0013 +#define pci_ss_info_16df_0013 pci_ss_info_10b5_9054_16df_0013 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0014 = + {0x16df, 0x0014, pci_subsys_10b5_9054_16df_0014, 0}; +#undef pci_ss_info_16df_0014 +#define pci_ss_info_16df_0014 pci_ss_info_10b5_9054_16df_0014 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0015 = + {0x16df, 0x0015, pci_subsys_10b5_9054_16df_0015, 0}; +#undef pci_ss_info_16df_0015 +#define pci_ss_info_16df_0015 pci_ss_info_10b5_9054_16df_0015 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0016 = + {0x16df, 0x0016, pci_subsys_10b5_9054_16df_0016, 0}; +#undef pci_ss_info_16df_0016 +#define pci_ss_info_16df_0016 pci_ss_info_10b5_9054_16df_0016 +static const pciSubsystemInfo pci_ss_info_10b5_9056_10b5_2979 = + {0x10b5, 0x2979, pci_subsys_10b5_9056_10b5_2979, 0}; +#undef pci_ss_info_10b5_2979 +#define pci_ss_info_10b5_2979 pci_ss_info_10b5_9056_10b5_2979 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10eb = + {0x103c, 0x10eb, pci_subsys_10b5_9080_103c_10eb, 0}; +#undef pci_ss_info_103c_10eb +#define pci_ss_info_103c_10eb pci_ss_info_10b5_9080_103c_10eb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10ec = + {0x103c, 0x10ec, pci_subsys_10b5_9080_103c_10ec, 0}; +#undef pci_ss_info_103c_10ec +#define pci_ss_info_103c_10ec pci_ss_info_10b5_9080_103c_10ec +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9080_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9080_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12df_4422 = + {0x12df, 0x4422, pci_subsys_10b5_9080_12df_4422, 0}; +#undef pci_ss_info_12df_4422 +#define pci_ss_info_12df_4422 pci_ss_info_10b5_9080_12df_4422 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_0013_10b7_2031 = + {0x10b7, 0x2031, pci_subsys_10b7_0013_10b7_2031, 0}; +#undef pci_ss_info_10b7_2031 +#define pci_ss_info_10b7_2031 pci_ss_info_10b7_0013_10b7_2031 +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_1700_1043_80eb = + {0x1043, 0x80eb, pci_subsys_10b7_1700_1043_80eb, 0}; +#undef pci_ss_info_1043_80eb +#define pci_ss_info_1043_80eb pci_ss_info_10b7_1700_1043_80eb +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0010 = + {0x10b7, 0x0010, pci_subsys_10b7_1700_10b7_0010, 0}; +#undef pci_ss_info_10b7_0010 +#define pci_ss_info_10b7_0010 pci_ss_info_10b7_1700_10b7_0010 +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0020 = + {0x10b7, 0x0020, pci_subsys_10b7_1700_10b7_0020, 0}; +#undef pci_ss_info_10b7_0020 +#define pci_ss_info_10b7_0020 pci_ss_info_10b7_1700_10b7_0020 +static const pciSubsystemInfo pci_ss_info_10b7_1700_147b_1407 = + {0x147b, 0x1407, pci_subsys_10b7_1700_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_10b7_1700_147b_1407 +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9200_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9200_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_00fe = + {0x1028, 0x00fe, pci_subsys_10b7_9200_1028_00fe, 0}; +#undef pci_ss_info_1028_00fe +#define pci_ss_info_1028_00fe pci_ss_info_10b7_9200_1028_00fe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_012a = + {0x1028, 0x012a, pci_subsys_10b7_9200_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_10b7_9200_1028_012a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10f1_2466 = + {0x10f1, 0x2466, pci_subsys_10b7_9200_10f1_2466, 0}; +#undef pci_ss_info_10f1_2466 +#define pci_ss_info_10f1_2466 pci_ss_info_10b7_9200_10f1_2466 +static const pciSubsystemInfo pci_ss_info_10b7_9201_1043_80ab = + {0x1043, 0x80ab, pci_subsys_10b7_9201_1043_80ab, 0}; +#undef pci_ss_info_1043_80ab +#define pci_ss_info_1043_80ab pci_ss_info_10b7_9201_1043_80ab +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_1014_053b = + {0x1014, 0x053b, pci_subsys_10b9_1533_1014_053b, 0}; +#undef pci_ss_info_1014_053b +#define pci_ss_info_1014_053b pci_ss_info_10b9_1533_1014_053b +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_050f = + {0x1014, 0x050f, pci_subsys_10b9_5229_1014_050f, 0}; +#undef pci_ss_info_1014_050f +#define pci_ss_info_1014_050f pci_ss_info_10b9_5229_1014_050f +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_053d = + {0x1014, 0x053d, pci_subsys_10b9_5229_1014_053d, 0}; +#undef pci_ss_info_1014_053d +#define pci_ss_info_1014_053d pci_ss_info_10b9_5229_1014_053d +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5229_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5229_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5229_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5237_1014_0540 = + {0x1014, 0x0540, pci_subsys_10b9_5237_1014_0540, 0}; +#undef pci_ss_info_1014_0540 +#define pci_ss_info_1014_0540 pci_ss_info_10b9_5237_1014_0540 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5237_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5237_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_104d_810f = + {0x104d, 0x810f, pci_subsys_10b9_5237_104d_810f, 0}; +#undef pci_ss_info_104d_810f +#define pci_ss_info_104d_810f pci_ss_info_10b9_5237_104d_810f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_053e = + {0x1014, 0x053e, pci_subsys_10b9_5451_1014_053e, 0}; +#undef pci_ss_info_1014_053e +#define pci_ss_info_1014_053e pci_ss_info_10b9_5451_1014_053e +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5451_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5451_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5451_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_10b9_5451 = + {0x10b9, 0x5451, pci_subsys_10b9_5451_10b9_5451, 0}; +#undef pci_ss_info_10b9_5451 +#define pci_ss_info_10b9_5451 pci_ss_info_10b9_5451_10b9_5451 +static const pciSubsystemInfo pci_ss_info_10b9_5457_1014_0535 = + {0x1014, 0x0535, pci_subsys_10b9_5457_1014_0535, 0}; +#undef pci_ss_info_1014_0535 +#define pci_ss_info_1014_0535 pci_ss_info_10b9_5457_1014_0535 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5457_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5457_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5457_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_0510 = + {0x1014, 0x0510, pci_subsys_10b9_7101_1014_0510, 0}; +#undef pci_ss_info_1014_0510 +#define pci_ss_info_1014_0510 pci_ss_info_10b9_7101_1014_0510 +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_053c = + {0x1014, 0x053c, pci_subsys_10b9_7101_1014_053c, 0}; +#undef pci_ss_info_1014_053c +#define pci_ss_info_1014_053c pci_ss_info_10b9_7101_1014_053c +#endif +static const pciSubsystemInfo pci_ss_info_10b9_7101_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_7101_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_7101_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_0005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_0005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_8005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_8005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c19 = + {0x1048, 0x0c19, pci_subsys_10de_0020_1048_0c19, 0}; +#undef pci_ss_info_1048_0c19 +#define pci_ss_info_1048_0c19 pci_ss_info_10de_0020_1048_0c19 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1c = + {0x1048, 0x0c1c, pci_subsys_10de_0020_1048_0c1c, 0}; +#undef pci_ss_info_1048_0c1c +#define pci_ss_info_1048_0c1c pci_ss_info_10de_0020_1048_0c1c +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_0028_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_0028_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c28 = + {0x1048, 0x0c28, pci_subsys_10de_0028_1048_0c28, 0}; +#undef pci_ss_info_1048_0c28 +#define pci_ss_info_1048_0c28 pci_ss_info_10de_0028_1048_0c28 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c29 = + {0x1048, 0x0c29, pci_subsys_10de_0028_1048_0c29, 0}; +#undef pci_ss_info_1048_0c29 +#define pci_ss_info_1048_0c29 pci_ss_info_10de_0028_1048_0c29 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2a = + {0x1048, 0x0c2a, pci_subsys_10de_0028_1048_0c2a, 0}; +#undef pci_ss_info_1048_0c2a +#define pci_ss_info_1048_0c2a pci_ss_info_10de_0028_1048_0c2a +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2b = + {0x1048, 0x0c2b, pci_subsys_10de_0028_1048_0c2b, 0}; +#undef pci_ss_info_1048_0c2b +#define pci_ss_info_1048_0c2b pci_ss_info_10de_0028_1048_0c2b +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c31 = + {0x1048, 0x0c31, pci_subsys_10de_0028_1048_0c31, 0}; +#undef pci_ss_info_1048_0c31 +#define pci_ss_info_1048_0c31 pci_ss_info_10de_0028_1048_0c31 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c32 = + {0x1048, 0x0c32, pci_subsys_10de_0028_1048_0c32, 0}; +#undef pci_ss_info_1048_0c32 +#define pci_ss_info_1048_0c32 pci_ss_info_10de_0028_1048_0c32 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c33 = + {0x1048, 0x0c33, pci_subsys_10de_0028_1048_0c33, 0}; +#undef pci_ss_info_1048_0c33 +#define pci_ss_info_1048_0c33 pci_ss_info_10de_0028_1048_0c33 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c34 = + {0x1048, 0x0c34, pci_subsys_10de_0028_1048_0c34, 0}; +#undef pci_ss_info_1048_0c34 +#define pci_ss_info_1048_0c34 pci_ss_info_10de_0028_1048_0c34 +static const pciSubsystemInfo pci_ss_info_10de_0028_107d_2134 = + {0x107d, 0x2134, pci_subsys_10de_0028_107d_2134, 0}; +#undef pci_ss_info_107d_2134 +#define pci_ss_info_107d_2134 pci_ss_info_10de_0028_107d_2134 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2e = + {0x1048, 0x0c2e, pci_subsys_10de_0029_1048_0c2e, 0}; +#undef pci_ss_info_1048_0c2e +#define pci_ss_info_1048_0c2e pci_ss_info_10de_0029_1048_0c2e +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2f = + {0x1048, 0x0c2f, pci_subsys_10de_0029_1048_0c2f, 0}; +#undef pci_ss_info_1048_0c2f +#define pci_ss_info_1048_0c2f pci_ss_info_10de_0029_1048_0c2f +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c30 = + {0x1048, 0x0c30, pci_subsys_10de_0029_1048_0c30, 0}; +#undef pci_ss_info_1048_0c30 +#define pci_ss_info_1048_0c30 pci_ss_info_10de_0029_1048_0c30 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c20 = + {0x1048, 0x0c20, pci_subsys_10de_002c_1048_0c20, 0}; +#undef pci_ss_info_1048_0c20 +#define pci_ss_info_1048_0c20 pci_ss_info_10de_002c_1048_0c20 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_002c_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_002c_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3b = + {0x1048, 0x0c3b, pci_subsys_10de_002d_1048_0c3b, 0}; +#undef pci_ss_info_1048_0c3b +#define pci_ss_info_1048_0c3b pci_ss_info_10de_002d_1048_0c3b +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_002d_1569_002d = + {0x1569, 0x002d, pci_subsys_10de_002d_1569_002d, 0}; +#undef pci_ss_info_1569_002d +#define pci_ss_info_1569_002d pci_ss_info_10de_002d_1569_002d +static const pciSubsystemInfo pci_ss_info_10de_0041_1043_817b = + {0x1043, 0x817b, pci_subsys_10de_0041_1043_817b, 0}; +#undef pci_ss_info_1043_817b +#define pci_ss_info_1043_817b pci_ss_info_10de_0041_1043_817b +static const pciSubsystemInfo pci_ss_info_10de_0047_1682_2109 = + {0x1682, 0x2109, pci_subsys_10de_0047_1682_2109, 0}; +#undef pci_ss_info_1682_2109 +#define pci_ss_info_1682_2109 pci_ss_info_10de_0047_1682_2109 +static const pciSubsystemInfo pci_ss_info_10de_0050_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0050_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0050_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0050_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0050_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0050_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0050_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0050_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0050_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0052_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0052_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0052_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0052_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0052_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0052_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0052_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0052_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0052_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0053_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0053_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0053_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0053_1458_5002 = + {0x1458, 0x5002, pci_subsys_10de_0053_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_10de_0053_1458_5002 +static const pciSubsystemInfo pci_ss_info_10de_0053_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0053_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0053_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0054_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0054_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0054_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0055_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0055_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0055_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0057_1043_8141 = + {0x1043, 0x8141, pci_subsys_10de_0057_1043_8141, 0}; +#undef pci_ss_info_1043_8141 +#define pci_ss_info_1043_8141 pci_ss_info_10de_0057_1043_8141 +static const pciSubsystemInfo pci_ss_info_10de_0057_1458_e000 = + {0x1458, 0xe000, pci_subsys_10de_0057_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10de_0057_1458_e000 +static const pciSubsystemInfo pci_ss_info_10de_0057_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0057_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0057_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0059_1043_812a = + {0x1043, 0x812a, pci_subsys_10de_0059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_10de_0059_1043_812a +static const pciSubsystemInfo pci_ss_info_10de_005a_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005a_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005a_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005a_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005a_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005a_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005a_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005a_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005a_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005b_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005b_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005b_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005b_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005b_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005b_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005b_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005b_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005b_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005e_1458_5000 = + {0x1458, 0x5000, pci_subsys_10de_005e_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_10de_005e_1458_5000 +static const pciSubsystemInfo pci_ss_info_10de_005e_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005e_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005e_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0066_1043_80a7 = + {0x1043, 0x80a7, pci_subsys_10de_0066_1043_80a7, 0}; +#undef pci_ss_info_1043_80a7 +#define pci_ss_info_1043_80a7 pci_ss_info_10de_0066_1043_80a7 +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_006b_10de_006b = + {0x10de, 0x006b, pci_subsys_10de_006b_10de_006b, 0}; +#undef pci_ss_info_10de_006b +#define pci_ss_info_10de_006b pci_ss_info_10de_006b_10de_006b +static const pciSubsystemInfo pci_ss_info_10de_0080_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0080_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0080_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0084_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0084_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0084_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0085_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0085_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0085_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0087_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0087_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0087_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0088_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0088_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0088_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_008a_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_008a_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_008a_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_00df_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00df_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00df_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e0_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e0_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e0_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e1_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e1_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e1_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e3_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e3_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e3_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e4_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e4_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e4_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e5_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e5_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e5_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e7_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e7_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e7_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e8_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e8_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e8_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00ea_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00ea_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00ea_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00f1_1043_81a6 = + {0x1043, 0x81a6, pci_subsys_10de_00f1_1043_81a6, 0}; +#undef pci_ss_info_1043_81a6 +#define pci_ss_info_1043_81a6 pci_ss_info_10de_00f1_1043_81a6 +static const pciSubsystemInfo pci_ss_info_10de_00f2_1682_211c = + {0x1682, 0x211c, pci_subsys_10de_00f2_1682_211c, 0}; +#undef pci_ss_info_1682_211c +#define pci_ss_info_1682_211c pci_ss_info_10de_00f2_1682_211c +static const pciSubsystemInfo pci_ss_info_10de_00f9_1682_2120 = + {0x1682, 0x2120, pci_subsys_10de_00f9_1682_2120, 0}; +#undef pci_ss_info_1682_2120 +#define pci_ss_info_1682_2120 pci_ss_info_10de_00f9_1682_2120 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c41 = + {0x1048, 0x0c41, pci_subsys_10de_0100_1048_0c41, 0}; +#undef pci_ss_info_1048_0c41 +#define pci_ss_info_1048_0c41 pci_ss_info_10de_0100_1048_0c41 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c43 = + {0x1048, 0x0c43, pci_subsys_10de_0100_1048_0c43, 0}; +#undef pci_ss_info_1048_0c43 +#define pci_ss_info_1048_0c43 pci_ss_info_10de_0100_1048_0c43 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c48 = + {0x1048, 0x0c48, pci_subsys_10de_0100_1048_0c48, 0}; +#undef pci_ss_info_1048_0c48 +#define pci_ss_info_1048_0c48 pci_ss_info_10de_0100_1048_0c48 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1048_0c42 = + {0x1048, 0x0c42, pci_subsys_10de_0101_1048_0c42, 0}; +#undef pci_ss_info_1048_0c42 +#define pci_ss_info_1048_0c42 pci_ss_info_10de_0101_1048_0c42 +static const pciSubsystemInfo pci_ss_info_10de_0101_107d_2822 = + {0x107d, 0x2822, pci_subsys_10de_0101_107d_2822, 0}; +#undef pci_ss_info_107d_2822 +#define pci_ss_info_107d_2822 pci_ss_info_10de_0101_107d_2822 +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c40 = + {0x1048, 0x0c40, pci_subsys_10de_0103_1048_0c40, 0}; +#undef pci_ss_info_1048_0c40 +#define pci_ss_info_1048_0c40 pci_ss_info_10de_0103_1048_0c40 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c44 = + {0x1048, 0x0c44, pci_subsys_10de_0103_1048_0c44, 0}; +#undef pci_ss_info_1048_0c44 +#define pci_ss_info_1048_0c44 pci_ss_info_10de_0103_1048_0c44 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c45 = + {0x1048, 0x0c45, pci_subsys_10de_0103_1048_0c45, 0}; +#undef pci_ss_info_1048_0c45 +#define pci_ss_info_1048_0c45 pci_ss_info_10de_0103_1048_0c45 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4a = + {0x1048, 0x0c4a, pci_subsys_10de_0103_1048_0c4a, 0}; +#undef pci_ss_info_1048_0c4a +#define pci_ss_info_1048_0c4a pci_ss_info_10de_0103_1048_0c4a +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4b = + {0x1048, 0x0c4b, pci_subsys_10de_0103_1048_0c4b, 0}; +#undef pci_ss_info_1048_0c4b +#define pci_ss_info_1048_0c4b pci_ss_info_10de_0103_1048_0c4b +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c60 = + {0x1048, 0x0c60, pci_subsys_10de_0110_1048_0c60, 0}; +#undef pci_ss_info_1048_0c60 +#define pci_ss_info_1048_0c60 pci_ss_info_10de_0110_1048_0c60 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c61 = + {0x1048, 0x0c61, pci_subsys_10de_0110_1048_0c61, 0}; +#undef pci_ss_info_1048_0c61 +#define pci_ss_info_1048_0c61 pci_ss_info_10de_0110_1048_0c61 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c63 = + {0x1048, 0x0c63, pci_subsys_10de_0110_1048_0c63, 0}; +#undef pci_ss_info_1048_0c63 +#define pci_ss_info_1048_0c63 pci_ss_info_10de_0110_1048_0c63 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c64 = + {0x1048, 0x0c64, pci_subsys_10de_0110_1048_0c64, 0}; +#undef pci_ss_info_1048_0c64 +#define pci_ss_info_1048_0c64 pci_ss_info_10de_0110_1048_0c64 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c65 = + {0x1048, 0x0c65, pci_subsys_10de_0110_1048_0c65, 0}; +#undef pci_ss_info_1048_0c65 +#define pci_ss_info_1048_0c65 pci_ss_info_10de_0110_1048_0c65 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c66 = + {0x1048, 0x0c66, pci_subsys_10de_0110_1048_0c66, 0}; +#undef pci_ss_info_1048_0c66 +#define pci_ss_info_1048_0c66 pci_ss_info_10de_0110_1048_0c66 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_0091 = + {0x10de, 0x0091, pci_subsys_10de_0110_10de_0091, 0}; +#undef pci_ss_info_10de_0091 +#define pci_ss_info_10de_0091 pci_ss_info_10de_0110_10de_0091 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_00a1 = + {0x10de, 0x00a1, pci_subsys_10de_0110_10de_00a1, 0}; +#undef pci_ss_info_10de_00a1 +#define pci_ss_info_10de_00a1 pci_ss_info_10de_0110_10de_00a1 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0141_1458_3124 = + {0x1458, 0x3124, pci_subsys_10de_0141_1458_3124, 0}; +#undef pci_ss_info_1458_3124 +#define pci_ss_info_1458_3124 pci_ss_info_10de_0141_1458_3124 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c50 = + {0x1048, 0x0c50, pci_subsys_10de_0150_1048_0c50, 0}; +#undef pci_ss_info_1048_0c50 +#define pci_ss_info_1048_0c50 pci_ss_info_10de_0150_1048_0c50 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c52 = + {0x1048, 0x0c52, pci_subsys_10de_0150_1048_0c52, 0}; +#undef pci_ss_info_1048_0c52 +#define pci_ss_info_1048_0c52 pci_ss_info_10de_0150_1048_0c52 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2842 = + {0x107d, 0x2842, pci_subsys_10de_0150_107d_2842, 0}; +#undef pci_ss_info_107d_2842 +#define pci_ss_info_107d_2842 pci_ss_info_10de_0150_107d_2842 +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0151_1462_5506 = + {0x1462, 0x5506, pci_subsys_10de_0151_1462_5506, 0}; +#undef pci_ss_info_1462_5506 +#define pci_ss_info_1462_5506 pci_ss_info_10de_0151_1462_5506 +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_10b0_0002 = + {0x10b0, 0x0002, pci_subsys_10de_0171_10b0_0002, 0}; +#undef pci_ss_info_10b0_0002 +#define pci_ss_info_10b0_0002 pci_ss_info_10de_0171_10b0_0002 +static const pciSubsystemInfo pci_ss_info_10de_0171_10de_0008 = + {0x10de, 0x0008, pci_subsys_10de_0171_10de_0008, 0}; +#undef pci_ss_info_10de_0008 +#define pci_ss_info_10de_0008 pci_ss_info_10de_0171_10de_0008 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8852 = + {0x1462, 0x8852, pci_subsys_10de_0171_1462_8852, 0}; +#undef pci_ss_info_1462_8852 +#define pci_ss_info_1462_8852 pci_ss_info_10de_0171_1462_8852 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0176_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_10de_0176_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_10de_0176_4c53_1090 +static const pciSubsystemInfo pci_ss_info_10de_0179_10de_0179 = + {0x10de, 0x0179, pci_subsys_10de_0179_10de_0179, 0}; +#undef pci_ss_info_10de_0179 +#define pci_ss_info_10de_0179 pci_ss_info_10de_0179_10de_0179 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_806f = + {0x1043, 0x806f, pci_subsys_10de_0181_1043_806f, 0}; +#undef pci_ss_info_1043_806f +#define pci_ss_info_1043_806f pci_ss_info_10de_0181_1043_806f +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8880 = + {0x1462, 0x8880, pci_subsys_10de_0181_1462_8880, 0}; +#undef pci_ss_info_1462_8880 +#define pci_ss_info_1462_8880 pci_ss_info_10de_0181_1462_8880 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8900 = + {0x1462, 0x8900, pci_subsys_10de_0181_1462_8900, 0}; +#undef pci_ss_info_1462_8900 +#define pci_ss_info_1462_8900 pci_ss_info_10de_0181_1462_8900 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_9350 = + {0x1462, 0x9350, pci_subsys_10de_0181_1462_9350, 0}; +#undef pci_ss_info_1462_9350 +#define pci_ss_info_1462_9350 pci_ss_info_10de_0181_1462_9350 +static const pciSubsystemInfo pci_ss_info_10de_0181_147b_8f0d = + {0x147b, 0x8f0d, pci_subsys_10de_0181_147b_8f0d, 0}; +#undef pci_ss_info_147b_8f0d +#define pci_ss_info_147b_8f0d pci_ss_info_10de_0181_147b_8f0d +static const pciSubsystemInfo pci_ss_info_10de_01e0_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_01e0_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_01e0_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0200_1048_0c70 = + {0x1048, 0x0c70, pci_subsys_10de_0200_1048_0c70, 0}; +#undef pci_ss_info_1048_0c70 +#define pci_ss_info_1048_0c70 pci_ss_info_10de_0200_1048_0c70 +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0251_1043_8023 = + {0x1043, 0x8023, pci_subsys_10de_0251_1043_8023, 0}; +#undef pci_ss_info_1043_8023 +#define pci_ss_info_1043_8023 pci_ss_info_10de_0251_1043_8023 +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +static const pciSubsystemInfo pci_ss_info_10de_0314_1043_814a = + {0x1043, 0x814a, pci_subsys_10de_0314_1043_814a, 0}; +#undef pci_ss_info_1043_814a +#define pci_ss_info_1043_814a pci_ss_info_10de_0314_1043_814a +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9171 = + {0x1462, 0x9171, pci_subsys_10de_0322_1462_9171, 0}; +#undef pci_ss_info_1462_9171 +#define pci_ss_info_1462_9171 pci_ss_info_10de_0322_1462_9171 +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9360 = + {0x1462, 0x9360, pci_subsys_10de_0322_1462_9360, 0}; +#undef pci_ss_info_1462_9360 +#define pci_ss_info_1462_9360 pci_ss_info_10de_0322_1462_9360 +static const pciSubsystemInfo pci_ss_info_10de_0324_1028_0196 = + {0x1028, 0x0196, pci_subsys_10de_0324_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_10de_0324_1028_0196 +static const pciSubsystemInfo pci_ss_info_10de_0324_1071_8160 = + {0x1071, 0x8160, pci_subsys_10de_0324_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10de_0324_1071_8160 +static const pciSubsystemInfo pci_ss_info_10de_0331_1043_8145 = + {0x1043, 0x8145, pci_subsys_10de_0331_1043_8145, 0}; +#undef pci_ss_info_1043_8145 +#define pci_ss_info_1043_8145 pci_ss_info_10de_0331_1043_8145 +static const pciSubsystemInfo pci_ss_info_10de_0347_103c_006a = + {0x103c, 0x006a, pci_subsys_10de_0347_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10de_0347_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +static const pciSubsystemInfo pci_ss_info_10ec_8139_0357_000a = + {0x0357, 0x000a, pci_subsys_10ec_8139_0357_000a, 0}; +#undef pci_ss_info_0357_000a +#define pci_ss_info_0357_000a pci_ss_info_10ec_8139_0357_000a +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_005a = + {0x1025, 0x005a, pci_subsys_10ec_8139_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_10ec_8139_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_103c_006a = + {0x103c, 0x006a, pci_subsys_10ec_8139_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10ec_8139_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_1043_8109 = + {0x1043, 0x8109, pci_subsys_10ec_8139_1043_8109, 0}; +#undef pci_ss_info_1043_8109 +#define pci_ss_info_1043_8109 pci_ss_info_10ec_8139_1043_8109 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1071_8160 = + {0x1071, 0x8160, pci_subsys_10ec_8139_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10ec_8139_1071_8160 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1113_ec01 = + {0x1113, 0xec01, pci_subsys_10ec_8139_1113_ec01, 0}; +#undef pci_ss_info_1113_ec01 +#define pci_ss_info_1113_ec01 pci_ss_info_10ec_8139_1113_ec01 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8139_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8139_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1462_788c = + {0x1462, 0x788c, pci_subsys_10ec_8139_1462_788c, 0}; +#undef pci_ss_info_1462_788c +#define pci_ss_info_1462_788c pci_ss_info_10ec_8139_1462_788c +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_14cb_0200 = + {0x14cb, 0x0200, pci_subsys_10ec_8139_14cb_0200, 0}; +#undef pci_ss_info_14cb_0200 +#define pci_ss_info_14cb_0200 pci_ss_info_10ec_8139_14cb_0200 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1799_5000 = + {0x1799, 0x5000, pci_subsys_10ec_8139_1799_5000, 0}; +#undef pci_ss_info_1799_5000 +#define pci_ss_info_1799_5000 pci_ss_info_10ec_8139_1799_5000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_9001_1695 = + {0x9001, 0x1695, pci_subsys_10ec_8139_9001_1695, 0}; +#undef pci_ss_info_9001_1695 +#define pci_ss_info_9001_1695 pci_ss_info_10ec_8139_9001_1695 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1259_c107 = + {0x1259, 0xc107, pci_subsys_10ec_8169_1259_c107, 0}; +#undef pci_ss_info_1259_c107 +#define pci_ss_info_1259_c107 pci_ss_info_10ec_8169_1259_c107 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +static const pciSubsystemInfo pci_ss_info_10ec_8169_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8169_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8169_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1462_702c = + {0x1462, 0x702c, pci_subsys_10ec_8169_1462_702c, 0}; +#undef pci_ss_info_1462_702c +#define pci_ss_info_1462_702c pci_ss_info_10ec_8169_1462_702c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_100a = + {0x1102, 0x100a, pci_subsys_1102_0002_1102_100a, 0}; +#undef pci_ss_info_1102_100a +#define pci_ss_info_1102_100a pci_ss_info_1102_0002_1102_100a +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8064 = + {0x1102, 0x8064, pci_subsys_1102_0002_1102_8064, 0}; +#undef pci_ss_info_1102_8064 +#define pci_ss_info_1102_8064 pci_ss_info_1102_0002_1102_8064 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8065 = + {0x1102, 0x8065, pci_subsys_1102_0002_1102_8065, 0}; +#undef pci_ss_info_1102_8065 +#define pci_ss_info_1102_8065 pci_ss_info_1102_0002_1102_8065 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8067 = + {0x1102, 0x8067, pci_subsys_1102_0002_1102_8067, 0}; +#undef pci_ss_info_1102_8067 +#define pci_ss_info_1102_8067 pci_ss_info_1102_0002_1102_8067 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0058 = + {0x1102, 0x0058, pci_subsys_1102_0004_1102_0058, 0}; +#undef pci_ss_info_1102_0058 +#define pci_ss_info_1102_0058 pci_ss_info_1102_0004_1102_0058 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_1007 = + {0x1102, 0x1007, pci_subsys_1102_0004_1102_1007, 0}; +#undef pci_ss_info_1102_1007 +#define pci_ss_info_1102_1007 pci_ss_info_1102_0004_1102_1007 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_2002 = + {0x1102, 0x2002, pci_subsys_1102_0004_1102_2002, 0}; +#undef pci_ss_info_1102_2002 +#define pci_ss_info_1102_2002 pci_ss_info_1102_0004_1102_2002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_0007 = + {0x1102, 0x0007, pci_subsys_1102_0007_1102_0007, 0}; +#undef pci_ss_info_1102_0007 +#define pci_ss_info_1102_0007 pci_ss_info_1102_0007_1102_0007 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_0007_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_0007_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_0007_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_0007_1102_1002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1006 = + {0x1102, 0x1006, pci_subsys_1102_0007_1102_1006, 0}; +#undef pci_ss_info_1102_1006 +#define pci_ss_info_1102_1006 pci_ss_info_1102_0007_1102_1006 +static const pciSubsystemInfo pci_ss_info_1102_0007_1462_1009 = + {0x1462, 0x1009, pci_subsys_1102_0007_1462_1009, 0}; +#undef pci_ss_info_1462_1009 +#define pci_ss_info_1462_1009 pci_ss_info_1102_0007_1462_1009 +static const pciSubsystemInfo pci_ss_info_1102_0008_1102_0008 = + {0x1102, 0x0008, pci_subsys_1102_0008_1102_0008, 0}; +#undef pci_ss_info_1102_0008 +#define pci_ss_info_1102_0008 pci_ss_info_1102_0008_1102_0008 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_7005_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_7005_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_7005_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_7005_1102_1002 +#endif +static const pciSubsystemInfo pci_ss_info_1102_8938_1033_80e5 = + {0x1033, 0x80e5, pci_subsys_1102_8938_1033_80e5, 0}; +#undef pci_ss_info_1033_80e5 +#define pci_ss_info_1033_80e5 pci_ss_info_1102_8938_1033_80e5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_8938_1071_7150 = + {0x1071, 0x7150, pci_subsys_1102_8938_1071_7150, 0}; +#undef pci_ss_info_1071_7150 +#define pci_ss_info_1071_7150 pci_ss_info_1102_8938_1071_7150 +static const pciSubsystemInfo pci_ss_info_1102_8938_110a_5938 = + {0x110a, 0x5938, pci_subsys_1102_8938_110a_5938, 0}; +#undef pci_ss_info_110a_5938 +#define pci_ss_info_110a_5938 pci_ss_info_1102_8938_110a_5938 +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100c = + {0x13bd, 0x100c, pci_subsys_1102_8938_13bd_100c, 0}; +#undef pci_ss_info_13bd_100c +#define pci_ss_info_13bd_100c pci_ss_info_1102_8938_13bd_100c +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100d = + {0x13bd, 0x100d, pci_subsys_1102_8938_13bd_100d, 0}; +#undef pci_ss_info_13bd_100d +#define pci_ss_info_13bd_100d pci_ss_info_1102_8938_13bd_100d +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100e = + {0x13bd, 0x100e, pci_subsys_1102_8938_13bd_100e, 0}; +#undef pci_ss_info_13bd_100e +#define pci_ss_info_13bd_100e pci_ss_info_1102_8938_13bd_100e +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_f6f1 = + {0x13bd, 0xf6f1, pci_subsys_1102_8938_13bd_f6f1, 0}; +#undef pci_ss_info_13bd_f6f1 +#define pci_ss_info_13bd_f6f1 pci_ss_info_1102_8938_13bd_f6f1 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_0e70 = + {0x14ff, 0x0e70, pci_subsys_1102_8938_14ff_0e70, 0}; +#undef pci_ss_info_14ff_0e70 +#define pci_ss_info_14ff_0e70 pci_ss_info_1102_8938_14ff_0e70 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_c401 = + {0x14ff, 0xc401, pci_subsys_1102_8938_14ff_c401, 0}; +#undef pci_ss_info_14ff_c401 +#define pci_ss_info_14ff_c401 pci_ss_info_1102_8938_14ff_c401 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b400 = + {0x156d, 0xb400, pci_subsys_1102_8938_156d_b400, 0}; +#undef pci_ss_info_156d_b400 +#define pci_ss_info_156d_b400 pci_ss_info_1102_8938_156d_b400 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b550 = + {0x156d, 0xb550, pci_subsys_1102_8938_156d_b550, 0}; +#undef pci_ss_info_156d_b550 +#define pci_ss_info_156d_b550 pci_ss_info_1102_8938_156d_b550 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b560 = + {0x156d, 0xb560, pci_subsys_1102_8938_156d_b560, 0}; +#undef pci_ss_info_156d_b560 +#define pci_ss_info_156d_b560 pci_ss_info_1102_8938_156d_b560 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b700 = + {0x156d, 0xb700, pci_subsys_1102_8938_156d_b700, 0}; +#undef pci_ss_info_156d_b700 +#define pci_ss_info_156d_b700 pci_ss_info_1102_8938_156d_b700 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b795 = + {0x156d, 0xb795, pci_subsys_1102_8938_156d_b795, 0}; +#undef pci_ss_info_156d_b795 +#define pci_ss_info_156d_b795 pci_ss_info_1102_8938_156d_b795 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b797 = + {0x156d, 0xb797, pci_subsys_1102_8938_156d_b797, 0}; +#undef pci_ss_info_156d_b797 +#define pci_ss_info_156d_b797 pci_ss_info_1102_8938_156d_b797 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0003 = + {0x1103, 0x0003, pci_subsys_1103_0004_1103_0003, 0}; +#undef pci_ss_info_1103_0003 +#define pci_ss_info_1103_0003 pci_ss_info_1103_0004_1103_0003 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0004 = + {0x1103, 0x0004, pci_subsys_1103_0004_1103_0004, 0}; +#undef pci_ss_info_1103_0004 +#define pci_ss_info_1103_0004 pci_ss_info_1103_0004_1103_0004 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0006 = + {0x1103, 0x0006, pci_subsys_1103_0004_1103_0006, 0}; +#undef pci_ss_info_1103_0006 +#define pci_ss_info_1103_0006 pci_ss_info_1103_0004_1103_0006 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0007 = + {0x1103, 0x0007, pci_subsys_1103_0004_1103_0007, 0}; +#undef pci_ss_info_1103_0007 +#define pci_ss_info_1103_0007 pci_ss_info_1103_0004_1103_0007 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0008 = + {0x1103, 0x0008, pci_subsys_1103_0004_1103_0008, 0}; +#undef pci_ss_info_1103_0008 +#define pci_ss_info_1103_0008 pci_ss_info_1103_0004_1103_0008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1105_8475_1105_0001 = + {0x1105, 0x0001, pci_subsys_1105_8475_1105_0001, 0}; +#undef pci_ss_info_1105_0001 +#define pci_ss_info_1105_0001 pci_ss_info_1105_8475_1105_0001 +static const pciSubsystemInfo pci_ss_info_1105_8476_127d_0000 = + {0x127d, 0x0000, pci_subsys_1105_8476_127d_0000, 0}; +#undef pci_ss_info_127d_0000 +#define pci_ss_info_127d_0000 pci_ss_info_1105_8476_127d_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_0282_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_0282_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_0282_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_0305_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_0305_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_0305_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0571_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0571_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_0571_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_0571_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_0571_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_0571_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_0571_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_0571_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_0571_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_0571_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_0571_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_0571_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0571_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_0571_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_0571_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_0571_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_0571_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_0571_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_0571_1849_0571 = + {0x1849, 0x0571, pci_subsys_1106_0571_1849_0571, 0}; +#undef pci_ss_info_1849_0571 +#define pci_ss_info_1849_0571 pci_ss_info_1106_0571_1849_0571 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0605_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0605_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0605_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0686_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0686_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0686_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0686_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0691_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0691_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3038_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3038_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3038_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3038_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_8080 = + {0x1043, 0x8080, pci_subsys_1106_3038_1043_8080, 0}; +#undef pci_ss_info_1043_8080 +#define pci_ss_info_1043_8080 pci_ss_info_1106_3038_1043_8080 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3038_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3038_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3038_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3038_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3038_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3038_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3038_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3038_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3038_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3038_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3038_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3038_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3038_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3038_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3038_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3038_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3038_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3038_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3038_1849_3038 = + {0x1849, 0x3038, pci_subsys_1106_3038_1849_3038, 0}; +#undef pci_ss_info_1849_3038 +#define pci_ss_info_1849_3038 pci_ss_info_1106_3038_1849_3038 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3044_0574_086c = + {0x0574, 0x086c, pci_subsys_1106_3044_0574_086c, 0}; +#undef pci_ss_info_0574_086c +#define pci_ss_info_0574_086c pci_ss_info_1106_3044_0574_086c +#endif +static const pciSubsystemInfo pci_ss_info_1106_3044_1025_005a = + {0x1025, 0x005a, pci_subsys_1106_3044_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1106_3044_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3044_1043_808a = + {0x1043, 0x808a, pci_subsys_1106_3044_1043_808a, 0}; +#undef pci_ss_info_1043_808a +#define pci_ss_info_1043_808a pci_ss_info_1106_3044_1043_808a +static const pciSubsystemInfo pci_ss_info_1106_3044_1458_1000 = + {0x1458, 0x1000, pci_subsys_1106_3044_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_1106_3044_1458_1000 +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_702d = + {0x1462, 0x702d, pci_subsys_1106_3044_1462_702d, 0}; +#undef pci_ss_info_1462_702d +#define pci_ss_info_1462_702d pci_ss_info_1106_3044_1462_702d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_971d = + {0x1462, 0x971d, pci_subsys_1106_3044_1462_971d, 0}; +#undef pci_ss_info_1462_971d +#define pci_ss_info_1462_971d pci_ss_info_1106_3044_1462_971d +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3057_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3057_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3057_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3057_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_0097 = + {0x0e11, 0x0097, pci_subsys_1106_3058_0e11_0097, 0}; +#undef pci_ss_info_0e11_0097 +#define pci_ss_info_0e11_0097 pci_ss_info_1106_3058_0e11_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3058_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3058_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3058_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3058_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3058_1043_1106 = + {0x1043, 0x1106, pci_subsys_1106_3058_1043_1106, 0}; +#undef pci_ss_info_1043_1106 +#define pci_ss_info_1043_1106 pci_ss_info_1106_3058_1043_1106 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3300 = + {0x1462, 0x3300, pci_subsys_1106_3058_1462_3300, 0}; +#undef pci_ss_info_1462_3300 +#define pci_ss_info_1462_3300 pci_ss_info_1106_3058_1462_3300 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3059_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3059_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_8095 = + {0x1043, 0x8095, pci_subsys_1106_3059_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_1106_3059_1043_8095 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3059_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3059_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80b0 = + {0x1043, 0x80b0, pci_subsys_1106_3059_1043_80b0, 0}; +#undef pci_ss_info_1043_80b0 +#define pci_ss_info_1043_80b0 pci_ss_info_1106_3059_1043_80b0 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_812a = + {0x1043, 0x812a, pci_subsys_1106_3059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_1106_3059_1043_812a +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_3059 = + {0x1106, 0x3059, pci_subsys_1106_3059_1106_3059, 0}; +#undef pci_ss_info_1106_3059 +#define pci_ss_info_1106_3059 pci_ss_info_1106_3059_1106_3059 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4161 = + {0x1106, 0x4161, pci_subsys_1106_3059_1106_4161, 0}; +#undef pci_ss_info_1106_4161 +#define pci_ss_info_1106_4161 pci_ss_info_1106_3059_1106_4161 +static const pciSubsystemInfo pci_ss_info_1106_3059_1297_c160 = + {0x1297, 0xc160, pci_subsys_1106_3059_1297_c160, 0}; +#undef pci_ss_info_1297_c160 +#define pci_ss_info_1297_c160 pci_ss_info_1106_3059_1297_c160 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_0080 = + {0x1462, 0x0080, pci_subsys_1106_3059_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_1106_3059_1462_0080 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_3800 = + {0x1462, 0x3800, pci_subsys_1106_3059_1462_3800, 0}; +#undef pci_ss_info_1462_3800 +#define pci_ss_info_1462_3800 pci_ss_info_1106_3059_1462_3800 +static const pciSubsystemInfo pci_ss_info_1106_3059_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3059_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3059_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3059_1849_9761 = + {0x1849, 0x9761, pci_subsys_1106_3059_1849_9761, 0}; +#undef pci_ss_info_1849_9761 +#define pci_ss_info_1849_9761 pci_ss_info_1106_3059_1849_9761 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3059_4005_4710 = + {0x4005, 0x4710, pci_subsys_1106_3059_4005_4710, 0}; +#undef pci_ss_info_4005_4710 +#define pci_ss_info_4005_4710 pci_ss_info_1106_3059_4005_4710 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3059_4170_1106 = + {0x4170, 0x1106, pci_subsys_1106_3059_4170_1106, 0}; +#undef pci_ss_info_4170_1106 +#define pci_ss_info_4170_1106 pci_ss_info_1106_3059_4170_1106 +static const pciSubsystemInfo pci_ss_info_1106_3059_4552_1106 = + {0x4552, 0x1106, pci_subsys_1106_3059_4552_1106, 0}; +#undef pci_ss_info_4552_1106 +#define pci_ss_info_4552_1106 pci_ss_info_1106_3059_4552_1106 +static const pciSubsystemInfo pci_ss_info_1106_3059_a0a0_01b6 = + {0xa0a0, 0x01b6, pci_subsys_1106_3059_a0a0_01b6, 0}; +#undef pci_ss_info_a0a0_01b6 +#define pci_ss_info_a0a0_01b6 pci_ss_info_1106_3059_a0a0_01b6 +static const pciSubsystemInfo pci_ss_info_1106_3065_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3065_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3065_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3065_13b9_1421 = + {0x13b9, 0x1421, pci_subsys_1106_3065_13b9_1421, 0}; +#undef pci_ss_info_13b9_1421 +#define pci_ss_info_13b9_1421 pci_ss_info_1106_3065_13b9_1421 +static const pciSubsystemInfo pci_ss_info_1106_3065_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_1106_3065_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_1106_3065_147b_1c09 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_3005 = + {0x1695, 0x3005, pci_subsys_1106_3065_1695_3005, 0}; +#undef pci_ss_info_1695_3005 +#define pci_ss_info_1695_3005 pci_ss_info_1106_3065_1695_3005 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_300c = + {0x1695, 0x300c, pci_subsys_1106_3065_1695_300c, 0}; +#undef pci_ss_info_1695_300c +#define pci_ss_info_1695_300c pci_ss_info_1106_3065_1695_300c +static const pciSubsystemInfo pci_ss_info_1106_3065_1849_3065 = + {0x1849, 0x3065, pci_subsys_1106_3065_1849_3065, 0}; +#undef pci_ss_info_1849_3065 +#define pci_ss_info_1849_3065 pci_ss_info_1106_3065_1849_3065 +static const pciSubsystemInfo pci_ss_info_1106_3068_1462_309e = + {0x1462, 0x309e, pci_subsys_1106_3068_1462_309e, 0}; +#undef pci_ss_info_1462_309e +#define pci_ss_info_1462_309e pci_ss_info_1106_3068_1462_309e +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3099_1849_3099 = + {0x1849, 0x3099, pci_subsys_1106_3099_1849_3099, 0}; +#undef pci_ss_info_1849_3099 +#define pci_ss_info_1849_3099 pci_ss_info_1106_3099_1849_3099 +static const pciSubsystemInfo pci_ss_info_1106_3104_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3104_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3104_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3104_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3104_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3104_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3104_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3104_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3104_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3104_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3104_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3104_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3104_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3104_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3104_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3104_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3104_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3104_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3104_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3104_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3104_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3104_1849_3104 = + {0x1849, 0x3104, pci_subsys_1106_3104_1849_3104, 0}; +#undef pci_ss_info_1849_3104 +#define pci_ss_info_1849_3104 pci_ss_info_1106_3104_1849_3104 +static const pciSubsystemInfo pci_ss_info_1106_3106_1186_1403 = + {0x1186, 0x1403, pci_subsys_1106_3106_1186_1403, 0}; +#undef pci_ss_info_1186_1403 +#define pci_ss_info_1186_1403 pci_ss_info_1106_3106_1186_1403 +static const pciSubsystemInfo pci_ss_info_1106_3116_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3116_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3116_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3147_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3147_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3147_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3149_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3149_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3149_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3149_1458_b003 = + {0x1458, 0xb003, pci_subsys_1106_3149_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_1106_3149_1458_b003 +static const pciSubsystemInfo pci_ss_info_1106_3149_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3149_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3149_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3149_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3149_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1408 = + {0x147b, 0x1408, pci_subsys_1106_3149_147b_1408, 0}; +#undef pci_ss_info_147b_1408 +#define pci_ss_info_147b_1408 pci_ss_info_1106_3149_147b_1408 +static const pciSubsystemInfo pci_ss_info_1106_3149_1849_3149 = + {0x1849, 0x3149, pci_subsys_1106_3149_1849_3149, 0}; +#undef pci_ss_info_1849_3149 +#define pci_ss_info_1849_3149 pci_ss_info_1106_3149_1849_3149 +static const pciSubsystemInfo pci_ss_info_1106_3164_1043_80f4 = + {0x1043, 0x80f4, pci_subsys_1106_3164_1043_80f4, 0}; +#undef pci_ss_info_1043_80f4 +#define pci_ss_info_1043_80f4 pci_ss_info_1106_3164_1043_80f4 +static const pciSubsystemInfo pci_ss_info_1106_3164_1462_7028 = + {0x1462, 0x7028, pci_subsys_1106_3164_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_1106_3164_1462_7028 +static const pciSubsystemInfo pci_ss_info_1106_3177_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3177_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3177_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3177_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3177_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3177_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3177_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3177_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3177_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3177_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3177_1849_3177 = + {0x1849, 0x3177, pci_subsys_1106_3177_1849_3177, 0}; +#undef pci_ss_info_1849_3177 +#define pci_ss_info_1849_3177 pci_ss_info_1106_3177_1849_3177 +static const pciSubsystemInfo pci_ss_info_1106_3188_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_3188_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_3188_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_3188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3188_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3189_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3189_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3189_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3189_1849_3189 = + {0x1849, 0x3189, pci_subsys_1106_3189_1849_3189, 0}; +#undef pci_ss_info_1849_3189 +#define pci_ss_info_1849_3189 pci_ss_info_1106_3189_1849_3189 +static const pciSubsystemInfo pci_ss_info_1106_3205_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3205_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3205_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3227_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3227_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3227_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3227_1106_3227 = + {0x1106, 0x3227, pci_subsys_1106_3227_1106_3227, 0}; +#undef pci_ss_info_1106_3227 +#define pci_ss_info_1106_3227 pci_ss_info_1106_3227_1106_3227 +static const pciSubsystemInfo pci_ss_info_1106_3227_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3227_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3227_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3227_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3227_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3227_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3227_1849_3227 = + {0x1849, 0x3227, pci_subsys_1106_3227_1849_3227, 0}; +#undef pci_ss_info_1849_3227 +#define pci_ss_info_1849_3227 pci_ss_info_1106_3227_1849_3227 +static const pciSubsystemInfo pci_ss_info_1106_7205_1458_d000 = + {0x1458, 0xd000, pci_subsys_1106_7205_1458_d000, 0}; +#undef pci_ss_info_1458_d000 +#define pci_ss_info_1458_d000 pci_ss_info_1106_7205_1458_d000 +static const pciSubsystemInfo pci_ss_info_1106_8598_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_8598_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_8598_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_b188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_b188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_b188_147b_1407 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_1113_2242 = + {0x1113, 0x2242, pci_subsys_1113_1216_1113_2242, 0}; +#undef pci_ss_info_1113_2242 +#define pci_ss_info_1113_2242 pci_ss_info_1113_1216_1113_2242 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_5402_1244_0f00 = + {0x1244, 0x0f00, pci_subsys_1131_5402_1244_0f00, 0}; +#undef pci_ss_info_1244_0f00 +#define pci_ss_info_1244_0f00 pci_ss_info_1131_5402_1244_0f00 +#endif +static const pciSubsystemInfo pci_ss_info_1131_7130_102b_48d0 = + {0x102b, 0x48d0, pci_subsys_1131_7130_102b_48d0, 0}; +#undef pci_ss_info_102b_48d0 +#define pci_ss_info_102b_48d0 pci_ss_info_1131_7130_102b_48d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7130_1048_226b = + {0x1048, 0x226b, pci_subsys_1131_7130_1048_226b, 0}; +#undef pci_ss_info_1048_226b +#define pci_ss_info_1048_226b pci_ss_info_1131_7130_1048_226b +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7130_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7130_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2005 = + {0x1131, 0x2005, pci_subsys_1131_7130_1131_2005, 0}; +#undef pci_ss_info_1131_2005 +#define pci_ss_info_1131_2005 pci_ss_info_1131_7130_1131_2005 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_050c = + {0x1461, 0x050c, pci_subsys_1131_7130_1461_050c, 0}; +#undef pci_ss_info_1461_050c +#define pci_ss_info_1461_050c pci_ss_info_1131_7130_1461_050c +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_10ff = + {0x1461, 0x10ff, pci_subsys_1131_7130_1461_10ff, 0}; +#undef pci_ss_info_1461_10ff +#define pci_ss_info_1461_10ff pci_ss_info_1131_7130_1461_10ff +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2108 = + {0x1461, 0x2108, pci_subsys_1131_7130_1461_2108, 0}; +#undef pci_ss_info_1461_2108 +#define pci_ss_info_1461_2108 pci_ss_info_1131_7130_1461_2108 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2115 = + {0x1461, 0x2115, pci_subsys_1131_7130_1461_2115, 0}; +#undef pci_ss_info_1461_2115 +#define pci_ss_info_1461_2115 pci_ss_info_1131_7130_1461_2115 +static const pciSubsystemInfo pci_ss_info_1131_7130_153b_1152 = + {0x153b, 0x1152, pci_subsys_1131_7130_153b_1152, 0}; +#undef pci_ss_info_153b_1152 +#define pci_ss_info_153b_1152 pci_ss_info_1131_7130_153b_1152 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7130_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7130_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c901 = + {0x185b, 0xc901, pci_subsys_1131_7130_185b_c901, 0}; +#undef pci_ss_info_185b_c901 +#define pci_ss_info_185b_c901 pci_ss_info_1131_7130_185b_c901 +static const pciSubsystemInfo pci_ss_info_1131_7130_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7130_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7130_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_0000_4091 = + {0x0000, 0x4091, pci_subsys_1131_7133_0000_4091, 0}; +#undef pci_ss_info_0000_4091 +#define pci_ss_info_0000_4091 pci_ss_info_1131_7133_0000_4091 +static const pciSubsystemInfo pci_ss_info_1131_7133_002b_11bd = + {0x002b, 0x11bd, pci_subsys_1131_7133_002b_11bd, 0}; +#undef pci_ss_info_002b_11bd +#define pci_ss_info_002b_11bd pci_ss_info_1131_7133_002b_11bd +static const pciSubsystemInfo pci_ss_info_1131_7133_1019_4cb5 = + {0x1019, 0x4cb5, pci_subsys_1131_7133_1019_4cb5, 0}; +#undef pci_ss_info_1019_4cb5 +#define pci_ss_info_1019_4cb5 pci_ss_info_1131_7133_1019_4cb5 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7133_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7133_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4843 = + {0x1043, 0x4843, pci_subsys_1131_7133_1043_4843, 0}; +#undef pci_ss_info_1043_4843 +#define pci_ss_info_1043_4843 pci_ss_info_1131_7133_1043_4843 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4845 = + {0x1043, 0x4845, pci_subsys_1131_7133_1043_4845, 0}; +#undef pci_ss_info_1043_4845 +#define pci_ss_info_1043_4845 pci_ss_info_1131_7133_1043_4845 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4862 = + {0x1043, 0x4862, pci_subsys_1131_7133_1043_4862, 0}; +#undef pci_ss_info_1043_4862 +#define pci_ss_info_1043_4862 pci_ss_info_1131_7133_1043_4862 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7133_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7133_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2018 = + {0x1131, 0x2018, pci_subsys_1131_7133_1131_2018, 0}; +#undef pci_ss_info_1131_2018 +#define pci_ss_info_1131_2018 pci_ss_info_1131_7133_1131_2018 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_4ee9 = + {0x1131, 0x4ee9, pci_subsys_1131_7133_1131_4ee9, 0}; +#undef pci_ss_info_1131_4ee9 +#define pci_ss_info_1131_4ee9 pci_ss_info_1131_7133_1131_4ee9 +static const pciSubsystemInfo pci_ss_info_1131_7133_11bd_002e = + {0x11bd, 0x002e, pci_subsys_1131_7133_11bd_002e, 0}; +#undef pci_ss_info_11bd_002e +#define pci_ss_info_11bd_002e pci_ss_info_1131_7133_11bd_002e +static const pciSubsystemInfo pci_ss_info_1131_7133_12ab_0800 = + {0x12ab, 0x0800, pci_subsys_1131_7133_12ab_0800, 0}; +#undef pci_ss_info_12ab_0800 +#define pci_ss_info_12ab_0800 pci_ss_info_1131_7133_12ab_0800 +static const pciSubsystemInfo pci_ss_info_1131_7133_1421_1370 = + {0x1421, 0x1370, pci_subsys_1131_7133_1421_1370, 0}; +#undef pci_ss_info_1421_1370 +#define pci_ss_info_1421_1370 pci_ss_info_1131_7133_1421_1370 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7330 = + {0x1435, 0x7330, pci_subsys_1131_7133_1435_7330, 0}; +#undef pci_ss_info_1435_7330 +#define pci_ss_info_1435_7330 pci_ss_info_1131_7133_1435_7330 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7350 = + {0x1435, 0x7350, pci_subsys_1131_7133_1435_7350, 0}; +#undef pci_ss_info_1435_7350 +#define pci_ss_info_1435_7350 pci_ss_info_1131_7133_1435_7350 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_1044 = + {0x1461, 0x1044, pci_subsys_1131_7133_1461_1044, 0}; +#undef pci_ss_info_1461_1044 +#define pci_ss_info_1461_1044 pci_ss_info_1131_7133_1461_1044 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_f31f = + {0x1461, 0xf31f, pci_subsys_1131_7133_1461_f31f, 0}; +#undef pci_ss_info_1461_f31f +#define pci_ss_info_1461_f31f pci_ss_info_1131_7133_1461_f31f +static const pciSubsystemInfo pci_ss_info_1131_7133_1462_6231 = + {0x1462, 0x6231, pci_subsys_1131_7133_1462_6231, 0}; +#undef pci_ss_info_1462_6231 +#define pci_ss_info_1462_6231 pci_ss_info_1131_7133_1462_6231 +static const pciSubsystemInfo pci_ss_info_1131_7133_1489_0214 = + {0x1489, 0x0214, pci_subsys_1131_7133_1489_0214, 0}; +#undef pci_ss_info_1489_0214 +#define pci_ss_info_1489_0214 pci_ss_info_1131_7133_1489_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_14c0_1212 = + {0x14c0, 0x1212, pci_subsys_1131_7133_14c0_1212, 0}; +#undef pci_ss_info_14c0_1212 +#define pci_ss_info_14c0_1212 pci_ss_info_1131_7133_14c0_1212 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1160 = + {0x153b, 0x1160, pci_subsys_1131_7133_153b_1160, 0}; +#undef pci_ss_info_153b_1160 +#define pci_ss_info_153b_1160 pci_ss_info_1131_7133_153b_1160 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1162 = + {0x153b, 0x1162, pci_subsys_1131_7133_153b_1162, 0}; +#undef pci_ss_info_153b_1162 +#define pci_ss_info_153b_1162 pci_ss_info_1131_7133_153b_1162 +static const pciSubsystemInfo pci_ss_info_1131_7133_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7133_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7133_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7133_4e42_0212 = + {0x4e42, 0x0212, pci_subsys_1131_7133_4e42_0212, 0}; +#undef pci_ss_info_4e42_0212 +#define pci_ss_info_4e42_0212 pci_ss_info_1131_7133_4e42_0212 +static const pciSubsystemInfo pci_ss_info_1131_7133_4e42_0502 = + {0x4e42, 0x0502, pci_subsys_1131_7133_4e42_0502, 0}; +#undef pci_ss_info_4e42_0502 +#define pci_ss_info_4e42_0502 pci_ss_info_1131_7133_4e42_0502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0306 = + {0x5168, 0x0306, pci_subsys_1131_7133_5168_0306, 0}; +#undef pci_ss_info_5168_0306 +#define pci_ss_info_5168_0306 pci_ss_info_1131_7133_5168_0306 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0319 = + {0x5168, 0x0319, pci_subsys_1131_7133_5168_0319, 0}; +#undef pci_ss_info_5168_0319 +#define pci_ss_info_5168_0319 pci_ss_info_1131_7133_5168_0319 +static const pciSubsystemInfo pci_ss_info_1131_7133_5456_7135 = + {0x5456, 0x7135, pci_subsys_1131_7133_5456_7135, 0}; +#undef pci_ss_info_5456_7135 +#define pci_ss_info_5456_7135 pci_ss_info_1131_7133_5456_7135 +static const pciSubsystemInfo pci_ss_info_1131_7134_1019_4cb4 = + {0x1019, 0x4cb4, pci_subsys_1131_7134_1019_4cb4, 0}; +#undef pci_ss_info_1019_4cb4 +#define pci_ss_info_1019_4cb4 pci_ss_info_1131_7134_1019_4cb4 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7134_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7134_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4840 = + {0x1043, 0x4840, pci_subsys_1131_7134_1043_4840, 0}; +#undef pci_ss_info_1043_4840 +#define pci_ss_info_1043_4840 pci_ss_info_1131_7134_1043_4840 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_2004 = + {0x1131, 0x2004, pci_subsys_1131_7134_1131_2004, 0}; +#undef pci_ss_info_1131_2004 +#define pci_ss_info_1131_2004 pci_ss_info_1131_7134_1131_2004 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_4e85 = + {0x1131, 0x4e85, pci_subsys_1131_7134_1131_4e85, 0}; +#undef pci_ss_info_1131_4e85 +#define pci_ss_info_1131_4e85 pci_ss_info_1131_7134_1131_4e85 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_6752 = + {0x1131, 0x6752, pci_subsys_1131_7134_1131_6752, 0}; +#undef pci_ss_info_1131_6752 +#define pci_ss_info_1131_6752 pci_ss_info_1131_7134_1131_6752 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_7133 = + {0x1131, 0x7133, pci_subsys_1131_7134_1131_7133, 0}; +#undef pci_ss_info_1131_7133 +#define pci_ss_info_1131_7133 pci_ss_info_1131_7134_1131_7133 +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7134_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7134_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002d = + {0x11bd, 0x002d, pci_subsys_1131_7134_11bd_002d, 0}; +#undef pci_ss_info_11bd_002d +#define pci_ss_info_11bd_002d pci_ss_info_1131_7134_11bd_002d +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_9715 = + {0x1461, 0x9715, pci_subsys_1131_7134_1461_9715, 0}; +#undef pci_ss_info_1461_9715 +#define pci_ss_info_1461_9715 pci_ss_info_1131_7134_1461_9715 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70a = + {0x1461, 0xa70a, pci_subsys_1131_7134_1461_a70a, 0}; +#undef pci_ss_info_1461_a70a +#define pci_ss_info_1461_a70a pci_ss_info_1131_7134_1461_a70a +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70b = + {0x1461, 0xa70b, pci_subsys_1131_7134_1461_a70b, 0}; +#undef pci_ss_info_1461_a70b +#define pci_ss_info_1461_a70b pci_ss_info_1131_7134_1461_a70b +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_d6ee = + {0x1461, 0xd6ee, pci_subsys_1131_7134_1461_d6ee, 0}; +#undef pci_ss_info_1461_d6ee +#define pci_ss_info_1461_d6ee pci_ss_info_1131_7134_1461_d6ee +static const pciSubsystemInfo pci_ss_info_1131_7134_1471_b7e9 = + {0x1471, 0xb7e9, pci_subsys_1131_7134_1471_b7e9, 0}; +#undef pci_ss_info_1471_b7e9 +#define pci_ss_info_1471_b7e9 pci_ss_info_1131_7134_1471_b7e9 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1142 = + {0x153b, 0x1142, pci_subsys_1131_7134_153b_1142, 0}; +#undef pci_ss_info_153b_1142 +#define pci_ss_info_153b_1142 pci_ss_info_1131_7134_153b_1142 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1143 = + {0x153b, 0x1143, pci_subsys_1131_7134_153b_1143, 0}; +#undef pci_ss_info_153b_1143 +#define pci_ss_info_153b_1143 pci_ss_info_1131_7134_153b_1143 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1158 = + {0x153b, 0x1158, pci_subsys_1131_7134_153b_1158, 0}; +#undef pci_ss_info_153b_1158 +#define pci_ss_info_153b_1158 pci_ss_info_1131_7134_153b_1158 +static const pciSubsystemInfo pci_ss_info_1131_7134_1540_9524 = + {0x1540, 0x9524, pci_subsys_1131_7134_1540_9524, 0}; +#undef pci_ss_info_1540_9524 +#define pci_ss_info_1540_9524 pci_ss_info_1131_7134_1540_9524 +static const pciSubsystemInfo pci_ss_info_1131_7134_16be_0003 = + {0x16be, 0x0003, pci_subsys_1131_7134_16be_0003, 0}; +#undef pci_ss_info_16be_0003 +#define pci_ss_info_16be_0003 pci_ss_info_1131_7134_16be_0003 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c200 = + {0x185b, 0xc200, pci_subsys_1131_7134_185b_c200, 0}; +#undef pci_ss_info_185b_c200 +#define pci_ss_info_185b_c200 pci_ss_info_1131_7134_185b_c200 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c900 = + {0x185b, 0xc900, pci_subsys_1131_7134_185b_c900, 0}; +#undef pci_ss_info_185b_c900 +#define pci_ss_info_185b_c900 pci_ss_info_1131_7134_185b_c900 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_a006 = + {0x1894, 0xa006, pci_subsys_1131_7134_1894_a006, 0}; +#undef pci_ss_info_1894_a006 +#define pci_ss_info_1894_a006 pci_ss_info_1131_7134_1894_a006 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_fe01 = + {0x1894, 0xfe01, pci_subsys_1131_7134_1894_fe01, 0}; +#undef pci_ss_info_1894_fe01 +#define pci_ss_info_1894_fe01 pci_ss_info_1131_7134_1894_fe01 +static const pciSubsystemInfo pci_ss_info_1131_7134_4e42_0138 = + {0x4e42, 0x0138, pci_subsys_1131_7134_4e42_0138, 0}; +#undef pci_ss_info_4e42_0138 +#define pci_ss_info_4e42_0138 pci_ss_info_1131_7134_4e42_0138 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_0000 = + {0x110a, 0x0000, pci_subsys_1131_7146_110a_0000, 0}; +#undef pci_ss_info_110a_0000 +#define pci_ss_info_110a_0000 pci_ss_info_1131_7146_110a_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_ffff = + {0x110a, 0xffff, pci_subsys_1131_7146_110a_ffff, 0}; +#undef pci_ss_info_110a_ffff +#define pci_ss_info_110a_ffff pci_ss_info_1131_7146_110a_ffff +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f56 = + {0x1131, 0x4f56, pci_subsys_1131_7146_1131_4f56, 0}; +#undef pci_ss_info_1131_4f56 +#define pci_ss_info_1131_4f56 pci_ss_info_1131_7146_1131_4f56 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f60 = + {0x1131, 0x4f60, pci_subsys_1131_7146_1131_4f60, 0}; +#undef pci_ss_info_1131_4f60 +#define pci_ss_info_1131_4f60 pci_ss_info_1131_7146_1131_4f60 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f61 = + {0x1131, 0x4f61, pci_subsys_1131_7146_1131_4f61, 0}; +#undef pci_ss_info_1131_4f61 +#define pci_ss_info_1131_4f61 pci_ss_info_1131_7146_1131_4f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_5f61 = + {0x1131, 0x5f61, pci_subsys_1131_7146_1131_5f61, 0}; +#undef pci_ss_info_1131_5f61 +#define pci_ss_info_1131_5f61 pci_ss_info_1131_7146_1131_5f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000f = + {0x11bd, 0x000f, pci_subsys_1131_7146_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_1131_7146_11bd_000f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_1131_7146_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_1131_7146_13c2_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0001 = + {0x13c2, 0x0001, pci_subsys_1131_7146_13c2_0001, 0}; +#undef pci_ss_info_13c2_0001 +#define pci_ss_info_13c2_0001 pci_ss_info_1131_7146_13c2_0001 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0002 = + {0x13c2, 0x0002, pci_subsys_1131_7146_13c2_0002, 0}; +#undef pci_ss_info_13c2_0002 +#define pci_ss_info_13c2_0002 pci_ss_info_1131_7146_13c2_0002 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0003 = + {0x13c2, 0x0003, pci_subsys_1131_7146_13c2_0003, 0}; +#undef pci_ss_info_13c2_0003 +#define pci_ss_info_13c2_0003 pci_ss_info_1131_7146_13c2_0003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0004 = + {0x13c2, 0x0004, pci_subsys_1131_7146_13c2_0004, 0}; +#undef pci_ss_info_13c2_0004 +#define pci_ss_info_13c2_0004 pci_ss_info_1131_7146_13c2_0004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0006 = + {0x13c2, 0x0006, pci_subsys_1131_7146_13c2_0006, 0}; +#undef pci_ss_info_13c2_0006 +#define pci_ss_info_13c2_0006 pci_ss_info_1131_7146_13c2_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0008 = + {0x13c2, 0x0008, pci_subsys_1131_7146_13c2_0008, 0}; +#undef pci_ss_info_13c2_0008 +#define pci_ss_info_13c2_0008 pci_ss_info_1131_7146_13c2_0008 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_000a = + {0x13c2, 0x000a, pci_subsys_1131_7146_13c2_000a, 0}; +#undef pci_ss_info_13c2_000a +#define pci_ss_info_13c2_000a pci_ss_info_1131_7146_13c2_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1003 = + {0x13c2, 0x1003, pci_subsys_1131_7146_13c2_1003, 0}; +#undef pci_ss_info_13c2_1003 +#define pci_ss_info_13c2_1003 pci_ss_info_1131_7146_13c2_1003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1004 = + {0x13c2, 0x1004, pci_subsys_1131_7146_13c2_1004, 0}; +#undef pci_ss_info_13c2_1004 +#define pci_ss_info_13c2_1004 pci_ss_info_1131_7146_13c2_1004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1005 = + {0x13c2, 0x1005, pci_subsys_1131_7146_13c2_1005, 0}; +#undef pci_ss_info_13c2_1005 +#define pci_ss_info_13c2_1005 pci_ss_info_1131_7146_13c2_1005 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100c = + {0x13c2, 0x100c, pci_subsys_1131_7146_13c2_100c, 0}; +#undef pci_ss_info_13c2_100c +#define pci_ss_info_13c2_100c pci_ss_info_1131_7146_13c2_100c +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100f = + {0x13c2, 0x100f, pci_subsys_1131_7146_13c2_100f, 0}; +#undef pci_ss_info_13c2_100f +#define pci_ss_info_13c2_100f pci_ss_info_1131_7146_13c2_100f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1011 = + {0x13c2, 0x1011, pci_subsys_1131_7146_13c2_1011, 0}; +#undef pci_ss_info_13c2_1011 +#define pci_ss_info_13c2_1011 pci_ss_info_1131_7146_13c2_1011 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1013 = + {0x13c2, 0x1013, pci_subsys_1131_7146_13c2_1013, 0}; +#undef pci_ss_info_13c2_1013 +#define pci_ss_info_13c2_1013 pci_ss_info_1131_7146_13c2_1013 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1016 = + {0x13c2, 0x1016, pci_subsys_1131_7146_13c2_1016, 0}; +#undef pci_ss_info_13c2_1016 +#define pci_ss_info_13c2_1016 pci_ss_info_1131_7146_13c2_1016 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1102 = + {0x13c2, 0x1102, pci_subsys_1131_7146_13c2_1102, 0}; +#undef pci_ss_info_13c2_1102 +#define pci_ss_info_13c2_1102 pci_ss_info_1131_7146_13c2_1102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e010_110a_0021 = + {0x110a, 0x0021, pci_subsys_1133_e010_110a_0021, 0}; +#undef pci_ss_info_110a_0021 +#define pci_ss_info_110a_0021 pci_ss_info_1133_e010_110a_0021 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_1300 = + {0x1133, 0x1300, pci_subsys_1133_e013_1133_1300, 0}; +#undef pci_ss_info_1133_1300 +#define pci_ss_info_1133_1300 pci_ss_info_1133_e013_1133_1300 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_e013 = + {0x1133, 0xe013, pci_subsys_1133_e013_1133_e013, 0}; +#undef pci_ss_info_1133_e013 +#define pci_ss_info_1133_e013 pci_ss_info_1133_e013_1133_e013 +static const pciSubsystemInfo pci_ss_info_1133_e015_1133_e015 = + {0x1133, 0xe015, pci_subsys_1133_e015_1133_e015, 0}; +#undef pci_ss_info_1133_e015 +#define pci_ss_info_1133_e015 pci_ss_info_1133_e015_1133_e015 +static const pciSubsystemInfo pci_ss_info_1133_e017_1133_e017 = + {0x1133, 0xe017, pci_subsys_1133_e017_1133_e017, 0}; +#undef pci_ss_info_1133_e017 +#define pci_ss_info_1133_e017 pci_ss_info_1133_e017_1133_e017 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_1800 = + {0x1133, 0x1800, pci_subsys_1133_e018_1133_1800, 0}; +#undef pci_ss_info_1133_1800 +#define pci_ss_info_1133_1800 pci_ss_info_1133_e018_1133_1800 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_e018 = + {0x1133, 0xe018, pci_subsys_1133_e018_1133_e018, 0}; +#undef pci_ss_info_1133_e018 +#define pci_ss_info_1133_e018 pci_ss_info_1133_e018_1133_e018 +static const pciSubsystemInfo pci_ss_info_1133_e019_1133_e019 = + {0x1133, 0xe019, pci_subsys_1133_e019_1133_e019, 0}; +#undef pci_ss_info_1133_e019 +#define pci_ss_info_1133_e019 pci_ss_info_1133_e019_1133_e019 +static const pciSubsystemInfo pci_ss_info_1133_e01b_1133_e01b = + {0x1133, 0xe01b, pci_subsys_1133_e01b_1133_e01b, 0}; +#undef pci_ss_info_1133_e01b +#define pci_ss_info_1133_e01b pci_ss_info_1133_e01b_1133_e01b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c01 = + {0x1133, 0x1c01, pci_subsys_1133_e01c_1133_1c01, 0}; +#undef pci_ss_info_1133_1c01 +#define pci_ss_info_1133_1c01 pci_ss_info_1133_e01c_1133_1c01 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c02 = + {0x1133, 0x1c02, pci_subsys_1133_e01c_1133_1c02, 0}; +#undef pci_ss_info_1133_1c02 +#define pci_ss_info_1133_1c02 pci_ss_info_1133_e01c_1133_1c02 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c03 = + {0x1133, 0x1c03, pci_subsys_1133_e01c_1133_1c03, 0}; +#undef pci_ss_info_1133_1c03 +#define pci_ss_info_1133_1c03 pci_ss_info_1133_e01c_1133_1c03 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c04 = + {0x1133, 0x1c04, pci_subsys_1133_e01c_1133_1c04, 0}; +#undef pci_ss_info_1133_1c04 +#define pci_ss_info_1133_1c04 pci_ss_info_1133_e01c_1133_1c04 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c05 = + {0x1133, 0x1c05, pci_subsys_1133_e01c_1133_1c05, 0}; +#undef pci_ss_info_1133_1c05 +#define pci_ss_info_1133_1c05 pci_ss_info_1133_e01c_1133_1c05 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c06 = + {0x1133, 0x1c06, pci_subsys_1133_e01c_1133_1c06, 0}; +#undef pci_ss_info_1133_1c06 +#define pci_ss_info_1133_1c06 pci_ss_info_1133_e01c_1133_1c06 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c07 = + {0x1133, 0x1c07, pci_subsys_1133_e01c_1133_1c07, 0}; +#undef pci_ss_info_1133_1c07 +#define pci_ss_info_1133_1c07 pci_ss_info_1133_e01c_1133_1c07 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c08 = + {0x1133, 0x1c08, pci_subsys_1133_e01c_1133_1c08, 0}; +#undef pci_ss_info_1133_1c08 +#define pci_ss_info_1133_1c08 pci_ss_info_1133_e01c_1133_1c08 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c09 = + {0x1133, 0x1c09, pci_subsys_1133_e01c_1133_1c09, 0}; +#undef pci_ss_info_1133_1c09 +#define pci_ss_info_1133_1c09 pci_ss_info_1133_e01c_1133_1c09 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0a = + {0x1133, 0x1c0a, pci_subsys_1133_e01c_1133_1c0a, 0}; +#undef pci_ss_info_1133_1c0a +#define pci_ss_info_1133_1c0a pci_ss_info_1133_e01c_1133_1c0a +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0b = + {0x1133, 0x1c0b, pci_subsys_1133_e01c_1133_1c0b, 0}; +#undef pci_ss_info_1133_1c0b +#define pci_ss_info_1133_1c0b pci_ss_info_1133_e01c_1133_1c0b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0c = + {0x1133, 0x1c0c, pci_subsys_1133_e01c_1133_1c0c, 0}; +#undef pci_ss_info_1133_1c0c +#define pci_ss_info_1133_1c0c pci_ss_info_1133_e01c_1133_1c0c +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_2400 = + {0x1133, 0x2400, pci_subsys_1133_e024_1133_2400, 0}; +#undef pci_ss_info_1133_2400 +#define pci_ss_info_1133_2400 pci_ss_info_1133_e024_1133_2400 +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_e024 = + {0x1133, 0xe024, pci_subsys_1133_e024_1133_e024, 0}; +#undef pci_ss_info_1133_e024 +#define pci_ss_info_1133_e024 pci_ss_info_1133_e024_1133_e024 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_2800 = + {0x1133, 0x2800, pci_subsys_1133_e028_1133_2800, 0}; +#undef pci_ss_info_1133_2800 +#define pci_ss_info_1133_2800 pci_ss_info_1133_e028_1133_2800 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_e028 = + {0x1133, 0xe028, pci_subsys_1133_e028_1133_e028, 0}; +#undef pci_ss_info_1133_e028 +#define pci_ss_info_1133_e028 pci_ss_info_1133_e028_1133_e028 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2971 = + {0x1259, 0x2971, pci_subsys_1148_4300_1259_2971, 0}; +#undef pci_ss_info_1259_2971 +#define pci_ss_info_1259_2971 pci_ss_info_1148_4300_1259_2971 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2973 = + {0x1259, 0x2973, pci_subsys_1148_4300_1259_2973, 0}; +#undef pci_ss_info_1259_2973 +#define pci_ss_info_1259_2973 pci_ss_info_1148_4300_1259_2973 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2974 = + {0x1259, 0x2974, pci_subsys_1148_4300_1259_2974, 0}; +#undef pci_ss_info_1259_2974 +#define pci_ss_info_1259_2974 pci_ss_info_1148_4300_1259_2974 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2976 = + {0x1259, 0x2976, pci_subsys_1148_4300_1259_2976, 0}; +#undef pci_ss_info_1259_2976 +#define pci_ss_info_1259_2976 pci_ss_info_1148_4300_1259_2976 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0121 = + {0x1148, 0x0121, pci_subsys_1148_4320_1148_0121, 0}; +#undef pci_ss_info_1148_0121 +#define pci_ss_info_1148_0121 pci_ss_info_1148_4320_1148_0121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0221 = + {0x1148, 0x0221, pci_subsys_1148_4320_1148_0221, 0}; +#undef pci_ss_info_1148_0221 +#define pci_ss_info_1148_0221 pci_ss_info_1148_4320_1148_0221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0321 = + {0x1148, 0x0321, pci_subsys_1148_4320_1148_0321, 0}; +#undef pci_ss_info_1148_0321 +#define pci_ss_info_1148_0321 pci_ss_info_1148_4320_1148_0321 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0421 = + {0x1148, 0x0421, pci_subsys_1148_4320_1148_0421, 0}; +#undef pci_ss_info_1148_0421 +#define pci_ss_info_1148_0421 pci_ss_info_1148_4320_1148_0421 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0621 = + {0x1148, 0x0621, pci_subsys_1148_4320_1148_0621, 0}; +#undef pci_ss_info_1148_0621 +#define pci_ss_info_1148_0621 pci_ss_info_1148_4320_1148_0621 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0721 = + {0x1148, 0x0721, pci_subsys_1148_4320_1148_0721, 0}; +#undef pci_ss_info_1148_0721 +#define pci_ss_info_1148_0721 pci_ss_info_1148_4320_1148_0721 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0821 = + {0x1148, 0x0821, pci_subsys_1148_4320_1148_0821, 0}; +#undef pci_ss_info_1148_0821 +#define pci_ss_info_1148_0821 pci_ss_info_1148_4320_1148_0821 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0921 = + {0x1148, 0x0921, pci_subsys_1148_4320_1148_0921, 0}; +#undef pci_ss_info_1148_0921 +#define pci_ss_info_1148_0921 pci_ss_info_1148_4320_1148_0921 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1121 = + {0x1148, 0x1121, pci_subsys_1148_4320_1148_1121, 0}; +#undef pci_ss_info_1148_1121 +#define pci_ss_info_1148_1121 pci_ss_info_1148_4320_1148_1121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1221 = + {0x1148, 0x1221, pci_subsys_1148_4320_1148_1221, 0}; +#undef pci_ss_info_1148_1221 +#define pci_ss_info_1148_1221 pci_ss_info_1148_4320_1148_1221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_3221 = + {0x1148, 0x3221, pci_subsys_1148_4320_1148_3221, 0}; +#undef pci_ss_info_1148_3221 +#define pci_ss_info_1148_3221 pci_ss_info_1148_4320_1148_3221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2100 = + {0x1148, 0x2100, pci_subsys_1148_9e00_1148_2100, 0}; +#undef pci_ss_info_1148_2100 +#define pci_ss_info_1148_2100 pci_ss_info_1148_9e00_1148_2100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_21d0 = + {0x1148, 0x21d0, pci_subsys_1148_9e00_1148_21d0, 0}; +#undef pci_ss_info_1148_21d0 +#define pci_ss_info_1148_21d0 pci_ss_info_1148_9e00_1148_21d0 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2200 = + {0x1148, 0x2200, pci_subsys_1148_9e00_1148_2200, 0}; +#undef pci_ss_info_1148_2200 +#define pci_ss_info_1148_2200 pci_ss_info_1148_9e00_1148_2200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8100 = + {0x1148, 0x8100, pci_subsys_1148_9e00_1148_8100, 0}; +#undef pci_ss_info_1148_8100 +#define pci_ss_info_1148_8100 pci_ss_info_1148_9e00_1148_8100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8200 = + {0x1148, 0x8200, pci_subsys_1148_9e00_1148_8200, 0}; +#undef pci_ss_info_1148_8200 +#define pci_ss_info_1148_8200 pci_ss_info_1148_9e00_1148_8200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9100 = + {0x1148, 0x9100, pci_subsys_1148_9e00_1148_9100, 0}; +#undef pci_ss_info_1148_9100 +#define pci_ss_info_1148_9100 pci_ss_info_1148_9e00_1148_9100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9200 = + {0x1148, 0x9200, pci_subsys_1148_9e00_1148_9200, 0}; +#undef pci_ss_info_1148_9200 +#define pci_ss_info_1148_9200 pci_ss_info_1148_9e00_1148_9200 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0003_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0003_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0201_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0201_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0201_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0203_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0203_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0203_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0212_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0212_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0212_4c53_1080 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_c134 = + {0x1028, 0xc134, pci_subsys_1166_0213_1028_c134, 0}; +#undef pci_ss_info_1028_c134 +#define pci_ss_info_1028_c134 pci_ss_info_1166_0213_1028_c134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0213_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0213_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0213_1734_1012 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0217_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0217_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0217_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0220_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0220_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0220_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0221_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0221_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0221_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0227_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0227_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0227_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0230_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0230_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0230_4c53_1080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0601_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0601_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0601_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_060a_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_060a_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_060a_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8013 = + {0x117c, 0x8013, pci_subsys_117c_0030_117c_8013, 0}; +#undef pci_ss_info_117c_8013 +#define pci_ss_info_117c_8013 pci_ss_info_117c_0030_117c_8013 +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8014 = + {0x117c, 0x8014, pci_subsys_117c_0030_117c_8014, 0}; +#undef pci_ss_info_117c_8014 +#define pci_ss_info_117c_8014 pci_ss_info_117c_0030_117c_8014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0476_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0476_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0476_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0476_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1987 = + {0x1043, 0x1987, pci_subsys_1180_0476_1043_1987, 0}; +#undef pci_ss_info_1043_1987 +#define pci_ss_info_1043_1987 pci_ss_info_1180_0476_1043_1987 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_14ef_0220 = + {0x14ef, 0x0220, pci_subsys_1180_0476_14ef_0220, 0}; +#undef pci_ss_info_14ef_0220 +#define pci_ss_info_14ef_0220 pci_ss_info_1180_0476_14ef_0220 +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0522_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0522_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0522_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0552_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0552_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0552_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0592_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0592_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0592_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0556 = + {0x1014, 0x0556, pci_subsys_1180_0822_1014_0556, 0}; +#undef pci_ss_info_1014_0556 +#define pci_ss_info_1014_0556 pci_ss_info_1180_0822_1014_0556 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0822_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0822_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_01a2 = + {0x1028, 0x01a2, pci_subsys_1180_0822_1028_01a2, 0}; +#undef pci_ss_info_1028_01a2 +#define pci_ss_info_1028_01a2 pci_ss_info_1180_0822_1028_01a2 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0822_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0822_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0822_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0852_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0852_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0852_1043_1967 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1303 = + {0x1186, 0x1303, pci_subsys_1186_1300_1186_1303, 0}; +#undef pci_ss_info_1186_1303 +#define pci_ss_info_1186_1303 pci_ss_info_1186_1300_1186_1303 +static const pciSubsystemInfo pci_ss_info_1186_4c00_1186_4c00 = + {0x1186, 0x4c00, pci_subsys_1186_4c00_1186_4c00, 0}; +#undef pci_ss_info_1186_4c00 +#define pci_ss_info_1186_4c00 pci_ss_info_1186_4c00_1186_4c00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_1faa_1385_4e00 = + {0x1385, 0x4e00, pci_subsys_11ab_1faa_1385_4e00, 0}; +#undef pci_ss_info_1385_4e00 +#define pci_ss_info_1385_4e00 pci_ss_info_11ab_1faa_1385_4e00 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_0f38 = + {0x1019, 0x0f38, pci_subsys_11ab_4320_1019_0f38, 0}; +#undef pci_ss_info_1019_0f38 +#define pci_ss_info_1019_0f38 pci_ss_info_11ab_4320_1019_0f38 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_8001 = + {0x1019, 0x8001, pci_subsys_11ab_4320_1019_8001, 0}; +#undef pci_ss_info_1019_8001 +#define pci_ss_info_1019_8001 pci_ss_info_11ab_4320_1019_8001 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_173c = + {0x1043, 0x173c, pci_subsys_11ab_4320_1043_173c, 0}; +#undef pci_ss_info_1043_173c +#define pci_ss_info_1043_173c pci_ss_info_11ab_4320_1043_173c +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_811a = + {0x1043, 0x811a, pci_subsys_11ab_4320_1043_811a, 0}; +#undef pci_ss_info_1043_811a +#define pci_ss_info_1043_811a pci_ss_info_11ab_4320_1043_811a +static const pciSubsystemInfo pci_ss_info_11ab_4320_105b_0c19 = + {0x105b, 0x0c19, pci_subsys_11ab_4320_105b_0c19, 0}; +#undef pci_ss_info_105b_0c19 +#define pci_ss_info_105b_0c19 pci_ss_info_11ab_4320_105b_0c19 +static const pciSubsystemInfo pci_ss_info_11ab_4320_10b8_b452 = + {0x10b8, 0xb452, pci_subsys_11ab_4320_10b8_b452, 0}; +#undef pci_ss_info_10b8_b452 +#define pci_ss_info_10b8_b452 pci_ss_info_11ab_4320_10b8_b452 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0121 = + {0x11ab, 0x0121, pci_subsys_11ab_4320_11ab_0121, 0}; +#undef pci_ss_info_11ab_0121 +#define pci_ss_info_11ab_0121 pci_ss_info_11ab_4320_11ab_0121 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0321 = + {0x11ab, 0x0321, pci_subsys_11ab_4320_11ab_0321, 0}; +#undef pci_ss_info_11ab_0321 +#define pci_ss_info_11ab_0321 pci_ss_info_11ab_4320_11ab_0321 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_1021 = + {0x11ab, 0x1021, pci_subsys_11ab_4320_11ab_1021, 0}; +#undef pci_ss_info_11ab_1021 +#define pci_ss_info_11ab_1021 pci_ss_info_11ab_4320_11ab_1021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4320_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4320_11ab_5021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_9521 = + {0x11ab, 0x9521, pci_subsys_11ab_4320_11ab_9521, 0}; +#undef pci_ss_info_11ab_9521 +#define pci_ss_info_11ab_9521 pci_ss_info_11ab_4320_11ab_9521 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4320_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4320_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4320_147b_1406 = + {0x147b, 0x1406, pci_subsys_11ab_4320_147b_1406, 0}; +#undef pci_ss_info_147b_1406 +#define pci_ss_info_147b_1406 pci_ss_info_11ab_4320_147b_1406 +static const pciSubsystemInfo pci_ss_info_11ab_4320_15d4_0047 = + {0x15d4, 0x0047, pci_subsys_11ab_4320_15d4_0047, 0}; +#undef pci_ss_info_15d4_0047 +#define pci_ss_info_15d4_0047 pci_ss_info_11ab_4320_15d4_0047 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1695_9025 = + {0x1695, 0x9025, pci_subsys_11ab_4320_1695_9025, 0}; +#undef pci_ss_info_1695_9025 +#define pci_ss_info_1695_9025 pci_ss_info_11ab_4320_1695_9025 +static const pciSubsystemInfo pci_ss_info_11ab_4320_17f2_1c03 = + {0x17f2, 0x1c03, pci_subsys_11ab_4320_17f2_1c03, 0}; +#undef pci_ss_info_17f2_1c03 +#define pci_ss_info_17f2_1c03 pci_ss_info_11ab_4320_17f2_1c03 +static const pciSubsystemInfo pci_ss_info_11ab_4320_270f_2803 = + {0x270f, 0x2803, pci_subsys_11ab_4320_270f_2803, 0}; +#undef pci_ss_info_270f_2803 +#define pci_ss_info_270f_2803 pci_ss_info_11ab_4320_270f_2803 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4350_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4350_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4350_11ab_3521 = + {0x11ab, 0x3521, pci_subsys_11ab_4350_11ab_3521, 0}; +#undef pci_ss_info_11ab_3521 +#define pci_ss_info_11ab_3521 pci_ss_info_11ab_4350_11ab_3521 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4350_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4350_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4350_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4350_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4350_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4350_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4350_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4350_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4350_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4350_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4350_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4350_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4350_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4350_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4350_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4350_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4350_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4350_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4350_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4350_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4350_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4350_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4350_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4350_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4351_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4351_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4351_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4351_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4351_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4351_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4351_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4351_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4351_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4351_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4351_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4351_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4351_11ab_3621 = + {0x11ab, 0x3621, pci_subsys_11ab_4351_11ab_3621, 0}; +#undef pci_ss_info_11ab_3621 +#define pci_ss_info_11ab_3621 pci_ss_info_11ab_4351_11ab_3621 +static const pciSubsystemInfo pci_ss_info_11ab_4351_13d1_ac12 = + {0x13d1, 0xac12, pci_subsys_11ab_4351_13d1_ac12, 0}; +#undef pci_ss_info_13d1_ac12 +#define pci_ss_info_13d1_ac12 pci_ss_info_11ab_4351_13d1_ac12 +static const pciSubsystemInfo pci_ss_info_11ab_4351_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4351_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4351_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4351_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4351_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4351_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4351_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4351_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4351_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4351_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4351_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4351_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4351_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4351_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4351_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4351_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4351_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4351_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4351_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4351_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4351_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4351_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4351_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4351_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4351_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4351_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4351_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1043_8134 = + {0x1043, 0x8134, pci_subsys_11ab_4360_1043_8134, 0}; +#undef pci_ss_info_1043_8134 +#define pci_ss_info_1043_8134 pci_ss_info_11ab_4360_1043_8134 +static const pciSubsystemInfo pci_ss_info_11ab_4360_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4360_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4360_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4360_11ab_5221 = + {0x11ab, 0x5221, pci_subsys_11ab_4360_11ab_5221, 0}; +#undef pci_ss_info_11ab_5221 +#define pci_ss_info_11ab_5221 pci_ss_info_11ab_4360_11ab_5221 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4360_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4360_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1462_052c = + {0x1462, 0x052c, pci_subsys_11ab_4360_1462_052c, 0}; +#undef pci_ss_info_1462_052c +#define pci_ss_info_1462_052c pci_ss_info_11ab_4360_1462_052c +static const pciSubsystemInfo pci_ss_info_11ab_4360_1849_8052 = + {0x1849, 0x8052, pci_subsys_11ab_4360_1849_8052, 0}; +#undef pci_ss_info_1849_8052 +#define pci_ss_info_1849_8052 pci_ss_info_11ab_4360_1849_8052 +static const pciSubsystemInfo pci_ss_info_11ab_4360_a0a0_0509 = + {0xa0a0, 0x0509, pci_subsys_11ab_4360_a0a0_0509, 0}; +#undef pci_ss_info_a0a0_0509 +#define pci_ss_info_a0a0_0509 pci_ss_info_11ab_4360_a0a0_0509 +static const pciSubsystemInfo pci_ss_info_11ab_4361_107b_3015 = + {0x107b, 0x3015, pci_subsys_11ab_4361_107b_3015, 0}; +#undef pci_ss_info_107b_3015 +#define pci_ss_info_107b_3015 pci_ss_info_11ab_4361_107b_3015 +static const pciSubsystemInfo pci_ss_info_11ab_4361_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4361_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4361_11ab_5021 +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3063 = + {0x8086, 0x3063, pci_subsys_11ab_4361_8086_3063, 0}; +#undef pci_ss_info_8086_3063 +#define pci_ss_info_8086_3063 pci_ss_info_11ab_4361_8086_3063 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3439 = + {0x8086, 0x3439, pci_subsys_11ab_4361_8086_3439, 0}; +#undef pci_ss_info_8086_3439 +#define pci_ss_info_8086_3439 pci_ss_info_11ab_4361_8086_3439 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4362_103c_2a0d = + {0x103c, 0x2a0d, pci_subsys_11ab_4362_103c_2a0d, 0}; +#undef pci_ss_info_103c_2a0d +#define pci_ss_info_103c_2a0d pci_ss_info_11ab_4362_103c_2a0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_4362_1043_8142 = + {0x1043, 0x8142, pci_subsys_11ab_4362_1043_8142, 0}; +#undef pci_ss_info_1043_8142 +#define pci_ss_info_1043_8142 pci_ss_info_11ab_4362_1043_8142 +static const pciSubsystemInfo pci_ss_info_11ab_4362_109f_3197 = + {0x109f, 0x3197, pci_subsys_11ab_4362_109f_3197, 0}; +#undef pci_ss_info_109f_3197 +#define pci_ss_info_109f_3197 pci_ss_info_11ab_4362_109f_3197 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4362_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4362_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10fd_a430 = + {0x10fd, 0xa430, pci_subsys_11ab_4362_10fd_a430, 0}; +#undef pci_ss_info_10fd_a430 +#define pci_ss_info_10fd_a430 pci_ss_info_11ab_4362_10fd_a430 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4362_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4362_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4362_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4362_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4362_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4362_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4362_11ab_5321 = + {0x11ab, 0x5321, pci_subsys_11ab_4362_11ab_5321, 0}; +#undef pci_ss_info_11ab_5321 +#define pci_ss_info_11ab_5321 pci_ss_info_11ab_4362_11ab_5321 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c240 = + {0x1297, 0xc240, pci_subsys_11ab_4362_1297_c240, 0}; +#undef pci_ss_info_1297_c240 +#define pci_ss_info_1297_c240 pci_ss_info_11ab_4362_1297_c240 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c241 = + {0x1297, 0xc241, pci_subsys_11ab_4362_1297_c241, 0}; +#undef pci_ss_info_1297_c241 +#define pci_ss_info_1297_c241 pci_ss_info_11ab_4362_1297_c241 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c242 = + {0x1297, 0xc242, pci_subsys_11ab_4362_1297_c242, 0}; +#undef pci_ss_info_1297_c242 +#define pci_ss_info_1297_c242 pci_ss_info_11ab_4362_1297_c242 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c243 = + {0x1297, 0xc243, pci_subsys_11ab_4362_1297_c243, 0}; +#undef pci_ss_info_1297_c243 +#define pci_ss_info_1297_c243 pci_ss_info_11ab_4362_1297_c243 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c244 = + {0x1297, 0xc244, pci_subsys_11ab_4362_1297_c244, 0}; +#undef pci_ss_info_1297_c244 +#define pci_ss_info_1297_c244 pci_ss_info_11ab_4362_1297_c244 +static const pciSubsystemInfo pci_ss_info_11ab_4362_13d1_ac11 = + {0x13d1, 0xac11, pci_subsys_11ab_4362_13d1_ac11, 0}; +#undef pci_ss_info_13d1_ac11 +#define pci_ss_info_13d1_ac11 pci_ss_info_11ab_4362_13d1_ac11 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4362_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4362_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1462_058c = + {0x1462, 0x058c, pci_subsys_11ab_4362_1462_058c, 0}; +#undef pci_ss_info_1462_058c +#define pci_ss_info_1462_058c pci_ss_info_11ab_4362_1462_058c +static const pciSubsystemInfo pci_ss_info_11ab_4362_14c0_0012 = + {0x14c0, 0x0012, pci_subsys_11ab_4362_14c0_0012, 0}; +#undef pci_ss_info_14c0_0012 +#define pci_ss_info_14c0_0012 pci_ss_info_11ab_4362_14c0_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1558_04a0 = + {0x1558, 0x04a0, pci_subsys_11ab_4362_1558_04a0, 0}; +#undef pci_ss_info_1558_04a0 +#define pci_ss_info_1558_04a0 pci_ss_info_11ab_4362_1558_04a0 +static const pciSubsystemInfo pci_ss_info_11ab_4362_15bd_1003 = + {0x15bd, 0x1003, pci_subsys_11ab_4362_15bd_1003, 0}; +#undef pci_ss_info_15bd_1003 +#define pci_ss_info_15bd_1003 pci_ss_info_11ab_4362_15bd_1003 +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203c = + {0x161f, 0x203c, pci_subsys_11ab_4362_161f_203c, 0}; +#undef pci_ss_info_161f_203c +#define pci_ss_info_161f_203c pci_ss_info_11ab_4362_161f_203c +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4362_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4362_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1695_9029 = + {0x1695, 0x9029, pci_subsys_11ab_4362_1695_9029, 0}; +#undef pci_ss_info_1695_9029 +#define pci_ss_info_1695_9029 pci_ss_info_11ab_4362_1695_9029 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17f2_2c08 = + {0x17f2, 0x2c08, pci_subsys_11ab_4362_17f2_2c08, 0}; +#undef pci_ss_info_17f2_2c08 +#define pci_ss_info_17f2_2c08 pci_ss_info_11ab_4362_17f2_2c08 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17ff_0585 = + {0x17ff, 0x0585, pci_subsys_11ab_4362_17ff_0585, 0}; +#undef pci_ss_info_17ff_0585 +#define pci_ss_info_17ff_0585 pci_ss_info_11ab_4362_17ff_0585 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1849_8053 = + {0x1849, 0x8053, pci_subsys_11ab_4362_1849_8053, 0}; +#undef pci_ss_info_1849_8053 +#define pci_ss_info_1849_8053 pci_ss_info_11ab_4362_1849_8053 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000b = + {0x1854, 0x000b, pci_subsys_11ab_4362_1854_000b, 0}; +#undef pci_ss_info_1854_000b +#define pci_ss_info_1854_000b pci_ss_info_11ab_4362_1854_000b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000c = + {0x1854, 0x000c, pci_subsys_11ab_4362_1854_000c, 0}; +#undef pci_ss_info_1854_000c +#define pci_ss_info_1854_000c pci_ss_info_11ab_4362_1854_000c +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0010 = + {0x1854, 0x0010, pci_subsys_11ab_4362_1854_0010, 0}; +#undef pci_ss_info_1854_0010 +#define pci_ss_info_1854_0010 pci_ss_info_11ab_4362_1854_0010 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0013 = + {0x1854, 0x0013, pci_subsys_11ab_4362_1854_0013, 0}; +#undef pci_ss_info_1854_0013 +#define pci_ss_info_1854_0013 pci_ss_info_11ab_4362_1854_0013 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0014 = + {0x1854, 0x0014, pci_subsys_11ab_4362_1854_0014, 0}; +#undef pci_ss_info_1854_0014 +#define pci_ss_info_1854_0014 pci_ss_info_11ab_4362_1854_0014 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0015 = + {0x1854, 0x0015, pci_subsys_11ab_4362_1854_0015, 0}; +#undef pci_ss_info_1854_0015 +#define pci_ss_info_1854_0015 pci_ss_info_11ab_4362_1854_0015 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001a = + {0x1854, 0x001a, pci_subsys_11ab_4362_1854_001a, 0}; +#undef pci_ss_info_1854_001a +#define pci_ss_info_1854_001a pci_ss_info_11ab_4362_1854_001a +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001b = + {0x1854, 0x001b, pci_subsys_11ab_4362_1854_001b, 0}; +#undef pci_ss_info_1854_001b +#define pci_ss_info_1854_001b pci_ss_info_11ab_4362_1854_001b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001d = + {0x1854, 0x001d, pci_subsys_11ab_4362_1854_001d, 0}; +#undef pci_ss_info_1854_001d +#define pci_ss_info_1854_001d pci_ss_info_11ab_4362_1854_001d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001f = + {0x1854, 0x001f, pci_subsys_11ab_4362_1854_001f, 0}; +#undef pci_ss_info_1854_001f +#define pci_ss_info_1854_001f pci_ss_info_11ab_4362_1854_001f +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0021 = + {0x1854, 0x0021, pci_subsys_11ab_4362_1854_0021, 0}; +#undef pci_ss_info_1854_0021 +#define pci_ss_info_1854_0021 pci_ss_info_11ab_4362_1854_0021 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0022 = + {0x1854, 0x0022, pci_subsys_11ab_4362_1854_0022, 0}; +#undef pci_ss_info_1854_0022 +#define pci_ss_info_1854_0022 pci_ss_info_11ab_4362_1854_0022 +static const pciSubsystemInfo pci_ss_info_11ab_4362_270f_2801 = + {0x270f, 0x2801, pci_subsys_11ab_4362_270f_2801, 0}; +#undef pci_ss_info_270f_2801 +#define pci_ss_info_270f_2801 pci_ss_info_11ab_4362_270f_2801 +static const pciSubsystemInfo pci_ss_info_11ab_4362_a0a0_0506 = + {0xa0a0, 0x0506, pci_subsys_11ab_4362_a0a0_0506, 0}; +#undef pci_ss_info_a0a0_0506 +#define pci_ss_info_a0a0_0506 pci_ss_info_11ab_4362_a0a0_0506 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2203 = + {0x8086, 0x2203, pci_subsys_11c1_0445_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_11c1_0445_8086_2203 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2204 = + {0x8086, 0x2204, pci_subsys_11c1_0445_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_11c1_0445_8086_2204 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_1033_80a8 = + {0x1033, 0x80a8, pci_subsys_11c1_0450_1033_80a8, 0}; +#undef pci_ss_info_1033_80a8 +#define pci_ss_info_1033_80a8 pci_ss_info_11c1_0450_1033_80a8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_1468_0450 = + {0x1468, 0x0450, pci_subsys_11c1_0450_1468_0450, 0}; +#undef pci_ss_info_1468_0450 +#define pci_ss_info_1468_0450 pci_ss_info_11c1_0450_1468_0450 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_4005_144f = + {0x4005, 0x144f, pci_subsys_11c1_0450_4005_144f, 0}; +#undef pci_ss_info_4005_144f +#define pci_ss_info_4005_144f pci_ss_info_11c1_0450_4005_144f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_5811_8086_524c = + {0x8086, 0x524c, pci_subsys_11c1_5811_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_11c1_5811_8086_524c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +static const pciSubsystemInfo pci_ss_info_11c1_8110_12d9_000c = + {0x12d9, 0x000c, pci_subsys_11c1_8110_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_11c1_8110_12d9_000c +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab12 = + {0x11c1, 0xab12, pci_subsys_11c1_ab11_11c1_ab12, 0}; +#undef pci_ss_info_11c1_ab12 +#define pci_ss_info_11c1_ab12 pci_ss_info_11c1_ab11_11c1_ab12 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab13 = + {0x11c1, 0xab13, pci_subsys_11c1_ab11_11c1_ab13, 0}; +#undef pci_ss_info_11c1_ab13 +#define pci_ss_info_11c1_ab13 pci_ss_info_11c1_ab11_11c1_ab13 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab15 = + {0x11c1, 0xab15, pci_subsys_11c1_ab11_11c1_ab15, 0}; +#undef pci_ss_info_11c1_ab15 +#define pci_ss_info_11c1_ab15 pci_ss_info_11c1_ab11_11c1_ab15 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab16 = + {0x11c1, 0xab16, pci_subsys_11c1_ab11_11c1_ab16, 0}; +#undef pci_ss_info_11c1_ab16 +#define pci_ss_info_11c1_ab16 pci_ss_info_11c1_ab11_11c1_ab16 +static const pciSubsystemInfo pci_ss_info_11c1_ab30_14cd_2012 = + {0x14cd, 0x2012, pci_subsys_11c1_ab30_14cd_2012, 0}; +#undef pci_ss_info_14cd_2012 +#define pci_ss_info_14cd_2012 pci_ss_info_11c1_ab30_14cd_2012 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_12f8_8a02 = + {0x12f8, 0x8a02, pci_subsys_11de_6057_12f8_8a02, 0}; +#undef pci_ss_info_12f8_8a02 +#define pci_ss_info_12f8_8a02 pci_ss_info_11de_6057_12f8_8a02 +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +static const pciSubsystemInfo pci_ss_info_11de_6120_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_11de_6120_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_11de_6120_13c2_0000 +static const pciSubsystemInfo pci_ss_info_11de_6120_1de1_9fff = + {0x1de1, 0x9fff, pci_subsys_11de_6120_1de1_9fff, 0}; +#undef pci_ss_info_1de1_9fff +#define pci_ss_info_1de1_9fff pci_ss_info_11de_6120_1de1_9fff +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1014_020c = + {0x1014, 0x020c, pci_subsys_1217_6972_1014_020c, 0}; +#undef pci_ss_info_1014_020c +#define pci_ss_info_1014_020c pci_ss_info_1217_6972_1014_020c +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7110_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7110_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7110_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7110_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7223_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7223_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7223_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7223_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0057 = + {0x121a, 0x0057, pci_subsys_121a_0005_121a_0057, 0}; +#undef pci_ss_info_121a_0057 +#define pci_ss_info_121a_0057 pci_ss_info_121a_0005_121a_0057 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0009_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0009_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000f = + {0x11bd, 0x000f, pci_subsys_123f_8120_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_123f_8120_11bd_000f +static const pciSubsystemInfo pci_ss_info_123f_8120_1809_0016 = + {0x1809, 0x0016, pci_subsys_123f_8120_1809_0016, 0}; +#undef pci_ss_info_1809_0016 +#define pci_ss_info_1809_0016 pci_ss_info_123f_8120_1809_0016 +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125b_1400_1186_1100 = + {0x1186, 0x1100, pci_subsys_125b_1400_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_125b_1400_1186_1100 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +static const pciSubsystemInfo pci_ss_info_125d_1969_153b_111b = + {0x153b, 0x111b, pci_subsys_125d_1969_153b_111b, 0}; +#undef pci_ss_info_153b_111b +#define pci_ss_info_153b_111b pci_ss_info_125d_1969_153b_111b +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_125d_1988_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_125d_1988_0e11_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_125d_1998_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_125d_1998_1028_00b1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3872_1468_0202 = + {0x1468, 0x0202, pci_subsys_1260_3872_1468_0202, 0}; +#undef pci_ss_info_1468_0202 +#define pci_ss_info_1468_0202 pci_ss_info_1260_3872_1468_0202 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3700 = + {0x1186, 0x3700, pci_subsys_1260_3873_1186_3700, 0}; +#undef pci_ss_info_1186_3700 +#define pci_ss_info_1186_3700 pci_ss_info_1260_3873_1186_3700 +static const pciSubsystemInfo pci_ss_info_1260_3873_1385_4105 = + {0x1385, 0x4105, pci_subsys_1260_3873_1385_4105, 0}; +#undef pci_ss_info_1385_4105 +#define pci_ss_info_1385_4105 pci_ss_info_1260_3873_1385_4105 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_16a5_1601 = + {0x16a5, 0x1601, pci_subsys_1260_3873_16a5_1601, 0}; +#undef pci_ss_info_16a5_1601 +#define pci_ss_info_16a5_1601 pci_ss_info_1260_3873_16a5_1601 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3886_17cf_0037 = + {0x17cf, 0x0037, pci_subsys_1260_3886_17cf_0037, 0}; +#undef pci_ss_info_17cf_0037 +#define pci_ss_info_17cf_0037 pci_ss_info_1260_3886_17cf_0037 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2802 = + {0x10b8, 0x2802, pci_subsys_1260_3890_10b8_2802, 0}; +#undef pci_ss_info_10b8_2802 +#define pci_ss_info_10b8_2802 pci_ss_info_1260_3890_10b8_2802 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2835 = + {0x10b8, 0x2835, pci_subsys_1260_3890_10b8_2835, 0}; +#undef pci_ss_info_10b8_2835 +#define pci_ss_info_10b8_2835 pci_ss_info_1260_3890_10b8_2835 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_a835 = + {0x10b8, 0xa835, pci_subsys_1260_3890_10b8_a835, 0}; +#undef pci_ss_info_10b8_a835 +#define pci_ss_info_10b8_a835 pci_ss_info_1260_3890_10b8_a835 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_4203 = + {0x1113, 0x4203, pci_subsys_1260_3890_1113_4203, 0}; +#undef pci_ss_info_1113_4203 +#define pci_ss_info_1113_4203 pci_ss_info_1260_3890_1113_4203 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee03 = + {0x1113, 0xee03, pci_subsys_1260_3890_1113_ee03, 0}; +#undef pci_ss_info_1113_ee03 +#define pci_ss_info_1113_ee03 pci_ss_info_1260_3890_1113_ee03 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee08 = + {0x1113, 0xee08, pci_subsys_1260_3890_1113_ee08, 0}; +#undef pci_ss_info_1113_ee08 +#define pci_ss_info_1113_ee08 pci_ss_info_1260_3890_1113_ee08 +static const pciSubsystemInfo pci_ss_info_1260_3890_1186_3202 = + {0x1186, 0x3202, pci_subsys_1260_3890_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_1260_3890_1186_3202 +static const pciSubsystemInfo pci_ss_info_1260_3890_1259_c104 = + {0x1259, 0xc104, pci_subsys_1260_3890_1259_c104, 0}; +#undef pci_ss_info_1259_c104 +#define pci_ss_info_1259_c104 pci_ss_info_1260_3890_1259_c104 +static const pciSubsystemInfo pci_ss_info_1260_3890_1385_4800 = + {0x1385, 0x4800, pci_subsys_1260_3890_1385_4800, 0}; +#undef pci_ss_info_1385_4800 +#define pci_ss_info_1385_4800 pci_ss_info_1260_3890_1385_4800 +static const pciSubsystemInfo pci_ss_info_1260_3890_16a5_1605 = + {0x16a5, 0x1605, pci_subsys_1260_3890_16a5_1605, 0}; +#undef pci_ss_info_16a5_1605 +#define pci_ss_info_16a5_1605 pci_ss_info_1260_3890_16a5_1605 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0014 = + {0x17cf, 0x0014, pci_subsys_1260_3890_17cf_0014, 0}; +#undef pci_ss_info_17cf_0014 +#define pci_ss_info_17cf_0014 pci_ss_info_1260_3890_17cf_0014 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0020 = + {0x17cf, 0x0020, pci_subsys_1260_3890_17cf_0020, 0}; +#undef pci_ss_info_17cf_0020 +#define pci_ss_info_17cf_0020 pci_ss_info_1260_3890_17cf_0020 +static const pciSubsystemInfo pci_ss_info_1260_ffff_1260_0000 = + {0x1260, 0x0000, pci_subsys_1260_ffff_1260_0000, 0}; +#undef pci_ss_info_1260_0000 +#define pci_ss_info_1260_0000 pci_ss_info_1260_ffff_1260_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_1371_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_1371_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4541 = + {0x8086, 0x4541, pci_subsys_1274_1371_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_1274_1371_8086_4541 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_5880_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_5880_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1005_127a = + {0x1005, 0x127a, pci_subsys_127a_1005_1005_127a, 0}; +#undef pci_ss_info_1005_127a +#define pci_ss_info_1005_127a pci_ss_info_127a_1005_1005_127a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1283_8211_1043_8138 = + {0x1043, 0x8138, pci_subsys_1283_8211_1043_8138, 0}; +#undef pci_ss_info_1043_8138 +#define pci_ss_info_1043_8138 pci_ss_info_1283_8211_1043_8138 +static const pciSubsystemInfo pci_ss_info_1283_8212_1283_0001 = + {0x1283, 0x0001, pci_subsys_1283_8212_1283_0001, 0}; +#undef pci_ss_info_1283_0001 +#define pci_ss_info_1283_0001 pci_ss_info_1283_8212_1283_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_1014_0104 = + {0x1014, 0x0104, pci_subsys_12ae_0001_1014_0104, 0}; +#undef pci_ss_info_1014_0104 +#define pci_ss_info_1014_0104 pci_ss_info_12ae_0001_1014_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_12ae_0002_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_12ae_0002_10a9_8002 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1317_8201_10b8_2635 = + {0x10b8, 0x2635, pci_subsys_1317_8201_10b8_2635, 0}; +#undef pci_ss_info_10b8_2635 +#define pci_ss_info_10b8_2635 pci_ss_info_1317_8201_10b8_2635 +static const pciSubsystemInfo pci_ss_info_1317_8201_1317_8201 = + {0x1317, 0x8201, pci_subsys_1317_8201_1317_8201, 0}; +#undef pci_ss_info_1317_8201 +#define pci_ss_info_1317_8201 pci_ss_info_1317_8201_1317_8201 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1319_0801_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0801_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0801_1319_1319 +static const pciSubsystemInfo pci_ss_info_1319_0802_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0802_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0802_1319_1319 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7890_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7890_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7890_134d_0001 +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1371_434e_1371_434e = + {0x1371, 0x434e, pci_subsys_1371_434e_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_1371_434e_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1704 = + {0x0675, 0x1704, pci_subsys_1397_2bd0_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1397_2bd0_0675_1704 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1708 = + {0x0675, 0x1708, pci_subsys_1397_2bd0_0675_1708, 0}; +#undef pci_ss_info_0675_1708 +#define pci_ss_info_0675_1708 pci_ss_info_1397_2bd0_0675_1708 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13c1_1001_13c1_1001 = + {0x13c1, 0x1001, pci_subsys_13c1_1001_13c1_1001, 0}; +#undef pci_ss_info_13c1_1001 +#define pci_ss_info_13c1_1001 pci_ss_info_13c1_1001_13c1_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8035 = + {0x1043, 0x8035, pci_subsys_13f6_0111_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_13f6_0111_1043_8035 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1681_a000 = + {0x1681, 0xa000, pci_subsys_13f6_0111_1681_a000, 0}; +#undef pci_ss_info_1681_a000 +#define pci_ss_info_1681_a000 pci_ss_info_13f6_0111_1681_a000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_1712 = + {0x1412, 0x1712, pci_subsys_1412_1712_1412_1712, 0}; +#undef pci_ss_info_1412_1712 +#define pci_ss_info_1412_1712 pci_ss_info_1412_1712_1412_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d630 = + {0x1412, 0xd630, pci_subsys_1412_1712_1412_d630, 0}; +#undef pci_ss_info_1412_d630 +#define pci_ss_info_1412_d630 pci_ss_info_1412_1712_1412_d630 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d631 = + {0x1412, 0xd631, pci_subsys_1412_1712_1412_d631, 0}; +#undef pci_ss_info_1412_d631 +#define pci_ss_info_1412_d631 pci_ss_info_1412_1712_1412_d631 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d632 = + {0x1412, 0xd632, pci_subsys_1412_1712_1412_d632, 0}; +#undef pci_ss_info_1412_d632 +#define pci_ss_info_1412_d632 pci_ss_info_1412_1712_1412_d632 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d633 = + {0x1412, 0xd633, pci_subsys_1412_1712_1412_d633, 0}; +#undef pci_ss_info_1412_d633 +#define pci_ss_info_1412_d633 pci_ss_info_1412_1712_1412_d633 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d634 = + {0x1412, 0xd634, pci_subsys_1412_1712_1412_d634, 0}; +#undef pci_ss_info_1412_d634 +#define pci_ss_info_1412_d634 pci_ss_info_1412_1712_1412_d634 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d635 = + {0x1412, 0xd635, pci_subsys_1412_1712_1412_d635, 0}; +#undef pci_ss_info_1412_d635 +#define pci_ss_info_1412_d635 pci_ss_info_1412_1712_1412_d635 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d637 = + {0x1412, 0xd637, pci_subsys_1412_1712_1412_d637, 0}; +#undef pci_ss_info_1412_d637 +#define pci_ss_info_1412_d637 pci_ss_info_1412_1712_1412_d637 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d638 = + {0x1412, 0xd638, pci_subsys_1412_1712_1412_d638, 0}; +#undef pci_ss_info_1412_d638 +#define pci_ss_info_1412_d638 pci_ss_info_1412_1712_1412_d638 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63b = + {0x1412, 0xd63b, pci_subsys_1412_1712_1412_d63b, 0}; +#undef pci_ss_info_1412_d63b +#define pci_ss_info_1412_d63b pci_ss_info_1412_1712_1412_d63b +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63c = + {0x1412, 0xd63c, pci_subsys_1412_1712_1412_d63c, 0}; +#undef pci_ss_info_1412_d63c +#define pci_ss_info_1412_d63c pci_ss_info_1412_1712_1412_d63c +static const pciSubsystemInfo pci_ss_info_1412_1712_1416_1712 = + {0x1416, 0x1712, pci_subsys_1412_1712_1416_1712, 0}; +#undef pci_ss_info_1416_1712 +#define pci_ss_info_1416_1712 pci_ss_info_1412_1712_1416_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1115 = + {0x153b, 0x1115, pci_subsys_1412_1712_153b_1115, 0}; +#undef pci_ss_info_153b_1115 +#define pci_ss_info_153b_1115 pci_ss_info_1412_1712_153b_1115 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1125 = + {0x153b, 0x1125, pci_subsys_1412_1712_153b_1125, 0}; +#undef pci_ss_info_153b_1125 +#define pci_ss_info_153b_1125 pci_ss_info_1412_1712_153b_1125 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112b = + {0x153b, 0x112b, pci_subsys_1412_1712_153b_112b, 0}; +#undef pci_ss_info_153b_112b +#define pci_ss_info_153b_112b pci_ss_info_1412_1712_153b_112b +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112c = + {0x153b, 0x112c, pci_subsys_1412_1712_153b_112c, 0}; +#undef pci_ss_info_153b_112c +#define pci_ss_info_153b_112c pci_ss_info_1412_1712_153b_112c +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1130 = + {0x153b, 0x1130, pci_subsys_1412_1712_153b_1130, 0}; +#undef pci_ss_info_153b_1130 +#define pci_ss_info_153b_1130 pci_ss_info_1412_1712_153b_1130 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1138 = + {0x153b, 0x1138, pci_subsys_1412_1712_153b_1138, 0}; +#undef pci_ss_info_153b_1138 +#define pci_ss_info_153b_1138 pci_ss_info_1412_1712_153b_1138 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1151 = + {0x153b, 0x1151, pci_subsys_1412_1712_153b_1151, 0}; +#undef pci_ss_info_153b_1151 +#define pci_ss_info_153b_1151 pci_ss_info_1412_1712_153b_1151 +static const pciSubsystemInfo pci_ss_info_1412_1712_16ce_1040 = + {0x16ce, 0x1040, pci_subsys_1412_1712_16ce_1040, 0}; +#undef pci_ss_info_16ce_1040 +#define pci_ss_info_16ce_1040 pci_ss_info_1412_1712_16ce_1040 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_1724 = + {0x1412, 0x1724, pci_subsys_1412_1724_1412_1724, 0}; +#undef pci_ss_info_1412_1724 +#define pci_ss_info_1412_1724 pci_ss_info_1412_1724_1412_1724 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3630 = + {0x1412, 0x3630, pci_subsys_1412_1724_1412_3630, 0}; +#undef pci_ss_info_1412_3630 +#define pci_ss_info_1412_3630 pci_ss_info_1412_1724_1412_3630 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3631 = + {0x1412, 0x3631, pci_subsys_1412_1724_1412_3631, 0}; +#undef pci_ss_info_1412_3631 +#define pci_ss_info_1412_3631 pci_ss_info_1412_1724_1412_3631 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1145 = + {0x153b, 0x1145, pci_subsys_1412_1724_153b_1145, 0}; +#undef pci_ss_info_153b_1145 +#define pci_ss_info_153b_1145 pci_ss_info_1412_1724_153b_1145 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1147 = + {0x153b, 0x1147, pci_subsys_1412_1724_153b_1147, 0}; +#undef pci_ss_info_153b_1147 +#define pci_ss_info_153b_1147 pci_ss_info_1412_1724_153b_1147 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1153 = + {0x153b, 0x1153, pci_subsys_1412_1724_153b_1153, 0}; +#undef pci_ss_info_153b_1153 +#define pci_ss_info_153b_1153 pci_ss_info_1412_1724_153b_1153 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f641 = + {0x270f, 0xf641, pci_subsys_1412_1724_270f_f641, 0}; +#undef pci_ss_info_270f_f641 +#define pci_ss_info_270f_f641 pci_ss_info_1412_1724_270f_f641 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f645 = + {0x270f, 0xf645, pci_subsys_1412_1724_270f_f645, 0}; +#undef pci_ss_info_270f_f645 +#define pci_ss_info_270f_f645 pci_ss_info_1412_1724_270f_f645 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2050 = + {0x131f, 0x2050, pci_subsys_1415_9501_131f_2050, 0}; +#undef pci_ss_info_131f_2050 +#define pci_ss_info_131f_2050 pci_ss_info_1415_9501_131f_2050 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2051 = + {0x131f, 0x2051, pci_subsys_1415_9501_131f_2051, 0}; +#undef pci_ss_info_131f_2051 +#define pci_ss_info_131f_2051 pci_ss_info_1415_9501_131f_2051 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128a = + {0x103c, 0x128a, pci_subsys_14e4_1645_103c_128a, 0}; +#undef pci_ss_info_103c_128a +#define pci_ss_info_103c_128a pci_ss_info_14e4_1645_103c_128a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128b = + {0x103c, 0x128b, pci_subsys_14e4_1645_103c_128b, 0}; +#undef pci_ss_info_103c_128b +#define pci_ss_info_103c_128b pci_ss_info_14e4_1645_103c_128b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12a4 = + {0x103c, 0x12a4, pci_subsys_14e4_1645_103c_12a4, 0}; +#undef pci_ss_info_103c_12a4 +#define pci_ss_info_103c_12a4 pci_ss_info_14e4_1645_103c_12a4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12c1 = + {0x103c, 0x12c1, pci_subsys_14e4_1645_103c_12c1, 0}; +#undef pci_ss_info_103c_12c1 +#define pci_ss_info_103c_12c1 pci_ss_info_14e4_1645_103c_12c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_1300 = + {0x103c, 0x1300, pci_subsys_14e4_1645_103c_1300, 0}; +#undef pci_ss_info_103c_1300 +#define pci_ss_info_103c_1300 pci_ss_info_14e4_1645_103c_1300 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1645_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1645_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8011 = + {0x10a9, 0x8011, pci_subsys_14e4_1645_10a9_8011, 0}; +#undef pci_ss_info_10a9_8011 +#define pci_ss_info_10a9_8011 pci_ss_info_14e4_1645_10a9_8011 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8012 = + {0x10a9, 0x8012, pci_subsys_14e4_1645_10a9_8012, 0}; +#undef pci_ss_info_10a9_8012 +#define pci_ss_info_10a9_8012 pci_ss_info_14e4_1645_10a9_8012 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1647_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1647_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1734_100b = + {0x1734, 0x100b, pci_subsys_14e4_1648_1734_100b, 0}; +#undef pci_ss_info_1734_100b +#define pci_ss_info_1734_100b pci_ss_info_14e4_1648_1734_100b +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3101 = + {0x103c, 0x3101, pci_subsys_14e4_164a_103c_3101, 0}; +#undef pci_ss_info_103c_3101 +#define pci_ss_info_103c_3101 pci_ss_info_14e4_164a_103c_3101 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1653_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1653_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1653_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1654_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1654_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3100 = + {0x103c, 0x3100, pci_subsys_14e4_1654_103c_3100, 0}; +#undef pci_ss_info_103c_3100 +#define pci_ss_info_103c_3100 pci_ss_info_14e4_1654_103c_3100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3226 = + {0x103c, 0x3226, pci_subsys_14e4_1654_103c_3226, 0}; +#undef pci_ss_info_103c_3226 +#define pci_ss_info_103c_3226 pci_ss_info_14e4_1654_103c_3226 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1014_02c6 = + {0x1014, 0x02c6, pci_subsys_14e4_1659_1014_02c6, 0}; +#undef pci_ss_info_1014_02c6 +#define pci_ss_info_1014_02c6 pci_ss_info_14e4_1659_1014_02c6 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7031 = + {0x103c, 0x7031, pci_subsys_14e4_1659_103c_7031, 0}; +#undef pci_ss_info_103c_7031 +#define pci_ss_info_103c_7031 pci_ss_info_14e4_1659_103c_7031 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7032 = + {0x103c, 0x7032, pci_subsys_14e4_1659_103c_7032, 0}; +#undef pci_ss_info_103c_7032 +#define pci_ss_info_103c_7032 pci_ss_info_14e4_1659_103c_7032 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1734_1061 = + {0x1734, 0x1061, pci_subsys_14e4_1659_1734_1061, 0}; +#undef pci_ss_info_1734_1061 +#define pci_ss_info_1734_1061 pci_ss_info_14e4_1659_1734_1061 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165d_1028_865d = + {0x1028, 0x865d, pci_subsys_14e4_165d_1028_865d, 0}; +#undef pci_ss_info_1028_865d +#define pci_ss_info_1028_865d pci_ss_info_14e4_165d_1028_865d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_088c = + {0x103c, 0x088c, pci_subsys_14e4_165e_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_14e4_165e_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_0890 = + {0x103c, 0x0890, pci_subsys_14e4_165e_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_14e4_165e_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_165e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_165e_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1668_103c_7039 = + {0x103c, 0x7039, pci_subsys_14e4_1668_103c_7039, 0}; +#undef pci_ss_info_103c_7039 +#define pci_ss_info_103c_7039 pci_ss_info_14e4_1668_103c_7039 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0179 = + {0x1028, 0x0179, pci_subsys_14e4_1677_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_14e4_1677_1028_0179 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0182 = + {0x1028, 0x0182, pci_subsys_14e4_1677_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_14e4_1677_1028_0182 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_01ad = + {0x1028, 0x01ad, pci_subsys_14e4_1677_1028_01ad, 0}; +#undef pci_ss_info_1028_01ad +#define pci_ss_info_1028_01ad pci_ss_info_14e4_1677_1028_01ad +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1677_1734_105d = + {0x1734, 0x105d, pci_subsys_14e4_1677_1734_105d, 0}; +#undef pci_ss_info_1734_105d +#define pci_ss_info_1734_105d pci_ss_info_14e4_1677_1734_105d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1696_103c_12bc = + {0x103c, 0x12bc, pci_subsys_14e4_1696_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_14e4_1696_103c_12bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_169c_103c_308b = + {0x103c, 0x308b, pci_subsys_14e4_169c_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_14e4_169c_103c_308b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16aa_103c_3102 = + {0x103c, 0x3102, pci_subsys_14e4_16aa_103c_3102, 0}; +#undef pci_ss_info_103c_3102 +#define pci_ss_info_103c_3102 pci_ss_info_14e4_16aa_103c_3102 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16c7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16c7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16c7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16c7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12c3 = + {0x103c, 0x12c3, pci_subsys_14e4_16c7_103c_12c3, 0}; +#undef pci_ss_info_103c_12c3 +#define pci_ss_info_103c_12c3 pci_ss_info_14e4_16c7_103c_12c3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12ca = + {0x103c, 0x12ca, pci_subsys_14e4_16c7_103c_12ca, 0}; +#undef pci_ss_info_103c_12ca +#define pci_ss_info_103c_12ca pci_ss_info_14e4_16c7_103c_12ca +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0188 = + {0x1028, 0x0188, pci_subsys_14e4_170c_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_14e4_170c_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0196 = + {0x1028, 0x0196, pci_subsys_14e4_170c_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_14e4_170c_1028_0196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_170c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_170c_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_170d_1014_0545 = + {0x1014, 0x0545, pci_subsys_14e4_170d_1014_0545, 0}; +#undef pci_ss_info_1014_0545 +#define pci_ss_info_1014_0545 pci_ss_info_14e4_170d_1014_0545 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4301_1028_0407 = + {0x1028, 0x0407, pci_subsys_14e4_4301_1028_0407, 0}; +#undef pci_ss_info_1028_0407 +#define pci_ss_info_1028_0407 pci_ss_info_14e4_4301_1028_0407 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4301_1043_0120 = + {0x1043, 0x0120, pci_subsys_14e4_4301_1043_0120, 0}; +#undef pci_ss_info_1043_0120 +#define pci_ss_info_1043_0120 pci_ss_info_14e4_4301_1043_0120 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4318_103c_1356 = + {0x103c, 0x1356, pci_subsys_14e4_4318_103c_1356, 0}; +#undef pci_ss_info_103c_1356 +#define pci_ss_info_103c_1356 pci_ss_info_14e4_4318_103c_1356 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0311 = + {0x1468, 0x0311, pci_subsys_14e4_4318_1468_0311, 0}; +#undef pci_ss_info_1468_0311 +#define pci_ss_info_1468_0311 pci_ss_info_14e4_4318_1468_0311 +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0312 = + {0x1468, 0x0312, pci_subsys_14e4_4318_1468_0312, 0}; +#undef pci_ss_info_1468_0312 +#define pci_ss_info_1468_0312 pci_ss_info_14e4_4318_1468_0312 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_0449 = + {0x14e4, 0x0449, pci_subsys_14e4_4318_14e4_0449, 0}; +#undef pci_ss_info_14e4_0449 +#define pci_ss_info_14e4_0449 pci_ss_info_14e4_4318_14e4_0449 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_4318 = + {0x14e4, 0x4318, pci_subsys_14e4_4318_14e4_4318, 0}; +#undef pci_ss_info_14e4_4318 +#define pci_ss_info_14e4_4318 pci_ss_info_14e4_4318_14e4_4318 +static const pciSubsystemInfo pci_ss_info_14e4_4318_16ec_0119 = + {0x16ec, 0x0119, pci_subsys_14e4_4318_16ec_0119, 0}; +#undef pci_ss_info_16ec_0119 +#define pci_ss_info_16ec_0119 pci_ss_info_14e4_4318_16ec_0119 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4320_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4320_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4320_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4320_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12f4 = + {0x103c, 0x12f4, pci_subsys_14e4_4320_103c_12f4, 0}; +#undef pci_ss_info_103c_12f4 +#define pci_ss_info_103c_12f4 pci_ss_info_14e4_4320_103c_12f4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12fa = + {0x103c, 0x12fa, pci_subsys_14e4_4320_103c_12fa, 0}; +#undef pci_ss_info_103c_12fa +#define pci_ss_info_103c_12fa pci_ss_info_14e4_4320_103c_12fa +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_1043_100f = + {0x1043, 0x100f, pci_subsys_14e4_4320_1043_100f, 0}; +#undef pci_ss_info_1043_100f +#define pci_ss_info_1043_100f pci_ss_info_14e4_4320_1043_100f +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1057_7025 = + {0x1057, 0x7025, pci_subsys_14e4_4320_1057_7025, 0}; +#undef pci_ss_info_1057_7025 +#define pci_ss_info_1057_7025 pci_ss_info_14e4_4320_1057_7025 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_106b_004e = + {0x106b, 0x004e, pci_subsys_14e4_4320_106b_004e, 0}; +#undef pci_ss_info_106b_004e +#define pci_ss_info_106b_004e pci_ss_info_14e4_4320_106b_004e +static const pciSubsystemInfo pci_ss_info_14e4_4320_144f_7050 = + {0x144f, 0x7050, pci_subsys_14e4_4320_144f_7050, 0}; +#undef pci_ss_info_144f_7050 +#define pci_ss_info_144f_7050 pci_ss_info_14e4_4320_144f_7050 +static const pciSubsystemInfo pci_ss_info_14e4_4320_14e4_4320 = + {0x14e4, 0x4320, pci_subsys_14e4_4320_14e4_4320, 0}; +#undef pci_ss_info_14e4_4320 +#define pci_ss_info_14e4_4320 pci_ss_info_14e4_4320_14e4_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1737_4320 = + {0x1737, 0x4320, pci_subsys_14e4_4320_1737_4320, 0}; +#undef pci_ss_info_1737_4320 +#define pci_ss_info_1737_4320 pci_ss_info_14e4_4320_1737_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7001 = + {0x1799, 0x7001, pci_subsys_14e4_4320_1799_7001, 0}; +#undef pci_ss_info_1799_7001 +#define pci_ss_info_1799_7001 pci_ss_info_14e4_4320_1799_7001 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7010 = + {0x1799, 0x7010, pci_subsys_14e4_4320_1799_7010, 0}; +#undef pci_ss_info_1799_7010 +#define pci_ss_info_1799_7010 pci_ss_info_14e4_4320_1799_7010 +static const pciSubsystemInfo pci_ss_info_14e4_4320_185f_1220 = + {0x185f, 0x1220, pci_subsys_14e4_4320_185f_1220, 0}; +#undef pci_ss_info_185f_1220 +#define pci_ss_info_185f_1220 pci_ss_info_14e4_4320_185f_1220 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4324_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4324_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4324_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4324_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0003 = + {0x1414, 0x0003, pci_subsys_14e4_4325_1414_0003, 0}; +#undef pci_ss_info_1414_0003 +#define pci_ss_info_1414_0003 pci_ss_info_14e4_4325_1414_0003 +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0004 = + {0x1414, 0x0004, pci_subsys_14e4_4325_1414_0004, 0}; +#undef pci_ss_info_1414_0004 +#define pci_ss_info_1414_0004 pci_ss_info_14e4_4325_1414_0004 +static const pciSubsystemInfo pci_ss_info_14e4_4401_1043_80a8 = + {0x1043, 0x80a8, pci_subsys_14e4_4401_1043_80a8, 0}; +#undef pci_ss_info_1043_80a8 +#define pci_ss_info_1043_80a8 pci_ss_info_14e4_4401_1043_80a8 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2045_14f1_2045 = + {0x14f1, 0x2045, pci_subsys_14f1_2045_14f1_2045, 0}; +#undef pci_ss_info_14f1_2045 +#define pci_ss_info_14f1_2045 pci_ss_info_14f1_2045_14f1_2045 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8800_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8800_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8800_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8800_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9001 = + {0x0070, 0x9001, pci_subsys_14f1_8800_0070_9001, 0}; +#undef pci_ss_info_0070_9001 +#define pci_ss_info_0070_9001 pci_ss_info_14f1_8800_0070_9001 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9200 = + {0x0070, 0x9200, pci_subsys_14f1_8800_0070_9200, 0}; +#undef pci_ss_info_0070_9200 +#define pci_ss_info_0070_9200 pci_ss_info_14f1_8800_0070_9200 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9202 = + {0x0070, 0x9202, pci_subsys_14f1_8800_0070_9202, 0}; +#undef pci_ss_info_0070_9202 +#define pci_ss_info_0070_9202 pci_ss_info_14f1_8800_0070_9202 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9402 = + {0x0070, 0x9402, pci_subsys_14f1_8800_0070_9402, 0}; +#undef pci_ss_info_0070_9402 +#define pci_ss_info_0070_9402 pci_ss_info_14f1_8800_0070_9402 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9802 = + {0x0070, 0x9802, pci_subsys_14f1_8800_0070_9802, 0}; +#undef pci_ss_info_0070_9802 +#define pci_ss_info_0070_9802 pci_ss_info_14f1_8800_0070_9802 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_00f8 = + {0x1002, 0x00f8, pci_subsys_14f1_8800_1002_00f8, 0}; +#undef pci_ss_info_1002_00f8 +#define pci_ss_info_1002_00f8 pci_ss_info_14f1_8800_1002_00f8 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_a101 = + {0x1002, 0xa101, pci_subsys_14f1_8800_1002_a101, 0}; +#undef pci_ss_info_1002_a101 +#define pci_ss_info_1002_a101 pci_ss_info_14f1_8800_1002_a101 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_8800_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8800_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8800_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6613 = + {0x107d, 0x6613, pci_subsys_14f1_8800_107d_6613, 0}; +#undef pci_ss_info_107d_6613 +#define pci_ss_info_107d_6613 pci_ss_info_14f1_8800_107d_6613 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6620 = + {0x107d, 0x6620, pci_subsys_14f1_8800_107d_6620, 0}; +#undef pci_ss_info_107d_6620 +#define pci_ss_info_107d_6620 pci_ss_info_14f1_8800_107d_6620 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8800_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8800_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_665f = + {0x107d, 0x665f, pci_subsys_14f1_8800_107d_665f, 0}; +#undef pci_ss_info_107d_665f +#define pci_ss_info_107d_665f pci_ss_info_14f1_8800_107d_665f +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d003 = + {0x10fc, 0xd003, pci_subsys_14f1_8800_10fc_d003, 0}; +#undef pci_ss_info_10fc_d003 +#define pci_ss_info_10fc_d003 pci_ss_info_14f1_8800_10fc_d003 +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d035 = + {0x10fc, 0xd035, pci_subsys_14f1_8800_10fc_d035, 0}; +#undef pci_ss_info_10fc_d035 +#define pci_ss_info_10fc_d035 pci_ss_info_14f1_8800_10fc_d035 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1421_0334 = + {0x1421, 0x0334, pci_subsys_14f1_8800_1421_0334, 0}; +#undef pci_ss_info_1421_0334 +#define pci_ss_info_1421_0334 pci_ss_info_14f1_8800_1421_0334 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000a = + {0x1461, 0x000a, pci_subsys_14f1_8800_1461_000a, 0}; +#undef pci_ss_info_1461_000a +#define pci_ss_info_1461_000a pci_ss_info_14f1_8800_1461_000a +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000b = + {0x1461, 0x000b, pci_subsys_14f1_8800_1461_000b, 0}; +#undef pci_ss_info_1461_000b +#define pci_ss_info_1461_000b pci_ss_info_14f1_8800_1461_000b +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_8011 = + {0x1461, 0x8011, pci_subsys_14f1_8800_1461_8011, 0}; +#undef pci_ss_info_1461_8011 +#define pci_ss_info_1461_8011 pci_ss_info_14f1_8800_1461_8011 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8800_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8800_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14c7_0107 = + {0x14c7, 0x0107, pci_subsys_14f1_8800_14c7_0107, 0}; +#undef pci_ss_info_14c7_0107 +#define pci_ss_info_14c7_0107 pci_ss_info_14f1_8800_14c7_0107 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8800_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8800_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0342 = + {0x14f1, 0x0342, pci_subsys_14f1_8800_14f1_0342, 0}; +#undef pci_ss_info_14f1_0342 +#define pci_ss_info_14f1_0342 pci_ss_info_14f1_8800_14f1_0342 +static const pciSubsystemInfo pci_ss_info_14f1_8800_153b_1166 = + {0x153b, 0x1166, pci_subsys_14f1_8800_153b_1166, 0}; +#undef pci_ss_info_153b_1166 +#define pci_ss_info_153b_1166 pci_ss_info_14f1_8800_153b_1166 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1540_2580 = + {0x1540, 0x2580, pci_subsys_14f1_8800_1540_2580, 0}; +#undef pci_ss_info_1540_2580 +#define pci_ss_info_1540_2580 pci_ss_info_14f1_8800_1540_2580 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4811 = + {0x1554, 0x4811, pci_subsys_14f1_8800_1554_4811, 0}; +#undef pci_ss_info_1554_4811 +#define pci_ss_info_1554_4811 pci_ss_info_14f1_8800_1554_4811 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4813 = + {0x1554, 0x4813, pci_subsys_14f1_8800_1554_4813, 0}; +#undef pci_ss_info_1554_4813 +#define pci_ss_info_1554_4813 pci_ss_info_14f1_8800_1554_4813 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8800_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8800_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8800_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8800_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08b2 = + {0x17de, 0x08b2, pci_subsys_14f1_8800_17de_08b2, 0}; +#undef pci_ss_info_17de_08b2 +#define pci_ss_info_17de_08b2 pci_ss_info_14f1_8800_17de_08b2 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_a8a6 = + {0x17de, 0xa8a6, pci_subsys_14f1_8800_17de_a8a6, 0}; +#undef pci_ss_info_17de_a8a6 +#define pci_ss_info_17de_a8a6 pci_ss_info_14f1_8800_17de_a8a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1822_0025 = + {0x1822, 0x0025, pci_subsys_14f1_8800_1822_0025, 0}; +#undef pci_ss_info_1822_0025 +#define pci_ss_info_1822_0025 pci_ss_info_14f1_8800_1822_0025 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8800_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8800_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8800_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8800_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8800_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8800_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8800_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8800_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db11 = + {0x18ac, 0xdb11, pci_subsys_14f1_8800_18ac_db11, 0}; +#undef pci_ss_info_18ac_db11 +#define pci_ss_info_18ac_db11 pci_ss_info_14f1_8800_18ac_db11 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db50 = + {0x18ac, 0xdb50, pci_subsys_14f1_8800_18ac_db50, 0}; +#undef pci_ss_info_18ac_db50 +#define pci_ss_info_18ac_db50 pci_ss_info_14f1_8800_18ac_db50 +static const pciSubsystemInfo pci_ss_info_14f1_8800_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8800_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8800_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8801_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8801_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8801_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8802_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8802_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8802_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8802_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8802_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8802_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8802_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8802_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8802_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8802_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8802_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8802_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8802_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8802_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8802_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8802_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8802_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8802_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8802_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8802_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8802_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8802_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8802_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8802_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8802_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8802_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8802_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8802_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8802_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8802_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8804_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8804_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8804_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8811_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8811_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8811_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8811_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8811_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8811_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8811_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8811_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8811_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8811_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8811_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8811_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8811_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8811_18ac_db00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0c00 = + {0x1522, 0x0c00, pci_subsys_1522_0100_1522_0c00, 0}; +#undef pci_ss_info_1522_0c00 +#define pci_ss_info_1522_0c00 pci_ss_info_1522_0100_1522_0c00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0d00 = + {0x1522, 0x0d00, pci_subsys_1522_0100_1522_0d00, 0}; +#undef pci_ss_info_1522_0d00 +#define pci_ss_info_1522_0d00 pci_ss_info_1522_0100_1522_0d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_1d00 = + {0x1522, 0x1d00, pci_subsys_1522_0100_1522_1d00, 0}; +#undef pci_ss_info_1522_1d00 +#define pci_ss_info_1522_1d00 pci_ss_info_1522_0100_1522_1d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2000 = + {0x1522, 0x2000, pci_subsys_1522_0100_1522_2000, 0}; +#undef pci_ss_info_1522_2000 +#define pci_ss_info_1522_2000 pci_ss_info_1522_0100_1522_2000 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2100 = + {0x1522, 0x2100, pci_subsys_1522_0100_1522_2100, 0}; +#undef pci_ss_info_1522_2100 +#define pci_ss_info_1522_2100 pci_ss_info_1522_0100_1522_2100 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2200 = + {0x1522, 0x2200, pci_subsys_1522_0100_1522_2200, 0}; +#undef pci_ss_info_1522_2200 +#define pci_ss_info_1522_2200 pci_ss_info_1522_0100_1522_2200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2300 = + {0x1522, 0x2300, pci_subsys_1522_0100_1522_2300, 0}; +#undef pci_ss_info_1522_2300 +#define pci_ss_info_1522_2300 pci_ss_info_1522_0100_1522_2300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2400 = + {0x1522, 0x2400, pci_subsys_1522_0100_1522_2400, 0}; +#undef pci_ss_info_1522_2400 +#define pci_ss_info_1522_2400 pci_ss_info_1522_0100_1522_2400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2500 = + {0x1522, 0x2500, pci_subsys_1522_0100_1522_2500, 0}; +#undef pci_ss_info_1522_2500 +#define pci_ss_info_1522_2500 pci_ss_info_1522_0100_1522_2500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2600 = + {0x1522, 0x2600, pci_subsys_1522_0100_1522_2600, 0}; +#undef pci_ss_info_1522_2600 +#define pci_ss_info_1522_2600 pci_ss_info_1522_0100_1522_2600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2700 = + {0x1522, 0x2700, pci_subsys_1522_0100_1522_2700, 0}; +#undef pci_ss_info_1522_2700 +#define pci_ss_info_1522_2700 pci_ss_info_1522_0100_1522_2700 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_0510_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_0510_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_0510_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_005a = + {0x1025, 0x005a, pci_subsys_1524_1410_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1524_1410_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1411_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_1411_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_1411_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_167b_2102_187e_3406 = + {0x187e, 0x3406, pci_subsys_167b_2102_187e_3406, 0}; +#undef pci_ss_info_187e_3406 +#define pci_ss_info_187e_3406 pci_ss_info_167b_2102_187e_3406 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_168c_0013_1113_d301 = + {0x1113, 0xd301, pci_subsys_168c_0013_1113_d301, 0}; +#undef pci_ss_info_1113_d301 +#define pci_ss_info_1113_d301 pci_ss_info_168c_0013_1113_d301 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3202 = + {0x1186, 0x3202, pci_subsys_168c_0013_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_168c_0013_1186_3202 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3203 = + {0x1186, 0x3203, pci_subsys_168c_0013_1186_3203, 0}; +#undef pci_ss_info_1186_3203 +#define pci_ss_info_1186_3203 pci_ss_info_168c_0013_1186_3203 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a12 = + {0x1186, 0x3a12, pci_subsys_168c_0013_1186_3a12, 0}; +#undef pci_ss_info_1186_3a12 +#define pci_ss_info_1186_3a12 pci_ss_info_168c_0013_1186_3a12 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a13 = + {0x1186, 0x3a13, pci_subsys_168c_0013_1186_3a13, 0}; +#undef pci_ss_info_1186_3a13 +#define pci_ss_info_1186_3a13 pci_ss_info_168c_0013_1186_3a13 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a14 = + {0x1186, 0x3a14, pci_subsys_168c_0013_1186_3a14, 0}; +#undef pci_ss_info_1186_3a14 +#define pci_ss_info_1186_3a14 pci_ss_info_168c_0013_1186_3a14 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a17 = + {0x1186, 0x3a17, pci_subsys_168c_0013_1186_3a17, 0}; +#undef pci_ss_info_1186_3a17 +#define pci_ss_info_1186_3a17 pci_ss_info_168c_0013_1186_3a17 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a18 = + {0x1186, 0x3a18, pci_subsys_168c_0013_1186_3a18, 0}; +#undef pci_ss_info_1186_3a18 +#define pci_ss_info_1186_3a18 pci_ss_info_168c_0013_1186_3a18 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a63 = + {0x1186, 0x3a63, pci_subsys_168c_0013_1186_3a63, 0}; +#undef pci_ss_info_1186_3a63 +#define pci_ss_info_1186_3a63 pci_ss_info_168c_0013_1186_3a63 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a94 = + {0x1186, 0x3a94, pci_subsys_168c_0013_1186_3a94, 0}; +#undef pci_ss_info_1186_3a94 +#define pci_ss_info_1186_3a94 pci_ss_info_168c_0013_1186_3a94 +static const pciSubsystemInfo pci_ss_info_168c_0013_1385_4d00 = + {0x1385, 0x4d00, pci_subsys_168c_0013_1385_4d00, 0}; +#undef pci_ss_info_1385_4d00 +#define pci_ss_info_1385_4d00 pci_ss_info_168c_0013_1385_4d00 +static const pciSubsystemInfo pci_ss_info_168c_0013_1458_e911 = + {0x1458, 0xe911, pci_subsys_168c_0013_1458_e911, 0}; +#undef pci_ss_info_1458_e911 +#define pci_ss_info_1458_e911 pci_ss_info_168c_0013_1458_e911 +static const pciSubsystemInfo pci_ss_info_168c_0013_14b7_0a60 = + {0x14b7, 0x0a60, pci_subsys_168c_0013_14b7_0a60, 0}; +#undef pci_ss_info_14b7_0a60 +#define pci_ss_info_14b7_0a60 pci_ss_info_168c_0013_14b7_0a60 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_0013 = + {0x168c, 0x0013, pci_subsys_168c_0013_168c_0013, 0}; +#undef pci_ss_info_168c_0013 +#define pci_ss_info_168c_0013 pci_ss_info_168c_0013_168c_0013 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1025 = + {0x168c, 0x1025, pci_subsys_168c_0013_168c_1025, 0}; +#undef pci_ss_info_168c_1025 +#define pci_ss_info_168c_1025 pci_ss_info_168c_0013_168c_1025 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1027 = + {0x168c, 0x1027, pci_subsys_168c_0013_168c_1027, 0}; +#undef pci_ss_info_168c_1027 +#define pci_ss_info_168c_1027 pci_ss_info_168c_0013_168c_1027 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2026 = + {0x168c, 0x2026, pci_subsys_168c_0013_168c_2026, 0}; +#undef pci_ss_info_168c_2026 +#define pci_ss_info_168c_2026 pci_ss_info_168c_0013_168c_2026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2041 = + {0x168c, 0x2041, pci_subsys_168c_0013_168c_2041, 0}; +#undef pci_ss_info_168c_2041 +#define pci_ss_info_168c_2041 pci_ss_info_168c_0013_168c_2041 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2042 = + {0x168c, 0x2042, pci_subsys_168c_0013_168c_2042, 0}; +#undef pci_ss_info_168c_2042 +#define pci_ss_info_168c_2042 pci_ss_info_168c_0013_168c_2042 +static const pciSubsystemInfo pci_ss_info_168c_0013_16ab_7302 = + {0x16ab, 0x7302, pci_subsys_168c_0013_16ab_7302, 0}; +#undef pci_ss_info_16ab_7302 +#define pci_ss_info_16ab_7302 pci_ss_info_168c_0013_16ab_7302 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a15 = + {0x1186, 0x3a15, pci_subsys_168c_001a_1186_3a15, 0}; +#undef pci_ss_info_1186_3a15 +#define pci_ss_info_1186_3a15 pci_ss_info_168c_001a_1186_3a15 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a16 = + {0x1186, 0x3a16, pci_subsys_168c_001a_1186_3a16, 0}; +#undef pci_ss_info_1186_3a16 +#define pci_ss_info_1186_3a16 pci_ss_info_168c_001a_1186_3a16 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a23 = + {0x1186, 0x3a23, pci_subsys_168c_001a_1186_3a23, 0}; +#undef pci_ss_info_1186_3a23 +#define pci_ss_info_1186_3a23 pci_ss_info_168c_001a_1186_3a23 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a24 = + {0x1186, 0x3a24, pci_subsys_168c_001a_1186_3a24, 0}; +#undef pci_ss_info_1186_3a24 +#define pci_ss_info_1186_3a24 pci_ss_info_168c_001a_1186_3a24 +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_1052 = + {0x168c, 0x1052, pci_subsys_168c_001a_168c_1052, 0}; +#undef pci_ss_info_168c_1052 +#define pci_ss_info_168c_1052 pci_ss_info_168c_001a_168c_1052 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a19 = + {0x1186, 0x3a19, pci_subsys_168c_001b_1186_3a19, 0}; +#undef pci_ss_info_1186_3a19 +#define pci_ss_info_1186_3a19 pci_ss_info_168c_001b_1186_3a19 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a22 = + {0x1186, 0x3a22, pci_subsys_168c_001b_1186_3a22, 0}; +#undef pci_ss_info_1186_3a22 +#define pci_ss_info_1186_3a22 pci_ss_info_168c_001b_1186_3a22 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0015 = + {0x1737, 0x0015, pci_subsys_1737_1032_1737_0015, 0}; +#undef pci_ss_info_1737_0015 +#define pci_ss_info_1737_0015 pci_ss_info_1737_1032_1737_0015 +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0024 = + {0x1737, 0x0024, pci_subsys_1737_1032_1737_0024, 0}; +#undef pci_ss_info_1737_0024 +#define pci_ss_info_1737_0024 pci_ss_info_1737_1032_1737_0024 +static const pciSubsystemInfo pci_ss_info_1737_1064_1737_0016 = + {0x1737, 0x0016, pci_subsys_1737_1064_1737_0016, 0}; +#undef pci_ss_info_1737_0016 +#define pci_ss_info_1737_0016 pci_ss_info_1737_1064_1737_0016 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_17d5_5831_103c_12d5 = + {0x103c, 0x12d5, pci_subsys_17d5_5831_103c_12d5, 0}; +#undef pci_ss_info_103c_12d5 +#define pci_ss_info_103c_12d5 pci_ss_info_17d5_5831_103c_12d5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17fe_2220_17fe_2220 = + {0x17fe, 0x2220, pci_subsys_17fe_2220_17fe_2220, 0}; +#undef pci_ss_info_17fe_2220 +#define pci_ss_info_17fe_2220 pci_ss_info_17fe_2220_17fe_2220 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1814_0101_1043_0127 = + {0x1043, 0x0127, pci_subsys_1814_0101_1043_0127, 0}; +#undef pci_ss_info_1043_0127 +#define pci_ss_info_1043_0127 pci_ss_info_1814_0101_1043_0127 +static const pciSubsystemInfo pci_ss_info_1814_0101_1462_6828 = + {0x1462, 0x6828, pci_subsys_1814_0101_1462_6828, 0}; +#undef pci_ss_info_1462_6828 +#define pci_ss_info_1462_6828 pci_ss_info_1814_0101_1462_6828 +static const pciSubsystemInfo pci_ss_info_1814_0201_1043_130f = + {0x1043, 0x130f, pci_subsys_1814_0201_1043_130f, 0}; +#undef pci_ss_info_1043_130f +#define pci_ss_info_1043_130f pci_ss_info_1814_0201_1043_130f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001e = + {0x1371, 0x001e, pci_subsys_1814_0201_1371_001e, 0}; +#undef pci_ss_info_1371_001e +#define pci_ss_info_1371_001e pci_ss_info_1814_0201_1371_001e +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001f = + {0x1371, 0x001f, pci_subsys_1814_0201_1371_001f, 0}; +#undef pci_ss_info_1371_001f +#define pci_ss_info_1371_001f pci_ss_info_1814_0201_1371_001f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_0020 = + {0x1371, 0x0020, pci_subsys_1814_0201_1371_0020, 0}; +#undef pci_ss_info_1371_0020 +#define pci_ss_info_1371_0020 pci_ss_info_1814_0201_1371_0020 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e381 = + {0x1458, 0xe381, pci_subsys_1814_0201_1458_e381, 0}; +#undef pci_ss_info_1458_e381 +#define pci_ss_info_1458_e381 pci_ss_info_1814_0201_1458_e381 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e931 = + {0x1458, 0xe931, pci_subsys_1814_0201_1458_e931, 0}; +#undef pci_ss_info_1458_e931 +#define pci_ss_info_1458_e931 pci_ss_info_1814_0201_1458_e931 +static const pciSubsystemInfo pci_ss_info_1814_0201_1462_6835 = + {0x1462, 0x6835, pci_subsys_1814_0201_1462_6835, 0}; +#undef pci_ss_info_1462_6835 +#define pci_ss_info_1462_6835 pci_ss_info_1814_0201_1462_6835 +static const pciSubsystemInfo pci_ss_info_1814_0201_1737_0032 = + {0x1737, 0x0032, pci_subsys_1814_0201_1737_0032, 0}; +#undef pci_ss_info_1737_0032 +#define pci_ss_info_1737_0032 pci_ss_info_1814_0201_1737_0032 +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_700a = + {0x1799, 0x700a, pci_subsys_1814_0201_1799_700a, 0}; +#undef pci_ss_info_1799_700a +#define pci_ss_info_1799_700a pci_ss_info_1814_0201_1799_700a +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_701a = + {0x1799, 0x701a, pci_subsys_1814_0201_1799_701a, 0}; +#undef pci_ss_info_1799_701a +#define pci_ss_info_1799_701a pci_ss_info_1814_0201_1799_701a +static const pciSubsystemInfo pci_ss_info_1814_0201_185f_22a0 = + {0x185f, 0x22a0, pci_subsys_1814_0201_185f_22a0, 0}; +#undef pci_ss_info_185f_22a0 +#define pci_ss_info_185f_22a0 pci_ss_info_1814_0201_185f_22a0 +static const pciSubsystemInfo pci_ss_info_1814_0301_2561_1814 = + {0x2561, 0x1814, pci_subsys_1814_0301_2561_1814, 0}; +#undef pci_ss_info_2561_1814 +#define pci_ss_info_2561_1814 pci_ss_info_1814_0301_2561_1814 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c006_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c006_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c006_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c006_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c006_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c006_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c006_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c006_18ec_d004 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c058_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c058_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c058_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c058_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c058_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c058_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c058_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c058_18ec_d004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_3388_0021_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_3388_0021_4c53_1050 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_3388_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_3388_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_3388_0021_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_3388_0021_4c53_1090 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_3388_0021_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_3388_0021_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3010 = + {0x4c53, 0x3010, pci_subsys_3388_0021_4c53_3010, 0}; +#undef pci_ss_info_4c53_3010 +#define pci_ss_info_4c53_3010 pci_ss_info_3388_0021_4c53_3010 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3011 = + {0x4c53, 0x3011, pci_subsys_3388_0021_4c53_3011, 0}; +#undef pci_ss_info_4c53_3011 +#define pci_ss_info_4c53_3011 pci_ss_info_3388_0021_4c53_3011 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_4000 = + {0x4c53, 0x4000, pci_subsys_3388_0021_4c53_4000, 0}; +#undef pci_ss_info_4c53_4000 +#define pci_ss_info_4c53_4000 pci_ss_info_3388_0021_4c53_4000 +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0002_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0002_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0002_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0003_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0003_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0003_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0006_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0006_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0006_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0006_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0008_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0008_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0008_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0009_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0009_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_3d3d_0009_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_3d3d_0009_13e9_1000 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0003 = + {0x0070, 0x0003, pci_subsys_4444_0016_0070_0003, 0}; +#undef pci_ss_info_0070_0003 +#define pci_ss_info_0070_0003 pci_ss_info_4444_0016_0070_0003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0009 = + {0x0070, 0x0009, pci_subsys_4444_0016_0070_0009, 0}; +#undef pci_ss_info_0070_0009 +#define pci_ss_info_0070_0009 pci_ss_info_4444_0016_0070_0009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0801 = + {0x0070, 0x0801, pci_subsys_4444_0016_0070_0801, 0}; +#undef pci_ss_info_0070_0801 +#define pci_ss_info_0070_0801 pci_ss_info_4444_0016_0070_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0807 = + {0x0070, 0x0807, pci_subsys_4444_0016_0070_0807, 0}; +#undef pci_ss_info_0070_0807 +#define pci_ss_info_0070_0807 pci_ss_info_4444_0016_0070_0807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0016_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0016_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4009 = + {0x0070, 0x4009, pci_subsys_4444_0016_0070_4009, 0}; +#undef pci_ss_info_0070_4009 +#define pci_ss_info_0070_4009 pci_ss_info_4444_0016_0070_4009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4801 = + {0x0070, 0x4801, pci_subsys_4444_0016_0070_4801, 0}; +#undef pci_ss_info_0070_4801 +#define pci_ss_info_0070_4801 pci_ss_info_4444_0016_0070_4801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4803 = + {0x0070, 0x4803, pci_subsys_4444_0016_0070_4803, 0}; +#undef pci_ss_info_0070_4803 +#define pci_ss_info_0070_4803 pci_ss_info_4444_0016_0070_4803 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8003 = + {0x0070, 0x8003, pci_subsys_4444_0016_0070_8003, 0}; +#undef pci_ss_info_0070_8003 +#define pci_ss_info_0070_8003 pci_ss_info_4444_0016_0070_8003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8801 = + {0x0070, 0x8801, pci_subsys_4444_0016_0070_8801, 0}; +#undef pci_ss_info_0070_8801 +#define pci_ss_info_0070_8801 pci_ss_info_4444_0016_0070_8801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_c801 = + {0x0070, 0xc801, pci_subsys_4444_0016_0070_c801, 0}; +#undef pci_ss_info_0070_c801 +#define pci_ss_info_0070_c801 pci_ss_info_4444_0016_0070_c801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e807 = + {0x0070, 0xe807, pci_subsys_4444_0016_0070_e807, 0}; +#undef pci_ss_info_0070_e807 +#define pci_ss_info_0070_e807 pci_ss_info_4444_0016_0070_e807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e817 = + {0x0070, 0xe817, pci_subsys_4444_0016_0070_e817, 0}; +#undef pci_ss_info_0070_e817 +#define pci_ss_info_0070_e817 pci_ss_info_4444_0016_0070_e817 +static const pciSubsystemInfo pci_ss_info_4444_0016_0270_0801 = + {0x0270, 0x0801, pci_subsys_4444_0016_0270_0801, 0}; +#undef pci_ss_info_0270_0801 +#define pci_ss_info_0270_0801 pci_ss_info_4444_0016_0270_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_fff3 = + {0x12ab, 0xfff3, pci_subsys_4444_0016_12ab_fff3, 0}; +#undef pci_ss_info_12ab_fff3 +#define pci_ss_info_12ab_fff3 pci_ss_info_4444_0016_12ab_fff3 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_ffff = + {0x12ab, 0xffff, pci_subsys_4444_0016_12ab_ffff, 0}; +#undef pci_ss_info_12ab_ffff +#define pci_ss_info_12ab_ffff pci_ss_info_4444_0016_12ab_ffff +static const pciSubsystemInfo pci_ss_info_4444_0016_4070_8801 = + {0x4070, 0x8801, pci_subsys_4444_0016_4070_8801, 0}; +#undef pci_ss_info_4070_8801 +#define pci_ss_info_4070_8801 pci_ss_info_4444_0016_4070_8801 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0092 = + {0x9005, 0x0092, pci_subsys_4444_0016_9005_0092, 0}; +#undef pci_ss_info_9005_0092 +#define pci_ss_info_9005_0092 pci_ss_info_4444_0016_9005_0092 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0093 = + {0x9005, 0x0093, pci_subsys_4444_0016_9005_0093, 0}; +#undef pci_ss_info_9005_0093 +#define pci_ss_info_9005_0093 pci_ss_info_4444_0016_9005_0093 +static const pciSubsystemInfo pci_ss_info_4444_0016_ff92_0070 = + {0xff92, 0x0070, pci_subsys_4444_0016_ff92_0070, 0}; +#undef pci_ss_info_ff92_0070 +#define pci_ss_info_ff92_0070 pci_ss_info_4444_0016_ff92_0070 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4000 = + {0x0070, 0x4000, pci_subsys_4444_0803_0070_4000, 0}; +#undef pci_ss_info_0070_4000 +#define pci_ss_info_0070_4000 pci_ss_info_4444_0803_0070_4000 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0803_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0803_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4800 = + {0x0070, 0x4800, pci_subsys_4444_0803_0070_4800, 0}; +#undef pci_ss_info_0070_4800 +#define pci_ss_info_0070_4800 pci_ss_info_4444_0803_0070_4800 +static const pciSubsystemInfo pci_ss_info_4444_0803_12ab_0000 = + {0x12ab, 0x0000, pci_subsys_4444_0803_12ab_0000, 0}; +#undef pci_ss_info_12ab_0000 +#define pci_ss_info_12ab_0000 pci_ss_info_4444_0803_12ab_0000 +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3ce = + {0x1461, 0xa3ce, pci_subsys_4444_0803_1461_a3ce, 0}; +#undef pci_ss_info_1461_a3ce +#define pci_ss_info_1461_a3ce pci_ss_info_4444_0803_1461_a3ce +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3cf = + {0x1461, 0xa3cf, pci_subsys_4444_0803_1461_a3cf, 0}; +#undef pci_ss_info_1461_a3cf +#define pci_ss_info_1461_a3cf pci_ss_info_4444_0803_1461_a3cf +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3000 = + {0x4c53, 0x3000, pci_subsys_4c53_0000_4c53_3000, 0}; +#undef pci_ss_info_4c53_3000 +#define pci_ss_info_4c53_3000 pci_ss_info_4c53_0000_4c53_3000 +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3001 = + {0x4c53, 0x3001, pci_subsys_4c53_0000_4c53_3001, 0}; +#undef pci_ss_info_4c53_3001 +#define pci_ss_info_4c53_3001 pci_ss_info_4c53_0000_4c53_3001 +static const pciSubsystemInfo pci_ss_info_4c53_0001_4c53_3002 = + {0x4c53, 0x3002, pci_subsys_4c53_0001_4c53_3002, 0}; +#undef pci_ss_info_4c53_3002 +#define pci_ss_info_4c53_3002 pci_ss_info_4c53_0001_4c53_3002 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8110 = + {0x1033, 0x8110, pci_subsys_5333_8a22_1033_8110, 0}; +#undef pci_ss_info_1033_8110 +#define pci_ss_info_1033_8110 pci_ss_info_5333_8a22_1033_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c12_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c12_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c12_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01af = + {0x8086, 0x01af, pci_subsys_8086_0600_8086_01af, 0}; +#undef pci_ss_info_8086_01af +#define pci_ss_info_8086_01af pci_ss_info_8086_0600_8086_01af +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01c1 = + {0x8086, 0x01c1, pci_subsys_8086_0600_8086_01c1, 0}; +#undef pci_ss_info_8086_01c1 +#define pci_ss_info_8086_01c1 pci_ss_info_8086_0600_8086_01c1 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01f7 = + {0x8086, 0x01f7, pci_subsys_8086_0600_8086_01f7, 0}; +#undef pci_ss_info_8086_01f7 +#define pci_ss_info_8086_01f7 pci_ss_info_8086_0600_8086_01f7 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1001_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1001_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_1008_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_1008_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_1008_1028_011c = + {0x1028, 0x011c, pci_subsys_8086_1008_1028_011c, 0}; +#undef pci_ss_info_1028_011c +#define pci_ss_info_1028_011c pci_ss_info_8086_1008_1028_011c +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_3108 = + {0x8086, 0x3108, pci_subsys_8086_1008_8086_3108, 0}; +#undef pci_ss_info_8086_3108 +#define pci_ss_info_8086_3108 pci_ss_info_8086_1008_8086_3108 +static const pciSubsystemInfo pci_ss_info_8086_1009_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1009_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1009_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100d_1028_0123 = + {0x1028, 0x0123, pci_subsys_8086_100d_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_8086_100d_1028_0123 +static const pciSubsystemInfo pci_ss_info_8086_100d_1079_891f = + {0x1079, 0x891f, pci_subsys_8086_100d_1079_891f, 0}; +#undef pci_ss_info_1079_891f +#define pci_ss_info_1079_891f pci_ss_info_8086_100d_1079_891f +static const pciSubsystemInfo pci_ss_info_8086_100d_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_100d_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_100d_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_100d_8086_110d = + {0x8086, 0x110d, pci_subsys_8086_100d_8086_110d, 0}; +#undef pci_ss_info_8086_110d +#define pci_ss_info_8086_110d pci_ss_info_8086_100d_8086_110d +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_100e_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_100e_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_100e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_100e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_100e_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_100e_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_100e_1024_0134 = + {0x1024, 0x0134, pci_subsys_8086_100e_1024_0134, 0}; +#undef pci_ss_info_1024_0134 +#define pci_ss_info_1024_0134 pci_ss_info_8086_100e_1024_0134 +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_002e = + {0x1028, 0x002e, pci_subsys_8086_100e_1028_002e, 0}; +#undef pci_ss_info_1028_002e +#define pci_ss_info_1028_002e pci_ss_info_8086_100e_1028_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0151 = + {0x1028, 0x0151, pci_subsys_8086_100e_1028_0151, 0}; +#undef pci_ss_info_1028_0151 +#define pci_ss_info_1028_0151 pci_ss_info_8086_100e_1028_0151 +static const pciSubsystemInfo pci_ss_info_8086_100e_107b_8920 = + {0x107b, 0x8920, pci_subsys_8086_100e_107b_8920, 0}; +#undef pci_ss_info_107b_8920 +#define pci_ss_info_107b_8920 pci_ss_info_8086_100e_107b_8920 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_100e_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_100e_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_100e_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_100e_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_100f_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_100f_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_028e = + {0x1014, 0x028e, pci_subsys_8086_100f_1014_028e, 0}; +#undef pci_ss_info_1014_028e +#define pci_ss_info_1014_028e pci_ss_info_8086_100f_1014_028e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_100f_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_100f_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_0e11_00db = + {0x0e11, 0x00db, pci_subsys_8086_1010_0e11_00db, 0}; +#undef pci_ss_info_0e11_00db +#define pci_ss_info_0e11_00db pci_ss_info_8086_1010_0e11_00db +static const pciSubsystemInfo pci_ss_info_8086_1010_1014_027c = + {0x1014, 0x027c, pci_subsys_8086_1010_1014_027c, 0}; +#undef pci_ss_info_1014_027c +#define pci_ss_info_1014_027c pci_ss_info_8086_1010_1014_027c +static const pciSubsystemInfo pci_ss_info_8086_1010_18fb_7872 = + {0x18fb, 0x7872, pci_subsys_8086_1010_18fb_7872, 0}; +#undef pci_ss_info_18fb_7872 +#define pci_ss_info_18fb_7872 pci_ss_info_8086_1010_18fb_7872 +static const pciSubsystemInfo pci_ss_info_8086_1010_1fc1_0026 = + {0x1fc1, 0x0026, pci_subsys_8086_1010_1fc1_0026, 0}; +#undef pci_ss_info_1fc1_0026 +#define pci_ss_info_1fc1_0026 pci_ss_info_8086_1010_1fc1_0026 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1010_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1010_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_1010_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_1010_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1010_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1010_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_1010_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_1010_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_1010_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_1010_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_1011_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1011_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1011_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1011_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1011_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1012_0e11_00dc = + {0x0e11, 0x00dc, pci_subsys_8086_1012_0e11_00dc, 0}; +#undef pci_ss_info_0e11_00dc +#define pci_ss_info_0e11_00dc pci_ss_info_8086_1012_0e11_00dc +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1013_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1013_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1013_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1013_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1113 = + {0x8086, 0x1113, pci_subsys_8086_1013_8086_1113, 0}; +#undef pci_ss_info_8086_1113 +#define pci_ss_info_8086_1113 pci_ss_info_8086_1013_8086_1113 +static const pciSubsystemInfo pci_ss_info_8086_1016_1014_052c = + {0x1014, 0x052c, pci_subsys_8086_1016_1014_052c, 0}; +#undef pci_ss_info_1014_052c +#define pci_ss_info_1014_052c pci_ss_info_8086_1016_1014_052c +static const pciSubsystemInfo pci_ss_info_8086_1016_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1016_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1016_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1016_8086_1016 = + {0x8086, 0x1016, pci_subsys_8086_1016_8086_1016, 0}; +#undef pci_ss_info_8086_1016 +#define pci_ss_info_8086_1016 pci_ss_info_8086_1016_8086_1016 +static const pciSubsystemInfo pci_ss_info_8086_1017_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1017_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1017_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1018_8086_1018 = + {0x8086, 0x1018, pci_subsys_8086_1018_8086_1018, 0}; +#undef pci_ss_info_8086_1018 +#define pci_ss_info_8086_1018 pci_ss_info_8086_1018_8086_1018 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_1019 = + {0x1458, 0x1019, pci_subsys_8086_1019_1458_1019, 0}; +#undef pci_ss_info_1458_1019 +#define pci_ss_info_1458_1019 pci_ss_info_8086_1019_1458_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_e000 = + {0x1458, 0xe000, pci_subsys_8086_1019_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_8086_1019_1458_e000 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_1019 = + {0x8086, 0x1019, pci_subsys_8086_1019_8086_1019, 0}; +#undef pci_ss_info_8086_1019 +#define pci_ss_info_8086_1019 pci_ss_info_8086_1019_8086_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_301f = + {0x8086, 0x301f, pci_subsys_8086_1019_8086_301f, 0}; +#undef pci_ss_info_8086_301f +#define pci_ss_info_8086_301f pci_ss_info_8086_1019_8086_301f +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1019_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1019_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_101d_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_101d_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_101d_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_101e_1014_0549 = + {0x1014, 0x0549, pci_subsys_8086_101e_1014_0549, 0}; +#undef pci_ss_info_1014_0549 +#define pci_ss_info_1014_0549 pci_ss_info_8086_101e_1014_0549 +static const pciSubsystemInfo pci_ss_info_8086_101e_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_101e_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_101e_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_101e_8086_101e = + {0x8086, 0x101e, pci_subsys_8086_101e_8086_101e, 0}; +#undef pci_ss_info_8086_101e +#define pci_ss_info_8086_101e pci_ss_info_8086_101e_8086_101e +static const pciSubsystemInfo pci_ss_info_8086_1026_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_1026_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_1026_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1026_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1026_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1026_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1026_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1026_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1026_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1026 = + {0x8086, 0x1026, pci_subsys_8086_1026_8086_1026, 0}; +#undef pci_ss_info_8086_1026 +#define pci_ss_info_8086_1026 pci_ss_info_8086_1026_8086_1026 +static const pciSubsystemInfo pci_ss_info_8086_1027_103c_3103 = + {0x103c, 0x3103, pci_subsys_8086_1027_103c_3103, 0}; +#undef pci_ss_info_103c_3103 +#define pci_ss_info_103c_3103 pci_ss_info_8086_1027_103c_3103 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1027_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1027_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1027_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1027_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1027_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1027_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1027 = + {0x8086, 0x1027, pci_subsys_8086_1027_8086_1027, 0}; +#undef pci_ss_info_8086_1027 +#define pci_ss_info_8086_1027 pci_ss_info_8086_1027_8086_1027 +static const pciSubsystemInfo pci_ss_info_8086_1028_8086_1028 = + {0x8086, 0x1028, pci_subsys_8086_1028_8086_1028, 0}; +#undef pci_ss_info_8086_1028 +#define pci_ss_info_8086_1028 pci_ss_info_8086_1028_8086_1028 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1031_813c_104d = + {0x813c, 0x104d, pci_subsys_8086_1031_813c_104d, 0}; +#undef pci_ss_info_813c_104d +#define pci_ss_info_813c_104d pci_ss_info_8086_1031_813c_104d +static const pciSubsystemInfo pci_ss_info_8086_1038_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_8086_1038_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_8086_1038_0e11_0098 +static const pciSubsystemInfo pci_ss_info_8086_1039_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_1039_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_1039_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1043_8086_2527 = + {0x8086, 0x2527, pci_subsys_8086_1043_8086_2527, 0}; +#undef pci_ss_info_8086_2527 +#define pci_ss_info_8086_2527 pci_ss_info_8086_1043_8086_2527 +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a01f = + {0x8086, 0xa01f, pci_subsys_8086_1048_8086_a01f, 0}; +#undef pci_ss_info_8086_a01f +#define pci_ss_info_8086_a01f pci_ss_info_8086_1048_8086_a01f +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a11f = + {0x8086, 0xa11f, pci_subsys_8086_1048_8086_a11f, 0}; +#undef pci_ss_info_8086_a11f +#define pci_ss_info_8086_a11f pci_ss_info_8086_1048_8086_a11f +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_728c = + {0x1462, 0x728c, pci_subsys_8086_1050_1462_728c, 0}; +#undef pci_ss_info_1462_728c +#define pci_ss_info_1462_728c pci_ss_info_8086_1050_1462_728c +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_758c = + {0x1462, 0x758c, pci_subsys_8086_1050_1462_758c, 0}; +#undef pci_ss_info_1462_758c +#define pci_ss_info_1462_758c pci_ss_info_8086_1050_1462_758c +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3020 = + {0x8086, 0x3020, pci_subsys_8086_1050_8086_3020, 0}; +#undef pci_ss_info_8086_3020 +#define pci_ss_info_8086_3020 pci_ss_info_8086_1050_8086_3020 +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_302f = + {0x8086, 0x302f, pci_subsys_8086_1050_8086_302f, 0}; +#undef pci_ss_info_8086_302f +#define pci_ss_info_8086_302f pci_ss_info_8086_1050_8086_302f +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1050_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1050_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_1064_1043_80f8 = + {0x1043, 0x80f8, pci_subsys_8086_1064_1043_80f8, 0}; +#undef pci_ss_info_1043_80f8 +#define pci_ss_info_1043_80f8 pci_ss_info_8086_1064_1043_80f8 +static const pciSubsystemInfo pci_ss_info_8086_1075_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1075_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1075_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_0075 = + {0x8086, 0x0075, pci_subsys_8086_1075_8086_0075, 0}; +#undef pci_ss_info_8086_0075 +#define pci_ss_info_8086_0075 pci_ss_info_8086_1075_8086_0075 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_1075 = + {0x8086, 0x1075, pci_subsys_8086_1075_8086_1075, 0}; +#undef pci_ss_info_8086_1075 +#define pci_ss_info_8086_1075 pci_ss_info_8086_1075_8086_1075 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1076_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1076_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_1076_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_1076_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_0076 = + {0x8086, 0x0076, pci_subsys_8086_1076_8086_0076, 0}; +#undef pci_ss_info_8086_0076 +#define pci_ss_info_8086_0076 pci_ss_info_8086_1076_8086_0076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1076 = + {0x8086, 0x1076, pci_subsys_8086_1076_8086_1076, 0}; +#undef pci_ss_info_8086_1076 +#define pci_ss_info_8086_1076 pci_ss_info_8086_1076_8086_1076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1176 = + {0x8086, 0x1176, pci_subsys_8086_1076_8086_1176, 0}; +#undef pci_ss_info_8086_1176 +#define pci_ss_info_8086_1176 pci_ss_info_8086_1076_8086_1176 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1276 = + {0x8086, 0x1276, pci_subsys_8086_1076_8086_1276, 0}; +#undef pci_ss_info_8086_1276 +#define pci_ss_info_8086_1276 pci_ss_info_8086_1076_8086_1276 +static const pciSubsystemInfo pci_ss_info_8086_1077_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1077_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1077_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_0077 = + {0x8086, 0x0077, pci_subsys_8086_1077_8086_0077, 0}; +#undef pci_ss_info_8086_0077 +#define pci_ss_info_8086_0077 pci_ss_info_8086_1077_8086_0077 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_1077 = + {0x8086, 0x1077, pci_subsys_8086_1077_8086_1077, 0}; +#undef pci_ss_info_8086_1077 +#define pci_ss_info_8086_1077 pci_ss_info_8086_1077_8086_1077 +static const pciSubsystemInfo pci_ss_info_8086_1078_8086_1078 = + {0x8086, 0x1078, pci_subsys_8086_1078_8086_1078, 0}; +#undef pci_ss_info_8086_1078 +#define pci_ss_info_8086_1078 pci_ss_info_8086_1078_8086_1078 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12a6 = + {0x103c, 0x12a6, pci_subsys_8086_1079_103c_12a6, 0}; +#undef pci_ss_info_103c_12a6 +#define pci_ss_info_103c_12a6 pci_ss_info_8086_1079_103c_12a6 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12cf = + {0x103c, 0x12cf, pci_subsys_8086_1079_103c_12cf, 0}; +#undef pci_ss_info_103c_12cf +#define pci_ss_info_103c_12cf pci_ss_info_8086_1079_103c_12cf +static const pciSubsystemInfo pci_ss_info_8086_1079_1fc1_0027 = + {0x1fc1, 0x0027, pci_subsys_8086_1079_1fc1_0027, 0}; +#undef pci_ss_info_1fc1_0027 +#define pci_ss_info_1fc1_0027 pci_ss_info_8086_1079_1fc1_0027 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1079_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1079_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_1079_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_1079_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_0079 = + {0x8086, 0x0079, pci_subsys_8086_1079_8086_0079, 0}; +#undef pci_ss_info_8086_0079 +#define pci_ss_info_8086_0079 pci_ss_info_8086_1079_8086_0079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1079 = + {0x8086, 0x1079, pci_subsys_8086_1079_8086_1079, 0}; +#undef pci_ss_info_8086_1079 +#define pci_ss_info_8086_1079 pci_ss_info_8086_1079_8086_1079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1179 = + {0x8086, 0x1179, pci_subsys_8086_1079_8086_1179, 0}; +#undef pci_ss_info_8086_1179 +#define pci_ss_info_8086_1179 pci_ss_info_8086_1079_8086_1179 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_117a = + {0x8086, 0x117a, pci_subsys_8086_1079_8086_117a, 0}; +#undef pci_ss_info_8086_117a +#define pci_ss_info_8086_117a pci_ss_info_8086_1079_8086_117a +static const pciSubsystemInfo pci_ss_info_8086_107a_103c_12a8 = + {0x103c, 0x12a8, pci_subsys_8086_107a_103c_12a8, 0}; +#undef pci_ss_info_103c_12a8 +#define pci_ss_info_103c_12a8 pci_ss_info_8086_107a_103c_12a8 +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_107a = + {0x8086, 0x107a, pci_subsys_8086_107a_8086_107a, 0}; +#undef pci_ss_info_8086_107a +#define pci_ss_info_8086_107a pci_ss_info_8086_107a_8086_107a +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_127a = + {0x8086, 0x127a, pci_subsys_8086_107a_8086_127a, 0}; +#undef pci_ss_info_8086_127a +#define pci_ss_info_8086_127a pci_ss_info_8086_107a_8086_127a +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_007b = + {0x8086, 0x007b, pci_subsys_8086_107b_8086_007b, 0}; +#undef pci_ss_info_8086_007b +#define pci_ss_info_8086_007b pci_ss_info_8086_107b_8086_007b +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_107b = + {0x8086, 0x107b, pci_subsys_8086_107b_8086_107b, 0}; +#undef pci_ss_info_8086_107b +#define pci_ss_info_8086_107b pci_ss_info_8086_107b_8086_107b +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1130_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1130_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1130_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1130_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1132_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1132_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_1132_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_1132_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1132_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1132_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_1209_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_1209_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_1209_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_1209_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1070 = + {0x4c53, 0x1070, pci_subsys_8086_1209_4c53_1070, 0}; +#undef pci_ss_info_4c53_1070 +#define pci_ss_info_4c53_1070 pci_ss_info_8086_1209_4c53_1070 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_00ce = + {0x1028, 0x00ce, pci_subsys_8086_1229_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_8086_1229_1028_00ce +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_108e_10cf = + {0x108e, 0x10cf, pci_subsys_8086_1229_108e_10cf, 0}; +#undef pci_ss_info_108e_10cf +#define pci_ss_info_108e_10cf pci_ss_info_8086_1229_108e_10cf +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_110a_008b = + {0x110a, 0x008b, pci_subsys_8086_1229_110a_008b, 0}; +#undef pci_ss_info_110a_008b +#define pci_ss_info_110a_008b pci_ss_info_8086_1229_110a_008b +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_8086_1229_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_8086_1229_13e9_1000 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1229_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1229_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_1229_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_1229_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3411 = + {0x8086, 0x3411, pci_subsys_8086_1229_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_8086_1229_8086_3411 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1461_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1461_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1461_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_8086_1960_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_8086_1960_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_8086_1960_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_8086_1960_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1040 = + {0xe4bf, 0x1040, pci_subsys_8086_1960_e4bf_1040, 0}; +#undef pci_ss_info_e4bf_1040 +#define pci_ss_info_e4bf_1040 pci_ss_info_8086_1960_e4bf_1040 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_3100 = + {0xe4bf, 0x3100, pci_subsys_8086_1960_e4bf_3100, 0}; +#undef pci_ss_info_e4bf_3100 +#define pci_ss_info_e4bf_3100 pci_ss_info_8086_1960_e4bf_3100 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1a30_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_1a30_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_1a30_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_110a_0051 = + {0x110a, 0x0051, pci_subsys_8086_2415_110a_0051, 0}; +#undef pci_ss_info_110a_0051 +#define pci_ss_info_110a_0051 pci_ss_info_8086_2415_110a_0051 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2415_1734_1025 = + {0x1734, 0x1025, pci_subsys_8086_2415_1734_1025, 0}; +#undef pci_ss_info_1734_1025 +#define pci_ss_info_1734_1025 pci_ss_info_8086_2415_1734_1025 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2442_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2442_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2442_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2442_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2442_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2442_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2442_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2442_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2442_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2443_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2443_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2443_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2443_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2443_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2443_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2444_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2444_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2444_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2444_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2444_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2444_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2444_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2445_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2445_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2448_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2448_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2448_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2448_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_2448_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_2448_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_2449_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_2449_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2449_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2449_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_2449_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_2449_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1179_ff01 = + {0x1179, 0xff01, pci_subsys_8086_2449_1179_ff01, 0}; +#undef pci_ss_info_1179_ff01 +#define pci_ss_info_1179_ff01 pci_ss_info_8086_2449_1179_ff01 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_244b_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_244b_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_244b_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_244b_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_244b_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_244b_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_244e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_244e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_244e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2482_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2482_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2482_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2482_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2482_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_2482_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_2482_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2484_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2484_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1013_5959 = + {0x1013, 0x5959, pci_subsys_8086_2485_1013_5959, 0}; +#undef pci_ss_info_1013_5959 +#define pci_ss_info_1013_5959 pci_ss_info_8086_2485_1013_5959 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_101f_1025 = + {0x101f, 0x1025, pci_subsys_8086_2486_101f_1025, 0}; +#undef pci_ss_info_101f_1025 +#define pci_ss_info_101f_1025 pci_ss_info_8086_2486_101f_1025 +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_2486_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_2486_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2487_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2487_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_248a_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_248a_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_248a_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_248a_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c0_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c0_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c2_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c2_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c2_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c2_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c2_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c2_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c2_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c2_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c2_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c2_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c2_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c2_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c2_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c2_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c2_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c2_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c2_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c2_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c2_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c2_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c2_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c2_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c2_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c2_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c2_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c2_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c3_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c3_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c3_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c3_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c3_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c3_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c3_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c3_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c3_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c3_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c3_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c3_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c3_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24c3_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24c3_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c3_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c3_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c3_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c3_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c3_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c4_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c4_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c4_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c4_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c4_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c4_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c4_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c4_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c4_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c4_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c4_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c4_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c4_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c4_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c4_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c4_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c4_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c4_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c4_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c4_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c4_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c4_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c4_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c5_0e11_00b8 = + {0x0e11, 0x00b8, pci_subsys_8086_24c5_0e11_00b8, 0}; +#undef pci_ss_info_0e11_00b8 +#define pci_ss_info_0e11_00b8 pci_ss_info_8086_24c5_0e11_00b8 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c5_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c5_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c5_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c5_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24c5_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24c5_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c5_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c5_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c5_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c5_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c5_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c5_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c5_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c5_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c5_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c5_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24c5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24c5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c5_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c5_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c6_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c6_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c6_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c6_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c6_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c6_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c6_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c6_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c6_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c6_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c6_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c7_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c7_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c7_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c7_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c7_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c7_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c7_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c7_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c7_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c7_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c7_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c7_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c7_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c7_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c7_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c7_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c7_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c7_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c7_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c7_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c7_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c7_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c7_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c7_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24ca_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24ca_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24ca_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24ca_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24ca_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24ca_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24ca_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24ca_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24ca_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24ca_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24ca_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24ca_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24ca_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24ca_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24ca_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24ca_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24ca_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cb_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cb_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cb_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cb_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24cb_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24cb_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cb_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cb_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24cc_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cc_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cc_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cd_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cd_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24cd_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24cd_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_011d = + {0x1028, 0x011d, pci_subsys_8086_24cd_1028_011d, 0}; +#undef pci_ss_info_1028_011d +#define pci_ss_info_1028_011d pci_ss_info_8086_24cd_1028_011d +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cd_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cd_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24cd_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24cd_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24cd_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24cd_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24cd_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24cd_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24cd_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24cd_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24cd_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24cd_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24cd_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24cd_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1509_1968 = + {0x1509, 0x1968, pci_subsys_8086_24cd_1509_1968, 0}; +#undef pci_ss_info_1509_1968 +#define pci_ss_info_1509_1968 pci_ss_info_8086_24cd_1509_1968 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cd_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cd_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cd_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cd_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d1_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d1_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d1_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d1_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d1_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d1_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d1_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d1_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d1_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d1_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1458_24d1 = + {0x1458, 0x24d1, pci_subsys_8086_24d1_1458_24d1, 0}; +#undef pci_ss_info_1458_24d1 +#define pci_ss_info_1458_24d1 pci_ss_info_8086_24d1_1458_24d1 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d1_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d1_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d1_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d1_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d1_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d1_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d1_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d1_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d1_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d1_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d1_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d2_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d2_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d2_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d2_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d2_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d2_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d2_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d2_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d2_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d2_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d2_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d2_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d2_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d2_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d2_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d2_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d2_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d2_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d2_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d2_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d2_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d2_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d2_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d2_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d2_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d2_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d2_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d2_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d2_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d2_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d2_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d3_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d3_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d3_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d3_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d3_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d3_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d3_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d3_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d3_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d3_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d3_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d3_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d3_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d3_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d3_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d3_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d3_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d3_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d3_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d3_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d4_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d4_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d4_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d4_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d4_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d4_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d4_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d4_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d4_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d4_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d4_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d4_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d4_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d4_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d4_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d4_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d4_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d4_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d4_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d4_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d4_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d4_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d4_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d4_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d4_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d4_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d4_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d4_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d4_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d4_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d4_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d5_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d5_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d5_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d5_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d5_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d5_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d5_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_80f3 = + {0x1043, 0x80f3, pci_subsys_8086_24d5_1043_80f3, 0}; +#undef pci_ss_info_1043_80f3 +#define pci_ss_info_1043_80f3 pci_ss_info_8086_24d5_1043_80f3 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_810f = + {0x1043, 0x810f, pci_subsys_8086_24d5_1043_810f, 0}; +#undef pci_ss_info_1043_810f +#define pci_ss_info_1043_810f pci_ss_info_8086_24d5_1043_810f +static const pciSubsystemInfo pci_ss_info_8086_24d5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24d5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24d5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_0080 = + {0x1462, 0x0080, pci_subsys_8086_24d5_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_8086_24d5_1462_0080 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d5_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d5_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_a000 = + {0x8086, 0xa000, pci_subsys_8086_24d5_8086_a000, 0}; +#undef pci_ss_info_8086_a000 +#define pci_ss_info_8086_a000 pci_ss_info_8086_24d5_8086_a000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e000 = + {0x8086, 0xe000, pci_subsys_8086_24d5_8086_e000, 0}; +#undef pci_ss_info_8086_e000 +#define pci_ss_info_8086_e000 pci_ss_info_8086_24d5_8086_e000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e001 = + {0x8086, 0xe001, pci_subsys_8086_24d5_8086_e001, 0}; +#undef pci_ss_info_8086_e001 +#define pci_ss_info_8086_e001 pci_ss_info_8086_24d5_8086_e001 +static const pciSubsystemInfo pci_ss_info_8086_24d6_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d6_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d6_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d7_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d7_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d7_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d7_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d7_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d7_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d7_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d7_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d7_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d7_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d7_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d7_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d7_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d7_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d7_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d7_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d7_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d7_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d7_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d7_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d7_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d7_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d7_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d7_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d7_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d7_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d7_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d7_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24db_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24db_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24db_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24db_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24db_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24db_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24db_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24db_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24db_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24db_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24db_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24db_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24db_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24db_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24db_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24db_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24db_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24db_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24db_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_24db_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_24db_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_24db_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24db_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24db_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24db_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24db_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24db_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_24db = + {0x8086, 0x24db, pci_subsys_8086_24db_8086_24db, 0}; +#undef pci_ss_info_8086_24db +#define pci_ss_info_8086_24db pci_ss_info_8086_24db_8086_24db +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24db_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24db_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24db_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24db_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24db_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24db_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24dd_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24dd_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24dd_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24dd_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24dd_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24dd_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24dd_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24dd_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24dd_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24dd_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24dd_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24dd_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24dd_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24dd_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24dd_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24dd_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_24dd_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_24dd_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24dd_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24dd_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24dd_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24dd_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24dd_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24dd_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24dd_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24dd_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24de_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24de_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24de_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24de_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24de_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24de_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24de_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24de_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24de_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24de_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24de_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24de_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24de_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24de_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24de_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24de_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24de_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24de_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24de_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24de_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24de_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24de_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24de_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24de_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24de_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24de_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24de_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2541_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2541_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_2541_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2541_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2541_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2544_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2544_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2544_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_254c_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_254c_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_254c_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_254c_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2560_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_2560_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_2560_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_2560_1458_2560 = + {0x1458, 0x2560, pci_subsys_8086_2560_1458_2560, 0}; +#undef pci_ss_info_1458_2560 +#define pci_ss_info_1458_2560 pci_ss_info_8086_2560_1458_2560 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_2562_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2562_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2562_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2570_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_2570_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_2570_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_2570_1043_80f2 = + {0x1043, 0x80f2, pci_subsys_8086_2570_1043_80f2, 0}; +#undef pci_ss_info_1043_80f2 +#define pci_ss_info_1043_80f2 pci_ss_info_8086_2570_1043_80f2 +static const pciSubsystemInfo pci_ss_info_8086_2570_1458_2570 = + {0x1458, 0x2570, pci_subsys_8086_2570_1458_2570, 0}; +#undef pci_ss_info_1458_2570 +#define pci_ss_info_1458_2570 pci_ss_info_8086_2570_1458_2570 +static const pciSubsystemInfo pci_ss_info_8086_2572_1028_019d = + {0x1028, 0x019d, pci_subsys_8086_2572_1028_019d, 0}; +#undef pci_ss_info_1028_019d +#define pci_ss_info_1028_019d pci_ss_info_8086_2572_1028_019d +static const pciSubsystemInfo pci_ss_info_8086_2572_1043_80a5 = + {0x1043, 0x80a5, pci_subsys_8086_2572_1043_80a5, 0}; +#undef pci_ss_info_1043_80a5 +#define pci_ss_info_1043_80a5 pci_ss_info_8086_2572_1043_80a5 +static const pciSubsystemInfo pci_ss_info_8086_2578_1458_2578 = + {0x1458, 0x2578, pci_subsys_8086_2578_1458_2578, 0}; +#undef pci_ss_info_1458_2578 +#define pci_ss_info_1458_2578 pci_ss_info_8086_2578_1458_2578 +static const pciSubsystemInfo pci_ss_info_8086_2578_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_2578_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_2578_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_2578_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_2578_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_2578_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1458_2580 = + {0x1458, 0x2580, pci_subsys_8086_2580_1458_2580, 0}; +#undef pci_ss_info_1458_2580 +#define pci_ss_info_1458_2580 pci_ss_info_8086_2580_1458_2580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2580_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2580_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2580_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2580_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2580_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2582_1028_1079 = + {0x1028, 0x1079, pci_subsys_8086_2582_1028_1079, 0}; +#undef pci_ss_info_1028_1079 +#define pci_ss_info_1028_1079 pci_ss_info_8086_2582_1028_1079 +static const pciSubsystemInfo pci_ss_info_8086_2582_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2582_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2582_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1458_2582 = + {0x1458, 0x2582, pci_subsys_8086_2582_1458_2582, 0}; +#undef pci_ss_info_1458_2582 +#define pci_ss_info_1458_2582 pci_ss_info_8086_2582_1458_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2582_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2582_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2590_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2590_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2590_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2590_a304_81b7 = + {0xa304, 0x81b7, pci_subsys_8086_2590_a304_81b7, 0}; +#undef pci_ss_info_a304_81b7 +#define pci_ss_info_a304_81b7 pci_ss_info_8086_2590_a304_81b7 +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2592_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2592_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2592_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2592_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2592_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a2_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a2_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a2_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a2_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a3_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a3_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a3_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a3_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a3_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a3_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a4_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a4_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a4_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a4_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a4_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a4_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a6_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a6_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a6_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a9_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a9_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a9_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a9_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a9_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a9_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25aa_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25aa_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25aa_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25aa_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ab_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ab_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ab_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ab_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ab_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ab_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ac_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ac_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ac_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ac_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ac_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ac_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ad_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ad_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ad_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ad_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ad_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ad_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25b0_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25b0_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25b0_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25b0_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_2640_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2640_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2640_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2640_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2640_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2640_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2641_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2641_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2641_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2651_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2651_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2651_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2651_1043_2601 = + {0x1043, 0x2601, pci_subsys_8086_2651_1043_2601, 0}; +#undef pci_ss_info_1043_2601 +#define pci_ss_info_1043_2601 pci_ss_info_8086_2651_1043_2601 +static const pciSubsystemInfo pci_ss_info_8086_2651_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2651_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2651_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2651_8086_4147 = + {0x8086, 0x4147, pci_subsys_8086_2651_8086_4147, 0}; +#undef pci_ss_info_8086_4147 +#define pci_ss_info_8086_4147 pci_ss_info_8086_2651_8086_4147 +static const pciSubsystemInfo pci_ss_info_8086_2652_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2652_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2652_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2658_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2658_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2658_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2658_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2658_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2658_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2658_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2658_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2658_1458_2558 = + {0x1458, 0x2558, pci_subsys_8086_2658_1458_2558, 0}; +#undef pci_ss_info_1458_2558 +#define pci_ss_info_1458_2558 pci_ss_info_8086_2658_1458_2558 +static const pciSubsystemInfo pci_ss_info_8086_2658_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2658_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2658_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2658_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2658_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2659_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2659_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2659_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2659_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2659_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2659_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2659_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2659_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2659_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2659_1458_2659 = + {0x1458, 0x2659, pci_subsys_8086_2659_1458_2659, 0}; +#undef pci_ss_info_1458_2659 +#define pci_ss_info_1458_2659 pci_ss_info_8086_2659_1458_2659 +static const pciSubsystemInfo pci_ss_info_8086_2659_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2659_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2659_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2659_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2659_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2659_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265a_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265a_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265a_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265a_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265a_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265a_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265b_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265b_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265b_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265b_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265b_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265b_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265b_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265b_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265b_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265b_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265b_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265b_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265b_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265b_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265b_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265b_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265b_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265b_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265c_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265c_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265c_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265c_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265c_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265c_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265c_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265c_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_265c_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_265c_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_265c_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265c_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265c_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265c_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265c_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265c_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2660_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2660_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2660_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2668_1043_814e = + {0x1043, 0x814e, pci_subsys_8086_2668_1043_814e, 0}; +#undef pci_ss_info_1043_814e +#define pci_ss_info_1043_814e pci_ss_info_8086_2668_1043_814e +static const pciSubsystemInfo pci_ss_info_8086_266a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266a_1458_266a = + {0x1458, 0x266a, pci_subsys_8086_266a_1458_266a, 0}; +#undef pci_ss_info_1458_266a +#define pci_ss_info_1458_266a pci_ss_info_8086_266a_1458_266a +static const pciSubsystemInfo pci_ss_info_8086_266a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_266d_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266d_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266d_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266d_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266d_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266d_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266e_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266e_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266e_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266e_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_266e_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_266e_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0188 = + {0x1028, 0x0188, pci_subsys_8086_266e_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_8086_266e_1028_0188 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266e_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_266e_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_266e_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_266e_1734_105a = + {0x1734, 0x105a, pci_subsys_8086_266e_1734_105a, 0}; +#undef pci_ss_info_1734_105a +#define pci_ss_info_1734_105a pci_ss_info_8086_266e_1734_105a +static const pciSubsystemInfo pci_ss_info_8086_266f_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266f_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266f_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266f_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266f_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266f_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266f_1458_266f = + {0x1458, 0x266f, pci_subsys_8086_266f_1458_266f, 0}; +#undef pci_ss_info_1458_266f +#define pci_ss_info_1458_266f pci_ss_info_8086_266f_1458_266f +static const pciSubsystemInfo pci_ss_info_8086_266f_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266f_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266f_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266f_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266f_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266f_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2770_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2770_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2770_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2772_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2772_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2772_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2782_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2782_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2782_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2782_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2782_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2782_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2792_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2792_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2792_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2792_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2792_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2792_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_27b8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27b8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27b8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c0_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c0_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c0_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c9_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c9_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c9_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27ca_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27ca_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27ca_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cb_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cb_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cb_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cc_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cc_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cc_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27da_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27da_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27da_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27dc_8086_308d = + {0x8086, 0x308d, pci_subsys_8086_27dc_8086_308d, 0}; +#undef pci_ss_info_8086_308d +#define pci_ss_info_8086_308d pci_ss_info_8086_27dc_8086_308d +static const pciSubsystemInfo pci_ss_info_8086_27df_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27df_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27df_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_3340_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_3340_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_3340_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_3340_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_3340_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_3340_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_3340_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_3575_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_3575_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_3575_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3580_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3580_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3580_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3580_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3580_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3580_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3580_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3580_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3580_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3580_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3580_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3580_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3580_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3581_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3581_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3581_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3582_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3582_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3582_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3582_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3582_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3582_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3582_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3582_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3584_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3584_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3584_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3584_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3584_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3584_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3584_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3584_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3584_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3584_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3584_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3584_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3584_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3585_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3585_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3585_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3585_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3585_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3585_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3585_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3585_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3585_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3585_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3585_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3585_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3585_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3590_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_3590_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_3590_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_3590_1734_103e = + {0x1734, 0x103e, pci_subsys_8086_3590_1734_103e, 0}; +#undef pci_ss_info_1734_103e +#define pci_ss_info_1734_103e pci_ss_info_8086_3590_1734_103e +static const pciSubsystemInfo pci_ss_info_8086_3590_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3590_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3590_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3591_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_3591_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_3591_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_3591_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3591_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3591_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3594_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3594_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3594_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_359e_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_359e_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_359e_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7110_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7110_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7110_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7111_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7111_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7111_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7112_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7112_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7112_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7113_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7113_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7113_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7120_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7120_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7120_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7120_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7121_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7121_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7121_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7121_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_8086_4341 = + {0x8086, 0x4341, pci_subsys_8086_7121_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_8086_7121_8086_4341 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7190_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7190_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_7190_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_7190_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_7190_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_7190_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7192_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_7192_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_7192_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7194_1033_0000 = + {0x1033, 0x0000, pci_subsys_8086_7194_1033_0000, 0}; +#undef pci_ss_info_1033_0000 +#define pci_ss_info_1033_0000 pci_ss_info_8086_7194_1033_0000 +static const pciSubsystemInfo pci_ss_info_8086_7194_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_7194_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_7194_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_7195_1033_80cc = + {0x1033, 0x80cc, pci_subsys_8086_7195_1033_80cc, 0}; +#undef pci_ss_info_1033_80cc +#define pci_ss_info_1033_80cc pci_ss_info_8086_7195_1033_80cc +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_71a0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_71a0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_71a0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_71a0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_71a2_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_71a2_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_71a2_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0ded = + {0x1993, 0x0ded, pci_subsys_8086_8500_1993_0ded, 0}; +#undef pci_ss_info_1993_0ded +#define pci_ss_info_1993_0ded pci_ss_info_8086_8500_1993_0ded +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0dee = + {0x1993, 0x0dee, pci_subsys_8086_8500_1993_0dee, 0}; +#undef pci_ss_info_1993_0dee +#define pci_ss_info_1993_0dee pci_ss_info_8086_8500_1993_0dee +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0def = + {0x1993, 0x0def, pci_subsys_8086_8500_1993_0def, 0}; +#undef pci_ss_info_1993_0def +#define pci_ss_info_1993_0def pci_ss_info_8086_8500_1993_0def +static const pciSubsystemInfo pci_ss_info_8086_b555_12d9_000a = + {0x12d9, 0x000a, pci_subsys_8086_b555_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_8086_b555_12d9_000a +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_b555_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_b555_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_b555_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_b555_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +#endif +#define pci_ss_list_0095_0680 NULL +#define pci_ss_list_018a_0106 NULL +#define pci_ss_list_021b_8139 NULL +#define pci_ss_list_0291_8212 NULL +#define pci_ss_list_02ac_1012 NULL +#define pci_ss_list_0357_000a NULL +#define pci_ss_list_0432_0001 NULL +#define pci_ss_list_045e_006e NULL +#define pci_ss_list_045e_00c2 NULL +#define pci_ss_list_04cf_8818 NULL +#define pci_ss_list_050d_7050 NULL +#define pci_ss_list_05e3_0701 NULL +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_0675_1703 NULL +#define pci_ss_list_0675_1704 NULL +#define pci_ss_list_067b_3507 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0b49_064f NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_0046[] = { + &pci_ss_info_0e11_0046_0e11_409a, + &pci_ss_info_0e11_0046_0e11_409b, + &pci_ss_info_0e11_0046_0e11_409c, + &pci_ss_info_0e11_0046_0e11_409d, + NULL +}; +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_005a NULL +#define pci_ss_list_0e11_007c NULL +#define pci_ss_list_0e11_007d NULL +#define pci_ss_list_0e11_0085 NULL +#define pci_ss_list_0e11_00b1 NULL +#define pci_ss_list_0e11_00bb NULL +#define pci_ss_list_0e11_00ca NULL +#define pci_ss_list_0e11_00cb NULL +#define pci_ss_list_0e11_00cf NULL +#define pci_ss_list_0e11_00d0 NULL +#define pci_ss_list_0e11_00d1 NULL +#define pci_ss_list_0e11_00e3 NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_4030 NULL +#define pci_ss_list_0e11_4031 NULL +#define pci_ss_list_0e11_4032 NULL +#define pci_ss_list_0e11_4033 NULL +#define pci_ss_list_0e11_4034 NULL +#define pci_ss_list_0e11_4040 NULL +#define pci_ss_list_0e11_4048 NULL +#define pci_ss_list_0e11_4050 NULL +#define pci_ss_list_0e11_4051 NULL +#define pci_ss_list_0e11_4058 NULL +#define pci_ss_list_0e11_4070 NULL +#define pci_ss_list_0e11_4080 NULL +#define pci_ss_list_0e11_4082 NULL +#define pci_ss_list_0e11_4083 NULL +#define pci_ss_list_0e11_4091 NULL +#define pci_ss_list_0e11_409a NULL +#define pci_ss_list_0e11_409b NULL +#define pci_ss_list_0e11_409c NULL +#define pci_ss_list_0e11_409d NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_b178[] = { + &pci_ss_info_0e11_b178_0e11_4080, + &pci_ss_info_0e11_b178_0e11_4082, + &pci_ss_info_0e11_b178_0e11_4083, + NULL +}; +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_b200 NULL +#define pci_ss_list_0e11_b203 NULL +#define pci_ss_list_0e11_b204 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0003[] = { + &pci_ss_info_1000_0003_1000_1000, + NULL +}; +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0006[] = { + &pci_ss_info_1000_0006_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000a[] = { + &pci_ss_info_1000_000a_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000b[] = { + &pci_ss_info_1000_000b_0e11_6004, + &pci_ss_info_1000_000b_1000_1000, + &pci_ss_info_1000_000b_1000_1010, + &pci_ss_info_1000_000b_1000_1020, + &pci_ss_info_1000_000b_13e9_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1000_1010, + &pci_ss_info_1000_000c_1000_1020, + &pci_ss_info_1000_000c_1de1_3906, + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1000_1000, + &pci_ss_info_1000_000f_1000_1010, + &pci_ss_info_1000_000f_1000_1020, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1de1_3904, + &pci_ss_info_1000_000f_4c53_1000, + &pci_ss_info_1000_000f_4c53_1050, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + &pci_ss_info_1000_0010_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0012[] = { + &pci_ss_info_1000_0012_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0013[] = { + &pci_ss_info_1000_0013_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1000_1000, + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0021[] = { + &pci_ss_info_1000_0021_1000_1000, + &pci_ss_info_1000_0021_1000_1010, + &pci_ss_info_1000_0021_124b_1070, + &pci_ss_info_1000_0021_4c53_1080, + &pci_ss_info_1000_0021_4c53_1300, + &pci_ss_info_1000_0021_4c53_1310, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_0e11_00da, + &pci_ss_info_1000_0030_1028_0123, + &pci_ss_info_1000_0030_1028_014a, + &pci_ss_info_1000_0030_1028_016c, + &pci_ss_info_1000_0030_1028_0183, + &pci_ss_info_1000_0030_1028_1010, + &pci_ss_info_1000_0030_124b_1170, + &pci_ss_info_1000_0030_1734_1052, + NULL +}; +#define pci_ss_list_1000_0031 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0032[] = { + &pci_ss_info_1000_0032_1000_1000, + NULL +}; +#define pci_ss_list_1000_0033 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0040[] = { + &pci_ss_info_1000_0040_1000_0033, + &pci_ss_info_1000_0040_1000_0066, + NULL +}; +#define pci_ss_list_1000_0041 NULL +#define pci_ss_list_1000_0050 NULL +#define pci_ss_list_1000_0054 NULL +#define pci_ss_list_1000_0056 NULL +#define pci_ss_list_1000_0058 NULL +#define pci_ss_list_1000_005a NULL +#define pci_ss_list_1000_005c NULL +#define pci_ss_list_1000_005e NULL +#define pci_ss_list_1000_0060 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0062[] = { + &pci_ss_info_1000_0062_1000_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0407[] = { + &pci_ss_info_1000_0407_1000_0530, + &pci_ss_info_1000_0407_1000_0531, + &pci_ss_info_1000_0407_1000_0532, + &pci_ss_info_1000_0407_1028_0531, + &pci_ss_info_1000_0407_1028_0533, + &pci_ss_info_1000_0407_8086_0530, + &pci_ss_info_1000_0407_8086_0532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0408[] = { + &pci_ss_info_1000_0408_1000_0001, + &pci_ss_info_1000_0408_1000_0002, + &pci_ss_info_1000_0408_1025_004d, + &pci_ss_info_1000_0408_1028_0001, + &pci_ss_info_1000_0408_1028_0002, + &pci_ss_info_1000_0408_1734_1065, + &pci_ss_info_1000_0408_8086_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0409[] = { + &pci_ss_info_1000_0409_1000_3004, + &pci_ss_info_1000_0409_1000_3008, + &pci_ss_info_1000_0409_8086_3008, + &pci_ss_info_1000_0409_8086_3431, + &pci_ss_info_1000_0409_8086_3499, + NULL +}; +#define pci_ss_list_1000_0621 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0622[] = { + &pci_ss_info_1000_0622_1000_1020, + NULL +}; +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0626[] = { + &pci_ss_info_1000_0626_1000_1010, + NULL +}; +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0640 NULL +#define pci_ss_list_1000_0642 NULL +#define pci_ss_list_1000_0646 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0804 NULL +#define pci_ss_list_1000_0805 NULL +#define pci_ss_list_1000_0806 NULL +#define pci_ss_list_1000_0807 NULL +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1000_0518, + &pci_ss_info_1000_1960_1000_0520, + &pci_ss_info_1000_1960_1000_0522, + &pci_ss_info_1000_1960_1000_0523, + &pci_ss_info_1000_1960_1000_4523, + &pci_ss_info_1000_1960_1000_a520, + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + &pci_ss_info_1000_1960_1028_0533, + &pci_ss_info_1000_1960_8086_0520, + &pci_ss_info_1000_1960_8086_0523, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_3150 NULL +#define pci_ss_list_1002_3152 NULL +#define pci_ss_list_1002_3154 NULL +#define pci_ss_list_1002_3e50 NULL +#define pci_ss_list_1002_3e54 NULL +#define pci_ss_list_1002_3e70 NULL +#define pci_ss_list_1002_4136 NULL +#define pci_ss_list_1002_4137 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4148 NULL +#define pci_ss_list_1002_4149 NULL +#define pci_ss_list_1002_414a NULL +#define pci_ss_list_1002_414b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4150[] = { + &pci_ss_info_1002_4150_1002_0002, + &pci_ss_info_1002_4150_1002_0003, + &pci_ss_info_1002_4150_1002_4722, + &pci_ss_info_1002_4150_1458_4024, + &pci_ss_info_1002_4150_148c_2064, + &pci_ss_info_1002_4150_148c_2066, + &pci_ss_info_1002_4150_174b_7c19, + &pci_ss_info_1002_4150_174b_7c29, + &pci_ss_info_1002_4150_17ee_2002, + &pci_ss_info_1002_4150_18bc_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4151[] = { + &pci_ss_info_1002_4151_1043_c004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4152[] = { + &pci_ss_info_1002_4152_1002_0002, + &pci_ss_info_1002_4152_1002_4772, + &pci_ss_info_1002_4152_1043_c002, + &pci_ss_info_1002_4152_1043_c01a, + &pci_ss_info_1002_4152_174b_7c29, + &pci_ss_info_1002_4152_1787_4002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4153[] = { + &pci_ss_info_1002_4153_1462_932c, + NULL +}; +#define pci_ss_list_1002_4154 NULL +#define pci_ss_list_1002_4155 NULL +#define pci_ss_list_1002_4156 NULL +#define pci_ss_list_1002_4157 NULL +#define pci_ss_list_1002_4158 NULL +#define pci_ss_list_1002_4164 NULL +#define pci_ss_list_1002_4165 NULL +#define pci_ss_list_1002_4166 NULL +#define pci_ss_list_1002_4168 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4170[] = { + &pci_ss_info_1002_4170_1002_0003, + &pci_ss_info_1002_4170_1002_4723, + &pci_ss_info_1002_4170_1458_4025, + &pci_ss_info_1002_4170_148c_2067, + &pci_ss_info_1002_4170_174b_7c28, + &pci_ss_info_1002_4170_17ee_2003, + &pci_ss_info_1002_4170_18bc_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4171[] = { + &pci_ss_info_1002_4171_1043_c005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4172[] = { + &pci_ss_info_1002_4172_1002_0003, + &pci_ss_info_1002_4172_1002_4773, + &pci_ss_info_1002_4172_1043_c003, + &pci_ss_info_1002_4172_1043_c01b, + &pci_ss_info_1002_4172_174b_7c28, + &pci_ss_info_1002_4172_1787_4003, + NULL +}; +#define pci_ss_list_1002_4173 NULL +#define pci_ss_list_1002_4237 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4243 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4336[] = { + &pci_ss_info_1002_4336_1002_4336, + &pci_ss_info_1002_4336_103c_0024, + &pci_ss_info_1002_4336_161f_2029, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4337[] = { + &pci_ss_info_1002_4337_1014_053a, + &pci_ss_info_1002_4337_103c_0850, + NULL +}; +#define pci_ss_list_1002_4341 NULL +#define pci_ss_list_1002_4345 NULL +#define pci_ss_list_1002_4347 NULL +#define pci_ss_list_1002_4348 NULL +#define pci_ss_list_1002_4349 NULL +#define pci_ss_list_1002_434d NULL +#define pci_ss_list_1002_4353 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4363 NULL +#define pci_ss_list_1002_436e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4370[] = { + &pci_ss_info_1002_4370_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4371[] = { + &pci_ss_info_1002_4371_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4372[] = { + &pci_ss_info_1002_4372_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4373[] = { + &pci_ss_info_1002_4373_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4374[] = { + &pci_ss_info_1002_4374_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4375[] = { + &pci_ss_info_1002_4375_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4376[] = { + &pci_ss_info_1002_4376_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4377[] = { + &pci_ss_info_1002_4377_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4378[] = { + &pci_ss_info_1002_4378_103c_308b, + NULL +}; +#define pci_ss_list_1002_4379 NULL +#define pci_ss_list_1002_437a NULL +#define pci_ss_list_1002_4437 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00ce, + &pci_ss_info_1002_4752_1028_00d1, + &pci_ss_info_1002_4752_1028_00d9, + &pci_ss_info_1002_4752_1028_0134, + &pci_ss_info_1002_4752_1734_007a, + &pci_ss_info_1002_4752_8086_3411, + &pci_ss_info_1002_4752_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0084, + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +#define pci_ss_list_1002_4a48 NULL +#define pci_ss_list_1002_4a49 NULL +#define pci_ss_list_1002_4a4a NULL +#define pci_ss_list_1002_4a4b NULL +#define pci_ss_list_1002_4a4c NULL +#define pci_ss_list_1002_4a4d NULL +#define pci_ss_list_1002_4a4e NULL +#define pci_ss_list_1002_4a50 NULL +#define pci_ss_list_1002_4a70 NULL +#define pci_ss_list_1002_4b49 NULL +#define pci_ss_list_1002_4b4b NULL +#define pci_ss_list_1002_4b4c NULL +#define pci_ss_list_1002_4b69 NULL +#define pci_ss_list_1002_4b6b NULL +#define pci_ss_list_1002_4b6c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e7, + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c46[] = { + &pci_ss_info_1002_4c46_1028_00b1, + NULL +}; +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_0e11_b160, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + &pci_ss_info_1002_4c4d_1028_00aa, + &pci_ss_info_1002_4c4d_1028_00bb, + &pci_ss_info_1002_4c4d_10e1_10cf, + &pci_ss_info_1002_4c4d_1179_ff00, + &pci_ss_info_1002_4c4d_13bd_1019, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c52[] = { + &pci_ss_info_1002_4c52_1033_8112, + NULL +}; +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_1028_012a, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_0e11_b111, + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + &pci_ss_info_1002_4c59_1509_1930, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4c6e NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e44[] = { + &pci_ss_info_1002_4e44_1002_515e, + &pci_ss_info_1002_4e44_1002_5965, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4e45[] = { + &pci_ss_info_1002_4e45_1002_0002, + &pci_ss_info_1002_4e45_1681_0002, + NULL +}; +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e48 NULL +#define pci_ss_list_1002_4e49 NULL +#define pci_ss_list_1002_4e4a NULL +#define pci_ss_list_1002_4e4b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e50[] = { + &pci_ss_info_1002_4e50_1025_005a, + &pci_ss_info_1002_4e50_103c_088c, + &pci_ss_info_1002_4e50_103c_0890, + &pci_ss_info_1002_4e50_1734_1055, + NULL +}; +#define pci_ss_list_1002_4e51 NULL +#define pci_ss_list_1002_4e52 NULL +#define pci_ss_list_1002_4e53 NULL +#define pci_ss_list_1002_4e54 NULL +#define pci_ss_list_1002_4e56 NULL +#define pci_ss_list_1002_4e64 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e65[] = { + &pci_ss_info_1002_4e65_1002_0003, + &pci_ss_info_1002_4e65_1681_0003, + NULL +}; +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_4e68 NULL +#define pci_ss_list_1002_4e69 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e6a[] = { + &pci_ss_info_1002_4e6a_1002_4e71, + NULL +}; +#define pci_ss_list_1002_4e71 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_1681_0010, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +#define pci_ss_list_1002_5154 NULL +#define pci_ss_list_1002_5155 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1002_103a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7146, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1014_029a, + &pci_ss_info_1002_5159_1014_02c8, + &pci_ss_info_1002_5159_1028_019a, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_174b_7c28, + &pci_ss_info_1002_5159_1787_0202, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_515e NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5346[] = { + &pci_ss_info_1002_5346_1002_0048, + NULL +}; +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +#define pci_ss_list_1002_5460 NULL +#define pci_ss_list_1002_5462 NULL +#define pci_ss_list_1002_5464 NULL +#define pci_ss_list_1002_5548 NULL +#define pci_ss_list_1002_5549 NULL +#define pci_ss_list_1002_554a NULL +#define pci_ss_list_1002_554b NULL +#define pci_ss_list_1002_554d NULL +#define pci_ss_list_1002_554f NULL +#define pci_ss_list_1002_5550 NULL +#define pci_ss_list_1002_5551 NULL +#define pci_ss_list_1002_5552 NULL +#define pci_ss_list_1002_5554 NULL +#define pci_ss_list_1002_556b NULL +#define pci_ss_list_1002_556d NULL +#define pci_ss_list_1002_556f NULL +#define pci_ss_list_1002_564a NULL +#define pci_ss_list_1002_564b NULL +#define pci_ss_list_1002_5652 NULL +#define pci_ss_list_1002_5653 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_5830 NULL +#define pci_ss_list_1002_5831 NULL +#define pci_ss_list_1002_5832 NULL +#define pci_ss_list_1002_5833 NULL +#define pci_ss_list_1002_5834 NULL +#define pci_ss_list_1002_5835 NULL +#define pci_ss_list_1002_5838 NULL +#define pci_ss_list_1002_5940 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5941[] = { + &pci_ss_info_1002_5941_1458_4019, + &pci_ss_info_1002_5941_174b_7c12, + &pci_ss_info_1002_5941_17af_200d, + &pci_ss_info_1002_5941_18bc_0050, + NULL +}; +#define pci_ss_list_1002_5944 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5950[] = { + &pci_ss_info_1002_5950_103c_308b, + NULL +}; +#define pci_ss_list_1002_5951 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5954[] = { + &pci_ss_info_1002_5954_1002_5954, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5955[] = { + &pci_ss_info_1002_5955_1002_5955, + &pci_ss_info_1002_5955_103c_308b, + NULL +}; +#define pci_ss_list_1002_5960 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5961[] = { + &pci_ss_info_1002_5961_1002_2f72, + &pci_ss_info_1002_5961_1019_4c30, + &pci_ss_info_1002_5961_12ab_5961, + &pci_ss_info_1002_5961_1458_4018, + &pci_ss_info_1002_5961_174b_7c13, + &pci_ss_info_1002_5961_17af_200c, + &pci_ss_info_1002_5961_18bc_0050, + &pci_ss_info_1002_5961_18bc_0051, + &pci_ss_info_1002_5961_18bc_0053, + NULL +}; +#define pci_ss_list_1002_5962 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5964[] = { + &pci_ss_info_1002_5964_1043_c006, + &pci_ss_info_1002_5964_1458_4018, + &pci_ss_info_1002_5964_147b_6191, + &pci_ss_info_1002_5964_148c_2073, + &pci_ss_info_1002_5964_174b_7c13, + &pci_ss_info_1002_5964_1787_5964, + &pci_ss_info_1002_5964_17af_2012, + &pci_ss_info_1002_5964_18bc_0170, + &pci_ss_info_1002_5964_18bc_0173, + NULL +}; +#define pci_ss_list_1002_5969 NULL +#define pci_ss_list_1002_5974 NULL +#define pci_ss_list_1002_5975 NULL +#define pci_ss_list_1002_5a34 NULL +#define pci_ss_list_1002_5a38 NULL +#define pci_ss_list_1002_5a3f NULL +#define pci_ss_list_1002_5a41 NULL +#define pci_ss_list_1002_5a42 NULL +#define pci_ss_list_1002_5a61 NULL +#define pci_ss_list_1002_5a62 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b60[] = { + &pci_ss_info_1002_5b60_1043_002a, + &pci_ss_info_1002_5b60_1043_032e, + &pci_ss_info_1002_5b60_1462_0402, + NULL +}; +#define pci_ss_list_1002_5b62 NULL +#define pci_ss_list_1002_5b63 NULL +#define pci_ss_list_1002_5b64 NULL +#define pci_ss_list_1002_5b65 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b70[] = { + &pci_ss_info_1002_5b70_1462_0403, + NULL +}; +#define pci_ss_list_1002_5b72 NULL +#define pci_ss_list_1002_5b73 NULL +#define pci_ss_list_1002_5b74 NULL +#define pci_ss_list_1002_5c61 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5c63[] = { + &pci_ss_info_1002_5c63_1002_5c63, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5d44[] = { + &pci_ss_info_1002_5d44_1458_4019, + &pci_ss_info_1002_5d44_174b_7c12, + &pci_ss_info_1002_5d44_1787_5965, + &pci_ss_info_1002_5d44_17af_2013, + &pci_ss_info_1002_5d44_18bc_0171, + &pci_ss_info_1002_5d44_18bc_0172, + NULL +}; +#define pci_ss_list_1002_5d48 NULL +#define pci_ss_list_1002_5d49 NULL +#define pci_ss_list_1002_5d4a NULL +#define pci_ss_list_1002_5d4d NULL +#define pci_ss_list_1002_5d4f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5d52[] = { + &pci_ss_info_1002_5d52_1002_0b12, + &pci_ss_info_1002_5d52_1002_0b13, + NULL +}; +#define pci_ss_list_1002_5d57 NULL +#define pci_ss_list_1002_5d6d NULL +#define pci_ss_list_1002_5d6f NULL +#define pci_ss_list_1002_5d72 NULL +#define pci_ss_list_1002_5d77 NULL +#define pci_ss_list_1002_5e48 NULL +#define pci_ss_list_1002_5e49 NULL +#define pci_ss_list_1002_5e4a NULL +#define pci_ss_list_1002_5e4b NULL +#define pci_ss_list_1002_5e4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e4d[] = { + &pci_ss_info_1002_5e4d_148c_2116, + NULL +}; +#define pci_ss_list_1002_5e4f NULL +#define pci_ss_list_1002_5e6b NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e6d[] = { + &pci_ss_info_1002_5e6d_148c_2117, + NULL +}; +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1002_7010 NULL +#define pci_ss_list_1002_7100 NULL +#define pci_ss_list_1002_7105 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7109[] = { + &pci_ss_info_1002_7109_1002_0322, + &pci_ss_info_1002_7109_1002_0d02, + NULL +}; +#define pci_ss_list_1002_7120 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7129[] = { + &pci_ss_info_1002_7129_1002_0323, + &pci_ss_info_1002_7129_1002_0d03, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7142[] = { + &pci_ss_info_1002_7142_1002_0322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7146[] = { + &pci_ss_info_1002_7146_1002_0322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7162[] = { + &pci_ss_info_1002_7162_1002_0323, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7166[] = { + &pci_ss_info_1002_7166_1002_0323, + NULL +}; +#define pci_ss_list_1002_71c0 NULL +#define pci_ss_list_1002_71c2 NULL +#define pci_ss_list_1002_71e0 NULL +#define pci_ss_list_1002_71e2 NULL +#define pci_ss_list_1002_7833 NULL +#define pci_ss_list_1002_7834 NULL +#define pci_ss_list_1002_7835 NULL +#define pci_ss_list_1002_7838 NULL +#define pci_ss_list_1002_7c37 NULL +#define pci_ss_list_1002_cab0 NULL +#define pci_ss_list_1002_cab2 NULL +#define pci_ss_list_1002_cab3 NULL +#define pci_ss_list_1002_cbb2 NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +static const pciSubsystemInfo *pci_ss_list_100b_0020[] = { + &pci_ss_info_100b_0020_103c_0024, + &pci_ss_info_100b_0020_12d9_000c, + &pci_ss_info_100b_0020_1385_f311, + NULL +}; +#define pci_ss_list_100b_0021 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0028 NULL +#define pci_ss_list_100b_002a NULL +#define pci_ss_list_100b_002b NULL +#define pci_ss_list_100b_002d NULL +#define pci_ss_list_100b_002e NULL +#define pci_ss_list_100b_002f NULL +#define pci_ss_list_100b_0030 NULL +#define pci_ss_list_100b_0035 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_0510 NULL +#define pci_ss_list_100b_0511 NULL +#define pci_ss_list_100b_0515 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +#define pci_ss_list_1011_000f NULL +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +#define pci_ss_list_1011_0017 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1186_1112, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_14cb_0100, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_4c53_1050, + &pci_ss_info_1011_0046_4c53_1051, + &pci_ss_info_1011_0046_9005_0364, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4000 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_153b_1136, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0031[] = { + &pci_ss_info_1014_0031_1014_0031, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_0037 NULL +#define pci_ss_list_1014_003a NULL +#define pci_ss_list_1014_003c NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0054 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_005e NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +#define pci_ss_list_1014_008b NULL +#define pci_ss_list_1014_008e NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0091 NULL +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_009f NULL +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1014_00b7[] = { + &pci_ss_info_1014_00b7_1092_00b8, + NULL +}; +#define pci_ss_list_1014_00b8 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0104 NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_015e NULL +#define pci_ss_list_1014_0160 NULL +#define pci_ss_list_1014_016e NULL +#define pci_ss_list_1014_0170 NULL +#define pci_ss_list_1014_017d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0180[] = { + &pci_ss_info_1014_0180_1014_0241, + &pci_ss_info_1014_0180_1014_0264, + NULL +}; +#define pci_ss_list_1014_0188 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_01c1 NULL +#define pci_ss_list_1014_01e6 NULL +#define pci_ss_list_1014_01ff NULL +static const pciSubsystemInfo *pci_ss_list_1014_0219[] = { + &pci_ss_info_1014_0219_1014_021a, + &pci_ss_info_1014_0219_1014_0251, + &pci_ss_info_1014_0219_1014_0252, + NULL +}; +#define pci_ss_list_1014_021b NULL +#define pci_ss_list_1014_021c NULL +#define pci_ss_list_1014_0233 NULL +#define pci_ss_list_1014_0266 NULL +#define pci_ss_list_1014_0268 NULL +#define pci_ss_list_1014_0269 NULL +static const pciSubsystemInfo *pci_ss_list_1014_028c[] = { + &pci_ss_info_1014_028c_1014_028d, + &pci_ss_info_1014_028c_1014_02be, + &pci_ss_info_1014_028c_1014_02c0, + &pci_ss_info_1014_028c_1014_030d, + NULL +}; +#define pci_ss_list_1014_02a1 NULL +static const pciSubsystemInfo *pci_ss_list_1014_02bd[] = { + &pci_ss_info_1014_02bd_1014_02c1, + &pci_ss_info_1014_02bd_1014_02c2, + NULL +}; +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_0314 NULL +#define pci_ss_list_1014_3022 NULL +#define pci_ss_list_1014_4022 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#define pci_ss_list_101e_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0477, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_101e_0494, + &pci_ss_info_101e_1960_101e_0503, + &pci_ss_info_101e_1960_101e_0511, + &pci_ss_info_101e_1960_101e_0522, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + &pci_ss_info_101e_1960_103c_60e7, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_1022_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + &pci_ss_info_1022_2000_1259_2702, + &pci_ss_info_1022_2000_1259_2703, + &pci_ss_info_1022_2000_4c53_1000, + &pci_ss_info_1022_2000_4c53_1010, + &pci_ss_info_1022_2000_4c53_1020, + &pci_ss_info_1022_2000_4c53_1030, + &pci_ss_info_1022_2000_4c53_1040, + &pci_ss_info_1022_2000_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2003 NULL +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_2081 NULL +#define pci_ss_list_1022_2082 NULL +#define pci_ss_list_1022_208f NULL +#define pci_ss_list_1022_2090 NULL +#define pci_ss_list_1022_2091 NULL +#define pci_ss_list_1022_2093 NULL +#define pci_ss_list_1022_2094 NULL +#define pci_ss_list_1022_2095 NULL +#define pci_ss_list_1022_2096 NULL +#define pci_ss_list_1022_2097 NULL +#define pci_ss_list_1022_209a NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700a NULL +#define pci_ss_list_1022_700b NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7458 NULL +#define pci_ss_list_1022_7459 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7460[] = { + &pci_ss_info_1022_7460_161f_3017, + NULL +}; +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7464[] = { + &pci_ss_info_1022_7464_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7468[] = { + &pci_ss_info_1022_7468_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7469[] = { + &pci_ss_info_1022_7469_1022_2b80, + &pci_ss_info_1022_7469_161f_3017, + NULL +}; +#define pci_ss_list_1022_746a NULL +static const pciSubsystemInfo *pci_ss_list_1022_746b[] = { + &pci_ss_info_1022_746b_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_746d[] = { + &pci_ss_info_1022_746d_161f_3017, + NULL +}; +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1022_756b NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +static const pciSubsystemInfo *pci_ss_list_1023_2001[] = { + &pci_ss_info_1023_2001_122d_1400, + NULL +}; +#define pci_ss_list_1023_2100 NULL +#define pci_ss_list_1023_2200 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + &pci_ss_info_1023_8620_1014_1025, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_1671 NULL +#define pci_ss_list_1025_1672 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +#define pci_ss_list_1028_0009 NULL +#define pci_ss_list_1028_000a NULL +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000d NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_1028_0010 NULL +#define pci_ss_list_1028_0011 NULL +#define pci_ss_list_1028_0012 NULL +static const pciSubsystemInfo *pci_ss_list_1028_0013[] = { + &pci_ss_info_1028_0013_1028_016c, + &pci_ss_info_1028_0013_1028_016d, + &pci_ss_info_1028_0013_1028_016e, + &pci_ss_info_1028_0013_1028_016f, + &pci_ss_info_1028_0013_1028_0170, + NULL +}; +#define pci_ss_list_1028_0014 NULL +#define pci_ss_list_1028_0015 NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102a_001f[] = { + &pci_ss_info_102a_001f_9005_000f, + &pci_ss_info_102a_001f_9005_0106, + &pci_ss_info_102a_001f_9005_a180, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00c5[] = { + &pci_ss_info_102a_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00cf[] = { + &pci_ss_info_102a_00cf_1028_0106, + &pci_ss_info_102a_00cf_1028_0121, + NULL +}; +#endif +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0100 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0d43, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + &pci_ss_info_102b_0527_102b_0850, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0528[] = { + &pci_ss_info_102b_0528_102b_1020, + &pci_ss_info_102b_0528_102b_1030, + &pci_ss_info_102b_0528_102b_14e1, + &pci_ss_info_102b_0528_102b_2021, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2537[] = { + &pci_ss_info_102b_2537_102b_1820, + &pci_ss_info_102b_2537_102b_1830, + &pci_ss_info_102b_2537_102b_1c10, + &pci_ss_info_102b_2537_102b_2811, + &pci_ss_info_102b_2537_102b_2c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2538[] = { + &pci_ss_info_102b_2538_102b_08c7, + &pci_ss_info_102b_2538_102b_0907, + &pci_ss_info_102b_2538_102b_1047, + &pci_ss_info_102b_2538_102b_1087, + &pci_ss_info_102b_2538_102b_2538, + &pci_ss_info_102b_2538_102b_3007, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + &pci_ss_info_102c_00c0_4c53_1000, + &pci_ss_info_102c_00c0_4c53_1010, + &pci_ss_info_102c_00c0_4c53_1020, + &pci_ss_info_102c_00c0_4c53_1030, + &pci_ss_info_102c_00c0_4c53_1050, + &pci_ss_info_102c_00c0_4c53_1051, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + &pci_ss_info_102c_00e5_1179_0001, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_102c_0c30[] = { + &pci_ss_info_102c_0c30_4c53_1000, + &pci_ss_info_102c_0c30_4c53_1050, + &pci_ss_info_102c_0c30_4c53_1051, + &pci_ss_info_102c_0c30_4c53_1080, + NULL +}; +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#define pci_ss_list_102f_000a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#define pci_ss_list_102f_0030 NULL +#define pci_ss_list_102f_0031 NULL +#define pci_ss_list_102f_0105 NULL +#define pci_ss_list_102f_0106 NULL +#define pci_ss_list_102f_0107 NULL +#define pci_ss_list_102f_0108 NULL +#define pci_ss_list_102f_0180 NULL +#define pci_ss_list_102f_0181 NULL +#define pci_ss_list_102f_0182 NULL +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0000 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1033_0035, + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_14c2_0105, + &pci_ss_info_1033_0035_1799_0001, + &pci_ss_info_1033_0035_1931_000a, + &pci_ss_info_1033_0035_1931_000b, + &pci_ss_info_1033_0035_807d_0035, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +#define pci_ss_list_1033_0072 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a5 NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +#define pci_ss_list_1033_00ce NULL +#define pci_ss_list_1033_00df NULL +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_14c2_0205, + &pci_ss_info_1033_00e0_1799_0002, + &pci_ss_info_1033_00e0_807d_1043, + NULL +}; +#define pci_ss_list_1033_00e7 NULL +#define pci_ss_list_1033_00f2 NULL +#define pci_ss_list_1033_00f3 NULL +#define pci_ss_list_1033_010c NULL +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0003 NULL +#define pci_ss_list_1039_0004 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_000a NULL +#define pci_ss_list_1039_0016 NULL +#define pci_ss_list_1039_0018 NULL +#define pci_ss_list_1039_0180 NULL +#define pci_ss_list_1039_0181 NULL +#define pci_ss_list_1039_0182 NULL +#define pci_ss_list_1039_0190 NULL +#define pci_ss_list_1039_0191 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0550 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0648 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0655 NULL +#define pci_ss_list_1039_0660 NULL +#define pci_ss_list_1039_0661 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0741 NULL +#define pci_ss_list_1039_0745 NULL +#define pci_ss_list_1039_0746 NULL +#define pci_ss_list_1039_0755 NULL +#define pci_ss_list_1039_0760 NULL +#define pci_ss_list_1039_0761 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1019_0a14, + &pci_ss_info_1039_0900_1039_0900, + &pci_ss_info_1039_0900_1043_8035, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_0963 NULL +#define pci_ss_list_1039_0964 NULL +#define pci_ss_list_1039_0965 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + &pci_ss_info_1039_5513_1043_8035, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + &pci_ss_info_1039_6300_1043_8035, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6330[] = { + &pci_ss_info_1039_6330_1039_6330, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1019_0a14, + &pci_ss_info_1039_7001_1039_7000, + &pci_ss_info_1039_7001_1462_5470, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7012[] = { + &pci_ss_info_1039_7012_15bd_1001, + NULL +}; +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_1039_7019 NULL +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1006 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_100a NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + &pci_ss_info_103c_1048_103c_1301, + NULL +}; +#define pci_ss_list_103c_1054 NULL +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_10f0 NULL +#define pci_ss_list_103c_10f1 NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_127c NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_1291 NULL +#define pci_ss_list_103c_12b4 NULL +#define pci_ss_list_103c_12fa NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_103c_3080 NULL +#define pci_ss_list_103c_3220 NULL +#define pci_ss_list_103c_3230 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043_0675[] = { + &pci_ss_info_1043_0675_0675_1704, + &pci_ss_info_1043_0675_0675_1707, + &pci_ss_info_1043_0675_10cf_105e, + NULL +}; +#define pci_ss_list_1043_4015 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1043_4057 NULL +#define pci_ss_list_1043_8043 NULL +#define pci_ss_list_1043_807b NULL +#define pci_ss_list_1043_80bb NULL +#define pci_ss_list_1043_80c5 NULL +#define pci_ss_list_1043_80df NULL +#define pci_ss_list_1043_8187 NULL +#define pci_ss_list_1043_8188 NULL +#endif +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1044_a511[] = { + &pci_ss_info_1044_a511_1044_c032, + &pci_ss_info_1044_a511_1044_c035, + NULL +}; +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0c60 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048_8901[] = { + &pci_ss_info_1048_8901_1048_0935, + NULL +}; +#endif +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0209 NULL +#define pci_ss_list_104a_020a NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_021a NULL +#define pci_ss_list_104a_021b NULL +#define pci_ss_list_104a_0500 NULL +#define pci_ss_list_104a_0564 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104a_55cc NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a34, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_1048_0a36, + &pci_ss_info_104c_3d07_1048_0a43, + &pci_ss_info_104c_3d07_1048_0a44, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8020[] = { + &pci_ss_info_104c_8020_11bd_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8023[] = { + &pci_ss_info_104c_8023_103c_088c, + &pci_ss_info_104c_8023_1043_808b, + NULL +}; +#define pci_ss_list_104c_8024 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8025[] = { + &pci_ss_info_104c_8025_1458_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8026[] = { + &pci_ss_info_104c_8026_103c_006a, + &pci_ss_info_104c_8026_1043_808d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8029[] = { + &pci_ss_info_104c_8029_1028_0163, + &pci_ss_info_104c_8029_1028_0196, + &pci_ss_info_104c_8029_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_802b[] = { + &pci_ss_info_104c_802b_1028_0139, + &pci_ss_info_104c_802b_1028_014e, + NULL +}; +#define pci_ss_list_104c_802e NULL +static const pciSubsystemInfo *pci_ss_list_104c_8031[] = { + &pci_ss_info_104c_8031_103c_099c, + &pci_ss_info_104c_8031_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8032[] = { + &pci_ss_info_104c_8032_103c_099c, + &pci_ss_info_104c_8032_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8033[] = { + &pci_ss_info_104c_8033_103c_099c, + &pci_ss_info_104c_8033_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8034[] = { + &pci_ss_info_104c_8034_103c_099c, + &pci_ss_info_104c_8034_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8035[] = { + &pci_ss_info_104c_8035_103c_099c, + NULL +}; +#define pci_ss_list_104c_8036 NULL +#define pci_ss_list_104c_8038 NULL +#define pci_ss_list_104c_8201 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8204[] = { + &pci_ss_info_104c_8204_1028_0139, + &pci_ss_info_104c_8204_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8400[] = { + &pci_ss_info_104c_8400_1186_3b00, + &pci_ss_info_104c_8400_1186_3b01, + &pci_ss_info_104c_8400_16ab_8501, + NULL +}; +#define pci_ss_list_104c_8401 NULL +#define pci_ss_list_104c_9000 NULL +#define pci_ss_list_104c_9065 NULL +static const pciSubsystemInfo *pci_ss_list_104c_9066[] = { + &pci_ss_info_104c_9066_104c_9066, + &pci_ss_info_104c_9066_1186_3b04, + &pci_ss_info_104c_9066_1186_3b05, + &pci_ss_info_104c_9066_13d1_aba0, + NULL +}; +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +static const pciSubsystemInfo *pci_ss_list_104c_a106[] = { + &pci_ss_info_104c_a106_175c_5000, + &pci_ss_info_104c_a106_175c_6400, + &pci_ss_info_104c_a106_175c_8700, + NULL +}; +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac16[] = { + &pci_ss_info_104c_ac16_1014_0092, + NULL +}; +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + &pci_ss_info_104c_ac1b_1014_0130, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac1c[] = { + &pci_ss_info_104c_ac1c_0e11_b121, + &pci_ss_info_104c_ac1c_1028_0088, + NULL +}; +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac44[] = { + &pci_ss_info_104c_ac44_1028_0163, + &pci_ss_info_104c_ac44_1028_0196, + &pci_ss_info_104c_ac44_1071_8160, + NULL +}; +#define pci_ss_list_104c_ac46 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac47[] = { + &pci_ss_info_104c_ac47_1028_0139, + &pci_ss_info_104c_ac47_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac4a[] = { + &pci_ss_info_104c_ac4a_1028_0139, + &pci_ss_info_104c_ac4a_1028_014e, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_0e11_004e, + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_1028_00b1, + &pci_ss_info_104c_ac51_1028_012a, + &pci_ss_info_104c_ac51_1033_80cd, + &pci_ss_info_104c_ac51_1095_10cf, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +#define pci_ss_list_104c_ac54 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac56[] = { + &pci_ss_info_104c_ac56_1014_0528, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac60[] = { + &pci_ss_info_104c_ac60_175c_5100, + &pci_ss_info_104c_ac60_175c_6100, + &pci_ss_info_104c_ac60_175c_6200, + &pci_ss_info_104c_ac60_175c_8800, + NULL +}; +#define pci_ss_list_104c_ac8d NULL +#define pci_ss_list_104c_ac8e NULL +#define pci_ss_list_104c_ac8f NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8004 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +static const pciSubsystemInfo *pci_ss_list_1050_6692[] = { + &pci_ss_info_1050_6692_1043_1702, + &pci_ss_info_1050_6692_1043_1703, + &pci_ss_info_1050_6692_1043_1707, + &pci_ss_info_1050_6692_144f_1702, + &pci_ss_info_1050_6692_144f_1703, + &pci_ss_info_1050_6692_144f_1707, + NULL +}; +#define pci_ss_list_1050_9921 NULL +#define pci_ss_list_1050_9922 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0008 NULL +#define pci_ss_list_1057_0009 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_14fb_0101, + &pci_ss_info_1057_1801_14fb_0102, + &pci_ss_info_1057_1801_14fb_0202, + &pci_ss_info_1057_1801_14fb_0611, + &pci_ss_info_1057_1801_14fb_0612, + &pci_ss_info_1057_1801_14fb_0613, + &pci_ss_info_1057_1801_14fb_0614, + &pci_ss_info_1057_1801_14fb_0621, + &pci_ss_info_1057_1801_14fb_0622, + &pci_ss_info_1057_1801_14fb_0810, + &pci_ss_info_1057_1801_175c_4200, + &pci_ss_info_1057_1801_175c_4300, + &pci_ss_info_1057_1801_175c_4400, + &pci_ss_info_1057_1801_ecc0_0010, + &pci_ss_info_1057_1801_ecc0_0020, + &pci_ss_info_1057_1801_ecc0_0030, + &pci_ss_info_1057_1801_ecc0_0031, + &pci_ss_info_1057_1801_ecc0_0040, + &pci_ss_info_1057_1801_ecc0_0041, + &pci_ss_info_1057_1801_ecc0_0050, + &pci_ss_info_1057_1801_ecc0_0051, + &pci_ss_info_1057_1801_ecc0_0070, + &pci_ss_info_1057_1801_ecc0_0071, + &pci_ss_info_1057_1801_ecc0_0072, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_18c1 NULL +static const pciSubsystemInfo *pci_ss_list_1057_3410[] = { + &pci_ss_info_1057_3410_ecc0_0050, + &pci_ss_info_1057_3410_ecc0_0051, + &pci_ss_info_1057_3410_ecc0_0060, + &pci_ss_info_1057_3410_ecc0_0070, + &pci_ss_info_1057_3410_ecc0_0071, + &pci_ss_info_1057_3410_ecc0_0072, + &pci_ss_info_1057_3410_ecc0_0080, + &pci_ss_info_1057_3410_ecc0_0081, + &pci_ss_info_1057_3410_ecc0_0090, + &pci_ss_info_1057_3410_ecc0_00a0, + &pci_ss_info_1057_3410_ecc0_00b0, + &pci_ss_info_1057_3410_ecc0_0100, + NULL +}; +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_5608 NULL +#define pci_ss_list_1057_5803 NULL +#define pci_ss_list_1057_5806 NULL +#define pci_ss_list_1057_5808 NULL +#define pci_ss_list_1057_6400 NULL +#define pci_ss_list_1057_6405 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3318 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3319[] = { + &pci_ss_info_105a_3319_8086_3427, + NULL +}; +#define pci_ss_list_105a_3371 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3373[] = { + &pci_ss_info_105a_3373_1043_80f5, + &pci_ss_info_105a_3373_1462_702e, + NULL +}; +#define pci_ss_list_105a_3375 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3376[] = { + &pci_ss_info_105a_3376_1043_809e, + NULL +}; +#define pci_ss_list_105a_3515 NULL +#define pci_ss_list_105a_3519 NULL +#define pci_ss_list_105a_3570 NULL +#define pci_ss_list_105a_3571 NULL +#define pci_ss_list_105a_3574 NULL +#define pci_ss_list_105a_3577 NULL +#define pci_ss_list_105a_3d17 NULL +#define pci_ss_list_105a_3d18 NULL +#define pci_ss_list_105a_3d73 NULL +#define pci_ss_list_105a_3d75 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d69[] = { + &pci_ss_info_105a_4d69_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_1043_807e, + &pci_ss_info_105a_5275_105a_0275, + &pci_ss_info_105a_5275_105a_1275, + &pci_ss_info_105a_5275_1458_b001, + NULL +}; +#define pci_ss_list_105a_5300 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6268[] = { + &pci_ss_info_105a_6268_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_6622 NULL +#define pci_ss_list_105a_6624 NULL +#define pci_ss_list_105a_6626 NULL +#define pci_ss_list_105a_6629 NULL +#define pci_ss_list_105a_7275 NULL +#define pci_ss_list_105a_8002 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_5348[] = { + &pci_ss_info_105d_5348_105d_0037, + NULL +}; +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_0301 NULL +#define pci_ss_list_1067_0304 NULL +#define pci_ss_list_1067_0308 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069_0050[] = { + &pci_ss_info_1069_0050_1069_0050, + &pci_ss_info_1069_0050_1069_0052, + &pci_ss_info_1069_0050_1069_0054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_b166[] = { + &pci_ss_info_1069_b166_1014_0242, + &pci_ss_info_1069_b166_1014_0266, + &pci_ss_info_1069_b166_1014_0278, + &pci_ss_info_1069_b166_1014_02d3, + &pci_ss_info_1069_b166_1014_02d4, + &pci_ss_info_1069_b166_1069_0200, + &pci_ss_info_1069_b166_1069_0202, + &pci_ss_info_1069_b166_1069_0204, + &pci_ss_info_1069_b166_1069_0206, + NULL +}; +#define pci_ss_list_1069_ba55 NULL +static const pciSubsystemInfo *pci_ss_list_1069_ba56[] = { + &pci_ss_info_1069_ba56_1069_0030, + &pci_ss_info_1069_ba56_1069_0040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_ba57[] = { + &pci_ss_info_1069_ba57_1069_0072, + NULL +}; +#endif +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000c NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b_0031[] = { + &pci_ss_info_106b_0031_106b_5811, + NULL +}; +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_0035 NULL +#define pci_ss_list_106b_0036 NULL +#define pci_ss_list_106b_003b NULL +#define pci_ss_list_106b_003e NULL +#define pci_ss_list_106b_003f NULL +#define pci_ss_list_106b_0040 NULL +#define pci_ss_list_106b_0041 NULL +#define pci_ss_list_106b_0042 NULL +#define pci_ss_list_106b_0043 NULL +#define pci_ss_list_106b_0045 NULL +#define pci_ss_list_106b_0046 NULL +#define pci_ss_list_106b_0047 NULL +#define pci_ss_list_106b_0048 NULL +#define pci_ss_list_106b_0049 NULL +#define pci_ss_list_106b_004b NULL +#define pci_ss_list_106b_004c NULL +#define pci_ss_list_106b_004f NULL +#define pci_ss_list_106b_0050 NULL +#define pci_ss_list_106b_0051 NULL +#define pci_ss_list_106b_0052 NULL +#define pci_ss_list_106b_0053 NULL +#define pci_ss_list_106b_0054 NULL +#define pci_ss_list_106b_0055 NULL +#define pci_ss_list_106b_0058 NULL +#define pci_ss_list_106b_0059 NULL +#define pci_ss_list_106b_0066 NULL +#define pci_ss_list_106b_0067 NULL +#define pci_ss_list_106b_0068 NULL +#define pci_ss_list_106b_0069 NULL +#define pci_ss_list_106b_006a NULL +#define pci_ss_list_106b_006b NULL +#define pci_ss_list_106b_1645 NULL +#endif +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1071_8160 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1077_2200[] = { + &pci_ss_info_1077_2200_1077_0002, + NULL +}; +#define pci_ss_list_1077_2300 NULL +#define pci_ss_list_1077_2312 NULL +#define pci_ss_list_1077_2322 NULL +#define pci_ss_list_1077_2422 NULL +#define pci_ss_list_1077_2432 NULL +#define pci_ss_list_1077_3010 NULL +#define pci_ss_list_1077_3022 NULL +#define pci_ss_list_1077_4010 NULL +#define pci_ss_list_1077_4022 NULL +#define pci_ss_list_1077_6312 NULL +#define pci_ss_list_1077_6322 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107d_2134 NULL +#define pci_ss_list_107d_2971 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_1648 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_8002 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_108e_a801 NULL +#define pci_ss_list_108e_abba NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1091_07a0 NULL +#define pci_ss_list_1091_1091 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1310 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_14e0 NULL +#define pci_ss_list_1093_14f0 NULL +#define pci_ss_list_1093_17d0 NULL +#define pci_ss_list_1093_1870 NULL +#define pci_ss_list_1093_1880 NULL +#define pci_ss_list_1093_18b0 NULL +#define pci_ss_list_1093_2410 NULL +#define pci_ss_list_1093_2890 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_2a70 NULL +#define pci_ss_list_1093_2a80 NULL +#define pci_ss_list_1093_2c80 NULL +#define pci_ss_list_1093_2ca0 NULL +#define pci_ss_list_1093_70a9 NULL +#define pci_ss_list_1093_70b8 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0240 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0648[] = { + &pci_ss_info_1095_0648_1043_8025, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0680[] = { + &pci_ss_info_1095_0680_1095_3680, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3112[] = { + &pci_ss_info_1095_3112_1095_3112, + &pci_ss_info_1095_3112_1095_6112, + &pci_ss_info_1095_3112_9005_0250, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3114[] = { + &pci_ss_info_1095_3114_1095_3114, + &pci_ss_info_1095_3114_1095_6114, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3124[] = { + &pci_ss_info_1095_3124_1095_3124, + NULL +}; +#define pci_ss_list_1095_3132 NULL +static const pciSubsystemInfo *pci_ss_list_1095_3512[] = { + &pci_ss_info_1095_3512_1095_3512, + &pci_ss_info_1095_3512_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_032e NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_0071_0101, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0002, + &pci_ss_info_109e_036e_1461_0003, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_1461_0761, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1822_0001, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_18ac_d500, + &pci_ss_info_109e_036e_270f_fc00, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_0071_0101, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0002, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_1461_0761, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_1822_0001, + &pci_ss_info_109e_0878_18ac_d500, + &pci_ss_info_109e_0878_270f_fc00, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_3052 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9_0009[] = { + &pci_ss_info_10a9_0009_10a9_8002, + NULL +}; +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_100a NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_4001 NULL +#define pci_ss_list_10a9_4002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#define pci_ss_list_10a9_8010 NULL +#define pci_ss_list_10a9_8018 NULL +#endif +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1042 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2540 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_6540[] = { + &pci_ss_info_10b5_6540_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6541[] = { + &pci_ss_info_10b5_6541_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6542[] = { + &pci_ss_info_10b5_6542_4c53_10e0, + NULL +}; +#define pci_ss_list_10b5_8111 NULL +#define pci_ss_list_10b5_8114 NULL +#define pci_ss_list_10b5_8516 NULL +#define pci_ss_list_10b5_8532 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_10b5_2862, + &pci_ss_info_10b5_9030_10b5_2906, + &pci_ss_info_10b5_9030_10b5_2940, + &pci_ss_info_10b5_9030_10b5_2977, + &pci_ss_info_10b5_9030_10b5_2978, + &pci_ss_info_10b5_9030_10b5_3025, + &pci_ss_info_10b5_9030_10b5_3068, + &pci_ss_info_10b5_9030_1397_3136, + &pci_ss_info_10b5_9030_1397_3137, + &pci_ss_info_10b5_9030_1518_0200, + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_1067, + &pci_ss_info_10b5_9050_10b5_1172, + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2221, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_2431, + &pci_ss_info_10b5_9050_10b5_2905, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1498_0362, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_2036, + &pci_ss_info_10b5_9050_5654_3132, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + &pci_ss_info_10b5_9054_10b5_2696, + &pci_ss_info_10b5_9054_10b5_2717, + &pci_ss_info_10b5_9054_10b5_2844, + &pci_ss_info_10b5_9054_12c7_4001, + &pci_ss_info_10b5_9054_12d9_0002, + &pci_ss_info_10b5_9054_16df_0011, + &pci_ss_info_10b5_9054_16df_0012, + &pci_ss_info_10b5_9054_16df_0013, + &pci_ss_info_10b5_9054_16df_0014, + &pci_ss_info_10b5_9054_16df_0015, + &pci_ss_info_10b5_9054_16df_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9056[] = { + &pci_ss_info_10b5_9056_10b5_2979, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_103c_10eb, + &pci_ss_info_10b5_9080_103c_10ec, + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + &pci_ss_info_10b5_9080_12d9_0002, + &pci_ss_info_10b5_9080_12df_4422, + NULL +}; +#define pci_ss_list_10b5_bb04 NULL +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_0013[] = { + &pci_ss_info_10b7_0013_10b7_2031, + NULL +}; +#define pci_ss_list_10b7_0910 NULL +#define pci_ss_list_10b7_1006 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_1201 NULL +#define pci_ss_list_10b7_1202 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1700[] = { + &pci_ss_info_10b7_1700_1043_80eb, + &pci_ss_info_10b7_1700_10b7_0010, + &pci_ss_info_10b7_1700_10b7_0020, + &pci_ss_info_10b7_1700_147b_1407, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6000 NULL +#define pci_ss_list_10b7_6001 NULL +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7770 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_80eb NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_1028_0097, + &pci_ss_info_10b7_9200_1028_00fe, + &pci_ss_info_10b7_9200_1028_012a, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + &pci_ss_info_10b7_9200_10f1_2466, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9201[] = { + &pci_ss_info_10b7_9201_1043_80ab, + NULL +}; +#define pci_ss_list_10b7_9202 NULL +#define pci_ss_list_10b7_9210 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990a NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_2802 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +#define pci_ss_list_10b9_0101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_0780 NULL +#define pci_ss_list_10b9_0782 NULL +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_1014_053b, + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1573 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1672 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_1689 NULL +#define pci_ss_list_10b9_1695 NULL +#define pci_ss_list_10b9_1697 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_3323 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +#define pci_ss_list_10b9_5228 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1014_050f, + &pci_ss_info_10b9_5229_1014_053d, + &pci_ss_info_10b9_5229_103c_0024, + &pci_ss_info_10b9_5229_1043_8053, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5237[] = { + &pci_ss_info_10b9_5237_1014_0540, + &pci_ss_info_10b9_5237_103c_0024, + &pci_ss_info_10b9_5237_104d_810f, + NULL +}; +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5246 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_524b NULL +#define pci_ss_list_10b9_524c NULL +#define pci_ss_list_10b9_524d NULL +#define pci_ss_list_10b9_524e NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +#define pci_ss_list_10b9_5263 NULL +#define pci_ss_list_10b9_5281 NULL +#define pci_ss_list_10b9_5287 NULL +#define pci_ss_list_10b9_5288 NULL +#define pci_ss_list_10b9_5289 NULL +#define pci_ss_list_10b9_5450 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + &pci_ss_info_10b9_5451_1014_053e, + &pci_ss_info_10b9_5451_103c_0024, + &pci_ss_info_10b9_5451_10b9_5451, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5457[] = { + &pci_ss_info_10b9_5457_1014_0535, + &pci_ss_info_10b9_5457_103c_0024, + NULL +}; +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5461 NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_1014_0510, + &pci_ss_info_10b9_7101_1014_053c, + &pci_ss_info_10b9_7101_103c_0024, + NULL +}; +#endif +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10ba_0304 NULL +#define pci_ss_list_10ba_0308 NULL +#define pci_ss_list_10ba_1002 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + &pci_ss_info_10c8_0005_1028_0088, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_0088, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cc_0660 NULL +#define pci_ss_list_10cc_0661 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0431 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8626 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10dd_0100 NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c19, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1048_0c1c, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1048_0c21, + &pci_ss_info_10de_0028_1048_0c28, + &pci_ss_info_10de_0028_1048_0c29, + &pci_ss_info_10de_0028_1048_0c2a, + &pci_ss_info_10de_0028_1048_0c2b, + &pci_ss_info_10de_0028_1048_0c31, + &pci_ss_info_10de_0028_1048_0c32, + &pci_ss_info_10de_0028_1048_0c33, + &pci_ss_info_10de_0028_1048_0c34, + &pci_ss_info_10de_0028_107d_2134, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1048_0c2e, + &pci_ss_info_10de_0029_1048_0c2f, + &pci_ss_info_10de_0029_1048_0c30, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1048_0c20, + &pci_ss_info_10de_002c_1048_0c21, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_1048_0c3b, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + &pci_ss_info_10de_002d_1569_002d, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +#define pci_ss_list_10de_0034 NULL +#define pci_ss_list_10de_0035 NULL +#define pci_ss_list_10de_0036 NULL +#define pci_ss_list_10de_0037 NULL +#define pci_ss_list_10de_0038 NULL +#define pci_ss_list_10de_003a NULL +#define pci_ss_list_10de_003b NULL +#define pci_ss_list_10de_003c NULL +#define pci_ss_list_10de_003d NULL +#define pci_ss_list_10de_003e NULL +#define pci_ss_list_10de_0040 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0041[] = { + &pci_ss_info_10de_0041_1043_817b, + NULL +}; +#define pci_ss_list_10de_0042 NULL +#define pci_ss_list_10de_0043 NULL +#define pci_ss_list_10de_0045 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0047[] = { + &pci_ss_info_10de_0047_1682_2109, + NULL +}; +#define pci_ss_list_10de_0049 NULL +#define pci_ss_list_10de_004e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0050[] = { + &pci_ss_info_10de_0050_1043_815a, + &pci_ss_info_10de_0050_1458_0c11, + &pci_ss_info_10de_0050_1462_7100, + NULL +}; +#define pci_ss_list_10de_0051 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0052[] = { + &pci_ss_info_10de_0052_1043_815a, + &pci_ss_info_10de_0052_1458_0c11, + &pci_ss_info_10de_0052_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0053[] = { + &pci_ss_info_10de_0053_1043_815a, + &pci_ss_info_10de_0053_1458_5002, + &pci_ss_info_10de_0053_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0054[] = { + &pci_ss_info_10de_0054_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0055[] = { + &pci_ss_info_10de_0055_1043_815a, + NULL +}; +#define pci_ss_list_10de_0056 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0057[] = { + &pci_ss_info_10de_0057_1043_8141, + &pci_ss_info_10de_0057_1458_e000, + &pci_ss_info_10de_0057_1462_7100, + NULL +}; +#define pci_ss_list_10de_0058 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0059[] = { + &pci_ss_info_10de_0059_1043_812a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005a[] = { + &pci_ss_info_10de_005a_1043_815a, + &pci_ss_info_10de_005a_1458_5004, + &pci_ss_info_10de_005a_1462_7100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005b[] = { + &pci_ss_info_10de_005b_1043_815a, + &pci_ss_info_10de_005b_1458_5004, + &pci_ss_info_10de_005b_1462_7100, + NULL +}; +#define pci_ss_list_10de_005c NULL +#define pci_ss_list_10de_005d NULL +static const pciSubsystemInfo *pci_ss_list_10de_005e[] = { + &pci_ss_info_10de_005e_1458_5000, + &pci_ss_info_10de_005e_1462_7100, + NULL +}; +#define pci_ss_list_10de_005f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + NULL +}; +#define pci_ss_list_10de_0064 NULL +#define pci_ss_list_10de_0065 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0066[] = { + &pci_ss_info_10de_0066_1043_80a7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + NULL +}; +#define pci_ss_list_10de_006a NULL +static const pciSubsystemInfo *pci_ss_list_10de_006b[] = { + &pci_ss_info_10de_006b_10de_006b, + NULL +}; +#define pci_ss_list_10de_006c NULL +#define pci_ss_list_10de_006d NULL +#define pci_ss_list_10de_006e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0080[] = { + &pci_ss_info_10de_0080_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0084[] = { + &pci_ss_info_10de_0084_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0085[] = { + &pci_ss_info_10de_0085_147b_1c09, + NULL +}; +#define pci_ss_list_10de_0086 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0087[] = { + &pci_ss_info_10de_0087_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0088[] = { + &pci_ss_info_10de_0088_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_008a[] = { + &pci_ss_info_10de_008a_147b_1c09, + NULL +}; +#define pci_ss_list_10de_008b NULL +#define pci_ss_list_10de_008c NULL +#define pci_ss_list_10de_008e NULL +#define pci_ss_list_10de_0091 NULL +#define pci_ss_list_10de_0092 NULL +#define pci_ss_list_10de_0099 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +#define pci_ss_list_10de_00c0 NULL +#define pci_ss_list_10de_00c1 NULL +#define pci_ss_list_10de_00c2 NULL +#define pci_ss_list_10de_00c8 NULL +#define pci_ss_list_10de_00c9 NULL +#define pci_ss_list_10de_00cc NULL +#define pci_ss_list_10de_00cd NULL +#define pci_ss_list_10de_00ce NULL +#define pci_ss_list_10de_00d0 NULL +#define pci_ss_list_10de_00d1 NULL +#define pci_ss_list_10de_00d2 NULL +#define pci_ss_list_10de_00d3 NULL +#define pci_ss_list_10de_00d4 NULL +#define pci_ss_list_10de_00d5 NULL +#define pci_ss_list_10de_00d6 NULL +#define pci_ss_list_10de_00d7 NULL +#define pci_ss_list_10de_00d8 NULL +#define pci_ss_list_10de_00d9 NULL +#define pci_ss_list_10de_00da NULL +#define pci_ss_list_10de_00dd NULL +static const pciSubsystemInfo *pci_ss_list_10de_00df[] = { + &pci_ss_info_10de_00df_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e0[] = { + &pci_ss_info_10de_00e0_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e1[] = { + &pci_ss_info_10de_00e1_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e2 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e3[] = { + &pci_ss_info_10de_00e3_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e4[] = { + &pci_ss_info_10de_00e4_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e5[] = { + &pci_ss_info_10de_00e5_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e6 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e7[] = { + &pci_ss_info_10de_00e7_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e8[] = { + &pci_ss_info_10de_00e8_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00ea[] = { + &pci_ss_info_10de_00ea_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00ed NULL +#define pci_ss_list_10de_00ee NULL +#define pci_ss_list_10de_00f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f1[] = { + &pci_ss_info_10de_00f1_1043_81a6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00f2[] = { + &pci_ss_info_10de_00f2_1682_211c, + NULL +}; +#define pci_ss_list_10de_00f3 NULL +#define pci_ss_list_10de_00f8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f9[] = { + &pci_ss_info_10de_00f9_1682_2120, + NULL +}; +#define pci_ss_list_10de_00fa NULL +#define pci_ss_list_10de_00fb NULL +#define pci_ss_list_10de_00fc NULL +#define pci_ss_list_10de_00fd NULL +#define pci_ss_list_10de_00fe NULL +#define pci_ss_list_10de_00ff NULL +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1048_0c41, + &pci_ss_info_10de_0100_1048_0c43, + &pci_ss_info_10de_0100_1048_0c48, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1048_0c42, + &pci_ss_info_10de_0101_107d_2822, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0103[] = { + &pci_ss_info_10de_0103_1048_0c40, + &pci_ss_info_10de_0103_1048_0c44, + &pci_ss_info_10de_0103_1048_0c45, + &pci_ss_info_10de_0103_1048_0c4a, + &pci_ss_info_10de_0103_1048_0c4b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1048_0c60, + &pci_ss_info_10de_0110_1048_0c61, + &pci_ss_info_10de_0110_1048_0c63, + &pci_ss_info_10de_0110_1048_0c64, + &pci_ss_info_10de_0110_1048_0c65, + &pci_ss_info_10de_0110_1048_0c66, + &pci_ss_info_10de_0110_10de_0091, + &pci_ss_info_10de_0110_10de_00a1, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +#define pci_ss_list_10de_0140 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0141[] = { + &pci_ss_info_10de_0141_1458_3124, + NULL +}; +#define pci_ss_list_10de_0142 NULL +#define pci_ss_list_10de_0144 NULL +#define pci_ss_list_10de_0145 NULL +#define pci_ss_list_10de_0146 NULL +#define pci_ss_list_10de_0148 NULL +#define pci_ss_list_10de_014e NULL +#define pci_ss_list_10de_014f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_1048_0c50, + &pci_ss_info_10de_0150_1048_0c52, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_107d_2842, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + &pci_ss_info_10de_0151_1462_5506, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0161 NULL +#define pci_ss_list_10de_0164 NULL +#define pci_ss_list_10de_0165 NULL +#define pci_ss_list_10de_0167 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_10b0_0002, + &pci_ss_info_10de_0171_10de_0008, + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_1462_8852, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0176[] = { + &pci_ss_info_10de_0176_4c53_1090, + NULL +}; +#define pci_ss_list_10de_0177 NULL +#define pci_ss_list_10de_0178 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0179[] = { + &pci_ss_info_10de_0179_10de_0179, + NULL +}; +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_017d NULL +static const pciSubsystemInfo *pci_ss_list_10de_0181[] = { + &pci_ss_info_10de_0181_1043_806f, + &pci_ss_info_10de_0181_1462_8880, + &pci_ss_info_10de_0181_1462_8900, + &pci_ss_info_10de_0181_1462_9350, + &pci_ss_info_10de_0181_147b_8f0d, + NULL +}; +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0185 NULL +#define pci_ss_list_10de_0186 NULL +#define pci_ss_list_10de_0187 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_018d NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b0 NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +static const pciSubsystemInfo *pci_ss_list_10de_01e0[] = { + &pci_ss_info_10de_01e0_147b_1c09, + NULL +}; +#define pci_ss_list_10de_01e8 NULL +#define pci_ss_list_10de_01ea NULL +#define pci_ss_list_10de_01eb NULL +#define pci_ss_list_10de_01ec NULL +#define pci_ss_list_10de_01ed NULL +#define pci_ss_list_10de_01ee NULL +#define pci_ss_list_10de_01ef NULL +#define pci_ss_list_10de_01f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + &pci_ss_info_10de_0200_1048_0c70, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0221 NULL +#define pci_ss_list_10de_0240 NULL +#define pci_ss_list_10de_0241 NULL +#define pci_ss_list_10de_0242 NULL +#define pci_ss_list_10de_0243 NULL +#define pci_ss_list_10de_0244 NULL +#define pci_ss_list_10de_0245 NULL +#define pci_ss_list_10de_0246 NULL +#define pci_ss_list_10de_0247 NULL +#define pci_ss_list_10de_0248 NULL +#define pci_ss_list_10de_0249 NULL +#define pci_ss_list_10de_024a NULL +#define pci_ss_list_10de_024b NULL +#define pci_ss_list_10de_024c NULL +#define pci_ss_list_10de_024d NULL +#define pci_ss_list_10de_024e NULL +#define pci_ss_list_10de_024f NULL +#define pci_ss_list_10de_0250 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0251[] = { + &pci_ss_info_10de_0251_1043_8023, + NULL +}; +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +#define pci_ss_list_10de_0260 NULL +#define pci_ss_list_10de_0261 NULL +#define pci_ss_list_10de_0262 NULL +#define pci_ss_list_10de_0263 NULL +#define pci_ss_list_10de_0264 NULL +#define pci_ss_list_10de_0265 NULL +#define pci_ss_list_10de_0266 NULL +#define pci_ss_list_10de_0267 NULL +#define pci_ss_list_10de_0268 NULL +#define pci_ss_list_10de_0269 NULL +#define pci_ss_list_10de_026a NULL +#define pci_ss_list_10de_026b NULL +#define pci_ss_list_10de_026c NULL +#define pci_ss_list_10de_026d NULL +#define pci_ss_list_10de_026e NULL +#define pci_ss_list_10de_026f NULL +#define pci_ss_list_10de_0270 NULL +#define pci_ss_list_10de_0271 NULL +#define pci_ss_list_10de_0272 NULL +#define pci_ss_list_10de_027e NULL +#define pci_ss_list_10de_027f NULL +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0286 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_028c NULL +#define pci_ss_list_10de_02a0 NULL +#define pci_ss_list_10de_02f0 NULL +#define pci_ss_list_10de_02f1 NULL +#define pci_ss_list_10de_02f2 NULL +#define pci_ss_list_10de_02f3 NULL +#define pci_ss_list_10de_02f4 NULL +#define pci_ss_list_10de_02f5 NULL +#define pci_ss_list_10de_02f6 NULL +#define pci_ss_list_10de_02f7 NULL +#define pci_ss_list_10de_02f8 NULL +#define pci_ss_list_10de_02f9 NULL +#define pci_ss_list_10de_02fa NULL +#define pci_ss_list_10de_02fb NULL +#define pci_ss_list_10de_02fc NULL +#define pci_ss_list_10de_02fd NULL +#define pci_ss_list_10de_02fe NULL +#define pci_ss_list_10de_02ff NULL +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10de_0311 NULL +#define pci_ss_list_10de_0312 NULL +#define pci_ss_list_10de_0313 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0314[] = { + &pci_ss_info_10de_0314_1043_814a, + NULL +}; +#define pci_ss_list_10de_0316 NULL +#define pci_ss_list_10de_0317 NULL +#define pci_ss_list_10de_031a NULL +#define pci_ss_list_10de_031b NULL +#define pci_ss_list_10de_031c NULL +#define pci_ss_list_10de_031d NULL +#define pci_ss_list_10de_031e NULL +#define pci_ss_list_10de_031f NULL +#define pci_ss_list_10de_0320 NULL +#define pci_ss_list_10de_0321 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0322[] = { + &pci_ss_info_10de_0322_1462_9171, + &pci_ss_info_10de_0322_1462_9360, + NULL +}; +#define pci_ss_list_10de_0323 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0324[] = { + &pci_ss_info_10de_0324_1028_0196, + &pci_ss_info_10de_0324_1071_8160, + NULL +}; +#define pci_ss_list_10de_0325 NULL +#define pci_ss_list_10de_0326 NULL +#define pci_ss_list_10de_0327 NULL +#define pci_ss_list_10de_0328 NULL +#define pci_ss_list_10de_0329 NULL +#define pci_ss_list_10de_032a NULL +#define pci_ss_list_10de_032b NULL +#define pci_ss_list_10de_032c NULL +#define pci_ss_list_10de_032d NULL +#define pci_ss_list_10de_032f NULL +#define pci_ss_list_10de_0330 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0331[] = { + &pci_ss_info_10de_0331_1043_8145, + NULL +}; +#define pci_ss_list_10de_0332 NULL +#define pci_ss_list_10de_0333 NULL +#define pci_ss_list_10de_0334 NULL +#define pci_ss_list_10de_0338 NULL +#define pci_ss_list_10de_033f NULL +#define pci_ss_list_10de_0341 NULL +#define pci_ss_list_10de_0342 NULL +#define pci_ss_list_10de_0343 NULL +#define pci_ss_list_10de_0344 NULL +#define pci_ss_list_10de_0345 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0347[] = { + &pci_ss_info_10de_0347_103c_006a, + NULL +}; +#define pci_ss_list_10de_0348 NULL +#define pci_ss_list_10de_0349 NULL +#define pci_ss_list_10de_034b NULL +#define pci_ss_list_10de_034c NULL +#define pci_ss_list_10de_034e NULL +#define pci_ss_list_10de_034f NULL +#define pci_ss_list_10de_0360 NULL +#define pci_ss_list_10de_0361 NULL +#define pci_ss_list_10de_0362 NULL +#define pci_ss_list_10de_0363 NULL +#define pci_ss_list_10de_0364 NULL +#define pci_ss_list_10de_0365 NULL +#define pci_ss_list_10de_0366 NULL +#define pci_ss_list_10de_0367 NULL +#define pci_ss_list_10de_0368 NULL +#define pci_ss_list_10de_0369 NULL +#define pci_ss_list_10de_036a NULL +#define pci_ss_list_10de_036c NULL +#define pci_ss_list_10de_036d NULL +#define pci_ss_list_10de_036e NULL +#define pci_ss_list_10de_0371 NULL +#define pci_ss_list_10de_0372 NULL +#define pci_ss_list_10de_0373 NULL +#define pci_ss_list_10de_037a NULL +#define pci_ss_list_10de_037e NULL +#define pci_ss_list_10de_037f NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f0a1 NULL +#define pci_ss_list_10df_f0a5 NULL +#define pci_ss_list_10df_f0b5 NULL +#define pci_ss_list_10df_f0d1 NULL +#define pci_ss_list_10df_f0d5 NULL +#define pci_ss_list_10df_f0e1 NULL +#define pci_ss_list_10df_f0e5 NULL +#define pci_ss_list_10df_f0f5 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f701 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f801 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f901 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10df_f981 NULL +#define pci_ss_list_10df_f982 NULL +#define pci_ss_list_10df_fa00 NULL +#define pci_ss_list_10df_fb00 NULL +#define pci_ss_list_10df_fc00 NULL +#define pci_ss_list_10df_fc10 NULL +#define pci_ss_list_10df_fc20 NULL +#define pci_ss_list_10df_fd00 NULL +#define pci_ss_list_10df_fe00 NULL +#define pci_ss_list_10df_ff00 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0148 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e3_8260 NULL +#define pci_ss_list_10e3_8261 NULL +#define pci_ss_list_10e4_8029 NULL +#define pci_ss_list_10e8_1072 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_814c NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_81e6 NULL +#define pci_ss_list_10e8_8291 NULL +#define pci_ss_list_10e8_82c4 NULL +#define pci_ss_list_10e8_82c5 NULL +#define pci_ss_list_10e8_82c6 NULL +#define pci_ss_list_10e8_82c7 NULL +#define pci_ss_list_10e8_82ca NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10e8_82e2 NULL +#define pci_ss_list_10e8_8851 NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10ea_5252 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#define pci_ss_list_10ec_0139 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_0357_000a, + &pci_ss_info_10ec_8139_1025_005a, + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_103c_006a, + &pci_ss_info_10ec_8139_1043_8109, + &pci_ss_info_10ec_8139_1071_8160, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1113_ec01, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_1458_e000, + &pci_ss_info_10ec_8139_1462_788c, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_14cb_0200, + &pci_ss_info_10ec_8139_1799_5000, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_9001_1695, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1259_c107, + &pci_ss_info_10ec_8169_1371_434e, + &pci_ss_info_10ec_8169_1458_e000, + &pci_ss_info_10ec_8169_1462_702c, + NULL +}; +#define pci_ss_list_10ec_8180 NULL +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_0205 NULL +#define pci_ss_list_10ee_0210 NULL +#define pci_ss_list_10ee_0314 NULL +#define pci_ss_list_10ee_0405 NULL +#define pci_ss_list_10ee_0410 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ee_3fc6 NULL +#define pci_ss_list_10ee_8381 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#define pci_ss_list_1101_9502 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_100a, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + &pci_ss_info_1102_0002_1102_8064, + &pci_ss_info_1102_0002_1102_8065, + &pci_ss_info_1102_0002_1102_8067, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + &pci_ss_info_1102_0004_1102_0058, + &pci_ss_info_1102_0004_1102_1007, + &pci_ss_info_1102_0004_1102_2002, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_0007[] = { + &pci_ss_info_1102_0007_1102_0007, + &pci_ss_info_1102_0007_1102_1001, + &pci_ss_info_1102_0007_1102_1002, + &pci_ss_info_1102_0007_1102_1006, + &pci_ss_info_1102_0007_1462_1009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0008[] = { + &pci_ss_info_1102_0008_1102_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +static const pciSubsystemInfo *pci_ss_list_1102_7005[] = { + &pci_ss_info_1102_7005_1102_1001, + &pci_ss_info_1102_7005_1102_1002, + NULL +}; +#define pci_ss_list_1102_8064 NULL +static const pciSubsystemInfo *pci_ss_list_1102_8938[] = { + &pci_ss_info_1102_8938_1033_80e5, + &pci_ss_info_1102_8938_1071_7150, + &pci_ss_info_1102_8938_110a_5938, + &pci_ss_info_1102_8938_13bd_100c, + &pci_ss_info_1102_8938_13bd_100d, + &pci_ss_info_1102_8938_13bd_100e, + &pci_ss_info_1102_8938_13bd_f6f1, + &pci_ss_info_1102_8938_14ff_0e70, + &pci_ss_info_1102_8938_14ff_c401, + &pci_ss_info_1102_8938_156d_b400, + &pci_ss_info_1102_8938_156d_b550, + &pci_ss_info_1102_8938_156d_b560, + &pci_ss_info_1102_8938_156d_b700, + &pci_ss_info_1102_8938_156d_b795, + &pci_ss_info_1102_8938_156d_b797, + NULL +}; +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0003, + &pci_ss_info_1103_0004_1103_0004, + &pci_ss_info_1103_0004_1103_0005, + &pci_ss_info_1103_0004_1103_0006, + &pci_ss_info_1103_0004_1103_0007, + &pci_ss_info_1103_0004_1103_0008, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#define pci_ss_list_1103_0009 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1105_8401 NULL +#define pci_ss_list_1105_8470 NULL +#define pci_ss_list_1105_8471 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105_8475[] = { + &pci_ss_info_1105_8475_1105_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1105_8476[] = { + &pci_ss_info_1105_8476_127d_0000, + NULL +}; +#define pci_ss_list_1105_8485 NULL +#define pci_ss_list_1105_8486 NULL +#endif +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +#define pci_ss_list_1106_0204 NULL +#define pci_ss_list_1106_0238 NULL +#define pci_ss_list_1106_0259 NULL +#define pci_ss_list_1106_0269 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106_0282[] = { + &pci_ss_info_1106_0282_1043_80a3, + NULL +}; +#define pci_ss_list_1106_0290 NULL +#define pci_ss_list_1106_0296 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1019_0987, + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0308 NULL +#define pci_ss_list_1106_0314 NULL +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1019_0985, + &pci_ss_info_1106_0571_1019_0a81, + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1043_808c, + &pci_ss_info_1106_0571_1043_80a1, + &pci_ss_info_1106_0571_1043_80ed, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1297_f641, + &pci_ss_info_1106_0571_1458_5002, + &pci_ss_info_1106_0571_1462_7020, + &pci_ss_info_1106_0571_147b_1407, + &pci_ss_info_1106_0571_1849_0571, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0591 NULL +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0605[] = { + &pci_ss_info_1106_0605_1043_802c, + NULL +}; +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1019_0985, + &pci_ss_info_1106_0686_1043_802c, + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1019_0985, + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1204 NULL +#define pci_ss_list_1106_1208 NULL +#define pci_ss_list_1106_1238 NULL +#define pci_ss_list_1106_1258 NULL +#define pci_ss_list_1106_1259 NULL +#define pci_ss_list_1106_1269 NULL +#define pci_ss_list_1106_1282 NULL +#define pci_ss_list_1106_1290 NULL +#define pci_ss_list_1106_1296 NULL +#define pci_ss_list_1106_1308 NULL +#define pci_ss_list_1106_1314 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +#define pci_ss_list_1106_2204 NULL +#define pci_ss_list_1106_2208 NULL +#define pci_ss_list_1106_2238 NULL +#define pci_ss_list_1106_2258 NULL +#define pci_ss_list_1106_2259 NULL +#define pci_ss_list_1106_2269 NULL +#define pci_ss_list_1106_2282 NULL +#define pci_ss_list_1106_2290 NULL +#define pci_ss_list_1106_2296 NULL +#define pci_ss_list_1106_2308 NULL +#define pci_ss_list_1106_2314 NULL +#define pci_ss_list_1106_287a NULL +#define pci_ss_list_1106_287b NULL +#define pci_ss_list_1106_287c NULL +#define pci_ss_list_1106_287d NULL +#define pci_ss_list_1106_287e NULL +#define pci_ss_list_1106_3022 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1019_0985, + &pci_ss_info_1106_3038_1019_0a81, + &pci_ss_info_1106_3038_1043_8080, + &pci_ss_info_1106_3038_1043_808c, + &pci_ss_info_1106_3038_1043_80a1, + &pci_ss_info_1106_3038_1043_80ed, + &pci_ss_info_1106_3038_1179_0001, + &pci_ss_info_1106_3038_1458_5004, + &pci_ss_info_1106_3038_1462_7020, + &pci_ss_info_1106_3038_147b_1407, + &pci_ss_info_1106_3038_182d_201d, + &pci_ss_info_1106_3038_1849_3038, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3044[] = { + &pci_ss_info_1106_3044_0574_086c, + &pci_ss_info_1106_3044_1025_005a, + &pci_ss_info_1106_3044_1043_808a, + &pci_ss_info_1106_3044_1458_1000, + &pci_ss_info_1106_3044_1462_702d, + &pci_ss_info_1106_3044_1462_971d, + NULL +}; +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +#define pci_ss_list_1106_3053 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1019_0985, + &pci_ss_info_1106_3057_1019_0987, + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_0097, + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1019_0985, + &pci_ss_info_1106_3058_1019_0987, + &pci_ss_info_1106_3058_1043_1106, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_1462_3300, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1019_0a81, + &pci_ss_info_1106_3059_1043_8095, + &pci_ss_info_1106_3059_1043_80a1, + &pci_ss_info_1106_3059_1043_80b0, + &pci_ss_info_1106_3059_1043_812a, + &pci_ss_info_1106_3059_1106_3059, + &pci_ss_info_1106_3059_1106_4161, + &pci_ss_info_1106_3059_1297_c160, + &pci_ss_info_1106_3059_1458_a002, + &pci_ss_info_1106_3059_1462_0080, + &pci_ss_info_1106_3059_1462_3800, + &pci_ss_info_1106_3059_147b_1407, + &pci_ss_info_1106_3059_1849_9761, + &pci_ss_info_1106_3059_4005_4710, + &pci_ss_info_1106_3059_4170_1106, + &pci_ss_info_1106_3059_4552_1106, + &pci_ss_info_1106_3059_a0a0_01b6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1043_80a1, + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + &pci_ss_info_1106_3065_13b9_1421, + &pci_ss_info_1106_3065_147b_1c09, + &pci_ss_info_1106_3065_1695_3005, + &pci_ss_info_1106_3065_1695_300c, + &pci_ss_info_1106_3065_1849_3065, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3068[] = { + &pci_ss_info_1106_3068_1462_309e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + &pci_ss_info_1106_3099_1849_3099, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1019_0a81, + &pci_ss_info_1106_3104_1043_808c, + &pci_ss_info_1106_3104_1043_80a1, + &pci_ss_info_1106_3104_1043_80ed, + &pci_ss_info_1106_3104_1297_f641, + &pci_ss_info_1106_3104_1458_5004, + &pci_ss_info_1106_3104_1462_7020, + &pci_ss_info_1106_3104_147b_1407, + &pci_ss_info_1106_3104_182d_201d, + &pci_ss_info_1106_3104_1849_3104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3106[] = { + &pci_ss_info_1106_3106_1186_1403, + NULL +}; +#define pci_ss_list_1106_3108 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3113 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3116[] = { + &pci_ss_info_1106_3116_1297_f641, + NULL +}; +#define pci_ss_list_1106_3118 NULL +#define pci_ss_list_1106_3119 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3147[] = { + &pci_ss_info_1106_3147_1043_808c, + NULL +}; +#define pci_ss_list_1106_3148 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3149[] = { + &pci_ss_info_1106_3149_1043_80ed, + &pci_ss_info_1106_3149_1458_b003, + &pci_ss_info_1106_3149_1462_7020, + &pci_ss_info_1106_3149_147b_1407, + &pci_ss_info_1106_3149_147b_1408, + &pci_ss_info_1106_3149_1849_3149, + NULL +}; +#define pci_ss_list_1106_3156 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3164[] = { + &pci_ss_info_1106_3164_1043_80f4, + &pci_ss_info_1106_3164_1462_7028, + NULL +}; +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1019_0a81, + &pci_ss_info_1106_3177_1043_808c, + &pci_ss_info_1106_3177_1043_80a1, + &pci_ss_info_1106_3177_1297_f641, + &pci_ss_info_1106_3177_1458_5001, + &pci_ss_info_1106_3177_1849_3177, + NULL +}; +#define pci_ss_list_1106_3178 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3188[] = { + &pci_ss_info_1106_3188_1043_80a3, + &pci_ss_info_1106_3188_147b_1407, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1043_807f, + &pci_ss_info_1106_3189_1458_5000, + &pci_ss_info_1106_3189_1849_3189, + NULL +}; +#define pci_ss_list_1106_3204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3205[] = { + &pci_ss_info_1106_3205_1458_5000, + NULL +}; +#define pci_ss_list_1106_3208 NULL +#define pci_ss_list_1106_3213 NULL +#define pci_ss_list_1106_3218 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3227[] = { + &pci_ss_info_1106_3227_1043_80ed, + &pci_ss_info_1106_3227_1106_3227, + &pci_ss_info_1106_3227_1458_5001, + &pci_ss_info_1106_3227_147b_1407, + &pci_ss_info_1106_3227_1849_3227, + NULL +}; +#define pci_ss_list_1106_3238 NULL +#define pci_ss_list_1106_3249 NULL +#define pci_ss_list_1106_3258 NULL +#define pci_ss_list_1106_3259 NULL +#define pci_ss_list_1106_3269 NULL +#define pci_ss_list_1106_3282 NULL +#define pci_ss_list_1106_3287 NULL +#define pci_ss_list_1106_3288 NULL +#define pci_ss_list_1106_3290 NULL +#define pci_ss_list_1106_3296 NULL +#define pci_ss_list_1106_3337 NULL +#define pci_ss_list_1106_3344 NULL +#define pci_ss_list_1106_3349 NULL +#define pci_ss_list_1106_337a NULL +#define pci_ss_list_1106_337b NULL +#define pci_ss_list_1106_4149 NULL +#define pci_ss_list_1106_4204 NULL +#define pci_ss_list_1106_4208 NULL +#define pci_ss_list_1106_4238 NULL +#define pci_ss_list_1106_4258 NULL +#define pci_ss_list_1106_4259 NULL +#define pci_ss_list_1106_4269 NULL +#define pci_ss_list_1106_4282 NULL +#define pci_ss_list_1106_4290 NULL +#define pci_ss_list_1106_4296 NULL +#define pci_ss_list_1106_4308 NULL +#define pci_ss_list_1106_4314 NULL +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_5208 NULL +#define pci_ss_list_1106_5238 NULL +#define pci_ss_list_1106_5290 NULL +#define pci_ss_list_1106_5308 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_7204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_7205[] = { + &pci_ss_info_1106_7205_1458_d000, + NULL +}; +#define pci_ss_list_1106_7208 NULL +#define pci_ss_list_1106_7238 NULL +#define pci_ss_list_1106_7258 NULL +#define pci_ss_list_1106_7259 NULL +#define pci_ss_list_1106_7269 NULL +#define pci_ss_list_1106_7282 NULL +#define pci_ss_list_1106_7290 NULL +#define pci_ss_list_1106_7296 NULL +#define pci_ss_list_1106_7308 NULL +#define pci_ss_list_1106_7314 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +static const pciSubsystemInfo *pci_ss_list_1106_8598[] = { + &pci_ss_info_1106_8598_1019_0985, + NULL +}; +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_a208 NULL +#define pci_ss_list_1106_a238 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b113 NULL +#define pci_ss_list_1106_b115 NULL +#define pci_ss_list_1106_b168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_b188[] = { + &pci_ss_info_1106_b188_147b_1407, + NULL +}; +#define pci_ss_list_1106_b198 NULL +#define pci_ss_list_1106_b213 NULL +#define pci_ss_list_1106_c208 NULL +#define pci_ss_list_1106_c238 NULL +#define pci_ss_list_1106_d104 NULL +#define pci_ss_list_1106_d208 NULL +#define pci_ss_list_1106_d213 NULL +#define pci_ss_list_1106_d238 NULL +#define pci_ss_list_1106_e208 NULL +#define pci_ss_list_1106_e238 NULL +#define pci_ss_list_1106_f208 NULL +#define pci_ss_list_1106_f238 NULL +#endif +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_0006 NULL +#define pci_ss_list_110a_0015 NULL +#define pci_ss_list_110a_001d NULL +#define pci_ss_list_110a_007b NULL +#define pci_ss_list_110a_007c NULL +#define pci_ss_list_110a_007d NULL +#define pci_ss_list_110a_2101 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_2104 NULL +#define pci_ss_list_110a_3142 NULL +#define pci_ss_list_110a_4021 NULL +#define pci_ss_list_110a_4029 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_1113_2242, + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#define pci_ss_list_1113_d301 NULL +#define pci_ss_list_1113_ec02 NULL +#endif +#define pci_ss_list_1114_0506 NULL +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0010 NULL +#define pci_ss_list_1119_0011 NULL +#define pci_ss_list_1119_0012 NULL +#define pci_ss_list_1119_0013 NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_02ff NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#define pci_ss_list_111a_1203 NULL +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111d_0004 NULL +#define pci_ss_list_111d_0005 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_112f_0008 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_5400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_5402[] = { + &pci_ss_info_1131_5402_1244_0f00, + NULL +}; +#define pci_ss_list_1131_5405 NULL +#define pci_ss_list_1131_5406 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7130[] = { + &pci_ss_info_1131_7130_102b_48d0, + &pci_ss_info_1131_7130_1048_226b, + &pci_ss_info_1131_7130_1131_2001, + &pci_ss_info_1131_7130_1131_2005, + &pci_ss_info_1131_7130_1461_050c, + &pci_ss_info_1131_7130_1461_10ff, + &pci_ss_info_1131_7130_1461_2108, + &pci_ss_info_1131_7130_1461_2115, + &pci_ss_info_1131_7130_153b_1152, + &pci_ss_info_1131_7130_185b_c100, + &pci_ss_info_1131_7130_185b_c901, + &pci_ss_info_1131_7130_5168_0138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7133[] = { + &pci_ss_info_1131_7133_0000_4091, + &pci_ss_info_1131_7133_002b_11bd, + &pci_ss_info_1131_7133_1019_4cb5, + &pci_ss_info_1131_7133_1043_0210, + &pci_ss_info_1131_7133_1043_4843, + &pci_ss_info_1131_7133_1043_4845, + &pci_ss_info_1131_7133_1043_4862, + &pci_ss_info_1131_7133_1131_2001, + &pci_ss_info_1131_7133_1131_2018, + &pci_ss_info_1131_7133_1131_4ee9, + &pci_ss_info_1131_7133_11bd_002e, + &pci_ss_info_1131_7133_12ab_0800, + &pci_ss_info_1131_7133_1421_1370, + &pci_ss_info_1131_7133_1435_7330, + &pci_ss_info_1131_7133_1435_7350, + &pci_ss_info_1131_7133_1461_1044, + &pci_ss_info_1131_7133_1461_f31f, + &pci_ss_info_1131_7133_1462_6231, + &pci_ss_info_1131_7133_1489_0214, + &pci_ss_info_1131_7133_14c0_1212, + &pci_ss_info_1131_7133_153b_1160, + &pci_ss_info_1131_7133_153b_1162, + &pci_ss_info_1131_7133_185b_c100, + &pci_ss_info_1131_7133_4e42_0212, + &pci_ss_info_1131_7133_4e42_0502, + &pci_ss_info_1131_7133_5168_0306, + &pci_ss_info_1131_7133_5168_0319, + &pci_ss_info_1131_7133_5456_7135, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7134[] = { + &pci_ss_info_1131_7134_1019_4cb4, + &pci_ss_info_1131_7134_1043_0210, + &pci_ss_info_1131_7134_1043_4840, + &pci_ss_info_1131_7134_1131_2004, + &pci_ss_info_1131_7134_1131_4e85, + &pci_ss_info_1131_7134_1131_6752, + &pci_ss_info_1131_7134_1131_7133, + &pci_ss_info_1131_7134_11bd_002b, + &pci_ss_info_1131_7134_11bd_002d, + &pci_ss_info_1131_7134_1461_9715, + &pci_ss_info_1131_7134_1461_a70a, + &pci_ss_info_1131_7134_1461_a70b, + &pci_ss_info_1131_7134_1461_d6ee, + &pci_ss_info_1131_7134_1471_b7e9, + &pci_ss_info_1131_7134_153b_1142, + &pci_ss_info_1131_7134_153b_1143, + &pci_ss_info_1131_7134_153b_1158, + &pci_ss_info_1131_7134_1540_9524, + &pci_ss_info_1131_7134_16be_0003, + &pci_ss_info_1131_7134_185b_c200, + &pci_ss_info_1131_7134_185b_c900, + &pci_ss_info_1131_7134_1894_a006, + &pci_ss_info_1131_7134_1894_fe01, + &pci_ss_info_1131_7134_4e42_0138, + NULL +}; +#define pci_ss_list_1131_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_110a_0000, + &pci_ss_info_1131_7146_110a_ffff, + &pci_ss_info_1131_7146_1131_4f56, + &pci_ss_info_1131_7146_1131_4f60, + &pci_ss_info_1131_7146_1131_4f61, + &pci_ss_info_1131_7146_1131_5f61, + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + &pci_ss_info_1131_7146_11bd_000f, + &pci_ss_info_1131_7146_13c2_0000, + &pci_ss_info_1131_7146_13c2_0001, + &pci_ss_info_1131_7146_13c2_0002, + &pci_ss_info_1131_7146_13c2_0003, + &pci_ss_info_1131_7146_13c2_0004, + &pci_ss_info_1131_7146_13c2_0006, + &pci_ss_info_1131_7146_13c2_0008, + &pci_ss_info_1131_7146_13c2_000a, + &pci_ss_info_1131_7146_13c2_1003, + &pci_ss_info_1131_7146_13c2_1004, + &pci_ss_info_1131_7146_13c2_1005, + &pci_ss_info_1131_7146_13c2_100c, + &pci_ss_info_1131_7146_13c2_100f, + &pci_ss_info_1131_7146_13c2_1011, + &pci_ss_info_1131_7146_13c2_1013, + &pci_ss_info_1131_7146_13c2_1016, + &pci_ss_info_1131_7146_13c2_1102, + NULL +}; +#define pci_ss_list_1131_9730 NULL +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#define pci_ss_list_1133_e001 NULL +#define pci_ss_list_1133_e002 NULL +#define pci_ss_list_1133_e003 NULL +#define pci_ss_list_1133_e004 NULL +#define pci_ss_list_1133_e005 NULL +#define pci_ss_list_1133_e006 NULL +#define pci_ss_list_1133_e007 NULL +#define pci_ss_list_1133_e008 NULL +#define pci_ss_list_1133_e009 NULL +#define pci_ss_list_1133_e00a NULL +#define pci_ss_list_1133_e00b NULL +#define pci_ss_list_1133_e00c NULL +#define pci_ss_list_1133_e00d NULL +#define pci_ss_list_1133_e00e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_110a_0021, + NULL +}; +#define pci_ss_list_1133_e011 NULL +#define pci_ss_list_1133_e012 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e013[] = { + &pci_ss_info_1133_e013_1133_1300, + &pci_ss_info_1133_e013_1133_e013, + NULL +}; +#define pci_ss_list_1133_e014 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e015[] = { + &pci_ss_info_1133_e015_1133_e015, + NULL +}; +#define pci_ss_list_1133_e016 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e017[] = { + &pci_ss_info_1133_e017_1133_e017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e018[] = { + &pci_ss_info_1133_e018_1133_1800, + &pci_ss_info_1133_e018_1133_e018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e019[] = { + &pci_ss_info_1133_e019_1133_e019, + NULL +}; +#define pci_ss_list_1133_e01a NULL +static const pciSubsystemInfo *pci_ss_list_1133_e01b[] = { + &pci_ss_info_1133_e01b_1133_e01b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e01c[] = { + &pci_ss_info_1133_e01c_1133_1c01, + &pci_ss_info_1133_e01c_1133_1c02, + &pci_ss_info_1133_e01c_1133_1c03, + &pci_ss_info_1133_e01c_1133_1c04, + &pci_ss_info_1133_e01c_1133_1c05, + &pci_ss_info_1133_e01c_1133_1c06, + &pci_ss_info_1133_e01c_1133_1c07, + &pci_ss_info_1133_e01c_1133_1c08, + &pci_ss_info_1133_e01c_1133_1c09, + &pci_ss_info_1133_e01c_1133_1c0a, + &pci_ss_info_1133_e01c_1133_1c0b, + &pci_ss_info_1133_e01c_1133_1c0c, + NULL +}; +#define pci_ss_list_1133_e01e NULL +#define pci_ss_list_1133_e020 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e024[] = { + &pci_ss_info_1133_e024_1133_2400, + &pci_ss_info_1133_e024_1133_e024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e028[] = { + &pci_ss_info_1133_e028_1133_2800, + &pci_ss_info_1133_e028_1133_e028, + NULL +}; +#define pci_ss_list_1133_e02a NULL +#define pci_ss_list_1133_e02c NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1134_0002 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#define pci_ss_list_1145_f020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2971, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2973, + &pci_ss_info_1148_4300_1259_2974, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2976, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_0121, + &pci_ss_info_1148_4320_1148_0221, + &pci_ss_info_1148_4320_1148_0321, + &pci_ss_info_1148_4320_1148_0421, + &pci_ss_info_1148_4320_1148_0621, + &pci_ss_info_1148_4320_1148_0721, + &pci_ss_info_1148_4320_1148_0821, + &pci_ss_info_1148_4320_1148_0921, + &pci_ss_info_1148_4320_1148_1121, + &pci_ss_info_1148_4320_1148_1221, + &pci_ss_info_1148_4320_1148_3221, + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#define pci_ss_list_1148_4500 NULL +#define pci_ss_list_1148_9000 NULL +#define pci_ss_list_1148_9843 NULL +static const pciSubsystemInfo *pci_ss_list_1148_9e00[] = { + &pci_ss_info_1148_9e00_1148_2100, + &pci_ss_info_1148_9e00_1148_21d0, + &pci_ss_info_1148_9e00_1148_2200, + &pci_ss_info_1148_9e00_1148_8100, + &pci_ss_info_1148_9e00_1148_8200, + &pci_ss_info_1148_9e00_1148_9100, + &pci_ss_info_1148_9e00_1148_9200, + NULL +}; +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0028 NULL +#define pci_ss_list_114f_0029 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0043 NULL +#define pci_ss_list_114f_0044 NULL +#define pci_ss_list_114f_0045 NULL +#define pci_ss_list_114f_004e NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_00b0 NULL +#define pci_ss_list_114f_00b1 NULL +#define pci_ss_list_114f_00c8 NULL +#define pci_ss_list_114f_00c9 NULL +#define pci_ss_list_114f_00ca NULL +#define pci_ss_list_114f_00cb NULL +#define pci_ss_list_114f_00d0 NULL +#define pci_ss_list_114f_00d1 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_0182, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +#define pci_ss_list_115d_00d4 NULL +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0000 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0006 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0036 NULL +#define pci_ss_list_1166_0101 NULL +#define pci_ss_list_1166_0104 NULL +#define pci_ss_list_1166_0110 NULL +#define pci_ss_list_1166_0130 NULL +#define pci_ss_list_1166_0132 NULL +#define pci_ss_list_1166_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166_0201[] = { + &pci_ss_info_1166_0201_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0203[] = { + &pci_ss_info_1166_0203_1734_1012, + NULL +}; +#define pci_ss_list_1166_0205 NULL +#define pci_ss_list_1166_0211 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0212[] = { + &pci_ss_info_1166_0212_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0213[] = { + &pci_ss_info_1166_0213_1028_c134, + &pci_ss_info_1166_0213_1734_1012, + NULL +}; +#define pci_ss_list_1166_0214 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0217[] = { + &pci_ss_info_1166_0217_1028_4134, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0220[] = { + &pci_ss_info_1166_0220_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0221[] = { + &pci_ss_info_1166_0221_1734_1012, + NULL +}; +#define pci_ss_list_1166_0223 NULL +#define pci_ss_list_1166_0225 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0227[] = { + &pci_ss_info_1166_0227_1734_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0230[] = { + &pci_ss_info_1166_0230_4c53_1080, + NULL +}; +#define pci_ss_list_1166_0234 NULL +#define pci_ss_list_1166_0240 NULL +#define pci_ss_list_1166_0241 NULL +#define pci_ss_list_1166_0242 NULL +#define pci_ss_list_1166_024a NULL +#endif +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0102 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0601[] = { + &pci_ss_info_1179_0601_1179_0001, + NULL +}; +#define pci_ss_list_1179_0603 NULL +static const pciSubsystemInfo *pci_ss_list_1179_060a[] = { + &pci_ss_info_1179_060a_1179_0001, + NULL +}; +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c_0030[] = { + &pci_ss_info_117c_0030_117c_8013, + &pci_ss_info_117c_0030_117c_8014, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_1028_0188, + &pci_ss_info_1180_0476_1043_1967, + &pci_ss_info_1180_0476_1043_1987, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + &pci_ss_info_1180_0476_14ef_0220, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +#define pci_ss_list_1180_0511 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + &pci_ss_info_1180_0522_1043_1967, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + &pci_ss_info_1180_0552_1028_0188, + NULL +}; +#define pci_ss_list_1180_0554 NULL +#define pci_ss_list_1180_0575 NULL +#define pci_ss_list_1180_0576 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0592[] = { + &pci_ss_info_1180_0592_1043_1967, + NULL +}; +#define pci_ss_list_1180_0811 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0822[] = { + &pci_ss_info_1180_0822_1014_0556, + &pci_ss_info_1180_0822_1028_0188, + &pci_ss_info_1180_0822_1028_01a2, + &pci_ss_info_1180_0822_1043_1967, + NULL +}; +#define pci_ss_list_1180_0841 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0852[] = { + &pci_ss_info_1180_0852_1043_1967, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +#define pci_ss_list_1186_1025 NULL +#define pci_ss_list_1186_1026 NULL +#define pci_ss_list_1186_1043 NULL +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + &pci_ss_info_1186_1300_1186_1303, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1541 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_2027 NULL +#define pci_ss_list_1186_3203 NULL +#define pci_ss_list_1186_3300 NULL +#define pci_ss_list_1186_3a03 NULL +#define pci_ss_list_1186_3a04 NULL +#define pci_ss_list_1186_3a05 NULL +#define pci_ss_list_1186_3a07 NULL +#define pci_ss_list_1186_3a08 NULL +#define pci_ss_list_1186_3a10 NULL +#define pci_ss_list_1186_3a11 NULL +#define pci_ss_list_1186_3a12 NULL +#define pci_ss_list_1186_3a13 NULL +#define pci_ss_list_1186_3a14 NULL +#define pci_ss_list_1186_3a63 NULL +#define pci_ss_list_1186_4000 NULL +#define pci_ss_list_1186_4300 NULL +static const pciSubsystemInfo *pci_ss_list_1186_4c00[] = { + &pci_ss_info_1186_4c00_1186_4c00, + NULL +}; +#define pci_ss_list_1186_8400 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1191_8060 NULL +#define pci_ss_list_1191_8080 NULL +#define pci_ss_list_1191_8081 NULL +#define pci_ss_list_1191_808a NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_1197_010c NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_138f NULL +#define pci_ss_list_11ab_1fa6 NULL +#define pci_ss_list_11ab_1fa7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab_1faa[] = { + &pci_ss_info_11ab_1faa_1385_4e00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4320[] = { + &pci_ss_info_11ab_4320_1019_0f38, + &pci_ss_info_11ab_4320_1019_8001, + &pci_ss_info_11ab_4320_1043_173c, + &pci_ss_info_11ab_4320_1043_811a, + &pci_ss_info_11ab_4320_105b_0c19, + &pci_ss_info_11ab_4320_10b8_b452, + &pci_ss_info_11ab_4320_11ab_0121, + &pci_ss_info_11ab_4320_11ab_0321, + &pci_ss_info_11ab_4320_11ab_1021, + &pci_ss_info_11ab_4320_11ab_5021, + &pci_ss_info_11ab_4320_11ab_9521, + &pci_ss_info_11ab_4320_1458_e000, + &pci_ss_info_11ab_4320_147b_1406, + &pci_ss_info_11ab_4320_15d4_0047, + &pci_ss_info_11ab_4320_1695_9025, + &pci_ss_info_11ab_4320_17f2_1c03, + &pci_ss_info_11ab_4320_270f_2803, + NULL +}; +#define pci_ss_list_11ab_4340 NULL +#define pci_ss_list_11ab_4341 NULL +#define pci_ss_list_11ab_4342 NULL +#define pci_ss_list_11ab_4343 NULL +#define pci_ss_list_11ab_4344 NULL +#define pci_ss_list_11ab_4345 NULL +#define pci_ss_list_11ab_4346 NULL +#define pci_ss_list_11ab_4347 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4350[] = { + &pci_ss_info_11ab_4350_1179_0001, + &pci_ss_info_11ab_4350_11ab_3521, + &pci_ss_info_11ab_4350_1854_000d, + &pci_ss_info_11ab_4350_1854_000e, + &pci_ss_info_11ab_4350_1854_000f, + &pci_ss_info_11ab_4350_1854_0011, + &pci_ss_info_11ab_4350_1854_0012, + &pci_ss_info_11ab_4350_1854_0016, + &pci_ss_info_11ab_4350_1854_0017, + &pci_ss_info_11ab_4350_1854_0018, + &pci_ss_info_11ab_4350_1854_0019, + &pci_ss_info_11ab_4350_1854_001c, + &pci_ss_info_11ab_4350_1854_001e, + &pci_ss_info_11ab_4350_1854_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4351[] = { + &pci_ss_info_11ab_4351_107b_4009, + &pci_ss_info_11ab_4351_10f7_8338, + &pci_ss_info_11ab_4351_1179_0001, + &pci_ss_info_11ab_4351_1179_ff00, + &pci_ss_info_11ab_4351_1179_ff10, + &pci_ss_info_11ab_4351_11ab_3621, + &pci_ss_info_11ab_4351_13d1_ac12, + &pci_ss_info_11ab_4351_161f_203d, + &pci_ss_info_11ab_4351_1854_000d, + &pci_ss_info_11ab_4351_1854_000e, + &pci_ss_info_11ab_4351_1854_000f, + &pci_ss_info_11ab_4351_1854_0011, + &pci_ss_info_11ab_4351_1854_0012, + &pci_ss_info_11ab_4351_1854_0016, + &pci_ss_info_11ab_4351_1854_0017, + &pci_ss_info_11ab_4351_1854_0018, + &pci_ss_info_11ab_4351_1854_0019, + &pci_ss_info_11ab_4351_1854_001c, + &pci_ss_info_11ab_4351_1854_001e, + &pci_ss_info_11ab_4351_1854_0020, + NULL +}; +#define pci_ss_list_11ab_4352 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4360[] = { + &pci_ss_info_11ab_4360_1043_8134, + &pci_ss_info_11ab_4360_107b_4009, + &pci_ss_info_11ab_4360_11ab_5221, + &pci_ss_info_11ab_4360_1458_e000, + &pci_ss_info_11ab_4360_1462_052c, + &pci_ss_info_11ab_4360_1849_8052, + &pci_ss_info_11ab_4360_a0a0_0509, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4361[] = { + &pci_ss_info_11ab_4361_107b_3015, + &pci_ss_info_11ab_4361_11ab_5021, + &pci_ss_info_11ab_4361_8086_3063, + &pci_ss_info_11ab_4361_8086_3439, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4362[] = { + &pci_ss_info_11ab_4362_103c_2a0d, + &pci_ss_info_11ab_4362_1043_8142, + &pci_ss_info_11ab_4362_109f_3197, + &pci_ss_info_11ab_4362_10f7_8338, + &pci_ss_info_11ab_4362_10fd_a430, + &pci_ss_info_11ab_4362_1179_0001, + &pci_ss_info_11ab_4362_1179_ff00, + &pci_ss_info_11ab_4362_1179_ff10, + &pci_ss_info_11ab_4362_11ab_5321, + &pci_ss_info_11ab_4362_1297_c240, + &pci_ss_info_11ab_4362_1297_c241, + &pci_ss_info_11ab_4362_1297_c242, + &pci_ss_info_11ab_4362_1297_c243, + &pci_ss_info_11ab_4362_1297_c244, + &pci_ss_info_11ab_4362_13d1_ac11, + &pci_ss_info_11ab_4362_1458_e000, + &pci_ss_info_11ab_4362_1462_058c, + &pci_ss_info_11ab_4362_14c0_0012, + &pci_ss_info_11ab_4362_1558_04a0, + &pci_ss_info_11ab_4362_15bd_1003, + &pci_ss_info_11ab_4362_161f_203c, + &pci_ss_info_11ab_4362_161f_203d, + &pci_ss_info_11ab_4362_1695_9029, + &pci_ss_info_11ab_4362_17f2_2c08, + &pci_ss_info_11ab_4362_17ff_0585, + &pci_ss_info_11ab_4362_1849_8053, + &pci_ss_info_11ab_4362_1854_000b, + &pci_ss_info_11ab_4362_1854_000c, + &pci_ss_info_11ab_4362_1854_0010, + &pci_ss_info_11ab_4362_1854_0013, + &pci_ss_info_11ab_4362_1854_0014, + &pci_ss_info_11ab_4362_1854_0015, + &pci_ss_info_11ab_4362_1854_001a, + &pci_ss_info_11ab_4362_1854_001b, + &pci_ss_info_11ab_4362_1854_001d, + &pci_ss_info_11ab_4362_1854_001f, + &pci_ss_info_11ab_4362_1854_0021, + &pci_ss_info_11ab_4362_1854_0022, + &pci_ss_info_11ab_4362_270f_2801, + &pci_ss_info_11ab_4362_a0a0_0506, + NULL +}; +#define pci_ss_list_11ab_4363 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_5005 NULL +#define pci_ss_list_11ab_5040 NULL +#define pci_ss_list_11ab_5041 NULL +#define pci_ss_list_11ab_5080 NULL +#define pci_ss_list_11ab_5081 NULL +#define pci_ss_list_11ab_6041 NULL +#define pci_ss_list_11ab_6081 NULL +#define pci_ss_list_11ab_6460 NULL +#define pci_ss_list_11ab_6480 NULL +#define pci_ss_list_11ab_f003 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11af_0001 NULL +#define pci_ss_list_11af_ee40 NULL +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#define pci_ss_list_11bd_002e NULL +#define pci_ss_list_11bd_bede NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0445[] = { + &pci_ss_info_11c1_0445_8086_2203, + &pci_ss_info_11c1_0445_8086_2204, + NULL +}; +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_1033_80a8, + &pci_ss_info_11c1_0450_144f_4005, + &pci_ss_info_11c1_0450_1468_0450, + &pci_ss_info_11c1_0450_4005_144f, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_048c NULL +#define pci_ss_list_11c1_048f NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_8086_524c, + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_8110[] = { + &pci_ss_info_11c1_8110_12d9_000c, + NULL +}; +#define pci_ss_list_11c1_ab10 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab11[] = { + &pci_ss_info_11c1_ab11_11c1_ab12, + &pci_ss_info_11c1_ab11_11c1_ab13, + &pci_ss_info_11c1_ab11_11c1_ab15, + &pci_ss_info_11c1_ab11_11c1_ab16, + NULL +}; +#define pci_ss_list_11c1_ab20 NULL +#define pci_ss_list_11c1_ab21 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab30[] = { + &pci_ss_info_11c1_ab30_14cd_2012, + NULL +}; +#define pci_ss_list_11c1_ed00 NULL +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1535 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d4_5340 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_12f8_8a02, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + &pci_ss_info_11de_6120_13c2_0000, + &pci_ss_info_11de_6120_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_11e3_0001 NULL +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_000d NULL +#define pci_ss_list_11fe_000e NULL +#define pci_ss_list_11fe_000f NULL +#define pci_ss_list_11fe_0801 NULL +#define pci_ss_list_11fe_0802 NULL +#define pci_ss_list_11fe_0803 NULL +#define pci_ss_list_11fe_0805 NULL +#define pci_ss_list_11fe_080c NULL +#define pci_ss_list_11fe_080d NULL +#define pci_ss_list_11fe_0812 NULL +#define pci_ss_list_11fe_0903 NULL +#define pci_ss_list_11fe_8015 NULL +#define pci_ss_list_11ff_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1014_020c, + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_7110[] = { + &pci_ss_info_1217_7110_103c_088c, + &pci_ss_info_1217_7110_103c_0890, + NULL +}; +#define pci_ss_list_1217_7112 NULL +#define pci_ss_list_1217_7113 NULL +#define pci_ss_list_1217_7114 NULL +#define pci_ss_list_1217_7134 NULL +#define pci_ss_list_1217_71e2 NULL +#define pci_ss_list_1217_7212 NULL +#define pci_ss_list_1217_7213 NULL +static const pciSubsystemInfo *pci_ss_list_1217_7223[] = { + &pci_ss_info_1217_7223_103c_088c, + &pci_ss_info_1217_7223_103c_0890, + NULL +}; +#define pci_ss_list_1217_7233 NULL +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0057, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0003, + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_1227_0006 NULL +#define pci_ss_list_1227_0023 NULL +#define pci_ss_list_122d_1206 NULL +#define pci_ss_list_122d_1400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + &pci_ss_info_123f_8120_11bd_000f, + &pci_ss_info_123f_8120_1809_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#define pci_ss_list_1242_6562 NULL +#define pci_ss_list_1242_656a NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#define pci_ss_list_1244_2700 NULL +#define pci_ss_list_1244_2900 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_1259_a117 NULL +#define pci_ss_list_1259_a120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125b_1400[] = { + &pci_ss_info_125b_1400_1186_1100, + NULL +}; +#endif +#define pci_ss_list_125c_0101 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + &pci_ss_info_125d_1969_153b_111b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_0e11_0098, + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00b1, + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3872[] = { + &pci_ss_info_1260_3872_1468_0202, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1186_3700, + &pci_ss_info_1260_3873_1385_4105, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_16a5_1601, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3886[] = { + &pci_ss_info_1260_3886_17cf_0037, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3890[] = { + &pci_ss_info_1260_3890_10b8_2802, + &pci_ss_info_1260_3890_10b8_2835, + &pci_ss_info_1260_3890_10b8_a835, + &pci_ss_info_1260_3890_1113_4203, + &pci_ss_info_1260_3890_1113_ee03, + &pci_ss_info_1260_3890_1113_ee08, + &pci_ss_info_1260_3890_1186_3202, + &pci_ss_info_1260_3890_1259_c104, + &pci_ss_info_1260_3890_1385_4800, + &pci_ss_info_1260_3890_16a5_1605, + &pci_ss_info_1260_3890_17cf_0014, + &pci_ss_info_1260_3890_17cf_0020, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +static const pciSubsystemInfo *pci_ss_list_1260_ffff[] = { + &pci_ss_info_1260_ffff_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126c_1211 NULL +#define pci_ss_list_126c_126c NULL +#define pci_ss_list_126f_0501 NULL +#define pci_ss_list_126f_0510 NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0730 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#define pci_ss_list_1274_1171 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1274_8001, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4541, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1274_8001, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1278_0710 NULL +#define pci_ss_list_1279_0060 NULL +#define pci_ss_list_1279_0061 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1005_127a, + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283_8211[] = { + &pci_ss_info_1283_8211_1043_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1283_8212[] = { + &pci_ss_info_1283_8212_1283_0001, + NULL +}; +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8872 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#endif +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12a3_8105 NULL +#define pci_ss_list_12ab_0002 NULL +#define pci_ss_list_12ab_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_1014_0104, + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_10a9_8002, + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#define pci_ss_list_12ae_00fa NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c4_0001 NULL +#define pci_ss_list_12c4_0002 NULL +#define pci_ss_list_12c4_0003 NULL +#define pci_ss_list_12c4_0004 NULL +#define pci_ss_list_12c4_0005 NULL +#define pci_ss_list_12c4_0006 NULL +#define pci_ss_list_12c4_0007 NULL +#define pci_ss_list_12c4_0008 NULL +#define pci_ss_list_12c4_0009 NULL +#define pci_ss_list_12c4_000a NULL +#define pci_ss_list_12c4_000b NULL +#define pci_ss_list_12c4_000c NULL +#define pci_ss_list_12c4_000d NULL +#define pci_ss_list_12c4_0100 NULL +#define pci_ss_list_12c4_0201 NULL +#define pci_ss_list_12c4_0202 NULL +#define pci_ss_list_12c4_0300 NULL +#define pci_ss_list_12c4_0301 NULL +#define pci_ss_list_12c4_0302 NULL +#define pci_ss_list_12c4_0310 NULL +#define pci_ss_list_12c4_0311 NULL +#define pci_ss_list_12c4_0312 NULL +#define pci_ss_list_12c4_0320 NULL +#define pci_ss_list_12c4_0321 NULL +#define pci_ss_list_12c4_0322 NULL +#define pci_ss_list_12c4_0330 NULL +#define pci_ss_list_12c4_0331 NULL +#define pci_ss_list_12c4_0332 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12d4_0200 NULL +#define pci_ss_list_12d5_0003 NULL +#define pci_ss_list_12d5_1000 NULL +#define pci_ss_list_12d8_8150 NULL +#define pci_ss_list_12d9_0002 NULL +#define pci_ss_list_12d9_0004 NULL +#define pci_ss_list_12d9_0005 NULL +#define pci_ss_list_12de_0200 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_12fb_0001 NULL +#define pci_ss_list_12fb_00f5 NULL +#define pci_ss_list_12fb_02ad NULL +#define pci_ss_list_12fb_2adc NULL +#define pci_ss_list_12fb_3100 NULL +#define pci_ss_list_12fb_3500 NULL +#define pci_ss_list_12fb_4d4f NULL +#define pci_ss_list_12fb_8120 NULL +#define pci_ss_list_12fb_da62 NULL +#define pci_ss_list_12fb_db62 NULL +#define pci_ss_list_12fb_dc62 NULL +#define pci_ss_list_12fb_dd62 NULL +#define pci_ss_list_12fb_eddc NULL +#define pci_ss_list_12fb_fa01 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#define pci_ss_list_1307_004d NULL +#define pci_ss_list_1307_0052 NULL +#define pci_ss_list_1307_0054 NULL +#define pci_ss_list_1307_005e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#define pci_ss_list_1317_0985 NULL +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1317_2850 NULL +#define pci_ss_list_1317_5120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317_8201[] = { + &pci_ss_info_1317_8201_10b8_2635, + &pci_ss_info_1317_8201_1317_8201, + NULL +}; +#define pci_ss_list_1317_8211 NULL +#define pci_ss_list_1317_9511 NULL +#endif +#define pci_ss_list_1318_0911 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319_0801[] = { + &pci_ss_info_1319_0801_1319_1319, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1319_0802[] = { + &pci_ss_info_1319_0802_1319_1319, + NULL +}; +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#endif +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#define pci_ss_list_131f_2081 NULL +#endif +#define pci_ss_list_1331_0030 NULL +#define pci_ss_list_1331_8200 NULL +#define pci_ss_list_1331_8201 NULL +#define pci_ss_list_1331_8202 NULL +#define pci_ss_list_1331_8210 NULL +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_1332_5425 NULL +#define pci_ss_list_1332_6140 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_2189 NULL +#define pci_ss_list_134d_2486 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7890[] = { + &pci_ss_info_134d_7890_134d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_5101 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1360_0101 NULL +#define pci_ss_list_1360_0102 NULL +#define pci_ss_list_1360_0103 NULL +#define pci_ss_list_1360_0201 NULL +#define pci_ss_list_1360_0202 NULL +#define pci_ss_list_1360_0203 NULL +#define pci_ss_list_1360_0301 NULL +#define pci_ss_list_1360_0302 NULL +#define pci_ss_list_136b_ff01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371_434e[] = { + &pci_ss_info_1371_434e_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1374_0024 NULL +#define pci_ss_list_1374_0025 NULL +#define pci_ss_list_1374_0026 NULL +#define pci_ss_list_1374_0027 NULL +#define pci_ss_list_1374_0029 NULL +#define pci_ss_list_1374_002a NULL +#define pci_ss_list_1374_002b NULL +#define pci_ss_list_1374_002c NULL +#define pci_ss_list_1374_002d NULL +#define pci_ss_list_1374_002e NULL +#define pci_ss_list_1374_002f NULL +#define pci_ss_list_1374_0030 NULL +#define pci_ss_list_1374_0031 NULL +#define pci_ss_list_1374_0032 NULL +#define pci_ss_list_1374_0034 NULL +#define pci_ss_list_1374_0035 NULL +#define pci_ss_list_1374_0036 NULL +#define pci_ss_list_1374_0037 NULL +#define pci_ss_list_1374_0038 NULL +#define pci_ss_list_1374_0039 NULL +#define pci_ss_list_1374_003a NULL +#define pci_ss_list_137a_0001 NULL +#define pci_ss_list_1382_0001 NULL +#define pci_ss_list_1382_2008 NULL +#define pci_ss_list_1382_2088 NULL +#define pci_ss_list_1382_20c8 NULL +#define pci_ss_list_1382_4008 NULL +#define pci_ss_list_1382_4010 NULL +#define pci_ss_list_1382_4048 NULL +#define pci_ss_list_1382_4088 NULL +#define pci_ss_list_1382_4248 NULL +#define pci_ss_list_1382_4424 NULL +#define pci_ss_list_1385_0013 NULL +#define pci_ss_list_1385_311a NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_4105 NULL +#define pci_ss_list_1385_4400 NULL +#define pci_ss_list_1385_4600 NULL +#define pci_ss_list_1385_4601 NULL +#define pci_ss_list_1385_4610 NULL +#define pci_ss_list_1385_4800 NULL +#define pci_ss_list_1385_4900 NULL +#define pci_ss_list_1385_4a00 NULL +#define pci_ss_list_1385_4b00 NULL +#define pci_ss_list_1385_4c00 NULL +#define pci_ss_list_1385_4d00 NULL +#define pci_ss_list_1385_4e00 NULL +#define pci_ss_list_1385_4f00 NULL +#define pci_ss_list_1385_5200 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_6b00 NULL +#define pci_ss_list_1385_6d00 NULL +#define pci_ss_list_1385_f004 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1141 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#define pci_ss_list_1397_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_0675_1704, + &pci_ss_info_1397_2bd0_0675_1708, + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a3_001d NULL +#define pci_ss_list_13a3_0020 NULL +#define pci_ss_list_13a3_0026 NULL +#define pci_ss_list_13a8_0152 NULL +#define pci_ss_list_13a8_0154 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c0_0020 NULL +#define pci_ss_list_13c0_0030 NULL +#define pci_ss_list_13c0_0210 NULL +#define pci_ss_list_13c1_1000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1_1001[] = { + &pci_ss_info_13c1_1001_13c1_1001, + NULL +}; +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13c1_1003 NULL +#endif +#define pci_ss_list_13c6_0520 NULL +#define pci_ss_list_13c6_0620 NULL +#define pci_ss_list_13c6_0820 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d0_2200 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab03 NULL +#define pci_ss_list_13d1_ab06 NULL +#define pci_ss_list_13d1_ab08 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13f0_0200 NULL +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f0_1023 NULL +#define pci_ss_list_13f4_1401 NULL +#define pci_ss_list_13f6_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8035, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + &pci_ss_info_13f6_0111_1681_a000, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1240 NULL +#define pci_ss_list_13fe_1600 NULL +#define pci_ss_list_13fe_1733 NULL +#define pci_ss_list_13fe_1752 NULL +#define pci_ss_list_13fe_1754 NULL +#define pci_ss_list_13fe_1756 NULL +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0110 NULL +#define pci_ss_list_1407_0111 NULL +#define pci_ss_list_1407_0120 NULL +#define pci_ss_list_1407_0121 NULL +#define pci_ss_list_1407_0180 NULL +#define pci_ss_list_1407_0181 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0220 NULL +#define pci_ss_list_1407_0221 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412_1712[] = { + &pci_ss_info_1412_1712_1412_1712, + &pci_ss_info_1412_1712_1412_d630, + &pci_ss_info_1412_1712_1412_d631, + &pci_ss_info_1412_1712_1412_d632, + &pci_ss_info_1412_1712_1412_d633, + &pci_ss_info_1412_1712_1412_d634, + &pci_ss_info_1412_1712_1412_d635, + &pci_ss_info_1412_1712_1412_d637, + &pci_ss_info_1412_1712_1412_d638, + &pci_ss_info_1412_1712_1412_d63b, + &pci_ss_info_1412_1712_1412_d63c, + &pci_ss_info_1412_1712_1416_1712, + &pci_ss_info_1412_1712_153b_1115, + &pci_ss_info_1412_1712_153b_1125, + &pci_ss_info_1412_1712_153b_112b, + &pci_ss_info_1412_1712_153b_112c, + &pci_ss_info_1412_1712_153b_1130, + &pci_ss_info_1412_1712_153b_1138, + &pci_ss_info_1412_1712_153b_1151, + &pci_ss_info_1412_1712_16ce_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1412_1724[] = { + &pci_ss_info_1412_1724_1412_1724, + &pci_ss_info_1412_1724_1412_3630, + &pci_ss_info_1412_1724_1412_3631, + &pci_ss_info_1412_1724_153b_1145, + &pci_ss_info_1412_1724_153b_1147, + &pci_ss_info_1412_1724_153b_1153, + &pci_ss_info_1412_1724_270f_f641, + &pci_ss_info_1412_1724_270f_f645, + NULL +}; +#endif +#define pci_ss_list_1415_8403 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_131f_2050, + &pci_ss_info_1415_9501_131f_2051, + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +#define pci_ss_list_1415_9510 NULL +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9521 NULL +#define pci_ss_list_1415_9523 NULL +#endif +#define pci_ss_list_1420_8002 NULL +#define pci_ss_list_1420_8003 NULL +#define pci_ss_list_1425_000b NULL +#define pci_ss_list_142e_4020 NULL +#define pci_ss_list_142e_4337 NULL +#define pci_ss_list_1432_9130 NULL +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8164 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_1458_0c11 NULL +#define pci_ss_list_1458_e911 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_1461_f436 NULL +#define pci_ss_list_1462_5501 NULL +#define pci_ss_list_1462_6819 NULL +#define pci_ss_list_1462_6825 NULL +#define pci_ss_list_1462_6834 NULL +#define pci_ss_list_1462_8725 NULL +#define pci_ss_list_1462_9000 NULL +#define pci_ss_list_1462_9110 NULL +#define pci_ss_list_1462_9119 NULL +#define pci_ss_list_1462_9591 NULL +#define pci_ss_list_146c_1430 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_1497_1497 NULL +#define pci_ss_list_1498_0330 NULL +#define pci_ss_list_1498_0385 NULL +#define pci_ss_list_1498_21cd NULL +#define pci_ss_list_1498_30c8 NULL +#define pci_ss_list_149d_0001 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14b9_a505 NULL +#define pci_ss_list_14b9_a506 NULL +#define pci_ss_list_14c1_8043 NULL +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14d9_0010 NULL +#define pci_ss_list_14d9_9000 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14db_2182 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#define pci_ss_list_14e4_0800 NULL +#define pci_ss_list_14e4_0804 NULL +#define pci_ss_list_14e4_0805 NULL +#define pci_ss_list_14e4_0806 NULL +#define pci_ss_list_14e4_080b NULL +#define pci_ss_list_14e4_080f NULL +#define pci_ss_list_14e4_0811 NULL +#define pci_ss_list_14e4_0816 NULL +#define pci_ss_list_14e4_1600 NULL +#define pci_ss_list_14e4_1601 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_103c_128a, + &pci_ss_info_14e4_1645_103c_128b, + &pci_ss_info_14e4_1645_103c_12a4, + &pci_ss_info_14e4_1645_103c_12c1, + &pci_ss_info_14e4_1645_103c_1300, + &pci_ss_info_14e4_1645_10a9_8010, + &pci_ss_info_14e4_1645_10a9_8011, + &pci_ss_info_14e4_1645_10a9_8012, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_10a9_8010, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + &pci_ss_info_14e4_1648_1734_100b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164a[] = { + &pci_ss_info_14e4_164a_103c_3101, + NULL +}; +#define pci_ss_list_14e4_164c NULL +#define pci_ss_list_14e4_164d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1653[] = { + &pci_ss_info_14e4_1653_0e11_00e3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1654[] = { + &pci_ss_info_14e4_1654_0e11_00e3, + &pci_ss_info_14e4_1654_103c_3100, + &pci_ss_info_14e4_1654_103c_3226, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1659[] = { + &pci_ss_info_14e4_1659_1014_02c6, + &pci_ss_info_14e4_1659_103c_7031, + &pci_ss_info_14e4_1659_103c_7032, + &pci_ss_info_14e4_1659_1734_1061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165d[] = { + &pci_ss_info_14e4_165d_1028_865d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165e[] = { + &pci_ss_info_14e4_165e_103c_088c, + &pci_ss_info_14e4_165e_103c_0890, + &pci_ss_info_14e4_165e_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1668[] = { + &pci_ss_info_14e4_1668_103c_7039, + NULL +}; +#define pci_ss_list_14e4_166a NULL +#define pci_ss_list_14e4_166b NULL +#define pci_ss_list_14e4_166e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1677[] = { + &pci_ss_info_14e4_1677_1028_0179, + &pci_ss_info_14e4_1677_1028_0182, + &pci_ss_info_14e4_1677_1028_01ad, + &pci_ss_info_14e4_1677_1734_105d, + NULL +}; +#define pci_ss_list_14e4_1678 NULL +#define pci_ss_list_14e4_167d NULL +#define pci_ss_list_14e4_167e NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_103c_12bc, + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_169c[] = { + &pci_ss_info_14e4_169c_103c_308b, + NULL +}; +#define pci_ss_list_14e4_169d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16aa[] = { + &pci_ss_info_14e4_16aa_103c_3102, + NULL +}; +#define pci_ss_list_14e4_16ac NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_0e11_00ca, + &pci_ss_info_14e4_16c7_0e11_00cb, + &pci_ss_info_14e4_16c7_103c_12c3, + &pci_ss_info_14e4_16c7_103c_12ca, + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_16dd NULL +#define pci_ss_list_14e4_16f7 NULL +#define pci_ss_list_14e4_16fd NULL +#define pci_ss_list_14e4_16fe NULL +static const pciSubsystemInfo *pci_ss_list_14e4_170c[] = { + &pci_ss_info_14e4_170c_1028_0188, + &pci_ss_info_14e4_170c_1028_0196, + &pci_ss_info_14e4_170c_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_170d[] = { + &pci_ss_info_14e4_170d_1014_0545, + NULL +}; +#define pci_ss_list_14e4_170e NULL +#define pci_ss_list_14e4_3352 NULL +#define pci_ss_list_14e4_3360 NULL +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4301[] = { + &pci_ss_info_14e4_4301_1028_0407, + &pci_ss_info_14e4_4301_1043_0120, + NULL +}; +#define pci_ss_list_14e4_4305 NULL +#define pci_ss_list_14e4_4306 NULL +#define pci_ss_list_14e4_4307 NULL +#define pci_ss_list_14e4_4310 NULL +#define pci_ss_list_14e4_4312 NULL +#define pci_ss_list_14e4_4313 NULL +#define pci_ss_list_14e4_4315 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4318[] = { + &pci_ss_info_14e4_4318_103c_1356, + &pci_ss_info_14e4_4318_1468_0311, + &pci_ss_info_14e4_4318_1468_0312, + &pci_ss_info_14e4_4318_14e4_0449, + &pci_ss_info_14e4_4318_14e4_4318, + &pci_ss_info_14e4_4318_16ec_0119, + NULL +}; +#define pci_ss_list_14e4_4319 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4320[] = { + &pci_ss_info_14e4_4320_1028_0001, + &pci_ss_info_14e4_4320_1028_0003, + &pci_ss_info_14e4_4320_103c_12f4, + &pci_ss_info_14e4_4320_103c_12fa, + &pci_ss_info_14e4_4320_1043_100f, + &pci_ss_info_14e4_4320_1057_7025, + &pci_ss_info_14e4_4320_106b_004e, + &pci_ss_info_14e4_4320_144f_7050, + &pci_ss_info_14e4_4320_14e4_4320, + &pci_ss_info_14e4_4320_1737_4320, + &pci_ss_info_14e4_4320_1799_7001, + &pci_ss_info_14e4_4320_1799_7010, + &pci_ss_info_14e4_4320_185f_1220, + NULL +}; +#define pci_ss_list_14e4_4321 NULL +#define pci_ss_list_14e4_4322 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4324[] = { + &pci_ss_info_14e4_4324_1028_0001, + &pci_ss_info_14e4_4324_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_4325[] = { + &pci_ss_info_14e4_4325_1414_0003, + &pci_ss_info_14e4_4325_1414_0004, + NULL +}; +#define pci_ss_list_14e4_4326 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4401[] = { + &pci_ss_info_14e4_4401_1043_80a8, + NULL +}; +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4403 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_4430 NULL +#define pci_ss_list_14e4_4432 NULL +#define pci_ss_list_14e4_4610 NULL +#define pci_ss_list_14e4_4611 NULL +#define pci_ss_list_14e4_4612 NULL +#define pci_ss_list_14e4_4613 NULL +#define pci_ss_list_14e4_4614 NULL +#define pci_ss_list_14e4_4615 NULL +#define pci_ss_list_14e4_4704 NULL +#define pci_ss_list_14e4_4705 NULL +#define pci_ss_list_14e4_4706 NULL +#define pci_ss_list_14e4_4707 NULL +#define pci_ss_list_14e4_4708 NULL +#define pci_ss_list_14e4_4710 NULL +#define pci_ss_list_14e4_4711 NULL +#define pci_ss_list_14e4_4712 NULL +#define pci_ss_list_14e4_4713 NULL +#define pci_ss_list_14e4_4714 NULL +#define pci_ss_list_14e4_4715 NULL +#define pci_ss_list_14e4_4716 NULL +#define pci_ss_list_14e4_4717 NULL +#define pci_ss_list_14e4_4718 NULL +#define pci_ss_list_14e4_4719 NULL +#define pci_ss_list_14e4_4720 NULL +#define pci_ss_list_14e4_5365 NULL +#define pci_ss_list_14e4_5600 NULL +#define pci_ss_list_14e4_5605 NULL +#define pci_ss_list_14e4_5615 NULL +#define pci_ss_list_14e4_5625 NULL +#define pci_ss_list_14e4_5645 NULL +#define pci_ss_list_14e4_5670 NULL +#define pci_ss_list_14e4_5680 NULL +#define pci_ss_list_14e4_5690 NULL +#define pci_ss_list_14e4_5691 NULL +#define pci_ss_list_14e4_5692 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#define pci_ss_list_14e4_5822 NULL +#define pci_ss_list_14e4_5823 NULL +#define pci_ss_list_14e4_5824 NULL +#define pci_ss_list_14e4_5840 NULL +#define pci_ss_list_14e4_5841 NULL +#define pci_ss_list_14e4_5850 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14ea_ab07 NULL +#define pci_ss_list_14ea_ab08 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1085 NULL +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +#define pci_ss_list_14f1_1620 NULL +#define pci_ss_list_14f1_1621 NULL +#define pci_ss_list_14f1_1622 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +#define pci_ss_list_14f1_1811 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2045[] = { + &pci_ss_info_14f1_2045_14f1_2045, + NULL +}; +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_2f02 NULL +#define pci_ss_list_14f1_2f11 NULL +#define pci_ss_list_14f1_2f20 NULL +#define pci_ss_list_14f1_8234 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_8800[] = { + &pci_ss_info_14f1_8800_0070_2801, + &pci_ss_info_14f1_8800_0070_3401, + &pci_ss_info_14f1_8800_0070_9001, + &pci_ss_info_14f1_8800_0070_9200, + &pci_ss_info_14f1_8800_0070_9202, + &pci_ss_info_14f1_8800_0070_9402, + &pci_ss_info_14f1_8800_0070_9802, + &pci_ss_info_14f1_8800_1002_00f8, + &pci_ss_info_14f1_8800_1002_a101, + &pci_ss_info_14f1_8800_1043_4823, + &pci_ss_info_14f1_8800_107d_6613, + &pci_ss_info_14f1_8800_107d_6620, + &pci_ss_info_14f1_8800_107d_663c, + &pci_ss_info_14f1_8800_107d_665f, + &pci_ss_info_14f1_8800_10fc_d003, + &pci_ss_info_14f1_8800_10fc_d035, + &pci_ss_info_14f1_8800_1421_0334, + &pci_ss_info_14f1_8800_1461_000a, + &pci_ss_info_14f1_8800_1461_000b, + &pci_ss_info_14f1_8800_1461_8011, + &pci_ss_info_14f1_8800_1462_8606, + &pci_ss_info_14f1_8800_14c7_0107, + &pci_ss_info_14f1_8800_14f1_0187, + &pci_ss_info_14f1_8800_14f1_0342, + &pci_ss_info_14f1_8800_153b_1166, + &pci_ss_info_14f1_8800_1540_2580, + &pci_ss_info_14f1_8800_1554_4811, + &pci_ss_info_14f1_8800_1554_4813, + &pci_ss_info_14f1_8800_17de_08a1, + &pci_ss_info_14f1_8800_17de_08a6, + &pci_ss_info_14f1_8800_17de_08b2, + &pci_ss_info_14f1_8800_17de_a8a6, + &pci_ss_info_14f1_8800_1822_0025, + &pci_ss_info_14f1_8800_18ac_d500, + &pci_ss_info_14f1_8800_18ac_d810, + &pci_ss_info_14f1_8800_18ac_d820, + &pci_ss_info_14f1_8800_18ac_db00, + &pci_ss_info_14f1_8800_18ac_db11, + &pci_ss_info_14f1_8800_18ac_db50, + &pci_ss_info_14f1_8800_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8801[] = { + &pci_ss_info_14f1_8801_0070_2801, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8802[] = { + &pci_ss_info_14f1_8802_0070_2801, + &pci_ss_info_14f1_8802_0070_9002, + &pci_ss_info_14f1_8802_1043_4823, + &pci_ss_info_14f1_8802_107d_663c, + &pci_ss_info_14f1_8802_14f1_0187, + &pci_ss_info_14f1_8802_17de_08a1, + &pci_ss_info_14f1_8802_17de_08a6, + &pci_ss_info_14f1_8802_18ac_d500, + &pci_ss_info_14f1_8802_18ac_d810, + &pci_ss_info_14f1_8802_18ac_d820, + &pci_ss_info_14f1_8802_18ac_db00, + &pci_ss_info_14f1_8802_18ac_db10, + &pci_ss_info_14f1_8802_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8804[] = { + &pci_ss_info_14f1_8804_0070_9002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8811[] = { + &pci_ss_info_14f1_8811_0070_3401, + &pci_ss_info_14f1_8811_1462_8606, + &pci_ss_info_14f1_8811_18ac_d500, + &pci_ss_info_14f1_8811_18ac_d810, + &pci_ss_info_14f1_8811_18ac_d820, + &pci_ss_info_14f1_8811_18ac_db00, + NULL +}; +#endif +#define pci_ss_list_14f2_0120 NULL +#define pci_ss_list_14f2_0121 NULL +#define pci_ss_list_14f2_0122 NULL +#define pci_ss_list_14f2_0123 NULL +#define pci_ss_list_14f2_0124 NULL +#define pci_ss_list_14f3_2030 NULL +#define pci_ss_list_14f3_2050 NULL +#define pci_ss_list_14f3_2060 NULL +#define pci_ss_list_14f8_2077 NULL +#define pci_ss_list_14fc_0000 NULL +#define pci_ss_list_14fc_0001 NULL +#define pci_ss_list_1500_1360 NULL +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#define pci_ss_list_1516_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#define pci_ss_list_1516_0891 NULL +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151c_0003 NULL +#define pci_ss_list_151c_4000 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + &pci_ss_info_1522_0100_1522_0c00, + &pci_ss_info_1522_0100_1522_0d00, + &pci_ss_info_1522_0100_1522_1d00, + &pci_ss_info_1522_0100_1522_2000, + &pci_ss_info_1522_0100_1522_2100, + &pci_ss_info_1522_0100_1522_2200, + &pci_ss_info_1522_0100_1522_2300, + &pci_ss_info_1522_0100_1522_2400, + &pci_ss_info_1522_0100_1522_2500, + &pci_ss_info_1522_0100_1522_2600, + &pci_ss_info_1522_0100_1522_2700, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1524_0510[] = { + &pci_ss_info_1524_0510_103c_006a, + NULL +}; +#define pci_ss_list_1524_0520 NULL +#define pci_ss_list_1524_0530 NULL +#define pci_ss_list_1524_0550 NULL +#define pci_ss_list_1524_0610 NULL +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +static const pciSubsystemInfo *pci_ss_list_1524_1410[] = { + &pci_ss_info_1524_1410_1025_005a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1524_1411[] = { + &pci_ss_info_1524_1411_103c_006a, + NULL +}; +#define pci_ss_list_1524_1412 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1524_1421 NULL +#define pci_ss_list_1524_1422 NULL +#endif +#define pci_ss_list_1532_0020 NULL +#define pci_ss_list_1538_0303 NULL +#define pci_ss_list_153b_1144 NULL +#define pci_ss_list_153b_1147 NULL +#define pci_ss_list_153b_1158 NULL +#define pci_ss_list_153f_0001 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_1578_5615 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0405 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15ad_0720 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15b3_5a44 NULL +#define pci_ss_list_15b3_5a45 NULL +#define pci_ss_list_15b3_5a46 NULL +#define pci_ss_list_15b3_5e8d NULL +#define pci_ss_list_15b3_6274 NULL +#define pci_ss_list_15b3_6278 NULL +#define pci_ss_list_15b3_6279 NULL +#define pci_ss_list_15b3_6282 NULL +#define pci_ss_list_15bc_1100 NULL +#define pci_ss_list_15bc_2922 NULL +#define pci_ss_list_15bc_2928 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c5_8010 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_15e9_1841 NULL +#define pci_ss_list_15ec_3101 NULL +#define pci_ss_list_15ec_5102 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1619_0610 NULL +#define pci_ss_list_1619_0620 NULL +#define pci_ss_list_1619_0640 NULL +#define pci_ss_list_1619_1610 NULL +#define pci_ss_list_1619_2610 NULL +#define pci_ss_list_1626_8410 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1637_3874 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_3052 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_165f_1020 NULL +#define pci_ss_list_1668_0100 NULL +#define pci_ss_list_166d_0001 NULL +#define pci_ss_list_166d_0002 NULL +#define pci_ss_list_1677_104e NULL +#define pci_ss_list_1677_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_167b_2102[] = { + &pci_ss_info_167b_2102_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1681_0010 NULL +#define pci_ss_list_1688_1170 NULL +#define pci_ss_list_168c_0007 NULL +#define pci_ss_list_168c_0011 NULL +#define pci_ss_list_168c_0012 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c_0013[] = { + &pci_ss_info_168c_0013_1113_d301, + &pci_ss_info_168c_0013_1186_3202, + &pci_ss_info_168c_0013_1186_3203, + &pci_ss_info_168c_0013_1186_3a12, + &pci_ss_info_168c_0013_1186_3a13, + &pci_ss_info_168c_0013_1186_3a14, + &pci_ss_info_168c_0013_1186_3a17, + &pci_ss_info_168c_0013_1186_3a18, + &pci_ss_info_168c_0013_1186_3a63, + &pci_ss_info_168c_0013_1186_3a94, + &pci_ss_info_168c_0013_1385_4d00, + &pci_ss_info_168c_0013_1458_e911, + &pci_ss_info_168c_0013_14b7_0a60, + &pci_ss_info_168c_0013_168c_0013, + &pci_ss_info_168c_0013_168c_1025, + &pci_ss_info_168c_0013_168c_1027, + &pci_ss_info_168c_0013_168c_2026, + &pci_ss_info_168c_0013_168c_2041, + &pci_ss_info_168c_0013_168c_2042, + &pci_ss_info_168c_0013_16ab_7302, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001a[] = { + &pci_ss_info_168c_001a_1186_3a15, + &pci_ss_info_168c_001a_1186_3a16, + &pci_ss_info_168c_001a_1186_3a23, + &pci_ss_info_168c_001a_1186_3a24, + &pci_ss_info_168c_001a_168c_1052, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001b[] = { + &pci_ss_info_168c_001b_1186_3a19, + &pci_ss_info_168c_001b_1186_3a22, + NULL +}; +#define pci_ss_list_168c_0020 NULL +#define pci_ss_list_168c_1014 NULL +#endif +#define pci_ss_list_169c_0044 NULL +#define pci_ss_list_16ab_1100 NULL +#define pci_ss_list_16ab_1101 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ab_8501 NULL +#define pci_ss_list_16ae_1141 NULL +#define pci_ss_list_16ca_0001 NULL +#define pci_ss_list_16e3_1e0f NULL +#define pci_ss_list_16ec_00ff NULL +#define pci_ss_list_16ec_0116 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_16ed_1001 NULL +#define pci_ss_list_16f4_8000 NULL +#define pci_ss_list_170b_0100 NULL +#define pci_ss_list_1725_7174 NULL +#define pci_ss_list_172a_13c8 NULL +#define pci_ss_list_1737_0013 NULL +#define pci_ss_list_1737_0015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737_1032[] = { + &pci_ss_info_1737_1032_1737_0015, + &pci_ss_info_1737_1032_1737_0024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1737_1064[] = { + &pci_ss_info_1737_1064_1737_0016, + NULL +}; +#define pci_ss_list_1737_ab08 NULL +#define pci_ss_list_1737_ab09 NULL +#endif +#define pci_ss_list_173b_03e8 NULL +#define pci_ss_list_173b_03e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#define pci_ss_list_173b_03eb NULL +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_1799_6001 NULL +#define pci_ss_list_1799_6020 NULL +#define pci_ss_list_1799_6060 NULL +#define pci_ss_list_1799_7000 NULL +#define pci_ss_list_1799_7010 NULL +#define pci_ss_list_179c_0557 NULL +#define pci_ss_list_179c_0566 NULL +#define pci_ss_list_179c_5031 NULL +#define pci_ss_list_179c_5121 NULL +#define pci_ss_list_179c_5211 NULL +#define pci_ss_list_179c_5679 NULL +#define pci_ss_list_17a0_8033 NULL +#define pci_ss_list_17a0_8034 NULL +#define pci_ss_list_17b3_ab08 NULL +#define pci_ss_list_17b4_0011 NULL +#define pci_ss_list_17cc_2280 NULL +#define pci_ss_list_17d3_1110 NULL +#define pci_ss_list_17d3_1120 NULL +#define pci_ss_list_17d3_1130 NULL +#define pci_ss_list_17d3_1160 NULL +#define pci_ss_list_17d3_1210 NULL +#define pci_ss_list_17d3_1220 NULL +#define pci_ss_list_17d3_1230 NULL +#define pci_ss_list_17d3_1260 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17d5_5831[] = { + &pci_ss_info_17d5_5831_103c_12d5, + NULL +}; +#define pci_ss_list_17d5_5832 NULL +#endif +#define pci_ss_list_17fe_2120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe_2220[] = { + &pci_ss_info_17fe_2220_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1814_0101[] = { + &pci_ss_info_1814_0101_1043_0127, + &pci_ss_info_1814_0101_1462_6828, + NULL +}; +#define pci_ss_list_1814_0200 NULL +static const pciSubsystemInfo *pci_ss_list_1814_0201[] = { + &pci_ss_info_1814_0201_1043_130f, + &pci_ss_info_1814_0201_1371_001e, + &pci_ss_info_1814_0201_1371_001f, + &pci_ss_info_1814_0201_1371_0020, + &pci_ss_info_1814_0201_1458_e381, + &pci_ss_info_1814_0201_1458_e931, + &pci_ss_info_1814_0201_1462_6835, + &pci_ss_info_1814_0201_1737_0032, + &pci_ss_info_1814_0201_1799_700a, + &pci_ss_info_1814_0201_1799_701a, + &pci_ss_info_1814_0201_185f_22a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0301[] = { + &pci_ss_info_1814_0301_2561_1814, + NULL +}; +#define pci_ss_list_1814_0401 NULL +#endif +#define pci_ss_list_1822_4e35 NULL +#define pci_ss_list_182d_3069 NULL +#define pci_ss_list_182d_9790 NULL +#define pci_ss_list_183b_08a7 NULL +#define pci_ss_list_183b_08a8 NULL +#define pci_ss_list_183b_08a9 NULL +#define pci_ss_list_1864_2110 NULL +#define pci_ss_list_1867_5a44 NULL +#define pci_ss_list_1867_5a45 NULL +#define pci_ss_list_1867_5a46 NULL +#define pci_ss_list_1867_6278 NULL +#define pci_ss_list_1867_6282 NULL +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_18ac_d500 NULL +#define pci_ss_list_18ac_d810 NULL +#define pci_ss_list_18ac_d820 NULL +#define pci_ss_list_18b8_b001 NULL +#define pci_ss_list_18ca_0020 NULL +#define pci_ss_list_18ca_0040 NULL +#define pci_ss_list_18d2_3069 NULL +#define pci_ss_list_18dd_4c6f NULL +#define pci_ss_list_18e6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec_c006[] = { + &pci_ss_info_18ec_c006_18ec_d001, + &pci_ss_info_18ec_c006_18ec_d002, + &pci_ss_info_18ec_c006_18ec_d003, + &pci_ss_info_18ec_c006_18ec_d004, + NULL +}; +#define pci_ss_list_18ec_c045 NULL +#define pci_ss_list_18ec_c050 NULL +static const pciSubsystemInfo *pci_ss_list_18ec_c058[] = { + &pci_ss_info_18ec_c058_18ec_d001, + &pci_ss_info_18ec_c058_18ec_d002, + &pci_ss_info_18ec_c058_18ec_d003, + &pci_ss_info_18ec_c058_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7_0001 NULL +#define pci_ss_list_18f7_0002 NULL +#define pci_ss_list_18f7_0004 NULL +#define pci_ss_list_18f7_0005 NULL +#define pci_ss_list_18f7_000a NULL +#define pci_ss_list_1923_0100 NULL +#define pci_ss_list_1942_e511 NULL +#define pci_ss_list_1957_0080 NULL +#define pci_ss_list_1957_0081 NULL +#define pci_ss_list_1957_0082 NULL +#define pci_ss_list_1957_0083 NULL +#define pci_ss_list_1957_0084 NULL +#define pci_ss_list_1957_0085 NULL +#define pci_ss_list_1957_0086 NULL +#define pci_ss_list_1957_0087 NULL +#define pci_ss_list_1966_1975 NULL +#define pci_ss_list_196a_0101 NULL +#define pci_ss_list_196a_0102 NULL +#define pci_ss_list_197b_2360 NULL +#define pci_ss_list_197b_2363 NULL +#define pci_ss_list_1989_0001 NULL +#define pci_ss_list_1989_8001 NULL +#define pci_ss_list_19ae_0520 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_1fc0_0300 NULL +#define pci_ss_list_1fc1_000d NULL +#define pci_ss_list_1fce_0001 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_0021[] = { + &pci_ss_info_3388_0021_4c53_1050, + &pci_ss_info_3388_0021_4c53_1080, + &pci_ss_info_3388_0021_4c53_1090, + &pci_ss_info_3388_0021_4c53_10a0, + &pci_ss_info_3388_0021_4c53_3010, + &pci_ss_info_3388_0021_4c53_3011, + &pci_ss_info_3388_0021_4c53_4000, + NULL +}; +#define pci_ss_list_3388_0022 NULL +#define pci_ss_list_3388_0026 NULL +#define pci_ss_list_3388_101a NULL +#define pci_ss_list_3388_101b NULL +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3842_c370 NULL +#define pci_ss_list_3d3d_0001 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0002[] = { + &pci_ss_info_3d3d_0002_0000_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0003[] = { + &pci_ss_info_3d3d_0003_0000_0000, + NULL +}; +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0006[] = { + &pci_ss_info_3d3d_0006_0000_0000, + &pci_ss_info_3d3d_0006_1048_0a42, + NULL +}; +#define pci_ss_list_3d3d_0007 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0008[] = { + &pci_ss_info_3d3d_0008_1048_0a42, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_1048_0a42, + &pci_ss_info_3d3d_0009_13e9_1000, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_000d NULL +#define pci_ss_list_3d3d_0011 NULL +#define pci_ss_list_3d3d_0012 NULL +#define pci_ss_list_3d3d_0013 NULL +#define pci_ss_list_3d3d_0020 NULL +#define pci_ss_list_3d3d_0022 NULL +#define pci_ss_list_3d3d_0024 NULL +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_07a1 NULL +#define pci_ss_list_3d3d_07a2 NULL +#define pci_ss_list_3d3d_07a3 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_4144_0044 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4444_0016[] = { + &pci_ss_info_4444_0016_0070_0003, + &pci_ss_info_4444_0016_0070_0009, + &pci_ss_info_4444_0016_0070_0801, + &pci_ss_info_4444_0016_0070_0807, + &pci_ss_info_4444_0016_0070_4001, + &pci_ss_info_4444_0016_0070_4009, + &pci_ss_info_4444_0016_0070_4801, + &pci_ss_info_4444_0016_0070_4803, + &pci_ss_info_4444_0016_0070_8003, + &pci_ss_info_4444_0016_0070_8801, + &pci_ss_info_4444_0016_0070_c801, + &pci_ss_info_4444_0016_0070_e807, + &pci_ss_info_4444_0016_0070_e817, + &pci_ss_info_4444_0016_0270_0801, + &pci_ss_info_4444_0016_12ab_fff3, + &pci_ss_info_4444_0016_12ab_ffff, + &pci_ss_info_4444_0016_4070_8801, + &pci_ss_info_4444_0016_9005_0092, + &pci_ss_info_4444_0016_9005_0093, + &pci_ss_info_4444_0016_ff92_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4444_0803[] = { + &pci_ss_info_4444_0803_0070_4000, + &pci_ss_info_4444_0803_0070_4001, + &pci_ss_info_4444_0803_0070_4800, + &pci_ss_info_4444_0803_12ab_0000, + &pci_ss_info_4444_0803_1461_a3ce, + &pci_ss_info_4444_0803_1461_a3cf, + NULL +}; +#endif +#define pci_ss_list_4916_1960 NULL +#define pci_ss_list_494f_10e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53_0000[] = { + &pci_ss_info_4c53_0000_4c53_3000, + &pci_ss_info_4c53_0000_4c53_3001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4c53_0001[] = { + &pci_ss_info_4c53_0001_4c53_3002, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5168_0301 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_1033_8110, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + &pci_ss_info_5333_8c12_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_544c_0350 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_5654_3132 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_6666_0004 NULL +#define pci_ss_list_6666_0101 NULL +#define pci_ss_list_7063_2000 NULL +#define pci_ss_list_7063_3000 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0309 NULL +#define pci_ss_list_8086_030d NULL +#define pci_ss_list_8086_0326 NULL +#define pci_ss_list_8086_0327 NULL +#define pci_ss_list_8086_0329 NULL +#define pci_ss_list_8086_032a NULL +#define pci_ss_list_8086_032c NULL +#define pci_ss_list_8086_0330 NULL +#define pci_ss_list_8086_0331 NULL +#define pci_ss_list_8086_0332 NULL +#define pci_ss_list_8086_0333 NULL +#define pci_ss_list_8086_0334 NULL +#define pci_ss_list_8086_0335 NULL +#define pci_ss_list_8086_0336 NULL +#define pci_ss_list_8086_0340 NULL +#define pci_ss_list_8086_0341 NULL +#define pci_ss_list_8086_0370 NULL +#define pci_ss_list_8086_0371 NULL +#define pci_ss_list_8086_0372 NULL +#define pci_ss_list_8086_0373 NULL +#define pci_ss_list_8086_0374 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0500 NULL +#define pci_ss_list_8086_0501 NULL +#define pci_ss_list_8086_0502 NULL +#define pci_ss_list_8086_0503 NULL +#define pci_ss_list_8086_0510 NULL +#define pci_ss_list_8086_0511 NULL +#define pci_ss_list_8086_0512 NULL +#define pci_ss_list_8086_0513 NULL +#define pci_ss_list_8086_0514 NULL +#define pci_ss_list_8086_0515 NULL +#define pci_ss_list_8086_0516 NULL +#define pci_ss_list_8086_0530 NULL +#define pci_ss_list_8086_0531 NULL +#define pci_ss_list_8086_0532 NULL +#define pci_ss_list_8086_0533 NULL +#define pci_ss_list_8086_0534 NULL +#define pci_ss_list_8086_0535 NULL +#define pci_ss_list_8086_0536 NULL +#define pci_ss_list_8086_0537 NULL +static const pciSubsystemInfo *pci_ss_list_8086_0600[] = { + &pci_ss_info_8086_0600_8086_01af, + &pci_ss_info_8086_0600_8086_01c1, + &pci_ss_info_8086_0600_8086_01f7, + NULL +}; +#define pci_ss_list_8086_061f NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1002, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_1014_0269, + &pci_ss_info_8086_1008_1028_011c, + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + &pci_ss_info_8086_1008_8086_3108, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_1014_0268, + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +#define pci_ss_list_8086_100a NULL +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100d[] = { + &pci_ss_info_8086_100d_1028_0123, + &pci_ss_info_8086_100d_1079_891f, + &pci_ss_info_8086_100d_4c53_1080, + &pci_ss_info_8086_100d_8086_110d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_1014_0265, + &pci_ss_info_8086_100e_1014_0267, + &pci_ss_info_8086_100e_1014_026a, + &pci_ss_info_8086_100e_1024_0134, + &pci_ss_info_8086_100e_1028_002e, + &pci_ss_info_8086_100e_1028_0151, + &pci_ss_info_8086_100e_107b_8920, + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + &pci_ss_info_8086_100e_8086_1376, + &pci_ss_info_8086_100e_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_1014_0269, + &pci_ss_info_8086_100f_1014_028e, + &pci_ss_info_8086_100f_8086_1000, + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_0e11_00db, + &pci_ss_info_8086_1010_1014_027c, + &pci_ss_info_8086_1010_18fb_7872, + &pci_ss_info_8086_1010_1fc1_0026, + &pci_ss_info_8086_1010_4c53_1080, + &pci_ss_info_8086_1010_4c53_10a0, + &pci_ss_info_8086_1010_8086_1011, + &pci_ss_info_8086_1010_8086_1012, + &pci_ss_info_8086_1010_8086_101a, + &pci_ss_info_8086_1010_8086_3424, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_1014_0268, + &pci_ss_info_8086_1011_8086_1002, + &pci_ss_info_8086_1011_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_0e11_00dc, + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1013[] = { + &pci_ss_info_8086_1013_8086_0013, + &pci_ss_info_8086_1013_8086_1013, + &pci_ss_info_8086_1013_8086_1113, + NULL +}; +#define pci_ss_list_8086_1014 NULL +#define pci_ss_list_8086_1015 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1016[] = { + &pci_ss_info_8086_1016_1014_052c, + &pci_ss_info_8086_1016_1179_0001, + &pci_ss_info_8086_1016_8086_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1017[] = { + &pci_ss_info_8086_1017_8086_1017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1018[] = { + &pci_ss_info_8086_1018_8086_1018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1019[] = { + &pci_ss_info_8086_1019_1458_1019, + &pci_ss_info_8086_1019_1458_e000, + &pci_ss_info_8086_1019_8086_1019, + &pci_ss_info_8086_1019_8086_301f, + &pci_ss_info_8086_1019_8086_3427, + NULL +}; +#define pci_ss_list_8086_101a NULL +static const pciSubsystemInfo *pci_ss_list_8086_101d[] = { + &pci_ss_info_8086_101d_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101e[] = { + &pci_ss_info_8086_101e_1014_0549, + &pci_ss_info_8086_101e_1179_0001, + &pci_ss_info_8086_101e_8086_101e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1026[] = { + &pci_ss_info_8086_1026_1028_0169, + &pci_ss_info_8086_1026_8086_1000, + &pci_ss_info_8086_1026_8086_1001, + &pci_ss_info_8086_1026_8086_1002, + &pci_ss_info_8086_1026_8086_1026, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1027[] = { + &pci_ss_info_8086_1027_103c_3103, + &pci_ss_info_8086_1027_8086_1001, + &pci_ss_info_8086_1027_8086_1002, + &pci_ss_info_8086_1027_8086_1003, + &pci_ss_info_8086_1027_8086_1027, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1028[] = { + &pci_ss_info_8086_1028_8086_1028, + NULL +}; +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + &pci_ss_info_8086_1031_813c_104d, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1038[] = { + &pci_ss_info_8086_1038_0e11_0098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1039[] = { + &pci_ss_info_8086_1039_1014_0267, + NULL +}; +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +#define pci_ss_list_8086_103d NULL +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1043[] = { + &pci_ss_info_8086_1043_8086_2527, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1048[] = { + &pci_ss_info_8086_1048_8086_a01f, + &pci_ss_info_8086_1048_8086_a11f, + NULL +}; +#define pci_ss_list_8086_104b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1050[] = { + &pci_ss_info_8086_1050_1462_728c, + &pci_ss_info_8086_1050_1462_758c, + &pci_ss_info_8086_1050_8086_3020, + &pci_ss_info_8086_1050_8086_302f, + &pci_ss_info_8086_1050_8086_3427, + NULL +}; +#define pci_ss_list_8086_1051 NULL +#define pci_ss_list_8086_1052 NULL +#define pci_ss_list_8086_1053 NULL +#define pci_ss_list_8086_1059 NULL +#define pci_ss_list_8086_105e NULL +#define pci_ss_list_8086_105f NULL +#define pci_ss_list_8086_1060 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1064[] = { + &pci_ss_info_8086_1064_1043_80f8, + NULL +}; +#define pci_ss_list_8086_1065 NULL +#define pci_ss_list_8086_1066 NULL +#define pci_ss_list_8086_1067 NULL +#define pci_ss_list_8086_1068 NULL +#define pci_ss_list_8086_1069 NULL +#define pci_ss_list_8086_106a NULL +#define pci_ss_list_8086_106b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1075[] = { + &pci_ss_info_8086_1075_1028_0165, + &pci_ss_info_8086_1075_8086_0075, + &pci_ss_info_8086_1075_8086_1075, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1076[] = { + &pci_ss_info_8086_1076_1028_0165, + &pci_ss_info_8086_1076_1028_019a, + &pci_ss_info_8086_1076_8086_0076, + &pci_ss_info_8086_1076_8086_1076, + &pci_ss_info_8086_1076_8086_1176, + &pci_ss_info_8086_1076_8086_1276, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1077[] = { + &pci_ss_info_8086_1077_1179_0001, + &pci_ss_info_8086_1077_8086_0077, + &pci_ss_info_8086_1077_8086_1077, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1078[] = { + &pci_ss_info_8086_1078_8086_1078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1079[] = { + &pci_ss_info_8086_1079_103c_12a6, + &pci_ss_info_8086_1079_103c_12cf, + &pci_ss_info_8086_1079_1fc1_0027, + &pci_ss_info_8086_1079_4c53_1090, + &pci_ss_info_8086_1079_4c53_10b0, + &pci_ss_info_8086_1079_8086_0079, + &pci_ss_info_8086_1079_8086_1079, + &pci_ss_info_8086_1079_8086_1179, + &pci_ss_info_8086_1079_8086_117a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107a[] = { + &pci_ss_info_8086_107a_103c_12a8, + &pci_ss_info_8086_107a_8086_107a, + &pci_ss_info_8086_107a_8086_127a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107b[] = { + &pci_ss_info_8086_107b_8086_007b, + &pci_ss_info_8086_107b_8086_107b, + NULL +}; +#define pci_ss_list_8086_107c NULL +#define pci_ss_list_8086_107d NULL +#define pci_ss_list_8086_107e NULL +#define pci_ss_list_8086_107f NULL +#define pci_ss_list_8086_1080 NULL +#define pci_ss_list_8086_1081 NULL +#define pci_ss_list_8086_1082 NULL +#define pci_ss_list_8086_1083 NULL +#define pci_ss_list_8086_1084 NULL +#define pci_ss_list_8086_1085 NULL +#define pci_ss_list_8086_1086 NULL +#define pci_ss_list_8086_1087 NULL +#define pci_ss_list_8086_1089 NULL +#define pci_ss_list_8086_108a NULL +#define pci_ss_list_8086_108b NULL +#define pci_ss_list_8086_108c NULL +#define pci_ss_list_8086_1096 NULL +#define pci_ss_list_8086_1097 NULL +#define pci_ss_list_8086_1098 NULL +#define pci_ss_list_8086_1099 NULL +#define pci_ss_list_8086_109a NULL +#define pci_ss_list_8086_1107 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + &pci_ss_info_8086_1130_8086_4532, + &pci_ss_info_8086_1130_8086_4557, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + &pci_ss_info_8086_1132_8086_4532, + &pci_ss_info_8086_1132_8086_4541, + &pci_ss_info_8086_1132_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1209[] = { + &pci_ss_info_8086_1209_4c53_1050, + &pci_ss_info_8086_1209_4c53_1051, + &pci_ss_info_8086_1209_4c53_1070, + NULL +}; +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1028_00ce, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_108e_10cf, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_110a_008b, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_13e9_1000, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_4c53_1080, + &pci_ss_info_8086_1229_4c53_10e0, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + &pci_ss_info_8086_1229_8086_3411, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123e NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + &pci_ss_info_8086_1461_4c53_1090, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + &pci_ss_info_8086_1960_e4bf_1010, + &pci_ss_info_8086_1960_e4bf_1020, + &pci_ss_info_8086_1960_e4bf_1040, + &pci_ss_info_8086_1960_e4bf_3100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1a30[] = { + &pci_ss_info_8086_1a30_1028_010e, + NULL +}; +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_1a38 NULL +#define pci_ss_list_8086_1a48 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_110a_0051, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + &pci_ss_info_8086_2415_1734_1025, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_1028_010e, + &pci_ss_info_8086_2442_1043_8027, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + &pci_ss_info_8086_2442_8086_4532, + &pci_ss_info_8086_2442_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1028_010e, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + &pci_ss_info_8086_2443_8086_4532, + &pci_ss_info_8086_2443_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_1028_010e, + &pci_ss_info_8086_2444_1043_8027, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + &pci_ss_info_8086_2444_8086_4532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + &pci_ss_info_8086_2445_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2448[] = { + &pci_ss_info_8086_2448_103c_099c, + &pci_ss_info_8086_2448_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_1014_0265, + &pci_ss_info_8086_2449_1014_0267, + &pci_ss_info_8086_2449_1014_026a, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1179_ff01, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1028_010e, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + &pci_ss_info_8086_244b_8086_4532, + &pci_ss_info_8086_244b_8086_4557, + NULL +}; +#define pci_ss_list_8086_244c NULL +static const pciSubsystemInfo *pci_ss_list_8086_244e[] = { + &pci_ss_info_8086_244e_1014_0267, + NULL +}; +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_0e11_0030, + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + &pci_ss_info_8086_2482_8086_3424, + &pci_ss_info_8086_2482_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_0e11_0030, + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1013_5959, + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_101f_1025, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_1179_0001, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_0e11_0030, + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_0e11_0030, + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + &pci_ss_info_8086_248a_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1014_0267, + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1014_0267, + &pci_ss_info_8086_24c2_1025_005a, + &pci_ss_info_8086_24c2_1028_0126, + &pci_ss_info_8086_24c2_1028_0163, + &pci_ss_info_8086_24c2_1028_0196, + &pci_ss_info_8086_24c2_103c_088c, + &pci_ss_info_8086_24c2_103c_0890, + &pci_ss_info_8086_24c2_1071_8160, + &pci_ss_info_8086_24c2_1462_5800, + &pci_ss_info_8086_24c2_1509_2990, + &pci_ss_info_8086_24c2_1734_1055, + &pci_ss_info_8086_24c2_4c53_1090, + &pci_ss_info_8086_24c2_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1014_0267, + &pci_ss_info_8086_24c3_1025_005a, + &pci_ss_info_8086_24c3_1028_0126, + &pci_ss_info_8086_24c3_103c_088c, + &pci_ss_info_8086_24c3_103c_0890, + &pci_ss_info_8086_24c3_1071_8160, + &pci_ss_info_8086_24c3_1458_24c2, + &pci_ss_info_8086_24c3_1462_5800, + &pci_ss_info_8086_24c3_1734_1055, + &pci_ss_info_8086_24c3_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1014_0267, + &pci_ss_info_8086_24c4_1025_005a, + &pci_ss_info_8086_24c4_1028_0126, + &pci_ss_info_8086_24c4_1028_0163, + &pci_ss_info_8086_24c4_1028_0196, + &pci_ss_info_8086_24c4_103c_088c, + &pci_ss_info_8086_24c4_103c_0890, + &pci_ss_info_8086_24c4_1071_8160, + &pci_ss_info_8086_24c4_1462_5800, + &pci_ss_info_8086_24c4_1509_2990, + &pci_ss_info_8086_24c4_4c53_1090, + &pci_ss_info_8086_24c4_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_0e11_00b8, + &pci_ss_info_8086_24c5_1014_0267, + &pci_ss_info_8086_24c5_1025_005a, + &pci_ss_info_8086_24c5_1028_0139, + &pci_ss_info_8086_24c5_1028_0163, + &pci_ss_info_8086_24c5_1028_0196, + &pci_ss_info_8086_24c5_103c_088c, + &pci_ss_info_8086_24c5_103c_0890, + &pci_ss_info_8086_24c5_1071_8160, + &pci_ss_info_8086_24c5_1458_a002, + &pci_ss_info_8086_24c5_1462_5800, + &pci_ss_info_8086_24c5_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c6[] = { + &pci_ss_info_8086_24c6_1025_005a, + &pci_ss_info_8086_24c6_1028_0196, + &pci_ss_info_8086_24c6_103c_088c, + &pci_ss_info_8086_24c6_103c_0890, + &pci_ss_info_8086_24c6_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1014_0267, + &pci_ss_info_8086_24c7_1025_005a, + &pci_ss_info_8086_24c7_1028_0126, + &pci_ss_info_8086_24c7_1028_0163, + &pci_ss_info_8086_24c7_1028_0196, + &pci_ss_info_8086_24c7_103c_088c, + &pci_ss_info_8086_24c7_103c_0890, + &pci_ss_info_8086_24c7_1071_8160, + &pci_ss_info_8086_24c7_1462_5800, + &pci_ss_info_8086_24c7_1509_2990, + &pci_ss_info_8086_24c7_4c53_1090, + &pci_ss_info_8086_24c7_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24ca[] = { + &pci_ss_info_8086_24ca_1025_005a, + &pci_ss_info_8086_24ca_1028_0163, + &pci_ss_info_8086_24ca_1028_0196, + &pci_ss_info_8086_24ca_103c_088c, + &pci_ss_info_8086_24ca_103c_0890, + &pci_ss_info_8086_24ca_1071_8160, + &pci_ss_info_8086_24ca_1734_1055, + &pci_ss_info_8086_24ca_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1014_0267, + &pci_ss_info_8086_24cb_1028_0126, + &pci_ss_info_8086_24cb_1458_24c2, + &pci_ss_info_8086_24cb_1462_5800, + &pci_ss_info_8086_24cb_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cc[] = { + &pci_ss_info_8086_24cc_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1014_0267, + &pci_ss_info_8086_24cd_1025_005a, + &pci_ss_info_8086_24cd_1028_011d, + &pci_ss_info_8086_24cd_1028_0126, + &pci_ss_info_8086_24cd_1028_0139, + &pci_ss_info_8086_24cd_1028_0163, + &pci_ss_info_8086_24cd_1028_0196, + &pci_ss_info_8086_24cd_103c_088c, + &pci_ss_info_8086_24cd_103c_0890, + &pci_ss_info_8086_24cd_1071_8160, + &pci_ss_info_8086_24cd_1462_3981, + &pci_ss_info_8086_24cd_1509_1968, + &pci_ss_info_8086_24cd_1734_1055, + &pci_ss_info_8086_24cd_4c53_1090, + NULL +}; +#define pci_ss_list_8086_24d0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d1[] = { + &pci_ss_info_8086_24d1_1028_0169, + &pci_ss_info_8086_24d1_1028_019a, + &pci_ss_info_8086_24d1_103c_12bc, + &pci_ss_info_8086_24d1_1043_80a6, + &pci_ss_info_8086_24d1_1458_24d1, + &pci_ss_info_8086_24d1_1462_7280, + &pci_ss_info_8086_24d1_15d9_4580, + &pci_ss_info_8086_24d1_8086_3427, + &pci_ss_info_8086_24d1_8086_4246, + &pci_ss_info_8086_24d1_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d2[] = { + &pci_ss_info_8086_24d2_1014_02ed, + &pci_ss_info_8086_24d2_1028_0169, + &pci_ss_info_8086_24d2_1028_0183, + &pci_ss_info_8086_24d2_1028_019a, + &pci_ss_info_8086_24d2_103c_006a, + &pci_ss_info_8086_24d2_103c_12bc, + &pci_ss_info_8086_24d2_1043_80a6, + &pci_ss_info_8086_24d2_1458_24d2, + &pci_ss_info_8086_24d2_1462_7280, + &pci_ss_info_8086_24d2_15d9_4580, + &pci_ss_info_8086_24d2_1734_101c, + &pci_ss_info_8086_24d2_8086_3427, + &pci_ss_info_8086_24d2_8086_4246, + &pci_ss_info_8086_24d2_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d3[] = { + &pci_ss_info_8086_24d3_1014_02ed, + &pci_ss_info_8086_24d3_1028_0169, + &pci_ss_info_8086_24d3_1043_80a6, + &pci_ss_info_8086_24d3_1458_24d2, + &pci_ss_info_8086_24d3_1462_7280, + &pci_ss_info_8086_24d3_15d9_4580, + &pci_ss_info_8086_24d3_1734_101c, + &pci_ss_info_8086_24d3_8086_3427, + &pci_ss_info_8086_24d3_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d4[] = { + &pci_ss_info_8086_24d4_1014_02ed, + &pci_ss_info_8086_24d4_1028_0169, + &pci_ss_info_8086_24d4_1028_0183, + &pci_ss_info_8086_24d4_1028_019a, + &pci_ss_info_8086_24d4_103c_006a, + &pci_ss_info_8086_24d4_103c_12bc, + &pci_ss_info_8086_24d4_1043_80a6, + &pci_ss_info_8086_24d4_1458_24d2, + &pci_ss_info_8086_24d4_1462_7280, + &pci_ss_info_8086_24d4_15d9_4580, + &pci_ss_info_8086_24d4_1734_101c, + &pci_ss_info_8086_24d4_8086_3427, + &pci_ss_info_8086_24d4_8086_4246, + &pci_ss_info_8086_24d4_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d5[] = { + &pci_ss_info_8086_24d5_1028_0169, + &pci_ss_info_8086_24d5_103c_006a, + &pci_ss_info_8086_24d5_103c_12bc, + &pci_ss_info_8086_24d5_1043_80f3, + &pci_ss_info_8086_24d5_1043_810f, + &pci_ss_info_8086_24d5_1458_a002, + &pci_ss_info_8086_24d5_1462_0080, + &pci_ss_info_8086_24d5_1462_7280, + &pci_ss_info_8086_24d5_8086_a000, + &pci_ss_info_8086_24d5_8086_e000, + &pci_ss_info_8086_24d5_8086_e001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d6[] = { + &pci_ss_info_8086_24d6_103c_006a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d7[] = { + &pci_ss_info_8086_24d7_1014_02ed, + &pci_ss_info_8086_24d7_1028_0169, + &pci_ss_info_8086_24d7_1028_0183, + &pci_ss_info_8086_24d7_103c_006a, + &pci_ss_info_8086_24d7_103c_12bc, + &pci_ss_info_8086_24d7_1043_80a6, + &pci_ss_info_8086_24d7_1458_24d2, + &pci_ss_info_8086_24d7_1462_7280, + &pci_ss_info_8086_24d7_15d9_4580, + &pci_ss_info_8086_24d7_1734_101c, + &pci_ss_info_8086_24d7_8086_3427, + &pci_ss_info_8086_24d7_8086_4246, + &pci_ss_info_8086_24d7_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24db[] = { + &pci_ss_info_8086_24db_1014_02ed, + &pci_ss_info_8086_24db_1028_0169, + &pci_ss_info_8086_24db_1028_019a, + &pci_ss_info_8086_24db_103c_006a, + &pci_ss_info_8086_24db_103c_12bc, + &pci_ss_info_8086_24db_1043_80a6, + &pci_ss_info_8086_24db_1458_24d2, + &pci_ss_info_8086_24db_1462_7280, + &pci_ss_info_8086_24db_1462_7580, + &pci_ss_info_8086_24db_15d9_4580, + &pci_ss_info_8086_24db_1734_101c, + &pci_ss_info_8086_24db_8086_24db, + &pci_ss_info_8086_24db_8086_3427, + &pci_ss_info_8086_24db_8086_4246, + &pci_ss_info_8086_24db_8086_524c, + NULL +}; +#define pci_ss_list_8086_24dc NULL +static const pciSubsystemInfo *pci_ss_list_8086_24dd[] = { + &pci_ss_info_8086_24dd_1014_02ed, + &pci_ss_info_8086_24dd_1028_0169, + &pci_ss_info_8086_24dd_1028_0183, + &pci_ss_info_8086_24dd_1028_019a, + &pci_ss_info_8086_24dd_103c_006a, + &pci_ss_info_8086_24dd_103c_12bc, + &pci_ss_info_8086_24dd_1043_80a6, + &pci_ss_info_8086_24dd_1458_5006, + &pci_ss_info_8086_24dd_1462_7280, + &pci_ss_info_8086_24dd_8086_3427, + &pci_ss_info_8086_24dd_8086_4246, + &pci_ss_info_8086_24dd_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24de[] = { + &pci_ss_info_8086_24de_1014_02ed, + &pci_ss_info_8086_24de_1028_0169, + &pci_ss_info_8086_24de_1043_80a6, + &pci_ss_info_8086_24de_1458_24d2, + &pci_ss_info_8086_24de_1462_7280, + &pci_ss_info_8086_24de_15d9_4580, + &pci_ss_info_8086_24de_1734_101c, + &pci_ss_info_8086_24de_8086_3427, + &pci_ss_info_8086_24de_8086_4246, + &pci_ss_info_8086_24de_8086_524c, + NULL +}; +#define pci_ss_list_8086_24df NULL +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + &pci_ss_info_8086_2541_4c53_1090, + &pci_ss_info_8086_2541_8086_3424, + NULL +}; +#define pci_ss_list_8086_2543 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2544[] = { + &pci_ss_info_8086_2544_4c53_1090, + NULL +}; +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_254c[] = { + &pci_ss_info_8086_254c_4c53_1090, + &pci_ss_info_8086_254c_8086_3424, + NULL +}; +#define pci_ss_list_8086_2550 NULL +#define pci_ss_list_8086_2551 NULL +#define pci_ss_list_8086_2552 NULL +#define pci_ss_list_8086_2553 NULL +#define pci_ss_list_8086_2554 NULL +#define pci_ss_list_8086_255d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1028_0126, + &pci_ss_info_8086_2560_1458_2560, + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2562[] = { + &pci_ss_info_8086_2562_1014_0267, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2570[] = { + &pci_ss_info_8086_2570_103c_006a, + &pci_ss_info_8086_2570_1043_80f2, + &pci_ss_info_8086_2570_1458_2570, + NULL +}; +#define pci_ss_list_8086_2571 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2572[] = { + &pci_ss_info_8086_2572_1028_019d, + &pci_ss_info_8086_2572_1043_80a5, + NULL +}; +#define pci_ss_list_8086_2573 NULL +#define pci_ss_list_8086_2576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2578[] = { + &pci_ss_info_8086_2578_1458_2578, + &pci_ss_info_8086_2578_1462_7580, + &pci_ss_info_8086_2578_15d9_4580, + NULL +}; +#define pci_ss_list_8086_2579 NULL +#define pci_ss_list_8086_257b NULL +#define pci_ss_list_8086_257e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2580[] = { + &pci_ss_info_8086_2580_1458_2580, + &pci_ss_info_8086_2580_1462_7028, + &pci_ss_info_8086_2580_1734_105b, + NULL +}; +#define pci_ss_list_8086_2581 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2582[] = { + &pci_ss_info_8086_2582_1028_1079, + &pci_ss_info_8086_2582_1043_2582, + &pci_ss_info_8086_2582_1458_2582, + &pci_ss_info_8086_2582_1734_105b, + NULL +}; +#define pci_ss_list_8086_2584 NULL +#define pci_ss_list_8086_2585 NULL +#define pci_ss_list_8086_2588 NULL +#define pci_ss_list_8086_2589 NULL +#define pci_ss_list_8086_258a NULL +static const pciSubsystemInfo *pci_ss_list_8086_2590[] = { + &pci_ss_info_8086_2590_103c_099c, + &pci_ss_info_8086_2590_a304_81b7, + NULL +}; +#define pci_ss_list_8086_2591 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2592[] = { + &pci_ss_info_8086_2592_103c_099c, + &pci_ss_info_8086_2592_1043_1881, + NULL +}; +#define pci_ss_list_8086_25a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a2[] = { + &pci_ss_info_8086_25a2_4c53_10b0, + &pci_ss_info_8086_25a2_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a3[] = { + &pci_ss_info_8086_25a3_4c53_10b0, + &pci_ss_info_8086_25a3_4c53_10d0, + &pci_ss_info_8086_25a3_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a4[] = { + &pci_ss_info_8086_25a4_4c53_10b0, + &pci_ss_info_8086_25a4_4c53_10d0, + &pci_ss_info_8086_25a4_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a6[] = { + &pci_ss_info_8086_25a6_4c53_10b0, + NULL +}; +#define pci_ss_list_8086_25a7 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a9[] = { + &pci_ss_info_8086_25a9_4c53_10b0, + &pci_ss_info_8086_25a9_4c53_10d0, + &pci_ss_info_8086_25a9_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25aa[] = { + &pci_ss_info_8086_25aa_4c53_10b0, + &pci_ss_info_8086_25aa_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ab[] = { + &pci_ss_info_8086_25ab_4c53_10b0, + &pci_ss_info_8086_25ab_4c53_10d0, + &pci_ss_info_8086_25ab_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ac[] = { + &pci_ss_info_8086_25ac_4c53_10b0, + &pci_ss_info_8086_25ac_4c53_10d0, + &pci_ss_info_8086_25ac_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ad[] = { + &pci_ss_info_8086_25ad_4c53_10b0, + &pci_ss_info_8086_25ad_4c53_10d0, + &pci_ss_info_8086_25ad_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25ae NULL +static const pciSubsystemInfo *pci_ss_list_8086_25b0[] = { + &pci_ss_info_8086_25b0_4c53_10d0, + &pci_ss_info_8086_25b0_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25c0 NULL +#define pci_ss_list_8086_25d0 NULL +#define pci_ss_list_8086_25d4 NULL +#define pci_ss_list_8086_25d8 NULL +#define pci_ss_list_8086_25e2 NULL +#define pci_ss_list_8086_25e3 NULL +#define pci_ss_list_8086_25e4 NULL +#define pci_ss_list_8086_25e5 NULL +#define pci_ss_list_8086_25e6 NULL +#define pci_ss_list_8086_25e7 NULL +#define pci_ss_list_8086_25e8 NULL +#define pci_ss_list_8086_25f0 NULL +#define pci_ss_list_8086_25f1 NULL +#define pci_ss_list_8086_25f3 NULL +#define pci_ss_list_8086_25f5 NULL +#define pci_ss_list_8086_25f6 NULL +#define pci_ss_list_8086_25f7 NULL +#define pci_ss_list_8086_25f8 NULL +#define pci_ss_list_8086_25f9 NULL +#define pci_ss_list_8086_25fa NULL +#define pci_ss_list_8086_2600 NULL +#define pci_ss_list_8086_2601 NULL +#define pci_ss_list_8086_2602 NULL +#define pci_ss_list_8086_2603 NULL +#define pci_ss_list_8086_2604 NULL +#define pci_ss_list_8086_2605 NULL +#define pci_ss_list_8086_2606 NULL +#define pci_ss_list_8086_2607 NULL +#define pci_ss_list_8086_2608 NULL +#define pci_ss_list_8086_2609 NULL +#define pci_ss_list_8086_260a NULL +#define pci_ss_list_8086_260c NULL +#define pci_ss_list_8086_2610 NULL +#define pci_ss_list_8086_2611 NULL +#define pci_ss_list_8086_2612 NULL +#define pci_ss_list_8086_2613 NULL +#define pci_ss_list_8086_2614 NULL +#define pci_ss_list_8086_2615 NULL +#define pci_ss_list_8086_2617 NULL +#define pci_ss_list_8086_2618 NULL +#define pci_ss_list_8086_2619 NULL +#define pci_ss_list_8086_261a NULL +#define pci_ss_list_8086_261b NULL +#define pci_ss_list_8086_261c NULL +#define pci_ss_list_8086_261d NULL +#define pci_ss_list_8086_261e NULL +#define pci_ss_list_8086_2620 NULL +#define pci_ss_list_8086_2621 NULL +#define pci_ss_list_8086_2622 NULL +#define pci_ss_list_8086_2623 NULL +#define pci_ss_list_8086_2624 NULL +#define pci_ss_list_8086_2625 NULL +#define pci_ss_list_8086_2626 NULL +#define pci_ss_list_8086_2627 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2640[] = { + &pci_ss_info_8086_2640_1462_7028, + &pci_ss_info_8086_2640_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2641[] = { + &pci_ss_info_8086_2641_103c_099c, + NULL +}; +#define pci_ss_list_8086_2642 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2651[] = { + &pci_ss_info_8086_2651_1028_0179, + &pci_ss_info_8086_2651_1043_2601, + &pci_ss_info_8086_2651_1734_105c, + &pci_ss_info_8086_2651_8086_4147, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2652[] = { + &pci_ss_info_8086_2652_1462_7028, + NULL +}; +#define pci_ss_list_8086_2653 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2658[] = { + &pci_ss_info_8086_2658_1028_0179, + &pci_ss_info_8086_2658_103c_099c, + &pci_ss_info_8086_2658_1043_80a6, + &pci_ss_info_8086_2658_1458_2558, + &pci_ss_info_8086_2658_1462_7028, + &pci_ss_info_8086_2658_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2659[] = { + &pci_ss_info_8086_2659_1028_0179, + &pci_ss_info_8086_2659_103c_099c, + &pci_ss_info_8086_2659_1043_80a6, + &pci_ss_info_8086_2659_1458_2659, + &pci_ss_info_8086_2659_1462_7028, + &pci_ss_info_8086_2659_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265a[] = { + &pci_ss_info_8086_265a_1028_0179, + &pci_ss_info_8086_265a_103c_099c, + &pci_ss_info_8086_265a_1043_80a6, + &pci_ss_info_8086_265a_1458_265a, + &pci_ss_info_8086_265a_1462_7028, + &pci_ss_info_8086_265a_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265b[] = { + &pci_ss_info_8086_265b_1028_0179, + &pci_ss_info_8086_265b_103c_099c, + &pci_ss_info_8086_265b_1043_80a6, + &pci_ss_info_8086_265b_1458_265a, + &pci_ss_info_8086_265b_1462_7028, + &pci_ss_info_8086_265b_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265c[] = { + &pci_ss_info_8086_265c_1028_0179, + &pci_ss_info_8086_265c_103c_099c, + &pci_ss_info_8086_265c_1043_80a6, + &pci_ss_info_8086_265c_1458_5006, + &pci_ss_info_8086_265c_1462_7028, + &pci_ss_info_8086_265c_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2660[] = { + &pci_ss_info_8086_2660_103c_099c, + NULL +}; +#define pci_ss_list_8086_2662 NULL +#define pci_ss_list_8086_2664 NULL +#define pci_ss_list_8086_2666 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2668[] = { + &pci_ss_info_8086_2668_1043_814e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266a[] = { + &pci_ss_info_8086_266a_1028_0179, + &pci_ss_info_8086_266a_1043_80a6, + &pci_ss_info_8086_266a_1458_266a, + &pci_ss_info_8086_266a_1462_7028, + &pci_ss_info_8086_266a_1734_105c, + NULL +}; +#define pci_ss_list_8086_266c NULL +static const pciSubsystemInfo *pci_ss_list_8086_266d[] = { + &pci_ss_info_8086_266d_1025_006a, + &pci_ss_info_8086_266d_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266e[] = { + &pci_ss_info_8086_266e_1025_006a, + &pci_ss_info_8086_266e_1028_0179, + &pci_ss_info_8086_266e_1028_0182, + &pci_ss_info_8086_266e_1028_0188, + &pci_ss_info_8086_266e_103c_099c, + &pci_ss_info_8086_266e_1458_a002, + &pci_ss_info_8086_266e_1734_105a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266f[] = { + &pci_ss_info_8086_266f_103c_099c, + &pci_ss_info_8086_266f_1043_80a6, + &pci_ss_info_8086_266f_1458_266f, + &pci_ss_info_8086_266f_1462_7028, + &pci_ss_info_8086_266f_1734_105c, + NULL +}; +#define pci_ss_list_8086_2670 NULL +#define pci_ss_list_8086_2680 NULL +#define pci_ss_list_8086_2681 NULL +#define pci_ss_list_8086_2682 NULL +#define pci_ss_list_8086_2683 NULL +#define pci_ss_list_8086_2688 NULL +#define pci_ss_list_8086_2689 NULL +#define pci_ss_list_8086_268a NULL +#define pci_ss_list_8086_268b NULL +#define pci_ss_list_8086_268c NULL +#define pci_ss_list_8086_2690 NULL +#define pci_ss_list_8086_2692 NULL +#define pci_ss_list_8086_2694 NULL +#define pci_ss_list_8086_2696 NULL +#define pci_ss_list_8086_2698 NULL +#define pci_ss_list_8086_2699 NULL +#define pci_ss_list_8086_269a NULL +#define pci_ss_list_8086_269b NULL +#define pci_ss_list_8086_269e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2770[] = { + &pci_ss_info_8086_2770_8086_544e, + NULL +}; +#define pci_ss_list_8086_2771 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2772[] = { + &pci_ss_info_8086_2772_8086_544e, + NULL +}; +#define pci_ss_list_8086_2774 NULL +#define pci_ss_list_8086_2775 NULL +#define pci_ss_list_8086_2776 NULL +#define pci_ss_list_8086_2778 NULL +#define pci_ss_list_8086_2779 NULL +#define pci_ss_list_8086_277a NULL +#define pci_ss_list_8086_277c NULL +#define pci_ss_list_8086_277d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2782[] = { + &pci_ss_info_8086_2782_1043_2582, + &pci_ss_info_8086_2782_1734_105b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2792[] = { + &pci_ss_info_8086_2792_103c_099c, + &pci_ss_info_8086_2792_1043_1881, + NULL +}; +#define pci_ss_list_8086_27a0 NULL +#define pci_ss_list_8086_27a1 NULL +#define pci_ss_list_8086_27a2 NULL +#define pci_ss_list_8086_27a6 NULL +#define pci_ss_list_8086_27b0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27b8[] = { + &pci_ss_info_8086_27b8_8086_544e, + NULL +}; +#define pci_ss_list_8086_27b9 NULL +#define pci_ss_list_8086_27bd NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c0[] = { + &pci_ss_info_8086_27c0_8086_544e, + NULL +}; +#define pci_ss_list_8086_27c1 NULL +#define pci_ss_list_8086_27c3 NULL +#define pci_ss_list_8086_27c4 NULL +#define pci_ss_list_8086_27c5 NULL +#define pci_ss_list_8086_27c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c8[] = { + &pci_ss_info_8086_27c8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27c9[] = { + &pci_ss_info_8086_27c9_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27ca[] = { + &pci_ss_info_8086_27ca_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cb[] = { + &pci_ss_info_8086_27cb_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cc[] = { + &pci_ss_info_8086_27cc_8086_544e, + NULL +}; +#define pci_ss_list_8086_27d0 NULL +#define pci_ss_list_8086_27d2 NULL +#define pci_ss_list_8086_27d4 NULL +#define pci_ss_list_8086_27d6 NULL +#define pci_ss_list_8086_27d8 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27da[] = { + &pci_ss_info_8086_27da_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27dc[] = { + &pci_ss_info_8086_27dc_8086_308d, + NULL +}; +#define pci_ss_list_8086_27dd NULL +#define pci_ss_list_8086_27de NULL +static const pciSubsystemInfo *pci_ss_list_8086_27df[] = { + &pci_ss_info_8086_27df_8086_544e, + NULL +}; +#define pci_ss_list_8086_27e0 NULL +#define pci_ss_list_8086_27e2 NULL +#define pci_ss_list_8086_2810 NULL +#define pci_ss_list_8086_2811 NULL +#define pci_ss_list_8086_2812 NULL +#define pci_ss_list_8086_2814 NULL +#define pci_ss_list_8086_2815 NULL +#define pci_ss_list_8086_2820 NULL +#define pci_ss_list_8086_2821 NULL +#define pci_ss_list_8086_2822 NULL +#define pci_ss_list_8086_2824 NULL +#define pci_ss_list_8086_2825 NULL +#define pci_ss_list_8086_2828 NULL +#define pci_ss_list_8086_2829 NULL +#define pci_ss_list_8086_282a NULL +#define pci_ss_list_8086_2830 NULL +#define pci_ss_list_8086_2831 NULL +#define pci_ss_list_8086_2832 NULL +#define pci_ss_list_8086_2834 NULL +#define pci_ss_list_8086_2835 NULL +#define pci_ss_list_8086_2836 NULL +#define pci_ss_list_8086_283a NULL +#define pci_ss_list_8086_283e NULL +#define pci_ss_list_8086_283f NULL +#define pci_ss_list_8086_2841 NULL +#define pci_ss_list_8086_2843 NULL +#define pci_ss_list_8086_2844 NULL +#define pci_ss_list_8086_2847 NULL +#define pci_ss_list_8086_2849 NULL +#define pci_ss_list_8086_284b NULL +#define pci_ss_list_8086_284f NULL +#define pci_ss_list_8086_2850 NULL +#define pci_ss_list_8086_2970 NULL +#define pci_ss_list_8086_2971 NULL +#define pci_ss_list_8086_2972 NULL +#define pci_ss_list_8086_2973 NULL +#define pci_ss_list_8086_3092 NULL +#define pci_ss_list_8086_3200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3340[] = { + &pci_ss_info_8086_3340_1025_005a, + &pci_ss_info_8086_3340_103c_088c, + &pci_ss_info_8086_3340_103c_0890, + NULL +}; +#define pci_ss_list_8086_3341 NULL +#define pci_ss_list_8086_3500 NULL +#define pci_ss_list_8086_3501 NULL +#define pci_ss_list_8086_3504 NULL +#define pci_ss_list_8086_3505 NULL +#define pci_ss_list_8086_350c NULL +#define pci_ss_list_8086_350d NULL +#define pci_ss_list_8086_3510 NULL +#define pci_ss_list_8086_3511 NULL +#define pci_ss_list_8086_3514 NULL +#define pci_ss_list_8086_3515 NULL +#define pci_ss_list_8086_3518 NULL +#define pci_ss_list_8086_3519 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_0e11_0030, + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3580[] = { + &pci_ss_info_8086_3580_1028_0139, + &pci_ss_info_8086_3580_1028_0163, + &pci_ss_info_8086_3580_1028_0196, + &pci_ss_info_8086_3580_1734_1055, + &pci_ss_info_8086_3580_4c53_10b0, + &pci_ss_info_8086_3580_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3581[] = { + &pci_ss_info_8086_3581_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3582[] = { + &pci_ss_info_8086_3582_1028_0139, + &pci_ss_info_8086_3582_1028_0163, + &pci_ss_info_8086_3582_4c53_10b0, + &pci_ss_info_8086_3582_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3584[] = { + &pci_ss_info_8086_3584_1028_0139, + &pci_ss_info_8086_3584_1028_0163, + &pci_ss_info_8086_3584_1028_0196, + &pci_ss_info_8086_3584_1734_1055, + &pci_ss_info_8086_3584_4c53_10b0, + &pci_ss_info_8086_3584_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3585[] = { + &pci_ss_info_8086_3585_1028_0139, + &pci_ss_info_8086_3585_1028_0163, + &pci_ss_info_8086_3585_1028_0196, + &pci_ss_info_8086_3585_1734_1055, + &pci_ss_info_8086_3585_4c53_10b0, + &pci_ss_info_8086_3585_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3590[] = { + &pci_ss_info_8086_3590_1028_019a, + &pci_ss_info_8086_3590_1734_103e, + &pci_ss_info_8086_3590_4c53_10d0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3591[] = { + &pci_ss_info_8086_3591_1028_0169, + &pci_ss_info_8086_3591_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3592 NULL +#define pci_ss_list_8086_3593 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3594[] = { + &pci_ss_info_8086_3594_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3595 NULL +#define pci_ss_list_8086_3596 NULL +#define pci_ss_list_8086_3597 NULL +#define pci_ss_list_8086_3598 NULL +#define pci_ss_list_8086_3599 NULL +#define pci_ss_list_8086_359a NULL +#define pci_ss_list_8086_359b NULL +static const pciSubsystemInfo *pci_ss_list_8086_359e[] = { + &pci_ss_info_8086_359e_1028_0169, + NULL +}; +#define pci_ss_list_8086_4220 NULL +#define pci_ss_list_8086_4223 NULL +#define pci_ss_list_8086_4224 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7050 NULL +#define pci_ss_list_8086_7051 NULL +#define pci_ss_list_8086_7100 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7110[] = { + &pci_ss_info_8086_7110_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7111[] = { + &pci_ss_info_8086_7111_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7112[] = { + &pci_ss_info_8086_7112_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7113[] = { + &pci_ss_info_8086_7113_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7120[] = { + &pci_ss_info_8086_7120_4c53_1040, + &pci_ss_info_8086_7120_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7121[] = { + &pci_ss_info_8086_7121_4c53_1040, + &pci_ss_info_8086_7121_4c53_1060, + &pci_ss_info_8086_7121_8086_4341, + NULL +}; +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1179_0001, + &pci_ss_info_8086_7190_15ad_1976, + &pci_ss_info_8086_7190_4c53_1050, + &pci_ss_info_8086_7190_4c53_1051, + NULL +}; +#define pci_ss_list_8086_7191 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + &pci_ss_info_8086_7192_4c53_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7194[] = { + &pci_ss_info_8086_7194_1033_0000, + &pci_ss_info_8086_7194_4c53_10a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_1033_80cc, + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a0[] = { + &pci_ss_info_8086_71a0_4c53_1050, + &pci_ss_info_8086_71a0_4c53_1051, + NULL +}; +#define pci_ss_list_8086_71a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a2[] = { + &pci_ss_info_8086_71a2_4c53_1000, + NULL +}; +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +static const pciSubsystemInfo *pci_ss_list_8086_8500[] = { + &pci_ss_info_8086_8500_1993_0ded, + &pci_ss_info_8086_8500_1993_0dee, + &pci_ss_info_8086_8500_1993_0def, + NULL +}; +#define pci_ss_list_8086_9000 NULL +#define pci_ss_list_8086_9001 NULL +#define pci_ss_list_8086_9004 NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_12d9_000a, + &pci_ss_info_8086_b555_4c53_1050, + &pci_ss_info_8086_b555_4c53_1051, + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8c4a_1980 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_0078 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7710 NULL +#define pci_ss_list_9004_7711 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +#define pci_ss_list_9004_8178 NULL +#endif +#ifdef INIT_VENDOR_SUBSYS_INFO +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0000[] = { + &pci_ss_info_0000_0000, + &pci_ss_info_0000_4091, + NULL +}; +#endif +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#define pci_ss_list_0059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_0003, + &pci_ss_info_0070_0009, + &pci_ss_info_0070_0801, + &pci_ss_info_0070_0807, + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_2801, + &pci_ss_info_0070_3401, + &pci_ss_info_0070_4000, + &pci_ss_info_0070_4001, + &pci_ss_info_0070_4009, + &pci_ss_info_0070_4800, + &pci_ss_info_0070_4801, + &pci_ss_info_0070_4803, + &pci_ss_info_0070_8003, + &pci_ss_info_0070_8801, + &pci_ss_info_0070_9001, + &pci_ss_info_0070_9002, + &pci_ss_info_0070_9200, + &pci_ss_info_0070_9202, + &pci_ss_info_0070_9402, + &pci_ss_info_0070_9802, + &pci_ss_info_0070_c801, + &pci_ss_info_0070_e807, + &pci_ss_info_0070_e817, + &pci_ss_info_0070_ff01, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0071[] = { + &pci_ss_info_0071_0101, + NULL +}; +#endif +#define pci_ss_list_0095 NULL +#define pci_ss_list_00a7 NULL +#define pci_ss_list_0100 NULL +#define pci_ss_list_018a NULL +#define pci_ss_list_021b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0270[] = { + &pci_ss_info_0270_0801, + NULL +}; +#endif +#define pci_ss_list_0291 NULL +#define pci_ss_list_02ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0357[] = { + &pci_ss_info_0357_000a, + NULL +}; +#endif +#define pci_ss_list_0432 NULL +#define pci_ss_list_045e NULL +#define pci_ss_list_04cf NULL +#define pci_ss_list_050d NULL +#define pci_ss_list_05e3 NULL +#define pci_ss_list_066f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0675[] = { + &pci_ss_info_0675_1704, + &pci_ss_info_0675_1707, + &pci_ss_info_0675_1708, + NULL +}; +#endif +#define pci_ss_list_067b NULL +#define pci_ss_list_0721 NULL +#define pci_ss_list_07e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +#define pci_ss_list_0b49 NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0030, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_004e, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0097, + &pci_ss_info_0e11_0098, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00b8, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_00da, + &pci_ss_info_0e11_00db, + &pci_ss_info_0e11_00dc, + &pci_ss_info_0e11_00e3, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_4080, + &pci_ss_info_0e11_4082, + &pci_ss_info_0e11_4083, + &pci_ss_info_0e11_409a, + &pci_ss_info_0e11_409b, + &pci_ss_info_0e11_409c, + &pci_ss_info_0e11_409d, + &pci_ss_info_0e11_6004, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e7, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b121, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b160, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + NULL +}; +#define pci_ss_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_0001, + &pci_ss_info_1000_0002, + &pci_ss_info_1000_0033, + &pci_ss_info_1000_0062, + &pci_ss_info_1000_0066, + &pci_ss_info_1000_0518, + &pci_ss_info_1000_0520, + &pci_ss_info_1000_0522, + &pci_ss_info_1000_0523, + &pci_ss_info_1000_0530, + &pci_ss_info_1000_0531, + &pci_ss_info_1000_0532, + &pci_ss_info_1000_1000, + &pci_ss_info_1000_1010, + &pci_ss_info_1000_1020, + &pci_ss_info_1000_3004, + &pci_ss_info_1000_3008, + &pci_ss_info_1000_4523, + &pci_ss_info_1000_a520, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_00f8, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0322, + &pci_ss_info_1002_0323, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_0b12, + &pci_ss_info_1002_0b13, + &pci_ss_info_1002_0d02, + &pci_ss_info_1002_0d03, + &pci_ss_info_1002_103a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_2f72, + &pci_ss_info_1002_4336, + &pci_ss_info_1002_4722, + &pci_ss_info_1002_4723, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4772, + &pci_ss_info_1002_4773, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_4e71, + &pci_ss_info_1002_515e, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_5954, + &pci_ss_info_1002_5955, + &pci_ss_info_1002_5965, + &pci_ss_info_1002_5c63, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + &pci_ss_info_1002_a101, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1005[] = { + &pci_ss_info_1005_127a, + NULL +}; +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + &pci_ss_info_1013_5959, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_0031, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0092, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0104, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0130, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020c, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021a, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0241, + &pci_ss_info_1014_0242, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0251, + &pci_ss_info_1014_0252, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0264, + &pci_ss_info_1014_0265, + &pci_ss_info_1014_0266, + &pci_ss_info_1014_0267, + &pci_ss_info_1014_0268, + &pci_ss_info_1014_0269, + &pci_ss_info_1014_026a, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0278, + &pci_ss_info_1014_027c, + &pci_ss_info_1014_028d, + &pci_ss_info_1014_028e, + &pci_ss_info_1014_029a, + &pci_ss_info_1014_02be, + &pci_ss_info_1014_02c0, + &pci_ss_info_1014_02c1, + &pci_ss_info_1014_02c2, + &pci_ss_info_1014_02c6, + &pci_ss_info_1014_02c8, + &pci_ss_info_1014_02d3, + &pci_ss_info_1014_02d4, + &pci_ss_info_1014_02ed, + &pci_ss_info_1014_030d, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_050f, + &pci_ss_info_1014_0510, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_0528, + &pci_ss_info_1014_052c, + &pci_ss_info_1014_0535, + &pci_ss_info_1014_053a, + &pci_ss_info_1014_053b, + &pci_ss_info_1014_053c, + &pci_ss_info_1014_053d, + &pci_ss_info_1014_053e, + &pci_ss_info_1014_0540, + &pci_ss_info_1014_0545, + &pci_ss_info_1014_0549, + &pci_ss_info_1014_0556, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_1025, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_0985, + &pci_ss_info_1019_0987, + &pci_ss_info_1019_0a14, + &pci_ss_info_1019_0a81, + &pci_ss_info_1019_0f38, + &pci_ss_info_1019_4c30, + &pci_ss_info_1019_4cb4, + &pci_ss_info_1019_4cb5, + &pci_ss_info_1019_7018, + &pci_ss_info_1019_8001, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0477, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0494, + &pci_ss_info_101e_0503, + &pci_ss_info_101e_0511, + &pci_ss_info_101e_0522, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101f[] = { + &pci_ss_info_101f_1025, + NULL +}; +#endif +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +static const pciSubsystemInfo *pci_ss_list_1022[] = { + &pci_ss_info_1022_2000, + &pci_ss_info_1022_2b80, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1024[] = { + &pci_ss_info_1024_0134, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_004d, + &pci_ss_info_1025_005a, + &pci_ss_info_1025_006a, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_002e, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00aa, + &pci_ss_info_1028_00b1, + &pci_ss_info_1028_00bb, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00ce, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_00fe, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_010e, + &pci_ss_info_1028_011c, + &pci_ss_info_1028_011d, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0123, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_012a, + &pci_ss_info_1028_0134, + &pci_ss_info_1028_0139, + &pci_ss_info_1028_014a, + &pci_ss_info_1028_014e, + &pci_ss_info_1028_0151, + &pci_ss_info_1028_0163, + &pci_ss_info_1028_0165, + &pci_ss_info_1028_0169, + &pci_ss_info_1028_016c, + &pci_ss_info_1028_016d, + &pci_ss_info_1028_016e, + &pci_ss_info_1028_016f, + &pci_ss_info_1028_0170, + &pci_ss_info_1028_0179, + &pci_ss_info_1028_0182, + &pci_ss_info_1028_0183, + &pci_ss_info_1028_0188, + &pci_ss_info_1028_0196, + &pci_ss_info_1028_019a, + &pci_ss_info_1028_019d, + &pci_ss_info_1028_01a2, + &pci_ss_info_1028_01ad, + &pci_ss_info_1028_0407, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_0533, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1079, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_4134, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_865d, + &pci_ss_info_1028_c082, + &pci_ss_info_1028_c134, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0850, + &pci_ss_info_102b_08c7, + &pci_ss_info_102b_0907, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0d43, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1020, + &pci_ss_info_102b_1030, + &pci_ss_info_102b_1047, + &pci_ss_info_102b_1087, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_14e1, + &pci_ss_info_102b_1820, + &pci_ss_info_102b_1830, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1c10, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2021, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2538, + &pci_ss_info_102b_2811, + &pci_ss_info_102b_2c11, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3007, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48d0, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_0000, + &pci_ss_info_1033_0035, + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80a8, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + &pci_ss_info_1033_80cc, + &pci_ss_info_1033_80cd, + &pci_ss_info_1033_80e5, + &pci_ss_info_1033_8110, + &pci_ss_info_1033_8112, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_6330, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_0024, + &pci_ss_info_103c_006a, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_0850, + &pci_ss_info_103c_088c, + &pci_ss_info_103c_0890, + &pci_ss_info_103c_099c, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_10eb, + &pci_ss_info_103c_10ec, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + &pci_ss_info_103c_128a, + &pci_ss_info_103c_128b, + &pci_ss_info_103c_12a4, + &pci_ss_info_103c_12a6, + &pci_ss_info_103c_12a8, + &pci_ss_info_103c_12bc, + &pci_ss_info_103c_12c1, + &pci_ss_info_103c_12c3, + &pci_ss_info_103c_12ca, + &pci_ss_info_103c_12cf, + &pci_ss_info_103c_12d5, + &pci_ss_info_103c_12f4, + &pci_ss_info_103c_12fa, + &pci_ss_info_103c_1300, + &pci_ss_info_103c_1301, + &pci_ss_info_103c_1356, + &pci_ss_info_103c_2a0d, + &pci_ss_info_103c_308b, + &pci_ss_info_103c_3100, + &pci_ss_info_103c_3101, + &pci_ss_info_103c_3102, + &pci_ss_info_103c_3103, + &pci_ss_info_103c_3226, + &pci_ss_info_103c_60e7, + &pci_ss_info_103c_7031, + &pci_ss_info_103c_7032, + &pci_ss_info_103c_7039, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_002a, + &pci_ss_info_1043_0120, + &pci_ss_info_1043_0127, + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0210, + &pci_ss_info_1043_032e, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_100f, + &pci_ss_info_1043_1106, + &pci_ss_info_1043_130f, + &pci_ss_info_1043_1702, + &pci_ss_info_1043_1703, + &pci_ss_info_1043_1707, + &pci_ss_info_1043_173c, + &pci_ss_info_1043_1881, + &pci_ss_info_1043_1967, + &pci_ss_info_1043_1987, + &pci_ss_info_1043_2582, + &pci_ss_info_1043_2601, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_4823, + &pci_ss_info_1043_4840, + &pci_ss_info_1043_4843, + &pci_ss_info_1043_4845, + &pci_ss_info_1043_4862, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8023, + &pci_ss_info_1043_8025, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_802c, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_8035, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_806f, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807e, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_8080, + &pci_ss_info_1043_808a, + &pci_ss_info_1043_808b, + &pci_ss_info_1043_808c, + &pci_ss_info_1043_808d, + &pci_ss_info_1043_8095, + &pci_ss_info_1043_809e, + &pci_ss_info_1043_80a1, + &pci_ss_info_1043_80a3, + &pci_ss_info_1043_80a5, + &pci_ss_info_1043_80a6, + &pci_ss_info_1043_80a7, + &pci_ss_info_1043_80a8, + &pci_ss_info_1043_80ab, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80b0, + &pci_ss_info_1043_80e2, + &pci_ss_info_1043_80eb, + &pci_ss_info_1043_80ed, + &pci_ss_info_1043_80f2, + &pci_ss_info_1043_80f3, + &pci_ss_info_1043_80f4, + &pci_ss_info_1043_80f5, + &pci_ss_info_1043_80f8, + &pci_ss_info_1043_8109, + &pci_ss_info_1043_810f, + &pci_ss_info_1043_811a, + &pci_ss_info_1043_812a, + &pci_ss_info_1043_8134, + &pci_ss_info_1043_8138, + &pci_ss_info_1043_8141, + &pci_ss_info_1043_8142, + &pci_ss_info_1043_8145, + &pci_ss_info_1043_814a, + &pci_ss_info_1043_814e, + &pci_ss_info_1043_815a, + &pci_ss_info_1043_817b, + &pci_ss_info_1043_81a6, + &pci_ss_info_1043_c002, + &pci_ss_info_1043_c003, + &pci_ss_info_1043_c004, + &pci_ss_info_1043_c005, + &pci_ss_info_1043_c006, + &pci_ss_info_1043_c01a, + &pci_ss_info_1043_c01b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c032, + &pci_ss_info_1044_c035, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0935, + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a34, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0a36, + &pci_ss_info_1048_0a42, + &pci_ss_info_1048_0a43, + &pci_ss_info_1048_0a44, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c19, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c1c, + &pci_ss_info_1048_0c20, + &pci_ss_info_1048_0c21, + &pci_ss_info_1048_0c28, + &pci_ss_info_1048_0c29, + &pci_ss_info_1048_0c2a, + &pci_ss_info_1048_0c2b, + &pci_ss_info_1048_0c2e, + &pci_ss_info_1048_0c2f, + &pci_ss_info_1048_0c30, + &pci_ss_info_1048_0c31, + &pci_ss_info_1048_0c32, + &pci_ss_info_1048_0c33, + &pci_ss_info_1048_0c34, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c3b, + &pci_ss_info_1048_0c40, + &pci_ss_info_1048_0c41, + &pci_ss_info_1048_0c42, + &pci_ss_info_1048_0c43, + &pci_ss_info_1048_0c44, + &pci_ss_info_1048_0c45, + &pci_ss_info_1048_0c48, + &pci_ss_info_1048_0c4a, + &pci_ss_info_1048_0c4b, + &pci_ss_info_1048_0c50, + &pci_ss_info_1048_0c52, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_0c60, + &pci_ss_info_1048_0c61, + &pci_ss_info_1048_0c63, + &pci_ss_info_1048_0c64, + &pci_ss_info_1048_0c65, + &pci_ss_info_1048_0c66, + &pci_ss_info_1048_0c70, + &pci_ss_info_1048_1500, + &pci_ss_info_1048_226b, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +#define pci_ss_list_104a NULL +#define pci_ss_list_104b NULL +static const pciSubsystemInfo *pci_ss_list_104c[] = { + &pci_ss_info_104c_9066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_810f, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + &pci_ss_info_1057_7025, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_1275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105b[] = { + &pci_ss_info_105b_0c19, + NULL +}; +#endif +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_0037, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + &pci_ss_info_1069_0030, + &pci_ss_info_1069_0040, + &pci_ss_info_1069_0050, + &pci_ss_info_1069_0052, + &pci_ss_info_1069_0054, + &pci_ss_info_1069_0072, + &pci_ss_info_1069_0200, + &pci_ss_info_1069_0202, + &pci_ss_info_1069_0204, + &pci_ss_info_1069_0206, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b[] = { + &pci_ss_info_106b_004e, + &pci_ss_info_106b_5811, + NULL +}; +#endif +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1071[] = { + &pci_ss_info_1071_7150, + &pci_ss_info_1071_8160, + NULL +}; +#endif +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + &pci_ss_info_1077_0002, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1079[] = { + &pci_ss_info_1079_891f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_3015, + &pci_ss_info_107b_4009, + &pci_ss_info_107b_5350, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + &pci_ss_info_107b_8920, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2134, + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2822, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2842, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + &pci_ss_info_107d_6613, + &pci_ss_info_107d_6620, + &pci_ss_info_107d_663c, + &pci_ss_info_107d_665f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_108e[] = { + &pci_ss_info_108e_10cf, + NULL +}; +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_00b8, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + &pci_ss_info_1095_10cf, + &pci_ss_info_1095_3112, + &pci_ss_info_1095_3114, + &pci_ss_info_1095_3124, + &pci_ss_info_1095_3512, + &pci_ss_info_1095_3680, + &pci_ss_info_1095_6112, + &pci_ss_info_1095_6114, + &pci_ss_info_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + &pci_ss_info_109f_3197, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9[] = { + &pci_ss_info_10a9_8002, + &pci_ss_info_10a9_8010, + &pci_ss_info_10a9_8011, + &pci_ss_info_10a9_8012, + NULL +}; +#endif +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + &pci_ss_info_10b0_0002, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_1067, + &pci_ss_info_10b5_1172, + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2221, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2431, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_2696, + &pci_ss_info_10b5_2717, + &pci_ss_info_10b5_2844, + &pci_ss_info_10b5_2862, + &pci_ss_info_10b5_2905, + &pci_ss_info_10b5_2906, + &pci_ss_info_10b5_2940, + &pci_ss_info_10b5_2977, + &pci_ss_info_10b5_2978, + &pci_ss_info_10b5_2979, + &pci_ss_info_10b5_3025, + &pci_ss_info_10b5_3068, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_0010, + &pci_ss_info_10b7_0020, + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2031, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_2635, + &pci_ss_info_10b8_2802, + &pci_ss_info_10b8_2835, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + &pci_ss_info_10b8_a835, + &pci_ss_info_10b8_b452, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_5451, + &pci_ss_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105e, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_0008, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + &pci_ss_info_10de_006b, + &pci_ss_info_10de_0091, + &pci_ss_info_10de_00a1, + &pci_ss_info_10de_0179, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + &pci_ss_info_10e1_10cf, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + &pci_ss_info_10f1_2466, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + &pci_ss_info_10f7_8338, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fc[] = { + &pci_ss_info_10fc_d003, + &pci_ss_info_10fc_d035, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fd[] = { + &pci_ss_info_10fd_a430, + NULL +}; +#endif +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0007, + &pci_ss_info_1102_0008, + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_0058, + &pci_ss_info_1102_1001, + &pci_ss_info_1102_1002, + &pci_ss_info_1102_1006, + &pci_ss_info_1102_1007, + &pci_ss_info_1102_100a, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_2002, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + &pci_ss_info_1102_8064, + &pci_ss_info_1102_8065, + &pci_ss_info_1102_8067, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0003, + &pci_ss_info_1103_0004, + &pci_ss_info_1103_0005, + &pci_ss_info_1103_0006, + &pci_ss_info_1103_0007, + &pci_ss_info_1103_0008, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105[] = { + &pci_ss_info_1105_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_3059, + &pci_ss_info_1106_3227, + &pci_ss_info_1106_4161, + &pci_ss_info_1106_4511, + NULL +}; +#endif +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0000, + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0021, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_0051, + &pci_ss_info_110a_008b, + &pci_ss_info_110a_5938, + &pci_ss_info_110a_8005, + &pci_ss_info_110a_ffff, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_2242, + &pci_ss_info_1113_4203, + &pci_ss_info_1113_9211, + &pci_ss_info_1113_d301, + &pci_ss_info_1113_ec01, + &pci_ss_info_1113_ee03, + &pci_ss_info_1113_ee08, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131[] = { + &pci_ss_info_1131_2001, + &pci_ss_info_1131_2004, + &pci_ss_info_1131_2005, + &pci_ss_info_1131_2018, + &pci_ss_info_1131_4e85, + &pci_ss_info_1131_4ee9, + &pci_ss_info_1131_4f56, + &pci_ss_info_1131_4f60, + &pci_ss_info_1131_4f61, + &pci_ss_info_1131_5f61, + &pci_ss_info_1131_6752, + &pci_ss_info_1131_7133, + NULL +}; +#endif +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_1300, + &pci_ss_info_1133_1800, + &pci_ss_info_1133_1c01, + &pci_ss_info_1133_1c02, + &pci_ss_info_1133_1c03, + &pci_ss_info_1133_1c04, + &pci_ss_info_1133_1c05, + &pci_ss_info_1133_1c06, + &pci_ss_info_1133_1c07, + &pci_ss_info_1133_1c08, + &pci_ss_info_1133_1c09, + &pci_ss_info_1133_1c0a, + &pci_ss_info_1133_1c0b, + &pci_ss_info_1133_1c0c, + &pci_ss_info_1133_2400, + &pci_ss_info_1133_2800, + &pci_ss_info_1133_e013, + &pci_ss_info_1133_e015, + &pci_ss_info_1133_e017, + &pci_ss_info_1133_e018, + &pci_ss_info_1133_e019, + &pci_ss_info_1133_e01b, + &pci_ss_info_1133_e024, + &pci_ss_info_1133_e028, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_0121, + &pci_ss_info_1148_0221, + &pci_ss_info_1148_0321, + &pci_ss_info_1148_0421, + &pci_ss_info_1148_0621, + &pci_ss_info_1148_0721, + &pci_ss_info_1148_0821, + &pci_ss_info_1148_0921, + &pci_ss_info_1148_1121, + &pci_ss_info_1148_1221, + &pci_ss_info_1148_2100, + &pci_ss_info_1148_21d0, + &pci_ss_info_1148_2200, + &pci_ss_info_1148_3221, + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_8100, + &pci_ss_info_1148_8200, + &pci_ss_info_1148_9100, + &pci_ss_info_1148_9200, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#define pci_ss_list_1154 NULL +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + &pci_ss_info_1179_ff01, + &pci_ss_info_1179_ff10, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c[] = { + &pci_ss_info_117c_8013, + &pci_ss_info_117c_8014, + NULL +}; +#endif +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1303, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_1403, + &pci_ss_info_1186_3202, + &pci_ss_info_1186_3203, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_3700, + &pci_ss_info_1186_3a12, + &pci_ss_info_1186_3a13, + &pci_ss_info_1186_3a14, + &pci_ss_info_1186_3a15, + &pci_ss_info_1186_3a16, + &pci_ss_info_1186_3a17, + &pci_ss_info_1186_3a18, + &pci_ss_info_1186_3a19, + &pci_ss_info_1186_3a22, + &pci_ss_info_1186_3a23, + &pci_ss_info_1186_3a24, + &pci_ss_info_1186_3a63, + &pci_ss_info_1186_3a94, + &pci_ss_info_1186_3b00, + &pci_ss_info_1186_3b01, + &pci_ss_info_1186_3b04, + &pci_ss_info_1186_3b05, + &pci_ss_info_1186_4c00, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#define pci_ss_list_1195 NULL +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab[] = { + &pci_ss_info_11ab_0121, + &pci_ss_info_11ab_0321, + &pci_ss_info_11ab_1021, + &pci_ss_info_11ab_3521, + &pci_ss_info_11ab_3621, + &pci_ss_info_11ab_5021, + &pci_ss_info_11ab_5221, + &pci_ss_info_11ab_5321, + &pci_ss_info_11ab_9521, + NULL +}; +#endif +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_000f, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + &pci_ss_info_11bd_002b, + &pci_ss_info_11bd_002d, + &pci_ss_info_11bd_002e, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + &pci_ss_info_11c1_ab12, + &pci_ss_info_11c1_ab13, + &pci_ss_info_11c1_ab15, + &pci_ss_info_11c1_ab16, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0057, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_1400, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + &pci_ss_info_1244_0f00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_1070, + &pci_ss_info_124b_1170, + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2702, + &pci_ss_info_1259_2703, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2971, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2973, + &pci_ss_info_1259_2974, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2976, + &pci_ss_info_1259_2977, + &pci_ss_info_1259_c104, + &pci_ss_info_1259_c107, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260[] = { + &pci_ss_info_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + &pci_ss_info_1274_8001, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127d[] = { + &pci_ss_info_127d_0000, + NULL +}; +#endif +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283[] = { + &pci_ss_info_1283_0001, + NULL +}; +#endif +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1297[] = { + &pci_ss_info_1297_c160, + &pci_ss_info_1297_c240, + &pci_ss_info_1297_c241, + &pci_ss_info_1297_c242, + &pci_ss_info_1297_c243, + &pci_ss_info_1297_c244, + &pci_ss_info_1297_f641, + NULL +}; +#endif +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ab[] = { + &pci_ss_info_12ab_0000, + &pci_ss_info_12ab_0800, + &pci_ss_info_12ab_5961, + &pci_ss_info_12ab_fff3, + &pci_ss_info_12ab_ffff, + NULL +}; +#endif +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#define pci_ss_list_12c4 NULL +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c7[] = { + &pci_ss_info_12c7_4001, + NULL +}; +#endif +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_0002, + &pci_ss_info_12d9_000a, + &pci_ss_info_12d9_000c, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12df[] = { + &pci_ss_info_12df_4422, + NULL +}; +#endif +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12f8[] = { + &pci_ss_info_12f8_8a02, + NULL +}; +#endif +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317[] = { + &pci_ss_info_1317_8201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319[] = { + &pci_ss_info_1319_1319, + NULL +}; +#endif +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + &pci_ss_info_131f_2050, + &pci_ss_info_131f_2051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#define pci_ss_list_1351 NULL +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_001e, + &pci_ss_info_1371_001f, + &pci_ss_info_1371_0020, + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_4105, + &pci_ss_info_1385_4800, + &pci_ss_info_1385_4d00, + &pci_ss_info_1385_4e00, + &pci_ss_info_1385_f004, + &pci_ss_info_1385_f311, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + &pci_ss_info_1397_3136, + &pci_ss_info_1397_3137, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13b9[] = { + &pci_ss_info_13b9_1421, + NULL +}; +#endif +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13bd[] = { + &pci_ss_info_13bd_100c, + &pci_ss_info_13bd_100d, + &pci_ss_info_13bd_100e, + &pci_ss_info_13bd_1019, + &pci_ss_info_13bd_f6f1, + NULL +}; +#endif +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1[] = { + &pci_ss_info_13c1_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c2[] = { + &pci_ss_info_13c2_0000, + &pci_ss_info_13c2_0001, + &pci_ss_info_13c2_0002, + &pci_ss_info_13c2_0003, + &pci_ss_info_13c2_0004, + &pci_ss_info_13c2_0006, + &pci_ss_info_13c2_0008, + &pci_ss_info_13c2_000a, + &pci_ss_info_13c2_1003, + &pci_ss_info_13c2_1004, + &pci_ss_info_13c2_1005, + &pci_ss_info_13c2_100c, + &pci_ss_info_13c2_100f, + &pci_ss_info_13c2_1011, + &pci_ss_info_13c2_1013, + &pci_ss_info_13c2_1016, + &pci_ss_info_13c2_1102, + NULL +}; +#endif +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + &pci_ss_info_13d1_aba0, + &pci_ss_info_13d1_ac11, + &pci_ss_info_13d1_ac12, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + &pci_ss_info_13e9_1000, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412[] = { + &pci_ss_info_1412_1712, + &pci_ss_info_1412_1724, + &pci_ss_info_1412_3630, + &pci_ss_info_1412_3631, + &pci_ss_info_1412_d630, + &pci_ss_info_1412_d631, + &pci_ss_info_1412_d632, + &pci_ss_info_1412_d633, + &pci_ss_info_1412_d634, + &pci_ss_info_1412_d635, + &pci_ss_info_1412_d637, + &pci_ss_info_1412_d638, + &pci_ss_info_1412_d63b, + &pci_ss_info_1412_d63c, + NULL +}; +#endif +#define pci_ss_list_1413 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1414[] = { + &pci_ss_info_1414_0003, + &pci_ss_info_1414_0004, + NULL +}; +#endif +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_1712, + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1421[] = { + &pci_ss_info_1421_0334, + &pci_ss_info_1421_1370, + NULL +}; +#endif +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1435[] = { + &pci_ss_info_1435_7330, + &pci_ss_info_1435_7350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_1702, + &pci_ss_info_144f_1703, + &pci_ss_info_144f_1707, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + &pci_ss_info_144f_7050, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_0c11, + &pci_ss_info_1458_1000, + &pci_ss_info_1458_1019, + &pci_ss_info_1458_24c2, + &pci_ss_info_1458_24d1, + &pci_ss_info_1458_24d2, + &pci_ss_info_1458_2558, + &pci_ss_info_1458_2560, + &pci_ss_info_1458_2570, + &pci_ss_info_1458_2578, + &pci_ss_info_1458_2580, + &pci_ss_info_1458_2582, + &pci_ss_info_1458_2659, + &pci_ss_info_1458_265a, + &pci_ss_info_1458_266a, + &pci_ss_info_1458_266f, + &pci_ss_info_1458_3124, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_4018, + &pci_ss_info_1458_4019, + &pci_ss_info_1458_4024, + &pci_ss_info_1458_4025, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_5006, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + &pci_ss_info_1458_b001, + &pci_ss_info_1458_b003, + &pci_ss_info_1458_d000, + &pci_ss_info_1458_e000, + &pci_ss_info_1458_e381, + &pci_ss_info_1458_e911, + &pci_ss_info_1458_e931, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0002, + &pci_ss_info_1461_0003, + &pci_ss_info_1461_0004, + &pci_ss_info_1461_000a, + &pci_ss_info_1461_000b, + &pci_ss_info_1461_050c, + &pci_ss_info_1461_0761, + &pci_ss_info_1461_1044, + &pci_ss_info_1461_10ff, + &pci_ss_info_1461_2108, + &pci_ss_info_1461_2115, + &pci_ss_info_1461_8011, + &pci_ss_info_1461_9715, + &pci_ss_info_1461_a3ce, + &pci_ss_info_1461_a3cf, + &pci_ss_info_1461_a70a, + &pci_ss_info_1461_a70b, + &pci_ss_info_1461_d6ee, + &pci_ss_info_1461_f31f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_0080, + &pci_ss_info_1462_0402, + &pci_ss_info_1462_0403, + &pci_ss_info_1462_052c, + &pci_ss_info_1462_058c, + &pci_ss_info_1462_1009, + &pci_ss_info_1462_3091, + &pci_ss_info_1462_309e, + &pci_ss_info_1462_3300, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3800, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5470, + &pci_ss_info_1462_5506, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6231, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6828, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6835, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_7020, + &pci_ss_info_1462_7028, + &pci_ss_info_1462_702c, + &pci_ss_info_1462_702d, + &pci_ss_info_1462_702e, + &pci_ss_info_1462_7100, + &pci_ss_info_1462_7280, + &pci_ss_info_1462_728c, + &pci_ss_info_1462_7580, + &pci_ss_info_1462_758c, + &pci_ss_info_1462_788c, + &pci_ss_info_1462_8606, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + &pci_ss_info_1462_8852, + &pci_ss_info_1462_8880, + &pci_ss_info_1462_8900, + &pci_ss_info_1462_9171, + &pci_ss_info_1462_932c, + &pci_ss_info_1462_9350, + &pci_ss_info_1462_9360, + &pci_ss_info_1462_971d, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0202, + &pci_ss_info_1468_0311, + &pci_ss_info_1468_0312, + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_0450, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1471[] = { + &pci_ss_info_1471_b7e9, + NULL +}; +#endif +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_1406, + &pci_ss_info_147b_1407, + &pci_ss_info_147b_1408, + &pci_ss_info_147b_1c09, + &pci_ss_info_147b_1c0b, + &pci_ss_info_147b_6191, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_8f0d, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_0214, + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + &pci_ss_info_148c_2064, + &pci_ss_info_148c_2066, + &pci_ss_info_148c_2067, + &pci_ss_info_148c_2073, + &pci_ss_info_148c_2116, + &pci_ss_info_148c_2117, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1498[] = { + &pci_ss_info_1498_0362, + NULL +}; +#endif +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14b7[] = { + &pci_ss_info_14b7_0a60, + NULL +}; +#endif +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + &pci_ss_info_14c0_0012, + &pci_ss_info_14c0_1212, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c2[] = { + &pci_ss_info_14c2_0105, + &pci_ss_info_14c2_0205, + NULL +}; +#endif +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c7[] = { + &pci_ss_info_14c7_0107, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cb[] = { + &pci_ss_info_14cb_0100, + &pci_ss_info_14cb_0200, + NULL +}; +#endif +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2012, + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_0449, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_4318, + &pci_ss_info_14e4_4320, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ef[] = { + &pci_ss_info_14ef_0220, + NULL +}; +#endif +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0187, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0342, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_2045, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fb[] = { + &pci_ss_info_14fb_0101, + &pci_ss_info_14fb_0102, + &pci_ss_info_14fb_0202, + &pci_ss_info_14fb_0611, + &pci_ss_info_14fb_0612, + &pci_ss_info_14fb_0613, + &pci_ss_info_14fb_0614, + &pci_ss_info_14fb_0621, + &pci_ss_info_14fb_0622, + &pci_ss_info_14fb_0810, + NULL +}; +#endif +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_0e70, + &pci_ss_info_14ff_1100, + &pci_ss_info_14ff_c401, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_1930, + &pci_ss_info_1509_1968, + &pci_ss_info_1509_2990, + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#define pci_ss_list_1517 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1518[] = { + &pci_ss_info_1518_0200, + NULL +}; +#endif +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + &pci_ss_info_1522_0c00, + &pci_ss_info_1522_0d00, + &pci_ss_info_1522_1d00, + &pci_ss_info_1522_2000, + &pci_ss_info_1522_2100, + &pci_ss_info_1522_2200, + &pci_ss_info_1522_2300, + &pci_ss_info_1522_2400, + &pci_ss_info_1522_2500, + &pci_ss_info_1522_2600, + &pci_ss_info_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_153b[] = { + &pci_ss_info_153b_1115, + &pci_ss_info_153b_111b, + &pci_ss_info_153b_1125, + &pci_ss_info_153b_112b, + &pci_ss_info_153b_112c, + &pci_ss_info_153b_1130, + &pci_ss_info_153b_1136, + &pci_ss_info_153b_1138, + &pci_ss_info_153b_1142, + &pci_ss_info_153b_1143, + &pci_ss_info_153b_1145, + &pci_ss_info_153b_1147, + &pci_ss_info_153b_1151, + &pci_ss_info_153b_1152, + &pci_ss_info_153b_1153, + &pci_ss_info_153b_1158, + &pci_ss_info_153b_1160, + &pci_ss_info_153b_1162, + &pci_ss_info_153b_1166, + NULL +}; +#endif +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1540[] = { + &pci_ss_info_1540_2580, + &pci_ss_info_1540_9524, + NULL +}; +#endif +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + &pci_ss_info_1554_4811, + &pci_ss_info_1554_4813, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_04a0, + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_002d, + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_156d[] = { + &pci_ss_info_156d_b400, + &pci_ss_info_156d_b550, + &pci_ss_info_156d_b560, + &pci_ss_info_156d_b700, + &pci_ss_info_156d_b795, + &pci_ss_info_156d_b797, + NULL +}; +#endif +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +static const pciSubsystemInfo *pci_ss_list_15ad[] = { + &pci_ss_info_15ad_1976, + NULL +}; +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15bd[] = { + &pci_ss_info_15bd_1001, + &pci_ss_info_15bd_1003, + NULL +}; +#endif +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d4[] = { + &pci_ss_info_15d4_0047, + NULL +}; +#endif +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_4580, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#define pci_ss_list_1601 NULL +#define pci_ss_list_1602 NULL +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#define pci_ss_list_1612 NULL +#define pci_ss_list_1619 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_161f[] = { + &pci_ss_info_161f_2029, + &pci_ss_info_161f_203c, + &pci_ss_info_161f_203d, + &pci_ss_info_161f_3017, + NULL +}; +#endif +#define pci_ss_list_1626 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1637 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_165f NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#define pci_ss_list_166d NULL +#define pci_ss_list_1677 NULL +#define pci_ss_list_167b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0002, + &pci_ss_info_1681_0003, + &pci_ss_info_1681_0010, + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a000, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1682[] = { + &pci_ss_info_1682_2109, + &pci_ss_info_1682_211c, + &pci_ss_info_1682_2120, + NULL +}; +#endif +#define pci_ss_list_1688 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c[] = { + &pci_ss_info_168c_0013, + &pci_ss_info_168c_1025, + &pci_ss_info_168c_1027, + &pci_ss_info_168c_1052, + &pci_ss_info_168c_2026, + &pci_ss_info_168c_2041, + &pci_ss_info_168c_2042, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1695[] = { + &pci_ss_info_1695_3005, + &pci_ss_info_1695_300c, + &pci_ss_info_1695_9025, + &pci_ss_info_1695_9029, + NULL +}; +#endif +#define pci_ss_list_169c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16a5[] = { + &pci_ss_info_16a5_1601, + &pci_ss_info_16a5_1605, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ab[] = { + &pci_ss_info_16ab_7302, + &pci_ss_info_16ab_8501, + NULL +}; +#endif +#define pci_ss_list_16ae NULL +#define pci_ss_list_16af NULL +#define pci_ss_list_16b4 NULL +#define pci_ss_list_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_0003, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16c8 NULL +#define pci_ss_list_16c9 NULL +#define pci_ss_list_16ca NULL +#define pci_ss_list_16cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ce[] = { + &pci_ss_info_16ce_1040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16df[] = { + &pci_ss_info_16df_0011, + &pci_ss_info_16df_0012, + &pci_ss_info_16df_0013, + &pci_ss_info_16df_0014, + &pci_ss_info_16df_0015, + &pci_ss_info_16df_0016, + NULL +}; +#endif +#define pci_ss_list_16e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ec[] = { + &pci_ss_info_16ec_0119, + NULL +}; +#endif +#define pci_ss_list_16ed NULL +#define pci_ss_list_16f3 NULL +#define pci_ss_list_16f4 NULL +#define pci_ss_list_16f6 NULL +#define pci_ss_list_1702 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#define pci_ss_list_1725 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1734[] = { + &pci_ss_info_1734_007a, + &pci_ss_info_1734_100b, + &pci_ss_info_1734_1012, + &pci_ss_info_1734_101c, + &pci_ss_info_1734_1025, + &pci_ss_info_1734_103e, + &pci_ss_info_1734_1052, + &pci_ss_info_1734_1055, + &pci_ss_info_1734_105a, + &pci_ss_info_1734_105b, + &pci_ss_info_1734_105c, + &pci_ss_info_1734_105d, + &pci_ss_info_1734_1061, + &pci_ss_info_1734_1065, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_0015, + &pci_ss_info_1737_0016, + &pci_ss_info_1737_0024, + &pci_ss_info_1737_0032, + &pci_ss_info_1737_3874, + &pci_ss_info_1737_4320, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#define pci_ss_list_1749 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7146, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + &pci_ss_info_174b_7c12, + &pci_ss_info_174b_7c13, + &pci_ss_info_174b_7c19, + &pci_ss_info_174b_7c28, + &pci_ss_info_174b_7c29, + NULL +}; +#endif +#define pci_ss_list_174d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_175c[] = { + &pci_ss_info_175c_4200, + &pci_ss_info_175c_4300, + &pci_ss_info_175c_4400, + &pci_ss_info_175c_5000, + &pci_ss_info_175c_5100, + &pci_ss_info_175c_6100, + &pci_ss_info_175c_6200, + &pci_ss_info_175c_6400, + &pci_ss_info_175c_8700, + &pci_ss_info_175c_8800, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#define pci_ss_list_1775 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + &pci_ss_info_1787_4002, + &pci_ss_info_1787_4003, + &pci_ss_info_1787_5964, + &pci_ss_info_1787_5965, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#define pci_ss_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + &pci_ss_info_1799_5000, + &pci_ss_info_1799_7001, + &pci_ss_info_1799_700a, + &pci_ss_info_1799_7010, + &pci_ss_info_1799_701a, + NULL +}; +#endif +#define pci_ss_list_179c NULL +#define pci_ss_list_17a0 NULL +#define pci_ss_list_17aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + &pci_ss_info_17af_200c, + &pci_ss_info_17af_200d, + &pci_ss_info_17af_2012, + &pci_ss_info_17af_2013, + NULL +}; +#endif +#define pci_ss_list_17b3 NULL +#define pci_ss_list_17b4 NULL +#define pci_ss_list_17c0 NULL +#define pci_ss_list_17c2 NULL +#define pci_ss_list_17cb NULL +#define pci_ss_list_17cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17cf[] = { + &pci_ss_info_17cf_0014, + &pci_ss_info_17cf_0020, + &pci_ss_info_17cf_0037, + NULL +}; +#endif +#define pci_ss_list_17d3 NULL +#define pci_ss_list_17d5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17de[] = { + &pci_ss_info_17de_08a1, + &pci_ss_info_17de_08a6, + &pci_ss_info_17de_08b2, + &pci_ss_info_17de_a8a6, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ee[] = { + &pci_ss_info_17ee_2002, + &pci_ss_info_17ee_2003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17f2[] = { + &pci_ss_info_17f2_1c03, + &pci_ss_info_17f2_2c08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe[] = { + &pci_ss_info_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ff[] = { + &pci_ss_info_17ff_0585, + NULL +}; +#endif +#define pci_ss_list_1813 NULL +#define pci_ss_list_1814 NULL +#define pci_ss_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1822[] = { + &pci_ss_info_1822_0001, + &pci_ss_info_1822_0025, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_182d[] = { + &pci_ss_info_182d_201d, + NULL +}; +#endif +#define pci_ss_list_1830 NULL +#define pci_ss_list_183b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1849[] = { + &pci_ss_info_1849_0571, + &pci_ss_info_1849_3038, + &pci_ss_info_1849_3065, + &pci_ss_info_1849_3099, + &pci_ss_info_1849_3104, + &pci_ss_info_1849_3149, + &pci_ss_info_1849_3177, + &pci_ss_info_1849_3189, + &pci_ss_info_1849_3227, + &pci_ss_info_1849_8052, + &pci_ss_info_1849_8053, + &pci_ss_info_1849_9761, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1854[] = { + &pci_ss_info_1854_000b, + &pci_ss_info_1854_000c, + &pci_ss_info_1854_000d, + &pci_ss_info_1854_000e, + &pci_ss_info_1854_000f, + &pci_ss_info_1854_0010, + &pci_ss_info_1854_0011, + &pci_ss_info_1854_0012, + &pci_ss_info_1854_0013, + &pci_ss_info_1854_0014, + &pci_ss_info_1854_0015, + &pci_ss_info_1854_0016, + &pci_ss_info_1854_0017, + &pci_ss_info_1854_0018, + &pci_ss_info_1854_0019, + &pci_ss_info_1854_001a, + &pci_ss_info_1854_001b, + &pci_ss_info_1854_001c, + &pci_ss_info_1854_001d, + &pci_ss_info_1854_001e, + &pci_ss_info_1854_001f, + &pci_ss_info_1854_0020, + &pci_ss_info_1854_0021, + &pci_ss_info_1854_0022, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185b[] = { + &pci_ss_info_185b_c100, + &pci_ss_info_185b_c200, + &pci_ss_info_185b_c900, + &pci_ss_info_185b_c901, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185f[] = { + &pci_ss_info_185f_1220, + &pci_ss_info_185f_22a0, + NULL +}; +#endif +#define pci_ss_list_1864 NULL +#define pci_ss_list_1867 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_187e[] = { + &pci_ss_info_187e_3406, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#define pci_ss_list_1890 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1894[] = { + &pci_ss_info_1894_a006, + &pci_ss_info_1894_fe01, + NULL +}; +#endif +#define pci_ss_list_1896 NULL +#define pci_ss_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ac[] = { + &pci_ss_info_18ac_d500, + &pci_ss_info_18ac_d810, + &pci_ss_info_18ac_d820, + &pci_ss_info_18ac_db00, + &pci_ss_info_18ac_db10, + &pci_ss_info_18ac_db11, + &pci_ss_info_18ac_db50, + NULL +}; +#endif +#define pci_ss_list_18b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18bc[] = { + &pci_ss_info_18bc_0050, + &pci_ss_info_18bc_0051, + &pci_ss_info_18bc_0053, + &pci_ss_info_18bc_0100, + &pci_ss_info_18bc_0101, + &pci_ss_info_18bc_0170, + &pci_ss_info_18bc_0171, + &pci_ss_info_18bc_0172, + &pci_ss_info_18bc_0173, + NULL +}; +#endif +#define pci_ss_list_18c8 NULL +#define pci_ss_list_18c9 NULL +#define pci_ss_list_18ca NULL +#define pci_ss_list_18d2 NULL +#define pci_ss_list_18dd NULL +#define pci_ss_list_18e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec[] = { + &pci_ss_info_18ec_d001, + &pci_ss_info_18ec_d002, + &pci_ss_info_18ec_d003, + &pci_ss_info_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18fb[] = { + &pci_ss_info_18fb_7872, + NULL +}; +#endif +#define pci_ss_list_1923 NULL +#define pci_ss_list_1924 NULL +#define pci_ss_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1931[] = { + &pci_ss_info_1931_000a, + &pci_ss_info_1931_000b, + NULL +}; +#endif +#define pci_ss_list_1942 NULL +#define pci_ss_list_1957 NULL +#define pci_ss_list_1958 NULL +#define pci_ss_list_1966 NULL +#define pci_ss_list_196a NULL +#define pci_ss_list_197b NULL +#define pci_ss_list_1989 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1993[] = { + &pci_ss_info_1993_0ded, + &pci_ss_info_1993_0dee, + &pci_ss_info_1993_0def, + NULL +}; +#endif +#define pci_ss_list_19a8 NULL +#define pci_ss_list_19ac NULL +#define pci_ss_list_19ae NULL +#define pci_ss_list_19d4 NULL +#define pci_ss_list_19e2 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3906, + &pci_ss_info_1de1_3907, + &pci_ss_info_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_1fc0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1fc1[] = { + &pci_ss_info_1fc1_0026, + &pci_ss_info_1fc1_0027, + NULL +}; +#endif +#define pci_ss_list_1fce NULL +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_2801, + &pci_ss_info_270f_2803, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + &pci_ss_info_270f_f641, + &pci_ss_info_270f_f645, + &pci_ss_info_270f_fc00, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_3842 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_144f, + &pci_ss_info_4005_4000, + &pci_ss_info_4005_4710, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_4144 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4321 NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_494f NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53[] = { + &pci_ss_info_4c53_1000, + &pci_ss_info_4c53_1010, + &pci_ss_info_4c53_1020, + &pci_ss_info_4c53_1030, + &pci_ss_info_4c53_1040, + &pci_ss_info_4c53_1050, + &pci_ss_info_4c53_1051, + &pci_ss_info_4c53_1060, + &pci_ss_info_4c53_1070, + &pci_ss_info_4c53_1080, + &pci_ss_info_4c53_1090, + &pci_ss_info_4c53_10a0, + &pci_ss_info_4c53_10b0, + &pci_ss_info_4c53_10d0, + &pci_ss_info_4c53_10e0, + &pci_ss_info_4c53_1300, + &pci_ss_info_4c53_1310, + &pci_ss_info_4c53_3000, + &pci_ss_info_4c53_3001, + &pci_ss_info_4c53_3002, + &pci_ss_info_4c53_3010, + &pci_ss_info_4c53_3011, + &pci_ss_info_4c53_4000, + NULL +}; +#endif +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5168[] = { + &pci_ss_info_5168_0138, + &pci_ss_info_5168_0306, + &pci_ss_info_5168_0319, + NULL +}; +#endif +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_2036, + &pci_ss_info_5654_3132, + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_5851 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_7063[] = { + &pci_ss_info_7063_3000, + NULL +}; +#endif +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_807d[] = { + &pci_ss_info_807d_0035, + &pci_ss_info_807d_1043, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_0075, + &pci_ss_info_8086_0076, + &pci_ss_info_8086_0077, + &pci_ss_info_8086_0079, + &pci_ss_info_8086_007b, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_01af, + &pci_ss_info_8086_01c1, + &pci_ss_info_8086_01f7, + &pci_ss_info_8086_0520, + &pci_ss_info_8086_0523, + &pci_ss_info_8086_0530, + &pci_ss_info_8086_0532, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1016, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1018, + &pci_ss_info_8086_1019, + &pci_ss_info_8086_101a, + &pci_ss_info_8086_101e, + &pci_ss_info_8086_1026, + &pci_ss_info_8086_1027, + &pci_ss_info_8086_1028, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_1075, + &pci_ss_info_8086_1076, + &pci_ss_info_8086_1077, + &pci_ss_info_8086_1078, + &pci_ss_info_8086_1079, + &pci_ss_info_8086_107a, + &pci_ss_info_8086_107b, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_110d, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1113, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_1176, + &pci_ss_info_8086_1179, + &pci_ss_info_8086_117a, + &pci_ss_info_8086_1276, + &pci_ss_info_8086_127a, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1376, + &pci_ss_info_8086_1476, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_24db, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_2527, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_301f, + &pci_ss_info_8086_3020, + &pci_ss_info_8086_302f, + &pci_ss_info_8086_3063, + &pci_ss_info_8086_308d, + &pci_ss_info_8086_3108, + &pci_ss_info_8086_3411, + &pci_ss_info_8086_3424, + &pci_ss_info_8086_3427, + &pci_ss_info_8086_3431, + &pci_ss_info_8086_3439, + &pci_ss_info_8086_3499, + &pci_ss_info_8086_4147, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4246, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4532, + &pci_ss_info_8086_4541, + &pci_ss_info_8086_4557, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_524c, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_544e, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + &pci_ss_info_8086_a000, + &pci_ss_info_8086_a01f, + &pci_ss_info_8086_a11f, + &pci_ss_info_8086_e000, + &pci_ss_info_8086_e001, + NULL +}; +#define pci_ss_list_8401 NULL +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8912 NULL +#define pci_ss_list_8c4a NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0095_0680 = { + 0x0680, pci_device_0095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0095_0680, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_018a_0106 = { + 0x0106, pci_device_018a_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_018a_0106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_021b_8139 = { + 0x8139, pci_device_021b_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_021b_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0291_8212 = { + 0x8212, pci_device_0291_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0291_8212, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_02ac_1012 = { + 0x1012, pci_device_02ac_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_02ac_1012, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0357_000a = { + 0x000a, pci_device_0357_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0357_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0432_0001 = { + 0x0001, pci_device_0432_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0432_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_045e_006e = { + 0x006e, pci_device_045e_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_045e_00c2 = { + 0x00c2, pci_device_045e_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_00c2, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_04cf_8818 = { + 0x8818, pci_device_04cf_8818, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_04cf_8818, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_050d_7050 = { + 0x7050, pci_device_050d_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_050d_7050, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05e3_0701 = { + 0x0701, pci_device_05e3_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05e3_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1703 = { + 0x1703, pci_device_0675_1703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1703, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1704 = { + 0x1704, pci_device_0675_1704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_067b_3507 = { + 0x3507, pci_device_067b_3507, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_3507, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b49_064f = { + 0x064f, pci_device_0b49_064f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b49_064f, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0046 = { + 0x0046, pci_device_0e11_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_005a = { + 0x005a, pci_device_0e11_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007c = { + 0x007c, pci_device_0e11_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007d = { + 0x007d, pci_device_0e11_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0085 = { + 0x0085, pci_device_0e11_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00b1 = { + 0x00b1, pci_device_0e11_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00bb = { + 0x00bb, pci_device_0e11_00bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00ca = { + 0x00ca, pci_device_0e11_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cb = { + 0x00cb, pci_device_0e11_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cf = { + 0x00cf, pci_device_0e11_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d0 = { + 0x00d0, pci_device_0e11_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d1 = { + 0x00d1, pci_device_0e11_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00e3 = { + 0x00e3, pci_device_0e11_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4030 = { + 0x4030, pci_device_0e11_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4031 = { + 0x4031, pci_device_0e11_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4032 = { + 0x4032, pci_device_0e11_4032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4033 = { + 0x4033, pci_device_0e11_4033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4034 = { + 0x4034, pci_device_0e11_4034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4040 = { + 0x4040, pci_device_0e11_4040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4048 = { + 0x4048, pci_device_0e11_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4050 = { + 0x4050, pci_device_0e11_4050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4051 = { + 0x4051, pci_device_0e11_4051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4058 = { + 0x4058, pci_device_0e11_4058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4070 = { + 0x4070, pci_device_0e11_4070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4080 = { + 0x4080, pci_device_0e11_4080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4082 = { + 0x4082, pci_device_0e11_4082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4083 = { + 0x4083, pci_device_0e11_4083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4091 = { + 0x4091, pci_device_0e11_4091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409a = { + 0x409a, pci_device_0e11_409a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409b = { + 0x409b, pci_device_0e11_409b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409c = { + 0x409c, pci_device_0e11_409c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409d = { + 0x409d, pci_device_0e11_409d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b200 = { + 0xb200, pci_device_0e11_b200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b203 = { + 0xb203, pci_device_0e11_b203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b204 = { + 0xb204, pci_device_0e11_b204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0031 = { + 0x0031, pci_device_1000_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0032 = { + 0x0032, pci_device_1000_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0033 = { + 0x0033, pci_device_1000_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0041 = { + 0x0041, pci_device_1000_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0050 = { + 0x0050, pci_device_1000_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0054 = { + 0x0054, pci_device_1000_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0056 = { + 0x0056, pci_device_1000_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0058 = { + 0x0058, pci_device_1000_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005a = { + 0x005a, pci_device_1000_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005c = { + 0x005c, pci_device_1000_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005e = { + 0x005e, pci_device_1000_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0060 = { + 0x0060, pci_device_1000_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0062 = { + 0x0062, pci_device_1000_0062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0407 = { + 0x0407, pci_device_1000_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0408 = { + 0x0408, pci_device_1000_0408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0409 = { + 0x0409, pci_device_1000_0409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0640 = { + 0x0640, pci_device_1000_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0642 = { + 0x0642, pci_device_1000_0642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0646 = { + 0x0646, pci_device_1000_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0804 = { + 0x0804, pci_device_1000_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0805 = { + 0x0805, pci_device_1000_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0806 = { + 0x0806, pci_device_1000_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0807 = { + 0x0807, pci_device_1000_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_3150 = { + 0x3150, pci_device_1002_3150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3152 = { + 0x3152, pci_device_1002_3152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3154 = { + 0x3154, pci_device_1002_3154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e50 = { + 0x3e50, pci_device_1002_3e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e54 = { + 0x3e54, pci_device_1002_3e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e70 = { + 0x3e70, pci_device_1002_3e70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4136 = { + 0x4136, pci_device_1002_4136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4137 = { + 0x4137, pci_device_1002_4137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4148 = { + 0x4148, pci_device_1002_4148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4149 = { + 0x4149, pci_device_1002_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414a = { + 0x414a, pci_device_1002_414a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414b = { + 0x414b, pci_device_1002_414b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4150 = { + 0x4150, pci_device_1002_4150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4151 = { + 0x4151, pci_device_1002_4151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4152 = { + 0x4152, pci_device_1002_4152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4153 = { + 0x4153, pci_device_1002_4153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4154 = { + 0x4154, pci_device_1002_4154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4155 = { + 0x4155, pci_device_1002_4155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4156 = { + 0x4156, pci_device_1002_4156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4157 = { + 0x4157, pci_device_1002_4157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4164 = { + 0x4164, pci_device_1002_4164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4165 = { + 0x4165, pci_device_1002_4165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4166 = { + 0x4166, pci_device_1002_4166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4168 = { + 0x4168, pci_device_1002_4168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4170 = { + 0x4170, pci_device_1002_4170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4171 = { + 0x4171, pci_device_1002_4171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4172 = { + 0x4172, pci_device_1002_4172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4173 = { + 0x4173, pci_device_1002_4173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4237 = { + 0x4237, pci_device_1002_4237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4243 = { + 0x4243, pci_device_1002_4243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4341 = { + 0x4341, pci_device_1002_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4345 = { + 0x4345, pci_device_1002_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4347 = { + 0x4347, pci_device_1002_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4348 = { + 0x4348, pci_device_1002_4348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4349 = { + 0x4349, pci_device_1002_4349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_434d = { + 0x434d, pci_device_1002_434d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_434d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4353 = { + 0x4353, pci_device_1002_4353, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4353, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4363 = { + 0x4363, pci_device_1002_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_436e = { + 0x436e, pci_device_1002_436e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_436e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4370 = { + 0x4370, pci_device_1002_4370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4371 = { + 0x4371, pci_device_1002_4371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4372 = { + 0x4372, pci_device_1002_4372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4373 = { + 0x4373, pci_device_1002_4373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4374 = { + 0x4374, pci_device_1002_4374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4375 = { + 0x4375, pci_device_1002_4375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4376 = { + 0x4376, pci_device_1002_4376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4377 = { + 0x4377, pci_device_1002_4377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4378 = { + 0x4378, pci_device_1002_4378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4379 = { + 0x4379, pci_device_1002_4379, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4379, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437a = { + 0x437a, pci_device_1002_437a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4437 = { + 0x4437, pci_device_1002_4437, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4437, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a48 = { + 0x4a48, pci_device_1002_4a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a49 = { + 0x4a49, pci_device_1002_4a49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4a = { + 0x4a4a, pci_device_1002_4a4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4b = { + 0x4a4b, pci_device_1002_4a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4c = { + 0x4a4c, pci_device_1002_4a4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4d = { + 0x4a4d, pci_device_1002_4a4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4e = { + 0x4a4e, pci_device_1002_4a4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a50 = { + 0x4a50, pci_device_1002_4a50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a70 = { + 0x4a70, pci_device_1002_4a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b49 = { + 0x4b49, pci_device_1002_4b49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4b = { + 0x4b4b, pci_device_1002_4b4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4c = { + 0x4b4c, pci_device_1002_4b4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b69 = { + 0x4b69, pci_device_1002_4b69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6b = { + 0x4b6b, pci_device_1002_4b6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6c = { + 0x4b6c, pci_device_1002_4b6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c6e = { + 0x4c6e, pci_device_1002_4c6e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c6e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e48 = { + 0x4e48, pci_device_1002_4e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e49 = { + 0x4e49, pci_device_1002_4e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4a = { + 0x4e4a, pci_device_1002_4e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4b = { + 0x4e4b, pci_device_1002_4e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e50 = { + 0x4e50, pci_device_1002_4e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e51 = { + 0x4e51, pci_device_1002_4e51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e52 = { + 0x4e52, pci_device_1002_4e52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e53 = { + 0x4e53, pci_device_1002_4e53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e54 = { + 0x4e54, pci_device_1002_4e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e56 = { + 0x4e56, pci_device_1002_4e56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e68 = { + 0x4e68, pci_device_1002_4e68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e69 = { + 0x4e69, pci_device_1002_4e69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e6a = { + 0x4e6a, pci_device_1002_4e6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e71 = { + 0x4e71, pci_device_1002_4e71, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e71, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5154 = { + 0x5154, pci_device_1002_5154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5155 = { + 0x5155, pci_device_1002_5155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515e = { + 0x515e, pci_device_1002_515e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5460 = { + 0x5460, pci_device_1002_5460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5462 = { + 0x5462, pci_device_1002_5462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5464 = { + 0x5464, pci_device_1002_5464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5548 = { + 0x5548, pci_device_1002_5548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5549 = { + 0x5549, pci_device_1002_5549, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5549, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554a = { + 0x554a, pci_device_1002_554a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554b = { + 0x554b, pci_device_1002_554b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554d = { + 0x554d, pci_device_1002_554d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554f = { + 0x554f, pci_device_1002_554f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5550 = { + 0x5550, pci_device_1002_5550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5551 = { + 0x5551, pci_device_1002_5551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5552 = { + 0x5552, pci_device_1002_5552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5554 = { + 0x5554, pci_device_1002_5554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556b = { + 0x556b, pci_device_1002_556b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556d = { + 0x556d, pci_device_1002_556d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556f = { + 0x556f, pci_device_1002_556f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564a = { + 0x564a, pci_device_1002_564a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564b = { + 0x564b, pci_device_1002_564b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5652 = { + 0x5652, pci_device_1002_5652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5653 = { + 0x5653, pci_device_1002_5653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5830 = { + 0x5830, pci_device_1002_5830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5831 = { + 0x5831, pci_device_1002_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5832 = { + 0x5832, pci_device_1002_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5833 = { + 0x5833, pci_device_1002_5833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5834 = { + 0x5834, pci_device_1002_5834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5835 = { + 0x5835, pci_device_1002_5835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5838 = { + 0x5838, pci_device_1002_5838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5940 = { + 0x5940, pci_device_1002_5940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5941 = { + 0x5941, pci_device_1002_5941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5944 = { + 0x5944, pci_device_1002_5944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5950 = { + 0x5950, pci_device_1002_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5951 = { + 0x5951, pci_device_1002_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5954 = { + 0x5954, pci_device_1002_5954, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5954, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5955 = { + 0x5955, pci_device_1002_5955, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5955, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5960 = { + 0x5960, pci_device_1002_5960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5961 = { + 0x5961, pci_device_1002_5961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5962 = { + 0x5962, pci_device_1002_5962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5964 = { + 0x5964, pci_device_1002_5964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5969 = { + 0x5969, pci_device_1002_5969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5974 = { + 0x5974, pci_device_1002_5974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5975 = { + 0x5975, pci_device_1002_5975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a34 = { + 0x5a34, pci_device_1002_5a34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a38 = { + 0x5a38, pci_device_1002_5a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a3f = { + 0x5a3f, pci_device_1002_5a3f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a3f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a41 = { + 0x5a41, pci_device_1002_5a41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a42 = { + 0x5a42, pci_device_1002_5a42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a61 = { + 0x5a61, pci_device_1002_5a61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a62 = { + 0x5a62, pci_device_1002_5a62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b60 = { + 0x5b60, pci_device_1002_5b60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b62 = { + 0x5b62, pci_device_1002_5b62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b63 = { + 0x5b63, pci_device_1002_5b63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b64 = { + 0x5b64, pci_device_1002_5b64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b65 = { + 0x5b65, pci_device_1002_5b65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b70 = { + 0x5b70, pci_device_1002_5b70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b72 = { + 0x5b72, pci_device_1002_5b72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b73 = { + 0x5b73, pci_device_1002_5b73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b74 = { + 0x5b74, pci_device_1002_5b74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c61 = { + 0x5c61, pci_device_1002_5c61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c63 = { + 0x5c63, pci_device_1002_5c63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d44 = { + 0x5d44, pci_device_1002_5d44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d48 = { + 0x5d48, pci_device_1002_5d48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d49 = { + 0x5d49, pci_device_1002_5d49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4a = { + 0x5d4a, pci_device_1002_5d4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4d = { + 0x5d4d, pci_device_1002_5d4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4f = { + 0x5d4f, pci_device_1002_5d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d52 = { + 0x5d52, pci_device_1002_5d52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d57 = { + 0x5d57, pci_device_1002_5d57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6d = { + 0x5d6d, pci_device_1002_5d6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6f = { + 0x5d6f, pci_device_1002_5d6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d72 = { + 0x5d72, pci_device_1002_5d72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d77 = { + 0x5d77, pci_device_1002_5d77, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d77, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e48 = { + 0x5e48, pci_device_1002_5e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e49 = { + 0x5e49, pci_device_1002_5e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4a = { + 0x5e4a, pci_device_1002_5e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4b = { + 0x5e4b, pci_device_1002_5e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4c = { + 0x5e4c, pci_device_1002_5e4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4d = { + 0x5e4d, pci_device_1002_5e4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4f = { + 0x5e4f, pci_device_1002_5e4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6b = { + 0x5e6b, pci_device_1002_5e6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6d = { + 0x5e6d, pci_device_1002_5e6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7010 = { + 0x7010, pci_device_1002_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7100 = { + 0x7100, pci_device_1002_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7105 = { + 0x7105, pci_device_1002_7105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7109 = { + 0x7109, pci_device_1002_7109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7120 = { + 0x7120, pci_device_1002_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7129 = { + 0x7129, pci_device_1002_7129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7142 = { + 0x7142, pci_device_1002_7142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7146 = { + 0x7146, pci_device_1002_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7162 = { + 0x7162, pci_device_1002_7162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7166 = { + 0x7166, pci_device_1002_7166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c0 = { + 0x71c0, pci_device_1002_71c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c2 = { + 0x71c2, pci_device_1002_71c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e0 = { + 0x71e0, pci_device_1002_71e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e2 = { + 0x71e2, pci_device_1002_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7833 = { + 0x7833, pci_device_1002_7833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7834 = { + 0x7834, pci_device_1002_7834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7835 = { + 0x7835, pci_device_1002_7835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7838 = { + 0x7838, pci_device_1002_7838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7c37 = { + 0x7c37, pci_device_1002_7c37, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7c37, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab0 = { + 0xcab0, pci_device_1002_cab0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab2 = { + 0xcab2, pci_device_1002_cab2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab3 = { + 0xcab3, pci_device_1002_cab3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cbb2 = { + 0xcbb2, pci_device_1002_cbb2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cbb2, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0021 = { + 0x0021, pci_device_100b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0028 = { + 0x0028, pci_device_100b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002a = { + 0x002a, pci_device_100b_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002b = { + 0x002b, pci_device_100b_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002d = { + 0x002d, pci_device_100b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002e = { + 0x002e, pci_device_100b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002f = { + 0x002f, pci_device_100b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0030 = { + 0x0030, pci_device_100b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0035 = { + 0x0035, pci_device_100b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0510 = { + 0x0510, pci_device_100b_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0511 = { + 0x0511, pci_device_100b_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0515 = { + 0x0515, pci_device_100b_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0017 = { + 0x0017, pci_device_1011_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4000 = { + 0x4000, pci_device_1013_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0031 = { + 0x0031, pci_device_1014_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0037 = { + 0x0037, pci_device_1014_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003c = { + 0x003c, pci_device_1014_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0054 = { + 0x0054, pci_device_1014_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005e = { + 0x005e, pci_device_1014_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008b = { + 0x008b, pci_device_1014_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008e = { + 0x008e, pci_device_1014_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0091 = { + 0x0091, pci_device_1014_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_009f = { + 0x009f, pci_device_1014_009f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_009f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b8 = { + 0x00b8, pci_device_1014_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0104 = { + 0x0104, pci_device_1014_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_015e = { + 0x015e, pci_device_1014_015e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_015e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0160 = { + 0x0160, pci_device_1014_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_016e = { + 0x016e, pci_device_1014_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0170 = { + 0x0170, pci_device_1014_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_017d = { + 0x017d, pci_device_1014_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0180 = { + 0x0180, pci_device_1014_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0188 = { + 0x0188, pci_device_1014_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01c1 = { + 0x01c1, pci_device_1014_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01e6 = { + 0x01e6, pci_device_1014_01e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01ff = { + 0x01ff, pci_device_1014_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0219 = { + 0x0219, pci_device_1014_0219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021b = { + 0x021b, pci_device_1014_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021c = { + 0x021c, pci_device_1014_021c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0233 = { + 0x0233, pci_device_1014_0233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0266 = { + 0x0266, pci_device_1014_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0268 = { + 0x0268, pci_device_1014_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0269 = { + 0x0269, pci_device_1014_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_028c = { + 0x028c, pci_device_1014_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02a1 = { + 0x02a1, pci_device_1014_02a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02bd = { + 0x02bd, pci_device_1014_02bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0314 = { + 0x0314, pci_device_1014_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_3022 = { + 0x3022, pci_device_1014_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_4022 = { + 0x4022, pci_device_1014_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_0009 = { + 0x0009, pci_device_101e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2003 = { + 0x2003, pci_device_1022_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2081 = { + 0x2081, pci_device_1022_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2082 = { + 0x2082, pci_device_1022_2082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_208f = { + 0x208f, pci_device_1022_208f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_208f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2090 = { + 0x2090, pci_device_1022_2090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2091 = { + 0x2091, pci_device_1022_2091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2093 = { + 0x2093, pci_device_1022_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2094 = { + 0x2094, pci_device_1022_2094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2095 = { + 0x2095, pci_device_1022_2095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2096 = { + 0x2096, pci_device_1022_2096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2097 = { + 0x2097, pci_device_1022_2097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_209a = { + 0x209a, pci_device_1022_209a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_209a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700a = { + 0x700a, pci_device_1022_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700b = { + 0x700b, pci_device_1022_700b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7458 = { + 0x7458, pci_device_1022_7458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7459 = { + 0x7459, pci_device_1022_7459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_756b = { + 0x756b, pci_device_1022_756b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_756b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2100 = { + 0x2100, pci_device_1023_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2200 = { + 0x2200, pci_device_1023_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1671 = { + 0x1671, pci_device_1025_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1672 = { + 0x1672, pci_device_1025_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0009 = { + 0x0009, pci_device_1028_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000d = { + 0x000d, pci_device_1028_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0010 = { + 0x0010, pci_device_1028_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0011 = { + 0x0011, pci_device_1028_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0012 = { + 0x0012, pci_device_1028_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0013 = { + 0x0013, pci_device_1028_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0014 = { + 0x0014, pci_device_1028_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0015 = { + 0x0015, pci_device_1028_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0015, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_001f = { + 0x001f, pci_device_102a_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00c5 = { + 0x00c5, pci_device_102a_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00cf = { + 0x00cf, pci_device_102a_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00cf, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0100 = { + 0x0100, pci_device_102b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0528 = { + 0x0528, pci_device_102b_0528, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0528, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2537 = { + 0x2537, pci_device_102b_2537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2538 = { + 0x2538, pci_device_102b_2538, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2538, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_000a = { + 0x000a, pci_device_102f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0030 = { + 0x0030, pci_device_102f_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0031 = { + 0x0031, pci_device_102f_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0105 = { + 0x0105, pci_device_102f_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0106 = { + 0x0106, pci_device_102f_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0107 = { + 0x0107, pci_device_102f_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0108 = { + 0x0108, pci_device_102f_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0180 = { + 0x0180, pci_device_102f_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0181 = { + 0x0181, pci_device_102f_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0182 = { + 0x0182, pci_device_102f_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0182, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0000 = { + 0x0000, pci_device_1033_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0072 = { + 0x0072, pci_device_1033_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a5 = { + 0x00a5, pci_device_1033_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00ce = { + 0x00ce, pci_device_1033_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00df = { + 0x00df, pci_device_1033_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e7 = { + 0x00e7, pci_device_1033_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f2 = { + 0x00f2, pci_device_1033_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f3 = { + 0x00f3, pci_device_1033_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_010c = { + 0x010c, pci_device_1033_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_010c, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0003 = { + 0x0003, pci_device_1039_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0004 = { + 0x0004, pci_device_1039_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_000a = { + 0x000a, pci_device_1039_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0016 = { + 0x0016, pci_device_1039_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0180 = { + 0x0180, pci_device_1039_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0181 = { + 0x0181, pci_device_1039_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0182 = { + 0x0182, pci_device_1039_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0190 = { + 0x0190, pci_device_1039_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0191 = { + 0x0191, pci_device_1039_0191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0550 = { + 0x0550, pci_device_1039_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0648 = { + 0x0648, pci_device_1039_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0655 = { + 0x0655, pci_device_1039_0655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0660 = { + 0x0660, pci_device_1039_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0661 = { + 0x0661, pci_device_1039_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0661, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0741 = { + 0x0741, pci_device_1039_0741, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0741, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0746 = { + 0x0746, pci_device_1039_0746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0755 = { + 0x0755, pci_device_1039_0755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0760 = { + 0x0760, pci_device_1039_0760, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0760, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0761 = { + 0x0761, pci_device_1039_0761, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0761, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0963 = { + 0x0963, pci_device_1039_0963, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0963, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0964 = { + 0x0964, pci_device_1039_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0965 = { + 0x0965, pci_device_1039_0965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6330 = { + 0x6330, pci_device_1039_6330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7019 = { + 0x7019, pci_device_1039_7019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1006 = { + 0x1006, pci_device_103c_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_100a = { + 0x100a, pci_device_103c_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1054 = { + 0x1054, pci_device_103c_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f0 = { + 0x10f0, pci_device_103c_10f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f1 = { + 0x10f1, pci_device_103c_10f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127c = { + 0x127c, pci_device_103c_127c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1291 = { + 0x1291, pci_device_103c_1291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12b4 = { + 0x12b4, pci_device_103c_12b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12fa = { + 0x12fa, pci_device_103c_12fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3080 = { + 0x3080, pci_device_103c_3080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3220 = { + 0x3220, pci_device_103c_3220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3230 = { + 0x3230, pci_device_103c_3230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3230, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4015 = { + 0x4015, pci_device_1043_4015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4057 = { + 0x4057, pci_device_1043_4057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8043 = { + 0x8043, pci_device_1043_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_807b = { + 0x807b, pci_device_1043_807b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_807b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80bb = { + 0x80bb, pci_device_1043_80bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80c5 = { + 0x80c5, pci_device_1043_80c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80df = { + 0x80df, pci_device_1043_80df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8187 = { + 0x8187, pci_device_1043_8187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8188 = { + 0x8188, pci_device_1043_8188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8188, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0c60 = { + 0x0c60, pci_device_1048_0c60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0c60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_8901 = { + 0x8901, pci_device_1048_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_8901, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0209 = { + 0x0209, pci_device_104a_0209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_020a = { + 0x020a, pci_device_104a_020a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_020a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021a = { + 0x021a, pci_device_104a_021a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021b = { + 0x021b, pci_device_104a_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0500 = { + 0x0500, pci_device_104a_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0564 = { + 0x0564, pci_device_104a_0564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_55cc = { + 0x55cc, pci_device_104a_55cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_55cc, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8025 = { + 0x8025, pci_device_104c_8025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8029 = { + 0x8029, pci_device_104c_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802b = { + 0x802b, pci_device_104c_802b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802e = { + 0x802e, pci_device_104c_802e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8031 = { + 0x8031, pci_device_104c_8031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8032 = { + 0x8032, pci_device_104c_8032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8033 = { + 0x8033, pci_device_104c_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8034 = { + 0x8034, pci_device_104c_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8035 = { + 0x8035, pci_device_104c_8035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8036 = { + 0x8036, pci_device_104c_8036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8038 = { + 0x8038, pci_device_104c_8038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8201 = { + 0x8201, pci_device_104c_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8204 = { + 0x8204, pci_device_104c_8204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8401 = { + 0x8401, pci_device_104c_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9000 = { + 0x9000, pci_device_104c_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9065 = { + 0x9065, pci_device_104c_9065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9066 = { + 0x9066, pci_device_104c_9066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac44 = { + 0xac44, pci_device_104c_ac44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac46 = { + 0xac46, pci_device_104c_ac46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac47 = { + 0xac47, pci_device_104c_ac47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac4a = { + 0xac4a, pci_device_104c_ac4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac54 = { + 0xac54, pci_device_104c_ac54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8d = { + 0xac8d, pci_device_104c_ac8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8e = { + 0xac8e, pci_device_104c_ac8e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8f = { + 0xac8f, pci_device_104c_ac8f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8004 = { + 0x8004, pci_device_104d_8004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9921 = { + 0x9921, pci_device_1050_9921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9922 = { + 0x9922, pci_device_1050_9922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0008 = { + 0x0008, pci_device_1057_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0009 = { + 0x0009, pci_device_1057_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c1 = { + 0x18c1, pci_device_1057_18c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3410 = { + 0x3410, pci_device_1057_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5608 = { + 0x5608, pci_device_1057_5608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5803 = { + 0x5803, pci_device_1057_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5806 = { + 0x5806, pci_device_1057_5806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5808 = { + 0x5808, pci_device_1057_5808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6405 = { + 0x6405, pci_device_1057_6405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6405, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3318 = { + 0x3318, pci_device_105a_3318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3319 = { + 0x3319, pci_device_105a_3319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3371 = { + 0x3371, pci_device_105a_3371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3373 = { + 0x3373, pci_device_105a_3373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3375 = { + 0x3375, pci_device_105a_3375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3515 = { + 0x3515, pci_device_105a_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3519 = { + 0x3519, pci_device_105a_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3570 = { + 0x3570, pci_device_105a_3570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3571 = { + 0x3571, pci_device_105a_3571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3574 = { + 0x3574, pci_device_105a_3574, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3574, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3577 = { + 0x3577, pci_device_105a_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d17 = { + 0x3d17, pci_device_105a_3d17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d18 = { + 0x3d18, pci_device_105a_3d18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d73 = { + 0x3d73, pci_device_105a_3d73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d75 = { + 0x3d75, pci_device_105a_3d75, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d75, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6622 = { + 0x6622, pci_device_105a_6622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6624 = { + 0x6624, pci_device_105a_6624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6626 = { + 0x6626, pci_device_105a_6626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6629 = { + 0x6629, pci_device_105a_6629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8002 = { + 0x8002, pci_device_105a_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_0301 = { + 0x0301, pci_device_1067_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0304 = { + 0x0304, pci_device_1067_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0308 = { + 0x0308, pci_device_1067_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0020 = { + 0x0020, pci_device_1069_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_b166 = { + 0xb166, pci_device_1069_b166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_b166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba57 = { + 0xba57, pci_device_1069_ba57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba57, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000c = { + 0x000c, pci_device_106b_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0035 = { + 0x0035, pci_device_106b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0036 = { + 0x0036, pci_device_106b_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003b = { + 0x003b, pci_device_106b_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003e = { + 0x003e, pci_device_106b_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003f = { + 0x003f, pci_device_106b_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0040 = { + 0x0040, pci_device_106b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0041 = { + 0x0041, pci_device_106b_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0042 = { + 0x0042, pci_device_106b_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0043 = { + 0x0043, pci_device_106b_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0045 = { + 0x0045, pci_device_106b_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0046 = { + 0x0046, pci_device_106b_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0047 = { + 0x0047, pci_device_106b_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0048 = { + 0x0048, pci_device_106b_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0049 = { + 0x0049, pci_device_106b_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004b = { + 0x004b, pci_device_106b_004b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004c = { + 0x004c, pci_device_106b_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004f = { + 0x004f, pci_device_106b_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0050 = { + 0x0050, pci_device_106b_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0051 = { + 0x0051, pci_device_106b_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0052 = { + 0x0052, pci_device_106b_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0053 = { + 0x0053, pci_device_106b_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0054 = { + 0x0054, pci_device_106b_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0055 = { + 0x0055, pci_device_106b_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0058 = { + 0x0058, pci_device_106b_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0059 = { + 0x0059, pci_device_106b_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0066 = { + 0x0066, pci_device_106b_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0067 = { + 0x0067, pci_device_106b_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0068 = { + 0x0068, pci_device_106b_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0069 = { + 0x0069, pci_device_106b_0069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006a = { + 0x006a, pci_device_106b_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006b = { + 0x006b, pci_device_106b_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1071_8160 = { + 0x8160, pci_device_1071_8160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1071_8160, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2322 = { + 0x2322, pci_device_1077_2322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2422 = { + 0x2422, pci_device_1077_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2432 = { + 0x2432, pci_device_1077_2432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3010 = { + 0x3010, pci_device_1077_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3022 = { + 0x3022, pci_device_1077_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4010 = { + 0x4010, pci_device_1077_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4022 = { + 0x4022, pci_device_1077_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6312 = { + 0x6312, pci_device_1077_6312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6322 = { + 0x6322, pci_device_1077_6322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6322, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2134 = { + 0x2134, pci_device_107d_2134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2971 = { + 0x2971, pci_device_107d_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2971, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1648 = { + 0x1648, pci_device_108e_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8002 = { + 0x8002, pci_device_108e_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a801 = { + 0xa801, pci_device_108e_a801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_abba = { + 0xabba, pci_device_108e_abba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_abba, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_07a0 = { + 0x07a0, pci_device_1091_07a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_07a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_1091 = { + 0x1091, pci_device_1091_1091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_1091, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1310 = { + 0x1310, pci_device_1093_1310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14e0 = { + 0x14e0, pci_device_1093_14e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14f0 = { + 0x14f0, pci_device_1093_14f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_17d0 = { + 0x17d0, pci_device_1093_17d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_17d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1870 = { + 0x1870, pci_device_1093_1870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1880 = { + 0x1880, pci_device_1093_1880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_18b0 = { + 0x18b0, pci_device_1093_18b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_18b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2410 = { + 0x2410, pci_device_1093_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2890 = { + 0x2890, pci_device_1093_2890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a70 = { + 0x2a70, pci_device_1093_2a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a80 = { + 0x2a80, pci_device_1093_2a80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2c80 = { + 0x2c80, pci_device_1093_2c80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2c80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2ca0 = { + 0x2ca0, pci_device_1093_2ca0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2ca0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70a9 = { + 0x70a9, pci_device_1093_70a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70b8 = { + 0x70b8, pci_device_1093_70b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0240 = { + 0x0240, pci_device_1095_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3114 = { + 0x3114, pci_device_1095_3114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3124 = { + 0x3124, pci_device_1095_3124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3132 = { + 0x3132, pci_device_1095_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3512 = { + 0x3512, pci_device_1095_3512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3512, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_032e = { + 0x032e, pci_device_109e_032e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_032e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_3052 = { + 0x3052, pci_device_10a5_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_100a = { + 0x100a, pci_device_10a9_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4001 = { + 0x4001, pci_device_10a9_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4002 = { + 0x4002, pci_device_10a9_4002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8010 = { + 0x8010, pci_device_10a9_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8018 = { + 0x8018, pci_device_10a9_8018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8018, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1042 = { + 0x1042, pci_device_10b5_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2540 = { + 0x2540, pci_device_10b5_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6540 = { + 0x6540, pci_device_10b5_6540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6541 = { + 0x6541, pci_device_10b5_6541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6542 = { + 0x6542, pci_device_10b5_6542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8111 = { + 0x8111, pci_device_10b5_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8114 = { + 0x8114, pci_device_10b5_8114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8516 = { + 0x8516, pci_device_10b5_8516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8532 = { + 0x8532, pci_device_10b5_8532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9056 = { + 0x9056, pci_device_10b5_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_bb04 = { + 0xbb04, pci_device_10b5_bb04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_bb04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0013 = { + 0x0013, pci_device_10b7_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0910 = { + 0x0910, pci_device_10b7_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1201 = { + 0x1201, pci_device_10b7_1201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1202 = { + 0x1202, pci_device_10b7_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1700 = { + 0x1700, pci_device_10b7_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6000 = { + 0x6000, pci_device_10b7_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6001 = { + 0x6001, pci_device_10b7_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7770 = { + 0x7770, pci_device_10b7_7770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_80eb = { + 0x80eb, pci_device_10b7_80eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_80eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9202 = { + 0x9202, pci_device_10b7_9202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9210 = { + 0x9210, pci_device_10b7_9210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990a = { + 0x990a, pci_device_10b7_990a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_2802 = { + 0x2802, pci_device_10b8_2802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_2802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b9_0101 = { + 0x0101, pci_device_10b9_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0780 = { + 0x0780, pci_device_10b9_0780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0782 = { + 0x0782, pci_device_10b9_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1573 = { + 0x1573, pci_device_10b9_1573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1672 = { + 0x1672, pci_device_10b9_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1689 = { + 0x1689, pci_device_10b9_1689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1695 = { + 0x1695, pci_device_10b9_1695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1695, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1697 = { + 0x1697, pci_device_10b9_1697, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1697, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3323 = { + 0x3323, pci_device_10b9_3323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5228 = { + 0x5228, pci_device_10b9_5228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5246 = { + 0x5246, pci_device_10b9_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524b = { + 0x524b, pci_device_10b9_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524c = { + 0x524c, pci_device_10b9_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524d = { + 0x524d, pci_device_10b9_524d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524e = { + 0x524e, pci_device_10b9_524e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5263 = { + 0x5263, pci_device_10b9_5263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5281 = { + 0x5281, pci_device_10b9_5281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5287 = { + 0x5287, pci_device_10b9_5287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5288 = { + 0x5288, pci_device_10b9_5288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5289 = { + 0x5289, pci_device_10b9_5289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5450 = { + 0x5450, pci_device_10b9_5450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5461 = { + 0x5461, pci_device_10b9_5461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0304 = { + 0x0304, pci_device_10ba_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0308 = { + 0x0308, pci_device_10ba_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_1002 = { + 0x1002, pci_device_10ba_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cc_0660 = { + 0x0660, pci_device_10cc_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cc_0661 = { + 0x0661, pci_device_10cc_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0661, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0431 = { + 0x0431, pci_device_10d9_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8626 = { + 0x8626, pci_device_10d9_8626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dd_0100 = { + 0x0100, pci_device_10dd_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dd_0100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0034 = { + 0x0034, pci_device_10de_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0035 = { + 0x0035, pci_device_10de_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0036 = { + 0x0036, pci_device_10de_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0037 = { + 0x0037, pci_device_10de_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0038 = { + 0x0038, pci_device_10de_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003a = { + 0x003a, pci_device_10de_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003b = { + 0x003b, pci_device_10de_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003c = { + 0x003c, pci_device_10de_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003d = { + 0x003d, pci_device_10de_003d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003e = { + 0x003e, pci_device_10de_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0040 = { + 0x0040, pci_device_10de_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0041 = { + 0x0041, pci_device_10de_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0042 = { + 0x0042, pci_device_10de_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0043 = { + 0x0043, pci_device_10de_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0045 = { + 0x0045, pci_device_10de_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0047 = { + 0x0047, pci_device_10de_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0049 = { + 0x0049, pci_device_10de_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004e = { + 0x004e, pci_device_10de_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0050 = { + 0x0050, pci_device_10de_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0051 = { + 0x0051, pci_device_10de_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0052 = { + 0x0052, pci_device_10de_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0053 = { + 0x0053, pci_device_10de_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0054 = { + 0x0054, pci_device_10de_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0055 = { + 0x0055, pci_device_10de_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0056 = { + 0x0056, pci_device_10de_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0057 = { + 0x0057, pci_device_10de_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0058 = { + 0x0058, pci_device_10de_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0059 = { + 0x0059, pci_device_10de_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005a = { + 0x005a, pci_device_10de_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005b = { + 0x005b, pci_device_10de_005b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005c = { + 0x005c, pci_device_10de_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005d = { + 0x005d, pci_device_10de_005d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005e = { + 0x005e, pci_device_10de_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005f = { + 0x005f, pci_device_10de_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006c = { + 0x006c, pci_device_10de_006c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006d = { + 0x006d, pci_device_10de_006d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0080 = { + 0x0080, pci_device_10de_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0084 = { + 0x0084, pci_device_10de_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0085 = { + 0x0085, pci_device_10de_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0086 = { + 0x0086, pci_device_10de_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0087 = { + 0x0087, pci_device_10de_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0088 = { + 0x0088, pci_device_10de_0088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008a = { + 0x008a, pci_device_10de_008a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008b = { + 0x008b, pci_device_10de_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008c = { + 0x008c, pci_device_10de_008c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008e = { + 0x008e, pci_device_10de_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0091 = { + 0x0091, pci_device_10de_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0092 = { + 0x0092, pci_device_10de_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0099 = { + 0x0099, pci_device_10de_0099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c0 = { + 0x00c0, pci_device_10de_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c1 = { + 0x00c1, pci_device_10de_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c2 = { + 0x00c2, pci_device_10de_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c8 = { + 0x00c8, pci_device_10de_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c9 = { + 0x00c9, pci_device_10de_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cc = { + 0x00cc, pci_device_10de_00cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cd = { + 0x00cd, pci_device_10de_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ce = { + 0x00ce, pci_device_10de_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d0 = { + 0x00d0, pci_device_10de_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d1 = { + 0x00d1, pci_device_10de_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d2 = { + 0x00d2, pci_device_10de_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d3 = { + 0x00d3, pci_device_10de_00d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d4 = { + 0x00d4, pci_device_10de_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d5 = { + 0x00d5, pci_device_10de_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d6 = { + 0x00d6, pci_device_10de_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d7 = { + 0x00d7, pci_device_10de_00d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d8 = { + 0x00d8, pci_device_10de_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d9 = { + 0x00d9, pci_device_10de_00d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00da = { + 0x00da, pci_device_10de_00da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00dd = { + 0x00dd, pci_device_10de_00dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00df = { + 0x00df, pci_device_10de_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e0 = { + 0x00e0, pci_device_10de_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e1 = { + 0x00e1, pci_device_10de_00e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e2 = { + 0x00e2, pci_device_10de_00e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e3 = { + 0x00e3, pci_device_10de_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e4 = { + 0x00e4, pci_device_10de_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e5 = { + 0x00e5, pci_device_10de_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e6 = { + 0x00e6, pci_device_10de_00e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e7 = { + 0x00e7, pci_device_10de_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e8 = { + 0x00e8, pci_device_10de_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ea = { + 0x00ea, pci_device_10de_00ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ed = { + 0x00ed, pci_device_10de_00ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ee = { + 0x00ee, pci_device_10de_00ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f0 = { + 0x00f0, pci_device_10de_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f1 = { + 0x00f1, pci_device_10de_00f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f2 = { + 0x00f2, pci_device_10de_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f3 = { + 0x00f3, pci_device_10de_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f8 = { + 0x00f8, pci_device_10de_00f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f9 = { + 0x00f9, pci_device_10de_00f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fa = { + 0x00fa, pci_device_10de_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fb = { + 0x00fb, pci_device_10de_00fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fc = { + 0x00fc, pci_device_10de_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fd = { + 0x00fd, pci_device_10de_00fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fe = { + 0x00fe, pci_device_10de_00fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ff = { + 0x00ff, pci_device_10de_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0140 = { + 0x0140, pci_device_10de_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0141 = { + 0x0141, pci_device_10de_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0142 = { + 0x0142, pci_device_10de_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0144 = { + 0x0144, pci_device_10de_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0145 = { + 0x0145, pci_device_10de_0145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0146 = { + 0x0146, pci_device_10de_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0148 = { + 0x0148, pci_device_10de_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014e = { + 0x014e, pci_device_10de_014e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014f = { + 0x014f, pci_device_10de_014f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0161 = { + 0x0161, pci_device_10de_0161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0164 = { + 0x0164, pci_device_10de_0164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0165 = { + 0x0165, pci_device_10de_0165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0167 = { + 0x0167, pci_device_10de_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0177 = { + 0x0177, pci_device_10de_0177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017d = { + 0x017d, pci_device_10de_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0185 = { + 0x0185, pci_device_10de_0185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0186 = { + 0x0186, pci_device_10de_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0187 = { + 0x0187, pci_device_10de_0187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018d = { + 0x018d, pci_device_10de_018d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b0 = { + 0x01b0, pci_device_10de_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e0 = { + 0x01e0, pci_device_10de_01e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ea = { + 0x01ea, pci_device_10de_01ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01eb = { + 0x01eb, pci_device_10de_01eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ec = { + 0x01ec, pci_device_10de_01ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ed = { + 0x01ed, pci_device_10de_01ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ee = { + 0x01ee, pci_device_10de_01ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ef = { + 0x01ef, pci_device_10de_01ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0221 = { + 0x0221, pci_device_10de_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0240 = { + 0x0240, pci_device_10de_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0241 = { + 0x0241, pci_device_10de_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0242 = { + 0x0242, pci_device_10de_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0243 = { + 0x0243, pci_device_10de_0243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0244 = { + 0x0244, pci_device_10de_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0245 = { + 0x0245, pci_device_10de_0245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0246 = { + 0x0246, pci_device_10de_0246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0247 = { + 0x0247, pci_device_10de_0247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0248 = { + 0x0248, pci_device_10de_0248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0249 = { + 0x0249, pci_device_10de_0249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024a = { + 0x024a, pci_device_10de_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024b = { + 0x024b, pci_device_10de_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024c = { + 0x024c, pci_device_10de_024c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024d = { + 0x024d, pci_device_10de_024d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024e = { + 0x024e, pci_device_10de_024e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024f = { + 0x024f, pci_device_10de_024f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0260 = { + 0x0260, pci_device_10de_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0261 = { + 0x0261, pci_device_10de_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0262 = { + 0x0262, pci_device_10de_0262, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0262, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0263 = { + 0x0263, pci_device_10de_0263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0264 = { + 0x0264, pci_device_10de_0264, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0264, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0265 = { + 0x0265, pci_device_10de_0265, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0265, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0266 = { + 0x0266, pci_device_10de_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0267 = { + 0x0267, pci_device_10de_0267, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0267, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0268 = { + 0x0268, pci_device_10de_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0269 = { + 0x0269, pci_device_10de_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026a = { + 0x026a, pci_device_10de_026a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026b = { + 0x026b, pci_device_10de_026b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026c = { + 0x026c, pci_device_10de_026c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026d = { + 0x026d, pci_device_10de_026d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026e = { + 0x026e, pci_device_10de_026e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026f = { + 0x026f, pci_device_10de_026f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0270 = { + 0x0270, pci_device_10de_0270, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0270, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0271 = { + 0x0271, pci_device_10de_0271, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0271, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0272 = { + 0x0272, pci_device_10de_0272, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0272, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027e = { + 0x027e, pci_device_10de_027e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027f = { + 0x027f, pci_device_10de_027f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0286 = { + 0x0286, pci_device_10de_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_028c = { + 0x028c, pci_device_10de_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02a0 = { + 0x02a0, pci_device_10de_02a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f0 = { + 0x02f0, pci_device_10de_02f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f1 = { + 0x02f1, pci_device_10de_02f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f2 = { + 0x02f2, pci_device_10de_02f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f3 = { + 0x02f3, pci_device_10de_02f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f4 = { + 0x02f4, pci_device_10de_02f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f5 = { + 0x02f5, pci_device_10de_02f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f6 = { + 0x02f6, pci_device_10de_02f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f7 = { + 0x02f7, pci_device_10de_02f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f8 = { + 0x02f8, pci_device_10de_02f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f9 = { + 0x02f9, pci_device_10de_02f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fa = { + 0x02fa, pci_device_10de_02fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fb = { + 0x02fb, pci_device_10de_02fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fc = { + 0x02fc, pci_device_10de_02fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fd = { + 0x02fd, pci_device_10de_02fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fe = { + 0x02fe, pci_device_10de_02fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02ff = { + 0x02ff, pci_device_10de_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0311 = { + 0x0311, pci_device_10de_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0312 = { + 0x0312, pci_device_10de_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0313 = { + 0x0313, pci_device_10de_0313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0314 = { + 0x0314, pci_device_10de_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0316 = { + 0x0316, pci_device_10de_0316, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0316, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0317 = { + 0x0317, pci_device_10de_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0317, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031a = { + 0x031a, pci_device_10de_031a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031b = { + 0x031b, pci_device_10de_031b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031c = { + 0x031c, pci_device_10de_031c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031d = { + 0x031d, pci_device_10de_031d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031e = { + 0x031e, pci_device_10de_031e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031f = { + 0x031f, pci_device_10de_031f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0320 = { + 0x0320, pci_device_10de_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0321 = { + 0x0321, pci_device_10de_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0322 = { + 0x0322, pci_device_10de_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0323 = { + 0x0323, pci_device_10de_0323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0324 = { + 0x0324, pci_device_10de_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0325 = { + 0x0325, pci_device_10de_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0326 = { + 0x0326, pci_device_10de_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0327 = { + 0x0327, pci_device_10de_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0328 = { + 0x0328, pci_device_10de_0328, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0328, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0329 = { + 0x0329, pci_device_10de_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032a = { + 0x032a, pci_device_10de_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032b = { + 0x032b, pci_device_10de_032b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032c = { + 0x032c, pci_device_10de_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032d = { + 0x032d, pci_device_10de_032d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032f = { + 0x032f, pci_device_10de_032f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0330 = { + 0x0330, pci_device_10de_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0331 = { + 0x0331, pci_device_10de_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0332 = { + 0x0332, pci_device_10de_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0333 = { + 0x0333, pci_device_10de_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0334 = { + 0x0334, pci_device_10de_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0338 = { + 0x0338, pci_device_10de_0338, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0338, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_033f = { + 0x033f, pci_device_10de_033f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_033f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0341 = { + 0x0341, pci_device_10de_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0342 = { + 0x0342, pci_device_10de_0342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0343 = { + 0x0343, pci_device_10de_0343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0344 = { + 0x0344, pci_device_10de_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0345 = { + 0x0345, pci_device_10de_0345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0347 = { + 0x0347, pci_device_10de_0347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0348 = { + 0x0348, pci_device_10de_0348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0349 = { + 0x0349, pci_device_10de_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034b = { + 0x034b, pci_device_10de_034b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034c = { + 0x034c, pci_device_10de_034c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034e = { + 0x034e, pci_device_10de_034e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034f = { + 0x034f, pci_device_10de_034f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0360 = { + 0x0360, pci_device_10de_0360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0361 = { + 0x0361, pci_device_10de_0361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0362 = { + 0x0362, pci_device_10de_0362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0363 = { + 0x0363, pci_device_10de_0363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0364 = { + 0x0364, pci_device_10de_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0365 = { + 0x0365, pci_device_10de_0365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0366 = { + 0x0366, pci_device_10de_0366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0367 = { + 0x0367, pci_device_10de_0367, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0367, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0368 = { + 0x0368, pci_device_10de_0368, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0368, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0369 = { + 0x0369, pci_device_10de_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036a = { + 0x036a, pci_device_10de_036a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036c = { + 0x036c, pci_device_10de_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036d = { + 0x036d, pci_device_10de_036d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036e = { + 0x036e, pci_device_10de_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0371 = { + 0x0371, pci_device_10de_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0372 = { + 0x0372, pci_device_10de_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0373 = { + 0x0373, pci_device_10de_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037a = { + 0x037a, pci_device_10de_037a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037e = { + 0x037e, pci_device_10de_037e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037f = { + 0x037f, pci_device_10de_037f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a1 = { + 0xf0a1, pci_device_10df_f0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a5 = { + 0xf0a5, pci_device_10df_f0a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0b5 = { + 0xf0b5, pci_device_10df_f0b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d1 = { + 0xf0d1, pci_device_10df_f0d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d5 = { + 0xf0d5, pci_device_10df_f0d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e1 = { + 0xf0e1, pci_device_10df_f0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e5 = { + 0xf0e5, pci_device_10df_f0e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0f5 = { + 0xf0f5, pci_device_10df_f0f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f701 = { + 0xf701, pci_device_10df_f701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f801 = { + 0xf801, pci_device_10df_f801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f901 = { + 0xf901, pci_device_10df_f901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f981 = { + 0xf981, pci_device_10df_f981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f982 = { + 0xf982, pci_device_10df_f982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fa00 = { + 0xfa00, pci_device_10df_fa00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fa00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fb00 = { + 0xfb00, pci_device_10df_fb00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fb00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc00 = { + 0xfc00, pci_device_10df_fc00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc10 = { + 0xfc10, pci_device_10df_fc10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc20 = { + 0xfc20, pci_device_10df_fc20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fd00 = { + 0xfd00, pci_device_10df_fd00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fd00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fe00 = { + 0xfe00, pci_device_10df_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_ff00 = { + 0xff00, pci_device_10df_ff00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_ff00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0148 = { + 0x0148, pci_device_10e3_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8260 = { + 0x8260, pci_device_10e3_8260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8261 = { + 0x8261, pci_device_10e3_8261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8261, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e4_8029 = { + 0x8029, pci_device_10e4_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e4_8029, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_1072 = { + 0x1072, pci_device_10e8_1072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_1072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_814c = { + 0x814c, pci_device_10e8_814c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_814c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_81e6 = { + 0x81e6, pci_device_10e8_81e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_81e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8291 = { + 0x8291, pci_device_10e8_8291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c4 = { + 0x82c4, pci_device_10e8_82c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c5 = { + 0x82c5, pci_device_10e8_82c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c6 = { + 0x82c6, pci_device_10e8_82c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c7 = { + 0x82c7, pci_device_10e8_82c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82ca = { + 0x82ca, pci_device_10e8_82ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82e2 = { + 0x82e2, pci_device_10e8_82e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8851 = { + 0x8851, pci_device_10e8_8851, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8851, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5252 = { + 0x5252, pci_device_10ea_5252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5252, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_0139 = { + 0x0139, pci_device_10ec_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8180 = { + 0x8180, pci_device_10ec_8180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_0205 = { + 0x0205, pci_device_10ee_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0210 = { + 0x0210, pci_device_10ee_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0314 = { + 0x0314, pci_device_10ee_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0405 = { + 0x0405, pci_device_10ee_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0410 = { + 0x0410, pci_device_10ee_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc6 = { + 0x3fc6, pci_device_10ee_3fc6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_8381 = { + 0x8381, pci_device_10ee_8381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_8381, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9502 = { + 0x9502, pci_device_1101_9502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9502, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0007 = { + 0x0007, pci_device_1102_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0008 = { + 0x0008, pci_device_1102_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7005 = { + 0x7005, pci_device_1102_7005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0009 = { + 0x0009, pci_device_1103_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0009, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8401 = { + 0x8401, pci_device_1105_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8470 = { + 0x8470, pci_device_1105_8470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8471 = { + 0x8471, pci_device_1105_8471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8475 = { + 0x8475, pci_device_1105_8475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8476 = { + 0x8476, pci_device_1105_8476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8485 = { + 0x8485, pci_device_1105_8485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8486 = { + 0x8486, pci_device_1105_8486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8486, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0204 = { + 0x0204, pci_device_1106_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0238 = { + 0x0238, pci_device_1106_0238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0259 = { + 0x0259, pci_device_1106_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0269 = { + 0x0269, pci_device_1106_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0282 = { + 0x0282, pci_device_1106_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0290 = { + 0x0290, pci_device_1106_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0296 = { + 0x0296, pci_device_1106_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0308 = { + 0x0308, pci_device_1106_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0314 = { + 0x0314, pci_device_1106_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0591 = { + 0x0591, pci_device_1106_0591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1204 = { + 0x1204, pci_device_1106_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1208 = { + 0x1208, pci_device_1106_1208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1238 = { + 0x1238, pci_device_1106_1238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1258 = { + 0x1258, pci_device_1106_1258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1259 = { + 0x1259, pci_device_1106_1259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1269 = { + 0x1269, pci_device_1106_1269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1282 = { + 0x1282, pci_device_1106_1282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1290 = { + 0x1290, pci_device_1106_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1296 = { + 0x1296, pci_device_1106_1296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1308 = { + 0x1308, pci_device_1106_1308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1314 = { + 0x1314, pci_device_1106_1314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2204 = { + 0x2204, pci_device_1106_2204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2208 = { + 0x2208, pci_device_1106_2208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2238 = { + 0x2238, pci_device_1106_2238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2258 = { + 0x2258, pci_device_1106_2258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2259 = { + 0x2259, pci_device_1106_2259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2269 = { + 0x2269, pci_device_1106_2269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2282 = { + 0x2282, pci_device_1106_2282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2290 = { + 0x2290, pci_device_1106_2290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2296 = { + 0x2296, pci_device_1106_2296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2308 = { + 0x2308, pci_device_1106_2308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2314 = { + 0x2314, pci_device_1106_2314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287a = { + 0x287a, pci_device_1106_287a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287b = { + 0x287b, pci_device_1106_287b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287c = { + 0x287c, pci_device_1106_287c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287d = { + 0x287d, pci_device_1106_287d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287e = { + 0x287e, pci_device_1106_287e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3022 = { + 0x3022, pci_device_1106_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3053 = { + 0x3053, pci_device_1106_3053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3108 = { + 0x3108, pci_device_1106_3108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3113 = { + 0x3113, pci_device_1106_3113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3118 = { + 0x3118, pci_device_1106_3118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3119 = { + 0x3119, pci_device_1106_3119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3149 = { + 0x3149, pci_device_1106_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3164 = { + 0x3164, pci_device_1106_3164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3178 = { + 0x3178, pci_device_1106_3178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3188 = { + 0x3188, pci_device_1106_3188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3204 = { + 0x3204, pci_device_1106_3204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3205 = { + 0x3205, pci_device_1106_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3208 = { + 0x3208, pci_device_1106_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3213 = { + 0x3213, pci_device_1106_3213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3218 = { + 0x3218, pci_device_1106_3218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3227 = { + 0x3227, pci_device_1106_3227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3238 = { + 0x3238, pci_device_1106_3238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3249 = { + 0x3249, pci_device_1106_3249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3258 = { + 0x3258, pci_device_1106_3258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3259 = { + 0x3259, pci_device_1106_3259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3269 = { + 0x3269, pci_device_1106_3269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3282 = { + 0x3282, pci_device_1106_3282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3287 = { + 0x3287, pci_device_1106_3287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3288 = { + 0x3288, pci_device_1106_3288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3290 = { + 0x3290, pci_device_1106_3290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3296 = { + 0x3296, pci_device_1106_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3337 = { + 0x3337, pci_device_1106_3337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3344 = { + 0x3344, pci_device_1106_3344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3349 = { + 0x3349, pci_device_1106_3349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337a = { + 0x337a, pci_device_1106_337a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337b = { + 0x337b, pci_device_1106_337b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4149 = { + 0x4149, pci_device_1106_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4204 = { + 0x4204, pci_device_1106_4204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4208 = { + 0x4208, pci_device_1106_4208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4238 = { + 0x4238, pci_device_1106_4238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4258 = { + 0x4258, pci_device_1106_4258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4259 = { + 0x4259, pci_device_1106_4259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4269 = { + 0x4269, pci_device_1106_4269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4282 = { + 0x4282, pci_device_1106_4282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4290 = { + 0x4290, pci_device_1106_4290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4296 = { + 0x4296, pci_device_1106_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4308 = { + 0x4308, pci_device_1106_4308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4314 = { + 0x4314, pci_device_1106_4314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5208 = { + 0x5208, pci_device_1106_5208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5238 = { + 0x5238, pci_device_1106_5238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5290 = { + 0x5290, pci_device_1106_5290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5308 = { + 0x5308, pci_device_1106_5308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7204 = { + 0x7204, pci_device_1106_7204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7205 = { + 0x7205, pci_device_1106_7205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7208 = { + 0x7208, pci_device_1106_7208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7238 = { + 0x7238, pci_device_1106_7238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7258 = { + 0x7258, pci_device_1106_7258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7259 = { + 0x7259, pci_device_1106_7259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7269 = { + 0x7269, pci_device_1106_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7282 = { + 0x7282, pci_device_1106_7282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7290 = { + 0x7290, pci_device_1106_7290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7296 = { + 0x7296, pci_device_1106_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7308 = { + 0x7308, pci_device_1106_7308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7314 = { + 0x7314, pci_device_1106_7314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a208 = { + 0xa208, pci_device_1106_a208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a238 = { + 0xa238, pci_device_1106_a238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b113 = { + 0xb113, pci_device_1106_b113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b115 = { + 0xb115, pci_device_1106_b115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b188 = { + 0xb188, pci_device_1106_b188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b198 = { + 0xb198, pci_device_1106_b198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b213 = { + 0xb213, pci_device_1106_b213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c208 = { + 0xc208, pci_device_1106_c208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c238 = { + 0xc238, pci_device_1106_c238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d104 = { + 0xd104, pci_device_1106_d104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d208 = { + 0xd208, pci_device_1106_d208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d213 = { + 0xd213, pci_device_1106_d213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d238 = { + 0xd238, pci_device_1106_d238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e208 = { + 0xe208, pci_device_1106_e208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e238 = { + 0xe238, pci_device_1106_e238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f208 = { + 0xf208, pci_device_1106_f208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f238 = { + 0xf238, pci_device_1106_f238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f238, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0006 = { + 0x0006, pci_device_110a_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0015 = { + 0x0015, pci_device_110a_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_001d = { + 0x001d, pci_device_110a_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007b = { + 0x007b, pci_device_110a_007b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007c = { + 0x007c, pci_device_110a_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007d = { + 0x007d, pci_device_110a_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2101 = { + 0x2101, pci_device_110a_2101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2104 = { + 0x2104, pci_device_110a_2104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_3142 = { + 0x3142, pci_device_110a_3142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_3142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4021 = { + 0x4021, pci_device_110a_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4029 = { + 0x4029, pci_device_110a_4029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_d301 = { + 0xd301, pci_device_1113_d301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_d301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_ec02 = { + 0xec02, pci_device_1113_ec02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_ec02, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1114_0506 = { + 0x0506, pci_device_1114_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1114_0506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0010 = { + 0x0010, pci_device_1119_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0011 = { + 0x0011, pci_device_1119_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0012 = { + 0x0012, pci_device_1119_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0013 = { + 0x0013, pci_device_1119_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_02ff = { + 0x02ff, pci_device_1119_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_1203 = { + 0x1203, pci_device_111a_1203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_1203, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0004 = { + 0x0004, pci_device_111d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0005 = { + 0x0005, pci_device_111d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0008 = { + 0x0008, pci_device_112f_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5400 = { + 0x5400, pci_device_1131_5400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5402 = { + 0x5402, pci_device_1131_5402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5405 = { + 0x5405, pci_device_1131_5405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5406 = { + 0x5406, pci_device_1131_5406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_9730 = { + 0x9730, pci_device_1131_9730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_9730, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e006 = { + 0xe006, pci_device_1133_e006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e007 = { + 0xe007, pci_device_1133_e007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e008 = { + 0xe008, pci_device_1133_e008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e009 = { + 0xe009, pci_device_1133_e009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00a = { + 0xe00a, pci_device_1133_e00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00c = { + 0xe00c, pci_device_1133_e00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00d = { + 0xe00d, pci_device_1133_e00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00e = { + 0xe00e, pci_device_1133_e00e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e011 = { + 0xe011, pci_device_1133_e011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e013 = { + 0xe013, pci_device_1133_e013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e015 = { + 0xe015, pci_device_1133_e015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e016 = { + 0xe016, pci_device_1133_e016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e017 = { + 0xe017, pci_device_1133_e017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e019 = { + 0xe019, pci_device_1133_e019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01a = { + 0xe01a, pci_device_1133_e01a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01b = { + 0xe01b, pci_device_1133_e01b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01c = { + 0xe01c, pci_device_1133_e01c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01e = { + 0xe01e, pci_device_1133_e01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e020 = { + 0xe020, pci_device_1133_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e024 = { + 0xe024, pci_device_1133_e024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e028 = { + 0xe028, pci_device_1133_e028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02a = { + 0xe02a, pci_device_1133_e02a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02c = { + 0xe02c, pci_device_1133_e02c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1134_0002 = { + 0x0002, pci_device_1134_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f020 = { + 0xf020, pci_device_1145_f020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4500 = { + 0x4500, pci_device_1148_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9000 = { + 0x9000, pci_device_1148_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9843 = { + 0x9843, pci_device_1148_9843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9e00 = { + 0x9e00, pci_device_1148_9e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9e00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0028 = { + 0x0028, pci_device_114f_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0029 = { + 0x0029, pci_device_114f_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0043 = { + 0x0043, pci_device_114f_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0044 = { + 0x0044, pci_device_114f_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0045 = { + 0x0045, pci_device_114f_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_004e = { + 0x004e, pci_device_114f_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b0 = { + 0x00b0, pci_device_114f_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b1 = { + 0x00b1, pci_device_114f_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c8 = { + 0x00c8, pci_device_114f_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c9 = { + 0x00c9, pci_device_114f_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00ca = { + 0x00ca, pci_device_114f_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00cb = { + 0x00cb, pci_device_114f_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d0 = { + 0x00d0, pci_device_114f_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d1 = { + 0x00d1, pci_device_114f_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_00d4 = { + 0x00d4, pci_device_115d_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0000 = { + 0x0000, pci_device_1166_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0006 = { + 0x0006, pci_device_1166_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0036 = { + 0x0036, pci_device_1166_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0101 = { + 0x0101, pci_device_1166_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0104 = { + 0x0104, pci_device_1166_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0110 = { + 0x0110, pci_device_1166_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0130 = { + 0x0130, pci_device_1166_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0132 = { + 0x0132, pci_device_1166_0132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0205 = { + 0x0205, pci_device_1166_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0214 = { + 0x0214, pci_device_1166_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0217 = { + 0x0217, pci_device_1166_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0223 = { + 0x0223, pci_device_1166_0223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0230 = { + 0x0230, pci_device_1166_0230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0234 = { + 0x0234, pci_device_1166_0234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0240 = { + 0x0240, pci_device_1166_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0241 = { + 0x0241, pci_device_1166_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0242 = { + 0x0242, pci_device_1166_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024a = { + 0x024a, pci_device_1166_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0102 = { + 0x0102, pci_device_1179_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_117c_0030 = { + 0x0030, pci_device_117c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_117c_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0511 = { + 0x0511, pci_device_1180_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0554 = { + 0x0554, pci_device_1180_0554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0575 = { + 0x0575, pci_device_1180_0575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0576 = { + 0x0576, pci_device_1180_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0592 = { + 0x0592, pci_device_1180_0592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0811 = { + 0x0811, pci_device_1180_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0822 = { + 0x0822, pci_device_1180_0822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0841 = { + 0x0841, pci_device_1180_0841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0852 = { + 0x0852, pci_device_1180_0852, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0852, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1025 = { + 0x1025, pci_device_1186_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1026 = { + 0x1026, pci_device_1186_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1043 = { + 0x1043, pci_device_1186_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1541 = { + 0x1541, pci_device_1186_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_2027 = { + 0x2027, pci_device_1186_2027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_2027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3203 = { + 0x3203, pci_device_1186_3203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3300 = { + 0x3300, pci_device_1186_3300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a03 = { + 0x3a03, pci_device_1186_3a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a04 = { + 0x3a04, pci_device_1186_3a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a05 = { + 0x3a05, pci_device_1186_3a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a07 = { + 0x3a07, pci_device_1186_3a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a08 = { + 0x3a08, pci_device_1186_3a08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a10 = { + 0x3a10, pci_device_1186_3a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a11 = { + 0x3a11, pci_device_1186_3a11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a12 = { + 0x3a12, pci_device_1186_3a12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a13 = { + 0x3a13, pci_device_1186_3a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a14 = { + 0x3a14, pci_device_1186_3a14, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a14, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a63 = { + 0x3a63, pci_device_1186_3a63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4300 = { + 0x4300, pci_device_1186_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4c00 = { + 0x4c00, pci_device_1186_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_8400 = { + 0x8400, pci_device_1186_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_8400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8060 = { + 0x8060, pci_device_1191_8060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8080 = { + 0x8080, pci_device_1191_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8081 = { + 0x8081, pci_device_1191_8081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_808a = { + 0x808a, pci_device_1191_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_808a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1197_010c = { + 0x010c, pci_device_1197_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1197_010c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_138f = { + 0x138f, pci_device_11ab_138f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_138f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa6 = { + 0x1fa6, pci_device_11ab_1fa6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa7 = { + 0x1fa7, pci_device_11ab_1fa7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1faa = { + 0x1faa, pci_device_11ab_1faa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1faa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4320 = { + 0x4320, pci_device_11ab_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4340 = { + 0x4340, pci_device_11ab_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4341 = { + 0x4341, pci_device_11ab_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4342 = { + 0x4342, pci_device_11ab_4342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4343 = { + 0x4343, pci_device_11ab_4343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4344 = { + 0x4344, pci_device_11ab_4344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4345 = { + 0x4345, pci_device_11ab_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4346 = { + 0x4346, pci_device_11ab_4346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4347 = { + 0x4347, pci_device_11ab_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4350 = { + 0x4350, pci_device_11ab_4350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4351 = { + 0x4351, pci_device_11ab_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4352 = { + 0x4352, pci_device_11ab_4352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4360 = { + 0x4360, pci_device_11ab_4360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4361 = { + 0x4361, pci_device_11ab_4361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4362 = { + 0x4362, pci_device_11ab_4362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4363 = { + 0x4363, pci_device_11ab_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5005 = { + 0x5005, pci_device_11ab_5005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5040 = { + 0x5040, pci_device_11ab_5040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5041 = { + 0x5041, pci_device_11ab_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5080 = { + 0x5080, pci_device_11ab_5080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5081 = { + 0x5081, pci_device_11ab_5081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6041 = { + 0x6041, pci_device_11ab_6041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6081 = { + 0x6081, pci_device_11ab_6081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6460 = { + 0x6460, pci_device_11ab_6460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6480 = { + 0x6480, pci_device_11ab_6480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11af_0001 = { + 0x0001, pci_device_11af_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11af_ee40 = { + 0xee40, pci_device_11af_ee40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_ee40, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bd_002e = { + 0x002e, pci_device_11bd_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11bd_bede = { + 0xbede, pci_device_11bd_bede, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_bede, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048c = { + 0x048c, pci_device_11c1_048c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048f = { + 0x048f, pci_device_11c1_048f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_8110 = { + 0x8110, pci_device_11c1_8110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_8110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab10 = { + 0xab10, pci_device_11c1_ab10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab11 = { + 0xab11, pci_device_11c1_ab11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab20 = { + 0xab20, pci_device_11c1_ab20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab21 = { + 0xab21, pci_device_11c1_ab21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab30 = { + 0xab30, pci_device_11c1_ab30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ed00 = { + 0xed00, pci_device_11c1_ed00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ed00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1535 = { + 0x1535, pci_device_11d4_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_5340 = { + 0x5340, pci_device_11d4_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_5340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_0001 = { + 0x0001, pci_device_11e3_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000d = { + 0x000d, pci_device_11fe_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000e = { + 0x000e, pci_device_11fe_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000f = { + 0x000f, pci_device_11fe_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0801 = { + 0x0801, pci_device_11fe_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0802 = { + 0x0802, pci_device_11fe_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0803 = { + 0x0803, pci_device_11fe_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0805 = { + 0x0805, pci_device_11fe_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080c = { + 0x080c, pci_device_11fe_080c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080d = { + 0x080d, pci_device_11fe_080d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0812 = { + 0x0812, pci_device_11fe_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0903 = { + 0x0903, pci_device_11fe_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ff_0003 = { + 0x0003, pci_device_11ff_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ff_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7110 = { + 0x7110, pci_device_1217_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7112 = { + 0x7112, pci_device_1217_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7113 = { + 0x7113, pci_device_1217_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7114 = { + 0x7114, pci_device_1217_7114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7134 = { + 0x7134, pci_device_1217_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_71e2 = { + 0x71e2, pci_device_1217_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7212 = { + 0x7212, pci_device_1217_7212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7213 = { + 0x7213, pci_device_1217_7213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7223 = { + 0x7223, pci_device_1217_7223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7233 = { + 0x7233, pci_device_1217_7233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7233, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1227_0006 = { + 0x0006, pci_device_1227_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1227_0023 = { + 0x0023, pci_device_1227_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_1400 = { + 0x1400, pci_device_122d_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_6562 = { + 0x6562, pci_device_1242_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_656a = { + 0x656a, pci_device_1242_656a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_656a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2700 = { + 0x2700, pci_device_1244_2700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2900 = { + 0x2900, pci_device_1244_2900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2900, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a117 = { + 0xa117, pci_device_1259_a117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a117, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a120 = { + 0xa120, pci_device_1259_a120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0101 = { + 0x0101, pci_device_125c_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3872 = { + 0x3872, pci_device_1260_3872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3886 = { + 0x3886, pci_device_1260_3886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3890 = { + 0x3890, pci_device_1260_3890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_ffff = { + 0xffff, pci_device_1260_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_126c_1211 = { + 0x1211, pci_device_126c_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126c_126c = { + 0x126c, pci_device_126c_126c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_126c, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0501 = { + 0x0501, pci_device_126f_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0510 = { + 0x0510, pci_device_126f_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0730 = { + 0x0730, pci_device_126f_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1171 = { + 0x1171, pci_device_1274_1171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1278_0710 = { + 0x0710, pci_device_1278_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0710, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0060 = { + 0x0060, pci_device_1279_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0061 = { + 0x0061, pci_device_1279_0061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8211 = { + 0x8211, pci_device_1283_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8212 = { + 0x8212, pci_device_1283_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8872 = { + 0x8872, pci_device_1283_8872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12a3_8105 = { + 0x8105, pci_device_12a3_8105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12a3_8105, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_0002 = { + 0x0002, pci_device_12ab_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_00fa = { + 0x00fa, pci_device_12ae_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_00fa, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c4_0001 = { + 0x0001, pci_device_12c4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0002 = { + 0x0002, pci_device_12c4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0003 = { + 0x0003, pci_device_12c4_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0004 = { + 0x0004, pci_device_12c4_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0005 = { + 0x0005, pci_device_12c4_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0006 = { + 0x0006, pci_device_12c4_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0007 = { + 0x0007, pci_device_12c4_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0008 = { + 0x0008, pci_device_12c4_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0009 = { + 0x0009, pci_device_12c4_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000a = { + 0x000a, pci_device_12c4_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000b = { + 0x000b, pci_device_12c4_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000c = { + 0x000c, pci_device_12c4_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000d = { + 0x000d, pci_device_12c4_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0100 = { + 0x0100, pci_device_12c4_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0201 = { + 0x0201, pci_device_12c4_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0202 = { + 0x0202, pci_device_12c4_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0300 = { + 0x0300, pci_device_12c4_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0301 = { + 0x0301, pci_device_12c4_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0302 = { + 0x0302, pci_device_12c4_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0310 = { + 0x0310, pci_device_12c4_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0311 = { + 0x0311, pci_device_12c4_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0312 = { + 0x0312, pci_device_12c4_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0320 = { + 0x0320, pci_device_12c4_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0321 = { + 0x0321, pci_device_12c4_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0322 = { + 0x0322, pci_device_12c4_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0330 = { + 0x0330, pci_device_12c4_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0331 = { + 0x0331, pci_device_12c4_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0332 = { + 0x0332, pci_device_12c4_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0332, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d4_0200 = { + 0x0200, pci_device_12d4_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d4_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d5_0003 = { + 0x0003, pci_device_12d5_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d5_1000 = { + 0x1000, pci_device_12d5_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_1000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d8_8150 = { + 0x8150, pci_device_12d8_8150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d8_8150, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d9_0002 = { + 0x0002, pci_device_12d9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0004 = { + 0x0004, pci_device_12d9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0005 = { + 0x0005, pci_device_12d9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12de_0200 = { + 0x0200, pci_device_12de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12de_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12fb_0001 = { + 0x0001, pci_device_12fb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_00f5 = { + 0x00f5, pci_device_12fb_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_02ad = { + 0x02ad, pci_device_12fb_02ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_02ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_2adc = { + 0x2adc, pci_device_12fb_2adc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_2adc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3100 = { + 0x3100, pci_device_12fb_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3500 = { + 0x3500, pci_device_12fb_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_4d4f = { + 0x4d4f, pci_device_12fb_4d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_4d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_8120 = { + 0x8120, pci_device_12fb_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_da62 = { + 0xda62, pci_device_12fb_da62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_da62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_db62 = { + 0xdb62, pci_device_12fb_db62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_db62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dc62 = { + 0xdc62, pci_device_12fb_dc62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dc62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dd62 = { + 0xdd62, pci_device_12fb_dd62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dd62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_eddc = { + 0xeddc, pci_device_12fb_eddc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_eddc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_fa01 = { + 0xfa01, pci_device_12fb_fa01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_fa01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004d = { + 0x004d, pci_device_1307_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0052 = { + 0x0052, pci_device_1307_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0054 = { + 0x0054, pci_device_1307_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_005e = { + 0x005e, pci_device_1307_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_005e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_2850 = { + 0x2850, pci_device_1317_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_5120 = { + 0x5120, pci_device_1317_5120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_5120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8201 = { + 0x8201, pci_device_1317_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8211 = { + 0x8211, pci_device_1317_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_9511 = { + 0x9511, pci_device_1317_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2081 = { + 0x2081, pci_device_131f_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2081, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1331_0030 = { + 0x0030, pci_device_1331_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8200 = { + 0x8200, pci_device_1331_8200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8201 = { + 0x8201, pci_device_1331_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8202 = { + 0x8202, pci_device_1331_8202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8210 = { + 0x8210, pci_device_1331_8210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_5425 = { + 0x5425, pci_device_1332_5425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_6140 = { + 0x6140, pci_device_1332_6140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_6140, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_2189 = { + 0x2189, pci_device_134d_2189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_2486 = { + 0x2486, pci_device_134d_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_5101 = { + 0x5101, pci_device_135e_5101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_5101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1360_0101 = { + 0x0101, pci_device_1360_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0102 = { + 0x0102, pci_device_1360_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0103 = { + 0x0103, pci_device_1360_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0201 = { + 0x0201, pci_device_1360_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0202 = { + 0x0202, pci_device_1360_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0203 = { + 0x0203, pci_device_1360_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0301 = { + 0x0301, pci_device_1360_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0302 = { + 0x0302, pci_device_1360_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0302, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136b_ff01 = { + 0xff01, pci_device_136b_ff01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136b_ff01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1371_434e = { + 0x434e, pci_device_1371_434e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1371_434e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1374_0024 = { + 0x0024, pci_device_1374_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0025 = { + 0x0025, pci_device_1374_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0026 = { + 0x0026, pci_device_1374_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0027 = { + 0x0027, pci_device_1374_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0029 = { + 0x0029, pci_device_1374_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002a = { + 0x002a, pci_device_1374_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002b = { + 0x002b, pci_device_1374_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002c = { + 0x002c, pci_device_1374_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002d = { + 0x002d, pci_device_1374_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002e = { + 0x002e, pci_device_1374_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002f = { + 0x002f, pci_device_1374_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0030 = { + 0x0030, pci_device_1374_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0031 = { + 0x0031, pci_device_1374_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0032 = { + 0x0032, pci_device_1374_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0034 = { + 0x0034, pci_device_1374_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0035 = { + 0x0035, pci_device_1374_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0036 = { + 0x0036, pci_device_1374_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0037 = { + 0x0037, pci_device_1374_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0038 = { + 0x0038, pci_device_1374_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0039 = { + 0x0039, pci_device_1374_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_003a = { + 0x003a, pci_device_1374_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_003a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_137a_0001 = { + 0x0001, pci_device_137a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_137a_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1382_0001 = { + 0x0001, pci_device_1382_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2008 = { + 0x2008, pci_device_1382_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2088 = { + 0x2088, pci_device_1382_2088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_20c8 = { + 0x20c8, pci_device_1382_20c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_20c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4008 = { + 0x4008, pci_device_1382_4008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4010 = { + 0x4010, pci_device_1382_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4048 = { + 0x4048, pci_device_1382_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4088 = { + 0x4088, pci_device_1382_4088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4248 = { + 0x4248, pci_device_1382_4248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4424 = { + 0x4424, pci_device_1382_4424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4424, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_0013 = { + 0x0013, pci_device_1385_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_311a = { + 0x311a, pci_device_1385_311a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_311a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4105 = { + 0x4105, pci_device_1385_4105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4400 = { + 0x4400, pci_device_1385_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4600 = { + 0x4600, pci_device_1385_4600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4601 = { + 0x4601, pci_device_1385_4601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4610 = { + 0x4610, pci_device_1385_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4800 = { + 0x4800, pci_device_1385_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4900 = { + 0x4900, pci_device_1385_4900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4a00 = { + 0x4a00, pci_device_1385_4a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4b00 = { + 0x4b00, pci_device_1385_4b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4c00 = { + 0x4c00, pci_device_1385_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4d00 = { + 0x4d00, pci_device_1385_4d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4e00 = { + 0x4e00, pci_device_1385_4e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4f00 = { + 0x4f00, pci_device_1385_4f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_5200 = { + 0x5200, pci_device_1385_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6b00 = { + 0x6b00, pci_device_1385_6b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6d00 = { + 0x6d00, pci_device_1385_6d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f004 = { + 0xf004, pci_device_1385_f004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1141 = { + 0x1141, pci_device_1393_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_16b8 = { + 0x16b8, pci_device_1397_16b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_16b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_001d = { + 0x001d, pci_device_13a3_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0020 = { + 0x0020, pci_device_13a3_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0026 = { + 0x0026, pci_device_13a3_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0026, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0152 = { + 0x0152, pci_device_13a8_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0154 = { + 0x0154, pci_device_13a8_0154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0020 = { + 0x0020, pci_device_13c0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0030 = { + 0x0030, pci_device_13c0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0210 = { + 0x0210, pci_device_13c0_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1003 = { + 0x1003, pci_device_13c1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c6_0520 = { + 0x0520, pci_device_13c6_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0620 = { + 0x0620, pci_device_13c6_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0820 = { + 0x0820, pci_device_13c6_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d0_2200 = { + 0x2200, pci_device_13d0_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab03 = { + 0xab03, pci_device_13d1_ab03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab08 = { + 0xab08, pci_device_13d1_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0200 = { + 0x0200, pci_device_13f0_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_1023 = { + 0x1023, pci_device_13f0_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_1023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0011 = { + 0x0011, pci_device_13f6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1240 = { + 0x1240, pci_device_13fe_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1600 = { + 0x1600, pci_device_13fe_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1733 = { + 0x1733, pci_device_13fe_1733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1752 = { + 0x1752, pci_device_13fe_1752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1754 = { + 0x1754, pci_device_13fe_1754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0110 = { + 0x0110, pci_device_1407_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0111 = { + 0x0111, pci_device_1407_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0120 = { + 0x0120, pci_device_1407_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0121 = { + 0x0121, pci_device_1407_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0180 = { + 0x0180, pci_device_1407_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0181 = { + 0x0181, pci_device_1407_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0220 = { + 0x0220, pci_device_1407_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0221 = { + 0x0221, pci_device_1407_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9510 = { + 0x9510, pci_device_1415_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9523 = { + 0x9523, pci_device_1415_9523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9523, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1420_8002 = { + 0x8002, pci_device_1420_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1420_8003 = { + 0x8003, pci_device_1420_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1425_000b = { + 0x000b, pci_device_1425_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1425_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_142e_4020 = { + 0x4020, pci_device_142e_4020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_142e_4337 = { + 0x4337, pci_device_142e_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4337, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1432_9130 = { + 0x9130, pci_device_1432_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1432_9130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8164 = { + 0x8164, pci_device_144a_8164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1458_0c11 = { + 0x0c11, pci_device_1458_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1458_e911 = { + 0xe911, pci_device_1458_e911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_e911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1461_f436 = { + 0xf436, pci_device_1461_f436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_f436, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1462_5501 = { + 0x5501, pci_device_1462_5501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_5501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6819 = { + 0x6819, pci_device_1462_6819, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6819, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6825 = { + 0x6825, pci_device_1462_6825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6834 = { + 0x6834, pci_device_1462_6834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_8725 = { + 0x8725, pci_device_1462_8725, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_8725, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9000 = { + 0x9000, pci_device_1462_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9110 = { + 0x9110, pci_device_1462_9110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9119 = { + 0x9119, pci_device_1462_9119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9591 = { + 0x9591, pci_device_1462_9591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9591, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_146c_1430 = { + 0x1430, pci_device_146c_1430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_146c_1430, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1497_1497 = { + 0x1497, pci_device_1497_1497, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1497_1497, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1498_0330 = { + 0x0330, pci_device_1498_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_0385 = { + 0x0385, pci_device_1498_0385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_21cd = { + 0x21cd, pci_device_1498_21cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_30c8 = { + 0x30c8, pci_device_1498_30c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_30c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_149d_0001 = { + 0x0001, pci_device_149d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_149d_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a505 = { + 0xa505, pci_device_14b9_a505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a506 = { + 0xa506, pci_device_14b9_a506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14c1_8043 = { + 0x8043, pci_device_14c1_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_8043, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d9_0010 = { + 0x0010, pci_device_14d9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d9_9000 = { + 0x9000, pci_device_14d9_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_9000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14db_2182 = { + 0x2182, pci_device_14db_2182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2182, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_0800 = { + 0x0800, pci_device_14e4_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0804 = { + 0x0804, pci_device_14e4_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0805 = { + 0x0805, pci_device_14e4_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0806 = { + 0x0806, pci_device_14e4_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080b = { + 0x080b, pci_device_14e4_080b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080f = { + 0x080f, pci_device_14e4_080f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0811 = { + 0x0811, pci_device_14e4_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0816 = { + 0x0816, pci_device_14e4_0816, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0816, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1600 = { + 0x1600, pci_device_14e4_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1601 = { + 0x1601, pci_device_14e4_1601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164a = { + 0x164a, pci_device_14e4_164a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164c = { + 0x164c, pci_device_14e4_164c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1654 = { + 0x1654, pci_device_14e4_1654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1659 = { + 0x1659, pci_device_14e4_1659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165e = { + 0x165e, pci_device_14e4_165e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1668 = { + 0x1668, pci_device_14e4_1668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166a = { + 0x166a, pci_device_14e4_166a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166b = { + 0x166b, pci_device_14e4_166b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166e = { + 0x166e, pci_device_14e4_166e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1677 = { + 0x1677, pci_device_14e4_1677, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1677, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1678 = { + 0x1678, pci_device_14e4_1678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167d = { + 0x167d, pci_device_14e4_167d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167e = { + 0x167e, pci_device_14e4_167e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169c = { + 0x169c, pci_device_14e4_169c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169d = { + 0x169d, pci_device_14e4_169d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16aa = { + 0x16aa, pci_device_14e4_16aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16ac = { + 0x16ac, pci_device_14e4_16ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16dd = { + 0x16dd, pci_device_14e4_16dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16f7 = { + 0x16f7, pci_device_14e4_16f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fd = { + 0x16fd, pci_device_14e4_16fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fe = { + 0x16fe, pci_device_14e4_16fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170c = { + 0x170c, pci_device_14e4_170c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170d = { + 0x170d, pci_device_14e4_170d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170e = { + 0x170e, pci_device_14e4_170e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3352 = { + 0x3352, pci_device_14e4_3352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3360 = { + 0x3360, pci_device_14e4_3360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4305 = { + 0x4305, pci_device_14e4_4305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4306 = { + 0x4306, pci_device_14e4_4306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4307 = { + 0x4307, pci_device_14e4_4307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4310 = { + 0x4310, pci_device_14e4_4310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4312 = { + 0x4312, pci_device_14e4_4312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4313 = { + 0x4313, pci_device_14e4_4313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4315 = { + 0x4315, pci_device_14e4_4315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4318 = { + 0x4318, pci_device_14e4_4318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4319 = { + 0x4319, pci_device_14e4_4319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4320 = { + 0x4320, pci_device_14e4_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4321 = { + 0x4321, pci_device_14e4_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4322 = { + 0x4322, pci_device_14e4_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4324 = { + 0x4324, pci_device_14e4_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4325 = { + 0x4325, pci_device_14e4_4325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4326 = { + 0x4326, pci_device_14e4_4326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4403 = { + 0x4403, pci_device_14e4_4403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4430 = { + 0x4430, pci_device_14e4_4430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4432 = { + 0x4432, pci_device_14e4_4432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4610 = { + 0x4610, pci_device_14e4_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4611 = { + 0x4611, pci_device_14e4_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4612 = { + 0x4612, pci_device_14e4_4612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4613 = { + 0x4613, pci_device_14e4_4613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4614 = { + 0x4614, pci_device_14e4_4614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4615 = { + 0x4615, pci_device_14e4_4615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4704 = { + 0x4704, pci_device_14e4_4704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4704, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4705 = { + 0x4705, pci_device_14e4_4705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4705, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4706 = { + 0x4706, pci_device_14e4_4706, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4706, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4707 = { + 0x4707, pci_device_14e4_4707, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4707, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4708 = { + 0x4708, pci_device_14e4_4708, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4708, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4710 = { + 0x4710, pci_device_14e4_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4711 = { + 0x4711, pci_device_14e4_4711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4712 = { + 0x4712, pci_device_14e4_4712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4713 = { + 0x4713, pci_device_14e4_4713, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4713, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4714 = { + 0x4714, pci_device_14e4_4714, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4714, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4715 = { + 0x4715, pci_device_14e4_4715, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4715, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4716 = { + 0x4716, pci_device_14e4_4716, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4716, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4717 = { + 0x4717, pci_device_14e4_4717, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4717, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4718 = { + 0x4718, pci_device_14e4_4718, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4718, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4719 = { + 0x4719, pci_device_14e4_4719, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4719, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4720 = { + 0x4720, pci_device_14e4_4720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5365 = { + 0x5365, pci_device_14e4_5365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5600 = { + 0x5600, pci_device_14e4_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5605 = { + 0x5605, pci_device_14e4_5605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5615 = { + 0x5615, pci_device_14e4_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5625 = { + 0x5625, pci_device_14e4_5625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5645 = { + 0x5645, pci_device_14e4_5645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5670 = { + 0x5670, pci_device_14e4_5670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5680 = { + 0x5680, pci_device_14e4_5680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5690 = { + 0x5690, pci_device_14e4_5690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5691 = { + 0x5691, pci_device_14e4_5691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5692 = { + 0x5692, pci_device_14e4_5692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5822 = { + 0x5822, pci_device_14e4_5822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5823 = { + 0x5823, pci_device_14e4_5823, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5823, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5824 = { + 0x5824, pci_device_14e4_5824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5840 = { + 0x5840, pci_device_14e4_5840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5841 = { + 0x5841, pci_device_14e4_5841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5850 = { + 0x5850, pci_device_14e4_5850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5850, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab07 = { + 0xab07, pci_device_14ea_ab07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab08 = { + 0xab08, pci_device_14ea_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1085 = { + 0x1085, pci_device_14f1_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1620 = { + 0x1620, pci_device_14f1_1620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1621 = { + 0x1621, pci_device_14f1_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1622 = { + 0x1622, pci_device_14f1_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1811 = { + 0x1811, pci_device_14f1_1811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f02 = { + 0x2f02, pci_device_14f1_2f02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f11 = { + 0x2f11, pci_device_14f1_2f11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f20 = { + 0x2f20, pci_device_14f1_2f20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8800 = { + 0x8800, pci_device_14f1_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8801 = { + 0x8801, pci_device_14f1_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8802 = { + 0x8802, pci_device_14f1_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8804 = { + 0x8804, pci_device_14f1_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8811 = { + 0x8811, pci_device_14f1_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f2_0120 = { + 0x0120, pci_device_14f2_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0121 = { + 0x0121, pci_device_14f2_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0122 = { + 0x0122, pci_device_14f2_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0123 = { + 0x0123, pci_device_14f2_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0124 = { + 0x0124, pci_device_14f2_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0124, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f3_2030 = { + 0x2030, pci_device_14f3_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2050 = { + 0x2050, pci_device_14f3_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2060 = { + 0x2060, pci_device_14f3_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2060, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f8_2077 = { + 0x2077, pci_device_14f8_2077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f8_2077, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14fc_0000 = { + 0x0000, pci_device_14fc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0001 = { + 0x0001, pci_device_14fc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1500_1360 = { + 0x1360, pci_device_1500_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1500_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0800 = { + 0x0800, pci_device_1516_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0891 = { + 0x0891, pci_device_1516_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151c_0003 = { + 0x0003, pci_device_151c_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151c_4000 = { + 0x4000, pci_device_151c_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_0510 = { + 0x0510, pci_device_1524_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0520 = { + 0x0520, pci_device_1524_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0530 = { + 0x0530, pci_device_1524_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0550 = { + 0x0550, pci_device_1524_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0610 = { + 0x0610, pci_device_1524_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1411 = { + 0x1411, pci_device_1524_1411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1412 = { + 0x1412, pci_device_1524_1412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1421 = { + 0x1421, pci_device_1524_1421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1422 = { + 0x1422, pci_device_1524_1422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1422, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1532_0020 = { + 0x0020, pci_device_1532_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1532_0020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1538_0303 = { + 0x0303, pci_device_1538_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1538_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153b_1144 = { + 0x1144, pci_device_153b_1144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1147 = { + 0x1147, pci_device_153b_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1158 = { + 0x1158, pci_device_153b_1158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153f_0001 = { + 0x0001, pci_device_153f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1578_5615 = { + 0x5615, pci_device_1578_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1578_5615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0405 = { + 0x0405, pci_device_15ad_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0720 = { + 0x0720, pci_device_15ad_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0720, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a44 = { + 0x5a44, pci_device_15b3_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a45 = { + 0x5a45, pci_device_15b3_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a46 = { + 0x5a46, pci_device_15b3_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5e8d = { + 0x5e8d, pci_device_15b3_5e8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5e8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6274 = { + 0x6274, pci_device_15b3_6274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6278 = { + 0x6278, pci_device_15b3_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6279 = { + 0x6279, pci_device_15b3_6279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6282 = { + 0x6282, pci_device_15b3_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_1100 = { + 0x1100, pci_device_15bc_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2922 = { + 0x2922, pci_device_15bc_2922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2928 = { + 0x2928, pci_device_15bc_2928, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2928, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c5_8010 = { + 0x8010, pci_device_15c5_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c5_8010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e9_1841 = { + 0x1841, pci_device_15e9_1841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e9_1841, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15ec_3101 = { + 0x3101, pci_device_15ec_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ec_5102 = { + 0x5102, pci_device_15ec_5102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_5102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0610 = { + 0x0610, pci_device_1619_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0620 = { + 0x0620, pci_device_1619_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0640 = { + 0x0640, pci_device_1619_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_1610 = { + 0x1610, pci_device_1619_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_2610 = { + 0x2610, pci_device_1619_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_2610, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1626_8410 = { + 0x8410, pci_device_1626_8410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1626_8410, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1637_3874 = { + 0x3874, pci_device_1637_3874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1637_3874, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_3052 = { + 0x3052, pci_device_163c_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165f_1020 = { + 0x1020, pci_device_165f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165f_1020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1668_0100 = { + 0x0100, pci_device_1668_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1668_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_166d_0001 = { + 0x0001, pci_device_166d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_166d_0002 = { + 0x0002, pci_device_166d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1677_104e = { + 0x104e, pci_device_1677_104e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_104e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_12d7 = { + 0x12d7, pci_device_1677_12d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_12d7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167b_2102 = { + 0x2102, pci_device_167b_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167b_2102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1681_0010 = { + 0x0010, pci_device_1681_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1681_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1688_1170 = { + 0x1170, pci_device_1688_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1688_1170, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_168c_0007 = { + 0x0007, pci_device_168c_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0011 = { + 0x0011, pci_device_168c_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0012 = { + 0x0012, pci_device_168c_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0013 = { + 0x0013, pci_device_168c_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001a = { + 0x001a, pci_device_168c_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001b = { + 0x001b, pci_device_168c_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0020 = { + 0x0020, pci_device_168c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_1014 = { + 0x1014, pci_device_168c_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_1014, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_169c_0044 = { + 0x0044, pci_device_169c_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_169c_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1100 = { + 0x1100, pci_device_16ab_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1101 = { + 0x1101, pci_device_16ab_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_8501 = { + 0x8501, pci_device_16ab_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_8501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ae_1141 = { + 0x1141, pci_device_16ae_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ae_1141, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ca_0001 = { + 0x0001, pci_device_16ca_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ca_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e3_1e0f = { + 0x1e0f, pci_device_16e3_1e0f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e3_1e0f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_00ff = { + 0x00ff, pci_device_16ec_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_0116 = { + 0x0116, pci_device_16ec_0116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_0116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ed_1001 = { + 0x1001, pci_device_16ed_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ed_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16f4_8000 = { + 0x8000, pci_device_16f4_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16f4_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_170b_0100 = { + 0x0100, pci_device_170b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_170b_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1725_7174 = { + 0x7174, pci_device_1725_7174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1725_7174, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_172a_13c8 = { + 0x13c8, pci_device_172a_13c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_172a_13c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1737_0013 = { + 0x0013, pci_device_1737_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_0015 = { + 0x0015, pci_device_1737_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1032 = { + 0x1032, pci_device_1737_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1064 = { + 0x1064, pci_device_1737_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab08 = { + 0xab08, pci_device_1737_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab09 = { + 0xab09, pci_device_1737_ab09, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab09, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03e9 = { + 0x03e9, pci_device_173b_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03eb = { + 0x03eb, pci_device_173b_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03eb, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1799_6001 = { + 0x6001, pci_device_1799_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6020 = { + 0x6020, pci_device_1799_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6060 = { + 0x6060, pci_device_1799_6060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7000 = { + 0x7000, pci_device_1799_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7010 = { + 0x7010, pci_device_1799_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_179c_0557 = { + 0x0557, pci_device_179c_0557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_0566 = { + 0x0566, pci_device_179c_0566, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0566, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5031 = { + 0x5031, pci_device_179c_5031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5121 = { + 0x5121, pci_device_179c_5121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5211 = { + 0x5211, pci_device_179c_5211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5679 = { + 0x5679, pci_device_179c_5679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5679, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17a0_8033 = { + 0x8033, pci_device_17a0_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17a0_8034 = { + 0x8034, pci_device_17a0_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8034, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b3_ab08 = { + 0xab08, pci_device_17b3_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b3_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b4_0011 = { + 0x0011, pci_device_17b4_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b4_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d3_1110 = { + 0x1110, pci_device_17d3_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1120 = { + 0x1120, pci_device_17d3_1120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1130 = { + 0x1130, pci_device_17d3_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1160 = { + 0x1160, pci_device_17d3_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1210 = { + 0x1210, pci_device_17d3_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1220 = { + 0x1220, pci_device_17d3_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1230 = { + 0x1230, pci_device_17d3_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1260 = { + 0x1260, pci_device_17d3_1260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1260, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d5_5831 = { + 0x5831, pci_device_17d5_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d5_5832 = { + 0x5832, pci_device_17d5_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5832, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17fe_2120 = { + 0x2120, pci_device_17fe_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17fe_2220 = { + 0x2220, pci_device_17fe_2220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1814_0101 = { + 0x0101, pci_device_1814_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0200 = { + 0x0200, pci_device_1814_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0201 = { + 0x0201, pci_device_1814_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0301 = { + 0x0301, pci_device_1814_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0401 = { + 0x0401, pci_device_1814_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1822_4e35 = { + 0x4e35, pci_device_1822_4e35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1822_4e35, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182d_3069 = { + 0x3069, pci_device_182d_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_3069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_182d_9790 = { + 0x9790, pci_device_182d_9790, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_9790, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_183b_08a7 = { + 0x08a7, pci_device_183b_08a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a8 = { + 0x08a8, pci_device_183b_08a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a9 = { + 0x08a9, pci_device_183b_08a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a9, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1864_2110 = { + 0x2110, pci_device_1864_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1864_2110, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1867_5a44 = { + 0x5a44, pci_device_1867_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a45 = { + 0x5a45, pci_device_1867_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a46 = { + 0x5a46, pci_device_1867_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6278 = { + 0x6278, pci_device_1867_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6282 = { + 0x6282, pci_device_1867_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ac_d500 = { + 0xd500, pci_device_18ac_d500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d810 = { + 0xd810, pci_device_18ac_d810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d820 = { + 0xd820, pci_device_18ac_d820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18b8_b001 = { + 0xb001, pci_device_18b8_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18b8_b001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ca_0020 = { + 0x0020, pci_device_18ca_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ca_0040 = { + 0x0040, pci_device_18ca_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18d2_3069 = { + 0x3069, pci_device_18d2_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18d2_3069, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18dd_4c6f = { + 0x4c6f, pci_device_18dd_4c6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18dd_4c6f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18e6_0001 = { + 0x0001, pci_device_18e6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18e6_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ec_c006 = { + 0xc006, pci_device_18ec_c006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c045 = { + 0xc045, pci_device_18ec_c045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c050 = { + 0xc050, pci_device_18ec_c050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c058 = { + 0xc058, pci_device_18ec_c058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c058, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f7_0001 = { + 0x0001, pci_device_18f7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0002 = { + 0x0002, pci_device_18f7_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0004 = { + 0x0004, pci_device_18f7_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0005 = { + 0x0005, pci_device_18f7_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_000a = { + 0x000a, pci_device_18f7_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1923_0100 = { + 0x0100, pci_device_1923_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1942_e511 = { + 0xe511, pci_device_1942_e511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1942_e511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1957_0080 = { + 0x0080, pci_device_1957_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0081 = { + 0x0081, pci_device_1957_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0082 = { + 0x0082, pci_device_1957_0082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0083 = { + 0x0083, pci_device_1957_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0084 = { + 0x0084, pci_device_1957_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0085 = { + 0x0085, pci_device_1957_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0086 = { + 0x0086, pci_device_1957_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0087 = { + 0x0087, pci_device_1957_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0087, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1966_1975 = { + 0x1975, pci_device_1966_1975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1966_1975, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_196a_0101 = { + 0x0101, pci_device_196a_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_196a_0102 = { + 0x0102, pci_device_196a_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_197b_2360 = { + 0x2360, pci_device_197b_2360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2363 = { + 0x2363, pci_device_197b_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2363, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1989_0001 = { + 0x0001, pci_device_1989_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1989_8001 = { + 0x8001, pci_device_1989_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ae_0520 = { + 0x0520, pci_device_19ae_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ae_0520, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc0_0300 = { + 0x0300, pci_device_1fc0_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc0_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc1_000d = { + 0x000d, pci_device_1fc1_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_000d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fce_0001 = { + 0x0001, pci_device_1fce_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fce_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0020 = { + 0x0020, pci_device_3388_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0022 = { + 0x0022, pci_device_3388_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0026 = { + 0x0026, pci_device_3388_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101a = { + 0x101a, pci_device_3388_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101b = { + 0x101b, pci_device_3388_101b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3842_c370 = { + 0xc370, pci_device_3842_c370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3842_c370, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000d = { + 0x000d, pci_device_3d3d_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0011 = { + 0x0011, pci_device_3d3d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0012 = { + 0x0012, pci_device_3d3d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0013 = { + 0x0013, pci_device_3d3d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0020 = { + 0x0020, pci_device_3d3d_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0022 = { + 0x0022, pci_device_3d3d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0024 = { + 0x0024, pci_device_3d3d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a1 = { + 0x07a1, pci_device_3d3d_07a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a2 = { + 0x07a2, pci_device_3d3d_07a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a3 = { + 0x07a3, pci_device_3d3d_07a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4144_0044 = { + 0x0044, pci_device_4144_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4144_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0016 = { + 0x0016, pci_device_4444_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_494f_10e8 = { + 0x10e8, pci_device_494f_10e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_494f_10e8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4c53_0000 = { + 0x0000, pci_device_4c53_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4c53_0001 = { + 0x0001, pci_device_4c53_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5168_0301 = { + 0x0301, pci_device_5168_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_544c_0350 = { + 0x0350, pci_device_544c_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_544c_0350, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5654_3132 = { + 0x3132, pci_device_5654_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5654_3132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0004 = { + 0x0004, pci_device_6666_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0101 = { + 0x0101, pci_device_6666_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_7063_2000 = { + 0x2000, pci_device_7063_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_3000 = { + 0x3000, pci_device_7063_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0309 = { + 0x0309, pci_device_8086_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_030d = { + 0x030d, pci_device_8086_030d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_030d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0326 = { + 0x0326, pci_device_8086_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0327 = { + 0x0327, pci_device_8086_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0329 = { + 0x0329, pci_device_8086_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032a = { + 0x032a, pci_device_8086_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032c = { + 0x032c, pci_device_8086_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0330 = { + 0x0330, pci_device_8086_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0331 = { + 0x0331, pci_device_8086_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0332 = { + 0x0332, pci_device_8086_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0333 = { + 0x0333, pci_device_8086_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0334 = { + 0x0334, pci_device_8086_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0335 = { + 0x0335, pci_device_8086_0335, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0335, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0336 = { + 0x0336, pci_device_8086_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0340 = { + 0x0340, pci_device_8086_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0341 = { + 0x0341, pci_device_8086_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0370 = { + 0x0370, pci_device_8086_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0371 = { + 0x0371, pci_device_8086_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0372 = { + 0x0372, pci_device_8086_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0373 = { + 0x0373, pci_device_8086_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0374 = { + 0x0374, pci_device_8086_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0500 = { + 0x0500, pci_device_8086_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0501 = { + 0x0501, pci_device_8086_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0502 = { + 0x0502, pci_device_8086_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0503 = { + 0x0503, pci_device_8086_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0510 = { + 0x0510, pci_device_8086_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0511 = { + 0x0511, pci_device_8086_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0512 = { + 0x0512, pci_device_8086_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0513 = { + 0x0513, pci_device_8086_0513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0514 = { + 0x0514, pci_device_8086_0514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0515 = { + 0x0515, pci_device_8086_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0516 = { + 0x0516, pci_device_8086_0516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0530 = { + 0x0530, pci_device_8086_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0531 = { + 0x0531, pci_device_8086_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0532 = { + 0x0532, pci_device_8086_0532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0533 = { + 0x0533, pci_device_8086_0533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0534 = { + 0x0534, pci_device_8086_0534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0535 = { + 0x0535, pci_device_8086_0535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0536 = { + 0x0536, pci_device_8086_0536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0537 = { + 0x0537, pci_device_8086_0537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_061f = { + 0x061f, pci_device_8086_061f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_061f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100a = { + 0x100a, pci_device_8086_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1013 = { + 0x1013, pci_device_8086_1013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1014 = { + 0x1014, pci_device_8086_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1016 = { + 0x1016, pci_device_8086_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1017 = { + 0x1017, pci_device_8086_1017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1018 = { + 0x1018, pci_device_8086_1018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1019 = { + 0x1019, pci_device_8086_1019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101a = { + 0x101a, pci_device_8086_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101d = { + 0x101d, pci_device_8086_101d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101e = { + 0x101e, pci_device_8086_101e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1026 = { + 0x1026, pci_device_8086_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1027 = { + 0x1027, pci_device_8086_1027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1028 = { + 0x1028, pci_device_8086_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1043 = { + 0x1043, pci_device_8086_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1048 = { + 0x1048, pci_device_8086_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104b = { + 0x104b, pci_device_8086_104b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1050 = { + 0x1050, pci_device_8086_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1051 = { + 0x1051, pci_device_8086_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1052 = { + 0x1052, pci_device_8086_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1053 = { + 0x1053, pci_device_8086_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105e = { + 0x105e, pci_device_8086_105e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105f = { + 0x105f, pci_device_8086_105f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1060 = { + 0x1060, pci_device_8086_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1064 = { + 0x1064, pci_device_8086_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1065 = { + 0x1065, pci_device_8086_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1066 = { + 0x1066, pci_device_8086_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1067 = { + 0x1067, pci_device_8086_1067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1068 = { + 0x1068, pci_device_8086_1068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1069 = { + 0x1069, pci_device_8086_1069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106a = { + 0x106a, pci_device_8086_106a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106b = { + 0x106b, pci_device_8086_106b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1075 = { + 0x1075, pci_device_8086_1075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1076 = { + 0x1076, pci_device_8086_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1077 = { + 0x1077, pci_device_8086_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1078 = { + 0x1078, pci_device_8086_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1079 = { + 0x1079, pci_device_8086_1079, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1079, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107a = { + 0x107a, pci_device_8086_107a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107b = { + 0x107b, pci_device_8086_107b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107c = { + 0x107c, pci_device_8086_107c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107d = { + 0x107d, pci_device_8086_107d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107e = { + 0x107e, pci_device_8086_107e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107f = { + 0x107f, pci_device_8086_107f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1080 = { + 0x1080, pci_device_8086_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1081 = { + 0x1081, pci_device_8086_1081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1082 = { + 0x1082, pci_device_8086_1082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1083 = { + 0x1083, pci_device_8086_1083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1084 = { + 0x1084, pci_device_8086_1084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1085 = { + 0x1085, pci_device_8086_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1086 = { + 0x1086, pci_device_8086_1086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1087 = { + 0x1087, pci_device_8086_1087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1089 = { + 0x1089, pci_device_8086_1089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108a = { + 0x108a, pci_device_8086_108a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108b = { + 0x108b, pci_device_8086_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108c = { + 0x108c, pci_device_8086_108c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1096 = { + 0x1096, pci_device_8086_1096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1097 = { + 0x1097, pci_device_8086_1097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1098 = { + 0x1098, pci_device_8086_1098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1099 = { + 0x1099, pci_device_8086_1099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109a = { + 0x109a, pci_device_8086_109a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1107 = { + 0x1107, pci_device_8086_1107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123e = { + 0x123e, pci_device_8086_123e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a38 = { + 0x1a38, pci_device_8086_1a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a48 = { + 0x1a48, pci_device_8086_1a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c1 = { + 0x24c1, pci_device_8086_24c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24ca = { + 0x24ca, pci_device_8086_24ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cc = { + 0x24cc, pci_device_8086_24cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d0 = { + 0x24d0, pci_device_8086_24d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d1 = { + 0x24d1, pci_device_8086_24d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d2 = { + 0x24d2, pci_device_8086_24d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d3 = { + 0x24d3, pci_device_8086_24d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d4 = { + 0x24d4, pci_device_8086_24d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d5 = { + 0x24d5, pci_device_8086_24d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d6 = { + 0x24d6, pci_device_8086_24d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d7 = { + 0x24d7, pci_device_8086_24d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24db = { + 0x24db, pci_device_8086_24db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dc = { + 0x24dc, pci_device_8086_24dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dd = { + 0x24dd, pci_device_8086_24dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24de = { + 0x24de, pci_device_8086_24de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24df = { + 0x24df, pci_device_8086_24df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_254c = { + 0x254c, pci_device_8086_254c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_254c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2550 = { + 0x2550, pci_device_8086_2550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2551 = { + 0x2551, pci_device_8086_2551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2552 = { + 0x2552, pci_device_8086_2552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2553 = { + 0x2553, pci_device_8086_2553, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2553, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2554 = { + 0x2554, pci_device_8086_2554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_255d = { + 0x255d, pci_device_8086_255d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_255d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2571 = { + 0x2571, pci_device_8086_2571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2573 = { + 0x2573, pci_device_8086_2573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2576 = { + 0x2576, pci_device_8086_2576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2578 = { + 0x2578, pci_device_8086_2578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2579 = { + 0x2579, pci_device_8086_2579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257b = { + 0x257b, pci_device_8086_257b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257e = { + 0x257e, pci_device_8086_257e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2580 = { + 0x2580, pci_device_8086_2580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2581 = { + 0x2581, pci_device_8086_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2582 = { + 0x2582, pci_device_8086_2582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2584 = { + 0x2584, pci_device_8086_2584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2585 = { + 0x2585, pci_device_8086_2585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2588 = { + 0x2588, pci_device_8086_2588, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2588, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2589 = { + 0x2589, pci_device_8086_2589, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2589, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_258a = { + 0x258a, pci_device_8086_258a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_258a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2590 = { + 0x2590, pci_device_8086_2590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2591 = { + 0x2591, pci_device_8086_2591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2592 = { + 0x2592, pci_device_8086_2592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a1 = { + 0x25a1, pci_device_8086_25a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a2 = { + 0x25a2, pci_device_8086_25a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a3 = { + 0x25a3, pci_device_8086_25a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a4 = { + 0x25a4, pci_device_8086_25a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a6 = { + 0x25a6, pci_device_8086_25a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a7 = { + 0x25a7, pci_device_8086_25a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a9 = { + 0x25a9, pci_device_8086_25a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25aa = { + 0x25aa, pci_device_8086_25aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ab = { + 0x25ab, pci_device_8086_25ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ac = { + 0x25ac, pci_device_8086_25ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ad = { + 0x25ad, pci_device_8086_25ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ae = { + 0x25ae, pci_device_8086_25ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25b0 = { + 0x25b0, pci_device_8086_25b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25c0 = { + 0x25c0, pci_device_8086_25c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d0 = { + 0x25d0, pci_device_8086_25d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d4 = { + 0x25d4, pci_device_8086_25d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d8 = { + 0x25d8, pci_device_8086_25d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e2 = { + 0x25e2, pci_device_8086_25e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e3 = { + 0x25e3, pci_device_8086_25e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e4 = { + 0x25e4, pci_device_8086_25e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e5 = { + 0x25e5, pci_device_8086_25e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e6 = { + 0x25e6, pci_device_8086_25e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e7 = { + 0x25e7, pci_device_8086_25e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e8 = { + 0x25e8, pci_device_8086_25e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f0 = { + 0x25f0, pci_device_8086_25f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f1 = { + 0x25f1, pci_device_8086_25f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f3 = { + 0x25f3, pci_device_8086_25f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f5 = { + 0x25f5, pci_device_8086_25f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f6 = { + 0x25f6, pci_device_8086_25f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f7 = { + 0x25f7, pci_device_8086_25f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f8 = { + 0x25f8, pci_device_8086_25f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f9 = { + 0x25f9, pci_device_8086_25f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25fa = { + 0x25fa, pci_device_8086_25fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2600 = { + 0x2600, pci_device_8086_2600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2601 = { + 0x2601, pci_device_8086_2601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2602 = { + 0x2602, pci_device_8086_2602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2603 = { + 0x2603, pci_device_8086_2603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2604 = { + 0x2604, pci_device_8086_2604, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2604, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2605 = { + 0x2605, pci_device_8086_2605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2606 = { + 0x2606, pci_device_8086_2606, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2606, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2607 = { + 0x2607, pci_device_8086_2607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2608 = { + 0x2608, pci_device_8086_2608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2609 = { + 0x2609, pci_device_8086_2609, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2609, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260a = { + 0x260a, pci_device_8086_260a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260c = { + 0x260c, pci_device_8086_260c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2610 = { + 0x2610, pci_device_8086_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2611 = { + 0x2611, pci_device_8086_2611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2612 = { + 0x2612, pci_device_8086_2612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2613 = { + 0x2613, pci_device_8086_2613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2614 = { + 0x2614, pci_device_8086_2614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2615 = { + 0x2615, pci_device_8086_2615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2617 = { + 0x2617, pci_device_8086_2617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2618 = { + 0x2618, pci_device_8086_2618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2619 = { + 0x2619, pci_device_8086_2619, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2619, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261a = { + 0x261a, pci_device_8086_261a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261b = { + 0x261b, pci_device_8086_261b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261c = { + 0x261c, pci_device_8086_261c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261d = { + 0x261d, pci_device_8086_261d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261e = { + 0x261e, pci_device_8086_261e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2620 = { + 0x2620, pci_device_8086_2620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2621 = { + 0x2621, pci_device_8086_2621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2622 = { + 0x2622, pci_device_8086_2622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2623 = { + 0x2623, pci_device_8086_2623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2624 = { + 0x2624, pci_device_8086_2624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2625 = { + 0x2625, pci_device_8086_2625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2626 = { + 0x2626, pci_device_8086_2626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2627 = { + 0x2627, pci_device_8086_2627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2640 = { + 0x2640, pci_device_8086_2640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2641 = { + 0x2641, pci_device_8086_2641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2642 = { + 0x2642, pci_device_8086_2642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2651 = { + 0x2651, pci_device_8086_2651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2652 = { + 0x2652, pci_device_8086_2652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2653 = { + 0x2653, pci_device_8086_2653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2658 = { + 0x2658, pci_device_8086_2658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2659 = { + 0x2659, pci_device_8086_2659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265a = { + 0x265a, pci_device_8086_265a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265b = { + 0x265b, pci_device_8086_265b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265c = { + 0x265c, pci_device_8086_265c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2660 = { + 0x2660, pci_device_8086_2660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2662 = { + 0x2662, pci_device_8086_2662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2664 = { + 0x2664, pci_device_8086_2664, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2664, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2666 = { + 0x2666, pci_device_8086_2666, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2666, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2668 = { + 0x2668, pci_device_8086_2668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266a = { + 0x266a, pci_device_8086_266a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266c = { + 0x266c, pci_device_8086_266c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266d = { + 0x266d, pci_device_8086_266d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266e = { + 0x266e, pci_device_8086_266e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266f = { + 0x266f, pci_device_8086_266f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2670 = { + 0x2670, pci_device_8086_2670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2680 = { + 0x2680, pci_device_8086_2680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2681 = { + 0x2681, pci_device_8086_2681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2682 = { + 0x2682, pci_device_8086_2682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2683 = { + 0x2683, pci_device_8086_2683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2688 = { + 0x2688, pci_device_8086_2688, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2688, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2689 = { + 0x2689, pci_device_8086_2689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268a = { + 0x268a, pci_device_8086_268a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268b = { + 0x268b, pci_device_8086_268b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268c = { + 0x268c, pci_device_8086_268c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2690 = { + 0x2690, pci_device_8086_2690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2692 = { + 0x2692, pci_device_8086_2692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2694 = { + 0x2694, pci_device_8086_2694, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2694, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2696 = { + 0x2696, pci_device_8086_2696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2698 = { + 0x2698, pci_device_8086_2698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2699 = { + 0x2699, pci_device_8086_2699, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2699, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269a = { + 0x269a, pci_device_8086_269a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269b = { + 0x269b, pci_device_8086_269b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269e = { + 0x269e, pci_device_8086_269e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2770 = { + 0x2770, pci_device_8086_2770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2771 = { + 0x2771, pci_device_8086_2771, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2771, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2772 = { + 0x2772, pci_device_8086_2772, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2772, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2774 = { + 0x2774, pci_device_8086_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2775 = { + 0x2775, pci_device_8086_2775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2776 = { + 0x2776, pci_device_8086_2776, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2776, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2778 = { + 0x2778, pci_device_8086_2778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2779 = { + 0x2779, pci_device_8086_2779, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2779, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277a = { + 0x277a, pci_device_8086_277a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277c = { + 0x277c, pci_device_8086_277c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277d = { + 0x277d, pci_device_8086_277d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2782 = { + 0x2782, pci_device_8086_2782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2792 = { + 0x2792, pci_device_8086_2792, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2792, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a0 = { + 0x27a0, pci_device_8086_27a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a1 = { + 0x27a1, pci_device_8086_27a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a2 = { + 0x27a2, pci_device_8086_27a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a6 = { + 0x27a6, pci_device_8086_27a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b0 = { + 0x27b0, pci_device_8086_27b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b8 = { + 0x27b8, pci_device_8086_27b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b9 = { + 0x27b9, pci_device_8086_27b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27bd = { + 0x27bd, pci_device_8086_27bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c0 = { + 0x27c0, pci_device_8086_27c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c1 = { + 0x27c1, pci_device_8086_27c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c3 = { + 0x27c3, pci_device_8086_27c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c4 = { + 0x27c4, pci_device_8086_27c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c5 = { + 0x27c5, pci_device_8086_27c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c6 = { + 0x27c6, pci_device_8086_27c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c8 = { + 0x27c8, pci_device_8086_27c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c9 = { + 0x27c9, pci_device_8086_27c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27ca = { + 0x27ca, pci_device_8086_27ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cb = { + 0x27cb, pci_device_8086_27cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cc = { + 0x27cc, pci_device_8086_27cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d0 = { + 0x27d0, pci_device_8086_27d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d2 = { + 0x27d2, pci_device_8086_27d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d4 = { + 0x27d4, pci_device_8086_27d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d6 = { + 0x27d6, pci_device_8086_27d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d8 = { + 0x27d8, pci_device_8086_27d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27da = { + 0x27da, pci_device_8086_27da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dc = { + 0x27dc, pci_device_8086_27dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dd = { + 0x27dd, pci_device_8086_27dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27de = { + 0x27de, pci_device_8086_27de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27df = { + 0x27df, pci_device_8086_27df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e0 = { + 0x27e0, pci_device_8086_27e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e2 = { + 0x27e2, pci_device_8086_27e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2810 = { + 0x2810, pci_device_8086_2810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2811 = { + 0x2811, pci_device_8086_2811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2812 = { + 0x2812, pci_device_8086_2812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2814 = { + 0x2814, pci_device_8086_2814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2815 = { + 0x2815, pci_device_8086_2815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2820 = { + 0x2820, pci_device_8086_2820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2821 = { + 0x2821, pci_device_8086_2821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2822 = { + 0x2822, pci_device_8086_2822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2824 = { + 0x2824, pci_device_8086_2824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2825 = { + 0x2825, pci_device_8086_2825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2828 = { + 0x2828, pci_device_8086_2828, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2828, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2829 = { + 0x2829, pci_device_8086_2829, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2829, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_282a = { + 0x282a, pci_device_8086_282a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_282a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2830 = { + 0x2830, pci_device_8086_2830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2831 = { + 0x2831, pci_device_8086_2831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2832 = { + 0x2832, pci_device_8086_2832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2834 = { + 0x2834, pci_device_8086_2834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2835 = { + 0x2835, pci_device_8086_2835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2836 = { + 0x2836, pci_device_8086_2836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283a = { + 0x283a, pci_device_8086_283a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283e = { + 0x283e, pci_device_8086_283e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283f = { + 0x283f, pci_device_8086_283f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2841 = { + 0x2841, pci_device_8086_2841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2843 = { + 0x2843, pci_device_8086_2843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2844 = { + 0x2844, pci_device_8086_2844, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2844, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2847 = { + 0x2847, pci_device_8086_2847, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2847, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2849 = { + 0x2849, pci_device_8086_2849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284b = { + 0x284b, pci_device_8086_284b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284f = { + 0x284f, pci_device_8086_284f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2850 = { + 0x2850, pci_device_8086_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2970 = { + 0x2970, pci_device_8086_2970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2971 = { + 0x2971, pci_device_8086_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2971, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2972 = { + 0x2972, pci_device_8086_2972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2973 = { + 0x2973, pci_device_8086_2973, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2973, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3200 = { + 0x3200, pci_device_8086_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3340 = { + 0x3340, pci_device_8086_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3341 = { + 0x3341, pci_device_8086_3341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3500 = { + 0x3500, pci_device_8086_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3501 = { + 0x3501, pci_device_8086_3501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3504 = { + 0x3504, pci_device_8086_3504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3505 = { + 0x3505, pci_device_8086_3505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350c = { + 0x350c, pci_device_8086_350c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350d = { + 0x350d, pci_device_8086_350d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3510 = { + 0x3510, pci_device_8086_3510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3511 = { + 0x3511, pci_device_8086_3511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3514 = { + 0x3514, pci_device_8086_3514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3515 = { + 0x3515, pci_device_8086_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3518 = { + 0x3518, pci_device_8086_3518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3519 = { + 0x3519, pci_device_8086_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3581 = { + 0x3581, pci_device_8086_3581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3584 = { + 0x3584, pci_device_8086_3584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3585 = { + 0x3585, pci_device_8086_3585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3590 = { + 0x3590, pci_device_8086_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3591 = { + 0x3591, pci_device_8086_3591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3592 = { + 0x3592, pci_device_8086_3592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3593 = { + 0x3593, pci_device_8086_3593, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3593, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3594 = { + 0x3594, pci_device_8086_3594, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3594, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3595 = { + 0x3595, pci_device_8086_3595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3596 = { + 0x3596, pci_device_8086_3596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3597 = { + 0x3597, pci_device_8086_3597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3598 = { + 0x3598, pci_device_8086_3598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3599 = { + 0x3599, pci_device_8086_3599, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3599, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359a = { + 0x359a, pci_device_8086_359a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359b = { + 0x359b, pci_device_8086_359b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359e = { + 0x359e, pci_device_8086_359e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4220 = { + 0x4220, pci_device_8086_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4223 = { + 0x4223, pci_device_8086_4223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4224 = { + 0x4224, pci_device_8086_4224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7050 = { + 0x7050, pci_device_8086_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7051 = { + 0x7051, pci_device_8086_7051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_8500 = { + 0x8500, pci_device_8086_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9000 = { + 0x9000, pci_device_8086_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9001 = { + 0x9001, pci_device_8086_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9004 = { + 0x9004, pci_device_8086_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8c4a_1980 = { + 0x1980, pci_device_8c4a_1980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8c4a_1980, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_0078 = { + 0x0078, pci_device_9004_0078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_0078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7710 = { + 0x7710, pci_device_9004_7710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7711 = { + 0x7711, pci_device_9004_7711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#define pci_dev_list_0070 NULL +#define pci_dev_list_0071 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0095[] = { + &pci_dev_info_0095_0680, + NULL +}; +#endif +#define pci_dev_list_00a7 NULL +#define pci_dev_list_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_018a[] = { + &pci_dev_info_018a_0106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_021b[] = { + &pci_dev_info_021b_8139, + NULL +}; +#endif +#define pci_dev_list_0270 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0291[] = { + &pci_dev_info_0291_8212, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_02ac[] = { + &pci_dev_info_02ac_1012, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0357[] = { + &pci_dev_info_0357_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0432[] = { + &pci_dev_info_0432_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_045e[] = { + &pci_dev_info_045e_006e, + &pci_dev_info_045e_00c2, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_04cf[] = { + &pci_dev_info_04cf_8818, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_050d[] = { + &pci_dev_info_050d_7050, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05e3[] = { + &pci_dev_info_05e3_0701, + NULL +}; +#endif +#define pci_dev_list_066f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + &pci_dev_info_0675_1703, + &pci_dev_info_0675_1704, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_067b[] = { + &pci_dev_info_067b_3507, + NULL +}; +#endif +#define pci_dev_list_0721 NULL +#define pci_dev_list_07e2 NULL +#define pci_dev_list_0925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b49[] = { + &pci_dev_info_0b49_064f, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0046, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_005a, + &pci_dev_info_0e11_007c, + &pci_dev_info_0e11_007d, + &pci_dev_info_0e11_0085, + &pci_dev_info_0e11_00b1, + &pci_dev_info_0e11_00bb, + &pci_dev_info_0e11_00ca, + &pci_dev_info_0e11_00cb, + &pci_dev_info_0e11_00cf, + &pci_dev_info_0e11_00d0, + &pci_dev_info_0e11_00d1, + &pci_dev_info_0e11_00e3, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_4030, + &pci_dev_info_0e11_4031, + &pci_dev_info_0e11_4032, + &pci_dev_info_0e11_4033, + &pci_dev_info_0e11_4034, + &pci_dev_info_0e11_4040, + &pci_dev_info_0e11_4048, + &pci_dev_info_0e11_4050, + &pci_dev_info_0e11_4051, + &pci_dev_info_0e11_4058, + &pci_dev_info_0e11_4070, + &pci_dev_info_0e11_4080, + &pci_dev_info_0e11_4082, + &pci_dev_info_0e11_4083, + &pci_dev_info_0e11_4091, + &pci_dev_info_0e11_409a, + &pci_dev_info_0e11_409b, + &pci_dev_info_0e11_409c, + &pci_dev_info_0e11_409d, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_b200, + &pci_dev_info_0e11_b203, + &pci_dev_info_0e11_b204, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e55 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0031, + &pci_dev_info_1000_0032, + &pci_dev_info_1000_0033, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_0041, + &pci_dev_info_1000_0050, + &pci_dev_info_1000_0054, + &pci_dev_info_1000_0056, + &pci_dev_info_1000_0058, + &pci_dev_info_1000_005a, + &pci_dev_info_1000_005c, + &pci_dev_info_1000_005e, + &pci_dev_info_1000_0060, + &pci_dev_info_1000_0062, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0407, + &pci_dev_info_1000_0408, + &pci_dev_info_1000_0409, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0640, + &pci_dev_info_1000_0642, + &pci_dev_info_1000_0646, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0804, + &pci_dev_info_1000_0805, + &pci_dev_info_1000_0806, + &pci_dev_info_1000_0807, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_3150, + &pci_dev_info_1002_3152, + &pci_dev_info_1002_3154, + &pci_dev_info_1002_3e50, + &pci_dev_info_1002_3e54, + &pci_dev_info_1002_3e70, + &pci_dev_info_1002_4136, + &pci_dev_info_1002_4137, + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4148, + &pci_dev_info_1002_4149, + &pci_dev_info_1002_414a, + &pci_dev_info_1002_414b, + &pci_dev_info_1002_4150, + &pci_dev_info_1002_4151, + &pci_dev_info_1002_4152, + &pci_dev_info_1002_4153, + &pci_dev_info_1002_4154, + &pci_dev_info_1002_4155, + &pci_dev_info_1002_4156, + &pci_dev_info_1002_4157, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4164, + &pci_dev_info_1002_4165, + &pci_dev_info_1002_4166, + &pci_dev_info_1002_4168, + &pci_dev_info_1002_4170, + &pci_dev_info_1002_4171, + &pci_dev_info_1002_4172, + &pci_dev_info_1002_4173, + &pci_dev_info_1002_4237, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4243, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4341, + &pci_dev_info_1002_4345, + &pci_dev_info_1002_4347, + &pci_dev_info_1002_4348, + &pci_dev_info_1002_4349, + &pci_dev_info_1002_434d, + &pci_dev_info_1002_4353, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4363, + &pci_dev_info_1002_436e, + &pci_dev_info_1002_4370, + &pci_dev_info_1002_4371, + &pci_dev_info_1002_4372, + &pci_dev_info_1002_4373, + &pci_dev_info_1002_4374, + &pci_dev_info_1002_4375, + &pci_dev_info_1002_4376, + &pci_dev_info_1002_4377, + &pci_dev_info_1002_4378, + &pci_dev_info_1002_4379, + &pci_dev_info_1002_437a, + &pci_dev_info_1002_4437, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4a48, + &pci_dev_info_1002_4a49, + &pci_dev_info_1002_4a4a, + &pci_dev_info_1002_4a4b, + &pci_dev_info_1002_4a4c, + &pci_dev_info_1002_4a4d, + &pci_dev_info_1002_4a4e, + &pci_dev_info_1002_4a50, + &pci_dev_info_1002_4a70, + &pci_dev_info_1002_4b49, + &pci_dev_info_1002_4b4b, + &pci_dev_info_1002_4b4c, + &pci_dev_info_1002_4b69, + &pci_dev_info_1002_4b6b, + &pci_dev_info_1002_4b6c, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4c6e, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e48, + &pci_dev_info_1002_4e49, + &pci_dev_info_1002_4e4a, + &pci_dev_info_1002_4e4b, + &pci_dev_info_1002_4e50, + &pci_dev_info_1002_4e51, + &pci_dev_info_1002_4e52, + &pci_dev_info_1002_4e53, + &pci_dev_info_1002_4e54, + &pci_dev_info_1002_4e56, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_4e68, + &pci_dev_info_1002_4e69, + &pci_dev_info_1002_4e6a, + &pci_dev_info_1002_4e71, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5154, + &pci_dev_info_1002_5155, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_515e, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5460, + &pci_dev_info_1002_5462, + &pci_dev_info_1002_5464, + &pci_dev_info_1002_5548, + &pci_dev_info_1002_5549, + &pci_dev_info_1002_554a, + &pci_dev_info_1002_554b, + &pci_dev_info_1002_554d, + &pci_dev_info_1002_554f, + &pci_dev_info_1002_5550, + &pci_dev_info_1002_5551, + &pci_dev_info_1002_5552, + &pci_dev_info_1002_5554, + &pci_dev_info_1002_556b, + &pci_dev_info_1002_556d, + &pci_dev_info_1002_556f, + &pci_dev_info_1002_564a, + &pci_dev_info_1002_564b, + &pci_dev_info_1002_5652, + &pci_dev_info_1002_5653, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_5830, + &pci_dev_info_1002_5831, + &pci_dev_info_1002_5832, + &pci_dev_info_1002_5833, + &pci_dev_info_1002_5834, + &pci_dev_info_1002_5835, + &pci_dev_info_1002_5838, + &pci_dev_info_1002_5940, + &pci_dev_info_1002_5941, + &pci_dev_info_1002_5944, + &pci_dev_info_1002_5950, + &pci_dev_info_1002_5951, + &pci_dev_info_1002_5954, + &pci_dev_info_1002_5955, + &pci_dev_info_1002_5960, + &pci_dev_info_1002_5961, + &pci_dev_info_1002_5962, + &pci_dev_info_1002_5964, + &pci_dev_info_1002_5969, + &pci_dev_info_1002_5974, + &pci_dev_info_1002_5975, + &pci_dev_info_1002_5a34, + &pci_dev_info_1002_5a38, + &pci_dev_info_1002_5a3f, + &pci_dev_info_1002_5a41, + &pci_dev_info_1002_5a42, + &pci_dev_info_1002_5a61, + &pci_dev_info_1002_5a62, + &pci_dev_info_1002_5b60, + &pci_dev_info_1002_5b62, + &pci_dev_info_1002_5b63, + &pci_dev_info_1002_5b64, + &pci_dev_info_1002_5b65, + &pci_dev_info_1002_5b70, + &pci_dev_info_1002_5b72, + &pci_dev_info_1002_5b73, + &pci_dev_info_1002_5b74, + &pci_dev_info_1002_5c61, + &pci_dev_info_1002_5c63, + &pci_dev_info_1002_5d44, + &pci_dev_info_1002_5d48, + &pci_dev_info_1002_5d49, + &pci_dev_info_1002_5d4a, + &pci_dev_info_1002_5d4d, + &pci_dev_info_1002_5d4f, + &pci_dev_info_1002_5d52, + &pci_dev_info_1002_5d57, + &pci_dev_info_1002_5d6d, + &pci_dev_info_1002_5d6f, + &pci_dev_info_1002_5d72, + &pci_dev_info_1002_5d77, + &pci_dev_info_1002_5e48, + &pci_dev_info_1002_5e49, + &pci_dev_info_1002_5e4a, + &pci_dev_info_1002_5e4b, + &pci_dev_info_1002_5e4c, + &pci_dev_info_1002_5e4d, + &pci_dev_info_1002_5e4f, + &pci_dev_info_1002_5e6b, + &pci_dev_info_1002_5e6d, + &pci_dev_info_1002_700f, + &pci_dev_info_1002_7010, + &pci_dev_info_1002_7100, + &pci_dev_info_1002_7105, + &pci_dev_info_1002_7109, + &pci_dev_info_1002_7120, + &pci_dev_info_1002_7129, + &pci_dev_info_1002_7142, + &pci_dev_info_1002_7146, + &pci_dev_info_1002_7162, + &pci_dev_info_1002_7166, + &pci_dev_info_1002_71c0, + &pci_dev_info_1002_71c2, + &pci_dev_info_1002_71e0, + &pci_dev_info_1002_71e2, + &pci_dev_info_1002_7833, + &pci_dev_info_1002_7834, + &pci_dev_info_1002_7835, + &pci_dev_info_1002_7838, + &pci_dev_info_1002_7c37, + &pci_dev_info_1002_cab0, + &pci_dev_info_1002_cab2, + &pci_dev_info_1002_cab3, + &pci_dev_info_1002_cbb2, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0021, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0028, + &pci_dev_info_100b_002a, + &pci_dev_info_100b_002b, + &pci_dev_info_100b_002d, + &pci_dev_info_100b_002e, + &pci_dev_info_100b_002f, + &pci_dev_info_100b_0030, + &pci_dev_info_100b_0035, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_0510, + &pci_dev_info_100b_0511, + &pci_dev_info_100b_0515, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0017, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4000, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0031, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_0037, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003c, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0054, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_005e, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_008b, + &pci_dev_info_1014_008e, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0091, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_009f, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00b8, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0104, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_015e, + &pci_dev_info_1014_0160, + &pci_dev_info_1014_016e, + &pci_dev_info_1014_0170, + &pci_dev_info_1014_017d, + &pci_dev_info_1014_0180, + &pci_dev_info_1014_0188, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_01c1, + &pci_dev_info_1014_01e6, + &pci_dev_info_1014_01ff, + &pci_dev_info_1014_0219, + &pci_dev_info_1014_021b, + &pci_dev_info_1014_021c, + &pci_dev_info_1014_0233, + &pci_dev_info_1014_0266, + &pci_dev_info_1014_0268, + &pci_dev_info_1014_0269, + &pci_dev_info_1014_028c, + &pci_dev_info_1014_02a1, + &pci_dev_info_1014_02bd, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_0314, + &pci_dev_info_1014_3022, + &pci_dev_info_1014_4022, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_0009, + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2003, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_2081, + &pci_dev_info_1022_2082, + &pci_dev_info_1022_208f, + &pci_dev_info_1022_2090, + &pci_dev_info_1022_2091, + &pci_dev_info_1022_2093, + &pci_dev_info_1022_2094, + &pci_dev_info_1022_2095, + &pci_dev_info_1022_2096, + &pci_dev_info_1022_2097, + &pci_dev_info_1022_209a, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700a, + &pci_dev_info_1022_700b, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7458, + &pci_dev_info_1022_7459, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + &pci_dev_info_1022_756b, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_2100, + &pci_dev_info_1023_2200, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_1671, + &pci_dev_info_1025_1672, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_0009, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000d, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + &pci_dev_info_1028_0010, + &pci_dev_info_1028_0011, + &pci_dev_info_1028_0012, + &pci_dev_info_1028_0013, + &pci_dev_info_1028_0014, + &pci_dev_info_1028_0015, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + &pci_dev_info_102a_001f, + &pci_dev_info_102a_00c5, + &pci_dev_info_102a_00cf, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0100, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0528, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_2537, + &pci_dev_info_102b_2538, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_000a, + &pci_dev_info_102f_0020, + &pci_dev_info_102f_0030, + &pci_dev_info_102f_0031, + &pci_dev_info_102f_0105, + &pci_dev_info_102f_0106, + &pci_dev_info_102f_0107, + &pci_dev_info_102f_0108, + &pci_dev_info_102f_0180, + &pci_dev_info_102f_0181, + &pci_dev_info_102f_0182, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0000, + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0072, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a5, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00ce, + &pci_dev_info_1033_00df, + &pci_dev_info_1033_00e0, + &pci_dev_info_1033_00e7, + &pci_dev_info_1033_00f2, + &pci_dev_info_1033_00f3, + &pci_dev_info_1033_010c, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0003, + &pci_dev_info_1039_0004, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_000a, + &pci_dev_info_1039_0016, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0180, + &pci_dev_info_1039_0181, + &pci_dev_info_1039_0182, + &pci_dev_info_1039_0190, + &pci_dev_info_1039_0191, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0550, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0648, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0655, + &pci_dev_info_1039_0660, + &pci_dev_info_1039_0661, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0741, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0746, + &pci_dev_info_1039_0755, + &pci_dev_info_1039_0760, + &pci_dev_info_1039_0761, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_0963, + &pci_dev_info_1039_0964, + &pci_dev_info_1039_0965, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_6330, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + &pci_dev_info_1039_7019, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1006, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_100a, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1054, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_10f0, + &pci_dev_info_103c_10f1, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_127c, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_1291, + &pci_dev_info_103c_12b4, + &pci_dev_info_103c_12fa, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + &pci_dev_info_103c_3080, + &pci_dev_info_103c_3220, + &pci_dev_info_103c_3230, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_4015, + &pci_dev_info_1043_4021, + &pci_dev_info_1043_4057, + &pci_dev_info_1043_8043, + &pci_dev_info_1043_807b, + &pci_dev_info_1043_80bb, + &pci_dev_info_1043_80c5, + &pci_dev_info_1043_80df, + &pci_dev_info_1043_8187, + &pci_dev_info_1043_8188, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0c60, + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + &pci_dev_info_1048_8901, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0209, + &pci_dev_info_104a_020a, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_021a, + &pci_dev_info_104a_021b, + &pci_dev_info_104a_0500, + &pci_dev_info_104a_0564, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + &pci_dev_info_104a_55cc, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8025, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8029, + &pci_dev_info_104c_802b, + &pci_dev_info_104c_802e, + &pci_dev_info_104c_8031, + &pci_dev_info_104c_8032, + &pci_dev_info_104c_8033, + &pci_dev_info_104c_8034, + &pci_dev_info_104c_8035, + &pci_dev_info_104c_8036, + &pci_dev_info_104c_8038, + &pci_dev_info_104c_8201, + &pci_dev_info_104c_8204, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_8401, + &pci_dev_info_104c_9000, + &pci_dev_info_104c_9065, + &pci_dev_info_104c_9066, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac44, + &pci_dev_info_104c_ac46, + &pci_dev_info_104c_ac47, + &pci_dev_info_104c_ac4a, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac54, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_ac8d, + &pci_dev_info_104c_ac8e, + &pci_dev_info_104c_ac8f, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8004, + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9921, + &pci_dev_info_1050_9922, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0008, + &pci_dev_info_1057_0009, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_18c1, + &pci_dev_info_1057_3410, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_5608, + &pci_dev_info_1057_5803, + &pci_dev_info_1057_5806, + &pci_dev_info_1057_5808, + &pci_dev_info_1057_6400, + &pci_dev_info_1057_6405, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3318, + &pci_dev_info_105a_3319, + &pci_dev_info_105a_3371, + &pci_dev_info_105a_3373, + &pci_dev_info_105a_3375, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_3515, + &pci_dev_info_105a_3519, + &pci_dev_info_105a_3570, + &pci_dev_info_105a_3571, + &pci_dev_info_105a_3574, + &pci_dev_info_105a_3577, + &pci_dev_info_105a_3d17, + &pci_dev_info_105a_3d18, + &pci_dev_info_105a_3d73, + &pci_dev_info_105a_3d75, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_6622, + &pci_dev_info_105a_6624, + &pci_dev_info_105a_6626, + &pci_dev_info_105a_6629, + &pci_dev_info_105a_7275, + &pci_dev_info_105a_8002, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_0301, + &pci_dev_info_1067_0304, + &pci_dev_info_1067_0308, + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0020, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_b166, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + &pci_dev_info_1069_ba57, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000c, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_0035, + &pci_dev_info_106b_0036, + &pci_dev_info_106b_003b, + &pci_dev_info_106b_003e, + &pci_dev_info_106b_003f, + &pci_dev_info_106b_0040, + &pci_dev_info_106b_0041, + &pci_dev_info_106b_0042, + &pci_dev_info_106b_0043, + &pci_dev_info_106b_0045, + &pci_dev_info_106b_0046, + &pci_dev_info_106b_0047, + &pci_dev_info_106b_0048, + &pci_dev_info_106b_0049, + &pci_dev_info_106b_004b, + &pci_dev_info_106b_004c, + &pci_dev_info_106b_004f, + &pci_dev_info_106b_0050, + &pci_dev_info_106b_0051, + &pci_dev_info_106b_0052, + &pci_dev_info_106b_0053, + &pci_dev_info_106b_0054, + &pci_dev_info_106b_0055, + &pci_dev_info_106b_0058, + &pci_dev_info_106b_0059, + &pci_dev_info_106b_0066, + &pci_dev_info_106b_0067, + &pci_dev_info_106b_0068, + &pci_dev_info_106b_0069, + &pci_dev_info_106b_006a, + &pci_dev_info_106b_006b, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1071[] = { + &pci_dev_info_1071_8160, + NULL +}; +#endif +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + &pci_dev_info_1077_2322, + &pci_dev_info_1077_2422, + &pci_dev_info_1077_2432, + &pci_dev_info_1077_3010, + &pci_dev_info_1077_3022, + &pci_dev_info_1077_4010, + &pci_dev_info_1077_4022, + &pci_dev_info_1077_6312, + &pci_dev_info_1077_6322, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + &pci_dev_info_107d_2134, + &pci_dev_info_107d_2971, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_1648, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_8002, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + &pci_dev_info_108e_a801, + &pci_dev_info_108e_abba, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + &pci_dev_info_1091_07a0, + &pci_dev_info_1091_1091, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1310, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_14e0, + &pci_dev_info_1093_14f0, + &pci_dev_info_1093_17d0, + &pci_dev_info_1093_1870, + &pci_dev_info_1093_1880, + &pci_dev_info_1093_18b0, + &pci_dev_info_1093_2410, + &pci_dev_info_1093_2890, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_2a70, + &pci_dev_info_1093_2a80, + &pci_dev_info_1093_2c80, + &pci_dev_info_1093_2ca0, + &pci_dev_info_1093_70a9, + &pci_dev_info_1093_70b8, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0240, + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + &pci_dev_info_1095_3114, + &pci_dev_info_1095_3124, + &pci_dev_info_1095_3132, + &pci_dev_info_1095_3512, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_032e, + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_3052, + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_100a, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_4001, + &pci_dev_info_10a9_4002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + &pci_dev_info_10a9_8010, + &pci_dev_info_10a9_8018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1042, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2540, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_6540, + &pci_dev_info_10b5_6541, + &pci_dev_info_10b5_6542, + &pci_dev_info_10b5_8111, + &pci_dev_info_10b5_8114, + &pci_dev_info_10b5_8516, + &pci_dev_info_10b5_8532, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9056, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + &pci_dev_info_10b5_bb04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_0013, + &pci_dev_info_10b7_0910, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_1201, + &pci_dev_info_10b7_1202, + &pci_dev_info_10b7_1700, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6000, + &pci_dev_info_10b7_6001, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7770, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_80eb, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9202, + &pci_dev_info_10b7_9210, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990a, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_2802, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0101, + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_0780, + &pci_dev_info_10b9_0782, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1573, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1672, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_1689, + &pci_dev_info_10b9_1695, + &pci_dev_info_10b9_1697, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_3323, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5228, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5246, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_524b, + &pci_dev_info_10b9_524c, + &pci_dev_info_10b9_524d, + &pci_dev_info_10b9_524e, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5263, + &pci_dev_info_10b9_5281, + &pci_dev_info_10b9_5287, + &pci_dev_info_10b9_5288, + &pci_dev_info_10b9_5289, + &pci_dev_info_10b9_5450, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5461, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + &pci_dev_info_10ba_0304, + &pci_dev_info_10ba_0308, + &pci_dev_info_10ba_1002, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cc[] = { + &pci_dev_info_10cc_0660, + &pci_dev_info_10cc_0661, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0431, + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8626, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dd[] = { + &pci_dev_info_10dd_0100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0034, + &pci_dev_info_10de_0035, + &pci_dev_info_10de_0036, + &pci_dev_info_10de_0037, + &pci_dev_info_10de_0038, + &pci_dev_info_10de_003a, + &pci_dev_info_10de_003b, + &pci_dev_info_10de_003c, + &pci_dev_info_10de_003d, + &pci_dev_info_10de_003e, + &pci_dev_info_10de_0040, + &pci_dev_info_10de_0041, + &pci_dev_info_10de_0042, + &pci_dev_info_10de_0043, + &pci_dev_info_10de_0045, + &pci_dev_info_10de_0047, + &pci_dev_info_10de_0049, + &pci_dev_info_10de_004e, + &pci_dev_info_10de_0050, + &pci_dev_info_10de_0051, + &pci_dev_info_10de_0052, + &pci_dev_info_10de_0053, + &pci_dev_info_10de_0054, + &pci_dev_info_10de_0055, + &pci_dev_info_10de_0056, + &pci_dev_info_10de_0057, + &pci_dev_info_10de_0058, + &pci_dev_info_10de_0059, + &pci_dev_info_10de_005a, + &pci_dev_info_10de_005b, + &pci_dev_info_10de_005c, + &pci_dev_info_10de_005d, + &pci_dev_info_10de_005e, + &pci_dev_info_10de_005f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006c, + &pci_dev_info_10de_006d, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_0080, + &pci_dev_info_10de_0084, + &pci_dev_info_10de_0085, + &pci_dev_info_10de_0086, + &pci_dev_info_10de_0087, + &pci_dev_info_10de_0088, + &pci_dev_info_10de_008a, + &pci_dev_info_10de_008b, + &pci_dev_info_10de_008c, + &pci_dev_info_10de_008e, + &pci_dev_info_10de_0091, + &pci_dev_info_10de_0092, + &pci_dev_info_10de_0099, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_00c0, + &pci_dev_info_10de_00c1, + &pci_dev_info_10de_00c2, + &pci_dev_info_10de_00c8, + &pci_dev_info_10de_00c9, + &pci_dev_info_10de_00cc, + &pci_dev_info_10de_00cd, + &pci_dev_info_10de_00ce, + &pci_dev_info_10de_00d0, + &pci_dev_info_10de_00d1, + &pci_dev_info_10de_00d2, + &pci_dev_info_10de_00d3, + &pci_dev_info_10de_00d4, + &pci_dev_info_10de_00d5, + &pci_dev_info_10de_00d6, + &pci_dev_info_10de_00d7, + &pci_dev_info_10de_00d8, + &pci_dev_info_10de_00d9, + &pci_dev_info_10de_00da, + &pci_dev_info_10de_00dd, + &pci_dev_info_10de_00df, + &pci_dev_info_10de_00e0, + &pci_dev_info_10de_00e1, + &pci_dev_info_10de_00e2, + &pci_dev_info_10de_00e3, + &pci_dev_info_10de_00e4, + &pci_dev_info_10de_00e5, + &pci_dev_info_10de_00e6, + &pci_dev_info_10de_00e7, + &pci_dev_info_10de_00e8, + &pci_dev_info_10de_00ea, + &pci_dev_info_10de_00ed, + &pci_dev_info_10de_00ee, + &pci_dev_info_10de_00f0, + &pci_dev_info_10de_00f1, + &pci_dev_info_10de_00f2, + &pci_dev_info_10de_00f3, + &pci_dev_info_10de_00f8, + &pci_dev_info_10de_00f9, + &pci_dev_info_10de_00fa, + &pci_dev_info_10de_00fb, + &pci_dev_info_10de_00fc, + &pci_dev_info_10de_00fd, + &pci_dev_info_10de_00fe, + &pci_dev_info_10de_00ff, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0140, + &pci_dev_info_10de_0141, + &pci_dev_info_10de_0142, + &pci_dev_info_10de_0144, + &pci_dev_info_10de_0145, + &pci_dev_info_10de_0146, + &pci_dev_info_10de_0148, + &pci_dev_info_10de_014e, + &pci_dev_info_10de_014f, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0161, + &pci_dev_info_10de_0164, + &pci_dev_info_10de_0165, + &pci_dev_info_10de_0167, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0177, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_017d, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0185, + &pci_dev_info_10de_0186, + &pci_dev_info_10de_0187, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_018d, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b0, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01e0, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01ea, + &pci_dev_info_10de_01eb, + &pci_dev_info_10de_01ec, + &pci_dev_info_10de_01ed, + &pci_dev_info_10de_01ee, + &pci_dev_info_10de_01ef, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0221, + &pci_dev_info_10de_0240, + &pci_dev_info_10de_0241, + &pci_dev_info_10de_0242, + &pci_dev_info_10de_0243, + &pci_dev_info_10de_0244, + &pci_dev_info_10de_0245, + &pci_dev_info_10de_0246, + &pci_dev_info_10de_0247, + &pci_dev_info_10de_0248, + &pci_dev_info_10de_0249, + &pci_dev_info_10de_024a, + &pci_dev_info_10de_024b, + &pci_dev_info_10de_024c, + &pci_dev_info_10de_024d, + &pci_dev_info_10de_024e, + &pci_dev_info_10de_024f, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0260, + &pci_dev_info_10de_0261, + &pci_dev_info_10de_0262, + &pci_dev_info_10de_0263, + &pci_dev_info_10de_0264, + &pci_dev_info_10de_0265, + &pci_dev_info_10de_0266, + &pci_dev_info_10de_0267, + &pci_dev_info_10de_0268, + &pci_dev_info_10de_0269, + &pci_dev_info_10de_026a, + &pci_dev_info_10de_026b, + &pci_dev_info_10de_026c, + &pci_dev_info_10de_026d, + &pci_dev_info_10de_026e, + &pci_dev_info_10de_026f, + &pci_dev_info_10de_0270, + &pci_dev_info_10de_0271, + &pci_dev_info_10de_0272, + &pci_dev_info_10de_027e, + &pci_dev_info_10de_027f, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0286, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_028c, + &pci_dev_info_10de_02a0, + &pci_dev_info_10de_02f0, + &pci_dev_info_10de_02f1, + &pci_dev_info_10de_02f2, + &pci_dev_info_10de_02f3, + &pci_dev_info_10de_02f4, + &pci_dev_info_10de_02f5, + &pci_dev_info_10de_02f6, + &pci_dev_info_10de_02f7, + &pci_dev_info_10de_02f8, + &pci_dev_info_10de_02f9, + &pci_dev_info_10de_02fa, + &pci_dev_info_10de_02fb, + &pci_dev_info_10de_02fc, + &pci_dev_info_10de_02fd, + &pci_dev_info_10de_02fe, + &pci_dev_info_10de_02ff, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + &pci_dev_info_10de_0311, + &pci_dev_info_10de_0312, + &pci_dev_info_10de_0313, + &pci_dev_info_10de_0314, + &pci_dev_info_10de_0316, + &pci_dev_info_10de_0317, + &pci_dev_info_10de_031a, + &pci_dev_info_10de_031b, + &pci_dev_info_10de_031c, + &pci_dev_info_10de_031d, + &pci_dev_info_10de_031e, + &pci_dev_info_10de_031f, + &pci_dev_info_10de_0320, + &pci_dev_info_10de_0321, + &pci_dev_info_10de_0322, + &pci_dev_info_10de_0323, + &pci_dev_info_10de_0324, + &pci_dev_info_10de_0325, + &pci_dev_info_10de_0326, + &pci_dev_info_10de_0327, + &pci_dev_info_10de_0328, + &pci_dev_info_10de_0329, + &pci_dev_info_10de_032a, + &pci_dev_info_10de_032b, + &pci_dev_info_10de_032c, + &pci_dev_info_10de_032d, + &pci_dev_info_10de_032f, + &pci_dev_info_10de_0330, + &pci_dev_info_10de_0331, + &pci_dev_info_10de_0332, + &pci_dev_info_10de_0333, + &pci_dev_info_10de_0334, + &pci_dev_info_10de_0338, + &pci_dev_info_10de_033f, + &pci_dev_info_10de_0341, + &pci_dev_info_10de_0342, + &pci_dev_info_10de_0343, + &pci_dev_info_10de_0344, + &pci_dev_info_10de_0345, + &pci_dev_info_10de_0347, + &pci_dev_info_10de_0348, + &pci_dev_info_10de_0349, + &pci_dev_info_10de_034b, + &pci_dev_info_10de_034c, + &pci_dev_info_10de_034e, + &pci_dev_info_10de_034f, + &pci_dev_info_10de_0360, + &pci_dev_info_10de_0361, + &pci_dev_info_10de_0362, + &pci_dev_info_10de_0363, + &pci_dev_info_10de_0364, + &pci_dev_info_10de_0365, + &pci_dev_info_10de_0366, + &pci_dev_info_10de_0367, + &pci_dev_info_10de_0368, + &pci_dev_info_10de_0369, + &pci_dev_info_10de_036a, + &pci_dev_info_10de_036c, + &pci_dev_info_10de_036d, + &pci_dev_info_10de_036e, + &pci_dev_info_10de_0371, + &pci_dev_info_10de_0372, + &pci_dev_info_10de_0373, + &pci_dev_info_10de_037a, + &pci_dev_info_10de_037e, + &pci_dev_info_10de_037f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f0a1, + &pci_dev_info_10df_f0a5, + &pci_dev_info_10df_f0b5, + &pci_dev_info_10df_f0d1, + &pci_dev_info_10df_f0d5, + &pci_dev_info_10df_f0e1, + &pci_dev_info_10df_f0e5, + &pci_dev_info_10df_f0f5, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f701, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f801, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f901, + &pci_dev_info_10df_f980, + &pci_dev_info_10df_f981, + &pci_dev_info_10df_f982, + &pci_dev_info_10df_fa00, + &pci_dev_info_10df_fb00, + &pci_dev_info_10df_fc00, + &pci_dev_info_10df_fc10, + &pci_dev_info_10df_fc20, + &pci_dev_info_10df_fd00, + &pci_dev_info_10df_fe00, + &pci_dev_info_10df_ff00, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0148, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + &pci_dev_info_10e3_8260, + &pci_dev_info_10e3_8261, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e4[] = { + &pci_dev_info_10e4_8029, + NULL +}; +#endif +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_1072, + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_814c, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_81e6, + &pci_dev_info_10e8_8291, + &pci_dev_info_10e8_82c4, + &pci_dev_info_10e8_82c5, + &pci_dev_info_10e8_82c6, + &pci_dev_info_10e8_82c7, + &pci_dev_info_10e8_82ca, + &pci_dev_info_10e8_82db, + &pci_dev_info_10e8_82e2, + &pci_dev_info_10e8_8851, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + &pci_dev_info_10ea_5252, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_0139, + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8180, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_0205, + &pci_dev_info_10ee_0210, + &pci_dev_info_10ee_0314, + &pci_dev_info_10ee_0405, + &pci_dev_info_10ee_0410, + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + &pci_dev_info_10ee_3fc6, + &pci_dev_info_10ee_8381, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#define pci_dev_list_10f1 NULL +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + &pci_dev_info_1101_9502, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_0007, + &pci_dev_info_1102_0008, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_7005, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + &pci_dev_info_1103_0009, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + &pci_dev_info_1105_8401, + &pci_dev_info_1105_8470, + &pci_dev_info_1105_8471, + &pci_dev_info_1105_8475, + &pci_dev_info_1105_8476, + &pci_dev_info_1105_8485, + &pci_dev_info_1105_8486, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0204, + &pci_dev_info_1106_0238, + &pci_dev_info_1106_0259, + &pci_dev_info_1106_0269, + &pci_dev_info_1106_0282, + &pci_dev_info_1106_0290, + &pci_dev_info_1106_0296, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0308, + &pci_dev_info_1106_0314, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0591, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1204, + &pci_dev_info_1106_1208, + &pci_dev_info_1106_1238, + &pci_dev_info_1106_1258, + &pci_dev_info_1106_1259, + &pci_dev_info_1106_1269, + &pci_dev_info_1106_1282, + &pci_dev_info_1106_1290, + &pci_dev_info_1106_1296, + &pci_dev_info_1106_1308, + &pci_dev_info_1106_1314, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_2204, + &pci_dev_info_1106_2208, + &pci_dev_info_1106_2238, + &pci_dev_info_1106_2258, + &pci_dev_info_1106_2259, + &pci_dev_info_1106_2269, + &pci_dev_info_1106_2282, + &pci_dev_info_1106_2290, + &pci_dev_info_1106_2296, + &pci_dev_info_1106_2308, + &pci_dev_info_1106_2314, + &pci_dev_info_1106_287a, + &pci_dev_info_1106_287b, + &pci_dev_info_1106_287c, + &pci_dev_info_1106_287d, + &pci_dev_info_1106_287e, + &pci_dev_info_1106_3022, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3053, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3108, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3113, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3118, + &pci_dev_info_1106_3119, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3149, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3164, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3178, + &pci_dev_info_1106_3188, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_3204, + &pci_dev_info_1106_3205, + &pci_dev_info_1106_3208, + &pci_dev_info_1106_3213, + &pci_dev_info_1106_3218, + &pci_dev_info_1106_3227, + &pci_dev_info_1106_3238, + &pci_dev_info_1106_3249, + &pci_dev_info_1106_3258, + &pci_dev_info_1106_3259, + &pci_dev_info_1106_3269, + &pci_dev_info_1106_3282, + &pci_dev_info_1106_3287, + &pci_dev_info_1106_3288, + &pci_dev_info_1106_3290, + &pci_dev_info_1106_3296, + &pci_dev_info_1106_3337, + &pci_dev_info_1106_3344, + &pci_dev_info_1106_3349, + &pci_dev_info_1106_337a, + &pci_dev_info_1106_337b, + &pci_dev_info_1106_4149, + &pci_dev_info_1106_4204, + &pci_dev_info_1106_4208, + &pci_dev_info_1106_4238, + &pci_dev_info_1106_4258, + &pci_dev_info_1106_4259, + &pci_dev_info_1106_4269, + &pci_dev_info_1106_4282, + &pci_dev_info_1106_4290, + &pci_dev_info_1106_4296, + &pci_dev_info_1106_4308, + &pci_dev_info_1106_4314, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_5208, + &pci_dev_info_1106_5238, + &pci_dev_info_1106_5290, + &pci_dev_info_1106_5308, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_7204, + &pci_dev_info_1106_7205, + &pci_dev_info_1106_7208, + &pci_dev_info_1106_7238, + &pci_dev_info_1106_7258, + &pci_dev_info_1106_7259, + &pci_dev_info_1106_7269, + &pci_dev_info_1106_7282, + &pci_dev_info_1106_7290, + &pci_dev_info_1106_7296, + &pci_dev_info_1106_7308, + &pci_dev_info_1106_7314, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_a208, + &pci_dev_info_1106_a238, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b113, + &pci_dev_info_1106_b115, + &pci_dev_info_1106_b168, + &pci_dev_info_1106_b188, + &pci_dev_info_1106_b198, + &pci_dev_info_1106_b213, + &pci_dev_info_1106_c208, + &pci_dev_info_1106_c238, + &pci_dev_info_1106_d104, + &pci_dev_info_1106_d208, + &pci_dev_info_1106_d213, + &pci_dev_info_1106_d238, + &pci_dev_info_1106_e208, + &pci_dev_info_1106_e238, + &pci_dev_info_1106_f208, + &pci_dev_info_1106_f238, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_0006, + &pci_dev_info_110a_0015, + &pci_dev_info_110a_001d, + &pci_dev_info_110a_007b, + &pci_dev_info_110a_007c, + &pci_dev_info_110a_007d, + &pci_dev_info_110a_2101, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_2104, + &pci_dev_info_110a_3142, + &pci_dev_info_110a_4021, + &pci_dev_info_110a_4029, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + &pci_dev_info_1113_d301, + &pci_dev_info_1113_ec02, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1114[] = { + &pci_dev_info_1114_0506, + NULL +}; +#endif +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0010, + &pci_dev_info_1119_0011, + &pci_dev_info_1119_0012, + &pci_dev_info_1119_0013, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_02ff, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + &pci_dev_info_111a_1203, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + &pci_dev_info_111d_0004, + &pci_dev_info_111d_0005, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#define pci_dev_list_1124 NULL +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + &pci_dev_info_112f_0008, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_5400, + &pci_dev_info_1131_5402, + &pci_dev_info_1131_5405, + &pci_dev_info_1131_5406, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + &pci_dev_info_1131_9730, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e006, + &pci_dev_info_1133_e007, + &pci_dev_info_1133_e008, + &pci_dev_info_1133_e009, + &pci_dev_info_1133_e00a, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e00c, + &pci_dev_info_1133_e00d, + &pci_dev_info_1133_e00e, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e011, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e013, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e015, + &pci_dev_info_1133_e016, + &pci_dev_info_1133_e017, + &pci_dev_info_1133_e018, + &pci_dev_info_1133_e019, + &pci_dev_info_1133_e01a, + &pci_dev_info_1133_e01b, + &pci_dev_info_1133_e01c, + &pci_dev_info_1133_e01e, + &pci_dev_info_1133_e020, + &pci_dev_info_1133_e024, + &pci_dev_info_1133_e028, + &pci_dev_info_1133_e02a, + &pci_dev_info_1133_e02c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + &pci_dev_info_1134_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + &pci_dev_info_1145_f020, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + &pci_dev_info_1148_4500, + &pci_dev_info_1148_9000, + &pci_dev_info_1148_9843, + &pci_dev_info_1148_9e00, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0028, + &pci_dev_info_114f_0029, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0043, + &pci_dev_info_114f_0044, + &pci_dev_info_114f_0045, + &pci_dev_info_114f_004e, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_00b0, + &pci_dev_info_114f_00b1, + &pci_dev_info_114f_00c8, + &pci_dev_info_114f_00c9, + &pci_dev_info_114f_00ca, + &pci_dev_info_114f_00cb, + &pci_dev_info_114f_00d0, + &pci_dev_info_114f_00d1, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_00d4, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0000, + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0006, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0036, + &pci_dev_info_1166_0101, + &pci_dev_info_1166_0104, + &pci_dev_info_1166_0110, + &pci_dev_info_1166_0130, + &pci_dev_info_1166_0132, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0205, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0214, + &pci_dev_info_1166_0217, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0223, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + &pci_dev_info_1166_0230, + &pci_dev_info_1166_0234, + &pci_dev_info_1166_0240, + &pci_dev_info_1166_0241, + &pci_dev_info_1166_0242, + &pci_dev_info_1166_024a, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0102, + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_117c[] = { + &pci_dev_info_117c_0030, + NULL +}; +#endif +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0511, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + &pci_dev_info_1180_0554, + &pci_dev_info_1180_0575, + &pci_dev_info_1180_0576, + &pci_dev_info_1180_0592, + &pci_dev_info_1180_0811, + &pci_dev_info_1180_0822, + &pci_dev_info_1180_0841, + &pci_dev_info_1180_0852, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1025, + &pci_dev_info_1186_1026, + &pci_dev_info_1186_1043, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1541, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_2027, + &pci_dev_info_1186_3203, + &pci_dev_info_1186_3300, + &pci_dev_info_1186_3a03, + &pci_dev_info_1186_3a04, + &pci_dev_info_1186_3a05, + &pci_dev_info_1186_3a07, + &pci_dev_info_1186_3a08, + &pci_dev_info_1186_3a10, + &pci_dev_info_1186_3a11, + &pci_dev_info_1186_3a12, + &pci_dev_info_1186_3a13, + &pci_dev_info_1186_3a14, + &pci_dev_info_1186_3a63, + &pci_dev_info_1186_4000, + &pci_dev_info_1186_4300, + &pci_dev_info_1186_4c00, + &pci_dev_info_1186_8400, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + &pci_dev_info_1191_8060, + &pci_dev_info_1191_8080, + &pci_dev_info_1191_8081, + &pci_dev_info_1191_808a, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1197[] = { + &pci_dev_info_1197_010c, + NULL +}; +#endif +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_138f, + &pci_dev_info_11ab_1fa6, + &pci_dev_info_11ab_1fa7, + &pci_dev_info_11ab_1faa, + &pci_dev_info_11ab_4320, + &pci_dev_info_11ab_4340, + &pci_dev_info_11ab_4341, + &pci_dev_info_11ab_4342, + &pci_dev_info_11ab_4343, + &pci_dev_info_11ab_4344, + &pci_dev_info_11ab_4345, + &pci_dev_info_11ab_4346, + &pci_dev_info_11ab_4347, + &pci_dev_info_11ab_4350, + &pci_dev_info_11ab_4351, + &pci_dev_info_11ab_4352, + &pci_dev_info_11ab_4360, + &pci_dev_info_11ab_4361, + &pci_dev_info_11ab_4362, + &pci_dev_info_11ab_4363, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_5005, + &pci_dev_info_11ab_5040, + &pci_dev_info_11ab_5041, + &pci_dev_info_11ab_5080, + &pci_dev_info_11ab_5081, + &pci_dev_info_11ab_6041, + &pci_dev_info_11ab_6081, + &pci_dev_info_11ab_6460, + &pci_dev_info_11ab_6480, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11af[] = { + &pci_dev_info_11af_0001, + &pci_dev_info_11af_ee40, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bd[] = { + &pci_dev_info_11bd_002e, + &pci_dev_info_11bd_bede, + NULL +}; +#endif +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_048c, + &pci_dev_info_11c1_048f, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + &pci_dev_info_11c1_8110, + &pci_dev_info_11c1_ab10, + &pci_dev_info_11c1_ab11, + &pci_dev_info_11c1_ab20, + &pci_dev_info_11c1_ab21, + &pci_dev_info_11c1_ab30, + &pci_dev_info_11c1_ed00, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1535, + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + &pci_dev_info_11d4_5340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_0001, + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_000d, + &pci_dev_info_11fe_000e, + &pci_dev_info_11fe_000f, + &pci_dev_info_11fe_0801, + &pci_dev_info_11fe_0802, + &pci_dev_info_11fe_0803, + &pci_dev_info_11fe_0805, + &pci_dev_info_11fe_080c, + &pci_dev_info_11fe_080d, + &pci_dev_info_11fe_0812, + &pci_dev_info_11fe_0903, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ff[] = { + &pci_dev_info_11ff_0003, + NULL +}; +#endif +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + &pci_dev_info_1217_7110, + &pci_dev_info_1217_7112, + &pci_dev_info_1217_7113, + &pci_dev_info_1217_7114, + &pci_dev_info_1217_7134, + &pci_dev_info_1217_71e2, + &pci_dev_info_1217_7212, + &pci_dev_info_1217_7213, + &pci_dev_info_1217_7223, + &pci_dev_info_1217_7233, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#define pci_dev_list_121e NULL +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1227[] = { + &pci_dev_info_1227_0006, + &pci_dev_info_1227_0023, + NULL +}; +#endif +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_1400, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + &pci_dev_info_1242_6562, + &pci_dev_info_1242_656a, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + &pci_dev_info_1244_2700, + &pci_dev_info_1244_2900, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + &pci_dev_info_1259_a117, + &pci_dev_info_1259_a120, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0101, + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3872, + &pci_dev_info_1260_3873, + &pci_dev_info_1260_3886, + &pci_dev_info_1260_3890, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + &pci_dev_info_1260_ffff, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_126c[] = { + &pci_dev_info_126c_1211, + &pci_dev_info_126c_126c, + NULL +}; +#endif +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0501, + &pci_dev_info_126f_0510, + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0730, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1171, + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + &pci_dev_info_1278_0710, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0060, + &pci_dev_info_1279_0061, + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8211, + &pci_dev_info_1283_8212, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8872, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12a3[] = { + &pci_dev_info_12a3_8105, + NULL +}; +#endif +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_0002, + &pci_dev_info_12ab_3000, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + &pci_dev_info_12ae_00fa, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c4[] = { + &pci_dev_info_12c4_0001, + &pci_dev_info_12c4_0002, + &pci_dev_info_12c4_0003, + &pci_dev_info_12c4_0004, + &pci_dev_info_12c4_0005, + &pci_dev_info_12c4_0006, + &pci_dev_info_12c4_0007, + &pci_dev_info_12c4_0008, + &pci_dev_info_12c4_0009, + &pci_dev_info_12c4_000a, + &pci_dev_info_12c4_000b, + &pci_dev_info_12c4_000c, + &pci_dev_info_12c4_000d, + &pci_dev_info_12c4_0100, + &pci_dev_info_12c4_0201, + &pci_dev_info_12c4_0202, + &pci_dev_info_12c4_0300, + &pci_dev_info_12c4_0301, + &pci_dev_info_12c4_0302, + &pci_dev_info_12c4_0310, + &pci_dev_info_12c4_0311, + &pci_dev_info_12c4_0312, + &pci_dev_info_12c4_0320, + &pci_dev_info_12c4_0321, + &pci_dev_info_12c4_0322, + &pci_dev_info_12c4_0330, + &pci_dev_info_12c4_0331, + &pci_dev_info_12c4_0332, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d4[] = { + &pci_dev_info_12d4_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d5[] = { + &pci_dev_info_12d5_0003, + &pci_dev_info_12d5_1000, + NULL +}; +#endif +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d8[] = { + &pci_dev_info_12d8_8150, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d9[] = { + &pci_dev_info_12d9_0002, + &pci_dev_info_12d9_0004, + &pci_dev_info_12d9_0005, + NULL +}; +#endif +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12de[] = { + &pci_dev_info_12de_0200, + NULL +}; +#endif +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12fb[] = { + &pci_dev_info_12fb_0001, + &pci_dev_info_12fb_00f5, + &pci_dev_info_12fb_02ad, + &pci_dev_info_12fb_2adc, + &pci_dev_info_12fb_3100, + &pci_dev_info_12fb_3500, + &pci_dev_info_12fb_4d4f, + &pci_dev_info_12fb_8120, + &pci_dev_info_12fb_da62, + &pci_dev_info_12fb_db62, + &pci_dev_info_12fb_dc62, + &pci_dev_info_12fb_dd62, + &pci_dev_info_12fb_eddc, + &pci_dev_info_12fb_fa01, + NULL +}; +#endif +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + &pci_dev_info_1307_004d, + &pci_dev_info_1307_0052, + &pci_dev_info_1307_0054, + &pci_dev_info_1307_005e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + &pci_dev_info_1317_2850, + &pci_dev_info_1317_5120, + &pci_dev_info_1317_8201, + &pci_dev_info_1317_8211, + &pci_dev_info_1317_9511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + &pci_dev_info_131f_2081, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1331[] = { + &pci_dev_info_1331_0030, + &pci_dev_info_1331_8200, + &pci_dev_info_1331_8201, + &pci_dev_info_1331_8202, + &pci_dev_info_1331_8210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + &pci_dev_info_1332_5425, + &pci_dev_info_1332_6140, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_2189, + &pci_dev_info_134d_2486, + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_5101, + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1360[] = { + &pci_dev_info_1360_0101, + &pci_dev_info_1360_0102, + &pci_dev_info_1360_0103, + &pci_dev_info_1360_0201, + &pci_dev_info_1360_0202, + &pci_dev_info_1360_0203, + &pci_dev_info_1360_0301, + &pci_dev_info_1360_0302, + NULL +}; +#endif +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#define pci_dev_list_136a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136b[] = { + &pci_dev_info_136b_ff01, + NULL +}; +#endif +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1371[] = { + &pci_dev_info_1371_434e, + NULL +}; +#endif +#define pci_dev_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1374[] = { + &pci_dev_info_1374_0024, + &pci_dev_info_1374_0025, + &pci_dev_info_1374_0026, + &pci_dev_info_1374_0027, + &pci_dev_info_1374_0029, + &pci_dev_info_1374_002a, + &pci_dev_info_1374_002b, + &pci_dev_info_1374_002c, + &pci_dev_info_1374_002d, + &pci_dev_info_1374_002e, + &pci_dev_info_1374_002f, + &pci_dev_info_1374_0030, + &pci_dev_info_1374_0031, + &pci_dev_info_1374_0032, + &pci_dev_info_1374_0034, + &pci_dev_info_1374_0035, + &pci_dev_info_1374_0036, + &pci_dev_info_1374_0037, + &pci_dev_info_1374_0038, + &pci_dev_info_1374_0039, + &pci_dev_info_1374_003a, + NULL +}; +#endif +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_137a[] = { + &pci_dev_info_137a_0001, + NULL +}; +#endif +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1382[] = { + &pci_dev_info_1382_0001, + &pci_dev_info_1382_2008, + &pci_dev_info_1382_2088, + &pci_dev_info_1382_20c8, + &pci_dev_info_1382_4008, + &pci_dev_info_1382_4010, + &pci_dev_info_1382_4048, + &pci_dev_info_1382_4088, + &pci_dev_info_1382_4248, + &pci_dev_info_1382_4424, + NULL +}; +#endif +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_0013, + &pci_dev_info_1385_311a, + &pci_dev_info_1385_4100, + &pci_dev_info_1385_4105, + &pci_dev_info_1385_4400, + &pci_dev_info_1385_4600, + &pci_dev_info_1385_4601, + &pci_dev_info_1385_4610, + &pci_dev_info_1385_4800, + &pci_dev_info_1385_4900, + &pci_dev_info_1385_4a00, + &pci_dev_info_1385_4b00, + &pci_dev_info_1385_4c00, + &pci_dev_info_1385_4d00, + &pci_dev_info_1385_4e00, + &pci_dev_info_1385_4f00, + &pci_dev_info_1385_5200, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_6b00, + &pci_dev_info_1385_6d00, + &pci_dev_info_1385_f004, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1141, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_16b8, + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + &pci_dev_info_13a3_001d, + &pci_dev_info_13a3_0020, + &pci_dev_info_13a3_0026, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0152, + &pci_dev_info_13a8_0154, + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + &pci_dev_info_13c0_0020, + &pci_dev_info_13c0_0030, + &pci_dev_info_13c0_0210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + &pci_dev_info_13c1_1003, + NULL +}; +#endif +#define pci_dev_list_13c2 NULL +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c6[] = { + &pci_dev_info_13c6_0520, + &pci_dev_info_13c6_0620, + &pci_dev_info_13c6_0820, + NULL +}; +#endif +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + &pci_dev_info_13d0_2200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab03, + &pci_dev_info_13d1_ab06, + &pci_dev_info_13d1_ab08, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#define pci_dev_list_13ec NULL +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0200, + &pci_dev_info_13f0_0201, + &pci_dev_info_13f0_1023, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0011, + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1240, + &pci_dev_info_13fe_1600, + &pci_dev_info_13fe_1733, + &pci_dev_info_13fe_1752, + &pci_dev_info_13fe_1754, + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0110, + &pci_dev_info_1407_0111, + &pci_dev_info_1407_0120, + &pci_dev_info_1407_0121, + &pci_dev_info_1407_0180, + &pci_dev_info_1407_0181, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0220, + &pci_dev_info_1407_0221, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9510, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9521, + &pci_dev_info_1415_9523, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1420[] = { + &pci_dev_info_1420_8002, + &pci_dev_info_1420_8003, + NULL +}; +#endif +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1425[] = { + &pci_dev_info_1425_000b, + NULL +}; +#endif +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_142e[] = { + &pci_dev_info_142e_4020, + &pci_dev_info_142e_4337, + NULL +}; +#endif +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1432[] = { + &pci_dev_info_1432_9130, + NULL +}; +#endif +#define pci_dev_list_1433 NULL +#define pci_dev_list_1435 NULL +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8164, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#define pci_dev_list_144d NULL +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1458[] = { + &pci_dev_info_1458_0c11, + &pci_dev_info_1458_e911, + NULL +}; +#endif +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1461[] = { + &pci_dev_info_1461_f436, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1462[] = { + &pci_dev_info_1462_5501, + &pci_dev_info_1462_6819, + &pci_dev_info_1462_6825, + &pci_dev_info_1462_6834, + &pci_dev_info_1462_8725, + &pci_dev_info_1462_9000, + &pci_dev_info_1462_9110, + &pci_dev_info_1462_9119, + &pci_dev_info_1462_9591, + NULL +}; +#endif +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_146c[] = { + &pci_dev_info_146c_1430, + NULL +}; +#endif +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1497[] = { + &pci_dev_info_1497_1497, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1498[] = { + &pci_dev_info_1498_0330, + &pci_dev_info_1498_0385, + &pci_dev_info_1498_21cd, + &pci_dev_info_1498_30c8, + NULL +}; +#endif +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_149d[] = { + &pci_dev_info_149d_0001, + NULL +}; +#endif +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + &pci_dev_info_14b9_a505, + &pci_dev_info_14b9_a506, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#define pci_dev_list_14bc NULL +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14c1[] = { + &pci_dev_info_14c1_8043, + NULL +}; +#endif +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d9[] = { + &pci_dev_info_14d9_0010, + &pci_dev_info_14d9_9000, + NULL +}; +#endif +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + &pci_dev_info_14db_2182, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_0800, + &pci_dev_info_14e4_0804, + &pci_dev_info_14e4_0805, + &pci_dev_info_14e4_0806, + &pci_dev_info_14e4_080b, + &pci_dev_info_14e4_080f, + &pci_dev_info_14e4_0811, + &pci_dev_info_14e4_0816, + &pci_dev_info_14e4_1600, + &pci_dev_info_14e4_1601, + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164a, + &pci_dev_info_14e4_164c, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_1654, + &pci_dev_info_14e4_1659, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_165e, + &pci_dev_info_14e4_1668, + &pci_dev_info_14e4_166a, + &pci_dev_info_14e4_166b, + &pci_dev_info_14e4_166e, + &pci_dev_info_14e4_1677, + &pci_dev_info_14e4_1678, + &pci_dev_info_14e4_167d, + &pci_dev_info_14e4_167e, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_169c, + &pci_dev_info_14e4_169d, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16aa, + &pci_dev_info_14e4_16ac, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_16dd, + &pci_dev_info_14e4_16f7, + &pci_dev_info_14e4_16fd, + &pci_dev_info_14e4_16fe, + &pci_dev_info_14e4_170c, + &pci_dev_info_14e4_170d, + &pci_dev_info_14e4_170e, + &pci_dev_info_14e4_3352, + &pci_dev_info_14e4_3360, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4305, + &pci_dev_info_14e4_4306, + &pci_dev_info_14e4_4307, + &pci_dev_info_14e4_4310, + &pci_dev_info_14e4_4312, + &pci_dev_info_14e4_4313, + &pci_dev_info_14e4_4315, + &pci_dev_info_14e4_4318, + &pci_dev_info_14e4_4319, + &pci_dev_info_14e4_4320, + &pci_dev_info_14e4_4321, + &pci_dev_info_14e4_4322, + &pci_dev_info_14e4_4324, + &pci_dev_info_14e4_4325, + &pci_dev_info_14e4_4326, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4403, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_4430, + &pci_dev_info_14e4_4432, + &pci_dev_info_14e4_4610, + &pci_dev_info_14e4_4611, + &pci_dev_info_14e4_4612, + &pci_dev_info_14e4_4613, + &pci_dev_info_14e4_4614, + &pci_dev_info_14e4_4615, + &pci_dev_info_14e4_4704, + &pci_dev_info_14e4_4705, + &pci_dev_info_14e4_4706, + &pci_dev_info_14e4_4707, + &pci_dev_info_14e4_4708, + &pci_dev_info_14e4_4710, + &pci_dev_info_14e4_4711, + &pci_dev_info_14e4_4712, + &pci_dev_info_14e4_4713, + &pci_dev_info_14e4_4714, + &pci_dev_info_14e4_4715, + &pci_dev_info_14e4_4716, + &pci_dev_info_14e4_4717, + &pci_dev_info_14e4_4718, + &pci_dev_info_14e4_4719, + &pci_dev_info_14e4_4720, + &pci_dev_info_14e4_5365, + &pci_dev_info_14e4_5600, + &pci_dev_info_14e4_5605, + &pci_dev_info_14e4_5615, + &pci_dev_info_14e4_5625, + &pci_dev_info_14e4_5645, + &pci_dev_info_14e4_5670, + &pci_dev_info_14e4_5680, + &pci_dev_info_14e4_5690, + &pci_dev_info_14e4_5691, + &pci_dev_info_14e4_5692, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + &pci_dev_info_14e4_5822, + &pci_dev_info_14e4_5823, + &pci_dev_info_14e4_5824, + &pci_dev_info_14e4_5840, + &pci_dev_info_14e4_5841, + &pci_dev_info_14e4_5850, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + &pci_dev_info_14ea_ab07, + &pci_dev_info_14ea_ab08, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1085, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1620, + &pci_dev_info_14f1_1621, + &pci_dev_info_14f1_1622, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1811, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_2f02, + &pci_dev_info_14f1_2f11, + &pci_dev_info_14f1_2f20, + &pci_dev_info_14f1_8234, + &pci_dev_info_14f1_8800, + &pci_dev_info_14f1_8801, + &pci_dev_info_14f1_8802, + &pci_dev_info_14f1_8804, + &pci_dev_info_14f1_8811, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f2[] = { + &pci_dev_info_14f2_0120, + &pci_dev_info_14f2_0121, + &pci_dev_info_14f2_0122, + &pci_dev_info_14f2_0123, + &pci_dev_info_14f2_0124, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f3[] = { + &pci_dev_info_14f3_2030, + &pci_dev_info_14f3_2050, + &pci_dev_info_14f3_2060, + NULL +}; +#endif +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f8[] = { + &pci_dev_info_14f8_2077, + NULL +}; +#endif +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14fc[] = { + &pci_dev_info_14fc_0000, + &pci_dev_info_14fc_0001, + NULL +}; +#endif +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1500[] = { + &pci_dev_info_1500_1360, + NULL +}; +#endif +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0800, + &pci_dev_info_1516_0803, + &pci_dev_info_1516_0891, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151c[] = { + &pci_dev_info_151c_0003, + &pci_dev_info_151c_4000, + NULL +}; +#endif +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_0510, + &pci_dev_info_1524_0520, + &pci_dev_info_1524_0530, + &pci_dev_info_1524_0550, + &pci_dev_info_1524_0610, + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1411, + &pci_dev_info_1524_1412, + &pci_dev_info_1524_1420, + &pci_dev_info_1524_1421, + &pci_dev_info_1524_1422, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1532[] = { + &pci_dev_info_1532_0020, + NULL +}; +#endif +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1538[] = { + &pci_dev_info_1538_0303, + NULL +}; +#endif +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153b[] = { + &pci_dev_info_153b_1144, + &pci_dev_info_153b_1147, + &pci_dev_info_153b_1158, + NULL +}; +#endif +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153f[] = { + &pci_dev_info_153f_0001, + NULL +}; +#endif +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#define pci_dev_list_1542 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1578[] = { + &pci_dev_info_1578_5615, + NULL +}; +#endif +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0405, + &pci_dev_info_15ad_0710, + &pci_dev_info_15ad_0720, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + &pci_dev_info_15b3_5a44, + &pci_dev_info_15b3_5a45, + &pci_dev_info_15b3_5a46, + &pci_dev_info_15b3_5e8d, + &pci_dev_info_15b3_6274, + &pci_dev_info_15b3_6278, + &pci_dev_info_15b3_6279, + &pci_dev_info_15b3_6282, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_1100, + &pci_dev_info_15bc_2922, + &pci_dev_info_15bc_2928, + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c5[] = { + &pci_dev_info_15c5_8010, + NULL +}; +#endif +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e9[] = { + &pci_dev_info_15e9_1841, + NULL +}; +#endif +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15ec[] = { + &pci_dev_info_15ec_3101, + &pci_dev_info_15ec_5102, + NULL +}; +#endif +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + &pci_dev_info_1619_0610, + &pci_dev_info_1619_0620, + &pci_dev_info_1619_0640, + &pci_dev_info_1619_1610, + &pci_dev_info_1619_2610, + NULL +}; +#endif +#define pci_dev_list_161f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1626[] = { + &pci_dev_info_1626_8410, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1637[] = { + &pci_dev_info_1637_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_3052, + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165f[] = { + &pci_dev_info_165f_1020, + NULL +}; +#endif +#define pci_dev_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1668[] = { + &pci_dev_info_1668_0100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_166d[] = { + &pci_dev_info_166d_0001, + &pci_dev_info_166d_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1677[] = { + &pci_dev_info_1677_104e, + &pci_dev_info_1677_12d7, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167b[] = { + &pci_dev_info_167b_2102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1681[] = { + &pci_dev_info_1681_0010, + NULL +}; +#endif +#define pci_dev_list_1682 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1688[] = { + &pci_dev_info_1688_1170, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_168c[] = { + &pci_dev_info_168c_0007, + &pci_dev_info_168c_0011, + &pci_dev_info_168c_0012, + &pci_dev_info_168c_0013, + &pci_dev_info_168c_001a, + &pci_dev_info_168c_001b, + &pci_dev_info_168c_0020, + &pci_dev_info_168c_1014, + NULL +}; +#endif +#define pci_dev_list_1695 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_169c[] = { + &pci_dev_info_169c_0044, + NULL +}; +#endif +#define pci_dev_list_16a5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1100, + &pci_dev_info_16ab_1101, + &pci_dev_info_16ab_1102, + &pci_dev_info_16ab_8501, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ae[] = { + &pci_dev_info_16ae_1141, + NULL +}; +#endif +#define pci_dev_list_16af NULL +#define pci_dev_list_16b4 NULL +#define pci_dev_list_16b8 NULL +#define pci_dev_list_16be NULL +#define pci_dev_list_16c8 NULL +#define pci_dev_list_16c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ca[] = { + &pci_dev_info_16ca_0001, + NULL +}; +#endif +#define pci_dev_list_16cd NULL +#define pci_dev_list_16ce NULL +#define pci_dev_list_16df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e3[] = { + &pci_dev_info_16e3_1e0f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_00ff, + &pci_dev_info_16ec_0116, + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ed[] = { + &pci_dev_info_16ed_1001, + NULL +}; +#endif +#define pci_dev_list_16f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16f4[] = { + &pci_dev_info_16f4_8000, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1702 NULL +#define pci_dev_list_1705 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_170b[] = { + &pci_dev_info_170b_0100, + NULL +}; +#endif +#define pci_dev_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1725[] = { + &pci_dev_info_1725_7174, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_172a[] = { + &pci_dev_info_172a_13c8, + NULL +}; +#endif +#define pci_dev_list_1734 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1737[] = { + &pci_dev_info_1737_0013, + &pci_dev_info_1737_0015, + &pci_dev_info_1737_1032, + &pci_dev_info_1737_1064, + &pci_dev_info_1737_ab08, + &pci_dev_info_1737_ab09, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03e9, + &pci_dev_info_173b_03ea, + &pci_dev_info_173b_03eb, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_1749 NULL +#define pci_dev_list_174b NULL +#define pci_dev_list_174d NULL +#define pci_dev_list_175c NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1775 NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1799[] = { + &pci_dev_info_1799_6001, + &pci_dev_info_1799_6020, + &pci_dev_info_1799_6060, + &pci_dev_info_1799_7000, + &pci_dev_info_1799_7010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_179c[] = { + &pci_dev_info_179c_0557, + &pci_dev_info_179c_0566, + &pci_dev_info_179c_5031, + &pci_dev_info_179c_5121, + &pci_dev_info_179c_5211, + &pci_dev_info_179c_5679, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17a0[] = { + &pci_dev_info_17a0_8033, + &pci_dev_info_17a0_8034, + NULL +}; +#endif +#define pci_dev_list_17aa NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b3[] = { + &pci_dev_info_17b3_ab08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b4[] = { + &pci_dev_info_17b4_0011, + NULL +}; +#endif +#define pci_dev_list_17c0 NULL +#define pci_dev_list_17c2 NULL +#define pci_dev_list_17cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#define pci_dev_list_17cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d3[] = { + &pci_dev_info_17d3_1110, + &pci_dev_info_17d3_1120, + &pci_dev_info_17d3_1130, + &pci_dev_info_17d3_1160, + &pci_dev_info_17d3_1210, + &pci_dev_info_17d3_1220, + &pci_dev_info_17d3_1230, + &pci_dev_info_17d3_1260, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d5[] = { + &pci_dev_info_17d5_5831, + &pci_dev_info_17d5_5832, + NULL +}; +#endif +#define pci_dev_list_17de NULL +#define pci_dev_list_17ee NULL +#define pci_dev_list_17f2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17fe[] = { + &pci_dev_info_17fe_2120, + &pci_dev_info_17fe_2220, + NULL +}; +#endif +#define pci_dev_list_17ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1814[] = { + &pci_dev_info_1814_0101, + &pci_dev_info_1814_0200, + &pci_dev_info_1814_0201, + &pci_dev_info_1814_0301, + &pci_dev_info_1814_0401, + NULL +}; +#endif +#define pci_dev_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1822[] = { + &pci_dev_info_1822_4e35, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182d[] = { + &pci_dev_info_182d_3069, + &pci_dev_info_182d_9790, + NULL +}; +#endif +#define pci_dev_list_1830 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_183b[] = { + &pci_dev_info_183b_08a7, + &pci_dev_info_183b_08a8, + &pci_dev_info_183b_08a9, + NULL +}; +#endif +#define pci_dev_list_1849 NULL +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#define pci_dev_list_1854 NULL +#define pci_dev_list_185b NULL +#define pci_dev_list_185f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1864[] = { + &pci_dev_info_1864_2110, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1867[] = { + &pci_dev_info_1867_5a44, + &pci_dev_info_1867_5a45, + &pci_dev_info_1867_5a46, + &pci_dev_info_1867_6278, + &pci_dev_info_1867_6282, + NULL +}; +#endif +#define pci_dev_list_187e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#define pci_dev_list_1890 NULL +#define pci_dev_list_1894 NULL +#define pci_dev_list_1896 NULL +#define pci_dev_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ac[] = { + &pci_dev_info_18ac_d500, + &pci_dev_info_18ac_d810, + &pci_dev_info_18ac_d820, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18b8[] = { + &pci_dev_info_18b8_b001, + NULL +}; +#endif +#define pci_dev_list_18bc NULL +#define pci_dev_list_18c8 NULL +#define pci_dev_list_18c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ca[] = { + &pci_dev_info_18ca_0020, + &pci_dev_info_18ca_0040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18d2[] = { + &pci_dev_info_18d2_3069, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18dd[] = { + &pci_dev_info_18dd_4c6f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18e6[] = { + &pci_dev_info_18e6_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ec[] = { + &pci_dev_info_18ec_c006, + &pci_dev_info_18ec_c045, + &pci_dev_info_18ec_c050, + &pci_dev_info_18ec_c058, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f7[] = { + &pci_dev_info_18f7_0001, + &pci_dev_info_18f7_0002, + &pci_dev_info_18f7_0004, + &pci_dev_info_18f7_0005, + &pci_dev_info_18f7_000a, + NULL +}; +#endif +#define pci_dev_list_18fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1923[] = { + &pci_dev_info_1923_0100, + NULL +}; +#endif +#define pci_dev_list_1924 NULL +#define pci_dev_list_192e NULL +#define pci_dev_list_1931 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1942[] = { + &pci_dev_info_1942_e511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1957[] = { + &pci_dev_info_1957_0080, + &pci_dev_info_1957_0081, + &pci_dev_info_1957_0082, + &pci_dev_info_1957_0083, + &pci_dev_info_1957_0084, + &pci_dev_info_1957_0085, + &pci_dev_info_1957_0086, + &pci_dev_info_1957_0087, + NULL +}; +#endif +#define pci_dev_list_1958 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1966[] = { + &pci_dev_info_1966_1975, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_196a[] = { + &pci_dev_info_196a_0101, + &pci_dev_info_196a_0102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_197b[] = { + &pci_dev_info_197b_2360, + &pci_dev_info_197b_2363, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1989[] = { + &pci_dev_info_1989_0001, + &pci_dev_info_1989_8001, + NULL +}; +#endif +#define pci_dev_list_1993 NULL +#define pci_dev_list_19a8 NULL +#define pci_dev_list_19ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ae[] = { + &pci_dev_info_19ae_0520, + NULL +}; +#endif +#define pci_dev_list_19d4 NULL +#define pci_dev_list_19e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc0[] = { + &pci_dev_info_1fc0_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc1[] = { + &pci_dev_info_1fc1_000d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fce[] = { + &pci_dev_info_1fce_0001, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0020, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_0022, + &pci_dev_info_3388_0026, + &pci_dev_info_3388_101a, + &pci_dev_info_3388_101b, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3842[] = { + &pci_dev_info_3842_c370, + NULL +}; +#endif +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_000d, + &pci_dev_info_3d3d_0011, + &pci_dev_info_3d3d_0012, + &pci_dev_info_3d3d_0013, + &pci_dev_info_3d3d_0020, + &pci_dev_info_3d3d_0022, + &pci_dev_info_3d3d_0024, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_07a1, + &pci_dev_info_3d3d_07a2, + &pci_dev_info_3d3d_07a3, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4144[] = { + &pci_dev_info_4144_0044, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#define pci_dev_list_4321 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0016, + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_494f[] = { + &pci_dev_info_494f_10e8, + NULL +}; +#endif +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4c53[] = { + &pci_dev_info_4c53_0000, + &pci_dev_info_4c53_0001, + NULL +}; +#endif +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5168[] = { + &pci_dev_info_5168_0301, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_544c[] = { + &pci_dev_info_544c_0350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5654[] = { + &pci_dev_info_5654_3132, + NULL +}; +#endif +#define pci_dev_list_5700 NULL +#define pci_dev_list_5851 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + &pci_dev_info_6666_0004, + &pci_dev_info_6666_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_7063[] = { + &pci_dev_info_7063_2000, + &pci_dev_info_7063_3000, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +#define pci_dev_list_807d NULL +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0309, + &pci_dev_info_8086_030d, + &pci_dev_info_8086_0326, + &pci_dev_info_8086_0327, + &pci_dev_info_8086_0329, + &pci_dev_info_8086_032a, + &pci_dev_info_8086_032c, + &pci_dev_info_8086_0330, + &pci_dev_info_8086_0331, + &pci_dev_info_8086_0332, + &pci_dev_info_8086_0333, + &pci_dev_info_8086_0334, + &pci_dev_info_8086_0335, + &pci_dev_info_8086_0336, + &pci_dev_info_8086_0340, + &pci_dev_info_8086_0341, + &pci_dev_info_8086_0370, + &pci_dev_info_8086_0371, + &pci_dev_info_8086_0372, + &pci_dev_info_8086_0373, + &pci_dev_info_8086_0374, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0500, + &pci_dev_info_8086_0501, + &pci_dev_info_8086_0502, + &pci_dev_info_8086_0503, + &pci_dev_info_8086_0510, + &pci_dev_info_8086_0511, + &pci_dev_info_8086_0512, + &pci_dev_info_8086_0513, + &pci_dev_info_8086_0514, + &pci_dev_info_8086_0515, + &pci_dev_info_8086_0516, + &pci_dev_info_8086_0530, + &pci_dev_info_8086_0531, + &pci_dev_info_8086_0532, + &pci_dev_info_8086_0533, + &pci_dev_info_8086_0534, + &pci_dev_info_8086_0535, + &pci_dev_info_8086_0536, + &pci_dev_info_8086_0537, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_061f, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100a, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1013, + &pci_dev_info_8086_1014, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1016, + &pci_dev_info_8086_1017, + &pci_dev_info_8086_1018, + &pci_dev_info_8086_1019, + &pci_dev_info_8086_101a, + &pci_dev_info_8086_101d, + &pci_dev_info_8086_101e, + &pci_dev_info_8086_1026, + &pci_dev_info_8086_1027, + &pci_dev_info_8086_1028, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1043, + &pci_dev_info_8086_1048, + &pci_dev_info_8086_104b, + &pci_dev_info_8086_1050, + &pci_dev_info_8086_1051, + &pci_dev_info_8086_1052, + &pci_dev_info_8086_1053, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_105e, + &pci_dev_info_8086_105f, + &pci_dev_info_8086_1060, + &pci_dev_info_8086_1064, + &pci_dev_info_8086_1065, + &pci_dev_info_8086_1066, + &pci_dev_info_8086_1067, + &pci_dev_info_8086_1068, + &pci_dev_info_8086_1069, + &pci_dev_info_8086_106a, + &pci_dev_info_8086_106b, + &pci_dev_info_8086_1075, + &pci_dev_info_8086_1076, + &pci_dev_info_8086_1077, + &pci_dev_info_8086_1078, + &pci_dev_info_8086_1079, + &pci_dev_info_8086_107a, + &pci_dev_info_8086_107b, + &pci_dev_info_8086_107c, + &pci_dev_info_8086_107d, + &pci_dev_info_8086_107e, + &pci_dev_info_8086_107f, + &pci_dev_info_8086_1080, + &pci_dev_info_8086_1081, + &pci_dev_info_8086_1082, + &pci_dev_info_8086_1083, + &pci_dev_info_8086_1084, + &pci_dev_info_8086_1085, + &pci_dev_info_8086_1086, + &pci_dev_info_8086_1087, + &pci_dev_info_8086_1089, + &pci_dev_info_8086_108a, + &pci_dev_info_8086_108b, + &pci_dev_info_8086_108c, + &pci_dev_info_8086_1096, + &pci_dev_info_8086_1097, + &pci_dev_info_8086_1098, + &pci_dev_info_8086_1099, + &pci_dev_info_8086_109a, + &pci_dev_info_8086_1107, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123e, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_1a38, + &pci_dev_info_8086_1a48, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c1, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24ca, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cc, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_24d0, + &pci_dev_info_8086_24d1, + &pci_dev_info_8086_24d2, + &pci_dev_info_8086_24d3, + &pci_dev_info_8086_24d4, + &pci_dev_info_8086_24d5, + &pci_dev_info_8086_24d6, + &pci_dev_info_8086_24d7, + &pci_dev_info_8086_24db, + &pci_dev_info_8086_24dc, + &pci_dev_info_8086_24dd, + &pci_dev_info_8086_24de, + &pci_dev_info_8086_24df, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_254c, + &pci_dev_info_8086_2550, + &pci_dev_info_8086_2551, + &pci_dev_info_8086_2552, + &pci_dev_info_8086_2553, + &pci_dev_info_8086_2554, + &pci_dev_info_8086_255d, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2571, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_2573, + &pci_dev_info_8086_2576, + &pci_dev_info_8086_2578, + &pci_dev_info_8086_2579, + &pci_dev_info_8086_257b, + &pci_dev_info_8086_257e, + &pci_dev_info_8086_2580, + &pci_dev_info_8086_2581, + &pci_dev_info_8086_2582, + &pci_dev_info_8086_2584, + &pci_dev_info_8086_2585, + &pci_dev_info_8086_2588, + &pci_dev_info_8086_2589, + &pci_dev_info_8086_258a, + &pci_dev_info_8086_2590, + &pci_dev_info_8086_2591, + &pci_dev_info_8086_2592, + &pci_dev_info_8086_25a1, + &pci_dev_info_8086_25a2, + &pci_dev_info_8086_25a3, + &pci_dev_info_8086_25a4, + &pci_dev_info_8086_25a6, + &pci_dev_info_8086_25a7, + &pci_dev_info_8086_25a9, + &pci_dev_info_8086_25aa, + &pci_dev_info_8086_25ab, + &pci_dev_info_8086_25ac, + &pci_dev_info_8086_25ad, + &pci_dev_info_8086_25ae, + &pci_dev_info_8086_25b0, + &pci_dev_info_8086_25c0, + &pci_dev_info_8086_25d0, + &pci_dev_info_8086_25d4, + &pci_dev_info_8086_25d8, + &pci_dev_info_8086_25e2, + &pci_dev_info_8086_25e3, + &pci_dev_info_8086_25e4, + &pci_dev_info_8086_25e5, + &pci_dev_info_8086_25e6, + &pci_dev_info_8086_25e7, + &pci_dev_info_8086_25e8, + &pci_dev_info_8086_25f0, + &pci_dev_info_8086_25f1, + &pci_dev_info_8086_25f3, + &pci_dev_info_8086_25f5, + &pci_dev_info_8086_25f6, + &pci_dev_info_8086_25f7, + &pci_dev_info_8086_25f8, + &pci_dev_info_8086_25f9, + &pci_dev_info_8086_25fa, + &pci_dev_info_8086_2600, + &pci_dev_info_8086_2601, + &pci_dev_info_8086_2602, + &pci_dev_info_8086_2603, + &pci_dev_info_8086_2604, + &pci_dev_info_8086_2605, + &pci_dev_info_8086_2606, + &pci_dev_info_8086_2607, + &pci_dev_info_8086_2608, + &pci_dev_info_8086_2609, + &pci_dev_info_8086_260a, + &pci_dev_info_8086_260c, + &pci_dev_info_8086_2610, + &pci_dev_info_8086_2611, + &pci_dev_info_8086_2612, + &pci_dev_info_8086_2613, + &pci_dev_info_8086_2614, + &pci_dev_info_8086_2615, + &pci_dev_info_8086_2617, + &pci_dev_info_8086_2618, + &pci_dev_info_8086_2619, + &pci_dev_info_8086_261a, + &pci_dev_info_8086_261b, + &pci_dev_info_8086_261c, + &pci_dev_info_8086_261d, + &pci_dev_info_8086_261e, + &pci_dev_info_8086_2620, + &pci_dev_info_8086_2621, + &pci_dev_info_8086_2622, + &pci_dev_info_8086_2623, + &pci_dev_info_8086_2624, + &pci_dev_info_8086_2625, + &pci_dev_info_8086_2626, + &pci_dev_info_8086_2627, + &pci_dev_info_8086_2640, + &pci_dev_info_8086_2641, + &pci_dev_info_8086_2642, + &pci_dev_info_8086_2651, + &pci_dev_info_8086_2652, + &pci_dev_info_8086_2653, + &pci_dev_info_8086_2658, + &pci_dev_info_8086_2659, + &pci_dev_info_8086_265a, + &pci_dev_info_8086_265b, + &pci_dev_info_8086_265c, + &pci_dev_info_8086_2660, + &pci_dev_info_8086_2662, + &pci_dev_info_8086_2664, + &pci_dev_info_8086_2666, + &pci_dev_info_8086_2668, + &pci_dev_info_8086_266a, + &pci_dev_info_8086_266c, + &pci_dev_info_8086_266d, + &pci_dev_info_8086_266e, + &pci_dev_info_8086_266f, + &pci_dev_info_8086_2670, + &pci_dev_info_8086_2680, + &pci_dev_info_8086_2681, + &pci_dev_info_8086_2682, + &pci_dev_info_8086_2683, + &pci_dev_info_8086_2688, + &pci_dev_info_8086_2689, + &pci_dev_info_8086_268a, + &pci_dev_info_8086_268b, + &pci_dev_info_8086_268c, + &pci_dev_info_8086_2690, + &pci_dev_info_8086_2692, + &pci_dev_info_8086_2694, + &pci_dev_info_8086_2696, + &pci_dev_info_8086_2698, + &pci_dev_info_8086_2699, + &pci_dev_info_8086_269a, + &pci_dev_info_8086_269b, + &pci_dev_info_8086_269e, + &pci_dev_info_8086_2770, + &pci_dev_info_8086_2771, + &pci_dev_info_8086_2772, + &pci_dev_info_8086_2774, + &pci_dev_info_8086_2775, + &pci_dev_info_8086_2776, + &pci_dev_info_8086_2778, + &pci_dev_info_8086_2779, + &pci_dev_info_8086_277a, + &pci_dev_info_8086_277c, + &pci_dev_info_8086_277d, + &pci_dev_info_8086_2782, + &pci_dev_info_8086_2792, + &pci_dev_info_8086_27a0, + &pci_dev_info_8086_27a1, + &pci_dev_info_8086_27a2, + &pci_dev_info_8086_27a6, + &pci_dev_info_8086_27b0, + &pci_dev_info_8086_27b8, + &pci_dev_info_8086_27b9, + &pci_dev_info_8086_27bd, + &pci_dev_info_8086_27c0, + &pci_dev_info_8086_27c1, + &pci_dev_info_8086_27c3, + &pci_dev_info_8086_27c4, + &pci_dev_info_8086_27c5, + &pci_dev_info_8086_27c6, + &pci_dev_info_8086_27c8, + &pci_dev_info_8086_27c9, + &pci_dev_info_8086_27ca, + &pci_dev_info_8086_27cb, + &pci_dev_info_8086_27cc, + &pci_dev_info_8086_27d0, + &pci_dev_info_8086_27d2, + &pci_dev_info_8086_27d4, + &pci_dev_info_8086_27d6, + &pci_dev_info_8086_27d8, + &pci_dev_info_8086_27da, + &pci_dev_info_8086_27dc, + &pci_dev_info_8086_27dd, + &pci_dev_info_8086_27de, + &pci_dev_info_8086_27df, + &pci_dev_info_8086_27e0, + &pci_dev_info_8086_27e2, + &pci_dev_info_8086_2810, + &pci_dev_info_8086_2811, + &pci_dev_info_8086_2812, + &pci_dev_info_8086_2814, + &pci_dev_info_8086_2815, + &pci_dev_info_8086_2820, + &pci_dev_info_8086_2821, + &pci_dev_info_8086_2822, + &pci_dev_info_8086_2824, + &pci_dev_info_8086_2825, + &pci_dev_info_8086_2828, + &pci_dev_info_8086_2829, + &pci_dev_info_8086_282a, + &pci_dev_info_8086_2830, + &pci_dev_info_8086_2831, + &pci_dev_info_8086_2832, + &pci_dev_info_8086_2834, + &pci_dev_info_8086_2835, + &pci_dev_info_8086_2836, + &pci_dev_info_8086_283a, + &pci_dev_info_8086_283e, + &pci_dev_info_8086_283f, + &pci_dev_info_8086_2841, + &pci_dev_info_8086_2843, + &pci_dev_info_8086_2844, + &pci_dev_info_8086_2847, + &pci_dev_info_8086_2849, + &pci_dev_info_8086_284b, + &pci_dev_info_8086_284f, + &pci_dev_info_8086_2850, + &pci_dev_info_8086_2970, + &pci_dev_info_8086_2971, + &pci_dev_info_8086_2972, + &pci_dev_info_8086_2973, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3200, + &pci_dev_info_8086_3340, + &pci_dev_info_8086_3341, + &pci_dev_info_8086_3500, + &pci_dev_info_8086_3501, + &pci_dev_info_8086_3504, + &pci_dev_info_8086_3505, + &pci_dev_info_8086_350c, + &pci_dev_info_8086_350d, + &pci_dev_info_8086_3510, + &pci_dev_info_8086_3511, + &pci_dev_info_8086_3514, + &pci_dev_info_8086_3515, + &pci_dev_info_8086_3518, + &pci_dev_info_8086_3519, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3581, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_3584, + &pci_dev_info_8086_3585, + &pci_dev_info_8086_3590, + &pci_dev_info_8086_3591, + &pci_dev_info_8086_3592, + &pci_dev_info_8086_3593, + &pci_dev_info_8086_3594, + &pci_dev_info_8086_3595, + &pci_dev_info_8086_3596, + &pci_dev_info_8086_3597, + &pci_dev_info_8086_3598, + &pci_dev_info_8086_3599, + &pci_dev_info_8086_359a, + &pci_dev_info_8086_359b, + &pci_dev_info_8086_359e, + &pci_dev_info_8086_4220, + &pci_dev_info_8086_4223, + &pci_dev_info_8086_4224, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7050, + &pci_dev_info_8086_7051, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_8500, + &pci_dev_info_8086_9000, + &pci_dev_info_8086_9001, + &pci_dev_info_8086_9004, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + NULL +}; +#define pci_dev_list_8401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8912 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8c4a[] = { + &pci_dev_info_8c4a_1980, + NULL +}; +#endif +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_0078, + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7710, + &pci_dev_info_9004_7711, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + NULL +}; +#endif + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_dev_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_dev_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_dev_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_dev_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_dev_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_dev_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_dev_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_dev_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_dev_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_dev_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_dev_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_dev_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_dev_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_dev_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_dev_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_dev_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_dev_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_dev_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_dev_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_dev_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_dev_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_dev_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_dev_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_dev_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_dev_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_dev_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_dev_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_dev_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_dev_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_dev_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_dev_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_dev_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_dev_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_dev_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_dev_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_dev_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_dev_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_dev_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_dev_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_dev_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_dev_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_dev_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_dev_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_dev_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_dev_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_dev_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_dev_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_dev_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_dev_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_dev_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_dev_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_dev_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_dev_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_dev_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_dev_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_dev_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_dev_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_dev_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_dev_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_dev_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_dev_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_dev_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_dev_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_dev_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_dev_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_dev_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_dev_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_dev_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_dev_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_dev_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_dev_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_dev_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_dev_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_dev_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_dev_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_dev_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_dev_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_dev_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_dev_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_dev_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_dev_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_dev_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_dev_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_dev_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_dev_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_dev_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_dev_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_dev_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_dev_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_dev_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_dev_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_dev_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_dev_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_dev_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_dev_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_dev_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_dev_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_dev_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_dev_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_dev_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_dev_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_dev_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_dev_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_dev_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_dev_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_dev_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_dev_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_dev_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_dev_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_dev_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_dev_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_dev_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_dev_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_dev_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_dev_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_dev_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_dev_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_dev_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_dev_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_dev_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_dev_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_dev_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_dev_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_dev_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_dev_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_dev_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_dev_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_dev_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_dev_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_ss_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_ss_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_ss_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_ss_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_ss_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_ss_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_ss_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_ss_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_ss_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_ss_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_ss_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_ss_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_ss_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_ss_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_ss_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_ss_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_ss_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_ss_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_ss_list_0b49}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_ss_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_ss_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_ss_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_ss_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_ss_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_ss_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_ss_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_ss_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_ss_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_ss_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_ss_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_ss_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_ss_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_ss_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_ss_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_ss_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_ss_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_ss_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_ss_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_ss_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_ss_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_ss_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_ss_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_ss_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_ss_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_ss_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_ss_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_ss_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_ss_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_ss_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_ss_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_ss_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_ss_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_ss_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_ss_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_ss_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_ss_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_ss_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_ss_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_ss_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_ss_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_ss_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_ss_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_ss_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_ss_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_ss_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_ss_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_ss_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_ss_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_ss_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_ss_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_ss_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_ss_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_ss_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_ss_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_ss_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_ss_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_ss_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_ss_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_ss_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_ss_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_ss_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_ss_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_ss_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_ss_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_ss_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_ss_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_ss_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_ss_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_ss_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_ss_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_ss_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_ss_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_ss_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_ss_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_ss_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_ss_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_ss_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_ss_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_ss_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_ss_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_ss_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_ss_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_ss_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_ss_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_ss_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_ss_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_ss_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_ss_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_ss_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_ss_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_ss_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_ss_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_ss_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_ss_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_ss_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_ss_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_ss_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_ss_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_ss_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_ss_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_ss_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_ss_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_ss_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_ss_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_ss_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_ss_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_ss_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_ss_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_ss_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif + {0x0000, NULL, NULL} +}; +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86PciStr.h (revision 51223) @@ -0,0 +1,67 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86PciStr.h,v 1.2 2003/08/24 17:37:10 dawes Exp $ */ +/* + * Copyright (c) 2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * Structs used to hold the pre-parsed pci.ids data. These are private + * to the scanpci and pcidata modules. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_PCISTR_H +#define _XF86_PCISTR_H + +typedef struct { + unsigned short VendorID; + unsigned short SubsystemID; + const char *SubsystemName; + unsigned short class; +} pciSubsystemInfo; + +typedef struct { + unsigned short DeviceID; + const char *DeviceName; + const pciSubsystemInfo **Subsystem; + unsigned short class; +} pciDeviceInfo; + +typedef struct { + unsigned short VendorID; + const char *VendorName; + const pciDeviceInfo **Device; +} pciVendorInfo; + +typedef struct { + unsigned short VendorID; + const char *VendorName; + const pciSubsystemInfo **Subsystem; +} pciVendorSubsysInfo; + +#endif /* _XF86_PCISTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Priv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Priv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Priv.h (revision 51223) @@ -0,0 +1,228 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Priv.h,v 3.83 2004/01/27 01:31:45 dawes Exp $ */ + +/* + * Copyright (c) 1997-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains declarations for private XFree86 functions and variables, + * and definitions of private macros. + * + * "private" means not available to video drivers. + */ + +#ifndef _XF86PRIV_H +#define _XF86PRIV_H + +#include "xf86Privstr.h" +#include "propertyst.h" + +/* + * Parameters set ONLY from the command line options + * The global state of these things is held in xf86InfoRec (when appropriate). + */ +extern const char *xf86ConfigFile; +extern Bool xf86AllowMouseOpenFail; +#ifdef XF86VIDMODE +extern Bool xf86VidModeDisabled; +extern Bool xf86VidModeAllowNonLocal; +#endif +#ifdef XF86MISC +extern Bool xf86MiscModInDevDisabled; +extern Bool xf86MiscModInDevAllowNonLocal; +#endif +extern Bool xf86fpFlag; +extern Bool xf86coFlag; +extern Bool xf86sFlag; +extern Bool xf86bsEnableFlag; +extern Bool xf86bsDisableFlag; +extern Bool xf86silkenMouseDisableFlag; +extern Bool xf86acpiDisableFlag; +extern char *xf86LayoutName; +extern char *xf86ScreenName; +extern char *xf86PointerName; +extern char *xf86KeyboardName; +#ifdef KEEPBPP +extern int xf86Bpp; +#endif +extern int xf86FbBpp; +extern int xf86Depth; +extern Pix24Flags xf86Pix24; +extern rgb xf86Weight; +extern Bool xf86FlipPixels; +extern Bool xf86BestRefresh; +extern Gamma xf86Gamma; +extern char *xf86ServerName; +extern Bool xf86ShowUnresolved; +extern PciBusId xf86IsolateDevice; + +/* Other parameters */ + +extern xf86InfoRec xf86Info; +extern const char *xf86InputDeviceList; +extern const char *xf86ModulePath; +extern MessageType xf86ModPathFrom; +extern const char *xf86LogFile; +extern MessageType xf86LogFileFrom; +extern Bool xf86LogFileWasOpened; +extern serverLayoutRec xf86ConfigLayout; +extern Pix24Flags xf86ConfigPix24; + +extern unsigned short xf86MouseCflags[]; +extern Bool xf86SupportedMouseTypes[]; +extern int xf86NumMouseTypes; + +#ifdef XFree86LOADER +extern DriverPtr *xf86DriverList; +extern ModuleInfoPtr *xf86ModuleInfoList; +extern int xf86NumModuleInfos; +#else +extern DriverPtr xf86DriverList[]; +#endif +extern int xf86NumDrivers; +extern Bool xf86Resetting; +extern Bool xf86Initialising; +extern Bool xf86ProbeFailed; +extern int xf86NumScreens; +extern pciVideoPtr *xf86PciVideoInfo; +extern xf86CurrentAccessRec xf86CurrentAccess; +extern const char *xf86VisualNames[]; +extern int xf86Verbose; /* verbosity level */ +extern int xf86LogVerbose; /* log file verbosity level */ +extern Bool xf86ProbeOnly; +extern Bool xf86DoProbe; +extern Bool xorgHWAccess; + +extern RootWinPropPtr *xf86RegisteredPropertiesTable; + +#ifndef DEFAULT_VERBOSE +#define DEFAULT_VERBOSE 0 +#endif +#ifndef DEFAULT_LOG_VERBOSE +#define DEFAULT_LOG_VERBOSE 3 +#endif +#ifndef DEFAULT_DPI +#define DEFAULT_DPI 75 +#endif + +#define DEFAULT_UNRESOLVED TRUE +#define DEFAULT_BEST_REFRESH FALSE + +/* Function Prototypes */ +#ifndef _NO_XF86_PROTOTYPES + +/* xf86Bus.c */ + +void xf86BusProbe(void); +void xf86ChangeBusIndex(int oldIndex, int newIndex); +void xf86AccessInit(void); +void xf86AccessEnter(void); +void xf86AccessLeave(void); +void xf86EntityInit(void); +void xf86EntityEnter(void); +void xf86EntityLeave(void); +void xf86AccessLeaveState(void); + +void xf86FindPrimaryDevice(void); +/* new RAC */ +void xf86ResourceBrokerInit(void); +void xf86PostProbe(void); +void xf86ClearEntityListForScreen(int scrnIndex); +void xf86AddDevToEntity(int entityIndex, GDevPtr dev); +extern void xf86PostPreInit(void); +extern void xf86PostScreenInit(void); +extern memType getValidBIOSBase(PCITAG tag, int num); +extern memType getEmptyPciRange(PCITAG tag, int base_reg); +extern int pciTestMultiDeviceCard(int bus, int dev, int func, PCITAG** pTag); + +/* xf86Config.c */ + +Bool xf86PathIsAbsolute(const char *path); +Bool xf86PathIsSafe(const char *path); + +/* xf86DefaultModes */ + +extern DisplayModeRec xf86DefaultModes []; + +/* xf86DoScanPci.c */ + +void DoScanPci(int argc, char **argv, int i); + +/* xf86DoProbe.c */ +void DoProbe(void); +void DoConfigure(void); + +/* xf86Events.c */ + +void xf86PostKbdEvent(unsigned key); +void xf86PostMseEvent(DeviceIntPtr device, int buttons, int dx, int dy); +void xf86Wakeup(pointer blockData, int err, pointer pReadmask); +void xf86SigHandler(int signo); +#ifdef MEMDEBUG +void xf86SigMemDebug(int signo); +#endif +void xf86HandlePMEvents(int fd, pointer data); +extern int (*xf86PMGetEventFromOs)(int fd,pmEvent *events,int num); +extern pmWait (*xf86PMConfirmEventToOs)(int fd,pmEvent event); +void xf86GrabServerCallback(CallbackListPtr *, pointer, pointer); + +/* xf86Helper.c */ +void xf86LogInit(void); +void xf86CloseLog(void); + +/* xf86Init.c */ +Bool xf86LoadModules(char **list, pointer *optlist); +int xf86SetVerbosity(int verb); +int xf86SetLogVerbosity(int verb); + +/* xf86Io.c */ + +void xf86KbdBell(int percent, DeviceIntPtr pKeyboard, pointer ctrl, + int unused); +void xf86KbdLeds(void); +void xf86UpdateKbdLeds(void); +void xf86KbdCtrl(DevicePtr pKeyboard, KeybdCtrl *ctrl); +void xf86InitKBD(Bool init); +int xf86KbdProc(DeviceIntPtr pKeyboard, int what); + +/* xf86Kbd.c */ + +void xf86KbdGetMapping(KeySymsPtr pKeySyms, CARD8 *pModMap); + +/* xf86Lock.c */ + +#ifdef USE_XF86_SERVERLOCK +void xf86UnlockServer(void); +#endif + +/* xf86XKB.c */ + +void xf86InitXkb(void); + +#endif /* _NO_XF86_PROTOTYPES */ + + +#endif /* _XF86PRIV_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Privstr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Privstr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Privstr.h (revision 51223) @@ -0,0 +1,236 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Privstr.h,v 1.41 2004/01/27 01:31:45 dawes Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the private XFree86 data structures/types. + * None of the data structures here should be used by video drivers. + */ + +#ifndef _XF86PRIVSTR_H +#define _XF86PRIVSTR_H + +#include "xf86Pci.h" +#include "xf86str.h" + +/* PCI probe flags */ + +typedef enum { + PCIProbe1 = 0, + PCIProbe2, + PCIForceConfig1, + PCIForceConfig2, + PCIForceNone, + PCIOsConfig +} PciProbeType; + +typedef enum { + LogNone, + LogFlush, + LogSync +} Log; + +typedef enum { + SKNever, + SKWhenNeeded, + SKAlways +} SpecialKeysInDDX; + +/* + * xf86InfoRec contains global parameters which the video drivers never + * need to access. Global parameters which the video drivers do need + * should be individual globals. + */ + +typedef struct { + + /* keyboard part */ + DeviceIntPtr pKeyboard; + DeviceProc kbdProc; /* procedure for initializing */ + void (* kbdEvents)(void); /* proc for processing events */ + int consoleFd; + int kbdFd; + int vtno; + int kbdType; /* AT84 / AT101 */ + int kbdRate; + int kbdDelay; + int bell_pitch; + int bell_duration; + Bool autoRepeat; + unsigned long leds; + unsigned long xleds; + char * vtinit; + int scanPrefix; /* scancode-state */ + Bool capsLock; + Bool numLock; + Bool scrollLock; + Bool modeSwitchLock; + Bool composeLock; + Bool vtSysreq; + SpecialKeysInDDX ddxSpecialKeys; + Bool ActionKeyBindingsSet; +#if defined(SVR4) && defined(i386) + Bool panix106; +#endif /* SVR4 && i386 */ +#if defined(__OpenBSD__) || defined(__NetBSD__) + int wsKbdType; +#endif + + /* mouse part */ + DeviceIntPtr pMouse; +#ifdef XINPUT + pointer mouseLocal; +#endif + + /* event handler part */ + int lastEventTime; + Bool vtRequestsPending; + Bool inputPending; + Bool dontVTSwitch; + Bool dontZap; + Bool dontZoom; + Bool notrapSignals; /* don't exit cleanly - die at fault */ + Bool caughtSignal; + + /* graphics part */ + Bool sharedMonitor; + ScreenPtr currentScreen; +#if defined(CSRG_BASED) || defined(__FreeBSD_kernel__) + int screenFd; /* fd for memory mapped access to + * vga card */ + int consType; /* Which console driver? */ +#endif + +#ifdef XKB + /* + * would like to use an XkbComponentNamesRec here but can't without + * pulling in a bunch of header files. :-( + */ + char * xkbkeymap; + char * xkbkeycodes; + char * xkbtypes; + char * xkbcompat; + char * xkbsymbols; + char * xkbgeometry; + Bool xkbcomponents_specified; + char * xkbrules; + char * xkbmodel; + char * xkblayout; + char * xkbvariant; + char * xkboptions; +#endif + + /* Other things */ + Bool allowMouseOpenFail; + Bool vidModeEnabled; /* VidMode extension enabled */ + Bool vidModeAllowNonLocal; /* allow non-local VidMode + * connections */ + Bool miscModInDevEnabled; /* Allow input devices to be + * changed */ + Bool miscModInDevAllowNonLocal; + PciProbeType pciFlags; + Pix24Flags pixmap24; + MessageType pix24From; +#if defined(i386) || defined(__i386__) + Bool pc98; +#endif + Bool pmFlag; + Log log; + int estimateSizesAggressively; + Bool kbdCustomKeycodes; + Bool disableRandR; + MessageType randRFrom; + Bool aiglx; + MessageType aiglxFrom; + struct { + Bool disabled; /* enable/disable deactivating + * grabs or closing the + * connection to the grabbing + * client */ + ClientPtr override; /* client that disabled + * grab deactivation. + */ + Bool allowDeactivate; + Bool allowClosedown; + ServerGrabInfoRec server; + } grabInfo; +} xf86InfoRec, *xf86InfoPtr; + +#ifdef DPMSExtension +/* Private info for DPMS */ +typedef struct { + CloseScreenProcPtr CloseScreen; + Bool Enabled; + int Flags; +} DPMSRec, *DPMSPtr; +#endif + +#ifdef XF86VIDMODE +/* Private info for Video Mode Extentsion */ +typedef struct { + DisplayModePtr First; + DisplayModePtr Next; + int Flags; + CloseScreenProcPtr CloseScreen; +} VidModeRec, *VidModePtr; +#endif + +/* Information for root window properties. */ +typedef struct _RootWinProp { + struct _RootWinProp * next; + char * name; + Atom type; + short format; + long size; + pointer data; +} RootWinProp, *RootWinPropPtr; + +/* private resource types */ +#define ResNoAvoid ResBios + +/* ISC's cc can't handle ~ of UL constants, so explicitly type cast them. */ +#define XLED1 ((unsigned long) 0x00000001) +#define XLED2 ((unsigned long) 0x00000002) +#define XLED3 ((unsigned long) 0x00000004) +#define XLED4 ((unsigned long) 0x00000008) +#define XCAPS ((unsigned long) 0x20000000) +#define XNUM ((unsigned long) 0x40000000) +#define XSCR ((unsigned long) 0x80000000) +#define XCOMP ((unsigned long) 0x00008000) + +/* BSD console driver types (consType) */ +#if defined(CSRG_BASED) || defined(__FreeBSD_kernel__) +#define PCCONS 0 +#define CODRV011 1 +#define CODRV01X 2 +#define SYSCONS 8 +#define PCVT 16 +#define WSCONS 32 +#endif + +#endif /* _XF86PRIVSTR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RAC.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RAC.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RAC.h (revision 51223) @@ -0,0 +1,18 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/rac/xf86RAC.h,v 1.2 1999/05/15 12:10:33 dawes Exp $ */ + +#ifndef __XF86RAC_H +#define __XF86RAC_H 1 + +#include "screenint.h" +#include "misc.h" +#include "xf86.h" + +Bool xf86RACInit(ScreenPtr pScreen, unsigned int flag); + +/* flags */ +#define RAC_FB 0x01 +#define RAC_CURSOR 0x02 +#define RAC_COLORMAP 0x04 +#define RAC_VIEWPORT 0x08 + +#endif /* __XF86RAC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDac.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDac.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDac.h (revision 51223) @@ -0,0 +1,124 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86RamDac.h,v 1.9 1999/03/28 15:33:02 dawes Exp $ */ + +#ifndef _XF86RAMDAC_H +#define _XF86RAMDAC_H 1 + +#include "colormapst.h" +#include "xf86Cursor.h" + +/* Define unique vendor codes for RAMDAC's */ +#define VENDOR_IBM 0x0000 +#define VENDOR_BT 0x0001 +#define VENDOR_TI 0x0002 + +typedef struct _RamDacRegRec { +/* This is probably the nastiest assumption, we allocate 1024 slots for + * ramdac registers, should be enough. I've checked IBM and TVP series + * and they seem o.k + * Then we allocate 768 entries for the DAC too. IBM640 needs 1024 -FIXME + */ + unsigned short DacRegs[0x400]; /* register set */ + unsigned char DAC[0x300]; /* colour map */ + Bool Overlay; +} RamDacRegRec, *RamDacRegRecPtr; + +typedef struct _RamDacHWRegRec { + RamDacRegRec SavedReg; + RamDacRegRec ModeReg; +} RamDacHWRec, *RamDacHWRecPtr; + +typedef struct _RamDacRec { + CARD32 RamDacType; + + void (*LoadPalette)( + ScrnInfoPtr pScrn, + int numColors, + int *indices, + LOCO *colors, + VisualPtr pVisual + ); + + unsigned char (*ReadDAC)( + ScrnInfoPtr pScrn, + CARD32 + ); + + void (*WriteDAC)( + ScrnInfoPtr pScrn, + CARD32, + unsigned char, + unsigned char + ); + + void (*WriteAddress)( + ScrnInfoPtr pScrn, + CARD32 + ); + + void (*WriteData)( + ScrnInfoPtr pScrn, + unsigned char + ); + + void (*ReadAddress)( + ScrnInfoPtr pScrn, + CARD32 + ); + + unsigned char (*ReadData)( + ScrnInfoPtr pScrn + ); +} RamDacRec, *RamDacRecPtr; + +typedef struct _RamDacHelperRec { + CARD32 RamDacType; + + void (*Restore)( + ScrnInfoPtr pScrn, + RamDacRecPtr ramdacPtr, + RamDacRegRecPtr ramdacReg + ); + + void (*Save)( + ScrnInfoPtr pScrn, + RamDacRecPtr ramdacPtr, + RamDacRegRecPtr ramdacReg + ); + + void (*SetBpp)( + ScrnInfoPtr pScrn, + RamDacRegRecPtr ramdacReg + ); + + void (*HWCursorInit)( + xf86CursorInfoPtr infoPtr + ); +} RamDacHelperRec, *RamDacHelperRecPtr; + +#define RAMDACHWPTR(p) ((RamDacHWRecPtr)((p)->privates[RamDacGetHWIndex()].ptr)) + +typedef struct _RamdacScreenRec { + RamDacRecPtr RamDacRec; +} RamDacScreenRec, *RamDacScreenRecPtr; +#define RAMDACSCRPTR(p) ((RamDacScreenRecPtr)((p)->privates[RamDacGetScreenIndex()].ptr))->RamDacRec + +extern int RamDacHWPrivateIndex; +extern int RamDacScreenPrivateIndex; + +typedef struct { + int token; +} RamDacSupportedInfoRec, *RamDacSupportedInfoRecPtr; + +RamDacRecPtr RamDacCreateInfoRec(void); +RamDacHelperRecPtr RamDacHelperCreateInfoRec(void); +void RamDacDestroyInfoRec(RamDacRecPtr RamDacRec); +void RamDacHelperDestroyInfoRec(RamDacHelperRecPtr RamDacRec); +Bool RamDacInit(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec); +void RamDacSetGamma(ScrnInfoPtr pScrn, Bool Real8BitDac); +void RamDacRestoreDACValues(ScrnInfoPtr pScrn); +Bool RamDacHandleColormaps(ScreenPtr pScreen, int maxColors, int sigRGBbits, + unsigned int flags); +void RamDacFreeRec(ScrnInfoPtr pScrn); +int RamDacGetHWIndex(void); + +#endif /* _XF86RAMDAC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDacPriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDacPriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86RamDacPriv.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/xf86RamDacPriv.h,v 1.3 1998/12/06 06:08:37 dawes Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#include "xf86RamDac.h" +#include "xf86cmap.h" + +void RamDacGetRecPrivate(void); +Bool RamDacGetRec(ScrnInfoPtr pScrn); +int RamDacGetScreenIndex(void); +void RamDacLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, + LOCO *colors, VisualPtr pVisual); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Resources.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Resources.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Resources.h (revision 51223) @@ -0,0 +1,140 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Resources.h,v 1.15 2003/08/24 17:36:55 dawes Exp $ */ + +/* + * Copyright (c) 1999-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86_RESOURCES_H + +#define _XF86_RESOURCES_H + +#include "xf86str.h" + +#define _END {ResEnd,0,0} + +#define _VGA_EXCLUSIVE \ + {ResExcMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResExcIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +#define _VGA_SHARED \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +#define _VGA_SHARED_MEM \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF} + +#define _VGA_SHARED_IO \ + {ResShrIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Exclusive unused VGA: resources unneeded but cannot be disabled. + * Like old Millennium. + */ +#define _VGA_EXCLUSIVE_UNUSED \ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcUusdMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcUusdIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResExcUusdIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Shared unused VGA: resources unneeded but cannot be disabled + * independently. This is used to determine if a device needs RAC. + */ +#define _VGA_SHARED_UNUSED \ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrUusdMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrUusdIoBlock | ResBios | ResBus, 0x03B0, 0x03BB},\ + {ResShrUusdIoBlock | ResBios | ResBus, 0x03C0, 0x03DF} + +/* + * Sparse versions of the above for those adapters that respond to all ISA + * aliases of VGA ports. + */ +#define _VGA_EXCLUSIVE_SPARSE \ + {ResExcMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResExcMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResExcIoSparse | ResBios | ResBus, 0x03B0, 0x03F8},\ + {ResExcIoSparse | ResBios | ResBus, 0x03B8, 0x03FC},\ + {ResExcIoSparse | ResBios | ResBus, 0x03C0, 0x03E0} + +#define _VGA_SHARED_SPARSE \ + {ResShrMemBlock | ResBios | ResBus, 0x000A0000, 0x000AFFFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B0000, 0x000B7FFF},\ + {ResShrMemBlock | ResBios | ResBus, 0x000B8000, 0x000BFFFF},\ + {ResShrIoSparse | ResBios | ResBus, 0x03B0, 0x03F8},\ + {ResShrIoSparse | ResBios | ResBus, 0x03B8, 0x03FC},\ + {ResShrIoSparse | ResBios | ResBus, 0x03C0, 0x03E0} + +#define _8514_EXCLUSIVE \ + {ResExcIoSparse | ResBios | ResBus, 0x02E8, 0x03F8} + +#define _8514_SHARED \ + {ResShrIoSparse | ResBios | ResBus, 0x02E8, 0x03F8} + +/* Predefined resources */ +extern resRange resVgaExclusive[]; +extern resRange resVgaShared[]; +extern resRange resVgaIoShared[]; +extern resRange resVgaMemShared[]; +extern resRange resVgaUnusedExclusive[]; +extern resRange resVgaUnusedShared[]; +extern resRange resVgaSparseExclusive[]; +extern resRange resVgaSparseShared[]; +extern resRange res8514Exclusive[]; +extern resRange res8514Shared[]; + +/* Less misleading aliases for xf86SetOperatingState() */ +#define resVgaMem resVgaMemShared +#define resVgaIo resVgaIoShared +#define resVga resVgaShared + +/* Old style names */ +#define RES_EXCLUSIVE_VGA resVgaExclusive +#define RES_SHARED_VGA resVgaShared +#define RES_EXCLUSIVE_8514 res8514Exclusive +#define RES_SHARED_8514 res8514Shared + +#define _PCI_AVOID_PC_STYLE \ + {ResExcIoSparse | ResBus, 0x0100, 0x0300},\ + {ResExcIoSparse | ResBus, 0x0200, 0x0200},\ + {ResExcMemBlock | ResBus, 0xA0000,0xFFFFF} + +extern resRange PciAvoid[]; + +#define RES_UNDEFINED NULL +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Sbus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Sbus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Sbus.h (revision 51223) @@ -0,0 +1,70 @@ +/* + * Platform specific SBUS and OpenPROM access declarations. + * + * Copyright (C) 2000 Jakub Jelinek (jakub@redhat.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Sbus.h,v 1.3 2001/04/20 17:02:43 tsi Exp $ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_SBUS_H +#define _XF86_SBUS_H + +#if defined(linux) +#include +#include +#include +#include +#elif defined(SVR4) +#include +#include +#elif defined(__OpenBSD__) && defined(__sparc64__) +/* XXX */ +#elif defined(CSRG_BASED) +#if defined(__FreeBSD__) +#include +#include +#include +#else +#include +#endif +#else +#include +#endif + +#ifndef FBTYPE_SUNGP3 +#define FBTYPE_SUNGP3 -1 +#endif +#ifndef FBTYPE_MDICOLOR +#define FBTYPE_MDICOLOR -1 +#endif +#ifndef FBTYPE_SUNLEO +#define FBTYPE_SUNLEO -1 +#endif +#ifndef FBTYPE_TCXCOLOR +#define FBTYPE_TCXCOLOR -1 +#endif +#ifndef FBTYPE_CREATOR +#define FBTYPE_CREATOR -1 +#endif + +#endif /* _XF86_SBUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86ScanPci.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86ScanPci.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86ScanPci.h (revision 51223) @@ -0,0 +1,49 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/xf86ScanPci.h,v 1.3 2003/08/24 17:37:10 dawes Exp $ */ +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef SCANPCI_H_ +#define SCANPCI_H_ + +#include "xf86PciData.h" + +typedef void (*ScanPciDisplayCardInfoProcPtr)(int verbosity); + +/* + * Whoever loads this module needs to define these and initialise them + * after loading. + */ + +extern ScanPciDisplayCardInfoProcPtr xf86DisplayPCICardInfo; + +void ScanPciDisplayPCICardInfo(int verbosity); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Version.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Version.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Version.h (revision 51223) @@ -0,0 +1,62 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/common/xf86Version.h,v 1.5 2005/08/24 11:18:35 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.566 2003/12/19 04:52:11 dawes Exp $ */ + +/* + * Copyright (c) 1994-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef XF86_VERSION_CURRENT + +#define XF86_VERSION_MAJOR 4 +#define XF86_VERSION_MINOR 3 +#define XF86_VERSION_PATCH 99 +#define XF86_VERSION_SNAP 902 + +/* This has five arguments for compatibilty reasons */ +#define XF86_VERSION_NUMERIC(major,minor,patch,snap,dummy) \ + (((major) * 10000000) + ((minor) * 100000) + ((patch) * 1000) + snap) + +#define XF86_GET_MAJOR_VERSION(vers) ((vers) / 10000000) +#define XF86_GET_MINOR_VERSION(vers) (((vers) % 10000000) / 100000) +#define XF86_GET_PATCH_VERSION(vers) (((vers) % 100000) / 1000) +#define XF86_GET_SNAP_VERSION(vers) ((vers) % 1000) + +/* Define these for compatibility. They'll be removed at some point. */ +#define XF86_VERSION_SUBMINOR XF86_VERSION_PATCH +#define XF86_VERSION_BETA 0 +#define XF86_VERSION_ALPHA XF86_VERSION_SNAP + +#define XF86_VERSION_CURRENT \ + XF86_VERSION_NUMERIC(XF86_VERSION_MAJOR, \ + XF86_VERSION_MINOR, \ + XF86_VERSION_PATCH, \ + XF86_VERSION_SNAP, \ + 0) + +#endif + +/* $XConsortium: xf86Version.h /main/78 1996/10/28 05:42:10 kaleb $ */ +/* $XdotOrg: xserver/xorg/hw/xfree86/common/xf86Version.h,v 1.5 2005/08/24 11:18:35 daniels Exp $ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Xinput.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Xinput.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86Xinput.h (revision 51223) @@ -0,0 +1,221 @@ +/* $XConsortium: xf86Xinput.h /main/11 1996/10/27 11:05:29 kaleb $ */ +/* + * Copyright 1995-1999 by Frederic Lepied, France. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Frederic Lepied not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Frederic Lepied makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * FREDERIC LEPIED DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL FREDERIC LEPIED BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * Copyright (c) 2000-2002 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Xinput.h,v 3.36 2003/08/24 17:36:55 dawes Exp $ */ + +#ifndef _xf86Xinput_h +#define _xf86Xinput_h + +#ifndef NEED_EVENTS +#define NEED_EVENTS +#endif +#include "xf86str.h" +#include "inputstr.h" +#ifdef XINPUT +#include +#include +#include "XIstubs.h" +#endif + +/* Input device flags */ +#define XI86_OPEN_ON_INIT 0x01 /* open the device at startup time */ +#define XI86_CONFIGURED 0x02 /* the device has been configured */ +#define XI86_ALWAYS_CORE 0x04 /* device always controls the pointer */ +/* the device sends Xinput and core pointer events */ +#define XI86_SEND_CORE_EVENTS XI86_ALWAYS_CORE +/* if the device is the core pointer or is sending core events, and + * SEND_DRAG_EVENTS is false, and a buttons is done, then no motion events + * (mouse drag action) are sent. This is mainly to allow a touch screen to be + * used with netscape and other browsers which do strange things if the mouse + * moves between button down and button up. With a touch screen, this motion + * is common due to the user's finger moving slightly. + */ +#define XI86_SEND_DRAG_EVENTS 0x08 +#define XI86_CORE_POINTER 0x10 /* device is the core pointer */ +#define XI86_CORE_KEYBOARD 0x20 /* device is the core keyboard */ +#define XI86_POINTER_CAPABLE 0x40 /* capable of being a core pointer */ +#define XI86_KEYBOARD_CAPABLE 0x80 /* capable of being a core keyboard */ + +#define XI_PRIVATE(dev) \ + (((LocalDevicePtr)((dev)->public.devicePrivate))->private) + +#ifdef DBG +#undef DBG +#endif +#define DBG(lvl, f) {if ((lvl) <= xf86GetVerbosity()) f;} + +#ifdef HAS_MOTION_HISTORY +#undef HAS_MOTION_HISTORY +#endif +#define HAS_MOTION_HISTORY(local) ((local)->dev->valuator && (local)->dev->valuator->numMotionEvents) + +#ifdef XINPUT +/* This holds the input driver entry and module information. */ +typedef struct _InputDriverRec { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + struct _LocalDeviceRec *(*PreInit)(struct _InputDriverRec *drv, + IDevPtr dev, int flags); + void (*UnInit)(struct _InputDriverRec *drv, + struct _LocalDeviceRec *pInfo, + int flags); + pointer module; + int refCount; +} InputDriverRec, *InputDriverPtr; +#endif + +/* This is to input devices what the ScrnInfoRec is to screens. */ + +typedef struct _LocalDeviceRec { + struct _LocalDeviceRec *next; + char * name; + int flags; + + Bool (*device_control)(DeviceIntPtr device, int what); + void (*read_input)(struct _LocalDeviceRec *local); + int (*control_proc)(struct _LocalDeviceRec *local, + xDeviceCtl *control); + void (*close_proc)(struct _LocalDeviceRec *local); + int (*switch_mode)(ClientPtr client, DeviceIntPtr dev, + int mode); + Bool (*conversion_proc)(struct _LocalDeviceRec *local, + int first, int num, int v0, + int v1, int v2, int v3, int v4, + int v5, int *x, int *y); + Bool (*reverse_conversion_proc)( + struct _LocalDeviceRec *local, + int x, int y, int *valuators); + + int fd; + Atom atom; + DeviceIntPtr dev; + pointer private; + int private_flags; + pointer motion_history; + ValuatorMotionProcPtr motion_history_proc; + unsigned int history_size; /* only for configuration purpose */ + unsigned int first; + unsigned int last; + int old_x; + int old_y; + float dxremaind; + float dyremaind; + char * type_name; + IntegerFeedbackPtr always_core_feedback; + IDevPtr conf_idev; + InputDriverPtr drv; + pointer module; + pointer options; +} LocalDeviceRec, *LocalDevicePtr, InputInfoRec, *InputInfoPtr; + +typedef struct _DeviceAssocRec +{ + char * config_section_name; + LocalDevicePtr (*device_allocate)(void); +} DeviceAssocRec, *DeviceAssocPtr; + +/* xf86Globals.c */ +extern InputInfoPtr xf86InputDevs; + +/* xf86Xinput.c */ +int xf86IsCorePointer(DeviceIntPtr dev); +int xf86IsCoreKeyboard(DeviceIntPtr dev); +void xf86XInputSetSendCoreEvents(LocalDevicePtr local, Bool always); +#define xf86AlwaysCore(a,b) xf86XInputSetSendCoreEvents(a,b) + +void InitExtInput(void); +Bool xf86eqInit(DevicePtr pKbd, DevicePtr pPtr); +void xf86eqEnqueue(struct _xEvent *event); +void xf86eqProcessInputEvents (void); +void xf86eqSwitchScreen(ScreenPtr pScreen, Bool fromDIX); +void xf86PostMotionEvent(DeviceIntPtr device, int is_absolute, + int first_valuator, int num_valuators, ...); +void xf86PostProximityEvent(DeviceIntPtr device, int is_in, + int first_valuator, int num_valuators, ...); +void xf86PostButtonEvent(DeviceIntPtr device, int is_absolute, int button, + int is_down, int first_valuator, int num_valuators, + ...); +void xf86PostKeyEvent(DeviceIntPtr device, unsigned int key_code, int is_down, + int is_absolute, int first_valuator, int num_valuators, + ...); +void xf86PostKeyboardEvent(DeviceIntPtr device, unsigned int key_code, + int is_down); +void xf86MotionHistoryAllocate(LocalDevicePtr local); +int xf86GetMotionEvents(DeviceIntPtr dev, xTimecoord *buff, + unsigned long start, unsigned long stop, + ScreenPtr pScreen); +void xf86XinputFinalizeInit(DeviceIntPtr dev); +void xf86ActivateDevice(LocalDevicePtr local); +Bool xf86CheckButton(int button, int down); +void xf86SwitchCoreDevice(LocalDevicePtr device, DeviceIntPtr core); +LocalDevicePtr xf86FirstLocalDevice(void); +int xf86ScaleAxis(int Cx, int Sxhigh, int Sxlow, int Rxhigh, int Rxlow); +void xf86XInputSetScreen(LocalDevicePtr local, int screen_number, int x, int y); +void xf86ProcessCommonOptions(InputInfoPtr pInfo, pointer options); +void xf86InitValuatorAxisStruct(DeviceIntPtr dev, int axnum, int minval, + int maxval, int resolution, int min_res, + int max_res); +void xf86InitValuatorDefaults(DeviceIntPtr dev, int axnum); +void xf86AddEnabledDevice(InputInfoPtr pInfo); +void xf86RemoveEnabledDevice(InputInfoPtr pInfo); + +/* xf86Helper.c */ +void xf86AddInputDriver(InputDriverPtr driver, pointer module, int flags); +void xf86DeleteInputDriver(int drvIndex); +InputInfoPtr xf86AllocateInput(InputDriverPtr drv, int flags); +void xf86DeleteInput(InputInfoPtr pInp, int flags); + +/* xf86Option.c */ +void xf86CollectInputOptions(InputInfoPtr pInfo, const char **defaultOpts, + pointer extraOpts); + +#endif /* _xf86Xinput_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSlib.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSlib.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSlib.h (revision 51223) @@ -0,0 +1,753 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSlib.h,v 3.94 2003/11/03 05:11:51 tsi Exp $ */ +/* + * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany + * Copyright 1992 by David Dawes + * Copyright 1992 by Jim Tsillas + * Copyright 1992 by Rich Murphey + * Copyright 1992 by Robert Baron + * Copyright 1992 by Orest Zborowski + * Copyright 1993 by Vrije Universiteit, The Netherlands + * Copyright 1993 by David Wexelblat + * Copyright 1994, 1996 by Holger Veit + * Copyright 1997 by Takis Psarogiannakopoulos + * Copyright 1994-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * The ARM32 code here carries the following copyright: + * + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the + * source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" + * name nor any trademark or logo of Digital Equipment Corporation may be + * used to endorse or promote products derived from this software without + * the prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. + * In no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for lost profits, loss + * of revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even + * if advised of the possibility of such damage. + * + */ + +/* $XConsortium: xf86_OSlib.h /main/22 1996/10/27 11:06:31 kaleb $ */ +/* $XdotOrg: xserver/xorg/hw/xfree86/os-support/xf86_OSlib.h,v 1.15 2006/02/03 02:37:52 reed Exp $ */ + +/* + * This is private, and should not be included by any drivers. Drivers + * may include xf86_OSproc.h to get prototypes for public interfaces. + */ + +#ifndef _XF86_OSLIB_H +#define _XF86_OSLIB_H + +#include +#include + +/* + * Define some things from the "ANSI" C wrappers that are needed in the + * the core server. + */ +#ifndef HAVE_WRAPPER_DECLS +#define HAVE_WRAPPER_DECLS +#undef usleep +#define usleep(a) xf86usleep(a) +extern void xf86usleep(unsigned long); +extern int xf86getpagesize(void); +extern int xf86GetErrno(void); +typedef unsigned long xf86size_t; +typedef signed long xf86ssize_t; +#endif + +#include +#include +#include + +/**************************************************************************/ +/* SYSV386 (SVR3, SVR4), including Solaris */ +/**************************************************************************/ +#if (defined(SYSV) || defined(SVR4)) && \ + !defined(DGUX) && !defined(sgi) && \ + (defined(sun) || defined(i386)) +# ifdef SCO325 +# ifndef _SVID3 +# define _SVID3 +# endif +# ifndef _NO_STATIC +# define _NO_STATIC +# endif +# endif +# include +# include +# include +# include +# include +# if defined(__SCO__) || defined(ISC) +# include +# endif + +# ifdef ISC +# define TIOCMSET (TIOC|26) /* set all modem bits */ +# define TIOCMBIS (TIOC|27) /* bis modem bits */ +# define TIOCMBIC (TIOC|28) /* bic modem bits */ +# define TIOCMGET (TIOC|29) /* get all modem bits */ +# endif + +# include + +# if defined(_NEED_SYSI86) +# include +# if !(defined (sun) && defined (SVR4)) +# include +# endif +# include +# include +# include +# if defined(SVR4) && !defined(sun) +# include +# endif /* SVR4 && !sun */ +/* V86SC_IOPL was moved to on Solaris 7 and later */ +# if defined(sun) && defined (SVR4) /* Solaris? */ +# if defined(i386) || defined(__x86) /* on x86 or x64? */ +# if !defined(V86SC_IOPL) /* Solaris 7 or later? */ +# include /* Nope */ +# endif +# endif /* V86SC_IOPL */ +# else +# include /* Not solaris */ +# endif /* sun && i386 && SVR4 */ +# if defined(sun) && (defined (i386) || defined(__x86)) && defined (SVR4) +# include +# endif +# endif /* _NEED_SYSI86 */ + +# if defined(HAS_SVR3_MMAPDRV) +# include +# if !defined(_NEED_SYSI86) +# include +# include +# endif +# include /* MMAP driver header */ +# endif + +# if !defined(sun) || (!defined(sparc) && !defined(__SOL8__)) +# define HAS_USL_VTS +# endif +# if !defined(sun) +# include +# endif +# if defined(SCO325) +# include +# include +# include +# include +# define LED_CAP CLKED +# define LED_NUM NLKED +# define LED_SCR SLKED +# elif defined(HAS_USL_VTS) +# include +# include +# include +# elif defined(sun) +# include +# include +# include + +/* undefine symbols from we don't need that conflict with enum + definitions in parser/xf86tokens.h */ +# undef STRING +# undef LEFTALT +# undef RIGHTALT + +# define LED_CAP LED_CAPS_LOCK +# define LED_NUM LED_NUM_LOCK +# define LED_SCR LED_SCROLL_LOCK +# define LED_COMP LED_COMPOSE +# endif /* sun */ + +# if !defined(VT_ACKACQ) +# define VT_ACKACQ 2 +# endif /* !VT_ACKACQ */ + +# if defined(__SCO__) +# include +# define POSIX_TTY +# endif /* __SCO__ */ + +# if defined(SVR4) || defined(SCO325) +# include +# if !(defined(sun) && defined (SVR4)) +# define DEV_MEM "/dev/pmem" +# endif +# ifdef SCO325 +# undef DEV_MEM +# define DEV_MEM "/dev/mem" +# endif +# define CLEARDTR_SUPPORT +# define POSIX_TTY +# endif /* SVR4 */ + +# ifdef ISC +# include +# define POSIX_TTY +# endif + +# if defined(sun) && defined (i386) && defined (SVR4) && !defined(__SOL8__) +# define USE_VT_SYSREQ +# define VT_SYSREQ_DEFAULT TRUE +# endif + +# if defined(ATT) && !defined(i386) +# define i386 /* not defined in ANSI C mode */ +# endif /* ATT && !i386 */ + +# if (defined(ATT) || defined(SVR4)) && !defined(sun) +# ifndef __UNIXWARE__ +# ifndef XQUEUE +# define XQUEUE +# endif +# endif +# include +# endif /* ATT || SVR4 */ + +# ifdef SYSV +# if !defined(ISC) || defined(ISC202) || defined(ISC22) +# define NEED_STRERROR +# endif +# endif + +#endif /* (SYSV || SVR4) && !DGUX */ + + + +/**************************************************************************/ +/* DG/ux R4.20MU03 Intel AViion Machines */ +/**************************************************************************/ +#if defined(DGUX) && defined(SVR4) +#include +#include +#include +#include /* Use termios for BSD Flavor ttys */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* Memory handling */ +#include /* definitios for KDENABIO KDDISABIO needed for IOPL s */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#define POSIX_TTY + +#undef HAS_USL_VTS +#undef USE_VT_SYSREQ +#undef VT_ACKACQ + +#define LED_CAP KBD_LED_CAPS_LOCK +#define LED_NUM KBD_LED_NUM_LOCK +#define LED_SCR KBD_LED_SCROLL_LOCK + +#define KDGKBTYPE KBD_GET_LANGUAGE + + +/* General keyboard types */ +# define KB_84 2 +# define KB_101 1 /* Because ioctl(dgkeybdFd,KBD_GET_LANGUAGE,&type) gives 1=US keyboard */ +# define KB_OTHER 3 + +#define KDSETLED KBD_SET_LED +#define KDGETLED KBD_GET_STATE +#undef KDMKTONE +#define KDMKTONE KBD_TONE_HIGH + + +#undef DEV_MEM +#define DEV_MEM "/dev/mem" +#define CLEARDTR_SUPPORT + +#undef VT_SYSREQ_DEFAULT +#define VT_SYSREQ_DEFAULT FALSE /* Make sure that we dont define any VTs since DG/ux has none */ + +#endif /* DGUX && SVR4 */ + +/**************************************************************************/ +/* Linux or Glibc-based system */ +/**************************************************************************/ +#if defined(__linux__) || defined(__GLIBC__) +# include +# include +# include +# include +# include + +#ifdef __GNU__ /* GNU/Hurd */ +# define USE_OSMOUSE +#endif + +# ifdef __linux__ +# include +# else /* __GLIBC__ */ +# include +# endif +# ifdef __sparc__ +# include +# endif + +# include + +# include + +# include +# ifdef __linux__ +# define HAS_USL_VTS +# include +# include +# define LDGMAP GIO_SCRNMAP +# define LDSMAP PIO_SCRNMAP +# define LDNMAP LDSMAP +# define CLEARDTR_SUPPORT +# define USE_VT_SYSREQ +# endif + +# define POSIX_TTY + +#endif /* __linux__ || __GLIBC__ */ + +/**************************************************************************/ +/* LynxOS AT */ +/**************************************************************************/ +#if defined(Lynx) + +# include +# include +# include +# include +# include +# include +# include + +# include +extern int errno; + +/* smem_create et.al. to access physical memory */ +# include + +/* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + +/* atc drivers ignores argument to VT_RELDISP ioctl */ +# define VT_ACKACQ 2 + +# include +# define POSIX_TTY +# define CLEARDTR_SUPPORT + +/* LynxOS 2.5.1 has these */ +# ifdef LED_NUMLOCK +# define LED_CAP LED_CAPSLOCK +# define LED_NUM LED_NUMLOCK +# define LED_SCR LED_SCROLLOCK +# endif + +#endif /* Lynx */ + +/**************************************************************************/ +/* 386BSD and derivatives, BSD/386 */ +/**************************************************************************/ + +#if defined(__386BSD__) && (defined(__FreeBSD__) || defined(__NetBSD__)) +# undef __386BSD__ +#endif + +#ifdef CSRG_BASED +# include +# include + +# include +# define termio termios +# define POSIX_TTY + +# include + +# include +# include +# include + +# if defined(__bsdi__) +# include +# if (_BSDI_VERSION < 199510) +# include +# endif +# endif /* __bsdi__ */ + +#endif /* CSRG_BASED */ + +/**************************************************************************/ +/* Kernel of *BSD */ +/**************************************************************************/ +#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || \ + defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__) || defined(__DragonFly__) + +# include +# if defined(__FreeBSD_version) && !defined(__FreeBSD_kernel_version) +# define __FreeBSD_kernel_version __FreeBSD_version +# endif + +# if !defined(LINKKIT) + /* Don't need this stuff for the Link Kit */ +# if defined(__bsdi__) +# include +# define CONSOLE_X_MODE_ON PCCONIOCRAW +# define CONSOLE_X_MODE_OFF PCCONIOCCOOK +# define CONSOLE_X_BELL PCCONIOCBEEP +# else /* __bsdi__ */ +# if defined(__OpenBSD__) +# ifdef PCCONS_SUPPORT +# include +# undef CONSOLE_X_MODE_ON +# undef CONSOLE_X_MODE_OFF +# undef CONSOLE_X_BELL +# endif +# endif +# ifdef SYSCONS_SUPPORT +# define COMPAT_SYSCONS +# if defined(__NetBSD__) || defined(__OpenBSD__) +# include +# else +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +# if defined(__DragonFly__) || (__FreeBSD_kernel_version >= 410000) +# include +# include +# else +# include +# endif /* FreeBSD 4.1 RELEASE or lator */ +# else +# include +# endif +# endif +# endif /* SYSCONS_SUPPORT */ +# if defined(PCVT_SUPPORT) +# if !defined(SYSCONS_SUPPORT) + /* no syscons, so include pcvt specific header file */ +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +# include +# else +# if defined(__NetBSD__) || defined(__OpenBSD__) +# if !defined(WSCONS_SUPPORT) +# include +# endif /* WSCONS_SUPPORT */ +# else +# include +# endif /* __NetBSD__ */ +# endif /* __FreeBSD_kernel__ || __OpenBSD__ */ +# else /* pcvt and syscons: hard-code the ID magic */ +# define VGAPCVTID _IOWR('V',113, struct pcvtid) + struct pcvtid { + char name[16]; + int rmajor, rminor; + }; +# endif /* PCVT_SUPPORT && SYSCONS_SUPPORT */ +# endif /* PCVT_SUPPORT */ +# ifdef WSCONS_SUPPORT +# include +# include +# endif /* WSCONS_SUPPORT */ +# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +# if defined(__FreeBSD_kernel_version) && (__FreeBSD_kernel_version >= 500013) +# include +# else +# undef MOUSE_GETINFO +# include +# endif +# endif + /* Include these definitions in case ioctl_pc.h didn't get included */ +# ifndef CONSOLE_X_MODE_ON +# define CONSOLE_X_MODE_ON _IO('t',121) +# endif +# ifndef CONSOLE_X_MODE_OFF +# define CONSOLE_X_MODE_OFF _IO('t',122) +# endif +# ifndef CONSOLE_X_BELL +# define CONSOLE_X_BELL _IOW('t',123,int[2]) +# endif +# ifndef CONSOLE_X_TV_ON +# define CONSOLE_X_TV_ON _IOW('t',155,int) +# define XMODE_RGB 0 +# define XMODE_NTSC 1 +# define XMODE_PAL 2 +# define XMODE_SECAM 3 +# endif +# ifndef CONSOLE_X_TV_OFF +# define CONSOLE_X_TV_OFF _IO('t',156) +# endif +#ifndef CONSOLE_GET_LINEAR_INFO +# define CONSOLE_GET_LINEAR_INFO _IOR('t',157,struct map_info) +#endif +#ifndef CONSOLE_GET_IO_INFO +# define CONSOLE_GET_IO_INFO _IOR('t',158,struct map_info) +#endif +#ifndef CONSOLE_GET_MEM_INFO +# define CONSOLE_GET_MEM_INFO _IOR('t',159,struct map_info) +#endif +# endif /* __bsdi__ */ +# endif /* !LINKKIT */ + +#if defined(USE_I386_IOPL) || defined(USE_AMD64_IOPL) +#include +#endif + +# define CLEARDTR_SUPPORT + +# if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT) || defined(WSCONS_SUPPORT) +# define USE_VT_SYSREQ +# endif + +#endif +/* __FreeBSD_kernel__ || __NetBSD__ || __OpenBSD__ || __bsdi__ */ + +/**************************************************************************/ +/* OS/2 */ +/**************************************************************************/ +/* currently OS/2 with a modified EMX/GCC compiler only */ +#if defined(__UNIXOS2__) +# include +# include +# include + +/* I would have liked to have this included here always, but + * it causes clashes for BYTE and BOOL with Xmd.h, which is too dangerous. + * So I'll include it in place where I know it does no harm. + */ +#if defined(I_NEED_OS2_H) +# undef BOOL +# undef BYTE +# include +#endif + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +/* could detect more keyboards */ +# define KB_OTHER 3 + + /* LEDs */ +# define LED_CAP 0x40 +# define LED_NUM 0x20 +# define LED_SCR 0x10 + + /* mouse driver */ +# define OSMOUSE_ONLY +# define MOUSE_PROTOCOL_IN_KERNEL + +extern char* __XOS2RedirRoot(char*); + +#endif + +/**************************************************************************/ +/* QNX4 */ +/**************************************************************************/ +/* This is the QNX code for Watcom 10.6 and QNX 4.x */ +#if defined(QNX4) +#include +#include +#include +#include +#include +#include + +/* Warning: by default, the fd_set size is 32 in QNX! */ +#define FD_SETSIZE 256 +#include + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + + /* LEDs */ +# define LED_CAP 0x04 +# define LED_NUM 0x02 +# define LED_SCR 0x01 + +# define POSIX_TTY +# define OSMOUSE_ONLY +# define MOUSE_PROTOCOL_IN_KERNEL + +#define TIOCM_DTR 0x0001 /* data terminal ready */ +#define TIOCM_RTS 0x0002 /* request to send */ +#define TIOCM_CTS 0x1000 /* clear to send */ +#define TIOCM_DSR 0x2000 /* data set ready */ +#define TIOCM_RI 0x4000 /* ring */ +#define TIOCM_RNG TIOCM_RI +#define TIOCM_CD 0x8000 /* carrier detect */ +#define TIOCM_CAR TIOCM_CD +#define TIOCM_LE 0x0100 /* line enable */ +#define TIOCM_ST 0x0200 /* secondary transmit */ +#define TIOCM_SR 0x0400 /* secondary receive */ + +#endif + +/**************************************************************************/ +/* QNX/Neutrino */ +/**************************************************************************/ +/* This is the Neutrino code for for NTO2.0 and GCC */ +#if defined(__QNXNTO__) +#include +#include +#include +#include +#include +#include + +/* Warning: by default, the fd_set size is 32 in NTO! */ +#define FD_SETSIZE 256 +#include + + /* keyboard types */ +# define KB_84 1 +# define KB_101 2 +# define KB_OTHER 3 + +# define POSIX_TTY + +#endif + +/**************************************************************************/ +/* IRIX */ +/**************************************************************************/ +#if defined(sgi) + +#include +#include +#include + +#endif + +/**************************************************************************/ +/* Generic */ +/**************************************************************************/ + +#include /* May need to adjust this for other OSs */ + +/* + * Hack originally for ISC 2.2 POSIX headers, but may apply elsewhere, + * and it's safe, so just do it. + */ +#if !defined(O_NDELAY) && defined(O_NONBLOCK) +# define O_NDELAY O_NONBLOCK +#endif /* !O_NDELAY && O_NONBLOCK */ + +#if !defined(MAXHOSTNAMELEN) +# define MAXHOSTNAMELEN 32 +#endif /* !MAXHOSTNAMELEN */ + +#if !defined(X_NOT_POSIX) +# if defined(_POSIX_SOURCE) +# include +# else +# define _POSIX_SOURCE +# include +# undef _POSIX_SOURCE +# endif /* _POSIX_SOURCE */ +#endif /* !X_NOT_POSIX */ +#if !defined(PATH_MAX) +# if defined(MAXPATHLEN) +# define PATH_MAX MAXPATHLEN +# else +# define PATH_MAX 1024 +# endif /* MAXPATHLEN */ +#endif /* !PATH_MAX */ + +#ifdef NEED_STRERROR +# ifndef strerror +extern char *sys_errlist[]; +extern int sys_nerr; +# define strerror(n) \ + ((n) >= 0 && (n) < sys_nerr) ? sys_errlist[n] : "unknown error" +# endif /* !strerror */ +#endif /* NEED_STRERROR */ + +#if defined(ISC) || defined(Lynx) +#define rint(x) RInt(x) +double RInt( + double x +); +#endif + +#ifndef DEV_MEM +#define DEV_MEM "/dev/mem" +#endif + +#ifndef VT_SYSREQ_DEFAULT +#define VT_SYSREQ_DEFAULT FALSE +#endif + +#ifdef OSMOUSE_ONLY +# ifndef MOUSE_PROTOCOL_IN_KERNEL +# define MOUSE_PROTOCOL_IN_KERNEL +# endif +#endif + +#define SYSCALL(call) while(((call) == -1) && (errno == EINTR)) + +#define XF86_OS_PRIVS +#include "xf86_OSproc.h" + +#ifndef NO_COMPILER_H +#include "compiler.h" +#endif + +#endif /* _XF86_OSLIB_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_OSproc.h (revision 51223) @@ -0,0 +1,277 @@ +/* + * Copyright 1990, 1991 by Thomas Roell, Dinkelscherben, Germany + * Copyright 1992 by David Dawes + * Copyright 1992 by Jim Tsillas + * Copyright 1992 by Rich Murphey + * Copyright 1992 by Robert Baron + * Copyright 1992 by Orest Zborowski + * Copyright 1993 by Vrije Universiteit, The Netherlands + * Copyright 1993 by David Wexelblat + * Copyright 1994, 1996 by Holger Veit + * Copyright 1994-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + * The ARM32 code here carries the following copyright: + * + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the + * source file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" + * name nor any trademark or logo of Digital Equipment Corporation may be + * used to endorse or promote products derived from this software without + * the prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. + * In no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for lost profits, loss + * of revenue or loss of use, whether such damages arise in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even + * if advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_OSproc.h,v 3.56 2003/08/24 17:37:03 dawes Exp $ */ + +#ifndef _XF86_OSPROC_H +#define _XF86_OSPROC_H + +#ifdef XF86_OS_PRIVS +#include "xf86Pci.h" +#endif + +/* + * The actual prototypes have been pulled into this seperate file so + * that they can can be used without pulling in all of the OS specific + * stuff like sys/stat.h, etc. This casues problem for loadable modules. + */ + +/* + * Flags for xf86MapVidMem(). Multiple flags can be or'd together. The + * flags may be used as hints. For example it would be permissible to + * enable write combining for memory marked only for framebuffer use. + */ + +#define VIDMEM_FRAMEBUFFER 0x01 /* memory for framebuffer use */ +#define VIDMEM_MMIO 0x02 /* memory for I/O use */ +#define VIDMEM_MMIO_32BIT 0x04 /* memory accesses >= 32bit */ +#define VIDMEM_READSIDEEFFECT 0x08 /* reads can have side-effects */ +#define VIDMEM_SPARSE 0x10 /* sparse mapping required + * assumed when VIDMEM_MMIO is + * set. May be used with + * VIDMEM_FRAMEBUFFER) */ +#define VIDMEM_READONLY 0x20 /* read-only mapping + * used when reading BIOS images + * through xf86MapVidMem() */ + +/* + * OS-independent modem state flags for xf86SetSerialModemState() and + * xf86GetSerialModemState(). + */ +#define XF86_M_LE 0x001 /* line enable */ +#define XF86_M_DTR 0x002 /* data terminal ready */ +#define XF86_M_RTS 0x004 /* request to send */ +#define XF86_M_ST 0x008 /* secondary transmit */ +#define XF86_M_SR 0x010 /* secondary receive */ +#define XF86_M_CTS 0x020 /* clear to send */ +#define XF86_M_CAR 0x040 /* carrier detect */ +#define XF86_M_RNG 0x080 /* ring */ +#define XF86_M_DSR 0x100 /* data set ready */ + +#ifdef XF86_OS_PRIVS +extern void xf86WrapperInit(void); +#endif + +#ifndef NO_OSLIB_PROTOTYPES +/* + * This is to prevent re-entrancy to FatalError() when aborting. + * Anything that can be called as a result of AbortDDX() should use this + * instead of FatalError(). + */ + +#define xf86FatalError(a, b) \ + if (dispatchException & DE_TERMINATE) { \ + ErrorF(a, b); \ + ErrorF("\n"); \ + return; \ + } else FatalError(a, b) + +/***************************************************************************/ +/* Prototypes */ +/***************************************************************************/ + +#include +#include "opaque.h" + +#if defined(XQUEUE) +#include "input.h" /* for DeviceIntPtr */ +#endif + +_XFUNCPROTOBEGIN + +/* public functions */ +extern Bool xf86LinearVidMem(void); +extern Bool xf86CheckMTRR(int); +extern pointer xf86MapVidMem(int, int, unsigned long, unsigned long); +extern void xf86UnMapVidMem(int, pointer, unsigned long); +extern void xf86MapReadSideEffects(int, int, pointer, unsigned long); +extern int xf86ReadBIOS(unsigned long, unsigned long, unsigned char *, int); +extern Bool xf86EnableIO(void); +extern void xf86DisableIO(void); +extern Bool xf86DisableInterrupts(void); +extern void xf86EnableInterrupts(void); +extern void xf86SetTVOut(int); +extern void xf86SetRGBOut(void); +extern void xf86SoundKbdBell(int, int, int); +#if defined(QNX4) +#pragma aux xf86BusToMem modify [eax ebx ecx edx esi edi]; +#pragma aux xf86MemToBus modify [eax ebx ecx edx esi edi]; +#endif +extern void xf86BusToMem(unsigned char *, unsigned char *, int); +extern void xf86MemToBus(unsigned char *, unsigned char *, int); +extern void xf86IODelay(void); +extern void xf86UDelay(long usec); +extern void xf86SlowBcopy(unsigned char *, unsigned char *, int); +extern int xf86OpenSerial(pointer options); +extern int xf86SetSerial(int fd, pointer options); +extern int xf86SetSerialSpeed(int fd, int speed); +extern int xf86ReadSerial(int fd, void *buf, int count); +extern int xf86WriteSerial(int fd, const void *buf, int count); +extern int xf86CloseSerial(int fd); +extern int xf86FlushInput(int fd); +extern int xf86WaitForInput(int fd, int timeout); +extern int xf86SerialSendBreak(int fd, int duration); +extern int xf86SetSerialModemState(int fd, int state); +extern int xf86GetSerialModemState(int fd); +extern int xf86SerialModemSetBits(int fd, int bits); +extern int xf86SerialModemClearBits(int fd, int bits); +extern int xf86LoadKernelModule(const char *pathname); + +/* AGP GART interface */ + +typedef struct _AgpInfo { + CARD32 bridgeId; + CARD32 agpMode; + unsigned long base; + unsigned long size; + unsigned long totalPages; + unsigned long systemPages; + unsigned long usedPages; +} AgpInfo, *AgpInfoPtr; + +extern Bool xf86AgpGARTSupported(void); +extern AgpInfoPtr xf86GetAGPInfo(int screenNum); +extern Bool xf86AcquireGART(int screenNum); +extern Bool xf86ReleaseGART(int screenNum); +extern int xf86AllocateGARTMemory(int screenNum, unsigned long size, int type, + unsigned long *physical); +extern Bool xf86DeallocateGARTMemory(int screenNum, int key); +extern Bool xf86BindGARTMemory(int screenNum, int key, unsigned long offset); +extern Bool xf86UnbindGARTMemory(int screenNum, int key); +extern Bool xf86EnableAGP(int screenNum, CARD32 mode); +extern Bool xf86GARTCloseScreen(int screenNum); + +/* These routines are in shared/sigio.c and are not loaded as part of the + module. These routines are small, and the code if very POSIX-signal (or + OS-signal) specific, so it seemed better to provide more complex + wrappers than to wrap each individual function called. */ +extern int xf86InstallSIGIOHandler(int fd, void (*f)(int, void *), void *); +extern int xf86RemoveSIGIOHandler(int fd); +extern int xf86BlockSIGIO (void); +extern void xf86UnblockSIGIO (int); +#ifdef XFree86Server +extern void xf86AssertBlockedSIGIO (char *); +#endif +extern Bool xf86SIGIOSupported (void); + +#ifdef XF86_OS_PRIVS +typedef void (*PMClose)(void); +extern void xf86OpenConsole(void); +extern void xf86CloseConsole(void); +extern Bool xf86VTSwitchPending(void); +extern Bool xf86VTSwitchAway(void); +extern Bool xf86VTSwitchTo(void); +extern void xf86VTRequest(int sig); +extern int xf86ProcessArgument(int, char **, int); +extern void xf86UseMsg(void); +extern void xf86SetKbdLeds(int); +extern int xf86GetKbdLeds(void); +extern void xf86SetKbdRepeat(char); +extern void xf86KbdInit(void); +extern int xf86KbdOn(void); +extern int xf86KbdOff(void); +extern void xf86KbdEvents(void); +#ifdef XQUEUE +extern int xf86XqueKbdProc(DeviceIntPtr, int); +extern void xf86XqueEvents(void); +#endif +extern void xf86ReloadInputDevs(int sig); +#ifdef WSCONS_SUPPORT +extern void xf86WSKbdEvents(void); +#endif +extern PMClose xf86OSPMOpen(void); + +#ifdef NEED_OS_RAC_PROTOS +/* RAC-related privs */ +/* internal to os-support layer */ +resPtr xf86StdBusAccWindowsFromOS(void); +resPtr xf86StdPciAccWindowsFromOS(void); +resPtr xf86StdIsaAccWindowsFromOS(void); +resPtr xf86StdAccResFromOS(resPtr ret); + +/* available to the common layer */ +resPtr xf86BusAccWindowsFromOS(void); +resPtr xf86PciBusAccWindowsFromOS(void); +#ifdef INCLUDE_UNUSED +resPtr xf86IsaBusAccWindowsFromOS(void); +#endif +resPtr xf86AccResFromOS(resPtr ret); +#endif /* NEED_OS_RAC_PROTOS */ + +extern Bool xf86GetPciSizeFromOS(PCITAG tag, int indx, int* bits); +extern Bool xf86GetPciOffsetFromOS(PCITAG tag, int indx, unsigned long* bases); +extern unsigned long xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base); + +extern void xf86MakeNewMapping(int, int, unsigned long, unsigned long, pointer); +extern void xf86InitVidMem(void); + +#endif /* XF86_OS_PRIVS */ + + +_XFUNCPROTOEND +#endif /* NO_OSLIB_PROTOTYPES */ + +#endif /* _XF86_OSPROC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_ansic.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_ansic.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_ansic.h (revision 51223) @@ -0,0 +1,355 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_ansic.h,v 3.53 2003/10/28 18:36:37 tsi Exp $ */ +/* + * Copyright 1997-2003 by The XFree86 Project, Inc + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holders + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holders make no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDERS BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef _XF86_ANSIC_H +#define _XF86_ANSIC_H + +/* Handle */ + +#ifndef IN_MODULE +# include +#else /* !IN_MODULE */ +# ifndef __OS2ELF__ +# include +# else /* __OS2ELF__ */ + /* EMX/gcc_elf under OS/2 does not have native header files */ +# if !defined (_VA_LIST) +# define _VA_LIST + typedef char *va_list; +# endif +# define _VA_ROUND(t) ((sizeof (t) + 3) & -4) +# if !defined (va_start) +# define va_start(ap,v) ap = (va_list)&v + ((sizeof (v) + 3) & -4) +# define va_end(ap) (ap = 0, (void)0) +# define va_arg(ap,t) (ap += _VA_ROUND (t), *(t *)(ap - _VA_ROUND (t))) +# endif +# endif /* __OS2ELF__ */ +#endif /* IN_MODULE */ + +/* + * The first set of definitions are required both for modules and + * libc_wrapper.c. + */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_TYPES) + +#if !defined(SYSV) && !defined(SVR4) && !defined(Lynx) || \ + defined(__SCO__) || defined(__UNIXWARE__) +#define HAVE_VSSCANF +#define HAVE_VFSCANF +#endif + +#ifndef NULL +#if (defined(SVR4) || defined(SYSV)) && !defined(__GNUC__) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif +#endif +#ifndef EOF +#define EOF (-1) +#endif + +#ifndef PATH_MAX +#define PATH_MAX 1024 +#endif + +/* stuff */ +#define x_BITSPERBYTE 8 +#define x_BITS(type) (x_BITSPERBYTE * (int)sizeof(type)) +#define x_SHORTBITS x_BITS(short) +#define x_INTBITS x_BITS(int) +#define x_LONGBITS x_BITS(long) +#ifndef SHRT_MIN +#define SHRT_MIN ((short)(1 << (x_SHORTBITS - 1))) +#endif + +#ifndef FONTMODULE +#include "misc.h" +#endif +#include "xf86_libc.h" +#ifndef SHRT_MAX +#define SHRT_MAX ((short)~SHRT_MIN) +#endif +#ifndef USHRT_MAX +#define USHRT_MAX ((unsigned short)~0) +#endif +#ifndef MINSHORT +#define MINSHORT SHRT_MIN +#endif +#ifndef MAXSHORT +#define MAXSHORT SHRT_MAX +#endif +#ifndef INT_MIN +#define INT_MIN (1 << (x_INTBITS - 1)) +#endif +#ifndef INT_MAX +#define INT_MAX (~INT_MIN) +#endif +#ifndef UINT_MAX +#define UINT_MAX (~0) +#endif +#ifndef MININT +#define MININT INT_MIN +#endif +#ifndef MAXINT +#define MAXINT INT_MAX +#endif +#ifndef LONG_MIN +#define LONG_MIN ((long)(1 << (x_LONGBITS - 1))) +#endif +#ifndef LONG_MAX +#define LONG_MAX ((long)~LONG_MIN) +#endif +#ifndef ULONG_MAX +#define ULONG_MAX ((unsigned long)~0UL) +#endif +#ifndef MINLONG +#define MINLONG LONG_MIN +#endif +#ifndef MAXLONG +#define MAXLONG LONG_MAX +#endif + +#endif /* XFree86LOADER || NEED_XF86_TYPES */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_PROTOTYPES) +/* + * ANSI C compilers only. + */ + +/* ANSI C emulation library */ + +extern void xf86abort(void); +extern int xf86abs(int); +extern double xf86acos(double); +extern double xf86asin(double); +extern double xf86atan(double); +extern double xf86atan2(double,double); +extern double xf86atof(const char*); +extern int xf86atoi(const char*); +extern long xf86atol(const char*); +extern void *xf86bsearch(const void *, const void *, xf86size_t, xf86size_t, + int (*)(const void *, const void *)); +extern double xf86ceil(double); +extern void* xf86calloc(xf86size_t,xf86size_t); +extern void xf86clearerr(XF86FILE*); +extern double xf86cos(double); +extern void xf86exit(int); +extern double xf86exp(double); +extern double xf86fabs(double); +extern int xf86fclose(XF86FILE*); +extern int xf86feof(XF86FILE*); +extern int xf86ferror(XF86FILE*); +extern int xf86fflush(XF86FILE*); +extern int xf86fgetc(XF86FILE*); +extern int xf86getc(XF86FILE*); +extern int xf86fgetpos(XF86FILE*,XF86fpos_t*); +extern char* xf86fgets(char*,INT32,XF86FILE*); +extern int xf86finite(double); +extern double xf86floor(double); +extern double xf86fmod(double,double); +extern XF86FILE* xf86fopen(const char*,const char*); +extern double xf86frexp(double, int*); +extern int xf86printf(const char*,...); +extern int xf86fprintf(XF86FILE*,const char*,...); +extern int xf86fputc(int,XF86FILE*); +extern int xf86fputs(const char*,XF86FILE*); +extern xf86size_t xf86fread(void*,xf86size_t,xf86size_t,XF86FILE*); +extern void xf86free(void*); +extern XF86FILE* xf86freopen(const char*,const char*,XF86FILE*); +#if defined(HAVE_VFSCANF) || !defined(NEED_XF86_PROTOTYPES) +extern int xf86fscanf(XF86FILE*,const char*,...); +#else +extern int xf86fscanf(/*XF86FILE*,const char*,char *,char *,char *,char *, + char *,char *,char *,char *,char *,char * */); +#endif +extern int xf86fseek(XF86FILE*,long,int); +extern int xf86fsetpos(XF86FILE*,const XF86fpos_t*); +extern long xf86ftell(XF86FILE*); +extern xf86size_t xf86fwrite(const void*,xf86size_t,xf86size_t,XF86FILE*); +extern char* xf86getenv(const char*); +extern int xf86isalnum(int); +extern int xf86isalpha(int); +extern int xf86iscntrl(int); +extern int xf86isdigit(int); +extern int xf86isgraph(int); +extern int xf86islower(int); +extern int xf86isprint(int); +extern int xf86ispunct(int); +extern int xf86isspace(int); +extern int xf86isupper(int); +extern int xf86isxdigit(int); +extern long xf86labs(long); +extern double xf86ldexp(double,int); +extern double xf86log(double); +extern double xf86log10(double); +extern void* xf86malloc(xf86size_t); +extern void* xf86memchr(const void*,int,xf86size_t); +extern int xf86memcmp(const void*,const void*,xf86size_t); +extern void* xf86memcpy(void*,const void*,xf86size_t); +extern void* xf86memmove(void*,const void*,xf86size_t); +extern void* xf86memset(void*,int,xf86size_t); +extern double xf86modf(double,double*); +extern void xf86perror(const char*); +extern double xf86pow(double,double); +extern void xf86qsort(void*, xf86size_t, xf86size_t, + int(*)(const void*, const void*)); +extern void* xf86realloc(void*,xf86size_t); +extern long xf86random(void); +extern int xf86remove(const char*); +extern int xf86rename(const char*,const char*); +extern void xf86rewind(XF86FILE*); +extern int xf86setbuf(XF86FILE*,char*); +extern int xf86setvbuf(XF86FILE*,char*,int,xf86size_t); +extern double xf86sin(double); +extern int xf86sprintf(char*,const char*,...); +extern int xf86snprintf(char*,xf86size_t,const char*,...); +extern double xf86sqrt(double); +#if defined(HAVE_VSSCANF) || !defined(NEED_XF86_PROTOTYPES) +extern int xf86sscanf(char*,const char*,...); +#else +extern int xf86sscanf(/*char*,const char*,char *,char *,char *,char *, + char *,char *,char *,char *,char *,char * */); +#endif +extern char* xf86strcat(char*,const char*); +extern char* xf86strchr(const char*, int c); +extern int xf86strcmp(const char*,const char*); +extern int xf86strcasecmp(const char*,const char*); +extern char* xf86strcpy(char*,const char*); +extern xf86size_t xf86strcspn(const char*,const char*); +extern char* xf86strerror(int); +extern xf86size_t xf86strlcat(char*,const char*,xf86size_t); +extern xf86size_t xf86strlcpy(char*,const char*,xf86size_t); +extern xf86size_t xf86strlen(const char*); +extern char* xf86strncat(char *, const char *, xf86size_t); +extern int xf86strncmp(const char*,const char*,xf86size_t); +extern int xf86strncasecmp(const char*,const char*,xf86size_t); +extern char* xf86strncpy(char*,const char*,xf86size_t); +extern char* xf86strpbrk(const char*,const char*); +extern char* xf86strrchr(const char*,int); +extern xf86size_t xf86strspn(const char*,const char*); +extern char* xf86strstr(const char*,const char*); +extern double xf86strtod(const char*,char**); +extern char* xf86strtok(char*,const char*); +extern long xf86strtol(const char*,char**,int); +extern unsigned long xf86strtoul(const char*,char**,int); +extern double xf86tan(double); +extern XF86FILE* xf86tmpfile(void); +extern char* xf86tmpnam(char*); +extern int xf86tolower(int); +extern int xf86toupper(int); +extern int xf86ungetc(int,XF86FILE*); +extern int xf86vfprintf(XF86FILE*,const char*,va_list); +extern int xf86vsprintf(char*,const char*,va_list); +extern int xf86vsnprintf(char*,xf86size_t,const char*,va_list); + +extern int xf86open(const char*, int,...); +extern int xf86close(int); +extern long xf86lseek(int, long, int); +extern int xf86ioctl(int, unsigned long, pointer); +extern xf86ssize_t xf86read(int, void *, xf86size_t); +extern xf86ssize_t xf86write(int, const void *, xf86size_t); +extern void* xf86mmap(void*, xf86size_t, int, int, int, xf86size_t /* off_t */); +extern int xf86munmap(void*, xf86size_t); +extern int xf86stat(const char *, struct xf86stat *); +extern int xf86fstat(int, struct xf86stat *); +extern int xf86access(const char *, int); +extern int xf86errno; +extern int xf86GetErrno(void); + +extern double xf86HUGE_VAL; + +extern double xf86hypot(double,double); + +/* non-ANSI C functions */ +extern XF86DIR* xf86opendir(const char*); +extern int xf86closedir(XF86DIR*); +extern XF86DIRENT* xf86readdir(XF86DIR*); +extern void xf86rewinddir(XF86DIR*); +extern void xf86bcopy(const void*,void*,xf86size_t); +extern int xf86ffs(int); +extern char* xf86strdup(const char*); +extern void xf86bzero(void*,unsigned int); +extern int xf86execl(const char *, const char *, ...); +extern long xf86fpossize(void); +extern int xf86chmod(const char *, xf86mode_t); +extern int xf86chown(const char *, xf86uid_t, xf86gid_t); +extern xf86uid_t xf86geteuid(void); +extern xf86gid_t xf86getegid(void); +extern int xf86getpid(void); +extern int xf86mknod(const char *, xf86mode_t, xf86dev_t); +extern int xf86mkdir(const char *, xf86mode_t); +unsigned int xf86sleep(unsigned int seconds); +/* sysv IPC */ +extern int xf86shmget(xf86key_t key, int size, int xf86shmflg); +extern char * xf86shmat(int id, char *addr, int xf86shmflg); +extern int xf86shmdt(char *addr); +extern int xf86shmctl(int id, int xf86cmd, pointer buf); + +extern int xf86setjmp(xf86jmp_buf env); +extern int xf86setjmp0(xf86jmp_buf env); +extern int xf86setjmp1(xf86jmp_buf env, int); +extern int xf86setjmp1_arg2(void); +extern int xf86setjmperror(xf86jmp_buf env); +extern int xf86getjmptype(void); +extern void xf86longjmp(xf86jmp_buf env, int val); +#define xf86setjmp_macro(env) \ + (xf86getjmptype() == 0 ? xf86setjmp0((env)) : \ + (xf86getjmptype() == 1 ? xf86setjmp1((env), xf86setjmp1_arg2()) : \ + xf86setjmperror((env)))) + +#else /* XFree86LOADER || NEED_XF86_PROTOTYPES */ +#include +#include +#include +#include +#include +#include +#ifdef HAVE_SYSV_IPC +#include +#include +#endif +#include +#define stat_t struct stat +#endif /* XFree86LOADER || NEED_XF86_PROTOTYPES */ + +/* + * These things are always required by drivers (but not by libc_wrapper.c), + * even for a static server because some OSs don't provide them. + */ + +extern int xf86getpagesize(void); +extern void xf86usleep(unsigned long); +extern void xf86getsecs(long *, long *); +#ifndef DONT_DEFINE_WRAPPERS +#undef getpagesize +#define getpagesize() xf86getpagesize() +#undef usleep +#define usleep(ul) xf86usleep(ul) +#undef getsecs +#define getsecs(a, b) xf86getsecs(a, b) +#endif +#endif /* _XF86_ANSIC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_libc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_libc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86_libc.h (revision 51223) @@ -0,0 +1,728 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/os-support/xf86_libc.h,v 1.10 2006/01/28 02:20:37 anholt Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86_libc.h,v 3.63 2003/12/08 21:46:55 alanh Exp $ */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file is an attempt to make developing code for the new loadable module + * architecure simpler. It tries to use macros to hide all libc wrappers so + * that all that is needed to "port" a module to this architecture is to + * include this one header file + * + * Revision history: + * + * + * 0.4 Apr 12 1997 add the ANSI defines + * 0.3 Feb 24 1997 handle getenv + * 0.2 Feb 24 1997 hide few FILE functions + * 0.1 Feb 24 1997 hide the trivial functions mem* str* + */ + +#ifndef XF86_LIBC_H +#define XF86_LIBC_H 1 + +#include +#include + +/* + * The first set of definitions are required both for modules and + * libc_wrapper.c. + */ + +#if defined(XFree86LOADER) || defined(NEED_XF86_TYPES) + +/* + * First, the new data types + * + * note: if some pointer is declared "opaque" here, pass it between + * xf86* functions only, and don't rely on it having a whatever internal + * structure, even if some source file might reveal the existence of + * such a structure. + */ +typedef void XF86FILE; /* opaque FILE replacement */ +extern XF86FILE* xf86stdin; +extern XF86FILE* xf86stdout; +extern XF86FILE* xf86stderr; + +typedef void XF86fpos_t; /* opaque fpos_t replacement */ + +#define _XF86NAMELEN 263 /* enough for a larger filename */ + /* (divisble by 8) */ +typedef void XF86DIR; /* opaque DIR replacement */ + +/* Note: the following is POSIX! POSIX only requires the d_name member. + * Normal Unix has often a number of other members, but don't rely on that + */ +struct _xf86dirent { /* types in struct dirent/direct: */ + char d_name[_XF86NAMELEN+1]; /* char [MAXNAMLEN]; might be smaller or unaligned */ +}; +typedef struct _xf86dirent XF86DIRENT; + +typedef unsigned long xf86size_t; +typedef signed long xf86ssize_t; +typedef unsigned long xf86dev_t; +typedef unsigned int xf86mode_t; +typedef unsigned int xf86uid_t; +typedef unsigned int xf86gid_t; + +struct xf86stat { + xf86dev_t st_rdev; /* This is incomplete, and makes assumptions */ +}; + +/* sysv IPC */ +typedef int xf86key_t; + +/* setjmp/longjmp */ +#if defined(__ia64__) +typedef int xf86jmp_buf[1024] __attribute__ ((aligned (16))); /* guarantees 128-bit alignment! */ +#else +typedef int xf86jmp_buf[1024]; +#endif + +/* for setvbuf */ +#define XF86_IONBF 1 +#define XF86_IOFBF 2 +#define XF86_IOLBF 3 + +/* for open (XXX not complete) */ +#define XF86_O_RDONLY 0x0000 +#define XF86_O_WRONLY 0x0001 +#define XF86_O_RDWR 0x0002 +#define XF86_O_CREAT 0x0200 + +/* for mmap */ +#define XF86_PROT_EXEC 0x0001 +#define XF86_PROT_READ 0x0002 +#define XF86_PROT_WRITE 0x0004 +#define XF86_PROT_NONE 0x0008 +#define XF86_MAP_FIXED 0x0001 +#define XF86_MAP_SHARED 0x0002 +#define XF86_MAP_PRIVATE 0x0004 +#define XF86_MAP_32BIT 0x0040 +#define XF86_MAP_FAILED ((void *)-1) + +/* for fseek */ +#define XF86_SEEK_SET 0 +#define XF86_SEEK_CUR 1 +#define XF86_SEEK_END 2 + +/* for access */ +#define XF86_R_OK 0 +#define XF86_W_OK 1 +#define XF86_X_OK 2 +#define XF86_F_OK 3 + +/* for chmod */ +#define XF86_S_ISUID 04000 /* set user ID on execution */ +#define XF86_S_ISGID 02000 /* set group ID on execution */ +#define XF86_S_ISVTX 01000 /* sticky bit */ +#define XF86_S_IRUSR 00400 /* read by owner */ +#define XF86_S_IWUSR 00200 /* write by owner */ +#define XF86_S_IXUSR 00100 /* execute/search by owner */ +#define XF86_S_IRGRP 00040 /* read by group */ +#define XF86_S_IWGRP 00020 /* write by group */ +#define XF86_S_IXGRP 00010 /* execute/search by group */ +#define XF86_S_IROTH 00004 /* read by others */ +#define XF86_S_IWOTH 00002 /* write by others */ +#define XF86_S_IXOTH 00001 /* execute/search by others */ + +/* for mknod */ +#define XF86_S_IFREG 0010000 +#define XF86_S_IFCHR 0020000 +#define XF86_S_IFBLK 0040000 +#define XF86_S_IFIFO 0100000 + +/* + * errno values + * They start at 1000 just so they don't match real errnos at all + */ +#define xf86_UNKNOWN 1000 +#define xf86_EACCES 1001 +#define xf86_EAGAIN 1002 +#define xf86_EBADF 1003 +#define xf86_EEXIST 1004 +#define xf86_EFAULT 1005 +#define xf86_EINTR 1006 +#define xf86_EINVAL 1007 +#define xf86_EISDIR 1008 +#define xf86_ELOOP 1009 +#define xf86_EMFILE 1010 +#define xf86_ENAMETOOLONG 1011 +#define xf86_ENFILE 1012 +#define xf86_ENOENT 1013 +#define xf86_ENOMEM 1014 +#define xf86_ENOSPC 1015 +#define xf86_ENOTDIR 1016 +#define xf86_EPIPE 1017 +#define xf86_EROFS 1018 +#define xf86_ETXTBSY 1019 +#define xf86_ENOTTY 1020 +#define xf86_ENOSYS 1021 +#define xf86_EBUSY 1022 +#define xf86_ENODEV 1023 +#define xf86_EIO 1024 + +#define xf86_ESRCH 1025 +#define xf86_ENXIO 1026 +#define xf86_E2BIG 1027 +#define xf86_ENOEXEC 1028 +#define xf86_ECHILD 1029 +#define xf86_ENOTBLK 1030 +#define xf86_EXDEV 1031 +#define xf86_EFBIG 1032 +#define xf86_ESPIPE 1033 +#define xf86_EMLINK 1034 +#define xf86_EDOM 1035 +#define xf86_ERANGE 1036 + + +/* sysv IPV */ +/* xf86shmget() */ +#define XF86IPC_CREAT 01000 +#define XF86IPC_EXCL 02000 +#define XF86IPC_NOWAIT 04000 +#define XF86SHM_R 0400 +#define XF86SHM_W 0200 +#define XF86IPC_PRIVATE ((xf86key_t)0) +/* xf86shmat() */ +#define XF86SHM_RDONLY 010000 /* attach read-only else read-write */ +#define XF86SHM_RND 020000 /* round attach address to SHMLBA */ +#define XF86SHM_REMAP 040000 /* take-over region on attach */ +/* xf86shmclt() */ +#define XF86IPC_RMID 0 + +#endif /* defined(XFree86LOADER) || defined(NEED_XF86_TYPES) */ + +/* + * the rest of this file should only be included for code that is supposed + * to go into modules + */ + +#if defined(XFree86LOADER) && !defined(DONT_DEFINE_WRAPPERS) + +#undef abort +#define abort() xf86abort() +#undef abs +#define abs(i) xf86abs(i) +#undef acos +#define acos(d) xf86acos(d) +#undef asin +#define asin(d) xf86asin(d) +#undef atan +#define atan(d) xf86atan(d) +#undef atan2 +#define atan2(d1,d2) xf86atan2(d1,d2) +#undef atof +#define atof(ccp) xf86atof(ccp) +#undef atoi +#define atoi(ccp) xf86atoi(ccp) +#undef atol +#define atol(ccp) xf86atol(ccp) +#undef bsearch +#define bsearch(a,b,c,d,e) xf86bsearch(a,b,c,d,e) +#undef ceil +#define ceil(d) xf86ceil(d) +#undef calloc +#define calloc(I1,I2) xf86calloc(I1,I2) +#undef clearerr +#define clearerr(FP) xf86clearerr(FP) +#undef cos +#define cos(d) xf86cos(d) +#undef exit +#define exit(i) xf86exit(i) +#undef exp +#define exp(d) xf86exp(d) +#undef fabs +#define fabs(d) xf86fabs(d) +#undef fclose +#define fclose(FP) xf86fclose(FP) +#undef feof +#define feof(FP) xf86feof(FP) +#undef ferror +#define ferror(FP) xf86ferror(FP) +#undef fflush +#define fflush(FP) xf86fflush(FP) +#undef fgetc +#define fgetc(FP) xf86fgetc(FP) +#undef getc +#define getc(FP) xf86getc(FP) +#undef fgetpos +#define fgetpos(FP,fpp) xf86fgetpos(FP,fpp) +#undef fgets +#define fgets(cp,i,FP) xf86fgets(cp,i,FP) +#undef finite +#define finite(d) xf86finite(d) +#undef floor +#define floor(d) xf86floor(d) +#undef fmod +#define fmod(d1,d2) xf86fmod(d1,d2) +#undef fopen +#define fopen(ccp1,ccp2) xf86fopen(ccp1,ccp2) +#undef printf +#define printf xf86printf +#undef fprintf +#define fprintf xf86fprintf +#undef fputc +#define fputc(i,FP) xf86fputc(i,FP) +#undef fputs +#define fputs(ccp,FP) xf86fputs(ccp,FP) +#undef fread +#define fread(vp,I1,I2,FP) xf86fread(vp,I1,I2,FP) +#undef free +#define free(vp) xf86free(vp) +#undef freopen +#define freopen(ccp1,ccp2,FP) xf86freopen(ccp1,ccp2,FP) +#undef frexp +#define frexp(x,exp) xf86frexp(x,exp) +#undef fscanf +#define fscanf xf86fscanf +#undef fseek +#define fseek(FP,l,i) xf86fseek(FP,l,i) +#undef fsetpos +#define fsetpos(FP,cfpp) xf86fsetpos(FP,cfpp) +#undef ftell +#define ftell(FP) xf86ftell(FP) +#undef fwrite +#define fwrite(cvp,I1,I2,FP) xf86fwrite(cvp,I1,I2,FP) +#undef getenv +#define getenv(ccp) xf86getenv(ccp) +#undef isalnum +#define isalnum(i) xf86isalnum(i) +#undef isalpha +#define isalpha(i) xf86isalpha(i) +#undef iscntrl +#define iscntrl(i) xf86iscntrl(i) +#undef isdigit +#define isdigit(i) xf86isdigit(i) +#undef isgraph +#define isgraph(i) xf86isgraph(i) +#undef islower +#define islower(i) xf86islower(i) +#undef isprint +#define isprint(i) xf86isprint(i) +#undef ispunct +#define ispunct(i) xf86ispunct(i) +#undef isspace +#define isspace(i) xf86isspace(i) +#undef isupper +#define isupper(i) xf86isupper(i) +#undef isxdigit +#define isxdigit(i) xf86isxdigit(i) +#undef labs +#define labs(l) xf86labs(l) +#undef ldexp +#define ldexp(x, exp) xf86ldexp(x, exp) +#undef log +#define log(d) xf86log(d) +#undef log10 +#define log10(d) xf86log10(d) +#undef malloc +#define malloc(I) xf86malloc(I) +#undef memchr +#define memchr(cvp,i,I) xf86memchr(cvp,i,I) +#undef memcmp +#define memcmp(cvp1,cvp2,I) xf86memcmp(cvp1,cvp2,I) +#undef memcpy +#define memcpy(vp,cvp,I) xf86memcpy(vp,cvp,I) +#undef memmove +#define memmove(vp,cvp,I) xf86memmove(vp,cvp,I) +#undef memset +#define memset(vp,int,I) xf86memset(vp,int,I) +#undef modf +#define modf(d,dp) xf86modf(d,dp) +#undef perror +#define perror(ccp) xf86perror(ccp) +#undef pow +#define pow(d1,d2) xf86pow(d1,d2) +#undef random +#define random() xf86random() +#undef realloc +#define realloc(vp,I) xf86realloc(vp,I) +#undef remove +#define remove(ccp) xf86remove(ccp) +#undef rename +#define rename(ccp1,ccp2) xf86rename(ccp1,ccp2) +#undef rewind +#define rewind(FP) xf86rewind(FP) +#undef setbuf +#define setbuf(FP,cp) xf86setbuf(FP,cp) +#undef setvbuf +#define setvbuf(FP,cp,i,I) xf86setvbuf(FP,cp,i,I) +#undef sin +#define sin(d) xf86sin(d) +#undef snprintf +#define snprintf xf86snprintf +#undef sprintf +#define sprintf xf86sprintf +#undef sqrt +#define sqrt(d) xf86sqrt(d) +#undef sscanf +#define sscanf xf86sscanf +#undef strcat +#define strcat(cp,ccp) xf86strcat(cp,ccp) +#undef strcmp +#define strcmp(ccp1,ccp2) xf86strcmp(ccp1,ccp2) +#undef strcasecmp +#define strcasecmp(ccp1,ccp2) xf86strcasecmp(ccp1,ccp2) +#undef strcpy +#define strcpy(cp,ccp) xf86strcpy(cp,ccp) +#undef strcspn +#define strcspn(ccp1,ccp2) xf86strcspn(ccp1,ccp2) +#undef strerror +#define strerror(i) xf86strerror(i) +#undef strlcat +#define strlcat(cp,ccp,I) xf86strlcat(cp,ccp,I) +#undef strlcpy +#define strlcpy(cp,ccp,I) xf86strlcpy(cp,ccp,I) +#undef strlen +#define strlen(ccp) xf86strlen(ccp) +#undef strncmp +#define strncmp(ccp1,ccp2,I) xf86strncmp(ccp1,ccp2,I) +#undef strncasecmp +#define strncasecmp(ccp1,ccp2,I) xf86strncasecmp(ccp1,ccp2,I) +#undef strncpy +#define strncpy(cp,ccp,I) xf86strncpy(cp,ccp,I) +#undef strpbrk +#define strpbrk(ccp1,ccp2) xf86strpbrk(ccp1,ccp2) +#undef strchr +#define strchr(ccp,i) xf86strchr(ccp,i) +#undef strrchr +#define strrchr(ccp,i) xf86strrchr(ccp,i) +#undef strspn +#define strspn(ccp1,ccp2) xf86strspn(ccp1,ccp2) +#undef strstr +#define strstr(ccp1,ccp2) xf86strstr(ccp1,ccp2) +#undef srttod +#define strtod(ccp,cpp) xf86strtod(ccp,cpp) +#undef strtok +#define strtok(cp,ccp) xf86strtok(cp,ccp) +#undef strtol +#define strtol(ccp,cpp,i) xf86strtol(ccp,cpp,i) +#undef strtoul +#define strtoul(ccp,cpp,i) xf86strtoul(ccp,cpp,i) +#undef tan +#define tan(d) xf86tan(d) +#undef tmpfile +#define tmpfile() xf86tmpfile() +#undef tolower +#define tolower(i) xf86tolower(i) +#undef toupper +#define toupper(i) xf86toupper(i) +#undef ungetc +#define ungetc(i,FP) xf86ungetc(i,FP) +#undef vfprinf +#define vfprintf(p,f,a) xf86vfprintf(p,f,a) +#undef vsnprintf +#define vsnprintf(s,n,f,a) xf86vsnprintf(s,n,f,a) +#undef vsprintf +#define vsprintf(s,f,a) xf86vsprintf(s,f,a) +/* XXX Disable assert as if NDEBUG was defined */ +/* Some X headers defined this away too */ +#undef assert +#define assert(a) ((void)0) +#undef HUGE_VAL +#define HUGE_VAL xf86HUGE_VAL + +#undef hypot +#define hypot(x,y) xf86hypot(x,y) + +#undef qsort +#define qsort(b, n, s, f) xf86qsort(b, n, s, f) + +/* non-ANSI C functions */ +#undef opendir +#define opendir(cp) xf86opendir(cp) +#undef closedir +#define closedir(DP) xf86closedir(DP) +#undef readdir +#define readdir(DP) xf86readdir(DP) +#undef rewinddir +#define rewinddir(DP) xf86rewinddir(DP) +#undef bcopy +#define bcopy(vp,cvp,I) xf86memmove(cvp,vp,I) +#undef ffs +#define ffs(i) xf86ffs(i) +#undef strdup +#define strdup(ccp) xf86strdup(ccp) +#undef bzero +#define bzero(vp,ui) xf86bzero(vp,ui) +#undef execl +#define execl xf86execl +#undef chmod +#define chmod(a,b) xf86chmod(a,b) +#undef chown +#define chown(a,b,c) xf86chown(a,b,c) +#undef geteuid +#define geteuid xf86geteuid +#undef getegid +#define getegid xf86getegid +#undef getpid +#define getpid xf86getpid +#undef mknod +#define mknod(a,b,c) xf86mknod(a,b,c) +#undef sleep +#define sleep(a) xf86sleep(a) +#undef mkdir +#define mkdir(a,b) xf86mkdir(a,b) +#undef getpagesize +#define getpagesize xf86getpagesize +#undef shmget +#define shmget(a,b,c) xf86shmget(a,b,c) +#undef shmat +#define shmat(a,b,c) xf86shmat(a,b,c) +#undef shmdt +#define shmdt(a) xf86shmdt(a) +#undef shmctl +#define shmctl(a,b,c) xf86shmctl(a,b,c) + +#undef S_ISUID +#define S_ISUID XF86_S_ISUID +#undef S_ISGID +#define S_ISGID XF86_S_ISGID +#undef S_ISVTX +#define S_ISVTX XF86_S_ISVTX +#undef S_IRUSR +#define S_IRUSR XF86_S_IRUSR +#undef S_IWUSR +#define S_IWUSR XF86_S_IWUSR +#undef S_IXUSR +#define S_IXUSR XF86_S_IXUSR +#undef S_IRGRP +#define S_IRGRP XF86_S_IRGRP +#undef S_IWGRP +#define S_IWGRP XF86_S_IWGRP +#undef S_IXGRP +#define S_IXGRP XF86_S_IXGRP +#undef S_IROTH +#define S_IROTH XF86_S_IROTH +#undef S_IWOTH +#define S_IWOTH XF86_S_IWOTH +#undef S_IXOTH +#define S_IXOTH XF86_S_IXOTH +#undef S_IFREG +#define S_IFREG XF86_S_IFREG +#undef S_IFCHR +#define S_IFCHR XF86_S_IFCHR +#undef S_IFBLK +#define S_IFBLK XF86_S_IFBLK +#undef S_IFIFO +#define S_IFIFO XF86_S_IFIFO + +/* some types */ +#undef FILE +#define FILE XF86FILE +#undef fpos_t +#define fpos_t XF86fpos_t +#undef DIR +#define DIR XF86DIR +#undef DIRENT +#define DIRENT XF86DIRENT +#undef size_t +#define size_t xf86size_t +#undef ssize_t +#define ssize_t xf86ssize_t +#undef dev_t +#define dev_t xf86dev_t +#undef mode_t +#define mode_t xf86mode_t +#undef uid_t +#define uid_t xf86uid_t +#undef gid_t +#define gid_t xf86gid_t +#undef stat_t +#define stat_t struct xf86stat + +#undef ulong +#define ulong unsigned long + +/* + * There should be no need to #undef any of these. If they are already + * defined it is because some illegal header has been included. + */ + +/* some vars */ +#undef stdin +#define stdin xf86stdin +#undef stdout +#define stdout xf86stdout +#undef stderr +#define stderr xf86stderr + +#undef SEEK_SET +#define SEEK_SET XF86_SEEK_SET +#undef SEEK_CUR +#define SEEK_CUR XF86_SEEK_CUR +#undef SEEK_END +#define SEEK_END XF86_SEEK_END + +/* + * XXX Basic I/O functions BAD,BAD,BAD! + */ +#define open xf86open +#define close(a) xf86close(a) +#define lseek(a,b,c) xf86lseek(a,b,c) +#if !defined(__DragonFly__) +#define ioctl(a,b,c) xf86ioctl(a,b,c) +#endif +#define read(a,b,c) xf86read(a,b,c) +#define write(a,b,c) xf86write(a,b,c) +#define mmap(a,b,c,d,e,f) xf86mmap(a,b,c,d,e,f) +#define munmap(a,b) xf86munmap(a,b) +#define stat(a,b) xf86stat(a,b) +#define fstat(a,b) xf86fstat(a,b) +#define access(a,b) xf86access(a,b) +#undef O_RDONLY +#define O_RDONLY XF86_O_RDONLY +#undef O_WRONLY +#define O_WRONLY XF86_O_WRONLY +#undef O_RDWR +#define O_RDWR XF86_O_RDWR +#undef O_CREAT +#define O_CREAT XF86_O_CREAT +#undef PROT_EXEC +#define PROT_EXEC XF86_PROT_EXEC +#undef PROT_READ +#define PROT_READ XF86_PROT_READ +#undef PROT_WRITE +#define PROT_WRITE XF86_PROT_WRITE +#undef PROT_NONE +#define PROT_NONE XF86_PROT_NONE +#undef MAP_FIXED +#define MAP_FIXED XF86_MAP_FIXED +#undef MAP_SHARED +#define MAP_SHARED XF86_MAP_SHARED +#undef MAP_PRIVATE +#define MAP_PRIVATE XF86_MAP_PRIVATE +#undef MAP_FAILED +#define MAP_FAILED XF86_MAP_FAILED +#undef R_OK +#define R_OK XF86_R_OK +#undef W_OK +#define W_OK XF86_W_OK +#undef X_OK +#define X_OK XF86_X_OK +#undef F_OK +#define F_OK XF86_F_OK +#undef errno +#define errno xf86errno +#undef putchar +#define putchar(i) xf86fputc(i, xf86stdout) +#undef puts +#define puts(s) xf86fputs(s, xf86stdout) + +#undef EACCES +#define EACCES xf86_EACCES +#undef EAGAIN +#define EAGAIN xf86_EAGAIN +#undef EBADF +#define EBADF xf86_EBADF +#undef EEXIST +#define EEXIST xf86_EEXIST +#undef EFAULT +#define EFAULT xf86_EFAULT +#undef EINTR +#define EINTR xf86_EINTR +#undef EINVAL +#define EINVAL xf86_EINVAL +#undef EISDIR +#define EISDIR xf86_EISDIR +#undef ELOOP +#define ELOOP xf86_ELOOP +#undef EMFILE +#define EMFILE xf86_EMFILE +#undef ENAMETOOLONG +#define ENAMETOOLONG xf86_ENAMETOOLONG +#undef ENFILE +#define ENFILE xf86_ENFILE +#undef ENOENT +#define ENOENT xf86_ENOENT +#undef ENOMEM +#define ENOMEM xf86_ENOMEM +#undef ENOSPC +#define ENOSPC xf86_ENOSPC +#undef ENOTDIR +#define ENOTDIR xf86_ENOTDIR +#undef EPIPE +#define EPIPE xf86_EPIPE +#undef EROFS +#define EROFS xf86_EROFS +#undef ETXTBSY +#define ETXTBSY xf86_ETXTBSY +#undef ENOTTY +#define ENOTTY xf86_ENOTTY +#undef ENOSYS +#define ENOSYS xf86_ENOSYS +#undef EBUSY +#define EBUSY xf86_EBUSY +#undef ENODEV +#define ENODEV xf86_ENODEV +#undef EIO +#define EIO xf86_EIO + +/* IPC stuff */ +#undef SHM_RDONLY +#define SHM_RDONLY XF86SHM_RDONLY +#undef SHM_RND +#define SHM_RND XF86SHM_RND +#undef SHM_REMAP +#define SHM_REMAP XF86SHM_REMAP +#undef IPC_RMID +#define IPC_RMID XF86IPC_RMID +#undef IPC_CREAT +#define IPC_CREAT XF86IPC_CREAT +#undef IPC_EXCL +#define IPC_EXCL XF86IPC_EXCL +#undef PC_NOWAIT +#define IPC_NOWAIT XF86IPC_NOWAIT +#undef SHM_R +#define SHM_R XF86SHM_R +#undef SHM_W +#define SHM_W XF86SHM_W +#undef IPC_PRIVATE +#define IPC_PRIVATE XF86IPC_PRIVATE + +/* Some ANSI macros */ +#undef FILENAME_MAX +#define FILENAME_MAX 1024 + +#if (defined(sun) && defined(__SVR4)) +# define _FILEDEFED /* Already have FILE defined, don't redefine it */ +#endif + +#endif /* XFree86LOADER && !DONT_DEFINE_WRAPPERS */ + +#if defined(XFree86LOADER) && \ + (!defined(DONT_DEFINE_WRAPPERS) || defined(DEFINE_SETJMP_WRAPPERS)) +#undef setjmp +#define setjmp(a) xf86setjmp_macro(a) +#undef longjmp +#define longjmp(a,b) xf86longjmp(a,b) +#undef jmp_buf +#define jmp_buf xf86jmp_buf +#endif + +#endif /* XF86_LIBC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86cmap.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86cmap.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86cmap.h (revision 51223) @@ -0,0 +1,76 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86cmap.h,v 1.9 2003/10/17 20:02:12 alanh Exp $ */ + +/* + * Copyright (c) 1998-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86CMAP_H +#define _XF86CMAP_H + +#include "xf86str.h" +#include "colormapst.h" + +#define CMAP_PALETTED_TRUECOLOR 0x0000001 +#define CMAP_RELOAD_ON_MODE_SWITCH 0x0000002 +#define CMAP_LOAD_EVEN_IF_OFFSCREEN 0x0000004 + +Bool xf86HandleColormaps( + ScreenPtr pScreen, + int maxCol, + int sigRGBbits, + xf86LoadPaletteProc *loadPalette, + xf86SetOverscanProc *setOverscan, + unsigned int flags +); + +int +xf86ChangeGamma( + ScreenPtr pScreen, + Gamma newGamma +); + +int +xf86ChangeGammaRamp( + ScreenPtr pScreen, + int size, + unsigned short *red, + unsigned short *green, + unsigned short *blue +); + +int xf86GetGammaRampSize(ScreenPtr pScreen); + +int +xf86GetGammaRamp( + ScreenPtr pScreen, + int size, + unsigned short *red, + unsigned short *green, + unsigned short *blue +); + +#endif /* _XF86CMAP_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86dgaext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86dgaext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86dgaext.h (revision 51223) @@ -0,0 +1,12 @@ +/* $XFree86$ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86DGAEXT_H_ +#define _XF86DGAEXT_H_ + +extern DISPATCH_PROC(ProcXF86DGADispatch); + +#endif /* _XF86DGAEXT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86drm.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86drm.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86drm.h (revision 51223) @@ -0,0 +1,638 @@ +/** + * \file xf86drm.h + * OS-independent header for DRM user-level library interface. + * + * \author Rickard E. (Rik) Faith + */ + +/* + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h,v 1.26 2003/08/16 19:26:37 dawes Exp $ */ + +#ifndef _XF86DRM_H_ +#define _XF86DRM_H_ + +#include + + /* Defaults, if nothing set in xf86config */ +#define DRM_DEV_UID 0 +#define DRM_DEV_GID 0 +/* Default /dev/dri directory permissions 0755 */ +#define DRM_DEV_DIRMODE \ + (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) +#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) + +#define DRM_DIR_NAME "/dev/dri" +#define DRM_DEV_NAME "%s/card%d" +#define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */ + +#define DRM_ERR_NO_DEVICE (-1001) +#define DRM_ERR_NO_ACCESS (-1002) +#define DRM_ERR_NOT_ROOT (-1003) +#define DRM_ERR_INVALID (-1004) +#define DRM_ERR_NO_FD (-1005) + +#define DRM_AGP_NO_HANDLE 0 + +typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */ +typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */ + +/** + * Driver version information. + * + * \sa drmGetVersion() and drmSetVersion(). + */ +typedef struct _drmVersion { + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ + int name_len; /**< Length of name buffer */ + char *name; /**< Name of driver */ + int date_len; /**< Length of date buffer */ + char *date; /**< User-space buffer to hold date */ + int desc_len; /**< Length of desc buffer */ + char *desc; /**< User-space buffer to hold desc */ +} drmVersion, *drmVersionPtr; + +typedef struct _drmStats { + unsigned long count; /**< Number of data */ + struct { + unsigned long value; /**< Value from kernel */ + const char *long_format; /**< Suggested format for long_name */ + const char *long_name; /**< Long name for value */ + const char *rate_format; /**< Suggested format for rate_name */ + const char *rate_name; /**< Short name for value per second */ + int isvalue; /**< True if value (vs. counter) */ + const char *mult_names; /**< Multiplier names (e.g., "KGM") */ + int mult; /**< Multiplier value (e.g., 1024) */ + int verbose; /**< Suggest only in verbose output */ + } data[15]; +} drmStatsT; + + + /* All of these enums *MUST* match with the + kernel implementation -- so do *NOT* + change them! (The drmlib implementation + will just copy the flags instead of + translating them.) */ +typedef enum { + DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */ + DRM_REGISTERS = 1, /**< no caching, no core dump */ + DRM_SHM = 2, /**< shared, cached */ + DRM_AGP = 3, /**< AGP/GART */ + DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */ + DRM_CONSISTENT = 5 /**< PCI consistent */ +} drmMapType; + +typedef enum { + DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */ + DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */ + DRM_LOCKED = 0x0004, /**< Physical pages locked */ + DRM_KERNEL = 0x0008, /**< Kernel requires access */ + DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */ + DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */ + DRM_REMOVABLE = 0x0040 /**< Removable mapping */ +} drmMapFlags; + +/** + * \warning These values *MUST* match drm.h + */ +typedef enum { + /** \name Flags for DMA buffer dispatch */ + /*@{*/ + DRM_DMA_BLOCK = 0x01, /**< + * Block until buffer dispatched. + * + * \note the buffer may not yet have been + * processed by the hardware -- getting a + * hardware lock with the hardware quiescent + * will ensure that the buffer has been + * processed. + */ + DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ + DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + /*@}*/ + + /** \name Flags for DMA buffer request */ + /*@{*/ + DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ + /*@}*/ +} drmDMAFlags; + +typedef enum { + DRM_PAGE_ALIGN = 0x01, + DRM_AGP_BUFFER = 0x02, + DRM_SG_BUFFER = 0x04, + DRM_FB_BUFFER = 0x08 +} drmBufDescFlags; + +typedef enum { + DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ + DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ +} drmLockFlags; + +typedef enum { + DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and + never swapped. */ + DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */ +} drm_context_tFlags, *drm_context_tFlagsPtr; + +typedef struct _drmBufDesc { + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ +} drmBufDesc, *drmBufDescPtr; + +typedef struct _drmBufInfo { + int count; /**< Number of buffers described in list */ + drmBufDescPtr list; /**< List of buffer descriptions */ +} drmBufInfo, *drmBufInfoPtr; + +typedef struct _drmBuf { + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + drmAddress address; /**< Address */ +} drmBuf, *drmBufPtr; + +/** + * Buffer mapping information. + * + * Used by drmMapBufs() and drmUnmapBufs() to store information about the + * mapped buffers. + */ +typedef struct _drmBufMap { + int count; /**< Number of buffers mapped */ + drmBufPtr list; /**< Buffers */ +} drmBufMap, *drmBufMapPtr; + +typedef struct _drmLock { + volatile unsigned int lock; + char padding[60]; + /* This is big enough for most current (and future?) architectures: + DEC Alpha: 32 bytes + Intel Merced: ? + Intel P5/PPro/PII/PIII: 32 bytes + Intel StrongARM: 32 bytes + Intel i386/i486: 16 bytes + MIPS: 32 bytes (?) + Motorola 68k: 16 bytes + Motorola PowerPC: 32 bytes + Sun SPARC: 32 bytes + */ +} drmLock, *drmLockPtr; + +/** + * Indices here refer to the offset into + * list in drmBufInfo + */ +typedef struct _drmDMAReq { + drm_context_t context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int *send_list; /**< List of handles to buffers */ + int *send_sizes; /**< Lengths of data to send, in bytes */ + drmDMAFlags flags; /**< Flags */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size of buffers requested */ + int *request_list; /**< Buffer information */ + int *request_sizes; /**< Minimum acceptable sizes */ + int granted_count; /**< Number of buffers granted at this size */ +} drmDMAReq, *drmDMAReqPtr; + +typedef struct _drmRegion { + drm_handle_t handle; + unsigned int offset; + drmSize size; + drmAddress map; +} drmRegion, *drmRegionPtr; + +typedef struct _drmTextureRegion { + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; /**< Explicitly pad this out */ + unsigned int age; +} drmTextureRegion, *drmTextureRegionPtr; + + +typedef enum { + DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ +} drmVBlankSeqType; + +typedef struct _drmVBlankReq { + drmVBlankSeqType type; + unsigned int sequence; + unsigned long signal; +} drmVBlankReq, *drmVBlankReqPtr; + +typedef struct _drmVBlankReply { + drmVBlankSeqType type; + unsigned int sequence; + long tval_sec; + long tval_usec; +} drmVBlankReply, *drmVBlankReplyPtr; + +typedef union _drmVBlank { + drmVBlankReq request; + drmVBlankReply reply; +} drmVBlank, *drmVBlankPtr; + +typedef struct _drmSetVersion { + int drm_di_major; + int drm_di_minor; + int drm_dd_major; + int drm_dd_minor; +} drmSetVersion, *drmSetVersionPtr; + + +#define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) + +#define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ +#define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ + +#if defined(__GNUC__) && (__GNUC__ >= 2) +# if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) + /* Reflect changes here to drmP.h */ +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + int __dummy; /* Can't mark eax as clobbered */ \ + __asm__ __volatile__( \ + "lock ; cmpxchg %4,%1\n\t" \ + "setnz %0" \ + : "=d" (__ret), \ + "=m" (__drm_dummy_lock(lock)), \ + "=a" (__dummy) \ + : "2" (old), \ + "r" (new)); \ + } while (0) + +#elif defined(__alpha__) + +#define DRM_CAS(lock, old, new, ret) \ + do { \ + int old32; \ + int cur32; \ + __asm__ __volatile__( \ + " mb\n" \ + " zap %4, 0xF0, %0\n" \ + " ldl_l %1, %2\n" \ + " zap %1, 0xF0, %1\n" \ + " cmpeq %0, %1, %1\n" \ + " beq %1, 1f\n" \ + " bis %5, %5, %1\n" \ + " stl_c %1, %2\n" \ + "1: xor %1, 1, %1\n" \ + " stl %1, %3" \ + : "=r" (old32), \ + "=&r" (cur32), \ + "=m" (__drm_dummy_lock(lock)),\ + "=m" (ret) \ + : "r" (old), \ + "r" (new)); \ + } while(0) + +#elif defined(__sparc__) + +#define DRM_CAS(lock,old,new,__ret) \ +do { register unsigned int __old __asm("o0"); \ + register unsigned int __new __asm("o1"); \ + register volatile unsigned int *__lock __asm("o2"); \ + __old = old; \ + __new = new; \ + __lock = (volatile unsigned int *)lock; \ + __asm__ __volatile__( \ + /*"cas [%2], %3, %0"*/ \ + ".word 0xd3e29008\n\t" \ + /*"membar #StoreStore | #StoreLoad"*/ \ + ".word 0x8143e00a" \ + : "=&r" (__new) \ + : "0" (__new), \ + "r" (__lock), \ + "r" (__old) \ + : "memory"); \ + __ret = (__new != __old); \ +} while(0) + +#elif defined(__ia64__) + +#ifdef __INTEL_COMPILER +/* this currently generates bad code (missing stop bits)... */ +#include + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned long __result, __old = (old) & 0xffffffff; \ + __mf(); \ + __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ + __ret = (__result) != (__old); \ +/* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ + (old), (new)) \ + != (old)); */\ + } while (0) + +#else +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned int __result, __old = (old); \ + __asm__ __volatile__( \ + "mf\n" \ + "mov ar.ccv=%2\n" \ + ";;\n" \ + "cmpxchg4.acq %0=%1,%3,ar.ccv" \ + : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ + : "r" ((unsigned long)__old), "r" (new) \ + : "memory"); \ + __ret = (__result) != (__old); \ + } while (0) + +#endif + +#elif defined(__powerpc__) + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + __asm__ __volatile__( \ + "sync;" \ + "0: lwarx %0,0,%1;" \ + " xor. %0,%3,%0;" \ + " bne 1f;" \ + " stwcx. %2,0,%1;" \ + " bne- 0b;" \ + "1: " \ + "sync;" \ + : "=&r"(__ret) \ + : "r"(lock), "r"(new), "r"(old) \ + : "cr0", "memory"); \ + } while (0) + +#endif /* architecture */ +#endif /* __GNUC__ >= 2 */ + +#ifndef DRM_CAS +#define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ +#endif + +#if defined(__alpha__) || defined(__powerpc__) +#define DRM_CAS_RESULT(_result) int _result +#else +#define DRM_CAS_RESULT(_result) char _result +#endif + +#define DRM_LIGHT_LOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + } while(0) + + /* This one counts fast locks -- for + benchmarking only. */ +#define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + else ++count; \ + } while(0) + +#define DRM_LOCK(fd,lock,context,flags) \ + do { \ + if (flags) drmGetLock(fd,context,flags); \ + else DRM_LIGHT_LOCK(fd,lock,context); \ + } while(0) + +#define DRM_UNLOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ + if (__ret) drmUnlock(fd,context); \ + } while(0) + + /* Simple spin locks */ +#define DRM_SPINLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + do { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) while ((spin)->lock); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_TAKE(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + int cur; \ + do { \ + cur = (*spin).lock; \ + DRM_CAS(spin,cur,val,__ret); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ + do { \ + int __i; \ + __ret = 1; \ + for (__i = 0; __ret && __i < count; __i++) { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) for (;__i < count && (spin)->lock; __i++); \ + } \ + } while(0) + +#define DRM_SPINUNLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + if ((*spin).lock == val) { /* else server stole lock */ \ + do { \ + DRM_CAS(spin,val,0,__ret); \ + } while (__ret); \ + } \ + } while(0) + +/* General user-level programmer's API: unprivileged */ +extern int drmAvailable(void); +extern int drmOpen(const char *name, const char *busid); +extern int drmClose(int fd); +extern drmVersionPtr drmGetVersion(int fd); +extern drmVersionPtr drmGetLibVersion(int fd); +extern void drmFreeVersion(drmVersionPtr); +extern int drmGetMagic(int fd, drm_magic_t * magic); +extern char *drmGetBusid(int fd); +extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, + int funcnum); +extern int drmGetMap(int fd, int idx, drm_handle_t *offset, + drmSize *size, drmMapType *type, + drmMapFlags *flags, drm_handle_t *handle, + int *mtrr); +extern int drmGetClient(int fd, int idx, int *auth, int *pid, + int *uid, unsigned long *magic, + unsigned long *iocs); +extern int drmGetStats(int fd, drmStatsT *stats); +extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); +extern int drmCommandNone(int fd, unsigned long drmCommandIndex); +extern int drmCommandRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); + +/* General user-level programmer's API: X server (root) only */ +extern void drmFreeBusid(const char *busid); +extern int drmSetBusid(int fd, const char *busid); +extern int drmAuthMagic(int fd, drm_magic_t magic); +extern int drmAddMap(int fd, + drm_handle_t offset, + drmSize size, + drmMapType type, + drmMapFlags flags, + drm_handle_t * handle); +extern int drmRmMap(int fd, drm_handle_t handle); +extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t handle); + +extern int drmAddBufs(int fd, int count, int size, + drmBufDescFlags flags, + int agp_offset); +extern int drmMarkBufs(int fd, double low, double high); +extern int drmCreateContext(int fd, drm_context_t * handle); +extern int drmSetContextFlags(int fd, drm_context_t context, + drm_context_tFlags flags); +extern int drmGetContextFlags(int fd, drm_context_t context, + drm_context_tFlagsPtr flags); +extern int drmAddContextTag(int fd, drm_context_t context, void *tag); +extern int drmDelContextTag(int fd, drm_context_t context); +extern void *drmGetContextTag(int fd, drm_context_t context); +extern drm_context_t * drmGetReservedContextList(int fd, int *count); +extern void drmFreeReservedContextList(drm_context_t *); +extern int drmSwitchToContext(int fd, drm_context_t context); +extern int drmDestroyContext(int fd, drm_context_t handle); +extern int drmCreateDrawable(int fd, drm_drawable_t * handle); +extern int drmDestroyDrawable(int fd, drm_drawable_t handle); +extern int drmCtlInstHandler(int fd, int irq); +extern int drmCtlUninstHandler(int fd); +extern int drmInstallSIGIOHandler(int fd, + void (*f)(int fd, + void *oldctx, + void *newctx)); +extern int drmRemoveSIGIOHandler(int fd); + +/* General user-level programmer's API: authenticated client and/or X */ +extern int drmMap(int fd, + drm_handle_t handle, + drmSize size, + drmAddressPtr address); +extern int drmUnmap(drmAddress address, drmSize size); +extern drmBufInfoPtr drmGetBufInfo(int fd); +extern drmBufMapPtr drmMapBufs(int fd); +extern int drmUnmapBufs(drmBufMapPtr bufs); +extern int drmDMA(int fd, drmDMAReqPtr request); +extern int drmFreeBufs(int fd, int count, int *list); +extern int drmGetLock(int fd, + drm_context_t context, + drmLockFlags flags); +extern int drmUnlock(int fd, drm_context_t context); +extern int drmFinish(int fd, int context, drmLockFlags flags); +extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t * handle); + +/* AGP/GART support: X server (root) only */ +extern int drmAgpAcquire(int fd); +extern int drmAgpRelease(int fd); +extern int drmAgpEnable(int fd, unsigned long mode); +extern int drmAgpAlloc(int fd, unsigned long size, + unsigned long type, unsigned long *address, + drm_handle_t *handle); +extern int drmAgpFree(int fd, drm_handle_t handle); +extern int drmAgpBind(int fd, drm_handle_t handle, + unsigned long offset); +extern int drmAgpUnbind(int fd, drm_handle_t handle); + +/* AGP/GART info: authenticated client and/or X */ +extern int drmAgpVersionMajor(int fd); +extern int drmAgpVersionMinor(int fd); +extern unsigned long drmAgpGetMode(int fd); +extern unsigned long drmAgpBase(int fd); /* Physical location */ +extern unsigned long drmAgpSize(int fd); /* Bytes */ +extern unsigned long drmAgpMemoryUsed(int fd); +extern unsigned long drmAgpMemoryAvail(int fd); +extern unsigned int drmAgpVendorId(int fd); +extern unsigned int drmAgpDeviceId(int fd); + +/* PCI scatter/gather support: X server (root) only */ +extern int drmScatterGatherAlloc(int fd, unsigned long size, + drm_handle_t *handle); +extern int drmScatterGatherFree(int fd, drm_handle_t handle); + +extern int drmWaitVBlank(int fd, drmVBlankPtr vbl); + +/* Support routines */ +extern int drmError(int err, const char *label); +extern void *drmMalloc(int size); +extern void drmFree(void *pt); + +/* Hash table routines */ +extern void *drmHashCreate(void); +extern int drmHashDestroy(void *t); +extern int drmHashLookup(void *t, unsigned long key, void **value); +extern int drmHashInsert(void *t, unsigned long key, void *value); +extern int drmHashDelete(void *t, unsigned long key); +extern int drmHashFirst(void *t, unsigned long *key, void **value); +extern int drmHashNext(void *t, unsigned long *key, void **value); + +/* PRNG routines */ +extern void *drmRandomCreate(unsigned long seed); +extern int drmRandomDestroy(void *state); +extern unsigned long drmRandom(void *state); +extern double drmRandomDouble(void *state); + +/* Skip list routines */ + +extern void *drmSLCreate(void); +extern int drmSLDestroy(void *l); +extern int drmSLLookup(void *l, unsigned long key, void **value); +extern int drmSLInsert(void *l, unsigned long key, void *value); +extern int drmSLDelete(void *l, unsigned long key); +extern int drmSLNext(void *l, unsigned long *key, void **value); +extern int drmSLFirst(void *l, unsigned long *key, void **value); +extern void drmSLDump(void *l); +extern int drmSLLookupNeighbors(void *l, unsigned long key, + unsigned long *prev_key, void **prev_value, + unsigned long *next_key, void **next_value); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86fbman.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86fbman.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86fbman.h (revision 51223) @@ -0,0 +1,227 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86fbman.h,v 1.14 2003/10/09 12:40:54 alanh Exp $ */ + +/* + * Copyright (c) 1998-2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86FBMAN_H +#define _XF86FBMAN_H + + +#include "scrnintstr.h" +#include "regionstr.h" + + +#define FAVOR_AREA_THEN_WIDTH 0 +#define FAVOR_AREA_THEN_HEIGHT 1 +#define FAVOR_WIDTH_THEN_AREA 2 +#define FAVOR_HEIGHT_THEN_AREA 3 + +#define PRIORITY_LOW 0 +#define PRIORITY_NORMAL 1 +#define PRIORITY_EXTREME 2 + + +typedef struct _FBArea { + ScreenPtr pScreen; + BoxRec box; + int granularity; + void (*MoveAreaCallback)(struct _FBArea*, struct _FBArea*); + void (*RemoveAreaCallback)(struct _FBArea*); + DevUnion devPrivate; +} FBArea, *FBAreaPtr; + +typedef struct _FBLinear { + ScreenPtr pScreen; + int size; + int offset; + int granularity; + void (*MoveLinearCallback)(struct _FBLinear*, struct _FBLinear*); + void (*RemoveLinearCallback)(struct _FBLinear*); + DevUnion devPrivate; +} FBLinear, *FBLinearPtr; + +typedef void (*FreeBoxCallbackProcPtr)(ScreenPtr, RegionPtr, pointer); +typedef void (*MoveAreaCallbackProcPtr)(FBAreaPtr, FBAreaPtr); +typedef void (*RemoveAreaCallbackProcPtr)(FBAreaPtr); + +typedef void (*MoveLinearCallbackProcPtr)(FBLinearPtr, FBLinearPtr); +typedef void (*RemoveLinearCallbackProcPtr)(FBLinearPtr); + + +typedef struct { + FBAreaPtr (*AllocateOffscreenArea)( + ScreenPtr pScreen, + int w, int h, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData); + void (*FreeOffscreenArea)(FBAreaPtr area); + Bool (*ResizeOffscreenArea)(FBAreaPtr area, int w, int h); + Bool (*QueryLargestOffscreenArea)( + ScreenPtr pScreen, + int *width, int *height, + int granularity, + int preferences, + int priority); + Bool (*RegisterFreeBoxCallback)( + ScreenPtr pScreen, + FreeBoxCallbackProcPtr FreeBoxCallback, + pointer devPriv); +/* linear functions */ + FBLinearPtr (*AllocateOffscreenLinear)( + ScreenPtr pScreen, + int size, + int granularity, + MoveLinearCallbackProcPtr moveCB, + RemoveLinearCallbackProcPtr removeCB, + pointer privData); + void (*FreeOffscreenLinear)(FBLinearPtr area); + Bool (*ResizeOffscreenLinear)(FBLinearPtr area, int size); + Bool (*QueryLargestOffscreenLinear)( + ScreenPtr pScreen, + int *size, + int granularity, + int priority); + Bool (*PurgeOffscreenAreas) (ScreenPtr); +} FBManagerFuncs, *FBManagerFuncsPtr; + + +Bool xf86RegisterOffscreenManager( + ScreenPtr pScreen, + FBManagerFuncsPtr funcs +); + +Bool +xf86InitFBManagerRegion( + ScreenPtr pScreen, + RegionPtr ScreenRegion +); + +Bool +xf86InitFBManagerArea( + ScreenPtr pScreen, + int PixalArea, + int Verbosity +); + +Bool +xf86InitFBManager( + ScreenPtr pScreen, + BoxPtr FullBox +); + +Bool +xf86InitFBManagerLinear( + ScreenPtr pScreen, + int offset, + int size +); + +Bool +xf86FBManagerRunning( + ScreenPtr pScreen +); + +FBAreaPtr +xf86AllocateOffscreenArea ( + ScreenPtr pScreen, + int w, int h, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData +); + +FBAreaPtr +xf86AllocateLinearOffscreenArea ( + ScreenPtr pScreen, + int length, + int granularity, + MoveAreaCallbackProcPtr moveCB, + RemoveAreaCallbackProcPtr removeCB, + pointer privData +); + +FBLinearPtr +xf86AllocateOffscreenLinear ( + ScreenPtr pScreen, + int length, + int granularity, + MoveLinearCallbackProcPtr moveCB, + RemoveLinearCallbackProcPtr removeCB, + pointer privData +); + +void xf86FreeOffscreenArea(FBAreaPtr area); +void xf86FreeOffscreenLinear(FBLinearPtr area); + +Bool +xf86ResizeOffscreenArea( + FBAreaPtr resize, + int w, int h +); + +Bool +xf86ResizeOffscreenLinear( + FBLinearPtr resize, + int size +); + + +Bool +xf86RegisterFreeBoxCallback( + ScreenPtr pScreen, + FreeBoxCallbackProcPtr FreeBoxCallback, + pointer devPriv +); + +Bool +xf86PurgeUnlockedOffscreenAreas( + ScreenPtr pScreen +); + + +Bool +xf86QueryLargestOffscreenArea( + ScreenPtr pScreen, + int *width, int *height, + int granularity, + int preferences, + int priority +); + +Bool +xf86QueryLargestOffscreenLinear( + ScreenPtr pScreen, + int *size, + int granularity, + int priority +); + + +#endif /* _XF86FBMAN_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx.h (revision 51223) @@ -0,0 +1,39 @@ +/* $XFree86: xc/programs/Xserver/GL/include/GL/xf86glx.h,v 1.3 1999/06/14 07:31:41 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "miscstruct.h" Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx_util.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx_util.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glx_util.h (revision 51223) @@ -0,0 +1,106 @@ +/* $XFree86: xc/programs/Xserver/GL/mesa/src/X/xf86glx_util.h,v 1.5 2000/08/10 17:40:29 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Brian Paul + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86GLX_UTIL_H_ +#define _XF86GLX_UTIL_H_ + +#ifdef __CYGWIN__ +#undef WIN32 +#undef _WIN32 +#endif + +#include +#include +#include +#include "GL/xmesa.h" + +#define XMESA_USE_PUTPIXEL_MACRO + +struct _XMesaImageRec { + int width, height; + char *data; + int bytes_per_line; /* Padded to 32 bits */ + int bits_per_pixel; +}; + +extern XMesaImage *XMesaCreateImage(int bitsPerPixel, int width, int height, + char *data); +extern void XMesaDestroyImage(XMesaImage *image); +extern unsigned long XMesaGetPixel(XMesaImage *image, int x, int y); +#ifdef XMESA_USE_PUTPIXEL_MACRO +#define XMesaPutPixel(__i,__x,__y,__p) \ +{ \ + CARD8 *__row = (CARD8 *)(__i->data + __y*__i->bytes_per_line); \ + CARD8 *__i8; \ + CARD16 *__i16; \ + CARD32 *__i32; \ + switch (__i->bits_per_pixel) { \ + case 8: \ + __i8 = (CARD8 *)__row; \ + __i8[__x] = (CARD8)__p; \ + break; \ + case 15: \ + case 16: \ + __i16 = (CARD16 *)__row; \ + __i16[__x] = (CARD16)__p; \ + break; \ + case 24: /* WARNING: architecture specific code */ \ + __i8 = (CARD8 *)__row; \ + __i8[__x*3] = (CARD8)(__p); \ + __i8[__x*3+1] = (CARD8)(__p>>8); \ + __i8[__x*3+2] = (CARD8)(__p>>16); \ + break; \ + case 32: \ + __i32 = (CARD32 *)__row; \ + __i32[__x] = (CARD32)__p; \ + break; \ + } \ +} +#else +extern void XMesaPutPixel(XMesaImage *image, int x, int y, + unsigned long pixel); +#endif + +extern void XMesaPutImageHelper(ScreenPtr display, + DrawablePtr d, GCPtr gc, + XMesaImage *image, + int src_x, int src_y, + int dest_x, int dest_y, + unsigned int width, unsigned int height); + +#endif /* _XF86GLX_UTIL_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glxint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glxint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86glxint.h (revision 51223) @@ -0,0 +1,46 @@ +/* $XFree86: xc/programs/Xserver/GL/mesa/src/X/xf86glxint.h,v 1.4 2002/02/22 21:45:08 dawes Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86GLXINT_H_ +#define _XF86GLXINT_H_ + +#include +#include +#include + +#endif /* _XF86GLXINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86i2c.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86i2c.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86i2c.h (revision 51223) @@ -0,0 +1,97 @@ +/* + * Copyright (C) 1998 Itai Nahshon, Michael Schimek + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/i2c/xf86i2c.h,v 1.10 2003/07/16 01:38:47 dawes Exp $ */ + +#ifndef _XF86I2C_H +#define _XF86I2C_H + +#include "regionstr.h" + +typedef unsigned char I2CByte; +typedef unsigned short I2CSlaveAddr; + +typedef struct _I2CBusRec *I2CBusPtr; +typedef struct _I2CDevRec *I2CDevPtr; + +/* I2C masters have to register themselves */ + +typedef struct _I2CBusRec { + char * BusName; + int scrnIndex; + + void (*I2CUDelay) (I2CBusPtr b, int usec); + + void (*I2CPutBits)(I2CBusPtr b, int scl, int sda); + void (*I2CGetBits)(I2CBusPtr b, int *scl, int *sda); + + /* Look at the generic routines to see how these functions should behave. */ + + Bool (*I2CStart) (I2CBusPtr b, int timeout); + Bool (*I2CAddress)(I2CDevPtr d, I2CSlaveAddr); + void (*I2CStop) (I2CDevPtr d); + Bool (*I2CPutByte)(I2CDevPtr d, I2CByte data); + Bool (*I2CGetByte)(I2CDevPtr d, I2CByte *data, Bool); + + DevUnion DriverPrivate; + + int HoldTime; /* 1 / bus clock frequency, 5 or 2 usec */ + + int BitTimeout; /* usec */ + int ByteTimeout; /* usec */ + int AcknTimeout; /* usec */ + int StartTimeout; /* usec */ + int RiseFallTime; /* usec */ + + I2CDevPtr FirstDev; + I2CBusPtr NextBus; + Bool (*I2CWriteRead)(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead); +} I2CBusRec; + +I2CBusPtr xf86CreateI2CBusRec(void); +void xf86DestroyI2CBusRec(I2CBusPtr pI2CBus, Bool unalloc, Bool devs_too); +Bool xf86I2CBusInit(I2CBusPtr pI2CBus); +I2CBusPtr xf86I2CFindBus(int scrnIndex, char *name); +int xf86I2CGetScreenBuses(int scrnIndex, I2CBusPtr **pppI2CBus); + + +/* I2C slave devices */ + +typedef struct _I2CDevRec { + char * DevName; + + int BitTimeout; /* usec */ + int ByteTimeout; /* usec */ + int AcknTimeout; /* usec */ + int StartTimeout; /* usec */ + + I2CSlaveAddr SlaveAddr; + I2CBusPtr pI2CBus; + I2CDevPtr NextDev; + DevUnion DriverPrivate; +} I2CDevRec; + +I2CDevPtr xf86CreateI2CDevRec(void); +void xf86DestroyI2CDevRec(I2CDevPtr pI2CDev, Bool unalloc); +Bool xf86I2CDevInit(I2CDevPtr pI2CDev); +I2CDevPtr xf86I2CFindDev(I2CBusPtr, I2CSlaveAddr); + +/* See descriptions of these functions in xf86i2c.c */ + +Bool xf86I2CProbeAddress(I2CBusPtr pI2CBus, I2CSlaveAddr); +Bool xf86I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead); +#define xf86I2CRead(d, rb, nr) xf86I2CWriteRead(d, NULL, 0, rb, nr) +Bool xf86I2CReadStatus(I2CDevPtr d, I2CByte *pbyte); +Bool xf86I2CReadByte(I2CDevPtr d, I2CByte subaddr, I2CByte *pbyte); +Bool xf86I2CReadBytes(I2CDevPtr d, I2CByte subaddr, I2CByte *pbyte, int n); +Bool xf86I2CReadWord(I2CDevPtr d, I2CByte subaddr, unsigned short *pword); +#define xf86I2CWrite(d, wb, nw) xf86I2CWriteRead(d, wb, nw, NULL, 0) +Bool xf86I2CWriteByte(I2CDevPtr d, I2CByte subaddr, I2CByte byte); +Bool xf86I2CWriteBytes(I2CDevPtr d, I2CByte subaddr, I2CByte *WriteBuffer, int nWrite); +Bool xf86I2CWriteWord(I2CDevPtr d, I2CByte subaddr, unsigned short word); +Bool xf86I2CWriteVec(I2CDevPtr d, I2CByte *vec, int nValues); + +#endif /*_XF86I2C_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86int10.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86int10.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86int10.h (revision 51223) @@ -0,0 +1,198 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86int10.h,v 1.23 2002/04/04 14:05:51 eich Exp $ */ + +/* + * XFree86 int10 module + * execute BIOS int 10h calls in x86 real mode environment + * Copyright 1999 Egbert Eich + */ + +#ifndef _XF86INT10_H +#define _XF86INT10_H + +#include +#include +#include "xf86Pci.h" + +#define SEG_ADDR(x) (((x) >> 4) & 0x00F000) +#define SEG_OFF(x) ((x) & 0x0FFFF) + +#define SET_BIOS_SCRATCH 0x1 +#define RESTORE_BIOS_SCRATCH 0x2 + +/* int10 info structure */ +typedef struct { + int entityIndex; + int scrnIndex; + pointer cpuRegs; + CARD16 BIOSseg; + CARD16 inb40time; + char * BIOSScratch; + int Flags; + pointer private; + struct _int10Mem* mem; + int num; + int ax; + int bx; + int cx; + int dx; + int si; + int di; + int es; + int bp; + int flags; + int stackseg; + PCITAG Tag; + IOADDRESS ioBase; +} xf86Int10InfoRec, *xf86Int10InfoPtr; + +typedef struct _int10Mem { + CARD8(*rb)(xf86Int10InfoPtr, int); + CARD16(*rw)(xf86Int10InfoPtr, int); + CARD32(*rl)(xf86Int10InfoPtr, int); + void(*wb)(xf86Int10InfoPtr, int, CARD8); + void(*ww)(xf86Int10InfoPtr, int, CARD16); + void(*wl)(xf86Int10InfoPtr, int, CARD32); +} int10MemRec, *int10MemPtr; + +typedef struct { + CARD8 save_msr; + CARD8 save_pos102; + CARD8 save_vse; + CARD8 save_46e8; +} legacyVGARec, *legacyVGAPtr; + +typedef struct { + BusType bus; + union { + struct { + int bus; + int dev; + int func; + } pci; + int legacy; + } location; +} xf86int10BiosLocation, *xf86int10BiosLocationPtr; + +/* OS dependent functions */ +xf86Int10InfoPtr xf86InitInt10(int entityIndex); +xf86Int10InfoPtr xf86ExtendedInitInt10(int entityIndex, int Flags); +void xf86FreeInt10(xf86Int10InfoPtr pInt); +void *xf86Int10AllocPages(xf86Int10InfoPtr pInt, int num, int *off); +void xf86Int10FreePages(xf86Int10InfoPtr pInt, void *pbase, int num); +pointer xf86int10Addr(xf86Int10InfoPtr pInt, CARD32 addr); + +/* x86 executor related functions */ +void xf86ExecX86int10(xf86Int10InfoPtr pInt); + +#ifdef _INT10_PRIVATE + +#define I_S_DEFAULT_INT_VECT 0xFF065 +#define SYS_SIZE 0x100000 +#define SYS_BIOS 0xF0000 +#if 1 +#define BIOS_SIZE 0x10000 +#else /* a bug in DGUX requires this - let's try it */ +#define BIOS_SIZE (0x10000 - 1) +#endif +#define LOW_PAGE_SIZE 0x600 +#define V_RAM 0xA0000 +#define VRAM_SIZE 0x20000 +#define V_BIOS_SIZE 0x10000 +#define V_BIOS 0xC0000 +#define BIOS_SCRATCH_OFF 0x449 +#define BIOS_SCRATCH_END 0x466 +#define BIOS_SCRATCH_LEN (BIOS_SCRATCH_END - BIOS_SCRATCH_OFF + 1) +#define HIGH_MEM V_BIOS +#define HIGH_MEM_SIZE (SYS_BIOS - HIGH_MEM) +#define SEG_ADR(type, seg, reg) type((seg << 4) + (X86_##reg)) +#define SEG_EADR(type, seg, reg) type((seg << 4) + (X86_E##reg)) + +#define X86_TF_MASK 0x00000100 +#define X86_IF_MASK 0x00000200 +#define X86_IOPL_MASK 0x00003000 +#define X86_NT_MASK 0x00004000 +#define X86_VM_MASK 0x00020000 +#define X86_AC_MASK 0x00040000 +#define X86_VIF_MASK 0x00080000 /* virtual interrupt flag */ +#define X86_VIP_MASK 0x00100000 /* virtual interrupt pending */ +#define X86_ID_MASK 0x00200000 + +#define MEM_RB(name, addr) (*name->mem->rb)(name, addr) +#define MEM_RW(name, addr) (*name->mem->rw)(name, addr) +#define MEM_RL(name, addr) (*name->mem->rl)(name, addr) +#define MEM_WB(name, addr, val) (*name->mem->wb)(name, addr, val) +#define MEM_WW(name, addr, val) (*name->mem->ww)(name, addr, val) +#define MEM_WL(name, addr, val) (*name->mem->wl)(name, addr, val) + +/* OS dependent functions */ +Bool MapCurrentInt10(xf86Int10InfoPtr pInt); +/* x86 executor related functions */ +Bool xf86Int10ExecSetup(xf86Int10InfoPtr pInt); + +/* int.c */ +extern xf86Int10InfoPtr Int10Current; +int int_handler(xf86Int10InfoPtr pInt); + +/* helper_exec.c */ +int setup_int(xf86Int10InfoPtr pInt); +void finish_int(xf86Int10InfoPtr, int sig); +CARD32 getIntVect(xf86Int10InfoPtr pInt, int num); +void pushw(xf86Int10InfoPtr pInt, CARD16 val); +int run_bios_int(int num, xf86Int10InfoPtr pInt); +void dump_code(xf86Int10InfoPtr pInt); +void dump_registers(xf86Int10InfoPtr pInt); +void stack_trace(xf86Int10InfoPtr pInt); +xf86Int10InfoPtr getInt10Rec(int entityIndex); +CARD8 bios_checksum(CARD8 *start, int size); +void LockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); +void UnlockLegacyVGA(xf86Int10InfoPtr pInt, legacyVGAPtr vga); +#if defined (_PC) +void xf86Int10SaveRestoreBIOSVars(xf86Int10InfoPtr pInt, Bool save); +#endif +int port_rep_inb(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_inw(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_inl(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outb(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outw(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); +int port_rep_outl(xf86Int10InfoPtr pInt, + CARD16 port, CARD32 base, int d_f, CARD32 count); + +CARD8 x_inb(CARD16 port); +CARD16 x_inw(CARD16 port); +void x_outb(CARD16 port, CARD8 val); +void x_outw(CARD16 port, CARD16 val); +CARD32 x_inl(CARD16 port); +void x_outl(CARD16 port, CARD32 val); + +CARD8 Mem_rb(CARD32 addr); +CARD16 Mem_rw(CARD32 addr); +CARD32 Mem_rl(CARD32 addr); +void Mem_wb(CARD32 addr, CARD8 val); +void Mem_ww(CARD32 addr, CARD16 val); +void Mem_wl(CARD32 addr, CARD32 val); + +/* helper_mem.c */ +void setup_int_vect(xf86Int10InfoPtr pInt); +int setup_system_bios(void *base_addr); +void reset_int_vect(xf86Int10InfoPtr pInt); +void set_return_trap(xf86Int10InfoPtr pInt); +void * xf86HandleInt10Options(ScrnInfoPtr pScrn, int entityIndex); +Bool int10skip(void* options); +Bool int10_check_bios(int scrnIndex, int codeSeg, unsigned char* vbiosMem); +Bool initPrimary(void* options); +void xf86int10ParseBiosLocation(void* options, + xf86int10BiosLocationPtr bios); +#ifdef DEBUG +void dprint(unsigned long start, unsigned long size); +#endif + +/* pci.c */ +int mapPciRom(int pciEntity, unsigned char *address); + +#endif /* _INT10_PRIVATE */ +#endif /* _XF86INT10_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86miscproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86miscproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86miscproc.h (revision 51223) @@ -0,0 +1,70 @@ +/* $XFree86: xc/programs/Xserver/Xext/xf86miscproc.h,v 1.5 2002/11/20 04:04:58 dawes Exp $ */ + +/* Prototypes for Pointer/Keyboard functions that the DDX must provide */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XF86MISCPROC_H_ +#define _XF86MISCPROC_H_ + +typedef enum { + MISC_MSE_PROTO, + MISC_MSE_BAUDRATE, + MISC_MSE_SAMPLERATE, + MISC_MSE_RESOLUTION, + MISC_MSE_BUTTONS, + MISC_MSE_EM3BUTTONS, + MISC_MSE_EM3TIMEOUT, + MISC_MSE_CHORDMIDDLE, + MISC_MSE_FLAGS +} MiscExtMseValType; + +typedef enum { + MISC_KBD_TYPE, + MISC_KBD_RATE, + MISC_KBD_DELAY, + MISC_KBD_SERVNUMLOCK +} MiscExtKbdValType; + +typedef enum { + MISC_RET_SUCCESS, + MISC_RET_BADVAL, + MISC_RET_BADMSEPROTO, + MISC_RET_BADBAUDRATE, + MISC_RET_BADFLAGS, + MISC_RET_BADCOMBO, + MISC_RET_BADKBDTYPE, + MISC_RET_NOMODULE +} MiscExtReturn; + +typedef enum { + MISC_POINTER, + MISC_KEYBOARD +} MiscExtStructType; + +#define MISC_MSEFLAG_CLEARDTR 1 +#define MISC_MSEFLAG_CLEARRTS 2 +#define MISC_MSEFLAG_REOPEN 128 + +void XFree86MiscExtensionInit(void); + +Bool MiscExtGetMouseSettings(pointer *mouse, char **devname); +int MiscExtGetMouseValue(pointer mouse, MiscExtMseValType valtype); +Bool MiscExtSetMouseValue(pointer mouse, MiscExtMseValType valtype, int value); +Bool MiscExtGetKbdSettings(pointer *kbd); +int MiscExtGetKbdValue(pointer kbd, MiscExtKbdValType valtype); +Bool MiscExtSetKbdValue(pointer kbd, MiscExtKbdValType valtype, int value); +int MiscExtSetGrabKeysState(ClientPtr client, int enable); +pointer MiscExtCreateStruct(MiscExtStructType mse_or_kbd); +void MiscExtDestroyStruct(pointer structure, MiscExtStructType mse_or_kbd); +MiscExtReturn MiscExtApply(pointer structure, MiscExtStructType mse_or_kbd); +Bool MiscExtSetMouseDevice(pointer mouse, char* device); +Bool MiscExtGetFilePaths(const char **configfile, const char **modulepath, + const char **logfile); +int MiscExtPassMessage(int scrn, const char *msgtype, const char *msgval, + char **retstr); + +#endif + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86pciBus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86pciBus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86pciBus.h (revision 51223) @@ -0,0 +1,99 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86pciBus.h,v 3.10 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 1999-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_PCI_BUS_H +#define _XF86_PCI_BUS_H + +#define PCITAG_SPECIAL pciTag(0xFF,0xFF,0xFF) + +typedef struct { + CARD32 command; + CARD32 base[6]; + CARD32 biosBase; +} pciSave, *pciSavePtr; + +typedef struct { + PCITAG tag; + CARD32 ctrl; +} pciArg; + +typedef struct { + int busnum; + int devnum; + int funcnum; + pciArg arg; + xf86AccessRec ioAccess; + xf86AccessRec io_memAccess; + xf86AccessRec memAccess; + pciSave save; + pciSave restore; + Bool ctrl; +} pciAccRec, *pciAccPtr; + +typedef union { + CARD16 control; +} pciBridgesSave, *pciBridgesSavePtr; + +typedef struct pciBusRec { + int brbus, brdev, brfunc; /* ID of the bridge to this bus */ + int primary, secondary, subordinate; + int subclass; /* bridge type */ + int interface; + resPtr preferred_io; /* I/O range */ + resPtr preferred_mem; /* non-prefetchable memory range */ + resPtr preferred_pmem; /* prefetchable memory range */ + resPtr io; /* for subtractive PCI-PCI bridges */ + resPtr mem; + resPtr pmem; + int brcontrol; /* bridge_control byte */ + struct pciBusRec *next; +} PciBusRec, *PciBusPtr; + +void xf86PciProbe(void); +void ValidatePci(void); +resList GetImplicitPciResources(int entityIndex); +void initPciState(void); +void initPciBusState(void); +void DisablePciAccess(void); +void DisablePciBusAccess(void); +void PciStateEnter(void); +void PciBusStateEnter(void); +void PciStateLeave(void); +void PciBusStateLeave(void); +resPtr ResourceBrokerInitPci(resPtr *osRes); +void pciConvertRange2Host(int entityIndex, resRange *pRange); +void isaConvertRange2Host(resRange *pRange); + +extern pciAccPtr * xf86PciAccInfo; + +#endif /* _XF86_PCI_BUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86sbusBus.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86sbusBus.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86sbusBus.h (revision 51223) @@ -0,0 +1,98 @@ +/* + * SBUS bus-specific declarations + * + * Copyright (C) 2000 Jakub Jelinek (jakub@redhat.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.h,v 3.4 2001/10/28 03:33:19 tsi Exp $ */ + +#ifndef _XF86_SBUSBUS_H +#define _XF86_SBUSBUS_H + +#include "xf86str.h" + +#define SBUS_DEVICE_BW2 0x0001 +#define SBUS_DEVICE_CG2 0x0002 +#define SBUS_DEVICE_CG3 0x0003 +#define SBUS_DEVICE_CG4 0x0004 +#define SBUS_DEVICE_CG6 0x0005 +#define SBUS_DEVICE_CG8 0x0006 +#define SBUS_DEVICE_CG12 0x0007 +#define SBUS_DEVICE_CG14 0x0008 +#define SBUS_DEVICE_LEO 0x0009 +#define SBUS_DEVICE_TCX 0x000a +#define SBUS_DEVICE_FFB 0x000b +#define SBUS_DEVICE_GT 0x000c +#define SBUS_DEVICE_MGX 0x000d + +typedef struct sbus_prom_node { + int node; + /* Because of misdesigned openpromio */ + int cookie[2]; +} sbusPromNode, *sbusPromNodePtr; + +typedef struct sbus_device { + int devId; + int fbNum; + int fd; + int width, height; + sbusPromNode node; + char *descr; + char *device; +} sbusDevice, *sbusDevicePtr; + +extern struct sbus_devtable { + int devId; + int fbType; + char *promName; + char *descr; +} sbusDeviceTable[]; + +void xf86SbusProbe(void); +extern sbusDevicePtr *xf86SbusInfo; + +int xf86MatchSbusInstances(const char *driverName, int sbusDevId, + GDevPtr *devList, int numDevs, DriverPtr drvp, + int **foundEntities); +sbusDevicePtr xf86GetSbusInfoForEntity(int entityIndex); +int xf86GetEntityForSbusInfo(sbusDevicePtr psdp); +void xf86SbusUseBuiltinMode(ScrnInfoPtr pScrn, sbusDevicePtr psdp); +pointer xf86MapSbusMem(sbusDevicePtr psdp, unsigned long offset, + unsigned long size); +void xf86UnmapSbusMem(sbusDevicePtr psdp, pointer addr, unsigned long size); +void xf86SbusHideOsHwCursor(sbusDevicePtr psdp); +void xf86SbusSetOsHwCursorCmap(sbusDevicePtr psdp, int bg, int fg); +Bool xf86SbusHandleColormaps(ScreenPtr pScreen, sbusDevicePtr psdp); + +extern int promRootNode; + +int promGetSibling(int node); +int promGetChild(int node); +char * promGetProperty(const char *prop, int *lenp); +int promGetBool(const char *prop); + +int sparcPromInit(void); +void sparcPromClose(void); +char * sparcPromGetProperty(sbusPromNodePtr pnode, const char *prop, int *lenp); +int sparcPromGetBool(sbusPromNodePtr pnode, const char *prop); +void sparcPromAssignNodes(void); +char * sparcPromNode2Pathname(sbusPromNodePtr pnode); +int sparcPromPathname2Node(const char *pathName); + +#endif /* _XF86_SBUSBUS_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86str.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86str.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86str.h (revision 51223) @@ -0,0 +1,1166 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86str.h,v 1.97 2003/10/30 17:36:56 tsi Exp $ */ + +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +/* + * This file contains definitions of the public XFree86 data structures/types. + * Any data structures that video drivers need to access should go here. + */ + +#ifndef _XF86STR_H +#define _XF86STR_H + +#include "misc.h" +#include "input.h" +#include "scrnintstr.h" +#include "pixmapstr.h" +#include "colormapst.h" +#include "xf86Module.h" +#include "xf86Opt.h" +#include "xf86Pci.h" + +/* + * memType is of the size of the addressable memory (machine size) + * usually unsigned long. + */ +typedef unsigned long memType; + +/* Video mode flags */ + +typedef enum { + V_PHSYNC = 0x0001, + V_NHSYNC = 0x0002, + V_PVSYNC = 0x0004, + V_NVSYNC = 0x0008, + V_INTERLACE = 0x0010, + V_DBLSCAN = 0x0020, + V_CSYNC = 0x0040, + V_PCSYNC = 0x0080, + V_NCSYNC = 0x0100, + V_HSKEW = 0x0200, /* hskew provided */ + V_BCAST = 0x0400, + V_PIXMUX = 0x1000, + V_DBLCLK = 0x2000, + V_CLKDIV2 = 0x4000 +} ModeFlags; + +typedef enum { + INTERLACE_HALVE_V = 0x0001 /* Halve V values for interlacing */ +} CrtcAdjustFlags; + +/* Flags passed to ChipValidMode() */ +typedef enum { + MODECHECK_INITIAL = 0, + MODECHECK_FINAL = 1 +} ModeCheckFlags; + +/* These are possible return values for xf86CheckMode() and ValidMode() */ +typedef enum { + MODE_OK = 0, /* Mode OK */ + MODE_HSYNC, /* hsync out of range */ + MODE_VSYNC, /* vsync out of range */ + MODE_H_ILLEGAL, /* mode has illegal horizontal timings */ + MODE_V_ILLEGAL, /* mode has illegal horizontal timings */ + MODE_BAD_WIDTH, /* requires an unsupported linepitch */ + MODE_NOMODE, /* no mode with a maching name */ + MODE_NO_INTERLACE, /* interlaced mode not supported */ + MODE_NO_DBLESCAN, /* doublescan mode not supported */ + MODE_NO_VSCAN, /* multiscan mode not supported */ + MODE_MEM, /* insufficient video memory */ + MODE_VIRTUAL_X, /* mode width too large for specified virtual size */ + MODE_VIRTUAL_Y, /* mode height too large for specified virtual size */ + MODE_MEM_VIRT, /* insufficient video memory given virtual size */ + MODE_NOCLOCK, /* no fixed clock available */ + MODE_CLOCK_HIGH, /* clock required is too high */ + MODE_CLOCK_LOW, /* clock required is too low */ + MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */ + MODE_BAD_HVALUE, /* horizontal timing was out of range */ + MODE_BAD_VVALUE, /* vertical timing was out of range */ + MODE_BAD_VSCAN, /* VScan value out of range */ + MODE_HSYNC_NARROW, /* horizontal sync too narrow */ + MODE_HSYNC_WIDE, /* horizontal sync too wide */ + MODE_HBLANK_NARROW, /* horizontal blanking too narrow */ + MODE_HBLANK_WIDE, /* horizontal blanking too wide */ + MODE_VSYNC_NARROW, /* vertical sync too narrow */ + MODE_VSYNC_WIDE, /* vertical sync too wide */ + MODE_VBLANK_NARROW, /* vertical blanking too narrow */ + MODE_VBLANK_WIDE, /* vertical blanking too wide */ + MODE_PANEL, /* exceeds panel dimensions */ + MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */ + MODE_ONE_WIDTH, /* only one width is supported */ + MODE_ONE_HEIGHT, /* only one height is supported */ + MODE_ONE_SIZE, /* only one resolution is supported */ + MODE_NO_REDUCED, /* monitor doesn't accept reduced blanking */ + MODE_BAD = -2, /* unspecified reason */ + MODE_ERROR = -1 /* error condition */ +} ModeStatus; + +# define M_T_BUILTIN 0x01 /* built-in mode */ +# define M_T_CLOCK_C (0x02 | M_T_BUILTIN) /* built-in mode - configure clock */ +# define M_T_CRTC_C (0x04 | M_T_BUILTIN) /* built-in mode - configure CRTC */ +# define M_T_CLOCK_CRTC_C (M_T_CLOCK_C | M_T_CRTC_C) + /* built-in mode - configure CRTC and clock */ +# define M_T_DEFAULT 0x10 /* (VESA) default modes */ +# define M_T_USERDEF 0x20 /* One of the modes from the config file */ + +/* Video mode */ +typedef struct _DisplayModeRec { + struct _DisplayModeRec * prev; + struct _DisplayModeRec * next; + char * name; /* identifier for the mode */ + ModeStatus status; + int type; + + /* These are the values that the user sees/provides */ + int Clock; /* pixel clock freq (kHz) */ + int HDisplay; /* horizontal timing */ + int HSyncStart; + int HSyncEnd; + int HTotal; + int HSkew; + int VDisplay; /* vertical timing */ + int VSyncStart; + int VSyncEnd; + int VTotal; + int VScan; + int Flags; + + /* These are the values the hardware uses */ + int ClockIndex; + int SynthClock; /* Actual clock freq to + * be programmed (kHz) */ + int CrtcHDisplay; + int CrtcHBlankStart; + int CrtcHSyncStart; + int CrtcHSyncEnd; + int CrtcHBlankEnd; + int CrtcHTotal; + int CrtcHSkew; + int CrtcVDisplay; + int CrtcVBlankStart; + int CrtcVSyncStart; + int CrtcVSyncEnd; + int CrtcVBlankEnd; + int CrtcVTotal; + Bool CrtcHAdjusted; + Bool CrtcVAdjusted; + int PrivSize; + INT32 * Private; + int PrivFlags; + + float HSync, VRefresh; +} DisplayModeRec, *DisplayModePtr; + +/* The monitor description */ + +#define MAX_HSYNC 8 +#define MAX_VREFRESH 8 + +typedef struct { float hi, lo; } range; + +typedef struct { CARD32 red, green, blue; } rgb; + +typedef struct { float red, green, blue; } Gamma; + +/* The permitted gamma range is 1 / GAMMA_MAX <= g <= GAMMA_MAX */ +#define GAMMA_MAX 10.0 +#define GAMMA_MIN (1.0 / GAMMA_MAX) +#define GAMMA_ZERO (GAMMA_MIN / 100.0) + +typedef struct { + char * id; + char * vendor; + char * model; + int nHsync; + range hsync[MAX_HSYNC]; + int nVrefresh; + range vrefresh[MAX_VREFRESH]; + DisplayModePtr Modes; /* Start of the monitor's mode list */ + DisplayModePtr Last; /* End of the monitor's mode list */ + Gamma gamma; /* Gamma of the monitor */ + int widthmm; + int heightmm; + pointer options; + pointer DDC; + Bool reducedblanking; /* Allow CVT reduced blanking modes? */ +} MonRec, *MonPtr; + +/* the list of clock ranges */ +typedef struct x_ClockRange { + struct x_ClockRange *next; + int minClock; /* (kHz) */ + int maxClock; /* (kHz) */ + int clockIndex; /* -1 for programmable clocks */ + Bool interlaceAllowed; + Bool doubleScanAllowed; + int ClockMulFactor; + int ClockDivFactor; + int PrivFlags; +} ClockRange, *ClockRangePtr; + +/* Need to store the strategy with clockRange for VidMode extension */ +typedef struct x_ClockRanges { + struct x_ClockRanges *next; + int minClock; + int maxClock; + int clockIndex; /* -1 for programmable clocks */ + Bool interlaceAllowed; + Bool doubleScanAllowed; + int ClockMulFactor; + int ClockDivFactor; + int PrivFlags; + int strategy; +} ClockRanges, *ClockRangesPtr; + +/* + * The driverFunc. xorgDriverFuncOp specifies the action driver should + * perform. If requested option is not supported function should return + * FALSE. pointer can be used to pass arguments to the function or + * to return data to the caller. + */ +typedef struct _ScrnInfoRec *ScrnInfoPtr; + +/* do not change order */ +typedef enum { + RR_GET_INFO, + RR_SET_CONFIG, + RR_GET_MODE_MM, + GET_REQUIRED_HW_INTERFACES = 10 +} xorgDriverFuncOp; + +typedef Bool xorgDriverFuncProc (ScrnInfoPtr, xorgDriverFuncOp, + pointer); + +/* RR_GET_INFO, RR_SET_CONFIG */ +typedef struct { + int rotation; + int rate; + int width; + int height; +} xorgRRConfig; + +typedef union { + short RRRotations; + xorgRRConfig RRConfig; +} xorgRRRotation, *xorgRRRotationPtr; + +/* RR_GET_MODE_MM */ +typedef struct { + DisplayModePtr mode; + int virtX; + int virtY; + int mmWidth; + int mmHeight; +} xorgRRModeMM, *xorgRRModeMMPtr; + +/* GET_REQUIRED_HW_INTERFACES */ +#define HW_IO 1 +#define HW_MMIO 2 +#define NEED_IO_ENABLED(x) (x & HW_IO) + +typedef CARD32 xorgHWFlags; + +/* + * The driver list struct. This contains the information required for each + * driver before a ScrnInfoRec has been allocated. + */ +struct _DriverRec; + +typedef struct { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + Bool (*Probe)(struct _DriverRec *drv, int flags); + const OptionInfoRec * (*AvailableOptions)(int chipid, int bustype); + pointer module; + int refCount; +} DriverRec1; + +typedef struct _DriverRec { + int driverVersion; + char * driverName; + void (*Identify)(int flags); + Bool (*Probe)(struct _DriverRec *drv, int flags); + const OptionInfoRec * (*AvailableOptions)(int chipid, int bustype); + pointer module; + int refCount; + xorgDriverFuncProc *driverFunc; +} DriverRec, *DriverPtr; + +/* + * AddDriver flags + */ +#define HaveDriverFuncs 1 + + +#ifdef XFree86LOADER +/* + * The optional module list struct. This allows modules exporting helping + * functions to configuration tools, the Xserver, or any other + * application/module interested in such information. + */ +typedef struct _ModuleInfoRec { + int moduleVersion; + char * moduleName; + pointer module; + int refCount; + const OptionInfoRec * (*AvailableOptions)(void *unused); + pointer unused[8]; /* leave some space for more fields */ +} ModuleInfoRec, *ModuleInfoPtr; +#endif + +/* + * These are the private bus types. New types can be added here. Types + * required for the public interface should be added to xf86str.h, with + * function prototypes added to xf86.h. + */ + +/* Tolerate prior #include */ +#if defined(linux) && defined(_INPUT_H) +#undef BUS_NONE +#undef BUS_ISA +#undef BUS_PCI +#undef BUS_SBUS +#undef BUS_last +#endif + +typedef enum { + BUS_NONE, + BUS_ISA, + BUS_PCI, + BUS_SBUS, + BUS_last /* Keep last */ +} BusType; + +typedef struct { + int bus; + int device; + int func; +} PciBusId; + +typedef struct { + unsigned int dummy; +} IsaBusId; + +typedef struct { + int fbNum; +} SbusBusId; + +typedef struct _bus { + BusType type; + union { + IsaBusId isa; + PciBusId pci; + SbusBusId sbus; + } id; +} BusRec, *BusPtr; + +#define MAXCLOCKS 128 +typedef enum { + DAC_BPP8 = 0, + DAC_BPP16, + DAC_BPP24, + DAC_BPP32, + MAXDACSPEEDS +} DacSpeedIndex; + +typedef struct { + char * identifier; + char * vendor; + char * board; + char * chipset; + char * ramdac; + char * driver; + struct _confscreenrec * myScreenSection; + Bool claimed; + int dacSpeeds[MAXDACSPEEDS]; + int numclocks; + int clock[MAXCLOCKS]; + char * clockchip; + char * busID; + Bool active; + Bool inUse; + int videoRam; + int textClockFreq; + unsigned long BiosBase; /* Base address of video BIOS */ + unsigned long MemBase; /* Frame buffer base address */ + unsigned long IOBase; + int chipID; + int chipRev; + pointer options; + int irq; + int screen; /* For multi-CRTC cards */ +} GDevRec, *GDevPtr; + +typedef int (*FindIsaDevProc)(GDevPtr dev); + +typedef struct { + char * identifier; + char * driver; + pointer commonOptions; + pointer extraOptions; +} IDevRec, *IDevPtr; + +typedef struct { + int vendor; + int chipType; + int chipRev; + int subsysVendor; + int subsysCard; + int bus; + int device; + int func; + int class; + int subclass; + int interface; + memType memBase[6]; + memType ioBase[6]; + int size[6]; + unsigned char type[6]; + memType biosBase; + int biosSize; + pointer thisCard; + Bool validSize; + Bool validate; +} pciVideoRec, *pciVideoPtr; + +typedef struct { + int frameX0; + int frameY0; + int virtualX; + int virtualY; + int depth; + int fbbpp; + rgb weight; + rgb blackColour; + rgb whiteColour; + int defaultVisual; + char ** modes; + pointer options; +} DispRec, *DispPtr; + +typedef struct _confxvportrec { + char * identifier; + pointer options; +} confXvPortRec, *confXvPortPtr; + +typedef struct _confxvadaptrec { + char * identifier; + int numports; + confXvPortPtr ports; + pointer options; +} confXvAdaptorRec, *confXvAdaptorPtr; + +typedef struct _confscreenrec { + char * id; + int screennum; + int defaultdepth; + int defaultbpp; + int defaultfbbpp; + MonPtr monitor; + GDevPtr device; + int numdisplays; + DispPtr displays; + int numxvadaptors; + confXvAdaptorPtr xvadaptors; + pointer options; +} confScreenRec, *confScreenPtr; + +typedef enum { + PosObsolete = -1, + PosAbsolute = 0, + PosRightOf, + PosLeftOf, + PosAbove, + PosBelow, + PosRelative +} PositionType; + +typedef struct _screenlayoutrec { + confScreenPtr screen; + char * topname; + confScreenPtr top; + char * bottomname; + confScreenPtr bottom; + char * leftname; + confScreenPtr left; + char * rightname; + confScreenPtr right; + PositionType where; + int x; + int y; + char * refname; + confScreenPtr refscreen; +} screenLayoutRec, *screenLayoutPtr; + +typedef struct _serverlayoutrec { + char * id; + screenLayoutPtr screens; + GDevPtr inactives; + IDevPtr inputs; + pointer options; +} serverLayoutRec, *serverLayoutPtr; + +typedef struct _confdribufferrec { + int count; + int size; + enum { + XF86DRI_WC_HINT = 0x0001 /* Placeholder: not implemented */ + } flags; +} confDRIBufferRec, *confDRIBufferPtr; + +typedef struct _confdrirec { + int group; + int mode; + int bufs_count; + confDRIBufferRec *bufs; +} confDRIRec, *confDRIPtr; + +/* These values should be adjusted when new fields are added to ScrnInfoRec */ +#define NUM_RESERVED_INTS 16 +#define NUM_RESERVED_POINTERS 15 +#define NUM_RESERVED_FUNCS 11 + +typedef pointer (*funcPointer)(void); + +/* flags for depth 24 pixmap options */ +typedef enum { + Pix24DontCare = 0, + Pix24Use24, + Pix24Use32 +} Pix24Flags; + +/* Power management events: so far we only support APM */ + +typedef enum { + XF86_APM_UNKNOWN = -1, + XF86_APM_SYS_STANDBY, + XF86_APM_SYS_SUSPEND, + XF86_APM_CRITICAL_SUSPEND, + XF86_APM_USER_STANDBY, + XF86_APM_USER_SUSPEND, + XF86_APM_STANDBY_RESUME, + XF86_APM_NORMAL_RESUME, + XF86_APM_CRITICAL_RESUME, + XF86_APM_LOW_BATTERY, + XF86_APM_POWER_STATUS_CHANGE, + XF86_APM_UPDATE_TIME, + XF86_APM_CAPABILITY_CHANGED, + XF86_APM_STANDBY_FAILED, + XF86_APM_SUSPEND_FAILED +} pmEvent; + +typedef enum { + PM_WAIT, + PM_CONTINUE, + PM_FAILED, + PM_NONE +} pmWait; + +/* + * The IO access enabler struct. This contains the address for + * the IOEnable/IODisable funcs for their specific bus along + * with a pointer to data needed by them + */ +typedef struct _AccessRec { + void (*AccessDisable)(void *arg); + void (*AccessEnable)(void *arg); + void *arg; +} xf86AccessRec, *xf86AccessPtr; + +typedef struct { + xf86AccessPtr mem; + xf86AccessPtr io; + xf86AccessPtr io_mem; +} xf86SetAccessFuncRec, *xf86SetAccessFuncPtr; + +/* bus-access-related types */ +typedef enum { + NONE, + IO, + MEM_IO, + MEM +} resType; + +typedef struct _EntityAccessRec { + xf86AccessPtr fallback; + xf86AccessPtr pAccess; + resType rt; + pointer busAcc; + struct _EntityAccessRec *next; +} EntityAccessRec, *EntityAccessPtr; + +typedef struct _CurrAccRec { + EntityAccessPtr pMemAccess; + EntityAccessPtr pIoAccess; +} xf86CurrentAccessRec, *xf86CurrentAccessPtr; + +/* new RAC */ + +/* Resource Type values */ +#define ResNone ((unsigned long)(-1)) + +#define ResMem 0x0001 +#define ResIo 0x0002 +#define ResIrq 0x0003 +#define ResDma 0x0004 +#define ResPciCfg 0x000e /* PCI Configuration space */ +#define ResPhysMask 0x000F + +#define ResExclusive 0x0010 +#define ResShared 0x0020 +#define ResAny 0x0040 +#define ResAccMask 0x0070 +#define ResUnused 0x0080 + +#define ResUnusedOpr 0x0100 +#define ResDisableOpr 0x0200 +#define ResOprMask 0x0300 + +#define ResBlock 0x0400 +#define ResSparse 0x0800 +#define ResExtMask 0x0C00 + +#define ResEstimated 0x001000 +#define ResInit 0x002000 +#define ResBios 0x004000 +#define ResMiscMask 0x00F000 + +#define ResBus 0x010000 +#define ResOverlap 0x020000 + +#if defined(__alpha__) && defined(linux) +# define ResDomain 0x1ff000000ul +#else +# define ResDomain 0xff000000ul +#endif +#define ResTypeMask (ResPhysMask | ResDomain) /* For conflict check */ + +#define ResEnd ResNone + +#define ResExcMemBlock (ResMem | ResExclusive | ResBlock) +#define ResExcIoBlock (ResIo | ResExclusive | ResBlock) +#define ResShrMemBlock (ResMem | ResShared | ResBlock) +#define ResShrIoBlock (ResIo | ResShared | ResBlock) +#define ResExcUusdMemBlock (ResMem | ResExclusive | ResUnused | ResBlock) +#define ResExcUusdIoBlock (ResIo | ResExclusive | ResUnused | ResBlock) +#define ResShrUusdMemBlock (ResMem | ResShared | ResUnused | ResBlock) +#define ResShrUusdIoBlock (ResIo | ResShared | ResUnused | ResBlock) +#define ResExcUusdMemSparse (ResMem | ResExclusive | ResUnused | ResSparse) +#define ResExcUusdIoSparse (ResIo | ResExclusive | ResUnused | ResSparse) +#define ResShrUusdMemSparse (ResMem | ResShared | ResUnused | ResSparse) +#define ResShrUusdIoSparse (ResIo | ResShared | ResUnused | ResSparse) + +#define ResExcMemSparse (ResMem | ResExclusive | ResSparse) +#define ResExcIoSparse (ResIo | ResExclusive | ResSparse) +#define ResShrMemSparse (ResMem | ResShared | ResSparse) +#define ResShrIoSparse (ResIo | ResShared | ResSparse) +#define ResUusdMemSparse (ResMem | ResUnused | ResSparse) +#define ResUusdIoSparse (ResIo | ResUnused | ResSparse) + +#define ResIsMem(r) (((r)->type & ResPhysMask) == ResMem) +#define ResIsIo(r) (((r)->type & ResPhysMask) == ResIo) +#define ResIsExclusive(r) (((r)->type & ResAccMask) == ResExclusive) +#define ResIsShared(r) (((r)->type & ResAccMask) == ResShared) +#define ResIsUnused(r) (((r)->type & ResAccMask) == ResUnused) +#define ResIsBlock(r) (((r)->type & ResExtMask) == ResBlock) +#define ResIsSparse(r) (((r)->type & ResExtMask) == ResSparse) +#define ResIsEstimated(r) (((r)->type & ResMiscMask) == ResEstimated) +#define ResCanOverlap(r) (ResIsEstimated(r) || ((r)->type & ResOverlap)) + +typedef struct { + unsigned long type; /* shared, exclusive, unused etc. */ + memType a; + memType b; +} resRange, *resList; + +#define RANGE_TYPE(type, domain) \ + (((unsigned long)(domain) << 24) | ((type) & ~ResBus)) +#define RANGE(r,u,v,t) {\ + (r).a = (u);\ + (r).b = (v);\ + (r).type = (t);\ + } + +#define rBase a +#define rMask b +#define rBegin a +#define rEnd b + +/* resource record */ +typedef struct _resRec *resPtr; +typedef struct _resRec { + resRange val; + int entityIndex; /* who owns the resource */ + resPtr next; +} resRec; + +#define sparse_base val.rBase +#define sparse_mask val.rMask +#define block_begin val.rBegin +#define block_end val.rEnd +#define res_type val.type + +typedef struct { + int numChipset; + resRange *resList; +} IsaChipsets; + +typedef struct { + /** + * Key used to match this device with its name in an array of + * \c SymTabRec. + */ + int numChipset; + + /** + * This value is quirky. Depending on the driver, it can take on one of + * three meanings. In drivers that have exactly one vendor ID (e.g., + * radeon, mga, i810) the low 16-bits are the device ID. + * + * In drivers that can have multiple vendor IDs (e.g., the glint driver + * can have either 3dlabs' ID or TI's ID, the i740 driver can have either + * Intel's ID or Real3D's ID, etc.) the low 16-bits are the device ID and + * the high 16-bits are the vendor ID. + * + * In drivers that don't have a specific vendor (e.g., vga) contains the + * device ID for either the generic VGA or generic 8514 devices. This + * turns out to be the same as the subclass and programming interface + * value (e.g., the full 24-bit class for the VGA device is 0x030000 (or + * 0x000101) and for 8514 is 0x030001). + */ + int PCIid; + + /** + * Resources associated with this type of device. + */ + resRange *resList; +} PciChipsets; + +/* Entity properties */ +typedef void (*EntityProc)(int entityIndex,pointer private); + +typedef struct _entityInfo { + int index; + BusRec location; + int chipset; + Bool active; + resPtr resources; + GDevPtr device; + DriverPtr driver; +} EntityInfoRec, *EntityInfoPtr; + +/* server states */ + +typedef enum { + SETUP, + OPERATING +} xf86State; + +typedef enum { + NOTIFY_SETUP_TRANSITION, + NOTIFY_SETUP, + NOTIFY_OPERATING, + NOTIFY_OPERATING_TRANSITION, + NOTIFY_ENABLE, + NOTIFY_ENTER, + NOTIFY_LEAVE +} xf86NotifyState; + +typedef void (*xf86StateChangeNotificationCallbackFunc)(xf86NotifyState state,pointer); + +/* DGA */ + +typedef struct { + int num; /* A unique identifier for the mode (num > 0) */ + DisplayModePtr mode; + int flags; /* DGA_CONCURRENT_ACCESS, etc... */ + int imageWidth; /* linear accessible portion (pixels) */ + int imageHeight; + int pixmapWidth; /* Xlib accessible portion (pixels) */ + int pixmapHeight; /* both fields ignored if no concurrent access */ + int bytesPerScanline; + int byteOrder; /* MSBFirst, LSBFirst */ + int depth; + int bitsPerPixel; + unsigned long red_mask; + unsigned long green_mask; + unsigned long blue_mask; + short visualClass; + int viewportWidth; + int viewportHeight; + int xViewportStep; /* viewport position granularity */ + int yViewportStep; + int maxViewportX; /* max viewport origin */ + int maxViewportY; + int viewportFlags; /* types of page flipping possible */ + int offset; /* offset into physical memory */ + unsigned char *address; /* server's mapped framebuffer */ + int reserved1; + int reserved2; +} DGAModeRec, *DGAModePtr; + +typedef struct { + DGAModePtr mode; + PixmapPtr pPix; +} DGADeviceRec, *DGADevicePtr; + +/* + * Flags for driver Probe() functions. + */ +#define PROBE_DEFAULT 0x00 +#define PROBE_DETECT 0x01 +#define PROBE_TRYHARD 0x02 + +/* + * Driver entry point types + */ + +typedef Bool xf86ProbeProc (DriverPtr, int); +typedef Bool xf86PreInitProc (ScrnInfoPtr, int); +typedef Bool xf86ScreenInitProc (int, ScreenPtr, int, char**); +typedef Bool xf86SwitchModeProc (int, DisplayModePtr, int); +typedef void xf86AdjustFrameProc (int, int, int, int); +typedef Bool xf86EnterVTProc (int, int); +typedef void xf86LeaveVTProc (int, int); +typedef void xf86FreeScreenProc (int, int); +typedef ModeStatus xf86ValidModeProc (int, DisplayModePtr, Bool, int); +typedef void xf86EnableDisableFBAccessProc(int, Bool); +typedef int xf86SetDGAModeProc (int, int, DGADevicePtr); +typedef int xf86ChangeGammaProc (int, Gamma); +typedef void xf86PointerMovedProc (int, int, int); +typedef Bool xf86PMEventProc (int, pmEvent, Bool); +typedef int xf86HandleMessageProc (int, const char*, const char*, char**); +typedef void xf86DPMSSetProc (ScrnInfoPtr, int, int); +typedef void xf86LoadPaletteProc (ScrnInfoPtr, int, int *, LOCO *, VisualPtr); +typedef void xf86SetOverscanProc (ScrnInfoPtr, int); + + +/* + * ScrnInfoRec + * + * There is one of these for each screen, and it holds all the screen-specific + * information. + * + * Note: the size and layout must be kept the same across versions. New + * fields are to be added in place of the "reserved*" fields. No fields + * are to be dependent on compile-time defines. + */ + + +typedef struct _ScrnInfoRec { + int driverVersion; + char * driverName; /* canonical name used in */ + /* the config file */ + ScreenPtr pScreen; /* Pointer to the ScreenRec */ + int scrnIndex; /* Number of this screen */ + Bool configured; /* Is this screen valid */ + int origIndex; /* initial number assigned to + * this screen before + * finalising the number of + * available screens */ + + /* Display-wide screenInfo values needed by this screen */ + int imageByteOrder; + int bitmapScanlineUnit; + int bitmapScanlinePad; + int bitmapBitOrder; + int numFormats; + PixmapFormatRec formats[MAXFORMATS]; + PixmapFormatRec fbFormat; + + int bitsPerPixel; /* fb bpp */ + Pix24Flags pixmap24; /* pixmap pref for depth 24 */ + int depth; /* depth of default visual */ + MessageType depthFrom; /* set from config? */ + MessageType bitsPerPixelFrom; /* set from config? */ + rgb weight; /* r/g/b weights */ + rgb mask; /* rgb masks */ + rgb offset; /* rgb offsets */ + int rgbBits; /* Number of bits in r/g/b */ + Gamma gamma; /* Gamma of the monitor */ + int defaultVisual; /* default visual class */ + int maxHValue; /* max horizontal timing */ + int maxVValue; /* max vertical timing value */ + int virtualX; /* Virtual width */ + int virtualY; /* Virtual height */ + int xInc; /* Horizontal timing increment */ + MessageType virtualFrom; /* set from config? */ + int displayWidth; /* memory pitch */ + int frameX0; /* viewport position */ + int frameY0; + int frameX1; + int frameY1; + int zoomLocked; /* Disallow mode changes */ + DisplayModePtr modePool; /* list of compatible modes */ + DisplayModePtr modes; /* list of actual modes */ + DisplayModePtr currentMode; /* current mode + * This was previously + * overloaded with the modes + * field, which is a pointer + * into a circular list */ + confScreenPtr confScreen; /* Screen config info */ + MonPtr monitor; /* Monitor information */ + DispPtr display; /* Display information */ + int * entityList; /* List of device entities */ + int numEntities; + int widthmm; /* physical display dimensions + * in mm */ + int heightmm; + int xDpi; /* width DPI */ + int yDpi; /* height DPI */ + char * name; /* Name to prefix messages */ + pointer driverPrivate; /* Driver private area */ + DevUnion * privates; /* Other privates can hook in + * here */ + DriverPtr drv; /* xf86DriverList[] entry */ + pointer module; /* Pointer to module head */ + int colorKey; + int overlayFlags; + + /* Some of these may be moved out of here into the driver private area */ + + char * chipset; /* chipset name */ + char * ramdac; /* ramdac name */ + char * clockchip; /* clock name */ + Bool progClock; /* clock is programmable */ + int numClocks; /* number of clocks */ + int clock[MAXCLOCKS]; /* list of clock frequencies */ + int videoRam; /* amount of video ram (kb) */ + unsigned long biosBase; /* Base address of video BIOS */ + unsigned long memPhysBase; /* Physical address of FB */ + unsigned long fbOffset; /* Offset of FB in the above */ + IOADDRESS domainIOBase; /* Domain I/O base address */ + int memClk; /* memory clock */ + int textClockFreq; /* clock of text mode */ + Bool flipPixels; /* swap default black/white */ + pointer options; + + int chipID; + int chipRev; + int racMemFlags; + int racIoFlags; + pointer access; + xf86CurrentAccessPtr CurrentAccess; + resType resourceType; + pointer busAccess; + + /* Allow screens to be enabled/disabled individually */ + Bool vtSema; + DevUnion pixmapPrivate; /* saved devPrivate from pixmap */ + + /* hw cursor moves at SIGIO time */ + Bool silkenMouse; + + /* Storage for clockRanges and adjustFlags for use with the VidMode ext */ + ClockRangesPtr clockRanges; + int adjustFlags; + + /* + * These can be used when the minor ABI version is incremented. + * The NUM_* parameters must be reduced appropriately to keep the + * structure size and alignment unchanged. + */ + int reservedInt[NUM_RESERVED_INTS]; + + int * entityInstanceList; + pointer reservedPtr[NUM_RESERVED_POINTERS]; + + /* + * Driver entry points. + * + */ + + xf86ProbeProc *Probe; + xf86PreInitProc *PreInit; + xf86ScreenInitProc *ScreenInit; + xf86SwitchModeProc *SwitchMode; + xf86AdjustFrameProc *AdjustFrame; + xf86EnterVTProc *EnterVT; + xf86LeaveVTProc *LeaveVT; + xf86FreeScreenProc *FreeScreen; + xf86ValidModeProc *ValidMode; + xf86EnableDisableFBAccessProc *EnableDisableFBAccess; + xf86SetDGAModeProc *SetDGAMode; + xf86ChangeGammaProc *ChangeGamma; + xf86PointerMovedProc *PointerMoved; + xf86PMEventProc *PMEvent; + xf86HandleMessageProc *HandleMessage; + xf86DPMSSetProc *DPMSSet; + xf86LoadPaletteProc *LoadPalette; + xf86SetOverscanProc *SetOverscan; + xorgDriverFuncProc *DriverFunc; + + /* + * This can be used when the minor ABI version is incremented. + * The NUM_* parameter must be reduced appropriately to keep the + * structure size and alignment unchanged. + */ + funcPointer reservedFuncs[NUM_RESERVED_FUNCS]; + +} ScrnInfoRec; + + +typedef struct { + Bool (*OpenFramebuffer)( + ScrnInfoPtr pScrn, + char **name, + unsigned char **mem, + int *size, + int *offset, + int *extra + ); + void (*CloseFramebuffer)(ScrnInfoPtr pScrn); + Bool (*SetMode)(ScrnInfoPtr pScrn, DGAModePtr pMode); + void (*SetViewport)(ScrnInfoPtr pScrn, int x, int y, int flags); + int (*GetViewport)(ScrnInfoPtr pScrn); + void (*Sync)(ScrnInfoPtr); + void (*FillRect)( + ScrnInfoPtr pScrn, + int x, int y, int w, int h, + unsigned long color + ); + void (*BlitRect)( + ScrnInfoPtr pScrn, + int srcx, int srcy, + int w, int h, + int dstx, int dsty + ); + void (*BlitTransRect)( + ScrnInfoPtr pScrn, + int srcx, int srcy, + int w, int h, + int dstx, int dsty, + unsigned long color + ); +} DGAFunctionRec, *DGAFunctionPtr; + +typedef struct { + int token; /* id of the token */ + const char * name; /* token name */ +} SymTabRec, *SymTabPtr; + +/* flags for xf86LookupMode */ +typedef enum { + LOOKUP_DEFAULT = 0, /* Use default mode lookup method */ + LOOKUP_BEST_REFRESH, /* Pick modes with best refresh */ + LOOKUP_CLOSEST_CLOCK, /* Pick modes with the closest clock */ + LOOKUP_LIST_ORDER, /* Pick first useful mode in list */ + LOOKUP_CLKDIV2 = 0x0100, /* Allow half clocks */ + LOOKUP_OPTIONAL_TOLERANCES = 0x0200 /* Allow missing hsync/vrefresh */ +} LookupModeFlags; + +#define NoDepth24Support 0x00 +#define Support24bppFb 0x01 /* 24bpp framebuffer supported */ +#define Support32bppFb 0x02 /* 32bpp framebuffer supported */ +#define SupportConvert24to32 0x04 /* Can convert 24bpp pixmap to 32bpp */ +#define SupportConvert32to24 0x08 /* Can convert 32bpp pixmap to 24bpp */ +#define PreferConvert24to32 0x10 /* prefer 24bpp pixmap to 32bpp conv */ +#define PreferConvert32to24 0x20 /* prefer 32bpp pixmap to 24bpp conv */ + + +/* For DPMS */ +typedef void (*DPMSSetProcPtr)(ScrnInfoPtr, int, int); + +/* Input handler proc */ +typedef void (*InputHandlerProc)(int fd, pointer data); + +/* These are used by xf86GetClocks */ +#define CLK_REG_SAVE -1 +#define CLK_REG_RESTORE -2 + +/* xf86Debug.c */ +#ifdef BUILDDEBUG +typedef struct { + long sec; + long usec; +} xf86TsRec, *xf86TsPtr; +#endif + +/* + * misc constants + */ +#define INTERLACE_REFRESH_WEIGHT 1.5 +#define SYNC_TOLERANCE 0.01 /* 1 percent */ +#define CLOCK_TOLERANCE 2000 /* Clock matching tolerance (2MHz) */ + + +#define OVERLAY_8_32_DUALFB 0x00000001 +#define OVERLAY_8_24_DUALFB 0x00000002 +#define OVERLAY_8_16_DUALFB 0x00000004 +#define OVERLAY_8_32_PLANAR 0x00000008 + +#if 0 +#define LD_RESOLV_IFDONE 0 /* only check if no more + delays pending */ +#define LD_RESOLV_NOW 1 /* finish one delay step */ +#define LD_RESOLV_FORCE 2 /* force checking... */ +#endif + +/* Values of xf86Info.mouseFlags */ +#define MF_CLEAR_DTR 1 +#define MF_CLEAR_RTS 2 + +/* Action Events */ +typedef enum { + ACTION_TERMINATE = 0, /* Terminate Server */ + ACTION_NEXT_MODE = 10, /* Switch to next video mode */ + ACTION_PREV_MODE, + ACTION_DISABLEGRAB = 20, /* Cancel server/pointer/kbd grabs */ + ACTION_CLOSECLIENT, /* Kill client holding grab */ + ACTION_SWITCHSCREEN = 100, /* VT switch */ + ACTION_SWITCHSCREEN_NEXT, + ACTION_SWITCHSCREEN_PREV, + ACTION_MESSAGE = 9999 /* Generic message passing */ +} ActionEvent; + +/* xf86Versions.c */ +/* + * Never change existing values, and always assign values explicitly. + * NUM_BUILTIN_IFS must always be the last entry. + */ +typedef enum { + BUILTIN_IF_OSMOUSE = 0, + BUILTIN_IF_OSKBD = 1, + NUM_BUILTIN_IFS +} BuiltinInterface; + +/* + * These are intentionally the same as the module version macros. + * It is possible to register a module as providing a specific interface, + * in which case the module's version is used. This feature isn't + * really ready for use yet though. + */ + +#define BUILTIN_INTERFACE_VERSION_NUMERIC(maj, min, patch) \ + ((((maj) & 0xFF) << 24) | (((min) & 0xFF) << 16) | (patch & 0xFFFF)) +#define GET_BUILTIN_INTERFACE_MAJOR_VERSION(vers) (((vers) >> 24) & 0xFF) +#define GET_BUILTIN_INTERFACE_MINOR_VERSION(vers) (((vers) >> 16) & 0xFF) +#define GET_BUILTIN_INTERFACE_PATCH_VERSION(vers) ((vers) & 0xFFFF) + +#endif /* _XF86STR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86tokens.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86tokens.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86tokens.h (revision 51223) @@ -0,0 +1,280 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/parser/xf86tokens.h,v 1.20 2003/08/24 17:37:09 dawes Exp $ */ +/* + * + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* + * Copyright (c) 1997-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _xf86_tokens_h +#define _xf86_tokens_h + +/* Undefine symbols that some OSs might define */ +#undef IOBASE + +/* + * Each token should have a unique value regardless of the section + * it is used in. + */ + +typedef enum { + /* errno-style tokens */ + EOF_TOKEN = -4, + LOCK_TOKEN = -3, + ERROR_TOKEN = -2, + + /* value type tokens */ + NUMBER = 1, + STRING, + + /* Tokens that can appear in many sections */ + SECTION, + SUBSECTION, + ENDSECTION, + ENDSUBSECTION, + IDENTIFIER, + VENDOR, + DASH, + COMMA, + OPTION, + COMMENT, + + /* Frequency units */ + HRZ, + KHZ, + MHZ, + + /* File tokens */ + FONTPATH, + RGBPATH, + MODULEPATH, + INPUTDEVICES, + LOGFILEPATH, + + /* Server Flag tokens. These are deprecated in favour of generic Options */ + NOTRAPSIGNALS, + DONTZAP, + DONTZOOM, + DISABLEVIDMODE, + ALLOWNONLOCAL, + DISABLEMODINDEV, + MODINDEVALLOWNONLOCAL, + ALLOWMOUSEOPENFAIL, + BLANKTIME, + STANDBYTIME, + SUSPENDTIME, + OFFTIME, + DEFAULTLAYOUT, + + /* Monitor tokens */ + MODEL, + MODELINE, + DISPLAYSIZE, + HORIZSYNC, + VERTREFRESH, + MODE, + GAMMA, + USEMODES, + + /* Modes tokens */ + /* no new ones */ + + /* Mode tokens */ + DOTCLOCK, + HTIMINGS, + VTIMINGS, + FLAGS, + HSKEW, + BCAST, + VSCAN, + ENDMODE, + + /* Screen tokens */ + OBSDRIVER, + MDEVICE, + MONITOR, + SCREENNO, + DEFAULTDEPTH, + DEFAULTBPP, + DEFAULTFBBPP, + + /* VideoAdaptor tokens */ + VIDEOADAPTOR, + + /* Mode timing tokens */ + TT_INTERLACE, + TT_PHSYNC, + TT_NHSYNC, + TT_PVSYNC, + TT_NVSYNC, + TT_CSYNC, + TT_PCSYNC, + TT_NCSYNC, + TT_DBLSCAN, + TT_HSKEW, + TT_BCAST, + TT_VSCAN, + TT_CUSTOM, + + /* Module tokens */ + LOAD, + LOAD_DRIVER, + + /* Device tokens */ + DRIVER, + CHIPSET, + CLOCKS, + VIDEORAM, + BOARD, + IOBASE, + RAMDAC, + DACSPEED, + BIOSBASE, + MEMBASE, + CLOCKCHIP, + CHIPID, + CHIPREV, + CARD, + BUSID, + TEXTCLOCKFRQ, + IRQ, + + /* Keyboard tokens */ + AUTOREPEAT, + XLEDS, + KPROTOCOL, + XKBKEYMAP, + XKBCOMPAT, + XKBTYPES, + XKBKEYCODES, + XKBGEOMETRY, + XKBSYMBOLS, + XKBDISABLE, + PANIX106, + XKBRULES, + XKBMODEL, + XKBLAYOUT, + XKBVARIANT, + XKBOPTIONS, + /* The next two have become ServerFlags options */ + VTINIT, + VTSYSREQ, + /* Obsolete keyboard tokens */ + SERVERNUM, + LEFTALT, + RIGHTALT, + SCROLLLOCK_TOK, + RIGHTCTL, + /* arguments for the above obsolete tokens */ + CONF_KM_META, + CONF_KM_COMPOSE, + CONF_KM_MODESHIFT, + CONF_KM_MODELOCK, + CONF_KM_SCROLLLOCK, + CONF_KM_CONTROL, + + /* Pointer tokens */ + EMULATE3, + BAUDRATE, + SAMPLERATE, + PRESOLUTION, + CLEARDTR, + CLEARRTS, + CHORDMIDDLE, + PROTOCOL, + PDEVICE, + EM3TIMEOUT, + DEVICE_NAME, + ALWAYSCORE, + PBUTTONS, + ZAXISMAPPING, + + /* Pointer Z axis mapping tokens */ + XAXIS, + YAXIS, + + /* Display tokens */ + MODES, + VIEWPORT, + VIRTUAL, + VISUAL, + BLACK_TOK, + WHITE_TOK, + DEPTH, + BPP, + WEIGHT, + + /* Layout Tokens */ + SCREEN, + INACTIVE, + INPUTDEVICE, + + /* Adjaceny Tokens */ + RIGHTOF, + LEFTOF, + ABOVE, + BELOW, + RELATIVE, + ABSOLUTE, + + /* Vendor Tokens */ + VENDORNAME, + + /* DRI Tokens */ + GROUP, + BUFFERS +} ParserTokens; + +#endif /* _xf86_tokens_h */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86x86emu.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86x86emu.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86x86emu.h (revision 51223) @@ -0,0 +1,55 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/int10/xf86x86emu.h,v 1.1 2000/01/23 04:44:35 dawes Exp $ */ +/* + * XFree86 int10 module + * execute BIOS int 10h calls in x86 real mode environment + * Copyright 1999 Egbert Eich + */ +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef XF86X86EMU_H_ +#define XF86X86EMU_H_ +#include + +#define M _X86EMU_env + +#define X86_EAX M.x86.R_EAX +#define X86_EBX M.x86.R_EBX +#define X86_ECX M.x86.R_ECX +#define X86_EDX M.x86.R_EDX +#define X86_ESI M.x86.R_ESI +#define X86_EDI M.x86.R_EDI +#define X86_EBP M.x86.R_EBP +#define X86_EIP M.x86.R_EIP +#define X86_ESP M.x86.R_ESP +#define X86_EFLAGS M.x86.R_EFLG + +#define X86_FLAGS M.x86.R_FLG +#define X86_AX M.x86.R_AX +#define X86_BX M.x86.R_BX +#define X86_CX M.x86.R_CX +#define X86_DX M.x86.R_DX +#define X86_SI M.x86.R_SI +#define X86_DI M.x86.R_DI +#define X86_BP M.x86.R_BP +#define X86_IP M.x86.R_IP +#define X86_SP M.x86.R_SP +#define X86_CS M.x86.R_CS +#define X86_DS M.x86.R_DS +#define X86_ES M.x86.R_ES +#define X86_SS M.x86.R_SS +#define X86_FS M.x86.R_FS +#define X86_GS M.x86.R_GS + +#define X86_AL M.x86.R_AL +#define X86_BL M.x86.R_BL +#define X86_CL M.x86.R_CL +#define X86_DL M.x86.R_DL + +#define X86_AH M.x86.R_AH +#define X86_BH M.x86.R_BH +#define X86_CH M.x86.R_CH +#define X86_DH M.x86.R_DH + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xv.h (revision 51223) @@ -0,0 +1,271 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xv.h,v 1.25 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 1998-2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XV_H_ +#define _XF86XV_H_ + +#include "xvdix.h" +#include "xf86str.h" + +#define VIDEO_NO_CLIPPING 0x00000001 +#define VIDEO_INVERT_CLIPLIST 0x00000002 +#define VIDEO_OVERLAID_IMAGES 0x00000004 +#define VIDEO_OVERLAID_STILLS 0x00000008 +#define VIDEO_CLIP_TO_VIEWPORT 0x00000010 + +typedef struct { + int id; + int type; + int byte_order; + unsigned char guid[16]; + int bits_per_pixel; + int format; + int num_planes; + + /* for RGB formats only */ + int depth; + unsigned int red_mask; + unsigned int green_mask; + unsigned int blue_mask; + + /* for YUV formats only */ + unsigned int y_sample_bits; + unsigned int u_sample_bits; + unsigned int v_sample_bits; + unsigned int horz_y_period; + unsigned int horz_u_period; + unsigned int horz_v_period; + unsigned int vert_y_period; + unsigned int vert_u_period; + unsigned int vert_v_period; + char component_order[32]; + int scanline_order; +} XF86ImageRec, *XF86ImagePtr; + + +typedef struct { + ScrnInfoPtr pScrn; + int id; + unsigned short width, height; + int *pitches; /* bytes */ + int *offsets; /* in bytes from start of framebuffer */ + DevUnion devPrivate; +} XF86SurfaceRec, *XF86SurfacePtr; + + +typedef int (* PutVideoFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef int (* PutStillFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef int (* GetVideoFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef int (* GetStillFuncPtr)( ScrnInfoPtr pScrn, + short vid_x, short vid_y, short drw_x, short drw_y, + short vid_w, short vid_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef void (* StopVideoFuncPtr)(ScrnInfoPtr pScrn, pointer data, Bool Exit); +typedef int (* SetPortAttributeFuncPtr)(ScrnInfoPtr pScrn, Atom attribute, + INT32 value, pointer data); +typedef int (* GetPortAttributeFuncPtr)(ScrnInfoPtr pScrn, Atom attribute, + INT32 *value, pointer data); +typedef void (* QueryBestSizeFuncPtr)(ScrnInfoPtr pScrn, Bool motion, + short vid_w, short vid_h, short drw_w, short drw_h, + unsigned int *p_w, unsigned int *p_h, pointer data); +typedef int (* PutImageFuncPtr)( ScrnInfoPtr pScrn, + short src_x, short src_y, short drw_x, short drw_y, + short src_w, short src_h, short drw_w, short drw_h, + int image, unsigned char* buf, short width, short height, Bool Sync, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef int (* ReputImageFuncPtr)( ScrnInfoPtr pScrn, short drw_x, short drw_y, + RegionPtr clipBoxes, pointer data, DrawablePtr pDraw ); +typedef int (*QueryImageAttributesFuncPtr)(ScrnInfoPtr pScrn, + int image, unsigned short *width, unsigned short *height, + int *pitches, int *offsets); + +typedef enum { + XV_OFF, + XV_PENDING, + XV_ON +} XvStatus; + +/*** this is what the driver needs to fill out ***/ + +typedef struct { + int id; + char *name; + unsigned short width, height; + XvRationalRec rate; +} XF86VideoEncodingRec, *XF86VideoEncodingPtr; + +typedef struct { + char depth; + short class; +} XF86VideoFormatRec, *XF86VideoFormatPtr; + +typedef struct { + int flags; + int min_value; + int max_value; + char *name; +} XF86AttributeRec, *XF86AttributePtr; + +typedef struct { + unsigned int type; + int flags; + char *name; + int nEncodings; + XF86VideoEncodingPtr pEncodings; + int nFormats; + XF86VideoFormatPtr pFormats; + int nPorts; + DevUnion *pPortPrivates; + int nAttributes; + XF86AttributePtr pAttributes; + int nImages; + XF86ImagePtr pImages; + PutVideoFuncPtr PutVideo; + PutStillFuncPtr PutStill; + GetVideoFuncPtr GetVideo; + GetStillFuncPtr GetStill; + StopVideoFuncPtr StopVideo; + SetPortAttributeFuncPtr SetPortAttribute; + GetPortAttributeFuncPtr GetPortAttribute; + QueryBestSizeFuncPtr QueryBestSize; + PutImageFuncPtr PutImage; + ReputImageFuncPtr ReputImage; + QueryImageAttributesFuncPtr QueryImageAttributes; +} XF86VideoAdaptorRec, *XF86VideoAdaptorPtr; + +typedef struct { + XF86ImagePtr image; + int flags; + int (*alloc_surface)(ScrnInfoPtr pScrn, + int id, + unsigned short width, + unsigned short height, + XF86SurfacePtr surface); + int (*free_surface)(XF86SurfacePtr surface); + int (*display) (XF86SurfacePtr surface, + short vid_x, short vid_y, + short drw_x, short drw_y, + short vid_w, short vid_h, + short drw_w, short drw_h, + RegionPtr clipBoxes); + int (*stop) (XF86SurfacePtr surface); + int (*getAttribute) (ScrnInfoPtr pScrn, Atom attr, INT32 *value); + int (*setAttribute) (ScrnInfoPtr pScrn, Atom attr, INT32 value); + int max_width; + int max_height; + int num_attributes; + XF86AttributePtr attributes; +} XF86OffscreenImageRec, *XF86OffscreenImagePtr; + +Bool +xf86XVScreenInit( + ScreenPtr pScreen, + XF86VideoAdaptorPtr *Adaptors, + int num +); + +typedef int (* xf86XVInitGenericAdaptorPtr)(ScrnInfoPtr pScrn, + XF86VideoAdaptorPtr **Adaptors); + +int +xf86XVRegisterGenericAdaptorDriver( + xf86XVInitGenericAdaptorPtr InitFunc +); + +int +xf86XVListGenericAdaptors( + ScrnInfoPtr pScrn, + XF86VideoAdaptorPtr **Adaptors +); + +Bool +xf86XVRegisterOffscreenImages( + ScreenPtr pScreen, + XF86OffscreenImagePtr images, + int num +); + +XF86OffscreenImagePtr +xf86XVQueryOffscreenImages( + ScreenPtr pScreen, + int *num +); + +XF86VideoAdaptorPtr xf86XVAllocateVideoAdaptorRec(ScrnInfoPtr pScrn); + +void xf86XVFreeVideoAdaptorRec(XF86VideoAdaptorPtr ptr); + +void +xf86XVFillKeyHelper (ScreenPtr pScreen, CARD32 key, RegionPtr clipboxes); + +Bool +xf86XVClipVideoHelper( + BoxPtr dst, + INT32 *xa, + INT32 *xb, + INT32 *ya, + INT32 *yb, + RegionPtr reg, + INT32 width, + INT32 height +); + +void +xf86XVCopyYUV12ToPacked( + const void *srcy, + const void *srcv, + const void *srcu, + void *dst, + int srcPitchy, + int srcPitchuv, + int dstPitch, + int h, + int w +); + +void +xf86XVCopyPacked( + const void *src, + void *dst, + int srcPitch, + int dstPitch, + int h, + int w +); + +#endif /* _XF86XV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvmc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvmc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvmc.h (revision 51223) @@ -0,0 +1,164 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xvmc.h,v 1.7 2003/10/08 22:31:59 mvojkovi Exp $ */ + +/* + * Copyright (c) 2001 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XVMC_H +#define _XF86XVMC_H + +#include "xvmcext.h" +#include "xf86xv.h" + +typedef struct { + int num_xvimages; + int *xvimage_ids; /* reference the subpictures in the XF86MCAdaptorRec */ +} XF86MCImageIDList; + +typedef struct { + int surface_type_id; /* Driver generated. Must be unique on the port */ + int chroma_format; + int color_description; /* no longer used */ + unsigned short max_width; + unsigned short max_height; + unsigned short subpicture_max_width; + unsigned short subpicture_max_height; + int mc_type; + int flags; + XF86MCImageIDList *compatible_subpictures; /* can be null, if none */ +} XF86MCSurfaceInfoRec, *XF86MCSurfaceInfoPtr; + + +/* + xf86XvMCCreateContextProc + + DIX will fill everything out in the context except the driver_priv. + The port_priv holds the private data specified for the port when + Xv was initialized by the driver. + The driver may store whatever it wants in driver_priv and edit + the width, height and flags. If the driver wants to return something + to the client it can allocate space in priv and specify the number + of 32 bit words in num_priv. This must be dynamically allocated + space because DIX will free it after it passes it to the client. +*/ + + +typedef int (*xf86XvMCCreateContextProcPtr) ( + ScrnInfoPtr pScrn, + XvMCContextPtr context, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroyContextProcPtr) ( + ScrnInfoPtr pScrn, + XvMCContextPtr context +); + +/* + xf86XvMCCreateSurfaceProc + + DIX will fill everything out in the surface except the driver_priv. + The driver may store whatever it wants in driver_priv. The driver + may pass data back to the client in the same manner as the + xf86XvMCCreateContextProc. +*/ + + +typedef int (*xf86XvMCCreateSurfaceProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSurfacePtr surface, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroySurfaceProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSurfacePtr surface +); + +/* + xf86XvMCCreateSubpictureProc + + DIX will fill everything out in the subpicture except the driver_priv, + num_palette_entries, entry_bytes and component_order. The driver may + store whatever it wants in driver_priv and edit the width and height. + If it is a paletted subpicture the driver needs to fill out the + num_palette_entries, entry_bytes and component_order. These are + not communicated to the client until the time the surface is + created. + + The driver may pass data back to the client in the same manner as the + xf86XvMCCreateContextProc. +*/ + + +typedef int (*xf86XvMCCreateSubpictureProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSubpicturePtr subpicture, + int *num_priv, + CARD32 **priv +); + +typedef void (*xf86XvMCDestroySubpictureProcPtr) ( + ScrnInfoPtr pScrn, + XvMCSubpicturePtr subpicture +); + + +typedef struct { + char *name; + int num_surfaces; + XF86MCSurfaceInfoPtr *surfaces; + int num_subpictures; + XF86ImagePtr *subpictures; + xf86XvMCCreateContextProcPtr CreateContext; + xf86XvMCDestroyContextProcPtr DestroyContext; + xf86XvMCCreateSurfaceProcPtr CreateSurface; + xf86XvMCDestroySurfaceProcPtr DestroySurface; + xf86XvMCCreateSubpictureProcPtr CreateSubpicture; + xf86XvMCDestroySubpictureProcPtr DestroySubpicture; +} XF86MCAdaptorRec, *XF86MCAdaptorPtr; + +/* + xf86XvMCScreenInit + + Unlike Xv, the adaptor data is not copied from this structure. + This structure's data is used so it must stick around for the + life of the server. Note that it's an array of pointers not + an array of structures. +*/ + +Bool xf86XvMCScreenInit( + ScreenPtr pScreen, + int num_adaptors, + XF86MCAdaptorPtr *adaptors +); + +XF86MCAdaptorPtr xf86XvMCCreateAdaptorRec (void); +void xf86XvMCDestroyAdaptorRec(XF86MCAdaptorPtr adaptor); + +#endif /* _XF86XVMC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvpriv.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvpriv.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xf86xvpriv.h (revision 51223) @@ -0,0 +1,86 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86xvpriv.h,v 1.2 2003/08/24 17:36:56 dawes Exp $ */ + +/* + * Copyright (c) 2003 by The XFree86 Project, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef _XF86XVPRIV_H_ +#define _XF86XVPRIV_H_ + +#include "xf86xv.h" + +/*** These are DDX layer privates ***/ + +extern int XF86XvScreenIndex; + +typedef struct { + DestroyWindowProcPtr DestroyWindow; + ClipNotifyProcPtr ClipNotify; + WindowExposuresProcPtr WindowExposures; + void (*AdjustFrame)(int, int, int, int); + Bool (*EnterVT)(int, int); + void (*LeaveVT)(int, int); + GCPtr videoGC; +} XF86XVScreenRec, *XF86XVScreenPtr; + +typedef struct { + int flags; + PutVideoFuncPtr PutVideo; + PutStillFuncPtr PutStill; + GetVideoFuncPtr GetVideo; + GetStillFuncPtr GetStill; + StopVideoFuncPtr StopVideo; + SetPortAttributeFuncPtr SetPortAttribute; + GetPortAttributeFuncPtr GetPortAttribute; + QueryBestSizeFuncPtr QueryBestSize; + PutImageFuncPtr PutImage; + ReputImageFuncPtr ReputImage; + QueryImageAttributesFuncPtr QueryImageAttributes; +} XvAdaptorRecPrivate, *XvAdaptorRecPrivatePtr; + +typedef struct { + ScrnInfoPtr pScrn; + DrawablePtr pDraw; + unsigned char type; + unsigned int subWindowMode; + DDXPointRec clipOrg; + RegionPtr clientClip; + RegionPtr pCompositeClip; + Bool FreeCompositeClip; + XvAdaptorRecPrivatePtr AdaptorRec; + XvStatus isOn; + Bool moved; + int vid_x, vid_y, vid_w, vid_h; + int drw_x, drw_y, drw_w, drw_h; + DevUnion DevPriv; +} XvPortRecPrivate, *XvPortRecPrivatePtr; + +typedef struct _XF86XVWindowRec{ + XvPortRecPrivatePtr PortRec; + struct _XF86XVWindowRec *next; +} XF86XVWindowRec, *XF86XVWindowPtr; + +#endif /* _XF86XVPRIV_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfIOKit.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfIOKit.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfIOKit.h (revision 51223) @@ -0,0 +1,57 @@ +/* + xfIOKit.h + + IOKit specific functions and definitions +*/ +/* + * Copyright (c) 2001-2002 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XFree86: xc/programs/Xserver/hw/darwin/xfIOKit.h,v 1.10 2003/03/15 18:02:08 torrey Exp $ */ + +#ifndef _XFIOKIT_H +#define _XFIOKIT_H + +#include +#include +#include +#include "screenint.h" +#include "darwin.h" + +typedef struct { + io_connect_t fbService; + StdFBShmem_t *cursorShmem; + unsigned char *framebuffer; + unsigned char *shadowPtr; +} XFIOKitScreenRec, *XFIOKitScreenPtr; + +#define XFIOKIT_SCREEN_PRIV(pScreen) \ + ((XFIOKitScreenPtr)pScreen->devPrivates[xfIOKitScreenIndex].ptr) + +extern int xfIOKitScreenIndex; // index into pScreen.devPrivates +extern io_connect_t xfIOKitInputConnect; + +Bool XFIOKitInitCursor(ScreenPtr pScreen); + +#endif /* _XFIOKIT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixes.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixes.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixes.h (revision 51223) @@ -0,0 +1,54 @@ +/* + * $Id: xfixes.h,v 1.5 2005/07/01 22:43:42 daniels Exp $ + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XFIXES_H_ +#define _XFIXES_H_ + +#include "resource.h" + +extern RESTYPE RegionResType; +extern int XFixesErrorBase; + +#define VERIFY_REGION(pRegion, rid, client, mode) { \ + pRegion = SecurityLookupIDByType (client, rid, RegionResType, mode); \ + if (!pRegion) { \ + client->errorValue = rid; \ + return XFixesErrorBase + BadRegion; \ + } \ +} + +#define VERIFY_REGION_OR_NONE(pRegion, rid, client, mode) { \ + pRegion = 0; \ + if (rid) VERIFY_REGION(pRegion, rid, client, mode); \ +} + +RegionPtr +XFixesRegionCopy (RegionPtr pRegion); + + +#endif /* _XFIXES_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixesint.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixesint.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xfixesint.h (revision 51223) @@ -0,0 +1,277 @@ +/* + * $Id: xfixesint.h,v 1.7 2005/07/03 08:53:54 daniels Exp $ + * + * Copyright © 2006 Sun Microsystems + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Sun Microsystems not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Sun Microsystems makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * SUN MICROSYSTEMS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL SUN MICROSYSTEMS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Copyright © 2002 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Keith Packard not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Keith Packard makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef _XFIXESINT_H_ +#define _XFIXESINT_H_ + +#define NEED_EVENTS +#include +#include +#include "misc.h" +#include "os.h" +#include "dixstruct.h" +#include "extnsionst.h" +#include +#include "windowstr.h" +#include "selection.h" +#include "xfixes.h" + +extern unsigned char XFixesReqCode; +extern int XFixesEventBase; +extern int XFixesClientPrivateIndex; + +typedef struct _XFixesClient { + CARD32 major_version; + CARD32 minor_version; +} XFixesClientRec, *XFixesClientPtr; + +#define GetXFixesClient(pClient) ((XFixesClientPtr) (pClient)->devPrivates[XFixesClientPrivateIndex].ptr) + +extern int (*ProcXFixesVector[XFixesNumberRequests])(ClientPtr); +extern int (*SProcXFixesVector[XFixesNumberRequests])(ClientPtr); + +/* Initialize extension at server startup time */ + +void +XFixesExtensionInit(void); + +/* Save set */ +int +ProcXFixesChangeSaveSet(ClientPtr client); + +int +SProcXFixesChangeSaveSet(ClientPtr client); + +/* Selection events */ +int +ProcXFixesSelectSelectionInput (ClientPtr client); + +int +SProcXFixesSelectSelectionInput (ClientPtr client); + +void +SXFixesSelectionNotifyEvent (xXFixesSelectionNotifyEvent *from, + xXFixesSelectionNotifyEvent *to); +Bool +XFixesSelectionInit (void); + +/* Cursor notification */ +Bool +XFixesCursorInit (void); + +int +ProcXFixesSelectCursorInput (ClientPtr client); + +int +SProcXFixesSelectCursorInput (ClientPtr client); + +void +SXFixesCursorNotifyEvent (xXFixesCursorNotifyEvent *from, + xXFixesCursorNotifyEvent *to); + +int +ProcXFixesGetCursorImage (ClientPtr client); + +int +SProcXFixesGetCursorImage (ClientPtr client); + +/* Cursor names (Version 2) */ + +int +ProcXFixesSetCursorName (ClientPtr client); + +int +SProcXFixesSetCursorName (ClientPtr client); + +int +ProcXFixesGetCursorName (ClientPtr client); + +int +SProcXFixesGetCursorName (ClientPtr client); + +int +ProcXFixesGetCursorImageAndName (ClientPtr client); + +int +SProcXFixesGetCursorImageAndName (ClientPtr client); + +/* Cursor replacement (Version 2) */ + +int +ProcXFixesChangeCursor (ClientPtr client); + +int +SProcXFixesChangeCursor (ClientPtr client); + +int +ProcXFixesChangeCursorByName (ClientPtr client); + +int +SProcXFixesChangeCursorByName (ClientPtr client); + +/* Region objects (Version 2* */ +Bool +XFixesRegionInit (void); + +int +ProcXFixesCreateRegion (ClientPtr client); + +int +SProcXFixesCreateRegion (ClientPtr client); + +int +ProcXFixesCreateRegionFromBitmap (ClientPtr client); + +int +SProcXFixesCreateRegionFromBitmap (ClientPtr client); + +int +ProcXFixesCreateRegionFromWindow (ClientPtr client); + +int +SProcXFixesCreateRegionFromWindow (ClientPtr client); + +int +ProcXFixesCreateRegionFromGC (ClientPtr client); + +int +SProcXFixesCreateRegionFromGC (ClientPtr client); + +int +ProcXFixesCreateRegionFromPicture (ClientPtr client); + +int +SProcXFixesCreateRegionFromPicture (ClientPtr client); + +int +ProcXFixesDestroyRegion (ClientPtr client); + +int +SProcXFixesDestroyRegion (ClientPtr client); + +int +ProcXFixesSetRegion (ClientPtr client); + +int +SProcXFixesSetRegion (ClientPtr client); + +int +ProcXFixesCopyRegion (ClientPtr client); + +int +SProcXFixesCopyRegion (ClientPtr client); + +int +ProcXFixesCombineRegion (ClientPtr client); + +int +SProcXFixesCombineRegion (ClientPtr client); + +int +ProcXFixesInvertRegion (ClientPtr client); + +int +SProcXFixesInvertRegion (ClientPtr client); + +int +ProcXFixesTranslateRegion (ClientPtr client); + +int +SProcXFixesTranslateRegion (ClientPtr client); + +int +ProcXFixesRegionExtents (ClientPtr client); + +int +SProcXFixesRegionExtents (ClientPtr client); + +int +ProcXFixesFetchRegion (ClientPtr client); + +int +SProcXFixesFetchRegion (ClientPtr client); + +int +ProcXFixesSetGCClipRegion (ClientPtr client); + +int +SProcXFixesSetGCClipRegion (ClientPtr client); + +int +ProcXFixesSetWindowShapeRegion (ClientPtr client); + +int +SProcXFixesSetWindowShapeRegion (ClientPtr client); + +int +ProcXFixesSetPictureClipRegion (ClientPtr client); + +int +SProcXFixesSetPictureClipRegion (ClientPtr client); + +int +ProcXFixesExpandRegion (ClientPtr client); + +int +SProcXFixesExpandRegion (ClientPtr client); + +/* Cursor Visibility (Version 4) */ + +int +ProcXFixesHideCursor (ClientPtr client); + +int +SProcXFixesHideCursor (ClientPtr client); + +int +ProcXFixesShowCursor (ClientPtr client); + +int +SProcXFixesShowCursor (ClientPtr client); + +#endif /* _XFIXESINT_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xisb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xisb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xisb.h (revision 51223) @@ -0,0 +1,66 @@ +/* + * Copyright (c) 1997 Metro Link Incorporated + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Metro Link shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Metro Link. + * + */ +/* $XFree86$ */ + +#ifndef _xisb_H_ +#define _xisb_H_ + +#include + +/****************************************************************************** + * Definitions + * structs, typedefs, #defines, enums + *****************************************************************************/ + +typedef struct _XISBuffer +{ + int fd; + int trace; + int block_duration; + ssize_t current; /* bytes read */ + ssize_t end; + ssize_t buffer_size; + unsigned char *buf; +} XISBuffer; + +/****************************************************************************** + * Declarations + * variables: use xisb_LOC in front + * of globals. + * put locals in the .c file. + *****************************************************************************/ +XISBuffer * XisbNew (int fd, ssize_t size); +void XisbFree (XISBuffer *b); +int XisbRead (XISBuffer *b); +ssize_t XisbWrite (XISBuffer *b, unsigned char *msg, ssize_t len); +void XisbTrace (XISBuffer *b, int trace); +void XisbBlockDuration (XISBuffer *b, int block_duration); + +/* + * DO NOT PUT ANYTHING AFTER THIS ENDIF + */ +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkb.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkb.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkb.h (revision 51223) @@ -0,0 +1,74 @@ +/* $XFree86$ */ + +/* #include "XKBfile.h" */ + +extern int ProcXkbUseExtension(ClientPtr client); +extern int ProcXkbSelectEvents(ClientPtr client); +extern int ProcXkbBell(ClientPtr client); +extern int ProcXkbGetState(ClientPtr client); +extern int ProcXkbLatchLockState(ClientPtr client); +extern int ProcXkbGetControls(ClientPtr client); +extern int ProcXkbSetControls(ClientPtr client); +extern int ProcXkbGetMap(ClientPtr client); +extern int ProcXkbSetMap(ClientPtr client); +extern int ProcXkbGetCompatMap(ClientPtr client); +extern int ProcXkbSetCompatMap(ClientPtr client); +extern int ProcXkbGetIndicatorState(ClientPtr client); +extern int ProcXkbGetIndicatorMap(ClientPtr client); +extern int ProcXkbSetIndicatorMap(ClientPtr client); +extern int ProcXkbGetNamedIndicator(ClientPtr client); +extern int ProcXkbSetNamedIndicator(ClientPtr client); +extern int ProcXkbGetNames(ClientPtr client); +extern int ProcXkbSetNames(ClientPtr client); +extern int ProcXkbGetGeometry(ClientPtr client); +extern int ProcXkbSetGeometry(ClientPtr client); +extern int ProcXkbPerClientFlags(ClientPtr client); +extern int ProcXkbListComponents(ClientPtr client); +extern int ProcXkbGetKbdByName(ClientPtr client); +extern int ProcXkbGetDeviceInfo(ClientPtr client); +extern int ProcXkbSetDeviceInfo(ClientPtr client); +extern int ProcXkbSetDebuggingFlags(ClientPtr client); + +extern int XkbSetRepeatRate(DeviceIntPtr dev, int timeout, int interval, int major, int minor); +extern int XkbGetRepeatRate(DeviceIntPtr dev, int *timeout, int *interval); + +extern void XkbExtensionInit(void); + +extern Status XkbComputeGetIndicatorMapReplySize( + XkbIndicatorPtr indicators, + xkbGetIndicatorMapReply *rep); +extern int XkbSendIndicatorMap( + ClientPtr client, + XkbIndicatorPtr indicators, + xkbGetIndicatorMapReply *rep); + +extern void XkbComputeCompatState(XkbSrvInfoPtr xkbi); +extern void XkbSetPhysicalLockingKey(DeviceIntPtr dev, unsigned key); + +extern Bool XkbFilterEvents(ClientPtr pClient, int nEvents, xEvent *xE); + +extern Bool XkbApplyLEDChangeToKeyboard( + XkbSrvInfoPtr xkbi, + XkbIndicatorMapPtr map, + Bool on, + XkbChangesPtr change); + +extern Bool XkbWriteRulesProp(ClientPtr client, pointer closure); + +extern XkbAction XkbGetButtonAction(DeviceIntPtr kbd, DeviceIntPtr dev, int button); + +/* extern Status XkbMergeFile(XkbDescPtr xkb, XkbFileInfo finfo); */ + +extern Bool XkbDDXCompileNamedKeymap( + XkbDescPtr xkb, + XkbComponentNamesPtr names, + char * nameRtrn, + int nameRtrnLen); + +extern Bool XkbDDXCompileKeymapByNames( + XkbDescPtr xkb, + XkbComponentNamesPtr names, + unsigned want, + unsigned need, + char * nameRtrn, + int nameRtrnLen); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkbDflts.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkbDflts.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xkbDflts.h (revision 51223) @@ -0,0 +1,508 @@ +/* $Xorg: xkbDflts.h,v 1.3 2000/08/17 19:53:47 cpqbld Exp $ */ +/* $XFree86: xc/programs/Xserver/xkb/xkbDflts.h,v 1.2 2001/10/28 03:34:20 tsi Exp $ */ +/* This file generated automatically by xkbcomp */ +/* DO NOT EDIT */ +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef DEFAULT_H +#define DEFAULT_H 1 + +#define GET_ATOM(d,s) MakeAtom(s,strlen(s),1) +#define DPYTYPE char * +#define NUM_KEYS 1 + +#define vmod_NumLock 0 +#define vmod_Alt 1 +#define vmod_LevelThree 2 +#define vmod_AltGr 3 +#define vmod_ScrollLock 4 + +#define vmod_NumLockMask (1<<0) +#define vmod_AltMask (1<<1) +#define vmod_LevelThreeMask (1<<2) +#define vmod_AltGrMask (1<<3) +#define vmod_ScrollLockMask (1<<4) + +/* types name is "default" */ +static Atom lnames_ONE_LEVEL[1]; + +static XkbKTMapEntryRec map_TWO_LEVEL[1]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } } +}; +static Atom lnames_TWO_LEVEL[2]; + +static XkbKTMapEntryRec map_ALPHABETIC[2]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 1, 0, { LockMask, LockMask, 0 } } +}; +static XkbModsRec preserve_ALPHABETIC[2]= { + { 0, 0, 0 }, + { LockMask, LockMask, 0 } +}; +static Atom lnames_ALPHABETIC[2]; + +static XkbKTMapEntryRec map_KEYPAD[2]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 0, 1, { 0, 0, vmod_NumLockMask } } +}; +static Atom lnames_KEYPAD[2]; + +static XkbKTMapEntryRec map_PC_BREAK[1]= { + { 1, 1, { ControlMask, ControlMask, 0 } } +}; +static Atom lnames_PC_BREAK[2]; + +static XkbKTMapEntryRec map_PC_SYSRQ[1]= { + { 0, 1, { 0, 0, vmod_AltMask } } +}; +static Atom lnames_PC_SYSRQ[2]; + +static XkbKTMapEntryRec map_CTRL_ALT[1]= { + { 0, 1, { ControlMask, ControlMask, vmod_AltMask } } +}; +static Atom lnames_CTRL_ALT[2]; + +static XkbKTMapEntryRec map_THREE_LEVEL[3]= { + { 1, 1, { ShiftMask, ShiftMask, 0 } }, + { 0, 2, { 0, 0, vmod_LevelThreeMask } }, + { 0, 2, { ShiftMask, ShiftMask, vmod_LevelThreeMask } } +}; +static Atom lnames_THREE_LEVEL[3]; + +static XkbKTMapEntryRec map_SHIFT_ALT[1]= { + { 0, 1, { ShiftMask, ShiftMask, vmod_AltMask } } +}; +static Atom lnames_SHIFT_ALT[2]; + +static XkbKeyTypeRec dflt_types[]= { + { + { 0, 0, 0 }, + 1, + 0, NULL, NULL, + None, lnames_ONE_LEVEL + }, + { + { ShiftMask, ShiftMask, 0 }, + 2, + 1, map_TWO_LEVEL, NULL, + None, lnames_TWO_LEVEL + }, + { + { ShiftMask|LockMask, ShiftMask|LockMask, 0 }, + 2, + 2, map_ALPHABETIC, preserve_ALPHABETIC, + None, lnames_ALPHABETIC + }, + { + { ShiftMask, ShiftMask, vmod_NumLockMask }, + 2, + 2, map_KEYPAD, NULL, + None, lnames_KEYPAD + }, + { + { ControlMask, ControlMask, 0 }, + 2, + 1, map_PC_BREAK, NULL, + None, lnames_PC_BREAK + }, + { + { 0, 0, vmod_AltMask }, + 2, + 1, map_PC_SYSRQ, NULL, + None, lnames_PC_SYSRQ + }, + { + { ControlMask, ControlMask, vmod_AltMask }, + 2, + 1, map_CTRL_ALT, NULL, + None, lnames_CTRL_ALT + }, + { + { ShiftMask, ShiftMask, vmod_LevelThreeMask }, + 3, + 3, map_THREE_LEVEL, NULL, + None, lnames_THREE_LEVEL + }, + { + { ShiftMask, ShiftMask, vmod_AltMask }, + 2, + 1, map_SHIFT_ALT, NULL, + None, lnames_SHIFT_ALT + } +}; +#define num_dflt_types (sizeof(dflt_types)/sizeof(XkbKeyTypeRec)) + + +static void +initTypeNames(DPYTYPE dpy) +{ + dflt_types[0].name= GET_ATOM(dpy,"ONE_LEVEL"); + lnames_ONE_LEVEL[0]= GET_ATOM(dpy,"Any"); + dflt_types[1].name= GET_ATOM(dpy,"TWO_LEVEL"); + lnames_TWO_LEVEL[0]= GET_ATOM(dpy,"Base"); + lnames_TWO_LEVEL[1]= GET_ATOM(dpy,"Shift"); + dflt_types[2].name= GET_ATOM(dpy,"ALPHABETIC"); + lnames_ALPHABETIC[0]= GET_ATOM(dpy,"Base"); + lnames_ALPHABETIC[1]= GET_ATOM(dpy,"Caps"); + dflt_types[3].name= GET_ATOM(dpy,"KEYPAD"); + lnames_KEYPAD[0]= GET_ATOM(dpy,"Base"); + lnames_KEYPAD[1]= GET_ATOM(dpy,"Number"); + dflt_types[4].name= GET_ATOM(dpy,"PC_BREAK"); + lnames_PC_BREAK[0]= GET_ATOM(dpy,"Base"); + lnames_PC_BREAK[1]= GET_ATOM(dpy,"Control"); + dflt_types[5].name= GET_ATOM(dpy,"PC_SYSRQ"); + lnames_PC_SYSRQ[0]= GET_ATOM(dpy,"Base"); + lnames_PC_SYSRQ[1]= GET_ATOM(dpy,"Alt"); + dflt_types[6].name= GET_ATOM(dpy,"CTRL+ALT"); + lnames_CTRL_ALT[0]= GET_ATOM(dpy,"Base"); + lnames_CTRL_ALT[1]= GET_ATOM(dpy,"Ctrl+Alt"); + dflt_types[7].name= GET_ATOM(dpy,"THREE_LEVEL"); + lnames_THREE_LEVEL[0]= GET_ATOM(dpy,"Base"); + lnames_THREE_LEVEL[1]= GET_ATOM(dpy,"Shift"); + lnames_THREE_LEVEL[2]= GET_ATOM(dpy,"Level3"); + dflt_types[8].name= GET_ATOM(dpy,"SHIFT+ALT"); + lnames_SHIFT_ALT[0]= GET_ATOM(dpy,"Base"); + lnames_SHIFT_ALT[1]= GET_ATOM(dpy,"Shift+Alt"); +} +/* compat name is "default" */ +static XkbSymInterpretRec dfltSI[69]= { + { XK_ISO_Level2_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_Exactly, ShiftMask, + 255, + { XkbSA_LatchMods, { 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Eisu_Shift, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Eisu_toggle, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Kana_Shift, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Kana_Lock, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_NoAction, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Shift_Lock, 0x0000, + XkbSI_AnyOf, ShiftMask|LockMask, + 255, + { XkbSA_LockMods, { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Num_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 0, + { XkbSA_LockMods, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_Alt_L, 0x0000, + XkbSI_AnyOf, 0xff, + 1, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Alt_R, 0x0000, + XkbSI_AnyOf, 0xff, + 1, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Scroll_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 4, + { XkbSA_LockMods, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Lock, 0x0000, + XkbSI_AnyOf, 0xff, + 255, + { XkbSA_ISOLock, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Level3_Shift, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOf, 0xff, + 2, + { XkbSA_SetMods, { 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00 } } }, + { XK_ISO_Level3_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOf, 0xff, + 2, + { XkbSA_LatchMods, { 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00 } } }, + { XK_Mode_switch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_SetGroup, { 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_1, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_End, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_2, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_Down, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_3, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_Next, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00 } } }, + { XK_KP_4, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Left, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_6, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Right, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_7, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Home, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_8, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Up, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_9, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_Prior, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_MovePtr, { 0x00, 0x00, 0x01, 0xff, 0xff, 0x00, 0x00 } } }, + { XK_KP_5, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Begin, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F1, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Divide, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F2, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Multiply, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_F3, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Subtract, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x04, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Separator, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Add, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_0, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Insert, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Decimal, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_KP_Delete, 0x0001, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Button3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DblClick3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_PtrBtn, { 0x00, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag_Dflt, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag1, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag2, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_Drag3, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockPtrBtn, { 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_EnableKeys, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00 } } }, + { XK_Pointer_Accelerate, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00 } } }, + { XK_Pointer_DfltBtnNext, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_Pointer_DfltBtnPrev, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_SetPtrDflt, { 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_AccessX_Enable, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockControls, { 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00 } } }, + { XK_Terminate_Server, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_Terminate, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Group_Latch, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LatchGroup, { 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Next_Group, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LockGroup, { 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Prev_Group, 0x0000, + XkbSI_LevelOneOnly|XkbSI_AnyOfOrNone, 0xff, + 3, + { XkbSA_LockGroup, { 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_First_Group, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockGroup, { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { XK_ISO_Last_Group, 0x0000, + XkbSI_AnyOfOrNone, 0xff, + 255, + { XkbSA_LockGroup, { 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } } }, + { NoSymbol, 0x0000, + XkbSI_Exactly, LockMask, + 255, + { XkbSA_LockMods, { 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00 } } }, + { NoSymbol, 0x0000, + XkbSI_AnyOf, 0xff, + 255, + { XkbSA_SetMods, { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } } +}; +#define num_dfltSI (sizeof(dfltSI)/sizeof(XkbSymInterpretRec)) + +static XkbCompatMapRec compatMap= { + dfltSI, + { /* group compatibility */ + { 0, 0, 0 }, + { 0, 0, vmod_AltGrMask }, + { 0, 0, vmod_AltGrMask }, + { 0, 0, vmod_AltGrMask } + }, + num_dfltSI, num_dfltSI +}; + +static XkbIndicatorRec indicators= { + 0x0, + { + { 0x80, 0, 0x00, XkbIM_UseEffective, { LockMask, LockMask, 0 }, 0 }, + { 0x80, 0, 0x00, XkbIM_UseEffective, { 0, 0, vmod_NumLockMask }, 0 }, + { 0x80, 0, 0x00, XkbIM_UseLocked, { ShiftMask, ShiftMask, 0 }, 0 }, + { 0x80, 0, 0x00, 0, { 0, 0, 0 }, XkbMouseKeysMask }, + { 0x80, 0, 0x00, XkbIM_UseLocked, { 0, 0, vmod_ScrollLockMask }, 0 }, + { 0x80, XkbIM_UseEffective, 0xfe, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 }, + { 0x00, 0, 0x00, 0, { 0, 0, 0 }, 0 } + } +}; +static void +initIndicatorNames(DPYTYPE dpy,XkbDescPtr xkb) +{ + xkb->names->indicators[ 0]= GET_ATOM(dpy,"Caps Lock"); + xkb->names->indicators[ 1]= GET_ATOM(dpy,"Num Lock"); + xkb->names->indicators[ 2]= GET_ATOM(dpy,"Shift Lock"); + xkb->names->indicators[ 3]= GET_ATOM(dpy,"Mouse Keys"); + xkb->names->indicators[ 4]= GET_ATOM(dpy,"Scroll Lock"); + xkb->names->indicators[ 5]= GET_ATOM(dpy,"Group 2"); +} +#endif /* DEFAULT_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-config.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-config.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-config.h (revision 51223) @@ -0,0 +1,116 @@ +/* include/xorg-config.h. Generated by configure. */ +/* xorg-config.h.in: not at all generated. -*- c -*- + * + * This file differs from xorg-server.h.in in that -server is installed + * with the rest of the SDK for external drivers/modules to use, whereas + * -config is for internal use only (i.e. building the DDX). + * + */ + +#ifndef _XORG_CONFIG_H_ +#define _XORG_CONFIG_H_ + +#include +#include + +/* Building Xorg server. */ +#define XORGSERVER 1 + +/* Current X.Org version. */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((1) * 100000) + ((0) * 1000) + 0) + +/* Need XFree86 libc-replacement typedefs. */ +#define NEED_XF86_TYPES 1 + +/* Need XFree86 libc-replacement functions. */ +#define NEED_XF86_PROTOTYPES 1 + +/* Name of X server. */ +#define __XSERVERNAME__ "Xorg" + +/* URL to go to for support. */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Use libdl-based loader. */ +#define DLOPEN_SUPPORT 1 + +/* Built-in output drivers. */ +#define DRIVERS {} + +/* Built-in input drivers. */ +#define IDRIVERS {} + +/* Path to configuration file. */ +#define XF86CONFIGFILE "xorg.conf" + +/* Path to configuration file. */ +#define __XCONFIGFILE__ "xorg.conf" + +/* Path to loadable modules. */ +#define DEFAULT_MODULE_PATH "/usr/local/lib/xorg/modules" + +/* Path to server log file. */ +#define DEFAULT_LOGPREFIX "/usr/local/var/log/Xorg." + +/* Building DRI-capable DDX. */ +#define XF86DRI 1 + +/* Solaris 8 or later? */ +/* #undef __SOL8__ */ + +/* Whether to use pixmap privates */ +#define PIXPRIV 1 + +/* Define to 1 if you have the `walkcontext' function (used on Solaris for + xorg_backtrace in hw/xfree86/common/xf86Events.c */ +/* #undef HAVE_WALKCONTEXT */ + +/* Define to 1 if unsigned long is 64 bits. */ +/* #undef _XSERVER64 */ + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* Define to 1 if NetBSD built-in MTRR support is available */ +/* #undef HAS_MTRR_BUILTIN */ + +/* Define to 1 if BSD MTRR support is available */ +#define HAS_MTRR_SUPPORT 1 + +/* NetBSD PIO alpha IO */ +/* #undef USE_ALPHA_PIO */ + +/* BSD AMD64 iopl */ +/* #undef USE_AMD64_IOPL */ + +/* BSD /dev/io */ +/* #undef USE_DEV_IO */ + +/* BSD i386 iopl */ +/* #undef USE_I386_IOPL */ + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PCVT console */ +/* #undef PCVT_SUPPORT */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +/* System has /dev/xf86 aperture driver */ +/* #undef HAS_APERTURE_DRV */ + +/* Has backtrace support */ +#define HAVE_BACKTRACE 1 + +#endif /* _XORG_CONFIG_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-server.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-server.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorg-server.h (revision 51223) @@ -0,0 +1,245 @@ +/* include/xorg-server.h. Generated by configure. */ +/* xorg-server.h.in -*- c -*- + * + * This file is the template file for the xorg-server.h file which gets + * installed as part of the SDK. The #defines in this file overlap + * with those from config.h, but only for those options that we want + * to export to external modules. Boilerplate autotool #defines such + * as HAVE_STUFF and PACKAGE_NAME is kept in config.h + * + * It is still possible to update config.h.in using autoheader, since + * autoheader only creates a .h.in file for the first + * AM_CONFIG_HEADER() line, and thus does not overwrite this file. + * + * However, it should be kept in sync with this file. + */ + +#ifndef _XORG_SERVER_H_ +#define _XORG_SERVER_H_ + +/* Support BigRequests extension */ +#define BIGREQS 1 + +/* Default font path */ +#define COMPILEDDEFAULTFONTPATH "/usr/local/lib/X11/fonts/misc/,/usr/local/lib/X11/fonts/TTF/,/usr/local/lib/X11/fonts/OTF,/usr/local/lib/X11/fonts/Type1/,/usr/local/lib/X11/fonts/CID/,/usr/local/lib/X11/fonts/100dpi/,/usr/local/lib/X11/fonts/75dpi/" + +/* Support Composite Extension */ +#define COMPOSITE 1 + +/* Use OsVendorInit */ +#define DDXOSINIT 1 + +/* Prefer dlloader modules to elfloader */ +#define DLOPEN_HACK 1 + +/* Building with libdl */ +#define DLOPEN_SUPPORT 1 + +/* Build DPMS extension */ +#define DPMSExtension 1 + +/* Built-in output drivers */ +#define DRIVERS {} + +/* Build GLX extension */ +#define GLXEXT 1 + +/* Include handhelds.org h3600 touchscreen driver */ +/* #undef H3600_TS */ + +/* Support XDM-AUTH*-1 */ +#define HASXDMAUTH 1 + +/* Support SHM */ +#define HAS_SHM 1 + +/* Built-in input drivers */ +#define IDRIVERS {} + +/* Support IPv6 for TCP connections */ +#define IPv6 1 + +/* Support MIT Misc extension */ +#define MITMISC 1 + +/* Support MIT-SHM Extension */ +#define MITSHM 1 + +/* Disable some debugging code */ +#define NDEBUG 1 + +/* Need XFree86 helper functions */ +#define NEED_XF86_PROTOTYPES 1 + +/* Need XFree86 typedefs */ +#define NEED_XF86_TYPES 1 + +/* Internal define for Xinerama */ +#define PANORAMIX 1 + +/* Support pixmap privates */ +#define PIXPRIV 1 + +/* Support RANDR extension */ +#define RANDR 1 + +/* Support RENDER extension */ +#define RENDER 1 + +/* Support X resource extension */ +#define RES 1 + +/* Support MIT-SCREEN-SAVER extension */ +#define SCREENSAVER 1 + +/* Use a lock to prevent multiple servers on a display */ +#define SERVER_LOCK 1 + +/* Support SHAPE extension */ +#define SHAPE 1 + +/* Include time-based scheduler */ +#define SMART_SCHEDULE 1 + +/* Define to 1 on systems derived from System V Release 4 */ +/* #undef SVR4 */ + +/* Support TCP socket connections */ +#define TCPCONN 1 + +/* Enable touchscreen support */ +/* #undef TOUCHSCREEN */ + +/* Support tslib touchscreen abstraction library */ +/* #undef TSLIB */ + +/* Support UNIX socket connections */ +#define UNIXCONN 1 + +/* Use builtin rgb color database */ +/* #undef USE_RGB_BUILTIN */ + +/* Use rgb.txt directly */ +#define USE_RGB_TXT 1 + +/* unaligned word accesses behave as expected */ +/* #undef WORKING_UNALIGNED_INT */ + +/* Support XCMisc extension */ +#define XCMISC 1 + +/* Support Xdmcp */ +#define XDMCP 1 + +/* Build XFree86 BigFont extension */ +#define XF86BIGFONT 1 + +/* Support XFree86 miscellaneous extensions */ +#define XF86MISC 1 + +/* Support XFree86 Video Mode extension */ +#define XF86VIDMODE 1 + +/* Build XDGA support */ +#define XFreeXDGA 1 + +/* Support Xinerama extension */ +#define XINERAMA 1 + +/* Support X Input extension */ +#define XINPUT 1 + +/* Build XKB */ +#define XKB 1 + +/* Enable XKB per default */ +#define XKB_DFLT_DISABLED 0 + +/* Build XKB server */ +#define XKB_IN_SERVER 1 + +/* Support loadable input and output drivers */ +/* #undef XLOADABLE */ + +/* Build DRI extension */ +#define XF86DRI 1 + +/* Build Xorg server */ +#define XORGSERVER 1 + +/* Vendor release */ +#define XORG_RELEASE "Release 7.1" + +/* Current Xorg version */ +#define XORG_VERSION_CURRENT (((7) * 10000000) + ((1) * 100000) + ((0) * 1000) + 0) + +/* Build Xv Extension */ +#define XvExtension 1 + +/* Build XvMC Extension */ +#define XvMCExtension 1 + +/* Build XRes extension */ +#define XResExtension 1 + +/* Support XSync extension */ +#define XSYNC 1 + +/* Support XTest extension */ +#define XTEST 1 + +/* Support XTrap extension */ +#define XTRAP 1 + +/* Support Xv Extension */ +#define XV 1 + +/* Vendor name */ +#define XVENDORNAME "The X.Org Foundation" + +/* Endian order */ +#define X_BYTE_ORDER X_LITTLE_ENDIAN + +/* BSD-compliant source */ +#define _BSD_SOURCE 1 + +/* POSIX-compliant source */ +#define _POSIX_SOURCE 1 + +/* X/Open-compliant source */ +#define _XOPEN_SOURCE 500 + +/* Vendor web address for support */ +#define __VENDORDWEBSUPPORT__ "http://wiki.x.org" + +/* Location of configuration file */ +#define __XCONFIGFILE__ "xorg.conf" + +/* XKB default rules */ +#define __XKBDEFRULES__ "xorg" + +/* Name of X server */ +#define __XSERVERNAME__ "Xorg" + +/* Define to 1 if unsigned long is 64 bits. */ +/* #undef _XSERVER64 */ + +/* Building vgahw module */ +#define WITH_VGAHW 1 + +/* System is BSD-like */ +/* #undef CSRG_BASED */ + +/* System has PC console */ +/* #undef PCCONS_SUPPORT */ + +/* System has PCVT console */ +/* #undef PCVT_SUPPORT */ + +/* System has syscons console */ +/* #undef SYSCONS_SUPPORT */ + +/* System has wscons console */ +/* #undef WSCONS_SUPPORT */ + +#endif /* _XORG_SERVER_H_ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorgVersion.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorgVersion.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xorgVersion.h (revision 51223) @@ -0,0 +1,51 @@ +/* $XdotOrg: xserver/xorg/hw/xfree86/common/xorgVersion.h,v 1.6 2005/08/24 11:18:35 daniels Exp $ */ + +/* + * Copyright (c) 2004, X.Org Foundation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ + +#ifndef XORG_VERSION_H +# define XORG_VERSION_H + +# ifndef XORG_VERSION_CURRENT +# error +# endif + +# define XORG_VERSION_NUMERIC(major,minor,patch,snap,dummy) \ + (((major) * 10000000) + ((minor) * 100000) + ((patch) * 1000) + snap) + +# define XORG_GET_MAJOR_VERSION(vers) ((vers) / 10000000) +# define XORG_GET_MINOR_VERSION(vers) (((vers) % 10000000) / 100000) +# define XORG_GET_PATCH_VERSION(vers) (((vers) % 100000) / 1000) +# define XORG_GET_SNAP_VERSION(vers) ((vers) % 1000) + +# define XORG_VERSION_MAJOR XORG_GET_MAJOR_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_MINOR XORG_GET_MINOR_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_PATCH XORG_GET_PATCH_VERSION(XORG_VERSION_CURRENT) +# define XORG_VERSION_SNAP XORG_GET_SNAP_VERSION(XORG_VERSION_CURRENT) + +#endif +/* $XdotOrg: xserver/xorg/hw/xfree86/common/xorgVersion.h,v 1.6 2005/08/24 11:18:35 daniels Exp $ */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xpr.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xpr.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xpr.h (revision 51223) @@ -0,0 +1,49 @@ +/* + * Xplugin rootless implementation + */ +/* + * Copyright (c) 2003 Torrey T. Lyons. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE ABOVE LISTED COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name(s) of the above copyright + * holders shall not be used in advertising or otherwise to promote the sale, + * use or other dealings in this Software without prior written authorization. + */ +/* $XdotOrg: xserver/xorg/hw/darwin/quartz/xpr/xpr.h,v 1.3 2005/07/01 22:43:08 daniels Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/darwin/quartz/xpr/xpr.h,v 1.4 2003/11/12 20:21:52 torrey Exp $ */ + +#ifndef XPR_H +#define XPR_H + +#include "screenint.h" + +extern Bool QuartzModeBundleInit(void); + +void AppleDRIExtensionInit(void); +void xprAppleWMInit(void); +Bool xprInit(ScreenPtr pScreen); +Bool xprIsX11Window(void *nsWindow, int windowNumber); +void xprHideWindows(Bool hide); + +Bool QuartzInitCursor(ScreenPtr pScreen); +void QuartzSuspendXCursor(ScreenPtr pScreen); +void QuartzResumeXCursor(ScreenPtr pScreen, int x, int y); + +#endif /* XPR_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xqueue.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xqueue.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xqueue.h (revision 51223) @@ -0,0 +1,12 @@ +/* $XFree86$ */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef _XF86_XQUEUE_H_ +#define _XF86_XQUEUE_H_ + +Bool XqueueMousePreInit(InputInfoPtr pInfo, const char *protocol, int flags); + +#endif Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xtest1dd.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xtest1dd.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xtest1dd.h (revision 51223) @@ -0,0 +1,127 @@ +/* $XFree86: xc/programs/Xserver/Xext/xtest1dd.h,v 3.2 2001/08/01 00:44:44 tsi Exp $ */ +/************************************************************ + +Copyright 1996 by Thomas E. Dickey + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of the above listed +copyright holder(s) not be used in advertising or publicity pertaining +to distribution of the software without specific, written prior +permission. + +THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE +LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#ifndef XTEST1DD_H +#define XTEST1DD_H 1 + +extern short xtest_mousex; +extern short xtest_mousey; +extern int playback_on; +extern ClientPtr current_xtest_client; +extern ClientPtr playback_client; +extern KeyCode xtest_command_key; + +extern void stop_stealing_input( + void +); + +extern void +steal_input( + ClientPtr /* client */, + CARD32 /* mode */ +); + +extern void +flush_input_actions( + void +); + +extern void +XTestStealJumpData( + int /* jx */, + int /* jy */, + int /* dev_type */ +); + +extern void +XTestStealMotionData( + int /* dx */, + int /* dy */, + int /* dev_type */, + int /* mx */, + int /* my */ +); + +extern Bool +XTestStealKeyData( + unsigned /* keycode */, + int /* keystate */, + int /* dev_type */, + int /* locx */, + int /* locy */ +); + +extern void +parse_fake_input( + ClientPtr /* client */, + char * /* req */ +); + +extern void +XTestComputeWaitTime( + struct timeval * /* waittime */ +); + +extern int +XTestProcessInputAction( + int /* readable */, + struct timeval * /* waittime */ +); + +extern void +abort_play_back( + void +); + +extern void +return_input_array_size( + ClientPtr /* client */ +); + +extern void XTestGenerateEvent( + int /* dev_type */, + int /* keycode */, + int /* keystate */, + int /* mousex */, + int /* mousey */ +); + +extern void XTestGetPointerPos( + short * /* fmousex */, + short * /* fmousey */ +); + +extern void XTestJumpPointer( + int /* jx */, + int /* jy */, + int /* dev_type */ +); + +#endif /* XTEST1DD_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdisp.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdisp.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdisp.h (revision 51223) @@ -0,0 +1,3 @@ +/* $XFree86$ */ + +extern void XineramifyXv(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdix.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdix.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvdix.h (revision 51223) @@ -0,0 +1,291 @@ +/*********************************************************** +Copyright 1991 by Digital Equipment Corporation, Maynard, Massachusetts, +and the Massachusetts Institute of Technology, Cambridge, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the names of Digital or MIT not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/programs/Xserver/Xext/xvdix.h,v 1.7 2001/05/07 21:37:51 tsi Exp $ */ + +#ifndef XVDIX_H +#define XVDIX_H +/* +** File: +** +** xvdix.h --- Xv device independent header file +** +** Author: +** +** David Carver (Digital Workstation Engineering/Project Athena) +** +** Revisions: +** +** 29.08.91 Carver +** - removed UnrealizeWindow wrapper unrealizing windows no longer +** preempts video +** +** 11.06.91 Carver +** - changed SetPortControl to SetPortAttribute +** - changed GetPortControl to GetPortAttribute +** - changed QueryBestSize +** +** 15.05.91 Carver +** - version 2.0 upgrade +** +** 24.01.91 Carver +** - version 1.4 upgrade +** +*/ + +#include "scrnintstr.h" +#include + +extern int XvScreenIndex; +extern unsigned long XvExtensionGeneration; +extern unsigned long XvScreenGeneration; +extern unsigned long XvResourceGeneration; + +extern int XvReqCode; +extern int XvEventBase; +extern int XvErrorBase; + +extern unsigned long XvRTPort; +extern unsigned long XvRTEncoding; +extern unsigned long XvRTGrab; +extern unsigned long XvRTVideoNotify; +extern unsigned long XvRTVideoNotifyList; +extern unsigned long XvRTPortNotify; + +typedef struct { + int numerator; + int denominator; +} XvRationalRec, *XvRationalPtr; + +typedef struct { + char depth; + unsigned long visual; +} XvFormatRec, *XvFormatPtr; + +typedef struct { + unsigned long id; + ClientPtr client; +} XvGrabRec, *XvGrabPtr; + +typedef struct _XvVideoNotifyRec { + struct _XvVideoNotifyRec *next; + ClientPtr client; + unsigned long id; + unsigned long mask; +} XvVideoNotifyRec, *XvVideoNotifyPtr; + +typedef struct _XvPortNotifyRec { + struct _XvPortNotifyRec *next; + ClientPtr client; + unsigned long id; +} XvPortNotifyRec, *XvPortNotifyPtr; + +typedef struct { + int id; + ScreenPtr pScreen; + char *name; + unsigned short width, height; + XvRationalRec rate; +} XvEncodingRec, *XvEncodingPtr; + +typedef struct _XvAttributeRec { + int flags; + int min_value; + int max_value; + char *name; +} XvAttributeRec, *XvAttributePtr; + +typedef struct { + int id; + int type; + int byte_order; + char guid[16]; + int bits_per_pixel; + int format; + int num_planes; + + /* for RGB formats only */ + int depth; + unsigned int red_mask; + unsigned int green_mask; + unsigned int blue_mask; + + /* for YUV formats only */ + unsigned int y_sample_bits; + unsigned int u_sample_bits; + unsigned int v_sample_bits; + unsigned int horz_y_period; + unsigned int horz_u_period; + unsigned int horz_v_period; + unsigned int vert_y_period; + unsigned int vert_u_period; + unsigned int vert_v_period; + char component_order[32]; + int scanline_order; +} XvImageRec, *XvImagePtr; + +typedef struct { + unsigned long base_id; + unsigned char type; + char *name; + int nEncodings; + XvEncodingPtr pEncodings; + int nFormats; + XvFormatPtr pFormats; + int nAttributes; + XvAttributePtr pAttributes; + int nImages; + XvImagePtr pImages; + int nPorts; + struct _XvPortRec *pPorts; + ScreenPtr pScreen; + int (* ddAllocatePort)(unsigned long, struct _XvPortRec*, + struct _XvPortRec**); + int (* ddFreePort)(struct _XvPortRec*); + int (* ddPutVideo)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddPutStill)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddGetVideo)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddGetStill)(ClientPtr, DrawablePtr,struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); + int (* ddStopVideo)(ClientPtr, struct _XvPortRec*, DrawablePtr); + int (* ddSetPortAttribute)(ClientPtr, struct _XvPortRec*, Atom, INT32); + int (* ddGetPortAttribute)(ClientPtr, struct _XvPortRec*, Atom, INT32*); + int (* ddQueryBestSize)(ClientPtr, struct _XvPortRec*, CARD8, + CARD16, CARD16,CARD16, CARD16, + unsigned int*, unsigned int*); + int (* ddPutImage)(ClientPtr, DrawablePtr, struct _XvPortRec*, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16, + XvImagePtr, unsigned char*, Bool, + CARD16, CARD16); + int (* ddQueryImageAttributes)(ClientPtr, struct _XvPortRec*, XvImagePtr, + CARD16*, CARD16*, int*, int*); + DevUnion devPriv; +} XvAdaptorRec, *XvAdaptorPtr; + +typedef struct _XvPortRec { + unsigned long id; + XvAdaptorPtr pAdaptor; + XvPortNotifyPtr pNotify; + DrawablePtr pDraw; + ClientPtr client; + XvGrabRec grab; + TimeStamp time; + DevUnion devPriv; +} XvPortRec, *XvPortPtr; + +#define LOOKUP_PORT(_id, client)\ + ((XvPortPtr)LookupIDByType(_id, XvRTPort)) + +#define LOOKUP_ENCODING(_id, client)\ + ((XvEncodingPtr)LookupIDByType(_id, XvRTEncoding)) + +#define LOOKUP_VIDEONOTIFY_LIST(_id, client)\ + ((XvVideoNotifyPtr)LookupIDByType(_id, XvRTVideoNotifyList)) + +#define LOOKUP_PORTNOTIFY_LIST(_id, client)\ + ((XvPortNotifyPtr)LookupIDByType(_id, XvRTPortNotifyList)) + +typedef struct { + int version, revision; + int nAdaptors; + XvAdaptorPtr pAdaptors; + DestroyWindowProcPtr DestroyWindow; + DestroyPixmapProcPtr DestroyPixmap; + CloseScreenProcPtr CloseScreen; + Bool (* ddCloseScreen)(int, ScreenPtr); + int (* ddQueryAdaptors)(ScreenPtr, XvAdaptorPtr*, int*); + DevUnion devPriv; +} XvScreenRec, *XvScreenPtr; + +#define SCREEN_PROLOGUE(pScreen, field)\ + ((pScreen)->field = \ + ((XvScreenPtr) \ + (pScreen)->devPrivates[XvScreenIndex].ptr)->field) + +#define SCREEN_EPILOGUE(pScreen, field, wrapper)\ + ((pScreen)->field = wrapper) + +/* Errors */ + +#define _XvBadPort (XvBadPort+XvErrorBase) +#define _XvBadEncoding (XvBadEncoding+XvErrorBase) + +extern int ProcXvDispatch(ClientPtr); +extern int SProcXvDispatch(ClientPtr); + +extern void XvExtensionInit(void); +extern int XvScreenInit(ScreenPtr); +extern int XvGetScreenIndex(void); +extern unsigned long XvGetRTPort(void); +extern int XvdiSendPortNotify(XvPortPtr, Atom, INT32); +extern int XvdiVideoStopped(XvPortPtr, int); + +extern int XvdiPutVideo(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiPutStill(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiGetVideo(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiGetStill(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16); +extern int XvdiPutImage(ClientPtr, DrawablePtr, XvPortPtr, GCPtr, + INT16, INT16, CARD16, CARD16, + INT16, INT16, CARD16, CARD16, + XvImagePtr, unsigned char*, Bool, + CARD16, CARD16); +extern int XvdiSelectVideoNotify(ClientPtr, DrawablePtr, BOOL); +extern int XvdiSelectPortNotify(ClientPtr, XvPortPtr, BOOL); +extern int XvdiSetPortAttribute(ClientPtr, XvPortPtr, Atom, INT32); +extern int XvdiGetPortAttribute(ClientPtr, XvPortPtr, Atom, INT32*); +extern int XvdiStopVideo(ClientPtr, XvPortPtr, DrawablePtr); +extern int XvdiPreemptVideo(ClientPtr, XvPortPtr, DrawablePtr); +extern int XvdiMatchPort(XvPortPtr, DrawablePtr); +extern int XvdiGrabPort(ClientPtr, XvPortPtr, Time, int *); +extern int XvdiUngrabPort( ClientPtr, XvPortPtr, Time); + + +#if !defined(UNIXCPP) + +#define XVCALL(name) Xv##name + +#else + +#define XVCALL(name) Xv/**/name + +#endif + + +#endif /* XVDIX_H */ + Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmcext.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmcext.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmcext.h (revision 51223) @@ -0,0 +1,116 @@ +/* $XFree86: xc/programs/Xserver/Xext/xvmcext.h,v 1.1 2001/04/07 11:04:21 alanh Exp $ */ + +#ifndef _XVMC_H +#define _XVMC_H +#include +#include "xvdix.h" + +typedef struct { + int num_xvimages; + int *xvimage_ids; +} XvMCImageIDList; + +typedef struct { + int surface_type_id; + int chroma_format; + int color_description; + unsigned short max_width; + unsigned short max_height; + unsigned short subpicture_max_width; + unsigned short subpicture_max_height; + int mc_type; + int flags; + XvMCImageIDList *compatible_subpictures; +} XvMCSurfaceInfoRec, *XvMCSurfaceInfoPtr; + +typedef struct { + XID context_id; + ScreenPtr pScreen; + int adapt_num; + int surface_type_id; + unsigned short width; + unsigned short height; + CARD32 flags; + int refcnt; + pointer port_priv; + pointer driver_priv; +} XvMCContextRec, *XvMCContextPtr; + +typedef struct { + XID surface_id; + int surface_type_id; + XvMCContextPtr context; + pointer driver_priv; +} XvMCSurfaceRec, *XvMCSurfacePtr; + + +typedef struct { + XID subpicture_id; + int xvimage_id; + unsigned short width; + unsigned short height; + int num_palette_entries; + int entry_bytes; + char component_order[4]; + XvMCContextPtr context; + pointer driver_priv; +} XvMCSubpictureRec, *XvMCSubpicturePtr; + +typedef int (*XvMCCreateContextProcPtr) ( + XvPortPtr port, + XvMCContextPtr context, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroyContextProcPtr) ( + XvMCContextPtr context +); + +typedef int (*XvMCCreateSurfaceProcPtr) ( + XvMCSurfacePtr surface, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroySurfaceProcPtr) ( + XvMCSurfacePtr surface +); + +typedef int (*XvMCCreateSubpictureProcPtr) ( + XvMCSubpicturePtr subpicture, + int *num_priv, + CARD32 **priv +); + +typedef void (*XvMCDestroySubpictureProcPtr) ( + XvMCSubpicturePtr subpicture +); + + +typedef struct { + XvAdaptorPtr xv_adaptor; + int num_surfaces; + XvMCSurfaceInfoPtr *surfaces; + int num_subpictures; + XvImagePtr *subpictures; + XvMCCreateContextProcPtr CreateContext; + XvMCDestroyContextProcPtr DestroyContext; + XvMCCreateSurfaceProcPtr CreateSurface; + XvMCDestroySurfaceProcPtr DestroySurface; + XvMCCreateSubpictureProcPtr CreateSubpicture; + XvMCDestroySubpictureProcPtr DestroySubpicture; +} XvMCAdaptorRec, *XvMCAdaptorPtr; + +void XvMCExtensionInit(void); + +int XvMCScreenInit(ScreenPtr pScreen, int num, XvMCAdaptorPtr adapt); + +XvImagePtr XvMCFindXvImage(XvPortPtr pPort, CARD32 id); + +int xf86XvMCRegisterDRInfo(ScreenPtr pScreen, char *name, + char *busID, int major, int minor, + int patchLevel); + + +#endif /* _XVMC_H */ Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmodproc.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmodproc.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/xvmodproc.h (revision 51223) @@ -0,0 +1,14 @@ +/* $XFree86: xc/programs/Xserver/Xext/xvmodproc.h,v 1.2 2001/03/05 04:51:55 mvojkovi Exp $ */ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "xvmcext.h" + +extern int (*XvGetScreenIndexProc)(void); +extern unsigned long (*XvGetRTPortProc)(void); +extern int (*XvScreenInitProc)(ScreenPtr); +extern int (*XvMCScreenInitProc)(ScreenPtr, int, XvMCAdaptorPtr); + +extern void XvRegister(void); Index: /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/zx1PCI.h =================================================================== --- /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/zx1PCI.h (revision 51223) +++ /trunk/src/VBox/Additions/x11/x11include/xorg-server-1.1.0/zx1PCI.h (revision 51223) @@ -0,0 +1,40 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.h,v 1.1 2003/02/23 20:26:49 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +#ifdef HAVE_XORG_CONFIG_H +#include +#endif + +#ifndef PCI_ZX1_H +#define PCI_ZX1_H 1 + +#include + +void xf86PreScanZX1(void); +void xf86PostScanZX1(void); + +#endif